Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 19
1 22:09:39.483021 lava-dispatcher, installed at version: 2023.06
2 22:09:39.483190 start: 0 validate
3 22:09:39.483302 Start time: 2023-09-05 22:09:39.483294+00:00 (UTC)
4 22:09:39.483424 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:09:39.483553 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 22:09:39.751518 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:09:39.752170 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:09:59.042500 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:09:59.043115 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:09:59.311481 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:09:59.311628 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:10:02.076179 validate duration: 22.59
14 22:10:02.076438 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:10:02.076527 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:10:02.076602 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:10:02.076719 Not decompressing ramdisk as can be used compressed.
18 22:10:02.076797 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 22:10:02.076855 saving as /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/ramdisk/rootfs.cpio.gz
20 22:10:02.076908 total size: 8181372 (7 MB)
21 22:10:02.078035 progress 0 % (0 MB)
22 22:10:02.079727 progress 5 % (0 MB)
23 22:10:02.081245 progress 10 % (0 MB)
24 22:10:02.082857 progress 15 % (1 MB)
25 22:10:02.084359 progress 20 % (1 MB)
26 22:10:02.086062 progress 25 % (1 MB)
27 22:10:02.087660 progress 30 % (2 MB)
28 22:10:02.089219 progress 35 % (2 MB)
29 22:10:02.090699 progress 40 % (3 MB)
30 22:10:02.092253 progress 45 % (3 MB)
31 22:10:02.093766 progress 50 % (3 MB)
32 22:10:02.095299 progress 55 % (4 MB)
33 22:10:02.096725 progress 60 % (4 MB)
34 22:10:02.098337 progress 65 % (5 MB)
35 22:10:02.099780 progress 70 % (5 MB)
36 22:10:02.101328 progress 75 % (5 MB)
37 22:10:02.102781 progress 80 % (6 MB)
38 22:10:02.104305 progress 85 % (6 MB)
39 22:10:02.105758 progress 90 % (7 MB)
40 22:10:02.107322 progress 95 % (7 MB)
41 22:10:02.108842 progress 100 % (7 MB)
42 22:10:02.108997 7 MB downloaded in 0.03 s (243.16 MB/s)
43 22:10:02.109136 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:10:02.109348 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:10:02.109430 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:10:02.109495 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:10:02.109614 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:10:02.109672 saving as /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/kernel/Image
50 22:10:02.109719 total size: 49220096 (46 MB)
51 22:10:02.109768 No compression specified
52 22:10:02.110916 progress 0 % (0 MB)
53 22:10:02.119861 progress 5 % (2 MB)
54 22:10:02.128590 progress 10 % (4 MB)
55 22:10:02.137338 progress 15 % (7 MB)
56 22:10:02.146072 progress 20 % (9 MB)
57 22:10:02.154872 progress 25 % (11 MB)
58 22:10:02.163621 progress 30 % (14 MB)
59 22:10:02.172365 progress 35 % (16 MB)
60 22:10:02.181238 progress 40 % (18 MB)
61 22:10:02.190406 progress 45 % (21 MB)
62 22:10:02.199661 progress 50 % (23 MB)
63 22:10:02.208763 progress 55 % (25 MB)
64 22:10:02.217645 progress 60 % (28 MB)
65 22:10:02.226398 progress 65 % (30 MB)
66 22:10:02.235139 progress 70 % (32 MB)
67 22:10:02.243864 progress 75 % (35 MB)
68 22:10:02.252603 progress 80 % (37 MB)
69 22:10:02.261544 progress 85 % (39 MB)
70 22:10:02.270215 progress 90 % (42 MB)
71 22:10:02.278781 progress 95 % (44 MB)
72 22:10:02.287406 progress 100 % (46 MB)
73 22:10:02.287514 46 MB downloaded in 0.18 s (264.02 MB/s)
74 22:10:02.287649 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:10:02.287851 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:10:02.287921 start: 1.3 download-retry (timeout 00:10:00) [common]
78 22:10:02.287989 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 22:10:02.288117 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:10:02.288176 saving as /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/dtb/mt8192-asurada-spherion-r0.dtb
81 22:10:02.288225 total size: 47278 (0 MB)
82 22:10:02.288273 No compression specified
83 22:10:02.289476 progress 69 % (0 MB)
84 22:10:02.289706 progress 100 % (0 MB)
85 22:10:02.289841 0 MB downloaded in 0.00 s (27.95 MB/s)
86 22:10:02.289954 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:10:02.290149 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:10:02.290219 start: 1.4 download-retry (timeout 00:10:00) [common]
90 22:10:02.290309 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 22:10:02.290418 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:10:02.290481 saving as /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/modules/modules.tar
93 22:10:02.290531 total size: 8619808 (8 MB)
94 22:10:02.290581 Using unxz to decompress xz
95 22:10:02.294220 progress 0 % (0 MB)
96 22:10:02.313584 progress 5 % (0 MB)
97 22:10:02.333692 progress 10 % (0 MB)
98 22:10:02.357375 progress 15 % (1 MB)
99 22:10:02.379927 progress 20 % (1 MB)
100 22:10:02.402600 progress 25 % (2 MB)
101 22:10:02.425407 progress 30 % (2 MB)
102 22:10:02.448626 progress 35 % (2 MB)
103 22:10:02.470565 progress 40 % (3 MB)
104 22:10:02.491222 progress 45 % (3 MB)
105 22:10:02.514242 progress 50 % (4 MB)
106 22:10:02.535998 progress 55 % (4 MB)
107 22:10:02.557277 progress 60 % (4 MB)
108 22:10:02.576909 progress 65 % (5 MB)
109 22:10:02.601101 progress 70 % (5 MB)
110 22:10:02.622162 progress 75 % (6 MB)
111 22:10:02.645076 progress 80 % (6 MB)
112 22:10:02.671101 progress 85 % (7 MB)
113 22:10:02.693887 progress 90 % (7 MB)
114 22:10:02.714685 progress 95 % (7 MB)
115 22:10:02.736771 progress 100 % (8 MB)
116 22:10:02.740620 8 MB downloaded in 0.45 s (18.26 MB/s)
117 22:10:02.740863 end: 1.4.1 http-download (duration 00:00:00) [common]
119 22:10:02.741127 end: 1.4 download-retry (duration 00:00:00) [common]
120 22:10:02.741223 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:10:02.741300 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:10:02.741382 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:10:02.741451 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:10:02.741643 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9
125 22:10:02.741755 makedir: /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin
126 22:10:02.741842 makedir: /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/tests
127 22:10:02.741922 makedir: /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/results
128 22:10:02.742024 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-add-keys
129 22:10:02.742142 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-add-sources
130 22:10:02.742240 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-background-process-start
131 22:10:02.742339 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-background-process-stop
132 22:10:02.742432 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-common-functions
133 22:10:02.742524 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-echo-ipv4
134 22:10:02.742618 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-install-packages
135 22:10:02.742712 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-installed-packages
136 22:10:02.742804 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-os-build
137 22:10:02.742904 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-probe-channel
138 22:10:02.742997 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-probe-ip
139 22:10:02.743088 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-target-ip
140 22:10:02.743180 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-target-mac
141 22:10:02.743271 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-target-storage
142 22:10:02.743367 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-test-case
143 22:10:02.743458 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-test-event
144 22:10:02.743552 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-test-feedback
145 22:10:02.743644 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-test-raise
146 22:10:02.743735 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-test-reference
147 22:10:02.743828 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-test-runner
148 22:10:02.743918 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-test-set
149 22:10:02.744010 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-test-shell
150 22:10:02.744104 Updating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-install-packages (oe)
151 22:10:02.744224 Updating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/bin/lava-installed-packages (oe)
152 22:10:02.744317 Creating /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/environment
153 22:10:02.744404 LAVA metadata
154 22:10:02.744463 - LAVA_JOB_ID=11440308
155 22:10:02.744515 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:10:02.744595 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:10:02.744649 skipped lava-vland-overlay
158 22:10:02.744707 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:10:02.744771 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:10:02.744820 skipped lava-multinode-overlay
161 22:10:02.744877 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:10:02.744939 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:10:02.744996 Loading test definitions
164 22:10:02.745068 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:10:02.745126 Using /lava-11440308 at stage 0
166 22:10:02.745384 uuid=11440308_1.5.2.3.1 testdef=None
167 22:10:02.745473 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:10:02.745539 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:10:02.745947 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:10:02.746121 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:10:02.746611 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:10:02.746789 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:10:02.747264 runner path: /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/0/tests/0_dmesg test_uuid 11440308_1.5.2.3.1
176 22:10:02.747388 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:10:02.747568 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 22:10:02.747623 Using /lava-11440308 at stage 1
180 22:10:02.747844 uuid=11440308_1.5.2.3.5 testdef=None
181 22:10:02.747911 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 22:10:02.747973 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 22:10:02.748327 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 22:10:02.748498 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 22:10:02.749399 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 22:10:02.749616 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 22:10:02.750124 runner path: /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/1/tests/1_bootrr test_uuid 11440308_1.5.2.3.5
190 22:10:02.750242 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 22:10:02.750405 Creating lava-test-runner.conf files
193 22:10:02.750453 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/0 for stage 0
194 22:10:02.750521 - 0_dmesg
195 22:10:02.750586 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11440308/lava-overlay-346_ajs9/lava-11440308/1 for stage 1
196 22:10:02.750657 - 1_bootrr
197 22:10:02.750731 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 22:10:02.750803 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 22:10:02.757075 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 22:10:02.757171 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 22:10:02.757244 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 22:10:02.757319 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 22:10:02.757419 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 22:10:02.924189 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 22:10:02.924483 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 22:10:02.924579 extracting modules file /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11440308/extract-overlay-ramdisk-abdjhtgd/ramdisk
207 22:10:03.065537 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 22:10:03.065702 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
209 22:10:03.065800 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11440308/compress-overlay-3cudsph_/overlay-1.5.2.4.tar.gz to ramdisk
210 22:10:03.065867 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11440308/compress-overlay-3cudsph_/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11440308/extract-overlay-ramdisk-abdjhtgd/ramdisk
211 22:10:03.071791 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 22:10:03.071918 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
213 22:10:03.072020 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 22:10:03.072121 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
215 22:10:03.072214 Building ramdisk /var/lib/lava/dispatcher/tmp/11440308/extract-overlay-ramdisk-abdjhtgd/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11440308/extract-overlay-ramdisk-abdjhtgd/ramdisk
216 22:10:03.243265 >> 145167 blocks
217 22:10:05.265855 rename /var/lib/lava/dispatcher/tmp/11440308/extract-overlay-ramdisk-abdjhtgd/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/ramdisk/ramdisk.cpio.gz
218 22:10:05.266337 end: 1.5.7 compress-ramdisk (duration 00:00:02) [common]
219 22:10:05.266521 start: 1.5.8 prepare-kernel (timeout 00:09:57) [common]
220 22:10:05.266648 start: 1.5.8.1 prepare-fit (timeout 00:09:57) [common]
221 22:10:05.266810 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/kernel/Image'
222 22:10:18.824258 Returned 0 in 13 seconds
223 22:10:18.925032 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/kernel/image.itb
224 22:10:19.172065 output: FIT description: Kernel Image image with one or more FDT blobs
225 22:10:19.172335 output: Created: Tue Sep 5 23:10:19 2023
226 22:10:19.172418 output: Image 0 (kernel-1)
227 22:10:19.172476 output: Description:
228 22:10:19.172528 output: Created: Tue Sep 5 23:10:19 2023
229 22:10:19.172577 output: Type: Kernel Image
230 22:10:19.172627 output: Compression: lzma compressed
231 22:10:19.172684 output: Data Size: 11037994 Bytes = 10779.29 KiB = 10.53 MiB
232 22:10:19.172736 output: Architecture: AArch64
233 22:10:19.172789 output: OS: Linux
234 22:10:19.172839 output: Load Address: 0x00000000
235 22:10:19.172886 output: Entry Point: 0x00000000
236 22:10:19.172933 output: Hash algo: crc32
237 22:10:19.172980 output: Hash value: 9d08b3de
238 22:10:19.173027 output: Image 1 (fdt-1)
239 22:10:19.173073 output: Description: mt8192-asurada-spherion-r0
240 22:10:19.173119 output: Created: Tue Sep 5 23:10:19 2023
241 22:10:19.173165 output: Type: Flat Device Tree
242 22:10:19.173212 output: Compression: uncompressed
243 22:10:19.173259 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 22:10:19.173310 output: Architecture: AArch64
245 22:10:19.173367 output: Hash algo: crc32
246 22:10:19.173422 output: Hash value: cc4352de
247 22:10:19.173469 output: Image 2 (ramdisk-1)
248 22:10:19.173520 output: Description: unavailable
249 22:10:19.173563 output: Created: Tue Sep 5 23:10:19 2023
250 22:10:19.173605 output: Type: RAMDisk Image
251 22:10:19.173648 output: Compression: Unknown Compression
252 22:10:19.173692 output: Data Size: 21382673 Bytes = 20881.52 KiB = 20.39 MiB
253 22:10:19.173735 output: Architecture: AArch64
254 22:10:19.173778 output: OS: Linux
255 22:10:19.173820 output: Load Address: unavailable
256 22:10:19.173864 output: Entry Point: unavailable
257 22:10:19.173907 output: Hash algo: crc32
258 22:10:19.173950 output: Hash value: 5208bf47
259 22:10:19.173993 output: Default Configuration: 'conf-1'
260 22:10:19.174035 output: Configuration 0 (conf-1)
261 22:10:19.174078 output: Description: mt8192-asurada-spherion-r0
262 22:10:19.174121 output: Kernel: kernel-1
263 22:10:19.174163 output: Init Ramdisk: ramdisk-1
264 22:10:19.174206 output: FDT: fdt-1
265 22:10:19.174249 output: Loadables: kernel-1
266 22:10:19.174291 output:
267 22:10:19.174433 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 22:10:19.174509 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 22:10:19.174588 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 22:10:19.174660 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
271 22:10:19.174721 No LXC device requested
272 22:10:19.174783 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 22:10:19.174847 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
274 22:10:19.174906 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 22:10:19.174957 Checking files for TFTP limit of 4294967296 bytes.
276 22:10:19.175320 end: 1 tftp-deploy (duration 00:00:17) [common]
277 22:10:19.175412 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 22:10:19.175480 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 22:10:19.175574 substitutions:
280 22:10:19.175626 - {DTB}: 11440308/tftp-deploy-yi_q08mg/dtb/mt8192-asurada-spherion-r0.dtb
281 22:10:19.175676 - {INITRD}: 11440308/tftp-deploy-yi_q08mg/ramdisk/ramdisk.cpio.gz
282 22:10:19.175722 - {KERNEL}: 11440308/tftp-deploy-yi_q08mg/kernel/Image
283 22:10:19.175767 - {LAVA_MAC}: None
284 22:10:19.175810 - {PRESEED_CONFIG}: None
285 22:10:19.175855 - {PRESEED_LOCAL}: None
286 22:10:19.175899 - {RAMDISK}: 11440308/tftp-deploy-yi_q08mg/ramdisk/ramdisk.cpio.gz
287 22:10:19.175943 - {ROOT_PART}: None
288 22:10:19.175987 - {ROOT}: None
289 22:10:19.176030 - {SERVER_IP}: 192.168.201.1
290 22:10:19.176073 - {TEE}: None
291 22:10:19.176116 Parsed boot commands:
292 22:10:19.176160 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 22:10:19.176303 Parsed boot commands: tftpboot 192.168.201.1 11440308/tftp-deploy-yi_q08mg/kernel/image.itb 11440308/tftp-deploy-yi_q08mg/kernel/cmdline
294 22:10:19.176377 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 22:10:19.176444 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 22:10:19.176517 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 22:10:19.176588 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 22:10:19.176646 Not connected, no need to disconnect.
299 22:10:19.176705 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 22:10:19.176767 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 22:10:19.176820 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
302 22:10:19.179955 Setting prompt string to ['lava-test: # ']
303 22:10:19.180283 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 22:10:19.180401 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 22:10:19.180497 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 22:10:19.180700 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 22:10:19.180873 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
308 22:10:24.326283 >> Command sent successfully.
309 22:10:24.334691 Returned 0 in 5 seconds
310 22:10:24.435719 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 22:10:24.436951 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 22:10:24.437456 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 22:10:24.437808 Setting prompt string to 'Starting depthcharge on Spherion...'
315 22:10:24.438083 Changing prompt to 'Starting depthcharge on Spherion...'
316 22:10:24.438345 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 22:10:24.439378 [Enter `^Ec?' for help]
318 22:10:24.611004
319 22:10:24.611469
320 22:10:24.611733 F0: 102B 0000
321 22:10:24.611962
322 22:10:24.612176 F3: 1001 0000 [0200]
323 22:10:24.614082
324 22:10:24.614535 F3: 1001 0000
325 22:10:24.614792
326 22:10:24.615015 F7: 102D 0000
327 22:10:24.615224
328 22:10:24.616911 F1: 0000 0000
329 22:10:24.617267
330 22:10:24.617556 V0: 0000 0000 [0001]
331 22:10:24.617792
332 22:10:24.620728 00: 0007 8000
333 22:10:24.621213
334 22:10:24.621530 01: 0000 0000
335 22:10:24.621770
336 22:10:24.624208 BP: 0C00 0209 [0000]
337 22:10:24.624674
338 22:10:24.624983 G0: 1182 0000
339 22:10:24.625233
340 22:10:24.627678 EC: 0000 0021 [4000]
341 22:10:24.628169
342 22:10:24.628462 S7: 0000 0000 [0000]
343 22:10:24.628710
344 22:10:24.630897 CC: 0000 0000 [0001]
345 22:10:24.631182
346 22:10:24.631404 T0: 0000 0040 [010F]
347 22:10:24.631637
348 22:10:24.631865 Jump to BL
349 22:10:24.633997
350 22:10:24.657951
351 22:10:24.658401
352 22:10:24.658650
353 22:10:24.664070 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 22:10:24.667867 ARM64: Exception handlers installed.
355 22:10:24.672279 ARM64: Testing exception
356 22:10:24.675124 ARM64: Done test exception
357 22:10:24.681247 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 22:10:24.691911 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 22:10:24.698727 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 22:10:24.708962 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 22:10:24.715658 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 22:10:24.722664 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 22:10:24.734736 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 22:10:24.741098 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 22:10:24.760388 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 22:10:24.763961 WDT: Last reset was cold boot
367 22:10:24.767227 SPI1(PAD0) initialized at 2873684 Hz
368 22:10:24.770340 SPI5(PAD0) initialized at 992727 Hz
369 22:10:24.773481 VBOOT: Loading verstage.
370 22:10:24.780155 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 22:10:24.783780 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 22:10:24.787122 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 22:10:24.790190 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 22:10:24.797898 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 22:10:24.804481 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 22:10:24.815536 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 22:10:24.815971
378 22:10:24.816226
379 22:10:24.825028 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 22:10:24.828611 ARM64: Exception handlers installed.
381 22:10:24.832370 ARM64: Testing exception
382 22:10:24.832837 ARM64: Done test exception
383 22:10:24.838621 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 22:10:24.841762 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 22:10:24.856566 Probing TPM: . done!
386 22:10:24.857057 TPM ready after 0 ms
387 22:10:24.862961 Connected to device vid:did:rid of 1ae0:0028:00
388 22:10:24.870106 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
389 22:10:24.944749 Initialized TPM device CR50 revision 0
390 22:10:24.948079 tlcl_send_startup: Startup return code is 0
391 22:10:24.955978 TPM: setup succeeded
392 22:10:24.967516 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 22:10:24.976157 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 22:10:24.986221 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 22:10:24.996026 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 22:10:24.999486 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 22:10:25.007782 in-header: 03 07 00 00 08 00 00 00
398 22:10:25.010931 in-data: aa e4 47 04 13 02 00 00
399 22:10:25.014623 Chrome EC: UHEPI supported
400 22:10:25.021857 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 22:10:25.025449 in-header: 03 95 00 00 08 00 00 00
402 22:10:25.028961 in-data: 18 20 20 08 00 00 00 00
403 22:10:25.029534 Phase 1
404 22:10:25.032539 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 22:10:25.040078 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 22:10:25.044388 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 22:10:25.047394 Recovery requested (1009000e)
408 22:10:25.057055 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 22:10:25.062708 tlcl_extend: response is 0
410 22:10:25.072072 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 22:10:25.077056 tlcl_extend: response is 0
412 22:10:25.084554 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 22:10:25.104389 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 22:10:25.111068 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 22:10:25.111376
416 22:10:25.111432
417 22:10:25.121444 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 22:10:25.124378 ARM64: Exception handlers installed.
419 22:10:25.127869 ARM64: Testing exception
420 22:10:25.128338 ARM64: Done test exception
421 22:10:25.149736 pmic_efuse_setting: Set efuses in 11 msecs
422 22:10:25.153676 pmwrap_interface_init: Select PMIF_VLD_RDY
423 22:10:25.160230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 22:10:25.163366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 22:10:25.170018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 22:10:25.173357 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 22:10:25.179875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 22:10:25.183030 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 22:10:25.189725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 22:10:25.193355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 22:10:25.196864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 22:10:25.203827 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 22:10:25.207301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 22:10:25.210857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 22:10:25.214635 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 22:10:25.221773 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 22:10:25.229095 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 22:10:25.232679 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 22:10:25.239523 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 22:10:25.243485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 22:10:25.250995 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 22:10:25.258277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 22:10:25.261921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 22:10:25.265927 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 22:10:25.272801 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 22:10:25.277260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 22:10:25.284450 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 22:10:25.287683 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 22:10:25.294978 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 22:10:25.299039 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 22:10:25.302115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 22:10:25.309323 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 22:10:25.312585 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 22:10:25.319883 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 22:10:25.323978 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 22:10:25.327611 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 22:10:25.334757 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 22:10:25.338393 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 22:10:25.345647 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 22:10:25.348906 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 22:10:25.352716 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 22:10:25.356958 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 22:10:25.360305 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 22:10:25.367395 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 22:10:25.370993 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 22:10:25.374708 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 22:10:25.378501 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 22:10:25.385826 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 22:10:25.389636 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 22:10:25.393006 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 22:10:25.396887 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 22:10:25.400306 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 22:10:25.404382 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 22:10:25.411720 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 22:10:25.421878 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 22:10:25.425700 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 22:10:25.433127 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 22:10:25.443913 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 22:10:25.447669 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 22:10:25.451593 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 22:10:25.454622 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 22:10:25.463846 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x15
483 22:10:25.466867 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 22:10:25.475076 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 22:10:25.478235 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 22:10:25.487272 [RTC]rtc_get_frequency_meter,154: input=15, output=764
487 22:10:25.496935 [RTC]rtc_get_frequency_meter,154: input=23, output=951
488 22:10:25.506802 [RTC]rtc_get_frequency_meter,154: input=19, output=856
489 22:10:25.516030 [RTC]rtc_get_frequency_meter,154: input=17, output=811
490 22:10:25.526071 [RTC]rtc_get_frequency_meter,154: input=16, output=788
491 22:10:25.535003 [RTC]rtc_get_frequency_meter,154: input=16, output=788
492 22:10:25.544916 [RTC]rtc_get_frequency_meter,154: input=17, output=811
493 22:10:25.548081 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 22:10:25.552341 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 22:10:25.559586 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 22:10:25.563172 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 22:10:25.567207 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 22:10:25.570098 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 22:10:25.573825 ADC[4]: Raw value=669327 ID=5
500 22:10:25.577174 ADC[3]: Raw value=212917 ID=1
501 22:10:25.577601 RAM Code: 0x51
502 22:10:25.581605 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 22:10:25.585242 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 22:10:25.596189 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
505 22:10:25.600148 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
506 22:10:25.603466 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 22:10:25.607060 in-header: 03 07 00 00 08 00 00 00
508 22:10:25.611345 in-data: aa e4 47 04 13 02 00 00
509 22:10:25.614794 Chrome EC: UHEPI supported
510 22:10:25.618219 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 22:10:25.622500 in-header: 03 95 00 00 08 00 00 00
512 22:10:25.625694 in-data: 18 20 20 08 00 00 00 00
513 22:10:25.629527 MRC: failed to locate region type 0.
514 22:10:25.637371 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 22:10:25.640437 DRAM-K: Running full calibration
516 22:10:25.644369 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
517 22:10:25.648364 header.status = 0x0
518 22:10:25.652151 header.version = 0x6 (expected: 0x6)
519 22:10:25.655391 header.size = 0xd00 (expected: 0xd00)
520 22:10:25.655750 header.flags = 0x0
521 22:10:25.662653 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 22:10:25.680124 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
523 22:10:25.687204 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 22:10:25.691115 dram_init: ddr_geometry: 0
525 22:10:25.691505 [EMI] MDL number = 0
526 22:10:25.695122 [EMI] Get MDL freq = 0
527 22:10:25.695718 dram_init: ddr_type: 0
528 22:10:25.698270 is_discrete_lpddr4: 1
529 22:10:25.701574 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 22:10:25.701956
531 22:10:25.702340
532 22:10:25.702717 [Bian_co] ETT version 0.0.0.1
533 22:10:25.708470 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
534 22:10:25.709064
535 22:10:25.712516 dramc_set_vcore_voltage set vcore to 650000
536 22:10:25.713037 Read voltage for 800, 4
537 22:10:25.716259 Vio18 = 0
538 22:10:25.716671 Vcore = 650000
539 22:10:25.716918 Vdram = 0
540 22:10:25.719859 Vddq = 0
541 22:10:25.720205 Vmddr = 0
542 22:10:25.722962 dram_init: config_dvfs: 1
543 22:10:25.727299 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 22:10:25.731182 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 22:10:25.734598 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
546 22:10:25.737411 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
547 22:10:25.744956 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
548 22:10:25.748926 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
549 22:10:25.749477 MEM_TYPE=3, freq_sel=18
550 22:10:25.752496 sv_algorithm_assistance_LP4_1600
551 22:10:25.756675 ============ PULL DRAM RESETB DOWN ============
552 22:10:25.760243 ========== PULL DRAM RESETB DOWN end =========
553 22:10:25.763986 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 22:10:25.767843 ===================================
555 22:10:25.771215 LPDDR4 DRAM CONFIGURATION
556 22:10:25.774488 ===================================
557 22:10:25.774854 EX_ROW_EN[0] = 0x0
558 22:10:25.778279 EX_ROW_EN[1] = 0x0
559 22:10:25.778638 LP4Y_EN = 0x0
560 22:10:25.781960 WORK_FSP = 0x0
561 22:10:25.782382 WL = 0x2
562 22:10:25.785206 RL = 0x2
563 22:10:25.785573 BL = 0x2
564 22:10:25.789426 RPST = 0x0
565 22:10:25.789783 RD_PRE = 0x0
566 22:10:25.793000 WR_PRE = 0x1
567 22:10:25.793397 WR_PST = 0x0
568 22:10:25.796672 DBI_WR = 0x0
569 22:10:25.797035 DBI_RD = 0x0
570 22:10:25.799859 OTF = 0x1
571 22:10:25.803630 ===================================
572 22:10:25.807115 ===================================
573 22:10:25.807620 ANA top config
574 22:10:25.810544 ===================================
575 22:10:25.813137 DLL_ASYNC_EN = 0
576 22:10:25.816905 ALL_SLAVE_EN = 1
577 22:10:25.817568 NEW_RANK_MODE = 1
578 22:10:25.820060 DLL_IDLE_MODE = 1
579 22:10:25.823941 LP45_APHY_COMB_EN = 1
580 22:10:25.824331 TX_ODT_DIS = 1
581 22:10:25.827661 NEW_8X_MODE = 1
582 22:10:25.831422 ===================================
583 22:10:25.834925 ===================================
584 22:10:25.838287 data_rate = 1600
585 22:10:25.841524 CKR = 1
586 22:10:25.841908 DQ_P2S_RATIO = 8
587 22:10:25.845538 ===================================
588 22:10:25.848582 CA_P2S_RATIO = 8
589 22:10:25.852303 DQ_CA_OPEN = 0
590 22:10:25.855914 DQ_SEMI_OPEN = 0
591 22:10:25.858967 CA_SEMI_OPEN = 0
592 22:10:25.859449 CA_FULL_RATE = 0
593 22:10:25.862426 DQ_CKDIV4_EN = 1
594 22:10:25.865937 CA_CKDIV4_EN = 1
595 22:10:25.869122 CA_PREDIV_EN = 0
596 22:10:25.872425 PH8_DLY = 0
597 22:10:25.872886 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 22:10:25.875856 DQ_AAMCK_DIV = 4
599 22:10:25.879071 CA_AAMCK_DIV = 4
600 22:10:25.882771 CA_ADMCK_DIV = 4
601 22:10:25.886504 DQ_TRACK_CA_EN = 0
602 22:10:25.886878 CA_PICK = 800
603 22:10:25.890244 CA_MCKIO = 800
604 22:10:25.893363 MCKIO_SEMI = 0
605 22:10:25.896910 PLL_FREQ = 3068
606 22:10:25.900885 DQ_UI_PI_RATIO = 32
607 22:10:25.901244 CA_UI_PI_RATIO = 0
608 22:10:25.905230 ===================================
609 22:10:25.908970 ===================================
610 22:10:25.912724 memory_type:LPDDR4
611 22:10:25.913184 GP_NUM : 10
612 22:10:25.916286 SRAM_EN : 1
613 22:10:25.916774 MD32_EN : 0
614 22:10:25.919831 ===================================
615 22:10:25.922811 [ANA_INIT] >>>>>>>>>>>>>>
616 22:10:25.926295 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 22:10:25.929964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 22:10:25.933090 ===================================
619 22:10:25.936189 data_rate = 1600,PCW = 0X7600
620 22:10:25.939878 ===================================
621 22:10:25.942965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 22:10:25.946479 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 22:10:25.953647 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 22:10:25.956724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 22:10:25.959893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 22:10:25.966634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 22:10:25.967139 [ANA_INIT] flow start
628 22:10:25.969719 [ANA_INIT] PLL >>>>>>>>
629 22:10:25.970216 [ANA_INIT] PLL <<<<<<<<
630 22:10:25.972974 [ANA_INIT] MIDPI >>>>>>>>
631 22:10:25.976639 [ANA_INIT] MIDPI <<<<<<<<
632 22:10:25.979857 [ANA_INIT] DLL >>>>>>>>
633 22:10:25.980430 [ANA_INIT] flow end
634 22:10:25.983148 ============ LP4 DIFF to SE enter ============
635 22:10:25.989836 ============ LP4 DIFF to SE exit ============
636 22:10:25.990219 [ANA_INIT] <<<<<<<<<<<<<
637 22:10:25.992591 [Flow] Enable top DCM control >>>>>
638 22:10:25.996551 [Flow] Enable top DCM control <<<<<
639 22:10:25.999893 Enable DLL master slave shuffle
640 22:10:26.006617 ==============================================================
641 22:10:26.007066 Gating Mode config
642 22:10:26.013156 ==============================================================
643 22:10:26.016409 Config description:
644 22:10:26.023072 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 22:10:26.029833 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 22:10:26.036901 SELPH_MODE 0: By rank 1: By Phase
647 22:10:26.042990 ==============================================================
648 22:10:26.046675 GAT_TRACK_EN = 1
649 22:10:26.047166 RX_GATING_MODE = 2
650 22:10:26.049777 RX_GATING_TRACK_MODE = 2
651 22:10:26.052958 SELPH_MODE = 1
652 22:10:26.056107 PICG_EARLY_EN = 1
653 22:10:26.059894 VALID_LAT_VALUE = 1
654 22:10:26.066491 ==============================================================
655 22:10:26.070020 Enter into Gating configuration >>>>
656 22:10:26.073135 Exit from Gating configuration <<<<
657 22:10:26.076099 Enter into DVFS_PRE_config >>>>>
658 22:10:26.086772 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 22:10:26.089683 Exit from DVFS_PRE_config <<<<<
660 22:10:26.093082 Enter into PICG configuration >>>>
661 22:10:26.096610 Exit from PICG configuration <<<<
662 22:10:26.100300 [RX_INPUT] configuration >>>>>
663 22:10:26.100800 [RX_INPUT] configuration <<<<<
664 22:10:26.106408 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 22:10:26.113243 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 22:10:26.116702 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 22:10:26.122984 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 22:10:26.129664 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 22:10:26.136427 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 22:10:26.139807 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 22:10:26.143288 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 22:10:26.149713 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 22:10:26.153660 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 22:10:26.156704 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 22:10:26.159876 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 22:10:26.162919 ===================================
677 22:10:26.166741 LPDDR4 DRAM CONFIGURATION
678 22:10:26.169762 ===================================
679 22:10:26.173075 EX_ROW_EN[0] = 0x0
680 22:10:26.173500 EX_ROW_EN[1] = 0x0
681 22:10:26.176351 LP4Y_EN = 0x0
682 22:10:26.176699 WORK_FSP = 0x0
683 22:10:26.179706 WL = 0x2
684 22:10:26.180020 RL = 0x2
685 22:10:26.183558 BL = 0x2
686 22:10:26.183916 RPST = 0x0
687 22:10:26.186633 RD_PRE = 0x0
688 22:10:26.186988 WR_PRE = 0x1
689 22:10:26.189841 WR_PST = 0x0
690 22:10:26.190199 DBI_WR = 0x0
691 22:10:26.193583 DBI_RD = 0x0
692 22:10:26.193935 OTF = 0x1
693 22:10:26.196740 ===================================
694 22:10:26.203310 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 22:10:26.206585 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 22:10:26.209912 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 22:10:26.213337 ===================================
698 22:10:26.216714 LPDDR4 DRAM CONFIGURATION
699 22:10:26.219992 ===================================
700 22:10:26.223016 EX_ROW_EN[0] = 0x10
701 22:10:26.223391 EX_ROW_EN[1] = 0x0
702 22:10:26.226491 LP4Y_EN = 0x0
703 22:10:26.226980 WORK_FSP = 0x0
704 22:10:26.229979 WL = 0x2
705 22:10:26.230476 RL = 0x2
706 22:10:26.233133 BL = 0x2
707 22:10:26.233548 RPST = 0x0
708 22:10:26.236676 RD_PRE = 0x0
709 22:10:26.237179 WR_PRE = 0x1
710 22:10:26.239564 WR_PST = 0x0
711 22:10:26.239938 DBI_WR = 0x0
712 22:10:26.243213 DBI_RD = 0x0
713 22:10:26.243563 OTF = 0x1
714 22:10:26.247018 ===================================
715 22:10:26.252897 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 22:10:26.257813 nWR fixed to 40
717 22:10:26.260722 [ModeRegInit_LP4] CH0 RK0
718 22:10:26.261084 [ModeRegInit_LP4] CH0 RK1
719 22:10:26.264402 [ModeRegInit_LP4] CH1 RK0
720 22:10:26.267760 [ModeRegInit_LP4] CH1 RK1
721 22:10:26.268228 match AC timing 12
722 22:10:26.274238 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
723 22:10:26.278148 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 22:10:26.280926 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 22:10:26.287892 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 22:10:26.291253 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 22:10:26.291719 [EMI DOE] emi_dcm 0
728 22:10:26.298117 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 22:10:26.298615 ==
730 22:10:26.301406 Dram Type= 6, Freq= 0, CH_0, rank 0
731 22:10:26.305024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
732 22:10:26.305562 ==
733 22:10:26.311426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 22:10:26.317825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 22:10:26.324895 [CA 0] Center 37 (7~68) winsize 62
736 22:10:26.328469 [CA 1] Center 37 (7~68) winsize 62
737 22:10:26.331709 [CA 2] Center 35 (5~66) winsize 62
738 22:10:26.335316 [CA 3] Center 35 (5~66) winsize 62
739 22:10:26.338805 [CA 4] Center 34 (4~65) winsize 62
740 22:10:26.341511 [CA 5] Center 34 (3~65) winsize 63
741 22:10:26.342004
742 22:10:26.345036 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 22:10:26.345548
744 22:10:26.348485 [CATrainingPosCal] consider 1 rank data
745 22:10:26.351582 u2DelayCellTimex100 = 270/100 ps
746 22:10:26.355678 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
747 22:10:26.358505 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
748 22:10:26.364988 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
749 22:10:26.368489 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
750 22:10:26.372098 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
751 22:10:26.374869 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
752 22:10:26.375272
753 22:10:26.377829 CA PerBit enable=1, Macro0, CA PI delay=34
754 22:10:26.378215
755 22:10:26.381863 [CBTSetCACLKResult] CA Dly = 34
756 22:10:26.382319 CS Dly: 6 (0~37)
757 22:10:26.382597 ==
758 22:10:26.384883 Dram Type= 6, Freq= 0, CH_0, rank 1
759 22:10:26.391834 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
760 22:10:26.392192 ==
761 22:10:26.395008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 22:10:26.401632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 22:10:26.410686 [CA 0] Center 37 (7~68) winsize 62
764 22:10:26.414476 [CA 1] Center 37 (6~68) winsize 63
765 22:10:26.417399 [CA 2] Center 35 (4~66) winsize 63
766 22:10:26.420747 [CA 3] Center 34 (4~65) winsize 62
767 22:10:26.423746 [CA 4] Center 33 (3~64) winsize 62
768 22:10:26.427873 [CA 5] Center 34 (3~65) winsize 63
769 22:10:26.428383
770 22:10:26.430544 [CmdBusTrainingLP45] Vref(ca) range 1: 32
771 22:10:26.430918
772 22:10:26.434617 [CATrainingPosCal] consider 2 rank data
773 22:10:26.437641 u2DelayCellTimex100 = 270/100 ps
774 22:10:26.440542 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
775 22:10:26.443866 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
776 22:10:26.450486 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
777 22:10:26.454173 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
778 22:10:26.457749 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
779 22:10:26.460429 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
780 22:10:26.460826
781 22:10:26.464468 CA PerBit enable=1, Macro0, CA PI delay=34
782 22:10:26.464844
783 22:10:26.468190 [CBTSetCACLKResult] CA Dly = 34
784 22:10:26.468661 CS Dly: 6 (0~37)
785 22:10:26.468941
786 22:10:26.472561 ----->DramcWriteLeveling(PI) begin...
787 22:10:26.473022 ==
788 22:10:26.475152 Dram Type= 6, Freq= 0, CH_0, rank 0
789 22:10:26.478934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
790 22:10:26.479368 ==
791 22:10:26.482333 Write leveling (Byte 0): 29 => 29
792 22:10:26.485385 Write leveling (Byte 1): 28 => 28
793 22:10:26.489265 DramcWriteLeveling(PI) end<-----
794 22:10:26.489719
795 22:10:26.489969 ==
796 22:10:26.493007 Dram Type= 6, Freq= 0, CH_0, rank 0
797 22:10:26.496227 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
798 22:10:26.496682 ==
799 22:10:26.499334 [Gating] SW mode calibration
800 22:10:26.506205 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 22:10:26.513104 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 22:10:26.516345 0 6 0 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0)
803 22:10:26.519370 0 6 4 | B1->B0 | 2626 2525 | 0 0 | (1 1) (1 1)
804 22:10:26.526140 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:10:26.529398 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:10:26.533010 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:10:26.539644 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:10:26.542430 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:10:26.546541 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:10:26.553043 0 7 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
811 22:10:26.556332 0 7 4 | B1->B0 | 3a3a 3e3e | 0 0 | (0 0) (1 1)
812 22:10:26.559436 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
813 22:10:26.566195 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
814 22:10:26.569463 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
815 22:10:26.573302 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
816 22:10:26.576299 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
817 22:10:26.582916 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
818 22:10:26.586252 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
819 22:10:26.589558 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
820 22:10:26.596602 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
821 22:10:26.599644 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
822 22:10:26.603496 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
823 22:10:26.609603 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
824 22:10:26.613152 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
825 22:10:26.616351 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
826 22:10:26.623285 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
827 22:10:26.626489 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
828 22:10:26.630049 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
829 22:10:26.637103 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
830 22:10:26.640166 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 22:10:26.643115 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 22:10:26.646781 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 22:10:26.653657 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 22:10:26.656862 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
835 22:10:26.660450 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
836 22:10:26.663257 Total UI for P1: 0, mck2ui 16
837 22:10:26.667026 best dqsien dly found for B1: ( 0, 10, 2)
838 22:10:26.673288 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 22:10:26.676979 Total UI for P1: 0, mck2ui 16
840 22:10:26.680318 best dqsien dly found for B0: ( 0, 10, 2)
841 22:10:26.683169 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
842 22:10:26.686487 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
843 22:10:26.686881
844 22:10:26.690164 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
845 22:10:26.693074 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
846 22:10:26.696703 [Gating] SW calibration Done
847 22:10:26.697207 ==
848 22:10:26.699781 Dram Type= 6, Freq= 0, CH_0, rank 0
849 22:10:26.703580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
850 22:10:26.703969 ==
851 22:10:26.706820 RX Vref Scan: 0
852 22:10:26.707287
853 22:10:26.707551 RX Vref 0 -> 0, step: 1
854 22:10:26.707771
855 22:10:26.709929 RX Delay -130 -> 252, step: 16
856 22:10:26.717038 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
857 22:10:26.720329 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
858 22:10:26.723299 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
859 22:10:26.726511 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
860 22:10:26.730079 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
861 22:10:26.733456 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
862 22:10:26.740167 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
863 22:10:26.743865 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
864 22:10:26.746841 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
865 22:10:26.750027 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
866 22:10:26.753417 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
867 22:10:26.760528 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
868 22:10:26.763772 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
869 22:10:26.766894 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
870 22:10:26.770868 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
871 22:10:26.776605 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
872 22:10:26.777072 ==
873 22:10:26.779668 Dram Type= 6, Freq= 0, CH_0, rank 0
874 22:10:26.783524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
875 22:10:26.784036 ==
876 22:10:26.784354 DQS Delay:
877 22:10:26.786743 DQS0 = 0, DQS1 = 0
878 22:10:26.787142 DQM Delay:
879 22:10:26.789961 DQM0 = 84, DQM1 = 74
880 22:10:26.790350 DQ Delay:
881 22:10:26.793184 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
882 22:10:26.796451 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
883 22:10:26.800368 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
884 22:10:26.804067 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
885 22:10:26.804574
886 22:10:26.804871
887 22:10:26.805094 ==
888 22:10:26.806678 Dram Type= 6, Freq= 0, CH_0, rank 0
889 22:10:26.809651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
890 22:10:26.809959 ==
891 22:10:26.810192
892 22:10:26.810403
893 22:10:26.813736 TX Vref Scan disable
894 22:10:26.816973 == TX Byte 0 ==
895 22:10:26.820025 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
896 22:10:26.823660 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
897 22:10:26.826533 == TX Byte 1 ==
898 22:10:26.830144 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
899 22:10:26.833071 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
900 22:10:26.833466 ==
901 22:10:26.836425 Dram Type= 6, Freq= 0, CH_0, rank 0
902 22:10:26.840151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
903 22:10:26.843149 ==
904 22:10:26.854383 TX Vref=22, minBit 0, minWin=27, winSum=445
905 22:10:26.857979 TX Vref=24, minBit 0, minWin=27, winSum=445
906 22:10:26.861051 TX Vref=26, minBit 4, minWin=27, winSum=450
907 22:10:26.864828 TX Vref=28, minBit 0, minWin=28, winSum=457
908 22:10:26.868279 TX Vref=30, minBit 0, minWin=28, winSum=456
909 22:10:26.871627 TX Vref=32, minBit 5, minWin=27, winSum=450
910 22:10:26.878169 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
911 22:10:26.878630
912 22:10:26.881805 Final TX Range 1 Vref 28
913 22:10:26.882165
914 22:10:26.882419 ==
915 22:10:26.885056 Dram Type= 6, Freq= 0, CH_0, rank 0
916 22:10:26.888116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
917 22:10:26.888517 ==
918 22:10:26.888794
919 22:10:26.889029
920 22:10:26.892086 TX Vref Scan disable
921 22:10:26.894868 == TX Byte 0 ==
922 22:10:26.898858 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
923 22:10:26.901671 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
924 22:10:26.905841 == TX Byte 1 ==
925 22:10:26.908423 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
926 22:10:26.911916 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
927 22:10:26.912418
928 22:10:26.915413 [DATLAT]
929 22:10:26.915805 Freq=800, CH0 RK0
930 22:10:26.916115
931 22:10:26.918816 DATLAT Default: 0xa
932 22:10:26.919312 0, 0xFFFF, sum = 0
933 22:10:26.921754 1, 0xFFFF, sum = 0
934 22:10:26.922149 2, 0xFFFF, sum = 0
935 22:10:26.925039 3, 0xFFFF, sum = 0
936 22:10:26.925545 4, 0xFFFF, sum = 0
937 22:10:26.928591 5, 0xFFFF, sum = 0
938 22:10:26.929078 6, 0xFFFF, sum = 0
939 22:10:26.932091 7, 0xFFFF, sum = 0
940 22:10:26.932484 8, 0x0, sum = 1
941 22:10:26.935456 9, 0x0, sum = 2
942 22:10:26.935936 10, 0x0, sum = 3
943 22:10:26.938703 11, 0x0, sum = 4
944 22:10:26.939192 best_step = 9
945 22:10:26.939475
946 22:10:26.939717 ==
947 22:10:26.941960 Dram Type= 6, Freq= 0, CH_0, rank 0
948 22:10:26.945166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
949 22:10:26.945519 ==
950 22:10:26.948632 RX Vref Scan: 1
951 22:10:26.949105
952 22:10:26.952101 Set Vref Range= 32 -> 127
953 22:10:26.952494
954 22:10:26.952745 RX Vref 32 -> 127, step: 1
955 22:10:26.952973
956 22:10:26.955455 RX Delay -111 -> 252, step: 8
957 22:10:26.955899
958 22:10:26.958632 Set Vref, RX VrefLevel [Byte0]: 32
959 22:10:26.962187 [Byte1]: 32
960 22:10:26.965554
961 22:10:26.966044 Set Vref, RX VrefLevel [Byte0]: 33
962 22:10:26.971612 [Byte1]: 33
963 22:10:26.972055
964 22:10:26.975179 Set Vref, RX VrefLevel [Byte0]: 34
965 22:10:26.978483 [Byte1]: 34
966 22:10:26.978877
967 22:10:26.981343 Set Vref, RX VrefLevel [Byte0]: 35
968 22:10:26.984548 [Byte1]: 35
969 22:10:26.988094
970 22:10:26.988598 Set Vref, RX VrefLevel [Byte0]: 36
971 22:10:26.991729 [Byte1]: 36
972 22:10:26.995910
973 22:10:26.996261 Set Vref, RX VrefLevel [Byte0]: 37
974 22:10:26.999109 [Byte1]: 37
975 22:10:27.003345
976 22:10:27.003906 Set Vref, RX VrefLevel [Byte0]: 38
977 22:10:27.007209 [Byte1]: 38
978 22:10:27.010924
979 22:10:27.011304 Set Vref, RX VrefLevel [Byte0]: 39
980 22:10:27.015039 [Byte1]: 39
981 22:10:27.019170
982 22:10:27.019841 Set Vref, RX VrefLevel [Byte0]: 40
983 22:10:27.021974 [Byte1]: 40
984 22:10:27.026199
985 22:10:27.026582 Set Vref, RX VrefLevel [Byte0]: 41
986 22:10:27.029703 [Byte1]: 41
987 22:10:27.034013
988 22:10:27.034360 Set Vref, RX VrefLevel [Byte0]: 42
989 22:10:27.037426 [Byte1]: 42
990 22:10:27.041517
991 22:10:27.041863 Set Vref, RX VrefLevel [Byte0]: 43
992 22:10:27.044761 [Byte1]: 43
993 22:10:27.049512
994 22:10:27.050041 Set Vref, RX VrefLevel [Byte0]: 44
995 22:10:27.052698 [Byte1]: 44
996 22:10:27.056935
997 22:10:27.057277 Set Vref, RX VrefLevel [Byte0]: 45
998 22:10:27.060580 [Byte1]: 45
999 22:10:27.064888
1000 22:10:27.065410 Set Vref, RX VrefLevel [Byte0]: 46
1001 22:10:27.068059 [Byte1]: 46
1002 22:10:27.072813
1003 22:10:27.073342 Set Vref, RX VrefLevel [Byte0]: 47
1004 22:10:27.075789 [Byte1]: 47
1005 22:10:27.079556
1006 22:10:27.080102 Set Vref, RX VrefLevel [Byte0]: 48
1007 22:10:27.083098 [Byte1]: 48
1008 22:10:27.087499
1009 22:10:27.087985 Set Vref, RX VrefLevel [Byte0]: 49
1010 22:10:27.090588 [Byte1]: 49
1011 22:10:27.095220
1012 22:10:27.095606 Set Vref, RX VrefLevel [Byte0]: 50
1013 22:10:27.098930 [Byte1]: 50
1014 22:10:27.102862
1015 22:10:27.103259 Set Vref, RX VrefLevel [Byte0]: 51
1016 22:10:27.106133 [Byte1]: 51
1017 22:10:27.110623
1018 22:10:27.110972 Set Vref, RX VrefLevel [Byte0]: 52
1019 22:10:27.113247 [Byte1]: 52
1020 22:10:27.117929
1021 22:10:27.118278 Set Vref, RX VrefLevel [Byte0]: 53
1022 22:10:27.121344 [Byte1]: 53
1023 22:10:27.126426
1024 22:10:27.126805 Set Vref, RX VrefLevel [Byte0]: 54
1025 22:10:27.128919 [Byte1]: 54
1026 22:10:27.133557
1027 22:10:27.134007 Set Vref, RX VrefLevel [Byte0]: 55
1028 22:10:27.137137 [Byte1]: 55
1029 22:10:27.140783
1030 22:10:27.141103 Set Vref, RX VrefLevel [Byte0]: 56
1031 22:10:27.144698 [Byte1]: 56
1032 22:10:27.149094
1033 22:10:27.149601 Set Vref, RX VrefLevel [Byte0]: 57
1034 22:10:27.152002 [Byte1]: 57
1035 22:10:27.156775
1036 22:10:27.159851 Set Vref, RX VrefLevel [Byte0]: 58
1037 22:10:27.160394 [Byte1]: 58
1038 22:10:27.164236
1039 22:10:27.164663 Set Vref, RX VrefLevel [Byte0]: 59
1040 22:10:27.167438 [Byte1]: 59
1041 22:10:27.171728
1042 22:10:27.172069 Set Vref, RX VrefLevel [Byte0]: 60
1043 22:10:27.175237 [Byte1]: 60
1044 22:10:27.179238
1045 22:10:27.179552 Set Vref, RX VrefLevel [Byte0]: 61
1046 22:10:27.182592 [Byte1]: 61
1047 22:10:27.186907
1048 22:10:27.187253 Set Vref, RX VrefLevel [Byte0]: 62
1049 22:10:27.191003 [Byte1]: 62
1050 22:10:27.194433
1051 22:10:27.194783 Set Vref, RX VrefLevel [Byte0]: 63
1052 22:10:27.198116 [Byte1]: 63
1053 22:10:27.202092
1054 22:10:27.202435 Set Vref, RX VrefLevel [Byte0]: 64
1055 22:10:27.205347 [Byte1]: 64
1056 22:10:27.209583
1057 22:10:27.209936 Set Vref, RX VrefLevel [Byte0]: 65
1058 22:10:27.213380 [Byte1]: 65
1059 22:10:27.217619
1060 22:10:27.218053 Set Vref, RX VrefLevel [Byte0]: 66
1061 22:10:27.221124 [Byte1]: 66
1062 22:10:27.225383
1063 22:10:27.225837 Set Vref, RX VrefLevel [Byte0]: 67
1064 22:10:27.228474 [Byte1]: 67
1065 22:10:27.232716
1066 22:10:27.233163 Set Vref, RX VrefLevel [Byte0]: 68
1067 22:10:27.235869 [Byte1]: 68
1068 22:10:27.240296
1069 22:10:27.240699 Set Vref, RX VrefLevel [Byte0]: 69
1070 22:10:27.243306 [Byte1]: 69
1071 22:10:27.248151
1072 22:10:27.248605 Set Vref, RX VrefLevel [Byte0]: 70
1073 22:10:27.251156 [Byte1]: 70
1074 22:10:27.255747
1075 22:10:27.256197 Set Vref, RX VrefLevel [Byte0]: 71
1076 22:10:27.258832 [Byte1]: 71
1077 22:10:27.263566
1078 22:10:27.264013 Set Vref, RX VrefLevel [Byte0]: 72
1079 22:10:27.266572 [Byte1]: 72
1080 22:10:27.271015
1081 22:10:27.271487 Set Vref, RX VrefLevel [Byte0]: 73
1082 22:10:27.274888 [Byte1]: 73
1083 22:10:27.278766
1084 22:10:27.279238 Set Vref, RX VrefLevel [Byte0]: 74
1085 22:10:27.281590 [Byte1]: 74
1086 22:10:27.286657
1087 22:10:27.287135 Final RX Vref Byte 0 = 53 to rank0
1088 22:10:27.289603 Final RX Vref Byte 1 = 56 to rank0
1089 22:10:27.293118 Final RX Vref Byte 0 = 53 to rank1
1090 22:10:27.296687 Final RX Vref Byte 1 = 56 to rank1==
1091 22:10:27.299780 Dram Type= 6, Freq= 0, CH_0, rank 0
1092 22:10:27.306415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1093 22:10:27.306904 ==
1094 22:10:27.307182 DQS Delay:
1095 22:10:27.307413 DQS0 = 0, DQS1 = 0
1096 22:10:27.309664 DQM Delay:
1097 22:10:27.310143 DQM0 = 83, DQM1 = 73
1098 22:10:27.313261 DQ Delay:
1099 22:10:27.316605 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1100 22:10:27.317103 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1101 22:10:27.319816 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1102 22:10:27.323056 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1103 22:10:27.326357
1104 22:10:27.326732
1105 22:10:27.333156 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1106 22:10:27.336578 CH0 RK0: MR19=606, MR18=3B3B
1107 22:10:27.343241 CH0_RK0: MR19=0x606, MR18=0x3B3B, DQSOSC=394, MR23=63, INC=95, DEC=63
1108 22:10:27.343753
1109 22:10:27.346270 ----->DramcWriteLeveling(PI) begin...
1110 22:10:27.346655 ==
1111 22:10:27.349608 Dram Type= 6, Freq= 0, CH_0, rank 1
1112 22:10:27.353011 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1113 22:10:27.353474 ==
1114 22:10:27.356647 Write leveling (Byte 0): 26 => 26
1115 22:10:27.359610 Write leveling (Byte 1): 26 => 26
1116 22:10:27.363268 DramcWriteLeveling(PI) end<-----
1117 22:10:27.363854
1118 22:10:27.364174 ==
1119 22:10:27.366472 Dram Type= 6, Freq= 0, CH_0, rank 1
1120 22:10:27.369521 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1121 22:10:27.369933 ==
1122 22:10:27.373035 [Gating] SW mode calibration
1123 22:10:27.379344 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1124 22:10:27.386404 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1125 22:10:27.389434 0 6 0 | B1->B0 | 3030 3232 | 0 0 | (0 1) (0 1)
1126 22:10:27.393464 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1127 22:10:27.400178 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1128 22:10:27.403374 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1129 22:10:27.406364 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1130 22:10:27.413285 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1131 22:10:27.416376 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1132 22:10:27.419814 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1133 22:10:27.426210 0 7 0 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
1134 22:10:27.429958 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1135 22:10:27.433050 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1136 22:10:27.436632 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1137 22:10:27.443161 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1138 22:10:27.446297 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1139 22:10:27.449829 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1140 22:10:27.456874 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1141 22:10:27.459993 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1142 22:10:27.463193 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1143 22:10:27.469630 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1144 22:10:27.473109 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1145 22:10:27.476785 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1146 22:10:27.483663 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1147 22:10:27.486281 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1148 22:10:27.489742 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1149 22:10:27.496634 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1150 22:10:27.499853 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1151 22:10:27.503246 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1152 22:10:27.509640 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1153 22:10:27.513766 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1154 22:10:27.516838 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1155 22:10:27.523263 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1156 22:10:27.526743 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1157 22:10:27.530104 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1158 22:10:27.533342 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1159 22:10:27.536977 Total UI for P1: 0, mck2ui 16
1160 22:10:27.580742 best dqsien dly found for B0: ( 0, 10, 0)
1161 22:10:27.581636 Total UI for P1: 0, mck2ui 16
1162 22:10:27.581995 best dqsien dly found for B1: ( 0, 10, 0)
1163 22:10:27.582377 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1164 22:10:27.582703 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1165 22:10:27.582937
1166 22:10:27.583160 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1167 22:10:27.583382 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1168 22:10:27.583601 [Gating] SW calibration Done
1169 22:10:27.583821 ==
1170 22:10:27.584040 Dram Type= 6, Freq= 0, CH_0, rank 1
1171 22:10:27.584258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1172 22:10:27.584477 ==
1173 22:10:27.584691 RX Vref Scan: 0
1174 22:10:27.584903
1175 22:10:27.585169 RX Vref 0 -> 0, step: 1
1176 22:10:27.585465
1177 22:10:27.585692 RX Delay -130 -> 252, step: 16
1178 22:10:27.621218 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1179 22:10:27.621819 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1180 22:10:27.622116 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1181 22:10:27.622429 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1182 22:10:27.622674 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1183 22:10:27.622900 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1184 22:10:27.623412 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1185 22:10:27.623673 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1186 22:10:27.623906 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1187 22:10:27.624129 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1188 22:10:27.625069 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1189 22:10:27.628902 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1190 22:10:27.631856 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1191 22:10:27.635154 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1192 22:10:27.638710 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1193 22:10:27.645765 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1194 22:10:27.646243 ==
1195 22:10:27.648124 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 22:10:27.652029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1197 22:10:27.652517 ==
1198 22:10:27.652798 DQS Delay:
1199 22:10:27.654698 DQS0 = 0, DQS1 = 0
1200 22:10:27.655073 DQM Delay:
1201 22:10:27.658453 DQM0 = 86, DQM1 = 75
1202 22:10:27.658937 DQ Delay:
1203 22:10:27.661614 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1204 22:10:27.665126 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1205 22:10:27.668605 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
1206 22:10:27.672102 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1207 22:10:27.672584
1208 22:10:27.672858
1209 22:10:27.673089 ==
1210 22:10:27.675213 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 22:10:27.678483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1212 22:10:27.678878 ==
1213 22:10:27.679151
1214 22:10:27.679389
1215 22:10:27.681589 TX Vref Scan disable
1216 22:10:27.685242 == TX Byte 0 ==
1217 22:10:27.688341 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1218 22:10:27.692012 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1219 22:10:27.695439 == TX Byte 1 ==
1220 22:10:27.698613 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1221 22:10:27.702201 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1222 22:10:27.702687 ==
1223 22:10:27.705020 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 22:10:27.711837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1225 22:10:27.712313 ==
1226 22:10:27.720687 TX Vref=22, minBit 13, minWin=26, winSum=439
1227 22:10:27.727437 TX Vref=24, minBit 0, minWin=27, winSum=444
1228 22:10:27.731241 TX Vref=26, minBit 14, minWin=27, winSum=450
1229 22:10:27.734684 TX Vref=28, minBit 0, minWin=28, winSum=455
1230 22:10:27.738361 TX Vref=30, minBit 0, minWin=28, winSum=455
1231 22:10:27.741552 TX Vref=32, minBit 6, minWin=27, winSum=454
1232 22:10:27.748041 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
1233 22:10:27.748419
1234 22:10:27.748688 Final TX Range 1 Vref 28
1235 22:10:27.751680
1236 22:10:27.752160 ==
1237 22:10:27.754490 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 22:10:27.758276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1239 22:10:27.758802 ==
1240 22:10:27.759124
1241 22:10:27.759361
1242 22:10:27.761597 TX Vref Scan disable
1243 22:10:27.761973 == TX Byte 0 ==
1244 22:10:27.768442 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1245 22:10:27.771251 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1246 22:10:27.771705 == TX Byte 1 ==
1247 22:10:27.778237 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1248 22:10:27.781419 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1249 22:10:27.781801
1250 22:10:27.782074 [DATLAT]
1251 22:10:27.784389 Freq=800, CH0 RK1
1252 22:10:27.784768
1253 22:10:27.785030 DATLAT Default: 0x9
1254 22:10:27.788411 0, 0xFFFF, sum = 0
1255 22:10:27.788914 1, 0xFFFF, sum = 0
1256 22:10:27.791710 2, 0xFFFF, sum = 0
1257 22:10:27.792200 3, 0xFFFF, sum = 0
1258 22:10:27.794774 4, 0xFFFF, sum = 0
1259 22:10:27.798141 5, 0xFFFF, sum = 0
1260 22:10:27.798625 6, 0xFFFF, sum = 0
1261 22:10:27.801527 7, 0xFFFF, sum = 0
1262 22:10:27.802017 8, 0x0, sum = 1
1263 22:10:27.802295 9, 0x0, sum = 2
1264 22:10:27.804975 10, 0x0, sum = 3
1265 22:10:27.805505 11, 0x0, sum = 4
1266 22:10:27.808583 best_step = 9
1267 22:10:27.809068
1268 22:10:27.809386 ==
1269 22:10:27.811479 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 22:10:27.814563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1271 22:10:27.814945 ==
1272 22:10:27.818502 RX Vref Scan: 0
1273 22:10:27.818986
1274 22:10:27.819274 RX Vref 0 -> 0, step: 1
1275 22:10:27.819515
1276 22:10:27.821842 RX Delay -111 -> 252, step: 8
1277 22:10:27.828067 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1278 22:10:27.831346 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1279 22:10:27.834597 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1280 22:10:27.837780 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1281 22:10:27.841366 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1282 22:10:27.848054 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1283 22:10:27.851160 iDelay=217, Bit 6, Center 96 (-23 ~ 216) 240
1284 22:10:27.854510 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1285 22:10:27.857626 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1286 22:10:27.861336 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1287 22:10:27.867815 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1288 22:10:27.871315 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1289 22:10:27.874325 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1290 22:10:27.877468 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1291 22:10:27.884240 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1292 22:10:27.887683 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1293 22:10:27.888070 ==
1294 22:10:27.891211 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 22:10:27.894404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1296 22:10:27.894762 ==
1297 22:10:27.895009 DQS Delay:
1298 22:10:27.897880 DQS0 = 0, DQS1 = 0
1299 22:10:27.898222 DQM Delay:
1300 22:10:27.900854 DQM0 = 86, DQM1 = 74
1301 22:10:27.901198 DQ Delay:
1302 22:10:27.904485 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =80
1303 22:10:27.908153 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1304 22:10:27.911395 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1305 22:10:27.914908 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =80
1306 22:10:27.915369
1307 22:10:27.915630
1308 22:10:27.924124 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1309 22:10:27.924472 CH0 RK1: MR19=606, MR18=4B4B
1310 22:10:27.930643 CH0_RK1: MR19=0x606, MR18=0x4B4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1311 22:10:27.934812 [RxdqsGatingPostProcess] freq 800
1312 22:10:27.941401 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1313 22:10:27.944571 Pre-setting of DQS Precalculation
1314 22:10:27.947501 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1315 22:10:27.947842 ==
1316 22:10:27.950965 Dram Type= 6, Freq= 0, CH_1, rank 0
1317 22:10:27.954332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1318 22:10:27.954721 ==
1319 22:10:27.961173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1320 22:10:27.967965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1321 22:10:27.976036 [CA 0] Center 37 (6~68) winsize 63
1322 22:10:27.979489 [CA 1] Center 37 (6~68) winsize 63
1323 22:10:27.982401 [CA 2] Center 34 (4~65) winsize 62
1324 22:10:27.986015 [CA 3] Center 34 (4~65) winsize 62
1325 22:10:27.989018 [CA 4] Center 33 (3~64) winsize 62
1326 22:10:27.992478 [CA 5] Center 33 (3~64) winsize 62
1327 22:10:27.992920
1328 22:10:27.996061 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1329 22:10:27.996513
1330 22:10:27.999052 [CATrainingPosCal] consider 1 rank data
1331 22:10:28.002645 u2DelayCellTimex100 = 270/100 ps
1332 22:10:28.006553 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1333 22:10:28.009650 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1334 22:10:28.016353 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1335 22:10:28.019653 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1336 22:10:28.022748 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1337 22:10:28.026232 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1338 22:10:28.026704
1339 22:10:28.029372 CA PerBit enable=1, Macro0, CA PI delay=33
1340 22:10:28.029853
1341 22:10:28.032776 [CBTSetCACLKResult] CA Dly = 33
1342 22:10:28.033260 CS Dly: 5 (0~36)
1343 22:10:28.033575 ==
1344 22:10:28.036168 Dram Type= 6, Freq= 0, CH_1, rank 1
1345 22:10:28.043270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1346 22:10:28.043754 ==
1347 22:10:28.046451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1348 22:10:28.053040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1349 22:10:28.061886 [CA 0] Center 37 (6~68) winsize 63
1350 22:10:28.065183 [CA 1] Center 37 (6~68) winsize 63
1351 22:10:28.068737 [CA 2] Center 34 (4~65) winsize 62
1352 22:10:28.071888 [CA 3] Center 34 (4~65) winsize 62
1353 22:10:28.075272 [CA 4] Center 33 (3~64) winsize 62
1354 22:10:28.078588 [CA 5] Center 33 (3~64) winsize 62
1355 22:10:28.078976
1356 22:10:28.081684 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1357 22:10:28.082086
1358 22:10:28.084988 [CATrainingPosCal] consider 2 rank data
1359 22:10:28.088573 u2DelayCellTimex100 = 270/100 ps
1360 22:10:28.091414 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1361 22:10:28.095185 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1362 22:10:28.101969 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1363 22:10:28.105161 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1364 22:10:28.108234 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1365 22:10:28.111651 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1366 22:10:28.112124
1367 22:10:28.115131 CA PerBit enable=1, Macro0, CA PI delay=33
1368 22:10:28.115619
1369 22:10:28.118352 [CBTSetCACLKResult] CA Dly = 33
1370 22:10:28.118730 CS Dly: 5 (0~36)
1371 22:10:28.118998
1372 22:10:28.122250 ----->DramcWriteLeveling(PI) begin...
1373 22:10:28.125035 ==
1374 22:10:28.125542 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 22:10:28.131719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1376 22:10:28.132227 ==
1377 22:10:28.135145 Write leveling (Byte 0): 23 => 23
1378 22:10:28.138435 Write leveling (Byte 1): 25 => 25
1379 22:10:28.138916 DramcWriteLeveling(PI) end<-----
1380 22:10:28.142343
1381 22:10:28.142767 ==
1382 22:10:28.144919 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 22:10:28.148902 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1384 22:10:28.149395 ==
1385 22:10:28.151906 [Gating] SW mode calibration
1386 22:10:28.158712 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1387 22:10:28.162111 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1388 22:10:28.169085 0 6 0 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
1389 22:10:28.172087 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1390 22:10:28.175121 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1391 22:10:28.181926 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1392 22:10:28.185220 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1393 22:10:28.188568 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1394 22:10:28.195191 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1395 22:10:28.198449 0 6 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1396 22:10:28.201935 0 7 0 | B1->B0 | 3030 3f3f | 0 1 | (0 0) (0 0)
1397 22:10:28.208885 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
1398 22:10:28.211671 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1399 22:10:28.215471 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1400 22:10:28.218797 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1401 22:10:28.225108 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1402 22:10:28.228940 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1403 22:10:28.232187 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1404 22:10:28.238860 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 22:10:28.241890 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 22:10:28.245392 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1407 22:10:28.252211 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1408 22:10:28.255372 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1409 22:10:28.258834 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1410 22:10:28.265399 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1411 22:10:28.269054 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1412 22:10:28.272289 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1413 22:10:28.278964 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1414 22:10:28.282034 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1415 22:10:28.285452 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1416 22:10:28.292191 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1417 22:10:28.295682 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1418 22:10:28.298715 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1419 22:10:28.302559 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1420 22:10:28.308507 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1421 22:10:28.312151 Total UI for P1: 0, mck2ui 16
1422 22:10:28.315740 best dqsien dly found for B0: ( 0, 9, 30)
1423 22:10:28.318939 Total UI for P1: 0, mck2ui 16
1424 22:10:28.322470 best dqsien dly found for B1: ( 0, 9, 30)
1425 22:10:28.325703 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1426 22:10:28.328983 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1427 22:10:28.329537
1428 22:10:28.331932 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1429 22:10:28.335385 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1430 22:10:28.338783 [Gating] SW calibration Done
1431 22:10:28.339264 ==
1432 22:10:28.342448 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 22:10:28.345020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1434 22:10:28.345423 ==
1435 22:10:28.348819 RX Vref Scan: 0
1436 22:10:28.349379
1437 22:10:28.352067 RX Vref 0 -> 0, step: 1
1438 22:10:28.352539
1439 22:10:28.352817 RX Delay -130 -> 252, step: 16
1440 22:10:28.358709 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1441 22:10:28.362078 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1442 22:10:28.365242 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1443 22:10:28.368654 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1444 22:10:28.372259 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1445 22:10:28.375924 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1446 22:10:28.383131 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1447 22:10:28.386717 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1448 22:10:28.389676 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1449 22:10:28.393387 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1450 22:10:28.397279 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1451 22:10:28.401026 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1452 22:10:28.404719 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1453 22:10:28.408535 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1454 22:10:28.415091 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1455 22:10:28.418240 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1456 22:10:28.418723 ==
1457 22:10:28.421652 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 22:10:28.424777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1459 22:10:28.425258 ==
1460 22:10:28.425588 DQS Delay:
1461 22:10:28.428691 DQS0 = 0, DQS1 = 0
1462 22:10:28.429175 DQM Delay:
1463 22:10:28.431888 DQM0 = 83, DQM1 = 75
1464 22:10:28.432374 DQ Delay:
1465 22:10:28.434872 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1466 22:10:28.438194 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =85
1467 22:10:28.441787 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1468 22:10:28.444794 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1469 22:10:28.445282
1470 22:10:28.445642
1471 22:10:28.445918 ==
1472 22:10:28.448394 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 22:10:28.451078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1474 22:10:28.454371 ==
1475 22:10:28.454746
1476 22:10:28.455013
1477 22:10:28.455304 TX Vref Scan disable
1478 22:10:28.458038 == TX Byte 0 ==
1479 22:10:28.461112 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1480 22:10:28.464436 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1481 22:10:28.468103 == TX Byte 1 ==
1482 22:10:28.471470 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1483 22:10:28.474526 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1484 22:10:28.477963 ==
1485 22:10:28.481662 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 22:10:28.484573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1487 22:10:28.485079 ==
1488 22:10:28.497166 TX Vref=22, minBit 3, minWin=27, winSum=447
1489 22:10:28.500230 TX Vref=24, minBit 3, minWin=27, winSum=450
1490 22:10:28.503960 TX Vref=26, minBit 3, minWin=27, winSum=452
1491 22:10:28.507276 TX Vref=28, minBit 0, minWin=28, winSum=453
1492 22:10:28.510091 TX Vref=30, minBit 0, minWin=28, winSum=461
1493 22:10:28.513345 TX Vref=32, minBit 9, minWin=27, winSum=455
1494 22:10:28.520371 [TxChooseVref] Worse bit 0, Min win 28, Win sum 461, Final Vref 30
1495 22:10:28.520862
1496 22:10:28.523795 Final TX Range 1 Vref 30
1497 22:10:28.524176
1498 22:10:28.524443 ==
1499 22:10:28.526816 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 22:10:28.530818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1501 22:10:28.531303 ==
1502 22:10:28.531577
1503 22:10:28.533916
1504 22:10:28.534398 TX Vref Scan disable
1505 22:10:28.537133 == TX Byte 0 ==
1506 22:10:28.540530 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1507 22:10:28.543826 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1508 22:10:28.547070 == TX Byte 1 ==
1509 22:10:28.550437 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1510 22:10:28.554111 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1511 22:10:28.554599
1512 22:10:28.557407 [DATLAT]
1513 22:10:28.557891 Freq=800, CH1 RK0
1514 22:10:28.558168
1515 22:10:28.560273 DATLAT Default: 0xa
1516 22:10:28.560730 0, 0xFFFF, sum = 0
1517 22:10:28.563965 1, 0xFFFF, sum = 0
1518 22:10:28.564465 2, 0xFFFF, sum = 0
1519 22:10:28.567029 3, 0xFFFF, sum = 0
1520 22:10:28.567519 4, 0xFFFF, sum = 0
1521 22:10:28.570629 5, 0xFFFF, sum = 0
1522 22:10:28.570981 6, 0xFFFF, sum = 0
1523 22:10:28.573719 7, 0xFFFF, sum = 0
1524 22:10:28.574106 8, 0x0, sum = 1
1525 22:10:28.577043 9, 0x0, sum = 2
1526 22:10:28.577415 10, 0x0, sum = 3
1527 22:10:28.580615 11, 0x0, sum = 4
1528 22:10:28.581126 best_step = 9
1529 22:10:28.581467
1530 22:10:28.581713 ==
1531 22:10:28.583536 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 22:10:28.590376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1533 22:10:28.590791 ==
1534 22:10:28.591160 RX Vref Scan: 1
1535 22:10:28.591445
1536 22:10:28.593804 Set Vref Range= 32 -> 127
1537 22:10:28.594150
1538 22:10:28.596680 RX Vref 32 -> 127, step: 1
1539 22:10:28.597101
1540 22:10:28.597388 RX Delay -111 -> 252, step: 8
1541 22:10:28.597619
1542 22:10:28.600251 Set Vref, RX VrefLevel [Byte0]: 32
1543 22:10:28.603734 [Byte1]: 32
1544 22:10:28.607923
1545 22:10:28.608382 Set Vref, RX VrefLevel [Byte0]: 33
1546 22:10:28.611182 [Byte1]: 33
1547 22:10:28.615834
1548 22:10:28.616333 Set Vref, RX VrefLevel [Byte0]: 34
1549 22:10:28.618899 [Byte1]: 34
1550 22:10:28.623612
1551 22:10:28.624086 Set Vref, RX VrefLevel [Byte0]: 35
1552 22:10:28.626409 [Byte1]: 35
1553 22:10:28.631054
1554 22:10:28.631561 Set Vref, RX VrefLevel [Byte0]: 36
1555 22:10:28.634016 [Byte1]: 36
1556 22:10:28.638499
1557 22:10:28.638981 Set Vref, RX VrefLevel [Byte0]: 37
1558 22:10:28.641631 [Byte1]: 37
1559 22:10:28.646097
1560 22:10:28.646580 Set Vref, RX VrefLevel [Byte0]: 38
1561 22:10:28.649670 [Byte1]: 38
1562 22:10:28.653938
1563 22:10:28.654445 Set Vref, RX VrefLevel [Byte0]: 39
1564 22:10:28.656776 [Byte1]: 39
1565 22:10:28.661711
1566 22:10:28.662199 Set Vref, RX VrefLevel [Byte0]: 40
1567 22:10:28.664801 [Byte1]: 40
1568 22:10:28.669564
1569 22:10:28.670052 Set Vref, RX VrefLevel [Byte0]: 41
1570 22:10:28.672554 [Byte1]: 41
1571 22:10:28.676869
1572 22:10:28.677392 Set Vref, RX VrefLevel [Byte0]: 42
1573 22:10:28.680518 [Byte1]: 42
1574 22:10:28.684279
1575 22:10:28.684670 Set Vref, RX VrefLevel [Byte0]: 43
1576 22:10:28.687606 [Byte1]: 43
1577 22:10:28.691629
1578 22:10:28.691975 Set Vref, RX VrefLevel [Byte0]: 44
1579 22:10:28.695382 [Byte1]: 44
1580 22:10:28.699653
1581 22:10:28.700011 Set Vref, RX VrefLevel [Byte0]: 45
1582 22:10:28.703142 [Byte1]: 45
1583 22:10:28.707343
1584 22:10:28.707963 Set Vref, RX VrefLevel [Byte0]: 46
1585 22:10:28.710744 [Byte1]: 46
1586 22:10:28.714689
1587 22:10:28.715149 Set Vref, RX VrefLevel [Byte0]: 47
1588 22:10:28.717884 [Byte1]: 47
1589 22:10:28.722038
1590 22:10:28.722383 Set Vref, RX VrefLevel [Byte0]: 48
1591 22:10:28.726064 [Byte1]: 48
1592 22:10:28.730217
1593 22:10:28.730703 Set Vref, RX VrefLevel [Byte0]: 49
1594 22:10:28.733483 [Byte1]: 49
1595 22:10:28.737896
1596 22:10:28.738324 Set Vref, RX VrefLevel [Byte0]: 50
1597 22:10:28.741290 [Byte1]: 50
1598 22:10:28.745757
1599 22:10:28.746425 Set Vref, RX VrefLevel [Byte0]: 51
1600 22:10:28.749422 [Byte1]: 51
1601 22:10:28.753069
1602 22:10:28.753636 Set Vref, RX VrefLevel [Byte0]: 52
1603 22:10:28.756084 [Byte1]: 52
1604 22:10:28.760950
1605 22:10:28.761479 Set Vref, RX VrefLevel [Byte0]: 53
1606 22:10:28.764138 [Byte1]: 53
1607 22:10:28.768897
1608 22:10:28.769436 Set Vref, RX VrefLevel [Byte0]: 54
1609 22:10:28.771735 [Byte1]: 54
1610 22:10:28.776579
1611 22:10:28.777068 Set Vref, RX VrefLevel [Byte0]: 55
1612 22:10:28.779778 [Byte1]: 55
1613 22:10:28.783745
1614 22:10:28.784237 Set Vref, RX VrefLevel [Byte0]: 56
1615 22:10:28.786983 [Byte1]: 56
1616 22:10:28.791216
1617 22:10:28.791675 Set Vref, RX VrefLevel [Byte0]: 57
1618 22:10:28.794943 [Byte1]: 57
1619 22:10:28.798942
1620 22:10:28.799418 Set Vref, RX VrefLevel [Byte0]: 58
1621 22:10:28.802634 [Byte1]: 58
1622 22:10:28.806746
1623 22:10:28.807232 Set Vref, RX VrefLevel [Byte0]: 59
1624 22:10:28.810051 [Byte1]: 59
1625 22:10:28.814195
1626 22:10:28.814607 Set Vref, RX VrefLevel [Byte0]: 60
1627 22:10:28.817757 [Byte1]: 60
1628 22:10:28.822135
1629 22:10:28.822484 Set Vref, RX VrefLevel [Byte0]: 61
1630 22:10:28.825189 [Byte1]: 61
1631 22:10:28.829541
1632 22:10:28.830150 Set Vref, RX VrefLevel [Byte0]: 62
1633 22:10:28.832954 [Byte1]: 62
1634 22:10:28.837763
1635 22:10:28.838232 Set Vref, RX VrefLevel [Byte0]: 63
1636 22:10:28.840218 [Byte1]: 63
1637 22:10:28.844768
1638 22:10:28.845217 Set Vref, RX VrefLevel [Byte0]: 64
1639 22:10:28.847851 [Byte1]: 64
1640 22:10:28.852816
1641 22:10:28.853280 Set Vref, RX VrefLevel [Byte0]: 65
1642 22:10:28.855982 [Byte1]: 65
1643 22:10:28.860230
1644 22:10:28.860718 Set Vref, RX VrefLevel [Byte0]: 66
1645 22:10:28.863865 [Byte1]: 66
1646 22:10:28.868160
1647 22:10:28.868657 Set Vref, RX VrefLevel [Byte0]: 67
1648 22:10:28.871626 [Byte1]: 67
1649 22:10:28.875637
1650 22:10:28.876129 Set Vref, RX VrefLevel [Byte0]: 68
1651 22:10:28.879403 [Byte1]: 68
1652 22:10:28.883248
1653 22:10:28.883734 Set Vref, RX VrefLevel [Byte0]: 69
1654 22:10:28.886239 [Byte1]: 69
1655 22:10:28.890748
1656 22:10:28.891135 Set Vref, RX VrefLevel [Byte0]: 70
1657 22:10:28.894018 [Byte1]: 70
1658 22:10:28.898205
1659 22:10:28.898613 Set Vref, RX VrefLevel [Byte0]: 71
1660 22:10:28.901444 [Byte1]: 71
1661 22:10:28.906116
1662 22:10:28.906593 Set Vref, RX VrefLevel [Byte0]: 72
1663 22:10:28.909525 [Byte1]: 72
1664 22:10:28.913831
1665 22:10:28.914175 Set Vref, RX VrefLevel [Byte0]: 73
1666 22:10:28.917008 [Byte1]: 73
1667 22:10:28.921128
1668 22:10:28.921562 Set Vref, RX VrefLevel [Byte0]: 74
1669 22:10:28.924381 [Byte1]: 74
1670 22:10:28.929195
1671 22:10:28.929718 Set Vref, RX VrefLevel [Byte0]: 75
1672 22:10:28.932383 [Byte1]: 75
1673 22:10:28.937173
1674 22:10:28.937719 Set Vref, RX VrefLevel [Byte0]: 76
1675 22:10:28.940160 [Byte1]: 76
1676 22:10:28.944472
1677 22:10:28.945101 Set Vref, RX VrefLevel [Byte0]: 77
1678 22:10:28.947302 [Byte1]: 77
1679 22:10:28.952388
1680 22:10:28.952888 Final RX Vref Byte 0 = 58 to rank0
1681 22:10:28.955719 Final RX Vref Byte 1 = 52 to rank0
1682 22:10:28.959511 Final RX Vref Byte 0 = 58 to rank1
1683 22:10:28.962735 Final RX Vref Byte 1 = 52 to rank1==
1684 22:10:28.966489 Dram Type= 6, Freq= 0, CH_1, rank 0
1685 22:10:28.969833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1686 22:10:28.970320 ==
1687 22:10:28.973009 DQS Delay:
1688 22:10:28.973456 DQS0 = 0, DQS1 = 0
1689 22:10:28.976122 DQM Delay:
1690 22:10:28.976616 DQM0 = 81, DQM1 = 75
1691 22:10:28.976993 DQ Delay:
1692 22:10:28.979018 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1693 22:10:28.982561 DQ4 =80, DQ5 =96, DQ6 =88, DQ7 =76
1694 22:10:28.986093 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1695 22:10:28.989043 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1696 22:10:28.989437
1697 22:10:28.989780
1698 22:10:28.999700 [DQSOSCAuto] RK0, (LSB)MR18= 0x5656, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1699 22:10:29.002861 CH1 RK0: MR19=606, MR18=5656
1700 22:10:29.006463 CH1_RK0: MR19=0x606, MR18=0x5656, DQSOSC=388, MR23=63, INC=98, DEC=65
1701 22:10:29.006927
1702 22:10:29.008878 ----->DramcWriteLeveling(PI) begin...
1703 22:10:29.013009 ==
1704 22:10:29.016329 Dram Type= 6, Freq= 0, CH_1, rank 1
1705 22:10:29.019358 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1706 22:10:29.019845 ==
1707 22:10:29.022687 Write leveling (Byte 0): 25 => 25
1708 22:10:29.025642 Write leveling (Byte 1): 25 => 25
1709 22:10:29.029457 DramcWriteLeveling(PI) end<-----
1710 22:10:29.029946
1711 22:10:29.030319 ==
1712 22:10:29.032864 Dram Type= 6, Freq= 0, CH_1, rank 1
1713 22:10:29.036466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1714 22:10:29.036962 ==
1715 22:10:29.039567 [Gating] SW mode calibration
1716 22:10:29.045952 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1717 22:10:29.049651 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1718 22:10:29.055962 0 6 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
1719 22:10:29.059647 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1720 22:10:29.062537 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1721 22:10:29.069720 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1722 22:10:29.072884 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1723 22:10:29.075963 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1724 22:10:29.082248 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1725 22:10:29.085833 0 6 28 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1726 22:10:29.088953 0 7 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1727 22:10:29.095775 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1728 22:10:29.099352 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1729 22:10:29.102729 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1730 22:10:29.109024 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1731 22:10:29.112825 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1732 22:10:29.115661 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1733 22:10:29.122708 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1734 22:10:29.125926 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1735 22:10:29.129108 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 22:10:29.135872 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1737 22:10:29.139533 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1738 22:10:29.142522 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1739 22:10:29.149234 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1740 22:10:29.152222 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1741 22:10:29.155676 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1742 22:10:29.162455 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1743 22:10:29.166181 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1744 22:10:29.169239 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1745 22:10:29.172239 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1746 22:10:29.179424 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1747 22:10:29.182450 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1748 22:10:29.185990 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1749 22:10:29.192781 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1750 22:10:29.196415 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1751 22:10:29.199413 Total UI for P1: 0, mck2ui 16
1752 22:10:29.202317 best dqsien dly found for B0: ( 0, 9, 26)
1753 22:10:29.205824 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1754 22:10:29.209058 Total UI for P1: 0, mck2ui 16
1755 22:10:29.212098 best dqsien dly found for B1: ( 0, 10, 0)
1756 22:10:29.215659 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1757 22:10:29.218970 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1758 22:10:29.219241
1759 22:10:29.225969 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1760 22:10:29.229294 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1761 22:10:29.229800 [Gating] SW calibration Done
1762 22:10:29.232737 ==
1763 22:10:29.236405 Dram Type= 6, Freq= 0, CH_1, rank 1
1764 22:10:29.239747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1765 22:10:29.240247 ==
1766 22:10:29.240541 RX Vref Scan: 0
1767 22:10:29.240785
1768 22:10:29.242720 RX Vref 0 -> 0, step: 1
1769 22:10:29.243104
1770 22:10:29.245707 RX Delay -130 -> 252, step: 16
1771 22:10:29.248775 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1772 22:10:29.252314 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1773 22:10:29.255562 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1774 22:10:29.262403 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1775 22:10:29.265824 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1776 22:10:29.269146 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1777 22:10:29.272619 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1778 22:10:29.275826 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1779 22:10:29.282790 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1780 22:10:29.286039 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1781 22:10:29.289213 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1782 22:10:29.292562 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1783 22:10:29.295595 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1784 22:10:29.302795 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1785 22:10:29.306548 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1786 22:10:29.309481 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1787 22:10:29.309556 ==
1788 22:10:29.312321 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 22:10:29.315502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1790 22:10:29.315587 ==
1791 22:10:29.319150 DQS Delay:
1792 22:10:29.319223 DQS0 = 0, DQS1 = 0
1793 22:10:29.322715 DQM Delay:
1794 22:10:29.322790 DQM0 = 85, DQM1 = 73
1795 22:10:29.322842 DQ Delay:
1796 22:10:29.325696 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1797 22:10:29.329083 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1798 22:10:29.332850 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
1799 22:10:29.336276 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1800 22:10:29.336352
1801 22:10:29.336405
1802 22:10:29.336452 ==
1803 22:10:29.339362 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 22:10:29.345687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1805 22:10:29.345763 ==
1806 22:10:29.345817
1807 22:10:29.345863
1808 22:10:29.345908 TX Vref Scan disable
1809 22:10:29.349853 == TX Byte 0 ==
1810 22:10:29.353203 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1811 22:10:29.356352 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1812 22:10:29.360097 == TX Byte 1 ==
1813 22:10:29.363107 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1814 22:10:29.366320 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1815 22:10:29.369776 ==
1816 22:10:29.372852 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 22:10:29.376406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1818 22:10:29.376486 ==
1819 22:10:29.388423 TX Vref=22, minBit 0, minWin=27, winSum=448
1820 22:10:29.391693 TX Vref=24, minBit 0, minWin=28, winSum=452
1821 22:10:29.395230 TX Vref=26, minBit 0, minWin=28, winSum=456
1822 22:10:29.398533 TX Vref=28, minBit 0, minWin=28, winSum=458
1823 22:10:29.401731 TX Vref=30, minBit 9, minWin=27, winSum=456
1824 22:10:29.405033 TX Vref=32, minBit 9, minWin=27, winSum=455
1825 22:10:29.412267 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1826 22:10:29.412343
1827 22:10:29.415619 Final TX Range 1 Vref 28
1828 22:10:29.415697
1829 22:10:29.415751 ==
1830 22:10:29.418518 Dram Type= 6, Freq= 0, CH_1, rank 1
1831 22:10:29.422123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1832 22:10:29.422197 ==
1833 22:10:29.422266
1834 22:10:29.422344
1835 22:10:29.425193 TX Vref Scan disable
1836 22:10:29.428571 == TX Byte 0 ==
1837 22:10:29.431975 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1838 22:10:29.435248 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1839 22:10:29.438785 == TX Byte 1 ==
1840 22:10:29.442438 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1841 22:10:29.445376 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1842 22:10:29.445451
1843 22:10:29.448558 [DATLAT]
1844 22:10:29.448644 Freq=800, CH1 RK1
1845 22:10:29.448704
1846 22:10:29.452152 DATLAT Default: 0x9
1847 22:10:29.452225 0, 0xFFFF, sum = 0
1848 22:10:29.455559 1, 0xFFFF, sum = 0
1849 22:10:29.455636 2, 0xFFFF, sum = 0
1850 22:10:29.458878 3, 0xFFFF, sum = 0
1851 22:10:29.458968 4, 0xFFFF, sum = 0
1852 22:10:29.462269 5, 0xFFFF, sum = 0
1853 22:10:29.462346 6, 0xFFFF, sum = 0
1854 22:10:29.465471 7, 0xFFFF, sum = 0
1855 22:10:29.465548 8, 0x0, sum = 1
1856 22:10:29.468956 9, 0x0, sum = 2
1857 22:10:29.469032 10, 0x0, sum = 3
1858 22:10:29.472068 11, 0x0, sum = 4
1859 22:10:29.472142 best_step = 9
1860 22:10:29.472210
1861 22:10:29.472287 ==
1862 22:10:29.475723 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 22:10:29.479120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1864 22:10:29.479217 ==
1865 22:10:29.482137 RX Vref Scan: 0
1866 22:10:29.482210
1867 22:10:29.485602 RX Vref 0 -> 0, step: 1
1868 22:10:29.485676
1869 22:10:29.485744 RX Delay -111 -> 252, step: 8
1870 22:10:29.493506 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1871 22:10:29.496724 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
1872 22:10:29.499827 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1873 22:10:29.503077 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1874 22:10:29.506473 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1875 22:10:29.513038 iDelay=217, Bit 5, Center 100 (-15 ~ 216) 232
1876 22:10:29.516554 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1877 22:10:29.519817 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1878 22:10:29.523374 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1879 22:10:29.526920 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1880 22:10:29.533458 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1881 22:10:29.536392 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1882 22:10:29.540068 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1883 22:10:29.543370 iDelay=217, Bit 13, Center 88 (-23 ~ 200) 224
1884 22:10:29.549643 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1885 22:10:29.553242 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1886 22:10:29.553324 ==
1887 22:10:29.556986 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 22:10:29.560085 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1889 22:10:29.560169 ==
1890 22:10:29.560227 DQS Delay:
1891 22:10:29.563301 DQS0 = 0, DQS1 = 0
1892 22:10:29.563375 DQM Delay:
1893 22:10:29.566626 DQM0 = 85, DQM1 = 75
1894 22:10:29.566699 DQ Delay:
1895 22:10:29.569667 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =80
1896 22:10:29.573217 DQ4 =84, DQ5 =100, DQ6 =92, DQ7 =84
1897 22:10:29.576274 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1898 22:10:29.580238 DQ12 =84, DQ13 =88, DQ14 =84, DQ15 =80
1899 22:10:29.580313
1900 22:10:29.580367
1901 22:10:29.590133 [DQSOSCAuto] RK1, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1902 22:10:29.590216 CH1 RK1: MR19=606, MR18=3737
1903 22:10:29.596494 CH1_RK1: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63
1904 22:10:29.600000 [RxdqsGatingPostProcess] freq 800
1905 22:10:29.606398 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1906 22:10:29.609937 Pre-setting of DQS Precalculation
1907 22:10:29.612893 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1908 22:10:29.619798 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1909 22:10:29.626123 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1910 22:10:29.626199
1911 22:10:29.629855
1912 22:10:29.629930 [Calibration Summary] 1600 Mbps
1913 22:10:29.633002 CH 0, Rank 0
1914 22:10:29.633077 SW Impedance : PASS
1915 22:10:29.636563 DUTY Scan : NO K
1916 22:10:29.639791 ZQ Calibration : PASS
1917 22:10:29.639866 Jitter Meter : NO K
1918 22:10:29.642960 CBT Training : PASS
1919 22:10:29.646445 Write leveling : PASS
1920 22:10:29.646521 RX DQS gating : PASS
1921 22:10:29.649551 RX DQ/DQS(RDDQC) : PASS
1922 22:10:29.652646 TX DQ/DQS : PASS
1923 22:10:29.652722 RX DATLAT : PASS
1924 22:10:29.656439 RX DQ/DQS(Engine): PASS
1925 22:10:29.659687 TX OE : NO K
1926 22:10:29.659770 All Pass.
1927 22:10:29.659830
1928 22:10:29.659881 CH 0, Rank 1
1929 22:10:29.662968 SW Impedance : PASS
1930 22:10:29.666004 DUTY Scan : NO K
1931 22:10:29.666078 ZQ Calibration : PASS
1932 22:10:29.669839 Jitter Meter : NO K
1933 22:10:29.669913 CBT Training : PASS
1934 22:10:29.672765 Write leveling : PASS
1935 22:10:29.676463 RX DQS gating : PASS
1936 22:10:29.676536 RX DQ/DQS(RDDQC) : PASS
1937 22:10:29.679747 TX DQ/DQS : PASS
1938 22:10:29.682769 RX DATLAT : PASS
1939 22:10:29.682843 RX DQ/DQS(Engine): PASS
1940 22:10:29.686526 TX OE : NO K
1941 22:10:29.686600 All Pass.
1942 22:10:29.686670
1943 22:10:29.689345 CH 1, Rank 0
1944 22:10:29.689420 SW Impedance : PASS
1945 22:10:29.692946 DUTY Scan : NO K
1946 22:10:29.696170 ZQ Calibration : PASS
1947 22:10:29.696248 Jitter Meter : NO K
1948 22:10:29.699559 CBT Training : PASS
1949 22:10:29.703051 Write leveling : PASS
1950 22:10:29.703125 RX DQS gating : PASS
1951 22:10:29.706414 RX DQ/DQS(RDDQC) : PASS
1952 22:10:29.706488 TX DQ/DQS : PASS
1953 22:10:29.709603 RX DATLAT : PASS
1954 22:10:29.712844 RX DQ/DQS(Engine): PASS
1955 22:10:29.712920 TX OE : NO K
1956 22:10:29.716207 All Pass.
1957 22:10:29.716282
1958 22:10:29.716334 CH 1, Rank 1
1959 22:10:29.719778 SW Impedance : PASS
1960 22:10:29.719854 DUTY Scan : NO K
1961 22:10:29.723021 ZQ Calibration : PASS
1962 22:10:29.726198 Jitter Meter : NO K
1963 22:10:29.726275 CBT Training : PASS
1964 22:10:29.729738 Write leveling : PASS
1965 22:10:29.732762 RX DQS gating : PASS
1966 22:10:29.732837 RX DQ/DQS(RDDQC) : PASS
1967 22:10:29.736152 TX DQ/DQS : PASS
1968 22:10:29.739682 RX DATLAT : PASS
1969 22:10:29.739756 RX DQ/DQS(Engine): PASS
1970 22:10:29.743128 TX OE : NO K
1971 22:10:29.743204 All Pass.
1972 22:10:29.743257
1973 22:10:29.746421 DramC Write-DBI off
1974 22:10:29.749473 PER_BANK_REFRESH: Hybrid Mode
1975 22:10:29.749562 TX_TRACKING: ON
1976 22:10:29.753230 [GetDramInforAfterCalByMRR] Vendor 6.
1977 22:10:29.756455 [GetDramInforAfterCalByMRR] Revision 606.
1978 22:10:29.759530 [GetDramInforAfterCalByMRR] Revision 2 0.
1979 22:10:29.763446 MR0 0x3939
1980 22:10:29.763520 MR8 0x1111
1981 22:10:29.766306 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1982 22:10:29.766379
1983 22:10:29.766448 MR0 0x3939
1984 22:10:29.769438 MR8 0x1111
1985 22:10:29.772913 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1986 22:10:29.772988
1987 22:10:29.779301 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1988 22:10:29.786059 [FAST_K] Save calibration result to emmc
1989 22:10:29.789465 [FAST_K] Save calibration result to emmc
1990 22:10:29.789540 dram_init: config_dvfs: 1
1991 22:10:29.796226 dramc_set_vcore_voltage set vcore to 662500
1992 22:10:29.796308 Read voltage for 1200, 2
1993 22:10:29.796361 Vio18 = 0
1994 22:10:29.799493 Vcore = 662500
1995 22:10:29.799567 Vdram = 0
1996 22:10:29.799635 Vddq = 0
1997 22:10:29.802921 Vmddr = 0
1998 22:10:29.805803 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1999 22:10:29.812380 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2000 22:10:29.816046 MEM_TYPE=3, freq_sel=15
2001 22:10:29.816123 sv_algorithm_assistance_LP4_1600
2002 22:10:29.822514 ============ PULL DRAM RESETB DOWN ============
2003 22:10:29.825803 ========== PULL DRAM RESETB DOWN end =========
2004 22:10:29.829273 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2005 22:10:29.832612 ===================================
2006 22:10:29.835818 LPDDR4 DRAM CONFIGURATION
2007 22:10:29.839427 ===================================
2008 22:10:29.842573 EX_ROW_EN[0] = 0x0
2009 22:10:29.842647 EX_ROW_EN[1] = 0x0
2010 22:10:29.846165 LP4Y_EN = 0x0
2011 22:10:29.846240 WORK_FSP = 0x0
2012 22:10:29.849520 WL = 0x4
2013 22:10:29.849605 RL = 0x4
2014 22:10:29.852626 BL = 0x2
2015 22:10:29.852701 RPST = 0x0
2016 22:10:29.856020 RD_PRE = 0x0
2017 22:10:29.856095 WR_PRE = 0x1
2018 22:10:29.859153 WR_PST = 0x0
2019 22:10:29.859237 DBI_WR = 0x0
2020 22:10:29.862972 DBI_RD = 0x0
2021 22:10:29.863046 OTF = 0x1
2022 22:10:29.866042 ===================================
2023 22:10:29.869223 ===================================
2024 22:10:29.872703 ANA top config
2025 22:10:29.875897 ===================================
2026 22:10:29.879439 DLL_ASYNC_EN = 0
2027 22:10:29.879514 ALL_SLAVE_EN = 0
2028 22:10:29.882606 NEW_RANK_MODE = 1
2029 22:10:29.885883 DLL_IDLE_MODE = 1
2030 22:10:29.889385 LP45_APHY_COMB_EN = 1
2031 22:10:29.889461 TX_ODT_DIS = 1
2032 22:10:29.892828 NEW_8X_MODE = 1
2033 22:10:29.895843 ===================================
2034 22:10:29.898990 ===================================
2035 22:10:29.902824 data_rate = 2400
2036 22:10:29.905970 CKR = 1
2037 22:10:29.909061 DQ_P2S_RATIO = 8
2038 22:10:29.912557 ===================================
2039 22:10:29.915923 CA_P2S_RATIO = 8
2040 22:10:29.916015 DQ_CA_OPEN = 0
2041 22:10:29.919206 DQ_SEMI_OPEN = 0
2042 22:10:29.922504 CA_SEMI_OPEN = 0
2043 22:10:29.925985 CA_FULL_RATE = 0
2044 22:10:29.928898 DQ_CKDIV4_EN = 0
2045 22:10:29.932271 CA_CKDIV4_EN = 0
2046 22:10:29.932345 CA_PREDIV_EN = 0
2047 22:10:29.935930 PH8_DLY = 17
2048 22:10:29.939106 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2049 22:10:29.942359 DQ_AAMCK_DIV = 4
2050 22:10:29.946003 CA_AAMCK_DIV = 4
2051 22:10:29.946078 CA_ADMCK_DIV = 4
2052 22:10:29.949045 DQ_TRACK_CA_EN = 0
2053 22:10:29.952351 CA_PICK = 1200
2054 22:10:29.955731 CA_MCKIO = 1200
2055 22:10:29.959551 MCKIO_SEMI = 0
2056 22:10:29.962403 PLL_FREQ = 2366
2057 22:10:29.966063 DQ_UI_PI_RATIO = 32
2058 22:10:29.968917 CA_UI_PI_RATIO = 0
2059 22:10:29.972635 ===================================
2060 22:10:29.975698 ===================================
2061 22:10:29.975771 memory_type:LPDDR4
2062 22:10:29.979451 GP_NUM : 10
2063 22:10:29.982381 SRAM_EN : 1
2064 22:10:29.982455 MD32_EN : 0
2065 22:10:29.985699 ===================================
2066 22:10:29.989294 [ANA_INIT] >>>>>>>>>>>>>>
2067 22:10:29.992456 <<<<<< [CONFIGURE PHASE]: ANA_TX
2068 22:10:29.995704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2069 22:10:29.999175 ===================================
2070 22:10:29.999252 data_rate = 2400,PCW = 0X5b00
2071 22:10:30.002704 ===================================
2072 22:10:30.006119 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2073 22:10:30.012494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2074 22:10:30.019313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2075 22:10:30.022583 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2076 22:10:30.025878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2077 22:10:30.028984 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2078 22:10:30.032760 [ANA_INIT] flow start
2079 22:10:30.035874 [ANA_INIT] PLL >>>>>>>>
2080 22:10:30.035961 [ANA_INIT] PLL <<<<<<<<
2081 22:10:30.039374 [ANA_INIT] MIDPI >>>>>>>>
2082 22:10:30.042762 [ANA_INIT] MIDPI <<<<<<<<
2083 22:10:30.042837 [ANA_INIT] DLL >>>>>>>>
2084 22:10:30.045994 [ANA_INIT] DLL <<<<<<<<
2085 22:10:30.049019 [ANA_INIT] flow end
2086 22:10:30.052537 ============ LP4 DIFF to SE enter ============
2087 22:10:30.055633 ============ LP4 DIFF to SE exit ============
2088 22:10:30.059038 [ANA_INIT] <<<<<<<<<<<<<
2089 22:10:30.062564 [Flow] Enable top DCM control >>>>>
2090 22:10:30.065686 [Flow] Enable top DCM control <<<<<
2091 22:10:30.069278 Enable DLL master slave shuffle
2092 22:10:30.072445 ==============================================================
2093 22:10:30.076102 Gating Mode config
2094 22:10:30.079152 ==============================================================
2095 22:10:30.082518 Config description:
2096 22:10:30.092264 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2097 22:10:30.099271 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2098 22:10:30.102419 SELPH_MODE 0: By rank 1: By Phase
2099 22:10:30.109009 ==============================================================
2100 22:10:30.112318 GAT_TRACK_EN = 1
2101 22:10:30.115639 RX_GATING_MODE = 2
2102 22:10:30.119142 RX_GATING_TRACK_MODE = 2
2103 22:10:30.122469 SELPH_MODE = 1
2104 22:10:30.125953 PICG_EARLY_EN = 1
2105 22:10:30.126029 VALID_LAT_VALUE = 1
2106 22:10:30.132571 ==============================================================
2107 22:10:30.135758 Enter into Gating configuration >>>>
2108 22:10:30.139337 Exit from Gating configuration <<<<
2109 22:10:30.142909 Enter into DVFS_PRE_config >>>>>
2110 22:10:30.153262 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2111 22:10:30.156139 Exit from DVFS_PRE_config <<<<<
2112 22:10:30.159309 Enter into PICG configuration >>>>
2113 22:10:30.162486 Exit from PICG configuration <<<<
2114 22:10:30.165768 [RX_INPUT] configuration >>>>>
2115 22:10:30.168943 [RX_INPUT] configuration <<<<<
2116 22:10:30.172663 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2117 22:10:30.179469 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2118 22:10:30.186071 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2119 22:10:30.192338 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2120 22:10:30.199246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2121 22:10:30.202734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2122 22:10:30.209539 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2123 22:10:30.212702 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2124 22:10:30.215776 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2125 22:10:30.219375 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2126 22:10:30.222401 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2127 22:10:30.228979 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2128 22:10:30.232455 ===================================
2129 22:10:30.236060 LPDDR4 DRAM CONFIGURATION
2130 22:10:30.239251 ===================================
2131 22:10:30.239327 EX_ROW_EN[0] = 0x0
2132 22:10:30.242454 EX_ROW_EN[1] = 0x0
2133 22:10:30.242514 LP4Y_EN = 0x0
2134 22:10:30.245882 WORK_FSP = 0x0
2135 22:10:30.245946 WL = 0x4
2136 22:10:30.249133 RL = 0x4
2137 22:10:30.249194 BL = 0x2
2138 22:10:30.252725 RPST = 0x0
2139 22:10:30.252781 RD_PRE = 0x0
2140 22:10:30.256166 WR_PRE = 0x1
2141 22:10:30.256225 WR_PST = 0x0
2142 22:10:30.259187 DBI_WR = 0x0
2143 22:10:30.259245 DBI_RD = 0x0
2144 22:10:30.262489 OTF = 0x1
2145 22:10:30.266180 ===================================
2146 22:10:30.269807 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2147 22:10:30.272799 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2148 22:10:30.279370 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2149 22:10:30.282710 ===================================
2150 22:10:30.282767 LPDDR4 DRAM CONFIGURATION
2151 22:10:30.285813 ===================================
2152 22:10:30.289168 EX_ROW_EN[0] = 0x10
2153 22:10:30.292686 EX_ROW_EN[1] = 0x0
2154 22:10:30.292756 LP4Y_EN = 0x0
2155 22:10:30.295678 WORK_FSP = 0x0
2156 22:10:30.295733 WL = 0x4
2157 22:10:30.299365 RL = 0x4
2158 22:10:30.299419 BL = 0x2
2159 22:10:30.302595 RPST = 0x0
2160 22:10:30.302662 RD_PRE = 0x0
2161 22:10:30.305797 WR_PRE = 0x1
2162 22:10:30.305854 WR_PST = 0x0
2163 22:10:30.309419 DBI_WR = 0x0
2164 22:10:30.309486 DBI_RD = 0x0
2165 22:10:30.312743 OTF = 0x1
2166 22:10:30.316497 ===================================
2167 22:10:30.322575 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2168 22:10:30.322640 ==
2169 22:10:30.326201 Dram Type= 6, Freq= 0, CH_0, rank 0
2170 22:10:30.329463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2171 22:10:30.329520 ==
2172 22:10:30.332492 [Duty_Offset_Calibration]
2173 22:10:30.332548 B0:0 B1:2 CA:1
2174 22:10:30.332594
2175 22:10:30.336049 [DutyScan_Calibration_Flow] k_type=0
2176 22:10:30.345761
2177 22:10:30.345838 ==CLK 0==
2178 22:10:30.349733 Final CLK duty delay cell = 0
2179 22:10:30.352678 [0] MAX Duty = 5093%(X100), DQS PI = 12
2180 22:10:30.355763 [0] MIN Duty = 4938%(X100), DQS PI = 52
2181 22:10:30.355827 [0] AVG Duty = 5015%(X100)
2182 22:10:30.359433
2183 22:10:30.362498 CH0 CLK Duty spec in!! Max-Min= 155%
2184 22:10:30.365660 [DutyScan_Calibration_Flow] ====Done====
2185 22:10:30.365723
2186 22:10:30.368947 [DutyScan_Calibration_Flow] k_type=1
2187 22:10:30.385095
2188 22:10:30.385159 ==DQS 0 ==
2189 22:10:30.388308 Final DQS duty delay cell = 0
2190 22:10:30.392140 [0] MAX Duty = 5125%(X100), DQS PI = 32
2191 22:10:30.395135 [0] MIN Duty = 5031%(X100), DQS PI = 4
2192 22:10:30.395214 [0] AVG Duty = 5078%(X100)
2193 22:10:30.398815
2194 22:10:30.398886 ==DQS 1 ==
2195 22:10:30.401704 Final DQS duty delay cell = 0
2196 22:10:30.404957 [0] MAX Duty = 5031%(X100), DQS PI = 54
2197 22:10:30.408433 [0] MIN Duty = 4906%(X100), DQS PI = 18
2198 22:10:30.408498 [0] AVG Duty = 4968%(X100)
2199 22:10:30.411809
2200 22:10:30.415200 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2201 22:10:30.415255
2202 22:10:30.418641 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2203 22:10:30.421799 [DutyScan_Calibration_Flow] ====Done====
2204 22:10:30.421854
2205 22:10:30.424988 [DutyScan_Calibration_Flow] k_type=3
2206 22:10:30.442306
2207 22:10:30.442362 ==DQM 0 ==
2208 22:10:30.445863 Final DQM duty delay cell = 0
2209 22:10:30.448810 [0] MAX Duty = 5156%(X100), DQS PI = 22
2210 22:10:30.452166 [0] MIN Duty = 4969%(X100), DQS PI = 40
2211 22:10:30.452242 [0] AVG Duty = 5062%(X100)
2212 22:10:30.455992
2213 22:10:30.456078 ==DQM 1 ==
2214 22:10:30.458978 Final DQM duty delay cell = 4
2215 22:10:30.462192 [4] MAX Duty = 5156%(X100), DQS PI = 48
2216 22:10:30.466012 [4] MIN Duty = 5000%(X100), DQS PI = 16
2217 22:10:30.466096 [4] AVG Duty = 5078%(X100)
2218 22:10:30.468835
2219 22:10:30.472193 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2220 22:10:30.472269
2221 22:10:30.475576 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2222 22:10:30.478947 [DutyScan_Calibration_Flow] ====Done====
2223 22:10:30.479022
2224 22:10:30.482222 [DutyScan_Calibration_Flow] k_type=2
2225 22:10:30.497415
2226 22:10:30.497504 ==DQ 0 ==
2227 22:10:30.500472 Final DQ duty delay cell = -4
2228 22:10:30.503971 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2229 22:10:30.507111 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2230 22:10:30.510452 [-4] AVG Duty = 4937%(X100)
2231 22:10:30.510527
2232 22:10:30.510582 ==DQ 1 ==
2233 22:10:30.513852 Final DQ duty delay cell = -4
2234 22:10:30.517887 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2235 22:10:30.520476 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2236 22:10:30.524221 [-4] AVG Duty = 4969%(X100)
2237 22:10:30.524298
2238 22:10:30.527275 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2239 22:10:30.527351
2240 22:10:30.530897 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2241 22:10:30.534203 [DutyScan_Calibration_Flow] ====Done====
2242 22:10:30.534279 ==
2243 22:10:30.537354 Dram Type= 6, Freq= 0, CH_1, rank 0
2244 22:10:30.540614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2245 22:10:30.540690 ==
2246 22:10:30.544041 [Duty_Offset_Calibration]
2247 22:10:30.544116 B0:0 B1:5 CA:-5
2248 22:10:30.544169
2249 22:10:30.547255 [DutyScan_Calibration_Flow] k_type=0
2250 22:10:30.557923
2251 22:10:30.558004 ==CLK 0==
2252 22:10:30.561043 Final CLK duty delay cell = 0
2253 22:10:30.564406 [0] MAX Duty = 5094%(X100), DQS PI = 24
2254 22:10:30.567942 [0] MIN Duty = 4875%(X100), DQS PI = 46
2255 22:10:30.568017 [0] AVG Duty = 4984%(X100)
2256 22:10:30.570959
2257 22:10:30.574329 CH1 CLK Duty spec in!! Max-Min= 219%
2258 22:10:30.577779 [DutyScan_Calibration_Flow] ====Done====
2259 22:10:30.577853
2260 22:10:30.581056 [DutyScan_Calibration_Flow] k_type=1
2261 22:10:30.596573
2262 22:10:30.596670 ==DQS 0 ==
2263 22:10:30.600104 Final DQS duty delay cell = 0
2264 22:10:30.602975 [0] MAX Duty = 5125%(X100), DQS PI = 16
2265 22:10:30.606505 [0] MIN Duty = 4875%(X100), DQS PI = 40
2266 22:10:30.609555 [0] AVG Duty = 5000%(X100)
2267 22:10:30.609635
2268 22:10:30.609699 ==DQS 1 ==
2269 22:10:30.612755 Final DQS duty delay cell = -4
2270 22:10:30.616378 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2271 22:10:30.619446 [-4] MIN Duty = 4876%(X100), DQS PI = 60
2272 22:10:30.623082 [-4] AVG Duty = 4938%(X100)
2273 22:10:30.623173
2274 22:10:30.626229 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2275 22:10:30.626302
2276 22:10:30.629695 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2277 22:10:30.633289 [DutyScan_Calibration_Flow] ====Done====
2278 22:10:30.633383
2279 22:10:30.636402 [DutyScan_Calibration_Flow] k_type=3
2280 22:10:30.652216
2281 22:10:30.652291 ==DQM 0 ==
2282 22:10:30.655088 Final DQM duty delay cell = -4
2283 22:10:30.658361 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2284 22:10:30.661603 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2285 22:10:30.664821 [-4] AVG Duty = 4953%(X100)
2286 22:10:30.664896
2287 22:10:30.664949 ==DQM 1 ==
2288 22:10:30.668446 Final DQM duty delay cell = -4
2289 22:10:30.671572 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2290 22:10:30.675048 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2291 22:10:30.678130 [-4] AVG Duty = 4968%(X100)
2292 22:10:30.678204
2293 22:10:30.681787 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2294 22:10:30.681863
2295 22:10:30.684980 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2296 22:10:30.688332 [DutyScan_Calibration_Flow] ====Done====
2297 22:10:30.688406
2298 22:10:30.691256 [DutyScan_Calibration_Flow] k_type=2
2299 22:10:30.708666
2300 22:10:30.708752 ==DQ 0 ==
2301 22:10:30.712298 Final DQ duty delay cell = 0
2302 22:10:30.715494 [0] MAX Duty = 5062%(X100), DQS PI = 0
2303 22:10:30.718418 [0] MIN Duty = 4938%(X100), DQS PI = 44
2304 22:10:30.718492 [0] AVG Duty = 5000%(X100)
2305 22:10:30.722226
2306 22:10:30.722299 ==DQ 1 ==
2307 22:10:30.725454 Final DQ duty delay cell = 0
2308 22:10:30.728707 [0] MAX Duty = 5000%(X100), DQS PI = 6
2309 22:10:30.732373 [0] MIN Duty = 4875%(X100), DQS PI = 46
2310 22:10:30.732456 [0] AVG Duty = 4937%(X100)
2311 22:10:30.732508
2312 22:10:30.735688 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2313 22:10:30.735765
2314 22:10:30.738649 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2315 22:10:30.745192 [DutyScan_Calibration_Flow] ====Done====
2316 22:10:30.748605 nWR fixed to 30
2317 22:10:30.748680 [ModeRegInit_LP4] CH0 RK0
2318 22:10:30.752023 [ModeRegInit_LP4] CH0 RK1
2319 22:10:30.755654 [ModeRegInit_LP4] CH1 RK0
2320 22:10:30.755727 [ModeRegInit_LP4] CH1 RK1
2321 22:10:30.758674 match AC timing 6
2322 22:10:30.762132 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2323 22:10:30.765192 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2324 22:10:30.772095 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2325 22:10:30.775129 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2326 22:10:30.781903 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2327 22:10:30.781977 ==
2328 22:10:30.785578 Dram Type= 6, Freq= 0, CH_0, rank 0
2329 22:10:30.788593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2330 22:10:30.788667 ==
2331 22:10:30.795666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2332 22:10:30.798698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2333 22:10:30.808367 [CA 0] Center 39 (9~70) winsize 62
2334 22:10:30.811744 [CA 1] Center 39 (8~70) winsize 63
2335 22:10:30.815306 [CA 2] Center 36 (5~67) winsize 63
2336 22:10:30.818506 [CA 3] Center 35 (4~66) winsize 63
2337 22:10:30.821612 [CA 4] Center 34 (3~65) winsize 63
2338 22:10:30.825155 [CA 5] Center 33 (3~64) winsize 62
2339 22:10:30.825228
2340 22:10:30.828240 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2341 22:10:30.828314
2342 22:10:30.831565 [CATrainingPosCal] consider 1 rank data
2343 22:10:30.835365 u2DelayCellTimex100 = 270/100 ps
2344 22:10:30.838522 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2345 22:10:30.841928 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2346 22:10:30.848398 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2347 22:10:30.852071 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2348 22:10:30.855007 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2349 22:10:30.858707 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2350 22:10:30.858780
2351 22:10:30.861919 CA PerBit enable=1, Macro0, CA PI delay=33
2352 22:10:30.861994
2353 22:10:30.864906 [CBTSetCACLKResult] CA Dly = 33
2354 22:10:30.864978 CS Dly: 7 (0~38)
2355 22:10:30.868409 ==
2356 22:10:30.868486 Dram Type= 6, Freq= 0, CH_0, rank 1
2357 22:10:30.875109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2358 22:10:30.875182 ==
2359 22:10:30.878268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2360 22:10:30.885154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2361 22:10:30.894133 [CA 0] Center 39 (9~70) winsize 62
2362 22:10:30.897173 [CA 1] Center 39 (8~70) winsize 63
2363 22:10:30.900579 [CA 2] Center 35 (5~66) winsize 62
2364 22:10:30.903992 [CA 3] Center 35 (4~66) winsize 63
2365 22:10:30.907096 [CA 4] Center 33 (3~64) winsize 62
2366 22:10:30.910663 [CA 5] Center 34 (3~65) winsize 63
2367 22:10:30.910736
2368 22:10:30.913781 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2369 22:10:30.913866
2370 22:10:30.917041 [CATrainingPosCal] consider 2 rank data
2371 22:10:30.920438 u2DelayCellTimex100 = 270/100 ps
2372 22:10:30.923769 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2373 22:10:30.930524 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2374 22:10:30.933644 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2375 22:10:30.936967 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2376 22:10:30.940487 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2377 22:10:30.943760 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2378 22:10:30.943833
2379 22:10:30.946894 CA PerBit enable=1, Macro0, CA PI delay=33
2380 22:10:30.946969
2381 22:10:30.950630 [CBTSetCACLKResult] CA Dly = 33
2382 22:10:30.950706 CS Dly: 7 (0~39)
2383 22:10:30.950760
2384 22:10:30.953664 ----->DramcWriteLeveling(PI) begin...
2385 22:10:30.957541 ==
2386 22:10:30.960319 Dram Type= 6, Freq= 0, CH_0, rank 0
2387 22:10:30.963916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2388 22:10:30.963991 ==
2389 22:10:30.967024 Write leveling (Byte 0): 29 => 29
2390 22:10:30.970611 Write leveling (Byte 1): 27 => 27
2391 22:10:30.973742 DramcWriteLeveling(PI) end<-----
2392 22:10:30.973824
2393 22:10:30.973888 ==
2394 22:10:30.977481 Dram Type= 6, Freq= 0, CH_0, rank 0
2395 22:10:30.980463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2396 22:10:30.980535 ==
2397 22:10:30.983971 [Gating] SW mode calibration
2398 22:10:30.990329 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2399 22:10:30.993916 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2400 22:10:31.000497 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2401 22:10:31.003932 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2402 22:10:31.007267 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2403 22:10:31.013898 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2404 22:10:31.016954 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2405 22:10:31.020774 0 11 20 | B1->B0 | 2d2d 2b2b | 0 0 | (1 0) (0 1)
2406 22:10:31.026998 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2407 22:10:31.030622 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2408 22:10:31.034491 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2409 22:10:31.040222 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2410 22:10:31.043748 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2411 22:10:31.046975 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2412 22:10:31.053724 0 12 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2413 22:10:31.057467 0 12 20 | B1->B0 | 3a3a 4040 | 0 0 | (0 0) (0 0)
2414 22:10:31.060519 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2415 22:10:31.067486 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2416 22:10:31.070652 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2417 22:10:31.073929 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2418 22:10:31.077432 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2419 22:10:31.084143 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2420 22:10:31.087221 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2421 22:10:31.090949 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2422 22:10:31.097108 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 22:10:31.100794 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2424 22:10:31.103958 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2425 22:10:31.110875 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2426 22:10:31.114261 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2427 22:10:31.117375 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2428 22:10:31.123977 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2429 22:10:31.127318 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2430 22:10:31.130603 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2431 22:10:31.137570 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2432 22:10:31.140514 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2433 22:10:31.143918 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2434 22:10:31.151003 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2435 22:10:31.153961 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2436 22:10:31.157121 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2437 22:10:31.163816 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2438 22:10:31.167210 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2439 22:10:31.170807 Total UI for P1: 0, mck2ui 16
2440 22:10:31.174047 best dqsien dly found for B0: ( 0, 15, 20)
2441 22:10:31.177229 Total UI for P1: 0, mck2ui 16
2442 22:10:31.180815 best dqsien dly found for B1: ( 0, 15, 20)
2443 22:10:31.183938 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2444 22:10:31.187245 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2445 22:10:31.187319
2446 22:10:31.190495 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2447 22:10:31.194139 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2448 22:10:31.197699 [Gating] SW calibration Done
2449 22:10:31.197774 ==
2450 22:10:31.200642 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 22:10:31.203974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2452 22:10:31.204049 ==
2453 22:10:31.207783 RX Vref Scan: 0
2454 22:10:31.207858
2455 22:10:31.211062 RX Vref 0 -> 0, step: 1
2456 22:10:31.211137
2457 22:10:31.211189 RX Delay -40 -> 252, step: 8
2458 22:10:31.217199 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2459 22:10:31.220514 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2460 22:10:31.224065 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2461 22:10:31.227391 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2462 22:10:31.231030 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2463 22:10:31.237197 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2464 22:10:31.240669 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2465 22:10:31.244197 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2466 22:10:31.247398 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2467 22:10:31.250750 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2468 22:10:31.254109 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2469 22:10:31.260925 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2470 22:10:31.263949 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2471 22:10:31.267113 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2472 22:10:31.270991 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2473 22:10:31.277346 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2474 22:10:31.277434 ==
2475 22:10:31.280938 Dram Type= 6, Freq= 0, CH_0, rank 0
2476 22:10:31.283919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2477 22:10:31.283995 ==
2478 22:10:31.284077 DQS Delay:
2479 22:10:31.287395 DQS0 = 0, DQS1 = 0
2480 22:10:31.287468 DQM Delay:
2481 22:10:31.290468 DQM0 = 115, DQM1 = 106
2482 22:10:31.290543 DQ Delay:
2483 22:10:31.293964 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2484 22:10:31.297269 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2485 22:10:31.300849 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2486 22:10:31.304080 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2487 22:10:31.304157
2488 22:10:31.304212
2489 22:10:31.304265 ==
2490 22:10:31.307192 Dram Type= 6, Freq= 0, CH_0, rank 0
2491 22:10:31.314126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2492 22:10:31.314200 ==
2493 22:10:31.314268
2494 22:10:31.314344
2495 22:10:31.314418 TX Vref Scan disable
2496 22:10:31.317490 == TX Byte 0 ==
2497 22:10:31.321047 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2498 22:10:31.327376 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2499 22:10:31.327449 == TX Byte 1 ==
2500 22:10:31.331015 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2501 22:10:31.337325 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2502 22:10:31.337399 ==
2503 22:10:31.340883 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 22:10:31.344141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2505 22:10:31.344216 ==
2506 22:10:31.355503 TX Vref=22, minBit 10, minWin=25, winSum=417
2507 22:10:31.358991 TX Vref=24, minBit 1, minWin=25, winSum=422
2508 22:10:31.362240 TX Vref=26, minBit 8, minWin=25, winSum=431
2509 22:10:31.365414 TX Vref=28, minBit 8, minWin=26, winSum=435
2510 22:10:31.368916 TX Vref=30, minBit 10, minWin=26, winSum=441
2511 22:10:31.375578 TX Vref=32, minBit 10, minWin=26, winSum=433
2512 22:10:31.378628 [TxChooseVref] Worse bit 10, Min win 26, Win sum 441, Final Vref 30
2513 22:10:31.378702
2514 22:10:31.382250 Final TX Range 1 Vref 30
2515 22:10:31.382325
2516 22:10:31.382385 ==
2517 22:10:31.385538 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 22:10:31.388774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2519 22:10:31.392271 ==
2520 22:10:31.392345
2521 22:10:31.392398
2522 22:10:31.392444 TX Vref Scan disable
2523 22:10:31.395597 == TX Byte 0 ==
2524 22:10:31.398790 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2525 22:10:31.405170 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2526 22:10:31.405244 == TX Byte 1 ==
2527 22:10:31.408971 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2528 22:10:31.415614 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2529 22:10:31.415693
2530 22:10:31.415750 [DATLAT]
2531 22:10:31.415796 Freq=1200, CH0 RK0
2532 22:10:31.415841
2533 22:10:31.418543 DATLAT Default: 0xd
2534 22:10:31.418618 0, 0xFFFF, sum = 0
2535 22:10:31.421823 1, 0xFFFF, sum = 0
2536 22:10:31.424962 2, 0xFFFF, sum = 0
2537 22:10:31.425039 3, 0xFFFF, sum = 0
2538 22:10:31.428436 4, 0xFFFF, sum = 0
2539 22:10:31.428511 5, 0xFFFF, sum = 0
2540 22:10:31.432260 6, 0xFFFF, sum = 0
2541 22:10:31.432340 7, 0xFFFF, sum = 0
2542 22:10:31.435122 8, 0xFFFF, sum = 0
2543 22:10:31.435197 9, 0xFFFF, sum = 0
2544 22:10:31.438724 10, 0xFFFF, sum = 0
2545 22:10:31.438795 11, 0x0, sum = 1
2546 22:10:31.441811 12, 0x0, sum = 2
2547 22:10:31.441866 13, 0x0, sum = 3
2548 22:10:31.445248 14, 0x0, sum = 4
2549 22:10:31.445309 best_step = 12
2550 22:10:31.445358
2551 22:10:31.445416 ==
2552 22:10:31.448424 Dram Type= 6, Freq= 0, CH_0, rank 0
2553 22:10:31.452026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2554 22:10:31.452109 ==
2555 22:10:31.455235 RX Vref Scan: 1
2556 22:10:31.455290
2557 22:10:31.458892 Set Vref Range= 32 -> 127
2558 22:10:31.458947
2559 22:10:31.458992 RX Vref 32 -> 127, step: 1
2560 22:10:31.459036
2561 22:10:31.461816 RX Delay -21 -> 252, step: 4
2562 22:10:31.461878
2563 22:10:31.465368 Set Vref, RX VrefLevel [Byte0]: 32
2564 22:10:31.468596 [Byte1]: 32
2565 22:10:31.472265
2566 22:10:31.472318 Set Vref, RX VrefLevel [Byte0]: 33
2567 22:10:31.475409 [Byte1]: 33
2568 22:10:31.480319
2569 22:10:31.480376 Set Vref, RX VrefLevel [Byte0]: 34
2570 22:10:31.483599 [Byte1]: 34
2571 22:10:31.487940
2572 22:10:31.487994 Set Vref, RX VrefLevel [Byte0]: 35
2573 22:10:31.491070 [Byte1]: 35
2574 22:10:31.495827
2575 22:10:31.495898 Set Vref, RX VrefLevel [Byte0]: 36
2576 22:10:31.499155 [Byte1]: 36
2577 22:10:31.504180
2578 22:10:31.504237 Set Vref, RX VrefLevel [Byte0]: 37
2579 22:10:31.507089 [Byte1]: 37
2580 22:10:31.511824
2581 22:10:31.511881 Set Vref, RX VrefLevel [Byte0]: 38
2582 22:10:31.515129 [Byte1]: 38
2583 22:10:31.519842
2584 22:10:31.519928 Set Vref, RX VrefLevel [Byte0]: 39
2585 22:10:31.522968 [Byte1]: 39
2586 22:10:31.527859
2587 22:10:31.527918 Set Vref, RX VrefLevel [Byte0]: 40
2588 22:10:31.531060 [Byte1]: 40
2589 22:10:31.535492
2590 22:10:31.535545 Set Vref, RX VrefLevel [Byte0]: 41
2591 22:10:31.538618 [Byte1]: 41
2592 22:10:31.543388
2593 22:10:31.543439 Set Vref, RX VrefLevel [Byte0]: 42
2594 22:10:31.546770 [Byte1]: 42
2595 22:10:31.551748
2596 22:10:31.551816 Set Vref, RX VrefLevel [Byte0]: 43
2597 22:10:31.554624 [Byte1]: 43
2598 22:10:31.559373
2599 22:10:31.559428 Set Vref, RX VrefLevel [Byte0]: 44
2600 22:10:31.562378 [Byte1]: 44
2601 22:10:31.567215
2602 22:10:31.567291 Set Vref, RX VrefLevel [Byte0]: 45
2603 22:10:31.570420 [Byte1]: 45
2604 22:10:31.574982
2605 22:10:31.575034 Set Vref, RX VrefLevel [Byte0]: 46
2606 22:10:31.578129 [Byte1]: 46
2607 22:10:31.582874
2608 22:10:31.582936 Set Vref, RX VrefLevel [Byte0]: 47
2609 22:10:31.586157 [Byte1]: 47
2610 22:10:31.590789
2611 22:10:31.590851 Set Vref, RX VrefLevel [Byte0]: 48
2612 22:10:31.593984 [Byte1]: 48
2613 22:10:31.599039
2614 22:10:31.599109 Set Vref, RX VrefLevel [Byte0]: 49
2615 22:10:31.602123 [Byte1]: 49
2616 22:10:31.606557
2617 22:10:31.606611 Set Vref, RX VrefLevel [Byte0]: 50
2618 22:10:31.610037 [Byte1]: 50
2619 22:10:31.614545
2620 22:10:31.614600 Set Vref, RX VrefLevel [Byte0]: 51
2621 22:10:31.617925 [Byte1]: 51
2622 22:10:31.622432
2623 22:10:31.622490 Set Vref, RX VrefLevel [Byte0]: 52
2624 22:10:31.625891 [Byte1]: 52
2625 22:10:31.630706
2626 22:10:31.630767 Set Vref, RX VrefLevel [Byte0]: 53
2627 22:10:31.633711 [Byte1]: 53
2628 22:10:31.638576
2629 22:10:31.638642 Set Vref, RX VrefLevel [Byte0]: 54
2630 22:10:31.641798 [Byte1]: 54
2631 22:10:31.646395
2632 22:10:31.646486 Set Vref, RX VrefLevel [Byte0]: 55
2633 22:10:31.649491 [Byte1]: 55
2634 22:10:31.654099
2635 22:10:31.654153 Set Vref, RX VrefLevel [Byte0]: 56
2636 22:10:31.657794 [Byte1]: 56
2637 22:10:31.662137
2638 22:10:31.662199 Set Vref, RX VrefLevel [Byte0]: 57
2639 22:10:31.665442 [Byte1]: 57
2640 22:10:31.669937
2641 22:10:31.669997 Set Vref, RX VrefLevel [Byte0]: 58
2642 22:10:31.673593 [Byte1]: 58
2643 22:10:31.678274
2644 22:10:31.678330 Set Vref, RX VrefLevel [Byte0]: 59
2645 22:10:31.681433 [Byte1]: 59
2646 22:10:31.686037
2647 22:10:31.689378 Set Vref, RX VrefLevel [Byte0]: 60
2648 22:10:31.692377 [Byte1]: 60
2649 22:10:31.692453
2650 22:10:31.695854 Set Vref, RX VrefLevel [Byte0]: 61
2651 22:10:31.698940 [Byte1]: 61
2652 22:10:31.699020
2653 22:10:31.702301 Set Vref, RX VrefLevel [Byte0]: 62
2654 22:10:31.706059 [Byte1]: 62
2655 22:10:31.710056
2656 22:10:31.710129 Set Vref, RX VrefLevel [Byte0]: 63
2657 22:10:31.713339 [Byte1]: 63
2658 22:10:31.717985
2659 22:10:31.718060 Set Vref, RX VrefLevel [Byte0]: 64
2660 22:10:31.720790 [Byte1]: 64
2661 22:10:31.726109
2662 22:10:31.726184 Set Vref, RX VrefLevel [Byte0]: 65
2663 22:10:31.729662 [Byte1]: 65
2664 22:10:31.733844
2665 22:10:31.733920 Set Vref, RX VrefLevel [Byte0]: 66
2666 22:10:31.736756 [Byte1]: 66
2667 22:10:31.741570
2668 22:10:31.741645 Final RX Vref Byte 0 = 52 to rank0
2669 22:10:31.744572 Final RX Vref Byte 1 = 48 to rank0
2670 22:10:31.748243 Final RX Vref Byte 0 = 52 to rank1
2671 22:10:31.751427 Final RX Vref Byte 1 = 48 to rank1==
2672 22:10:31.755094 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 22:10:31.761731 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2674 22:10:31.761815 ==
2675 22:10:31.761891 DQS Delay:
2676 22:10:31.761958 DQS0 = 0, DQS1 = 0
2677 22:10:31.765284 DQM Delay:
2678 22:10:31.765364 DQM0 = 114, DQM1 = 104
2679 22:10:31.768343 DQ Delay:
2680 22:10:31.771713 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =110
2681 22:10:31.774800 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2682 22:10:31.778331 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2683 22:10:31.781797 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2684 22:10:31.781873
2685 22:10:31.781942
2686 22:10:31.788448 [DQSOSCAuto] RK0, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2687 22:10:31.791391 CH0 RK0: MR19=404, MR18=C0C
2688 22:10:31.798102 CH0_RK0: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
2689 22:10:31.798182
2690 22:10:31.801258 ----->DramcWriteLeveling(PI) begin...
2691 22:10:31.801340 ==
2692 22:10:31.805094 Dram Type= 6, Freq= 0, CH_0, rank 1
2693 22:10:31.808133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2694 22:10:31.808215 ==
2695 22:10:31.811912 Write leveling (Byte 0): 28 => 28
2696 22:10:31.814793 Write leveling (Byte 1): 26 => 26
2697 22:10:31.818554 DramcWriteLeveling(PI) end<-----
2698 22:10:31.818630
2699 22:10:31.818700 ==
2700 22:10:31.821661 Dram Type= 6, Freq= 0, CH_0, rank 1
2701 22:10:31.825107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2702 22:10:31.828509 ==
2703 22:10:31.828585 [Gating] SW mode calibration
2704 22:10:31.834924 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2705 22:10:31.841763 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2706 22:10:31.844832 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2707 22:10:31.851746 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2708 22:10:31.854945 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2709 22:10:31.858160 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2710 22:10:31.865029 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 1)
2711 22:10:31.868611 0 11 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2712 22:10:31.871685 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2713 22:10:31.878452 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2714 22:10:31.881479 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2715 22:10:31.884685 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2716 22:10:31.891666 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2717 22:10:31.894942 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2718 22:10:31.898440 0 12 16 | B1->B0 | 2424 3333 | 0 1 | (0 0) (0 0)
2719 22:10:31.901368 0 12 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2720 22:10:31.908476 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2721 22:10:31.911821 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2722 22:10:31.914878 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2723 22:10:31.921531 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2724 22:10:31.925256 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2725 22:10:31.928239 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2726 22:10:31.935044 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2727 22:10:31.938270 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2728 22:10:31.941375 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 22:10:31.948204 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 22:10:31.951605 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2731 22:10:31.954946 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2732 22:10:31.961627 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2733 22:10:31.965095 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2734 22:10:31.968114 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2735 22:10:31.975235 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2736 22:10:31.978474 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2737 22:10:31.981317 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2738 22:10:31.984998 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2739 22:10:31.991678 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2740 22:10:31.994957 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2741 22:10:31.998578 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2742 22:10:32.005111 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2743 22:10:32.008448 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2744 22:10:32.011424 Total UI for P1: 0, mck2ui 16
2745 22:10:32.015009 best dqsien dly found for B0: ( 0, 15, 16)
2746 22:10:32.018648 Total UI for P1: 0, mck2ui 16
2747 22:10:32.021866 best dqsien dly found for B1: ( 0, 15, 16)
2748 22:10:32.024596 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2749 22:10:32.027997 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
2750 22:10:32.028073
2751 22:10:32.031382 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2752 22:10:32.034784 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
2753 22:10:32.037899 [Gating] SW calibration Done
2754 22:10:32.037987 ==
2755 22:10:32.041564 Dram Type= 6, Freq= 0, CH_0, rank 1
2756 22:10:32.048432 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2757 22:10:32.048508 ==
2758 22:10:32.048577 RX Vref Scan: 0
2759 22:10:32.048636
2760 22:10:32.051431 RX Vref 0 -> 0, step: 1
2761 22:10:32.051512
2762 22:10:32.054957 RX Delay -40 -> 252, step: 8
2763 22:10:32.058168 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2764 22:10:32.061359 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2765 22:10:32.064768 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2766 22:10:32.068372 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2767 22:10:32.075267 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2768 22:10:32.078330 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2769 22:10:32.081318 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2770 22:10:32.084884 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2771 22:10:32.087946 iDelay=200, Bit 8, Center 95 (32 ~ 159) 128
2772 22:10:32.095046 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2773 22:10:32.098041 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2774 22:10:32.101749 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2775 22:10:32.104738 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2776 22:10:32.108406 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2777 22:10:32.115115 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2778 22:10:32.117902 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2779 22:10:32.117977 ==
2780 22:10:32.121472 Dram Type= 6, Freq= 0, CH_0, rank 1
2781 22:10:32.124920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2782 22:10:32.124996 ==
2783 22:10:32.125065 DQS Delay:
2784 22:10:32.128214 DQS0 = 0, DQS1 = 0
2785 22:10:32.128289 DQM Delay:
2786 22:10:32.131630 DQM0 = 115, DQM1 = 106
2787 22:10:32.131709 DQ Delay:
2788 22:10:32.134735 DQ0 =107, DQ1 =119, DQ2 =115, DQ3 =111
2789 22:10:32.138292 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2790 22:10:32.141321 DQ8 =95, DQ9 =91, DQ10 =107, DQ11 =99
2791 22:10:32.144868 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2792 22:10:32.148081
2793 22:10:32.148140
2794 22:10:32.148188 ==
2795 22:10:32.151348 Dram Type= 6, Freq= 0, CH_0, rank 1
2796 22:10:32.154619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2797 22:10:32.154684 ==
2798 22:10:32.154734
2799 22:10:32.154778
2800 22:10:32.158154 TX Vref Scan disable
2801 22:10:32.158225 == TX Byte 0 ==
2802 22:10:32.164892 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2803 22:10:32.167967 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2804 22:10:32.168027 == TX Byte 1 ==
2805 22:10:32.174735 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2806 22:10:32.177838 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2807 22:10:32.177890 ==
2808 22:10:32.181652 Dram Type= 6, Freq= 0, CH_0, rank 1
2809 22:10:32.184764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2810 22:10:32.184817 ==
2811 22:10:32.196786 TX Vref=22, minBit 8, minWin=25, winSum=418
2812 22:10:32.200159 TX Vref=24, minBit 8, minWin=25, winSum=427
2813 22:10:32.203579 TX Vref=26, minBit 10, minWin=25, winSum=430
2814 22:10:32.207111 TX Vref=28, minBit 8, minWin=26, winSum=431
2815 22:10:32.210208 TX Vref=30, minBit 8, minWin=26, winSum=435
2816 22:10:32.214487 TX Vref=32, minBit 8, minWin=25, winSum=436
2817 22:10:32.220248 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
2818 22:10:32.220306
2819 22:10:32.223711 Final TX Range 1 Vref 30
2820 22:10:32.223768
2821 22:10:32.223813 ==
2822 22:10:32.227282 Dram Type= 6, Freq= 0, CH_0, rank 1
2823 22:10:32.230599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2824 22:10:32.230659 ==
2825 22:10:32.230715
2826 22:10:32.233798
2827 22:10:32.233866 TX Vref Scan disable
2828 22:10:32.237184 == TX Byte 0 ==
2829 22:10:32.240476 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2830 22:10:32.243978 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2831 22:10:32.246985 == TX Byte 1 ==
2832 22:10:32.250290 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2833 22:10:32.254029 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2834 22:10:32.254087
2835 22:10:32.257401 [DATLAT]
2836 22:10:32.257456 Freq=1200, CH0 RK1
2837 22:10:32.257502
2838 22:10:32.260174 DATLAT Default: 0xc
2839 22:10:32.260230 0, 0xFFFF, sum = 0
2840 22:10:32.263818 1, 0xFFFF, sum = 0
2841 22:10:32.263877 2, 0xFFFF, sum = 0
2842 22:10:32.267128 3, 0xFFFF, sum = 0
2843 22:10:32.267207 4, 0xFFFF, sum = 0
2844 22:10:32.270412 5, 0xFFFF, sum = 0
2845 22:10:32.270472 6, 0xFFFF, sum = 0
2846 22:10:32.274397 7, 0xFFFF, sum = 0
2847 22:10:32.274454 8, 0xFFFF, sum = 0
2848 22:10:32.277191 9, 0xFFFF, sum = 0
2849 22:10:32.280654 10, 0xFFFF, sum = 0
2850 22:10:32.280714 11, 0x0, sum = 1
2851 22:10:32.280761 12, 0x0, sum = 2
2852 22:10:32.283807 13, 0x0, sum = 3
2853 22:10:32.283864 14, 0x0, sum = 4
2854 22:10:32.287453 best_step = 12
2855 22:10:32.287527
2856 22:10:32.287592 ==
2857 22:10:32.290547 Dram Type= 6, Freq= 0, CH_0, rank 1
2858 22:10:32.293621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2859 22:10:32.293688 ==
2860 22:10:32.297416 RX Vref Scan: 0
2861 22:10:32.297476
2862 22:10:32.297524 RX Vref 0 -> 0, step: 1
2863 22:10:32.297569
2864 22:10:32.300630 RX Delay -21 -> 252, step: 4
2865 22:10:32.307262 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2866 22:10:32.310433 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2867 22:10:32.314028 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2868 22:10:32.317170 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2869 22:10:32.320644 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2870 22:10:32.327454 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2871 22:10:32.330513 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2872 22:10:32.334003 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2873 22:10:32.337195 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2874 22:10:32.340647 iDelay=199, Bit 9, Center 88 (27 ~ 150) 124
2875 22:10:32.347041 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
2876 22:10:32.350613 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2877 22:10:32.353995 iDelay=199, Bit 12, Center 110 (47 ~ 174) 128
2878 22:10:32.356959 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2879 22:10:32.360432 iDelay=199, Bit 14, Center 116 (55 ~ 178) 124
2880 22:10:32.367395 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2881 22:10:32.367471 ==
2882 22:10:32.370825 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 22:10:32.374379 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2884 22:10:32.374452 ==
2885 22:10:32.374521 DQS Delay:
2886 22:10:32.377044 DQS0 = 0, DQS1 = 0
2887 22:10:32.377118 DQM Delay:
2888 22:10:32.380789 DQM0 = 115, DQM1 = 104
2889 22:10:32.380863 DQ Delay:
2890 22:10:32.383779 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2891 22:10:32.387320 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2892 22:10:32.390641 DQ8 =92, DQ9 =88, DQ10 =108, DQ11 =96
2893 22:10:32.393876 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
2894 22:10:32.393977
2895 22:10:32.394049
2896 22:10:32.403893 [DQSOSCAuto] RK1, (LSB)MR18= 0x1010, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2897 22:10:32.407458 CH0 RK1: MR19=404, MR18=1010
2898 22:10:32.410360 CH0_RK1: MR19=0x404, MR18=0x1010, DQSOSC=403, MR23=63, INC=40, DEC=26
2899 22:10:32.414021 [RxdqsGatingPostProcess] freq 1200
2900 22:10:32.420240 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2901 22:10:32.423967 Pre-setting of DQS Precalculation
2902 22:10:32.427467 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2903 22:10:32.430458 ==
2904 22:10:32.430545 Dram Type= 6, Freq= 0, CH_1, rank 0
2905 22:10:32.436977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2906 22:10:32.437053 ==
2907 22:10:32.440712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2908 22:10:32.446927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2909 22:10:32.455847 [CA 0] Center 37 (7~68) winsize 62
2910 22:10:32.459009 [CA 1] Center 37 (6~68) winsize 63
2911 22:10:32.462336 [CA 2] Center 34 (4~65) winsize 62
2912 22:10:32.465826 [CA 3] Center 33 (3~64) winsize 62
2913 22:10:32.469098 [CA 4] Center 32 (2~63) winsize 62
2914 22:10:32.472288 [CA 5] Center 32 (2~63) winsize 62
2915 22:10:32.472362
2916 22:10:32.475814 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2917 22:10:32.475897
2918 22:10:32.478823 [CATrainingPosCal] consider 1 rank data
2919 22:10:32.482421 u2DelayCellTimex100 = 270/100 ps
2920 22:10:32.485821 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2921 22:10:32.489187 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2922 22:10:32.495761 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2923 22:10:32.499285 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2924 22:10:32.502571 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2925 22:10:32.505867 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2926 22:10:32.505954
2927 22:10:32.509032 CA PerBit enable=1, Macro0, CA PI delay=32
2928 22:10:32.509107
2929 22:10:32.512319 [CBTSetCACLKResult] CA Dly = 32
2930 22:10:32.512394 CS Dly: 5 (0~36)
2931 22:10:32.515478 ==
2932 22:10:32.519129 Dram Type= 6, Freq= 0, CH_1, rank 1
2933 22:10:32.522359 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2934 22:10:32.522432 ==
2935 22:10:32.525274 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2936 22:10:32.532258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2937 22:10:32.540872 [CA 0] Center 37 (7~68) winsize 62
2938 22:10:32.544593 [CA 1] Center 37 (7~68) winsize 62
2939 22:10:32.547702 [CA 2] Center 34 (3~65) winsize 63
2940 22:10:32.551292 [CA 3] Center 33 (3~64) winsize 62
2941 22:10:32.554673 [CA 4] Center 32 (2~63) winsize 62
2942 22:10:32.557754 [CA 5] Center 32 (1~63) winsize 63
2943 22:10:32.557836
2944 22:10:32.561421 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2945 22:10:32.561501
2946 22:10:32.564770 [CATrainingPosCal] consider 2 rank data
2947 22:10:32.567894 u2DelayCellTimex100 = 270/100 ps
2948 22:10:32.571384 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2949 22:10:32.574404 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2950 22:10:32.577935 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2951 22:10:32.584787 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2952 22:10:32.588241 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2953 22:10:32.591145 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2954 22:10:32.591235
2955 22:10:32.594662 CA PerBit enable=1, Macro0, CA PI delay=32
2956 22:10:32.594738
2957 22:10:32.597738 [CBTSetCACLKResult] CA Dly = 32
2958 22:10:32.597819 CS Dly: 6 (0~38)
2959 22:10:32.597875
2960 22:10:32.601682 ----->DramcWriteLeveling(PI) begin...
2961 22:10:32.601762 ==
2962 22:10:32.604784 Dram Type= 6, Freq= 0, CH_1, rank 0
2963 22:10:32.611328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2964 22:10:32.611403 ==
2965 22:10:32.614596 Write leveling (Byte 0): 20 => 20
2966 22:10:32.618048 Write leveling (Byte 1): 22 => 22
2967 22:10:32.618121 DramcWriteLeveling(PI) end<-----
2968 22:10:32.621523
2969 22:10:32.621595 ==
2970 22:10:32.624869 Dram Type= 6, Freq= 0, CH_1, rank 0
2971 22:10:32.627925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2972 22:10:32.628000 ==
2973 22:10:32.631455 [Gating] SW mode calibration
2974 22:10:32.638007 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2975 22:10:32.641434 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2976 22:10:32.647946 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2977 22:10:32.651462 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2978 22:10:32.654730 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2979 22:10:32.661343 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2980 22:10:32.664488 0 11 16 | B1->B0 | 3333 2727 | 0 0 | (0 0) (0 1)
2981 22:10:32.667924 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2982 22:10:32.674861 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2983 22:10:32.678041 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2984 22:10:32.681183 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2985 22:10:32.688209 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2986 22:10:32.691481 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2987 22:10:32.694800 0 12 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2988 22:10:32.701182 0 12 16 | B1->B0 | 3232 4545 | 0 0 | (0 0) (0 0)
2989 22:10:32.704728 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2990 22:10:32.708059 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2991 22:10:32.711496 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2992 22:10:32.717621 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2993 22:10:32.721205 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2994 22:10:32.724470 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2995 22:10:32.731122 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2996 22:10:32.734324 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2997 22:10:32.737905 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2998 22:10:32.744669 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 22:10:32.747800 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 22:10:32.751554 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 22:10:32.757757 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 22:10:32.760914 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3003 22:10:32.764660 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3004 22:10:32.771089 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3005 22:10:32.774690 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3006 22:10:32.777751 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3007 22:10:32.784650 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3008 22:10:32.787713 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3009 22:10:32.790951 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3010 22:10:32.798017 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3011 22:10:32.800884 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3012 22:10:32.804555 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3013 22:10:32.811455 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3014 22:10:32.811531 Total UI for P1: 0, mck2ui 16
3015 22:10:32.814360 best dqsien dly found for B0: ( 0, 15, 16)
3016 22:10:32.820879 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3017 22:10:32.825028 Total UI for P1: 0, mck2ui 16
3018 22:10:32.827802 best dqsien dly found for B1: ( 0, 15, 18)
3019 22:10:32.831040 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3020 22:10:32.834503 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3021 22:10:32.834577
3022 22:10:32.837740 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3023 22:10:32.841560 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3024 22:10:32.844304 [Gating] SW calibration Done
3025 22:10:32.844378 ==
3026 22:10:32.847733 Dram Type= 6, Freq= 0, CH_1, rank 0
3027 22:10:32.851319 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3028 22:10:32.851394 ==
3029 22:10:32.854538 RX Vref Scan: 0
3030 22:10:32.854619
3031 22:10:32.857644 RX Vref 0 -> 0, step: 1
3032 22:10:32.857718
3033 22:10:32.857772 RX Delay -40 -> 252, step: 8
3034 22:10:32.864465 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3035 22:10:32.867975 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3036 22:10:32.871124 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3037 22:10:32.874373 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3038 22:10:32.877947 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3039 22:10:32.884811 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3040 22:10:32.887882 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3041 22:10:32.891374 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3042 22:10:32.894575 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3043 22:10:32.898678 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3044 22:10:32.901176 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3045 22:10:32.907629 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3046 22:10:32.911095 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3047 22:10:32.914491 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3048 22:10:32.917925 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3049 22:10:32.924813 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3050 22:10:32.924887 ==
3051 22:10:32.927861 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 22:10:32.931362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3053 22:10:32.931437 ==
3054 22:10:32.931491 DQS Delay:
3055 22:10:32.934465 DQS0 = 0, DQS1 = 0
3056 22:10:32.934538 DQM Delay:
3057 22:10:32.937526 DQM0 = 116, DQM1 = 108
3058 22:10:32.937599 DQ Delay:
3059 22:10:32.941199 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3060 22:10:32.944511 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3061 22:10:32.948006 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3062 22:10:32.951067 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3063 22:10:32.951142
3064 22:10:32.951195
3065 22:10:32.951242 ==
3066 22:10:32.954650 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 22:10:32.961410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3068 22:10:32.961486 ==
3069 22:10:32.961539
3070 22:10:32.961585
3071 22:10:32.961628 TX Vref Scan disable
3072 22:10:32.964509 == TX Byte 0 ==
3073 22:10:32.967752 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3074 22:10:32.971473 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3075 22:10:32.974490 == TX Byte 1 ==
3076 22:10:32.978240 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3077 22:10:32.984625 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3078 22:10:32.984682 ==
3079 22:10:32.987815 Dram Type= 6, Freq= 0, CH_1, rank 0
3080 22:10:32.991386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3081 22:10:32.991441 ==
3082 22:10:33.002468 TX Vref=22, minBit 3, minWin=25, winSum=413
3083 22:10:33.005866 TX Vref=24, minBit 1, minWin=25, winSum=415
3084 22:10:33.008872 TX Vref=26, minBit 11, minWin=25, winSum=424
3085 22:10:33.012242 TX Vref=28, minBit 7, minWin=26, winSum=431
3086 22:10:33.015668 TX Vref=30, minBit 9, minWin=25, winSum=429
3087 22:10:33.019414 TX Vref=32, minBit 2, minWin=26, winSum=427
3088 22:10:33.025773 [TxChooseVref] Worse bit 7, Min win 26, Win sum 431, Final Vref 28
3089 22:10:33.025829
3090 22:10:33.029504 Final TX Range 1 Vref 28
3091 22:10:33.029558
3092 22:10:33.029604 ==
3093 22:10:33.032468 Dram Type= 6, Freq= 0, CH_1, rank 0
3094 22:10:33.036132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3095 22:10:33.036194 ==
3096 22:10:33.036258
3097 22:10:33.039058
3098 22:10:33.039111 TX Vref Scan disable
3099 22:10:33.042946 == TX Byte 0 ==
3100 22:10:33.045830 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3101 22:10:33.049013 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3102 22:10:33.052009 == TX Byte 1 ==
3103 22:10:33.055672 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3104 22:10:33.059085 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3105 22:10:33.059146
3106 22:10:33.062189 [DATLAT]
3107 22:10:33.062249 Freq=1200, CH1 RK0
3108 22:10:33.062297
3109 22:10:33.065458 DATLAT Default: 0xd
3110 22:10:33.065520 0, 0xFFFF, sum = 0
3111 22:10:33.068955 1, 0xFFFF, sum = 0
3112 22:10:33.069014 2, 0xFFFF, sum = 0
3113 22:10:33.072208 3, 0xFFFF, sum = 0
3114 22:10:33.072264 4, 0xFFFF, sum = 0
3115 22:10:33.075883 5, 0xFFFF, sum = 0
3116 22:10:33.075945 6, 0xFFFF, sum = 0
3117 22:10:33.078949 7, 0xFFFF, sum = 0
3118 22:10:33.079005 8, 0xFFFF, sum = 0
3119 22:10:33.082071 9, 0xFFFF, sum = 0
3120 22:10:33.085842 10, 0xFFFF, sum = 0
3121 22:10:33.085902 11, 0x0, sum = 1
3122 22:10:33.085949 12, 0x0, sum = 2
3123 22:10:33.088983 13, 0x0, sum = 3
3124 22:10:33.089042 14, 0x0, sum = 4
3125 22:10:33.092349 best_step = 12
3126 22:10:33.092408
3127 22:10:33.092455 ==
3128 22:10:33.095749 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 22:10:33.099183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3130 22:10:33.099240 ==
3131 22:10:33.102572 RX Vref Scan: 1
3132 22:10:33.102627
3133 22:10:33.102672 Set Vref Range= 32 -> 127
3134 22:10:33.102715
3135 22:10:33.105769 RX Vref 32 -> 127, step: 1
3136 22:10:33.105823
3137 22:10:33.108915 RX Delay -29 -> 252, step: 4
3138 22:10:33.108969
3139 22:10:33.112386 Set Vref, RX VrefLevel [Byte0]: 32
3140 22:10:33.115715 [Byte1]: 32
3141 22:10:33.115776
3142 22:10:33.118915 Set Vref, RX VrefLevel [Byte0]: 33
3143 22:10:33.122525 [Byte1]: 33
3144 22:10:33.127023
3145 22:10:33.127079 Set Vref, RX VrefLevel [Byte0]: 34
3146 22:10:33.130195 [Byte1]: 34
3147 22:10:33.134548
3148 22:10:33.134604 Set Vref, RX VrefLevel [Byte0]: 35
3149 22:10:33.137897 [Byte1]: 35
3150 22:10:33.142672
3151 22:10:33.142725 Set Vref, RX VrefLevel [Byte0]: 36
3152 22:10:33.145787 [Byte1]: 36
3153 22:10:33.150557
3154 22:10:33.150613 Set Vref, RX VrefLevel [Byte0]: 37
3155 22:10:33.154029 [Byte1]: 37
3156 22:10:33.158394
3157 22:10:33.158454 Set Vref, RX VrefLevel [Byte0]: 38
3158 22:10:33.161841 [Byte1]: 38
3159 22:10:33.166627
3160 22:10:33.166691 Set Vref, RX VrefLevel [Byte0]: 39
3161 22:10:33.169775 [Byte1]: 39
3162 22:10:33.174976
3163 22:10:33.175049 Set Vref, RX VrefLevel [Byte0]: 40
3164 22:10:33.177936 [Byte1]: 40
3165 22:10:33.182698
3166 22:10:33.182772 Set Vref, RX VrefLevel [Byte0]: 41
3167 22:10:33.185836 [Byte1]: 41
3168 22:10:33.190532
3169 22:10:33.190605 Set Vref, RX VrefLevel [Byte0]: 42
3170 22:10:33.193631 [Byte1]: 42
3171 22:10:33.198635
3172 22:10:33.198710 Set Vref, RX VrefLevel [Byte0]: 43
3173 22:10:33.201630 [Byte1]: 43
3174 22:10:33.206426
3175 22:10:33.206499 Set Vref, RX VrefLevel [Byte0]: 44
3176 22:10:33.209633 [Byte1]: 44
3177 22:10:33.214049
3178 22:10:33.214129 Set Vref, RX VrefLevel [Byte0]: 45
3179 22:10:33.217632 [Byte1]: 45
3180 22:10:33.222193
3181 22:10:33.222267 Set Vref, RX VrefLevel [Byte0]: 46
3182 22:10:33.225578 [Byte1]: 46
3183 22:10:33.230001
3184 22:10:33.230075 Set Vref, RX VrefLevel [Byte0]: 47
3185 22:10:33.233446 [Byte1]: 47
3186 22:10:33.237970
3187 22:10:33.238044 Set Vref, RX VrefLevel [Byte0]: 48
3188 22:10:33.241606 [Byte1]: 48
3189 22:10:33.246191
3190 22:10:33.246265 Set Vref, RX VrefLevel [Byte0]: 49
3191 22:10:33.249391 [Byte1]: 49
3192 22:10:33.253719
3193 22:10:33.253798 Set Vref, RX VrefLevel [Byte0]: 50
3194 22:10:33.257448 [Byte1]: 50
3195 22:10:33.261881
3196 22:10:33.261954 Set Vref, RX VrefLevel [Byte0]: 51
3197 22:10:33.265106 [Byte1]: 51
3198 22:10:33.270139
3199 22:10:33.270211 Set Vref, RX VrefLevel [Byte0]: 52
3200 22:10:33.273382 [Byte1]: 52
3201 22:10:33.278271
3202 22:10:33.278354 Set Vref, RX VrefLevel [Byte0]: 53
3203 22:10:33.281466 [Byte1]: 53
3204 22:10:33.286168
3205 22:10:33.286241 Set Vref, RX VrefLevel [Byte0]: 54
3206 22:10:33.289196 [Byte1]: 54
3207 22:10:33.293822
3208 22:10:33.293907 Set Vref, RX VrefLevel [Byte0]: 55
3209 22:10:33.297165 [Byte1]: 55
3210 22:10:33.301874
3211 22:10:33.301947 Set Vref, RX VrefLevel [Byte0]: 56
3212 22:10:33.305437 [Byte1]: 56
3213 22:10:33.310107
3214 22:10:33.310180 Set Vref, RX VrefLevel [Byte0]: 57
3215 22:10:33.313174 [Byte1]: 57
3216 22:10:33.317778
3217 22:10:33.317857 Set Vref, RX VrefLevel [Byte0]: 58
3218 22:10:33.321065 [Byte1]: 58
3219 22:10:33.325585
3220 22:10:33.325657 Set Vref, RX VrefLevel [Byte0]: 59
3221 22:10:33.328782 [Byte1]: 59
3222 22:10:33.333603
3223 22:10:33.333681 Set Vref, RX VrefLevel [Byte0]: 60
3224 22:10:33.336788 [Byte1]: 60
3225 22:10:33.341653
3226 22:10:33.341728 Set Vref, RX VrefLevel [Byte0]: 61
3227 22:10:33.345111 [Byte1]: 61
3228 22:10:33.349583
3229 22:10:33.349664 Set Vref, RX VrefLevel [Byte0]: 62
3230 22:10:33.352781 [Byte1]: 62
3231 22:10:33.357421
3232 22:10:33.357506 Set Vref, RX VrefLevel [Byte0]: 63
3233 22:10:33.361114 [Byte1]: 63
3234 22:10:33.365860
3235 22:10:33.365936 Set Vref, RX VrefLevel [Byte0]: 64
3236 22:10:33.368864 [Byte1]: 64
3237 22:10:33.373609
3238 22:10:33.373683 Set Vref, RX VrefLevel [Byte0]: 65
3239 22:10:33.377114 [Byte1]: 65
3240 22:10:33.381380
3241 22:10:33.381454 Set Vref, RX VrefLevel [Byte0]: 66
3242 22:10:33.384697 [Byte1]: 66
3243 22:10:33.389526
3244 22:10:33.389602 Set Vref, RX VrefLevel [Byte0]: 67
3245 22:10:33.392692 [Byte1]: 67
3246 22:10:33.397317
3247 22:10:33.397408 Final RX Vref Byte 0 = 53 to rank0
3248 22:10:33.400581 Final RX Vref Byte 1 = 50 to rank0
3249 22:10:33.404319 Final RX Vref Byte 0 = 53 to rank1
3250 22:10:33.407506 Final RX Vref Byte 1 = 50 to rank1==
3251 22:10:33.410718 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 22:10:33.413910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3253 22:10:33.417144 ==
3254 22:10:33.417222 DQS Delay:
3255 22:10:33.417275 DQS0 = 0, DQS1 = 0
3256 22:10:33.420745 DQM Delay:
3257 22:10:33.420819 DQM0 = 115, DQM1 = 106
3258 22:10:33.423973 DQ Delay:
3259 22:10:33.427738 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3260 22:10:33.430731 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3261 22:10:33.434142 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =96
3262 22:10:33.437221 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3263 22:10:33.437295
3264 22:10:33.437357
3265 22:10:33.443767 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3266 22:10:33.447332 CH1 RK0: MR19=404, MR18=1515
3267 22:10:33.453977 CH1_RK0: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27
3268 22:10:33.454052
3269 22:10:33.457345 ----->DramcWriteLeveling(PI) begin...
3270 22:10:33.457433 ==
3271 22:10:33.460842 Dram Type= 6, Freq= 0, CH_1, rank 1
3272 22:10:33.464061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3273 22:10:33.464145 ==
3274 22:10:33.467404 Write leveling (Byte 0): 21 => 21
3275 22:10:33.470535 Write leveling (Byte 1): 21 => 21
3276 22:10:33.474591 DramcWriteLeveling(PI) end<-----
3277 22:10:33.474665
3278 22:10:33.474716 ==
3279 22:10:33.477567 Dram Type= 6, Freq= 0, CH_1, rank 1
3280 22:10:33.484306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3281 22:10:33.484380 ==
3282 22:10:33.484430 [Gating] SW mode calibration
3283 22:10:33.494040 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3284 22:10:33.497485 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3285 22:10:33.501027 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3286 22:10:33.507435 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3287 22:10:33.511014 0 11 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3288 22:10:33.514138 0 11 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
3289 22:10:33.521034 0 11 16 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0)
3290 22:10:33.524025 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3291 22:10:33.527686 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3292 22:10:33.534456 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3293 22:10:33.537121 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3294 22:10:33.540667 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3295 22:10:33.547570 0 12 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3296 22:10:33.550682 0 12 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3297 22:10:33.553950 0 12 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3298 22:10:33.560560 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3299 22:10:33.564455 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3300 22:10:33.567350 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3301 22:10:33.570642 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3302 22:10:33.577634 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3303 22:10:33.581006 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3304 22:10:33.584097 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3305 22:10:33.591091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3306 22:10:33.593945 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3307 22:10:33.597467 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3308 22:10:33.604111 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3309 22:10:33.607263 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3310 22:10:33.610949 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3311 22:10:33.617438 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3312 22:10:33.620405 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3313 22:10:33.624075 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3314 22:10:33.630400 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3315 22:10:33.634397 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3316 22:10:33.637616 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3317 22:10:33.644010 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3318 22:10:33.647452 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3319 22:10:33.650412 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3320 22:10:33.657927 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3321 22:10:33.660699 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3322 22:10:33.663979 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3323 22:10:33.667462 Total UI for P1: 0, mck2ui 16
3324 22:10:33.670900 best dqsien dly found for B0: ( 0, 15, 14)
3325 22:10:33.673813 Total UI for P1: 0, mck2ui 16
3326 22:10:33.677518 best dqsien dly found for B1: ( 0, 15, 16)
3327 22:10:33.680498 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3328 22:10:33.683864 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3329 22:10:33.683938
3330 22:10:33.687097 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3331 22:10:33.693816 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3332 22:10:33.693890 [Gating] SW calibration Done
3333 22:10:33.693943 ==
3334 22:10:33.697317 Dram Type= 6, Freq= 0, CH_1, rank 1
3335 22:10:33.704023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3336 22:10:33.704098 ==
3337 22:10:33.704151 RX Vref Scan: 0
3338 22:10:33.704206
3339 22:10:33.707254 RX Vref 0 -> 0, step: 1
3340 22:10:33.707332
3341 22:10:33.710736 RX Delay -40 -> 252, step: 8
3342 22:10:33.713858 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3343 22:10:33.716977 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3344 22:10:33.720285 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3345 22:10:33.727096 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3346 22:10:33.730646 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3347 22:10:33.733707 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3348 22:10:33.737182 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3349 22:10:33.740439 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3350 22:10:33.744072 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3351 22:10:33.750449 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3352 22:10:33.753731 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3353 22:10:33.757246 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3354 22:10:33.760425 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3355 22:10:33.764013 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3356 22:10:33.770673 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3357 22:10:33.773944 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3358 22:10:33.774003 ==
3359 22:10:33.777483 Dram Type= 6, Freq= 0, CH_1, rank 1
3360 22:10:33.780636 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3361 22:10:33.780692 ==
3362 22:10:33.784074 DQS Delay:
3363 22:10:33.784135 DQS0 = 0, DQS1 = 0
3364 22:10:33.784195 DQM Delay:
3365 22:10:33.787535 DQM0 = 116, DQM1 = 106
3366 22:10:33.787596 DQ Delay:
3367 22:10:33.790507 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3368 22:10:33.794282 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3369 22:10:33.797083 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =103
3370 22:10:33.804282 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3371 22:10:33.804347
3372 22:10:33.804397
3373 22:10:33.804442 ==
3374 22:10:33.807737 Dram Type= 6, Freq= 0, CH_1, rank 1
3375 22:10:33.810933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3376 22:10:33.811004 ==
3377 22:10:33.811080
3378 22:10:33.811127
3379 22:10:33.814394 TX Vref Scan disable
3380 22:10:33.814450 == TX Byte 0 ==
3381 22:10:33.820955 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3382 22:10:33.824240 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3383 22:10:33.824315 == TX Byte 1 ==
3384 22:10:33.830830 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3385 22:10:33.834271 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3386 22:10:33.834345 ==
3387 22:10:33.837680 Dram Type= 6, Freq= 0, CH_1, rank 1
3388 22:10:33.840731 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3389 22:10:33.840806 ==
3390 22:10:33.853065 TX Vref=22, minBit 0, minWin=26, winSum=424
3391 22:10:33.856181 TX Vref=24, minBit 9, minWin=25, winSum=425
3392 22:10:33.859545 TX Vref=26, minBit 8, minWin=26, winSum=430
3393 22:10:33.862816 TX Vref=28, minBit 9, minWin=26, winSum=432
3394 22:10:33.866308 TX Vref=30, minBit 9, minWin=26, winSum=432
3395 22:10:33.872911 TX Vref=32, minBit 3, minWin=26, winSum=431
3396 22:10:33.876089 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
3397 22:10:33.876155
3398 22:10:33.879573 Final TX Range 1 Vref 28
3399 22:10:33.879631
3400 22:10:33.879678 ==
3401 22:10:33.882875 Dram Type= 6, Freq= 0, CH_1, rank 1
3402 22:10:33.886667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3403 22:10:33.886723 ==
3404 22:10:33.889493
3405 22:10:33.889558
3406 22:10:33.889608 TX Vref Scan disable
3407 22:10:33.892633 == TX Byte 0 ==
3408 22:10:33.896139 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3409 22:10:33.899846 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3410 22:10:33.902990 == TX Byte 1 ==
3411 22:10:33.906137 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3412 22:10:33.909520 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3413 22:10:33.909580
3414 22:10:33.912828 [DATLAT]
3415 22:10:33.912884 Freq=1200, CH1 RK1
3416 22:10:33.912930
3417 22:10:33.916333 DATLAT Default: 0xc
3418 22:10:33.916402 0, 0xFFFF, sum = 0
3419 22:10:33.919713 1, 0xFFFF, sum = 0
3420 22:10:33.919772 2, 0xFFFF, sum = 0
3421 22:10:33.922669 3, 0xFFFF, sum = 0
3422 22:10:33.922725 4, 0xFFFF, sum = 0
3423 22:10:33.926014 5, 0xFFFF, sum = 0
3424 22:10:33.926071 6, 0xFFFF, sum = 0
3425 22:10:33.929206 7, 0xFFFF, sum = 0
3426 22:10:33.932835 8, 0xFFFF, sum = 0
3427 22:10:33.932896 9, 0xFFFF, sum = 0
3428 22:10:33.936152 10, 0xFFFF, sum = 0
3429 22:10:33.936211 11, 0x0, sum = 1
3430 22:10:33.936263 12, 0x0, sum = 2
3431 22:10:33.939560 13, 0x0, sum = 3
3432 22:10:33.939623 14, 0x0, sum = 4
3433 22:10:33.942799 best_step = 12
3434 22:10:33.942871
3435 22:10:33.942934 ==
3436 22:10:33.946218 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 22:10:33.949875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3438 22:10:33.949950 ==
3439 22:10:33.953113 RX Vref Scan: 0
3440 22:10:33.953173
3441 22:10:33.953223 RX Vref 0 -> 0, step: 1
3442 22:10:33.953278
3443 22:10:33.956356 RX Delay -29 -> 252, step: 4
3444 22:10:33.963473 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3445 22:10:33.966030 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3446 22:10:33.969479 iDelay=199, Bit 2, Center 106 (35 ~ 178) 144
3447 22:10:33.972922 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3448 22:10:33.979599 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3449 22:10:33.982804 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3450 22:10:33.986409 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3451 22:10:33.989656 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3452 22:10:33.993120 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3453 22:10:33.996421 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3454 22:10:34.002943 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3455 22:10:34.006179 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3456 22:10:34.009669 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3457 22:10:34.012819 iDelay=199, Bit 13, Center 112 (43 ~ 182) 140
3458 22:10:34.016151 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3459 22:10:34.022705 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3460 22:10:34.022779 ==
3461 22:10:34.026360 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 22:10:34.029470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3463 22:10:34.029545 ==
3464 22:10:34.029597 DQS Delay:
3465 22:10:34.032977 DQS0 = 0, DQS1 = 0
3466 22:10:34.033051 DQM Delay:
3467 22:10:34.036396 DQM0 = 114, DQM1 = 104
3468 22:10:34.036471 DQ Delay:
3469 22:10:34.039550 DQ0 =114, DQ1 =112, DQ2 =106, DQ3 =112
3470 22:10:34.043119 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3471 22:10:34.046187 DQ8 =88, DQ9 =94, DQ10 =106, DQ11 =98
3472 22:10:34.049292 DQ12 =114, DQ13 =112, DQ14 =112, DQ15 =110
3473 22:10:34.049371
3474 22:10:34.049423
3475 22:10:34.059414 [DQSOSCAuto] RK1, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3476 22:10:34.063036 CH1 RK1: MR19=404, MR18=808
3477 22:10:34.066184 CH1_RK1: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
3478 22:10:34.069322 [RxdqsGatingPostProcess] freq 1200
3479 22:10:34.076256 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3480 22:10:34.079569 Pre-setting of DQS Precalculation
3481 22:10:34.083022 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3482 22:10:34.092826 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3483 22:10:34.099661 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3484 22:10:34.099733
3485 22:10:34.099785
3486 22:10:34.103072 [Calibration Summary] 2400 Mbps
3487 22:10:34.103142 CH 0, Rank 0
3488 22:10:34.106057 SW Impedance : PASS
3489 22:10:34.106115 DUTY Scan : NO K
3490 22:10:34.109443 ZQ Calibration : PASS
3491 22:10:34.113260 Jitter Meter : NO K
3492 22:10:34.113324 CBT Training : PASS
3493 22:10:34.116431 Write leveling : PASS
3494 22:10:34.119857 RX DQS gating : PASS
3495 22:10:34.119919 RX DQ/DQS(RDDQC) : PASS
3496 22:10:34.123310 TX DQ/DQS : PASS
3497 22:10:34.126265 RX DATLAT : PASS
3498 22:10:34.126325 RX DQ/DQS(Engine): PASS
3499 22:10:34.129711 TX OE : NO K
3500 22:10:34.129775 All Pass.
3501 22:10:34.129828
3502 22:10:34.133013 CH 0, Rank 1
3503 22:10:34.133075 SW Impedance : PASS
3504 22:10:34.136316 DUTY Scan : NO K
3505 22:10:34.136382 ZQ Calibration : PASS
3506 22:10:34.139433 Jitter Meter : NO K
3507 22:10:34.143109 CBT Training : PASS
3508 22:10:34.143165 Write leveling : PASS
3509 22:10:34.146430 RX DQS gating : PASS
3510 22:10:34.149384 RX DQ/DQS(RDDQC) : PASS
3511 22:10:34.149460 TX DQ/DQS : PASS
3512 22:10:34.152701 RX DATLAT : PASS
3513 22:10:34.156291 RX DQ/DQS(Engine): PASS
3514 22:10:34.156355 TX OE : NO K
3515 22:10:34.159375 All Pass.
3516 22:10:34.159438
3517 22:10:34.159490 CH 1, Rank 0
3518 22:10:34.162755 SW Impedance : PASS
3519 22:10:34.162810 DUTY Scan : NO K
3520 22:10:34.165994 ZQ Calibration : PASS
3521 22:10:34.169343 Jitter Meter : NO K
3522 22:10:34.169408 CBT Training : PASS
3523 22:10:34.172651 Write leveling : PASS
3524 22:10:34.175850 RX DQS gating : PASS
3525 22:10:34.175919 RX DQ/DQS(RDDQC) : PASS
3526 22:10:34.179202 TX DQ/DQS : PASS
3527 22:10:34.179300 RX DATLAT : PASS
3528 22:10:34.182666 RX DQ/DQS(Engine): PASS
3529 22:10:34.186238 TX OE : NO K
3530 22:10:34.186310 All Pass.
3531 22:10:34.186373
3532 22:10:34.186434 CH 1, Rank 1
3533 22:10:34.189459 SW Impedance : PASS
3534 22:10:34.192772 DUTY Scan : NO K
3535 22:10:34.192834 ZQ Calibration : PASS
3536 22:10:34.196061 Jitter Meter : NO K
3537 22:10:34.199491 CBT Training : PASS
3538 22:10:34.199553 Write leveling : PASS
3539 22:10:34.202573 RX DQS gating : PASS
3540 22:10:34.206155 RX DQ/DQS(RDDQC) : PASS
3541 22:10:34.206225 TX DQ/DQS : PASS
3542 22:10:34.209275 RX DATLAT : PASS
3543 22:10:34.212835 RX DQ/DQS(Engine): PASS
3544 22:10:34.212892 TX OE : NO K
3545 22:10:34.212939 All Pass.
3546 22:10:34.216138
3547 22:10:34.216197 DramC Write-DBI off
3548 22:10:34.219338 PER_BANK_REFRESH: Hybrid Mode
3549 22:10:34.219407 TX_TRACKING: ON
3550 22:10:34.229109 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3551 22:10:34.232737 [FAST_K] Save calibration result to emmc
3552 22:10:34.236052 dramc_set_vcore_voltage set vcore to 650000
3553 22:10:34.239594 Read voltage for 600, 5
3554 22:10:34.239654 Vio18 = 0
3555 22:10:34.242692 Vcore = 650000
3556 22:10:34.242747 Vdram = 0
3557 22:10:34.242793 Vddq = 0
3558 22:10:34.242838 Vmddr = 0
3559 22:10:34.249695 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3560 22:10:34.255990 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3561 22:10:34.256062 MEM_TYPE=3, freq_sel=19
3562 22:10:34.259721 sv_algorithm_assistance_LP4_1600
3563 22:10:34.262690 ============ PULL DRAM RESETB DOWN ============
3564 22:10:34.269460 ========== PULL DRAM RESETB DOWN end =========
3565 22:10:34.272532 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3566 22:10:34.275827 ===================================
3567 22:10:34.279298 LPDDR4 DRAM CONFIGURATION
3568 22:10:34.282528 ===================================
3569 22:10:34.282596 EX_ROW_EN[0] = 0x0
3570 22:10:34.285776 EX_ROW_EN[1] = 0x0
3571 22:10:34.285840 LP4Y_EN = 0x0
3572 22:10:34.289240 WORK_FSP = 0x0
3573 22:10:34.289299 WL = 0x2
3574 22:10:34.292595 RL = 0x2
3575 22:10:34.292658 BL = 0x2
3576 22:10:34.295729 RPST = 0x0
3577 22:10:34.298901 RD_PRE = 0x0
3578 22:10:34.298962 WR_PRE = 0x1
3579 22:10:34.302431 WR_PST = 0x0
3580 22:10:34.302501 DBI_WR = 0x0
3581 22:10:34.305822 DBI_RD = 0x0
3582 22:10:34.305882 OTF = 0x1
3583 22:10:34.309211 ===================================
3584 22:10:34.312407 ===================================
3585 22:10:34.315660 ANA top config
3586 22:10:34.319049 ===================================
3587 22:10:34.319108 DLL_ASYNC_EN = 0
3588 22:10:34.322278 ALL_SLAVE_EN = 1
3589 22:10:34.325491 NEW_RANK_MODE = 1
3590 22:10:34.329025 DLL_IDLE_MODE = 1
3591 22:10:34.329084 LP45_APHY_COMB_EN = 1
3592 22:10:34.332359 TX_ODT_DIS = 1
3593 22:10:34.335584 NEW_8X_MODE = 1
3594 22:10:34.339053 ===================================
3595 22:10:34.342173 ===================================
3596 22:10:34.345530 data_rate = 1200
3597 22:10:34.349036 CKR = 1
3598 22:10:34.349090 DQ_P2S_RATIO = 8
3599 22:10:34.352317 ===================================
3600 22:10:34.355373 CA_P2S_RATIO = 8
3601 22:10:34.358690 DQ_CA_OPEN = 0
3602 22:10:34.362222 DQ_SEMI_OPEN = 0
3603 22:10:34.366064 CA_SEMI_OPEN = 0
3604 22:10:34.369104 CA_FULL_RATE = 0
3605 22:10:34.369176 DQ_CKDIV4_EN = 1
3606 22:10:34.372228 CA_CKDIV4_EN = 1
3607 22:10:34.375825 CA_PREDIV_EN = 0
3608 22:10:34.379269 PH8_DLY = 0
3609 22:10:34.382402 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3610 22:10:34.385836 DQ_AAMCK_DIV = 4
3611 22:10:34.385910 CA_AAMCK_DIV = 4
3612 22:10:34.389042 CA_ADMCK_DIV = 4
3613 22:10:34.392170 DQ_TRACK_CA_EN = 0
3614 22:10:34.395455 CA_PICK = 600
3615 22:10:34.399045 CA_MCKIO = 600
3616 22:10:34.402380 MCKIO_SEMI = 0
3617 22:10:34.405546 PLL_FREQ = 2288
3618 22:10:34.405623 DQ_UI_PI_RATIO = 32
3619 22:10:34.408813 CA_UI_PI_RATIO = 0
3620 22:10:34.412089 ===================================
3621 22:10:34.415572 ===================================
3622 22:10:34.419095 memory_type:LPDDR4
3623 22:10:34.422231 GP_NUM : 10
3624 22:10:34.422306 SRAM_EN : 1
3625 22:10:34.425459 MD32_EN : 0
3626 22:10:34.428611 ===================================
3627 22:10:34.432018 [ANA_INIT] >>>>>>>>>>>>>>
3628 22:10:34.432093 <<<<<< [CONFIGURE PHASE]: ANA_TX
3629 22:10:34.435140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3630 22:10:34.438828 ===================================
3631 22:10:34.441703 data_rate = 1200,PCW = 0X5800
3632 22:10:34.445018 ===================================
3633 22:10:34.448722 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3634 22:10:34.455224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3635 22:10:34.461461 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3636 22:10:34.465062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3637 22:10:34.468350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3638 22:10:34.471541 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3639 22:10:34.474959 [ANA_INIT] flow start
3640 22:10:34.475034 [ANA_INIT] PLL >>>>>>>>
3641 22:10:34.478099 [ANA_INIT] PLL <<<<<<<<
3642 22:10:34.481552 [ANA_INIT] MIDPI >>>>>>>>
3643 22:10:34.485149 [ANA_INIT] MIDPI <<<<<<<<
3644 22:10:34.485223 [ANA_INIT] DLL >>>>>>>>
3645 22:10:34.488298 [ANA_INIT] flow end
3646 22:10:34.491406 ============ LP4 DIFF to SE enter ============
3647 22:10:34.495048 ============ LP4 DIFF to SE exit ============
3648 22:10:34.497791 [ANA_INIT] <<<<<<<<<<<<<
3649 22:10:34.501130 [Flow] Enable top DCM control >>>>>
3650 22:10:34.504730 [Flow] Enable top DCM control <<<<<
3651 22:10:34.507607 Enable DLL master slave shuffle
3652 22:10:34.514244 ==============================================================
3653 22:10:34.514308 Gating Mode config
3654 22:10:34.520899 ==============================================================
3655 22:10:34.520963 Config description:
3656 22:10:34.530884 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3657 22:10:34.537526 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3658 22:10:34.544046 SELPH_MODE 0: By rank 1: By Phase
3659 22:10:34.547592 ==============================================================
3660 22:10:34.550987 GAT_TRACK_EN = 1
3661 22:10:34.554185 RX_GATING_MODE = 2
3662 22:10:34.557526 RX_GATING_TRACK_MODE = 2
3663 22:10:34.560664 SELPH_MODE = 1
3664 22:10:34.563835 PICG_EARLY_EN = 1
3665 22:10:34.567635 VALID_LAT_VALUE = 1
3666 22:10:34.573762 ==============================================================
3667 22:10:34.577488 Enter into Gating configuration >>>>
3668 22:10:34.580749 Exit from Gating configuration <<<<
3669 22:10:34.583985 Enter into DVFS_PRE_config >>>>>
3670 22:10:34.593688 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3671 22:10:34.596967 Exit from DVFS_PRE_config <<<<<
3672 22:10:34.600447 Enter into PICG configuration >>>>
3673 22:10:34.604104 Exit from PICG configuration <<<<
3674 22:10:34.607140 [RX_INPUT] configuration >>>>>
3675 22:10:34.607194 [RX_INPUT] configuration <<<<<
3676 22:10:34.613779 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3677 22:10:34.620441 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3678 22:10:34.623608 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3679 22:10:34.629998 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3680 22:10:34.636932 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3681 22:10:34.643445 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3682 22:10:34.647001 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3683 22:10:34.650126 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3684 22:10:34.657016 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3685 22:10:34.660041 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3686 22:10:34.663126 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3687 22:10:34.670006 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3688 22:10:34.673071 ===================================
3689 22:10:34.673126 LPDDR4 DRAM CONFIGURATION
3690 22:10:34.676491 ===================================
3691 22:10:34.679801 EX_ROW_EN[0] = 0x0
3692 22:10:34.679857 EX_ROW_EN[1] = 0x0
3693 22:10:34.683226 LP4Y_EN = 0x0
3694 22:10:34.686575 WORK_FSP = 0x0
3695 22:10:34.686644 WL = 0x2
3696 22:10:34.689664 RL = 0x2
3697 22:10:34.689728 BL = 0x2
3698 22:10:34.693237 RPST = 0x0
3699 22:10:34.693294 RD_PRE = 0x0
3700 22:10:34.696188 WR_PRE = 0x1
3701 22:10:34.696243 WR_PST = 0x0
3702 22:10:34.699374 DBI_WR = 0x0
3703 22:10:34.699438 DBI_RD = 0x0
3704 22:10:34.703116 OTF = 0x1
3705 22:10:34.706756 ===================================
3706 22:10:34.709334 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3707 22:10:34.712783 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3708 22:10:34.719790 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3709 22:10:34.722941 ===================================
3710 22:10:34.723003 LPDDR4 DRAM CONFIGURATION
3711 22:10:34.726001 ===================================
3712 22:10:34.729253 EX_ROW_EN[0] = 0x10
3713 22:10:34.729318 EX_ROW_EN[1] = 0x0
3714 22:10:34.732376 LP4Y_EN = 0x0
3715 22:10:34.736150 WORK_FSP = 0x0
3716 22:10:34.736205 WL = 0x2
3717 22:10:34.739224 RL = 0x2
3718 22:10:34.739279 BL = 0x2
3719 22:10:34.743147 RPST = 0x0
3720 22:10:34.743217 RD_PRE = 0x0
3721 22:10:34.745759 WR_PRE = 0x1
3722 22:10:34.745815 WR_PST = 0x0
3723 22:10:34.749245 DBI_WR = 0x0
3724 22:10:34.749299 DBI_RD = 0x0
3725 22:10:34.752217 OTF = 0x1
3726 22:10:34.755681 ===================================
3727 22:10:34.762436 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3728 22:10:34.765510 nWR fixed to 30
3729 22:10:34.765568 [ModeRegInit_LP4] CH0 RK0
3730 22:10:34.768753 [ModeRegInit_LP4] CH0 RK1
3731 22:10:34.772017 [ModeRegInit_LP4] CH1 RK0
3732 22:10:34.775603 [ModeRegInit_LP4] CH1 RK1
3733 22:10:34.775659 match AC timing 16
3734 22:10:34.781993 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3735 22:10:34.785098 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3736 22:10:34.788729 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3737 22:10:34.795443 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3738 22:10:34.799095 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3739 22:10:34.799159 ==
3740 22:10:34.801904 Dram Type= 6, Freq= 0, CH_0, rank 0
3741 22:10:34.805593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3742 22:10:34.805653 ==
3743 22:10:34.811841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3744 22:10:34.818352 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3745 22:10:34.822227 [CA 0] Center 35 (5~66) winsize 62
3746 22:10:34.824911 [CA 1] Center 35 (5~66) winsize 62
3747 22:10:34.828628 [CA 2] Center 34 (4~65) winsize 62
3748 22:10:34.832009 [CA 3] Center 34 (3~65) winsize 63
3749 22:10:34.835198 [CA 4] Center 33 (3~64) winsize 62
3750 22:10:34.838198 [CA 5] Center 33 (3~64) winsize 62
3751 22:10:34.838253
3752 22:10:34.842063 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3753 22:10:34.842120
3754 22:10:34.844921 [CATrainingPosCal] consider 1 rank data
3755 22:10:34.848588 u2DelayCellTimex100 = 270/100 ps
3756 22:10:34.851588 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3757 22:10:34.855213 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3758 22:10:34.858097 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3759 22:10:34.861362 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3760 22:10:34.864689 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3761 22:10:34.868369 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3762 22:10:34.868426
3763 22:10:34.874569 CA PerBit enable=1, Macro0, CA PI delay=33
3764 22:10:34.874624
3765 22:10:34.874673 [CBTSetCACLKResult] CA Dly = 33
3766 22:10:34.877914 CS Dly: 5 (0~36)
3767 22:10:34.877969 ==
3768 22:10:34.881366 Dram Type= 6, Freq= 0, CH_0, rank 1
3769 22:10:34.884584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3770 22:10:34.884640 ==
3771 22:10:34.891024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3772 22:10:34.897814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3773 22:10:34.901278 [CA 0] Center 35 (5~66) winsize 62
3774 22:10:34.904687 [CA 1] Center 35 (5~66) winsize 62
3775 22:10:34.908014 [CA 2] Center 34 (4~65) winsize 62
3776 22:10:34.911190 [CA 3] Center 34 (4~65) winsize 62
3777 22:10:34.914598 [CA 4] Center 33 (3~64) winsize 62
3778 22:10:34.917909 [CA 5] Center 33 (3~64) winsize 62
3779 22:10:34.917966
3780 22:10:34.921220 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3781 22:10:34.921293
3782 22:10:34.924163 [CATrainingPosCal] consider 2 rank data
3783 22:10:34.927855 u2DelayCellTimex100 = 270/100 ps
3784 22:10:34.930802 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3785 22:10:34.934073 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3786 22:10:34.937407 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3787 22:10:34.941002 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3788 22:10:34.944116 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3789 22:10:34.950844 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3790 22:10:34.950903
3791 22:10:34.954525 CA PerBit enable=1, Macro0, CA PI delay=33
3792 22:10:34.954587
3793 22:10:34.957341 [CBTSetCACLKResult] CA Dly = 33
3794 22:10:34.957411 CS Dly: 5 (0~36)
3795 22:10:34.957457
3796 22:10:34.960425 ----->DramcWriteLeveling(PI) begin...
3797 22:10:34.960484 ==
3798 22:10:34.964017 Dram Type= 6, Freq= 0, CH_0, rank 0
3799 22:10:34.970722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3800 22:10:34.970780 ==
3801 22:10:34.973773 Write leveling (Byte 0): 30 => 30
3802 22:10:34.973838 Write leveling (Byte 1): 30 => 30
3803 22:10:34.977364 DramcWriteLeveling(PI) end<-----
3804 22:10:34.977423
3805 22:10:34.980334 ==
3806 22:10:34.984063 Dram Type= 6, Freq= 0, CH_0, rank 0
3807 22:10:34.987275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3808 22:10:34.987330 ==
3809 22:10:34.990437 [Gating] SW mode calibration
3810 22:10:34.997038 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3811 22:10:35.000476 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3812 22:10:35.007255 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3813 22:10:35.010237 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3814 22:10:35.013655 0 5 8 | B1->B0 | 3333 3131 | 1 1 | (1 0) (0 0)
3815 22:10:35.020185 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3816 22:10:35.023562 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3817 22:10:35.026687 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3818 22:10:35.033655 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3819 22:10:35.036884 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3820 22:10:35.039963 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3821 22:10:35.046915 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3822 22:10:35.050088 0 6 8 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 0)
3823 22:10:35.053881 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3824 22:10:35.060120 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3825 22:10:35.063085 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3826 22:10:35.066766 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3827 22:10:35.073349 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3828 22:10:35.076762 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3829 22:10:35.080120 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3830 22:10:35.083285 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3831 22:10:35.089927 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3832 22:10:35.093600 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3833 22:10:35.096718 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3834 22:10:35.103597 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3835 22:10:35.106637 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3836 22:10:35.109847 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3837 22:10:35.116305 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3838 22:10:35.119777 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3839 22:10:35.123363 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3840 22:10:35.129695 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3841 22:10:35.133429 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3842 22:10:35.136604 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3843 22:10:35.143003 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3844 22:10:35.146491 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3845 22:10:35.149915 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3846 22:10:35.156686 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3847 22:10:35.159662 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3848 22:10:35.163057 Total UI for P1: 0, mck2ui 16
3849 22:10:35.166395 best dqsien dly found for B0: ( 0, 9, 8)
3850 22:10:35.170004 Total UI for P1: 0, mck2ui 16
3851 22:10:35.172998 best dqsien dly found for B1: ( 0, 9, 10)
3852 22:10:35.176480 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3853 22:10:35.179880 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3854 22:10:35.179947
3855 22:10:35.182931 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3856 22:10:35.186648 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3857 22:10:35.189932 [Gating] SW calibration Done
3858 22:10:35.189998 ==
3859 22:10:35.193031 Dram Type= 6, Freq= 0, CH_0, rank 0
3860 22:10:35.196329 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3861 22:10:35.200111 ==
3862 22:10:35.200185 RX Vref Scan: 0
3863 22:10:35.200238
3864 22:10:35.203107 RX Vref 0 -> 0, step: 1
3865 22:10:35.203167
3866 22:10:35.206443 RX Delay -230 -> 252, step: 16
3867 22:10:35.209434 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3868 22:10:35.212680 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3869 22:10:35.216386 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3870 22:10:35.222812 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3871 22:10:35.226212 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3872 22:10:35.229769 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3873 22:10:35.232803 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3874 22:10:35.236116 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3875 22:10:35.242981 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3876 22:10:35.246043 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3877 22:10:35.249396 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3878 22:10:35.252671 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3879 22:10:35.259563 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3880 22:10:35.262525 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3881 22:10:35.266067 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3882 22:10:35.269090 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3883 22:10:35.269191 ==
3884 22:10:35.272410 Dram Type= 6, Freq= 0, CH_0, rank 0
3885 22:10:35.279136 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3886 22:10:35.279274 ==
3887 22:10:35.279364 DQS Delay:
3888 22:10:35.282502 DQS0 = 0, DQS1 = 0
3889 22:10:35.282571 DQM Delay:
3890 22:10:35.282625 DQM0 = 38, DQM1 = 33
3891 22:10:35.285884 DQ Delay:
3892 22:10:35.289176 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3893 22:10:35.292539 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
3894 22:10:35.295735 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3895 22:10:35.298847 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3896 22:10:35.298948
3897 22:10:35.299025
3898 22:10:35.299098 ==
3899 22:10:35.302655 Dram Type= 6, Freq= 0, CH_0, rank 0
3900 22:10:35.305948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3901 22:10:35.306043 ==
3902 22:10:35.306117
3903 22:10:35.306184
3904 22:10:35.308856 TX Vref Scan disable
3905 22:10:35.308930 == TX Byte 0 ==
3906 22:10:35.315682 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3907 22:10:35.318785 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3908 22:10:35.322161 == TX Byte 1 ==
3909 22:10:35.325554 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3910 22:10:35.328958 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3911 22:10:35.329052 ==
3912 22:10:35.331943 Dram Type= 6, Freq= 0, CH_0, rank 0
3913 22:10:35.335508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3914 22:10:35.335578 ==
3915 22:10:35.338704
3916 22:10:35.338779
3917 22:10:35.338848 TX Vref Scan disable
3918 22:10:35.342517 == TX Byte 0 ==
3919 22:10:35.345454 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3920 22:10:35.352270 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3921 22:10:35.352351 == TX Byte 1 ==
3922 22:10:35.355932 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3923 22:10:35.362260 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3924 22:10:35.362335
3925 22:10:35.362388 [DATLAT]
3926 22:10:35.362434 Freq=600, CH0 RK0
3927 22:10:35.362481
3928 22:10:35.365639 DATLAT Default: 0x9
3929 22:10:35.365736 0, 0xFFFF, sum = 0
3930 22:10:35.368861 1, 0xFFFF, sum = 0
3931 22:10:35.372179 2, 0xFFFF, sum = 0
3932 22:10:35.372243 3, 0xFFFF, sum = 0
3933 22:10:35.375730 4, 0xFFFF, sum = 0
3934 22:10:35.375819 5, 0xFFFF, sum = 0
3935 22:10:35.378662 6, 0xFFFF, sum = 0
3936 22:10:35.378721 7, 0x0, sum = 1
3937 22:10:35.378769 8, 0x0, sum = 2
3938 22:10:35.382062 9, 0x0, sum = 3
3939 22:10:35.382125 10, 0x0, sum = 4
3940 22:10:35.385593 best_step = 8
3941 22:10:35.385680
3942 22:10:35.385750 ==
3943 22:10:35.388923 Dram Type= 6, Freq= 0, CH_0, rank 0
3944 22:10:35.391865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3945 22:10:35.391951 ==
3946 22:10:35.395487 RX Vref Scan: 1
3947 22:10:35.395547
3948 22:10:35.395594 RX Vref 0 -> 0, step: 1
3949 22:10:35.395638
3950 22:10:35.398655 RX Delay -195 -> 252, step: 8
3951 22:10:35.398724
3952 22:10:35.401937 Set Vref, RX VrefLevel [Byte0]: 52
3953 22:10:35.405472 [Byte1]: 48
3954 22:10:35.409539
3955 22:10:35.409595 Final RX Vref Byte 0 = 52 to rank0
3956 22:10:35.412741 Final RX Vref Byte 1 = 48 to rank0
3957 22:10:35.416371 Final RX Vref Byte 0 = 52 to rank1
3958 22:10:35.419494 Final RX Vref Byte 1 = 48 to rank1==
3959 22:10:35.422757 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 22:10:35.429291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3961 22:10:35.429366 ==
3962 22:10:35.429420 DQS Delay:
3963 22:10:35.429470 DQS0 = 0, DQS1 = 0
3964 22:10:35.432936 DQM Delay:
3965 22:10:35.432990 DQM0 = 39, DQM1 = 30
3966 22:10:35.435882 DQ Delay:
3967 22:10:35.439523 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3968 22:10:35.439584 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
3969 22:10:35.442699 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24
3970 22:10:35.449130 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3971 22:10:35.449187
3972 22:10:35.449231
3973 22:10:35.456070 [DQSOSCAuto] RK0, (LSB)MR18= 0x5656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3974 22:10:35.459050 CH0 RK0: MR19=808, MR18=5656
3975 22:10:35.465853 CH0_RK0: MR19=0x808, MR18=0x5656, DQSOSC=393, MR23=63, INC=169, DEC=113
3976 22:10:35.465926
3977 22:10:35.469464 ----->DramcWriteLeveling(PI) begin...
3978 22:10:35.469528 ==
3979 22:10:35.472732 Dram Type= 6, Freq= 0, CH_0, rank 1
3980 22:10:35.475727 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3981 22:10:35.475786 ==
3982 22:10:35.479369 Write leveling (Byte 0): 30 => 30
3983 22:10:35.482684 Write leveling (Byte 1): 30 => 30
3984 22:10:35.486074 DramcWriteLeveling(PI) end<-----
3985 22:10:35.486139
3986 22:10:35.486202 ==
3987 22:10:35.490032 Dram Type= 6, Freq= 0, CH_0, rank 1
3988 22:10:35.492843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3989 22:10:35.492898 ==
3990 22:10:35.496278 [Gating] SW mode calibration
3991 22:10:35.502621 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3992 22:10:35.509203 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3993 22:10:35.512296 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 22:10:35.515845 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3995 22:10:35.522305 0 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
3996 22:10:35.525903 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3997 22:10:35.528971 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 22:10:35.535734 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 22:10:35.538916 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 22:10:35.542719 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 22:10:35.549083 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 22:10:35.552157 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 22:10:35.555404 0 6 8 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
4004 22:10:35.562076 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4005 22:10:35.565276 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 22:10:35.568914 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 22:10:35.575448 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 22:10:35.578664 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 22:10:35.581893 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 22:10:35.588477 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 22:10:35.591877 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4012 22:10:35.595474 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4013 22:10:35.601940 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 22:10:35.605095 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:10:35.608510 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 22:10:35.615319 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 22:10:35.618485 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 22:10:35.621576 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 22:10:35.628353 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 22:10:35.631611 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 22:10:35.635105 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 22:10:35.641496 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 22:10:35.644838 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 22:10:35.648192 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 22:10:35.654784 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 22:10:35.658049 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 22:10:35.661477 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4028 22:10:35.667943 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4029 22:10:35.668009 Total UI for P1: 0, mck2ui 16
4030 22:10:35.674685 best dqsien dly found for B0: ( 0, 9, 8)
4031 22:10:35.677881 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 22:10:35.680762 Total UI for P1: 0, mck2ui 16
4033 22:10:35.684463 best dqsien dly found for B1: ( 0, 9, 10)
4034 22:10:35.687730 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4035 22:10:35.691142 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4036 22:10:35.691228
4037 22:10:35.694335 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4038 22:10:35.698190 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4039 22:10:35.701135 [Gating] SW calibration Done
4040 22:10:35.701196 ==
4041 22:10:35.704462 Dram Type= 6, Freq= 0, CH_0, rank 1
4042 22:10:35.707866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4043 22:10:35.711111 ==
4044 22:10:35.711166 RX Vref Scan: 0
4045 22:10:35.711211
4046 22:10:35.714422 RX Vref 0 -> 0, step: 1
4047 22:10:35.714476
4048 22:10:35.717399 RX Delay -230 -> 252, step: 16
4049 22:10:35.720632 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4050 22:10:35.723980 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4051 22:10:35.727356 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4052 22:10:35.734098 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4053 22:10:35.737802 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4054 22:10:35.740669 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4055 22:10:35.744239 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4056 22:10:35.747539 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4057 22:10:35.754198 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4058 22:10:35.757570 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4059 22:10:35.760568 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4060 22:10:35.764036 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4061 22:10:35.770589 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4062 22:10:35.773826 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4063 22:10:35.776985 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4064 22:10:35.780774 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4065 22:10:35.780841 ==
4066 22:10:35.783962 Dram Type= 6, Freq= 0, CH_0, rank 1
4067 22:10:35.790446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4068 22:10:35.790505 ==
4069 22:10:35.790551 DQS Delay:
4070 22:10:35.793697 DQS0 = 0, DQS1 = 0
4071 22:10:35.793763 DQM Delay:
4072 22:10:35.796728 DQM0 = 41, DQM1 = 33
4073 22:10:35.796785 DQ Delay:
4074 22:10:35.800371 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4075 22:10:35.803464 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4076 22:10:35.807173 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4077 22:10:35.810272 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4078 22:10:35.810328
4079 22:10:35.810373
4080 22:10:35.810416 ==
4081 22:10:35.813460 Dram Type= 6, Freq= 0, CH_0, rank 1
4082 22:10:35.816572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4083 22:10:35.816629 ==
4084 22:10:35.816679
4085 22:10:35.816729
4086 22:10:35.820233 TX Vref Scan disable
4087 22:10:35.823341 == TX Byte 0 ==
4088 22:10:35.826741 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4089 22:10:35.829912 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4090 22:10:35.833310 == TX Byte 1 ==
4091 22:10:35.836539 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4092 22:10:35.840018 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4093 22:10:35.840072 ==
4094 22:10:35.843099 Dram Type= 6, Freq= 0, CH_0, rank 1
4095 22:10:35.846753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4096 22:10:35.850054 ==
4097 22:10:35.850147
4098 22:10:35.850193
4099 22:10:35.850235 TX Vref Scan disable
4100 22:10:35.853661 == TX Byte 0 ==
4101 22:10:35.857129 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4102 22:10:35.863864 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4103 22:10:35.863940 == TX Byte 1 ==
4104 22:10:35.867377 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4105 22:10:35.873884 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4106 22:10:35.873959
4107 22:10:35.874012 [DATLAT]
4108 22:10:35.874058 Freq=600, CH0 RK1
4109 22:10:35.874104
4110 22:10:35.877201 DATLAT Default: 0x8
4111 22:10:35.877288 0, 0xFFFF, sum = 0
4112 22:10:35.880656 1, 0xFFFF, sum = 0
4113 22:10:35.883537 2, 0xFFFF, sum = 0
4114 22:10:35.883611 3, 0xFFFF, sum = 0
4115 22:10:35.886911 4, 0xFFFF, sum = 0
4116 22:10:35.886984 5, 0xFFFF, sum = 0
4117 22:10:35.890425 6, 0xFFFF, sum = 0
4118 22:10:35.890587 7, 0x0, sum = 1
4119 22:10:35.890666 8, 0x0, sum = 2
4120 22:10:35.893739 9, 0x0, sum = 3
4121 22:10:35.893828 10, 0x0, sum = 4
4122 22:10:35.896686 best_step = 8
4123 22:10:35.896750
4124 22:10:35.896799 ==
4125 22:10:35.899964 Dram Type= 6, Freq= 0, CH_0, rank 1
4126 22:10:35.903585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4127 22:10:35.903673 ==
4128 22:10:35.906698 RX Vref Scan: 0
4129 22:10:35.906760
4130 22:10:35.906823 RX Vref 0 -> 0, step: 1
4131 22:10:35.906876
4132 22:10:35.909986 RX Delay -195 -> 252, step: 8
4133 22:10:35.917405 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4134 22:10:35.920835 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4135 22:10:35.924245 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4136 22:10:35.927543 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4137 22:10:35.933818 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4138 22:10:35.937425 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4139 22:10:35.940632 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4140 22:10:35.943872 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4141 22:10:35.950801 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4142 22:10:35.953855 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4143 22:10:35.957246 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4144 22:10:35.960355 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4145 22:10:35.963823 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4146 22:10:35.970441 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4147 22:10:35.974208 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4148 22:10:35.977082 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4149 22:10:35.977139 ==
4150 22:10:35.980385 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 22:10:35.987346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4152 22:10:35.987408 ==
4153 22:10:35.987471 DQS Delay:
4154 22:10:35.987529 DQS0 = 0, DQS1 = 0
4155 22:10:35.990344 DQM Delay:
4156 22:10:35.990407 DQM0 = 41, DQM1 = 32
4157 22:10:35.993951 DQ Delay:
4158 22:10:35.996978 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =36
4159 22:10:35.997038 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4160 22:10:36.000181 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4161 22:10:36.007336 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4162 22:10:36.007404
4163 22:10:36.007467
4164 22:10:36.013746 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d6d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4165 22:10:36.017542 CH0 RK1: MR19=808, MR18=6D6D
4166 22:10:36.023788 CH0_RK1: MR19=0x808, MR18=0x6D6D, DQSOSC=389, MR23=63, INC=173, DEC=115
4167 22:10:36.026986 [RxdqsGatingPostProcess] freq 600
4168 22:10:36.030391 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4169 22:10:36.033692 Pre-setting of DQS Precalculation
4170 22:10:36.040555 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4171 22:10:36.040637 ==
4172 22:10:36.043525 Dram Type= 6, Freq= 0, CH_1, rank 0
4173 22:10:36.046688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4174 22:10:36.046762 ==
4175 22:10:36.053431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4176 22:10:36.056835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4177 22:10:36.061281 [CA 0] Center 35 (5~66) winsize 62
4178 22:10:36.064314 [CA 1] Center 35 (5~66) winsize 62
4179 22:10:36.067952 [CA 2] Center 33 (3~64) winsize 62
4180 22:10:36.070910 [CA 3] Center 33 (3~64) winsize 62
4181 22:10:36.074480 [CA 4] Center 33 (2~64) winsize 63
4182 22:10:36.077436 [CA 5] Center 33 (2~64) winsize 63
4183 22:10:36.077493
4184 22:10:36.081085 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4185 22:10:36.081140
4186 22:10:36.084100 [CATrainingPosCal] consider 1 rank data
4187 22:10:36.087689 u2DelayCellTimex100 = 270/100 ps
4188 22:10:36.090636 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4189 22:10:36.097334 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4190 22:10:36.101115 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4191 22:10:36.104222 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4192 22:10:36.107618 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4193 22:10:36.110643 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4194 22:10:36.110706
4195 22:10:36.114054 CA PerBit enable=1, Macro0, CA PI delay=33
4196 22:10:36.114121
4197 22:10:36.117176 [CBTSetCACLKResult] CA Dly = 33
4198 22:10:36.117235 CS Dly: 4 (0~35)
4199 22:10:36.120432 ==
4200 22:10:36.123847 Dram Type= 6, Freq= 0, CH_1, rank 1
4201 22:10:36.127241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4202 22:10:36.127297 ==
4203 22:10:36.134049 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4204 22:10:36.137145 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4205 22:10:36.141719 [CA 0] Center 35 (5~66) winsize 62
4206 22:10:36.144436 [CA 1] Center 34 (4~65) winsize 62
4207 22:10:36.147776 [CA 2] Center 33 (3~64) winsize 62
4208 22:10:36.150865 [CA 3] Center 33 (3~64) winsize 62
4209 22:10:36.154380 [CA 4] Center 33 (2~64) winsize 63
4210 22:10:36.157712 [CA 5] Center 33 (2~64) winsize 63
4211 22:10:36.157770
4212 22:10:36.160740 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4213 22:10:36.160798
4214 22:10:36.164017 [CATrainingPosCal] consider 2 rank data
4215 22:10:36.167457 u2DelayCellTimex100 = 270/100 ps
4216 22:10:36.171136 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4217 22:10:36.177563 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4218 22:10:36.181102 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4219 22:10:36.184344 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4220 22:10:36.187420 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4221 22:10:36.190731 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4222 22:10:36.190786
4223 22:10:36.194207 CA PerBit enable=1, Macro0, CA PI delay=33
4224 22:10:36.194264
4225 22:10:36.197520 [CBTSetCACLKResult] CA Dly = 33
4226 22:10:36.197582 CS Dly: 4 (0~36)
4227 22:10:36.200589
4228 22:10:36.203989 ----->DramcWriteLeveling(PI) begin...
4229 22:10:36.204050 ==
4230 22:10:36.207330 Dram Type= 6, Freq= 0, CH_1, rank 0
4231 22:10:36.210981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4232 22:10:36.211036 ==
4233 22:10:36.214034 Write leveling (Byte 0): 27 => 27
4234 22:10:36.217396 Write leveling (Byte 1): 29 => 29
4235 22:10:36.220555 DramcWriteLeveling(PI) end<-----
4236 22:10:36.220612
4237 22:10:36.220661 ==
4238 22:10:36.224063 Dram Type= 6, Freq= 0, CH_1, rank 0
4239 22:10:36.227190 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4240 22:10:36.227257 ==
4241 22:10:36.231200 [Gating] SW mode calibration
4242 22:10:36.237268 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4243 22:10:36.244443 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4244 22:10:36.247187 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 22:10:36.251189 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 1)
4246 22:10:36.257037 0 5 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 1) (0 0)
4247 22:10:36.260859 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 22:10:36.263843 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 22:10:36.267518 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 22:10:36.273823 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 22:10:36.277038 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 22:10:36.280731 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 22:10:36.287075 0 6 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4254 22:10:36.290541 0 6 8 | B1->B0 | 3b3b 4444 | 0 0 | (1 1) (0 0)
4255 22:10:36.293803 0 6 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4256 22:10:36.300395 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 22:10:36.304162 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 22:10:36.307234 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 22:10:36.313734 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 22:10:36.317561 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 22:10:36.320645 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 22:10:36.327295 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4263 22:10:36.330572 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 22:10:36.333687 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 22:10:36.340889 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 22:10:36.343961 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 22:10:36.347169 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 22:10:36.353721 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 22:10:36.357223 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 22:10:36.360513 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 22:10:36.366815 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 22:10:36.370190 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 22:10:36.373723 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 22:10:36.380336 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 22:10:36.383491 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 22:10:36.386734 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 22:10:36.393221 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 22:10:36.396868 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4279 22:10:36.400041 Total UI for P1: 0, mck2ui 16
4280 22:10:36.403728 best dqsien dly found for B0: ( 0, 9, 6)
4281 22:10:36.407141 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 22:10:36.410369 Total UI for P1: 0, mck2ui 16
4283 22:10:36.413309 best dqsien dly found for B1: ( 0, 9, 8)
4284 22:10:36.416509 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4285 22:10:36.420108 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4286 22:10:36.420167
4287 22:10:36.423326 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4288 22:10:36.426547 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4289 22:10:36.430194 [Gating] SW calibration Done
4290 22:10:36.430249 ==
4291 22:10:36.433149 Dram Type= 6, Freq= 0, CH_1, rank 0
4292 22:10:36.440096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4293 22:10:36.440156 ==
4294 22:10:36.440202 RX Vref Scan: 0
4295 22:10:36.440245
4296 22:10:36.443870 RX Vref 0 -> 0, step: 1
4297 22:10:36.443926
4298 22:10:36.446641 RX Delay -230 -> 252, step: 16
4299 22:10:36.450036 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4300 22:10:36.453455 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4301 22:10:36.456671 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4302 22:10:36.463398 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4303 22:10:36.466444 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4304 22:10:36.469879 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4305 22:10:36.473030 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4306 22:10:36.476384 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4307 22:10:36.483122 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4308 22:10:36.486503 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4309 22:10:36.490000 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4310 22:10:36.493592 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4311 22:10:36.499928 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4312 22:10:36.503149 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4313 22:10:36.506308 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4314 22:10:36.510057 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4315 22:10:36.513137 ==
4316 22:10:36.513212 Dram Type= 6, Freq= 0, CH_1, rank 0
4317 22:10:36.519874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4318 22:10:36.519950 ==
4319 22:10:36.520004 DQS Delay:
4320 22:10:36.523449 DQS0 = 0, DQS1 = 0
4321 22:10:36.523525 DQM Delay:
4322 22:10:36.526282 DQM0 = 41, DQM1 = 34
4323 22:10:36.526387 DQ Delay:
4324 22:10:36.529522 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4325 22:10:36.533049 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4326 22:10:36.536268 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4327 22:10:36.539429 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4328 22:10:36.539504
4329 22:10:36.539557
4330 22:10:36.539603 ==
4331 22:10:36.542720 Dram Type= 6, Freq= 0, CH_1, rank 0
4332 22:10:36.546118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4333 22:10:36.546195 ==
4334 22:10:36.546249
4335 22:10:36.546310
4336 22:10:36.549245 TX Vref Scan disable
4337 22:10:36.552709 == TX Byte 0 ==
4338 22:10:36.555999 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4339 22:10:36.559628 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4340 22:10:36.562941 == TX Byte 1 ==
4341 22:10:36.565698 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4342 22:10:36.569075 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4343 22:10:36.569166 ==
4344 22:10:36.572805 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 22:10:36.578950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4346 22:10:36.579026 ==
4347 22:10:36.579080
4348 22:10:36.579126
4349 22:10:36.579170 TX Vref Scan disable
4350 22:10:36.583577 == TX Byte 0 ==
4351 22:10:36.586682 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4352 22:10:36.593070 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4353 22:10:36.593146 == TX Byte 1 ==
4354 22:10:36.596532 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4355 22:10:36.600048 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4356 22:10:36.603424
4357 22:10:36.603500 [DATLAT]
4358 22:10:36.603553 Freq=600, CH1 RK0
4359 22:10:36.603600
4360 22:10:36.606533 DATLAT Default: 0x9
4361 22:10:36.606623 0, 0xFFFF, sum = 0
4362 22:10:36.609756 1, 0xFFFF, sum = 0
4363 22:10:36.609829 2, 0xFFFF, sum = 0
4364 22:10:36.613270 3, 0xFFFF, sum = 0
4365 22:10:36.616276 4, 0xFFFF, sum = 0
4366 22:10:36.616347 5, 0xFFFF, sum = 0
4367 22:10:36.619981 6, 0xFFFF, sum = 0
4368 22:10:36.620038 7, 0x0, sum = 1
4369 22:10:36.620086 8, 0x0, sum = 2
4370 22:10:36.622925 9, 0x0, sum = 3
4371 22:10:36.622996 10, 0x0, sum = 4
4372 22:10:36.626639 best_step = 8
4373 22:10:36.626693
4374 22:10:36.626738 ==
4375 22:10:36.629635 Dram Type= 6, Freq= 0, CH_1, rank 0
4376 22:10:36.632860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4377 22:10:36.632917 ==
4378 22:10:36.636212 RX Vref Scan: 1
4379 22:10:36.636277
4380 22:10:36.636332 RX Vref 0 -> 0, step: 1
4381 22:10:36.636388
4382 22:10:36.639706 RX Delay -195 -> 252, step: 8
4383 22:10:36.639769
4384 22:10:36.642952 Set Vref, RX VrefLevel [Byte0]: 53
4385 22:10:36.646179 [Byte1]: 50
4386 22:10:36.650152
4387 22:10:36.650212 Final RX Vref Byte 0 = 53 to rank0
4388 22:10:36.653789 Final RX Vref Byte 1 = 50 to rank0
4389 22:10:36.656789 Final RX Vref Byte 0 = 53 to rank1
4390 22:10:36.660063 Final RX Vref Byte 1 = 50 to rank1==
4391 22:10:36.663842 Dram Type= 6, Freq= 0, CH_1, rank 0
4392 22:10:36.670718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4393 22:10:36.670783 ==
4394 22:10:36.670843 DQS Delay:
4395 22:10:36.670897 DQS0 = 0, DQS1 = 0
4396 22:10:36.673796 DQM Delay:
4397 22:10:36.673850 DQM0 = 37, DQM1 = 30
4398 22:10:36.676913 DQ Delay:
4399 22:10:36.679943 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4400 22:10:36.683776 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4401 22:10:36.686659 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4402 22:10:36.690026 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4403 22:10:36.690086
4404 22:10:36.690132
4405 22:10:36.696849 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f7f, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4406 22:10:36.699945 CH1 RK0: MR19=808, MR18=7F7F
4407 22:10:36.707066 CH1_RK0: MR19=0x808, MR18=0x7F7F, DQSOSC=386, MR23=63, INC=176, DEC=117
4408 22:10:36.707135
4409 22:10:36.710130 ----->DramcWriteLeveling(PI) begin...
4410 22:10:36.710189 ==
4411 22:10:36.713450 Dram Type= 6, Freq= 0, CH_1, rank 1
4412 22:10:36.716547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4413 22:10:36.716604 ==
4414 22:10:36.720208 Write leveling (Byte 0): 29 => 29
4415 22:10:36.723324 Write leveling (Byte 1): 27 => 27
4416 22:10:36.726649 DramcWriteLeveling(PI) end<-----
4417 22:10:36.726705
4418 22:10:36.726751 ==
4419 22:10:36.729856 Dram Type= 6, Freq= 0, CH_1, rank 1
4420 22:10:36.733453 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4421 22:10:36.733523 ==
4422 22:10:36.736439 [Gating] SW mode calibration
4423 22:10:36.743245 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4424 22:10:36.750031 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4425 22:10:36.753521 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 22:10:36.759993 0 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4427 22:10:36.763039 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4428 22:10:36.766497 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 22:10:36.773159 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 22:10:36.776639 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 22:10:36.779321 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 22:10:36.786128 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 22:10:36.789277 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 22:10:36.792938 0 6 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4435 22:10:36.799202 0 6 8 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
4436 22:10:36.802969 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 22:10:36.805791 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 22:10:36.809260 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 22:10:36.816043 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 22:10:36.819498 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 22:10:36.822694 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 22:10:36.829377 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4443 22:10:36.832534 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4444 22:10:36.836085 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 22:10:36.842515 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 22:10:36.845951 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 22:10:36.848950 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 22:10:36.855741 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 22:10:36.859149 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 22:10:36.862377 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:10:36.869338 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 22:10:36.872243 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 22:10:36.875879 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 22:10:36.882195 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 22:10:36.885622 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 22:10:36.888758 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 22:10:36.895561 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 22:10:36.898872 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4459 22:10:36.902164 Total UI for P1: 0, mck2ui 16
4460 22:10:36.905744 best dqsien dly found for B0: ( 0, 9, 2)
4461 22:10:36.908580 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4462 22:10:36.916113 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 22:10:36.916194 Total UI for P1: 0, mck2ui 16
4464 22:10:36.921762 best dqsien dly found for B1: ( 0, 9, 6)
4465 22:10:36.925265 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4466 22:10:36.928364 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4467 22:10:36.928442
4468 22:10:36.932172 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4469 22:10:36.935030 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4470 22:10:36.938470 [Gating] SW calibration Done
4471 22:10:36.938555 ==
4472 22:10:36.941643 Dram Type= 6, Freq= 0, CH_1, rank 1
4473 22:10:36.945327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4474 22:10:36.945413 ==
4475 22:10:36.948314 RX Vref Scan: 0
4476 22:10:36.948391
4477 22:10:36.948463 RX Vref 0 -> 0, step: 1
4478 22:10:36.948525
4479 22:10:36.951966 RX Delay -230 -> 252, step: 16
4480 22:10:36.958297 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4481 22:10:36.961616 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4482 22:10:36.964687 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4483 22:10:36.968498 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4484 22:10:36.971667 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4485 22:10:36.978568 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4486 22:10:36.981635 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4487 22:10:36.985427 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4488 22:10:36.988610 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4489 22:10:36.995387 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4490 22:10:36.998161 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4491 22:10:37.001632 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4492 22:10:37.004838 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4493 22:10:37.007968 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4494 22:10:37.014665 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4495 22:10:37.018534 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4496 22:10:37.018611 ==
4497 22:10:37.021353 Dram Type= 6, Freq= 0, CH_1, rank 1
4498 22:10:37.024866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4499 22:10:37.024951 ==
4500 22:10:37.027865 DQS Delay:
4501 22:10:37.027945 DQS0 = 0, DQS1 = 0
4502 22:10:37.031285 DQM Delay:
4503 22:10:37.031362 DQM0 = 41, DQM1 = 34
4504 22:10:37.031433 DQ Delay:
4505 22:10:37.034680 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4506 22:10:37.037832 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4507 22:10:37.041212 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4508 22:10:37.044484 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4509 22:10:37.044558
4510 22:10:37.044611
4511 22:10:37.048095 ==
4512 22:10:37.048162 Dram Type= 6, Freq= 0, CH_1, rank 1
4513 22:10:37.054305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4514 22:10:37.054366 ==
4515 22:10:37.054413
4516 22:10:37.054458
4517 22:10:37.057862 TX Vref Scan disable
4518 22:10:37.057933 == TX Byte 0 ==
4519 22:10:37.061525 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4520 22:10:37.067555 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4521 22:10:37.067621 == TX Byte 1 ==
4522 22:10:37.071353 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4523 22:10:37.077822 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4524 22:10:37.077898 ==
4525 22:10:37.081100 Dram Type= 6, Freq= 0, CH_1, rank 1
4526 22:10:37.084375 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4527 22:10:37.084430 ==
4528 22:10:37.084476
4529 22:10:37.084521
4530 22:10:37.087650 TX Vref Scan disable
4531 22:10:37.091444 == TX Byte 0 ==
4532 22:10:37.094401 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4533 22:10:37.097795 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4534 22:10:37.100700 == TX Byte 1 ==
4535 22:10:37.104081 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4536 22:10:37.107658 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4537 22:10:37.107724
4538 22:10:37.110878 [DATLAT]
4539 22:10:37.110946 Freq=600, CH1 RK1
4540 22:10:37.110994
4541 22:10:37.114314 DATLAT Default: 0x8
4542 22:10:37.114367 0, 0xFFFF, sum = 0
4543 22:10:37.117650 1, 0xFFFF, sum = 0
4544 22:10:37.117707 2, 0xFFFF, sum = 0
4545 22:10:37.121029 3, 0xFFFF, sum = 0
4546 22:10:37.121089 4, 0xFFFF, sum = 0
4547 22:10:37.124212 5, 0xFFFF, sum = 0
4548 22:10:37.124270 6, 0xFFFF, sum = 0
4549 22:10:37.127372 7, 0x0, sum = 1
4550 22:10:37.127437 8, 0x0, sum = 2
4551 22:10:37.131115 9, 0x0, sum = 3
4552 22:10:37.131171 10, 0x0, sum = 4
4553 22:10:37.134240 best_step = 8
4554 22:10:37.134298
4555 22:10:37.134350 ==
4556 22:10:37.137198 Dram Type= 6, Freq= 0, CH_1, rank 1
4557 22:10:37.140550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4558 22:10:37.140615 ==
4559 22:10:37.140665 RX Vref Scan: 0
4560 22:10:37.140710
4561 22:10:37.143863 RX Vref 0 -> 0, step: 1
4562 22:10:37.143923
4563 22:10:37.147607 RX Delay -195 -> 252, step: 8
4564 22:10:37.153702 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4565 22:10:37.157540 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4566 22:10:37.160533 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4567 22:10:37.163711 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4568 22:10:37.170656 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4569 22:10:37.174133 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4570 22:10:37.176857 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4571 22:10:37.180492 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4572 22:10:37.183627 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4573 22:10:37.190458 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4574 22:10:37.193608 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4575 22:10:37.197050 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4576 22:10:37.200253 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4577 22:10:37.206847 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4578 22:10:37.210073 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4579 22:10:37.213430 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4580 22:10:37.213492 ==
4581 22:10:37.216894 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 22:10:37.223205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4583 22:10:37.223302 ==
4584 22:10:37.223398 DQS Delay:
4585 22:10:37.223476 DQS0 = 0, DQS1 = 0
4586 22:10:37.226809 DQM Delay:
4587 22:10:37.226866 DQM0 = 36, DQM1 = 29
4588 22:10:37.229874 DQ Delay:
4589 22:10:37.233521 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4590 22:10:37.233576 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4591 22:10:37.236661 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4592 22:10:37.243264 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4593 22:10:37.243333
4594 22:10:37.243381
4595 22:10:37.249863 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4596 22:10:37.253289 CH1 RK1: MR19=808, MR18=6161
4597 22:10:37.260018 CH1_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4598 22:10:37.263172 [RxdqsGatingPostProcess] freq 600
4599 22:10:37.266284 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4600 22:10:37.269650 Pre-setting of DQS Precalculation
4601 22:10:37.276181 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4602 22:10:37.282885 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4603 22:10:37.289740 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4604 22:10:37.289797
4605 22:10:37.289843
4606 22:10:37.292772 [Calibration Summary] 1200 Mbps
4607 22:10:37.292826 CH 0, Rank 0
4608 22:10:37.296504 SW Impedance : PASS
4609 22:10:37.299620 DUTY Scan : NO K
4610 22:10:37.299676 ZQ Calibration : PASS
4611 22:10:37.302700 Jitter Meter : NO K
4612 22:10:37.305991 CBT Training : PASS
4613 22:10:37.306052 Write leveling : PASS
4614 22:10:37.309435 RX DQS gating : PASS
4615 22:10:37.312807 RX DQ/DQS(RDDQC) : PASS
4616 22:10:37.312870 TX DQ/DQS : PASS
4617 22:10:37.316176 RX DATLAT : PASS
4618 22:10:37.319518 RX DQ/DQS(Engine): PASS
4619 22:10:37.319581 TX OE : NO K
4620 22:10:37.319629 All Pass.
4621 22:10:37.319674
4622 22:10:37.322615 CH 0, Rank 1
4623 22:10:37.326027 SW Impedance : PASS
4624 22:10:37.326102 DUTY Scan : NO K
4625 22:10:37.329097 ZQ Calibration : PASS
4626 22:10:37.329153 Jitter Meter : NO K
4627 22:10:37.332391 CBT Training : PASS
4628 22:10:37.336037 Write leveling : PASS
4629 22:10:37.336106 RX DQS gating : PASS
4630 22:10:37.338951 RX DQ/DQS(RDDQC) : PASS
4631 22:10:37.342704 TX DQ/DQS : PASS
4632 22:10:37.342771 RX DATLAT : PASS
4633 22:10:37.345692 RX DQ/DQS(Engine): PASS
4634 22:10:37.349259 TX OE : NO K
4635 22:10:37.349341 All Pass.
4636 22:10:37.349402
4637 22:10:37.349446 CH 1, Rank 0
4638 22:10:37.352780 SW Impedance : PASS
4639 22:10:37.355656 DUTY Scan : NO K
4640 22:10:37.355713 ZQ Calibration : PASS
4641 22:10:37.358791 Jitter Meter : NO K
4642 22:10:37.362482 CBT Training : PASS
4643 22:10:37.362540 Write leveling : PASS
4644 22:10:37.365511 RX DQS gating : PASS
4645 22:10:37.369161 RX DQ/DQS(RDDQC) : PASS
4646 22:10:37.369228 TX DQ/DQS : PASS
4647 22:10:37.372354 RX DATLAT : PASS
4648 22:10:37.375447 RX DQ/DQS(Engine): PASS
4649 22:10:37.375508 TX OE : NO K
4650 22:10:37.375560 All Pass.
4651 22:10:37.378754
4652 22:10:37.378810 CH 1, Rank 1
4653 22:10:37.382185 SW Impedance : PASS
4654 22:10:37.382241 DUTY Scan : NO K
4655 22:10:37.385404 ZQ Calibration : PASS
4656 22:10:37.385461 Jitter Meter : NO K
4657 22:10:37.388846 CBT Training : PASS
4658 22:10:37.392337 Write leveling : PASS
4659 22:10:37.392393 RX DQS gating : PASS
4660 22:10:37.395637 RX DQ/DQS(RDDQC) : PASS
4661 22:10:37.398894 TX DQ/DQS : PASS
4662 22:10:37.398949 RX DATLAT : PASS
4663 22:10:37.402570 RX DQ/DQS(Engine): PASS
4664 22:10:37.405521 TX OE : NO K
4665 22:10:37.405600 All Pass.
4666 22:10:37.405671
4667 22:10:37.409034 DramC Write-DBI off
4668 22:10:37.409110 PER_BANK_REFRESH: Hybrid Mode
4669 22:10:37.412557 TX_TRACKING: ON
4670 22:10:37.418733 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4671 22:10:37.425345 [FAST_K] Save calibration result to emmc
4672 22:10:37.428587 dramc_set_vcore_voltage set vcore to 662500
4673 22:10:37.428666 Read voltage for 933, 3
4674 22:10:37.432389 Vio18 = 0
4675 22:10:37.432474 Vcore = 662500
4676 22:10:37.432551 Vdram = 0
4677 22:10:37.435520 Vddq = 0
4678 22:10:37.435595 Vmddr = 0
4679 22:10:37.438572 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4680 22:10:37.445250 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4681 22:10:37.448797 MEM_TYPE=3, freq_sel=17
4682 22:10:37.452105 sv_algorithm_assistance_LP4_1600
4683 22:10:37.455394 ============ PULL DRAM RESETB DOWN ============
4684 22:10:37.458509 ========== PULL DRAM RESETB DOWN end =========
4685 22:10:37.465525 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4686 22:10:37.468517 ===================================
4687 22:10:37.468605 LPDDR4 DRAM CONFIGURATION
4688 22:10:37.471946 ===================================
4689 22:10:37.475182 EX_ROW_EN[0] = 0x0
4690 22:10:37.475258 EX_ROW_EN[1] = 0x0
4691 22:10:37.478447 LP4Y_EN = 0x0
4692 22:10:37.478523 WORK_FSP = 0x0
4693 22:10:37.482019 WL = 0x3
4694 22:10:37.482095 RL = 0x3
4695 22:10:37.485018 BL = 0x2
4696 22:10:37.485095 RPST = 0x0
4697 22:10:37.488655 RD_PRE = 0x0
4698 22:10:37.492080 WR_PRE = 0x1
4699 22:10:37.492155 WR_PST = 0x0
4700 22:10:37.495328 DBI_WR = 0x0
4701 22:10:37.495405 DBI_RD = 0x0
4702 22:10:37.498477 OTF = 0x1
4703 22:10:37.501671 ===================================
4704 22:10:37.505351 ===================================
4705 22:10:37.505429 ANA top config
4706 22:10:37.508543 ===================================
4707 22:10:37.512024 DLL_ASYNC_EN = 0
4708 22:10:37.512102 ALL_SLAVE_EN = 1
4709 22:10:37.515471 NEW_RANK_MODE = 1
4710 22:10:37.518473 DLL_IDLE_MODE = 1
4711 22:10:37.521653 LP45_APHY_COMB_EN = 1
4712 22:10:37.525333 TX_ODT_DIS = 1
4713 22:10:37.525424 NEW_8X_MODE = 1
4714 22:10:37.528393 ===================================
4715 22:10:37.531777 ===================================
4716 22:10:37.535034 data_rate = 1866
4717 22:10:37.538712 CKR = 1
4718 22:10:37.541641 DQ_P2S_RATIO = 8
4719 22:10:37.544800 ===================================
4720 22:10:37.548444 CA_P2S_RATIO = 8
4721 22:10:37.551937 DQ_CA_OPEN = 0
4722 22:10:37.552012 DQ_SEMI_OPEN = 0
4723 22:10:37.554794 CA_SEMI_OPEN = 0
4724 22:10:37.557997 CA_FULL_RATE = 0
4725 22:10:37.561539 DQ_CKDIV4_EN = 1
4726 22:10:37.564857 CA_CKDIV4_EN = 1
4727 22:10:37.568868 CA_PREDIV_EN = 0
4728 22:10:37.568945 PH8_DLY = 0
4729 22:10:37.571848 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4730 22:10:37.574600 DQ_AAMCK_DIV = 4
4731 22:10:37.577925 CA_AAMCK_DIV = 4
4732 22:10:37.581516 CA_ADMCK_DIV = 4
4733 22:10:37.584497 DQ_TRACK_CA_EN = 0
4734 22:10:37.584554 CA_PICK = 933
4735 22:10:37.588350 CA_MCKIO = 933
4736 22:10:37.591305 MCKIO_SEMI = 0
4737 22:10:37.594423 PLL_FREQ = 3732
4738 22:10:37.597956 DQ_UI_PI_RATIO = 32
4739 22:10:37.600988 CA_UI_PI_RATIO = 0
4740 22:10:37.604337 ===================================
4741 22:10:37.607876 ===================================
4742 22:10:37.611109 memory_type:LPDDR4
4743 22:10:37.611185 GP_NUM : 10
4744 22:10:37.614679 SRAM_EN : 1
4745 22:10:37.614754 MD32_EN : 0
4746 22:10:37.617757 ===================================
4747 22:10:37.620892 [ANA_INIT] >>>>>>>>>>>>>>
4748 22:10:37.624575 <<<<<< [CONFIGURE PHASE]: ANA_TX
4749 22:10:37.627673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4750 22:10:37.630714 ===================================
4751 22:10:37.634913 data_rate = 1866,PCW = 0X8f00
4752 22:10:37.637420 ===================================
4753 22:10:37.640935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4754 22:10:37.647589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4755 22:10:37.650725 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4756 22:10:37.657299 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4757 22:10:37.660880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4758 22:10:37.664227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4759 22:10:37.664285 [ANA_INIT] flow start
4760 22:10:37.667134 [ANA_INIT] PLL >>>>>>>>
4761 22:10:37.670580 [ANA_INIT] PLL <<<<<<<<
4762 22:10:37.670649 [ANA_INIT] MIDPI >>>>>>>>
4763 22:10:37.673848 [ANA_INIT] MIDPI <<<<<<<<
4764 22:10:37.677194 [ANA_INIT] DLL >>>>>>>>
4765 22:10:37.677262 [ANA_INIT] flow end
4766 22:10:37.683669 ============ LP4 DIFF to SE enter ============
4767 22:10:37.686864 ============ LP4 DIFF to SE exit ============
4768 22:10:37.690652 [ANA_INIT] <<<<<<<<<<<<<
4769 22:10:37.693509 [Flow] Enable top DCM control >>>>>
4770 22:10:37.697234 [Flow] Enable top DCM control <<<<<
4771 22:10:37.697292 Enable DLL master slave shuffle
4772 22:10:37.703548 ==============================================================
4773 22:10:37.706982 Gating Mode config
4774 22:10:37.710004 ==============================================================
4775 22:10:37.713533 Config description:
4776 22:10:37.723193 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4777 22:10:37.730011 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4778 22:10:37.733576 SELPH_MODE 0: By rank 1: By Phase
4779 22:10:37.739654 ==============================================================
4780 22:10:37.743417 GAT_TRACK_EN = 1
4781 22:10:37.746442 RX_GATING_MODE = 2
4782 22:10:37.749732 RX_GATING_TRACK_MODE = 2
4783 22:10:37.752810 SELPH_MODE = 1
4784 22:10:37.756397 PICG_EARLY_EN = 1
4785 22:10:37.756456 VALID_LAT_VALUE = 1
4786 22:10:37.763211 ==============================================================
4787 22:10:37.766316 Enter into Gating configuration >>>>
4788 22:10:37.769639 Exit from Gating configuration <<<<
4789 22:10:37.773028 Enter into DVFS_PRE_config >>>>>
4790 22:10:37.782976 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4791 22:10:37.786394 Exit from DVFS_PRE_config <<<<<
4792 22:10:37.789396 Enter into PICG configuration >>>>
4793 22:10:37.792835 Exit from PICG configuration <<<<
4794 22:10:37.796003 [RX_INPUT] configuration >>>>>
4795 22:10:37.799624 [RX_INPUT] configuration <<<<<
4796 22:10:37.806186 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4797 22:10:37.809673 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4798 22:10:37.815855 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4799 22:10:37.822549 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4800 22:10:37.829603 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4801 22:10:37.835727 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4802 22:10:37.839347 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4803 22:10:37.842250 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4804 22:10:37.845951 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4805 22:10:37.852556 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4806 22:10:37.855485 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4807 22:10:37.858847 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4808 22:10:37.862462 ===================================
4809 22:10:37.865759 LPDDR4 DRAM CONFIGURATION
4810 22:10:37.869402 ===================================
4811 22:10:37.869483 EX_ROW_EN[0] = 0x0
4812 22:10:37.872465 EX_ROW_EN[1] = 0x0
4813 22:10:37.875553 LP4Y_EN = 0x0
4814 22:10:37.875610 WORK_FSP = 0x0
4815 22:10:37.878690 WL = 0x3
4816 22:10:37.878763 RL = 0x3
4817 22:10:37.882340 BL = 0x2
4818 22:10:37.882410 RPST = 0x0
4819 22:10:37.885227 RD_PRE = 0x0
4820 22:10:37.885284 WR_PRE = 0x1
4821 22:10:37.888854 WR_PST = 0x0
4822 22:10:37.888912 DBI_WR = 0x0
4823 22:10:37.892303 DBI_RD = 0x0
4824 22:10:37.892381 OTF = 0x1
4825 22:10:37.895218 ===================================
4826 22:10:37.898838 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4827 22:10:37.905272 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4828 22:10:37.908467 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4829 22:10:37.911776 ===================================
4830 22:10:37.915542 LPDDR4 DRAM CONFIGURATION
4831 22:10:37.918632 ===================================
4832 22:10:37.918689 EX_ROW_EN[0] = 0x10
4833 22:10:37.922107 EX_ROW_EN[1] = 0x0
4834 22:10:37.925162 LP4Y_EN = 0x0
4835 22:10:37.925220 WORK_FSP = 0x0
4836 22:10:37.928271 WL = 0x3
4837 22:10:37.928349 RL = 0x3
4838 22:10:37.931720 BL = 0x2
4839 22:10:37.931807 RPST = 0x0
4840 22:10:37.935354 RD_PRE = 0x0
4841 22:10:37.935431 WR_PRE = 0x1
4842 22:10:37.938571 WR_PST = 0x0
4843 22:10:37.938674 DBI_WR = 0x0
4844 22:10:37.941850 DBI_RD = 0x0
4845 22:10:37.941906 OTF = 0x1
4846 22:10:37.945028 ===================================
4847 22:10:37.951918 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4848 22:10:37.956098 nWR fixed to 30
4849 22:10:37.959344 [ModeRegInit_LP4] CH0 RK0
4850 22:10:37.959406 [ModeRegInit_LP4] CH0 RK1
4851 22:10:37.962397 [ModeRegInit_LP4] CH1 RK0
4852 22:10:37.965843 [ModeRegInit_LP4] CH1 RK1
4853 22:10:37.965905 match AC timing 8
4854 22:10:37.972454 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4855 22:10:37.975693 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4856 22:10:37.979244 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4857 22:10:37.986019 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4858 22:10:37.989211 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4859 22:10:37.989266 ==
4860 22:10:37.992491 Dram Type= 6, Freq= 0, CH_0, rank 0
4861 22:10:37.995769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4862 22:10:37.995836 ==
4863 22:10:38.002319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4864 22:10:38.009182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4865 22:10:38.012341 [CA 0] Center 39 (8~70) winsize 63
4866 22:10:38.015432 [CA 1] Center 38 (8~69) winsize 62
4867 22:10:38.019041 [CA 2] Center 36 (6~67) winsize 62
4868 22:10:38.022397 [CA 3] Center 36 (5~67) winsize 63
4869 22:10:38.025700 [CA 4] Center 34 (4~65) winsize 62
4870 22:10:38.028751 [CA 5] Center 34 (4~65) winsize 62
4871 22:10:38.028815
4872 22:10:38.032623 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4873 22:10:38.032683
4874 22:10:38.035367 [CATrainingPosCal] consider 1 rank data
4875 22:10:38.038909 u2DelayCellTimex100 = 270/100 ps
4876 22:10:38.042098 CA0 delay=39 (8~70),Diff = 5 PI (31 cell)
4877 22:10:38.045239 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4878 22:10:38.048986 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4879 22:10:38.051768 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4880 22:10:38.055212 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4881 22:10:38.062221 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4882 22:10:38.062280
4883 22:10:38.065606 CA PerBit enable=1, Macro0, CA PI delay=34
4884 22:10:38.065671
4885 22:10:38.068415 [CBTSetCACLKResult] CA Dly = 34
4886 22:10:38.068474 CS Dly: 7 (0~38)
4887 22:10:38.068527 ==
4888 22:10:38.071748 Dram Type= 6, Freq= 0, CH_0, rank 1
4889 22:10:38.075213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4890 22:10:38.078484 ==
4891 22:10:38.081636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4892 22:10:38.088398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4893 22:10:38.091944 [CA 0] Center 38 (8~69) winsize 62
4894 22:10:38.095108 [CA 1] Center 38 (7~69) winsize 63
4895 22:10:38.098202 [CA 2] Center 36 (5~67) winsize 63
4896 22:10:38.101773 [CA 3] Center 35 (5~66) winsize 62
4897 22:10:38.104849 [CA 4] Center 34 (4~65) winsize 62
4898 22:10:38.108075 [CA 5] Center 34 (4~65) winsize 62
4899 22:10:38.108139
4900 22:10:38.111283 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4901 22:10:38.111342
4902 22:10:38.114879 [CATrainingPosCal] consider 2 rank data
4903 22:10:38.118486 u2DelayCellTimex100 = 270/100 ps
4904 22:10:38.121804 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4905 22:10:38.124823 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4906 22:10:38.128344 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4907 22:10:38.134890 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4908 22:10:38.138051 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4909 22:10:38.141614 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4910 22:10:38.141689
4911 22:10:38.144602 CA PerBit enable=1, Macro0, CA PI delay=34
4912 22:10:38.144678
4913 22:10:38.148323 [CBTSetCACLKResult] CA Dly = 34
4914 22:10:38.148411 CS Dly: 7 (0~39)
4915 22:10:38.148464
4916 22:10:38.151569 ----->DramcWriteLeveling(PI) begin...
4917 22:10:38.151645 ==
4918 22:10:38.155124 Dram Type= 6, Freq= 0, CH_0, rank 0
4919 22:10:38.161364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4920 22:10:38.161428 ==
4921 22:10:38.164541 Write leveling (Byte 0): 30 => 30
4922 22:10:38.168302 Write leveling (Byte 1): 29 => 29
4923 22:10:38.168360 DramcWriteLeveling(PI) end<-----
4924 22:10:38.168415
4925 22:10:38.171494 ==
4926 22:10:38.174878 Dram Type= 6, Freq= 0, CH_0, rank 0
4927 22:10:38.177786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4928 22:10:38.177851 ==
4929 22:10:38.181535 [Gating] SW mode calibration
4930 22:10:38.187704 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4931 22:10:38.191412 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4932 22:10:38.198225 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4933 22:10:38.201154 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4934 22:10:38.204443 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4935 22:10:38.211379 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4936 22:10:38.214500 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4937 22:10:38.217855 0 10 20 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 1)
4938 22:10:38.224512 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4939 22:10:38.227776 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4940 22:10:38.231001 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4941 22:10:38.237676 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4942 22:10:38.241123 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4943 22:10:38.244642 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4944 22:10:38.250854 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4945 22:10:38.254475 0 11 20 | B1->B0 | 2828 2b2b | 0 0 | (0 0) (0 0)
4946 22:10:38.257713 0 11 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4947 22:10:38.264289 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4948 22:10:38.267776 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4949 22:10:38.270991 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4950 22:10:38.277481 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4951 22:10:38.281232 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4952 22:10:38.284297 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4953 22:10:38.291036 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4954 22:10:38.294256 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4955 22:10:38.297592 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4956 22:10:38.300750 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4957 22:10:38.307496 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4958 22:10:38.310760 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4959 22:10:38.313951 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4960 22:10:38.320778 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4961 22:10:38.323983 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4962 22:10:38.327021 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4963 22:10:38.333712 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4964 22:10:38.337181 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4965 22:10:38.341108 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4966 22:10:38.346973 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4967 22:10:38.350370 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4968 22:10:38.353544 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4969 22:10:38.360421 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4970 22:10:38.363494 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4971 22:10:38.366943 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4972 22:10:38.370320 Total UI for P1: 0, mck2ui 16
4973 22:10:38.373948 best dqsien dly found for B0: ( 0, 14, 22)
4974 22:10:38.376818 Total UI for P1: 0, mck2ui 16
4975 22:10:38.380316 best dqsien dly found for B1: ( 0, 14, 24)
4976 22:10:38.383833 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4977 22:10:38.386674 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
4978 22:10:38.390167
4979 22:10:38.393549 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4980 22:10:38.396791 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
4981 22:10:38.400175 [Gating] SW calibration Done
4982 22:10:38.400262 ==
4983 22:10:38.403539 Dram Type= 6, Freq= 0, CH_0, rank 0
4984 22:10:38.406759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4985 22:10:38.406848 ==
4986 22:10:38.406926 RX Vref Scan: 0
4987 22:10:38.407006
4988 22:10:38.409936 RX Vref 0 -> 0, step: 1
4989 22:10:38.409997
4990 22:10:38.413771 RX Delay -80 -> 252, step: 8
4991 22:10:38.416718 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4992 22:10:38.419972 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
4993 22:10:38.426748 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4994 22:10:38.429924 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4995 22:10:38.433146 iDelay=208, Bit 4, Center 95 (-8 ~ 199) 208
4996 22:10:38.436487 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4997 22:10:38.440282 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4998 22:10:38.443339 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
4999 22:10:38.450182 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5000 22:10:38.452971 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5001 22:10:38.456485 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5002 22:10:38.460360 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5003 22:10:38.463295 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5004 22:10:38.469570 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5005 22:10:38.473205 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5006 22:10:38.476536 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5007 22:10:38.476592 ==
5008 22:10:38.479673 Dram Type= 6, Freq= 0, CH_0, rank 0
5009 22:10:38.483225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5010 22:10:38.483293 ==
5011 22:10:38.486535 DQS Delay:
5012 22:10:38.486603 DQS0 = 0, DQS1 = 0
5013 22:10:38.486648 DQM Delay:
5014 22:10:38.489714 DQM0 = 94, DQM1 = 85
5015 22:10:38.489791 DQ Delay:
5016 22:10:38.493179 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =91
5017 22:10:38.496172 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5018 22:10:38.499876 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5019 22:10:38.503090 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5020 22:10:38.503166
5021 22:10:38.503220
5022 22:10:38.503266 ==
5023 22:10:38.506382 Dram Type= 6, Freq= 0, CH_0, rank 0
5024 22:10:38.512901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5025 22:10:38.512978 ==
5026 22:10:38.513032
5027 22:10:38.513078
5028 22:10:38.516225 TX Vref Scan disable
5029 22:10:38.516301 == TX Byte 0 ==
5030 22:10:38.519399 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5031 22:10:38.526255 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5032 22:10:38.526338 == TX Byte 1 ==
5033 22:10:38.529291 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5034 22:10:38.536459 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5035 22:10:38.536535 ==
5036 22:10:38.539631 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 22:10:38.542690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5038 22:10:38.542767 ==
5039 22:10:38.542821
5040 22:10:38.542868
5041 22:10:38.546211 TX Vref Scan disable
5042 22:10:38.549235 == TX Byte 0 ==
5043 22:10:38.552972 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5044 22:10:38.555838 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5045 22:10:38.559429 == TX Byte 1 ==
5046 22:10:38.562911 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5047 22:10:38.566097 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5048 22:10:38.566173
5049 22:10:38.566226 [DATLAT]
5050 22:10:38.569367 Freq=933, CH0 RK0
5051 22:10:38.569451
5052 22:10:38.572501 DATLAT Default: 0xd
5053 22:10:38.572586 0, 0xFFFF, sum = 0
5054 22:10:38.576229 1, 0xFFFF, sum = 0
5055 22:10:38.576307 2, 0xFFFF, sum = 0
5056 22:10:38.579404 3, 0xFFFF, sum = 0
5057 22:10:38.579506 4, 0xFFFF, sum = 0
5058 22:10:38.583059 5, 0xFFFF, sum = 0
5059 22:10:38.583135 6, 0xFFFF, sum = 0
5060 22:10:38.586210 7, 0xFFFF, sum = 0
5061 22:10:38.586297 8, 0xFFFF, sum = 0
5062 22:10:38.589737 9, 0xFFFF, sum = 0
5063 22:10:38.589813 10, 0x0, sum = 1
5064 22:10:38.592609 11, 0x0, sum = 2
5065 22:10:38.592686 12, 0x0, sum = 3
5066 22:10:38.596141 13, 0x0, sum = 4
5067 22:10:38.596228 best_step = 11
5068 22:10:38.596281
5069 22:10:38.596327 ==
5070 22:10:38.599132 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 22:10:38.602490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5072 22:10:38.602566 ==
5073 22:10:38.605932 RX Vref Scan: 1
5074 22:10:38.606022
5075 22:10:38.609006 RX Vref 0 -> 0, step: 1
5076 22:10:38.609082
5077 22:10:38.609135 RX Delay -69 -> 252, step: 4
5078 22:10:38.612602
5079 22:10:38.612677 Set Vref, RX VrefLevel [Byte0]: 52
5080 22:10:38.615766 [Byte1]: 48
5081 22:10:38.620564
5082 22:10:38.620640 Final RX Vref Byte 0 = 52 to rank0
5083 22:10:38.623935 Final RX Vref Byte 1 = 48 to rank0
5084 22:10:38.627302 Final RX Vref Byte 0 = 52 to rank1
5085 22:10:38.630860 Final RX Vref Byte 1 = 48 to rank1==
5086 22:10:38.634064 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 22:10:38.640877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5088 22:10:38.640961 ==
5089 22:10:38.641020 DQS Delay:
5090 22:10:38.641072 DQS0 = 0, DQS1 = 0
5091 22:10:38.643898 DQM Delay:
5092 22:10:38.643973 DQM0 = 96, DQM1 = 86
5093 22:10:38.647504 DQ Delay:
5094 22:10:38.650635 DQ0 =92, DQ1 =96, DQ2 =96, DQ3 =92
5095 22:10:38.654286 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =104
5096 22:10:38.657496 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =78
5097 22:10:38.660648 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5098 22:10:38.660723
5099 22:10:38.660775
5100 22:10:38.667121 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5101 22:10:38.670879 CH0 RK0: MR19=505, MR18=2323
5102 22:10:38.677382 CH0_RK0: MR19=0x505, MR18=0x2323, DQSOSC=410, MR23=63, INC=64, DEC=42
5103 22:10:38.677469
5104 22:10:38.680417 ----->DramcWriteLeveling(PI) begin...
5105 22:10:38.680492 ==
5106 22:10:38.684330 Dram Type= 6, Freq= 0, CH_0, rank 1
5107 22:10:38.687205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5108 22:10:38.687279 ==
5109 22:10:38.690484 Write leveling (Byte 0): 27 => 27
5110 22:10:38.693781 Write leveling (Byte 1): 25 => 25
5111 22:10:38.696918 DramcWriteLeveling(PI) end<-----
5112 22:10:38.696993
5113 22:10:38.697046 ==
5114 22:10:38.700570 Dram Type= 6, Freq= 0, CH_0, rank 1
5115 22:10:38.703751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5116 22:10:38.703829 ==
5117 22:10:38.707126 [Gating] SW mode calibration
5118 22:10:38.713660 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5119 22:10:38.720627 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5120 22:10:38.723600 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 22:10:38.730571 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 22:10:38.733676 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 22:10:38.736753 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 22:10:38.743668 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5125 22:10:38.746759 0 10 20 | B1->B0 | 3131 3030 | 1 0 | (1 1) (0 0)
5126 22:10:38.750126 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5127 22:10:38.756538 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 22:10:38.760346 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 22:10:38.763415 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 22:10:38.770050 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 22:10:38.773433 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 22:10:38.776643 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 22:10:38.780302 0 11 20 | B1->B0 | 2c2c 3838 | 0 0 | (0 0) (0 0)
5134 22:10:38.786643 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 22:10:38.790107 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 22:10:38.793228 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 22:10:38.800082 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 22:10:38.803660 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 22:10:38.806595 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 22:10:38.812964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 22:10:38.816481 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 22:10:38.820217 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 22:10:38.826285 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 22:10:38.829991 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 22:10:38.833105 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 22:10:38.839727 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 22:10:38.843029 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 22:10:38.846567 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 22:10:38.853225 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 22:10:38.856332 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 22:10:38.859880 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 22:10:38.866327 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 22:10:38.870109 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 22:10:38.873191 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 22:10:38.879500 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 22:10:38.882867 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 22:10:38.886025 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5158 22:10:38.892670 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5159 22:10:38.896399 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 22:10:38.899465 Total UI for P1: 0, mck2ui 16
5161 22:10:38.902733 best dqsien dly found for B0: ( 0, 14, 22)
5162 22:10:38.906187 Total UI for P1: 0, mck2ui 16
5163 22:10:38.909402 best dqsien dly found for B1: ( 0, 14, 22)
5164 22:10:38.912505 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5165 22:10:38.915925 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5166 22:10:38.916000
5167 22:10:38.919593 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5168 22:10:38.922595 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5169 22:10:38.926241 [Gating] SW calibration Done
5170 22:10:38.926316 ==
5171 22:10:38.929054 Dram Type= 6, Freq= 0, CH_0, rank 1
5172 22:10:38.932799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5173 22:10:38.935998 ==
5174 22:10:38.936073 RX Vref Scan: 0
5175 22:10:38.936127
5176 22:10:38.939216 RX Vref 0 -> 0, step: 1
5177 22:10:38.939309
5178 22:10:38.939376 RX Delay -80 -> 252, step: 8
5179 22:10:38.946142 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5180 22:10:38.949522 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5181 22:10:38.953143 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5182 22:10:38.956221 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5183 22:10:38.959309 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5184 22:10:38.963082 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5185 22:10:38.969432 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5186 22:10:38.972819 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5187 22:10:38.975956 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5188 22:10:38.979215 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5189 22:10:38.983119 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5190 22:10:38.989692 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5191 22:10:38.992852 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5192 22:10:38.996018 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5193 22:10:38.999525 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5194 22:10:39.002641 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5195 22:10:39.002718 ==
5196 22:10:39.006050 Dram Type= 6, Freq= 0, CH_0, rank 1
5197 22:10:39.012572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5198 22:10:39.012649 ==
5199 22:10:39.012704 DQS Delay:
5200 22:10:39.015710 DQS0 = 0, DQS1 = 0
5201 22:10:39.015788 DQM Delay:
5202 22:10:39.015841 DQM0 = 96, DQM1 = 85
5203 22:10:39.019194 DQ Delay:
5204 22:10:39.022354 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87
5205 22:10:39.025881 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5206 22:10:39.029000 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =79
5207 22:10:39.032038 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =95
5208 22:10:39.032114
5209 22:10:39.032167
5210 22:10:39.032213 ==
5211 22:10:39.035637 Dram Type= 6, Freq= 0, CH_0, rank 1
5212 22:10:39.038999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5213 22:10:39.039075 ==
5214 22:10:39.039129
5215 22:10:39.039175
5216 22:10:39.042427 TX Vref Scan disable
5217 22:10:39.045665 == TX Byte 0 ==
5218 22:10:39.049124 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5219 22:10:39.052290 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5220 22:10:39.055153 == TX Byte 1 ==
5221 22:10:39.058581 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5222 22:10:39.061779 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5223 22:10:39.061852 ==
5224 22:10:39.065080 Dram Type= 6, Freq= 0, CH_0, rank 1
5225 22:10:39.068717 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5226 22:10:39.071614 ==
5227 22:10:39.071697
5228 22:10:39.071754
5229 22:10:39.071805 TX Vref Scan disable
5230 22:10:39.075249 == TX Byte 0 ==
5231 22:10:39.078595 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5232 22:10:39.085535 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5233 22:10:39.085608 == TX Byte 1 ==
5234 22:10:39.088512 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5235 22:10:39.095289 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5236 22:10:39.095361
5237 22:10:39.095413 [DATLAT]
5238 22:10:39.095459 Freq=933, CH0 RK1
5239 22:10:39.095503
5240 22:10:39.098760 DATLAT Default: 0xb
5241 22:10:39.098835 0, 0xFFFF, sum = 0
5242 22:10:39.102528 1, 0xFFFF, sum = 0
5243 22:10:39.105478 2, 0xFFFF, sum = 0
5244 22:10:39.105555 3, 0xFFFF, sum = 0
5245 22:10:39.108582 4, 0xFFFF, sum = 0
5246 22:10:39.108658 5, 0xFFFF, sum = 0
5247 22:10:39.111871 6, 0xFFFF, sum = 0
5248 22:10:39.111948 7, 0xFFFF, sum = 0
5249 22:10:39.115350 8, 0xFFFF, sum = 0
5250 22:10:39.115427 9, 0xFFFF, sum = 0
5251 22:10:39.118687 10, 0x0, sum = 1
5252 22:10:39.118763 11, 0x0, sum = 2
5253 22:10:39.121916 12, 0x0, sum = 3
5254 22:10:39.121991 13, 0x0, sum = 4
5255 22:10:39.122044 best_step = 11
5256 22:10:39.122090
5257 22:10:39.125502 ==
5258 22:10:39.128758 Dram Type= 6, Freq= 0, CH_0, rank 1
5259 22:10:39.131965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5260 22:10:39.132041 ==
5261 22:10:39.132095 RX Vref Scan: 0
5262 22:10:39.132142
5263 22:10:39.135424 RX Vref 0 -> 0, step: 1
5264 22:10:39.135500
5265 22:10:39.138849 RX Delay -77 -> 252, step: 4
5266 22:10:39.141862 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5267 22:10:39.148752 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5268 22:10:39.151910 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5269 22:10:39.155120 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184
5270 22:10:39.158809 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5271 22:10:39.161824 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5272 22:10:39.165595 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5273 22:10:39.171520 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5274 22:10:39.174914 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5275 22:10:39.178248 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5276 22:10:39.181955 iDelay=203, Bit 10, Center 90 (-1 ~ 182) 184
5277 22:10:39.185011 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5278 22:10:39.191850 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5279 22:10:39.195025 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5280 22:10:39.198281 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5281 22:10:39.201472 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5282 22:10:39.201549 ==
5283 22:10:39.204783 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 22:10:39.208275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5285 22:10:39.211709 ==
5286 22:10:39.211784 DQS Delay:
5287 22:10:39.211838 DQS0 = 0, DQS1 = 0
5288 22:10:39.214862 DQM Delay:
5289 22:10:39.214937 DQM0 = 97, DQM1 = 86
5290 22:10:39.219359 DQ Delay:
5291 22:10:39.221566 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =90
5292 22:10:39.224552 DQ4 =100, DQ5 =90, DQ6 =106, DQ7 =108
5293 22:10:39.227985 DQ8 =76, DQ9 =72, DQ10 =90, DQ11 =78
5294 22:10:39.231319 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5295 22:10:39.231394
5296 22:10:39.231447
5297 22:10:39.237751 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5298 22:10:39.241481 CH0 RK1: MR19=505, MR18=2A2A
5299 22:10:39.247915 CH0_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5300 22:10:39.251380 [RxdqsGatingPostProcess] freq 933
5301 22:10:39.254549 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5302 22:10:39.257492 Pre-setting of DQS Precalculation
5303 22:10:39.264268 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5304 22:10:39.264342 ==
5305 22:10:39.268081 Dram Type= 6, Freq= 0, CH_1, rank 0
5306 22:10:39.271084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5307 22:10:39.271170 ==
5308 22:10:39.277565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5309 22:10:39.284256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5310 22:10:39.287348 [CA 0] Center 37 (6~68) winsize 63
5311 22:10:39.290661 [CA 1] Center 37 (6~68) winsize 63
5312 22:10:39.294301 [CA 2] Center 34 (4~65) winsize 62
5313 22:10:39.297596 [CA 3] Center 34 (4~65) winsize 62
5314 22:10:39.300729 [CA 4] Center 33 (2~64) winsize 63
5315 22:10:39.300804 [CA 5] Center 33 (2~64) winsize 63
5316 22:10:39.304146
5317 22:10:39.307161 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5318 22:10:39.307249
5319 22:10:39.310626 [CATrainingPosCal] consider 1 rank data
5320 22:10:39.313725 u2DelayCellTimex100 = 270/100 ps
5321 22:10:39.317366 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5322 22:10:39.320501 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5323 22:10:39.324107 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5324 22:10:39.327206 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5325 22:10:39.330344 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5326 22:10:39.333749 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5327 22:10:39.333826
5328 22:10:39.337504 CA PerBit enable=1, Macro0, CA PI delay=33
5329 22:10:39.340456
5330 22:10:39.340530 [CBTSetCACLKResult] CA Dly = 33
5331 22:10:39.343776 CS Dly: 5 (0~36)
5332 22:10:39.343851 ==
5333 22:10:39.347041 Dram Type= 6, Freq= 0, CH_1, rank 1
5334 22:10:39.350543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5335 22:10:39.350618 ==
5336 22:10:39.357007 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5337 22:10:39.363958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5338 22:10:39.366983 [CA 0] Center 37 (6~68) winsize 63
5339 22:10:39.370388 [CA 1] Center 37 (6~68) winsize 63
5340 22:10:39.374165 [CA 2] Center 34 (4~65) winsize 62
5341 22:10:39.377276 [CA 3] Center 34 (4~65) winsize 62
5342 22:10:39.380307 [CA 4] Center 33 (2~64) winsize 63
5343 22:10:39.383610 [CA 5] Center 32 (2~63) winsize 62
5344 22:10:39.383683
5345 22:10:39.386613 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5346 22:10:39.386687
5347 22:10:39.390465 [CATrainingPosCal] consider 2 rank data
5348 22:10:39.393402 u2DelayCellTimex100 = 270/100 ps
5349 22:10:39.396887 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5350 22:10:39.400162 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5351 22:10:39.403475 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5352 22:10:39.407423 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5353 22:10:39.410238 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5354 22:10:39.413286 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5355 22:10:39.413369
5356 22:10:39.419871 CA PerBit enable=1, Macro0, CA PI delay=32
5357 22:10:39.419948
5358 22:10:39.423430 [CBTSetCACLKResult] CA Dly = 32
5359 22:10:39.423503 CS Dly: 5 (0~37)
5360 22:10:39.423555
5361 22:10:39.426519 ----->DramcWriteLeveling(PI) begin...
5362 22:10:39.426637 ==
5363 22:10:39.430136 Dram Type= 6, Freq= 0, CH_1, rank 0
5364 22:10:39.433578 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5365 22:10:39.433653 ==
5366 22:10:39.436622 Write leveling (Byte 0): 26 => 26
5367 22:10:39.439989 Write leveling (Byte 1): 26 => 26
5368 22:10:39.443147 DramcWriteLeveling(PI) end<-----
5369 22:10:39.443220
5370 22:10:39.443272 ==
5371 22:10:39.447100 Dram Type= 6, Freq= 0, CH_1, rank 0
5372 22:10:39.453128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5373 22:10:39.453203 ==
5374 22:10:39.453256 [Gating] SW mode calibration
5375 22:10:39.463156 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5376 22:10:39.466445 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5377 22:10:39.469480 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 22:10:39.476567 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 22:10:39.480316 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 22:10:39.483581 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 22:10:39.489925 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5382 22:10:39.492886 0 10 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
5383 22:10:39.496250 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 22:10:39.502945 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 22:10:39.506399 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 22:10:39.509979 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 22:10:39.516360 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 22:10:39.519896 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 22:10:39.523122 0 11 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
5390 22:10:39.529604 0 11 20 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
5391 22:10:39.533109 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5392 22:10:39.536258 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 22:10:39.542875 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 22:10:39.546684 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 22:10:39.549652 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 22:10:39.556403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 22:10:39.559457 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5398 22:10:39.562731 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5399 22:10:39.569832 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 22:10:39.572639 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 22:10:39.575840 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 22:10:39.582559 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 22:10:39.585727 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 22:10:39.589320 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 22:10:39.595690 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 22:10:39.599136 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 22:10:39.602515 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 22:10:39.609365 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 22:10:39.612478 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 22:10:39.616235 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 22:10:39.619178 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 22:10:39.625864 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 22:10:39.629217 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 22:10:39.632567 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5415 22:10:39.638896 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 22:10:39.642372 Total UI for P1: 0, mck2ui 16
5417 22:10:39.645866 best dqsien dly found for B0: ( 0, 14, 20)
5418 22:10:39.649149 Total UI for P1: 0, mck2ui 16
5419 22:10:39.652699 best dqsien dly found for B1: ( 0, 14, 20)
5420 22:10:39.655725 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5421 22:10:39.658876 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5422 22:10:39.658965
5423 22:10:39.662157 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5424 22:10:39.665721 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5425 22:10:39.668943 [Gating] SW calibration Done
5426 22:10:39.669018 ==
5427 22:10:39.672074 Dram Type= 6, Freq= 0, CH_1, rank 0
5428 22:10:39.675993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5429 22:10:39.676074 ==
5430 22:10:39.678560 RX Vref Scan: 0
5431 22:10:39.678651
5432 22:10:39.682366 RX Vref 0 -> 0, step: 1
5433 22:10:39.682426
5434 22:10:39.682482 RX Delay -80 -> 252, step: 8
5435 22:10:39.688559 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5436 22:10:39.692081 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5437 22:10:39.695443 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5438 22:10:39.698473 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5439 22:10:39.702040 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5440 22:10:39.705005 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5441 22:10:39.712103 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5442 22:10:39.714769 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5443 22:10:39.718343 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5444 22:10:39.721521 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5445 22:10:39.724773 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5446 22:10:39.731649 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5447 22:10:39.735146 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5448 22:10:39.738370 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5449 22:10:39.741610 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5450 22:10:39.744678 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5451 22:10:39.744736 ==
5452 22:10:39.748101 Dram Type= 6, Freq= 0, CH_1, rank 0
5453 22:10:39.754970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5454 22:10:39.755032 ==
5455 22:10:39.755084 DQS Delay:
5456 22:10:39.757997 DQS0 = 0, DQS1 = 0
5457 22:10:39.758053 DQM Delay:
5458 22:10:39.758099 DQM0 = 95, DQM1 = 87
5459 22:10:39.761247 DQ Delay:
5460 22:10:39.764815 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5461 22:10:39.767986 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5462 22:10:39.771251 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79
5463 22:10:39.774731 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5464 22:10:39.774799
5465 22:10:39.774861
5466 22:10:39.774905 ==
5467 22:10:39.778269 Dram Type= 6, Freq= 0, CH_1, rank 0
5468 22:10:39.781575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5469 22:10:39.781632 ==
5470 22:10:39.781678
5471 22:10:39.781732
5472 22:10:39.784919 TX Vref Scan disable
5473 22:10:39.788256 == TX Byte 0 ==
5474 22:10:39.791544 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5475 22:10:39.794556 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5476 22:10:39.797857 == TX Byte 1 ==
5477 22:10:39.801261 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5478 22:10:39.804876 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5479 22:10:39.804931 ==
5480 22:10:39.808055 Dram Type= 6, Freq= 0, CH_1, rank 0
5481 22:10:39.812051 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5482 22:10:39.814602 ==
5483 22:10:39.814672
5484 22:10:39.814717
5485 22:10:39.814761 TX Vref Scan disable
5486 22:10:39.818066 == TX Byte 0 ==
5487 22:10:39.821401 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5488 22:10:39.828181 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5489 22:10:39.828237 == TX Byte 1 ==
5490 22:10:39.831267 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5491 22:10:39.837932 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5492 22:10:39.837987
5493 22:10:39.838037 [DATLAT]
5494 22:10:39.838086 Freq=933, CH1 RK0
5495 22:10:39.838130
5496 22:10:39.841119 DATLAT Default: 0xd
5497 22:10:39.841227 0, 0xFFFF, sum = 0
5498 22:10:39.844876 1, 0xFFFF, sum = 0
5499 22:10:39.844939 2, 0xFFFF, sum = 0
5500 22:10:39.848097 3, 0xFFFF, sum = 0
5501 22:10:39.851269 4, 0xFFFF, sum = 0
5502 22:10:39.851340 5, 0xFFFF, sum = 0
5503 22:10:39.854372 6, 0xFFFF, sum = 0
5504 22:10:39.854430 7, 0xFFFF, sum = 0
5505 22:10:39.857773 8, 0xFFFF, sum = 0
5506 22:10:39.857831 9, 0xFFFF, sum = 0
5507 22:10:39.861021 10, 0x0, sum = 1
5508 22:10:39.861081 11, 0x0, sum = 2
5509 22:10:39.864612 12, 0x0, sum = 3
5510 22:10:39.864672 13, 0x0, sum = 4
5511 22:10:39.864719 best_step = 11
5512 22:10:39.864765
5513 22:10:39.867951 ==
5514 22:10:39.871022 Dram Type= 6, Freq= 0, CH_1, rank 0
5515 22:10:39.874642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5516 22:10:39.874707 ==
5517 22:10:39.874763 RX Vref Scan: 1
5518 22:10:39.874810
5519 22:10:39.877909 RX Vref 0 -> 0, step: 1
5520 22:10:39.877965
5521 22:10:39.880974 RX Delay -69 -> 252, step: 4
5522 22:10:39.881030
5523 22:10:39.884381 Set Vref, RX VrefLevel [Byte0]: 53
5524 22:10:39.887733 [Byte1]: 50
5525 22:10:39.887809
5526 22:10:39.890787 Final RX Vref Byte 0 = 53 to rank0
5527 22:10:39.894382 Final RX Vref Byte 1 = 50 to rank0
5528 22:10:39.897884 Final RX Vref Byte 0 = 53 to rank1
5529 22:10:39.901134 Final RX Vref Byte 1 = 50 to rank1==
5530 22:10:39.904323 Dram Type= 6, Freq= 0, CH_1, rank 0
5531 22:10:39.907824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5532 22:10:39.910904 ==
5533 22:10:39.910981 DQS Delay:
5534 22:10:39.911034 DQS0 = 0, DQS1 = 0
5535 22:10:39.914457 DQM Delay:
5536 22:10:39.914529 DQM0 = 94, DQM1 = 88
5537 22:10:39.917256 DQ Delay:
5538 22:10:39.920699 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5539 22:10:39.920775 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =92
5540 22:10:39.924150 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5541 22:10:39.930900 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5542 22:10:39.931004
5543 22:10:39.931056
5544 22:10:39.937142 [DQSOSCAuto] RK0, (LSB)MR18= 0x3333, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5545 22:10:39.940748 CH1 RK0: MR19=505, MR18=3333
5546 22:10:39.947315 CH1_RK0: MR19=0x505, MR18=0x3333, DQSOSC=405, MR23=63, INC=66, DEC=44
5547 22:10:39.947437
5548 22:10:39.950795 ----->DramcWriteLeveling(PI) begin...
5549 22:10:39.950859 ==
5550 22:10:39.953751 Dram Type= 6, Freq= 0, CH_1, rank 1
5551 22:10:39.956988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5552 22:10:39.957056 ==
5553 22:10:39.960363 Write leveling (Byte 0): 25 => 25
5554 22:10:39.964113 Write leveling (Byte 1): 24 => 24
5555 22:10:39.967250 DramcWriteLeveling(PI) end<-----
5556 22:10:39.967321
5557 22:10:39.967369 ==
5558 22:10:39.970316 Dram Type= 6, Freq= 0, CH_1, rank 1
5559 22:10:39.973401 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5560 22:10:39.973462 ==
5561 22:10:39.977250 [Gating] SW mode calibration
5562 22:10:39.983508 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5563 22:10:39.990410 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5564 22:10:39.993530 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 22:10:39.997033 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 22:10:40.004141 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 22:10:40.007137 0 10 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5568 22:10:40.010278 0 10 16 | B1->B0 | 3434 2525 | 1 1 | (1 0) (1 1)
5569 22:10:40.017244 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5570 22:10:40.020353 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 22:10:40.023415 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 22:10:40.030603 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 22:10:40.033456 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 22:10:40.037018 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 22:10:40.043741 0 11 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5576 22:10:40.047148 0 11 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
5577 22:10:40.050162 0 11 20 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
5578 22:10:40.056700 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 22:10:40.060629 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 22:10:40.063482 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 22:10:40.070097 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 22:10:40.073467 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 22:10:40.076818 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5584 22:10:40.083017 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5585 22:10:40.086738 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5586 22:10:40.089806 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 22:10:40.096450 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 22:10:40.099681 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 22:10:40.103024 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 22:10:40.109789 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 22:10:40.112649 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 22:10:40.116153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 22:10:40.122645 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 22:10:40.126288 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 22:10:40.129379 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 22:10:40.136591 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 22:10:40.139562 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 22:10:40.142676 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 22:10:40.149515 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 22:10:40.152735 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5601 22:10:40.156016 Total UI for P1: 0, mck2ui 16
5602 22:10:40.159653 best dqsien dly found for B0: ( 0, 14, 14)
5603 22:10:40.162734 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 22:10:40.166327 Total UI for P1: 0, mck2ui 16
5605 22:10:40.169253 best dqsien dly found for B1: ( 0, 14, 16)
5606 22:10:40.172522 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5607 22:10:40.176066 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5608 22:10:40.176140
5609 22:10:40.182795 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5610 22:10:40.185982 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5611 22:10:40.186056 [Gating] SW calibration Done
5612 22:10:40.189319 ==
5613 22:10:40.189408 Dram Type= 6, Freq= 0, CH_1, rank 1
5614 22:10:40.195953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5615 22:10:40.196027 ==
5616 22:10:40.196080 RX Vref Scan: 0
5617 22:10:40.196127
5618 22:10:40.199214 RX Vref 0 -> 0, step: 1
5619 22:10:40.199289
5620 22:10:40.202453 RX Delay -80 -> 252, step: 8
5621 22:10:40.205806 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5622 22:10:40.209174 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5623 22:10:40.212834 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5624 22:10:40.219292 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5625 22:10:40.222638 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5626 22:10:40.225639 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5627 22:10:40.229030 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5628 22:10:40.232341 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5629 22:10:40.235871 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5630 22:10:40.242208 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5631 22:10:40.245840 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5632 22:10:40.248935 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5633 22:10:40.252073 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5634 22:10:40.255831 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5635 22:10:40.262701 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5636 22:10:40.265674 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5637 22:10:40.265739 ==
5638 22:10:40.268974 Dram Type= 6, Freq= 0, CH_1, rank 1
5639 22:10:40.272428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5640 22:10:40.272498 ==
5641 22:10:40.272560 DQS Delay:
5642 22:10:40.275649 DQS0 = 0, DQS1 = 0
5643 22:10:40.275715 DQM Delay:
5644 22:10:40.278657 DQM0 = 95, DQM1 = 87
5645 22:10:40.278713 DQ Delay:
5646 22:10:40.281962 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91
5647 22:10:40.285474 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5648 22:10:40.288643 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5649 22:10:40.291822 DQ12 =99, DQ13 =99, DQ14 =91, DQ15 =95
5650 22:10:40.291928
5651 22:10:40.291980
5652 22:10:40.292027 ==
5653 22:10:40.295478 Dram Type= 6, Freq= 0, CH_1, rank 1
5654 22:10:40.301702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5655 22:10:40.301776 ==
5656 22:10:40.301830
5657 22:10:40.301876
5658 22:10:40.301918 TX Vref Scan disable
5659 22:10:40.305311 == TX Byte 0 ==
5660 22:10:40.308414 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5661 22:10:40.311997 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5662 22:10:40.314927 == TX Byte 1 ==
5663 22:10:40.318445 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5664 22:10:40.325229 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5665 22:10:40.325311 ==
5666 22:10:40.328290 Dram Type= 6, Freq= 0, CH_1, rank 1
5667 22:10:40.331658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5668 22:10:40.331732 ==
5669 22:10:40.331784
5670 22:10:40.331829
5671 22:10:40.335093 TX Vref Scan disable
5672 22:10:40.335175 == TX Byte 0 ==
5673 22:10:40.341937 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5674 22:10:40.345118 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5675 22:10:40.345196 == TX Byte 1 ==
5676 22:10:40.351474 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5677 22:10:40.355124 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5678 22:10:40.355198
5679 22:10:40.355249 [DATLAT]
5680 22:10:40.358160 Freq=933, CH1 RK1
5681 22:10:40.358236
5682 22:10:40.358289 DATLAT Default: 0xb
5683 22:10:40.361560 0, 0xFFFF, sum = 0
5684 22:10:40.361636 1, 0xFFFF, sum = 0
5685 22:10:40.365238 2, 0xFFFF, sum = 0
5686 22:10:40.365321 3, 0xFFFF, sum = 0
5687 22:10:40.368515 4, 0xFFFF, sum = 0
5688 22:10:40.368590 5, 0xFFFF, sum = 0
5689 22:10:40.371373 6, 0xFFFF, sum = 0
5690 22:10:40.374710 7, 0xFFFF, sum = 0
5691 22:10:40.374787 8, 0xFFFF, sum = 0
5692 22:10:40.378682 9, 0xFFFF, sum = 0
5693 22:10:40.378759 10, 0x0, sum = 1
5694 22:10:40.381618 11, 0x0, sum = 2
5695 22:10:40.381696 12, 0x0, sum = 3
5696 22:10:40.381751 13, 0x0, sum = 4
5697 22:10:40.384824 best_step = 11
5698 22:10:40.384900
5699 22:10:40.384952 ==
5700 22:10:40.388079 Dram Type= 6, Freq= 0, CH_1, rank 1
5701 22:10:40.391146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5702 22:10:40.391229 ==
5703 22:10:40.394536 RX Vref Scan: 0
5704 22:10:40.394611
5705 22:10:40.394665 RX Vref 0 -> 0, step: 1
5706 22:10:40.398166
5707 22:10:40.398240 RX Delay -69 -> 252, step: 4
5708 22:10:40.405528 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5709 22:10:40.408856 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5710 22:10:40.412272 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5711 22:10:40.415175 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5712 22:10:40.419260 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5713 22:10:40.425338 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5714 22:10:40.429012 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5715 22:10:40.432016 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5716 22:10:40.435229 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5717 22:10:40.438405 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5718 22:10:40.441793 iDelay=203, Bit 10, Center 90 (-1 ~ 182) 184
5719 22:10:40.449031 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5720 22:10:40.451833 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5721 22:10:40.455184 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5722 22:10:40.458758 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5723 22:10:40.461795 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5724 22:10:40.461875 ==
5725 22:10:40.464958 Dram Type= 6, Freq= 0, CH_1, rank 1
5726 22:10:40.471782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5727 22:10:40.471859 ==
5728 22:10:40.471915 DQS Delay:
5729 22:10:40.475664 DQS0 = 0, DQS1 = 0
5730 22:10:40.475740 DQM Delay:
5731 22:10:40.475793 DQM0 = 95, DQM1 = 87
5732 22:10:40.478617 DQ Delay:
5733 22:10:40.481781 DQ0 =96, DQ1 =92, DQ2 =88, DQ3 =92
5734 22:10:40.484965 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5735 22:10:40.488958 DQ8 =74, DQ9 =76, DQ10 =90, DQ11 =80
5736 22:10:40.491855 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
5737 22:10:40.491931
5738 22:10:40.491984
5739 22:10:40.498883 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5740 22:10:40.501784 CH1 RK1: MR19=505, MR18=2525
5741 22:10:40.508214 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5742 22:10:40.511713 [RxdqsGatingPostProcess] freq 933
5743 22:10:40.514759 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5744 22:10:40.518744 Pre-setting of DQS Precalculation
5745 22:10:40.525010 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5746 22:10:40.531889 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5747 22:10:40.538557 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5748 22:10:40.538632
5749 22:10:40.538684
5750 22:10:40.541863 [Calibration Summary] 1866 Mbps
5751 22:10:40.544857 CH 0, Rank 0
5752 22:10:40.544932 SW Impedance : PASS
5753 22:10:40.548196 DUTY Scan : NO K
5754 22:10:40.548283 ZQ Calibration : PASS
5755 22:10:40.551434 Jitter Meter : NO K
5756 22:10:40.554836 CBT Training : PASS
5757 22:10:40.554913 Write leveling : PASS
5758 22:10:40.558154 RX DQS gating : PASS
5759 22:10:40.561312 RX DQ/DQS(RDDQC) : PASS
5760 22:10:40.561396 TX DQ/DQS : PASS
5761 22:10:40.564914 RX DATLAT : PASS
5762 22:10:40.568147 RX DQ/DQS(Engine): PASS
5763 22:10:40.568221 TX OE : NO K
5764 22:10:40.571359 All Pass.
5765 22:10:40.571434
5766 22:10:40.571488 CH 0, Rank 1
5767 22:10:40.575090 SW Impedance : PASS
5768 22:10:40.575176 DUTY Scan : NO K
5769 22:10:40.578149 ZQ Calibration : PASS
5770 22:10:40.581173 Jitter Meter : NO K
5771 22:10:40.581249 CBT Training : PASS
5772 22:10:40.584900 Write leveling : PASS
5773 22:10:40.588266 RX DQS gating : PASS
5774 22:10:40.588342 RX DQ/DQS(RDDQC) : PASS
5775 22:10:40.591396 TX DQ/DQS : PASS
5776 22:10:40.594567 RX DATLAT : PASS
5777 22:10:40.594642 RX DQ/DQS(Engine): PASS
5778 22:10:40.598093 TX OE : NO K
5779 22:10:40.598168 All Pass.
5780 22:10:40.598221
5781 22:10:40.601055 CH 1, Rank 0
5782 22:10:40.601132 SW Impedance : PASS
5783 22:10:40.604492 DUTY Scan : NO K
5784 22:10:40.604567 ZQ Calibration : PASS
5785 22:10:40.607879 Jitter Meter : NO K
5786 22:10:40.611132 CBT Training : PASS
5787 22:10:40.611209 Write leveling : PASS
5788 22:10:40.614483 RX DQS gating : PASS
5789 22:10:40.617868 RX DQ/DQS(RDDQC) : PASS
5790 22:10:40.617959 TX DQ/DQS : PASS
5791 22:10:40.620840 RX DATLAT : PASS
5792 22:10:40.624345 RX DQ/DQS(Engine): PASS
5793 22:10:40.624421 TX OE : NO K
5794 22:10:40.627752 All Pass.
5795 22:10:40.627838
5796 22:10:40.627895 CH 1, Rank 1
5797 22:10:40.630917 SW Impedance : PASS
5798 22:10:40.630994 DUTY Scan : NO K
5799 22:10:40.634561 ZQ Calibration : PASS
5800 22:10:40.637645 Jitter Meter : NO K
5801 22:10:40.637719 CBT Training : PASS
5802 22:10:40.641070 Write leveling : PASS
5803 22:10:40.644089 RX DQS gating : PASS
5804 22:10:40.644163 RX DQ/DQS(RDDQC) : PASS
5805 22:10:40.647414 TX DQ/DQS : PASS
5806 22:10:40.650890 RX DATLAT : PASS
5807 22:10:40.650969 RX DQ/DQS(Engine): PASS
5808 22:10:40.654289 TX OE : NO K
5809 22:10:40.654367 All Pass.
5810 22:10:40.654422
5811 22:10:40.657243 DramC Write-DBI off
5812 22:10:40.660685 PER_BANK_REFRESH: Hybrid Mode
5813 22:10:40.660767 TX_TRACKING: ON
5814 22:10:40.670676 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5815 22:10:40.674335 [FAST_K] Save calibration result to emmc
5816 22:10:40.677433 dramc_set_vcore_voltage set vcore to 650000
5817 22:10:40.680439 Read voltage for 400, 6
5818 22:10:40.680512 Vio18 = 0
5819 22:10:40.680566 Vcore = 650000
5820 22:10:40.683903 Vdram = 0
5821 22:10:40.683977 Vddq = 0
5822 22:10:40.684029 Vmddr = 0
5823 22:10:40.690567 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5824 22:10:40.693789 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5825 22:10:40.697278 MEM_TYPE=3, freq_sel=20
5826 22:10:40.700512 sv_algorithm_assistance_LP4_800
5827 22:10:40.703634 ============ PULL DRAM RESETB DOWN ============
5828 22:10:40.706861 ========== PULL DRAM RESETB DOWN end =========
5829 22:10:40.713743 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5830 22:10:40.716962 ===================================
5831 22:10:40.717038 LPDDR4 DRAM CONFIGURATION
5832 22:10:40.720454 ===================================
5833 22:10:40.723956 EX_ROW_EN[0] = 0x0
5834 22:10:40.727374 EX_ROW_EN[1] = 0x0
5835 22:10:40.727449 LP4Y_EN = 0x0
5836 22:10:40.730337 WORK_FSP = 0x0
5837 22:10:40.730412 WL = 0x2
5838 22:10:40.733980 RL = 0x2
5839 22:10:40.734054 BL = 0x2
5840 22:10:40.737033 RPST = 0x0
5841 22:10:40.737109 RD_PRE = 0x0
5842 22:10:40.740373 WR_PRE = 0x1
5843 22:10:40.740448 WR_PST = 0x0
5844 22:10:40.743552 DBI_WR = 0x0
5845 22:10:40.743628 DBI_RD = 0x0
5846 22:10:40.747264 OTF = 0x1
5847 22:10:40.750155 ===================================
5848 22:10:40.753665 ===================================
5849 22:10:40.753739 ANA top config
5850 22:10:40.757308 ===================================
5851 22:10:40.760078 DLL_ASYNC_EN = 0
5852 22:10:40.763403 ALL_SLAVE_EN = 1
5853 22:10:40.766846 NEW_RANK_MODE = 1
5854 22:10:40.766923 DLL_IDLE_MODE = 1
5855 22:10:40.770063 LP45_APHY_COMB_EN = 1
5856 22:10:40.773818 TX_ODT_DIS = 1
5857 22:10:40.776787 NEW_8X_MODE = 1
5858 22:10:40.780315 ===================================
5859 22:10:40.783396 ===================================
5860 22:10:40.786658 data_rate = 800
5861 22:10:40.786733 CKR = 1
5862 22:10:40.790075 DQ_P2S_RATIO = 4
5863 22:10:40.793136 ===================================
5864 22:10:40.796482 CA_P2S_RATIO = 4
5865 22:10:40.800164 DQ_CA_OPEN = 0
5866 22:10:40.803289 DQ_SEMI_OPEN = 1
5867 22:10:40.806872 CA_SEMI_OPEN = 1
5868 22:10:40.806948 CA_FULL_RATE = 0
5869 22:10:40.810118 DQ_CKDIV4_EN = 0
5870 22:10:40.813158 CA_CKDIV4_EN = 1
5871 22:10:40.816906 CA_PREDIV_EN = 0
5872 22:10:40.819935 PH8_DLY = 0
5873 22:10:40.823078 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5874 22:10:40.823154 DQ_AAMCK_DIV = 0
5875 22:10:40.826372 CA_AAMCK_DIV = 0
5876 22:10:40.829885 CA_ADMCK_DIV = 4
5877 22:10:40.833331 DQ_TRACK_CA_EN = 0
5878 22:10:40.836868 CA_PICK = 800
5879 22:10:40.839468 CA_MCKIO = 400
5880 22:10:40.843312 MCKIO_SEMI = 400
5881 22:10:40.843391 PLL_FREQ = 3016
5882 22:10:40.846477 DQ_UI_PI_RATIO = 32
5883 22:10:40.849548 CA_UI_PI_RATIO = 32
5884 22:10:40.852694 ===================================
5885 22:10:40.856345 ===================================
5886 22:10:40.859393 memory_type:LPDDR4
5887 22:10:40.862829 GP_NUM : 10
5888 22:10:40.862904 SRAM_EN : 1
5889 22:10:40.866226 MD32_EN : 0
5890 22:10:40.869854 ===================================
5891 22:10:40.869929 [ANA_INIT] >>>>>>>>>>>>>>
5892 22:10:40.872650 <<<<<< [CONFIGURE PHASE]: ANA_TX
5893 22:10:40.875732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5894 22:10:40.879260 ===================================
5895 22:10:40.882449 data_rate = 800,PCW = 0X7400
5896 22:10:40.885734 ===================================
5897 22:10:40.888995 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5898 22:10:40.895780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5899 22:10:40.905875 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5900 22:10:40.912130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5901 22:10:40.915754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5902 22:10:40.919043 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5903 22:10:40.919119 [ANA_INIT] flow start
5904 22:10:40.922682 [ANA_INIT] PLL >>>>>>>>
5905 22:10:40.925454 [ANA_INIT] PLL <<<<<<<<
5906 22:10:40.925542 [ANA_INIT] MIDPI >>>>>>>>
5907 22:10:40.929386 [ANA_INIT] MIDPI <<<<<<<<
5908 22:10:40.932085 [ANA_INIT] DLL >>>>>>>>
5909 22:10:40.932161 [ANA_INIT] flow end
5910 22:10:40.938738 ============ LP4 DIFF to SE enter ============
5911 22:10:40.942220 ============ LP4 DIFF to SE exit ============
5912 22:10:40.945900 [ANA_INIT] <<<<<<<<<<<<<
5913 22:10:40.948732 [Flow] Enable top DCM control >>>>>
5914 22:10:40.952390 [Flow] Enable top DCM control <<<<<
5915 22:10:40.955450 Enable DLL master slave shuffle
5916 22:10:40.958571 ==============================================================
5917 22:10:40.962198 Gating Mode config
5918 22:10:40.965623 ==============================================================
5919 22:10:40.968425 Config description:
5920 22:10:40.978583 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5921 22:10:40.985070 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5922 22:10:40.988180 SELPH_MODE 0: By rank 1: By Phase
5923 22:10:40.995002 ==============================================================
5924 22:10:40.998218 GAT_TRACK_EN = 0
5925 22:10:41.001744 RX_GATING_MODE = 2
5926 22:10:41.005586 RX_GATING_TRACK_MODE = 2
5927 22:10:41.008063 SELPH_MODE = 1
5928 22:10:41.011633 PICG_EARLY_EN = 1
5929 22:10:41.014787 VALID_LAT_VALUE = 1
5930 22:10:41.017931 ==============================================================
5931 22:10:41.021266 Enter into Gating configuration >>>>
5932 22:10:41.024849 Exit from Gating configuration <<<<
5933 22:10:41.027972 Enter into DVFS_PRE_config >>>>>
5934 22:10:41.041321 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5935 22:10:41.041420 Exit from DVFS_PRE_config <<<<<
5936 22:10:41.044365 Enter into PICG configuration >>>>
5937 22:10:41.047617 Exit from PICG configuration <<<<
5938 22:10:41.051229 [RX_INPUT] configuration >>>>>
5939 22:10:41.054290 [RX_INPUT] configuration <<<<<
5940 22:10:41.061047 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5941 22:10:41.064394 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5942 22:10:41.071076 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5943 22:10:41.077626 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5944 22:10:41.084162 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5945 22:10:41.090779 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5946 22:10:41.094017 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5947 22:10:41.097274 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5948 22:10:41.100832 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5949 22:10:41.107597 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5950 22:10:41.110908 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5951 22:10:41.114121 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5952 22:10:41.117453 ===================================
5953 22:10:41.120672 LPDDR4 DRAM CONFIGURATION
5954 22:10:41.124043 ===================================
5955 22:10:41.127139 EX_ROW_EN[0] = 0x0
5956 22:10:41.127215 EX_ROW_EN[1] = 0x0
5957 22:10:41.130603 LP4Y_EN = 0x0
5958 22:10:41.130679 WORK_FSP = 0x0
5959 22:10:41.134105 WL = 0x2
5960 22:10:41.134180 RL = 0x2
5961 22:10:41.137036 BL = 0x2
5962 22:10:41.137112 RPST = 0x0
5963 22:10:41.140673 RD_PRE = 0x0
5964 22:10:41.140754 WR_PRE = 0x1
5965 22:10:41.144193 WR_PST = 0x0
5966 22:10:41.144275 DBI_WR = 0x0
5967 22:10:41.147269 DBI_RD = 0x0
5968 22:10:41.147344 OTF = 0x1
5969 22:10:41.150296 ===================================
5970 22:10:41.156766 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5971 22:10:41.160110 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5972 22:10:41.163496 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5973 22:10:41.167091 ===================================
5974 22:10:41.170127 LPDDR4 DRAM CONFIGURATION
5975 22:10:41.173769 ===================================
5976 22:10:41.173860 EX_ROW_EN[0] = 0x10
5977 22:10:41.177032 EX_ROW_EN[1] = 0x0
5978 22:10:41.180514 LP4Y_EN = 0x0
5979 22:10:41.180590 WORK_FSP = 0x0
5980 22:10:41.184209 WL = 0x2
5981 22:10:41.184287 RL = 0x2
5982 22:10:41.187010 BL = 0x2
5983 22:10:41.187085 RPST = 0x0
5984 22:10:41.190242 RD_PRE = 0x0
5985 22:10:41.190316 WR_PRE = 0x1
5986 22:10:41.193706 WR_PST = 0x0
5987 22:10:41.193783 DBI_WR = 0x0
5988 22:10:41.196812 DBI_RD = 0x0
5989 22:10:41.196888 OTF = 0x1
5990 22:10:41.200339 ===================================
5991 22:10:41.207296 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5992 22:10:41.211324 nWR fixed to 30
5993 22:10:41.214438 [ModeRegInit_LP4] CH0 RK0
5994 22:10:41.214520 [ModeRegInit_LP4] CH0 RK1
5995 22:10:41.217644 [ModeRegInit_LP4] CH1 RK0
5996 22:10:41.221277 [ModeRegInit_LP4] CH1 RK1
5997 22:10:41.221361 match AC timing 18
5998 22:10:41.227724 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5999 22:10:41.231559 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6000 22:10:41.234247 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6001 22:10:41.241185 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6002 22:10:41.244281 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6003 22:10:41.244356 ==
6004 22:10:41.247711 Dram Type= 6, Freq= 0, CH_0, rank 0
6005 22:10:41.250997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6006 22:10:41.251073 ==
6007 22:10:41.257873 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6008 22:10:41.264628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6009 22:10:41.267812 [CA 0] Center 36 (8~64) winsize 57
6010 22:10:41.270854 [CA 1] Center 36 (8~64) winsize 57
6011 22:10:41.274660 [CA 2] Center 36 (8~64) winsize 57
6012 22:10:41.274738 [CA 3] Center 36 (8~64) winsize 57
6013 22:10:41.277862 [CA 4] Center 36 (8~64) winsize 57
6014 22:10:41.280826 [CA 5] Center 36 (8~64) winsize 57
6015 22:10:41.280902
6016 22:10:41.287740 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6017 22:10:41.287815
6018 22:10:41.290820 [CATrainingPosCal] consider 1 rank data
6019 22:10:41.294264 u2DelayCellTimex100 = 270/100 ps
6020 22:10:41.297713 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6021 22:10:41.300748 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6022 22:10:41.304045 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6023 22:10:41.307387 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6024 22:10:41.310946 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6025 22:10:41.314073 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6026 22:10:41.314148
6027 22:10:41.317178 CA PerBit enable=1, Macro0, CA PI delay=36
6028 22:10:41.317254
6029 22:10:41.320579 [CBTSetCACLKResult] CA Dly = 36
6030 22:10:41.324034 CS Dly: 1 (0~32)
6031 22:10:41.324111 ==
6032 22:10:41.327183 Dram Type= 6, Freq= 0, CH_0, rank 1
6033 22:10:41.330418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6034 22:10:41.330495 ==
6035 22:10:41.337933 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6036 22:10:41.343802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6037 22:10:41.343888 [CA 0] Center 36 (8~64) winsize 57
6038 22:10:41.346953 [CA 1] Center 36 (8~64) winsize 57
6039 22:10:41.350449 [CA 2] Center 36 (8~64) winsize 57
6040 22:10:41.353707 [CA 3] Center 36 (8~64) winsize 57
6041 22:10:41.356940 [CA 4] Center 36 (8~64) winsize 57
6042 22:10:41.360866 [CA 5] Center 36 (8~64) winsize 57
6043 22:10:41.360941
6044 22:10:41.364076 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6045 22:10:41.364150
6046 22:10:41.367151 [CATrainingPosCal] consider 2 rank data
6047 22:10:41.370242 u2DelayCellTimex100 = 270/100 ps
6048 22:10:41.373552 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6049 22:10:41.376961 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6050 22:10:41.383844 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6051 22:10:41.386948 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6052 22:10:41.390534 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6053 22:10:41.393771 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6054 22:10:41.393847
6055 22:10:41.397090 CA PerBit enable=1, Macro0, CA PI delay=36
6056 22:10:41.397169
6057 22:10:41.400158 [CBTSetCACLKResult] CA Dly = 36
6058 22:10:41.400247 CS Dly: 1 (0~32)
6059 22:10:41.400311
6060 22:10:41.403804 ----->DramcWriteLeveling(PI) begin...
6061 22:10:41.406833 ==
6062 22:10:41.410038 Dram Type= 6, Freq= 0, CH_0, rank 0
6063 22:10:41.413568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6064 22:10:41.413676 ==
6065 22:10:41.416791 Write leveling (Byte 0): 32 => 0
6066 22:10:41.420270 Write leveling (Byte 1): 32 => 0
6067 22:10:41.423260 DramcWriteLeveling(PI) end<-----
6068 22:10:41.423336
6069 22:10:41.423390 ==
6070 22:10:41.427030 Dram Type= 6, Freq= 0, CH_0, rank 0
6071 22:10:41.430251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6072 22:10:41.430339 ==
6073 22:10:41.433364 [Gating] SW mode calibration
6074 22:10:41.440028 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6075 22:10:41.443328 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6076 22:10:41.449817 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6077 22:10:41.453158 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6078 22:10:41.456543 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6079 22:10:41.463337 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6080 22:10:41.466695 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6081 22:10:41.470171 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6082 22:10:41.476390 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6083 22:10:41.479997 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6084 22:10:41.483353 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6085 22:10:41.486760 Total UI for P1: 0, mck2ui 16
6086 22:10:41.489930 best dqsien dly found for B0: ( 0, 10, 16)
6087 22:10:41.492763 Total UI for P1: 0, mck2ui 16
6088 22:10:41.496547 best dqsien dly found for B1: ( 0, 10, 24)
6089 22:10:41.499727 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6090 22:10:41.506520 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6091 22:10:41.506594
6092 22:10:41.509408 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6093 22:10:41.513075 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6094 22:10:41.516244 [Gating] SW calibration Done
6095 22:10:41.516320 ==
6096 22:10:41.519487 Dram Type= 6, Freq= 0, CH_0, rank 0
6097 22:10:41.522621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6098 22:10:41.522697 ==
6099 22:10:41.526259 RX Vref Scan: 0
6100 22:10:41.526331
6101 22:10:41.526382 RX Vref 0 -> 0, step: 1
6102 22:10:41.526427
6103 22:10:41.529274 RX Delay -410 -> 252, step: 16
6104 22:10:41.532613 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6105 22:10:41.539701 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6106 22:10:41.542872 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6107 22:10:41.546349 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6108 22:10:41.549254 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6109 22:10:41.555852 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6110 22:10:41.559202 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6111 22:10:41.562329 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6112 22:10:41.565686 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6113 22:10:41.572307 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6114 22:10:41.575948 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6115 22:10:41.578934 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6116 22:10:41.585706 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6117 22:10:41.589085 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6118 22:10:41.592201 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6119 22:10:41.595646 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6120 22:10:41.598767 ==
6121 22:10:41.598839 Dram Type= 6, Freq= 0, CH_0, rank 0
6122 22:10:41.605610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6123 22:10:41.605683 ==
6124 22:10:41.605736 DQS Delay:
6125 22:10:41.608506 DQS0 = 43, DQS1 = 59
6126 22:10:41.608580 DQM Delay:
6127 22:10:41.611802 DQM0 = 5, DQM1 = 12
6128 22:10:41.611885 DQ Delay:
6129 22:10:41.615456 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6130 22:10:41.618740 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6131 22:10:41.618814 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6132 22:10:41.625289 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6133 22:10:41.625371
6134 22:10:41.625436
6135 22:10:41.625481 ==
6136 22:10:41.628503 Dram Type= 6, Freq= 0, CH_0, rank 0
6137 22:10:41.632199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6138 22:10:41.632274 ==
6139 22:10:41.632326
6140 22:10:41.632372
6141 22:10:41.635297 TX Vref Scan disable
6142 22:10:41.635374 == TX Byte 0 ==
6143 22:10:41.638449 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6144 22:10:41.644954 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6145 22:10:41.645030 == TX Byte 1 ==
6146 22:10:41.652143 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6147 22:10:41.655316 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6148 22:10:41.655417 ==
6149 22:10:41.658701 Dram Type= 6, Freq= 0, CH_0, rank 0
6150 22:10:41.661667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6151 22:10:41.661750 ==
6152 22:10:41.661810
6153 22:10:41.661861
6154 22:10:41.665816 TX Vref Scan disable
6155 22:10:41.665889 == TX Byte 0 ==
6156 22:10:41.671568 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6157 22:10:41.675276 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6158 22:10:41.675364 == TX Byte 1 ==
6159 22:10:41.682008 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6160 22:10:41.685221 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6161 22:10:41.685296
6162 22:10:41.685369 [DATLAT]
6163 22:10:41.688684 Freq=400, CH0 RK0
6164 22:10:41.688758
6165 22:10:41.688811 DATLAT Default: 0xf
6166 22:10:41.691874 0, 0xFFFF, sum = 0
6167 22:10:41.691950 1, 0xFFFF, sum = 0
6168 22:10:41.695427 2, 0xFFFF, sum = 0
6169 22:10:41.695547 3, 0xFFFF, sum = 0
6170 22:10:41.698391 4, 0xFFFF, sum = 0
6171 22:10:41.698478 5, 0xFFFF, sum = 0
6172 22:10:41.701468 6, 0xFFFF, sum = 0
6173 22:10:41.701541 7, 0xFFFF, sum = 0
6174 22:10:41.705074 8, 0xFFFF, sum = 0
6175 22:10:41.708103 9, 0xFFFF, sum = 0
6176 22:10:41.708179 10, 0xFFFF, sum = 0
6177 22:10:41.711470 11, 0xFFFF, sum = 0
6178 22:10:41.711560 12, 0x0, sum = 1
6179 22:10:41.714777 13, 0x0, sum = 2
6180 22:10:41.714852 14, 0x0, sum = 3
6181 22:10:41.714905 15, 0x0, sum = 4
6182 22:10:41.718362 best_step = 13
6183 22:10:41.718436
6184 22:10:41.718487 ==
6185 22:10:41.721384 Dram Type= 6, Freq= 0, CH_0, rank 0
6186 22:10:41.724910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6187 22:10:41.724985 ==
6188 22:10:41.728032 RX Vref Scan: 1
6189 22:10:41.728107
6190 22:10:41.731252 RX Vref 0 -> 0, step: 1
6191 22:10:41.731326
6192 22:10:41.731380 RX Delay -359 -> 252, step: 8
6193 22:10:41.731425
6194 22:10:41.735083 Set Vref, RX VrefLevel [Byte0]: 52
6195 22:10:41.738071 [Byte1]: 48
6196 22:10:41.743434
6197 22:10:41.743506 Final RX Vref Byte 0 = 52 to rank0
6198 22:10:41.746785 Final RX Vref Byte 1 = 48 to rank0
6199 22:10:41.750311 Final RX Vref Byte 0 = 52 to rank1
6200 22:10:41.753519 Final RX Vref Byte 1 = 48 to rank1==
6201 22:10:41.756608 Dram Type= 6, Freq= 0, CH_0, rank 0
6202 22:10:41.763648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6203 22:10:41.763727 ==
6204 22:10:41.763783 DQS Delay:
6205 22:10:41.766527 DQS0 = 52, DQS1 = 68
6206 22:10:41.766600 DQM Delay:
6207 22:10:41.766651 DQM0 = 8, DQM1 = 17
6208 22:10:41.770051 DQ Delay:
6209 22:10:41.770126 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6210 22:10:41.773139 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6211 22:10:41.776559 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6212 22:10:41.779834 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6213 22:10:41.779912
6214 22:10:41.779966
6215 22:10:41.789905 [DQSOSCAuto] RK0, (LSB)MR18= 0xb3b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6216 22:10:41.793192 CH0 RK0: MR19=C0C, MR18=B3B3
6217 22:10:41.800266 CH0_RK0: MR19=0xC0C, MR18=0xB3B3, DQSOSC=387, MR23=63, INC=394, DEC=262
6218 22:10:41.800347 ==
6219 22:10:41.803198 Dram Type= 6, Freq= 0, CH_0, rank 1
6220 22:10:41.806494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6221 22:10:41.806570 ==
6222 22:10:41.809960 [Gating] SW mode calibration
6223 22:10:41.816416 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6224 22:10:41.823248 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6225 22:10:41.826262 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6226 22:10:41.829451 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6227 22:10:41.832881 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6228 22:10:41.839690 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6229 22:10:41.842976 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6230 22:10:41.846064 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6231 22:10:41.853008 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6232 22:10:41.856198 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6233 22:10:41.859695 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6234 22:10:41.862820 Total UI for P1: 0, mck2ui 16
6235 22:10:41.866247 best dqsien dly found for B0: ( 0, 10, 16)
6236 22:10:41.869231 Total UI for P1: 0, mck2ui 16
6237 22:10:41.872774 best dqsien dly found for B1: ( 0, 10, 16)
6238 22:10:41.876063 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6239 22:10:41.879529 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6240 22:10:41.882850
6241 22:10:41.886185 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6242 22:10:41.889204 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6243 22:10:41.892523 [Gating] SW calibration Done
6244 22:10:41.892597 ==
6245 22:10:41.895789 Dram Type= 6, Freq= 0, CH_0, rank 1
6246 22:10:41.899243 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6247 22:10:41.899318 ==
6248 22:10:41.902819 RX Vref Scan: 0
6249 22:10:41.902893
6250 22:10:41.902953 RX Vref 0 -> 0, step: 1
6251 22:10:41.903000
6252 22:10:41.905797 RX Delay -410 -> 252, step: 16
6253 22:10:41.909414 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6254 22:10:41.915705 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6255 22:10:41.919220 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6256 22:10:41.922482 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6257 22:10:41.926056 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6258 22:10:41.932378 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6259 22:10:41.936005 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6260 22:10:41.939100 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6261 22:10:41.942543 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6262 22:10:41.949191 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6263 22:10:41.952583 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6264 22:10:41.955680 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6265 22:10:41.959267 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6266 22:10:41.965653 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6267 22:10:41.968781 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6268 22:10:41.972095 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6269 22:10:41.972171 ==
6270 22:10:41.975660 Dram Type= 6, Freq= 0, CH_0, rank 1
6271 22:10:41.982100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6272 22:10:41.982189 ==
6273 22:10:41.982257 DQS Delay:
6274 22:10:41.985314 DQS0 = 51, DQS1 = 59
6275 22:10:41.985390 DQM Delay:
6276 22:10:41.985442 DQM0 = 14, DQM1 = 16
6277 22:10:41.989092 DQ Delay:
6278 22:10:41.992233 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6279 22:10:41.995459 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6280 22:10:41.995532 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6281 22:10:42.002122 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6282 22:10:42.002199
6283 22:10:42.002264
6284 22:10:42.002310 ==
6285 22:10:42.005188 Dram Type= 6, Freq= 0, CH_0, rank 1
6286 22:10:42.008529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6287 22:10:42.008606 ==
6288 22:10:42.008661
6289 22:10:42.008707
6290 22:10:42.012079 TX Vref Scan disable
6291 22:10:42.012164 == TX Byte 0 ==
6292 22:10:42.015355 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6293 22:10:42.022001 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6294 22:10:42.022075 == TX Byte 1 ==
6295 22:10:42.024956 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6296 22:10:42.031782 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6297 22:10:42.031856 ==
6298 22:10:42.035063 Dram Type= 6, Freq= 0, CH_0, rank 1
6299 22:10:42.038155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6300 22:10:42.038228 ==
6301 22:10:42.038280
6302 22:10:42.038325
6303 22:10:42.041777 TX Vref Scan disable
6304 22:10:42.041850 == TX Byte 0 ==
6305 22:10:42.048334 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6306 22:10:42.052057 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6307 22:10:42.052143 == TX Byte 1 ==
6308 22:10:42.058175 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6309 22:10:42.061253 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6310 22:10:42.061353
6311 22:10:42.061421 [DATLAT]
6312 22:10:42.064988 Freq=400, CH0 RK1
6313 22:10:42.065062
6314 22:10:42.065114 DATLAT Default: 0xd
6315 22:10:42.068179 0, 0xFFFF, sum = 0
6316 22:10:42.068253 1, 0xFFFF, sum = 0
6317 22:10:42.071462 2, 0xFFFF, sum = 0
6318 22:10:42.071536 3, 0xFFFF, sum = 0
6319 22:10:42.074912 4, 0xFFFF, sum = 0
6320 22:10:42.074993 5, 0xFFFF, sum = 0
6321 22:10:42.078348 6, 0xFFFF, sum = 0
6322 22:10:42.078422 7, 0xFFFF, sum = 0
6323 22:10:42.081430 8, 0xFFFF, sum = 0
6324 22:10:42.081503 9, 0xFFFF, sum = 0
6325 22:10:42.084710 10, 0xFFFF, sum = 0
6326 22:10:42.084785 11, 0xFFFF, sum = 0
6327 22:10:42.088205 12, 0x0, sum = 1
6328 22:10:42.088291 13, 0x0, sum = 2
6329 22:10:42.091087 14, 0x0, sum = 3
6330 22:10:42.091173 15, 0x0, sum = 4
6331 22:10:42.094920 best_step = 13
6332 22:10:42.094992
6333 22:10:42.095042 ==
6334 22:10:42.097976 Dram Type= 6, Freq= 0, CH_0, rank 1
6335 22:10:42.100802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6336 22:10:42.100885 ==
6337 22:10:42.104179 RX Vref Scan: 0
6338 22:10:42.104269
6339 22:10:42.104325 RX Vref 0 -> 0, step: 1
6340 22:10:42.104375
6341 22:10:42.107678 RX Delay -359 -> 252, step: 8
6342 22:10:42.115914 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6343 22:10:42.119207 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6344 22:10:42.122541 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6345 22:10:42.125995 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6346 22:10:42.132436 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6347 22:10:42.136039 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6348 22:10:42.139325 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6349 22:10:42.142892 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6350 22:10:42.149237 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6351 22:10:42.152717 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488
6352 22:10:42.155973 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6353 22:10:42.159171 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6354 22:10:42.165748 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6355 22:10:42.169029 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6356 22:10:42.172248 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6357 22:10:42.179000 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6358 22:10:42.179075 ==
6359 22:10:42.182414 Dram Type= 6, Freq= 0, CH_0, rank 1
6360 22:10:42.185885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6361 22:10:42.185959 ==
6362 22:10:42.186009 DQS Delay:
6363 22:10:42.188981 DQS0 = 52, DQS1 = 68
6364 22:10:42.189056 DQM Delay:
6365 22:10:42.192184 DQM0 = 11, DQM1 = 17
6366 22:10:42.192258 DQ Delay:
6367 22:10:42.195485 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6368 22:10:42.199065 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6369 22:10:42.202283 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6370 22:10:42.205789 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6371 22:10:42.205873
6372 22:10:42.205928
6373 22:10:42.212087 [DQSOSCAuto] RK1, (LSB)MR18= 0xc2c2, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6374 22:10:42.215392 CH0 RK1: MR19=C0C, MR18=C2C2
6375 22:10:42.222075 CH0_RK1: MR19=0xC0C, MR18=0xC2C2, DQSOSC=385, MR23=63, INC=398, DEC=265
6376 22:10:42.225336 [RxdqsGatingPostProcess] freq 400
6377 22:10:42.232119 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6378 22:10:42.232196 Pre-setting of DQS Precalculation
6379 22:10:42.238755 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6380 22:10:42.238829 ==
6381 22:10:42.242369 Dram Type= 6, Freq= 0, CH_1, rank 0
6382 22:10:42.245290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6383 22:10:42.245384 ==
6384 22:10:42.252091 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6385 22:10:42.258575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6386 22:10:42.262209 [CA 0] Center 36 (8~64) winsize 57
6387 22:10:42.265249 [CA 1] Center 36 (8~64) winsize 57
6388 22:10:42.268658 [CA 2] Center 36 (8~64) winsize 57
6389 22:10:42.271811 [CA 3] Center 36 (8~64) winsize 57
6390 22:10:42.271887 [CA 4] Center 36 (8~64) winsize 57
6391 22:10:42.275376 [CA 5] Center 36 (8~64) winsize 57
6392 22:10:42.275462
6393 22:10:42.281960 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6394 22:10:42.282034
6395 22:10:42.284963 [CATrainingPosCal] consider 1 rank data
6396 22:10:42.288634 u2DelayCellTimex100 = 270/100 ps
6397 22:10:42.291992 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6398 22:10:42.294989 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6399 22:10:42.298536 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6400 22:10:42.301625 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6401 22:10:42.305336 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6402 22:10:42.308332 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6403 22:10:42.308408
6404 22:10:42.311490 CA PerBit enable=1, Macro0, CA PI delay=36
6405 22:10:42.311574
6406 22:10:42.315056 [CBTSetCACLKResult] CA Dly = 36
6407 22:10:42.318026 CS Dly: 1 (0~32)
6408 22:10:42.318100 ==
6409 22:10:42.321638 Dram Type= 6, Freq= 0, CH_1, rank 1
6410 22:10:42.324658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6411 22:10:42.324734 ==
6412 22:10:42.331231 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6413 22:10:42.337877 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6414 22:10:42.341275 [CA 0] Center 36 (8~64) winsize 57
6415 22:10:42.341358 [CA 1] Center 36 (8~64) winsize 57
6416 22:10:42.344525 [CA 2] Center 36 (8~64) winsize 57
6417 22:10:42.347864 [CA 3] Center 36 (8~64) winsize 57
6418 22:10:42.351837 [CA 4] Center 36 (8~64) winsize 57
6419 22:10:42.354798 [CA 5] Center 36 (8~64) winsize 57
6420 22:10:42.354872
6421 22:10:42.358035 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6422 22:10:42.358111
6423 22:10:42.361526 [CATrainingPosCal] consider 2 rank data
6424 22:10:42.364653 u2DelayCellTimex100 = 270/100 ps
6425 22:10:42.367835 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6426 22:10:42.371471 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6427 22:10:42.378363 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6428 22:10:42.381432 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6429 22:10:42.384414 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6430 22:10:42.388105 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6431 22:10:42.388212
6432 22:10:42.391141 CA PerBit enable=1, Macro0, CA PI delay=36
6433 22:10:42.391215
6434 22:10:42.394590 [CBTSetCACLKResult] CA Dly = 36
6435 22:10:42.394664 CS Dly: 1 (0~32)
6436 22:10:42.394732
6437 22:10:42.398003 ----->DramcWriteLeveling(PI) begin...
6438 22:10:42.400937 ==
6439 22:10:42.404658 Dram Type= 6, Freq= 0, CH_1, rank 0
6440 22:10:42.407675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6441 22:10:42.407749 ==
6442 22:10:42.411327 Write leveling (Byte 0): 32 => 0
6443 22:10:42.414531 Write leveling (Byte 1): 32 => 0
6444 22:10:42.417627 DramcWriteLeveling(PI) end<-----
6445 22:10:42.417702
6446 22:10:42.417769 ==
6447 22:10:42.421180 Dram Type= 6, Freq= 0, CH_1, rank 0
6448 22:10:42.424297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6449 22:10:42.424374 ==
6450 22:10:42.427475 [Gating] SW mode calibration
6451 22:10:42.434317 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6452 22:10:42.440589 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6453 22:10:42.444143 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 22:10:42.447414 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 22:10:42.450678 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 22:10:42.457480 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6457 22:10:42.460721 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 22:10:42.464141 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 22:10:42.470982 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 22:10:42.474052 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6461 22:10:42.477437 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 22:10:42.480474 Total UI for P1: 0, mck2ui 16
6463 22:10:42.484169 best dqsien dly found for B0: ( 0, 10, 16)
6464 22:10:42.487199 Total UI for P1: 0, mck2ui 16
6465 22:10:42.490734 best dqsien dly found for B1: ( 0, 10, 16)
6466 22:10:42.494102 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6467 22:10:42.497534 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6468 22:10:42.500987
6469 22:10:42.504029 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6470 22:10:42.507353 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6471 22:10:42.510481 [Gating] SW calibration Done
6472 22:10:42.510563 ==
6473 22:10:42.514147 Dram Type= 6, Freq= 0, CH_1, rank 0
6474 22:10:42.517205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6475 22:10:42.517285 ==
6476 22:10:42.517349 RX Vref Scan: 0
6477 22:10:42.520874
6478 22:10:42.520949 RX Vref 0 -> 0, step: 1
6479 22:10:42.521002
6480 22:10:42.524188 RX Delay -410 -> 252, step: 16
6481 22:10:42.527299 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6482 22:10:42.534018 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6483 22:10:42.537033 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6484 22:10:42.540825 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6485 22:10:42.543723 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6486 22:10:42.550287 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6487 22:10:42.553809 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6488 22:10:42.557713 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6489 22:10:42.560421 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6490 22:10:42.567200 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6491 22:10:42.570596 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6492 22:10:42.573499 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6493 22:10:42.577122 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6494 22:10:42.583870 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6495 22:10:42.587075 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6496 22:10:42.590244 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6497 22:10:42.590321 ==
6498 22:10:42.593512 Dram Type= 6, Freq= 0, CH_1, rank 0
6499 22:10:42.600329 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6500 22:10:42.600404 ==
6501 22:10:42.600471 DQS Delay:
6502 22:10:42.603489 DQS0 = 43, DQS1 = 59
6503 22:10:42.603562 DQM Delay:
6504 22:10:42.603631 DQM0 = 6, DQM1 = 15
6505 22:10:42.607059 DQ Delay:
6506 22:10:42.610285 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6507 22:10:42.610368 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6508 22:10:42.613789 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6509 22:10:42.617216 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6510 22:10:42.617292
6511 22:10:42.617362
6512 22:10:42.620296 ==
6513 22:10:42.623304 Dram Type= 6, Freq= 0, CH_1, rank 0
6514 22:10:42.626964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6515 22:10:42.627039 ==
6516 22:10:42.627108
6517 22:10:42.627184
6518 22:10:42.630132 TX Vref Scan disable
6519 22:10:42.630207 == TX Byte 0 ==
6520 22:10:42.633362 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6521 22:10:42.639850 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6522 22:10:42.639934 == TX Byte 1 ==
6523 22:10:42.643646 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6524 22:10:42.649914 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6525 22:10:42.649988 ==
6526 22:10:42.653497 Dram Type= 6, Freq= 0, CH_1, rank 0
6527 22:10:42.656442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6528 22:10:42.656520 ==
6529 22:10:42.656588
6530 22:10:42.656634
6531 22:10:42.659965 TX Vref Scan disable
6532 22:10:42.660041 == TX Byte 0 ==
6533 22:10:42.666239 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6534 22:10:42.669807 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6535 22:10:42.669881 == TX Byte 1 ==
6536 22:10:42.676557 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6537 22:10:42.679709 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6538 22:10:42.679783
6539 22:10:42.679853 [DATLAT]
6540 22:10:42.683081 Freq=400, CH1 RK0
6541 22:10:42.683155
6542 22:10:42.683224 DATLAT Default: 0xf
6543 22:10:42.686432 0, 0xFFFF, sum = 0
6544 22:10:42.686509 1, 0xFFFF, sum = 0
6545 22:10:42.690011 2, 0xFFFF, sum = 0
6546 22:10:42.690095 3, 0xFFFF, sum = 0
6547 22:10:42.693028 4, 0xFFFF, sum = 0
6548 22:10:42.693104 5, 0xFFFF, sum = 0
6549 22:10:42.696698 6, 0xFFFF, sum = 0
6550 22:10:42.696775 7, 0xFFFF, sum = 0
6551 22:10:42.699857 8, 0xFFFF, sum = 0
6552 22:10:42.699932 9, 0xFFFF, sum = 0
6553 22:10:42.703120 10, 0xFFFF, sum = 0
6554 22:10:42.706630 11, 0xFFFF, sum = 0
6555 22:10:42.706707 12, 0x0, sum = 1
6556 22:10:42.706760 13, 0x0, sum = 2
6557 22:10:42.709521 14, 0x0, sum = 3
6558 22:10:42.709598 15, 0x0, sum = 4
6559 22:10:42.712751 best_step = 13
6560 22:10:42.712827
6561 22:10:42.712881 ==
6562 22:10:42.716289 Dram Type= 6, Freq= 0, CH_1, rank 0
6563 22:10:42.719715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6564 22:10:42.719792 ==
6565 22:10:42.722768 RX Vref Scan: 1
6566 22:10:42.722855
6567 22:10:42.722924 RX Vref 0 -> 0, step: 1
6568 22:10:42.726099
6569 22:10:42.726175 RX Delay -359 -> 252, step: 8
6570 22:10:42.726229
6571 22:10:42.729755 Set Vref, RX VrefLevel [Byte0]: 53
6572 22:10:42.732601 [Byte1]: 50
6573 22:10:42.737812
6574 22:10:42.737885 Final RX Vref Byte 0 = 53 to rank0
6575 22:10:42.741196 Final RX Vref Byte 1 = 50 to rank0
6576 22:10:42.744175 Final RX Vref Byte 0 = 53 to rank1
6577 22:10:42.747661 Final RX Vref Byte 1 = 50 to rank1==
6578 22:10:42.751013 Dram Type= 6, Freq= 0, CH_1, rank 0
6579 22:10:42.757828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6580 22:10:42.757903 ==
6581 22:10:42.757973 DQS Delay:
6582 22:10:42.760923 DQS0 = 48, DQS1 = 64
6583 22:10:42.760998 DQM Delay:
6584 22:10:42.761052 DQM0 = 8, DQM1 = 16
6585 22:10:42.764613 DQ Delay:
6586 22:10:42.767724 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6587 22:10:42.767799 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6588 22:10:42.770915 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6589 22:10:42.774339 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6590 22:10:42.774414
6591 22:10:42.774467
6592 22:10:42.784698 [DQSOSCAuto] RK0, (LSB)MR18= 0xe4e4, (MSB)MR19= 0xc0c, tDQSOscB0 = 381 ps tDQSOscB1 = 381 ps
6593 22:10:42.788358 CH1 RK0: MR19=C0C, MR18=E4E4
6594 22:10:42.794202 CH1_RK0: MR19=0xC0C, MR18=0xE4E4, DQSOSC=381, MR23=63, INC=406, DEC=271
6595 22:10:42.794291 ==
6596 22:10:42.797551 Dram Type= 6, Freq= 0, CH_1, rank 1
6597 22:10:42.800899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6598 22:10:42.800976 ==
6599 22:10:42.804043 [Gating] SW mode calibration
6600 22:10:42.810764 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6601 22:10:42.813990 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6602 22:10:42.820716 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6603 22:10:42.823923 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6604 22:10:42.827226 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6605 22:10:42.833995 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6606 22:10:42.837674 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6607 22:10:42.840557 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6608 22:10:42.847495 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6609 22:10:42.850615 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6610 22:10:42.853679 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6611 22:10:42.856985 Total UI for P1: 0, mck2ui 16
6612 22:10:42.860362 best dqsien dly found for B0: ( 0, 10, 16)
6613 22:10:42.863725 Total UI for P1: 0, mck2ui 16
6614 22:10:42.867355 best dqsien dly found for B1: ( 0, 10, 16)
6615 22:10:42.870554 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6616 22:10:42.873690 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6617 22:10:42.877301
6618 22:10:42.880220 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6619 22:10:42.883640 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6620 22:10:42.886809 [Gating] SW calibration Done
6621 22:10:42.886884 ==
6622 22:10:42.890076 Dram Type= 6, Freq= 0, CH_1, rank 1
6623 22:10:42.893595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6624 22:10:42.893683 ==
6625 22:10:42.896790 RX Vref Scan: 0
6626 22:10:42.896875
6627 22:10:42.896934 RX Vref 0 -> 0, step: 1
6628 22:10:42.896988
6629 22:10:42.900223 RX Delay -410 -> 252, step: 16
6630 22:10:42.903480 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6631 22:10:42.910216 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6632 22:10:42.913906 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6633 22:10:42.916851 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6634 22:10:42.920552 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6635 22:10:42.926771 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6636 22:10:42.930422 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6637 22:10:42.933502 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6638 22:10:42.936962 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6639 22:10:42.943810 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6640 22:10:42.946967 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6641 22:10:42.950147 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6642 22:10:42.953419 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6643 22:10:42.959804 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6644 22:10:42.963360 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6645 22:10:42.966669 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6646 22:10:42.966743 ==
6647 22:10:42.970374 Dram Type= 6, Freq= 0, CH_1, rank 1
6648 22:10:42.976467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6649 22:10:42.976552 ==
6650 22:10:42.976620 DQS Delay:
6651 22:10:42.980043 DQS0 = 43, DQS1 = 59
6652 22:10:42.980118 DQM Delay:
6653 22:10:42.980169 DQM0 = 10, DQM1 = 17
6654 22:10:42.983264 DQ Delay:
6655 22:10:42.986639 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6656 22:10:42.986712 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6657 22:10:42.989592 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6658 22:10:42.993077 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6659 22:10:42.996314
6660 22:10:42.996389
6661 22:10:42.996441 ==
6662 22:10:42.999809 Dram Type= 6, Freq= 0, CH_1, rank 1
6663 22:10:43.002838 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6664 22:10:43.002913 ==
6665 22:10:43.002967
6666 22:10:43.003011
6667 22:10:43.006491 TX Vref Scan disable
6668 22:10:43.006578 == TX Byte 0 ==
6669 22:10:43.009613 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6670 22:10:43.016168 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6671 22:10:43.016247 == TX Byte 1 ==
6672 22:10:43.019858 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6673 22:10:43.026088 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6674 22:10:43.026171 ==
6675 22:10:43.029809 Dram Type= 6, Freq= 0, CH_1, rank 1
6676 22:10:43.032739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6677 22:10:43.032815 ==
6678 22:10:43.032868
6679 22:10:43.032915
6680 22:10:43.036168 TX Vref Scan disable
6681 22:10:43.036243 == TX Byte 0 ==
6682 22:10:43.039168 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6683 22:10:43.046390 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6684 22:10:43.046481 == TX Byte 1 ==
6685 22:10:43.049323 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6686 22:10:43.056211 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6687 22:10:43.056287
6688 22:10:43.056341 [DATLAT]
6689 22:10:43.059370 Freq=400, CH1 RK1
6690 22:10:43.059457
6691 22:10:43.059509 DATLAT Default: 0xd
6692 22:10:43.062229 0, 0xFFFF, sum = 0
6693 22:10:43.062306 1, 0xFFFF, sum = 0
6694 22:10:43.066207 2, 0xFFFF, sum = 0
6695 22:10:43.066282 3, 0xFFFF, sum = 0
6696 22:10:43.068835 4, 0xFFFF, sum = 0
6697 22:10:43.068912 5, 0xFFFF, sum = 0
6698 22:10:43.072182 6, 0xFFFF, sum = 0
6699 22:10:43.072258 7, 0xFFFF, sum = 0
6700 22:10:43.075601 8, 0xFFFF, sum = 0
6701 22:10:43.075687 9, 0xFFFF, sum = 0
6702 22:10:43.078915 10, 0xFFFF, sum = 0
6703 22:10:43.078991 11, 0xFFFF, sum = 0
6704 22:10:43.082619 12, 0x0, sum = 1
6705 22:10:43.082695 13, 0x0, sum = 2
6706 22:10:43.085520 14, 0x0, sum = 3
6707 22:10:43.085595 15, 0x0, sum = 4
6708 22:10:43.088688 best_step = 13
6709 22:10:43.088762
6710 22:10:43.088816 ==
6711 22:10:43.091919 Dram Type= 6, Freq= 0, CH_1, rank 1
6712 22:10:43.095397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6713 22:10:43.095471 ==
6714 22:10:43.098599 RX Vref Scan: 0
6715 22:10:43.098685
6716 22:10:43.098738 RX Vref 0 -> 0, step: 1
6717 22:10:43.098784
6718 22:10:43.102331 RX Delay -359 -> 252, step: 8
6719 22:10:43.109899 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6720 22:10:43.113744 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6721 22:10:43.116938 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6722 22:10:43.119970 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6723 22:10:43.127086 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6724 22:10:43.130160 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6725 22:10:43.133418 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6726 22:10:43.136533 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6727 22:10:43.143232 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6728 22:10:43.146898 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6729 22:10:43.150001 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6730 22:10:43.153123 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6731 22:10:43.159781 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6732 22:10:43.163412 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6733 22:10:43.166784 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6734 22:10:43.173368 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6735 22:10:43.173444 ==
6736 22:10:43.176808 Dram Type= 6, Freq= 0, CH_1, rank 1
6737 22:10:43.180057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6738 22:10:43.180131 ==
6739 22:10:43.180184 DQS Delay:
6740 22:10:43.183525 DQS0 = 48, DQS1 = 64
6741 22:10:43.183611 DQM Delay:
6742 22:10:43.186659 DQM0 = 10, DQM1 = 15
6743 22:10:43.186732 DQ Delay:
6744 22:10:43.190174 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6745 22:10:43.193179 DQ4 =12, DQ5 =24, DQ6 =16, DQ7 =8
6746 22:10:43.196729 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6747 22:10:43.199900 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6748 22:10:43.199974
6749 22:10:43.200027
6750 22:10:43.206656 [DQSOSCAuto] RK1, (LSB)MR18= 0xadad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6751 22:10:43.209568 CH1 RK1: MR19=C0C, MR18=ADAD
6752 22:10:43.216194 CH1_RK1: MR19=0xC0C, MR18=0xADAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6753 22:10:43.219851 [RxdqsGatingPostProcess] freq 400
6754 22:10:43.226240 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6755 22:10:43.226314 Pre-setting of DQS Precalculation
6756 22:10:43.232934 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6757 22:10:43.239432 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6758 22:10:43.245949 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6759 22:10:43.246024
6760 22:10:43.246077
6761 22:10:43.249233 [Calibration Summary] 800 Mbps
6762 22:10:43.252842 CH 0, Rank 0
6763 22:10:43.252917 SW Impedance : PASS
6764 22:10:43.256332 DUTY Scan : NO K
6765 22:10:43.259387 ZQ Calibration : PASS
6766 22:10:43.259463 Jitter Meter : NO K
6767 22:10:43.263020 CBT Training : PASS
6768 22:10:43.266469 Write leveling : PASS
6769 22:10:43.266556 RX DQS gating : PASS
6770 22:10:43.269557 RX DQ/DQS(RDDQC) : PASS
6771 22:10:43.269631 TX DQ/DQS : PASS
6772 22:10:43.272650 RX DATLAT : PASS
6773 22:10:43.276009 RX DQ/DQS(Engine): PASS
6774 22:10:43.276095 TX OE : NO K
6775 22:10:43.279641 All Pass.
6776 22:10:43.279714
6777 22:10:43.279765 CH 0, Rank 1
6778 22:10:43.282794 SW Impedance : PASS
6779 22:10:43.282868 DUTY Scan : NO K
6780 22:10:43.286150 ZQ Calibration : PASS
6781 22:10:43.289559 Jitter Meter : NO K
6782 22:10:43.289641 CBT Training : PASS
6783 22:10:43.292674 Write leveling : NO K
6784 22:10:43.295825 RX DQS gating : PASS
6785 22:10:43.295899 RX DQ/DQS(RDDQC) : PASS
6786 22:10:43.299231 TX DQ/DQS : PASS
6787 22:10:43.302709 RX DATLAT : PASS
6788 22:10:43.302785 RX DQ/DQS(Engine): PASS
6789 22:10:43.305905 TX OE : NO K
6790 22:10:43.305992 All Pass.
6791 22:10:43.306046
6792 22:10:43.309252 CH 1, Rank 0
6793 22:10:43.309332 SW Impedance : PASS
6794 22:10:43.312732 DUTY Scan : NO K
6795 22:10:43.315715 ZQ Calibration : PASS
6796 22:10:43.315791 Jitter Meter : NO K
6797 22:10:43.319162 CBT Training : PASS
6798 22:10:43.319237 Write leveling : PASS
6799 22:10:43.322685 RX DQS gating : PASS
6800 22:10:43.325667 RX DQ/DQS(RDDQC) : PASS
6801 22:10:43.325747 TX DQ/DQS : PASS
6802 22:10:43.329548 RX DATLAT : PASS
6803 22:10:43.332485 RX DQ/DQS(Engine): PASS
6804 22:10:43.332560 TX OE : NO K
6805 22:10:43.335779 All Pass.
6806 22:10:43.335853
6807 22:10:43.335906 CH 1, Rank 1
6808 22:10:43.339380 SW Impedance : PASS
6809 22:10:43.339456 DUTY Scan : NO K
6810 22:10:43.342323 ZQ Calibration : PASS
6811 22:10:43.345921 Jitter Meter : NO K
6812 22:10:43.345996 CBT Training : PASS
6813 22:10:43.348911 Write leveling : NO K
6814 22:10:43.352583 RX DQS gating : PASS
6815 22:10:43.352659 RX DQ/DQS(RDDQC) : PASS
6816 22:10:43.355942 TX DQ/DQS : PASS
6817 22:10:43.359073 RX DATLAT : PASS
6818 22:10:43.359148 RX DQ/DQS(Engine): PASS
6819 22:10:43.362485 TX OE : NO K
6820 22:10:43.362577 All Pass.
6821 22:10:43.362630
6822 22:10:43.365654 DramC Write-DBI off
6823 22:10:43.369200 PER_BANK_REFRESH: Hybrid Mode
6824 22:10:43.369275 TX_TRACKING: ON
6825 22:10:43.379226 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6826 22:10:43.382359 [FAST_K] Save calibration result to emmc
6827 22:10:43.385761 dramc_set_vcore_voltage set vcore to 725000
6828 22:10:43.388675 Read voltage for 1600, 0
6829 22:10:43.388749 Vio18 = 0
6830 22:10:43.388802 Vcore = 725000
6831 22:10:43.391938 Vdram = 0
6832 22:10:43.392012 Vddq = 0
6833 22:10:43.392065 Vmddr = 0
6834 22:10:43.398863 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6835 22:10:43.401868 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6836 22:10:43.405596 MEM_TYPE=3, freq_sel=13
6837 22:10:43.408627 sv_algorithm_assistance_LP4_3733
6838 22:10:43.412060 ============ PULL DRAM RESETB DOWN ============
6839 22:10:43.415540 ========== PULL DRAM RESETB DOWN end =========
6840 22:10:43.422219 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6841 22:10:43.425190 ===================================
6842 22:10:43.425257 LPDDR4 DRAM CONFIGURATION
6843 22:10:43.428826 ===================================
6844 22:10:43.431983 EX_ROW_EN[0] = 0x0
6845 22:10:43.435579 EX_ROW_EN[1] = 0x0
6846 22:10:43.435664 LP4Y_EN = 0x0
6847 22:10:43.438846 WORK_FSP = 0x1
6848 22:10:43.438923 WL = 0x5
6849 22:10:43.441803 RL = 0x5
6850 22:10:43.441879 BL = 0x2
6851 22:10:43.445076 RPST = 0x0
6852 22:10:43.445150 RD_PRE = 0x0
6853 22:10:43.449081 WR_PRE = 0x1
6854 22:10:43.449154 WR_PST = 0x1
6855 22:10:43.451965 DBI_WR = 0x0
6856 22:10:43.452039 DBI_RD = 0x0
6857 22:10:43.455113 OTF = 0x1
6858 22:10:43.458723 ===================================
6859 22:10:43.461745 ===================================
6860 22:10:43.461820 ANA top config
6861 22:10:43.465473 ===================================
6862 22:10:43.468716 DLL_ASYNC_EN = 0
6863 22:10:43.471760 ALL_SLAVE_EN = 0
6864 22:10:43.474867 NEW_RANK_MODE = 1
6865 22:10:43.474937 DLL_IDLE_MODE = 1
6866 22:10:43.478711 LP45_APHY_COMB_EN = 1
6867 22:10:43.481874 TX_ODT_DIS = 0
6868 22:10:43.484807 NEW_8X_MODE = 1
6869 22:10:43.488510 ===================================
6870 22:10:43.491813 ===================================
6871 22:10:43.494886 data_rate = 3200
6872 22:10:43.494958 CKR = 1
6873 22:10:43.498215 DQ_P2S_RATIO = 8
6874 22:10:43.501769 ===================================
6875 22:10:43.504918 CA_P2S_RATIO = 8
6876 22:10:43.508136 DQ_CA_OPEN = 0
6877 22:10:43.511745 DQ_SEMI_OPEN = 0
6878 22:10:43.515467 CA_SEMI_OPEN = 0
6879 22:10:43.515542 CA_FULL_RATE = 0
6880 22:10:43.518396 DQ_CKDIV4_EN = 0
6881 22:10:43.521588 CA_CKDIV4_EN = 0
6882 22:10:43.525058 CA_PREDIV_EN = 0
6883 22:10:43.528043 PH8_DLY = 12
6884 22:10:43.531468 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6885 22:10:43.531542 DQ_AAMCK_DIV = 4
6886 22:10:43.534945 CA_AAMCK_DIV = 4
6887 22:10:43.538445 CA_ADMCK_DIV = 4
6888 22:10:43.541555 DQ_TRACK_CA_EN = 0
6889 22:10:43.544886 CA_PICK = 1600
6890 22:10:43.548170 CA_MCKIO = 1600
6891 22:10:43.551527 MCKIO_SEMI = 0
6892 22:10:43.551602 PLL_FREQ = 3068
6893 22:10:43.555064 DQ_UI_PI_RATIO = 32
6894 22:10:43.558285 CA_UI_PI_RATIO = 0
6895 22:10:43.562042 ===================================
6896 22:10:43.565099 ===================================
6897 22:10:43.568401 memory_type:LPDDR4
6898 22:10:43.568476 GP_NUM : 10
6899 22:10:43.571256 SRAM_EN : 1
6900 22:10:43.574777 MD32_EN : 0
6901 22:10:43.578332 ===================================
6902 22:10:43.578419 [ANA_INIT] >>>>>>>>>>>>>>
6903 22:10:43.581489 <<<<<< [CONFIGURE PHASE]: ANA_TX
6904 22:10:43.585037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6905 22:10:43.588415 ===================================
6906 22:10:43.591619 data_rate = 3200,PCW = 0X7600
6907 22:10:43.594980 ===================================
6908 22:10:43.598648 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6909 22:10:43.605221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6910 22:10:43.608410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6911 22:10:43.615161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6912 22:10:43.618326 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6913 22:10:43.621063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6914 22:10:43.624500 [ANA_INIT] flow start
6915 22:10:43.625063 [ANA_INIT] PLL >>>>>>>>
6916 22:10:43.628045 [ANA_INIT] PLL <<<<<<<<
6917 22:10:43.631729 [ANA_INIT] MIDPI >>>>>>>>
6918 22:10:43.632242 [ANA_INIT] MIDPI <<<<<<<<
6919 22:10:43.635485 [ANA_INIT] DLL >>>>>>>>
6920 22:10:43.638163 [ANA_INIT] DLL <<<<<<<<
6921 22:10:43.638506 [ANA_INIT] flow end
6922 22:10:43.641747 ============ LP4 DIFF to SE enter ============
6923 22:10:43.647920 ============ LP4 DIFF to SE exit ============
6924 22:10:43.648358 [ANA_INIT] <<<<<<<<<<<<<
6925 22:10:43.651990 [Flow] Enable top DCM control >>>>>
6926 22:10:43.655196 [Flow] Enable top DCM control <<<<<
6927 22:10:43.657909 Enable DLL master slave shuffle
6928 22:10:43.664761 ==============================================================
6929 22:10:43.667838 Gating Mode config
6930 22:10:43.671538 ==============================================================
6931 22:10:43.674522 Config description:
6932 22:10:43.684602 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6933 22:10:43.691635 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6934 22:10:43.694926 SELPH_MODE 0: By rank 1: By Phase
6935 22:10:43.701553 ==============================================================
6936 22:10:43.704780 GAT_TRACK_EN = 1
6937 22:10:43.708086 RX_GATING_MODE = 2
6938 22:10:43.708571 RX_GATING_TRACK_MODE = 2
6939 22:10:43.710811 SELPH_MODE = 1
6940 22:10:43.714168 PICG_EARLY_EN = 1
6941 22:10:43.717257 VALID_LAT_VALUE = 1
6942 22:10:43.723980 ==============================================================
6943 22:10:43.727507 Enter into Gating configuration >>>>
6944 22:10:43.731316 Exit from Gating configuration <<<<
6945 22:10:43.734402 Enter into DVFS_PRE_config >>>>>
6946 22:10:43.744369 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6947 22:10:43.747976 Exit from DVFS_PRE_config <<<<<
6948 22:10:43.750811 Enter into PICG configuration >>>>
6949 22:10:43.754420 Exit from PICG configuration <<<<
6950 22:10:43.757657 [RX_INPUT] configuration >>>>>
6951 22:10:43.760704 [RX_INPUT] configuration <<<<<
6952 22:10:43.764235 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6953 22:10:43.770889 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6954 22:10:43.777709 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6955 22:10:43.784018 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6956 22:10:43.790884 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6957 22:10:43.794130 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6958 22:10:43.800595 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6959 22:10:43.804038 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6960 22:10:43.807776 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6961 22:10:43.810518 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6962 22:10:43.813679 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6963 22:10:43.820763 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6964 22:10:43.823913 ===================================
6965 22:10:43.827572 LPDDR4 DRAM CONFIGURATION
6966 22:10:43.830517 ===================================
6967 22:10:43.830904 EX_ROW_EN[0] = 0x0
6968 22:10:43.833393 EX_ROW_EN[1] = 0x0
6969 22:10:43.833689 LP4Y_EN = 0x0
6970 22:10:43.836979 WORK_FSP = 0x1
6971 22:10:43.837514 WL = 0x5
6972 22:10:43.840336 RL = 0x5
6973 22:10:43.840712 BL = 0x2
6974 22:10:43.843755 RPST = 0x0
6975 22:10:43.844243 RD_PRE = 0x0
6976 22:10:43.847016 WR_PRE = 0x1
6977 22:10:43.847473 WR_PST = 0x1
6978 22:10:43.850395 DBI_WR = 0x0
6979 22:10:43.853982 DBI_RD = 0x0
6980 22:10:43.854464 OTF = 0x1
6981 22:10:43.857012 ===================================
6982 22:10:43.860196 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6983 22:10:43.863432 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6984 22:10:43.870163 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6985 22:10:43.873281 ===================================
6986 22:10:43.876351 LPDDR4 DRAM CONFIGURATION
6987 22:10:43.880453 ===================================
6988 22:10:43.880940 EX_ROW_EN[0] = 0x10
6989 22:10:43.883574 EX_ROW_EN[1] = 0x0
6990 22:10:43.884060 LP4Y_EN = 0x0
6991 22:10:43.886832 WORK_FSP = 0x1
6992 22:10:43.887297 WL = 0x5
6993 22:10:43.890248 RL = 0x5
6994 22:10:43.890746 BL = 0x2
6995 22:10:43.893301 RPST = 0x0
6996 22:10:43.893827 RD_PRE = 0x0
6997 22:10:43.897020 WR_PRE = 0x1
6998 22:10:43.897559 WR_PST = 0x1
6999 22:10:43.900006 DBI_WR = 0x0
7000 22:10:43.900490 DBI_RD = 0x0
7001 22:10:43.903379 OTF = 0x1
7002 22:10:43.906413 ===================================
7003 22:10:43.913280 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7004 22:10:43.913787 ==
7005 22:10:43.916512 Dram Type= 6, Freq= 0, CH_0, rank 0
7006 22:10:43.919760 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7007 22:10:43.920264 ==
7008 22:10:43.923339 [Duty_Offset_Calibration]
7009 22:10:43.923839 B0:0 B1:2 CA:1
7010 22:10:43.924129
7011 22:10:43.926365 [DutyScan_Calibration_Flow] k_type=0
7012 22:10:43.937914
7013 22:10:43.938402 ==CLK 0==
7014 22:10:43.941028 Final CLK duty delay cell = 0
7015 22:10:43.944406 [0] MAX Duty = 5156%(X100), DQS PI = 22
7016 22:10:43.947657 [0] MIN Duty = 4938%(X100), DQS PI = 52
7017 22:10:43.950777 [0] AVG Duty = 5047%(X100)
7018 22:10:43.951263
7019 22:10:43.953778 CH0 CLK Duty spec in!! Max-Min= 218%
7020 22:10:43.957699 [DutyScan_Calibration_Flow] ====Done====
7021 22:10:43.958184
7022 22:10:43.960886 [DutyScan_Calibration_Flow] k_type=1
7023 22:10:43.977619
7024 22:10:43.978094 ==DQS 0 ==
7025 22:10:43.980783 Final DQS duty delay cell = 0
7026 22:10:43.984673 [0] MAX Duty = 5156%(X100), DQS PI = 34
7027 22:10:43.987743 [0] MIN Duty = 5000%(X100), DQS PI = 10
7028 22:10:43.988129 [0] AVG Duty = 5078%(X100)
7029 22:10:43.991157
7030 22:10:43.991654 ==DQS 1 ==
7031 22:10:43.994783 Final DQS duty delay cell = 0
7032 22:10:43.997743 [0] MAX Duty = 5031%(X100), DQS PI = 4
7033 22:10:44.001205 [0] MIN Duty = 4907%(X100), DQS PI = 12
7034 22:10:44.001739 [0] AVG Duty = 4969%(X100)
7035 22:10:44.003968
7036 22:10:44.007883 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7037 22:10:44.008398
7038 22:10:44.011192 CH0 DQS 1 Duty spec in!! Max-Min= 124%
7039 22:10:44.014328 [DutyScan_Calibration_Flow] ====Done====
7040 22:10:44.014823
7041 22:10:44.017598 [DutyScan_Calibration_Flow] k_type=3
7042 22:10:44.034885
7043 22:10:44.035358 ==DQM 0 ==
7044 22:10:44.037948 Final DQM duty delay cell = 0
7045 22:10:44.041256 [0] MAX Duty = 5187%(X100), DQS PI = 22
7046 22:10:44.044792 [0] MIN Duty = 4907%(X100), DQS PI = 42
7047 22:10:44.047845 [0] AVG Duty = 5047%(X100)
7048 22:10:44.048326
7049 22:10:44.048592 ==DQM 1 ==
7050 22:10:44.051608 Final DQM duty delay cell = 0
7051 22:10:44.054753 [0] MAX Duty = 5031%(X100), DQS PI = 52
7052 22:10:44.057900 [0] MIN Duty = 4782%(X100), DQS PI = 14
7053 22:10:44.061253 [0] AVG Duty = 4906%(X100)
7054 22:10:44.061774
7055 22:10:44.064362 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7056 22:10:44.064742
7057 22:10:44.067940 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7058 22:10:44.071029 [DutyScan_Calibration_Flow] ====Done====
7059 22:10:44.071515
7060 22:10:44.074599 [DutyScan_Calibration_Flow] k_type=2
7061 22:10:44.091239
7062 22:10:44.091726 ==DQ 0 ==
7063 22:10:44.094404 Final DQ duty delay cell = 0
7064 22:10:44.097577 [0] MAX Duty = 5218%(X100), DQS PI = 18
7065 22:10:44.100828 [0] MIN Duty = 4938%(X100), DQS PI = 56
7066 22:10:44.101338 [0] AVG Duty = 5078%(X100)
7067 22:10:44.104523
7068 22:10:44.105002 ==DQ 1 ==
7069 22:10:44.107743 Final DQ duty delay cell = -4
7070 22:10:44.111269 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7071 22:10:44.114068 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7072 22:10:44.117909 [-4] AVG Duty = 4953%(X100)
7073 22:10:44.118352
7074 22:10:44.120862 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7075 22:10:44.121238
7076 22:10:44.124416 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7077 22:10:44.127957 [DutyScan_Calibration_Flow] ====Done====
7078 22:10:44.128358 ==
7079 22:10:44.131226 Dram Type= 6, Freq= 0, CH_1, rank 0
7080 22:10:44.134079 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7081 22:10:44.134465 ==
7082 22:10:44.137675 [Duty_Offset_Calibration]
7083 22:10:44.138049 B0:0 B1:4 CA:-5
7084 22:10:44.138319
7085 22:10:44.140943 [DutyScan_Calibration_Flow] k_type=0
7086 22:10:44.152142
7087 22:10:44.152641 ==CLK 0==
7088 22:10:44.155273 Final CLK duty delay cell = 0
7089 22:10:44.158601 [0] MAX Duty = 5156%(X100), DQS PI = 20
7090 22:10:44.161731 [0] MIN Duty = 4875%(X100), DQS PI = 50
7091 22:10:44.165179 [0] AVG Duty = 5015%(X100)
7092 22:10:44.165617
7093 22:10:44.168420 CH1 CLK Duty spec in!! Max-Min= 281%
7094 22:10:44.172144 [DutyScan_Calibration_Flow] ====Done====
7095 22:10:44.172643
7096 22:10:44.175098 [DutyScan_Calibration_Flow] k_type=1
7097 22:10:44.190972
7098 22:10:44.191460 ==DQS 0 ==
7099 22:10:44.194807 Final DQS duty delay cell = 0
7100 22:10:44.197249 [0] MAX Duty = 5156%(X100), DQS PI = 18
7101 22:10:44.200582 [0] MIN Duty = 4844%(X100), DQS PI = 44
7102 22:10:44.204400 [0] AVG Duty = 5000%(X100)
7103 22:10:44.204882
7104 22:10:44.205156 ==DQS 1 ==
7105 22:10:44.207506 Final DQS duty delay cell = -4
7106 22:10:44.210845 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7107 22:10:44.213529 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7108 22:10:44.217032 [-4] AVG Duty = 4922%(X100)
7109 22:10:44.217557
7110 22:10:44.220803 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7111 22:10:44.221348
7112 22:10:44.223636 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7113 22:10:44.226900 [DutyScan_Calibration_Flow] ====Done====
7114 22:10:44.227279
7115 22:10:44.230182 [DutyScan_Calibration_Flow] k_type=3
7116 22:10:44.246294
7117 22:10:44.246772 ==DQM 0 ==
7118 22:10:44.249701 Final DQM duty delay cell = -4
7119 22:10:44.252926 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7120 22:10:44.256740 [-4] MIN Duty = 4751%(X100), DQS PI = 46
7121 22:10:44.259650 [-4] AVG Duty = 4906%(X100)
7122 22:10:44.260136
7123 22:10:44.260409 ==DQM 1 ==
7124 22:10:44.262589 Final DQM duty delay cell = -4
7125 22:10:44.266168 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7126 22:10:44.269484 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7127 22:10:44.273142 [-4] AVG Duty = 4984%(X100)
7128 22:10:44.273672
7129 22:10:44.276192 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7130 22:10:44.276698
7131 22:10:44.279652 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7132 22:10:44.282988 [DutyScan_Calibration_Flow] ====Done====
7133 22:10:44.283461
7134 22:10:44.286189 [DutyScan_Calibration_Flow] k_type=2
7135 22:10:44.304058
7136 22:10:44.304529 ==DQ 0 ==
7137 22:10:44.307587 Final DQ duty delay cell = 0
7138 22:10:44.310818 [0] MAX Duty = 5093%(X100), DQS PI = 20
7139 22:10:44.313606 [0] MIN Duty = 4938%(X100), DQS PI = 48
7140 22:10:44.314113 [0] AVG Duty = 5015%(X100)
7141 22:10:44.316969
7142 22:10:44.317393 ==DQ 1 ==
7143 22:10:44.320583 Final DQ duty delay cell = 0
7144 22:10:44.323737 [0] MAX Duty = 5031%(X100), DQS PI = 4
7145 22:10:44.327045 [0] MIN Duty = 4907%(X100), DQS PI = 14
7146 22:10:44.327533 [0] AVG Duty = 4969%(X100)
7147 22:10:44.327816
7148 22:10:44.333759 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7149 22:10:44.334146
7150 22:10:44.336967 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7151 22:10:44.340813 [DutyScan_Calibration_Flow] ====Done====
7152 22:10:44.343295 nWR fixed to 30
7153 22:10:44.343724 [ModeRegInit_LP4] CH0 RK0
7154 22:10:44.346817 [ModeRegInit_LP4] CH0 RK1
7155 22:10:44.350660 [ModeRegInit_LP4] CH1 RK0
7156 22:10:44.354080 [ModeRegInit_LP4] CH1 RK1
7157 22:10:44.354565 match AC timing 4
7158 22:10:44.357229 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7159 22:10:44.363664 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7160 22:10:44.367354 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7161 22:10:44.373739 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7162 22:10:44.377291 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7163 22:10:44.377945 [MiockJmeterHQA]
7164 22:10:44.378249
7165 22:10:44.380494 [DramcMiockJmeter] u1RxGatingPI = 0
7166 22:10:44.383742 0 : 4363, 4137
7167 22:10:44.384240 4 : 4252, 4027
7168 22:10:44.384519 8 : 4363, 4137
7169 22:10:44.386956 12 : 4252, 4027
7170 22:10:44.387451 16 : 4252, 4027
7171 22:10:44.390504 20 : 4363, 4137
7172 22:10:44.390991 24 : 4253, 4027
7173 22:10:44.394021 28 : 4252, 4026
7174 22:10:44.394505 32 : 4252, 4027
7175 22:10:44.397195 36 : 4255, 4029
7176 22:10:44.397727 40 : 4363, 4137
7177 22:10:44.398021 44 : 4252, 4027
7178 22:10:44.400415 48 : 4363, 4138
7179 22:10:44.400904 52 : 4252, 4027
7180 22:10:44.404132 56 : 4252, 4027
7181 22:10:44.404625 60 : 4252, 4027
7182 22:10:44.406915 64 : 4363, 4139
7183 22:10:44.407339 68 : 4253, 4027
7184 22:10:44.410390 72 : 4361, 4138
7185 22:10:44.410893 76 : 4250, 4026
7186 22:10:44.411196 80 : 4249, 4027
7187 22:10:44.413574 84 : 4250, 4027
7188 22:10:44.413962 88 : 4252, 4029
7189 22:10:44.416832 92 : 4250, 4027
7190 22:10:44.417221 96 : 4250, 4026
7191 22:10:44.420459 100 : 4363, 2298
7192 22:10:44.420951 104 : 4360, 0
7193 22:10:44.421239 108 : 4252, 0
7194 22:10:44.423560 112 : 4363, 0
7195 22:10:44.424060 116 : 4361, 0
7196 22:10:44.427009 120 : 4363, 0
7197 22:10:44.427478 124 : 4253, 0
7198 22:10:44.427770 128 : 4360, 0
7199 22:10:44.430010 132 : 4250, 0
7200 22:10:44.430402 136 : 4250, 0
7201 22:10:44.433845 140 : 4250, 0
7202 22:10:44.434342 144 : 4250, 0
7203 22:10:44.434625 148 : 4252, 0
7204 22:10:44.437099 152 : 4360, 0
7205 22:10:44.437531 156 : 4250, 0
7206 22:10:44.437810 160 : 4250, 0
7207 22:10:44.440128 164 : 4250, 0
7208 22:10:44.440622 168 : 4361, 0
7209 22:10:44.443774 172 : 4361, 0
7210 22:10:44.444307 176 : 4250, 0
7211 22:10:44.444604 180 : 4250, 0
7212 22:10:44.446955 184 : 4250, 0
7213 22:10:44.447343 188 : 4252, 0
7214 22:10:44.450191 192 : 4249, 0
7215 22:10:44.450670 196 : 4250, 0
7216 22:10:44.450952 200 : 4252, 0
7217 22:10:44.453421 204 : 4250, 0
7218 22:10:44.453777 208 : 4250, 0
7219 22:10:44.456746 212 : 4253, 0
7220 22:10:44.457207 216 : 4250, 0
7221 22:10:44.457499 220 : 4361, 589
7222 22:10:44.460024 224 : 4253, 3997
7223 22:10:44.460463 228 : 4250, 4027
7224 22:10:44.463553 232 : 4252, 4029
7225 22:10:44.463934 236 : 4249, 4027
7226 22:10:44.467052 240 : 4250, 4027
7227 22:10:44.467512 244 : 4252, 4029
7228 22:10:44.469953 248 : 4249, 4027
7229 22:10:44.470414 252 : 4360, 4137
7230 22:10:44.473701 256 : 4363, 4140
7231 22:10:44.474196 260 : 4250, 4027
7232 22:10:44.474477 264 : 4363, 4140
7233 22:10:44.476493 268 : 4360, 4138
7234 22:10:44.476863 272 : 4250, 4027
7235 22:10:44.479948 276 : 4250, 4027
7236 22:10:44.480383 280 : 4252, 4030
7237 22:10:44.483006 284 : 4250, 4026
7238 22:10:44.483395 288 : 4250, 4027
7239 22:10:44.486573 292 : 4250, 4027
7240 22:10:44.487079 296 : 4252, 4029
7241 22:10:44.489410 300 : 4250, 4026
7242 22:10:44.489802 304 : 4360, 4137
7243 22:10:44.493479 308 : 4360, 4137
7244 22:10:44.494039 312 : 4249, 4027
7245 22:10:44.496473 316 : 4363, 4140
7246 22:10:44.496880 320 : 4360, 4137
7247 22:10:44.499937 324 : 4250, 4027
7248 22:10:44.500440 328 : 4250, 4026
7249 22:10:44.500701 332 : 4253, 4029
7250 22:10:44.503245 336 : 4250, 3961
7251 22:10:44.503750 340 : 4249, 1915
7252 22:10:44.504035
7253 22:10:44.506418 MIOCK jitter meter ch=0
7254 22:10:44.506896
7255 22:10:44.509651 1T = (340-104) = 236 dly cells
7256 22:10:44.515918 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7257 22:10:44.516438 ==
7258 22:10:44.519541 Dram Type= 6, Freq= 0, CH_0, rank 0
7259 22:10:44.523156 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7260 22:10:44.523618 ==
7261 22:10:44.529713 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7262 22:10:44.532894 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7263 22:10:44.536204 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7264 22:10:44.542897 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7265 22:10:44.551353 [CA 0] Center 42 (12~73) winsize 62
7266 22:10:44.554820 [CA 1] Center 42 (12~73) winsize 62
7267 22:10:44.557843 [CA 2] Center 39 (9~69) winsize 61
7268 22:10:44.561091 [CA 3] Center 38 (9~68) winsize 60
7269 22:10:44.564101 [CA 4] Center 37 (7~67) winsize 61
7270 22:10:44.567711 [CA 5] Center 36 (6~66) winsize 61
7271 22:10:44.568194
7272 22:10:44.570752 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7273 22:10:44.571189
7274 22:10:44.574529 [CATrainingPosCal] consider 1 rank data
7275 22:10:44.577570 u2DelayCellTimex100 = 275/100 ps
7276 22:10:44.584438 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7277 22:10:44.587848 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7278 22:10:44.591535 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7279 22:10:44.594607 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7280 22:10:44.598020 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7281 22:10:44.600991 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7282 22:10:44.601499
7283 22:10:44.604053 CA PerBit enable=1, Macro0, CA PI delay=36
7284 22:10:44.604544
7285 22:10:44.607439 [CBTSetCACLKResult] CA Dly = 36
7286 22:10:44.610761 CS Dly: 10 (0~41)
7287 22:10:44.614151 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7288 22:10:44.617153 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7289 22:10:44.617555 ==
7290 22:10:44.621082 Dram Type= 6, Freq= 0, CH_0, rank 1
7291 22:10:44.627647 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7292 22:10:44.628129 ==
7293 22:10:44.630976 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7294 22:10:44.634109 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7295 22:10:44.640462 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7296 22:10:44.647480 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7297 22:10:44.653863 [CA 0] Center 42 (12~73) winsize 62
7298 22:10:44.657253 [CA 1] Center 41 (11~72) winsize 62
7299 22:10:44.660346 [CA 2] Center 38 (8~68) winsize 61
7300 22:10:44.664197 [CA 3] Center 37 (7~67) winsize 61
7301 22:10:44.667028 [CA 4] Center 35 (5~65) winsize 61
7302 22:10:44.670712 [CA 5] Center 35 (5~66) winsize 62
7303 22:10:44.671200
7304 22:10:44.674231 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7305 22:10:44.674660
7306 22:10:44.677296 [CATrainingPosCal] consider 2 rank data
7307 22:10:44.680377 u2DelayCellTimex100 = 275/100 ps
7308 22:10:44.684000 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7309 22:10:44.690124 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7310 22:10:44.693695 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7311 22:10:44.697160 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7312 22:10:44.700512 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7313 22:10:44.703828 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7314 22:10:44.704278
7315 22:10:44.707306 CA PerBit enable=1, Macro0, CA PI delay=36
7316 22:10:44.707761
7317 22:10:44.710459 [CBTSetCACLKResult] CA Dly = 36
7318 22:10:44.713702 CS Dly: 11 (0~43)
7319 22:10:44.716697 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7320 22:10:44.719974 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7321 22:10:44.720379
7322 22:10:44.723453 ----->DramcWriteLeveling(PI) begin...
7323 22:10:44.723878 ==
7324 22:10:44.727122 Dram Type= 6, Freq= 0, CH_0, rank 0
7325 22:10:44.730152 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7326 22:10:44.733657 ==
7327 22:10:44.736792 Write leveling (Byte 0): 29 => 29
7328 22:10:44.737244 Write leveling (Byte 1): 24 => 24
7329 22:10:44.740110 DramcWriteLeveling(PI) end<-----
7330 22:10:44.740448
7331 22:10:44.740688 ==
7332 22:10:44.743358 Dram Type= 6, Freq= 0, CH_0, rank 0
7333 22:10:44.750205 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7334 22:10:44.750550 ==
7335 22:10:44.753242 [Gating] SW mode calibration
7336 22:10:44.760042 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7337 22:10:44.763677 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7338 22:10:44.769883 0 12 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7339 22:10:44.773478 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7340 22:10:44.776861 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7341 22:10:44.783367 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7342 22:10:44.786481 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7343 22:10:44.789735 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7344 22:10:44.796142 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7345 22:10:44.800121 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7346 22:10:44.802901 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
7347 22:10:44.809751 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
7348 22:10:44.813079 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7349 22:10:44.816535 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7350 22:10:44.822720 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7351 22:10:44.826609 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7352 22:10:44.830075 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7353 22:10:44.836254 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7354 22:10:44.839366 0 14 0 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7355 22:10:44.842858 0 14 4 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
7356 22:10:44.849118 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7357 22:10:44.852603 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7358 22:10:44.856097 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7359 22:10:44.859358 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7360 22:10:44.866679 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7361 22:10:44.869496 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7362 22:10:44.872950 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7363 22:10:44.879024 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7364 22:10:44.883022 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7365 22:10:44.886129 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7366 22:10:44.892786 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7367 22:10:44.896359 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7368 22:10:44.899355 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7369 22:10:44.905673 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7370 22:10:44.908761 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7371 22:10:44.912563 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7372 22:10:44.918937 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7373 22:10:44.922194 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7374 22:10:44.925977 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7375 22:10:44.932400 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7376 22:10:44.935629 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7377 22:10:44.938951 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7378 22:10:44.945641 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7379 22:10:44.948764 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7380 22:10:44.951982 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7381 22:10:44.955734 Total UI for P1: 0, mck2ui 16
7382 22:10:44.958789 best dqsien dly found for B0: ( 1, 1, 0)
7383 22:10:44.961971 Total UI for P1: 0, mck2ui 16
7384 22:10:44.965077 best dqsien dly found for B1: ( 1, 1, 4)
7385 22:10:44.968330 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7386 22:10:44.972020 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7387 22:10:44.972505
7388 22:10:44.977908 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7389 22:10:44.981622 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7390 22:10:44.982029 [Gating] SW calibration Done
7391 22:10:44.984627 ==
7392 22:10:44.985015 Dram Type= 6, Freq= 0, CH_0, rank 0
7393 22:10:44.991750 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7394 22:10:44.992251 ==
7395 22:10:44.992536 RX Vref Scan: 0
7396 22:10:44.992777
7397 22:10:44.995493 RX Vref 0 -> 0, step: 1
7398 22:10:44.995978
7399 22:10:44.998349 RX Delay 0 -> 252, step: 8
7400 22:10:45.001848 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7401 22:10:45.004993 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7402 22:10:45.008625 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7403 22:10:45.014688 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7404 22:10:45.017920 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7405 22:10:45.021412 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7406 22:10:45.024990 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7407 22:10:45.028648 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7408 22:10:45.034949 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7409 22:10:45.038635 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7410 22:10:45.041694 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7411 22:10:45.044728 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7412 22:10:45.048232 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7413 22:10:45.054722 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7414 22:10:45.057874 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7415 22:10:45.061374 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7416 22:10:45.061854 ==
7417 22:10:45.064879 Dram Type= 6, Freq= 0, CH_0, rank 0
7418 22:10:45.067896 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7419 22:10:45.071150 ==
7420 22:10:45.071640 DQS Delay:
7421 22:10:45.071914 DQS0 = 0, DQS1 = 0
7422 22:10:45.074407 DQM Delay:
7423 22:10:45.074898 DQM0 = 130, DQM1 = 124
7424 22:10:45.077359 DQ Delay:
7425 22:10:45.081423 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7426 22:10:45.084097 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7427 22:10:45.087827 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7428 22:10:45.090844 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7429 22:10:45.091338
7430 22:10:45.091606
7431 22:10:45.091843 ==
7432 22:10:45.094371 Dram Type= 6, Freq= 0, CH_0, rank 0
7433 22:10:45.097774 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7434 22:10:45.098431 ==
7435 22:10:45.098757
7436 22:10:45.101164
7437 22:10:45.101708 TX Vref Scan disable
7438 22:10:45.104613 == TX Byte 0 ==
7439 22:10:45.107569 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7440 22:10:45.110984 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7441 22:10:45.114460 == TX Byte 1 ==
7442 22:10:45.117269 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7443 22:10:45.121025 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7444 22:10:45.121465 ==
7445 22:10:45.124244 Dram Type= 6, Freq= 0, CH_0, rank 0
7446 22:10:45.130539 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7447 22:10:45.131002 ==
7448 22:10:45.144232
7449 22:10:45.147490 TX Vref early break, caculate TX vref
7450 22:10:45.150689 TX Vref=16, minBit 10, minWin=22, winSum=373
7451 22:10:45.153578 TX Vref=18, minBit 4, minWin=23, winSum=380
7452 22:10:45.156689 TX Vref=20, minBit 6, minWin=24, winSum=395
7453 22:10:45.160677 TX Vref=22, minBit 4, minWin=24, winSum=401
7454 22:10:45.163801 TX Vref=24, minBit 8, minWin=24, winSum=409
7455 22:10:45.170251 TX Vref=26, minBit 7, minWin=25, winSum=415
7456 22:10:45.173302 TX Vref=28, minBit 1, minWin=25, winSum=416
7457 22:10:45.177034 TX Vref=30, minBit 0, minWin=25, winSum=411
7458 22:10:45.181100 TX Vref=32, minBit 6, minWin=24, winSum=399
7459 22:10:45.183857 TX Vref=34, minBit 3, minWin=24, winSum=396
7460 22:10:45.187059 TX Vref=36, minBit 3, minWin=23, winSum=384
7461 22:10:45.193657 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 28
7462 22:10:45.194147
7463 22:10:45.196764 Final TX Range 0 Vref 28
7464 22:10:45.197143
7465 22:10:45.197437 ==
7466 22:10:45.199901 Dram Type= 6, Freq= 0, CH_0, rank 0
7467 22:10:45.203339 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7468 22:10:45.203713 ==
7469 22:10:45.203980
7470 22:10:45.206504
7471 22:10:45.206845 TX Vref Scan disable
7472 22:10:45.213433 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7473 22:10:45.213920 == TX Byte 0 ==
7474 22:10:45.216442 u2DelayCellOfst[0]=10 cells (3 PI)
7475 22:10:45.219645 u2DelayCellOfst[1]=17 cells (5 PI)
7476 22:10:45.223609 u2DelayCellOfst[2]=14 cells (4 PI)
7477 22:10:45.226595 u2DelayCellOfst[3]=10 cells (3 PI)
7478 22:10:45.229643 u2DelayCellOfst[4]=7 cells (2 PI)
7479 22:10:45.233260 u2DelayCellOfst[5]=0 cells (0 PI)
7480 22:10:45.236578 u2DelayCellOfst[6]=17 cells (5 PI)
7481 22:10:45.239673 u2DelayCellOfst[7]=17 cells (5 PI)
7482 22:10:45.243404 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7483 22:10:45.246057 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7484 22:10:45.249632 == TX Byte 1 ==
7485 22:10:45.253163 u2DelayCellOfst[8]=3 cells (1 PI)
7486 22:10:45.256287 u2DelayCellOfst[9]=0 cells (0 PI)
7487 22:10:45.260162 u2DelayCellOfst[10]=7 cells (2 PI)
7488 22:10:45.260620 u2DelayCellOfst[11]=3 cells (1 PI)
7489 22:10:45.263240 u2DelayCellOfst[12]=14 cells (4 PI)
7490 22:10:45.265920 u2DelayCellOfst[13]=14 cells (4 PI)
7491 22:10:45.269765 u2DelayCellOfst[14]=17 cells (5 PI)
7492 22:10:45.273094 u2DelayCellOfst[15]=14 cells (4 PI)
7493 22:10:45.279280 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
7494 22:10:45.282864 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
7495 22:10:45.283267 DramC Write-DBI on
7496 22:10:45.286100 ==
7497 22:10:45.286483 Dram Type= 6, Freq= 0, CH_0, rank 0
7498 22:10:45.292985 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7499 22:10:45.293497 ==
7500 22:10:45.293792
7501 22:10:45.294099
7502 22:10:45.296427 TX Vref Scan disable
7503 22:10:45.296914 == TX Byte 0 ==
7504 22:10:45.303114 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7505 22:10:45.303627 == TX Byte 1 ==
7506 22:10:45.306405 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
7507 22:10:45.309660 DramC Write-DBI off
7508 22:10:45.310146
7509 22:10:45.310417 [DATLAT]
7510 22:10:45.312758 Freq=1600, CH0 RK0
7511 22:10:45.313240
7512 22:10:45.313632 DATLAT Default: 0xf
7513 22:10:45.316104 0, 0xFFFF, sum = 0
7514 22:10:45.316493 1, 0xFFFF, sum = 0
7515 22:10:45.318902 2, 0xFFFF, sum = 0
7516 22:10:45.319200 3, 0xFFFF, sum = 0
7517 22:10:45.322408 4, 0xFFFF, sum = 0
7518 22:10:45.322763 5, 0xFFFF, sum = 0
7519 22:10:45.325655 6, 0xFFFF, sum = 0
7520 22:10:45.326010 7, 0xFFFF, sum = 0
7521 22:10:45.329468 8, 0xFFFF, sum = 0
7522 22:10:45.329914 9, 0xFFFF, sum = 0
7523 22:10:45.332418 10, 0xFFFF, sum = 0
7524 22:10:45.335888 11, 0xFFFF, sum = 0
7525 22:10:45.336383 12, 0x8BFF, sum = 0
7526 22:10:45.339046 13, 0x0, sum = 1
7527 22:10:45.339531 14, 0x0, sum = 2
7528 22:10:45.342469 15, 0x0, sum = 3
7529 22:10:45.342865 16, 0x0, sum = 4
7530 22:10:45.343143 best_step = 14
7531 22:10:45.343384
7532 22:10:45.345619 ==
7533 22:10:45.349113 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 22:10:45.352313 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7535 22:10:45.352709 ==
7536 22:10:45.353013 RX Vref Scan: 1
7537 22:10:45.353267
7538 22:10:45.356093 Set Vref Range= 24 -> 127
7539 22:10:45.356578
7540 22:10:45.358762 RX Vref 24 -> 127, step: 1
7541 22:10:45.359213
7542 22:10:45.361979 RX Delay 11 -> 252, step: 4
7543 22:10:45.362363
7544 22:10:45.365194 Set Vref, RX VrefLevel [Byte0]: 24
7545 22:10:45.369005 [Byte1]: 24
7546 22:10:45.369529
7547 22:10:45.372258 Set Vref, RX VrefLevel [Byte0]: 25
7548 22:10:45.376045 [Byte1]: 25
7549 22:10:45.376491
7550 22:10:45.378682 Set Vref, RX VrefLevel [Byte0]: 26
7551 22:10:45.381956 [Byte1]: 26
7552 22:10:45.386161
7553 22:10:45.386578 Set Vref, RX VrefLevel [Byte0]: 27
7554 22:10:45.389297 [Byte1]: 27
7555 22:10:45.393674
7556 22:10:45.394171 Set Vref, RX VrefLevel [Byte0]: 28
7557 22:10:45.396756 [Byte1]: 28
7558 22:10:45.401101
7559 22:10:45.401682 Set Vref, RX VrefLevel [Byte0]: 29
7560 22:10:45.404255 [Byte1]: 29
7561 22:10:45.408695
7562 22:10:45.409088 Set Vref, RX VrefLevel [Byte0]: 30
7563 22:10:45.411963 [Byte1]: 30
7564 22:10:45.415983
7565 22:10:45.416363 Set Vref, RX VrefLevel [Byte0]: 31
7566 22:10:45.419416 [Byte1]: 31
7567 22:10:45.423775
7568 22:10:45.424235 Set Vref, RX VrefLevel [Byte0]: 32
7569 22:10:45.426902 [Byte1]: 32
7570 22:10:45.431558
7571 22:10:45.431913 Set Vref, RX VrefLevel [Byte0]: 33
7572 22:10:45.434471 [Byte1]: 33
7573 22:10:45.439544
7574 22:10:45.439898 Set Vref, RX VrefLevel [Byte0]: 34
7575 22:10:45.442118 [Byte1]: 34
7576 22:10:45.446331
7577 22:10:45.446754 Set Vref, RX VrefLevel [Byte0]: 35
7578 22:10:45.449924 [Byte1]: 35
7579 22:10:45.454497
7580 22:10:45.454854 Set Vref, RX VrefLevel [Byte0]: 36
7581 22:10:45.457222 [Byte1]: 36
7582 22:10:45.461734
7583 22:10:45.462134 Set Vref, RX VrefLevel [Byte0]: 37
7584 22:10:45.464725 [Byte1]: 37
7585 22:10:45.469631
7586 22:10:45.470062 Set Vref, RX VrefLevel [Byte0]: 38
7587 22:10:45.472671 [Byte1]: 38
7588 22:10:45.477205
7589 22:10:45.477679 Set Vref, RX VrefLevel [Byte0]: 39
7590 22:10:45.480003 [Byte1]: 39
7591 22:10:45.484780
7592 22:10:45.485300 Set Vref, RX VrefLevel [Byte0]: 40
7593 22:10:45.488298 [Byte1]: 40
7594 22:10:45.492305
7595 22:10:45.492805 Set Vref, RX VrefLevel [Byte0]: 41
7596 22:10:45.495457 [Byte1]: 41
7597 22:10:45.499633
7598 22:10:45.499988 Set Vref, RX VrefLevel [Byte0]: 42
7599 22:10:45.503570 [Byte1]: 42
7600 22:10:45.507646
7601 22:10:45.508101 Set Vref, RX VrefLevel [Byte0]: 43
7602 22:10:45.510977 [Byte1]: 43
7603 22:10:45.515684
7604 22:10:45.516165 Set Vref, RX VrefLevel [Byte0]: 44
7605 22:10:45.518528 [Byte1]: 44
7606 22:10:45.522755
7607 22:10:45.523141 Set Vref, RX VrefLevel [Byte0]: 45
7608 22:10:45.526084 [Byte1]: 45
7609 22:10:45.530358
7610 22:10:45.530710 Set Vref, RX VrefLevel [Byte0]: 46
7611 22:10:45.533372 [Byte1]: 46
7612 22:10:45.537717
7613 22:10:45.538126 Set Vref, RX VrefLevel [Byte0]: 47
7614 22:10:45.541532 [Byte1]: 47
7615 22:10:45.545611
7616 22:10:45.546020 Set Vref, RX VrefLevel [Byte0]: 48
7617 22:10:45.549162 [Byte1]: 48
7618 22:10:45.552816
7619 22:10:45.553163 Set Vref, RX VrefLevel [Byte0]: 49
7620 22:10:45.556177 [Byte1]: 49
7621 22:10:45.561074
7622 22:10:45.561586 Set Vref, RX VrefLevel [Byte0]: 50
7623 22:10:45.564322 [Byte1]: 50
7624 22:10:45.567980
7625 22:10:45.568410 Set Vref, RX VrefLevel [Byte0]: 51
7626 22:10:45.571629 [Byte1]: 51
7627 22:10:45.576128
7628 22:10:45.576540 Set Vref, RX VrefLevel [Byte0]: 52
7629 22:10:45.579525 [Byte1]: 52
7630 22:10:45.583585
7631 22:10:45.584097 Set Vref, RX VrefLevel [Byte0]: 53
7632 22:10:45.587336 [Byte1]: 53
7633 22:10:45.591515
7634 22:10:45.591980 Set Vref, RX VrefLevel [Byte0]: 54
7635 22:10:45.595053 [Byte1]: 54
7636 22:10:45.598872
7637 22:10:45.599223 Set Vref, RX VrefLevel [Byte0]: 55
7638 22:10:45.602248 [Byte1]: 55
7639 22:10:45.606763
7640 22:10:45.607218 Set Vref, RX VrefLevel [Byte0]: 56
7641 22:10:45.609810 [Byte1]: 56
7642 22:10:45.614136
7643 22:10:45.614663 Set Vref, RX VrefLevel [Byte0]: 57
7644 22:10:45.617987 [Byte1]: 57
7645 22:10:45.621547
7646 22:10:45.621943 Set Vref, RX VrefLevel [Byte0]: 58
7647 22:10:45.624924 [Byte1]: 58
7648 22:10:45.629213
7649 22:10:45.629612 Set Vref, RX VrefLevel [Byte0]: 59
7650 22:10:45.632297 [Byte1]: 59
7651 22:10:45.636892
7652 22:10:45.637380 Set Vref, RX VrefLevel [Byte0]: 60
7653 22:10:45.640304 [Byte1]: 60
7654 22:10:45.644612
7655 22:10:45.645093 Set Vref, RX VrefLevel [Byte0]: 61
7656 22:10:45.647936 [Byte1]: 61
7657 22:10:45.652004
7658 22:10:45.652403 Set Vref, RX VrefLevel [Byte0]: 62
7659 22:10:45.655424 [Byte1]: 62
7660 22:10:45.659588
7661 22:10:45.660027 Set Vref, RX VrefLevel [Byte0]: 63
7662 22:10:45.663734 [Byte1]: 63
7663 22:10:45.667360
7664 22:10:45.667718 Set Vref, RX VrefLevel [Byte0]: 64
7665 22:10:45.670663 [Byte1]: 64
7666 22:10:45.675416
7667 22:10:45.675929 Set Vref, RX VrefLevel [Byte0]: 65
7668 22:10:45.678729 [Byte1]: 65
7669 22:10:45.682393
7670 22:10:45.682741 Set Vref, RX VrefLevel [Byte0]: 66
7671 22:10:45.685634 [Byte1]: 66
7672 22:10:45.690619
7673 22:10:45.691071 Set Vref, RX VrefLevel [Byte0]: 67
7674 22:10:45.693385 [Byte1]: 67
7675 22:10:45.697695
7676 22:10:45.698041 Set Vref, RX VrefLevel [Byte0]: 68
7677 22:10:45.700923 [Byte1]: 68
7678 22:10:45.705757
7679 22:10:45.706227 Set Vref, RX VrefLevel [Byte0]: 69
7680 22:10:45.708938 [Byte1]: 69
7681 22:10:45.713474
7682 22:10:45.713926 Final RX Vref Byte 0 = 52 to rank0
7683 22:10:45.716641 Final RX Vref Byte 1 = 54 to rank0
7684 22:10:45.719466 Final RX Vref Byte 0 = 52 to rank1
7685 22:10:45.723504 Final RX Vref Byte 1 = 54 to rank1==
7686 22:10:45.726592 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 22:10:45.733202 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7688 22:10:45.733750 ==
7689 22:10:45.734034 DQS Delay:
7690 22:10:45.734273 DQS0 = 0, DQS1 = 0
7691 22:10:45.736399 DQM Delay:
7692 22:10:45.736860 DQM0 = 126, DQM1 = 120
7693 22:10:45.740173 DQ Delay:
7694 22:10:45.743210 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7695 22:10:45.746138 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7696 22:10:45.749186 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7697 22:10:45.752854 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7698 22:10:45.753392
7699 22:10:45.753734
7700 22:10:45.754020
7701 22:10:45.756603 [DramC_TX_OE_Calibration] TA2
7702 22:10:45.759891 Original DQ_B0 (3 6) =30, OEN = 27
7703 22:10:45.762973 Original DQ_B1 (3 6) =30, OEN = 27
7704 22:10:45.765823 24, 0x0, End_B0=24 End_B1=24
7705 22:10:45.766243 25, 0x0, End_B0=25 End_B1=25
7706 22:10:45.769586 26, 0x0, End_B0=26 End_B1=26
7707 22:10:45.773096 27, 0x0, End_B0=27 End_B1=27
7708 22:10:45.776379 28, 0x0, End_B0=28 End_B1=28
7709 22:10:45.776769 29, 0x0, End_B0=29 End_B1=29
7710 22:10:45.779270 30, 0x0, End_B0=30 End_B1=30
7711 22:10:45.782530 31, 0x4141, End_B0=30 End_B1=30
7712 22:10:45.786168 Byte0 end_step=30 best_step=27
7713 22:10:45.789871 Byte1 end_step=30 best_step=27
7714 22:10:45.792985 Byte0 TX OE(2T, 0.5T) = (3, 3)
7715 22:10:45.793487 Byte1 TX OE(2T, 0.5T) = (3, 3)
7716 22:10:45.796273
7717 22:10:45.796625
7718 22:10:45.802753 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7719 22:10:45.806386 CH0 RK0: MR19=303, MR18=1E1E
7720 22:10:45.812644 CH0_RK0: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
7721 22:10:45.813089
7722 22:10:45.815991 ----->DramcWriteLeveling(PI) begin...
7723 22:10:45.816515 ==
7724 22:10:45.819340 Dram Type= 6, Freq= 0, CH_0, rank 1
7725 22:10:45.822828 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7726 22:10:45.823220 ==
7727 22:10:45.825985 Write leveling (Byte 0): 30 => 30
7728 22:10:45.829038 Write leveling (Byte 1): 25 => 25
7729 22:10:45.832377 DramcWriteLeveling(PI) end<-----
7730 22:10:45.832763
7731 22:10:45.833086 ==
7732 22:10:45.835814 Dram Type= 6, Freq= 0, CH_0, rank 1
7733 22:10:45.839462 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7734 22:10:45.839921 ==
7735 22:10:45.842548 [Gating] SW mode calibration
7736 22:10:45.849069 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7737 22:10:45.855973 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7738 22:10:45.859720 0 12 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7739 22:10:45.862528 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7740 22:10:45.869287 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7741 22:10:45.872320 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7742 22:10:45.875630 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7743 22:10:45.882096 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7744 22:10:45.885504 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7745 22:10:45.888674 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7746 22:10:45.894974 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 1)
7747 22:10:45.898271 0 13 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
7748 22:10:45.901649 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7749 22:10:45.908657 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7750 22:10:45.911905 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7751 22:10:45.915063 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7752 22:10:45.921909 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7753 22:10:45.924874 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7754 22:10:45.928035 0 14 0 | B1->B0 | 2323 4444 | 0 1 | (0 0) (0 0)
7755 22:10:45.934953 0 14 4 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7756 22:10:45.938097 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7757 22:10:45.941058 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7758 22:10:45.948088 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7759 22:10:45.951617 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7760 22:10:45.954966 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7761 22:10:45.961250 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7762 22:10:45.964689 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7763 22:10:45.968103 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7764 22:10:45.974960 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7765 22:10:45.978067 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 22:10:45.981147 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 22:10:45.988022 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7768 22:10:45.991435 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7769 22:10:45.994929 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7770 22:10:46.001683 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7771 22:10:46.004931 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7772 22:10:46.008001 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7773 22:10:46.014662 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7774 22:10:46.017685 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7775 22:10:46.021230 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7776 22:10:46.028095 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7777 22:10:46.031487 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7778 22:10:46.034838 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7779 22:10:46.040956 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7780 22:10:46.041405 Total UI for P1: 0, mck2ui 16
7781 22:10:46.044632 best dqsien dly found for B0: ( 1, 0, 30)
7782 22:10:46.050959 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7783 22:10:46.054552 Total UI for P1: 0, mck2ui 16
7784 22:10:46.057725 best dqsien dly found for B1: ( 1, 1, 2)
7785 22:10:46.061277 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7786 22:10:46.065031 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7787 22:10:46.065528
7788 22:10:46.067899 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7789 22:10:46.071010 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7790 22:10:46.074002 [Gating] SW calibration Done
7791 22:10:46.074374 ==
7792 22:10:46.077892 Dram Type= 6, Freq= 0, CH_0, rank 1
7793 22:10:46.080884 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7794 22:10:46.081380 ==
7795 22:10:46.084604 RX Vref Scan: 0
7796 22:10:46.084956
7797 22:10:46.087663 RX Vref 0 -> 0, step: 1
7798 22:10:46.088015
7799 22:10:46.088267 RX Delay 0 -> 252, step: 8
7800 22:10:46.094698 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7801 22:10:46.097630 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7802 22:10:46.101345 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7803 22:10:46.104110 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7804 22:10:46.107465 iDelay=200, Bit 4, Center 135 (72 ~ 199) 128
7805 22:10:46.114271 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7806 22:10:46.117271 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7807 22:10:46.120407 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7808 22:10:46.123543 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7809 22:10:46.127305 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7810 22:10:46.133895 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7811 22:10:46.137249 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7812 22:10:46.140362 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7813 22:10:46.143839 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7814 22:10:46.147331 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7815 22:10:46.153751 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7816 22:10:46.154114 ==
7817 22:10:46.157444 Dram Type= 6, Freq= 0, CH_0, rank 1
7818 22:10:46.160479 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7819 22:10:46.160983 ==
7820 22:10:46.161251 DQS Delay:
7821 22:10:46.163424 DQS0 = 0, DQS1 = 0
7822 22:10:46.163682 DQM Delay:
7823 22:10:46.166722 DQM0 = 130, DQM1 = 123
7824 22:10:46.167083 DQ Delay:
7825 22:10:46.170647 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7826 22:10:46.173816 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7827 22:10:46.177405 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7828 22:10:46.180383 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7829 22:10:46.184059
7830 22:10:46.184589
7831 22:10:46.184878 ==
7832 22:10:46.187677 Dram Type= 6, Freq= 0, CH_0, rank 1
7833 22:10:46.190482 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7834 22:10:46.190875 ==
7835 22:10:46.191148
7836 22:10:46.191435
7837 22:10:46.193579 TX Vref Scan disable
7838 22:10:46.193961 == TX Byte 0 ==
7839 22:10:46.200257 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7840 22:10:46.203961 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7841 22:10:46.204474 == TX Byte 1 ==
7842 22:10:46.210251 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7843 22:10:46.213235 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7844 22:10:46.213689 ==
7845 22:10:46.216683 Dram Type= 6, Freq= 0, CH_0, rank 1
7846 22:10:46.219757 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7847 22:10:46.220202 ==
7848 22:10:46.234943
7849 22:10:46.238100 TX Vref early break, caculate TX vref
7850 22:10:46.241208 TX Vref=16, minBit 8, minWin=22, winSum=374
7851 22:10:46.244822 TX Vref=18, minBit 0, minWin=23, winSum=382
7852 22:10:46.247942 TX Vref=20, minBit 1, minWin=23, winSum=391
7853 22:10:46.251941 TX Vref=22, minBit 1, minWin=24, winSum=397
7854 22:10:46.254905 TX Vref=24, minBit 1, minWin=24, winSum=404
7855 22:10:46.261696 TX Vref=26, minBit 13, minWin=24, winSum=411
7856 22:10:46.264575 TX Vref=28, minBit 0, minWin=25, winSum=412
7857 22:10:46.268079 TX Vref=30, minBit 8, minWin=24, winSum=408
7858 22:10:46.271432 TX Vref=32, minBit 7, minWin=24, winSum=400
7859 22:10:46.274898 TX Vref=34, minBit 8, minWin=22, winSum=392
7860 22:10:46.278330 TX Vref=36, minBit 4, minWin=23, winSum=384
7861 22:10:46.284568 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 28
7862 22:10:46.285054
7863 22:10:46.288365 Final TX Range 0 Vref 28
7864 22:10:46.288844
7865 22:10:46.289117 ==
7866 22:10:46.291695 Dram Type= 6, Freq= 0, CH_0, rank 1
7867 22:10:46.294594 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7868 22:10:46.295062 ==
7869 22:10:46.295352
7870 22:10:46.298775
7871 22:10:46.299296 TX Vref Scan disable
7872 22:10:46.305736 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7873 22:10:46.306410 == TX Byte 0 ==
7874 22:10:46.308099 u2DelayCellOfst[0]=14 cells (4 PI)
7875 22:10:46.311770 u2DelayCellOfst[1]=21 cells (6 PI)
7876 22:10:46.314756 u2DelayCellOfst[2]=14 cells (4 PI)
7877 22:10:46.318099 u2DelayCellOfst[3]=14 cells (4 PI)
7878 22:10:46.321182 u2DelayCellOfst[4]=7 cells (2 PI)
7879 22:10:46.325010 u2DelayCellOfst[5]=0 cells (0 PI)
7880 22:10:46.327771 u2DelayCellOfst[6]=17 cells (5 PI)
7881 22:10:46.331375 u2DelayCellOfst[7]=17 cells (5 PI)
7882 22:10:46.334478 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7883 22:10:46.337644 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7884 22:10:46.341437 == TX Byte 1 ==
7885 22:10:46.344546 u2DelayCellOfst[8]=3 cells (1 PI)
7886 22:10:46.347587 u2DelayCellOfst[9]=0 cells (0 PI)
7887 22:10:46.347993 u2DelayCellOfst[10]=10 cells (3 PI)
7888 22:10:46.351286 u2DelayCellOfst[11]=7 cells (2 PI)
7889 22:10:46.354329 u2DelayCellOfst[12]=14 cells (4 PI)
7890 22:10:46.357825 u2DelayCellOfst[13]=17 cells (5 PI)
7891 22:10:46.361251 u2DelayCellOfst[14]=21 cells (6 PI)
7892 22:10:46.364602 u2DelayCellOfst[15]=17 cells (5 PI)
7893 22:10:46.371461 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7894 22:10:46.374732 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7895 22:10:46.375244 DramC Write-DBI on
7896 22:10:46.375657 ==
7897 22:10:46.377871 Dram Type= 6, Freq= 0, CH_0, rank 1
7898 22:10:46.384399 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7899 22:10:46.384856 ==
7900 22:10:46.385222
7901 22:10:46.385570
7902 22:10:46.385891 TX Vref Scan disable
7903 22:10:46.388624 == TX Byte 0 ==
7904 22:10:46.392051 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7905 22:10:46.394834 == TX Byte 1 ==
7906 22:10:46.398673 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7907 22:10:46.399139 DramC Write-DBI off
7908 22:10:46.401296
7909 22:10:46.401633 [DATLAT]
7910 22:10:46.401926 Freq=1600, CH0 RK1
7911 22:10:46.402207
7912 22:10:46.405077 DATLAT Default: 0xe
7913 22:10:46.405568 0, 0xFFFF, sum = 0
7914 22:10:46.408671 1, 0xFFFF, sum = 0
7915 22:10:46.409032 2, 0xFFFF, sum = 0
7916 22:10:46.411816 3, 0xFFFF, sum = 0
7917 22:10:46.415195 4, 0xFFFF, sum = 0
7918 22:10:46.415634 5, 0xFFFF, sum = 0
7919 22:10:46.418321 6, 0xFFFF, sum = 0
7920 22:10:46.418681 7, 0xFFFF, sum = 0
7921 22:10:46.421601 8, 0xFFFF, sum = 0
7922 22:10:46.421894 9, 0xFFFF, sum = 0
7923 22:10:46.424640 10, 0xFFFF, sum = 0
7924 22:10:46.424941 11, 0xFFFF, sum = 0
7925 22:10:46.427956 12, 0x8FFF, sum = 0
7926 22:10:46.428321 13, 0x0, sum = 1
7927 22:10:46.431985 14, 0x0, sum = 2
7928 22:10:46.432470 15, 0x0, sum = 3
7929 22:10:46.435132 16, 0x0, sum = 4
7930 22:10:46.435578 best_step = 14
7931 22:10:46.435923
7932 22:10:46.436201 ==
7933 22:10:46.438367 Dram Type= 6, Freq= 0, CH_0, rank 1
7934 22:10:46.441368 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7935 22:10:46.445252 ==
7936 22:10:46.445771 RX Vref Scan: 0
7937 22:10:46.446045
7938 22:10:46.448436 RX Vref 0 -> 0, step: 1
7939 22:10:46.448893
7940 22:10:46.449167 RX Delay 11 -> 252, step: 4
7941 22:10:46.455598 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7942 22:10:46.459245 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7943 22:10:46.462229 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7944 22:10:46.466029 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7945 22:10:46.468775 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7946 22:10:46.475564 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7947 22:10:46.478758 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7948 22:10:46.482059 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7949 22:10:46.485682 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7950 22:10:46.489010 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7951 22:10:46.495650 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7952 22:10:46.498881 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7953 22:10:46.502125 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7954 22:10:46.505506 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7955 22:10:46.512135 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7956 22:10:46.515123 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7957 22:10:46.515517 ==
7958 22:10:46.518687 Dram Type= 6, Freq= 0, CH_0, rank 1
7959 22:10:46.521395 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7960 22:10:46.521751 ==
7961 22:10:46.524873 DQS Delay:
7962 22:10:46.525201 DQS0 = 0, DQS1 = 0
7963 22:10:46.525504 DQM Delay:
7964 22:10:46.528185 DQM0 = 128, DQM1 = 120
7965 22:10:46.528617 DQ Delay:
7966 22:10:46.531799 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =122
7967 22:10:46.535149 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
7968 22:10:46.537916 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7969 22:10:46.544926 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7970 22:10:46.545418
7971 22:10:46.545681
7972 22:10:46.545896
7973 22:10:46.547949 [DramC_TX_OE_Calibration] TA2
7974 22:10:46.548337 Original DQ_B0 (3 6) =30, OEN = 27
7975 22:10:46.551883 Original DQ_B1 (3 6) =30, OEN = 27
7976 22:10:46.555096 24, 0x0, End_B0=24 End_B1=24
7977 22:10:46.558320 25, 0x0, End_B0=25 End_B1=25
7978 22:10:46.561202 26, 0x0, End_B0=26 End_B1=26
7979 22:10:46.565351 27, 0x0, End_B0=27 End_B1=27
7980 22:10:46.565842 28, 0x0, End_B0=28 End_B1=28
7981 22:10:46.568176 29, 0x0, End_B0=29 End_B1=29
7982 22:10:46.571486 30, 0x0, End_B0=30 End_B1=30
7983 22:10:46.574428 31, 0x4141, End_B0=30 End_B1=30
7984 22:10:46.578864 Byte0 end_step=30 best_step=27
7985 22:10:46.579297 Byte1 end_step=30 best_step=27
7986 22:10:46.581135 Byte0 TX OE(2T, 0.5T) = (3, 3)
7987 22:10:46.584919 Byte1 TX OE(2T, 0.5T) = (3, 3)
7988 22:10:46.585271
7989 22:10:46.585564
7990 22:10:46.594604 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7991 22:10:46.595061 CH0 RK1: MR19=303, MR18=2222
7992 22:10:46.601257 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
7993 22:10:46.604375 [RxdqsGatingPostProcess] freq 1600
7994 22:10:46.611077 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7995 22:10:46.614281 Pre-setting of DQS Precalculation
7996 22:10:46.617960 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7997 22:10:46.618383 ==
7998 22:10:46.621203 Dram Type= 6, Freq= 0, CH_1, rank 0
7999 22:10:46.627828 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8000 22:10:46.628309 ==
8001 22:10:46.630727 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8002 22:10:46.637417 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8003 22:10:46.640552 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8004 22:10:46.647508 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8005 22:10:46.657870 [CA 0] Center 41 (11~71) winsize 61
8006 22:10:46.658295 [CA 1] Center 40 (10~70) winsize 61
8007 22:10:46.660671 [CA 2] Center 36 (7~66) winsize 60
8008 22:10:46.664275 [CA 3] Center 35 (6~65) winsize 60
8009 22:10:46.667305 [CA 4] Center 33 (4~63) winsize 60
8010 22:10:46.671129 [CA 5] Center 33 (4~63) winsize 60
8011 22:10:46.671485
8012 22:10:46.674631 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8013 22:10:46.675116
8014 22:10:46.677816 [CATrainingPosCal] consider 1 rank data
8015 22:10:46.680731 u2DelayCellTimex100 = 275/100 ps
8016 22:10:46.687047 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8017 22:10:46.690967 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8018 22:10:46.694072 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8019 22:10:46.697458 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8020 22:10:46.701119 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8021 22:10:46.703765 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8022 22:10:46.704149
8023 22:10:46.707343 CA PerBit enable=1, Macro0, CA PI delay=33
8024 22:10:46.707699
8025 22:10:46.710331 [CBTSetCACLKResult] CA Dly = 33
8026 22:10:46.714060 CS Dly: 8 (0~39)
8027 22:10:46.717162 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8028 22:10:46.720407 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8029 22:10:46.720755 ==
8030 22:10:46.723512 Dram Type= 6, Freq= 0, CH_1, rank 1
8031 22:10:46.727601 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8032 22:10:46.730283 ==
8033 22:10:46.733634 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8034 22:10:46.737120 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8035 22:10:46.743786 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8036 22:10:46.750180 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8037 22:10:46.756565 [CA 0] Center 40 (10~70) winsize 61
8038 22:10:46.760079 [CA 1] Center 39 (9~70) winsize 62
8039 22:10:46.763570 [CA 2] Center 35 (6~65) winsize 60
8040 22:10:46.766917 [CA 3] Center 35 (6~65) winsize 60
8041 22:10:46.770084 [CA 4] Center 33 (4~63) winsize 60
8042 22:10:46.773244 [CA 5] Center 33 (3~63) winsize 61
8043 22:10:46.773702
8044 22:10:46.776503 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8045 22:10:46.776937
8046 22:10:46.779721 [CATrainingPosCal] consider 2 rank data
8047 22:10:46.783049 u2DelayCellTimex100 = 275/100 ps
8048 22:10:46.786577 CA0 delay=40 (11~70),Diff = 7 PI (24 cell)
8049 22:10:46.793663 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8050 22:10:46.796644 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8051 22:10:46.799882 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8052 22:10:46.803505 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8053 22:10:46.806701 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8054 22:10:46.807187
8055 22:10:46.810164 CA PerBit enable=1, Macro0, CA PI delay=33
8056 22:10:46.810669
8057 22:10:46.813273 [CBTSetCACLKResult] CA Dly = 33
8058 22:10:46.816574 CS Dly: 9 (0~41)
8059 22:10:46.819739 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8060 22:10:46.822979 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8061 22:10:46.823368
8062 22:10:46.826182 ----->DramcWriteLeveling(PI) begin...
8063 22:10:46.826585 ==
8064 22:10:46.829110 Dram Type= 6, Freq= 0, CH_1, rank 0
8065 22:10:46.833366 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8066 22:10:46.836208 ==
8067 22:10:46.836562 Write leveling (Byte 0): 21 => 21
8068 22:10:46.839724 Write leveling (Byte 1): 21 => 21
8069 22:10:46.843058 DramcWriteLeveling(PI) end<-----
8070 22:10:46.843418
8071 22:10:46.843671 ==
8072 22:10:46.846472 Dram Type= 6, Freq= 0, CH_1, rank 0
8073 22:10:46.852588 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8074 22:10:46.852981 ==
8075 22:10:46.856342 [Gating] SW mode calibration
8076 22:10:46.862562 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8077 22:10:46.865990 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8078 22:10:46.873046 0 12 0 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
8079 22:10:46.876529 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8080 22:10:46.879837 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 22:10:46.885761 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8082 22:10:46.889638 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8083 22:10:46.892787 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 22:10:46.899731 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8085 22:10:46.902567 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8086 22:10:46.906452 0 13 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
8087 22:10:46.913170 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8088 22:10:46.916244 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 22:10:46.919435 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 22:10:46.922890 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 22:10:46.929050 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 22:10:46.932774 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 22:10:46.936039 0 13 28 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8094 22:10:46.942467 0 14 0 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
8095 22:10:46.945487 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 22:10:46.948793 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 22:10:46.955546 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 22:10:46.959209 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 22:10:46.962212 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 22:10:46.968510 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 22:10:46.972104 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8102 22:10:46.975427 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8103 22:10:46.981972 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8104 22:10:46.985157 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 22:10:46.988704 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 22:10:46.995774 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 22:10:46.999071 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 22:10:47.002122 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 22:10:47.008810 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 22:10:47.011978 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 22:10:47.015068 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 22:10:47.021973 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 22:10:47.025280 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 22:10:47.028593 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 22:10:47.035245 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 22:10:47.038757 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8117 22:10:47.041828 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8118 22:10:47.048350 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8119 22:10:47.048795 Total UI for P1: 0, mck2ui 16
8120 22:10:47.055142 best dqsien dly found for B0: ( 1, 0, 26)
8121 22:10:47.058478 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8122 22:10:47.062084 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 22:10:47.065269 Total UI for P1: 0, mck2ui 16
8124 22:10:47.068279 best dqsien dly found for B1: ( 1, 1, 2)
8125 22:10:47.071753 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8126 22:10:47.075472 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8127 22:10:47.075947
8128 22:10:47.078585 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8129 22:10:47.084613 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8130 22:10:47.084715 [Gating] SW calibration Done
8131 22:10:47.084790 ==
8132 22:10:47.088035 Dram Type= 6, Freq= 0, CH_1, rank 0
8133 22:10:47.095191 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8134 22:10:47.095619 ==
8135 22:10:47.095873 RX Vref Scan: 0
8136 22:10:47.096093
8137 22:10:47.098260 RX Vref 0 -> 0, step: 1
8138 22:10:47.098603
8139 22:10:47.101360 RX Delay 0 -> 252, step: 8
8140 22:10:47.105285 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8141 22:10:47.108338 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8142 22:10:47.111643 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8143 22:10:47.114858 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8144 22:10:47.121955 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8145 22:10:47.124928 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8146 22:10:47.128318 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8147 22:10:47.131653 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8148 22:10:47.134826 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8149 22:10:47.141741 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8150 22:10:47.144815 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8151 22:10:47.148275 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8152 22:10:47.151121 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8153 22:10:47.157703 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8154 22:10:47.161071 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8155 22:10:47.164912 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8156 22:10:47.165458 ==
8157 22:10:47.167581 Dram Type= 6, Freq= 0, CH_1, rank 0
8158 22:10:47.171279 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8159 22:10:47.171776 ==
8160 22:10:47.174280 DQS Delay:
8161 22:10:47.174664 DQS0 = 0, DQS1 = 0
8162 22:10:47.178175 DQM Delay:
8163 22:10:47.178665 DQM0 = 130, DQM1 = 125
8164 22:10:47.178950 DQ Delay:
8165 22:10:47.184131 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8166 22:10:47.187628 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8167 22:10:47.190929 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =119
8168 22:10:47.194712 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8169 22:10:47.195161
8170 22:10:47.195477
8171 22:10:47.195722 ==
8172 22:10:47.198067 Dram Type= 6, Freq= 0, CH_1, rank 0
8173 22:10:47.200952 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8174 22:10:47.201446 ==
8175 22:10:47.201721
8176 22:10:47.201936
8177 22:10:47.203968 TX Vref Scan disable
8178 22:10:47.207627 == TX Byte 0 ==
8179 22:10:47.211466 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8180 22:10:47.214620 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8181 22:10:47.217750 == TX Byte 1 ==
8182 22:10:47.220899 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8183 22:10:47.224232 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8184 22:10:47.224697 ==
8185 22:10:47.227412 Dram Type= 6, Freq= 0, CH_1, rank 0
8186 22:10:47.233690 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8187 22:10:47.234107 ==
8188 22:10:47.244795
8189 22:10:47.247871 TX Vref early break, caculate TX vref
8190 22:10:47.251432 TX Vref=16, minBit 3, minWin=21, winSum=370
8191 22:10:47.255002 TX Vref=18, minBit 1, minWin=22, winSum=377
8192 22:10:47.257814 TX Vref=20, minBit 1, minWin=23, winSum=391
8193 22:10:47.261134 TX Vref=22, minBit 3, minWin=22, winSum=394
8194 22:10:47.264581 TX Vref=24, minBit 1, minWin=24, winSum=405
8195 22:10:47.271486 TX Vref=26, minBit 3, minWin=24, winSum=413
8196 22:10:47.274674 TX Vref=28, minBit 1, minWin=24, winSum=415
8197 22:10:47.277718 TX Vref=30, minBit 3, minWin=24, winSum=403
8198 22:10:47.281213 TX Vref=32, minBit 1, minWin=23, winSum=395
8199 22:10:47.284395 TX Vref=34, minBit 3, minWin=23, winSum=393
8200 22:10:47.291335 [TxChooseVref] Worse bit 1, Min win 24, Win sum 415, Final Vref 28
8201 22:10:47.291788
8202 22:10:47.295041 Final TX Range 0 Vref 28
8203 22:10:47.295545
8204 22:10:47.295825 ==
8205 22:10:47.298008 Dram Type= 6, Freq= 0, CH_1, rank 0
8206 22:10:47.301045 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8207 22:10:47.301597 ==
8208 22:10:47.301883
8209 22:10:47.302118
8210 22:10:47.304115 TX Vref Scan disable
8211 22:10:47.311085 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8212 22:10:47.311572 == TX Byte 0 ==
8213 22:10:47.314808 u2DelayCellOfst[0]=17 cells (5 PI)
8214 22:10:47.317612 u2DelayCellOfst[1]=14 cells (4 PI)
8215 22:10:47.320946 u2DelayCellOfst[2]=0 cells (0 PI)
8216 22:10:47.324493 u2DelayCellOfst[3]=7 cells (2 PI)
8217 22:10:47.327366 u2DelayCellOfst[4]=10 cells (3 PI)
8218 22:10:47.331346 u2DelayCellOfst[5]=17 cells (5 PI)
8219 22:10:47.334355 u2DelayCellOfst[6]=17 cells (5 PI)
8220 22:10:47.334749 u2DelayCellOfst[7]=7 cells (2 PI)
8221 22:10:47.341505 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8222 22:10:47.344440 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8223 22:10:47.344926 == TX Byte 1 ==
8224 22:10:47.347910 u2DelayCellOfst[8]=0 cells (0 PI)
8225 22:10:47.351302 u2DelayCellOfst[9]=3 cells (1 PI)
8226 22:10:47.354109 u2DelayCellOfst[10]=10 cells (3 PI)
8227 22:10:47.357265 u2DelayCellOfst[11]=3 cells (1 PI)
8228 22:10:47.360314 u2DelayCellOfst[12]=17 cells (5 PI)
8229 22:10:47.364379 u2DelayCellOfst[13]=17 cells (5 PI)
8230 22:10:47.367317 u2DelayCellOfst[14]=21 cells (6 PI)
8231 22:10:47.370924 u2DelayCellOfst[15]=17 cells (5 PI)
8232 22:10:47.374035 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8233 22:10:47.380434 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8234 22:10:47.380905 DramC Write-DBI on
8235 22:10:47.381180 ==
8236 22:10:47.383836 Dram Type= 6, Freq= 0, CH_1, rank 0
8237 22:10:47.387690 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8238 22:10:47.390682 ==
8239 22:10:47.391079
8240 22:10:47.391346
8241 22:10:47.391578 TX Vref Scan disable
8242 22:10:47.393796 == TX Byte 0 ==
8243 22:10:47.397793 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8244 22:10:47.400549 == TX Byte 1 ==
8245 22:10:47.404633 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8246 22:10:47.407508 DramC Write-DBI off
8247 22:10:47.407889
8248 22:10:47.408155 [DATLAT]
8249 22:10:47.408389 Freq=1600, CH1 RK0
8250 22:10:47.408619
8251 22:10:47.410632 DATLAT Default: 0xf
8252 22:10:47.411007 0, 0xFFFF, sum = 0
8253 22:10:47.413854 1, 0xFFFF, sum = 0
8254 22:10:47.417231 2, 0xFFFF, sum = 0
8255 22:10:47.417685 3, 0xFFFF, sum = 0
8256 22:10:47.420138 4, 0xFFFF, sum = 0
8257 22:10:47.420626 5, 0xFFFF, sum = 0
8258 22:10:47.423803 6, 0xFFFF, sum = 0
8259 22:10:47.424265 7, 0xFFFF, sum = 0
8260 22:10:47.426978 8, 0xFFFF, sum = 0
8261 22:10:47.427344 9, 0xFFFF, sum = 0
8262 22:10:47.429970 10, 0xFFFF, sum = 0
8263 22:10:47.430379 11, 0xFFFF, sum = 0
8264 22:10:47.433292 12, 0xFFF, sum = 0
8265 22:10:47.433671 13, 0x0, sum = 1
8266 22:10:47.436764 14, 0x0, sum = 2
8267 22:10:47.437039 15, 0x0, sum = 3
8268 22:10:47.440205 16, 0x0, sum = 4
8269 22:10:47.440564 best_step = 14
8270 22:10:47.440807
8271 22:10:47.441018 ==
8272 22:10:47.443938 Dram Type= 6, Freq= 0, CH_1, rank 0
8273 22:10:47.447146 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8274 22:10:47.449972 ==
8275 22:10:47.450326 RX Vref Scan: 1
8276 22:10:47.450569
8277 22:10:47.453573 Set Vref Range= 24 -> 127
8278 22:10:47.453915
8279 22:10:47.456904 RX Vref 24 -> 127, step: 1
8280 22:10:47.457410
8281 22:10:47.457714 RX Delay 3 -> 252, step: 4
8282 22:10:47.457950
8283 22:10:47.460144 Set Vref, RX VrefLevel [Byte0]: 24
8284 22:10:47.463666 [Byte1]: 24
8285 22:10:47.467146
8286 22:10:47.467488 Set Vref, RX VrefLevel [Byte0]: 25
8287 22:10:47.470228 [Byte1]: 25
8288 22:10:47.475068
8289 22:10:47.475521 Set Vref, RX VrefLevel [Byte0]: 26
8290 22:10:47.478117 [Byte1]: 26
8291 22:10:47.482355
8292 22:10:47.482790 Set Vref, RX VrefLevel [Byte0]: 27
8293 22:10:47.485369 [Byte1]: 27
8294 22:10:47.490101
8295 22:10:47.490603 Set Vref, RX VrefLevel [Byte0]: 28
8296 22:10:47.493593 [Byte1]: 28
8297 22:10:47.497513
8298 22:10:47.497889 Set Vref, RX VrefLevel [Byte0]: 29
8299 22:10:47.501240 [Byte1]: 29
8300 22:10:47.505629
8301 22:10:47.505997 Set Vref, RX VrefLevel [Byte0]: 30
8302 22:10:47.508737 [Byte1]: 30
8303 22:10:47.513279
8304 22:10:47.513769 Set Vref, RX VrefLevel [Byte0]: 31
8305 22:10:47.516708 [Byte1]: 31
8306 22:10:47.520598
8307 22:10:47.520965 Set Vref, RX VrefLevel [Byte0]: 32
8308 22:10:47.523845 [Byte1]: 32
8309 22:10:47.529024
8310 22:10:47.529425 Set Vref, RX VrefLevel [Byte0]: 33
8311 22:10:47.531288 [Byte1]: 33
8312 22:10:47.535774
8313 22:10:47.536044 Set Vref, RX VrefLevel [Byte0]: 34
8314 22:10:47.538905 [Byte1]: 34
8315 22:10:47.543949
8316 22:10:47.544336 Set Vref, RX VrefLevel [Byte0]: 35
8317 22:10:47.546956 [Byte1]: 35
8318 22:10:47.551173
8319 22:10:47.551537 Set Vref, RX VrefLevel [Byte0]: 36
8320 22:10:47.554929 [Byte1]: 36
8321 22:10:47.559080
8322 22:10:47.559427 Set Vref, RX VrefLevel [Byte0]: 37
8323 22:10:47.562344 [Byte1]: 37
8324 22:10:47.566646
8325 22:10:47.567003 Set Vref, RX VrefLevel [Byte0]: 38
8326 22:10:47.570151 [Byte1]: 38
8327 22:10:47.574551
8328 22:10:47.574901 Set Vref, RX VrefLevel [Byte0]: 39
8329 22:10:47.577793 [Byte1]: 39
8330 22:10:47.581926
8331 22:10:47.582287 Set Vref, RX VrefLevel [Byte0]: 40
8332 22:10:47.584742 [Byte1]: 40
8333 22:10:47.589338
8334 22:10:47.589728 Set Vref, RX VrefLevel [Byte0]: 41
8335 22:10:47.593402 [Byte1]: 41
8336 22:10:47.597921
8337 22:10:47.598384 Set Vref, RX VrefLevel [Byte0]: 42
8338 22:10:47.600949 [Byte1]: 42
8339 22:10:47.604769
8340 22:10:47.605188 Set Vref, RX VrefLevel [Byte0]: 43
8341 22:10:47.608596 [Byte1]: 43
8342 22:10:47.612440
8343 22:10:47.612850 Set Vref, RX VrefLevel [Byte0]: 44
8344 22:10:47.615966 [Byte1]: 44
8345 22:10:47.620445
8346 22:10:47.620924 Set Vref, RX VrefLevel [Byte0]: 45
8347 22:10:47.623801 [Byte1]: 45
8348 22:10:47.628042
8349 22:10:47.628504 Set Vref, RX VrefLevel [Byte0]: 46
8350 22:10:47.631220 [Byte1]: 46
8351 22:10:47.635667
8352 22:10:47.636059 Set Vref, RX VrefLevel [Byte0]: 47
8353 22:10:47.638842 [Byte1]: 47
8354 22:10:47.643338
8355 22:10:47.643789 Set Vref, RX VrefLevel [Byte0]: 48
8356 22:10:47.646267 [Byte1]: 48
8357 22:10:47.651088
8358 22:10:47.651547 Set Vref, RX VrefLevel [Byte0]: 49
8359 22:10:47.654475 [Byte1]: 49
8360 22:10:47.658827
8361 22:10:47.659235 Set Vref, RX VrefLevel [Byte0]: 50
8362 22:10:47.661736 [Byte1]: 50
8363 22:10:47.665978
8364 22:10:47.666420 Set Vref, RX VrefLevel [Byte0]: 51
8365 22:10:47.669225 [Byte1]: 51
8366 22:10:47.673546
8367 22:10:47.673891 Set Vref, RX VrefLevel [Byte0]: 52
8368 22:10:47.677244 [Byte1]: 52
8369 22:10:47.681587
8370 22:10:47.682034 Set Vref, RX VrefLevel [Byte0]: 53
8371 22:10:47.684843 [Byte1]: 53
8372 22:10:47.689122
8373 22:10:47.689596 Set Vref, RX VrefLevel [Byte0]: 54
8374 22:10:47.692236 [Byte1]: 54
8375 22:10:47.697141
8376 22:10:47.697660 Set Vref, RX VrefLevel [Byte0]: 55
8377 22:10:47.700209 [Byte1]: 55
8378 22:10:47.704506
8379 22:10:47.705014 Set Vref, RX VrefLevel [Byte0]: 56
8380 22:10:47.707900 [Byte1]: 56
8381 22:10:47.712028
8382 22:10:47.712483 Set Vref, RX VrefLevel [Byte0]: 57
8383 22:10:47.715592 [Byte1]: 57
8384 22:10:47.719683
8385 22:10:47.720070 Set Vref, RX VrefLevel [Byte0]: 58
8386 22:10:47.723176 [Byte1]: 58
8387 22:10:47.727306
8388 22:10:47.727652 Set Vref, RX VrefLevel [Byte0]: 59
8389 22:10:47.730501 [Byte1]: 59
8390 22:10:47.734787
8391 22:10:47.735131 Set Vref, RX VrefLevel [Byte0]: 60
8392 22:10:47.738719 [Byte1]: 60
8393 22:10:47.742771
8394 22:10:47.743219 Set Vref, RX VrefLevel [Byte0]: 61
8395 22:10:47.745759 [Byte1]: 61
8396 22:10:47.750783
8397 22:10:47.751130 Set Vref, RX VrefLevel [Byte0]: 62
8398 22:10:47.753301 [Byte1]: 62
8399 22:10:47.757959
8400 22:10:47.758411 Set Vref, RX VrefLevel [Byte0]: 63
8401 22:10:47.761419 [Byte1]: 63
8402 22:10:47.766010
8403 22:10:47.766366 Set Vref, RX VrefLevel [Byte0]: 64
8404 22:10:47.769069 [Byte1]: 64
8405 22:10:47.773189
8406 22:10:47.773659 Set Vref, RX VrefLevel [Byte0]: 65
8407 22:10:47.776449 [Byte1]: 65
8408 22:10:47.780923
8409 22:10:47.781358 Set Vref, RX VrefLevel [Byte0]: 66
8410 22:10:47.784000 [Byte1]: 66
8411 22:10:47.788911
8412 22:10:47.789427 Set Vref, RX VrefLevel [Byte0]: 67
8413 22:10:47.792084 [Byte1]: 67
8414 22:10:47.796538
8415 22:10:47.796974 Set Vref, RX VrefLevel [Byte0]: 68
8416 22:10:47.799546 [Byte1]: 68
8417 22:10:47.803695
8418 22:10:47.804154 Set Vref, RX VrefLevel [Byte0]: 69
8419 22:10:47.807444 [Byte1]: 69
8420 22:10:47.811802
8421 22:10:47.812243 Set Vref, RX VrefLevel [Byte0]: 70
8422 22:10:47.814867 [Byte1]: 70
8423 22:10:47.819838
8424 22:10:47.820323 Set Vref, RX VrefLevel [Byte0]: 71
8425 22:10:47.822617 [Byte1]: 71
8426 22:10:47.826744
8427 22:10:47.827207 Set Vref, RX VrefLevel [Byte0]: 72
8428 22:10:47.829956 [Byte1]: 72
8429 22:10:47.834460
8430 22:10:47.834844 Set Vref, RX VrefLevel [Byte0]: 73
8431 22:10:47.837521 [Byte1]: 73
8432 22:10:47.842091
8433 22:10:47.842439 Set Vref, RX VrefLevel [Byte0]: 74
8434 22:10:47.845562 [Byte1]: 74
8435 22:10:47.849665
8436 22:10:47.850090 Set Vref, RX VrefLevel [Byte0]: 75
8437 22:10:47.853085 [Byte1]: 75
8438 22:10:47.857721
8439 22:10:47.858165 Final RX Vref Byte 0 = 60 to rank0
8440 22:10:47.860394 Final RX Vref Byte 1 = 55 to rank0
8441 22:10:47.864397 Final RX Vref Byte 0 = 60 to rank1
8442 22:10:47.867101 Final RX Vref Byte 1 = 55 to rank1==
8443 22:10:47.870526 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 22:10:47.877186 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8445 22:10:47.877566 ==
8446 22:10:47.877819 DQS Delay:
8447 22:10:47.880938 DQS0 = 0, DQS1 = 0
8448 22:10:47.881432 DQM Delay:
8449 22:10:47.881726 DQM0 = 128, DQM1 = 124
8450 22:10:47.883705 DQ Delay:
8451 22:10:47.887172 DQ0 =134, DQ1 =124, DQ2 =116, DQ3 =126
8452 22:10:47.890336 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =124
8453 22:10:47.894268 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =114
8454 22:10:47.896928 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8455 22:10:47.897249
8456 22:10:47.897540
8457 22:10:47.897759
8458 22:10:47.900542 [DramC_TX_OE_Calibration] TA2
8459 22:10:47.904156 Original DQ_B0 (3 6) =30, OEN = 27
8460 22:10:47.907398 Original DQ_B1 (3 6) =30, OEN = 27
8461 22:10:47.911122 24, 0x0, End_B0=24 End_B1=24
8462 22:10:47.911582 25, 0x0, End_B0=25 End_B1=25
8463 22:10:47.913758 26, 0x0, End_B0=26 End_B1=26
8464 22:10:47.917387 27, 0x0, End_B0=27 End_B1=27
8465 22:10:47.920702 28, 0x0, End_B0=28 End_B1=28
8466 22:10:47.924341 29, 0x0, End_B0=29 End_B1=29
8467 22:10:47.924807 30, 0x0, End_B0=30 End_B1=30
8468 22:10:47.927054 31, 0x5151, End_B0=30 End_B1=30
8469 22:10:47.930007 Byte0 end_step=30 best_step=27
8470 22:10:47.933168 Byte1 end_step=30 best_step=27
8471 22:10:47.936955 Byte0 TX OE(2T, 0.5T) = (3, 3)
8472 22:10:47.940148 Byte1 TX OE(2T, 0.5T) = (3, 3)
8473 22:10:47.940497
8474 22:10:47.940746
8475 22:10:47.947322 [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8476 22:10:47.950546 CH1 RK0: MR19=303, MR18=2828
8477 22:10:47.956887 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16
8478 22:10:47.957350
8479 22:10:47.960254 ----->DramcWriteLeveling(PI) begin...
8480 22:10:47.960609 ==
8481 22:10:47.963690 Dram Type= 6, Freq= 0, CH_1, rank 1
8482 22:10:47.967372 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8483 22:10:47.967885 ==
8484 22:10:47.970365 Write leveling (Byte 0): 22 => 22
8485 22:10:47.973816 Write leveling (Byte 1): 21 => 21
8486 22:10:47.976947 DramcWriteLeveling(PI) end<-----
8487 22:10:47.977334
8488 22:10:47.977599 ==
8489 22:10:47.980048 Dram Type= 6, Freq= 0, CH_1, rank 1
8490 22:10:47.984043 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8491 22:10:47.984489 ==
8492 22:10:47.986693 [Gating] SW mode calibration
8493 22:10:47.993543 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8494 22:10:48.000339 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8495 22:10:48.003577 0 12 0 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
8496 22:10:48.010270 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8497 22:10:48.013432 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8498 22:10:48.016835 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8499 22:10:48.020305 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8500 22:10:48.026860 0 12 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8501 22:10:48.029837 0 12 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8502 22:10:48.033359 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8503 22:10:48.039983 0 13 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8504 22:10:48.043264 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8505 22:10:48.047110 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8506 22:10:48.053003 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8507 22:10:48.056592 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8508 22:10:48.059954 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8509 22:10:48.066856 0 13 24 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
8510 22:10:48.069664 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8511 22:10:48.073279 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8512 22:10:48.079763 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8513 22:10:48.083193 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8514 22:10:48.086165 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8515 22:10:48.093048 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8516 22:10:48.096516 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8517 22:10:48.099957 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8518 22:10:48.106580 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8519 22:10:48.109404 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8520 22:10:48.113527 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8521 22:10:48.119783 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8522 22:10:48.123544 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8523 22:10:48.126230 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8524 22:10:48.132616 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8525 22:10:48.136280 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8526 22:10:48.139849 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8527 22:10:48.146087 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8528 22:10:48.149346 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8529 22:10:48.152634 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8530 22:10:48.159435 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8531 22:10:48.162373 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8532 22:10:48.165509 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8533 22:10:48.172346 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8534 22:10:48.175986 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8535 22:10:48.179324 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8536 22:10:48.182845 Total UI for P1: 0, mck2ui 16
8537 22:10:48.185529 best dqsien dly found for B0: ( 1, 0, 26)
8538 22:10:48.189256 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8539 22:10:48.192978 Total UI for P1: 0, mck2ui 16
8540 22:10:48.196010 best dqsien dly found for B1: ( 1, 1, 0)
8541 22:10:48.198958 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8542 22:10:48.202443 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8543 22:10:48.202843
8544 22:10:48.209202 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8545 22:10:48.212434 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8546 22:10:48.216102 [Gating] SW calibration Done
8547 22:10:48.216563 ==
8548 22:10:48.219668 Dram Type= 6, Freq= 0, CH_1, rank 1
8549 22:10:48.222880 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8550 22:10:48.223339 ==
8551 22:10:48.223621 RX Vref Scan: 0
8552 22:10:48.223845
8553 22:10:48.225596 RX Vref 0 -> 0, step: 1
8554 22:10:48.225948
8555 22:10:48.229516 RX Delay 0 -> 252, step: 8
8556 22:10:48.232434 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8557 22:10:48.235650 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8558 22:10:48.239482 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8559 22:10:48.245500 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8560 22:10:48.249062 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8561 22:10:48.252501 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8562 22:10:48.255704 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8563 22:10:48.258737 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8564 22:10:48.265256 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8565 22:10:48.268678 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8566 22:10:48.271983 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8567 22:10:48.275216 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8568 22:10:48.282294 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8569 22:10:48.285297 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8570 22:10:48.289035 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8571 22:10:48.291998 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8572 22:10:48.292491 ==
8573 22:10:48.295264 Dram Type= 6, Freq= 0, CH_1, rank 1
8574 22:10:48.302150 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8575 22:10:48.302647 ==
8576 22:10:48.302933 DQS Delay:
8577 22:10:48.303178 DQS0 = 0, DQS1 = 0
8578 22:10:48.305336 DQM Delay:
8579 22:10:48.305722 DQM0 = 131, DQM1 = 125
8580 22:10:48.308378 DQ Delay:
8581 22:10:48.311885 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8582 22:10:48.315271 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8583 22:10:48.318723 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8584 22:10:48.321962 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8585 22:10:48.322375
8586 22:10:48.322648
8587 22:10:48.322942 ==
8588 22:10:48.325296 Dram Type= 6, Freq= 0, CH_1, rank 1
8589 22:10:48.328656 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8590 22:10:48.331964 ==
8591 22:10:48.332435
8592 22:10:48.332844
8593 22:10:48.333102 TX Vref Scan disable
8594 22:10:48.335105 == TX Byte 0 ==
8595 22:10:48.338945 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8596 22:10:48.341488 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8597 22:10:48.345297 == TX Byte 1 ==
8598 22:10:48.348554 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8599 22:10:48.351977 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8600 22:10:48.352374 ==
8601 22:10:48.355446 Dram Type= 6, Freq= 0, CH_1, rank 1
8602 22:10:48.361635 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8603 22:10:48.362195 ==
8604 22:10:48.374031
8605 22:10:48.377058 TX Vref early break, caculate TX vref
8606 22:10:48.380712 TX Vref=16, minBit 0, minWin=23, winSum=379
8607 22:10:48.383924 TX Vref=18, minBit 0, minWin=23, winSum=389
8608 22:10:48.387353 TX Vref=20, minBit 0, minWin=23, winSum=390
8609 22:10:48.391196 TX Vref=22, minBit 2, minWin=24, winSum=403
8610 22:10:48.394508 TX Vref=24, minBit 5, minWin=23, winSum=411
8611 22:10:48.400791 TX Vref=26, minBit 0, minWin=25, winSum=418
8612 22:10:48.404549 TX Vref=28, minBit 0, minWin=23, winSum=418
8613 22:10:48.407584 TX Vref=30, minBit 0, minWin=24, winSum=418
8614 22:10:48.410693 TX Vref=32, minBit 0, minWin=23, winSum=400
8615 22:10:48.414047 TX Vref=34, minBit 0, minWin=22, winSum=400
8616 22:10:48.417433 TX Vref=36, minBit 0, minWin=21, winSum=386
8617 22:10:48.424037 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8618 22:10:48.424506
8619 22:10:48.427207 Final TX Range 0 Vref 26
8620 22:10:48.427571
8621 22:10:48.427827 ==
8622 22:10:48.430950 Dram Type= 6, Freq= 0, CH_1, rank 1
8623 22:10:48.433621 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8624 22:10:48.434050 ==
8625 22:10:48.434345
8626 22:10:48.434591
8627 22:10:48.436744 TX Vref Scan disable
8628 22:10:48.443994 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8629 22:10:48.444482 == TX Byte 0 ==
8630 22:10:48.447354 u2DelayCellOfst[0]=17 cells (5 PI)
8631 22:10:48.450279 u2DelayCellOfst[1]=10 cells (3 PI)
8632 22:10:48.453821 u2DelayCellOfst[2]=0 cells (0 PI)
8633 22:10:48.457235 u2DelayCellOfst[3]=7 cells (2 PI)
8634 22:10:48.460512 u2DelayCellOfst[4]=10 cells (3 PI)
8635 22:10:48.463664 u2DelayCellOfst[5]=17 cells (5 PI)
8636 22:10:48.467275 u2DelayCellOfst[6]=17 cells (5 PI)
8637 22:10:48.469741 u2DelayCellOfst[7]=7 cells (2 PI)
8638 22:10:48.473604 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8639 22:10:48.476758 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8640 22:10:48.480232 == TX Byte 1 ==
8641 22:10:48.483694 u2DelayCellOfst[8]=0 cells (0 PI)
8642 22:10:48.486538 u2DelayCellOfst[9]=7 cells (2 PI)
8643 22:10:48.489965 u2DelayCellOfst[10]=14 cells (4 PI)
8644 22:10:48.490460 u2DelayCellOfst[11]=7 cells (2 PI)
8645 22:10:48.493343 u2DelayCellOfst[12]=17 cells (5 PI)
8646 22:10:48.496717 u2DelayCellOfst[13]=21 cells (6 PI)
8647 22:10:48.500256 u2DelayCellOfst[14]=21 cells (6 PI)
8648 22:10:48.503384 u2DelayCellOfst[15]=21 cells (6 PI)
8649 22:10:48.509984 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8650 22:10:48.513442 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8651 22:10:48.513909 DramC Write-DBI on
8652 22:10:48.514193 ==
8653 22:10:48.516818 Dram Type= 6, Freq= 0, CH_1, rank 1
8654 22:10:48.523521 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8655 22:10:48.524019 ==
8656 22:10:48.524305
8657 22:10:48.524545
8658 22:10:48.524772 TX Vref Scan disable
8659 22:10:48.527047 == TX Byte 0 ==
8660 22:10:48.530435 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8661 22:10:48.533647 == TX Byte 1 ==
8662 22:10:48.537280 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8663 22:10:48.540465 DramC Write-DBI off
8664 22:10:48.540810
8665 22:10:48.541093 [DATLAT]
8666 22:10:48.541361 Freq=1600, CH1 RK1
8667 22:10:48.541616
8668 22:10:48.543894 DATLAT Default: 0xe
8669 22:10:48.544235 0, 0xFFFF, sum = 0
8670 22:10:48.547153 1, 0xFFFF, sum = 0
8671 22:10:48.547501 2, 0xFFFF, sum = 0
8672 22:10:48.550429 3, 0xFFFF, sum = 0
8673 22:10:48.553617 4, 0xFFFF, sum = 0
8674 22:10:48.553965 5, 0xFFFF, sum = 0
8675 22:10:48.557067 6, 0xFFFF, sum = 0
8676 22:10:48.557570 7, 0xFFFF, sum = 0
8677 22:10:48.560091 8, 0xFFFF, sum = 0
8678 22:10:48.560512 9, 0xFFFF, sum = 0
8679 22:10:48.563657 10, 0xFFFF, sum = 0
8680 22:10:48.564021 11, 0xFFFF, sum = 0
8681 22:10:48.567452 12, 0xF7F, sum = 0
8682 22:10:48.567801 13, 0x0, sum = 1
8683 22:10:48.570216 14, 0x0, sum = 2
8684 22:10:48.570610 15, 0x0, sum = 3
8685 22:10:48.573651 16, 0x0, sum = 4
8686 22:10:48.574107 best_step = 14
8687 22:10:48.574365
8688 22:10:48.574584 ==
8689 22:10:48.577347 Dram Type= 6, Freq= 0, CH_1, rank 1
8690 22:10:48.580186 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8691 22:10:48.580551 ==
8692 22:10:48.583587 RX Vref Scan: 0
8693 22:10:48.583935
8694 22:10:48.586850 RX Vref 0 -> 0, step: 1
8695 22:10:48.587205
8696 22:10:48.587454 RX Delay 3 -> 252, step: 4
8697 22:10:48.594580 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8698 22:10:48.597432 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8699 22:10:48.600822 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8700 22:10:48.604174 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8701 22:10:48.607751 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8702 22:10:48.614523 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8703 22:10:48.617141 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8704 22:10:48.620463 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8705 22:10:48.624184 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8706 22:10:48.627658 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8707 22:10:48.633924 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8708 22:10:48.637013 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8709 22:10:48.640945 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8710 22:10:48.644341 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8711 22:10:48.651113 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8712 22:10:48.653880 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8713 22:10:48.654284 ==
8714 22:10:48.657415 Dram Type= 6, Freq= 0, CH_1, rank 1
8715 22:10:48.660766 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8716 22:10:48.661258 ==
8717 22:10:48.661603 DQS Delay:
8718 22:10:48.664313 DQS0 = 0, DQS1 = 0
8719 22:10:48.664797 DQM Delay:
8720 22:10:48.667069 DQM0 = 126, DQM1 = 122
8721 22:10:48.667437 DQ Delay:
8722 22:10:48.670320 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =122
8723 22:10:48.673644 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8724 22:10:48.677240 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8725 22:10:48.683535 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8726 22:10:48.684005
8727 22:10:48.684275
8728 22:10:48.684510
8729 22:10:48.686692 [DramC_TX_OE_Calibration] TA2
8730 22:10:48.686944 Original DQ_B0 (3 6) =30, OEN = 27
8731 22:10:48.690803 Original DQ_B1 (3 6) =30, OEN = 27
8732 22:10:48.693761 24, 0x0, End_B0=24 End_B1=24
8733 22:10:48.697023 25, 0x0, End_B0=25 End_B1=25
8734 22:10:48.700832 26, 0x0, End_B0=26 End_B1=26
8735 22:10:48.703800 27, 0x0, End_B0=27 End_B1=27
8736 22:10:48.704283 28, 0x0, End_B0=28 End_B1=28
8737 22:10:48.706918 29, 0x0, End_B0=29 End_B1=29
8738 22:10:48.710577 30, 0x0, End_B0=30 End_B1=30
8739 22:10:48.713910 31, 0x5151, End_B0=30 End_B1=30
8740 22:10:48.717275 Byte0 end_step=30 best_step=27
8741 22:10:48.717792 Byte1 end_step=30 best_step=27
8742 22:10:48.720914 Byte0 TX OE(2T, 0.5T) = (3, 3)
8743 22:10:48.723924 Byte1 TX OE(2T, 0.5T) = (3, 3)
8744 22:10:48.724410
8745 22:10:48.724685
8746 22:10:48.733487 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8747 22:10:48.734203 CH1 RK1: MR19=303, MR18=1B1B
8748 22:10:48.740222 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8749 22:10:48.743981 [RxdqsGatingPostProcess] freq 1600
8750 22:10:48.750186 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8751 22:10:48.753932 Pre-setting of DQS Precalculation
8752 22:10:48.757176 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8753 22:10:48.764212 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8754 22:10:48.774088 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8755 22:10:48.774575
8756 22:10:48.774850
8757 22:10:48.775093 [Calibration Summary] 3200 Mbps
8758 22:10:48.777014 CH 0, Rank 0
8759 22:10:48.777425 SW Impedance : PASS
8760 22:10:48.780441 DUTY Scan : NO K
8761 22:10:48.783730 ZQ Calibration : PASS
8762 22:10:48.784214 Jitter Meter : NO K
8763 22:10:48.787019 CBT Training : PASS
8764 22:10:48.790392 Write leveling : PASS
8765 22:10:48.790887 RX DQS gating : PASS
8766 22:10:48.793526 RX DQ/DQS(RDDQC) : PASS
8767 22:10:48.796688 TX DQ/DQS : PASS
8768 22:10:48.797165 RX DATLAT : PASS
8769 22:10:48.800319 RX DQ/DQS(Engine): PASS
8770 22:10:48.803837 TX OE : PASS
8771 22:10:48.804225 All Pass.
8772 22:10:48.804501
8773 22:10:48.804737 CH 0, Rank 1
8774 22:10:48.807042 SW Impedance : PASS
8775 22:10:48.810370 DUTY Scan : NO K
8776 22:10:48.810856 ZQ Calibration : PASS
8777 22:10:48.813804 Jitter Meter : NO K
8778 22:10:48.817050 CBT Training : PASS
8779 22:10:48.817576 Write leveling : PASS
8780 22:10:48.820404 RX DQS gating : PASS
8781 22:10:48.820888 RX DQ/DQS(RDDQC) : PASS
8782 22:10:48.823773 TX DQ/DQS : PASS
8783 22:10:48.826938 RX DATLAT : PASS
8784 22:10:48.827482 RX DQ/DQS(Engine): PASS
8785 22:10:48.829902 TX OE : PASS
8786 22:10:48.830290 All Pass.
8787 22:10:48.830566
8788 22:10:48.833216 CH 1, Rank 0
8789 22:10:48.833637 SW Impedance : PASS
8790 22:10:48.836463 DUTY Scan : NO K
8791 22:10:48.840062 ZQ Calibration : PASS
8792 22:10:48.840553 Jitter Meter : NO K
8793 22:10:48.843345 CBT Training : PASS
8794 22:10:48.846875 Write leveling : PASS
8795 22:10:48.847360 RX DQS gating : PASS
8796 22:10:48.849686 RX DQ/DQS(RDDQC) : PASS
8797 22:10:48.853440 TX DQ/DQS : PASS
8798 22:10:48.853930 RX DATLAT : PASS
8799 22:10:48.856372 RX DQ/DQS(Engine): PASS
8800 22:10:48.859904 TX OE : PASS
8801 22:10:48.860418 All Pass.
8802 22:10:48.860702
8803 22:10:48.860946 CH 1, Rank 1
8804 22:10:48.863661 SW Impedance : PASS
8805 22:10:48.866584 DUTY Scan : NO K
8806 22:10:48.867072 ZQ Calibration : PASS
8807 22:10:48.869673 Jitter Meter : NO K
8808 22:10:48.872633 CBT Training : PASS
8809 22:10:48.872982 Write leveling : PASS
8810 22:10:48.876664 RX DQS gating : PASS
8811 22:10:48.880001 RX DQ/DQS(RDDQC) : PASS
8812 22:10:48.880488 TX DQ/DQS : PASS
8813 22:10:48.882987 RX DATLAT : PASS
8814 22:10:48.886499 RX DQ/DQS(Engine): PASS
8815 22:10:48.886986 TX OE : PASS
8816 22:10:48.887270 All Pass.
8817 22:10:48.889907
8818 22:10:48.890389 DramC Write-DBI on
8819 22:10:48.892631 PER_BANK_REFRESH: Hybrid Mode
8820 22:10:48.893016 TX_TRACKING: ON
8821 22:10:48.903376 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8822 22:10:48.909645 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8823 22:10:48.919558 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8824 22:10:48.923246 [FAST_K] Save calibration result to emmc
8825 22:10:48.925671 sync common calibartion params.
8826 22:10:48.926058 sync cbt_mode0:0, 1:0
8827 22:10:48.929407 dram_init: ddr_geometry: 0
8828 22:10:48.932594 dram_init: ddr_geometry: 0
8829 22:10:48.933078 dram_init: ddr_geometry: 0
8830 22:10:48.935712 0:dram_rank_size:80000000
8831 22:10:48.939284 1:dram_rank_size:80000000
8832 22:10:48.942322 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8833 22:10:48.945599 DFS_SHUFFLE_HW_MODE: ON
8834 22:10:48.948957 dramc_set_vcore_voltage set vcore to 725000
8835 22:10:48.952815 Read voltage for 1600, 0
8836 22:10:48.953293 Vio18 = 0
8837 22:10:48.955550 Vcore = 725000
8838 22:10:48.956010 Vdram = 0
8839 22:10:48.956281 Vddq = 0
8840 22:10:48.956524 Vmddr = 0
8841 22:10:48.958817 switch to 3200 Mbps bootup
8842 22:10:48.962025 [DramcRunTimeConfig]
8843 22:10:48.962486 PHYPLL
8844 22:10:48.965443 DPM_CONTROL_AFTERK: ON
8845 22:10:48.965774 PER_BANK_REFRESH: ON
8846 22:10:48.969034 REFRESH_OVERHEAD_REDUCTION: ON
8847 22:10:48.972162 CMD_PICG_NEW_MODE: OFF
8848 22:10:48.972513 XRTWTW_NEW_MODE: ON
8849 22:10:48.975976 XRTRTR_NEW_MODE: ON
8850 22:10:48.976463 TX_TRACKING: ON
8851 22:10:48.979182 RDSEL_TRACKING: OFF
8852 22:10:48.982322 DQS Precalculation for DVFS: ON
8853 22:10:48.982808 RX_TRACKING: OFF
8854 22:10:48.983090 HW_GATING DBG: ON
8855 22:10:48.985961 ZQCS_ENABLE_LP4: ON
8856 22:10:48.988866 RX_PICG_NEW_MODE: ON
8857 22:10:48.989243 TX_PICG_NEW_MODE: ON
8858 22:10:48.992317 ENABLE_RX_DCM_DPHY: ON
8859 22:10:48.995761 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8860 22:10:48.996154 DUMMY_READ_FOR_TRACKING: OFF
8861 22:10:48.998792 !!! SPM_CONTROL_AFTERK: OFF
8862 22:10:49.002126 !!! SPM could not control APHY
8863 22:10:49.005241 IMPEDANCE_TRACKING: ON
8864 22:10:49.005623 TEMP_SENSOR: ON
8865 22:10:49.008743 HW_SAVE_FOR_SR: OFF
8866 22:10:49.012064 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8867 22:10:49.015469 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8868 22:10:49.015977 Read ODT Tracking: ON
8869 22:10:49.018391 Refresh Rate DeBounce: ON
8870 22:10:49.021883 DFS_NO_QUEUE_FLUSH: ON
8871 22:10:49.025080 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8872 22:10:49.025565 ENABLE_DFS_RUNTIME_MRW: OFF
8873 22:10:49.028788 DDR_RESERVE_NEW_MODE: ON
8874 22:10:49.031900 MR_CBT_SWITCH_FREQ: ON
8875 22:10:49.032385 =========================
8876 22:10:49.051963 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8877 22:10:49.055046 dram_init: ddr_geometry: 0
8878 22:10:49.073350 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8879 22:10:49.076699 dram_init: dram init end (result: 0)
8880 22:10:49.083246 DRAM-K: Full calibration passed in 23432 msecs
8881 22:10:49.086174 MRC: failed to locate region type 0.
8882 22:10:49.086563 DRAM rank0 size:0x80000000,
8883 22:10:49.090036 DRAM rank1 size=0x80000000
8884 22:10:49.099913 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8885 22:10:49.106356 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8886 22:10:49.113130 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8887 22:10:49.119973 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8888 22:10:49.122548 DRAM rank0 size:0x80000000,
8889 22:10:49.126279 DRAM rank1 size=0x80000000
8890 22:10:49.126762 CBMEM:
8891 22:10:49.129125 IMD: root @ 0xfffff000 254 entries.
8892 22:10:49.132724 IMD: root @ 0xffffec00 62 entries.
8893 22:10:49.136096 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8894 22:10:49.139590 WARNING: RO_VPD is uninitialized or empty.
8895 22:10:49.146012 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8896 22:10:49.152759 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8897 22:10:49.165363 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8898 22:10:49.176936 BS: romstage times (exec / console): total (unknown) / 22968 ms
8899 22:10:49.177437
8900 22:10:49.177727
8901 22:10:49.186706 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8902 22:10:49.190396 ARM64: Exception handlers installed.
8903 22:10:49.193283 ARM64: Testing exception
8904 22:10:49.196967 ARM64: Done test exception
8905 22:10:49.197516 Enumerating buses...
8906 22:10:49.200136 Show all devs... Before device enumeration.
8907 22:10:49.203617 Root Device: enabled 1
8908 22:10:49.207078 CPU_CLUSTER: 0: enabled 1
8909 22:10:49.207675 CPU: 00: enabled 1
8910 22:10:49.210272 Compare with tree...
8911 22:10:49.210657 Root Device: enabled 1
8912 22:10:49.213184 CPU_CLUSTER: 0: enabled 1
8913 22:10:49.217043 CPU: 00: enabled 1
8914 22:10:49.217635 Root Device scanning...
8915 22:10:49.220174 scan_static_bus for Root Device
8916 22:10:49.223412 CPU_CLUSTER: 0 enabled
8917 22:10:49.226375 scan_static_bus for Root Device done
8918 22:10:49.229623 scan_bus: bus Root Device finished in 8 msecs
8919 22:10:49.230013 done
8920 22:10:49.236180 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8921 22:10:49.239639 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8922 22:10:49.246547 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8923 22:10:49.250076 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8924 22:10:49.253220 Allocating resources...
8925 22:10:49.256326 Reading resources...
8926 22:10:49.259961 Root Device read_resources bus 0 link: 0
8927 22:10:49.260355 DRAM rank0 size:0x80000000,
8928 22:10:49.263164 DRAM rank1 size=0x80000000
8929 22:10:49.266468 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8930 22:10:49.270039 CPU: 00 missing read_resources
8931 22:10:49.272847 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8932 22:10:49.280043 Root Device read_resources bus 0 link: 0 done
8933 22:10:49.280530 Done reading resources.
8934 22:10:49.286359 Show resources in subtree (Root Device)...After reading.
8935 22:10:49.289598 Root Device child on link 0 CPU_CLUSTER: 0
8936 22:10:49.293142 CPU_CLUSTER: 0 child on link 0 CPU: 00
8937 22:10:49.302814 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8938 22:10:49.303300 CPU: 00
8939 22:10:49.306091 Root Device assign_resources, bus 0 link: 0
8940 22:10:49.309710 CPU_CLUSTER: 0 missing set_resources
8941 22:10:49.316151 Root Device assign_resources, bus 0 link: 0 done
8942 22:10:49.316635 Done setting resources.
8943 22:10:49.323070 Show resources in subtree (Root Device)...After assigning values.
8944 22:10:49.326346 Root Device child on link 0 CPU_CLUSTER: 0
8945 22:10:49.329253 CPU_CLUSTER: 0 child on link 0 CPU: 00
8946 22:10:49.339332 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8947 22:10:49.339839 CPU: 00
8948 22:10:49.342511 Done allocating resources.
8949 22:10:49.345928 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8950 22:10:49.348827 Enabling resources...
8951 22:10:49.349266 done.
8952 22:10:49.355819 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8953 22:10:49.356241 Initializing devices...
8954 22:10:49.359550 Root Device init
8955 22:10:49.359971 init hardware done!
8956 22:10:49.362755 0x00000018: ctrlr->caps
8957 22:10:49.365980 52.000 MHz: ctrlr->f_max
8958 22:10:49.366473 0.400 MHz: ctrlr->f_min
8959 22:10:49.369184 0x40ff8080: ctrlr->voltages
8960 22:10:49.369758 sclk: 390625
8961 22:10:49.372641 Bus Width = 1
8962 22:10:49.373039 sclk: 390625
8963 22:10:49.375978 Bus Width = 1
8964 22:10:49.376465 Early init status = 3
8965 22:10:49.382197 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8966 22:10:49.385927 in-header: 03 fc 00 00 01 00 00 00
8967 22:10:49.386420 in-data: 00
8968 22:10:49.392177 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8969 22:10:49.396038 in-header: 03 fd 00 00 00 00 00 00
8970 22:10:49.398766 in-data:
8971 22:10:49.402005 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8972 22:10:49.405798 in-header: 03 fc 00 00 01 00 00 00
8973 22:10:49.409006 in-data: 00
8974 22:10:49.412038 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8975 22:10:49.417418 in-header: 03 fd 00 00 00 00 00 00
8976 22:10:49.420644 in-data:
8977 22:10:49.423524 [SSUSB] Setting up USB HOST controller...
8978 22:10:49.427463 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8979 22:10:49.430556 [SSUSB] phy power-on done.
8980 22:10:49.433631 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8981 22:10:49.440658 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8982 22:10:49.443545 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8983 22:10:49.450038 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8984 22:10:49.456383 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8985 22:10:49.463512 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8986 22:10:49.469826 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8987 22:10:49.476383 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8988 22:10:49.480307 SPM: binary array size = 0x9dc
8989 22:10:49.483290 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8990 22:10:49.489574 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8991 22:10:49.496813 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8992 22:10:49.503683 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8993 22:10:49.506808 configure_display: Starting display init
8994 22:10:49.540497 anx7625_power_on_init: Init interface.
8995 22:10:49.544067 anx7625_disable_pd_protocol: Disabled PD feature.
8996 22:10:49.547029 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8997 22:10:49.575095 anx7625_start_dp_work: Secure OCM version=00
8998 22:10:49.577808 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8999 22:10:49.593179 sp_tx_get_edid_block: EDID Block = 1
9000 22:10:49.695403 Extracted contents:
9001 22:10:49.699243 header: 00 ff ff ff ff ff ff 00
9002 22:10:49.702095 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9003 22:10:49.705016 version: 01 04
9004 22:10:49.708416 basic params: 95 1f 11 78 0a
9005 22:10:49.711830 chroma info: 76 90 94 55 54 90 27 21 50 54
9006 22:10:49.715329 established: 00 00 00
9007 22:10:49.722036 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9008 22:10:49.728699 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9009 22:10:49.731628 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9010 22:10:49.738163 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9011 22:10:49.744550 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9012 22:10:49.748045 extensions: 00
9013 22:10:49.748421 checksum: fb
9014 22:10:49.748692
9015 22:10:49.754715 Manufacturer: IVO Model 57d Serial Number 0
9016 22:10:49.755198 Made week 0 of 2020
9017 22:10:49.758244 EDID version: 1.4
9018 22:10:49.758624 Digital display
9019 22:10:49.761508 6 bits per primary color channel
9020 22:10:49.761888 DisplayPort interface
9021 22:10:49.764769 Maximum image size: 31 cm x 17 cm
9022 22:10:49.767931 Gamma: 220%
9023 22:10:49.768418 Check DPMS levels
9024 22:10:49.774602 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9025 22:10:49.777898 First detailed timing is preferred timing
9026 22:10:49.778378 Established timings supported:
9027 22:10:49.780961 Standard timings supported:
9028 22:10:49.784598 Detailed timings
9029 22:10:49.787987 Hex of detail: 383680a07038204018303c0035ae10000019
9030 22:10:49.794544 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9031 22:10:49.798119 0780 0798 07c8 0820 hborder 0
9032 22:10:49.801426 0438 043b 0447 0458 vborder 0
9033 22:10:49.804443 -hsync -vsync
9034 22:10:49.804927 Did detailed timing
9035 22:10:49.811567 Hex of detail: 000000000000000000000000000000000000
9036 22:10:49.814722 Manufacturer-specified data, tag 0
9037 22:10:49.817905 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9038 22:10:49.821175 ASCII string: InfoVision
9039 22:10:49.824052 Hex of detail: 000000fe00523134304e574635205248200a
9040 22:10:49.827416 ASCII string: R140NWF5 RH
9041 22:10:49.827900 Checksum
9042 22:10:49.831268 Checksum: 0xfb (valid)
9043 22:10:49.833872 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9044 22:10:49.837605 DSI data_rate: 832800000 bps
9045 22:10:49.843994 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9046 22:10:49.847757 anx7625_parse_edid: pixelclock(138800).
9047 22:10:49.850730 hactive(1920), hsync(48), hfp(24), hbp(88)
9048 22:10:49.854528 vactive(1080), vsync(12), vfp(3), vbp(17)
9049 22:10:49.857385 anx7625_dsi_config: config dsi.
9050 22:10:49.863918 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9051 22:10:49.877569 anx7625_dsi_config: success to config DSI
9052 22:10:49.880840 anx7625_dp_start: MIPI phy setup OK.
9053 22:10:49.884595 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9054 22:10:49.887430 mtk_ddp_mode_set invalid vrefresh 60
9055 22:10:49.890568 main_disp_path_setup
9056 22:10:49.890969 ovl_layer_smi_id_en
9057 22:10:49.894035 ovl_layer_smi_id_en
9058 22:10:49.894528 ccorr_config
9059 22:10:49.894802 aal_config
9060 22:10:49.897141 gamma_config
9061 22:10:49.897668 postmask_config
9062 22:10:49.900746 dither_config
9063 22:10:49.904056 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9064 22:10:49.910478 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9065 22:10:49.914025 Root Device init finished in 551 msecs
9066 22:10:49.917378 CPU_CLUSTER: 0 init
9067 22:10:49.924194 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9068 22:10:49.927192 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9069 22:10:49.930504 APU_MBOX 0x190000b0 = 0x10001
9070 22:10:49.934247 APU_MBOX 0x190001b0 = 0x10001
9071 22:10:49.937289 APU_MBOX 0x190005b0 = 0x10001
9072 22:10:49.940779 APU_MBOX 0x190006b0 = 0x10001
9073 22:10:49.943798 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9074 22:10:49.956509 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9075 22:10:49.968958 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9076 22:10:49.975197 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9077 22:10:49.987428 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9078 22:10:49.996386 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9079 22:10:49.999847 CPU_CLUSTER: 0 init finished in 81 msecs
9080 22:10:50.002982 Devices initialized
9081 22:10:50.006008 Show all devs... After init.
9082 22:10:50.006495 Root Device: enabled 1
9083 22:10:50.009513 CPU_CLUSTER: 0: enabled 1
9084 22:10:50.013391 CPU: 00: enabled 1
9085 22:10:50.016058 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9086 22:10:50.019184 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9087 22:10:50.022584 ELOG: NV offset 0x57f000 size 0x1000
9088 22:10:50.029212 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9089 22:10:50.036206 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9090 22:10:50.039123 ELOG: Event(17) added with size 13 at 2023-09-05 22:10:50 UTC
9091 22:10:50.046193 out: cmd=0x121: 03 db 21 01 00 00 00 00
9092 22:10:50.049482 in-header: 03 ca 00 00 2c 00 00 00
9093 22:10:50.062026 in-data: 99 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9094 22:10:50.065840 ELOG: Event(A1) added with size 10 at 2023-09-05 22:10:50 UTC
9095 22:10:50.075829 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9096 22:10:50.078931 ELOG: Event(A0) added with size 9 at 2023-09-05 22:10:50 UTC
9097 22:10:50.082408 elog_add_boot_reason: Logged dev mode boot
9098 22:10:50.088401 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9099 22:10:50.088785 Finalize devices...
9100 22:10:50.091829 Devices finalized
9101 22:10:50.095306 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9102 22:10:50.098662 Writing coreboot table at 0xffe64000
9103 22:10:50.105574 0. 000000000010a000-0000000000113fff: RAMSTAGE
9104 22:10:50.108610 1. 0000000040000000-00000000400fffff: RAM
9105 22:10:50.112299 2. 0000000040100000-000000004032afff: RAMSTAGE
9106 22:10:50.115409 3. 000000004032b000-00000000545fffff: RAM
9107 22:10:50.118329 4. 0000000054600000-000000005465ffff: BL31
9108 22:10:50.124932 5. 0000000054660000-00000000ffe63fff: RAM
9109 22:10:50.128158 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9110 22:10:50.131539 7. 0000000100000000-000000013fffffff: RAM
9111 22:10:50.135100 Passing 5 GPIOs to payload:
9112 22:10:50.141037 NAME | PORT | POLARITY | VALUE
9113 22:10:50.144665 EC in RW | 0x000000aa | low | undefined
9114 22:10:50.147761 EC interrupt | 0x00000005 | low | undefined
9115 22:10:50.154949 TPM interrupt | 0x000000ab | high | undefined
9116 22:10:50.157874 SD card detect | 0x00000011 | high | undefined
9117 22:10:50.164815 speaker enable | 0x00000093 | high | undefined
9118 22:10:50.168051 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9119 22:10:50.170895 in-header: 03 f8 00 00 02 00 00 00
9120 22:10:50.171275 in-data: 03 00
9121 22:10:50.174206 ADC[4]: Raw value=668222 ID=5
9122 22:10:50.177991 ADC[3]: Raw value=212180 ID=1
9123 22:10:50.178495 RAM Code: 0x51
9124 22:10:50.180789 ADC[6]: Raw value=74410 ID=0
9125 22:10:50.184744 ADC[5]: Raw value=211444 ID=1
9126 22:10:50.185217 SKU Code: 0x1
9127 22:10:50.191158 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 17ad
9128 22:10:50.194023 coreboot table: 964 bytes.
9129 22:10:50.197188 IMD ROOT 0. 0xfffff000 0x00001000
9130 22:10:50.200795 IMD SMALL 1. 0xffffe000 0x00001000
9131 22:10:50.204281 RO MCACHE 2. 0xffffc000 0x00001104
9132 22:10:50.207902 CONSOLE 3. 0xfff7c000 0x00080000
9133 22:10:50.210525 FMAP 4. 0xfff7b000 0x00000452
9134 22:10:50.213950 TIME STAMP 5. 0xfff7a000 0x00000910
9135 22:10:50.217174 VBOOT WORK 6. 0xfff66000 0x00014000
9136 22:10:50.220573 RAMOOPS 7. 0xffe66000 0x00100000
9137 22:10:50.224201 COREBOOT 8. 0xffe64000 0x00002000
9138 22:10:50.224687 IMD small region:
9139 22:10:50.227199 IMD ROOT 0. 0xffffec00 0x00000400
9140 22:10:50.231023 VPD 1. 0xffffeb80 0x0000006c
9141 22:10:50.234015 MMC STATUS 2. 0xffffeb60 0x00000004
9142 22:10:50.241009 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9143 22:10:50.241667 Probing TPM: done!
9144 22:10:50.247557 Connected to device vid:did:rid of 1ae0:0028:00
9145 22:10:50.254036 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9146 22:10:50.257477 Initialized TPM device CR50 revision 0
9147 22:10:50.261086 Checking cr50 for pending updates
9148 22:10:50.267029 Reading cr50 TPM mode
9149 22:10:50.275800 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9150 22:10:50.282250 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9151 22:10:50.322511 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9152 22:10:50.325479 Checking segment from ROM address 0x40100000
9153 22:10:50.328402 Checking segment from ROM address 0x4010001c
9154 22:10:50.335049 Loading segment from ROM address 0x40100000
9155 22:10:50.335463 code (compression=0)
9156 22:10:50.345292 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9157 22:10:50.351986 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9158 22:10:50.352410 it's not compressed!
9159 22:10:50.358791 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9160 22:10:50.362434 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9161 22:10:50.383161 Loading segment from ROM address 0x4010001c
9162 22:10:50.383650 Entry Point 0x80000000
9163 22:10:50.385853 Loaded segments
9164 22:10:50.388817 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9165 22:10:50.396030 Jumping to boot code at 0x80000000(0xffe64000)
9166 22:10:50.402824 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9167 22:10:50.409668 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9168 22:10:50.417362 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9169 22:10:50.420830 Checking segment from ROM address 0x40100000
9170 22:10:50.423973 Checking segment from ROM address 0x4010001c
9171 22:10:50.430842 Loading segment from ROM address 0x40100000
9172 22:10:50.431332 code (compression=1)
9173 22:10:50.437122 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9174 22:10:50.447346 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9175 22:10:50.447849 using LZMA
9176 22:10:50.455074 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9177 22:10:50.462147 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9178 22:10:50.465359 Loading segment from ROM address 0x4010001c
9179 22:10:50.465841 Entry Point 0x54601000
9180 22:10:50.468668 Loaded segments
9181 22:10:50.472165 NOTICE: MT8192 bl31_setup
9182 22:10:50.478916 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9183 22:10:50.482582 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9184 22:10:50.485822 WARNING: region 0:
9185 22:10:50.488835 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9186 22:10:50.489294 WARNING: region 1:
9187 22:10:50.495210 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9188 22:10:50.498601 WARNING: region 2:
9189 22:10:50.502220 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9190 22:10:50.505081 WARNING: region 3:
9191 22:10:50.509216 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9192 22:10:50.512426 WARNING: region 4:
9193 22:10:50.518842 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9194 22:10:50.519470 WARNING: region 5:
9195 22:10:50.522381 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9196 22:10:50.525903 WARNING: region 6:
9197 22:10:50.529150 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9198 22:10:50.532110 WARNING: region 7:
9199 22:10:50.535944 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9200 22:10:50.542042 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9201 22:10:50.546021 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9202 22:10:50.549239 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9203 22:10:50.555980 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9204 22:10:50.559317 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9205 22:10:50.562426 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9206 22:10:50.568808 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9207 22:10:50.572075 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9208 22:10:50.578929 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9209 22:10:50.582246 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9210 22:10:50.585237 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9211 22:10:50.592415 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9212 22:10:50.595834 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9213 22:10:50.598981 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9214 22:10:50.605354 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9215 22:10:50.609203 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9216 22:10:50.611966 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9217 22:10:50.618579 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9218 22:10:50.622394 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9219 22:10:50.629218 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9220 22:10:50.631966 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9221 22:10:50.636049 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9222 22:10:50.641779 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9223 22:10:50.645633 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9224 22:10:50.652569 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9225 22:10:50.655869 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9226 22:10:50.659486 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9227 22:10:50.665510 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9228 22:10:50.669245 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9229 22:10:50.672256 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9230 22:10:50.679403 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9231 22:10:50.682228 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9232 22:10:50.689579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9233 22:10:50.691954 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9234 22:10:50.695271 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9235 22:10:50.699221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9236 22:10:50.702352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9237 22:10:50.708836 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9238 22:10:50.712795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9239 22:10:50.715690 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9240 22:10:50.719252 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9241 22:10:50.725792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9242 22:10:50.728878 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9243 22:10:50.732372 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9244 22:10:50.735278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9245 22:10:50.742080 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9246 22:10:50.745141 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9247 22:10:50.749362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9248 22:10:50.755680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9249 22:10:50.759328 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9250 22:10:50.765880 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9251 22:10:50.769051 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9252 22:10:50.772633 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9253 22:10:50.779118 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9254 22:10:50.782291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9255 22:10:50.789157 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9256 22:10:50.792548 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9257 22:10:50.795791 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9258 22:10:50.802390 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9259 22:10:50.806063 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9260 22:10:50.812444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9261 22:10:50.815494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9262 22:10:50.822555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9263 22:10:50.825621 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9264 22:10:50.832294 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9265 22:10:50.835967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9266 22:10:50.839070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9267 22:10:50.845892 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9268 22:10:50.848993 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9269 22:10:50.855348 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9270 22:10:50.858726 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9271 22:10:50.865763 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9272 22:10:50.868760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9273 22:10:50.872554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9274 22:10:50.878467 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9275 22:10:50.881982 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9276 22:10:50.888646 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9277 22:10:50.892449 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9278 22:10:50.898374 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9279 22:10:50.901778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9280 22:10:50.909077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9281 22:10:50.912093 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9282 22:10:50.915777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9283 22:10:50.922501 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9284 22:10:50.926013 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9285 22:10:50.932287 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9286 22:10:50.936273 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9287 22:10:50.939115 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9288 22:10:50.945233 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9289 22:10:50.948859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9290 22:10:50.955414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9291 22:10:50.958688 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9292 22:10:50.965118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9293 22:10:50.968632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9294 22:10:50.975623 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9295 22:10:50.978843 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9296 22:10:50.982186 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9297 22:10:50.985710 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9298 22:10:50.992395 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9299 22:10:50.995730 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9300 22:10:50.999339 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9301 22:10:51.005652 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9302 22:10:51.009361 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9303 22:10:51.012549 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9304 22:10:51.018910 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9305 22:10:51.022334 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9306 22:10:51.029333 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9307 22:10:51.032676 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9308 22:10:51.035568 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9309 22:10:51.042221 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9310 22:10:51.045465 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9311 22:10:51.052067 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9312 22:10:51.055520 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9313 22:10:51.059110 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9314 22:10:51.065526 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9315 22:10:51.069123 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9316 22:10:51.072085 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9317 22:10:51.078569 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9318 22:10:51.082329 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9319 22:10:51.085219 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9320 22:10:51.088528 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9321 22:10:51.095400 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9322 22:10:51.099141 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9323 22:10:51.101911 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9324 22:10:51.108814 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9325 22:10:51.112363 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9326 22:10:51.115746 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9327 22:10:51.122635 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9328 22:10:51.125917 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9329 22:10:51.132463 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9330 22:10:51.135538 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9331 22:10:51.138871 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9332 22:10:51.145400 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9333 22:10:51.148997 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9334 22:10:51.155478 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9335 22:10:51.159484 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9336 22:10:51.162294 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9337 22:10:51.169124 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9338 22:10:51.172233 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9339 22:10:51.175372 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9340 22:10:51.181971 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9341 22:10:51.185756 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9342 22:10:51.192425 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9343 22:10:51.195296 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9344 22:10:51.199350 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9345 22:10:51.206140 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9346 22:10:51.209039 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9347 22:10:51.215860 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9348 22:10:51.219349 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9349 22:10:51.222475 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9350 22:10:51.228921 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9351 22:10:51.232321 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9352 22:10:51.236121 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9353 22:10:51.242131 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9354 22:10:51.245297 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9355 22:10:51.252303 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9356 22:10:51.255782 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9357 22:10:51.259059 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9358 22:10:51.266062 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9359 22:10:51.269421 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9360 22:10:51.275368 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9361 22:10:51.279311 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9362 22:10:51.282001 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9363 22:10:51.288915 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9364 22:10:51.292645 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9365 22:10:51.295411 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9366 22:10:51.301898 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9367 22:10:51.305359 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9368 22:10:51.311726 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9369 22:10:51.315390 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9370 22:10:51.321785 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9371 22:10:51.325178 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9372 22:10:51.328627 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9373 22:10:51.335451 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9374 22:10:51.338790 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9375 22:10:51.341519 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9376 22:10:51.348072 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9377 22:10:51.351226 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9378 22:10:51.357979 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9379 22:10:51.361298 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9380 22:10:51.364608 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9381 22:10:51.371344 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9382 22:10:51.375021 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9383 22:10:51.381409 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9384 22:10:51.384644 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9385 22:10:51.388077 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9386 22:10:51.394630 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9387 22:10:51.398004 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9388 22:10:51.404832 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9389 22:10:51.407929 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9390 22:10:51.411490 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9391 22:10:51.418225 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9392 22:10:51.421282 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9393 22:10:51.427776 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9394 22:10:51.431360 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9395 22:10:51.437832 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9396 22:10:51.441370 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9397 22:10:51.444383 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9398 22:10:51.450958 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9399 22:10:51.453848 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9400 22:10:51.460797 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9401 22:10:51.464398 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9402 22:10:51.470780 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9403 22:10:51.473940 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9404 22:10:51.477005 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9405 22:10:51.483979 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9406 22:10:51.487370 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9407 22:10:51.493854 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9408 22:10:51.497158 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9409 22:10:51.500686 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9410 22:10:51.507179 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9411 22:10:51.510621 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9412 22:10:51.517046 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9413 22:10:51.520572 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9414 22:10:51.527853 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9415 22:10:51.530257 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9416 22:10:51.533428 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9417 22:10:51.540059 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9418 22:10:51.543684 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9419 22:10:51.549983 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9420 22:10:51.553764 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9421 22:10:51.559969 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9422 22:10:51.563526 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9423 22:10:51.566628 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9424 22:10:51.573546 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9425 22:10:51.576692 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9426 22:10:51.583686 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9427 22:10:51.586725 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9428 22:10:51.589761 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9429 22:10:51.596646 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9430 22:10:51.599571 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9431 22:10:51.603310 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9432 22:10:51.606287 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9433 22:10:51.613840 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9434 22:10:51.616429 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9435 22:10:51.619698 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9436 22:10:51.626420 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9437 22:10:51.629689 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9438 22:10:51.633063 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9439 22:10:51.639443 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9440 22:10:51.643400 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9441 22:10:51.649167 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9442 22:10:51.652919 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9443 22:10:51.656231 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9444 22:10:51.662878 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9445 22:10:51.666174 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9446 22:10:51.669882 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9447 22:10:51.676155 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9448 22:10:51.679962 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9449 22:10:51.682726 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9450 22:10:51.689464 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9451 22:10:51.692624 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9452 22:10:51.699228 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9453 22:10:51.702573 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9454 22:10:51.705982 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9455 22:10:51.712664 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9456 22:10:51.716414 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9457 22:10:51.719854 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9458 22:10:51.726032 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9459 22:10:51.729282 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9460 22:10:51.735778 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9461 22:10:51.739267 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9462 22:10:51.742395 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9463 22:10:51.748551 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9464 22:10:51.752249 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9465 22:10:51.755594 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9466 22:10:51.762976 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9467 22:10:51.766599 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9468 22:10:51.768926 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9469 22:10:51.775853 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9470 22:10:51.778925 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9471 22:10:51.782636 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9472 22:10:51.785746 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9473 22:10:51.788811 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9474 22:10:51.795402 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9475 22:10:51.798839 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9476 22:10:51.802063 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9477 22:10:51.808497 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9478 22:10:51.812336 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9479 22:10:51.815339 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9480 22:10:51.818666 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9481 22:10:51.825337 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9482 22:10:51.828432 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9483 22:10:51.835056 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9484 22:10:51.838480 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9485 22:10:51.841899 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9486 22:10:51.848360 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9487 22:10:51.851759 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9488 22:10:51.858125 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9489 22:10:51.861603 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9490 22:10:51.865025 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9491 22:10:51.871796 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9492 22:10:51.874863 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9493 22:10:51.881501 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9494 22:10:51.884852 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9495 22:10:51.891531 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9496 22:10:51.894500 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9497 22:10:51.898143 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9498 22:10:51.904897 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9499 22:10:51.907863 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9500 22:10:51.914827 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9501 22:10:51.918036 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9502 22:10:51.920984 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9503 22:10:51.928125 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9504 22:10:51.931302 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9505 22:10:51.937956 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9506 22:10:51.941164 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9507 22:10:51.944262 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9508 22:10:51.951668 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9509 22:10:51.954562 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9510 22:10:51.961168 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9511 22:10:51.964337 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9512 22:10:51.970952 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9513 22:10:51.974620 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9514 22:10:51.977335 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9515 22:10:51.984494 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9516 22:10:51.987945 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9517 22:10:51.991090 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9518 22:10:51.997256 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9519 22:10:52.001024 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9520 22:10:52.007566 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9521 22:10:52.011047 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9522 22:10:52.013945 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9523 22:10:52.020817 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9524 22:10:52.024222 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9525 22:10:52.030526 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9526 22:10:52.034416 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9527 22:10:52.040754 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9528 22:10:52.044396 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9529 22:10:52.047155 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9530 22:10:52.054022 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9531 22:10:52.056961 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9532 22:10:52.063699 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9533 22:10:52.067177 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9534 22:10:52.070420 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9535 22:10:52.077142 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9536 22:10:52.080726 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9537 22:10:52.087335 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9538 22:10:52.090480 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9539 22:10:52.093674 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9540 22:10:52.100591 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9541 22:10:52.103942 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9542 22:10:52.110494 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9543 22:10:52.114059 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9544 22:10:52.120642 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9545 22:10:52.123444 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9546 22:10:52.127090 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9547 22:10:52.133369 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9548 22:10:52.136981 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9549 22:10:52.143667 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9550 22:10:52.147001 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9551 22:10:52.150216 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9552 22:10:52.156526 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9553 22:10:52.159723 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9554 22:10:52.166503 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9555 22:10:52.170328 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9556 22:10:52.176734 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9557 22:10:52.180022 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9558 22:10:52.183355 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9559 22:10:52.189856 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9560 22:10:52.193272 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9561 22:10:52.199839 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9562 22:10:52.203035 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9563 22:10:52.210016 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9564 22:10:52.213198 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9565 22:10:52.216467 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9566 22:10:52.223412 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9567 22:10:52.226535 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9568 22:10:52.232937 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9569 22:10:52.236307 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9570 22:10:52.242795 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9571 22:10:52.245915 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9572 22:10:52.252649 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9573 22:10:52.256101 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9574 22:10:52.259387 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9575 22:10:52.265927 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9576 22:10:52.269026 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9577 22:10:52.276046 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9578 22:10:52.279391 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9579 22:10:52.286234 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9580 22:10:52.289394 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9581 22:10:52.292523 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9582 22:10:52.299120 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9583 22:10:52.302793 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9584 22:10:52.309475 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9585 22:10:52.312565 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9586 22:10:52.319347 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9587 22:10:52.322326 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9588 22:10:52.329091 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9589 22:10:52.332472 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9590 22:10:52.335647 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9591 22:10:52.342494 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9592 22:10:52.345662 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9593 22:10:52.352278 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9594 22:10:52.355416 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9595 22:10:52.362407 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9596 22:10:52.365117 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9597 22:10:52.368692 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9598 22:10:52.375562 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9599 22:10:52.378816 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9600 22:10:52.385510 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9601 22:10:52.388633 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9602 22:10:52.392488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9603 22:10:52.398963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9604 22:10:52.401869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9605 22:10:52.408863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9606 22:10:52.412356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9607 22:10:52.418882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9608 22:10:52.422252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9609 22:10:52.429071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9610 22:10:52.432158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9611 22:10:52.439026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9612 22:10:52.442112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9613 22:10:52.448997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9614 22:10:52.451622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9615 22:10:52.458705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9616 22:10:52.461776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9617 22:10:52.468682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9618 22:10:52.471869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9619 22:10:52.478662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9620 22:10:52.481910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9621 22:10:52.485438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9622 22:10:52.491615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9623 22:10:52.498068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9624 22:10:52.501354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9625 22:10:52.508148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9626 22:10:52.511473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9627 22:10:52.518040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9628 22:10:52.521113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9629 22:10:52.528435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9630 22:10:52.531478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9631 22:10:52.537780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9632 22:10:52.541110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9633 22:10:52.547825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9634 22:10:52.550611 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9635 22:10:52.554797 INFO: [APUAPC] vio 0
9636 22:10:52.557988 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9637 22:10:52.560873 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9638 22:10:52.564255 INFO: [APUAPC] D0_APC_0: 0x400510
9639 22:10:52.567860 INFO: [APUAPC] D0_APC_1: 0x0
9640 22:10:52.570964 INFO: [APUAPC] D0_APC_2: 0x1540
9641 22:10:52.574180 INFO: [APUAPC] D0_APC_3: 0x0
9642 22:10:52.577426 INFO: [APUAPC] D1_APC_0: 0xffffffff
9643 22:10:52.580828 INFO: [APUAPC] D1_APC_1: 0xffffffff
9644 22:10:52.584296 INFO: [APUAPC] D1_APC_2: 0x3fffff
9645 22:10:52.587634 INFO: [APUAPC] D1_APC_3: 0x0
9646 22:10:52.590608 INFO: [APUAPC] D2_APC_0: 0xffffffff
9647 22:10:52.594250 INFO: [APUAPC] D2_APC_1: 0xffffffff
9648 22:10:52.597392 INFO: [APUAPC] D2_APC_2: 0x3fffff
9649 22:10:52.600540 INFO: [APUAPC] D2_APC_3: 0x0
9650 22:10:52.603511 INFO: [APUAPC] D3_APC_0: 0xffffffff
9651 22:10:52.607068 INFO: [APUAPC] D3_APC_1: 0xffffffff
9652 22:10:52.610183 INFO: [APUAPC] D3_APC_2: 0x3fffff
9653 22:10:52.614016 INFO: [APUAPC] D3_APC_3: 0x0
9654 22:10:52.616833 INFO: [APUAPC] D4_APC_0: 0xffffffff
9655 22:10:52.620421 INFO: [APUAPC] D4_APC_1: 0xffffffff
9656 22:10:52.623836 INFO: [APUAPC] D4_APC_2: 0x3fffff
9657 22:10:52.627050 INFO: [APUAPC] D4_APC_3: 0x0
9658 22:10:52.630542 INFO: [APUAPC] D5_APC_0: 0xffffffff
9659 22:10:52.634023 INFO: [APUAPC] D5_APC_1: 0xffffffff
9660 22:10:52.637007 INFO: [APUAPC] D5_APC_2: 0x3fffff
9661 22:10:52.640097 INFO: [APUAPC] D5_APC_3: 0x0
9662 22:10:52.643477 INFO: [APUAPC] D6_APC_0: 0xffffffff
9663 22:10:52.647257 INFO: [APUAPC] D6_APC_1: 0xffffffff
9664 22:10:52.649836 INFO: [APUAPC] D6_APC_2: 0x3fffff
9665 22:10:52.653153 INFO: [APUAPC] D6_APC_3: 0x0
9666 22:10:52.656467 INFO: [APUAPC] D7_APC_0: 0xffffffff
9667 22:10:52.659839 INFO: [APUAPC] D7_APC_1: 0xffffffff
9668 22:10:52.663361 INFO: [APUAPC] D7_APC_2: 0x3fffff
9669 22:10:52.666807 INFO: [APUAPC] D7_APC_3: 0x0
9670 22:10:52.669526 INFO: [APUAPC] D8_APC_0: 0xffffffff
9671 22:10:52.672944 INFO: [APUAPC] D8_APC_1: 0xffffffff
9672 22:10:52.676172 INFO: [APUAPC] D8_APC_2: 0x3fffff
9673 22:10:52.679416 INFO: [APUAPC] D8_APC_3: 0x0
9674 22:10:52.682688 INFO: [APUAPC] D9_APC_0: 0xffffffff
9675 22:10:52.686578 INFO: [APUAPC] D9_APC_1: 0xffffffff
9676 22:10:52.689879 INFO: [APUAPC] D9_APC_2: 0x3fffff
9677 22:10:52.693343 INFO: [APUAPC] D9_APC_3: 0x0
9678 22:10:52.696208 INFO: [APUAPC] D10_APC_0: 0xffffffff
9679 22:10:52.700003 INFO: [APUAPC] D10_APC_1: 0xffffffff
9680 22:10:52.703339 INFO: [APUAPC] D10_APC_2: 0x3fffff
9681 22:10:52.706388 INFO: [APUAPC] D10_APC_3: 0x0
9682 22:10:52.709519 INFO: [APUAPC] D11_APC_0: 0xffffffff
9683 22:10:52.712799 INFO: [APUAPC] D11_APC_1: 0xffffffff
9684 22:10:52.716068 INFO: [APUAPC] D11_APC_2: 0x3fffff
9685 22:10:52.719868 INFO: [APUAPC] D11_APC_3: 0x0
9686 22:10:52.723071 INFO: [APUAPC] D12_APC_0: 0xffffffff
9687 22:10:52.726402 INFO: [APUAPC] D12_APC_1: 0xffffffff
9688 22:10:52.729991 INFO: [APUAPC] D12_APC_2: 0x3fffff
9689 22:10:52.733017 INFO: [APUAPC] D12_APC_3: 0x0
9690 22:10:52.736674 INFO: [APUAPC] D13_APC_0: 0xffffffff
9691 22:10:52.739970 INFO: [APUAPC] D13_APC_1: 0xffffffff
9692 22:10:52.743330 INFO: [APUAPC] D13_APC_2: 0x3fffff
9693 22:10:52.746327 INFO: [APUAPC] D13_APC_3: 0x0
9694 22:10:52.749947 INFO: [APUAPC] D14_APC_0: 0xffffffff
9695 22:10:52.752925 INFO: [APUAPC] D14_APC_1: 0xffffffff
9696 22:10:52.756312 INFO: [APUAPC] D14_APC_2: 0x3fffff
9697 22:10:52.759443 INFO: [APUAPC] D14_APC_3: 0x0
9698 22:10:52.762955 INFO: [APUAPC] D15_APC_0: 0xffffffff
9699 22:10:52.766283 INFO: [APUAPC] D15_APC_1: 0xffffffff
9700 22:10:52.769482 INFO: [APUAPC] D15_APC_2: 0x3fffff
9701 22:10:52.772752 INFO: [APUAPC] D15_APC_3: 0x0
9702 22:10:52.775991 INFO: [APUAPC] APC_CON: 0x4
9703 22:10:52.776381 INFO: [NOCDAPC] D0_APC_0: 0x0
9704 22:10:52.779563 INFO: [NOCDAPC] D0_APC_1: 0x0
9705 22:10:52.782849 INFO: [NOCDAPC] D1_APC_0: 0x0
9706 22:10:52.786113 INFO: [NOCDAPC] D1_APC_1: 0xfff
9707 22:10:52.789463 INFO: [NOCDAPC] D2_APC_0: 0x0
9708 22:10:52.792712 INFO: [NOCDAPC] D2_APC_1: 0xfff
9709 22:10:52.796354 INFO: [NOCDAPC] D3_APC_0: 0x0
9710 22:10:52.799454 INFO: [NOCDAPC] D3_APC_1: 0xfff
9711 22:10:52.802655 INFO: [NOCDAPC] D4_APC_0: 0x0
9712 22:10:52.806095 INFO: [NOCDAPC] D4_APC_1: 0xfff
9713 22:10:52.806579 INFO: [NOCDAPC] D5_APC_0: 0x0
9714 22:10:52.809201 INFO: [NOCDAPC] D5_APC_1: 0xfff
9715 22:10:52.812383 INFO: [NOCDAPC] D6_APC_0: 0x0
9716 22:10:52.816117 INFO: [NOCDAPC] D6_APC_1: 0xfff
9717 22:10:52.818862 INFO: [NOCDAPC] D7_APC_0: 0x0
9718 22:10:52.822857 INFO: [NOCDAPC] D7_APC_1: 0xfff
9719 22:10:52.825934 INFO: [NOCDAPC] D8_APC_0: 0x0
9720 22:10:52.829073 INFO: [NOCDAPC] D8_APC_1: 0xfff
9721 22:10:52.832774 INFO: [NOCDAPC] D9_APC_0: 0x0
9722 22:10:52.835683 INFO: [NOCDAPC] D9_APC_1: 0xfff
9723 22:10:52.839212 INFO: [NOCDAPC] D10_APC_0: 0x0
9724 22:10:52.842214 INFO: [NOCDAPC] D10_APC_1: 0xfff
9725 22:10:52.842701 INFO: [NOCDAPC] D11_APC_0: 0x0
9726 22:10:52.845727 INFO: [NOCDAPC] D11_APC_1: 0xfff
9727 22:10:52.848514 INFO: [NOCDAPC] D12_APC_0: 0x0
9728 22:10:52.852552 INFO: [NOCDAPC] D12_APC_1: 0xfff
9729 22:10:52.855508 INFO: [NOCDAPC] D13_APC_0: 0x0
9730 22:10:52.859281 INFO: [NOCDAPC] D13_APC_1: 0xfff
9731 22:10:52.862579 INFO: [NOCDAPC] D14_APC_0: 0x0
9732 22:10:52.865014 INFO: [NOCDAPC] D14_APC_1: 0xfff
9733 22:10:52.868462 INFO: [NOCDAPC] D15_APC_0: 0x0
9734 22:10:52.872009 INFO: [NOCDAPC] D15_APC_1: 0xfff
9735 22:10:52.875790 INFO: [NOCDAPC] APC_CON: 0x4
9736 22:10:52.878514 INFO: [APUAPC] set_apusys_apc done
9737 22:10:52.882451 INFO: [DEVAPC] devapc_init done
9738 22:10:52.885661 INFO: GICv3 without legacy support detected.
9739 22:10:52.888785 INFO: ARM GICv3 driver initialized in EL3
9740 22:10:52.891953 INFO: Maximum SPI INTID supported: 639
9741 22:10:52.898244 INFO: BL31: Initializing runtime services
9742 22:10:52.901956 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9743 22:10:52.905271 INFO: SPM: enable CPC mode
9744 22:10:52.912029 INFO: mcdi ready for mcusys-off-idle and system suspend
9745 22:10:52.915316 INFO: BL31: Preparing for EL3 exit to normal world
9746 22:10:52.918766 INFO: Entry point address = 0x80000000
9747 22:10:52.922067 INFO: SPSR = 0x8
9748 22:10:52.927237
9749 22:10:52.927721
9750 22:10:52.927999
9751 22:10:52.930057 Starting depthcharge on Spherion...
9752 22:10:52.930434
9753 22:10:52.930736 Wipe memory regions:
9754 22:10:52.930973
9755 22:10:52.932601 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9756 22:10:52.933065 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9757 22:10:52.933556 Setting prompt string to ['asurada:']
9758 22:10:52.933880 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9759 22:10:52.934433 [0x00000040000000, 0x00000054600000)
9760 22:10:53.055848
9761 22:10:53.056344 [0x00000054660000, 0x00000080000000)
9762 22:10:53.316434
9763 22:10:53.316917 [0x000000821a7280, 0x000000ffe64000)
9764 22:10:54.060886
9765 22:10:54.061408 [0x00000100000000, 0x00000140000000)
9766 22:10:54.442517
9767 22:10:54.445566 Initializing XHCI USB controller at 0x11200000.
9768 22:10:55.483023
9769 22:10:55.486431 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9770 22:10:55.486893
9771 22:10:55.487167
9772 22:10:55.487400
9773 22:10:55.488008 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9775 22:10:55.589051 asurada: tftpboot 192.168.201.1 11440308/tftp-deploy-yi_q08mg/kernel/image.itb 11440308/tftp-deploy-yi_q08mg/kernel/cmdline
9776 22:10:55.589807 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9777 22:10:55.590173 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9778 22:10:55.595121 tftpboot 192.168.201.1 11440308/tftp-deploy-yi_q08mg/kernel/image.itp-deploy-yi_q08mg/kernel/cmdline
9779 22:10:55.595508
9780 22:10:55.595782 Waiting for link
9781 22:10:55.755585
9782 22:10:55.756074 R8152: Initializing
9783 22:10:55.756359
9784 22:10:55.758926 Version 9 (ocp_data = 6010)
9785 22:10:55.759305
9786 22:10:55.762262 R8152: Done initializing
9787 22:10:55.762748
9788 22:10:55.763022 Adding net device
9789 22:10:57.886517
9790 22:10:57.887005 done.
9791 22:10:57.887281
9792 22:10:57.887519 MAC: 00:e0:4c:68:03:bd
9793 22:10:57.887753
9794 22:10:57.889505 Sending DHCP discover... done.
9795 22:10:57.889885
9796 22:11:03.679109 Waiting for reply... done.
9797 22:11:03.679591
9798 22:11:03.679867 Sending DHCP request... done.
9799 22:11:03.681681
9800 22:11:03.686683 Waiting for reply... done.
9801 22:11:03.687160
9802 22:11:03.687437 My ip is 192.168.201.16
9803 22:11:03.687678
9804 22:11:03.690274 The DHCP server ip is 192.168.201.1
9805 22:11:03.690657
9806 22:11:03.696780 TFTP server IP predefined by user: 192.168.201.1
9807 22:11:03.697266
9808 22:11:03.703267 Bootfile predefined by user: 11440308/tftp-deploy-yi_q08mg/kernel/image.itb
9809 22:11:03.703728
9810 22:11:03.706166 Sending tftp read request... done.
9811 22:11:03.706560
9812 22:11:03.712435 Waiting for the transfer...
9813 22:11:03.712801
9814 22:11:03.942150 00000000 ################################################################
9815 22:11:03.942277
9816 22:11:04.170809 00080000 ################################################################
9817 22:11:04.170959
9818 22:11:04.398423 00100000 ################################################################
9819 22:11:04.398548
9820 22:11:04.627549 00180000 ################################################################
9821 22:11:04.627708
9822 22:11:04.858857 00200000 ################################################################
9823 22:11:04.858985
9824 22:11:05.087884 00280000 ################################################################
9825 22:11:05.088012
9826 22:11:05.315613 00300000 ################################################################
9827 22:11:05.315748
9828 22:11:05.545299 00380000 ################################################################
9829 22:11:05.545436
9830 22:11:05.771620 00400000 ################################################################
9831 22:11:05.771749
9832 22:11:05.999289 00480000 ################################################################
9833 22:11:05.999426
9834 22:11:06.228082 00500000 ################################################################
9835 22:11:06.228211
9836 22:11:06.454630 00580000 ################################################################
9837 22:11:06.454764
9838 22:11:06.682401 00600000 ################################################################
9839 22:11:06.682558
9840 22:11:06.913063 00680000 ################################################################
9841 22:11:06.913217
9842 22:11:07.142377 00700000 ################################################################
9843 22:11:07.142505
9844 22:11:07.371052 00780000 ################################################################
9845 22:11:07.371215
9846 22:11:07.600014 00800000 ################################################################
9847 22:11:07.600178
9848 22:11:07.828843 00880000 ################################################################
9849 22:11:07.828989
9850 22:11:08.057550 00900000 ################################################################
9851 22:11:08.057709
9852 22:11:08.286699 00980000 ################################################################
9853 22:11:08.286855
9854 22:11:08.516145 00a00000 ################################################################
9855 22:11:08.516292
9856 22:11:08.744110 00a80000 ################################################################
9857 22:11:08.744268
9858 22:11:08.972594 00b00000 ################################################################
9859 22:11:08.972735
9860 22:11:09.202283 00b80000 ################################################################
9861 22:11:09.202428
9862 22:11:09.429437 00c00000 ################################################################
9863 22:11:09.429584
9864 22:11:09.658487 00c80000 ################################################################
9865 22:11:09.658641
9866 22:11:09.886075 00d00000 ################################################################
9867 22:11:09.886220
9868 22:11:10.114799 00d80000 ################################################################
9869 22:11:10.114943
9870 22:11:10.342215 00e00000 ################################################################
9871 22:11:10.342360
9872 22:11:10.569504 00e80000 ################################################################
9873 22:11:10.569646
9874 22:11:10.797707 00f00000 ################################################################
9875 22:11:10.797872
9876 22:11:11.026385 00f80000 ################################################################
9877 22:11:11.026533
9878 22:11:11.255439 01000000 ################################################################
9879 22:11:11.255589
9880 22:11:11.485404 01080000 ################################################################
9881 22:11:11.485540
9882 22:11:11.712624 01100000 ################################################################
9883 22:11:11.712764
9884 22:11:11.941675 01180000 ################################################################
9885 22:11:11.941819
9886 22:11:12.169319 01200000 ################################################################
9887 22:11:12.169469
9888 22:11:12.397626 01280000 ################################################################
9889 22:11:12.397766
9890 22:11:12.626809 01300000 ################################################################
9891 22:11:12.626966
9892 22:11:12.857035 01380000 ################################################################
9893 22:11:12.857181
9894 22:11:13.086757 01400000 ################################################################
9895 22:11:13.086956
9896 22:11:13.314678 01480000 ################################################################
9897 22:11:13.314833
9898 22:11:13.545463 01500000 ################################################################
9899 22:11:13.545610
9900 22:11:13.774175 01580000 ################################################################
9901 22:11:13.774320
9902 22:11:14.003330 01600000 ################################################################
9903 22:11:14.003480
9904 22:11:14.231498 01680000 ################################################################
9905 22:11:14.231650
9906 22:11:14.459905 01700000 ################################################################
9907 22:11:14.460050
9908 22:11:14.689665 01780000 ################################################################
9909 22:11:14.689820
9910 22:11:14.918577 01800000 ################################################################
9911 22:11:14.918751
9912 22:11:15.148051 01880000 ################################################################
9913 22:11:15.148199
9914 22:11:15.379430 01900000 ################################################################
9915 22:11:15.379585
9916 22:11:15.607208 01980000 ################################################################
9917 22:11:15.607347
9918 22:11:15.836404 01a00000 ################################################################
9919 22:11:15.836546
9920 22:11:16.066376 01a80000 ################################################################
9921 22:11:16.066531
9922 22:11:16.295356 01b00000 ################################################################
9923 22:11:16.295503
9924 22:11:16.523950 01b80000 ################################################################
9925 22:11:16.524090
9926 22:11:16.752462 01c00000 ################################################################
9927 22:11:16.752608
9928 22:11:16.980672 01c80000 ################################################################
9929 22:11:16.980825
9930 22:11:17.209036 01d00000 ################################################################
9931 22:11:17.209180
9932 22:11:17.437142 01d80000 ################################################################
9933 22:11:17.437290
9934 22:11:17.663051 01e00000 ################################################################
9935 22:11:17.663196
9936 22:11:17.874184 01e80000 ############################################################ done.
9937 22:11:17.874340
9938 22:11:17.877399 The bootfile was 32469982 bytes long.
9939 22:11:17.877469
9940 22:11:17.880936 Sending tftp read request... done.
9941 22:11:17.881007
9942 22:11:17.883947 Waiting for the transfer...
9943 22:11:17.884018
9944 22:11:17.887861 00000000 # done.
9945 22:11:17.888115
9946 22:11:17.894361 Command line loaded dynamically from TFTP file: 11440308/tftp-deploy-yi_q08mg/kernel/cmdline
9947 22:11:17.894771
9948 22:11:17.907842 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
9949 22:11:17.908314
9950 22:11:17.908665 Loading FIT.
9951 22:11:17.908949
9952 22:11:17.910701 Image ramdisk-1 has 21382673 bytes.
9953 22:11:17.911057
9954 22:11:17.913833 Image fdt-1 has 47278 bytes.
9955 22:11:17.914128
9956 22:11:17.917400 Image kernel-1 has 11037994 bytes.
9957 22:11:17.917781
9958 22:11:17.927434 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9959 22:11:17.927885
9960 22:11:17.943735 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9961 22:11:17.944219
9962 22:11:17.951049 Choosing best match conf-1 for compat google,spherion-rev3.
9963 22:11:17.951523
9964 22:11:17.958530 Connected to device vid:did:rid of 1ae0:0028:00
9965 22:11:17.966904
9966 22:11:17.969954 tpm_get_response: command 0x17b, return code 0x0
9967 22:11:17.970457
9968 22:11:17.972919 ec_init: CrosEC protocol v3 supported (256, 248)
9969 22:11:17.977350
9970 22:11:17.980691 tpm_cleanup: add release locality here.
9971 22:11:17.981220
9972 22:11:17.981550 Shutting down all USB controllers.
9973 22:11:17.984160
9974 22:11:17.984646 Removing current net device
9975 22:11:17.984932
9976 22:11:17.991069 Exiting depthcharge with code 4 at timestamp: 53329406
9977 22:11:17.991566
9978 22:11:17.994367 LZMA decompressing kernel-1 to 0x821a6718
9979 22:11:17.994863
9980 22:11:17.996994 LZMA decompressing kernel-1 to 0x40000000
9981 22:11:19.384029
9982 22:11:19.384512 jumping to kernel
9983 22:11:19.385633 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
9984 22:11:19.386031 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
9985 22:11:19.386329 Setting prompt string to ['Linux version [0-9]']
9986 22:11:19.386596 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9987 22:11:19.386859 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
9988 22:11:19.433753
9989 22:11:19.436655 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
9990 22:11:19.440474 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
9991 22:11:19.440914 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
9992 22:11:19.441271 Setting prompt string to []
9993 22:11:19.441681 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
9994 22:11:19.442018 Using line separator: #'\n'#
9995 22:11:19.442308 No login prompt set.
9996 22:11:19.442622 Parsing kernel messages
9997 22:11:19.442904 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
9998 22:11:19.443383 [login-action] Waiting for messages, (timeout 00:04:00)
9999 22:11:19.460516 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j35911-arm64-gcc-10-defconfig-arm64-chromebook-zzzh4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Sep 5 21:54:53 UTC 2023
10000 22:11:19.463540 [ 0.000000] random: crng init done
10001 22:11:19.469839 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10002 22:11:19.473404 [ 0.000000] efi: UEFI not found.
10003 22:11:19.479750 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10004 22:11:19.486479 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10005 22:11:19.496546 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10006 22:11:19.506155 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10007 22:11:19.513128 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10008 22:11:19.519106 [ 0.000000] printk: bootconsole [mtk8250] enabled
10009 22:11:19.526407 [ 0.000000] NUMA: No NUMA configuration found
10010 22:11:19.532406 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10011 22:11:19.535775 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10012 22:11:19.539453 [ 0.000000] Zone ranges:
10013 22:11:19.545952 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10014 22:11:19.549242 [ 0.000000] DMA32 empty
10015 22:11:19.555823 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10016 22:11:19.559252 [ 0.000000] Movable zone start for each node
10017 22:11:19.562437 [ 0.000000] Early memory node ranges
10018 22:11:19.569189 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10019 22:11:19.576048 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10020 22:11:19.582166 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10021 22:11:19.589073 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10022 22:11:19.596131 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10023 22:11:19.602121 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10024 22:11:19.632596 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10025 22:11:19.638824 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10026 22:11:19.645164 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10027 22:11:19.648709 [ 0.000000] psci: probing for conduit method from DT.
10028 22:11:19.655478 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10029 22:11:19.658678 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10030 22:11:19.665272 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10031 22:11:19.668964 [ 0.000000] psci: SMC Calling Convention v1.2
10032 22:11:19.675099 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10033 22:11:19.678940 [ 0.000000] Detected VIPT I-cache on CPU0
10034 22:11:19.684996 [ 0.000000] CPU features: detected: GIC system register CPU interface
10035 22:11:19.692251 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10036 22:11:19.698743 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10037 22:11:19.704829 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10038 22:11:19.714673 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10039 22:11:19.721091 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10040 22:11:19.724471 [ 0.000000] alternatives: applying boot alternatives
10041 22:11:19.731031 [ 0.000000] Fallback order for Node 0: 0
10042 22:11:19.737430 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10043 22:11:19.740636 [ 0.000000] Policy zone: Normal
10044 22:11:19.753839 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10045 22:11:19.764161 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10046 22:11:19.774185 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10047 22:11:19.784556 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10048 22:11:19.791406 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10049 22:11:19.794174 <6>[ 0.000000] software IO TLB: area num 8.
10050 22:11:19.850248 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10051 22:11:19.930681 <6>[ 0.000000] Memory: 3834264K/4191232K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 324200K reserved, 32768K cma-reserved)
10052 22:11:19.937354 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10053 22:11:19.943437 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10054 22:11:19.947223 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10055 22:11:19.953470 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10056 22:11:19.960599 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10057 22:11:19.963418 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10058 22:11:19.973289 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10059 22:11:19.980337 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10060 22:11:19.986513 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10061 22:11:19.993176 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10062 22:11:19.996315 <6>[ 0.000000] GICv3: 608 SPIs implemented
10063 22:11:20.000068 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10064 22:11:20.006276 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10065 22:11:20.009902 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10066 22:11:20.016576 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10067 22:11:20.029914 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10068 22:11:20.042656 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10069 22:11:20.049538 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10070 22:11:20.057023 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10071 22:11:20.070140 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10072 22:11:20.077073 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10073 22:11:20.083195 <6>[ 0.009225] Console: colour dummy device 80x25
10074 22:11:20.093579 <6>[ 0.013951] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10075 22:11:20.100090 <6>[ 0.024393] pid_max: default: 32768 minimum: 301
10076 22:11:20.103297 <6>[ 0.029264] LSM: Security Framework initializing
10077 22:11:20.109891 <6>[ 0.034178] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10078 22:11:20.119485 <6>[ 0.041784] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10079 22:11:20.126613 <6>[ 0.051069] cblist_init_generic: Setting adjustable number of callback queues.
10080 22:11:20.133137 <6>[ 0.058515] cblist_init_generic: Setting shift to 3 and lim to 1.
10081 22:11:20.142930 <6>[ 0.064853] cblist_init_generic: Setting adjustable number of callback queues.
10082 22:11:20.146004 <6>[ 0.072278] cblist_init_generic: Setting shift to 3 and lim to 1.
10083 22:11:20.153153 <6>[ 0.078715] rcu: Hierarchical SRCU implementation.
10084 22:11:20.159411 <6>[ 0.083728] rcu: Max phase no-delay instances is 1000.
10085 22:11:20.166077 <6>[ 0.090760] EFI services will not be available.
10086 22:11:20.169091 <6>[ 0.095725] smp: Bringing up secondary CPUs ...
10087 22:11:20.177668 <6>[ 0.100774] Detected VIPT I-cache on CPU1
10088 22:11:20.184608 <6>[ 0.100842] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10089 22:11:20.190315 <6>[ 0.100874] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10090 22:11:20.193709 <6>[ 0.101208] Detected VIPT I-cache on CPU2
10091 22:11:20.203495 <6>[ 0.101255] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10092 22:11:20.210557 <6>[ 0.101269] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10093 22:11:20.213696 <6>[ 0.101528] Detected VIPT I-cache on CPU3
10094 22:11:20.219820 <6>[ 0.101574] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10095 22:11:20.226936 <6>[ 0.101588] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10096 22:11:20.230131 <6>[ 0.101895] CPU features: detected: Spectre-v4
10097 22:11:20.236445 <6>[ 0.101902] CPU features: detected: Spectre-BHB
10098 22:11:20.239990 <6>[ 0.101906] Detected PIPT I-cache on CPU4
10099 22:11:20.246629 <6>[ 0.101962] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10100 22:11:20.252883 <6>[ 0.101979] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10101 22:11:20.259905 <6>[ 0.102272] Detected PIPT I-cache on CPU5
10102 22:11:20.266596 <6>[ 0.102333] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10103 22:11:20.273047 <6>[ 0.102350] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10104 22:11:20.276418 <6>[ 0.102630] Detected PIPT I-cache on CPU6
10105 22:11:20.283255 <6>[ 0.102691] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10106 22:11:20.289854 <6>[ 0.102707] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10107 22:11:20.296351 <6>[ 0.103007] Detected PIPT I-cache on CPU7
10108 22:11:20.303210 <6>[ 0.103069] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10109 22:11:20.309670 <6>[ 0.103086] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10110 22:11:20.312871 <6>[ 0.103133] smp: Brought up 1 node, 8 CPUs
10111 22:11:20.319208 <6>[ 0.244438] SMP: Total of 8 processors activated.
10112 22:11:20.322851 <6>[ 0.249359] CPU features: detected: 32-bit EL0 Support
10113 22:11:20.332856 <6>[ 0.254721] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10114 22:11:20.339377 <6>[ 0.263576] CPU features: detected: Common not Private translations
10115 22:11:20.345913 <6>[ 0.270051] CPU features: detected: CRC32 instructions
10116 22:11:20.349249 <6>[ 0.275402] CPU features: detected: RCpc load-acquire (LDAPR)
10117 22:11:20.355919 <6>[ 0.281361] CPU features: detected: LSE atomic instructions
10118 22:11:20.362686 <6>[ 0.287143] CPU features: detected: Privileged Access Never
10119 22:11:20.369009 <6>[ 0.292922] CPU features: detected: RAS Extension Support
10120 22:11:20.376404 <6>[ 0.298531] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10121 22:11:20.379429 <6>[ 0.305751] CPU: All CPU(s) started at EL2
10122 22:11:20.386073 <6>[ 0.310067] alternatives: applying system-wide alternatives
10123 22:11:20.394512 <6>[ 0.319910] devtmpfs: initialized
10124 22:11:20.408831 <6>[ 0.328121] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10125 22:11:20.415351 <6>[ 0.338084] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10126 22:11:20.421741 <6>[ 0.346107] pinctrl core: initialized pinctrl subsystem
10127 22:11:20.425524 <6>[ 0.352744] DMI not present or invalid.
10128 22:11:20.432401 <6>[ 0.357141] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10129 22:11:20.441699 <6>[ 0.363968] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10130 22:11:20.448231 <6>[ 0.371414] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10131 22:11:20.458239 <6>[ 0.379504] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10132 22:11:20.461497 <6>[ 0.387659] audit: initializing netlink subsys (disabled)
10133 22:11:20.471491 <5>[ 0.393352] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10134 22:11:20.478078 <6>[ 0.394048] thermal_sys: Registered thermal governor 'step_wise'
10135 22:11:20.484418 <6>[ 0.401317] thermal_sys: Registered thermal governor 'power_allocator'
10136 22:11:20.488417 <6>[ 0.407574] cpuidle: using governor menu
10137 22:11:20.494414 <6>[ 0.418534] NET: Registered PF_QIPCRTR protocol family
10138 22:11:20.501239 <6>[ 0.424016] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10139 22:11:20.504342 <6>[ 0.431122] ASID allocator initialised with 32768 entries
10140 22:11:20.511906 <6>[ 0.437652] Serial: AMBA PL011 UART driver
10141 22:11:20.520201 <4>[ 0.446353] Trying to register duplicate clock ID: 134
10142 22:11:20.574738 <6>[ 0.503841] KASLR enabled
10143 22:11:20.588936 <6>[ 0.511535] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10144 22:11:20.595483 <6>[ 0.518549] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10145 22:11:20.602222 <6>[ 0.525040] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10146 22:11:20.608687 <6>[ 0.532045] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10147 22:11:20.615429 <6>[ 0.538531] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10148 22:11:20.621783 <6>[ 0.545536] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10149 22:11:20.628614 <6>[ 0.552022] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10150 22:11:20.634824 <6>[ 0.559025] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10151 22:11:20.638133 <6>[ 0.566528] ACPI: Interpreter disabled.
10152 22:11:20.647341 <6>[ 0.572926] iommu: Default domain type: Translated
10153 22:11:20.653741 <6>[ 0.578039] iommu: DMA domain TLB invalidation policy: strict mode
10154 22:11:20.656823 <5>[ 0.584668] SCSI subsystem initialized
10155 22:11:20.664418 <6>[ 0.588833] usbcore: registered new interface driver usbfs
10156 22:11:20.670335 <6>[ 0.594563] usbcore: registered new interface driver hub
10157 22:11:20.673483 <6>[ 0.600115] usbcore: registered new device driver usb
10158 22:11:20.680635 <6>[ 0.606212] pps_core: LinuxPPS API ver. 1 registered
10159 22:11:20.690119 <6>[ 0.611405] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10160 22:11:20.693288 <6>[ 0.620754] PTP clock support registered
10161 22:11:20.696717 <6>[ 0.624998] EDAC MC: Ver: 3.0.0
10162 22:11:20.704664 <6>[ 0.630130] FPGA manager framework
10163 22:11:20.707850 <6>[ 0.633807] Advanced Linux Sound Architecture Driver Initialized.
10164 22:11:20.711183 <6>[ 0.640577] vgaarb: loaded
10165 22:11:20.718092 <6>[ 0.643733] clocksource: Switched to clocksource arch_sys_counter
10166 22:11:20.724549 <5>[ 0.650166] VFS: Disk quotas dquot_6.6.0
10167 22:11:20.731346 <6>[ 0.654352] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10168 22:11:20.734446 <6>[ 0.661537] pnp: PnP ACPI: disabled
10169 22:11:20.742006 <6>[ 0.668201] NET: Registered PF_INET protocol family
10170 22:11:20.748822 <6>[ 0.673580] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10171 22:11:20.761124 <6>[ 0.683591] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10172 22:11:20.770725 <6>[ 0.692377] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10173 22:11:20.777246 <6>[ 0.700342] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10174 22:11:20.783810 <6>[ 0.708746] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10175 22:11:20.794871 <6>[ 0.717405] TCP: Hash tables configured (established 32768 bind 32768)
10176 22:11:20.801387 <6>[ 0.724264] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10177 22:11:20.808130 <6>[ 0.731283] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10178 22:11:20.814602 <6>[ 0.738802] NET: Registered PF_UNIX/PF_LOCAL protocol family
10179 22:11:20.821065 <6>[ 0.744954] RPC: Registered named UNIX socket transport module.
10180 22:11:20.824269 <6>[ 0.751108] RPC: Registered udp transport module.
10181 22:11:20.831379 <6>[ 0.756040] RPC: Registered tcp transport module.
10182 22:11:20.837851 <6>[ 0.760971] RPC: Registered tcp NFSv4.1 backchannel transport module.
10183 22:11:20.840955 <6>[ 0.767636] PCI: CLS 0 bytes, default 64
10184 22:11:20.844184 <6>[ 0.772028] Unpacking initramfs...
10185 22:11:20.853864 <6>[ 0.775743] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10186 22:11:20.861038 <6>[ 0.784406] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10187 22:11:20.867801 <6>[ 0.793246] kvm [1]: IPA Size Limit: 40 bits
10188 22:11:20.870736 <6>[ 0.797776] kvm [1]: GICv3: no GICV resource entry
10189 22:11:20.877626 <6>[ 0.802799] kvm [1]: disabling GICv2 emulation
10190 22:11:20.883834 <6>[ 0.807486] kvm [1]: GIC system register CPU interface enabled
10191 22:11:20.886938 <6>[ 0.813660] kvm [1]: vgic interrupt IRQ18
10192 22:11:20.894286 <6>[ 0.818019] kvm [1]: VHE mode initialized successfully
10193 22:11:20.897391 <5>[ 0.824532] Initialise system trusted keyrings
10194 22:11:20.903650 <6>[ 0.829337] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10195 22:11:20.913915 <6>[ 0.839310] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10196 22:11:20.920169 <5>[ 0.845694] NFS: Registering the id_resolver key type
10197 22:11:20.923034 <5>[ 0.850993] Key type id_resolver registered
10198 22:11:20.930051 <5>[ 0.855407] Key type id_legacy registered
10199 22:11:20.936801 <6>[ 0.859701] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10200 22:11:20.943437 <6>[ 0.866625] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10201 22:11:20.949907 <6>[ 0.874351] 9p: Installing v9fs 9p2000 file system support
10202 22:11:20.986791 <5>[ 0.912790] Key type asymmetric registered
10203 22:11:20.990200 <5>[ 0.917121] Asymmetric key parser 'x509' registered
10204 22:11:21.000129 <6>[ 0.922263] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10205 22:11:21.003317 <6>[ 0.929879] io scheduler mq-deadline registered
10206 22:11:21.006563 <6>[ 0.934640] io scheduler kyber registered
10207 22:11:21.025459 <6>[ 0.951612] EINJ: ACPI disabled.
10208 22:11:21.057886 <4>[ 0.976947] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10209 22:11:21.067767 <4>[ 0.987584] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10210 22:11:21.082941 <6>[ 1.008504] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10211 22:11:21.091363 <6>[ 1.016607] printk: console [ttyS0] disabled
10212 22:11:21.118661 <6>[ 1.041251] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10213 22:11:21.125614 <6>[ 1.050724] printk: console [ttyS0] enabled
10214 22:11:21.128693 <6>[ 1.050724] printk: console [ttyS0] enabled
10215 22:11:21.135093 <6>[ 1.059617] printk: bootconsole [mtk8250] disabled
10216 22:11:21.138558 <6>[ 1.059617] printk: bootconsole [mtk8250] disabled
10217 22:11:21.144717 <6>[ 1.070850] SuperH (H)SCI(F) driver initialized
10218 22:11:21.148341 <6>[ 1.076148] msm_serial: driver initialized
10219 22:11:21.162523 <6>[ 1.085116] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10220 22:11:21.172613 <6>[ 1.093664] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10221 22:11:21.179165 <6>[ 1.102205] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10222 22:11:21.189069 <6>[ 1.110833] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10223 22:11:21.195880 <6>[ 1.119540] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10224 22:11:21.205894 <6>[ 1.128260] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10225 22:11:21.215755 <6>[ 1.136801] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10226 22:11:21.221753 <6>[ 1.145605] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10227 22:11:21.231761 <6>[ 1.154149] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10228 22:11:21.243587 <6>[ 1.169704] loop: module loaded
10229 22:11:21.250067 <6>[ 1.175718] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10230 22:11:21.273473 <4>[ 1.199116] mtk-pmic-keys: Failed to locate of_node [id: -1]
10231 22:11:21.280321 <6>[ 1.206094] megasas: 07.719.03.00-rc1
10232 22:11:21.289924 <6>[ 1.215907] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10233 22:11:21.297239 <6>[ 1.223160] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10234 22:11:21.313380 <6>[ 1.239126] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10235 22:11:21.369227 <6>[ 1.288630] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10236 22:11:21.744535 <6>[ 1.670638] Freeing initrd memory: 20876K
10237 22:11:21.760222 <6>[ 1.686259] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10238 22:11:21.771254 <6>[ 1.697335] tun: Universal TUN/TAP device driver, 1.6
10239 22:11:21.774911 <6>[ 1.703413] thunder_xcv, ver 1.0
10240 22:11:21.778059 <6>[ 1.706919] thunder_bgx, ver 1.0
10241 22:11:21.781648 <6>[ 1.710415] nicpf, ver 1.0
10242 22:11:21.792068 <6>[ 1.714441] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10243 22:11:21.795256 <6>[ 1.721916] hns3: Copyright (c) 2017 Huawei Corporation.
10244 22:11:21.801976 <6>[ 1.727507] hclge is initializing
10245 22:11:21.804914 <6>[ 1.731089] e1000: Intel(R) PRO/1000 Network Driver
10246 22:11:21.811496 <6>[ 1.736219] e1000: Copyright (c) 1999-2006 Intel Corporation.
10247 22:11:21.815023 <6>[ 1.742230] e1000e: Intel(R) PRO/1000 Network Driver
10248 22:11:21.821580 <6>[ 1.747446] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10249 22:11:21.828264 <6>[ 1.753633] igb: Intel(R) Gigabit Ethernet Network Driver
10250 22:11:21.835043 <6>[ 1.759283] igb: Copyright (c) 2007-2014 Intel Corporation.
10251 22:11:21.841085 <6>[ 1.765120] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10252 22:11:21.847932 <6>[ 1.771638] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10253 22:11:21.851020 <6>[ 1.778097] sky2: driver version 1.30
10254 22:11:21.858471 <6>[ 1.783099] VFIO - User Level meta-driver version: 0.3
10255 22:11:21.865444 <6>[ 1.791349] usbcore: registered new interface driver usb-storage
10256 22:11:21.871901 <6>[ 1.797796] usbcore: registered new device driver onboard-usb-hub
10257 22:11:21.881222 <6>[ 1.806930] mt6397-rtc mt6359-rtc: registered as rtc0
10258 22:11:21.891225 <6>[ 1.812396] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-05T22:11:22 UTC (1693951882)
10259 22:11:21.894101 <6>[ 1.821960] i2c_dev: i2c /dev entries driver
10260 22:11:21.910971 <6>[ 1.833748] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10261 22:11:21.931648 <6>[ 1.857725] cpu cpu0: EM: created perf domain
10262 22:11:21.935101 <6>[ 1.862690] cpu cpu4: EM: created perf domain
10263 22:11:21.942502 <6>[ 1.868269] sdhci: Secure Digital Host Controller Interface driver
10264 22:11:21.948880 <6>[ 1.874710] sdhci: Copyright(c) Pierre Ossman
10265 22:11:21.955422 <6>[ 1.879621] Synopsys Designware Multimedia Card Interface Driver
10266 22:11:21.962054 <6>[ 1.886227] sdhci-pltfm: SDHCI platform and OF driver helper
10267 22:11:21.965449 <6>[ 1.886292] mmc0: CQHCI version 5.10
10268 22:11:21.972300 <6>[ 1.896562] ledtrig-cpu: registered to indicate activity on CPUs
10269 22:11:21.978517 <6>[ 1.903567] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10270 22:11:21.985463 <6>[ 1.910592] usbcore: registered new interface driver usbhid
10271 22:11:21.988852 <6>[ 1.916415] usbhid: USB HID core driver
10272 22:11:21.995757 <6>[ 1.920622] spi_master spi0: will run message pump with realtime priority
10273 22:11:22.039740 <6>[ 1.959095] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10274 22:11:22.056306 <6>[ 1.975252] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10275 22:11:22.063202 <6>[ 1.988835] mmc0: Command Queue Engine enabled
10276 22:11:22.069932 <6>[ 1.993614] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10277 22:11:22.073119 <6>[ 2.000879] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10278 22:11:22.080020 <6>[ 2.005808] cros-ec-spi spi0.0: Chrome EC device registered
10279 22:11:22.086204 <6>[ 2.009447] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10280 22:11:22.093717 <6>[ 2.019343] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10281 22:11:22.100054 <6>[ 2.025197] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10282 22:11:22.106592 <6>[ 2.031280] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10283 22:11:22.122590 <6>[ 2.045387] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10284 22:11:22.129239 <6>[ 2.055564] NET: Registered PF_PACKET protocol family
10285 22:11:22.136252 <6>[ 2.060960] 9pnet: Installing 9P2000 support
10286 22:11:22.139392 <5>[ 2.065527] Key type dns_resolver registered
10287 22:11:22.142919 <6>[ 2.070489] registered taskstats version 1
10288 22:11:22.149109 <5>[ 2.074879] Loading compiled-in X.509 certificates
10289 22:11:22.176878 <4>[ 2.096198] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10290 22:11:22.187245 <4>[ 2.107005] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10291 22:11:22.193833 <3>[ 2.117556] debugfs: File 'uA_load' in directory '/' already present!
10292 22:11:22.199926 <3>[ 2.124263] debugfs: File 'min_uV' in directory '/' already present!
10293 22:11:22.206766 <3>[ 2.130871] debugfs: File 'max_uV' in directory '/' already present!
10294 22:11:22.213285 <3>[ 2.137484] debugfs: File 'constraint_flags' in directory '/' already present!
10295 22:11:22.224924 <3>[ 2.147262] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10296 22:11:22.233212 <6>[ 2.159307] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10297 22:11:22.240271 <6>[ 2.166132] xhci-mtk 11200000.usb: xHCI Host Controller
10298 22:11:22.246837 <6>[ 2.171627] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10299 22:11:22.256521 <6>[ 2.179485] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10300 22:11:22.263422 <6>[ 2.188920] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10301 22:11:22.269991 <6>[ 2.195003] xhci-mtk 11200000.usb: xHCI Host Controller
10302 22:11:22.276483 <6>[ 2.200492] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10303 22:11:22.283407 <6>[ 2.208142] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10304 22:11:22.289741 <6>[ 2.215912] hub 1-0:1.0: USB hub found
10305 22:11:22.293434 <6>[ 2.219926] hub 1-0:1.0: 1 port detected
10306 22:11:22.302872 <6>[ 2.224208] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10307 22:11:22.306547 <6>[ 2.232936] hub 2-0:1.0: USB hub found
10308 22:11:22.309511 <6>[ 2.236960] hub 2-0:1.0: 1 port detected
10309 22:11:22.318114 <6>[ 2.244096] mtk-msdc 11f70000.mmc: Got CD GPIO
10310 22:11:22.329897 <6>[ 2.252383] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10311 22:11:22.336752 <6>[ 2.260411] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10312 22:11:22.346017 <4>[ 2.268305] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10313 22:11:22.355906 <6>[ 2.277819] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10314 22:11:22.362761 <6>[ 2.285895] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10315 22:11:22.369982 <6>[ 2.293915] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10316 22:11:22.379563 <6>[ 2.301826] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10317 22:11:22.386326 <6>[ 2.309646] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10318 22:11:22.396417 <6>[ 2.317463] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10319 22:11:22.406414 <6>[ 2.327694] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10320 22:11:22.412318 <6>[ 2.336046] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10321 22:11:22.422631 <6>[ 2.344390] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10322 22:11:22.428895 <6>[ 2.352727] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10323 22:11:22.438878 <6>[ 2.361063] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10324 22:11:22.445508 <6>[ 2.369400] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10325 22:11:22.455209 <6>[ 2.377737] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10326 22:11:22.461816 <6>[ 2.386074] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10327 22:11:22.471731 <6>[ 2.394411] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10328 22:11:22.478364 <6>[ 2.402748] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10329 22:11:22.488769 <6>[ 2.411085] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10330 22:11:22.495624 <6>[ 2.419422] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10331 22:11:22.505356 <6>[ 2.427759] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10332 22:11:22.515050 <6>[ 2.436096] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10333 22:11:22.521217 <6>[ 2.444435] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10334 22:11:22.528544 <6>[ 2.453170] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10335 22:11:22.535095 <6>[ 2.460300] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10336 22:11:22.541668 <6>[ 2.467058] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10337 22:11:22.548238 <6>[ 2.473798] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10338 22:11:22.558116 <6>[ 2.480711] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10339 22:11:22.564582 <6>[ 2.487557] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10340 22:11:22.574653 <6>[ 2.496689] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10341 22:11:22.584617 <6>[ 2.505811] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10342 22:11:22.594004 <6>[ 2.515104] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10343 22:11:22.604167 <6>[ 2.524571] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10344 22:11:22.611295 <6>[ 2.534037] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10345 22:11:22.621489 <6>[ 2.543157] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10346 22:11:22.630897 <6>[ 2.552623] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10347 22:11:22.641014 <6>[ 2.561741] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10348 22:11:22.650520 <6>[ 2.571035] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10349 22:11:22.660650 <6>[ 2.581194] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10350 22:11:22.670365 <6>[ 2.592519] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10351 22:11:22.713037 <6>[ 2.635967] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10352 22:11:22.866592 <6>[ 2.792551] hub 1-1:1.0: USB hub found
10353 22:11:22.870065 <6>[ 2.796951] hub 1-1:1.0: 4 ports detected
10354 22:11:22.993071 <6>[ 2.916258] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10355 22:11:23.019238 <6>[ 2.945086] hub 2-1:1.0: USB hub found
10356 22:11:23.022417 <6>[ 2.949563] hub 2-1:1.0: 3 ports detected
10357 22:11:23.189143 <6>[ 3.112024] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10358 22:11:23.321963 <6>[ 3.248075] hub 1-1.4:1.0: USB hub found
10359 22:11:23.324815 <6>[ 3.252794] hub 1-1.4:1.0: 2 ports detected
10360 22:11:23.400848 <6>[ 3.324068] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10361 22:11:23.621173 <6>[ 3.544050] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10362 22:11:23.813450 <6>[ 3.736047] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10363 22:11:34.966014 <6>[ 14.897007] ALSA device list:
10364 22:11:34.972905 <6>[ 14.900300] No soundcards found.
10365 22:11:34.980451 <6>[ 14.908072] Freeing unused kernel memory: 8384K
10366 22:11:34.983996 <6>[ 14.913074] Run /init as init process
10367 22:11:35.018088 Starting syslogd: OK
10368 22:11:35.023500 Starting klogd: OK
10369 22:11:35.032696 Running sysctl: OK
10370 22:11:35.039229 Populating /dev using udev: <30>[ 14.967545] udevd[187]: starting version 3.2.9
10371 22:11:35.046415 <27>[ 14.974009] udevd[187]: specified user 'tss' unknown
10372 22:11:35.052935 <27>[ 14.979354] udevd[187]: specified group 'tss' unknown
10373 22:11:35.056801 <30>[ 14.985707] udevd[188]: starting eudev-3.2.9
10374 22:11:35.073294 <27>[ 15.000843] udevd[188]: specified user 'tss' unknown
10375 22:11:35.079961 <27>[ 15.006268] udevd[188]: specified group 'tss' unknown
10376 22:11:35.211593 <6>[ 15.135655] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10377 22:11:35.218092 <6>[ 15.144541] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10378 22:11:35.227959 <6>[ 15.152266] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10379 22:11:35.238087 <3>[ 15.154448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10380 22:11:35.244847 <6>[ 15.161217] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10381 22:11:35.254661 <3>[ 15.169143] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10382 22:11:35.257799 <6>[ 15.178110] remoteproc remoteproc0: scp is available
10383 22:11:35.264994 <6>[ 15.192520] remoteproc remoteproc0: powering up scp
10384 22:11:35.272120 <3>[ 15.193166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10385 22:11:35.281742 <6>[ 15.197723] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10386 22:11:35.288707 <6>[ 15.197762] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10387 22:11:35.294992 <6>[ 15.204380] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10388 22:11:35.305347 <3>[ 15.205960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10389 22:11:35.308199 <6>[ 15.221784] mc: Linux media interface: v0.10
10390 22:11:35.315004 <6>[ 15.222128] usbcore: registered new interface driver r8152
10391 22:11:35.321137 <3>[ 15.228672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10392 22:11:35.331723 <4>[ 15.240797] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10393 22:11:35.334923 <4>[ 15.240797] Fallback method does not support PEC.
10394 22:11:35.341850 <3>[ 15.246079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10395 22:11:35.351657 <3>[ 15.246088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10396 22:11:35.359370 <3>[ 15.246096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10397 22:11:35.368868 <3>[ 15.246168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10398 22:11:35.372433 <6>[ 15.255471] videodev: Linux video capture interface: v2.00
10399 22:11:35.382222 <3>[ 15.268008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10400 22:11:35.388515 <4>[ 15.269230] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10401 22:11:35.395045 <4>[ 15.269377] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10402 22:11:35.405490 <3>[ 15.270389] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10403 22:11:35.414932 <3>[ 15.293448] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10404 22:11:35.421213 <3>[ 15.300279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10405 22:11:35.431534 <3>[ 15.300288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10406 22:11:35.437947 <6>[ 15.304062] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10407 22:11:35.445419 <6>[ 15.305305] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10408 22:11:35.448153 <6>[ 15.305313] pci_bus 0000:00: root bus resource [bus 00-ff]
10409 22:11:35.458076 <6>[ 15.305320] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10410 22:11:35.468142 <6>[ 15.305326] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10411 22:11:35.474445 <6>[ 15.305361] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10412 22:11:35.481105 <6>[ 15.305387] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10413 22:11:35.484814 <6>[ 15.305477] pci 0000:00:00.0: supports D1 D2
10414 22:11:35.490880 <6>[ 15.305482] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10415 22:11:35.501042 <6>[ 15.307197] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10416 22:11:35.507539 <3>[ 15.314239] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10417 22:11:35.513882 <6>[ 15.321771] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10418 22:11:35.524082 <6>[ 15.323142] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10419 22:11:35.530845 <6>[ 15.323157] remoteproc remoteproc0: remote processor scp is now up
10420 22:11:35.537241 <6>[ 15.323157] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10421 22:11:35.547617 <4>[ 15.327210] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10422 22:11:35.553611 <4>[ 15.327216] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10423 22:11:35.560343 <3>[ 15.328796] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10424 22:11:35.570493 <3>[ 15.328798] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10425 22:11:35.577384 <3>[ 15.328802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10426 22:11:35.586836 <3>[ 15.328805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10427 22:11:35.593390 <3>[ 15.328832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10428 22:11:35.603384 <6>[ 15.356781] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10429 22:11:35.613229 <6>[ 15.362972] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10430 22:11:35.619812 <6>[ 15.363825] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10431 22:11:35.629832 <6>[ 15.366191] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10432 22:11:35.636194 <6>[ 15.370053] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10433 22:11:35.645983 <6>[ 15.376662] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10434 22:11:35.652698 <6>[ 15.378731] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10435 22:11:35.659638 <6>[ 15.400116] usbcore: registered new interface driver cdc_ether
10436 22:11:35.666553 <6>[ 15.406051] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10437 22:11:35.672673 <6>[ 15.406587] Bluetooth: Core ver 2.22
10438 22:11:35.675996 <6>[ 15.406694] NET: Registered PF_BLUETOOTH protocol family
10439 22:11:35.682522 <6>[ 15.406701] Bluetooth: HCI device and connection manager initialized
10440 22:11:35.689086 <6>[ 15.406733] Bluetooth: HCI socket layer initialized
10441 22:11:35.692783 <6>[ 15.406738] Bluetooth: L2CAP socket layer initialized
10442 22:11:35.699256 <6>[ 15.406751] Bluetooth: SCO socket layer initialized
10443 22:11:35.705178 <6>[ 15.424749] usbcore: registered new interface driver r8153_ecm
10444 22:11:35.709172 <6>[ 15.433117] pci 0000:01:00.0: supports D1 D2
10445 22:11:35.715374 <6>[ 15.448142] usbcore: registered new interface driver btusb
10446 22:11:35.722145 <6>[ 15.455799] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10447 22:11:35.729119 <6>[ 15.455861] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10448 22:11:35.732136 <6>[ 15.456050] r8152 2-1.3:1.0 eth0: v1.12.13
10449 22:11:35.745377 <4>[ 15.456279] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10450 22:11:35.748600 <3>[ 15.456293] Bluetooth: hci0: Failed to load firmware file (-2)
10451 22:11:35.755768 <3>[ 15.456296] Bluetooth: hci0: Failed to set up firmware (-2)
10452 22:11:35.765728 <4>[ 15.456301] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10453 22:11:35.778713 <6>[ 15.457733] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10454 22:11:35.785102 <6>[ 15.457826] usbcore: registered new interface driver uvcvideo
10455 22:11:35.791446 <6>[ 15.478935] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10456 22:11:35.811816 <6>[ 15.736142] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10457 22:11:35.818984 <6>[ 15.743093] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10458 22:11:35.825357 <6>[ 15.751193] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10459 22:11:35.835489 <6>[ 15.759190] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10460 22:11:35.841844 <6>[ 15.767191] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10461 22:11:35.851387 <6>[ 15.775191] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10462 22:11:35.854905 <6>[ 15.783190] pci 0000:00:00.0: PCI bridge to [bus 01]
10463 22:11:35.865159 <6>[ 15.788406] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10464 22:11:35.871661 <6>[ 15.796601] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10465 22:11:35.877948 <6>[ 15.803432] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10466 22:11:35.884709 <6>[ 15.810252] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10467 22:11:35.905703 <5>[ 15.829842] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10468 22:11:35.924557 <5>[ 15.849139] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10469 22:11:35.931609 <4>[ 15.856173] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10470 22:11:35.938151 <6>[ 15.865141] cfg80211: failed to load regulatory.db
10471 22:11:35.998738 <6>[ 15.922951] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10472 22:11:36.005683 <6>[ 15.930545] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10473 22:11:36.029775 <6>[ 15.957582] mt7921e 0000:01:00.0: ASIC revision: 79610010
10474 22:11:36.134789 <4>[ 16.056226] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10475 22:11:36.135263 done
10476 22:11:36.153955 Saving random seed: OK
10477 22:11:36.169224 Starting network: OK
10478 22:11:36.204920 Starting dropbear sshd: <6>[ 16.132576] NET: Registered PF_INET6 protocol family
10479 22:11:36.211872 <6>[ 16.139054] Segment Routing with IPv6
10480 22:11:36.214832 <6>[ 16.143178] In-situ OAM (IOAM) with IPv6
10481 22:11:36.218996 OK
10482 22:11:36.230982 /bin/sh: can't access tty; job control turned off
10483 22:11:36.231873 Matched prompt #10: / #
10485 22:11:36.232731 Setting prompt string to ['/ #']
10486 22:11:36.233080 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10488 22:11:36.233922 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10489 22:11:36.234278 start: 2.2.6 expect-shell-connection (timeout 00:03:43) [common]
10490 22:11:36.234561 Setting prompt string to ['/ #']
10491 22:11:36.234801 Forcing a shell prompt, looking for ['/ #']
10493 22:11:36.285493 / #
10494 22:11:36.286077 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10495 22:11:36.286465 Waiting using forced prompt support (timeout 00:02:30)
10496 22:11:36.286885 <4>[ 16.178121] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10497 22:11:36.291604
10498 22:11:36.292593 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10499 22:11:36.293016 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
10500 22:11:36.293447 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10501 22:11:36.293817 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
10502 22:11:36.294159 end: 2 depthcharge-action (duration 00:01:17) [common]
10503 22:11:36.294492 start: 3 lava-test-retry (timeout 00:01:00) [common]
10504 22:11:36.294827 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10505 22:11:36.295106 Using namespace: common
10507 22:11:36.396047 / # #
10508 22:11:36.396635 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10509 22:11:36.397133 #<4>[ 16.295487] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10510 22:11:36.402742
10511 22:11:36.403518 Using /lava-11440308
10513 22:11:36.504542 / # export SHELL=/bin/sh
10514 22:11:36.505273 export SHELL=/bin/sh<4>[ 16.416219] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10515 22:11:36.511238
10517 22:11:36.612770 / # . /lava-11440308/environment
10518 22:11:36.615256 . /lava-11440308/environment<4>[ 16.536348] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10519 22:11:36.657813
10521 22:11:36.759404 / # /lava-11440308/bin/lava-test-runner /lava-11440308/0
10522 22:11:36.759970 Test shell timeout: 10s (minimum of the action and connection timeout)
10523 22:11:36.761347 /lava-11440308/bin/lava-test-runner /lava-11440308/0<4>[ 16.656474] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10524 22:11:36.765836
10525 22:11:36.809785 + export 'TESTRUN_ID=0_dmesg'
10526 22:11:36.810266 +<8>[ 16.717895] <LAVA_SIGNAL_STARTRUN 0_dmesg 11440308_1.5.2.3.1>
10527 22:11:36.810546 cd /lava-11440308/0/tests/0_dmesg
10528 22:11:36.810812 + cat uuid
10529 22:11:36.811065 + UUID=11440308_1.5.2.3.1
10530 22:11:36.811300 + set +x
10531 22:11:36.811527 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10532 22:11:36.812013 Received signal: <STARTRUN> 0_dmesg 11440308_1.5.2.3.1
10533 22:11:36.812296 Starting test lava.0_dmesg (11440308_1.5.2.3.1)
10534 22:11:36.812613 Skipping test definition patterns.
10535 22:11:36.813021 <8>[ 16.735445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10536 22:11:36.813555 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10538 22:11:36.831793 <8>[ 16.756098] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10539 22:11:36.832531 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10541 22:11:36.857249 <4>[ 16.778316] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10542 22:11:36.864249 <8>[ 16.780053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10543 22:11:36.864999 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10545 22:11:36.869402 + set +x
10546 22:11:36.873223 Received signal: <ENDRUN> 0_dmesg 11440308_1.5.2.3.1
10547 22:11:36.873755 Ending use of test pattern.
10548 22:11:36.874040 Ending test lava.0_dmesg (11440308_1.5.2.3.1), duration 0.06
10550 22:11:36.875960 <8>[ 16.800468] <LAVA_SIGNAL_ENDRUN 0_dmesg 11440308_1.5.2.3.1>
10551 22:11:36.879211 <LAVA_TEST_RUNNER EXIT>
10552 22:11:36.879951 ok: lava_test_shell seems to have completed
10553 22:11:36.880414 alert: pass
crit: pass
emerg: pass
10554 22:11:36.880754 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10555 22:11:36.881080 end: 3 lava-test-retry (duration 00:00:01) [common]
10556 22:11:36.881451 start: 4 lava-test-retry (timeout 00:01:00) [common]
10557 22:11:36.881776 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10558 22:11:36.882039 Using namespace: common
10560 22:11:36.982975 / # #
10561 22:11:36.983570 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10562 22:11:36.984080 Using /lava-11440308
10564 22:11:37.085143 export SHELL=/bin/sh
10565 22:11:37.085921 #<4>[ 16.896082] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10566 22:11:37.086302
10568 22:11:37.187574 / # export SHELL=/bin/sh<4>[ 17.016471] mt7921e 0000:01:00.0. /lava-11440308/environment
10569 22:11:37.188273 : Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10570 22:11:37.188599
10572 22:11:37.289876 / # . /lava-11440308/environment/lava-11440308/bin/lava-test-runner /lava-11440308/1
10573 22:11:37.290427 Test shell timeout: 10s (minimum of the action and connection timeout)
10574 22:11:37.290880
10575 22:11:37.291158 / # <4>[ 17.136357] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10576 22:11:37.296318 /lava-11440308/bin/lava-test-runner /lava-11440308/1
10577 22:11:37.337816 + export 'TESTRUN_ID=1_bootrr'
10578 22:11:37.338294 + cd /lava-11440<8>[ 17.249209] <LAVA_SIGNAL_STARTRUN 1_bootrr 11440308_1.5.2.3.5>
10579 22:11:37.338573 <3>[ 17.253267] mt7921e 0000:01:00.0: hardware init failed
10580 22:11:37.338817 308/1/tests/1_bootrr
10581 22:11:37.339052 + cat uuid
10582 22:11:37.339280 + UUID=11440308_1.5.2.3.5
10583 22:11:37.339509 + set +x
10584 22:11:37.339992 Received signal: <STARTRUN> 1_bootrr 11440308_1.5.2.3.5
10585 22:11:37.340265 Starting test lava.1_bootrr (11440308_1.5.2.3.5)
10586 22:11:37.340569 Skipping test definition patterns.
10587 22:11:37.345186 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11440308/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10588 22:11:37.354930 + cd /opt/bootr<8>[ 17.277695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10589 22:11:37.355381 r/libexec/bootrr
10590 22:11:37.355892 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10592 22:11:37.358584 + sh helpers/bootrr-auto
10593 22:11:37.361785 /lava-11440308/1/../bin/lava-test-case
10594 22:11:37.364975 /lava-11440308/1/../bin/lava-test-case
10595 22:11:37.371768 <8>[ 17.296428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10596 22:11:37.372516 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10598 22:11:37.376875 /usr/bin/tpm2_getcap
10599 22:11:37.411447 /lava-11440308/1/../bin/lava-test-case
10600 22:11:37.417836 <8>[ 17.343143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10601 22:11:37.418570 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10603 22:11:37.438630 /lava-11440308/1/../bin/lava-test-case
10604 22:11:37.444920 <8>[ 17.369473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10605 22:11:37.445717 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10607 22:11:37.455766 /lava-11440308/1/../bin/lava-test-case
10608 22:11:37.462177 <8>[ 17.386665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10609 22:11:37.462919 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10611 22:11:37.474820 /lava-11440308/1/../bin/lava-test-case
10612 22:11:37.481343 <8>[ 17.407078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10613 22:11:37.482097 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10615 22:11:37.494374 /lava-11440308/1/../bin/lava-test-case
10616 22:11:37.504278 <8>[ 17.428678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10617 22:11:37.505023 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10619 22:11:37.514156 /lava-11440308/1/../bin/lava-test-case
10620 22:11:37.520828 <8>[ 17.445523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10621 22:11:37.521613 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10623 22:11:37.529534 /lava-11440308/1/../bin/lava-test-case
10624 22:11:37.535643 <8>[ 17.460929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10625 22:11:37.536418 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10627 22:11:37.548446 /lava-11440308/1/../bin/lava-test-case
10628 22:11:37.554743 <8>[ 17.479188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10629 22:11:37.555485 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10631 22:11:37.571694 /lava-11440308/1/../bin/lava-tes<8>[ 17.495599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10632 22:11:37.572170 t-case
10633 22:11:37.572701 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10635 22:11:37.582045 /lava-11440308/1/../bin/lava-test-case
10636 22:11:37.588652 <8>[ 17.513874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10637 22:11:37.589395 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10639 22:11:37.607533 /lava-11440308/1/../bin/lava-tes<8>[ 17.531015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10640 22:11:37.608024 t-case
10641 22:11:37.608557 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10643 22:11:37.618919 /lava-11440308/1/../bin/lava-test-case
10644 22:11:37.625507 <8>[ 17.550201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10645 22:11:37.626257 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10647 22:11:37.636841 /lava-11440308/1/../bin/lava-test-case
10648 22:11:37.643106 <8>[ 17.567688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10649 22:11:37.643819 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10651 22:11:37.652348 /lava-11440308/1/../bin/lava-test-case
10652 22:11:37.658953 <8>[ 17.583124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10653 22:11:37.659681 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10655 22:11:37.672142 /lava-11440308/1/../bin/lava-test-case
10656 22:11:37.678444 <8>[ 17.603060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10657 22:11:37.679154 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10659 22:11:37.686209 /lava-11440308/1/../bin/lava-test-case
10660 22:11:37.695792 <8>[ 17.619252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10661 22:11:37.696518 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10663 22:11:37.705664 /lava-11440308/1/../bin/lava-test-case
10664 22:11:37.712470 <8>[ 17.636797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10665 22:11:37.713225 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10667 22:11:37.720238 /lava-11440308/1/../bin/lava-test-case
10668 22:11:37.726654 <8>[ 17.652236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10669 22:11:37.727406 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10671 22:11:37.738391 /lava-11440308/1/../bin/lava-test-case
10672 22:11:37.744993 <8>[ 17.669357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10673 22:11:37.745766 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10675 22:11:37.752417 /lava-11440308/1/../bin/lava-test-case
10676 22:11:37.759214 <8>[ 17.684403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10677 22:11:37.759962 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10679 22:11:37.772694 /lava-11440308/1/../bin/lava-test-case
10680 22:11:37.779303 <8>[ 17.703207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10681 22:11:37.780051 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10683 22:11:37.787514 /lava-11440308/1/../bin/lava-test-case
10684 22:11:37.793780 <8>[ 17.719669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10685 22:11:37.794530 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10687 22:11:37.805899 /lava-11440308/1/../bin/lava-test-case
10688 22:11:37.812949 <8>[ 17.737460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10689 22:11:37.813741 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10691 22:11:37.823046 /lava-11440308/1/../bin/lava-test-case
10692 22:11:37.829173 <8>[ 17.753995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10693 22:11:37.830019 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10695 22:11:37.836950 /lava-11440308/1/../bin/lava-test-case
10696 22:11:37.847335 <8>[ 17.772075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10697 22:11:37.848091 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10699 22:11:37.858851 /lava-11440308/1/../bin/lava-test-case
10700 22:11:37.865477 <8>[ 17.790068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10701 22:11:37.866220 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10703 22:11:37.873864 /lava-11440308/1/../bin/lava-test-case
10704 22:11:37.880016 <8>[ 17.805716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10705 22:11:37.880759 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10707 22:11:37.892008 /lava-11440308/1/../bin/lava-test-case
10708 22:11:37.898942 <8>[ 17.823114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10709 22:11:37.899686 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10711 22:11:37.907902 /lava-11440308/1/../bin/lava-test-case
10712 22:11:37.914849 <8>[ 17.840215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10713 22:11:37.915582 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10715 22:11:37.925991 /lava-11440308/1/../bin/lava-test-case
10716 22:11:37.932360 <8>[ 17.857303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10717 22:11:37.933110 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10719 22:11:37.942378 /lava-11440308/1/../bin/lava-test-case
10720 22:11:37.952591 <8>[ 17.877051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10721 22:11:37.953382 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10723 22:11:37.961549 /lava-11440308/1/../bin/lava-test-case
10724 22:11:37.968030 <8>[ 17.892813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10725 22:11:37.968789 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10727 22:11:37.978024 /lava-11440308/1/../bin/lava-test-case
10728 22:11:37.984939 <8>[ 17.910205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10729 22:11:37.985741 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10731 22:11:37.995720 /lava-11440308/1/../bin/lava-test-case
10732 22:11:38.002227 <8>[ 17.926568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10733 22:11:38.002971 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10735 22:11:38.010154 /lava-11440308/1/../bin/lava-test-case
10736 22:11:38.016868 <8>[ 17.942095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10737 22:11:38.017648 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10739 22:11:38.028951 /lava-11440308/1/../bin/lava-test-case
10740 22:11:38.035401 <8>[ 17.960411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10741 22:11:38.036270 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10743 22:11:38.043892 /lava-11440308/1/../bin/lava-test-case
10744 22:11:38.053885 <8>[ 17.976934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10745 22:11:38.054632 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10747 22:11:38.070497 /lava-11440308/1/../bin/lava-tes<8>[ 17.994558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10748 22:11:38.070972 t-case
10749 22:11:38.071488 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10751 22:11:38.080285 /lava-11440308/1/../bin/lava-test-case
10752 22:11:38.089700 <8>[ 18.012919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10753 22:11:38.090441 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10755 22:11:38.099495 /lava-11440308/1/../bin/lava-test-case
10756 22:11:38.106109 <8>[ 18.032274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10757 22:11:38.106855 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10759 22:11:38.115652 /lava-11440308/1/../bin/lava-test-case
10760 22:11:38.122119 <8>[ 18.047620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10761 22:11:38.122858 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10763 22:11:38.134810 /lava-11440308/1/../bin/lava-test-case
10764 22:11:38.141010 <8>[ 18.065483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
10765 22:11:38.141818 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
10767 22:11:38.157040 /lava-11440308/1/../bin/lava-tes<8>[ 18.081263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
10768 22:11:38.157663 t-case
10769 22:11:38.158199 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
10771 22:11:38.178408 /lava-11440308/1/../bin/lava-tes<8>[ 18.101976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
10772 22:11:38.178889 t-case
10773 22:11:38.179414 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
10775 22:11:38.185436 /lava-11440308/1/../bin/lava-test-case
10776 22:11:38.192139 <8>[ 18.116483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
10777 22:11:38.192887 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
10779 22:11:38.203114 /lava-11440308/1/../bin/lava-test-case
10780 22:11:38.210086 <8>[ 18.134825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
10781 22:11:38.210830 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
10783 22:11:38.217696 /lava-11440308/1/../bin/lava-test-case
10784 22:11:38.224275 <8>[ 18.149366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
10785 22:11:38.225022 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
10787 22:11:38.234722 /lava-11440308/1/../bin/lava-test-case
10788 22:11:38.241278 <8>[ 18.166795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
10789 22:11:38.242089 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
10791 22:11:38.259885 /lava-11440308/1/../bin/lava-tes<8>[ 18.183335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
10792 22:11:38.260354 t-case
10793 22:11:38.260879 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
10795 22:11:38.266684 /lava-11440308/1/../bin/lava-test-case
10796 22:11:38.276851 <8>[ 18.201516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
10797 22:11:38.277664 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
10799 22:11:38.287987 /lava-11440308/1/../bin/lava-test-case
10800 22:11:38.294001 <8>[ 18.220266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
10801 22:11:38.294768 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
10803 22:11:38.304068 /lava-11440308/1/../bin/lava-test-case
10804 22:11:38.310512 <8>[ 18.235587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
10805 22:11:38.311263 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
10807 22:11:38.328472 /lava-11440308/1/../bin/lava-tes<8>[ 18.252324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
10808 22:11:38.328966 t-case
10809 22:11:38.329489 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
10811 22:11:38.337448 /lava-11440308/1/../bin/lava-test-case
10812 22:11:38.344210 <8>[ 18.270062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
10813 22:11:38.344973 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
10815 22:11:38.354490 /lava-11440308/1/../bin/lava-test-case
10816 22:11:38.360966 <8>[ 18.286491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
10817 22:11:38.361628 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
10819 22:11:38.372268 /lava-11440308/1/../bin/lava-test-case
10820 22:11:38.378902 <8>[ 18.305285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
10821 22:11:38.379655 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
10823 22:11:38.390596 /lava-11440308/1/../bin/lava-test-case
10824 22:11:38.396764 <8>[ 18.321815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
10825 22:11:38.397626 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
10827 22:11:38.405104 /lava-11440308/1/../bin/lava-test-case
10828 22:11:38.411205 <8>[ 18.335654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
10829 22:11:38.411970 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
10831 22:11:38.421821 /lava-11440308/1/../bin/lava-test-case
10832 22:11:38.431897 <8>[ 18.356464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
10833 22:11:38.432668 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
10835 22:11:38.440396 /lava-11440308/1/../bin/lava-test-case
10836 22:11:38.451065 <8>[ 18.375277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
10837 22:11:38.451835 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
10839 22:11:38.458170 /lava-11440308/1/../bin/lava-test-case
10840 22:11:38.465520 <8>[ 18.389542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
10841 22:11:38.466318 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
10843 22:11:38.477100 /lava-11440308/1/../bin/lava-test-case
10844 22:11:38.483522 <8>[ 18.410038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
10845 22:11:38.484269 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
10847 22:11:38.493143 /lava-11440308/1/../bin/lava-test-case
10848 22:11:38.499699 <8>[ 18.425154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
10849 22:11:38.500426 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
10851 22:11:38.512962 /lava-11440308/1/../bin/lava-test-case
10852 22:11:38.519655 <8>[ 18.444276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
10853 22:11:38.520407 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
10855 22:11:38.527719 /lava-11440308/1/../bin/lava-test-case
10856 22:11:38.534107 <8>[ 18.459275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
10857 22:11:38.534859 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
10859 22:11:38.544835 /lava-11440308/1/../bin/lava-test-case
10860 22:11:38.550923 <8>[ 18.476566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
10861 22:11:38.551645 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
10863 22:11:38.561157 /lava-11440308/1/../bin/lava-test-case
10864 22:11:38.567899 <8>[ 18.493271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
10865 22:11:38.568642 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
10867 22:11:38.578420 /lava-11440308/1/../bin/lava-test-case
10868 22:11:38.585161 <8>[ 18.509762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
10869 22:11:38.585990 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
10871 22:11:38.595204 /lava-11440308/1/../bin/lava-test-case
10872 22:11:38.601922 <8>[ 18.526205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
10873 22:11:38.602668 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
10875 22:11:38.611469 /lava-11440308/1/../bin/lava-test-case
10876 22:11:38.618162 <8>[ 18.543857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
10877 22:11:38.618908 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
10879 22:11:38.628919 /lava-11440308/1/../bin/lava-test-case
10880 22:11:38.635054 <8>[ 18.560473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
10881 22:11:38.635792 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
10883 22:11:38.644972 /lava-11440308/1/../bin/lava-test-case
10884 22:11:38.651688 <8>[ 18.577212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
10885 22:11:38.652437 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
10887 22:11:38.662957 /lava-11440308/1/../bin/lava-test-case
10888 22:11:38.669098 <8>[ 18.593970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
10889 22:11:38.669854 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
10891 22:11:38.678445 /lava-11440308/1/../bin/lava-test-case
10892 22:11:38.684974 <8>[ 18.610640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
10893 22:11:38.685758 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
10895 22:11:38.695867 /lava-11440308/1/../bin/lava-test-case
10896 22:11:38.701755 <8>[ 18.627363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
10897 22:11:38.702405 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
10899 22:11:38.711776 /lava-11440308/1/../bin/lava-test-case
10900 22:11:38.718520 <8>[ 18.643576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
10901 22:11:38.719180 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
10903 22:11:38.729179 /lava-11440308/1/../bin/lava-test-case
10904 22:11:38.735460 <8>[ 18.660394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
10905 22:11:38.736209 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
10907 22:11:38.753384 /lava-11440308/1/../bin/lava-tes<8>[ 18.677297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
10908 22:11:38.753877 t-case
10909 22:11:38.754412 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
10911 22:11:38.770518 /lava-11440308/1/../bin/lava-tes<8>[ 18.694216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
10912 22:11:38.771014 t-case
10913 22:11:38.771550 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
10915 22:11:38.780128 /lava-11440308/1/../bin/lava-test-case
10916 22:11:38.789483 <8>[ 18.714701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
10917 22:11:38.790197 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
10919 22:11:38.798433 /lava-11440308/1/../bin/lava-test-case
10920 22:11:38.805613 <8>[ 18.730940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
10921 22:11:38.806359 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
10923 22:11:38.816640 /lava-11440308/1/../bin/lava-test-case
10924 22:11:38.823061 <8>[ 18.747963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
10925 22:11:38.823804 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
10927 22:11:38.830997 /lava-11440308/1/../bin/lava-test-case
10928 22:11:38.837822 <8>[ 18.762925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
10929 22:11:38.838583 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
10931 22:11:38.849137 /lava-11440308/1/../bin/lava-test-case
10932 22:11:38.855994 <8>[ 18.781493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
10933 22:11:38.856738 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
10935 22:11:38.864347 /lava-11440308/1/../bin/lava-test-case
10936 22:11:38.871254 <8>[ 18.795361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
10937 22:11:38.872011 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
10939 22:11:38.883126 /lava-11440308/1/../bin/lava-test-case
10940 22:11:38.889670 <8>[ 18.814463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
10941 22:11:38.890410 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
10943 22:11:38.898043 /lava-11440308/1/../bin/lava-test-case
10944 22:11:38.904609 <8>[ 18.829938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
10945 22:11:38.905457 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
10947 22:11:38.915042 /lava-11440308/1/../bin/lava-test-case
10948 22:11:38.921899 <8>[ 18.846026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
10949 22:11:38.922641 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
10951 22:11:38.937090 /lava-11440308/1/../bin/lava-tes<8>[ 18.861074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
10952 22:11:38.937620 t-case
10953 22:11:38.938155 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
10955 22:11:38.958191 /lava-11440308/1/../bin/lava-tes<8>[ 18.882263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
10956 22:11:38.958661 t-case
10957 22:11:38.959193 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
10959 22:11:38.965508 /lava-11440308/1/../bin/lava-test-case
10960 22:11:38.971837 <8>[ 18.897134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
10961 22:11:38.972585 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
10963 22:11:38.983160 /lava-11440308/1/../bin/lava-test-case
10964 22:11:38.989661 <8>[ 18.914550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
10965 22:11:38.990376 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
10967 22:11:39.001220 /lava-11440308/1/../bin/lava-test-case
10968 22:11:39.007367 <8>[ 18.932360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
10969 22:11:39.008114 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
10971 22:11:39.016177 /lava-11440308/1/../bin/lava-test-case
10972 22:11:39.022917 <8>[ 18.947906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
10973 22:11:39.023662 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
10975 22:11:39.033085 /lava-11440308/1/../bin/lava-test-case
10976 22:11:39.039973 <8>[ 18.965283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
10977 22:11:39.040722 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
10979 22:11:39.048429 /lava-11440308/1/../bin/lava-test-case
10980 22:11:39.054938 <8>[ 18.980565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
10981 22:11:39.055684 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
10983 22:11:39.067182 /lava-11440308/1/../bin/lava-test-case
10984 22:11:39.073989 <8>[ 18.998872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
10985 22:11:39.074738 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
10987 22:11:39.082158 /lava-11440308/1/../bin/lava-test-case
10988 22:11:39.088568 <8>[ 19.013690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
10989 22:11:39.089348 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
10991 22:11:40.101206 /lava-11440308/1/../bin/lava-test-case
10992 22:11:40.107455 <8>[ 20.032273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
10993 22:11:40.107733 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
10995 22:11:40.116769 /lava-11440308/1/../bin/lava-test-case
10996 22:11:40.127272 <8>[ 20.051923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
10997 22:11:40.128015 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
10999 22:11:41.139075 /lava-11440308/1/../bin/lava-test-case
11000 22:11:41.145432 <8>[ 21.070000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11001 22:11:41.146181 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11003 22:11:41.154260 /lava-11440308/1/../bin/lava-test-case
11004 22:11:41.164283 <8>[ 21.088731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11005 22:11:41.165029 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11007 22:11:42.175871 /lava-11440308/1/../bin/lava-test-case
11008 22:11:42.182460 <8>[ 22.107320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11009 22:11:42.183165 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11011 22:11:42.193257 /lava-11440308/1/../bin/lava-test-case
11012 22:11:42.199570 <8>[ 22.125042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11013 22:11:42.200287 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11015 22:11:43.216934 /lava-11440308/1/../bin/lava-test-case
11016 22:11:43.223595 <8>[ 23.149532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11017 22:11:43.224338 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11019 22:11:43.231626 /lava-11440308/1/../bin/lava-test-case
11020 22:11:43.237937 <8>[ 23.164385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11021 22:11:43.238680 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11023 22:11:44.250922 /lava-11440308/1/../bin/lava-test-case
11024 22:11:44.258060 <8>[ 24.184314] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11025 22:11:44.258843 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11027 22:11:44.268076 /lava-11440308/1/../bin/lava-test-case
11028 22:11:44.274932 <8>[ 24.200752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11029 22:11:44.275612 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11031 22:11:45.292352 /lava-11440308/1/../bin/lava-test-case
11032 22:11:45.298334 <8>[ 25.225549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11033 22:11:45.298977 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11035 22:11:45.308528 /lava-11440308/1/../bin/lava-test-case
11036 22:11:45.315398 <8>[ 25.240838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11037 22:11:45.316452 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11039 22:11:46.327750 /lava-11440308/1/../bin/lava-test-case
11040 22:11:46.334369 <8>[ 26.259983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11041 22:11:46.335125 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11043 22:11:46.342260 /lava-11440308/1/../bin/lava-test-case
11044 22:11:46.352755 <8>[ 26.278147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11045 22:11:46.353497 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11047 22:11:46.361500 /lava-11440308/1/../bin/lava-test-case
11048 22:11:46.368613 <8>[ 26.294592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11049 22:11:46.369456 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11051 22:11:47.381147 /lava-11440308/1/../bin/lava-test-case
11052 22:11:47.387484 <8>[ 27.313380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11053 22:11:47.388237 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11055 22:11:47.396437 /lava-11440308/1/../bin/lava-test-case
11056 22:11:47.406201 <8>[ 27.331155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11057 22:11:47.406939 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11059 22:11:47.422234 /lava-11440308/1/../bin/lava-tes<8>[ 27.347179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11060 22:11:47.422716 t-case
11061 22:11:47.423257 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11063 22:11:47.429562 /lava-11440308/1/../bin/lava-test-case
11064 22:11:47.436067 <8>[ 27.362849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11065 22:11:47.436846 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11067 22:11:47.447687 /lava-11440308/1/../bin/lava-test-case
11068 22:11:47.454223 <8>[ 27.380639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11069 22:11:47.455000 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11071 22:11:47.464903 /lava-11440308/1/../bin/lava-test-case
11072 22:11:47.473998 <8>[ 27.398855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11073 22:11:47.474877 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11075 22:11:47.483688 /lava-11440308/1/../bin/lava-test-case
11076 22:11:47.489731 <8>[ 27.416046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11077 22:11:47.490481 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11079 22:11:47.499183 /lava-11440308/1/../bin/lava-test-case
11080 22:11:47.505340 <8>[ 27.431853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11081 22:11:47.505934 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11083 22:11:47.516493 /lava-11440308/1/../bin/lava-test-case
11084 22:11:47.527027 <8>[ 27.452508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11085 22:11:47.527790 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11087 22:11:47.537804 /lava-11440308/1/../bin/lava-test-case
11088 22:11:47.544459 <8>[ 27.471769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11089 22:11:47.545232 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11091 22:11:47.554879 /lava-11440308/1/../bin/lava-test-case
11092 22:11:47.561383 <8>[ 27.487381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11093 22:11:47.562134 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11095 22:11:47.572673 /lava-11440308/1/../bin/lava-test-case
11096 22:11:47.579278 <8>[ 27.505193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11097 22:11:47.579919 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11099 22:11:47.595284 /lava-11440308/1/../bin/lava-tes<8>[ 27.520280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11100 22:11:47.595779 t-case
11101 22:11:47.596599 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11103 22:11:47.607418 /lava-11440308/1/../bin/lava-test-case
11104 22:11:47.613900 <8>[ 27.538964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11105 22:11:47.614645 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11107 22:11:47.622320 /lava-11440308/1/../bin/lava-test-case
11108 22:11:47.629375 <8>[ 27.555637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11109 22:11:47.630126 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11111 22:11:47.640601 /lava-11440308/1/../bin/lava-test-case
11112 22:11:47.647306 <8>[ 27.573563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11113 22:11:47.648066 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11115 22:11:47.656247 /lava-11440308/1/../bin/lava-test-case
11116 22:11:47.662468 <8>[ 27.588222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11117 22:11:47.663220 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11119 22:11:47.675294 /lava-11440308/1/../bin/lava-test-case
11120 22:11:47.682190 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11122 22:11:47.685254 <8>[ 27.609541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11123 22:11:47.692110 /lava-11440308/1/../bin/lava-test-case
11124 22:11:47.699080 <8>[ 27.625541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11125 22:11:47.699839 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11127 22:11:47.711177 /lava-11440308/1/../bin/lava-test-case
11128 22:11:47.717223 <8>[ 27.643156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11129 22:11:47.718020 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11131 22:11:47.725294 /lava-11440308/1/../bin/lava-test-case
11132 22:11:47.731228 <8>[ 27.658141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11133 22:11:47.731865 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11135 22:11:48.746927 /lava-11440308/1/../bin/lava-test-case
11136 22:11:48.757050 <8>[ 28.682425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11137 22:11:48.757844 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11139 22:11:49.769030 /lava-11440308/1/../bin/lava-test-case
11140 22:11:49.775141 <8>[ 29.700950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11141 22:11:49.775898 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11143 22:11:49.784586 /lava-11440308/1/../bin/lava-test-case
11144 22:11:49.790979 <8>[ 29.717958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11145 22:11:49.791738 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11147 22:11:49.801895 /lava-11440308/1/../bin/lava-test-case
11148 22:11:49.808731 <8>[ 29.735046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11149 22:11:49.809841 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11151 22:11:49.817039 /lava-11440308/1/../bin/lava-test-case
11152 22:11:49.823300 <8>[ 29.749048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11153 22:11:49.824060 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11155 22:11:49.832874 /lava-11440308/1/../bin/lava-test-case
11156 22:11:49.839663 <8>[ 29.767348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11157 22:11:49.840415 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11159 22:11:49.849621 /lava-11440308/1/../bin/lava-test-case
11160 22:11:49.856114 <8>[ 29.782143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11161 22:11:49.856873 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11163 22:11:49.865656 /lava-11440308/1/../bin/lava-test-case
11164 22:11:49.872579 <8>[ 29.798608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11165 22:11:49.873425 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11167 22:11:49.880501 /lava-11440308/1/../bin/lava-test-case
11168 22:11:49.887507 <8>[ 29.813384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11169 22:11:49.888262 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11171 22:11:49.900311 /lava-11440308/1/../bin/lava-test-case
11172 22:11:49.906685 <8>[ 29.832135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11173 22:11:49.907429 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11175 22:11:49.915318 /lava-11440308/1/../bin/lava-test-case
11176 22:11:49.921942 <8>[ 29.848069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11177 22:11:49.922661 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11179 22:11:49.932112 /lava-11440308/1/../bin/lava-test-case
11180 22:11:49.942371 <8>[ 29.868178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11181 22:11:49.943125 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11183 22:11:49.949189 /lava-11440308/1/../bin/lava-test-case
11184 22:11:49.955838 <8>[ 29.882831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11185 22:11:49.956601 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11187 22:11:49.966789 /lava-11440308/1/../bin/lava-test-case
11188 22:11:49.973689 <8>[ 29.900005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11189 22:11:49.974435 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11191 22:11:49.981770 /lava-11440308/1/../bin/lava-test-case
11192 22:11:49.988533 <8>[ 29.914247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11193 22:11:49.989256 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11195 22:11:49.998139 /lava-11440308/1/../bin/lava-test-case
11196 22:11:50.004508 <8>[ 29.931623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11197 22:11:50.005283 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11199 22:11:50.020096 /lava-11440308/1/../bin/lava-tes<8>[ 29.945424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11200 22:11:50.020611 t-case
11201 22:11:50.021237 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11203 22:11:50.035165 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11205 22:11:50.037850 /lava-11440308/1/../bin/lava-tes<8>[ 29.963183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11206 22:11:50.038236 t-case
11207 22:11:50.053130 /lava-11440308/1/../bin/lava-tes<8>[ 29.978246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11208 22:11:50.053688 t-case
11209 22:11:50.054324 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11211 22:11:50.063616 /lava-11440308/1/../bin/lava-test-case
11212 22:11:50.071029 <8>[ 29.996622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11213 22:11:50.071835 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11215 22:11:50.078566 /lava-11440308/1/../bin/lava-test-case
11216 22:11:50.088478 <8>[ 30.012930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11217 22:11:50.089253 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11219 22:11:50.100094 /lava-11440308/1/../bin/lava-test-case
11220 22:11:50.106518 <8>[ 30.033189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11221 22:11:50.107431 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11223 22:11:51.117147 /lava-11440308/1/../bin/lava-test-case
11224 22:11:51.126865 <8>[ 31.051589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11225 22:11:51.127594 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11227 22:11:52.135880 /lava-11440308/1/../bin/lava-test-case
11228 22:11:52.142694 <8>[ 32.068913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11229 22:11:52.143418 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11230 22:11:52.143780 Bad test result: blocked
11231 22:11:52.152357 /lava-11440308/1/../bin/lava-test-case
11232 22:11:52.158685 <8>[ 32.085938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11233 22:11:52.159446 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11235 22:11:53.172098 /lava-11440308/1/../bin/lava-test-case
11236 22:11:53.178641 <8>[ 33.104617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11237 22:11:53.179403 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11239 22:11:53.187715 /lava-11440308/1/../bin/lava-test-case
11240 22:11:53.197999 <8>[ 33.124389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11241 22:11:53.198767 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11243 22:11:53.207674 /lava-11440308/1/../bin/lava-test-case
11244 22:11:53.214212 <8>[ 33.141336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11245 22:11:53.214973 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11247 22:11:53.223651 /lava-11440308/1/../bin/lava-test-case
11248 22:11:53.229814 <8>[ 33.157553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11249 22:11:53.230516 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11251 22:11:53.238308 /lava-11440308/1/../bin/lava-test-case
11252 22:11:53.245047 <8>[ 33.171363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11253 22:11:53.245854 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11255 22:11:53.260206 /lava-11440308/1/../bin/lava-test-case
11256 22:11:53.265887 <8>[ 33.193010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11257 22:11:53.266622 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11259 22:11:53.275473 /lava-11440308/1/../bin/lava-test-case
11260 22:11:53.282195 <8>[ 33.208677] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11261 22:11:53.282925 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11263 22:11:54.294328 /lava-11440308/1/../bin/lava-test-case
11264 22:11:54.301141 <8>[ 34.227287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11265 22:11:54.301946 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11267 22:11:54.310466 /lava-11440308/1/../bin/lava-test-case
11268 22:11:54.320078 <8>[ 34.246079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11269 22:11:54.320844 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11271 22:11:55.331126 /lava-11440308/1/../bin/lava-test-case
11272 22:11:55.337938 <8>[ 35.264268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11273 22:11:55.338704 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11275 22:11:55.347299 /lava-11440308/1/../bin/lava-test-case
11276 22:11:55.357420 <8>[ 35.283865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11277 22:11:55.358182 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11279 22:11:56.368857 /lava-11440308/1/../bin/lava-test-case
11280 22:11:56.374846 <8>[ 36.301854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11281 22:11:56.375499 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11283 22:11:56.384069 /lava-11440308/1/../bin/lava-test-case
11284 22:11:56.393882 <8>[ 36.320364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11285 22:11:56.394595 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11287 22:11:57.406868 /lava-11440308/1/../bin/lava-test-case
11288 22:11:57.413173 <8>[ 37.339986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11289 22:11:57.413967 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11291 22:11:57.421513 /lava-11440308/1/../bin/lava-test-case
11292 22:11:57.431151 <8>[ 37.358037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11293 22:11:57.431914 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11295 22:11:57.440386 /lava-11440308/1/../bin/lava-test-case
11296 22:11:57.447143 <8>[ 37.374871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11297 22:11:57.447942 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11299 22:11:57.456575 /lava-11440308/1/../bin/lava-test-case
11300 22:11:57.463530 <8>[ 37.390789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11301 22:11:57.464292 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11303 22:11:57.471134 /lava-11440308/1/../bin/lava-test-case
11304 22:11:57.477690 <8>[ 37.404557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11305 22:11:57.478454 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11307 22:11:57.492475 /lava-11440308/1/../bin/lava-tes<8>[ 37.422153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11308 22:11:57.493226 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11310 22:11:57.495793 t-case
11311 22:11:57.512061 /lava-11440308/1/../bin/lava-tes<8>[ 37.438014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11312 22:11:57.512562 t-case
11313 22:11:57.513191 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11315 22:11:57.520876 /lava-11440308/1/../bin/lava-test-case
11316 22:11:57.528068 <8>[ 37.454619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11317 22:11:57.528835 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11319 22:11:57.537149 /lava-11440308/1/../bin/lava-test-case
11320 22:11:57.543839 <8>[ 37.470700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11321 22:11:57.544601 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11323 22:11:57.554004 /lava-11440308/1/../bin/lava-test-case
11324 22:11:57.560588 <8>[ 37.487369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11325 22:11:57.561386 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11327 22:11:57.564032 + set +x
11328 22:11:57.567356 Received signal: <ENDRUN> 1_bootrr 11440308_1.5.2.3.5
11329 22:11:57.567862 Ending use of test pattern.
11330 22:11:57.568215 Ending test lava.1_bootrr (11440308_1.5.2.3.5), duration 20.23
11332 22:11:57.570516 <8>[ 37.497458] <LAVA_SIGNAL_ENDRUN 1_bootrr 11440308_1.5.2.3.5>
11333 22:11:57.570904 <LAVA_TEST_RUNNER EXIT>
11334 22:11:57.571470 ok: lava_test_shell seems to have completed
11335 22:11:57.575719 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11336 22:11:57.576328 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11337 22:11:57.576668 end: 4 lava-test-retry (duration 00:00:21) [common]
11338 22:11:57.576986 start: 5 finalize (timeout 00:08:04) [common]
11339 22:11:57.577362 start: 5.1 power-off (timeout 00:00:30) [common]
11340 22:11:57.577925 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11341 22:11:57.663071 >> Command sent successfully.
11342 22:11:57.671205 Returned 0 in 0 seconds
11343 22:11:57.772311 end: 5.1 power-off (duration 00:00:00) [common]
11345 22:11:57.773639 start: 5.2 read-feedback (timeout 00:08:04) [common]
11346 22:11:57.774486 Listened to connection for namespace 'common' for up to 1s
11347 22:11:57.775147 Listened to connection for namespace 'common' for up to 1s
11348 22:11:58.775356 Finalising connection for namespace 'common'
11349 22:11:58.775927 Disconnecting from shell: Finalise
11350 22:11:58.776303 / #
11351 22:11:58.877260 end: 5.2 read-feedback (duration 00:00:01) [common]
11352 22:11:58.877950 end: 5 finalize (duration 00:00:01) [common]
11353 22:11:58.878459 Cleaning after the job
11354 22:11:58.878880 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/ramdisk
11355 22:11:58.883970 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/kernel
11356 22:11:58.891234 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/dtb
11357 22:11:58.891474 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440308/tftp-deploy-yi_q08mg/modules
11358 22:11:58.897624 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11440308
11359 22:11:58.926774 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11440308
11360 22:11:58.926961 Job finished correctly