[Enter `^Ec?' for help] F0: 102B 0000 F3: 1001 0000 [0200] F3: 1001 0000 F7: 102D 0000 F1: 0000 0000 V0: 0000 0000 [0001] 00: 0007 8000 01: 0000 0000 BP: 0C00 0209 [0000] G0: 1182 0000 EC: 0000 0021 [4000] S7: 0000 0000 [0000] CC: 0000 0000 [0001] T0: 0000 0040 [010F] Jump to BL coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal Backing address range [0x00000000:0x40000000) with new page table @0x0010f000 Backing address range [0x00000000:0x00200000) with new page table @0x00110000 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal Backing address range [0x00200000:0x00400000) with new page table @0x00111000 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal WDT: Last reset was cold boot SPI1(PAD0) initialized at 2873684 Hz SPI5(PAD0) initialized at 992727 Hz VBOOT: Loading verstage. SF: Detected 00 0000 with sector size 0x1000, total 0x800000 FMAP: Found "FLASH" version 1.1 at 0x20000. FMAP: base = 0x0 size = 0x800000 #areas = 25 FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception FMAP: area RW_NVRAM found @ 57b000 (8192 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x800000 Probing TPM: . done! TPM ready after 0 ms Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6 Initialized TPM device CR50 revision 0 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes) src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 07 00 00 08 00 00 00 in-data: aa e4 47 04 13 02 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 in-header: 03 95 00 00 08 00 00 00 in-data: 18 20 20 08 00 00 00 00 Phase 1 FMAP: area GBB found @ 3f5000 (12032 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7 Recovery requested (1009000e) TPM: Extending digest for VBOOT: boot mode into PCR 0 tlcl_extend: response is 0 TPM: Extending digest for VBOOT: GBB HWID into PCR 1 tlcl_extend: response is 0 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps BS: bootblock times (exec / console): total (unknown) / 148 ms coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception pmic_efuse_setting: Set efuses in 11 msecs pmwrap_interface_init: Select PMIF_VLD_RDY [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x15 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2 [RTC]rtc_osc_init,62: osc32con val = 0xde70 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a [RTC]rtc_get_frequency_meter,154: input=15, output=764 [RTC]rtc_get_frequency_meter,154: input=23, output=951 [RTC]rtc_get_frequency_meter,154: input=19, output=856 [RTC]rtc_get_frequency_meter,154: input=17, output=811 [RTC]rtc_get_frequency_meter,154: input=16, output=788 [RTC]rtc_get_frequency_meter,154: input=16, output=788 [RTC]rtc_get_frequency_meter,154: input=17, output=811 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81 ADC[4]: Raw value=669327 ID=5 ADC[3]: Raw value=212917 ID=1 RAM Code: 0x51 FMAP: area COREBOOT found @ 21000 (4014080 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x800000 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 07 00 00 08 00 00 00 in-data: aa e4 47 04 13 02 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 in-header: 03 95 00 00 08 00 00 00 in-data: 18 20 20 08 00 00 00 00 MRC: failed to locate region type 0. DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0) DRAM-K: Running full calibration DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2 header.status = 0x0 header.version = 0x6 (expected: 0x6) header.size = 0xd00 (expected: 0xd00) header.flags = 0x0 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6 dram_init: ddr_geometry: 0 [EMI] MDL number = 0 [EMI] Get MDL freq = 0 dram_init: ddr_type: 0 is_discrete_lpddr4: 1 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0 [Bian_co] ETT version 0.0.0.1 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6 dramc_set_vcore_voltage set vcore to 650000 Read voltage for 800, 4 Vio18 = 0 Vcore = 650000 Vdram = 0 Vddq = 0 Vmddr = 0 dram_init: config_dvfs: 1 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9 MEM_TYPE=3, freq_sel=18 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 1600 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 1 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 800 CA_MCKIO = 800 MCKIO_SEMI = 0 PLL_FREQ = 3068 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 1600,PCW = 0X7600 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 40 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 12 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6) [EMI DOE] emi_dcm 0 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (7~68) winsize 62 [CA 2] Center 35 (5~66) winsize 62 [CA 3] Center 35 (5~66) winsize 62 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (3~65) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 34 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 3 PI (21 cell) CA1 delay=37 (7~68),Diff = 3 PI (21 cell) CA2 delay=35 (5~66),Diff = 1 PI (7 cell) CA3 delay=35 (5~66),Diff = 1 PI (7 cell) CA4 delay=34 (4~65),Diff = 0 PI (0 cell) CA5 delay=34 (3~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 6 (0~37) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 35 (4~66) winsize 63 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 34 (3~65) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 32 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 3 PI (21 cell) CA1 delay=37 (7~68),Diff = 3 PI (21 cell) CA2 delay=35 (5~66),Diff = 1 PI (7 cell) CA3 delay=35 (5~65),Diff = 1 PI (7 cell) CA4 delay=34 (4~64),Diff = 0 PI (0 cell) CA5 delay=34 (3~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 6 (0~37) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 29 => 29 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0) 0 6 4 | B1->B0 | 2626 2525 | 0 0 | (1 1) (1 1) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 3a3a 3e3e | 0 0 | (0 0) (1 1) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 2) 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 2) best DQS0 dly(MCK, UI, PI) = (0, 10, 2) best DQS1 dly(MCK, UI, PI) = (0, 10, 2) best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2) best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 84, DQM1 = 74 DQ Delay: DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6) Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6) Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 0, minWin=27, winSum=445 TX Vref=24, minBit 0, minWin=27, winSum=445 TX Vref=26, minBit 4, minWin=27, winSum=450 TX Vref=28, minBit 0, minWin=28, winSum=457 TX Vref=30, minBit 0, minWin=28, winSum=456 TX Vref=32, minBit 5, minWin=27, winSum=450 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28 Final TX Range 1 Vref 28 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6) Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6) Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH0 RK0 DATLAT Default: 0xa 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -111 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Set Vref, RX VrefLevel [Byte0]: 73 [Byte1]: 73 Set Vref, RX VrefLevel [Byte0]: 74 [Byte1]: 74 Final RX Vref Byte 0 = 53 to rank0 Final RX Vref Byte 1 = 56 to rank0 Final RX Vref Byte 0 = 53 to rank1 Final RX Vref Byte 1 = 56 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 83, DQM1 = 73 DQ Delay: DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps CH0 RK0: MR19=606, MR18=3B3B CH0_RK0: MR19=0x606, MR18=0x3B3B, DQSOSC=394, MR23=63, INC=95, DEC=63 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 26 => 26 Write leveling (Byte 1): 26 => 26 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 3030 3232 | 0 0 | (0 1) (0 1) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 0) best DQS0 dly(MCK, UI, PI) = (0, 10, 0) best DQS1 dly(MCK, UI, PI) = (0, 10, 0) best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0) best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 86, DQM1 = 75 DQ Delay: DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 13, minWin=26, winSum=439 TX Vref=24, minBit 0, minWin=27, winSum=444 TX Vref=26, minBit 14, minWin=27, winSum=450 TX Vref=28, minBit 0, minWin=28, winSum=455 TX Vref=30, minBit 0, minWin=28, winSum=455 TX Vref=32, minBit 6, minWin=27, winSum=454 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28 Final TX Range 1 Vref 28 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH0 RK1 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -111 -> 252, step: 8 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232 iDelay=217, Bit 6, Center 96 (-23 ~ 216) 240 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 86, DQM1 = 74 DQ Delay: DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =80 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =80 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps CH0 RK1: MR19=606, MR18=4B4B CH0_RK1: MR19=0x606, MR18=0x4B4B, DQSOSC=391, MR23=63, INC=96, DEC=64 [RxdqsGatingPostProcess] freq 800 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 34 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (6~68),Diff = 4 PI (28 cell) CA1 delay=37 (6~68),Diff = 4 PI (28 cell) CA2 delay=34 (4~65),Diff = 1 PI (7 cell) CA3 delay=34 (4~65),Diff = 1 PI (7 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 34 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (6~68),Diff = 4 PI (28 cell) CA1 delay=37 (6~68),Diff = 4 PI (28 cell) CA2 delay=34 (4~65),Diff = 1 PI (7 cell) CA3 delay=34 (4~65),Diff = 1 PI (7 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 23 => 23 Write leveling (Byte 1): 25 => 25 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 3030 3f3f | 0 1 | (0 0) (0 0) 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 30) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 30) best DQS0 dly(MCK, UI, PI) = (0, 9, 30) best DQS1 dly(MCK, UI, PI) = (0, 9, 30) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 83, DQM1 = 75 DQ Delay: DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =85 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 3, minWin=27, winSum=447 TX Vref=24, minBit 3, minWin=27, winSum=450 TX Vref=26, minBit 3, minWin=27, winSum=452 TX Vref=28, minBit 0, minWin=28, winSum=453 TX Vref=30, minBit 0, minWin=28, winSum=461 TX Vref=32, minBit 9, minWin=27, winSum=455 [TxChooseVref] Worse bit 0, Min win 28, Win sum 461, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH1 RK0 DATLAT Default: 0xa 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -111 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Set Vref, RX VrefLevel [Byte0]: 73 [Byte1]: 73 Set Vref, RX VrefLevel [Byte0]: 74 [Byte1]: 74 Set Vref, RX VrefLevel [Byte0]: 75 [Byte1]: 75 Set Vref, RX VrefLevel [Byte0]: 76 [Byte1]: 76 Set Vref, RX VrefLevel [Byte0]: 77 [Byte1]: 77 Final RX Vref Byte 0 = 58 to rank0 Final RX Vref Byte 1 = 52 to rank0 Final RX Vref Byte 0 = 58 to rank1 Final RX Vref Byte 1 = 52 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 81, DQM1 = 75 DQ Delay: DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76 DQ4 =80, DQ5 =96, DQ6 =88, DQ7 =76 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84 [DQSOSCAuto] RK0, (LSB)MR18= 0x5656, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps CH1 RK0: MR19=606, MR18=5656 CH1_RK0: MR19=0x606, MR18=0x5656, DQSOSC=388, MR23=63, INC=98, DEC=65 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 25 => 25 Write leveling (Byte 1): 25 => 25 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0) 0 7 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 26) 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 0) best DQS0 dly(MCK, UI, PI) = (0, 9, 26) best DQS1 dly(MCK, UI, PI) = (0, 10, 0) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26) best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 85, DQM1 = 73 DQ Delay: DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 0, minWin=27, winSum=448 TX Vref=24, minBit 0, minWin=28, winSum=452 TX Vref=26, minBit 0, minWin=28, winSum=456 TX Vref=28, minBit 0, minWin=28, winSum=458 TX Vref=30, minBit 9, minWin=27, winSum=456 TX Vref=32, minBit 9, minWin=27, winSum=455 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28 Final TX Range 1 Vref 28 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH1 RK1 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -111 -> 252, step: 8 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 5, Center 100 (-15 ~ 216) 232 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 13, Center 88 (-23 ~ 200) 224 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 85, DQM1 = 75 DQ Delay: DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =80 DQ4 =84, DQ5 =100, DQ6 =92, DQ7 =84 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68 DQ12 =84, DQ13 =88, DQ14 =84, DQ15 =80 [DQSOSCAuto] RK1, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps CH1 RK1: MR19=606, MR18=3737 CH1_RK1: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63 [RxdqsGatingPostProcess] freq 800 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 1600 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [GetDramInforAfterCalByMRR] Vendor 6. [GetDramInforAfterCalByMRR] Revision 606. [GetDramInforAfterCalByMRR] Revision 2 0. MR0 0x3939 MR8 0x1111 RK0, DieNum 1, Density 16Gb, RKsize 16Gb. MR0 0x3939 MR8 0x1111 RK1, DieNum 1, Density 16Gb, RKsize 16Gb. [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0 [FAST_K] Save calibration result to emmc [FAST_K] Save calibration result to emmc dram_init: config_dvfs: 1 dramc_set_vcore_voltage set vcore to 662500 Read voltage for 1200, 2 Vio18 = 0 Vcore = 662500 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=15 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x4 RL = 0x4 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 0 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 2400 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 0 CA_CKDIV4_EN = 0 CA_PREDIV_EN = 0 PH8_DLY = 17 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 1200 CA_MCKIO = 1200 MCKIO_SEMI = 0 PLL_FREQ = 2366 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 2400,PCW = 0X5b00 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] DLL <<<<<<<< [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x4 RL = 0x4 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x4 RL = 0x4 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Duty_Offset_Calibration] B0:0 B1:2 CA:1 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5093%(X100), DQS PI = 12 [0] MIN Duty = 4938%(X100), DQS PI = 52 [0] AVG Duty = 5015%(X100) CH0 CLK Duty spec in!! Max-Min= 155% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5125%(X100), DQS PI = 32 [0] MIN Duty = 5031%(X100), DQS PI = 4 [0] AVG Duty = 5078%(X100) ==DQS 1 == Final DQS duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 54 [0] MIN Duty = 4906%(X100), DQS PI = 18 [0] AVG Duty = 4968%(X100) CH0 DQS 0 Duty spec in!! Max-Min= 94% CH0 DQS 1 Duty spec in!! Max-Min= 125% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 22 [0] MIN Duty = 4969%(X100), DQS PI = 40 [0] AVG Duty = 5062%(X100) ==DQM 1 == Final DQM duty delay cell = 4 [4] MAX Duty = 5156%(X100), DQS PI = 48 [4] MIN Duty = 5000%(X100), DQS PI = 16 [4] AVG Duty = 5078%(X100) CH0 DQM 0 Duty spec in!! Max-Min= 187% CH0 DQM 1 Duty spec in!! Max-Min= 156% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 16 [-4] MIN Duty = 4813%(X100), DQS PI = 8 [-4] AVG Duty = 4937%(X100) ==DQ 1 == Final DQ duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 6 [-4] MIN Duty = 4876%(X100), DQS PI = 62 [-4] AVG Duty = 4969%(X100) CH0 DQ 0 Duty spec in!! Max-Min= 249% CH0 DQ 1 Duty spec in!! Max-Min= 186% [DutyScan_Calibration_Flow] ====Done==== == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Duty_Offset_Calibration] B0:0 B1:5 CA:-5 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5094%(X100), DQS PI = 24 [0] MIN Duty = 4875%(X100), DQS PI = 46 [0] AVG Duty = 4984%(X100) CH1 CLK Duty spec in!! Max-Min= 219% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5125%(X100), DQS PI = 16 [0] MIN Duty = 4875%(X100), DQS PI = 40 [0] AVG Duty = 5000%(X100) ==DQS 1 == Final DQS duty delay cell = -4 [-4] MAX Duty = 5000%(X100), DQS PI = 18 [-4] MIN Duty = 4876%(X100), DQS PI = 60 [-4] AVG Duty = 4938%(X100) CH1 DQS 0 Duty spec in!! Max-Min= 250% CH1 DQS 1 Duty spec in!! Max-Min= 124% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 30 [-4] MIN Duty = 4844%(X100), DQS PI = 40 [-4] AVG Duty = 4953%(X100) ==DQM 1 == Final DQM duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 4 [-4] MIN Duty = 4875%(X100), DQS PI = 60 [-4] AVG Duty = 4968%(X100) CH1 DQM 0 Duty spec in!! Max-Min= 218% CH1 DQM 1 Duty spec in!! Max-Min= 187% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = 0 [0] MAX Duty = 5062%(X100), DQS PI = 0 [0] MIN Duty = 4938%(X100), DQS PI = 44 [0] AVG Duty = 5000%(X100) ==DQ 1 == Final DQ duty delay cell = 0 [0] MAX Duty = 5000%(X100), DQS PI = 6 [0] MIN Duty = 4875%(X100), DQS PI = 46 [0] AVG Duty = 4937%(X100) CH1 DQ 0 Duty spec in!! Max-Min= 124% CH1 DQ 1 Duty spec in!! Max-Min= 125% [DutyScan_Calibration_Flow] ====Done==== nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 6 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39 [CA 0] Center 39 (9~70) winsize 62 [CA 1] Center 39 (8~70) winsize 63 [CA 2] Center 36 (5~67) winsize 63 [CA 3] Center 35 (4~66) winsize 63 [CA 4] Center 34 (3~65) winsize 63 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 39 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=39 (9~70),Diff = 6 PI (28 cell) CA1 delay=39 (8~70),Diff = 6 PI (28 cell) CA2 delay=36 (5~67),Diff = 3 PI (14 cell) CA3 delay=35 (4~66),Diff = 2 PI (9 cell) CA4 delay=34 (3~65),Diff = 1 PI (4 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 7 (0~38) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37 [CA 0] Center 39 (9~70) winsize 62 [CA 1] Center 39 (8~70) winsize 63 [CA 2] Center 35 (5~66) winsize 62 [CA 3] Center 35 (4~66) winsize 63 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 34 (3~65) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=39 (9~70),Diff = 6 PI (28 cell) CA1 delay=39 (8~70),Diff = 6 PI (28 cell) CA2 delay=35 (5~66),Diff = 2 PI (9 cell) CA3 delay=35 (4~66),Diff = 2 PI (9 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 7 (0~39) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 29 => 29 Write leveling (Byte 1): 27 => 27 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11) 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 20 | B1->B0 | 2d2d 2b2b | 0 0 | (1 0) (0 1) 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0) 0 12 20 | B1->B0 | 3a3a 4040 | 0 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 15, 20) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 15, 20) best DQS0 dly(MCK, UI, PI) = (0, 15, 20) best DQS1 dly(MCK, UI, PI) = (0, 15, 20) best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20) best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 115, DQM1 = 106 DQ Delay: DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7) Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7) Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 10, minWin=25, winSum=417 TX Vref=24, minBit 1, minWin=25, winSum=422 TX Vref=26, minBit 8, minWin=25, winSum=431 TX Vref=28, minBit 8, minWin=26, winSum=435 TX Vref=30, minBit 10, minWin=26, winSum=441 TX Vref=32, minBit 10, minWin=26, winSum=433 [TxChooseVref] Worse bit 10, Min win 26, Win sum 441, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7) Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7) Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7) [DATLAT] Freq=1200, CH0 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0x0, sum = 1 12, 0x0, sum = 2 13, 0x0, sum = 3 14, 0x0, sum = 4 best_step = 12 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -21 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Final RX Vref Byte 0 = 52 to rank0 Final RX Vref Byte 1 = 48 to rank0 Final RX Vref Byte 0 = 52 to rank1 Final RX Vref Byte 1 = 48 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 114, DQM1 = 104 DQ Delay: DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =110 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114 [DQSOSCAuto] RK0, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps CH0 RK0: MR19=404, MR18=C0C CH0_RK0: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 28 => 28 Write leveling (Byte 1): 26 => 26 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11) 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 1) 0 11 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0) 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 2424 3333 | 0 1 | (0 0) (0 0) 0 12 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 15, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 15, 16) best DQS0 dly(MCK, UI, PI) = (0, 15, 16) best DQS1 dly(MCK, UI, PI) = (0, 15, 16) best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16) best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152 iDelay=200, Bit 8, Center 95 (32 ~ 159) 128 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 115, DQM1 = 106 DQ Delay: DQ0 =107, DQ1 =119, DQ2 =115, DQ3 =111 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123 DQ8 =95, DQ9 =91, DQ10 =107, DQ11 =99 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7) Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6) Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 8, minWin=25, winSum=418 TX Vref=24, minBit 8, minWin=25, winSum=427 TX Vref=26, minBit 10, minWin=25, winSum=430 TX Vref=28, minBit 8, minWin=26, winSum=431 TX Vref=30, minBit 8, minWin=26, winSum=435 TX Vref=32, minBit 8, minWin=25, winSum=436 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7) Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7) Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7) [DATLAT] Freq=1200, CH0 RK1 DATLAT Default: 0xc 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0x0, sum = 1 12, 0x0, sum = 2 13, 0x0, sum = 3 14, 0x0, sum = 4 best_step = 12 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -21 -> 252, step: 4 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124 iDelay=199, Bit 9, Center 88 (27 ~ 150) 124 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124 iDelay=199, Bit 12, Center 110 (47 ~ 174) 128 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132 iDelay=199, Bit 14, Center 116 (55 ~ 178) 124 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 115, DQM1 = 104 DQ Delay: DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124 DQ8 =92, DQ9 =88, DQ10 =108, DQ11 =96 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114 [DQSOSCAuto] RK1, (LSB)MR18= 0x1010, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps CH0 RK1: MR19=404, MR18=1010 CH0_RK1: MR19=0x404, MR18=0x1010, DQSOSC=403, MR23=63, INC=40, DEC=26 [RxdqsGatingPostProcess] freq 1200 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 32 (2~63) winsize 62 [CA 5] Center 32 (2~63) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 5 PI (24 cell) CA1 delay=37 (6~68),Diff = 5 PI (24 cell) CA2 delay=34 (4~65),Diff = 2 PI (9 cell) CA3 delay=33 (3~64),Diff = 1 PI (4 cell) CA4 delay=32 (2~63),Diff = 0 PI (0 cell) CA5 delay=32 (2~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (7~68) winsize 62 [CA 2] Center 34 (3~65) winsize 63 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 32 (2~63) winsize 62 [CA 5] Center 32 (1~63) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 39 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 5 PI (24 cell) CA1 delay=37 (7~68),Diff = 5 PI (24 cell) CA2 delay=34 (4~65),Diff = 2 PI (9 cell) CA3 delay=33 (3~64),Diff = 1 PI (4 cell) CA4 delay=32 (2~63),Diff = 0 PI (0 cell) CA5 delay=32 (2~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 6 (0~38) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 20 => 20 Write leveling (Byte 1): 22 => 22 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11) 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0) 0 11 16 | B1->B0 | 3333 2727 | 0 0 | (0 0) (0 1) 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0) 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 3232 4545 | 0 0 | (0 0) (0 0) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 15, 16) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 15, 18) best DQS0 dly(MCK, UI, PI) = (0, 15, 16) best DQS1 dly(MCK, UI, PI) = (0, 15, 18) best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16) best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 116, DQM1 = 108 DQ Delay: DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6) Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6) == TX Byte 1 == Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6) Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 3, minWin=25, winSum=413 TX Vref=24, minBit 1, minWin=25, winSum=415 TX Vref=26, minBit 11, minWin=25, winSum=424 TX Vref=28, minBit 7, minWin=26, winSum=431 TX Vref=30, minBit 9, minWin=25, winSum=429 TX Vref=32, minBit 2, minWin=26, winSum=427 [TxChooseVref] Worse bit 7, Min win 26, Win sum 431, Final Vref 28 Final TX Range 1 Vref 28 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6) Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6) == TX Byte 1 == Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6) Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6) [DATLAT] Freq=1200, CH1 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0x0, sum = 1 12, 0x0, sum = 2 13, 0x0, sum = 3 14, 0x0, sum = 4 best_step = 12 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -29 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Final RX Vref Byte 0 = 53 to rank0 Final RX Vref Byte 1 = 50 to rank0 Final RX Vref Byte 0 = 53 to rank1 Final RX Vref Byte 1 = 50 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 115, DQM1 = 106 DQ Delay: DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =96 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps CH1 RK0: MR19=404, MR18=1515 CH1_RK0: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 21 => 21 Write leveling (Byte 1): 21 => 21 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11) 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0) 0 11 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0) 0 11 16 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0) 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0) 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 15, 14) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 15, 16) best DQS0 dly(MCK, UI, PI) = (0, 15, 14) best DQS1 dly(MCK, UI, PI) = (0, 15, 16) best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14) best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 116, DQM1 = 106 DQ Delay: DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =103 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6) Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6) == TX Byte 1 == Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6) Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 0, minWin=26, winSum=424 TX Vref=24, minBit 9, minWin=25, winSum=425 TX Vref=26, minBit 8, minWin=26, winSum=430 TX Vref=28, minBit 9, minWin=26, winSum=432 TX Vref=30, minBit 9, minWin=26, winSum=432 TX Vref=32, minBit 3, minWin=26, winSum=431 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28 Final TX Range 1 Vref 28 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6) Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6) == TX Byte 1 == Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6) Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6) [DATLAT] Freq=1200, CH1 RK1 DATLAT Default: 0xc 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0x0, sum = 1 12, 0x0, sum = 2 13, 0x0, sum = 3 14, 0x0, sum = 4 best_step = 12 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -29 -> 252, step: 4 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140 iDelay=199, Bit 2, Center 106 (35 ~ 178) 144 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144 iDelay=199, Bit 13, Center 112 (43 ~ 182) 140 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 114, DQM1 = 104 DQ Delay: DQ0 =114, DQ1 =112, DQ2 =106, DQ3 =112 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114 DQ8 =88, DQ9 =94, DQ10 =106, DQ11 =98 DQ12 =114, DQ13 =112, DQ14 =112, DQ15 =110 [DQSOSCAuto] RK1, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps CH1 RK1: MR19=404, MR18=808 CH1_RK1: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26 [RxdqsGatingPostProcess] freq 1200 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 2400 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 650000 Read voltage for 600, 5 Vio18 = 0 Vcore = 650000 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=19 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 1200 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 1 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 600 CA_MCKIO = 600 MCKIO_SEMI = 0 PLL_FREQ = 2288 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 1200,PCW = 0X5800 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 16 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 35 (5~66) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (3~65) winsize 63 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 39 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 2 PI (19 cell) CA1 delay=35 (5~66),Diff = 2 PI (19 cell) CA2 delay=34 (4~65),Diff = 1 PI (9 cell) CA3 delay=34 (3~65),Diff = 1 PI (9 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 35 (5~66) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 2 PI (19 cell) CA1 delay=35 (5~66),Diff = 2 PI (19 cell) CA2 delay=34 (4~65),Diff = 1 PI (9 cell) CA3 delay=34 (4~65),Diff = 1 PI (9 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 30 => 30 Write leveling (Byte 1): 30 => 30 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5) 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 8 | B1->B0 | 3333 3131 | 1 1 | (1 0) (0 0) 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0) 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 8) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 10) best DQS0 dly(MCK, UI, PI) = (0, 9, 8) best DQS1 dly(MCK, UI, PI) = (0, 9, 10) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 38, DQM1 = 33 DQ Delay: DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH0 RK0 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0x0, sum = 1 8, 0x0, sum = 2 9, 0x0, sum = 3 10, 0x0, sum = 4 best_step = 8 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -195 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 48 Final RX Vref Byte 0 = 52 to rank0 Final RX Vref Byte 1 = 48 to rank0 Final RX Vref Byte 0 = 52 to rank1 Final RX Vref Byte 1 = 48 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 39, DQM1 = 30 DQ Delay: DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40 [DQSOSCAuto] RK0, (LSB)MR18= 0x5656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps CH0 RK0: MR19=808, MR18=5656 CH0_RK0: MR19=0x808, MR18=0x5656, DQSOSC=393, MR23=63, INC=169, DEC=113 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 30 => 30 Write leveling (Byte 1): 30 => 30 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5) 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0) 0 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0) 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0) 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 8) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 10) best DQS0 dly(MCK, UI, PI) = (0, 9, 8) best DQS1 dly(MCK, UI, PI) = (0, 9, 10) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 41, DQM1 = 33 DQ Delay: DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH0 RK1 DATLAT Default: 0x8 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0x0, sum = 1 8, 0x0, sum = 2 9, 0x0, sum = 3 10, 0x0, sum = 4 best_step = 8 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -195 -> 252, step: 8 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 41, DQM1 = 32 DQ Delay: DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =36 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d6d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps CH0 RK1: MR19=808, MR18=6D6D CH0_RK1: MR19=0x808, MR18=0x6D6D, DQSOSC=389, MR23=63, INC=173, DEC=115 [RxdqsGatingPostProcess] freq 600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 35 (5~66) winsize 62 [CA 2] Center 33 (3~64) winsize 62 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 33 (2~64) winsize 63 [CA 5] Center 33 (2~64) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 2 PI (19 cell) CA1 delay=35 (5~66),Diff = 2 PI (19 cell) CA2 delay=33 (3~64),Diff = 0 PI (0 cell) CA3 delay=33 (3~64),Diff = 0 PI (0 cell) CA4 delay=33 (2~64),Diff = 0 PI (0 cell) CA5 delay=33 (2~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 4 (0~35) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 34 (4~65) winsize 62 [CA 2] Center 33 (3~64) winsize 62 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 33 (2~64) winsize 63 [CA 5] Center 33 (2~64) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 39 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 2 PI (19 cell) CA1 delay=35 (5~65),Diff = 2 PI (19 cell) CA2 delay=33 (3~64),Diff = 0 PI (0 cell) CA3 delay=33 (3~64),Diff = 0 PI (0 cell) CA4 delay=33 (2~64),Diff = 0 PI (0 cell) CA5 delay=33 (2~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 4 (0~36) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 27 => 27 Write leveling (Byte 1): 29 => 29 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5) 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 1) 0 5 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 1) (0 0) 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 3b3b 4444 | 0 0 | (1 1) (0 0) 0 6 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 6) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 8) best DQS0 dly(MCK, UI, PI) = (0, 9, 6) best DQS1 dly(MCK, UI, PI) = (0, 9, 8) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 41, DQM1 = 34 DQ Delay: DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6) Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6) Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH1 RK0 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0x0, sum = 1 8, 0x0, sum = 2 9, 0x0, sum = 3 10, 0x0, sum = 4 best_step = 8 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -195 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 50 Final RX Vref Byte 0 = 53 to rank0 Final RX Vref Byte 1 = 50 to rank0 Final RX Vref Byte 0 = 53 to rank1 Final RX Vref Byte 1 = 50 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 37, DQM1 = 30 DQ Delay: DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f7f, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps CH1 RK0: MR19=808, MR18=7F7F CH1_RK0: MR19=0x808, MR18=0x7F7F, DQSOSC=386, MR23=63, INC=176, DEC=117 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 29 => 29 Write leveling (Byte 1): 27 => 27 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5) 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1) 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0) 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 2) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 6) best DQS0 dly(MCK, UI, PI) = (0, 9, 2) best DQS1 dly(MCK, UI, PI) = (0, 9, 6) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 41, DQM1 = 34 DQ Delay: DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6) Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH1 RK1 DATLAT Default: 0x8 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0x0, sum = 1 8, 0x0, sum = 2 9, 0x0, sum = 3 10, 0x0, sum = 4 best_step = 8 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -195 -> 252, step: 8 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 36, DQM1 = 29 DQ Delay: DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps CH1 RK1: MR19=808, MR18=6161 CH1_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114 [RxdqsGatingPostProcess] freq 600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 1200 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 662500 Read voltage for 933, 3 Vio18 = 0 Vcore = 662500 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=17 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x3 RL = 0x3 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 1866 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 1 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 933 CA_MCKIO = 933 MCKIO_SEMI = 0 PLL_FREQ = 3732 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 1866,PCW = 0X8f00 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x3 RL = 0x3 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x3 RL = 0x3 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 8 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39 [CA 0] Center 39 (8~70) winsize 63 [CA 1] Center 38 (8~69) winsize 62 [CA 2] Center 36 (6~67) winsize 62 [CA 3] Center 36 (5~67) winsize 63 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (4~65) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 39 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=39 (8~70),Diff = 5 PI (31 cell) CA1 delay=38 (8~69),Diff = 4 PI (24 cell) CA2 delay=36 (6~67),Diff = 2 PI (12 cell) CA3 delay=36 (5~67),Diff = 2 PI (12 cell) CA4 delay=34 (4~65),Diff = 0 PI (0 cell) CA5 delay=34 (4~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 7 (0~38) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 38 (8~69) winsize 62 [CA 1] Center 38 (7~69) winsize 63 [CA 2] Center 36 (5~67) winsize 63 [CA 3] Center 35 (5~66) winsize 62 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (4~65) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=38 (8~69),Diff = 4 PI (24 cell) CA1 delay=38 (8~69),Diff = 4 PI (24 cell) CA2 delay=36 (6~67),Diff = 2 PI (12 cell) CA3 delay=35 (5~66),Diff = 1 PI (6 cell) CA4 delay=34 (4~65),Diff = 0 PI (0 cell) CA5 delay=34 (4~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 7 (0~39) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 30 => 30 Write leveling (Byte 1): 29 => 29 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 20 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 1) 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 2828 2b2b | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 22) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 24) best DQS0 dly(MCK, UI, PI) = (0, 14, 22) best DQS1 dly(MCK, UI, PI) = (0, 14, 24) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 4, Center 95 (-8 ~ 199) 208 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 94, DQM1 = 85 DQ Delay: DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =91 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2) Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2) Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2) Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2) Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH0 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -69 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 48 Final RX Vref Byte 0 = 52 to rank0 Final RX Vref Byte 1 = 48 to rank0 Final RX Vref Byte 0 = 52 to rank1 Final RX Vref Byte 1 = 48 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 96, DQM1 = 86 DQ Delay: DQ0 =92, DQ1 =96, DQ2 =96, DQ3 =92 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =104 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =78 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps CH0 RK0: MR19=505, MR18=2323 CH0_RK0: MR19=0x505, MR18=0x2323, DQSOSC=410, MR23=63, INC=64, DEC=42 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 27 => 27 Write leveling (Byte 1): 25 => 25 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0) 0 10 20 | B1->B0 | 3131 3030 | 1 0 | (1 1) (0 0) 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 2c2c 3838 | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 22) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 22) best DQS0 dly(MCK, UI, PI) = (0, 14, 22) best DQS1 dly(MCK, UI, PI) = (0, 14, 22) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 96, DQM1 = 85 DQ Delay: DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =79 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =95 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2) Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2) Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2) Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2) Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH0 RK1 DATLAT Default: 0xb 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -77 -> 252, step: 4 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180 iDelay=203, Bit 10, Center 90 (-1 ~ 182) 184 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 97, DQM1 = 86 DQ Delay: DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =90 DQ4 =100, DQ5 =90, DQ6 =106, DQ7 =108 DQ8 =76, DQ9 =72, DQ10 =90, DQ11 =78 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps CH0 RK1: MR19=505, MR18=2A2A CH0_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43 [RxdqsGatingPostProcess] freq 933 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (2~64) winsize 63 [CA 5] Center 33 (2~64) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (6~68),Diff = 4 PI (24 cell) CA1 delay=37 (6~68),Diff = 4 PI (24 cell) CA2 delay=34 (4~65),Diff = 1 PI (6 cell) CA3 delay=34 (4~65),Diff = 1 PI (6 cell) CA4 delay=33 (2~64),Diff = 0 PI (0 cell) CA5 delay=33 (2~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (2~64) winsize 63 [CA 5] Center 32 (2~63) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 39 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (6~68),Diff = 5 PI (31 cell) CA1 delay=37 (6~68),Diff = 5 PI (31 cell) CA2 delay=34 (4~65),Diff = 2 PI (12 cell) CA3 delay=34 (4~65),Diff = 2 PI (12 cell) CA4 delay=33 (2~64),Diff = 1 PI (6 cell) CA5 delay=32 (2~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 5 (0~37) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 26 => 26 Write leveling (Byte 1): 26 => 26 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1) 0 10 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0) 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1) 0 11 20 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 20) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 20) best DQS0 dly(MCK, UI, PI) = (0, 14, 20) best DQS1 dly(MCK, UI, PI) = (0, 14, 20) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 95, DQM1 = 87 DQ Delay: DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2) Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2) Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2) Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2) Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH1 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -69 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 50 Final RX Vref Byte 0 = 53 to rank0 Final RX Vref Byte 1 = 50 to rank0 Final RX Vref Byte 0 = 53 to rank1 Final RX Vref Byte 1 = 50 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 94, DQM1 = 88 DQ Delay: DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =92 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98 [DQSOSCAuto] RK0, (LSB)MR18= 0x3333, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps CH1 RK0: MR19=505, MR18=3333 CH1_RK0: MR19=0x505, MR18=0x3333, DQSOSC=405, MR23=63, INC=66, DEC=44 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 25 => 25 Write leveling (Byte 1): 24 => 24 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1) 0 10 16 | B1->B0 | 3434 2525 | 1 1 | (1 0) (1 1) 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0) 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1) 0 11 20 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 14) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 16) best DQS0 dly(MCK, UI, PI) = (0, 14, 14) best DQS1 dly(MCK, UI, PI) = (0, 14, 16) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 95, DQM1 = 87 DQ Delay: DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79 DQ12 =99, DQ13 =99, DQ14 =91, DQ15 =95 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2) Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2) Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2) Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2) Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH1 RK1 DATLAT Default: 0xb 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -69 -> 252, step: 4 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188 iDelay=203, Bit 10, Center 90 (-1 ~ 182) 184 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 95, DQM1 = 87 DQ Delay: DQ0 =96, DQ1 =92, DQ2 =88, DQ3 =92 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92 DQ8 =74, DQ9 =76, DQ10 =90, DQ11 =80 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps CH1 RK1: MR19=505, MR18=2525 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42 [RxdqsGatingPostProcess] freq 933 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 1866 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 650000 Read voltage for 400, 6 Vio18 = 0 Vcore = 650000 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=20 sv_algorithm_assistance_LP4_800 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 800 CKR = 1 DQ_P2S_RATIO = 4 =================================== CA_P2S_RATIO = 4 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 1 CA_SEMI_OPEN = 1 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 0 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 4 DQ_AAMCK_DIV = 0 CA_AAMCK_DIV = 0 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 800 CA_MCKIO = 400 MCKIO_SEMI = 400 PLL_FREQ = 3016 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 32 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 800,PCW = 0X7400 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 0 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 18 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 39 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == Write leveling (Byte 0): 32 => 0 Write leveling (Byte 1): 32 => 0 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 24) best DQS0 dly(MCK, UI, PI) = (0, 10, 16) best DQS1 dly(MCK, UI, PI) = (0, 10, 24) best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16) best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 43, DQS1 = 59 DQM Delay: DQM0 = 5, DQM1 = 12 DQ Delay: DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == TX Byte 1 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == TX Byte 1 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) [DATLAT] Freq=400, CH0 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -359 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 48 Final RX Vref Byte 0 = 52 to rank0 Final RX Vref Byte 1 = 48 to rank0 Final RX Vref Byte 0 = 52 to rank1 Final RX Vref Byte 1 = 48 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 52, DQS1 = 68 DQM Delay: DQM0 = 8, DQM1 = 17 DQ Delay: DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28 [DQSOSCAuto] RK0, (LSB)MR18= 0xb3b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps CH0 RK0: MR19=C0C, MR18=B3B3 CH0_RK0: MR19=0xC0C, MR18=0xB3B3, DQSOSC=387, MR23=63, INC=394, DEC=262 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 16) best DQS0 dly(MCK, UI, PI) = (0, 10, 16) best DQS1 dly(MCK, UI, PI) = (0, 10, 16) best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16) best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 51, DQS1 = 59 DQM Delay: DQM0 = 14, DQM1 = 16 DQ Delay: DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3) Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3) Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3) Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3) Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3) [DATLAT] Freq=400, CH0 RK1 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -359 -> 252, step: 8 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 52, DQS1 = 68 DQM Delay: DQM0 = 11, DQM1 = 17 DQ Delay: DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24 [DQSOSCAuto] RK1, (LSB)MR18= 0xc2c2, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps CH0 RK1: MR19=C0C, MR18=C2C2 CH0_RK1: MR19=0xC0C, MR18=0xC2C2, DQSOSC=385, MR23=63, INC=398, DEC=265 [RxdqsGatingPostProcess] freq 400 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 39 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == Write leveling (Byte 0): 32 => 0 Write leveling (Byte 1): 32 => 0 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 16) best DQS0 dly(MCK, UI, PI) = (0, 10, 16) best DQS1 dly(MCK, UI, PI) = (0, 10, 16) best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16) best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 43, DQS1 = 59 DQM Delay: DQM0 = 6, DQM1 = 15 DQ Delay: DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == TX Byte 1 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == TX Byte 1 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) [DATLAT] Freq=400, CH1 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -359 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 50 Final RX Vref Byte 0 = 53 to rank0 Final RX Vref Byte 1 = 50 to rank0 Final RX Vref Byte 0 = 53 to rank1 Final RX Vref Byte 1 = 50 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 48, DQS1 = 64 DQM Delay: DQM0 = 8, DQM1 = 16 DQ Delay: DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24 [DQSOSCAuto] RK0, (LSB)MR18= 0xe4e4, (MSB)MR19= 0xc0c, tDQSOscB0 = 381 ps tDQSOscB1 = 381 ps CH1 RK0: MR19=C0C, MR18=E4E4 CH1_RK0: MR19=0xC0C, MR18=0xE4E4, DQSOSC=381, MR23=63, INC=406, DEC=271 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 16) best DQS0 dly(MCK, UI, PI) = (0, 10, 16) best DQS1 dly(MCK, UI, PI) = (0, 10, 16) best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16) best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 43, DQS1 = 59 DQM Delay: DQM0 = 10, DQM1 = 17 DQ Delay: DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3) Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3) Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3) Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3) Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3) [DATLAT] Freq=400, CH1 RK1 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -359 -> 252, step: 8 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 48, DQS1 = 64 DQM Delay: DQM0 = 10, DQM1 = 15 DQ Delay: DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4 DQ4 =12, DQ5 =24, DQ6 =16, DQ7 =8 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24 [DQSOSCAuto] RK1, (LSB)MR18= 0xadad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps CH1 RK1: MR19=C0C, MR18=ADAD CH1_RK1: MR19=0xC0C, MR18=0xADAD, DQSOSC=388, MR23=63, INC=392, DEC=261 [RxdqsGatingPostProcess] freq 400 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 800 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : NO K RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : NO K RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 725000 Read voltage for 1600, 0 Vio18 = 0 Vcore = 725000 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=13 sv_algorithm_assistance_LP4_3733 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x1 WL = 0x5 RL = 0x5 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x1 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 0 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 0 NEW_8X_MODE = 1 =================================== =================================== data_rate = 3200 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 0 CA_CKDIV4_EN = 0 CA_PREDIV_EN = 0 PH8_DLY = 12 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 1600 CA_MCKIO = 1600 MCKIO_SEMI = 0 PLL_FREQ = 3068 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 3200,PCW = 0X7600 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] DLL <<<<<<<< [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x1 WL = 0x5 RL = 0x5 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x1 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x1 WL = 0x5 RL = 0x5 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x1 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Duty_Offset_Calibration] B0:0 B1:2 CA:1 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 22 [0] MIN Duty = 4938%(X100), DQS PI = 52 [0] AVG Duty = 5047%(X100) CH0 CLK Duty spec in!! Max-Min= 218% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 34 [0] MIN Duty = 5000%(X100), DQS PI = 10 [0] AVG Duty = 5078%(X100) ==DQS 1 == Final DQS duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 4 [0] MIN Duty = 4907%(X100), DQS PI = 12 [0] AVG Duty = 4969%(X100) CH0 DQS 0 Duty spec in!! Max-Min= 156% CH0 DQS 1 Duty spec in!! Max-Min= 124% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = 0 [0] MAX Duty = 5187%(X100), DQS PI = 22 [0] MIN Duty = 4907%(X100), DQS PI = 42 [0] AVG Duty = 5047%(X100) ==DQM 1 == Final DQM duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 52 [0] MIN Duty = 4782%(X100), DQS PI = 14 [0] AVG Duty = 4906%(X100) CH0 DQM 0 Duty spec in!! Max-Min= 280% CH0 DQM 1 Duty spec in!! Max-Min= 249% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = 0 [0] MAX Duty = 5218%(X100), DQS PI = 18 [0] MIN Duty = 4938%(X100), DQS PI = 56 [0] AVG Duty = 5078%(X100) ==DQ 1 == Final DQ duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 4 [-4] MIN Duty = 4844%(X100), DQS PI = 34 [-4] AVG Duty = 4953%(X100) CH0 DQ 0 Duty spec in!! Max-Min= 280% CH0 DQ 1 Duty spec in!! Max-Min= 218% [DutyScan_Calibration_Flow] ====Done==== == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Duty_Offset_Calibration] B0:0 B1:4 CA:-5 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 20 [0] MIN Duty = 4875%(X100), DQS PI = 50 [0] AVG Duty = 5015%(X100) CH1 CLK Duty spec in!! Max-Min= 281% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 18 [0] MIN Duty = 4844%(X100), DQS PI = 44 [0] AVG Duty = 5000%(X100) ==DQS 1 == Final DQS duty delay cell = -4 [-4] MAX Duty = 5000%(X100), DQS PI = 18 [-4] MIN Duty = 4844%(X100), DQS PI = 40 [-4] AVG Duty = 4922%(X100) CH1 DQS 0 Duty spec in!! Max-Min= 312% CH1 DQS 1 Duty spec in!! Max-Min= 156% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 34 [-4] MIN Duty = 4751%(X100), DQS PI = 46 [-4] AVG Duty = 4906%(X100) ==DQM 1 == Final DQM duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 12 [-4] MIN Duty = 4907%(X100), DQS PI = 36 [-4] AVG Duty = 4984%(X100) CH1 DQM 0 Duty spec in!! Max-Min= 311% CH1 DQM 1 Duty spec in!! Max-Min= 155% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = 0 [0] MAX Duty = 5093%(X100), DQS PI = 20 [0] MIN Duty = 4938%(X100), DQS PI = 48 [0] AVG Duty = 5015%(X100) ==DQ 1 == Final DQ duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 4 [0] MIN Duty = 4907%(X100), DQS PI = 14 [0] AVG Duty = 4969%(X100) CH1 DQ 0 Duty spec in!! Max-Min= 155% CH1 DQ 1 Duty spec in!! Max-Min= 124% [DutyScan_Calibration_Flow] ====Done==== nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 4 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2) [MiockJmeterHQA] [DramcMiockJmeter] u1RxGatingPI = 0 0 : 4363, 4137 4 : 4252, 4027 8 : 4363, 4137 12 : 4252, 4027 16 : 4252, 4027 20 : 4363, 4137 24 : 4253, 4027 28 : 4252, 4026 32 : 4252, 4027 36 : 4255, 4029 40 : 4363, 4137 44 : 4252, 4027 48 : 4363, 4138 52 : 4252, 4027 56 : 4252, 4027 60 : 4252, 4027 64 : 4363, 4139 68 : 4253, 4027 72 : 4361, 4138 76 : 4250, 4026 80 : 4249, 4027 84 : 4250, 4027 88 : 4252, 4029 92 : 4250, 4027 96 : 4250, 4026 100 : 4363, 2298 104 : 4360, 0 108 : 4252, 0 112 : 4363, 0 116 : 4361, 0 120 : 4363, 0 124 : 4253, 0 128 : 4360, 0 132 : 4250, 0 136 : 4250, 0 140 : 4250, 0 144 : 4250, 0 148 : 4252, 0 152 : 4360, 0 156 : 4250, 0 160 : 4250, 0 164 : 4250, 0 168 : 4361, 0 172 : 4361, 0 176 : 4250, 0 180 : 4250, 0 184 : 4250, 0 188 : 4252, 0 192 : 4249, 0 196 : 4250, 0 200 : 4252, 0 204 : 4250, 0 208 : 4250, 0 212 : 4253, 0 216 : 4250, 0 220 : 4361, 589 224 : 4253, 3997 228 : 4250, 4027 232 : 4252, 4029 236 : 4249, 4027 240 : 4250, 4027 244 : 4252, 4029 248 : 4249, 4027 252 : 4360, 4137 256 : 4363, 4140 260 : 4250, 4027 264 : 4363, 4140 268 : 4360, 4138 272 : 4250, 4027 276 : 4250, 4027 280 : 4252, 4030 284 : 4250, 4026 288 : 4250, 4027 292 : 4250, 4027 296 : 4252, 4029 300 : 4250, 4026 304 : 4360, 4137 308 : 4360, 4137 312 : 4249, 4027 316 : 4363, 4140 320 : 4360, 4137 324 : 4250, 4027 328 : 4250, 4026 332 : 4253, 4029 336 : 4250, 3961 340 : 4249, 1915 MIOCK jitter meter ch=0 1T = (340-104) = 236 dly cells Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 42 (12~73) winsize 62 [CA 1] Center 42 (12~73) winsize 62 [CA 2] Center 39 (9~69) winsize 61 [CA 3] Center 38 (9~68) winsize 60 [CA 4] Center 37 (7~67) winsize 61 [CA 5] Center 36 (6~66) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 275/100 ps CA0 delay=42 (12~73),Diff = 6 PI (21 cell) CA1 delay=42 (12~73),Diff = 6 PI (21 cell) CA2 delay=39 (9~69),Diff = 3 PI (10 cell) CA3 delay=38 (9~68),Diff = 2 PI (7 cell) CA4 delay=37 (7~67),Diff = 1 PI (3 cell) CA5 delay=36 (6~66),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 10 (0~41) [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 42 (12~73) winsize 62 [CA 1] Center 41 (11~72) winsize 62 [CA 2] Center 38 (8~68) winsize 61 [CA 3] Center 37 (7~67) winsize 61 [CA 4] Center 35 (5~65) winsize 61 [CA 5] Center 35 (5~66) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 275/100 ps CA0 delay=42 (12~73),Diff = 6 PI (21 cell) CA1 delay=42 (12~72),Diff = 6 PI (21 cell) CA2 delay=38 (9~68),Diff = 2 PI (7 cell) CA3 delay=38 (9~67),Diff = 2 PI (7 cell) CA4 delay=36 (7~65),Diff = 0 PI (0 cell) CA5 delay=36 (6~66),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 11 (0~43) [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 29 => 29 Write leveling (Byte 1): 24 => 24 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12) 0 12 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1) 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0) 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0) 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0) 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0) 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 14 0 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0) 0 14 4 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 1, 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 1, 4) best DQS0 dly(MCK, UI, PI) = (1, 1, 0) best DQS1 dly(MCK, UI, PI) = (1, 1, 4) best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0) best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 130, DQM1 = 124 DQ Delay: DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3) Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3) Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 10, minWin=22, winSum=373 TX Vref=18, minBit 4, minWin=23, winSum=380 TX Vref=20, minBit 6, minWin=24, winSum=395 TX Vref=22, minBit 4, minWin=24, winSum=401 TX Vref=24, minBit 8, minWin=24, winSum=409 TX Vref=26, minBit 7, minWin=25, winSum=415 TX Vref=28, minBit 1, minWin=25, winSum=416 TX Vref=30, minBit 0, minWin=25, winSum=411 TX Vref=32, minBit 6, minWin=24, winSum=399 TX Vref=34, minBit 3, minWin=24, winSum=396 TX Vref=36, minBit 3, minWin=23, winSum=384 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 28 Final TX Range 0 Vref 28 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps == TX Byte 0 == u2DelayCellOfst[0]=10 cells (3 PI) u2DelayCellOfst[1]=17 cells (5 PI) u2DelayCellOfst[2]=14 cells (4 PI) u2DelayCellOfst[3]=10 cells (3 PI) u2DelayCellOfst[4]=7 cells (2 PI) u2DelayCellOfst[5]=0 cells (0 PI) u2DelayCellOfst[6]=17 cells (5 PI) u2DelayCellOfst[7]=17 cells (5 PI) Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3) Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=3 cells (1 PI) u2DelayCellOfst[9]=0 cells (0 PI) u2DelayCellOfst[10]=7 cells (2 PI) u2DelayCellOfst[11]=3 cells (1 PI) u2DelayCellOfst[12]=14 cells (4 PI) u2DelayCellOfst[13]=14 cells (4 PI) u2DelayCellOfst[14]=17 cells (5 PI) u2DelayCellOfst[15]=14 cells (4 PI) Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3) Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH0 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x8BFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 24 -> 127 RX Vref 24 -> 127, step: 1 RX Delay 11 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 24 [Byte1]: 24 Set Vref, RX VrefLevel [Byte0]: 25 [Byte1]: 25 Set Vref, RX VrefLevel [Byte0]: 26 [Byte1]: 26 Set Vref, RX VrefLevel [Byte0]: 27 [Byte1]: 27 Set Vref, RX VrefLevel [Byte0]: 28 [Byte1]: 28 Set Vref, RX VrefLevel [Byte0]: 29 [Byte1]: 29 Set Vref, RX VrefLevel [Byte0]: 30 [Byte1]: 30 Set Vref, RX VrefLevel [Byte0]: 31 [Byte1]: 31 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Final RX Vref Byte 0 = 52 to rank0 Final RX Vref Byte 1 = 54 to rank0 Final RX Vref Byte 0 = 52 to rank1 Final RX Vref Byte 1 = 54 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 126, DQM1 = 120 DQ Delay: DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x4141, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps CH0 RK0: MR19=303, MR18=1E1E CH0_RK0: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 30 => 30 Write leveling (Byte 1): 25 => 25 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12) 0 12 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1) 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0) 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0) 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 1) 0 13 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0) 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0) 0 14 0 | B1->B0 | 2323 4444 | 0 1 | (0 0) (0 0) 0 14 4 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 0, 30) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 1, 2) best DQS0 dly(MCK, UI, PI) = (1, 0, 30) best DQS1 dly(MCK, UI, PI) = (1, 1, 2) best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30) best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120 iDelay=200, Bit 4, Center 135 (72 ~ 199) 128 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 130, DQM1 = 123 DQ Delay: DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3) Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3) Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 8, minWin=22, winSum=374 TX Vref=18, minBit 0, minWin=23, winSum=382 TX Vref=20, minBit 1, minWin=23, winSum=391 TX Vref=22, minBit 1, minWin=24, winSum=397 TX Vref=24, minBit 1, minWin=24, winSum=404 TX Vref=26, minBit 13, minWin=24, winSum=411 TX Vref=28, minBit 0, minWin=25, winSum=412 TX Vref=30, minBit 8, minWin=24, winSum=408 TX Vref=32, minBit 7, minWin=24, winSum=400 TX Vref=34, minBit 8, minWin=22, winSum=392 TX Vref=36, minBit 4, minWin=23, winSum=384 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 28 Final TX Range 0 Vref 28 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps == TX Byte 0 == u2DelayCellOfst[0]=14 cells (4 PI) u2DelayCellOfst[1]=21 cells (6 PI) u2DelayCellOfst[2]=14 cells (4 PI) u2DelayCellOfst[3]=14 cells (4 PI) u2DelayCellOfst[4]=7 cells (2 PI) u2DelayCellOfst[5]=0 cells (0 PI) u2DelayCellOfst[6]=17 cells (5 PI) u2DelayCellOfst[7]=17 cells (5 PI) Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3) Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=3 cells (1 PI) u2DelayCellOfst[9]=0 cells (0 PI) u2DelayCellOfst[10]=10 cells (3 PI) u2DelayCellOfst[11]=7 cells (2 PI) u2DelayCellOfst[12]=14 cells (4 PI) u2DelayCellOfst[13]=17 cells (5 PI) u2DelayCellOfst[14]=21 cells (6 PI) u2DelayCellOfst[15]=17 cells (5 PI) Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3) Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH0 RK1 DATLAT Default: 0xe 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x8FFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 11 -> 252, step: 4 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 128, DQM1 = 120 DQ Delay: DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =122 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x4141, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps CH0 RK1: MR19=303, MR18=2222 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16 [RxdqsGatingPostProcess] freq 1600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 41 (11~71) winsize 61 [CA 1] Center 40 (10~70) winsize 61 [CA 2] Center 36 (7~66) winsize 60 [CA 3] Center 35 (6~65) winsize 60 [CA 4] Center 33 (4~63) winsize 60 [CA 5] Center 33 (4~63) winsize 60 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 275/100 ps CA0 delay=41 (11~71),Diff = 8 PI (28 cell) CA1 delay=40 (10~70),Diff = 7 PI (24 cell) CA2 delay=36 (7~66),Diff = 3 PI (10 cell) CA3 delay=35 (6~65),Diff = 2 PI (7 cell) CA4 delay=33 (4~63),Diff = 0 PI (0 cell) CA5 delay=33 (4~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 8 (0~39) [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 40 (10~70) winsize 61 [CA 1] Center 39 (9~70) winsize 62 [CA 2] Center 35 (6~65) winsize 60 [CA 3] Center 35 (6~65) winsize 60 [CA 4] Center 33 (4~63) winsize 60 [CA 5] Center 33 (3~63) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 275/100 ps CA0 delay=40 (11~70),Diff = 7 PI (24 cell) CA1 delay=40 (10~70),Diff = 7 PI (24 cell) CA2 delay=36 (7~65),Diff = 3 PI (10 cell) CA3 delay=35 (6~65),Diff = 2 PI (7 cell) CA4 delay=33 (4~63),Diff = 0 PI (0 cell) CA5 delay=33 (4~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 9 (0~41) [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 21 => 21 Write leveling (Byte 1): 21 => 21 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12) 0 12 0 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1) 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0) 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0) 0 13 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0) 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0) 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 28 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0) 0 14 0 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 0, 26) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 1, 2) best DQS0 dly(MCK, UI, PI) = (1, 0, 26) best DQS1 dly(MCK, UI, PI) = (1, 1, 2) best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26) best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 130, DQM1 = 125 DQ Delay: DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =119 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3) Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3) Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 3, minWin=21, winSum=370 TX Vref=18, minBit 1, minWin=22, winSum=377 TX Vref=20, minBit 1, minWin=23, winSum=391 TX Vref=22, minBit 3, minWin=22, winSum=394 TX Vref=24, minBit 1, minWin=24, winSum=405 TX Vref=26, minBit 3, minWin=24, winSum=413 TX Vref=28, minBit 1, minWin=24, winSum=415 TX Vref=30, minBit 3, minWin=24, winSum=403 TX Vref=32, minBit 1, minWin=23, winSum=395 TX Vref=34, minBit 3, minWin=23, winSum=393 [TxChooseVref] Worse bit 1, Min win 24, Win sum 415, Final Vref 28 Final TX Range 0 Vref 28 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps == TX Byte 0 == u2DelayCellOfst[0]=17 cells (5 PI) u2DelayCellOfst[1]=14 cells (4 PI) u2DelayCellOfst[2]=0 cells (0 PI) u2DelayCellOfst[3]=7 cells (2 PI) u2DelayCellOfst[4]=10 cells (3 PI) u2DelayCellOfst[5]=17 cells (5 PI) u2DelayCellOfst[6]=17 cells (5 PI) u2DelayCellOfst[7]=7 cells (2 PI) Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3) Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=0 cells (0 PI) u2DelayCellOfst[9]=3 cells (1 PI) u2DelayCellOfst[10]=10 cells (3 PI) u2DelayCellOfst[11]=3 cells (1 PI) u2DelayCellOfst[12]=17 cells (5 PI) u2DelayCellOfst[13]=17 cells (5 PI) u2DelayCellOfst[14]=21 cells (6 PI) u2DelayCellOfst[15]=17 cells (5 PI) Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3) Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH1 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0xFFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 24 -> 127 RX Vref 24 -> 127, step: 1 RX Delay 3 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 24 [Byte1]: 24 Set Vref, RX VrefLevel [Byte0]: 25 [Byte1]: 25 Set Vref, RX VrefLevel [Byte0]: 26 [Byte1]: 26 Set Vref, RX VrefLevel [Byte0]: 27 [Byte1]: 27 Set Vref, RX VrefLevel [Byte0]: 28 [Byte1]: 28 Set Vref, RX VrefLevel [Byte0]: 29 [Byte1]: 29 Set Vref, RX VrefLevel [Byte0]: 30 [Byte1]: 30 Set Vref, RX VrefLevel [Byte0]: 31 [Byte1]: 31 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Set Vref, RX VrefLevel [Byte0]: 73 [Byte1]: 73 Set Vref, RX VrefLevel [Byte0]: 74 [Byte1]: 74 Set Vref, RX VrefLevel [Byte0]: 75 [Byte1]: 75 Final RX Vref Byte 0 = 60 to rank0 Final RX Vref Byte 1 = 55 to rank0 Final RX Vref Byte 0 = 60 to rank1 Final RX Vref Byte 1 = 55 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 128, DQM1 = 124 DQ Delay: DQ0 =134, DQ1 =124, DQ2 =116, DQ3 =126 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =124 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =114 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x5151, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps CH1 RK0: MR19=303, MR18=2828 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 22 => 22 Write leveling (Byte 1): 21 => 21 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12) 0 12 0 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1) 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1) 0 12 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0) 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0) 0 13 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0) 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 24 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0) 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0) 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 0, 26) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 1, 0) best DQS0 dly(MCK, UI, PI) = (1, 0, 26) best DQS1 dly(MCK, UI, PI) = (1, 1, 0) best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26) best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 131, DQM1 = 125 DQ Delay: DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3) Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3) Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 0, minWin=23, winSum=379 TX Vref=18, minBit 0, minWin=23, winSum=389 TX Vref=20, minBit 0, minWin=23, winSum=390 TX Vref=22, minBit 2, minWin=24, winSum=403 TX Vref=24, minBit 5, minWin=23, winSum=411 TX Vref=26, minBit 0, minWin=25, winSum=418 TX Vref=28, minBit 0, minWin=23, winSum=418 TX Vref=30, minBit 0, minWin=24, winSum=418 TX Vref=32, minBit 0, minWin=23, winSum=400 TX Vref=34, minBit 0, minWin=22, winSum=400 TX Vref=36, minBit 0, minWin=21, winSum=386 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26 Final TX Range 0 Vref 26 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps == TX Byte 0 == u2DelayCellOfst[0]=17 cells (5 PI) u2DelayCellOfst[1]=10 cells (3 PI) u2DelayCellOfst[2]=0 cells (0 PI) u2DelayCellOfst[3]=7 cells (2 PI) u2DelayCellOfst[4]=10 cells (3 PI) u2DelayCellOfst[5]=17 cells (5 PI) u2DelayCellOfst[6]=17 cells (5 PI) u2DelayCellOfst[7]=7 cells (2 PI) Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3) Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=0 cells (0 PI) u2DelayCellOfst[9]=7 cells (2 PI) u2DelayCellOfst[10]=14 cells (4 PI) u2DelayCellOfst[11]=7 cells (2 PI) u2DelayCellOfst[12]=17 cells (5 PI) u2DelayCellOfst[13]=21 cells (6 PI) u2DelayCellOfst[14]=21 cells (6 PI) u2DelayCellOfst[15]=21 cells (6 PI) Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3) Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH1 RK1 DATLAT Default: 0xe 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0xF7F, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 3 -> 252, step: 4 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 126, DQM1 = 122 DQ Delay: DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =122 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x5151, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps CH1 RK1: MR19=303, MR18=1B1B CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15 [RxdqsGatingPostProcess] freq 1600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 3200 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. DramC Write-DBI on PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [FAST_K] Save calibration result to emmc sync common calibartion params. sync cbt_mode0:0, 1:0 dram_init: ddr_geometry: 0 dram_init: ddr_geometry: 0 dram_init: ddr_geometry: 0 0:dram_rank_size:80000000 1:dram_rank_size:80000000 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000 DFS_SHUFFLE_HW_MODE: ON dramc_set_vcore_voltage set vcore to 725000 Read voltage for 1600, 0 Vio18 = 0 Vcore = 725000 Vdram = 0 Vddq = 0 Vmddr = 0 switch to 3200 Mbps bootup [DramcRunTimeConfig] PHYPLL DPM_CONTROL_AFTERK: ON PER_BANK_REFRESH: ON REFRESH_OVERHEAD_REDUCTION: ON CMD_PICG_NEW_MODE: OFF XRTWTW_NEW_MODE: ON XRTRTR_NEW_MODE: ON TX_TRACKING: ON RDSEL_TRACKING: OFF DQS Precalculation for DVFS: ON RX_TRACKING: OFF HW_GATING DBG: ON ZQCS_ENABLE_LP4: ON RX_PICG_NEW_MODE: ON TX_PICG_NEW_MODE: ON ENABLE_RX_DCM_DPHY: ON LOWPOWER_GOLDEN_SETTINGS(DCM): ON DUMMY_READ_FOR_TRACKING: OFF !!! SPM_CONTROL_AFTERK: OFF !!! SPM could not control APHY IMPEDANCE_TRACKING: ON TEMP_SENSOR: ON HW_SAVE_FOR_SR: OFF CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF Read ODT Tracking: ON Refresh Rate DeBounce: ON DFS_NO_QUEUE_FLUSH: ON DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF ENABLE_DFS_RUNTIME_MRW: OFF DDR_RESERVE_NEW_MODE: ON MR_CBT_SWITCH_FREQ: ON ========================= [MEM] 1st complex R/W mem test pass (start addr:0x4c400000) dram_init: ddr_geometry: 0 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1) dram_init: dram init end (result: 0) DRAM-K: Full calibration passed in 23432 msecs MRC: failed to locate region type 0. DRAM rank0 size:0x80000000, DRAM rank1 size=0x80000000 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal Backing address range [0x40000000:0x80000000) with new page table @0x00112000 Backing address range [0x40000000:0x40200000) with new page table @0x00113000 DRAM rank0 size:0x80000000, DRAM rank1 size=0x80000000 CBMEM: IMD: root @ 0xfffff000 254 entries. IMD: root @ 0xffffec00 62 entries. FMAP: area RO_VPD found @ 3f8000 (32768 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 577000 (16384 bytes) CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps BS: romstage times (exec / console): total (unknown) / 22968 ms coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 Root Device scanning... scan_static_bus for Root Device CPU_CLUSTER: 0 enabled scan_static_bus for Root Device done scan_bus: bus Root Device finished in 8 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x800000 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 DRAM rank0 size:0x80000000, DRAM rank1 size=0x80000000 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 CPU: 00 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0 CPU: 00 Root Device assign_resources, bus 0 link: 0 CPU_CLUSTER: 0 missing set_resources Root Device assign_resources, bus 0 link: 0 done Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 CPU: 00 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0 CPU: 00 Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms Enabling resources... done. BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms Initializing devices... Root Device init init hardware done! 0x00000018: ctrlr->caps 52.000 MHz: ctrlr->f_max 0.400 MHz: ctrlr->f_min 0x40ff8080: ctrlr->voltages sclk: 390625 Bus Width = 1 sclk: 390625 Bus Width = 1 Early init status = 3 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 in-header: 03 fc 00 00 01 00 00 00 in-data: 00 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 in-header: 03 fd 00 00 00 00 00 00 in-data: out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 in-header: 03 fc 00 00 01 00 00 00 in-data: 00 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 in-header: 03 fd 00 00 00 00 00 00 in-data: [SSUSB] Setting up USB HOST controller... [SSUSB] u3phy_ports_enable u2p:1, u3p:1 [SSUSB] phy power-on done. FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes) CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes) CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps SPM: binary array size = 0x9dc SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16) spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes) SPM: spm_init done in 34 msecs, spm pc = 0x3f4 configure_display: Starting display init anx7625_power_on_init: Init interface. anx7625_disable_pd_protocol: Disabled PD feature. anx7625_power_on_init: Firmware: ver 0x13, rev 0x0. anx7625_start_dp_work: Secure OCM version=00 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91 sp_tx_get_edid_block: EDID Block = 1 Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 26 cf 7d 05 00 00 00 00 00 1e version: 01 04 basic params: 95 1f 11 78 0a chroma info: 76 90 94 55 54 90 27 21 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a extensions: 00 checksum: fb Manufacturer: IVO Model 57d Serial Number 0 Made week 0 of 2020 EDID version: 1.4 Digital display 6 bits per primary color channel DisplayPort interface Maximum image size: 31 cm x 17 cm Gamma: 220% Check DPMS levels Supported color formats: RGB 4:4:4, YCrCb 4:2:2 First detailed timing is preferred timing Established timings supported: Standard timings supported: Detailed timings Hex of detail: 383680a07038204018303c0035ae10000019 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm 0780 0798 07c8 0820 hborder 0 0438 043b 0447 0458 vborder 0 -hsync -vsync Did detailed timing Hex of detail: 000000000000000000000000000000000000 Manufacturer-specified data, tag 0 Hex of detail: 000000fe00496e666f566973696f6e0a2020 ASCII string: InfoVision Hex of detail: 000000fe00523134304e574635205248200a ASCII string: R140NWF5 RH Checksum Checksum: 0xfb (valid) configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz DSI data_rate: 832800000 bps anx7625_parse_edid: detected IVO panel, use k value 0x3b anx7625_parse_edid: pixelclock(138800). hactive(1920), hsync(48), hfp(24), hbp(88) vactive(1080), vsync(12), vfp(3), vbp(17) anx7625_dsi_config: config dsi. anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4). anx7625_dsi_config: success to config DSI anx7625_dp_start: MIPI phy setup OK. mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4 mtk_ddp_mode_set invalid vrefresh 60 main_disp_path_setup ovl_layer_smi_id_en ovl_layer_smi_id_en ccorr_config aal_config gamma_config postmask_config dither_config framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0 Root Device init finished in 551 msecs CPU_CLUSTER: 0 init Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff APU_MBOX 0x190000b0 = 0x10001 APU_MBOX 0x190001b0 = 0x10001 APU_MBOX 0x190005b0 = 0x10001 APU_MBOX 0x190006b0 = 0x10001 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes) CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes) CPU_CLUSTER: 0 init finished in 81 msecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms FMAP: area RW_ELOG found @ 57f000 (4096 bytes) ELOG: NV offset 0x57f000 size 0x1000 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(17) added with size 13 at 2023-09-05 22:10:50 UTC out: cmd=0x121: 03 db 21 01 00 00 00 00 in-header: 03 ca 00 00 2c 00 00 00 in-data: 99 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ELOG: Event(A1) added with size 10 at 2023-09-05 22:10:50 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b ELOG: Event(A0) added with size 9 at 2023-09-05 22:10:50 UTC elog_add_boot_reason: Logged dev mode boot BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms Finalize devices... Devices finalized BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms Writing coreboot table at 0xffe64000 0. 000000000010a000-0000000000113fff: RAMSTAGE 1. 0000000040000000-00000000400fffff: RAM 2. 0000000040100000-000000004032afff: RAMSTAGE 3. 000000004032b000-00000000545fffff: RAM 4. 0000000054600000-000000005465ffff: BL31 5. 0000000054660000-00000000ffe63fff: RAM 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES 7. 0000000100000000-000000013fffffff: RAM Passing 5 GPIOs to payload: NAME | PORT | POLARITY | VALUE EC in RW | 0x000000aa | low | undefined EC interrupt | 0x00000005 | low | undefined TPM interrupt | 0x000000ab | high | undefined SD card detect | 0x00000011 | high | undefined speaker enable | 0x00000093 | high | undefined out: cmd=0x6: 03 f7 06 00 00 00 00 00 in-header: 03 f8 00 00 02 00 00 00 in-data: 03 00 ADC[4]: Raw value=668222 ID=5 ADC[3]: Raw value=212180 ID=1 RAM Code: 0x51 ADC[6]: Raw value=74410 ID=0 ADC[5]: Raw value=211444 ID=1 SKU Code: 0x1 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 17ad coreboot table: 964 bytes. IMD ROOT 0. 0xfffff000 0x00001000 IMD SMALL 1. 0xffffe000 0x00001000 RO MCACHE 2. 0xffffc000 0x00001104 CONSOLE 3. 0xfff7c000 0x00080000 FMAP 4. 0xfff7b000 0x00000452 TIME STAMP 5. 0xfff7a000 0x00000910 VBOOT WORK 6. 0xfff66000 0x00014000 RAMOOPS 7. 0xffe66000 0x00100000 COREBOOT 8. 0xffe64000 0x00002000 IMD small region: IMD ROOT 0. 0xffffec00 0x00000400 VPD 1. 0xffffeb80 0x0000006c MMC STATUS 2. 0xffffeb60 0x00000004 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6 Initialized TPM device CR50 revision 0 Checking cr50 for pending updates Reading cr50 TPM mode BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps Checking segment from ROM address 0x40100000 Checking segment from ROM address 0x4010001c Loading segment from ROM address 0x40100000 code (compression=0) New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178 it's not compressed! [ 0x80000000, 8004f178, 0x821a7280) <- 40100038 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108 Loading segment from ROM address 0x4010001c Entry Point 0x80000000 Loaded segments BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms Jumping to boot code at 0x80000000(0xffe64000) CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps Checking segment from ROM address 0x40100000 Checking segment from ROM address 0x4010001c Loading segment from ROM address 0x40100000 code (compression=1) New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470 using LZMA [ 0x54600000, 54614abc, 0x5462e000) <- 40100038 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544 Loading segment from ROM address 0x4010001c Entry Point 0x54601000 Loaded segments NOTICE: MT8192 bl31_setup NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021 WARNING: region 0: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 WARNING: region 1: WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d WARNING: region 2: WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d WARNING: region 3: WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d WARNING: region 4: WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d WARNING: region 5: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 WARNING: region 6: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 WARNING: region 7: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0 INFO: [APUAPC] vio 0 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS! INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS! INFO: [APUAPC] D0_APC_0: 0x400510 INFO: [APUAPC] D0_APC_1: 0x0 INFO: [APUAPC] D0_APC_2: 0x1540 INFO: [APUAPC] D0_APC_3: 0x0 INFO: [APUAPC] D1_APC_0: 0xffffffff INFO: [APUAPC] D1_APC_1: 0xffffffff INFO: [APUAPC] D1_APC_2: 0x3fffff INFO: [APUAPC] D1_APC_3: 0x0 INFO: [APUAPC] D2_APC_0: 0xffffffff INFO: [APUAPC] D2_APC_1: 0xffffffff INFO: [APUAPC] D2_APC_2: 0x3fffff INFO: [APUAPC] D2_APC_3: 0x0 INFO: [APUAPC] D3_APC_0: 0xffffffff INFO: [APUAPC] D3_APC_1: 0xffffffff INFO: [APUAPC] D3_APC_2: 0x3fffff INFO: [APUAPC] D3_APC_3: 0x0 INFO: [APUAPC] D4_APC_0: 0xffffffff INFO: [APUAPC] D4_APC_1: 0xffffffff INFO: [APUAPC] D4_APC_2: 0x3fffff INFO: [APUAPC] D4_APC_3: 0x0 INFO: [APUAPC] D5_APC_0: 0xffffffff INFO: [APUAPC] D5_APC_1: 0xffffffff INFO: [APUAPC] D5_APC_2: 0x3fffff INFO: [APUAPC] D5_APC_3: 0x0 INFO: [APUAPC] D6_APC_0: 0xffffffff INFO: [APUAPC] D6_APC_1: 0xffffffff INFO: [APUAPC] D6_APC_2: 0x3fffff INFO: [APUAPC] D6_APC_3: 0x0 INFO: [APUAPC] D7_APC_0: 0xffffffff INFO: [APUAPC] D7_APC_1: 0xffffffff INFO: [APUAPC] D7_APC_2: 0x3fffff INFO: [APUAPC] D7_APC_3: 0x0 INFO: [APUAPC] D8_APC_0: 0xffffffff INFO: [APUAPC] D8_APC_1: 0xffffffff INFO: [APUAPC] D8_APC_2: 0x3fffff INFO: [APUAPC] D8_APC_3: 0x0 INFO: [APUAPC] D9_APC_0: 0xffffffff INFO: [APUAPC] D9_APC_1: 0xffffffff INFO: [APUAPC] D9_APC_2: 0x3fffff INFO: [APUAPC] D9_APC_3: 0x0 INFO: [APUAPC] D10_APC_0: 0xffffffff INFO: [APUAPC] D10_APC_1: 0xffffffff INFO: [APUAPC] D10_APC_2: 0x3fffff INFO: [APUAPC] D10_APC_3: 0x0 INFO: [APUAPC] D11_APC_0: 0xffffffff INFO: [APUAPC] D11_APC_1: 0xffffffff INFO: [APUAPC] D11_APC_2: 0x3fffff INFO: [APUAPC] D11_APC_3: 0x0 INFO: [APUAPC] D12_APC_0: 0xffffffff INFO: [APUAPC] D12_APC_1: 0xffffffff INFO: [APUAPC] D12_APC_2: 0x3fffff INFO: [APUAPC] D12_APC_3: 0x0 INFO: [APUAPC] D13_APC_0: 0xffffffff INFO: [APUAPC] D13_APC_1: 0xffffffff INFO: [APUAPC] D13_APC_2: 0x3fffff INFO: [APUAPC] D13_APC_3: 0x0 INFO: [APUAPC] D14_APC_0: 0xffffffff INFO: [APUAPC] D14_APC_1: 0xffffffff INFO: [APUAPC] D14_APC_2: 0x3fffff INFO: [APUAPC] D14_APC_3: 0x0 INFO: [APUAPC] D15_APC_0: 0xffffffff INFO: [APUAPC] D15_APC_1: 0xffffffff INFO: [APUAPC] D15_APC_2: 0x3fffff INFO: [APUAPC] D15_APC_3: 0x0 INFO: [APUAPC] APC_CON: 0x4 INFO: [NOCDAPC] D0_APC_0: 0x0 INFO: [NOCDAPC] D0_APC_1: 0x0 INFO: [NOCDAPC] D1_APC_0: 0x0 INFO: [NOCDAPC] D1_APC_1: 0xfff INFO: [NOCDAPC] D2_APC_0: 0x0 INFO: [NOCDAPC] D2_APC_1: 0xfff INFO: [NOCDAPC] D3_APC_0: 0x0 INFO: [NOCDAPC] D3_APC_1: 0xfff INFO: [NOCDAPC] D4_APC_0: 0x0 INFO: [NOCDAPC] D4_APC_1: 0xfff INFO: [NOCDAPC] D5_APC_0: 0x0 INFO: [NOCDAPC] D5_APC_1: 0xfff INFO: [NOCDAPC] D6_APC_0: 0x0 INFO: [NOCDAPC] D6_APC_1: 0xfff INFO: [NOCDAPC] D7_APC_0: 0x0 INFO: [NOCDAPC] D7_APC_1: 0xfff INFO: [NOCDAPC] D8_APC_0: 0x0 INFO: [NOCDAPC] D8_APC_1: 0xfff INFO: [NOCDAPC] D9_APC_0: 0x0 INFO: [NOCDAPC] D9_APC_1: 0xfff INFO: [NOCDAPC] D10_APC_0: 0x0 INFO: [NOCDAPC] D10_APC_1: 0xfff INFO: [NOCDAPC] D11_APC_0: 0x0 INFO: [NOCDAPC] D11_APC_1: 0xfff INFO: [NOCDAPC] D12_APC_0: 0x0 INFO: [NOCDAPC] D12_APC_1: 0xfff INFO: [NOCDAPC] D13_APC_0: 0x0 INFO: [NOCDAPC] D13_APC_1: 0xfff INFO: [NOCDAPC] D14_APC_0: 0x0 INFO: [NOCDAPC] D14_APC_1: 0xfff INFO: [NOCDAPC] D15_APC_0: 0x0 INFO: [NOCDAPC] D15_APC_1: 0xfff INFO: [NOCDAPC] APC_CON: 0x4 INFO: [APUAPC] set_apusys_apc done INFO: [DEVAPC] devapc_init done INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: Maximum SPI INTID supported: 639 INFO: BL31: Initializing runtime services WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing! INFO: SPM: enable CPC mode INFO: mcdi ready for mcusys-off-idle and system suspend INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x80000000 INFO: SPSR = 0x8 Starting depthcharge on Spherion... Wipe memory regions: [0x00000040000000, 0x00000054600000) [0x00000054660000, 0x00000080000000) [0x000000821a7280, 0x000000ffe64000) [0x00000100000000, 0x00000140000000) Initializing XHCI USB controller at 0x11200000. [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38 asurada: tftpboot 192.168.201.1 11440308/tftp-deploy-yi_q08mg/kernel/image.itb 11440308/tftp-deploy-yi_q08mg/kernel/cmdline tftpboot 192.168.201.1 11440308/tftp-deploy-yi_q08mg/kernel/image.itp-deploy-yi_q08mg/kernel/cmdline Waiting for link R8152: Initializing Version 9 (ocp_data = 6010) R8152: Done initializing Adding net device done. MAC: 00:e0:4c:68:03:bd Sending DHCP discover... done. Waiting for reply... done. Sending DHCP request... done. Waiting for reply... done. My ip is 192.168.201.16 The DHCP server ip is 192.168.201.1 TFTP server IP predefined by user: 192.168.201.1 Bootfile predefined by user: 11440308/tftp-deploy-yi_q08mg/kernel/image.itb Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ################################################################ 00880000 ################################################################ 00900000 ################################################################ 00980000 ################################################################ 00a00000 ################################################################ 00a80000 ################################################################ 00b00000 ################################################################ 00b80000 ################################################################ 00c00000 ################################################################ 00c80000 ################################################################ 00d00000 ################################################################ 00d80000 ################################################################ 00e00000 ################################################################ 00e80000 ################################################################ 00f00000 ################################################################ 00f80000 ################################################################ 01000000 ################################################################ 01080000 ################################################################ 01100000 ################################################################ 01180000 ################################################################ 01200000 ################################################################ 01280000 ################################################################ 01300000 ################################################################ 01380000 ################################################################ 01400000 ################################################################ 01480000 ################################################################ 01500000 ################################################################ 01580000 ################################################################ 01600000 ################################################################ 01680000 ################################################################ 01700000 ################################################################ 01780000 ################################################################ 01800000 ################################################################ 01880000 ################################################################ 01900000 ################################################################ 01980000 ################################################################ 01a00000 ################################################################ 01a80000 ################################################################ 01b00000 ################################################################ 01b80000 ################################################################ 01c00000 ################################################################ 01c80000 ################################################################ 01d00000 ################################################################ 01d80000 ################################################################ 01e00000 ################################################################ 01e80000 ############################################################ done. The bootfile was 32469982 bytes long. Sending tftp read request... done. Waiting for the transfer... 00000000 # done. Command line loaded dynamically from TFTP file: 11440308/tftp-deploy-yi_q08mg/kernel/cmdline The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1 Loading FIT. Image ramdisk-1 has 21382673 bytes. Image fdt-1 has 47278 bytes. Image kernel-1 has 11037994 bytes. Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192 Choosing best match conf-1 for compat google,spherion-rev3. Connected to device vid:did:rid of 1ae0:0028:00 tpm_get_response: command 0x17b, return code 0x0 ec_init: CrosEC protocol v3 supported (256, 248) tpm_cleanup: add release locality here. Shutting down all USB controllers. Removing current net device Exiting depthcharge with code 4 at timestamp: 53329406 LZMA decompressing kernel-1 to 0x821a6718 LZMA decompressing kernel-1 to 0x40000000 jumping to kernel [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050] [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j35911-arm64-gcc-10-defconfig-arm64-chromebook-zzzh4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Sep 5 21:54:53 UTC 2023 [ 0.000000] random: crng init done [ 0.000000] Machine model: Google Spherion (rev0 - 3) [ 0.000000] efi: UEFI not found. [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8') [ 0.000000] printk: bootconsole [mtk8250] enabled [ 0.000000] NUMA: No NUMA configuration found [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff] [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff] [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff] [ 0.000000] DMA32 empty [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff] [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff] [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff] [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff] [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff] [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.2 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: GIC system register CPU interface [ 0.000000] CPU features: detected: Virtualization Host Extensions [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI) [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923 [ 0.000000] alternatives: applying boot alternatives [ 0.000000] Fallback order for Node 0: 0 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424 [ 0.000000] Policy zone: Normal [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space. <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off <6>[ 0.000000] software IO TLB: area num 8. <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB) <6>[ 0.000000] Memory: 3834264K/4191232K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 324200K reserved, 32768K cma-reserved) <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation. <6>[ 0.000000] rcu: RCU event tracing is enabled. <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8. <6>[ 0.000000] Trampoline variant of Tasks RCU enabled. <6>[ 0.000000] Tracing variant of Tasks RCU enabled. <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode <6>[ 0.000000] GICv3: 608 SPIs implemented <6>[ 0.000000] GICv3: 0 Extended SPIs implemented <6>[ 0.000000] Root IRQ handler: gic_handle_irq <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] } <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] } <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys). <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns <6>[ 0.009225] Console: colour dummy device 80x25 <6>[ 0.013951] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000) <6>[ 0.024393] pid_max: default: 32768 minimum: 301 <6>[ 0.029264] LSM: Security Framework initializing <6>[ 0.034178] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) <6>[ 0.041784] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) <6>[ 0.051069] cblist_init_generic: Setting adjustable number of callback queues. <6>[ 0.058515] cblist_init_generic: Setting shift to 3 and lim to 1. <6>[ 0.064853] cblist_init_generic: Setting adjustable number of callback queues. <6>[ 0.072278] cblist_init_generic: Setting shift to 3 and lim to 1. <6>[ 0.078715] rcu: Hierarchical SRCU implementation. <6>[ 0.083728] rcu: Max phase no-delay instances is 1000. <6>[ 0.090760] EFI services will not be available. <6>[ 0.095725] smp: Bringing up secondary CPUs ... <6>[ 0.100774] Detected VIPT I-cache on CPU1 <6>[ 0.100842] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000 <6>[ 0.100874] CPU1: Booted secondary processor 0x0000000100 [0x412fd050] <6>[ 0.101208] Detected VIPT I-cache on CPU2 <6>[ 0.101255] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000 <6>[ 0.101269] CPU2: Booted secondary processor 0x0000000200 [0x412fd050] <6>[ 0.101528] Detected VIPT I-cache on CPU3 <6>[ 0.101574] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000 <6>[ 0.101588] CPU3: Booted secondary processor 0x0000000300 [0x412fd050] <6>[ 0.101895] CPU features: detected: Spectre-v4 <6>[ 0.101902] CPU features: detected: Spectre-BHB <6>[ 0.101906] Detected PIPT I-cache on CPU4 <6>[ 0.101962] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000 <6>[ 0.101979] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0] <6>[ 0.102272] Detected PIPT I-cache on CPU5 <6>[ 0.102333] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000 <6>[ 0.102350] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0] <6>[ 0.102630] Detected PIPT I-cache on CPU6 <6>[ 0.102691] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000 <6>[ 0.102707] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0] <6>[ 0.103007] Detected PIPT I-cache on CPU7 <6>[ 0.103069] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000 <6>[ 0.103086] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0] <6>[ 0.103133] smp: Brought up 1 node, 8 CPUs <6>[ 0.244438] SMP: Total of 8 processors activated. <6>[ 0.249359] CPU features: detected: 32-bit EL0 Support <6>[ 0.254721] CPU features: detected: Data cache clean to the PoU not required for I/D coherence <6>[ 0.263576] CPU features: detected: Common not Private translations <6>[ 0.270051] CPU features: detected: CRC32 instructions <6>[ 0.275402] CPU features: detected: RCpc load-acquire (LDAPR) <6>[ 0.281361] CPU features: detected: LSE atomic instructions <6>[ 0.287143] CPU features: detected: Privileged Access Never <6>[ 0.292922] CPU features: detected: RAS Extension Support <6>[ 0.298531] CPU features: detected: Speculative Store Bypassing Safe (SSBS) <6>[ 0.305751] CPU: All CPU(s) started at EL2 <6>[ 0.310067] alternatives: applying system-wide alternatives <6>[ 0.319910] devtmpfs: initialized <6>[ 0.328121] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns <6>[ 0.338084] futex hash table entries: 2048 (order: 5, 131072 bytes, linear) <6>[ 0.346107] pinctrl core: initialized pinctrl subsystem <6>[ 0.352744] DMI not present or invalid. <6>[ 0.357141] NET: Registered PF_NETLINK/PF_ROUTE protocol family <6>[ 0.363968] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations <6>[ 0.371414] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations <6>[ 0.379504] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations <6>[ 0.387659] audit: initializing netlink subsys (disabled) <5>[ 0.393352] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1 <6>[ 0.394048] thermal_sys: Registered thermal governor 'step_wise' <6>[ 0.401317] thermal_sys: Registered thermal governor 'power_allocator' <6>[ 0.407574] cpuidle: using governor menu <6>[ 0.418534] NET: Registered PF_QIPCRTR protocol family <6>[ 0.424016] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. <6>[ 0.431122] ASID allocator initialised with 32768 entries <6>[ 0.437652] Serial: AMBA PL011 UART driver <4>[ 0.446353] Trying to register duplicate clock ID: 134 <6>[ 0.503841] KASLR enabled <6>[ 0.511535] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages <6>[ 0.518549] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page <6>[ 0.525040] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages <6>[ 0.532045] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page <6>[ 0.538531] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages <6>[ 0.545536] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page <6>[ 0.552022] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages <6>[ 0.559025] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page <6>[ 0.566528] ACPI: Interpreter disabled. <6>[ 0.572926] iommu: Default domain type: Translated <6>[ 0.578039] iommu: DMA domain TLB invalidation policy: strict mode <5>[ 0.584668] SCSI subsystem initialized <6>[ 0.588833] usbcore: registered new interface driver usbfs <6>[ 0.594563] usbcore: registered new interface driver hub <6>[ 0.600115] usbcore: registered new device driver usb <6>[ 0.606212] pps_core: LinuxPPS API ver. 1 registered <6>[ 0.611405] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <6>[ 0.620754] PTP clock support registered <6>[ 0.624998] EDAC MC: Ver: 3.0.0 <6>[ 0.630130] FPGA manager framework <6>[ 0.633807] Advanced Linux Sound Architecture Driver Initialized. <6>[ 0.640577] vgaarb: loaded <6>[ 0.643733] clocksource: Switched to clocksource arch_sys_counter <5>[ 0.650166] VFS: Disk quotas dquot_6.6.0 <6>[ 0.654352] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) <6>[ 0.661537] pnp: PnP ACPI: disabled <6>[ 0.668201] NET: Registered PF_INET protocol family <6>[ 0.673580] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear) <6>[ 0.683591] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear) <6>[ 0.692377] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) <6>[ 0.700342] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear) <6>[ 0.708746] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear) <6>[ 0.717405] TCP: Hash tables configured (established 32768 bind 32768) <6>[ 0.724264] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear) <6>[ 0.731283] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear) <6>[ 0.738802] NET: Registered PF_UNIX/PF_LOCAL protocol family <6>[ 0.744954] RPC: Registered named UNIX socket transport module. <6>[ 0.751108] RPC: Registered udp transport module. <6>[ 0.756040] RPC: Registered tcp transport module. <6>[ 0.760971] RPC: Registered tcp NFSv4.1 backchannel transport module. <6>[ 0.767636] PCI: CLS 0 bytes, default 64 <6>[ 0.772028] Unpacking initramfs... <6>[ 0.775743] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available <6>[ 0.784406] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available <6>[ 0.793246] kvm [1]: IPA Size Limit: 40 bits <6>[ 0.797776] kvm [1]: GICv3: no GICV resource entry <6>[ 0.802799] kvm [1]: disabling GICv2 emulation <6>[ 0.807486] kvm [1]: GIC system register CPU interface enabled <6>[ 0.813660] kvm [1]: vgic interrupt IRQ18 <6>[ 0.818019] kvm [1]: VHE mode initialized successfully <5>[ 0.824532] Initialise system trusted keyrings <6>[ 0.829337] workingset: timestamp_bits=42 max_order=20 bucket_order=0 <6>[ 0.839310] squashfs: version 4.0 (2009/01/31) Phillip Lougher <5>[ 0.845694] NFS: Registering the id_resolver key type <5>[ 0.850993] Key type id_resolver registered <5>[ 0.855407] Key type id_legacy registered <6>[ 0.859701] nfs4filelayout_init: NFSv4 File Layout Driver Registering... <6>[ 0.866625] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... <6>[ 0.874351] 9p: Installing v9fs 9p2000 file system support <5>[ 0.912790] Key type asymmetric registered <5>[ 0.917121] Asymmetric key parser 'x509' registered <6>[ 0.922263] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243) <6>[ 0.929879] io scheduler mq-deadline registered <6>[ 0.934640] io scheduler kyber registered <6>[ 0.951612] EINJ: ACPI disabled. <4>[ 0.976947] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator <4>[ 0.987584] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator <6>[ 1.008504] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled <6>[ 1.016607] printk: console [ttyS0] disabled <6>[ 1.041251] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2 <6>[ 1.050724] printk: console [ttyS0] enabled <6>[ 1.050724] printk: console [ttyS0] enabled <6>[ 1.059617] printk: bootconsole [mtk8250] disabled <6>[ 1.059617] printk: bootconsole [mtk8250] disabled <6>[ 1.070850] SuperH (H)SCI(F) driver initialized <6>[ 1.076148] msm_serial: driver initialized <6>[ 1.085116] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000 <6>[ 1.093664] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000 <6>[ 1.102205] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000 <6>[ 1.110833] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000 <6>[ 1.119540] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000 <6>[ 1.128260] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000 <6>[ 1.136801] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000 <6>[ 1.145605] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000 <6>[ 1.154149] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000 <6>[ 1.169704] loop: module loaded <6>[ 1.175718] vgpu11_sshub: Bringing 400000uV into 575000-575000uV <4>[ 1.199116] mtk-pmic-keys: Failed to locate of_node [id: -1] <6>[ 1.206094] megasas: 07.719.03.00-rc1 <6>[ 1.215907] spi-nor spi2.0: w25q64jwm (8192 Kbytes) <6>[ 1.223160] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2 <6>[ 1.239126] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0) <6>[ 1.288630] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2 <6>[ 1.670638] Freeing initrd memory: 20876K <6>[ 1.686259] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz <6>[ 1.697335] tun: Universal TUN/TAP device driver, 1.6 <6>[ 1.703413] thunder_xcv, ver 1.0 <6>[ 1.706919] thunder_bgx, ver 1.0 <6>[ 1.710415] nicpf, ver 1.0 <6>[ 1.714441] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version <6>[ 1.721916] hns3: Copyright (c) 2017 Huawei Corporation. <6>[ 1.727507] hclge is initializing <6>[ 1.731089] e1000: Intel(R) PRO/1000 Network Driver <6>[ 1.736219] e1000: Copyright (c) 1999-2006 Intel Corporation. <6>[ 1.742230] e1000e: Intel(R) PRO/1000 Network Driver <6>[ 1.747446] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. <6>[ 1.753633] igb: Intel(R) Gigabit Ethernet Network Driver <6>[ 1.759283] igb: Copyright (c) 2007-2014 Intel Corporation. <6>[ 1.765120] igbvf: Intel(R) Gigabit Virtual Function Network Driver <6>[ 1.771638] igbvf: Copyright (c) 2009 - 2012 Intel Corporation. <6>[ 1.778097] sky2: driver version 1.30 <6>[ 1.783099] VFIO - User Level meta-driver version: 0.3 <6>[ 1.791349] usbcore: registered new interface driver usb-storage <6>[ 1.797796] usbcore: registered new device driver onboard-usb-hub <6>[ 1.806930] mt6397-rtc mt6359-rtc: registered as rtc0 <6>[ 1.812396] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-05T22:11:22 UTC (1693951882) <6>[ 1.821960] i2c_dev: i2c /dev entries driver <6>[ 1.833748] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0) <6>[ 1.857725] cpu cpu0: EM: created perf domain <6>[ 1.862690] cpu cpu4: EM: created perf domain <6>[ 1.868269] sdhci: Secure Digital Host Controller Interface driver <6>[ 1.874710] sdhci: Copyright(c) Pierre Ossman <6>[ 1.879621] Synopsys Designware Multimedia Card Interface Driver <6>[ 1.886227] sdhci-pltfm: SDHCI platform and OF driver helper <6>[ 1.886292] mmc0: CQHCI version 5.10 <6>[ 1.896562] ledtrig-cpu: registered to indicate activity on CPUs <6>[ 1.903567] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000 <6>[ 1.910592] usbcore: registered new interface driver usbhid <6>[ 1.916415] usbhid: USB HID core driver <6>[ 1.920622] spi_master spi0: will run message pump with realtime priority <6>[ 1.959095] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0 <6>[ 1.975252] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1 <6>[ 1.988835] mmc0: Command Queue Engine enabled <6>[ 1.993614] mmc0: new HS400 Enhanced strobe MMC card at address 0001 <6>[ 2.000879] mmcblk0: mmc0:0001 DA4064 58.2 GiB <6>[ 2.005808] cros-ec-spi spi0.0: Chrome EC device registered <6>[ 2.009447] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 <6>[ 2.019343] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB <6>[ 2.025197] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB <6>[ 2.031280] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0) <6>[ 2.045387] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0) <6>[ 2.055564] NET: Registered PF_PACKET protocol family <6>[ 2.060960] 9pnet: Installing 9P2000 support <5>[ 2.065527] Key type dns_resolver registered <6>[ 2.070489] registered taskstats version 1 <5>[ 2.074879] Loading compiled-in X.509 certificates <4>[ 2.096198] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator <4>[ 2.107005] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator <3>[ 2.117556] debugfs: File 'uA_load' in directory '/' already present! <3>[ 2.124263] debugfs: File 'min_uV' in directory '/' already present! <3>[ 2.130871] debugfs: File 'max_uV' in directory '/' already present! <3>[ 2.137484] debugfs: File 'constraint_flags' in directory '/' already present! <3>[ 2.147262] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0) <6>[ 2.159307] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102 <6>[ 2.166132] xhci-mtk 11200000.usb: xHCI Host Controller <6>[ 2.171627] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1 <6>[ 2.179485] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010 <6>[ 2.188920] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000 <6>[ 2.195003] xhci-mtk 11200000.usb: xHCI Host Controller <6>[ 2.200492] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2 <6>[ 2.208142] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed <6>[ 2.215912] hub 1-0:1.0: USB hub found <6>[ 2.219926] hub 1-0:1.0: 1 port detected <6>[ 2.224208] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. <6>[ 2.232936] hub 2-0:1.0: USB hub found <6>[ 2.236960] hub 2-0:1.0: 1 port detected <6>[ 2.244096] mtk-msdc 11f70000.mmc: Got CD GPIO <6>[ 2.252383] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume() <6>[ 2.260411] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock() <4>[ 2.268305] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW <6>[ 2.277819] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend() <6>[ 2.285895] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock() <6>[ 2.293915] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register() <6>[ 2.301826] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register() <6>[ 2.309646] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register() <6>[ 2.317463] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39 <6>[ 2.327694] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.336046] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.344390] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.352727] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.361063] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.369400] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.377737] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.386074] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.394411] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.402748] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.411085] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.419422] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.427759] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.436096] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.444435] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.453170] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0 <6>[ 2.460300] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0 <6>[ 2.467058] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0 <6>[ 2.473798] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0 <6>[ 2.480711] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0 <6>[ 2.487557] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 2.496689] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 2.505811] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops) <6>[ 2.515104] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops) <6>[ 2.524571] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops) <6>[ 2.534037] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops) <6>[ 2.543157] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops) <6>[ 2.552623] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 2.561741] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops) <6>[ 2.571035] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing <6>[ 2.581194] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing <6>[ 2.592519] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0 <6>[ 2.635967] usb 1-1: new high-speed USB device number 2 using xhci-mtk <6>[ 2.792551] hub 1-1:1.0: USB hub found <6>[ 2.796951] hub 1-1:1.0: 4 ports detected <6>[ 2.916258] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk <6>[ 2.945086] hub 2-1:1.0: USB hub found <6>[ 2.949563] hub 2-1:1.0: 3 ports detected <6>[ 3.112024] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk <6>[ 3.248075] hub 1-1.4:1.0: USB hub found <6>[ 3.252794] hub 1-1.4:1.0: 2 ports detected <6>[ 3.324068] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk <6>[ 3.544050] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk <6>[ 3.736047] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk <6>[ 14.897007] ALSA device list: <6>[ 14.900300] No soundcards found. <6>[ 14.908072] Freeing unused kernel memory: 8384K <6>[ 14.913074] Run /init as init process Starting syslogd: OK Starting klogd: OK Running sysctl: OK Populating /dev using udev: <30>[ 14.967545] udevd[187]: starting version 3.2.9 <27>[ 14.974009] udevd[187]: specified user 'tss' unknown <27>[ 14.979354] udevd[187]: specified group 'tss' unknown <30>[ 14.985707] udevd[188]: starting eudev-3.2.9 <27>[ 15.000843] udevd[188]: specified user 'tss' unknown <27>[ 15.006268] udevd[188]: specified group 'tss' unknown <6>[ 15.135655] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges: <6>[ 15.144541] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000 <6>[ 15.152266] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000 <3>[ 15.154448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <6>[ 15.161217] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000 <3>[ 15.169143] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <6>[ 15.178110] remoteproc remoteproc0: scp is available <6>[ 15.192520] remoteproc remoteproc0: powering up scp <3>[ 15.193166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <6>[ 15.197723] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164 <6>[ 15.197762] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0 <6>[ 15.204380] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered <3>[ 15.205960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <6>[ 15.221784] mc: Linux media interface: v0.10 <6>[ 15.222128] usbcore: registered new interface driver r8152 <3>[ 15.228672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <4>[ 15.240797] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA. <4>[ 15.240797] Fallback method does not support PEC. <3>[ 15.246079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 15.246088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 15.246096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 15.246168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <6>[ 15.255471] videodev: Linux video capture interface: v2.00 <3>[ 15.268008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <4>[ 15.269230] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator <4>[ 15.269377] elants_i2c 4-0010: supply vccio not found, using dummy regulator <3>[ 15.270389] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <3>[ 15.293448] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <3>[ 15.300279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 15.300288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <6>[ 15.304062] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk <6>[ 15.305305] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00 <6>[ 15.305313] pci_bus 0000:00: root bus resource [bus 00-ff] <6>[ 15.305320] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff] <6>[ 15.305326] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff]) <6>[ 15.305361] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400 <6>[ 15.305387] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref] <6>[ 15.305477] pci 0000:00:00.0: supports D1 D2 <6>[ 15.305482] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold <6>[ 15.307197] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring <3>[ 15.314239] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <6>[ 15.321771] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000 <6>[ 15.323142] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e <6>[ 15.323157] remoteproc remoteproc0: remote processor scp is now up <6>[ 15.323157] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd <4>[ 15.327210] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2 <4>[ 15.327216] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2) <3>[ 15.328796] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 15.328798] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 15.328802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 15.328805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 15.328832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <6>[ 15.356781] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003 <6>[ 15.362972] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref] <6>[ 15.363825] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected <6>[ 15.366191] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered <6>[ 15.370053] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2 <6>[ 15.376662] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref] <6>[ 15.378731] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3 <6>[ 15.400116] usbcore: registered new interface driver cdc_ether <6>[ 15.406051] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref] <6>[ 15.406587] Bluetooth: Core ver 2.22 <6>[ 15.406694] NET: Registered PF_BLUETOOTH protocol family <6>[ 15.406701] Bluetooth: HCI device and connection manager initialized <6>[ 15.406733] Bluetooth: HCI socket layer initialized <6>[ 15.406738] Bluetooth: L2CAP socket layer initialized <6>[ 15.406751] Bluetooth: SCO socket layer initialized <6>[ 15.424749] usbcore: registered new interface driver r8153_ecm <6>[ 15.433117] pci 0000:01:00.0: supports D1 D2 <6>[ 15.448142] usbcore: registered new interface driver btusb <6>[ 15.455799] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold <6>[ 15.455861] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741) <6>[ 15.456050] r8152 2-1.3:1.0 eth0: v1.12.13 <4>[ 15.456279] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2 <3>[ 15.456293] Bluetooth: hci0: Failed to load firmware file (-2) <3>[ 15.456296] Bluetooth: hci0: Failed to set up firmware (-2) <4>[ 15.456301] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported. <6>[ 15.457733] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4 <6>[ 15.457826] usbcore: registered new interface driver uvcvideo <6>[ 15.478935] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0 <6>[ 15.736142] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 <6>[ 15.743093] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref] <6>[ 15.751193] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref] <6>[ 15.759190] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref] <6>[ 15.767191] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref] <6>[ 15.775191] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref] <6>[ 15.783190] pci 0000:00:00.0: PCI bridge to [bus 01] <6>[ 15.788406] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref] <6>[ 15.796601] pcieport 0000:00:00.0: enabling device (0000 -> 0002) <6>[ 15.803432] pcieport 0000:00:00.0: PME: Signaling with IRQ 283 <6>[ 15.810252] pcieport 0000:00:00.0: AER: enabled with IRQ 283 <5>[ 15.829842] cfg80211: Loading compiled-in X.509 certificates for regulatory database <5>[ 15.849139] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' <4>[ 15.856173] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2 <6>[ 15.865141] cfg80211: failed to load regulatory.db <6>[ 15.922951] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000 <6>[ 15.930545] mt7921e 0000:01:00.0: enabling device (0000 -> 0002) <6>[ 15.957582] mt7921e 0000:01:00.0: ASIC revision: 79610010 <4>[ 16.056226] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 done Saving random seed: OK Starting network: OK Starting dropbear sshd: <6>[ 16.132576] NET: Registered PF_INET6 protocol family <6>[ 16.139054] Segment Routing with IPv6 <6>[ 16.143178] In-situ OAM (IOAM) with IPv6 OK /bin/sh: can't access tty; job control turned off / # <4>[ 16.178121] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 / # # #<4>[ 16.295487] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 / # export SHELL=/bin/sh export SHELL=/bin/sh<4>[ 16.416219] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 / # . /lava-11440308/environment . /lava-11440308/environment<4>[ 16.536348] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 / # /lava-11440308/bin/lava-test-runner /lava-11440308/0 /lava-11440308/bin/lava-test-runner /lava-11440308/0<4>[ 16.656474] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 + export 'TESTRUN_ID=0_dmesg' +<8>[ 16.717895] cd /lava-11440308/0/tests/0_dmesg + cat uuid + UUID=11440308_1.5.2.3.1 + set +x + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh <8>[ 16.735445] <8>[ 16.756098] <4>[ 16.778316] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 <8>[ 16.780053] + set +x <8>[ 16.800468] / # # export SHELL=/bin/sh #<4>[ 16.896082] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 / # export SHELL=/bin/sh<4>[ 17.016471] mt7921e 0000:01:00.0. /lava-11440308/environment : Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 / # . /lava-11440308/environment/lava-11440308/bin/lava-test-runner /lava-11440308/1 / # <4>[ 17.136357] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 /lava-11440308/bin/lava-test-runner /lava-11440308/1 + export 'TESTRUN_ID=1_bootrr' + cd /lava-11440<8>[ 17.249209] <3>[ 17.253267] mt7921e 0000:01:00.0: hardware init failed 308/1/tests/1_bootrr + cat uuid + UUID=11440308_1.5.2.3.5 + set +x + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11440308/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin' + cd /opt/bootr<8>[ 17.277695] r/libexec/bootrr + sh helpers/bootrr-auto /lava-11440308/1/../bin/lava-test-case /lava-11440308/1/../bin/lava-test-case <8>[ 17.296428] /usr/bin/tpm2_getcap /lava-11440308/1/../bin/lava-test-case <8>[ 17.343143] /lava-11440308/1/../bin/lava-test-case <8>[ 17.369473] /lava-11440308/1/../bin/lava-test-case <8>[ 17.386665] /lava-11440308/1/../bin/lava-test-case <8>[ 17.407078] /lava-11440308/1/../bin/lava-test-case <8>[ 17.428678] /lava-11440308/1/../bin/lava-test-case <8>[ 17.445523] /lava-11440308/1/../bin/lava-test-case <8>[ 17.460929] /lava-11440308/1/../bin/lava-test-case <8>[ 17.479188] /lava-11440308/1/../bin/lava-tes<8>[ 17.495599] t-case /lava-11440308/1/../bin/lava-test-case <8>[ 17.513874] /lava-11440308/1/../bin/lava-tes<8>[ 17.531015] t-case /lava-11440308/1/../bin/lava-test-case <8>[ 17.550201] /lava-11440308/1/../bin/lava-test-case <8>[ 17.567688] /lava-11440308/1/../bin/lava-test-case <8>[ 17.583124] /lava-11440308/1/../bin/lava-test-case <8>[ 17.603060] /lava-11440308/1/../bin/lava-test-case <8>[ 17.619252] /lava-11440308/1/../bin/lava-test-case <8>[ 17.636797] /lava-11440308/1/../bin/lava-test-case <8>[ 17.652236] /lava-11440308/1/../bin/lava-test-case <8>[ 17.669357] /lava-11440308/1/../bin/lava-test-case <8>[ 17.684403] /lava-11440308/1/../bin/lava-test-case <8>[ 17.703207] /lava-11440308/1/../bin/lava-test-case <8>[ 17.719669] /lava-11440308/1/../bin/lava-test-case <8>[ 17.737460] /lava-11440308/1/../bin/lava-test-case <8>[ 17.753995] /lava-11440308/1/../bin/lava-test-case <8>[ 17.772075] /lava-11440308/1/../bin/lava-test-case <8>[ 17.790068] /lava-11440308/1/../bin/lava-test-case <8>[ 17.805716] /lava-11440308/1/../bin/lava-test-case <8>[ 17.823114] /lava-11440308/1/../bin/lava-test-case <8>[ 17.840215] /lava-11440308/1/../bin/lava-test-case <8>[ 17.857303] /lava-11440308/1/../bin/lava-test-case <8>[ 17.877051] /lava-11440308/1/../bin/lava-test-case <8>[ 17.892813] /lava-11440308/1/../bin/lava-test-case <8>[ 17.910205] /lava-11440308/1/../bin/lava-test-case <8>[ 17.926568] /lava-11440308/1/../bin/lava-test-case <8>[ 17.942095] /lava-11440308/1/../bin/lava-test-case <8>[ 17.960411] /lava-11440308/1/../bin/lava-test-case <8>[ 17.976934] /lava-11440308/1/../bin/lava-tes<8>[ 17.994558] t-case /lava-11440308/1/../bin/lava-test-case <8>[ 18.012919] /lava-11440308/1/../bin/lava-test-case <8>[ 18.032274] /lava-11440308/1/../bin/lava-test-case <8>[ 18.047620] /lava-11440308/1/../bin/lava-test-case <8>[ 18.065483] /lava-11440308/1/../bin/lava-tes<8>[ 18.081263] t-case /lava-11440308/1/../bin/lava-tes<8>[ 18.101976] t-case /lava-11440308/1/../bin/lava-test-case <8>[ 18.116483] /lava-11440308/1/../bin/lava-test-case <8>[ 18.134825] /lava-11440308/1/../bin/lava-test-case <8>[ 18.149366] /lava-11440308/1/../bin/lava-test-case <8>[ 18.166795] /lava-11440308/1/../bin/lava-tes<8>[ 18.183335] t-case /lava-11440308/1/../bin/lava-test-case <8>[ 18.201516] /lava-11440308/1/../bin/lava-test-case <8>[ 18.220266] /lava-11440308/1/../bin/lava-test-case <8>[ 18.235587] /lava-11440308/1/../bin/lava-tes<8>[ 18.252324] t-case /lava-11440308/1/../bin/lava-test-case <8>[ 18.270062] /lava-11440308/1/../bin/lava-test-case <8>[ 18.286491] /lava-11440308/1/../bin/lava-test-case <8>[ 18.305285] /lava-11440308/1/../bin/lava-test-case <8>[ 18.321815] /lava-11440308/1/../bin/lava-test-case <8>[ 18.335654] /lava-11440308/1/../bin/lava-test-case <8>[ 18.356464] /lava-11440308/1/../bin/lava-test-case <8>[ 18.375277] /lava-11440308/1/../bin/lava-test-case <8>[ 18.389542] /lava-11440308/1/../bin/lava-test-case <8>[ 18.410038] /lava-11440308/1/../bin/lava-test-case <8>[ 18.425154] /lava-11440308/1/../bin/lava-test-case <8>[ 18.444276] /lava-11440308/1/../bin/lava-test-case <8>[ 18.459275] /lava-11440308/1/../bin/lava-test-case <8>[ 18.476566] /lava-11440308/1/../bin/lava-test-case <8>[ 18.493271] /lava-11440308/1/../bin/lava-test-case <8>[ 18.509762] /lava-11440308/1/../bin/lava-test-case <8>[ 18.526205] /lava-11440308/1/../bin/lava-test-case <8>[ 18.543857] /lava-11440308/1/../bin/lava-test-case <8>[ 18.560473] /lava-11440308/1/../bin/lava-test-case <8>[ 18.577212] /lava-11440308/1/../bin/lava-test-case <8>[ 18.593970] /lava-11440308/1/../bin/lava-test-case <8>[ 18.610640] /lava-11440308/1/../bin/lava-test-case <8>[ 18.627363] /lava-11440308/1/../bin/lava-test-case <8>[ 18.643576] /lava-11440308/1/../bin/lava-test-case <8>[ 18.660394] /lava-11440308/1/../bin/lava-tes<8>[ 18.677297] t-case /lava-11440308/1/../bin/lava-tes<8>[ 18.694216] t-case /lava-11440308/1/../bin/lava-test-case <8>[ 18.714701] /lava-11440308/1/../bin/lava-test-case <8>[ 18.730940] /lava-11440308/1/../bin/lava-test-case <8>[ 18.747963] /lava-11440308/1/../bin/lava-test-case <8>[ 18.762925] /lava-11440308/1/../bin/lava-test-case <8>[ 18.781493] /lava-11440308/1/../bin/lava-test-case <8>[ 18.795361] /lava-11440308/1/../bin/lava-test-case <8>[ 18.814463] /lava-11440308/1/../bin/lava-test-case <8>[ 18.829938] /lava-11440308/1/../bin/lava-test-case <8>[ 18.846026] /lava-11440308/1/../bin/lava-tes<8>[ 18.861074] t-case /lava-11440308/1/../bin/lava-tes<8>[ 18.882263] t-case /lava-11440308/1/../bin/lava-test-case <8>[ 18.897134] /lava-11440308/1/../bin/lava-test-case <8>[ 18.914550] /lava-11440308/1/../bin/lava-test-case <8>[ 18.932360] /lava-11440308/1/../bin/lava-test-case <8>[ 18.947906] /lava-11440308/1/../bin/lava-test-case <8>[ 18.965283] /lava-11440308/1/../bin/lava-test-case <8>[ 18.980565] /lava-11440308/1/../bin/lava-test-case <8>[ 18.998872] /lava-11440308/1/../bin/lava-test-case <8>[ 19.013690] /lava-11440308/1/../bin/lava-test-case <8>[ 20.032273] /lava-11440308/1/../bin/lava-test-case <8>[ 20.051923] /lava-11440308/1/../bin/lava-test-case <8>[ 21.070000] /lava-11440308/1/../bin/lava-test-case <8>[ 21.088731] /lava-11440308/1/../bin/lava-test-case <8>[ 22.107320] /lava-11440308/1/../bin/lava-test-case <8>[ 22.125042] /lava-11440308/1/../bin/lava-test-case <8>[ 23.149532] /lava-11440308/1/../bin/lava-test-case <8>[ 23.164385] /lava-11440308/1/../bin/lava-test-case <8>[ 24.184314] /lava-11440308/1/../bin/lava-test-case <8>[ 24.200752] /lava-11440308/1/../bin/lava-test-case <8>[ 25.225549] /lava-11440308/1/../bin/lava-test-case <8>[ 25.240838] /lava-11440308/1/../bin/lava-test-case <8>[ 26.259983] /lava-11440308/1/../bin/lava-test-case <8>[ 26.278147] /lava-11440308/1/../bin/lava-test-case <8>[ 26.294592] /lava-11440308/1/../bin/lava-test-case <8>[ 27.313380] /lava-11440308/1/../bin/lava-test-case <8>[ 27.331155] /lava-11440308/1/../bin/lava-tes<8>[ 27.347179] t-case /lava-11440308/1/../bin/lava-test-case <8>[ 27.362849] /lava-11440308/1/../bin/lava-test-case <8>[ 27.380639] /lava-11440308/1/../bin/lava-test-case <8>[ 27.398855] /lava-11440308/1/../bin/lava-test-case <8>[ 27.416046] /lava-11440308/1/../bin/lava-test-case <8>[ 27.431853] /lava-11440308/1/../bin/lava-test-case <8>[ 27.452508] /lava-11440308/1/../bin/lava-test-case <8>[ 27.471769] /lava-11440308/1/../bin/lava-test-case <8>[ 27.487381] /lava-11440308/1/../bin/lava-test-case <8>[ 27.505193] /lava-11440308/1/../bin/lava-tes<8>[ 27.520280] t-case /lava-11440308/1/../bin/lava-test-case <8>[ 27.538964] /lava-11440308/1/../bin/lava-test-case <8>[ 27.555637] /lava-11440308/1/../bin/lava-test-case <8>[ 27.573563] /lava-11440308/1/../bin/lava-test-case <8>[ 27.588222] /lava-11440308/1/../bin/lava-test-case <8>[ 27.609541] /lava-11440308/1/../bin/lava-test-case <8>[ 27.625541] /lava-11440308/1/../bin/lava-test-case <8>[ 27.643156] /lava-11440308/1/../bin/lava-test-case <8>[ 27.658141] /lava-11440308/1/../bin/lava-test-case <8>[ 28.682425] /lava-11440308/1/../bin/lava-test-case <8>[ 29.700950] /lava-11440308/1/../bin/lava-test-case <8>[ 29.717958] /lava-11440308/1/../bin/lava-test-case <8>[ 29.735046] /lava-11440308/1/../bin/lava-test-case <8>[ 29.749048] /lava-11440308/1/../bin/lava-test-case <8>[ 29.767348] /lava-11440308/1/../bin/lava-test-case <8>[ 29.782143] /lava-11440308/1/../bin/lava-test-case <8>[ 29.798608] /lava-11440308/1/../bin/lava-test-case <8>[ 29.813384] /lava-11440308/1/../bin/lava-test-case <8>[ 29.832135] /lava-11440308/1/../bin/lava-test-case <8>[ 29.848069] /lava-11440308/1/../bin/lava-test-case <8>[ 29.868178] /lava-11440308/1/../bin/lava-test-case <8>[ 29.882831] /lava-11440308/1/../bin/lava-test-case <8>[ 29.900005] /lava-11440308/1/../bin/lava-test-case <8>[ 29.914247] /lava-11440308/1/../bin/lava-test-case <8>[ 29.931623] /lava-11440308/1/../bin/lava-tes<8>[ 29.945424] t-case /lava-11440308/1/../bin/lava-tes<8>[ 29.963183] t-case /lava-11440308/1/../bin/lava-tes<8>[ 29.978246] t-case /lava-11440308/1/../bin/lava-test-case <8>[ 29.996622] /lava-11440308/1/../bin/lava-test-case <8>[ 30.012930] /lava-11440308/1/../bin/lava-test-case <8>[ 30.033189] /lava-11440308/1/../bin/lava-test-case <8>[ 31.051589] /lava-11440308/1/../bin/lava-test-case <8>[ 32.068913] /lava-11440308/1/../bin/lava-test-case <8>[ 32.085938] /lava-11440308/1/../bin/lava-test-case <8>[ 33.104617] /lava-11440308/1/../bin/lava-test-case <8>[ 33.124389] /lava-11440308/1/../bin/lava-test-case <8>[ 33.141336] /lava-11440308/1/../bin/lava-test-case <8>[ 33.157553] /lava-11440308/1/../bin/lava-test-case <8>[ 33.171363] /lava-11440308/1/../bin/lava-test-case <8>[ 33.193010] /lava-11440308/1/../bin/lava-test-case <8>[ 33.208677] /lava-11440308/1/../bin/lava-test-case <8>[ 34.227287] /lava-11440308/1/../bin/lava-test-case <8>[ 34.246079] /lava-11440308/1/../bin/lava-test-case <8>[ 35.264268] /lava-11440308/1/../bin/lava-test-case <8>[ 35.283865] /lava-11440308/1/../bin/lava-test-case <8>[ 36.301854] /lava-11440308/1/../bin/lava-test-case <8>[ 36.320364] /lava-11440308/1/../bin/lava-test-case <8>[ 37.339986] /lava-11440308/1/../bin/lava-test-case <8>[ 37.358037] /lava-11440308/1/../bin/lava-test-case <8>[ 37.374871] /lava-11440308/1/../bin/lava-test-case <8>[ 37.390789] /lava-11440308/1/../bin/lava-test-case <8>[ 37.404557] /lava-11440308/1/../bin/lava-tes<8>[ 37.422153] t-case /lava-11440308/1/../bin/lava-tes<8>[ 37.438014] t-case /lava-11440308/1/../bin/lava-test-case <8>[ 37.454619] /lava-11440308/1/../bin/lava-test-case <8>[ 37.470700] /lava-11440308/1/../bin/lava-test-case <8>[ 37.487369] + set +x <8>[ 37.497458] / #