Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 27
1 22:09:31.367448 lava-dispatcher, installed at version: 2023.06
2 22:09:31.367651 start: 0 validate
3 22:09:31.367786 Start time: 2023-09-05 22:09:31.367777+00:00 (UTC)
4 22:09:31.367923 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:09:31.368065 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 22:09:31.636414 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:09:31.636634 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:09:43.394337 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:09:43.394512 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:09:43.653346 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:09:43.653510 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:09:44.173612 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:09:44.173775 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:09:46.674926 validate duration: 15.31
16 22:09:46.675194 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:09:46.675295 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:09:46.675382 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:09:46.675507 Not decompressing ramdisk as can be used compressed.
20 22:09:46.675593 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 22:09:46.675656 saving as /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/ramdisk/initrd.cpio.gz
22 22:09:46.675719 total size: 4665412 (4 MB)
23 22:09:46.933268 progress 0 % (0 MB)
24 22:09:46.934697 progress 5 % (0 MB)
25 22:09:46.935973 progress 10 % (0 MB)
26 22:09:46.937268 progress 15 % (0 MB)
27 22:09:46.938547 progress 20 % (0 MB)
28 22:09:46.939768 progress 25 % (1 MB)
29 22:09:46.941124 progress 30 % (1 MB)
30 22:09:46.942335 progress 35 % (1 MB)
31 22:09:46.943687 progress 40 % (1 MB)
32 22:09:46.945115 progress 45 % (2 MB)
33 22:09:46.946333 progress 50 % (2 MB)
34 22:09:46.947646 progress 55 % (2 MB)
35 22:09:46.948961 progress 60 % (2 MB)
36 22:09:46.950204 progress 65 % (2 MB)
37 22:09:46.951473 progress 70 % (3 MB)
38 22:09:46.952718 progress 75 % (3 MB)
39 22:09:46.953981 progress 80 % (3 MB)
40 22:09:46.955398 progress 85 % (3 MB)
41 22:09:46.956725 progress 90 % (4 MB)
42 22:09:46.957964 progress 95 % (4 MB)
43 22:09:46.959203 progress 100 % (4 MB)
44 22:09:46.959371 4 MB downloaded in 0.28 s (15.69 MB/s)
45 22:09:46.959543 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:09:46.959812 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:09:46.959917 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:09:46.960019 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:09:46.960169 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:09:46.960268 saving as /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/kernel/Image
52 22:09:46.960367 total size: 49220096 (46 MB)
53 22:09:46.960467 No compression specified
54 22:09:46.962138 progress 0 % (0 MB)
55 22:09:46.975156 progress 5 % (2 MB)
56 22:09:46.987741 progress 10 % (4 MB)
57 22:09:47.000218 progress 15 % (7 MB)
58 22:09:47.012887 progress 20 % (9 MB)
59 22:09:47.025326 progress 25 % (11 MB)
60 22:09:47.037743 progress 30 % (14 MB)
61 22:09:47.050549 progress 35 % (16 MB)
62 22:09:47.063402 progress 40 % (18 MB)
63 22:09:47.076310 progress 45 % (21 MB)
64 22:09:47.089218 progress 50 % (23 MB)
65 22:09:47.101777 progress 55 % (25 MB)
66 22:09:47.114285 progress 60 % (28 MB)
67 22:09:47.126726 progress 65 % (30 MB)
68 22:09:47.139215 progress 70 % (32 MB)
69 22:09:47.151666 progress 75 % (35 MB)
70 22:09:47.164582 progress 80 % (37 MB)
71 22:09:47.177978 progress 85 % (39 MB)
72 22:09:47.190635 progress 90 % (42 MB)
73 22:09:47.203007 progress 95 % (44 MB)
74 22:09:47.215584 progress 100 % (46 MB)
75 22:09:47.215745 46 MB downloaded in 0.26 s (183.81 MB/s)
76 22:09:47.215920 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:09:47.216185 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:09:47.216291 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:09:47.216396 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:09:47.216552 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:09:47.216653 saving as /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/dtb/mt8192-asurada-spherion-r0.dtb
83 22:09:47.216779 total size: 47278 (0 MB)
84 22:09:47.216896 No compression specified
85 22:09:47.218581 progress 69 % (0 MB)
86 22:09:47.218886 progress 100 % (0 MB)
87 22:09:47.219078 0 MB downloaded in 0.00 s (19.63 MB/s)
88 22:09:47.219219 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:09:47.219474 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:09:47.219621 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:09:47.219760 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:09:47.219912 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 22:09:47.220011 saving as /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/nfsrootfs/full.rootfs.tar
95 22:09:47.220110 total size: 125290964 (119 MB)
96 22:09:47.220210 Using unxz to decompress xz
97 22:09:47.224241 progress 0 % (0 MB)
98 22:09:47.550552 progress 5 % (6 MB)
99 22:09:47.883493 progress 10 % (11 MB)
100 22:09:48.212683 progress 15 % (17 MB)
101 22:09:48.398091 progress 20 % (23 MB)
102 22:09:48.581117 progress 25 % (29 MB)
103 22:09:48.929547 progress 30 % (35 MB)
104 22:09:49.283646 progress 35 % (41 MB)
105 22:09:49.665604 progress 40 % (47 MB)
106 22:09:50.057247 progress 45 % (53 MB)
107 22:09:50.448649 progress 50 % (59 MB)
108 22:09:50.795932 progress 55 % (65 MB)
109 22:09:51.156158 progress 60 % (71 MB)
110 22:09:51.491965 progress 65 % (77 MB)
111 22:09:51.854328 progress 70 % (83 MB)
112 22:09:52.232350 progress 75 % (89 MB)
113 22:09:52.649302 progress 80 % (95 MB)
114 22:09:53.060863 progress 85 % (101 MB)
115 22:09:53.308869 progress 90 % (107 MB)
116 22:09:53.647785 progress 95 % (113 MB)
117 22:09:54.023275 progress 100 % (119 MB)
118 22:09:54.031092 119 MB downloaded in 6.81 s (17.54 MB/s)
119 22:09:54.031452 end: 1.4.1 http-download (duration 00:00:07) [common]
121 22:09:54.031718 end: 1.4 download-retry (duration 00:00:07) [common]
122 22:09:54.031809 start: 1.5 download-retry (timeout 00:09:53) [common]
123 22:09:54.031899 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 22:09:54.032051 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:09:54.032122 saving as /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/modules/modules.tar
126 22:09:54.032183 total size: 8619808 (8 MB)
127 22:09:54.032248 Using unxz to decompress xz
128 22:09:54.300154 progress 0 % (0 MB)
129 22:09:54.328800 progress 5 % (0 MB)
130 22:09:54.354439 progress 10 % (0 MB)
131 22:09:54.381351 progress 15 % (1 MB)
132 22:09:54.408320 progress 20 % (1 MB)
133 22:09:54.434766 progress 25 % (2 MB)
134 22:09:54.461759 progress 30 % (2 MB)
135 22:09:54.489701 progress 35 % (2 MB)
136 22:09:54.514719 progress 40 % (3 MB)
137 22:09:54.539393 progress 45 % (3 MB)
138 22:09:54.565925 progress 50 % (4 MB)
139 22:09:54.591839 progress 55 % (4 MB)
140 22:09:54.616673 progress 60 % (4 MB)
141 22:09:54.639849 progress 65 % (5 MB)
142 22:09:54.667326 progress 70 % (5 MB)
143 22:09:54.693176 progress 75 % (6 MB)
144 22:09:54.719416 progress 80 % (6 MB)
145 22:09:54.748865 progress 85 % (7 MB)
146 22:09:54.775633 progress 90 % (7 MB)
147 22:09:54.801225 progress 95 % (7 MB)
148 22:09:54.826856 progress 100 % (8 MB)
149 22:09:54.831448 8 MB downloaded in 0.80 s (10.29 MB/s)
150 22:09:54.831722 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:09:54.831992 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:09:54.832086 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 22:09:54.832186 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 22:09:56.818536 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11440304/extract-nfsrootfs-i13_qaj1
156 22:09:56.818752 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 22:09:56.818859 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 22:09:56.819035 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2
159 22:09:56.819161 makedir: /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin
160 22:09:56.819280 makedir: /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/tests
161 22:09:56.819437 makedir: /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/results
162 22:09:56.819543 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-add-keys
163 22:09:56.819690 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-add-sources
164 22:09:56.819819 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-background-process-start
165 22:09:56.819947 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-background-process-stop
166 22:09:56.820074 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-common-functions
167 22:09:56.820211 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-echo-ipv4
168 22:09:56.820333 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-install-packages
169 22:09:56.820454 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-installed-packages
170 22:09:56.820573 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-os-build
171 22:09:56.820694 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-probe-channel
172 22:09:56.820855 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-probe-ip
173 22:09:56.820979 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-target-ip
174 22:09:56.821100 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-target-mac
175 22:09:56.821220 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-target-storage
176 22:09:56.821344 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-test-case
177 22:09:56.821469 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-test-event
178 22:09:56.821590 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-test-feedback
179 22:09:56.821714 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-test-raise
180 22:09:56.821833 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-test-reference
181 22:09:56.821956 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-test-runner
182 22:09:56.822077 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-test-set
183 22:09:56.822226 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-test-shell
184 22:09:56.822348 Updating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-install-packages (oe)
185 22:09:56.822500 Updating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/bin/lava-installed-packages (oe)
186 22:09:56.822659 Creating /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/environment
187 22:09:56.822754 LAVA metadata
188 22:09:56.822847 - LAVA_JOB_ID=11440304
189 22:09:56.822926 - LAVA_DISPATCHER_IP=192.168.201.1
190 22:09:56.823030 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 22:09:56.823099 skipped lava-vland-overlay
192 22:09:56.823176 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 22:09:56.823257 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 22:09:56.823319 skipped lava-multinode-overlay
195 22:09:56.823392 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 22:09:56.823474 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 22:09:56.823549 Loading test definitions
198 22:09:56.823638 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 22:09:56.823710 Using /lava-11440304 at stage 0
200 22:09:56.824004 uuid=11440304_1.6.2.3.1 testdef=None
201 22:09:56.824096 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 22:09:56.824182 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 22:09:56.824678 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 22:09:56.824938 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 22:09:56.825577 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 22:09:56.825810 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 22:09:56.826420 runner path: /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/0/tests/0_dmesg test_uuid 11440304_1.6.2.3.1
210 22:09:56.826574 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 22:09:56.826802 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 22:09:56.826875 Using /lava-11440304 at stage 1
214 22:09:56.827172 uuid=11440304_1.6.2.3.5 testdef=None
215 22:09:56.827278 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 22:09:56.827379 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 22:09:56.827834 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 22:09:56.828053 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 22:09:56.828686 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 22:09:56.828951 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 22:09:56.829687 runner path: /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/1/tests/1_bootrr test_uuid 11440304_1.6.2.3.5
224 22:09:56.829838 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 22:09:56.830046 Creating lava-test-runner.conf files
227 22:09:56.830110 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/0 for stage 0
228 22:09:56.830199 - 0_dmesg
229 22:09:56.830279 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11440304/lava-overlay-jvcbuwl2/lava-11440304/1 for stage 1
230 22:09:56.830368 - 1_bootrr
231 22:09:56.830464 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 22:09:56.830551 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 22:09:56.838357 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 22:09:56.838498 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 22:09:56.838594 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 22:09:56.838685 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 22:09:56.838773 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 22:09:56.952739 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 22:09:56.953142 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 22:09:56.953263 extracting modules file /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11440304/extract-nfsrootfs-i13_qaj1
241 22:09:57.156835 extracting modules file /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11440304/extract-overlay-ramdisk-kl_c5k4i/ramdisk
242 22:09:57.368022 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 22:09:57.368233 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 22:09:57.368327 [common] Applying overlay to NFS
245 22:09:57.368399 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11440304/compress-overlay-kl9crc0p/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11440304/extract-nfsrootfs-i13_qaj1
246 22:09:57.376410 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 22:09:57.376557 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 22:09:57.376651 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 22:09:57.376742 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 22:09:57.376860 Building ramdisk /var/lib/lava/dispatcher/tmp/11440304/extract-overlay-ramdisk-kl_c5k4i/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11440304/extract-overlay-ramdisk-kl_c5k4i/ramdisk
251 22:09:57.679145 >> 119255 blocks
252 22:09:59.640922 rename /var/lib/lava/dispatcher/tmp/11440304/extract-overlay-ramdisk-kl_c5k4i/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/ramdisk/ramdisk.cpio.gz
253 22:09:59.641406 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 22:09:59.641570 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 22:09:59.641710 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 22:09:59.641869 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/kernel/Image'
257 22:10:12.077424 Returned 0 in 12 seconds
258 22:10:12.178187 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/kernel/image.itb
259 22:10:12.515676 output: FIT description: Kernel Image image with one or more FDT blobs
260 22:10:12.516037 output: Created: Tue Sep 5 23:10:12 2023
261 22:10:12.516126 output: Image 0 (kernel-1)
262 22:10:12.516223 output: Description:
263 22:10:12.516316 output: Created: Tue Sep 5 23:10:12 2023
264 22:10:12.516424 output: Type: Kernel Image
265 22:10:12.516487 output: Compression: lzma compressed
266 22:10:12.516548 output: Data Size: 11037994 Bytes = 10779.29 KiB = 10.53 MiB
267 22:10:12.516611 output: Architecture: AArch64
268 22:10:12.516672 output: OS: Linux
269 22:10:12.516733 output: Load Address: 0x00000000
270 22:10:12.516815 output: Entry Point: 0x00000000
271 22:10:12.516870 output: Hash algo: crc32
272 22:10:12.516924 output: Hash value: 9d08b3de
273 22:10:12.516978 output: Image 1 (fdt-1)
274 22:10:12.517031 output: Description: mt8192-asurada-spherion-r0
275 22:10:12.517085 output: Created: Tue Sep 5 23:10:12 2023
276 22:10:12.517139 output: Type: Flat Device Tree
277 22:10:12.517222 output: Compression: uncompressed
278 22:10:12.517276 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 22:10:12.517330 output: Architecture: AArch64
280 22:10:12.517413 output: Hash algo: crc32
281 22:10:12.517497 output: Hash value: cc4352de
282 22:10:12.517550 output: Image 2 (ramdisk-1)
283 22:10:12.517628 output: Description: unavailable
284 22:10:12.517696 output: Created: Tue Sep 5 23:10:12 2023
285 22:10:12.517749 output: Type: RAMDisk Image
286 22:10:12.517802 output: Compression: Unknown Compression
287 22:10:12.517870 output: Data Size: 17784206 Bytes = 17367.39 KiB = 16.96 MiB
288 22:10:12.517938 output: Architecture: AArch64
289 22:10:12.517991 output: OS: Linux
290 22:10:12.518073 output: Load Address: unavailable
291 22:10:12.518127 output: Entry Point: unavailable
292 22:10:12.518208 output: Hash algo: crc32
293 22:10:12.518261 output: Hash value: af0526c4
294 22:10:12.518314 output: Default Configuration: 'conf-1'
295 22:10:12.518366 output: Configuration 0 (conf-1)
296 22:10:12.518419 output: Description: mt8192-asurada-spherion-r0
297 22:10:12.518472 output: Kernel: kernel-1
298 22:10:12.518525 output: Init Ramdisk: ramdisk-1
299 22:10:12.518577 output: FDT: fdt-1
300 22:10:12.518660 output: Loadables: kernel-1
301 22:10:12.518713 output:
302 22:10:12.518902 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 22:10:12.519067 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 22:10:12.519202 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 22:10:12.519296 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
306 22:10:12.519409 No LXC device requested
307 22:10:12.519488 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 22:10:12.519608 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
309 22:10:12.519687 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 22:10:12.519790 Checking files for TFTP limit of 4294967296 bytes.
311 22:10:12.520336 end: 1 tftp-deploy (duration 00:00:26) [common]
312 22:10:12.520445 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 22:10:12.520536 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 22:10:12.520703 substitutions:
315 22:10:12.520794 - {DTB}: 11440304/tftp-deploy-fbu5alh4/dtb/mt8192-asurada-spherion-r0.dtb
316 22:10:12.520860 - {INITRD}: 11440304/tftp-deploy-fbu5alh4/ramdisk/ramdisk.cpio.gz
317 22:10:12.520920 - {KERNEL}: 11440304/tftp-deploy-fbu5alh4/kernel/Image
318 22:10:12.520979 - {LAVA_MAC}: None
319 22:10:12.521035 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11440304/extract-nfsrootfs-i13_qaj1
320 22:10:12.521139 - {NFS_SERVER_IP}: 192.168.201.1
321 22:10:12.521208 - {PRESEED_CONFIG}: None
322 22:10:12.521263 - {PRESEED_LOCAL}: None
323 22:10:12.521317 - {RAMDISK}: 11440304/tftp-deploy-fbu5alh4/ramdisk/ramdisk.cpio.gz
324 22:10:12.521372 - {ROOT_PART}: None
325 22:10:12.521425 - {ROOT}: None
326 22:10:12.521511 - {SERVER_IP}: 192.168.201.1
327 22:10:12.521564 - {TEE}: None
328 22:10:12.521618 Parsed boot commands:
329 22:10:12.521701 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 22:10:12.521876 Parsed boot commands: tftpboot 192.168.201.1 11440304/tftp-deploy-fbu5alh4/kernel/image.itb 11440304/tftp-deploy-fbu5alh4/kernel/cmdline
331 22:10:12.521966 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 22:10:12.522054 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 22:10:12.522145 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 22:10:12.522228 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 22:10:12.522301 Not connected, no need to disconnect.
336 22:10:12.522404 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 22:10:12.522485 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 22:10:12.522552 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
339 22:10:12.526124 Setting prompt string to ['lava-test: # ']
340 22:10:12.526487 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 22:10:12.526660 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 22:10:12.526775 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 22:10:12.526935 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 22:10:12.527174 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
345 22:10:17.663774 >> Command sent successfully.
346 22:10:17.667149 Returned 0 in 5 seconds
347 22:10:17.767562 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 22:10:17.767931 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 22:10:17.768048 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 22:10:17.768153 Setting prompt string to 'Starting depthcharge on Spherion...'
352 22:10:17.768247 Changing prompt to 'Starting depthcharge on Spherion...'
353 22:10:17.768378 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 22:10:17.768844 [Enter `^Ec?' for help]
355 22:10:17.943181
356 22:10:17.943353
357 22:10:17.943449 F0: 102B 0000
358 22:10:17.943533
359 22:10:17.943614 F3: 1001 0000 [0200]
360 22:10:17.943693
361 22:10:17.947481 F3: 1001 0000
362 22:10:17.947570
363 22:10:17.947658 F7: 102D 0000
364 22:10:17.947740
365 22:10:17.947821 F1: 0000 0000
366 22:10:17.947899
367 22:10:17.950923 V0: 0000 0000 [0001]
368 22:10:17.951018
369 22:10:17.951105 00: 0007 8000
370 22:10:17.951189
371 22:10:17.954590 01: 0000 0000
372 22:10:17.954679
373 22:10:17.954765 BP: 0C00 0209 [0000]
374 22:10:17.954897
375 22:10:17.955009 G0: 1182 0000
376 22:10:17.955149
377 22:10:17.958484 EC: 0000 0021 [4000]
378 22:10:17.958573
379 22:10:17.958675 S7: 0000 0000 [0000]
380 22:10:17.962085
381 22:10:17.962170 CC: 0000 0000 [0001]
382 22:10:17.962256
383 22:10:17.962338 T0: 0000 0040 [010F]
384 22:10:17.965252
385 22:10:17.965337 Jump to BL
386 22:10:17.965424
387 22:10:17.990159
388 22:10:17.990284
389 22:10:17.990414
390 22:10:17.997374 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 22:10:18.000934 ARM64: Exception handlers installed.
392 22:10:18.005078 ARM64: Testing exception
393 22:10:18.008560 ARM64: Done test exception
394 22:10:18.015771 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 22:10:18.022594 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 22:10:18.029698 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 22:10:18.040675 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 22:10:18.047447 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 22:10:18.057757 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 22:10:18.067971 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 22:10:18.074782 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 22:10:18.092850 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 22:10:18.096074 WDT: Last reset was cold boot
404 22:10:18.099417 SPI1(PAD0) initialized at 2873684 Hz
405 22:10:18.102697 SPI5(PAD0) initialized at 992727 Hz
406 22:10:18.106148 VBOOT: Loading verstage.
407 22:10:18.112541 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 22:10:18.116124 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 22:10:18.119404 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 22:10:18.122738 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 22:10:18.130156 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 22:10:18.136810 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 22:10:18.147757 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 22:10:18.147844
415 22:10:18.147913
416 22:10:18.157687 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 22:10:18.161344 ARM64: Exception handlers installed.
418 22:10:18.164230 ARM64: Testing exception
419 22:10:18.164316 ARM64: Done test exception
420 22:10:18.170982 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 22:10:18.174485 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:10:18.188927 Probing TPM: . done!
423 22:10:18.189014 TPM ready after 0 ms
424 22:10:18.195312 Connected to device vid:did:rid of 1ae0:0028:00
425 22:10:18.202908 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 22:10:18.260394 Initialized TPM device CR50 revision 0
427 22:10:18.271591 tlcl_send_startup: Startup return code is 0
428 22:10:18.271691 TPM: setup succeeded
429 22:10:18.283137 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 22:10:18.291752 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 22:10:18.302040 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 22:10:18.311435 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 22:10:18.314885 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 22:10:18.322532 in-header: 03 07 00 00 08 00 00 00
435 22:10:18.326971 in-data: aa e4 47 04 13 02 00 00
436 22:10:18.330306 Chrome EC: UHEPI supported
437 22:10:18.337242 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 22:10:18.341289 in-header: 03 ad 00 00 08 00 00 00
439 22:10:18.345188 in-data: 00 20 20 08 00 00 00 00
440 22:10:18.345272 Phase 1
441 22:10:18.348657 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 22:10:18.355812 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 22:10:18.360043 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 22:10:18.363597 Recovery requested (1009000e)
445 22:10:18.371690 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 22:10:18.377177 tlcl_extend: response is 0
447 22:10:18.386540 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 22:10:18.392192 tlcl_extend: response is 0
449 22:10:18.398790 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 22:10:18.419129 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 22:10:18.426812 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 22:10:18.426915
453 22:10:18.427014
454 22:10:18.436382 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 22:10:18.439688 ARM64: Exception handlers installed.
456 22:10:18.439788 ARM64: Testing exception
457 22:10:18.443410 ARM64: Done test exception
458 22:10:18.464924 pmic_efuse_setting: Set efuses in 11 msecs
459 22:10:18.468004 pmwrap_interface_init: Select PMIF_VLD_RDY
460 22:10:18.474711 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 22:10:18.478344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 22:10:18.481950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 22:10:18.488403 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 22:10:18.491864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 22:10:18.499355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 22:10:18.502595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 22:10:18.506485 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 22:10:18.510314 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 22:10:18.517848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 22:10:18.521623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 22:10:18.525984 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 22:10:18.528930 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 22:10:18.536032 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 22:10:18.542430 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 22:10:18.549712 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 22:10:18.553437 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 22:10:18.560740 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 22:10:18.564976 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 22:10:18.571617 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 22:10:18.574945 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 22:10:18.581901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 22:10:18.588583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 22:10:18.592141 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 22:10:18.598941 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 22:10:18.605518 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 22:10:18.608789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 22:10:18.612337 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 22:10:18.619126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 22:10:18.622094 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 22:10:18.628614 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 22:10:18.631813 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 22:10:18.638598 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 22:10:18.641939 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 22:10:18.648841 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 22:10:18.652348 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 22:10:18.658593 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 22:10:18.662373 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 22:10:18.669063 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 22:10:18.671954 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 22:10:18.675683 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 22:10:18.682234 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 22:10:18.685564 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 22:10:18.689201 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 22:10:18.692342 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 22:10:18.699699 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 22:10:18.703610 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 22:10:18.707102 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 22:10:18.710755 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 22:10:18.714425 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 22:10:18.718311 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 22:10:18.729228 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 22:10:18.736573 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 22:10:18.740155 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 22:10:18.747954 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 22:10:18.755398 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 22:10:18.762305 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 22:10:18.765507 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 22:10:18.768676 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 22:10:18.777050 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x4
520 22:10:18.784045 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 22:10:18.787124 [RTC]rtc_osc_init,62: osc32con val = 0xde70
522 22:10:18.790394 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 22:10:18.801461 [RTC]rtc_get_frequency_meter,154: input=15, output=771
524 22:10:18.811606 [RTC]rtc_get_frequency_meter,154: input=23, output=957
525 22:10:18.820875 [RTC]rtc_get_frequency_meter,154: input=19, output=864
526 22:10:18.830945 [RTC]rtc_get_frequency_meter,154: input=17, output=819
527 22:10:18.839944 [RTC]rtc_get_frequency_meter,154: input=16, output=795
528 22:10:18.843371 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
529 22:10:18.847175 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
530 22:10:18.853529 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
531 22:10:18.857007 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
532 22:10:18.860451 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
533 22:10:18.863596 ADC[4]: Raw value=903245 ID=7
534 22:10:18.867279 ADC[3]: Raw value=213179 ID=1
535 22:10:18.867400 RAM Code: 0x71
536 22:10:18.874111 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
537 22:10:18.876942 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
538 22:10:18.887362 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
539 22:10:18.894093 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
540 22:10:18.897392 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
541 22:10:18.900945 in-header: 03 07 00 00 08 00 00 00
542 22:10:18.904003 in-data: aa e4 47 04 13 02 00 00
543 22:10:18.904127 Chrome EC: UHEPI supported
544 22:10:18.910642 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
545 22:10:18.914002 in-header: 03 ed 00 00 08 00 00 00
546 22:10:18.917527 in-data: 80 20 60 08 00 00 00 00
547 22:10:18.920685 MRC: failed to locate region type 0.
548 22:10:18.927254 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
549 22:10:18.930750 DRAM-K: Running full calibration
550 22:10:18.937370 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
551 22:10:18.940426 header.status = 0x0
552 22:10:18.943900 header.version = 0x6 (expected: 0x6)
553 22:10:18.947240 header.size = 0xd00 (expected: 0xd00)
554 22:10:18.947360 header.flags = 0x0
555 22:10:18.953897 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
556 22:10:18.971528 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
557 22:10:18.978359 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
558 22:10:18.981563 dram_init: ddr_geometry: 2
559 22:10:18.985024 [EMI] MDL number = 2
560 22:10:18.985110 [EMI] Get MDL freq = 0
561 22:10:18.988014 dram_init: ddr_type: 0
562 22:10:18.988099 is_discrete_lpddr4: 1
563 22:10:18.992157 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
564 22:10:18.992266
565 22:10:18.992374
566 22:10:18.994992 [Bian_co] ETT version 0.0.0.1
567 22:10:19.001542 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
568 22:10:19.001623
569 22:10:19.004796 dramc_set_vcore_voltage set vcore to 650000
570 22:10:19.004920 Read voltage for 800, 4
571 22:10:19.008163 Vio18 = 0
572 22:10:19.008247 Vcore = 650000
573 22:10:19.008313 Vdram = 0
574 22:10:19.011868 Vddq = 0
575 22:10:19.011969 Vmddr = 0
576 22:10:19.014818 dram_init: config_dvfs: 1
577 22:10:19.018449 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
578 22:10:19.025170 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
579 22:10:19.028309 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
580 22:10:19.031775 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
581 22:10:19.035214 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
582 22:10:19.038394 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
583 22:10:19.041956 MEM_TYPE=3, freq_sel=18
584 22:10:19.045345 sv_algorithm_assistance_LP4_1600
585 22:10:19.048291 ============ PULL DRAM RESETB DOWN ============
586 22:10:19.051957 ========== PULL DRAM RESETB DOWN end =========
587 22:10:19.058481 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
588 22:10:19.062026 ===================================
589 22:10:19.062102 LPDDR4 DRAM CONFIGURATION
590 22:10:19.065187 ===================================
591 22:10:19.068427 EX_ROW_EN[0] = 0x0
592 22:10:19.071792 EX_ROW_EN[1] = 0x0
593 22:10:19.071885 LP4Y_EN = 0x0
594 22:10:19.075209 WORK_FSP = 0x0
595 22:10:19.075316 WL = 0x2
596 22:10:19.078941 RL = 0x2
597 22:10:19.079017 BL = 0x2
598 22:10:19.081870 RPST = 0x0
599 22:10:19.081973 RD_PRE = 0x0
600 22:10:19.085137 WR_PRE = 0x1
601 22:10:19.085210 WR_PST = 0x0
602 22:10:19.088579 DBI_WR = 0x0
603 22:10:19.088676 DBI_RD = 0x0
604 22:10:19.091928 OTF = 0x1
605 22:10:19.095306 ===================================
606 22:10:19.099100 ===================================
607 22:10:19.099201 ANA top config
608 22:10:19.102146 ===================================
609 22:10:19.105260 DLL_ASYNC_EN = 0
610 22:10:19.108609 ALL_SLAVE_EN = 1
611 22:10:19.108694 NEW_RANK_MODE = 1
612 22:10:19.111901 DLL_IDLE_MODE = 1
613 22:10:19.115401 LP45_APHY_COMB_EN = 1
614 22:10:19.118551 TX_ODT_DIS = 1
615 22:10:19.121991 NEW_8X_MODE = 1
616 22:10:19.125453 ===================================
617 22:10:19.128598 ===================================
618 22:10:19.128683 data_rate = 1600
619 22:10:19.132281 CKR = 1
620 22:10:19.135284 DQ_P2S_RATIO = 8
621 22:10:19.138798 ===================================
622 22:10:19.142091 CA_P2S_RATIO = 8
623 22:10:19.145414 DQ_CA_OPEN = 0
624 22:10:19.148717 DQ_SEMI_OPEN = 0
625 22:10:19.148807 CA_SEMI_OPEN = 0
626 22:10:19.151989 CA_FULL_RATE = 0
627 22:10:19.155329 DQ_CKDIV4_EN = 1
628 22:10:19.158745 CA_CKDIV4_EN = 1
629 22:10:19.162181 CA_PREDIV_EN = 0
630 22:10:19.162260 PH8_DLY = 0
631 22:10:19.165506 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
632 22:10:19.169117 DQ_AAMCK_DIV = 4
633 22:10:19.172617 CA_AAMCK_DIV = 4
634 22:10:19.175785 CA_ADMCK_DIV = 4
635 22:10:19.179241 DQ_TRACK_CA_EN = 0
636 22:10:19.179324 CA_PICK = 800
637 22:10:19.182261 CA_MCKIO = 800
638 22:10:19.185587 MCKIO_SEMI = 0
639 22:10:19.188665 PLL_FREQ = 3068
640 22:10:19.192387 DQ_UI_PI_RATIO = 32
641 22:10:19.195622 CA_UI_PI_RATIO = 0
642 22:10:19.199125 ===================================
643 22:10:19.202507 ===================================
644 22:10:19.202592 memory_type:LPDDR4
645 22:10:19.206568 GP_NUM : 10
646 22:10:19.206653 SRAM_EN : 1
647 22:10:19.209746 MD32_EN : 0
648 22:10:19.213697 ===================================
649 22:10:19.217122 [ANA_INIT] >>>>>>>>>>>>>>
650 22:10:19.217207 <<<<<< [CONFIGURE PHASE]: ANA_TX
651 22:10:19.221698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
652 22:10:19.224446 ===================================
653 22:10:19.228273 data_rate = 1600,PCW = 0X7600
654 22:10:19.231706 ===================================
655 22:10:19.235564 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
656 22:10:19.239723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
657 22:10:19.246746 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
658 22:10:19.249987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
659 22:10:19.254071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
660 22:10:19.257833 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
661 22:10:19.257920 [ANA_INIT] flow start
662 22:10:19.261139 [ANA_INIT] PLL >>>>>>>>
663 22:10:19.264641 [ANA_INIT] PLL <<<<<<<<
664 22:10:19.264727 [ANA_INIT] MIDPI >>>>>>>>
665 22:10:19.268168 [ANA_INIT] MIDPI <<<<<<<<
666 22:10:19.271778 [ANA_INIT] DLL >>>>>>>>
667 22:10:19.271863 [ANA_INIT] flow end
668 22:10:19.275212 ============ LP4 DIFF to SE enter ============
669 22:10:19.282484 ============ LP4 DIFF to SE exit ============
670 22:10:19.282569 [ANA_INIT] <<<<<<<<<<<<<
671 22:10:19.286430 [Flow] Enable top DCM control >>>>>
672 22:10:19.289755 [Flow] Enable top DCM control <<<<<
673 22:10:19.293447 Enable DLL master slave shuffle
674 22:10:19.297266 ==============================================================
675 22:10:19.301154 Gating Mode config
676 22:10:19.304775 ==============================================================
677 22:10:19.308450 Config description:
678 22:10:19.315911 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
679 22:10:19.323193 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
680 22:10:19.327229 SELPH_MODE 0: By rank 1: By Phase
681 22:10:19.334087 ==============================================================
682 22:10:19.338419 GAT_TRACK_EN = 1
683 22:10:19.341794 RX_GATING_MODE = 2
684 22:10:19.341924 RX_GATING_TRACK_MODE = 2
685 22:10:19.345440 SELPH_MODE = 1
686 22:10:19.349264 PICG_EARLY_EN = 1
687 22:10:19.353157 VALID_LAT_VALUE = 1
688 22:10:19.356600 ==============================================================
689 22:10:19.360254 Enter into Gating configuration >>>>
690 22:10:19.363967 Exit from Gating configuration <<<<
691 22:10:19.368042 Enter into DVFS_PRE_config >>>>>
692 22:10:19.378986 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
693 22:10:19.382383 Exit from DVFS_PRE_config <<<<<
694 22:10:19.386522 Enter into PICG configuration >>>>
695 22:10:19.386647 Exit from PICG configuration <<<<
696 22:10:19.389762 [RX_INPUT] configuration >>>>>
697 22:10:19.393640 [RX_INPUT] configuration <<<<<
698 22:10:19.397344 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
699 22:10:19.405282 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
700 22:10:19.409165 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
701 22:10:19.416568 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
702 22:10:19.423977 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
703 22:10:19.427580 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
704 22:10:19.433867 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
705 22:10:19.437402 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
706 22:10:19.440925 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
707 22:10:19.444411 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
708 22:10:19.448075 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
709 22:10:19.455207 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
710 22:10:19.458243 ===================================
711 22:10:19.458363 LPDDR4 DRAM CONFIGURATION
712 22:10:19.461732 ===================================
713 22:10:19.464868 EX_ROW_EN[0] = 0x0
714 22:10:19.464994 EX_ROW_EN[1] = 0x0
715 22:10:19.468083 LP4Y_EN = 0x0
716 22:10:19.468199 WORK_FSP = 0x0
717 22:10:19.471609 WL = 0x2
718 22:10:19.474895 RL = 0x2
719 22:10:19.474980 BL = 0x2
720 22:10:19.478235 RPST = 0x0
721 22:10:19.478319 RD_PRE = 0x0
722 22:10:19.481905 WR_PRE = 0x1
723 22:10:19.481991 WR_PST = 0x0
724 22:10:19.484850 DBI_WR = 0x0
725 22:10:19.484978 DBI_RD = 0x0
726 22:10:19.488174 OTF = 0x1
727 22:10:19.491617 ===================================
728 22:10:19.494956 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
729 22:10:19.498494 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
730 22:10:19.501627 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
731 22:10:19.504823 ===================================
732 22:10:19.508511 LPDDR4 DRAM CONFIGURATION
733 22:10:19.511525 ===================================
734 22:10:19.515016 EX_ROW_EN[0] = 0x10
735 22:10:19.515138 EX_ROW_EN[1] = 0x0
736 22:10:19.518358 LP4Y_EN = 0x0
737 22:10:19.518481 WORK_FSP = 0x0
738 22:10:19.521834 WL = 0x2
739 22:10:19.521955 RL = 0x2
740 22:10:19.525037 BL = 0x2
741 22:10:19.525161 RPST = 0x0
742 22:10:19.528517 RD_PRE = 0x0
743 22:10:19.528638 WR_PRE = 0x1
744 22:10:19.532020 WR_PST = 0x0
745 22:10:19.532143 DBI_WR = 0x0
746 22:10:19.535014 DBI_RD = 0x0
747 22:10:19.535142 OTF = 0x1
748 22:10:19.538512 ===================================
749 22:10:19.545335 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
750 22:10:19.550077 nWR fixed to 40
751 22:10:19.553070 [ModeRegInit_LP4] CH0 RK0
752 22:10:19.553155 [ModeRegInit_LP4] CH0 RK1
753 22:10:19.556913 [ModeRegInit_LP4] CH1 RK0
754 22:10:19.560025 [ModeRegInit_LP4] CH1 RK1
755 22:10:19.560142 match AC timing 13
756 22:10:19.566953 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
757 22:10:19.569764 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
758 22:10:19.573595 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
759 22:10:19.579957 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
760 22:10:19.583934 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
761 22:10:19.584020 [EMI DOE] emi_dcm 0
762 22:10:19.590247 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
763 22:10:19.590346 ==
764 22:10:19.593735 Dram Type= 6, Freq= 0, CH_0, rank 0
765 22:10:19.597219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
766 22:10:19.597305 ==
767 22:10:19.603781 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
768 22:10:19.606724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
769 22:10:19.617594 [CA 0] Center 38 (7~69) winsize 63
770 22:10:19.620928 [CA 1] Center 38 (7~69) winsize 63
771 22:10:19.624363 [CA 2] Center 35 (5~66) winsize 62
772 22:10:19.627656 [CA 3] Center 35 (5~66) winsize 62
773 22:10:19.631091 [CA 4] Center 34 (4~65) winsize 62
774 22:10:19.634511 [CA 5] Center 33 (3~64) winsize 62
775 22:10:19.634596
776 22:10:19.637521 [CmdBusTrainingLP45] Vref(ca) range 1: 32
777 22:10:19.637606
778 22:10:19.640937 [CATrainingPosCal] consider 1 rank data
779 22:10:19.644209 u2DelayCellTimex100 = 270/100 ps
780 22:10:19.647418 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
781 22:10:19.650799 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
782 22:10:19.657617 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
783 22:10:19.660970 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
784 22:10:19.664110 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
785 22:10:19.667886 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
786 22:10:19.667970
787 22:10:19.670860 CA PerBit enable=1, Macro0, CA PI delay=33
788 22:10:19.670945
789 22:10:19.674300 [CBTSetCACLKResult] CA Dly = 33
790 22:10:19.674385 CS Dly: 6 (0~37)
791 22:10:19.674452 ==
792 22:10:19.677658 Dram Type= 6, Freq= 0, CH_0, rank 1
793 22:10:19.684725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
794 22:10:19.684832 ==
795 22:10:19.688142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
796 22:10:19.695039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
797 22:10:19.704337 [CA 0] Center 38 (7~69) winsize 63
798 22:10:19.707484 [CA 1] Center 38 (7~69) winsize 63
799 22:10:19.710624 [CA 2] Center 36 (5~67) winsize 63
800 22:10:19.714198 [CA 3] Center 35 (5~66) winsize 62
801 22:10:19.717811 [CA 4] Center 35 (4~66) winsize 63
802 22:10:19.720904 [CA 5] Center 34 (4~65) winsize 62
803 22:10:19.720990
804 22:10:19.724069 [CmdBusTrainingLP45] Vref(ca) range 1: 32
805 22:10:19.724248
806 22:10:19.727482 [CATrainingPosCal] consider 2 rank data
807 22:10:19.730773 u2DelayCellTimex100 = 270/100 ps
808 22:10:19.734156 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
809 22:10:19.737397 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
810 22:10:19.744040 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
811 22:10:19.747383 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
812 22:10:19.750784 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
813 22:10:19.753913 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
814 22:10:19.753998
815 22:10:19.757566 CA PerBit enable=1, Macro0, CA PI delay=34
816 22:10:19.757651
817 22:10:19.761160 [CBTSetCACLKResult] CA Dly = 34
818 22:10:19.761245 CS Dly: 6 (0~38)
819 22:10:19.761312
820 22:10:19.764110 ----->DramcWriteLeveling(PI) begin...
821 22:10:19.767507 ==
822 22:10:19.767609 Dram Type= 6, Freq= 0, CH_0, rank 0
823 22:10:19.773985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
824 22:10:19.774071 ==
825 22:10:19.777428 Write leveling (Byte 0): 33 => 33
826 22:10:19.780658 Write leveling (Byte 1): 28 => 28
827 22:10:19.783979 DramcWriteLeveling(PI) end<-----
828 22:10:19.784095
829 22:10:19.784192 ==
830 22:10:19.787280 Dram Type= 6, Freq= 0, CH_0, rank 0
831 22:10:19.790533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
832 22:10:19.790664 ==
833 22:10:19.794104 [Gating] SW mode calibration
834 22:10:19.800989 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
835 22:10:19.804193 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
836 22:10:19.810845 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
837 22:10:19.814074 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
838 22:10:19.817654 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
839 22:10:19.824336 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 22:10:19.827631 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 22:10:19.831115 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 22:10:19.837566 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 22:10:19.841379 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 22:10:19.845141 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 22:10:19.848640 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 22:10:19.852189 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 22:10:19.859938 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 22:10:19.863682 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 22:10:19.866530 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 22:10:19.869680 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 22:10:19.877023 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 22:10:19.880550 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 22:10:19.883609 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
854 22:10:19.890473 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
855 22:10:19.893362 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 22:10:19.896952 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:10:19.903449 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:10:19.907007 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:10:19.910114 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:10:19.916925 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:10:19.919965 0 9 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
862 22:10:19.923210 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
863 22:10:19.929987 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
864 22:10:19.933189 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 22:10:19.936734 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
866 22:10:19.943078 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
867 22:10:19.946709 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 22:10:19.950245 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
869 22:10:19.953117 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
870 22:10:19.959967 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
871 22:10:19.963527 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 22:10:19.966766 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 22:10:19.973094 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:10:19.976625 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:10:19.979832 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:10:19.986506 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:10:19.989840 0 11 4 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
878 22:10:19.993117 0 11 8 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
879 22:10:19.999859 0 11 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
880 22:10:20.003270 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 22:10:20.006668 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
882 22:10:20.013565 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
883 22:10:20.016625 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 22:10:20.019815 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
885 22:10:20.026806 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
886 22:10:20.030134 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
887 22:10:20.033237 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 22:10:20.036920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 22:10:20.043519 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 22:10:20.046845 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 22:10:20.050565 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 22:10:20.056682 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 22:10:20.059937 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 22:10:20.063277 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 22:10:20.070177 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 22:10:20.073553 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 22:10:20.077081 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 22:10:20.083613 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 22:10:20.086750 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 22:10:20.090315 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 22:10:20.097123 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
902 22:10:20.100566 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
903 22:10:20.103495 Total UI for P1: 0, mck2ui 16
904 22:10:20.106926 best dqsien dly found for B0: ( 0, 14, 4)
905 22:10:20.110298 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
906 22:10:20.113977 Total UI for P1: 0, mck2ui 16
907 22:10:20.117086 best dqsien dly found for B1: ( 0, 14, 8)
908 22:10:20.120345 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
909 22:10:20.123610 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
910 22:10:20.123717
911 22:10:20.127173 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
912 22:10:20.130428 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
913 22:10:20.133799 [Gating] SW calibration Done
914 22:10:20.133902 ==
915 22:10:20.136998 Dram Type= 6, Freq= 0, CH_0, rank 0
916 22:10:20.140422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 22:10:20.143922 ==
918 22:10:20.144006 RX Vref Scan: 0
919 22:10:20.144072
920 22:10:20.147005 RX Vref 0 -> 0, step: 1
921 22:10:20.147089
922 22:10:20.150286 RX Delay -130 -> 252, step: 16
923 22:10:20.153559 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
924 22:10:20.157329 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
925 22:10:20.160526 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
926 22:10:20.163679 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
927 22:10:20.170631 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
928 22:10:20.173863 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
929 22:10:20.177178 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
930 22:10:20.180936 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
931 22:10:20.183881 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
932 22:10:20.187246 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
933 22:10:20.193874 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
934 22:10:20.197107 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
935 22:10:20.200563 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
936 22:10:20.204092 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
937 22:10:20.210413 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
938 22:10:20.213892 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
939 22:10:20.213977 ==
940 22:10:20.217302 Dram Type= 6, Freq= 0, CH_0, rank 0
941 22:10:20.220925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
942 22:10:20.221055 ==
943 22:10:20.221177 DQS Delay:
944 22:10:20.223742 DQS0 = 0, DQS1 = 0
945 22:10:20.223877 DQM Delay:
946 22:10:20.227067 DQM0 = 90, DQM1 = 78
947 22:10:20.227190 DQ Delay:
948 22:10:20.230616 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
949 22:10:20.234238 DQ4 =85, DQ5 =77, DQ6 =109, DQ7 =109
950 22:10:20.237203 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
951 22:10:20.240923 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
952 22:10:20.241007
953 22:10:20.241074
954 22:10:20.241135 ==
955 22:10:20.243875 Dram Type= 6, Freq= 0, CH_0, rank 0
956 22:10:20.247573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 22:10:20.250536 ==
958 22:10:20.250620
959 22:10:20.250687
960 22:10:20.250748 TX Vref Scan disable
961 22:10:20.253964 == TX Byte 0 ==
962 22:10:20.257441 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
963 22:10:20.260540 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
964 22:10:20.263905 == TX Byte 1 ==
965 22:10:20.267551 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
966 22:10:20.270705 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
967 22:10:20.274380 ==
968 22:10:20.274465 Dram Type= 6, Freq= 0, CH_0, rank 0
969 22:10:20.280681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 22:10:20.280770 ==
971 22:10:20.293559 TX Vref=22, minBit 8, minWin=26, winSum=441
972 22:10:20.296792 TX Vref=24, minBit 6, minWin=27, winSum=444
973 22:10:20.300031 TX Vref=26, minBit 8, minWin=27, winSum=447
974 22:10:20.303646 TX Vref=28, minBit 12, minWin=27, winSum=453
975 22:10:20.306840 TX Vref=30, minBit 5, minWin=28, winSum=456
976 22:10:20.309928 TX Vref=32, minBit 3, minWin=28, winSum=455
977 22:10:20.316683 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 30
978 22:10:20.316779
979 22:10:20.320293 Final TX Range 1 Vref 30
980 22:10:20.320430
981 22:10:20.320551 ==
982 22:10:20.323496 Dram Type= 6, Freq= 0, CH_0, rank 0
983 22:10:20.326895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 22:10:20.326983 ==
985 22:10:20.327074
986 22:10:20.327179
987 22:10:20.330125 TX Vref Scan disable
988 22:10:20.333512 == TX Byte 0 ==
989 22:10:20.337169 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
990 22:10:20.340194 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
991 22:10:20.343640 == TX Byte 1 ==
992 22:10:20.347141 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
993 22:10:20.350481 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
994 22:10:20.350604
995 22:10:20.353614 [DATLAT]
996 22:10:20.353714 Freq=800, CH0 RK0
997 22:10:20.353812
998 22:10:20.356715 DATLAT Default: 0xa
999 22:10:20.356838 0, 0xFFFF, sum = 0
1000 22:10:20.360322 1, 0xFFFF, sum = 0
1001 22:10:20.360398 2, 0xFFFF, sum = 0
1002 22:10:20.363607 3, 0xFFFF, sum = 0
1003 22:10:20.363683 4, 0xFFFF, sum = 0
1004 22:10:20.366721 5, 0xFFFF, sum = 0
1005 22:10:20.366800 6, 0xFFFF, sum = 0
1006 22:10:20.370533 7, 0xFFFF, sum = 0
1007 22:10:20.370612 8, 0xFFFF, sum = 0
1008 22:10:20.373587 9, 0x0, sum = 1
1009 22:10:20.373660 10, 0x0, sum = 2
1010 22:10:20.376982 11, 0x0, sum = 3
1011 22:10:20.377057 12, 0x0, sum = 4
1012 22:10:20.380549 best_step = 10
1013 22:10:20.380623
1014 22:10:20.380685 ==
1015 22:10:20.383643 Dram Type= 6, Freq= 0, CH_0, rank 0
1016 22:10:20.387258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1017 22:10:20.387333 ==
1018 22:10:20.390791 RX Vref Scan: 1
1019 22:10:20.390862
1020 22:10:20.390922 Set Vref Range= 32 -> 127
1021 22:10:20.390988
1022 22:10:20.393711 RX Vref 32 -> 127, step: 1
1023 22:10:20.393783
1024 22:10:20.396872 RX Delay -95 -> 252, step: 8
1025 22:10:20.396948
1026 22:10:20.400630 Set Vref, RX VrefLevel [Byte0]: 32
1027 22:10:20.403607 [Byte1]: 32
1028 22:10:20.403684
1029 22:10:20.406992 Set Vref, RX VrefLevel [Byte0]: 33
1030 22:10:20.410285 [Byte1]: 33
1031 22:10:20.413937
1032 22:10:20.414051 Set Vref, RX VrefLevel [Byte0]: 34
1033 22:10:20.417600 [Byte1]: 34
1034 22:10:20.421167
1035 22:10:20.421269 Set Vref, RX VrefLevel [Byte0]: 35
1036 22:10:20.424576 [Byte1]: 35
1037 22:10:20.428831
1038 22:10:20.428915 Set Vref, RX VrefLevel [Byte0]: 36
1039 22:10:20.432075 [Byte1]: 36
1040 22:10:20.436518
1041 22:10:20.436594 Set Vref, RX VrefLevel [Byte0]: 37
1042 22:10:20.439825 [Byte1]: 37
1043 22:10:20.444764
1044 22:10:20.444862 Set Vref, RX VrefLevel [Byte0]: 38
1045 22:10:20.447624 [Byte1]: 38
1046 22:10:20.451681
1047 22:10:20.451763 Set Vref, RX VrefLevel [Byte0]: 39
1048 22:10:20.454966 [Byte1]: 39
1049 22:10:20.459393
1050 22:10:20.459476 Set Vref, RX VrefLevel [Byte0]: 40
1051 22:10:20.462766 [Byte1]: 40
1052 22:10:20.466897
1053 22:10:20.466979 Set Vref, RX VrefLevel [Byte0]: 41
1054 22:10:20.470115 [Byte1]: 41
1055 22:10:20.474386
1056 22:10:20.474480 Set Vref, RX VrefLevel [Byte0]: 42
1057 22:10:20.477720 [Byte1]: 42
1058 22:10:20.481966
1059 22:10:20.482064 Set Vref, RX VrefLevel [Byte0]: 43
1060 22:10:20.485698 [Byte1]: 43
1061 22:10:20.489603
1062 22:10:20.489685 Set Vref, RX VrefLevel [Byte0]: 44
1063 22:10:20.493111 [Byte1]: 44
1064 22:10:20.497163
1065 22:10:20.497244 Set Vref, RX VrefLevel [Byte0]: 45
1066 22:10:20.500589 [Byte1]: 45
1067 22:10:20.505030
1068 22:10:20.505112 Set Vref, RX VrefLevel [Byte0]: 46
1069 22:10:20.508219 [Byte1]: 46
1070 22:10:20.512626
1071 22:10:20.512736 Set Vref, RX VrefLevel [Byte0]: 47
1072 22:10:20.515937 [Byte1]: 47
1073 22:10:20.520665
1074 22:10:20.520824 Set Vref, RX VrefLevel [Byte0]: 48
1075 22:10:20.524020 [Byte1]: 48
1076 22:10:20.528068
1077 22:10:20.528203 Set Vref, RX VrefLevel [Byte0]: 49
1078 22:10:20.531878 [Byte1]: 49
1079 22:10:20.535204
1080 22:10:20.535307 Set Vref, RX VrefLevel [Byte0]: 50
1081 22:10:20.538714 [Byte1]: 50
1082 22:10:20.543317
1083 22:10:20.543399 Set Vref, RX VrefLevel [Byte0]: 51
1084 22:10:20.546826 [Byte1]: 51
1085 22:10:20.550555
1086 22:10:20.550640 Set Vref, RX VrefLevel [Byte0]: 52
1087 22:10:20.554457 [Byte1]: 52
1088 22:10:20.558233
1089 22:10:20.558340 Set Vref, RX VrefLevel [Byte0]: 53
1090 22:10:20.561657 [Byte1]: 53
1091 22:10:20.565624
1092 22:10:20.565701 Set Vref, RX VrefLevel [Byte0]: 54
1093 22:10:20.568879 [Byte1]: 54
1094 22:10:20.573239
1095 22:10:20.573322 Set Vref, RX VrefLevel [Byte0]: 55
1096 22:10:20.576472 [Byte1]: 55
1097 22:10:20.580908
1098 22:10:20.580990 Set Vref, RX VrefLevel [Byte0]: 56
1099 22:10:20.584164 [Byte1]: 56
1100 22:10:20.588603
1101 22:10:20.588686 Set Vref, RX VrefLevel [Byte0]: 57
1102 22:10:20.592170 [Byte1]: 57
1103 22:10:20.596514
1104 22:10:20.596597 Set Vref, RX VrefLevel [Byte0]: 58
1105 22:10:20.599573 [Byte1]: 58
1106 22:10:20.603530
1107 22:10:20.603627 Set Vref, RX VrefLevel [Byte0]: 59
1108 22:10:20.606710 [Byte1]: 59
1109 22:10:20.611113
1110 22:10:20.611195 Set Vref, RX VrefLevel [Byte0]: 60
1111 22:10:20.614410 [Byte1]: 60
1112 22:10:20.618869
1113 22:10:20.618952 Set Vref, RX VrefLevel [Byte0]: 61
1114 22:10:20.622276 [Byte1]: 61
1115 22:10:20.626579
1116 22:10:20.626702 Set Vref, RX VrefLevel [Byte0]: 62
1117 22:10:20.629846 [Byte1]: 62
1118 22:10:20.633937
1119 22:10:20.634019 Set Vref, RX VrefLevel [Byte0]: 63
1120 22:10:20.637595 [Byte1]: 63
1121 22:10:20.641424
1122 22:10:20.641506 Set Vref, RX VrefLevel [Byte0]: 64
1123 22:10:20.644834 [Byte1]: 64
1124 22:10:20.649188
1125 22:10:20.649270 Set Vref, RX VrefLevel [Byte0]: 65
1126 22:10:20.652640 [Byte1]: 65
1127 22:10:20.656640
1128 22:10:20.656722 Set Vref, RX VrefLevel [Byte0]: 66
1129 22:10:20.660138 [Byte1]: 66
1130 22:10:20.664209
1131 22:10:20.664326 Set Vref, RX VrefLevel [Byte0]: 67
1132 22:10:20.667773 [Byte1]: 67
1133 22:10:20.671979
1134 22:10:20.672099 Set Vref, RX VrefLevel [Byte0]: 68
1135 22:10:20.675398 [Byte1]: 68
1136 22:10:20.679518
1137 22:10:20.679643 Set Vref, RX VrefLevel [Byte0]: 69
1138 22:10:20.683054 [Byte1]: 69
1139 22:10:20.687125
1140 22:10:20.687247 Set Vref, RX VrefLevel [Byte0]: 70
1141 22:10:20.691186 [Byte1]: 70
1142 22:10:20.694884
1143 22:10:20.695004 Set Vref, RX VrefLevel [Byte0]: 71
1144 22:10:20.698384 [Byte1]: 71
1145 22:10:20.702555
1146 22:10:20.702675 Set Vref, RX VrefLevel [Byte0]: 72
1147 22:10:20.705665 [Byte1]: 72
1148 22:10:20.710295
1149 22:10:20.710418 Set Vref, RX VrefLevel [Byte0]: 73
1150 22:10:20.714084 [Byte1]: 73
1151 22:10:20.717492
1152 22:10:20.717614 Set Vref, RX VrefLevel [Byte0]: 74
1153 22:10:20.720886 [Byte1]: 74
1154 22:10:20.725333
1155 22:10:20.725416 Set Vref, RX VrefLevel [Byte0]: 75
1156 22:10:20.728353 [Byte1]: 75
1157 22:10:20.732886
1158 22:10:20.732968 Set Vref, RX VrefLevel [Byte0]: 76
1159 22:10:20.736556 [Byte1]: 76
1160 22:10:20.740330
1161 22:10:20.740439 Set Vref, RX VrefLevel [Byte0]: 77
1162 22:10:20.743811 [Byte1]: 77
1163 22:10:20.748142
1164 22:10:20.748237 Final RX Vref Byte 0 = 61 to rank0
1165 22:10:20.751127 Final RX Vref Byte 1 = 53 to rank0
1166 22:10:20.754784 Final RX Vref Byte 0 = 61 to rank1
1167 22:10:20.758481 Final RX Vref Byte 1 = 53 to rank1==
1168 22:10:20.761692 Dram Type= 6, Freq= 0, CH_0, rank 0
1169 22:10:20.764823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1170 22:10:20.768113 ==
1171 22:10:20.768195 DQS Delay:
1172 22:10:20.768260 DQS0 = 0, DQS1 = 0
1173 22:10:20.771675 DQM Delay:
1174 22:10:20.771757 DQM0 = 93, DQM1 = 81
1175 22:10:20.774787 DQ Delay:
1176 22:10:20.778070 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1177 22:10:20.778154 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1178 22:10:20.781472 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1179 22:10:20.788062 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1180 22:10:20.788177
1181 22:10:20.788278
1182 22:10:20.795262 [DQSOSCAuto] RK0, (LSB)MR18= 0x403c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1183 22:10:20.798184 CH0 RK0: MR19=606, MR18=403C
1184 22:10:20.804723 CH0_RK0: MR19=0x606, MR18=0x403C, DQSOSC=393, MR23=63, INC=95, DEC=63
1185 22:10:20.804833
1186 22:10:20.808322 ----->DramcWriteLeveling(PI) begin...
1187 22:10:20.808402 ==
1188 22:10:20.811898 Dram Type= 6, Freq= 0, CH_0, rank 1
1189 22:10:20.814992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 22:10:20.815076 ==
1191 22:10:20.818226 Write leveling (Byte 0): 31 => 31
1192 22:10:20.821294 Write leveling (Byte 1): 29 => 29
1193 22:10:20.824850 DramcWriteLeveling(PI) end<-----
1194 22:10:20.824936
1195 22:10:20.825003 ==
1196 22:10:20.828135 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 22:10:20.831506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 22:10:20.831590 ==
1199 22:10:20.834914 [Gating] SW mode calibration
1200 22:10:20.841604 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1201 22:10:20.848242 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1202 22:10:20.851374 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1203 22:10:20.854918 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1204 22:10:20.861614 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 22:10:20.864996 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 22:10:20.868186 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 22:10:20.912873 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 22:10:20.913138 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 22:10:20.913517 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 22:10:20.913782 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 22:10:20.913855 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 22:10:20.913930 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 22:10:20.914569 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 22:10:20.914866 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 22:10:20.914967 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 22:10:20.915060 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 22:10:20.956203 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 22:10:20.956633 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 22:10:20.956797 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1220 22:10:20.957117 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 22:10:20.957235 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 22:10:20.957540 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 22:10:20.957853 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 22:10:20.957993 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:10:20.958109 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:10:20.958277 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:10:20.961031 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:10:20.964658 0 9 8 | B1->B0 | 2e2e 3232 | 1 1 | (0 0) (1 1)
1229 22:10:20.971020 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 22:10:20.974383 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 22:10:20.977813 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 22:10:20.984583 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 22:10:20.987839 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 22:10:20.991244 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 22:10:20.997706 0 10 4 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 1)
1236 22:10:21.001145 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
1237 22:10:21.004644 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 22:10:21.011059 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 22:10:21.014512 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 22:10:21.017716 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:10:21.021457 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 22:10:21.028103 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 22:10:21.031199 0 11 4 | B1->B0 | 2626 3030 | 1 0 | (0 0) (0 0)
1244 22:10:21.034500 0 11 8 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
1245 22:10:21.040983 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 22:10:21.044383 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 22:10:21.048026 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 22:10:21.054770 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 22:10:21.058484 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 22:10:21.061149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 22:10:21.068150 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1252 22:10:21.071320 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1253 22:10:21.074505 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 22:10:21.081207 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 22:10:21.084484 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 22:10:21.088068 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 22:10:21.095136 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 22:10:21.098877 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 22:10:21.102103 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 22:10:21.105652 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 22:10:21.109613 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 22:10:21.115764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 22:10:21.119277 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 22:10:21.122886 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 22:10:21.129917 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 22:10:21.132736 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 22:10:21.136509 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1268 22:10:21.142907 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1269 22:10:21.146228 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 22:10:21.149918 Total UI for P1: 0, mck2ui 16
1271 22:10:21.152988 best dqsien dly found for B0: ( 0, 14, 6)
1272 22:10:21.156481 Total UI for P1: 0, mck2ui 16
1273 22:10:21.159764 best dqsien dly found for B1: ( 0, 14, 8)
1274 22:10:21.162852 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1275 22:10:21.166421 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1276 22:10:21.166506
1277 22:10:21.169519 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1278 22:10:21.172990 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1279 22:10:21.176490 [Gating] SW calibration Done
1280 22:10:21.176587 ==
1281 22:10:21.179635 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 22:10:21.183419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 22:10:21.183505 ==
1284 22:10:21.186380 RX Vref Scan: 0
1285 22:10:21.186465
1286 22:10:21.186548 RX Vref 0 -> 0, step: 1
1287 22:10:21.189785
1288 22:10:21.189868 RX Delay -130 -> 252, step: 16
1289 22:10:21.196533 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1290 22:10:21.199646 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1291 22:10:21.203060 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1292 22:10:21.206581 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1293 22:10:21.209836 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1294 22:10:21.213344 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1295 22:10:21.219967 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1296 22:10:21.223013 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1297 22:10:21.226579 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1298 22:10:21.229642 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1299 22:10:21.233296 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1300 22:10:21.239653 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1301 22:10:21.243133 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1302 22:10:21.246670 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1303 22:10:21.250113 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1304 22:10:21.256534 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1305 22:10:21.256620 ==
1306 22:10:21.260027 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 22:10:21.263512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 22:10:21.263597 ==
1309 22:10:21.263680 DQS Delay:
1310 22:10:21.266397 DQS0 = 0, DQS1 = 0
1311 22:10:21.266481 DQM Delay:
1312 22:10:21.269864 DQM0 = 90, DQM1 = 78
1313 22:10:21.269949 DQ Delay:
1314 22:10:21.273207 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1315 22:10:21.276555 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
1316 22:10:21.280198 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1317 22:10:21.283574 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
1318 22:10:21.283658
1319 22:10:21.283758
1320 22:10:21.283851 ==
1321 22:10:21.286579 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 22:10:21.290347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 22:10:21.290432 ==
1324 22:10:21.290517
1325 22:10:21.290617
1326 22:10:21.293454 TX Vref Scan disable
1327 22:10:21.296675 == TX Byte 0 ==
1328 22:10:21.300226 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1329 22:10:21.303705 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1330 22:10:21.306886 == TX Byte 1 ==
1331 22:10:21.310095 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1332 22:10:21.313862 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1333 22:10:21.313950 ==
1334 22:10:21.316606 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 22:10:21.320104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 22:10:21.323852 ==
1337 22:10:21.335039 TX Vref=22, minBit 3, minWin=27, winSum=443
1338 22:10:21.338300 TX Vref=24, minBit 8, minWin=27, winSum=446
1339 22:10:21.341827 TX Vref=26, minBit 8, minWin=27, winSum=451
1340 22:10:21.345102 TX Vref=28, minBit 8, minWin=27, winSum=455
1341 22:10:21.348223 TX Vref=30, minBit 8, minWin=27, winSum=458
1342 22:10:21.351591 TX Vref=32, minBit 8, minWin=27, winSum=456
1343 22:10:21.358418 [TxChooseVref] Worse bit 8, Min win 27, Win sum 458, Final Vref 30
1344 22:10:21.358503
1345 22:10:21.361478 Final TX Range 1 Vref 30
1346 22:10:21.361586
1347 22:10:21.361678 ==
1348 22:10:21.364750 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 22:10:21.368208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 22:10:21.368289 ==
1351 22:10:21.368353
1352 22:10:21.368413
1353 22:10:21.372016 TX Vref Scan disable
1354 22:10:21.375043 == TX Byte 0 ==
1355 22:10:21.378447 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1356 22:10:21.381956 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1357 22:10:21.385131 == TX Byte 1 ==
1358 22:10:21.388288 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1359 22:10:21.391856 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1360 22:10:21.391936
1361 22:10:21.394883 [DATLAT]
1362 22:10:21.394980 Freq=800, CH0 RK1
1363 22:10:21.395088
1364 22:10:21.398329 DATLAT Default: 0xa
1365 22:10:21.398435 0, 0xFFFF, sum = 0
1366 22:10:21.401787 1, 0xFFFF, sum = 0
1367 22:10:21.401885 2, 0xFFFF, sum = 0
1368 22:10:21.405001 3, 0xFFFF, sum = 0
1369 22:10:21.405127 4, 0xFFFF, sum = 0
1370 22:10:21.408465 5, 0xFFFF, sum = 0
1371 22:10:21.408547 6, 0xFFFF, sum = 0
1372 22:10:21.411889 7, 0xFFFF, sum = 0
1373 22:10:21.411971 8, 0xFFFF, sum = 0
1374 22:10:21.415102 9, 0x0, sum = 1
1375 22:10:21.415183 10, 0x0, sum = 2
1376 22:10:21.418539 11, 0x0, sum = 3
1377 22:10:21.418620 12, 0x0, sum = 4
1378 22:10:21.421687 best_step = 10
1379 22:10:21.421766
1380 22:10:21.421829 ==
1381 22:10:21.425016 Dram Type= 6, Freq= 0, CH_0, rank 1
1382 22:10:21.428601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 22:10:21.428682 ==
1384 22:10:21.431724 RX Vref Scan: 0
1385 22:10:21.431804
1386 22:10:21.431867 RX Vref 0 -> 0, step: 1
1387 22:10:21.431925
1388 22:10:21.435639 RX Delay -95 -> 252, step: 8
1389 22:10:21.441912 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1390 22:10:21.445373 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1391 22:10:21.448397 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1392 22:10:21.452120 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1393 22:10:21.455270 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1394 22:10:21.462154 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1395 22:10:21.465217 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1396 22:10:21.468517 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1397 22:10:21.472026 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1398 22:10:21.475508 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1399 22:10:21.478602 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1400 22:10:21.485510 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1401 22:10:21.488663 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1402 22:10:21.492060 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1403 22:10:21.495398 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1404 22:10:21.498827 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1405 22:10:21.502302 ==
1406 22:10:21.505280 Dram Type= 6, Freq= 0, CH_0, rank 1
1407 22:10:21.508694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 22:10:21.508827 ==
1409 22:10:21.508891 DQS Delay:
1410 22:10:21.512469 DQS0 = 0, DQS1 = 0
1411 22:10:21.512567 DQM Delay:
1412 22:10:21.515342 DQM0 = 90, DQM1 = 83
1413 22:10:21.515465 DQ Delay:
1414 22:10:21.518561 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1415 22:10:21.521887 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1416 22:10:21.525440 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =80
1417 22:10:21.528663 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1418 22:10:21.528800
1419 22:10:21.528912
1420 22:10:21.535476 [DQSOSCAuto] RK1, (LSB)MR18= 0x4520, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1421 22:10:21.538966 CH0 RK1: MR19=606, MR18=4520
1422 22:10:21.545764 CH0_RK1: MR19=0x606, MR18=0x4520, DQSOSC=392, MR23=63, INC=96, DEC=64
1423 22:10:21.548624 [RxdqsGatingPostProcess] freq 800
1424 22:10:21.552121 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1425 22:10:21.555337 Pre-setting of DQS Precalculation
1426 22:10:21.561979 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1427 22:10:21.562086 ==
1428 22:10:21.565382 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 22:10:21.568683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 22:10:21.568845 ==
1431 22:10:21.575530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1432 22:10:21.582270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1433 22:10:21.590107 [CA 0] Center 36 (6~67) winsize 62
1434 22:10:21.593470 [CA 1] Center 36 (6~67) winsize 62
1435 22:10:21.596676 [CA 2] Center 34 (4~65) winsize 62
1436 22:10:21.599860 [CA 3] Center 34 (4~65) winsize 62
1437 22:10:21.603274 [CA 4] Center 34 (4~65) winsize 62
1438 22:10:21.606479 [CA 5] Center 34 (4~65) winsize 62
1439 22:10:21.606599
1440 22:10:21.609864 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1441 22:10:21.609986
1442 22:10:21.613118 [CATrainingPosCal] consider 1 rank data
1443 22:10:21.616565 u2DelayCellTimex100 = 270/100 ps
1444 22:10:21.619791 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1445 22:10:21.623628 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1446 22:10:21.630162 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1447 22:10:21.633596 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1448 22:10:21.636540 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1449 22:10:21.640059 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1450 22:10:21.640158
1451 22:10:21.643757 CA PerBit enable=1, Macro0, CA PI delay=34
1452 22:10:21.643855
1453 22:10:21.646442 [CBTSetCACLKResult] CA Dly = 34
1454 22:10:21.646540 CS Dly: 5 (0~36)
1455 22:10:21.646632 ==
1456 22:10:21.650081 Dram Type= 6, Freq= 0, CH_1, rank 1
1457 22:10:21.656512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 22:10:21.656612 ==
1459 22:10:21.659941 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1460 22:10:21.666714 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1461 22:10:21.675903 [CA 0] Center 37 (7~67) winsize 61
1462 22:10:21.679863 [CA 1] Center 37 (6~68) winsize 63
1463 22:10:21.682712 [CA 2] Center 35 (4~66) winsize 63
1464 22:10:21.686230 [CA 3] Center 34 (4~65) winsize 62
1465 22:10:21.689489 [CA 4] Center 34 (4~65) winsize 62
1466 22:10:21.692760 [CA 5] Center 34 (3~65) winsize 63
1467 22:10:21.692844
1468 22:10:21.696468 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1469 22:10:21.696565
1470 22:10:21.699347 [CATrainingPosCal] consider 2 rank data
1471 22:10:21.703147 u2DelayCellTimex100 = 270/100 ps
1472 22:10:21.706288 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1473 22:10:21.709542 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1474 22:10:21.716585 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1475 22:10:21.719706 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 22:10:21.723382 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1477 22:10:21.726686 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1478 22:10:21.726817
1479 22:10:21.729655 CA PerBit enable=1, Macro0, CA PI delay=34
1480 22:10:21.729737
1481 22:10:21.733004 [CBTSetCACLKResult] CA Dly = 34
1482 22:10:21.733098 CS Dly: 6 (0~38)
1483 22:10:21.733166
1484 22:10:21.736370 ----->DramcWriteLeveling(PI) begin...
1485 22:10:21.736442 ==
1486 22:10:21.739627 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 22:10:21.746400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1488 22:10:21.746475 ==
1489 22:10:21.749500 Write leveling (Byte 0): 26 => 26
1490 22:10:21.753588 Write leveling (Byte 1): 27 => 27
1491 22:10:21.753687 DramcWriteLeveling(PI) end<-----
1492 22:10:21.753776
1493 22:10:21.756411 ==
1494 22:10:21.760099 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 22:10:21.763931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 22:10:21.764037 ==
1497 22:10:21.764128 [Gating] SW mode calibration
1498 22:10:21.770835 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1499 22:10:21.778601 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1500 22:10:21.782202 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1501 22:10:21.785885 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 22:10:21.789597 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 22:10:21.797244 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 22:10:21.800026 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 22:10:21.803374 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 22:10:21.806767 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 22:10:21.813485 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 22:10:21.816958 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 22:10:21.820193 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 22:10:21.826895 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 22:10:21.830157 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 22:10:21.833698 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 22:10:21.840730 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 22:10:21.843987 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 22:10:21.847207 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 22:10:21.853635 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1517 22:10:21.857329 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1518 22:10:21.860465 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 22:10:21.863809 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 22:10:21.870325 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:10:21.873944 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:10:21.877283 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:10:21.883628 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:10:21.887339 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:10:21.890302 0 9 4 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
1526 22:10:21.897161 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1527 22:10:21.900639 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 22:10:21.903706 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 22:10:21.910531 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 22:10:21.913661 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 22:10:21.917108 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 22:10:21.923827 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 22:10:21.927251 0 10 4 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (0 0)
1534 22:10:21.930700 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1535 22:10:21.937385 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 22:10:21.940913 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 22:10:21.943912 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 22:10:21.947267 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 22:10:21.953887 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 22:10:21.957737 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 22:10:21.960679 0 11 4 | B1->B0 | 2d2d 3333 | 1 0 | (0 0) (0 0)
1542 22:10:21.967380 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 22:10:21.970853 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 22:10:21.974241 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 22:10:21.980852 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 22:10:21.984587 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 22:10:21.987416 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 22:10:21.994405 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 22:10:21.997934 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1550 22:10:22.001016 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 22:10:22.007569 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 22:10:22.010868 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 22:10:22.014261 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 22:10:22.017885 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 22:10:22.024529 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 22:10:22.027460 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 22:10:22.031026 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 22:10:22.037643 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 22:10:22.040730 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 22:10:22.044198 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 22:10:22.051040 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 22:10:22.054499 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 22:10:22.057506 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 22:10:22.064035 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 22:10:22.067483 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1566 22:10:22.070969 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 22:10:22.074448 Total UI for P1: 0, mck2ui 16
1568 22:10:22.077551 best dqsien dly found for B0: ( 0, 14, 4)
1569 22:10:22.080701 Total UI for P1: 0, mck2ui 16
1570 22:10:22.084246 best dqsien dly found for B1: ( 0, 14, 4)
1571 22:10:22.087750 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1572 22:10:22.090821 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1573 22:10:22.090902
1574 22:10:22.094336 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1575 22:10:22.100884 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1576 22:10:22.100966 [Gating] SW calibration Done
1577 22:10:22.101032 ==
1578 22:10:22.104115 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 22:10:22.111092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 22:10:22.111176 ==
1581 22:10:22.111241 RX Vref Scan: 0
1582 22:10:22.111301
1583 22:10:22.114164 RX Vref 0 -> 0, step: 1
1584 22:10:22.114246
1585 22:10:22.117607 RX Delay -130 -> 252, step: 16
1586 22:10:22.121031 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1587 22:10:22.124058 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1588 22:10:22.128046 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1589 22:10:22.134007 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1590 22:10:22.137442 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1591 22:10:22.140780 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1592 22:10:22.144003 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1593 22:10:22.147663 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1594 22:10:22.154230 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1595 22:10:22.157349 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1596 22:10:22.160865 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1597 22:10:22.164106 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1598 22:10:22.167206 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1599 22:10:22.174051 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1600 22:10:22.177170 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1601 22:10:22.180652 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1602 22:10:22.180757 ==
1603 22:10:22.184029 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 22:10:22.187516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 22:10:22.187602 ==
1606 22:10:22.190763 DQS Delay:
1607 22:10:22.190834 DQS0 = 0, DQS1 = 0
1608 22:10:22.193989 DQM Delay:
1609 22:10:22.194059 DQM0 = 91, DQM1 = 85
1610 22:10:22.194120 DQ Delay:
1611 22:10:22.197729 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1612 22:10:22.200932 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93
1613 22:10:22.203960 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1614 22:10:22.207538 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1615 22:10:22.207619
1616 22:10:22.207684
1617 22:10:22.210602 ==
1618 22:10:22.214102 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 22:10:22.217537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 22:10:22.217683 ==
1621 22:10:22.217761
1622 22:10:22.217821
1623 22:10:22.220988 TX Vref Scan disable
1624 22:10:22.221070 == TX Byte 0 ==
1625 22:10:22.224231 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1626 22:10:22.231171 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1627 22:10:22.231253 == TX Byte 1 ==
1628 22:10:22.233989 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1629 22:10:22.241243 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1630 22:10:22.241349 ==
1631 22:10:22.244355 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 22:10:22.247622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 22:10:22.247705 ==
1634 22:10:22.260273 TX Vref=22, minBit 10, minWin=27, winSum=451
1635 22:10:22.263589 TX Vref=24, minBit 15, minWin=27, winSum=456
1636 22:10:22.267036 TX Vref=26, minBit 15, minWin=27, winSum=458
1637 22:10:22.270319 TX Vref=28, minBit 9, minWin=28, winSum=461
1638 22:10:22.273684 TX Vref=30, minBit 9, minWin=28, winSum=461
1639 22:10:22.280914 TX Vref=32, minBit 9, minWin=27, winSum=458
1640 22:10:22.283883 [TxChooseVref] Worse bit 9, Min win 28, Win sum 461, Final Vref 28
1641 22:10:22.283965
1642 22:10:22.287241 Final TX Range 1 Vref 28
1643 22:10:22.287323
1644 22:10:22.287388 ==
1645 22:10:22.290778 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 22:10:22.294217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 22:10:22.294299 ==
1648 22:10:22.294364
1649 22:10:22.297253
1650 22:10:22.297334 TX Vref Scan disable
1651 22:10:22.300545 == TX Byte 0 ==
1652 22:10:22.304127 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1653 22:10:22.307371 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1654 22:10:22.310517 == TX Byte 1 ==
1655 22:10:22.314308 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1656 22:10:22.317491 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1657 22:10:22.320675
1658 22:10:22.320777 [DATLAT]
1659 22:10:22.320856 Freq=800, CH1 RK0
1660 22:10:22.320918
1661 22:10:22.323879 DATLAT Default: 0xa
1662 22:10:22.323967 0, 0xFFFF, sum = 0
1663 22:10:22.327525 1, 0xFFFF, sum = 0
1664 22:10:22.327614 2, 0xFFFF, sum = 0
1665 22:10:22.331013 3, 0xFFFF, sum = 0
1666 22:10:22.331096 4, 0xFFFF, sum = 0
1667 22:10:22.334106 5, 0xFFFF, sum = 0
1668 22:10:22.334190 6, 0xFFFF, sum = 0
1669 22:10:22.337297 7, 0xFFFF, sum = 0
1670 22:10:22.337381 8, 0xFFFF, sum = 0
1671 22:10:22.341272 9, 0x0, sum = 1
1672 22:10:22.341355 10, 0x0, sum = 2
1673 22:10:22.344561 11, 0x0, sum = 3
1674 22:10:22.344671 12, 0x0, sum = 4
1675 22:10:22.347843 best_step = 10
1676 22:10:22.347988
1677 22:10:22.348052 ==
1678 22:10:22.351308 Dram Type= 6, Freq= 0, CH_1, rank 0
1679 22:10:22.354720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1680 22:10:22.354803 ==
1681 22:10:22.354868 RX Vref Scan: 1
1682 22:10:22.357893
1683 22:10:22.357975 Set Vref Range= 32 -> 127
1684 22:10:22.358040
1685 22:10:22.361131 RX Vref 32 -> 127, step: 1
1686 22:10:22.361212
1687 22:10:22.364699 RX Delay -95 -> 252, step: 8
1688 22:10:22.364816
1689 22:10:22.367991 Set Vref, RX VrefLevel [Byte0]: 32
1690 22:10:22.371386 [Byte1]: 32
1691 22:10:22.371467
1692 22:10:22.374983 Set Vref, RX VrefLevel [Byte0]: 33
1693 22:10:22.378163 [Byte1]: 33
1694 22:10:22.378245
1695 22:10:22.380944 Set Vref, RX VrefLevel [Byte0]: 34
1696 22:10:22.384534 [Byte1]: 34
1697 22:10:22.388629
1698 22:10:22.388711 Set Vref, RX VrefLevel [Byte0]: 35
1699 22:10:22.392310 [Byte1]: 35
1700 22:10:22.396279
1701 22:10:22.396361 Set Vref, RX VrefLevel [Byte0]: 36
1702 22:10:22.399600 [Byte1]: 36
1703 22:10:22.403740
1704 22:10:22.403822 Set Vref, RX VrefLevel [Byte0]: 37
1705 22:10:22.407051 [Byte1]: 37
1706 22:10:22.411401
1707 22:10:22.411484 Set Vref, RX VrefLevel [Byte0]: 38
1708 22:10:22.414635 [Byte1]: 38
1709 22:10:22.418763
1710 22:10:22.418845 Set Vref, RX VrefLevel [Byte0]: 39
1711 22:10:22.422123 [Byte1]: 39
1712 22:10:22.426435
1713 22:10:22.426519 Set Vref, RX VrefLevel [Byte0]: 40
1714 22:10:22.429721 [Byte1]: 40
1715 22:10:22.434166
1716 22:10:22.434250 Set Vref, RX VrefLevel [Byte0]: 41
1717 22:10:22.437508 [Byte1]: 41
1718 22:10:22.441638
1719 22:10:22.441722 Set Vref, RX VrefLevel [Byte0]: 42
1720 22:10:22.448121 [Byte1]: 42
1721 22:10:22.448203
1722 22:10:22.451504 Set Vref, RX VrefLevel [Byte0]: 43
1723 22:10:22.454773 [Byte1]: 43
1724 22:10:22.454854
1725 22:10:22.458103 Set Vref, RX VrefLevel [Byte0]: 44
1726 22:10:22.461885 [Byte1]: 44
1727 22:10:22.461967
1728 22:10:22.464927 Set Vref, RX VrefLevel [Byte0]: 45
1729 22:10:22.468321 [Byte1]: 45
1730 22:10:22.471939
1731 22:10:22.472020 Set Vref, RX VrefLevel [Byte0]: 46
1732 22:10:22.475394 [Byte1]: 46
1733 22:10:22.479642
1734 22:10:22.479723 Set Vref, RX VrefLevel [Byte0]: 47
1735 22:10:22.483278 [Byte1]: 47
1736 22:10:22.487620
1737 22:10:22.487701 Set Vref, RX VrefLevel [Byte0]: 48
1738 22:10:22.491008 [Byte1]: 48
1739 22:10:22.494769
1740 22:10:22.494851 Set Vref, RX VrefLevel [Byte0]: 49
1741 22:10:22.498171 [Byte1]: 49
1742 22:10:22.502476
1743 22:10:22.502559 Set Vref, RX VrefLevel [Byte0]: 50
1744 22:10:22.505566 [Byte1]: 50
1745 22:10:22.510393
1746 22:10:22.510476 Set Vref, RX VrefLevel [Byte0]: 51
1747 22:10:22.513235 [Byte1]: 51
1748 22:10:22.517752
1749 22:10:22.517834 Set Vref, RX VrefLevel [Byte0]: 52
1750 22:10:22.521242 [Byte1]: 52
1751 22:10:22.525296
1752 22:10:22.525379 Set Vref, RX VrefLevel [Byte0]: 53
1753 22:10:22.528686 [Byte1]: 53
1754 22:10:22.532662
1755 22:10:22.532806 Set Vref, RX VrefLevel [Byte0]: 54
1756 22:10:22.536031 [Byte1]: 54
1757 22:10:22.540332
1758 22:10:22.540420 Set Vref, RX VrefLevel [Byte0]: 55
1759 22:10:22.543765 [Byte1]: 55
1760 22:10:22.547840
1761 22:10:22.547939 Set Vref, RX VrefLevel [Byte0]: 56
1762 22:10:22.551570 [Byte1]: 56
1763 22:10:22.555535
1764 22:10:22.555634 Set Vref, RX VrefLevel [Byte0]: 57
1765 22:10:22.559105 [Byte1]: 57
1766 22:10:22.563226
1767 22:10:22.563323 Set Vref, RX VrefLevel [Byte0]: 58
1768 22:10:22.566553 [Byte1]: 58
1769 22:10:22.570698
1770 22:10:22.570780 Set Vref, RX VrefLevel [Byte0]: 59
1771 22:10:22.574362 [Byte1]: 59
1772 22:10:22.578548
1773 22:10:22.578629 Set Vref, RX VrefLevel [Byte0]: 60
1774 22:10:22.581998 [Byte1]: 60
1775 22:10:22.586200
1776 22:10:22.586335 Set Vref, RX VrefLevel [Byte0]: 61
1777 22:10:22.589202 [Byte1]: 61
1778 22:10:22.593733
1779 22:10:22.593814 Set Vref, RX VrefLevel [Byte0]: 62
1780 22:10:22.596905 [Byte1]: 62
1781 22:10:22.601487
1782 22:10:22.601569 Set Vref, RX VrefLevel [Byte0]: 63
1783 22:10:22.604497 [Byte1]: 63
1784 22:10:22.608693
1785 22:10:22.608824 Set Vref, RX VrefLevel [Byte0]: 64
1786 22:10:22.611934 [Byte1]: 64
1787 22:10:22.616250
1788 22:10:22.616332 Set Vref, RX VrefLevel [Byte0]: 65
1789 22:10:22.619507 [Byte1]: 65
1790 22:10:22.623872
1791 22:10:22.623954 Set Vref, RX VrefLevel [Byte0]: 66
1792 22:10:22.627288 [Byte1]: 66
1793 22:10:22.631794
1794 22:10:22.631876 Set Vref, RX VrefLevel [Byte0]: 67
1795 22:10:22.634993 [Byte1]: 67
1796 22:10:22.639530
1797 22:10:22.639612 Set Vref, RX VrefLevel [Byte0]: 68
1798 22:10:22.642831 [Byte1]: 68
1799 22:10:22.646857
1800 22:10:22.646940 Set Vref, RX VrefLevel [Byte0]: 69
1801 22:10:22.650231 [Byte1]: 69
1802 22:10:22.654239
1803 22:10:22.654351 Set Vref, RX VrefLevel [Byte0]: 70
1804 22:10:22.657505 [Byte1]: 70
1805 22:10:22.661984
1806 22:10:22.662095 Set Vref, RX VrefLevel [Byte0]: 71
1807 22:10:22.665308 [Byte1]: 71
1808 22:10:22.669605
1809 22:10:22.669702 Set Vref, RX VrefLevel [Byte0]: 72
1810 22:10:22.673034 [Byte1]: 72
1811 22:10:22.677352
1812 22:10:22.677435 Set Vref, RX VrefLevel [Byte0]: 73
1813 22:10:22.680379 [Byte1]: 73
1814 22:10:22.684860
1815 22:10:22.684942 Set Vref, RX VrefLevel [Byte0]: 74
1816 22:10:22.688228 [Byte1]: 74
1817 22:10:22.692617
1818 22:10:22.692726 Set Vref, RX VrefLevel [Byte0]: 75
1819 22:10:22.695550 [Byte1]: 75
1820 22:10:22.700224
1821 22:10:22.700305 Set Vref, RX VrefLevel [Byte0]: 76
1822 22:10:22.703383 [Byte1]: 76
1823 22:10:22.707710
1824 22:10:22.707793 Set Vref, RX VrefLevel [Byte0]: 77
1825 22:10:22.710623 [Byte1]: 77
1826 22:10:22.714952
1827 22:10:22.715034 Set Vref, RX VrefLevel [Byte0]: 78
1828 22:10:22.718659 [Byte1]: 78
1829 22:10:22.722582
1830 22:10:22.722693 Final RX Vref Byte 0 = 53 to rank0
1831 22:10:22.726114 Final RX Vref Byte 1 = 63 to rank0
1832 22:10:22.729255 Final RX Vref Byte 0 = 53 to rank1
1833 22:10:22.732996 Final RX Vref Byte 1 = 63 to rank1==
1834 22:10:22.736175 Dram Type= 6, Freq= 0, CH_1, rank 0
1835 22:10:22.743213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 22:10:22.743319 ==
1837 22:10:22.743405 DQS Delay:
1838 22:10:22.743465 DQS0 = 0, DQS1 = 0
1839 22:10:22.746220 DQM Delay:
1840 22:10:22.746316 DQM0 = 92, DQM1 = 83
1841 22:10:22.749591 DQ Delay:
1842 22:10:22.752912 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =84
1843 22:10:22.756182 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1844 22:10:22.756260 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1845 22:10:22.762634 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1846 22:10:22.762709
1847 22:10:22.762772
1848 22:10:22.769568 [DQSOSCAuto] RK0, (LSB)MR18= 0x314e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1849 22:10:22.772661 CH1 RK0: MR19=606, MR18=314E
1850 22:10:22.779466 CH1_RK0: MR19=0x606, MR18=0x314E, DQSOSC=390, MR23=63, INC=97, DEC=64
1851 22:10:22.779544
1852 22:10:22.782972 ----->DramcWriteLeveling(PI) begin...
1853 22:10:22.783075 ==
1854 22:10:22.786105 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 22:10:22.789498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 22:10:22.789574 ==
1857 22:10:22.792730 Write leveling (Byte 0): 25 => 25
1858 22:10:22.796203 Write leveling (Byte 1): 30 => 30
1859 22:10:22.799529 DramcWriteLeveling(PI) end<-----
1860 22:10:22.799611
1861 22:10:22.799675 ==
1862 22:10:22.803093 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 22:10:22.806293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 22:10:22.806456 ==
1865 22:10:22.809706 [Gating] SW mode calibration
1866 22:10:22.816619 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1867 22:10:22.822818 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1868 22:10:22.826294 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1869 22:10:22.829746 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1870 22:10:22.836327 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1871 22:10:22.839533 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 22:10:22.843043 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 22:10:22.849716 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 22:10:22.852955 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 22:10:22.856196 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 22:10:22.862813 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 22:10:22.866736 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 22:10:22.869597 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 22:10:22.873230 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:10:22.879687 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:10:22.882984 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:10:22.886635 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:10:22.893368 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 22:10:22.896382 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1885 22:10:22.899813 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1886 22:10:22.906450 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:10:22.909620 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:10:22.913269 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:10:22.919736 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:10:22.923498 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:10:22.926478 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:10:22.933590 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:10:22.936642 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1894 22:10:22.939780 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1895 22:10:22.943105 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 22:10:22.950035 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 22:10:22.953312 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 22:10:22.956732 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 22:10:22.963478 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 22:10:22.966556 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 22:10:22.970115 0 10 4 | B1->B0 | 2d2d 2f2f | 0 1 | (0 0) (1 0)
1902 22:10:22.976624 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1903 22:10:22.980451 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 22:10:22.983521 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 22:10:22.990240 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 22:10:22.993370 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 22:10:22.996742 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 22:10:23.003372 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 22:10:23.007277 0 11 4 | B1->B0 | 3535 3131 | 0 0 | (0 0) (0 0)
1910 22:10:23.010311 0 11 8 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
1911 22:10:23.013827 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 22:10:23.020396 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 22:10:23.023697 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 22:10:23.027371 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 22:10:23.034015 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 22:10:23.037139 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 22:10:23.040586 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1918 22:10:23.047180 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 22:10:23.050389 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 22:10:23.053958 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 22:10:23.060618 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 22:10:23.063759 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 22:10:23.067198 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 22:10:23.073802 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 22:10:23.077294 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 22:10:23.080512 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 22:10:23.083905 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 22:10:23.090497 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 22:10:23.093905 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 22:10:23.097383 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 22:10:23.103861 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 22:10:23.107275 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 22:10:23.111033 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1934 22:10:23.117744 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 22:10:23.117829 Total UI for P1: 0, mck2ui 16
1936 22:10:23.124075 best dqsien dly found for B0: ( 0, 14, 4)
1937 22:10:23.124160 Total UI for P1: 0, mck2ui 16
1938 22:10:23.131106 best dqsien dly found for B1: ( 0, 14, 4)
1939 22:10:23.133966 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1940 22:10:23.137475 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1941 22:10:23.137560
1942 22:10:23.140734 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1943 22:10:23.144414 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1944 22:10:23.147724 [Gating] SW calibration Done
1945 22:10:23.147834 ==
1946 22:10:23.150870 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 22:10:23.154507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 22:10:23.154590 ==
1949 22:10:23.157467 RX Vref Scan: 0
1950 22:10:23.157549
1951 22:10:23.157656 RX Vref 0 -> 0, step: 1
1952 22:10:23.157748
1953 22:10:23.160750 RX Delay -130 -> 252, step: 16
1954 22:10:23.164213 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1955 22:10:23.167364 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1956 22:10:23.174251 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1957 22:10:23.177531 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1958 22:10:23.180782 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1959 22:10:23.184454 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1960 22:10:23.187841 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1961 22:10:23.194363 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1962 22:10:23.197530 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1963 22:10:23.201103 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1964 22:10:23.204447 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1965 22:10:23.207379 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1966 22:10:23.214668 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1967 22:10:23.217745 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1968 22:10:23.220940 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1969 22:10:23.224298 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1970 22:10:23.224382 ==
1971 22:10:23.227846 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 22:10:23.234498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 22:10:23.234583 ==
1974 22:10:23.234666 DQS Delay:
1975 22:10:23.234744 DQS0 = 0, DQS1 = 0
1976 22:10:23.237560 DQM Delay:
1977 22:10:23.237643 DQM0 = 92, DQM1 = 83
1978 22:10:23.240930 DQ Delay:
1979 22:10:23.244093 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1980 22:10:23.247429 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1981 22:10:23.251201 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1982 22:10:23.254218 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1983 22:10:23.254301
1984 22:10:23.254384
1985 22:10:23.254462 ==
1986 22:10:23.257529 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 22:10:23.260655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 22:10:23.260739 ==
1989 22:10:23.260855
1990 22:10:23.260933
1991 22:10:23.264498 TX Vref Scan disable
1992 22:10:23.267763 == TX Byte 0 ==
1993 22:10:23.270848 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1994 22:10:23.274198 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1995 22:10:23.277582 == TX Byte 1 ==
1996 22:10:23.281025 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1997 22:10:23.284430 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1998 22:10:23.284514 ==
1999 22:10:23.287611 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 22:10:23.290859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 22:10:23.290943 ==
2002 22:10:23.305668 TX Vref=22, minBit 13, minWin=27, winSum=452
2003 22:10:23.308605 TX Vref=24, minBit 13, minWin=27, winSum=454
2004 22:10:23.311897 TX Vref=26, minBit 13, minWin=27, winSum=455
2005 22:10:23.315272 TX Vref=28, minBit 13, minWin=27, winSum=456
2006 22:10:23.318586 TX Vref=30, minBit 15, minWin=27, winSum=458
2007 22:10:23.325853 TX Vref=32, minBit 15, minWin=27, winSum=459
2008 22:10:23.328580 [TxChooseVref] Worse bit 15, Min win 27, Win sum 459, Final Vref 32
2009 22:10:23.328669
2010 22:10:23.331826 Final TX Range 1 Vref 32
2011 22:10:23.331912
2012 22:10:23.331996 ==
2013 22:10:23.335269 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 22:10:23.338554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 22:10:23.341810 ==
2016 22:10:23.341894
2017 22:10:23.341976
2018 22:10:23.342054 TX Vref Scan disable
2019 22:10:23.345848 == TX Byte 0 ==
2020 22:10:23.349483 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2021 22:10:23.355917 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2022 22:10:23.356008 == TX Byte 1 ==
2023 22:10:23.358926 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2024 22:10:23.366099 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2025 22:10:23.366208
2026 22:10:23.366302 [DATLAT]
2027 22:10:23.366390 Freq=800, CH1 RK1
2028 22:10:23.366481
2029 22:10:23.369366 DATLAT Default: 0xa
2030 22:10:23.369447 0, 0xFFFF, sum = 0
2031 22:10:23.372553 1, 0xFFFF, sum = 0
2032 22:10:23.372694 2, 0xFFFF, sum = 0
2033 22:10:23.375934 3, 0xFFFF, sum = 0
2034 22:10:23.376046 4, 0xFFFF, sum = 0
2035 22:10:23.379230 5, 0xFFFF, sum = 0
2036 22:10:23.382429 6, 0xFFFF, sum = 0
2037 22:10:23.382512 7, 0xFFFF, sum = 0
2038 22:10:23.385955 8, 0xFFFF, sum = 0
2039 22:10:23.386038 9, 0x0, sum = 1
2040 22:10:23.386104 10, 0x0, sum = 2
2041 22:10:23.389115 11, 0x0, sum = 3
2042 22:10:23.389223 12, 0x0, sum = 4
2043 22:10:23.392574 best_step = 10
2044 22:10:23.392658
2045 22:10:23.392724 ==
2046 22:10:23.396300 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 22:10:23.399209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 22:10:23.399288 ==
2049 22:10:23.402979 RX Vref Scan: 0
2050 22:10:23.403061
2051 22:10:23.403125 RX Vref 0 -> 0, step: 1
2052 22:10:23.403186
2053 22:10:23.405947 RX Delay -95 -> 252, step: 8
2054 22:10:23.412546 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2055 22:10:23.416125 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2056 22:10:23.419467 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2057 22:10:23.422391 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2058 22:10:23.426063 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2059 22:10:23.432902 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2060 22:10:23.435661 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2061 22:10:23.439142 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2062 22:10:23.442467 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2063 22:10:23.445786 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2064 22:10:23.452660 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2065 22:10:23.456064 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2066 22:10:23.459243 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2067 22:10:23.462396 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2068 22:10:23.465831 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2069 22:10:23.472526 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2070 22:10:23.472669 ==
2071 22:10:23.475643 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 22:10:23.479350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 22:10:23.479433 ==
2074 22:10:23.479497 DQS Delay:
2075 22:10:23.482479 DQS0 = 0, DQS1 = 0
2076 22:10:23.482561 DQM Delay:
2077 22:10:23.486062 DQM0 = 92, DQM1 = 83
2078 22:10:23.486144 DQ Delay:
2079 22:10:23.489169 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2080 22:10:23.492675 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2081 22:10:23.495871 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2082 22:10:23.499135 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2083 22:10:23.499256
2084 22:10:23.499368
2085 22:10:23.506276 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2086 22:10:23.509036 CH1 RK1: MR19=606, MR18=3B11
2087 22:10:23.515867 CH1_RK1: MR19=0x606, MR18=0x3B11, DQSOSC=394, MR23=63, INC=95, DEC=63
2088 22:10:23.519442 [RxdqsGatingPostProcess] freq 800
2089 22:10:23.526204 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 22:10:23.526329 Pre-setting of DQS Precalculation
2091 22:10:23.533049 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 22:10:23.539317 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 22:10:23.546139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 22:10:23.546250
2095 22:10:23.546353
2096 22:10:23.549472 [Calibration Summary] 1600 Mbps
2097 22:10:23.552736 CH 0, Rank 0
2098 22:10:23.552859 SW Impedance : PASS
2099 22:10:23.556025 DUTY Scan : NO K
2100 22:10:23.559599 ZQ Calibration : PASS
2101 22:10:23.559754 Jitter Meter : NO K
2102 22:10:23.562599 CBT Training : PASS
2103 22:10:23.562721 Write leveling : PASS
2104 22:10:23.566066 RX DQS gating : PASS
2105 22:10:23.569633 RX DQ/DQS(RDDQC) : PASS
2106 22:10:23.569752 TX DQ/DQS : PASS
2107 22:10:23.572458 RX DATLAT : PASS
2108 22:10:23.576110 RX DQ/DQS(Engine): PASS
2109 22:10:23.576229 TX OE : NO K
2110 22:10:23.579812 All Pass.
2111 22:10:23.579915
2112 22:10:23.580007 CH 0, Rank 1
2113 22:10:23.582882 SW Impedance : PASS
2114 22:10:23.582978 DUTY Scan : NO K
2115 22:10:23.585992 ZQ Calibration : PASS
2116 22:10:23.589269 Jitter Meter : NO K
2117 22:10:23.589352 CBT Training : PASS
2118 22:10:23.592567 Write leveling : PASS
2119 22:10:23.596170 RX DQS gating : PASS
2120 22:10:23.596253 RX DQ/DQS(RDDQC) : PASS
2121 22:10:23.599532 TX DQ/DQS : PASS
2122 22:10:23.599615 RX DATLAT : PASS
2123 22:10:23.602775 RX DQ/DQS(Engine): PASS
2124 22:10:23.606129 TX OE : NO K
2125 22:10:23.606211 All Pass.
2126 22:10:23.606276
2127 22:10:23.606336 CH 1, Rank 0
2128 22:10:23.609553 SW Impedance : PASS
2129 22:10:23.612665 DUTY Scan : NO K
2130 22:10:23.612748 ZQ Calibration : PASS
2131 22:10:23.616120 Jitter Meter : NO K
2132 22:10:23.619681 CBT Training : PASS
2133 22:10:23.619762 Write leveling : PASS
2134 22:10:23.623101 RX DQS gating : PASS
2135 22:10:23.626020 RX DQ/DQS(RDDQC) : PASS
2136 22:10:23.626116 TX DQ/DQS : PASS
2137 22:10:23.629628 RX DATLAT : PASS
2138 22:10:23.633579 RX DQ/DQS(Engine): PASS
2139 22:10:23.633660 TX OE : NO K
2140 22:10:23.633726 All Pass.
2141 22:10:23.633786
2142 22:10:23.636146 CH 1, Rank 1
2143 22:10:23.636227 SW Impedance : PASS
2144 22:10:23.639852 DUTY Scan : NO K
2145 22:10:23.643104 ZQ Calibration : PASS
2146 22:10:23.643186 Jitter Meter : NO K
2147 22:10:23.646651 CBT Training : PASS
2148 22:10:23.649586 Write leveling : PASS
2149 22:10:23.649669 RX DQS gating : PASS
2150 22:10:23.652864 RX DQ/DQS(RDDQC) : PASS
2151 22:10:23.656253 TX DQ/DQS : PASS
2152 22:10:23.656356 RX DATLAT : PASS
2153 22:10:23.660019 RX DQ/DQS(Engine): PASS
2154 22:10:23.663450 TX OE : NO K
2155 22:10:23.663529 All Pass.
2156 22:10:23.663594
2157 22:10:23.663670 DramC Write-DBI off
2158 22:10:23.666469 PER_BANK_REFRESH: Hybrid Mode
2159 22:10:23.669723 TX_TRACKING: ON
2160 22:10:23.673119 [GetDramInforAfterCalByMRR] Vendor 6.
2161 22:10:23.676509 [GetDramInforAfterCalByMRR] Revision 606.
2162 22:10:23.679954 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 22:10:23.680028 MR0 0x3b3b
2164 22:10:23.683063 MR8 0x5151
2165 22:10:23.686362 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 22:10:23.686430
2167 22:10:23.686496 MR0 0x3b3b
2168 22:10:23.686557 MR8 0x5151
2169 22:10:23.689678 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 22:10:23.689760
2171 22:10:23.699754 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 22:10:23.703408 [FAST_K] Save calibration result to emmc
2173 22:10:23.706674 [FAST_K] Save calibration result to emmc
2174 22:10:23.709750 dram_init: config_dvfs: 1
2175 22:10:23.713256 dramc_set_vcore_voltage set vcore to 662500
2176 22:10:23.716584 Read voltage for 1200, 2
2177 22:10:23.716707 Vio18 = 0
2178 22:10:23.716829 Vcore = 662500
2179 22:10:23.720143 Vdram = 0
2180 22:10:23.720262 Vddq = 0
2181 22:10:23.720372 Vmddr = 0
2182 22:10:23.726452 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 22:10:23.730408 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 22:10:23.733181 MEM_TYPE=3, freq_sel=15
2185 22:10:23.736325 sv_algorithm_assistance_LP4_1600
2186 22:10:23.739810 ============ PULL DRAM RESETB DOWN ============
2187 22:10:23.743577 ========== PULL DRAM RESETB DOWN end =========
2188 22:10:23.750038 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 22:10:23.753408 ===================================
2190 22:10:23.757109 LPDDR4 DRAM CONFIGURATION
2191 22:10:23.760061 ===================================
2192 22:10:23.760167 EX_ROW_EN[0] = 0x0
2193 22:10:23.763607 EX_ROW_EN[1] = 0x0
2194 22:10:23.763688 LP4Y_EN = 0x0
2195 22:10:23.766794 WORK_FSP = 0x0
2196 22:10:23.766891 WL = 0x4
2197 22:10:23.770034 RL = 0x4
2198 22:10:23.770117 BL = 0x2
2199 22:10:23.773664 RPST = 0x0
2200 22:10:23.773746 RD_PRE = 0x0
2201 22:10:23.776675 WR_PRE = 0x1
2202 22:10:23.776766 WR_PST = 0x0
2203 22:10:23.780293 DBI_WR = 0x0
2204 22:10:23.780375 DBI_RD = 0x0
2205 22:10:23.783740 OTF = 0x1
2206 22:10:23.786906 ===================================
2207 22:10:23.790200 ===================================
2208 22:10:23.790323 ANA top config
2209 22:10:23.793818 ===================================
2210 22:10:23.796821 DLL_ASYNC_EN = 0
2211 22:10:23.800073 ALL_SLAVE_EN = 0
2212 22:10:23.803547 NEW_RANK_MODE = 1
2213 22:10:23.803645 DLL_IDLE_MODE = 1
2214 22:10:23.806726 LP45_APHY_COMB_EN = 1
2215 22:10:23.810008 TX_ODT_DIS = 1
2216 22:10:23.813583 NEW_8X_MODE = 1
2217 22:10:23.816827 ===================================
2218 22:10:23.820627 ===================================
2219 22:10:23.820731 data_rate = 2400
2220 22:10:23.823644 CKR = 1
2221 22:10:23.827304 DQ_P2S_RATIO = 8
2222 22:10:23.830333 ===================================
2223 22:10:23.833856 CA_P2S_RATIO = 8
2224 22:10:23.837218 DQ_CA_OPEN = 0
2225 22:10:23.840240 DQ_SEMI_OPEN = 0
2226 22:10:23.840352 CA_SEMI_OPEN = 0
2227 22:10:23.843757 CA_FULL_RATE = 0
2228 22:10:23.846982 DQ_CKDIV4_EN = 0
2229 22:10:23.850520 CA_CKDIV4_EN = 0
2230 22:10:23.853639 CA_PREDIV_EN = 0
2231 22:10:23.856879 PH8_DLY = 17
2232 22:10:23.856964 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 22:10:23.860590 DQ_AAMCK_DIV = 4
2234 22:10:23.863659 CA_AAMCK_DIV = 4
2235 22:10:23.866883 CA_ADMCK_DIV = 4
2236 22:10:23.870281 DQ_TRACK_CA_EN = 0
2237 22:10:23.873594 CA_PICK = 1200
2238 22:10:23.877078 CA_MCKIO = 1200
2239 22:10:23.877161 MCKIO_SEMI = 0
2240 22:10:23.880460 PLL_FREQ = 2366
2241 22:10:23.883879 DQ_UI_PI_RATIO = 32
2242 22:10:23.887407 CA_UI_PI_RATIO = 0
2243 22:10:23.890757 ===================================
2244 22:10:23.893918 ===================================
2245 22:10:23.897245 memory_type:LPDDR4
2246 22:10:23.897327 GP_NUM : 10
2247 22:10:23.900986 SRAM_EN : 1
2248 22:10:23.901068 MD32_EN : 0
2249 22:10:23.903957 ===================================
2250 22:10:23.907300 [ANA_INIT] >>>>>>>>>>>>>>
2251 22:10:23.910691 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 22:10:23.914110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 22:10:23.917447 ===================================
2254 22:10:23.920696 data_rate = 2400,PCW = 0X5b00
2255 22:10:23.924648 ===================================
2256 22:10:23.927483 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 22:10:23.930943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 22:10:23.937542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 22:10:23.940676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 22:10:23.944452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 22:10:23.947748 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 22:10:23.951325 [ANA_INIT] flow start
2263 22:10:23.954551 [ANA_INIT] PLL >>>>>>>>
2264 22:10:23.954633 [ANA_INIT] PLL <<<<<<<<
2265 22:10:23.957638 [ANA_INIT] MIDPI >>>>>>>>
2266 22:10:23.960822 [ANA_INIT] MIDPI <<<<<<<<
2267 22:10:23.964423 [ANA_INIT] DLL >>>>>>>>
2268 22:10:23.964505 [ANA_INIT] DLL <<<<<<<<
2269 22:10:23.967468 [ANA_INIT] flow end
2270 22:10:23.971099 ============ LP4 DIFF to SE enter ============
2271 22:10:23.974414 ============ LP4 DIFF to SE exit ============
2272 22:10:23.977591 [ANA_INIT] <<<<<<<<<<<<<
2273 22:10:23.981027 [Flow] Enable top DCM control >>>>>
2274 22:10:23.984715 [Flow] Enable top DCM control <<<<<
2275 22:10:23.987604 Enable DLL master slave shuffle
2276 22:10:23.991022 ==============================================================
2277 22:10:23.994260 Gating Mode config
2278 22:10:24.001267 ==============================================================
2279 22:10:24.001350 Config description:
2280 22:10:24.011038 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 22:10:24.017575 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 22:10:24.020948 SELPH_MODE 0: By rank 1: By Phase
2283 22:10:24.027614 ==============================================================
2284 22:10:24.031183 GAT_TRACK_EN = 1
2285 22:10:24.034180 RX_GATING_MODE = 2
2286 22:10:24.037849 RX_GATING_TRACK_MODE = 2
2287 22:10:24.040972 SELPH_MODE = 1
2288 22:10:24.044251 PICG_EARLY_EN = 1
2289 22:10:24.047800 VALID_LAT_VALUE = 1
2290 22:10:24.051033 ==============================================================
2291 22:10:24.054408 Enter into Gating configuration >>>>
2292 22:10:24.057668 Exit from Gating configuration <<<<
2293 22:10:24.061068 Enter into DVFS_PRE_config >>>>>
2294 22:10:24.071120 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 22:10:24.074811 Exit from DVFS_PRE_config <<<<<
2296 22:10:24.078065 Enter into PICG configuration >>>>
2297 22:10:24.081352 Exit from PICG configuration <<<<
2298 22:10:24.084946 [RX_INPUT] configuration >>>>>
2299 22:10:24.088104 [RX_INPUT] configuration <<<<<
2300 22:10:24.091660 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 22:10:24.097864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 22:10:24.104568 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 22:10:24.111380 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 22:10:24.117889 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 22:10:24.124659 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 22:10:24.127927 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 22:10:24.131411 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 22:10:24.134483 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 22:10:24.137849 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 22:10:24.144641 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 22:10:24.147873 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 22:10:24.151742 ===================================
2313 22:10:24.154999 LPDDR4 DRAM CONFIGURATION
2314 22:10:24.158645 ===================================
2315 22:10:24.158728 EX_ROW_EN[0] = 0x0
2316 22:10:24.161612 EX_ROW_EN[1] = 0x0
2317 22:10:24.161694 LP4Y_EN = 0x0
2318 22:10:24.164897 WORK_FSP = 0x0
2319 22:10:24.164978 WL = 0x4
2320 22:10:24.167892 RL = 0x4
2321 22:10:24.167974 BL = 0x2
2322 22:10:24.171464 RPST = 0x0
2323 22:10:24.171546 RD_PRE = 0x0
2324 22:10:24.174521 WR_PRE = 0x1
2325 22:10:24.174603 WR_PST = 0x0
2326 22:10:24.178284 DBI_WR = 0x0
2327 22:10:24.181436 DBI_RD = 0x0
2328 22:10:24.181518 OTF = 0x1
2329 22:10:24.184642 ===================================
2330 22:10:24.188336 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 22:10:24.191453 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 22:10:24.197957 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 22:10:24.201507 ===================================
2334 22:10:24.201588 LPDDR4 DRAM CONFIGURATION
2335 22:10:24.204775 ===================================
2336 22:10:24.208137 EX_ROW_EN[0] = 0x10
2337 22:10:24.211584 EX_ROW_EN[1] = 0x0
2338 22:10:24.211666 LP4Y_EN = 0x0
2339 22:10:24.214809 WORK_FSP = 0x0
2340 22:10:24.214890 WL = 0x4
2341 22:10:24.218455 RL = 0x4
2342 22:10:24.218536 BL = 0x2
2343 22:10:24.221551 RPST = 0x0
2344 22:10:24.221632 RD_PRE = 0x0
2345 22:10:24.224676 WR_PRE = 0x1
2346 22:10:24.224761 WR_PST = 0x0
2347 22:10:24.228445 DBI_WR = 0x0
2348 22:10:24.228526 DBI_RD = 0x0
2349 22:10:24.231342 OTF = 0x1
2350 22:10:24.235248 ===================================
2351 22:10:24.241840 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 22:10:24.241920 ==
2353 22:10:24.245103 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 22:10:24.248577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 22:10:24.248658 ==
2356 22:10:24.251842 [Duty_Offset_Calibration]
2357 22:10:24.251908 B0:2 B1:0 CA:1
2358 22:10:24.251967
2359 22:10:24.255104 [DutyScan_Calibration_Flow] k_type=0
2360 22:10:24.264356
2361 22:10:24.264434 ==CLK 0==
2362 22:10:24.267495 Final CLK duty delay cell = -4
2363 22:10:24.271096 [-4] MAX Duty = 5062%(X100), DQS PI = 22
2364 22:10:24.274240 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2365 22:10:24.278104 [-4] AVG Duty = 4968%(X100)
2366 22:10:24.278183
2367 22:10:24.281002 CH0 CLK Duty spec in!! Max-Min= 187%
2368 22:10:24.284416 [DutyScan_Calibration_Flow] ====Done====
2369 22:10:24.284495
2370 22:10:24.287906 [DutyScan_Calibration_Flow] k_type=1
2371 22:10:24.302954
2372 22:10:24.303034 ==DQS 0 ==
2373 22:10:24.306503 Final DQS duty delay cell = 0
2374 22:10:24.309920 [0] MAX Duty = 5187%(X100), DQS PI = 30
2375 22:10:24.313344 [0] MIN Duty = 4938%(X100), DQS PI = 0
2376 22:10:24.313423 [0] AVG Duty = 5062%(X100)
2377 22:10:24.316612
2378 22:10:24.316726 ==DQS 1 ==
2379 22:10:24.320091 Final DQS duty delay cell = -4
2380 22:10:24.323016 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2381 22:10:24.326531 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2382 22:10:24.329607 [-4] AVG Duty = 5031%(X100)
2383 22:10:24.329686
2384 22:10:24.333448 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2385 22:10:24.333528
2386 22:10:24.336632 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2387 22:10:24.339871 [DutyScan_Calibration_Flow] ====Done====
2388 22:10:24.339952
2389 22:10:24.342973 [DutyScan_Calibration_Flow] k_type=3
2390 22:10:24.359743
2391 22:10:24.359823 ==DQM 0 ==
2392 22:10:24.363420 Final DQM duty delay cell = 0
2393 22:10:24.366664 [0] MAX Duty = 5062%(X100), DQS PI = 24
2394 22:10:24.369943 [0] MIN Duty = 4813%(X100), DQS PI = 2
2395 22:10:24.370022 [0] AVG Duty = 4937%(X100)
2396 22:10:24.373128
2397 22:10:24.373222 ==DQM 1 ==
2398 22:10:24.376587 Final DQM duty delay cell = 0
2399 22:10:24.380495 [0] MAX Duty = 5187%(X100), DQS PI = 48
2400 22:10:24.383508 [0] MIN Duty = 5000%(X100), DQS PI = 12
2401 22:10:24.383667 [0] AVG Duty = 5093%(X100)
2402 22:10:24.386640
2403 22:10:24.389878 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2404 22:10:24.389959
2405 22:10:24.393443 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2406 22:10:24.396850 [DutyScan_Calibration_Flow] ====Done====
2407 22:10:24.396931
2408 22:10:24.400154 [DutyScan_Calibration_Flow] k_type=2
2409 22:10:24.416395
2410 22:10:24.416534 ==DQ 0 ==
2411 22:10:24.419576 Final DQ duty delay cell = -4
2412 22:10:24.423179 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2413 22:10:24.426252 [-4] MIN Duty = 4844%(X100), DQS PI = 16
2414 22:10:24.429803 [-4] AVG Duty = 4937%(X100)
2415 22:10:24.429911
2416 22:10:24.430066 ==DQ 1 ==
2417 22:10:24.433307 Final DQ duty delay cell = 4
2418 22:10:24.436502 [4] MAX Duty = 5093%(X100), DQS PI = 4
2419 22:10:24.439636 [4] MIN Duty = 5031%(X100), DQS PI = 0
2420 22:10:24.439734 [4] AVG Duty = 5062%(X100)
2421 22:10:24.443058
2422 22:10:24.446615 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2423 22:10:24.446717
2424 22:10:24.449863 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2425 22:10:24.453197 [DutyScan_Calibration_Flow] ====Done====
2426 22:10:24.453298 ==
2427 22:10:24.456829 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 22:10:24.459880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 22:10:24.459984 ==
2430 22:10:24.463219 [Duty_Offset_Calibration]
2431 22:10:24.463323 B0:0 B1:-1 CA:2
2432 22:10:24.463412
2433 22:10:24.466412 [DutyScan_Calibration_Flow] k_type=0
2434 22:10:24.476627
2435 22:10:24.476725 ==CLK 0==
2436 22:10:24.479629 Final CLK duty delay cell = 0
2437 22:10:24.483481 [0] MAX Duty = 5156%(X100), DQS PI = 16
2438 22:10:24.486322 [0] MIN Duty = 4938%(X100), DQS PI = 44
2439 22:10:24.486420 [0] AVG Duty = 5047%(X100)
2440 22:10:24.489846
2441 22:10:24.493203 CH1 CLK Duty spec in!! Max-Min= 218%
2442 22:10:24.496853 [DutyScan_Calibration_Flow] ====Done====
2443 22:10:24.496931
2444 22:10:24.499641 [DutyScan_Calibration_Flow] k_type=1
2445 22:10:24.515837
2446 22:10:24.515941 ==DQS 0 ==
2447 22:10:24.519146 Final DQS duty delay cell = 0
2448 22:10:24.522410 [0] MAX Duty = 5093%(X100), DQS PI = 24
2449 22:10:24.525886 [0] MIN Duty = 4969%(X100), DQS PI = 0
2450 22:10:24.525990 [0] AVG Duty = 5031%(X100)
2451 22:10:24.529253
2452 22:10:24.529358 ==DQS 1 ==
2453 22:10:24.532549 Final DQS duty delay cell = 0
2454 22:10:24.535965 [0] MAX Duty = 5156%(X100), DQS PI = 0
2455 22:10:24.539210 [0] MIN Duty = 4813%(X100), DQS PI = 36
2456 22:10:24.539313 [0] AVG Duty = 4984%(X100)
2457 22:10:24.539414
2458 22:10:24.545828 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2459 22:10:24.545935
2460 22:10:24.549238 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2461 22:10:24.552523 [DutyScan_Calibration_Flow] ====Done====
2462 22:10:24.552622
2463 22:10:24.555911 [DutyScan_Calibration_Flow] k_type=3
2464 22:10:24.573383
2465 22:10:24.573491 ==DQM 0 ==
2466 22:10:24.576694 Final DQM duty delay cell = 4
2467 22:10:24.579818 [4] MAX Duty = 5093%(X100), DQS PI = 20
2468 22:10:24.583175 [4] MIN Duty = 4938%(X100), DQS PI = 48
2469 22:10:24.583258 [4] AVG Duty = 5015%(X100)
2470 22:10:24.586594
2471 22:10:24.586676 ==DQM 1 ==
2472 22:10:24.590255 Final DQM duty delay cell = 0
2473 22:10:24.593474 [0] MAX Duty = 5249%(X100), DQS PI = 0
2474 22:10:24.596844 [0] MIN Duty = 4907%(X100), DQS PI = 36
2475 22:10:24.596926 [0] AVG Duty = 5078%(X100)
2476 22:10:24.596992
2477 22:10:24.603357 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2478 22:10:24.603440
2479 22:10:24.606643 CH1 DQM 1 Duty spec in!! Max-Min= 342%
2480 22:10:24.610056 [DutyScan_Calibration_Flow] ====Done====
2481 22:10:24.610184
2482 22:10:24.613169 [DutyScan_Calibration_Flow] k_type=2
2483 22:10:24.630181
2484 22:10:24.630264 ==DQ 0 ==
2485 22:10:24.632926 Final DQ duty delay cell = 0
2486 22:10:24.636573 [0] MAX Duty = 5062%(X100), DQS PI = 20
2487 22:10:24.639637 [0] MIN Duty = 4938%(X100), DQS PI = 46
2488 22:10:24.639720 [0] AVG Duty = 5000%(X100)
2489 22:10:24.639786
2490 22:10:24.642914 ==DQ 1 ==
2491 22:10:24.646483 Final DQ duty delay cell = 0
2492 22:10:24.649770 [0] MAX Duty = 5062%(X100), DQS PI = 4
2493 22:10:24.653053 [0] MIN Duty = 4813%(X100), DQS PI = 34
2494 22:10:24.653136 [0] AVG Duty = 4937%(X100)
2495 22:10:24.653202
2496 22:10:24.656577 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2497 22:10:24.656676
2498 22:10:24.659817 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2499 22:10:24.666645 [DutyScan_Calibration_Flow] ====Done====
2500 22:10:24.669798 nWR fixed to 30
2501 22:10:24.669882 [ModeRegInit_LP4] CH0 RK0
2502 22:10:24.673043 [ModeRegInit_LP4] CH0 RK1
2503 22:10:24.676843 [ModeRegInit_LP4] CH1 RK0
2504 22:10:24.676924 [ModeRegInit_LP4] CH1 RK1
2505 22:10:24.679817 match AC timing 7
2506 22:10:24.683368 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 22:10:24.686474 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 22:10:24.693700 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 22:10:24.696598 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 22:10:24.703557 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 22:10:24.703638 ==
2512 22:10:24.706705 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 22:10:24.710098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 22:10:24.710196 ==
2515 22:10:24.716787 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 22:10:24.719855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2517 22:10:24.729677 [CA 0] Center 38 (7~69) winsize 63
2518 22:10:24.733152 [CA 1] Center 38 (8~69) winsize 62
2519 22:10:24.736468 [CA 2] Center 34 (4~65) winsize 62
2520 22:10:24.739617 [CA 3] Center 34 (4~65) winsize 62
2521 22:10:24.742729 [CA 4] Center 34 (4~64) winsize 61
2522 22:10:24.746739 [CA 5] Center 33 (3~64) winsize 62
2523 22:10:24.746838
2524 22:10:24.749452 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2525 22:10:24.749536
2526 22:10:24.753092 [CATrainingPosCal] consider 1 rank data
2527 22:10:24.756134 u2DelayCellTimex100 = 270/100 ps
2528 22:10:24.759635 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2529 22:10:24.762942 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2530 22:10:24.769672 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
2531 22:10:24.772947 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2532 22:10:24.776120 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2533 22:10:24.779535 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2534 22:10:24.779659
2535 22:10:24.782893 CA PerBit enable=1, Macro0, CA PI delay=33
2536 22:10:24.783015
2537 22:10:24.786470 [CBTSetCACLKResult] CA Dly = 33
2538 22:10:24.786593 CS Dly: 6 (0~37)
2539 22:10:24.786710 ==
2540 22:10:24.789544 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 22:10:24.796450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 22:10:24.796573 ==
2543 22:10:24.799991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 22:10:24.806160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2545 22:10:24.815257 [CA 0] Center 39 (8~70) winsize 63
2546 22:10:24.818854 [CA 1] Center 38 (8~69) winsize 62
2547 22:10:24.822049 [CA 2] Center 35 (5~66) winsize 62
2548 22:10:24.825321 [CA 3] Center 35 (5~66) winsize 62
2549 22:10:24.828624 [CA 4] Center 34 (4~65) winsize 62
2550 22:10:24.831814 [CA 5] Center 34 (4~64) winsize 61
2551 22:10:24.831937
2552 22:10:24.835280 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2553 22:10:24.835403
2554 22:10:24.838876 [CATrainingPosCal] consider 2 rank data
2555 22:10:24.841866 u2DelayCellTimex100 = 270/100 ps
2556 22:10:24.845167 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2557 22:10:24.848500 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2558 22:10:24.851909 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
2559 22:10:24.858862 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
2560 22:10:24.861865 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
2561 22:10:24.865114 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2562 22:10:24.865238
2563 22:10:24.868724 CA PerBit enable=1, Macro0, CA PI delay=34
2564 22:10:24.868882
2565 22:10:24.871956 [CBTSetCACLKResult] CA Dly = 34
2566 22:10:24.872078 CS Dly: 7 (0~39)
2567 22:10:24.872193
2568 22:10:24.875217 ----->DramcWriteLeveling(PI) begin...
2569 22:10:24.875339 ==
2570 22:10:24.878704 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 22:10:24.885843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 22:10:24.885967 ==
2573 22:10:24.888730 Write leveling (Byte 0): 34 => 34
2574 22:10:24.892002 Write leveling (Byte 1): 30 => 30
2575 22:10:24.892124 DramcWriteLeveling(PI) end<-----
2576 22:10:24.895310
2577 22:10:24.895427 ==
2578 22:10:24.899306 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 22:10:24.901903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 22:10:24.902025 ==
2581 22:10:24.905609 [Gating] SW mode calibration
2582 22:10:24.912235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 22:10:24.915291 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 22:10:24.921957 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2585 22:10:24.925242 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2586 22:10:24.928707 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 22:10:24.935497 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 22:10:24.938805 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 22:10:24.942117 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 22:10:24.948898 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2591 22:10:24.952149 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2592 22:10:24.955495 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2593 22:10:24.961970 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 22:10:24.965146 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 22:10:24.968588 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 22:10:24.975469 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 22:10:24.978762 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 22:10:24.981884 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2599 22:10:24.985756 1 0 28 | B1->B0 | 2525 4545 | 1 1 | (0 0) (0 0)
2600 22:10:24.991975 1 1 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
2601 22:10:24.995265 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 22:10:24.998614 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 22:10:25.005428 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 22:10:25.008892 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 22:10:25.012236 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 22:10:25.018869 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 22:10:25.022125 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 22:10:25.025361 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 22:10:25.032120 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2610 22:10:25.035448 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 22:10:25.038874 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 22:10:25.045511 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 22:10:25.048869 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 22:10:25.052227 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 22:10:25.055607 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 22:10:25.062550 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 22:10:25.065671 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 22:10:25.069125 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 22:10:25.075935 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 22:10:25.079168 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 22:10:25.082512 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 22:10:25.089132 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2623 22:10:25.092595 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 22:10:25.095648 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2625 22:10:25.098954 Total UI for P1: 0, mck2ui 16
2626 22:10:25.102540 best dqsien dly found for B0: ( 1, 3, 26)
2627 22:10:25.109124 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 22:10:25.109206 Total UI for P1: 0, mck2ui 16
2629 22:10:25.112579 best dqsien dly found for B1: ( 1, 4, 0)
2630 22:10:25.119225 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2631 22:10:25.122449 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2632 22:10:25.122532
2633 22:10:25.126087 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2634 22:10:25.129146 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2635 22:10:25.132630 [Gating] SW calibration Done
2636 22:10:25.132756 ==
2637 22:10:25.136044 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 22:10:25.139357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 22:10:25.139456 ==
2640 22:10:25.139547 RX Vref Scan: 0
2641 22:10:25.139641
2642 22:10:25.142655 RX Vref 0 -> 0, step: 1
2643 22:10:25.142756
2644 22:10:25.146180 RX Delay -40 -> 252, step: 8
2645 22:10:25.149383 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2646 22:10:25.152999 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2647 22:10:25.159743 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2648 22:10:25.163039 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2649 22:10:25.166442 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2650 22:10:25.169718 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2651 22:10:25.172671 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2652 22:10:25.176135 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2653 22:10:25.182831 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2654 22:10:25.186280 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2655 22:10:25.189490 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2656 22:10:25.193276 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2657 22:10:25.196245 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2658 22:10:25.203145 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2659 22:10:25.206153 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2660 22:10:25.209704 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2661 22:10:25.209787 ==
2662 22:10:25.212909 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 22:10:25.216348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 22:10:25.216431 ==
2665 22:10:25.219634 DQS Delay:
2666 22:10:25.219765 DQS0 = 0, DQS1 = 0
2667 22:10:25.223048 DQM Delay:
2668 22:10:25.223148 DQM0 = 122, DQM1 = 111
2669 22:10:25.226678 DQ Delay:
2670 22:10:25.229418 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2671 22:10:25.233303 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2672 22:10:25.236037 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2673 22:10:25.239373 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =119
2674 22:10:25.239487
2675 22:10:25.239584
2676 22:10:25.239675 ==
2677 22:10:25.242886 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 22:10:25.246916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 22:10:25.246998 ==
2680 22:10:25.247063
2681 22:10:25.247122
2682 22:10:25.249567 TX Vref Scan disable
2683 22:10:25.252712 == TX Byte 0 ==
2684 22:10:25.256392 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2685 22:10:25.259562 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2686 22:10:25.263010 == TX Byte 1 ==
2687 22:10:25.266258 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2688 22:10:25.269636 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2689 22:10:25.269718 ==
2690 22:10:25.273041 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 22:10:25.276375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 22:10:25.279581 ==
2693 22:10:25.290325 TX Vref=22, minBit 0, minWin=24, winSum=408
2694 22:10:25.293369 TX Vref=24, minBit 7, minWin=24, winSum=411
2695 22:10:25.296612 TX Vref=26, minBit 0, minWin=25, winSum=418
2696 22:10:25.299959 TX Vref=28, minBit 0, minWin=25, winSum=423
2697 22:10:25.303411 TX Vref=30, minBit 3, minWin=25, winSum=422
2698 22:10:25.306811 TX Vref=32, minBit 7, minWin=24, winSum=420
2699 22:10:25.313192 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
2700 22:10:25.313276
2701 22:10:25.316696 Final TX Range 1 Vref 28
2702 22:10:25.316830
2703 22:10:25.316896 ==
2704 22:10:25.319987 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 22:10:25.323248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 22:10:25.323331 ==
2707 22:10:25.323418
2708 22:10:25.323513
2709 22:10:25.326732 TX Vref Scan disable
2710 22:10:25.330132 == TX Byte 0 ==
2711 22:10:25.333375 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2712 22:10:25.336766 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2713 22:10:25.340298 == TX Byte 1 ==
2714 22:10:25.343326 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2715 22:10:25.346589 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2716 22:10:25.346727
2717 22:10:25.349980 [DATLAT]
2718 22:10:25.350066 Freq=1200, CH0 RK0
2719 22:10:25.350128
2720 22:10:25.353334 DATLAT Default: 0xd
2721 22:10:25.353428 0, 0xFFFF, sum = 0
2722 22:10:25.356624 1, 0xFFFF, sum = 0
2723 22:10:25.356709 2, 0xFFFF, sum = 0
2724 22:10:25.359951 3, 0xFFFF, sum = 0
2725 22:10:25.360022 4, 0xFFFF, sum = 0
2726 22:10:25.363290 5, 0xFFFF, sum = 0
2727 22:10:25.363368 6, 0xFFFF, sum = 0
2728 22:10:25.366996 7, 0xFFFF, sum = 0
2729 22:10:25.367078 8, 0xFFFF, sum = 0
2730 22:10:25.370348 9, 0xFFFF, sum = 0
2731 22:10:25.370424 10, 0xFFFF, sum = 0
2732 22:10:25.373418 11, 0xFFFF, sum = 0
2733 22:10:25.373494 12, 0x0, sum = 1
2734 22:10:25.376865 13, 0x0, sum = 2
2735 22:10:25.376980 14, 0x0, sum = 3
2736 22:10:25.380461 15, 0x0, sum = 4
2737 22:10:25.380583 best_step = 13
2738 22:10:25.380696
2739 22:10:25.380842 ==
2740 22:10:25.383725 Dram Type= 6, Freq= 0, CH_0, rank 0
2741 22:10:25.390449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2742 22:10:25.390580 ==
2743 22:10:25.390688 RX Vref Scan: 1
2744 22:10:25.390798
2745 22:10:25.393778 Set Vref Range= 32 -> 127
2746 22:10:25.393896
2747 22:10:25.397346 RX Vref 32 -> 127, step: 1
2748 22:10:25.397466
2749 22:10:25.397577 RX Delay -13 -> 252, step: 4
2750 22:10:25.400244
2751 22:10:25.400365 Set Vref, RX VrefLevel [Byte0]: 32
2752 22:10:25.403785 [Byte1]: 32
2753 22:10:25.408206
2754 22:10:25.408326 Set Vref, RX VrefLevel [Byte0]: 33
2755 22:10:25.411212 [Byte1]: 33
2756 22:10:25.415688
2757 22:10:25.415820 Set Vref, RX VrefLevel [Byte0]: 34
2758 22:10:25.419547 [Byte1]: 34
2759 22:10:25.423744
2760 22:10:25.423862 Set Vref, RX VrefLevel [Byte0]: 35
2761 22:10:25.427673 [Byte1]: 35
2762 22:10:25.431618
2763 22:10:25.431739 Set Vref, RX VrefLevel [Byte0]: 36
2764 22:10:25.435243 [Byte1]: 36
2765 22:10:25.439463
2766 22:10:25.439581 Set Vref, RX VrefLevel [Byte0]: 37
2767 22:10:25.443113 [Byte1]: 37
2768 22:10:25.447742
2769 22:10:25.447862 Set Vref, RX VrefLevel [Byte0]: 38
2770 22:10:25.451193 [Byte1]: 38
2771 22:10:25.455460
2772 22:10:25.455582 Set Vref, RX VrefLevel [Byte0]: 39
2773 22:10:25.458548 [Byte1]: 39
2774 22:10:25.463382
2775 22:10:25.463479 Set Vref, RX VrefLevel [Byte0]: 40
2776 22:10:25.466654 [Byte1]: 40
2777 22:10:25.471177
2778 22:10:25.471259 Set Vref, RX VrefLevel [Byte0]: 41
2779 22:10:25.474628 [Byte1]: 41
2780 22:10:25.478886
2781 22:10:25.478967 Set Vref, RX VrefLevel [Byte0]: 42
2782 22:10:25.482506 [Byte1]: 42
2783 22:10:25.486804
2784 22:10:25.486885 Set Vref, RX VrefLevel [Byte0]: 43
2785 22:10:25.490228 [Byte1]: 43
2786 22:10:25.495097
2787 22:10:25.495177 Set Vref, RX VrefLevel [Byte0]: 44
2788 22:10:25.498272 [Byte1]: 44
2789 22:10:25.502691
2790 22:10:25.502787 Set Vref, RX VrefLevel [Byte0]: 45
2791 22:10:25.505948 [Byte1]: 45
2792 22:10:25.511125
2793 22:10:25.511253 Set Vref, RX VrefLevel [Byte0]: 46
2794 22:10:25.513842 [Byte1]: 46
2795 22:10:25.518374
2796 22:10:25.518456 Set Vref, RX VrefLevel [Byte0]: 47
2797 22:10:25.522195 [Byte1]: 47
2798 22:10:25.526809
2799 22:10:25.526892 Set Vref, RX VrefLevel [Byte0]: 48
2800 22:10:25.529589 [Byte1]: 48
2801 22:10:25.534245
2802 22:10:25.534346 Set Vref, RX VrefLevel [Byte0]: 49
2803 22:10:25.537617 [Byte1]: 49
2804 22:10:25.542116
2805 22:10:25.542198 Set Vref, RX VrefLevel [Byte0]: 50
2806 22:10:25.545477 [Byte1]: 50
2807 22:10:25.550235
2808 22:10:25.550343 Set Vref, RX VrefLevel [Byte0]: 51
2809 22:10:25.553168 [Byte1]: 51
2810 22:10:25.558078
2811 22:10:25.558162 Set Vref, RX VrefLevel [Byte0]: 52
2812 22:10:25.561441 [Byte1]: 52
2813 22:10:25.565988
2814 22:10:25.566070 Set Vref, RX VrefLevel [Byte0]: 53
2815 22:10:25.569772 [Byte1]: 53
2816 22:10:25.573783
2817 22:10:25.573934 Set Vref, RX VrefLevel [Byte0]: 54
2818 22:10:25.577357 [Byte1]: 54
2819 22:10:25.581696
2820 22:10:25.581778 Set Vref, RX VrefLevel [Byte0]: 55
2821 22:10:25.585047 [Byte1]: 55
2822 22:10:25.589943
2823 22:10:25.590024 Set Vref, RX VrefLevel [Byte0]: 56
2824 22:10:25.592942 [Byte1]: 56
2825 22:10:25.597446
2826 22:10:25.597526 Set Vref, RX VrefLevel [Byte0]: 57
2827 22:10:25.600684 [Byte1]: 57
2828 22:10:25.605259
2829 22:10:25.605343 Set Vref, RX VrefLevel [Byte0]: 58
2830 22:10:25.608645 [Byte1]: 58
2831 22:10:25.613537
2832 22:10:25.613621 Set Vref, RX VrefLevel [Byte0]: 59
2833 22:10:25.616534 [Byte1]: 59
2834 22:10:25.621227
2835 22:10:25.621311 Set Vref, RX VrefLevel [Byte0]: 60
2836 22:10:25.624536 [Byte1]: 60
2837 22:10:25.629549
2838 22:10:25.629634 Set Vref, RX VrefLevel [Byte0]: 61
2839 22:10:25.632157 [Byte1]: 61
2840 22:10:25.636676
2841 22:10:25.636768 Set Vref, RX VrefLevel [Byte0]: 62
2842 22:10:25.640197 [Byte1]: 62
2843 22:10:25.644658
2844 22:10:25.644742 Set Vref, RX VrefLevel [Byte0]: 63
2845 22:10:25.647909 [Byte1]: 63
2846 22:10:25.652567
2847 22:10:25.652651 Set Vref, RX VrefLevel [Byte0]: 64
2848 22:10:25.655836 [Byte1]: 64
2849 22:10:25.660892
2850 22:10:25.661001 Set Vref, RX VrefLevel [Byte0]: 65
2851 22:10:25.663965 [Byte1]: 65
2852 22:10:25.668545
2853 22:10:25.668626 Set Vref, RX VrefLevel [Byte0]: 66
2854 22:10:25.671524 [Byte1]: 66
2855 22:10:25.676194
2856 22:10:25.676278 Set Vref, RX VrefLevel [Byte0]: 67
2857 22:10:25.679504 [Byte1]: 67
2858 22:10:25.684092
2859 22:10:25.684175 Set Vref, RX VrefLevel [Byte0]: 68
2860 22:10:25.687626 [Byte1]: 68
2861 22:10:25.691921
2862 22:10:25.692003 Set Vref, RX VrefLevel [Byte0]: 69
2863 22:10:25.695384 [Byte1]: 69
2864 22:10:25.699902
2865 22:10:25.699983 Final RX Vref Byte 0 = 61 to rank0
2866 22:10:25.703372 Final RX Vref Byte 1 = 51 to rank0
2867 22:10:25.706704 Final RX Vref Byte 0 = 61 to rank1
2868 22:10:25.709881 Final RX Vref Byte 1 = 51 to rank1==
2869 22:10:25.713383 Dram Type= 6, Freq= 0, CH_0, rank 0
2870 22:10:25.719909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 22:10:25.720006 ==
2872 22:10:25.720072 DQS Delay:
2873 22:10:25.720133 DQS0 = 0, DQS1 = 0
2874 22:10:25.723542 DQM Delay:
2875 22:10:25.723624 DQM0 = 122, DQM1 = 109
2876 22:10:25.726551 DQ Delay:
2877 22:10:25.730235 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2878 22:10:25.733464 DQ4 =126, DQ5 =116, DQ6 =128, DQ7 =128
2879 22:10:25.736406 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2880 22:10:25.739950 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2881 22:10:25.740048
2882 22:10:25.740129
2883 22:10:25.746449 [DQSOSCAuto] RK0, (LSB)MR18= 0xa07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2884 22:10:25.749902 CH0 RK0: MR19=404, MR18=A07
2885 22:10:25.756605 CH0_RK0: MR19=0x404, MR18=0xA07, DQSOSC=406, MR23=63, INC=39, DEC=26
2886 22:10:25.756729
2887 22:10:25.760038 ----->DramcWriteLeveling(PI) begin...
2888 22:10:25.760165 ==
2889 22:10:25.763333 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 22:10:25.766603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 22:10:25.766727 ==
2892 22:10:25.769849 Write leveling (Byte 0): 34 => 34
2893 22:10:25.773205 Write leveling (Byte 1): 29 => 29
2894 22:10:25.776843 DramcWriteLeveling(PI) end<-----
2895 22:10:25.776947
2896 22:10:25.777039 ==
2897 22:10:25.779909 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 22:10:25.783331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 22:10:25.786822 ==
2900 22:10:25.786906 [Gating] SW mode calibration
2901 22:10:25.793782 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2902 22:10:25.800080 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2903 22:10:25.803414 0 15 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2904 22:10:25.810126 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 22:10:25.813680 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 22:10:25.816717 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 22:10:25.823421 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 22:10:25.826998 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 22:10:25.830211 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2910 22:10:25.836669 0 15 28 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
2911 22:10:25.840442 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 22:10:25.843728 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 22:10:25.847272 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 22:10:25.853517 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 22:10:25.857358 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 22:10:25.860483 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 22:10:25.866977 1 0 24 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
2918 22:10:25.870323 1 0 28 | B1->B0 | 3232 3b3b | 0 1 | (0 0) (0 0)
2919 22:10:25.874035 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2920 22:10:25.880280 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 22:10:25.883825 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 22:10:25.887067 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 22:10:25.893581 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 22:10:25.897256 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 22:10:25.900423 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 22:10:25.907286 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2927 22:10:25.910340 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2928 22:10:25.913743 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 22:10:25.920338 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 22:10:25.923892 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 22:10:25.927151 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 22:10:25.930337 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 22:10:25.937067 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 22:10:25.940979 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 22:10:25.943907 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 22:10:25.950508 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 22:10:25.953751 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 22:10:25.957244 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 22:10:25.963723 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 22:10:25.967195 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 22:10:25.970501 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 22:10:25.977249 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2943 22:10:25.980824 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2944 22:10:25.983818 Total UI for P1: 0, mck2ui 16
2945 22:10:25.987461 best dqsien dly found for B1: ( 1, 3, 28)
2946 22:10:25.990337 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 22:10:25.993860 Total UI for P1: 0, mck2ui 16
2948 22:10:25.997105 best dqsien dly found for B0: ( 1, 3, 30)
2949 22:10:26.000634 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2950 22:10:26.003853 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2951 22:10:26.003935
2952 22:10:26.007333 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2953 22:10:26.014061 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2954 22:10:26.014144 [Gating] SW calibration Done
2955 22:10:26.014210 ==
2956 22:10:26.017429 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 22:10:26.023999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 22:10:26.024083 ==
2959 22:10:26.024149 RX Vref Scan: 0
2960 22:10:26.024210
2961 22:10:26.027842 RX Vref 0 -> 0, step: 1
2962 22:10:26.027925
2963 22:10:26.030828 RX Delay -40 -> 252, step: 8
2964 22:10:26.034209 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2965 22:10:26.038064 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2966 22:10:26.040688 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2967 22:10:26.044277 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2968 22:10:26.050823 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2969 22:10:26.054284 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2970 22:10:26.057628 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2971 22:10:26.061033 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2972 22:10:26.064151 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2973 22:10:26.070843 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2974 22:10:26.074245 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2975 22:10:26.077412 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2976 22:10:26.080878 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2977 22:10:26.084127 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2978 22:10:26.091024 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2979 22:10:26.094439 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2980 22:10:26.094557 ==
2981 22:10:26.097663 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 22:10:26.101014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 22:10:26.101097 ==
2984 22:10:26.101162 DQS Delay:
2985 22:10:26.104528 DQS0 = 0, DQS1 = 0
2986 22:10:26.104610 DQM Delay:
2987 22:10:26.107889 DQM0 = 120, DQM1 = 108
2988 22:10:26.107972 DQ Delay:
2989 22:10:26.110901 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2990 22:10:26.114341 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2991 22:10:26.117628 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2992 22:10:26.120929 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2993 22:10:26.124262
2994 22:10:26.124344
2995 22:10:26.124409 ==
2996 22:10:26.127636 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 22:10:26.130945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 22:10:26.131042 ==
2999 22:10:26.131107
3000 22:10:26.131168
3001 22:10:26.134471 TX Vref Scan disable
3002 22:10:26.134551 == TX Byte 0 ==
3003 22:10:26.141926 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3004 22:10:26.144485 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3005 22:10:26.144589 == TX Byte 1 ==
3006 22:10:26.147915 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3007 22:10:26.154577 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3008 22:10:26.154670 ==
3009 22:10:26.157850 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 22:10:26.161042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 22:10:26.161114 ==
3012 22:10:26.173420 TX Vref=22, minBit 1, minWin=24, winSum=411
3013 22:10:26.176883 TX Vref=24, minBit 0, minWin=24, winSum=414
3014 22:10:26.180111 TX Vref=26, minBit 1, minWin=24, winSum=420
3015 22:10:26.183409 TX Vref=28, minBit 1, minWin=25, winSum=420
3016 22:10:26.187147 TX Vref=30, minBit 1, minWin=25, winSum=423
3017 22:10:26.190356 TX Vref=32, minBit 1, minWin=25, winSum=418
3018 22:10:26.196885 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 30
3019 22:10:26.196963
3020 22:10:26.200353 Final TX Range 1 Vref 30
3021 22:10:26.200436
3022 22:10:26.200501 ==
3023 22:10:26.203406 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 22:10:26.206934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 22:10:26.207034 ==
3026 22:10:26.207133
3027 22:10:26.210403
3028 22:10:26.210485 TX Vref Scan disable
3029 22:10:26.213762 == TX Byte 0 ==
3030 22:10:26.216882 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3031 22:10:26.220295 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3032 22:10:26.223931 == TX Byte 1 ==
3033 22:10:26.227104 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3034 22:10:26.230676 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3035 22:10:26.230760
3036 22:10:26.234120 [DATLAT]
3037 22:10:26.234203 Freq=1200, CH0 RK1
3038 22:10:26.234270
3039 22:10:26.237062 DATLAT Default: 0xd
3040 22:10:26.237144 0, 0xFFFF, sum = 0
3041 22:10:26.240489 1, 0xFFFF, sum = 0
3042 22:10:26.240574 2, 0xFFFF, sum = 0
3043 22:10:26.243857 3, 0xFFFF, sum = 0
3044 22:10:26.243941 4, 0xFFFF, sum = 0
3045 22:10:26.247259 5, 0xFFFF, sum = 0
3046 22:10:26.247392 6, 0xFFFF, sum = 0
3047 22:10:26.250376 7, 0xFFFF, sum = 0
3048 22:10:26.250500 8, 0xFFFF, sum = 0
3049 22:10:26.253949 9, 0xFFFF, sum = 0
3050 22:10:26.254075 10, 0xFFFF, sum = 0
3051 22:10:26.257245 11, 0xFFFF, sum = 0
3052 22:10:26.257367 12, 0x0, sum = 1
3053 22:10:26.260413 13, 0x0, sum = 2
3054 22:10:26.260533 14, 0x0, sum = 3
3055 22:10:26.263707 15, 0x0, sum = 4
3056 22:10:26.263833 best_step = 13
3057 22:10:26.263942
3058 22:10:26.264055 ==
3059 22:10:26.267116 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 22:10:26.273742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 22:10:26.273843 ==
3062 22:10:26.273926 RX Vref Scan: 0
3063 22:10:26.274019
3064 22:10:26.277128 RX Vref 0 -> 0, step: 1
3065 22:10:26.277245
3066 22:10:26.280493 RX Delay -21 -> 252, step: 4
3067 22:10:26.283834 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3068 22:10:26.287085 iDelay=199, Bit 1, Center 122 (55 ~ 190) 136
3069 22:10:26.293774 iDelay=199, Bit 2, Center 118 (51 ~ 186) 136
3070 22:10:26.297027 iDelay=199, Bit 3, Center 114 (47 ~ 182) 136
3071 22:10:26.300321 iDelay=199, Bit 4, Center 122 (55 ~ 190) 136
3072 22:10:26.303749 iDelay=199, Bit 5, Center 114 (51 ~ 178) 128
3073 22:10:26.307075 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3074 22:10:26.313695 iDelay=199, Bit 7, Center 126 (59 ~ 194) 136
3075 22:10:26.317206 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3076 22:10:26.320273 iDelay=199, Bit 9, Center 96 (31 ~ 162) 132
3077 22:10:26.323703 iDelay=199, Bit 10, Center 110 (47 ~ 174) 128
3078 22:10:26.327377 iDelay=199, Bit 11, Center 104 (43 ~ 166) 124
3079 22:10:26.333989 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3080 22:10:26.337100 iDelay=199, Bit 13, Center 110 (47 ~ 174) 128
3081 22:10:26.340876 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3082 22:10:26.343807 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
3083 22:10:26.343891 ==
3084 22:10:26.347194 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 22:10:26.350800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 22:10:26.354143 ==
3087 22:10:26.354225 DQS Delay:
3088 22:10:26.354291 DQS0 = 0, DQS1 = 0
3089 22:10:26.357500 DQM Delay:
3090 22:10:26.357582 DQM0 = 120, DQM1 = 107
3091 22:10:26.360887 DQ Delay:
3092 22:10:26.364123 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3093 22:10:26.367497 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =126
3094 22:10:26.370779 DQ8 =98, DQ9 =96, DQ10 =110, DQ11 =104
3095 22:10:26.374034 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3096 22:10:26.374142
3097 22:10:26.374234
3098 22:10:26.381163 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3099 22:10:26.384501 CH0 RK1: MR19=403, MR18=CF3
3100 22:10:26.390864 CH0_RK1: MR19=0x403, MR18=0xCF3, DQSOSC=405, MR23=63, INC=39, DEC=26
3101 22:10:26.394293 [RxdqsGatingPostProcess] freq 1200
3102 22:10:26.397413 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3103 22:10:26.401085 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 22:10:26.404126 best DQS1 dly(2T, 0.5T) = (0, 12)
3105 22:10:26.407495 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 22:10:26.410850 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3107 22:10:26.414386 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 22:10:26.417608 best DQS1 dly(2T, 0.5T) = (0, 11)
3109 22:10:26.420647 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 22:10:26.424030 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3111 22:10:26.427718 Pre-setting of DQS Precalculation
3112 22:10:26.431075 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3113 22:10:26.431182 ==
3114 22:10:26.434281 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 22:10:26.440937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 22:10:26.441044 ==
3117 22:10:26.444365 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 22:10:26.450940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3119 22:10:26.459617 [CA 0] Center 37 (7~68) winsize 62
3120 22:10:26.462805 [CA 1] Center 37 (7~68) winsize 62
3121 22:10:26.466221 [CA 2] Center 35 (5~65) winsize 61
3122 22:10:26.469565 [CA 3] Center 34 (4~65) winsize 62
3123 22:10:26.472888 [CA 4] Center 34 (4~64) winsize 61
3124 22:10:26.476295 [CA 5] Center 33 (3~64) winsize 62
3125 22:10:26.476419
3126 22:10:26.479337 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3127 22:10:26.479457
3128 22:10:26.482746 [CATrainingPosCal] consider 1 rank data
3129 22:10:26.486057 u2DelayCellTimex100 = 270/100 ps
3130 22:10:26.489424 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 22:10:26.493240 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 22:10:26.499488 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3133 22:10:26.503050 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3134 22:10:26.506268 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 22:10:26.509700 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3136 22:10:26.509782
3137 22:10:26.513162 CA PerBit enable=1, Macro0, CA PI delay=33
3138 22:10:26.513250
3139 22:10:26.516331 [CBTSetCACLKResult] CA Dly = 33
3140 22:10:26.516430 CS Dly: 5 (0~36)
3141 22:10:26.516527 ==
3142 22:10:26.519375 Dram Type= 6, Freq= 0, CH_1, rank 1
3143 22:10:26.526247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 22:10:26.526334 ==
3145 22:10:26.529530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 22:10:26.536309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3147 22:10:26.545047 [CA 0] Center 38 (8~68) winsize 61
3148 22:10:26.548595 [CA 1] Center 38 (7~69) winsize 63
3149 22:10:26.552037 [CA 2] Center 35 (5~66) winsize 62
3150 22:10:26.555251 [CA 3] Center 35 (5~65) winsize 61
3151 22:10:26.558364 [CA 4] Center 35 (5~65) winsize 61
3152 22:10:26.561835 [CA 5] Center 34 (4~64) winsize 61
3153 22:10:26.561917
3154 22:10:26.565181 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3155 22:10:26.565265
3156 22:10:26.568418 [CATrainingPosCal] consider 2 rank data
3157 22:10:26.571742 u2DelayCellTimex100 = 270/100 ps
3158 22:10:26.575077 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3159 22:10:26.578538 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3160 22:10:26.585037 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3161 22:10:26.588556 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3162 22:10:26.592112 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3163 22:10:26.595576 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3164 22:10:26.595660
3165 22:10:26.598888 CA PerBit enable=1, Macro0, CA PI delay=34
3166 22:10:26.598972
3167 22:10:26.601989 [CBTSetCACLKResult] CA Dly = 34
3168 22:10:26.602074 CS Dly: 6 (0~39)
3169 22:10:26.602158
3170 22:10:26.605681 ----->DramcWriteLeveling(PI) begin...
3171 22:10:26.605783 ==
3172 22:10:26.608386 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 22:10:26.615271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 22:10:26.615381 ==
3175 22:10:26.618405 Write leveling (Byte 0): 25 => 25
3176 22:10:26.621942 Write leveling (Byte 1): 28 => 28
3177 22:10:26.622027 DramcWriteLeveling(PI) end<-----
3178 22:10:26.625218
3179 22:10:26.625301 ==
3180 22:10:26.628403 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 22:10:26.632336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 22:10:26.632420 ==
3183 22:10:26.635200 [Gating] SW mode calibration
3184 22:10:26.641928 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3185 22:10:26.645183 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3186 22:10:26.651869 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 22:10:26.655264 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 22:10:26.658797 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 22:10:26.665223 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 22:10:26.668475 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 22:10:26.671970 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3192 22:10:26.678760 0 15 24 | B1->B0 | 2d2d 2626 | 1 0 | (1 1) (0 0)
3193 22:10:26.682153 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3194 22:10:26.685562 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 22:10:26.691992 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 22:10:26.695436 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 22:10:26.698978 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 22:10:26.702029 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 22:10:26.708659 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3200 22:10:26.712340 1 0 24 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
3201 22:10:26.715527 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 22:10:26.722043 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 22:10:26.725477 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 22:10:26.728523 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 22:10:26.735784 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 22:10:26.738981 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 22:10:26.742536 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3208 22:10:26.749049 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3209 22:10:26.752517 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3210 22:10:26.755630 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 22:10:26.762584 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 22:10:26.766224 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 22:10:26.769009 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 22:10:26.772588 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 22:10:26.779195 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 22:10:26.782580 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 22:10:26.785725 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 22:10:26.793001 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 22:10:26.795732 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 22:10:26.799202 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 22:10:26.806098 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 22:10:26.809224 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 22:10:26.812884 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 22:10:26.819229 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 22:10:26.822709 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3226 22:10:26.826343 Total UI for P1: 0, mck2ui 16
3227 22:10:26.829310 best dqsien dly found for B0: ( 1, 3, 24)
3228 22:10:26.832741 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 22:10:26.835920 Total UI for P1: 0, mck2ui 16
3230 22:10:26.839495 best dqsien dly found for B1: ( 1, 3, 26)
3231 22:10:26.842909 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3232 22:10:26.846183 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3233 22:10:26.846265
3234 22:10:26.849572 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3235 22:10:26.856004 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3236 22:10:26.856087 [Gating] SW calibration Done
3237 22:10:26.856153 ==
3238 22:10:26.859713 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 22:10:26.866327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 22:10:26.866411 ==
3241 22:10:26.866476 RX Vref Scan: 0
3242 22:10:26.866536
3243 22:10:26.869600 RX Vref 0 -> 0, step: 1
3244 22:10:26.869682
3245 22:10:26.872940 RX Delay -40 -> 252, step: 8
3246 22:10:26.876137 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3247 22:10:26.880063 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3248 22:10:26.882812 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3249 22:10:26.886156 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3250 22:10:26.893003 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3251 22:10:26.896327 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3252 22:10:26.899776 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3253 22:10:26.903025 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3254 22:10:26.906127 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3255 22:10:26.912781 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3256 22:10:26.916096 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3257 22:10:26.919541 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3258 22:10:26.922969 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3259 22:10:26.926372 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3260 22:10:26.933435 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3261 22:10:26.936661 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3262 22:10:26.936823 ==
3263 22:10:26.939550 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 22:10:26.942924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 22:10:26.943051 ==
3266 22:10:26.943163 DQS Delay:
3267 22:10:26.946203 DQS0 = 0, DQS1 = 0
3268 22:10:26.946325 DQM Delay:
3269 22:10:26.949749 DQM0 = 120, DQM1 = 112
3270 22:10:26.949872 DQ Delay:
3271 22:10:26.953091 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3272 22:10:26.956153 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =123
3273 22:10:26.959696 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3274 22:10:26.963203 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3275 22:10:26.963281
3276 22:10:26.966954
3277 22:10:26.967022 ==
3278 22:10:26.969847 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 22:10:26.973486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 22:10:26.973554 ==
3281 22:10:26.973615
3282 22:10:26.973681
3283 22:10:26.976446 TX Vref Scan disable
3284 22:10:26.976512 == TX Byte 0 ==
3285 22:10:26.983092 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3286 22:10:26.986493 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3287 22:10:26.986561 == TX Byte 1 ==
3288 22:10:26.992905 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3289 22:10:26.996460 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3290 22:10:26.996529 ==
3291 22:10:26.999853 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 22:10:27.002887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 22:10:27.002955 ==
3294 22:10:27.015126 TX Vref=22, minBit 15, minWin=24, winSum=406
3295 22:10:27.018417 TX Vref=24, minBit 1, minWin=25, winSum=408
3296 22:10:27.021735 TX Vref=26, minBit 9, minWin=25, winSum=417
3297 22:10:27.025313 TX Vref=28, minBit 9, minWin=25, winSum=419
3298 22:10:27.028563 TX Vref=30, minBit 10, minWin=25, winSum=425
3299 22:10:27.031797 TX Vref=32, minBit 9, minWin=25, winSum=420
3300 22:10:27.038514 [TxChooseVref] Worse bit 10, Min win 25, Win sum 425, Final Vref 30
3301 22:10:27.038647
3302 22:10:27.042442 Final TX Range 1 Vref 30
3303 22:10:27.042566
3304 22:10:27.042678 ==
3305 22:10:27.045669 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 22:10:27.049181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 22:10:27.049304 ==
3308 22:10:27.049419
3309 22:10:27.052279
3310 22:10:27.052401 TX Vref Scan disable
3311 22:10:27.055474 == TX Byte 0 ==
3312 22:10:27.058936 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3313 22:10:27.062314 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3314 22:10:27.065433 == TX Byte 1 ==
3315 22:10:27.068722 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3316 22:10:27.072191 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3317 22:10:27.072290
3318 22:10:27.075560 [DATLAT]
3319 22:10:27.075689 Freq=1200, CH1 RK0
3320 22:10:27.075799
3321 22:10:27.079154 DATLAT Default: 0xd
3322 22:10:27.079273 0, 0xFFFF, sum = 0
3323 22:10:27.082260 1, 0xFFFF, sum = 0
3324 22:10:27.082386 2, 0xFFFF, sum = 0
3325 22:10:27.085723 3, 0xFFFF, sum = 0
3326 22:10:27.085843 4, 0xFFFF, sum = 0
3327 22:10:27.088939 5, 0xFFFF, sum = 0
3328 22:10:27.089057 6, 0xFFFF, sum = 0
3329 22:10:27.092366 7, 0xFFFF, sum = 0
3330 22:10:27.092484 8, 0xFFFF, sum = 0
3331 22:10:27.096124 9, 0xFFFF, sum = 0
3332 22:10:27.096247 10, 0xFFFF, sum = 0
3333 22:10:27.098893 11, 0xFFFF, sum = 0
3334 22:10:27.099013 12, 0x0, sum = 1
3335 22:10:27.102345 13, 0x0, sum = 2
3336 22:10:27.102465 14, 0x0, sum = 3
3337 22:10:27.105534 15, 0x0, sum = 4
3338 22:10:27.105658 best_step = 13
3339 22:10:27.105765
3340 22:10:27.105875 ==
3341 22:10:27.109161 Dram Type= 6, Freq= 0, CH_1, rank 0
3342 22:10:27.115592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3343 22:10:27.115696 ==
3344 22:10:27.115790 RX Vref Scan: 1
3345 22:10:27.115879
3346 22:10:27.118812 Set Vref Range= 32 -> 127
3347 22:10:27.118908
3348 22:10:27.122344 RX Vref 32 -> 127, step: 1
3349 22:10:27.122425
3350 22:10:27.126132 RX Delay -13 -> 252, step: 4
3351 22:10:27.126214
3352 22:10:27.126279 Set Vref, RX VrefLevel [Byte0]: 32
3353 22:10:27.129038 [Byte1]: 32
3354 22:10:27.133537
3355 22:10:27.133617 Set Vref, RX VrefLevel [Byte0]: 33
3356 22:10:27.136882 [Byte1]: 33
3357 22:10:27.141567
3358 22:10:27.141648 Set Vref, RX VrefLevel [Byte0]: 34
3359 22:10:27.144999 [Byte1]: 34
3360 22:10:27.149353
3361 22:10:27.149433 Set Vref, RX VrefLevel [Byte0]: 35
3362 22:10:27.152644 [Byte1]: 35
3363 22:10:27.157025
3364 22:10:27.157105 Set Vref, RX VrefLevel [Byte0]: 36
3365 22:10:27.160590 [Byte1]: 36
3366 22:10:27.165203
3367 22:10:27.165283 Set Vref, RX VrefLevel [Byte0]: 37
3368 22:10:27.168280 [Byte1]: 37
3369 22:10:27.173539
3370 22:10:27.173619 Set Vref, RX VrefLevel [Byte0]: 38
3371 22:10:27.176251 [Byte1]: 38
3372 22:10:27.180897
3373 22:10:27.180977 Set Vref, RX VrefLevel [Byte0]: 39
3374 22:10:27.184174 [Byte1]: 39
3375 22:10:27.188880
3376 22:10:27.188985 Set Vref, RX VrefLevel [Byte0]: 40
3377 22:10:27.192124 [Byte1]: 40
3378 22:10:27.196603
3379 22:10:27.196702 Set Vref, RX VrefLevel [Byte0]: 41
3380 22:10:27.200012 [Byte1]: 41
3381 22:10:27.204681
3382 22:10:27.204816 Set Vref, RX VrefLevel [Byte0]: 42
3383 22:10:27.208063 [Byte1]: 42
3384 22:10:27.212515
3385 22:10:27.212614 Set Vref, RX VrefLevel [Byte0]: 43
3386 22:10:27.215635 [Byte1]: 43
3387 22:10:27.220212
3388 22:10:27.220309 Set Vref, RX VrefLevel [Byte0]: 44
3389 22:10:27.223679 [Byte1]: 44
3390 22:10:27.228189
3391 22:10:27.228263 Set Vref, RX VrefLevel [Byte0]: 45
3392 22:10:27.231982 [Byte1]: 45
3393 22:10:27.236067
3394 22:10:27.236177 Set Vref, RX VrefLevel [Byte0]: 46
3395 22:10:27.239434 [Byte1]: 46
3396 22:10:27.243979
3397 22:10:27.244062 Set Vref, RX VrefLevel [Byte0]: 47
3398 22:10:27.247395 [Byte1]: 47
3399 22:10:27.252090
3400 22:10:27.252169 Set Vref, RX VrefLevel [Byte0]: 48
3401 22:10:27.255063 [Byte1]: 48
3402 22:10:27.259640
3403 22:10:27.259722 Set Vref, RX VrefLevel [Byte0]: 49
3404 22:10:27.263117 [Byte1]: 49
3405 22:10:27.267588
3406 22:10:27.267667 Set Vref, RX VrefLevel [Byte0]: 50
3407 22:10:27.270875 [Byte1]: 50
3408 22:10:27.275794
3409 22:10:27.275873 Set Vref, RX VrefLevel [Byte0]: 51
3410 22:10:27.278710 [Byte1]: 51
3411 22:10:27.283458
3412 22:10:27.283538 Set Vref, RX VrefLevel [Byte0]: 52
3413 22:10:27.286625 [Byte1]: 52
3414 22:10:27.291110
3415 22:10:27.291230 Set Vref, RX VrefLevel [Byte0]: 53
3416 22:10:27.294595 [Byte1]: 53
3417 22:10:27.299020
3418 22:10:27.299140 Set Vref, RX VrefLevel [Byte0]: 54
3419 22:10:27.302323 [Byte1]: 54
3420 22:10:27.306892
3421 22:10:27.307011 Set Vref, RX VrefLevel [Byte0]: 55
3422 22:10:27.310374 [Byte1]: 55
3423 22:10:27.314722
3424 22:10:27.314840 Set Vref, RX VrefLevel [Byte0]: 56
3425 22:10:27.318538 [Byte1]: 56
3426 22:10:27.322713
3427 22:10:27.322835 Set Vref, RX VrefLevel [Byte0]: 57
3428 22:10:27.326186 [Byte1]: 57
3429 22:10:27.330626
3430 22:10:27.330728 Set Vref, RX VrefLevel [Byte0]: 58
3431 22:10:27.334097 [Byte1]: 58
3432 22:10:27.338446
3433 22:10:27.338557 Set Vref, RX VrefLevel [Byte0]: 59
3434 22:10:27.342318 [Byte1]: 59
3435 22:10:27.346516
3436 22:10:27.346623 Set Vref, RX VrefLevel [Byte0]: 60
3437 22:10:27.349641 [Byte1]: 60
3438 22:10:27.354312
3439 22:10:27.354392 Set Vref, RX VrefLevel [Byte0]: 61
3440 22:10:27.357552 [Byte1]: 61
3441 22:10:27.362378
3442 22:10:27.362458 Set Vref, RX VrefLevel [Byte0]: 62
3443 22:10:27.365584 [Byte1]: 62
3444 22:10:27.370371
3445 22:10:27.370453 Set Vref, RX VrefLevel [Byte0]: 63
3446 22:10:27.373578 [Byte1]: 63
3447 22:10:27.378373
3448 22:10:27.378456 Set Vref, RX VrefLevel [Byte0]: 64
3449 22:10:27.381368 [Byte1]: 64
3450 22:10:27.385880
3451 22:10:27.385988 Set Vref, RX VrefLevel [Byte0]: 65
3452 22:10:27.389484 [Byte1]: 65
3453 22:10:27.393684
3454 22:10:27.393780 Set Vref, RX VrefLevel [Byte0]: 66
3455 22:10:27.397651 [Byte1]: 66
3456 22:10:27.401846
3457 22:10:27.401928 Set Vref, RX VrefLevel [Byte0]: 67
3458 22:10:27.404985 [Byte1]: 67
3459 22:10:27.409739
3460 22:10:27.409821 Final RX Vref Byte 0 = 52 to rank0
3461 22:10:27.412802 Final RX Vref Byte 1 = 52 to rank0
3462 22:10:27.416359 Final RX Vref Byte 0 = 52 to rank1
3463 22:10:27.419574 Final RX Vref Byte 1 = 52 to rank1==
3464 22:10:27.422949 Dram Type= 6, Freq= 0, CH_1, rank 0
3465 22:10:27.429554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 22:10:27.429637 ==
3467 22:10:27.429702 DQS Delay:
3468 22:10:27.429763 DQS0 = 0, DQS1 = 0
3469 22:10:27.432856 DQM Delay:
3470 22:10:27.432963 DQM0 = 119, DQM1 = 112
3471 22:10:27.436419 DQ Delay:
3472 22:10:27.439695 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3473 22:10:27.443103 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3474 22:10:27.446433 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3475 22:10:27.449422 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3476 22:10:27.449504
3477 22:10:27.449568
3478 22:10:27.456135 [DQSOSCAuto] RK0, (LSB)MR18= 0x619, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3479 22:10:27.459589 CH1 RK0: MR19=404, MR18=619
3480 22:10:27.466149 CH1_RK0: MR19=0x404, MR18=0x619, DQSOSC=400, MR23=63, INC=40, DEC=27
3481 22:10:27.466232
3482 22:10:27.469502 ----->DramcWriteLeveling(PI) begin...
3483 22:10:27.469586 ==
3484 22:10:27.472933 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 22:10:27.476269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 22:10:27.476352 ==
3487 22:10:27.479749 Write leveling (Byte 0): 26 => 26
3488 22:10:27.482719 Write leveling (Byte 1): 29 => 29
3489 22:10:27.486226 DramcWriteLeveling(PI) end<-----
3490 22:10:27.486334
3491 22:10:27.486429 ==
3492 22:10:27.490055 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 22:10:27.496252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 22:10:27.496337 ==
3495 22:10:27.496403 [Gating] SW mode calibration
3496 22:10:27.506575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3497 22:10:27.509698 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3498 22:10:27.513321 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 22:10:27.520053 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 22:10:27.523090 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 22:10:27.526407 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 22:10:27.533293 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 22:10:27.536568 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3504 22:10:27.540030 0 15 24 | B1->B0 | 2c2c 3434 | 1 1 | (1 0) (1 0)
3505 22:10:27.546367 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (1 0) (1 0)
3506 22:10:27.549841 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 22:10:27.553325 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 22:10:27.559837 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 22:10:27.563530 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 22:10:27.566559 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 22:10:27.570059 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 22:10:27.576756 1 0 24 | B1->B0 | 3232 2928 | 0 1 | (1 1) (0 0)
3513 22:10:27.580088 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3514 22:10:27.583220 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 22:10:27.590073 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 22:10:27.593210 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 22:10:27.596909 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 22:10:27.603231 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 22:10:27.606578 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 22:10:27.609971 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3521 22:10:27.616521 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3522 22:10:27.620097 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 22:10:27.623171 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 22:10:27.629601 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 22:10:27.633097 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 22:10:27.636267 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 22:10:27.643104 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 22:10:27.646351 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 22:10:27.649996 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 22:10:27.656286 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 22:10:27.659851 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 22:10:27.663016 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 22:10:27.669667 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 22:10:27.673161 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 22:10:27.676197 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 22:10:27.682807 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3537 22:10:27.686250 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 22:10:27.689459 Total UI for P1: 0, mck2ui 16
3539 22:10:27.692727 best dqsien dly found for B0: ( 1, 3, 24)
3540 22:10:27.696545 Total UI for P1: 0, mck2ui 16
3541 22:10:27.699589 best dqsien dly found for B1: ( 1, 3, 24)
3542 22:10:27.702647 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3543 22:10:27.706059 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3544 22:10:27.706179
3545 22:10:27.709587 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3546 22:10:27.712842 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3547 22:10:27.716111 [Gating] SW calibration Done
3548 22:10:27.716249 ==
3549 22:10:27.719777 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 22:10:27.722814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 22:10:27.722918 ==
3552 22:10:27.726711 RX Vref Scan: 0
3553 22:10:27.726810
3554 22:10:27.726930 RX Vref 0 -> 0, step: 1
3555 22:10:27.727018
3556 22:10:27.729670 RX Delay -40 -> 252, step: 8
3557 22:10:27.736365 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3558 22:10:27.739549 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3559 22:10:27.743186 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3560 22:10:27.746387 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3561 22:10:27.749754 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3562 22:10:27.756313 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3563 22:10:27.759560 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3564 22:10:27.762901 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3565 22:10:27.766265 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3566 22:10:27.769533 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3567 22:10:27.772849 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3568 22:10:27.779600 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3569 22:10:27.782940 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3570 22:10:27.786724 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3571 22:10:27.789495 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3572 22:10:27.796124 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3573 22:10:27.796223 ==
3574 22:10:27.799468 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 22:10:27.802720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 22:10:27.802817 ==
3577 22:10:27.802883 DQS Delay:
3578 22:10:27.806356 DQS0 = 0, DQS1 = 0
3579 22:10:27.806438 DQM Delay:
3580 22:10:27.809519 DQM0 = 120, DQM1 = 113
3581 22:10:27.809602 DQ Delay:
3582 22:10:27.812591 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3583 22:10:27.816064 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3584 22:10:27.819149 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3585 22:10:27.822820 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3586 22:10:27.822902
3587 22:10:27.822968
3588 22:10:27.825794 ==
3589 22:10:27.825877 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 22:10:27.832635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 22:10:27.832734 ==
3592 22:10:27.832820
3593 22:10:27.832880
3594 22:10:27.835676 TX Vref Scan disable
3595 22:10:27.835757 == TX Byte 0 ==
3596 22:10:27.839322 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3597 22:10:27.845659 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3598 22:10:27.845741 == TX Byte 1 ==
3599 22:10:27.849369 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3600 22:10:27.855776 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3601 22:10:27.855857 ==
3602 22:10:27.858951 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 22:10:27.862357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 22:10:27.862439 ==
3605 22:10:27.874355 TX Vref=22, minBit 3, minWin=25, winSum=416
3606 22:10:27.877534 TX Vref=24, minBit 1, minWin=25, winSum=424
3607 22:10:27.881061 TX Vref=26, minBit 1, minWin=26, winSum=425
3608 22:10:27.884310 TX Vref=28, minBit 1, minWin=26, winSum=429
3609 22:10:27.888226 TX Vref=30, minBit 7, minWin=26, winSum=429
3610 22:10:27.894363 TX Vref=32, minBit 1, minWin=26, winSum=426
3611 22:10:27.897862 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3612 22:10:27.897992
3613 22:10:27.901071 Final TX Range 1 Vref 28
3614 22:10:27.901154
3615 22:10:27.901219 ==
3616 22:10:27.904113 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 22:10:27.907685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 22:10:27.907769 ==
3619 22:10:27.907834
3620 22:10:27.911062
3621 22:10:27.911171 TX Vref Scan disable
3622 22:10:27.914722 == TX Byte 0 ==
3623 22:10:27.917700 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3624 22:10:27.921049 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3625 22:10:27.924474 == TX Byte 1 ==
3626 22:10:27.927675 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3627 22:10:27.930929 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3628 22:10:27.931037
3629 22:10:27.934698 [DATLAT]
3630 22:10:27.934782 Freq=1200, CH1 RK1
3631 22:10:27.934845
3632 22:10:27.937592 DATLAT Default: 0xd
3633 22:10:27.937666 0, 0xFFFF, sum = 0
3634 22:10:27.940887 1, 0xFFFF, sum = 0
3635 22:10:27.940960 2, 0xFFFF, sum = 0
3636 22:10:27.944278 3, 0xFFFF, sum = 0
3637 22:10:27.944376 4, 0xFFFF, sum = 0
3638 22:10:27.947606 5, 0xFFFF, sum = 0
3639 22:10:27.947704 6, 0xFFFF, sum = 0
3640 22:10:27.951365 7, 0xFFFF, sum = 0
3641 22:10:27.951463 8, 0xFFFF, sum = 0
3642 22:10:27.954274 9, 0xFFFF, sum = 0
3643 22:10:27.957484 10, 0xFFFF, sum = 0
3644 22:10:27.957554 11, 0xFFFF, sum = 0
3645 22:10:27.961339 12, 0x0, sum = 1
3646 22:10:27.961409 13, 0x0, sum = 2
3647 22:10:27.964163 14, 0x0, sum = 3
3648 22:10:27.964267 15, 0x0, sum = 4
3649 22:10:27.964359 best_step = 13
3650 22:10:27.964445
3651 22:10:27.967784 ==
3652 22:10:27.970804 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 22:10:27.974051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 22:10:27.974127 ==
3655 22:10:27.974190 RX Vref Scan: 0
3656 22:10:27.974248
3657 22:10:27.977367 RX Vref 0 -> 0, step: 1
3658 22:10:27.977456
3659 22:10:27.980513 RX Delay -13 -> 252, step: 4
3660 22:10:27.984054 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3661 22:10:27.990813 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3662 22:10:27.994612 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3663 22:10:27.997291 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3664 22:10:28.000574 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3665 22:10:28.004144 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3666 22:10:28.010667 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3667 22:10:28.014024 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3668 22:10:28.017373 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3669 22:10:28.020785 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3670 22:10:28.024100 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3671 22:10:28.027486 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3672 22:10:28.033846 iDelay=195, Bit 12, Center 120 (55 ~ 186) 132
3673 22:10:28.037098 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3674 22:10:28.040517 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3675 22:10:28.043861 iDelay=195, Bit 15, Center 122 (55 ~ 190) 136
3676 22:10:28.043944 ==
3677 22:10:28.047306 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 22:10:28.054076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 22:10:28.054160 ==
3680 22:10:28.054227 DQS Delay:
3681 22:10:28.056975 DQS0 = 0, DQS1 = 0
3682 22:10:28.057057 DQM Delay:
3683 22:10:28.060507 DQM0 = 119, DQM1 = 112
3684 22:10:28.060615 DQ Delay:
3685 22:10:28.063686 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3686 22:10:28.066961 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3687 22:10:28.070780 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3688 22:10:28.073498 DQ12 =120, DQ13 =118, DQ14 =122, DQ15 =122
3689 22:10:28.073581
3690 22:10:28.073646
3691 22:10:28.083529 [DQSOSCAuto] RK1, (LSB)MR18= 0xbef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3692 22:10:28.083614 CH1 RK1: MR19=403, MR18=BEF
3693 22:10:28.090473 CH1_RK1: MR19=0x403, MR18=0xBEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3694 22:10:28.093427 [RxdqsGatingPostProcess] freq 1200
3695 22:10:28.100370 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3696 22:10:28.103659 best DQS0 dly(2T, 0.5T) = (0, 11)
3697 22:10:28.106901 best DQS1 dly(2T, 0.5T) = (0, 11)
3698 22:10:28.110103 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3699 22:10:28.113532 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3700 22:10:28.116944 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 22:10:28.117027 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 22:10:28.120151 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 22:10:28.123312 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 22:10:28.127017 Pre-setting of DQS Precalculation
3705 22:10:28.133423 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3706 22:10:28.140063 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3707 22:10:28.147106 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3708 22:10:28.147190
3709 22:10:28.147255
3710 22:10:28.150039 [Calibration Summary] 2400 Mbps
3711 22:10:28.150122 CH 0, Rank 0
3712 22:10:28.153364 SW Impedance : PASS
3713 22:10:28.156787 DUTY Scan : NO K
3714 22:10:28.156883 ZQ Calibration : PASS
3715 22:10:28.160190 Jitter Meter : NO K
3716 22:10:28.163212 CBT Training : PASS
3717 22:10:28.163321 Write leveling : PASS
3718 22:10:28.166739 RX DQS gating : PASS
3719 22:10:28.170322 RX DQ/DQS(RDDQC) : PASS
3720 22:10:28.170406 TX DQ/DQS : PASS
3721 22:10:28.173173 RX DATLAT : PASS
3722 22:10:28.176901 RX DQ/DQS(Engine): PASS
3723 22:10:28.176983 TX OE : NO K
3724 22:10:28.179775 All Pass.
3725 22:10:28.179857
3726 22:10:28.179922 CH 0, Rank 1
3727 22:10:28.183597 SW Impedance : PASS
3728 22:10:28.183680 DUTY Scan : NO K
3729 22:10:28.186602 ZQ Calibration : PASS
3730 22:10:28.189960 Jitter Meter : NO K
3731 22:10:28.190043 CBT Training : PASS
3732 22:10:28.193210 Write leveling : PASS
3733 22:10:28.196857 RX DQS gating : PASS
3734 22:10:28.196940 RX DQ/DQS(RDDQC) : PASS
3735 22:10:28.200173 TX DQ/DQS : PASS
3736 22:10:28.200256 RX DATLAT : PASS
3737 22:10:28.203195 RX DQ/DQS(Engine): PASS
3738 22:10:28.206573 TX OE : NO K
3739 22:10:28.206656 All Pass.
3740 22:10:28.206722
3741 22:10:28.206781 CH 1, Rank 0
3742 22:10:28.209793 SW Impedance : PASS
3743 22:10:28.213769 DUTY Scan : NO K
3744 22:10:28.213851 ZQ Calibration : PASS
3745 22:10:28.216871 Jitter Meter : NO K
3746 22:10:28.219782 CBT Training : PASS
3747 22:10:28.219864 Write leveling : PASS
3748 22:10:28.223212 RX DQS gating : PASS
3749 22:10:28.226774 RX DQ/DQS(RDDQC) : PASS
3750 22:10:28.226902 TX DQ/DQS : PASS
3751 22:10:28.229911 RX DATLAT : PASS
3752 22:10:28.233260 RX DQ/DQS(Engine): PASS
3753 22:10:28.233402 TX OE : NO K
3754 22:10:28.233514 All Pass.
3755 22:10:28.236699
3756 22:10:28.236787 CH 1, Rank 1
3757 22:10:28.239761 SW Impedance : PASS
3758 22:10:28.239862 DUTY Scan : NO K
3759 22:10:28.243204 ZQ Calibration : PASS
3760 22:10:28.243286 Jitter Meter : NO K
3761 22:10:28.246610 CBT Training : PASS
3762 22:10:28.249739 Write leveling : PASS
3763 22:10:28.249820 RX DQS gating : PASS
3764 22:10:28.253556 RX DQ/DQS(RDDQC) : PASS
3765 22:10:28.256336 TX DQ/DQS : PASS
3766 22:10:28.256418 RX DATLAT : PASS
3767 22:10:28.259610 RX DQ/DQS(Engine): PASS
3768 22:10:28.263353 TX OE : NO K
3769 22:10:28.263456 All Pass.
3770 22:10:28.263556
3771 22:10:28.266580 DramC Write-DBI off
3772 22:10:28.266661 PER_BANK_REFRESH: Hybrid Mode
3773 22:10:28.269770 TX_TRACKING: ON
3774 22:10:28.279472 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3775 22:10:28.283157 [FAST_K] Save calibration result to emmc
3776 22:10:28.286564 dramc_set_vcore_voltage set vcore to 650000
3777 22:10:28.286645 Read voltage for 600, 5
3778 22:10:28.289335 Vio18 = 0
3779 22:10:28.289416 Vcore = 650000
3780 22:10:28.289481 Vdram = 0
3781 22:10:28.292805 Vddq = 0
3782 22:10:28.292900 Vmddr = 0
3783 22:10:28.296081 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3784 22:10:28.303051 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3785 22:10:28.306408 MEM_TYPE=3, freq_sel=19
3786 22:10:28.309881 sv_algorithm_assistance_LP4_1600
3787 22:10:28.312853 ============ PULL DRAM RESETB DOWN ============
3788 22:10:28.316087 ========== PULL DRAM RESETB DOWN end =========
3789 22:10:28.322844 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3790 22:10:28.326141 ===================================
3791 22:10:28.326223 LPDDR4 DRAM CONFIGURATION
3792 22:10:28.329507 ===================================
3793 22:10:28.333026 EX_ROW_EN[0] = 0x0
3794 22:10:28.333096 EX_ROW_EN[1] = 0x0
3795 22:10:28.336029 LP4Y_EN = 0x0
3796 22:10:28.336112 WORK_FSP = 0x0
3797 22:10:28.339350 WL = 0x2
3798 22:10:28.339433 RL = 0x2
3799 22:10:28.343191 BL = 0x2
3800 22:10:28.346225 RPST = 0x0
3801 22:10:28.346349 RD_PRE = 0x0
3802 22:10:28.349716 WR_PRE = 0x1
3803 22:10:28.349798 WR_PST = 0x0
3804 22:10:28.353113 DBI_WR = 0x0
3805 22:10:28.353196 DBI_RD = 0x0
3806 22:10:28.356213 OTF = 0x1
3807 22:10:28.359362 ===================================
3808 22:10:28.362989 ===================================
3809 22:10:28.363072 ANA top config
3810 22:10:28.366246 ===================================
3811 22:10:28.369467 DLL_ASYNC_EN = 0
3812 22:10:28.372595 ALL_SLAVE_EN = 1
3813 22:10:28.372677 NEW_RANK_MODE = 1
3814 22:10:28.375961 DLL_IDLE_MODE = 1
3815 22:10:28.379565 LP45_APHY_COMB_EN = 1
3816 22:10:28.382645 TX_ODT_DIS = 1
3817 22:10:28.382728 NEW_8X_MODE = 1
3818 22:10:28.386142 ===================================
3819 22:10:28.389582 ===================================
3820 22:10:28.392952 data_rate = 1200
3821 22:10:28.395870 CKR = 1
3822 22:10:28.399492 DQ_P2S_RATIO = 8
3823 22:10:28.402636 ===================================
3824 22:10:28.405875 CA_P2S_RATIO = 8
3825 22:10:28.409436 DQ_CA_OPEN = 0
3826 22:10:28.409519 DQ_SEMI_OPEN = 0
3827 22:10:28.412603 CA_SEMI_OPEN = 0
3828 22:10:28.416244 CA_FULL_RATE = 0
3829 22:10:28.419346 DQ_CKDIV4_EN = 1
3830 22:10:28.422447 CA_CKDIV4_EN = 1
3831 22:10:28.425896 CA_PREDIV_EN = 0
3832 22:10:28.425979 PH8_DLY = 0
3833 22:10:28.429281 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3834 22:10:28.432766 DQ_AAMCK_DIV = 4
3835 22:10:28.435836 CA_AAMCK_DIV = 4
3836 22:10:28.439070 CA_ADMCK_DIV = 4
3837 22:10:28.442355 DQ_TRACK_CA_EN = 0
3838 22:10:28.442439 CA_PICK = 600
3839 22:10:28.445935 CA_MCKIO = 600
3840 22:10:28.449229 MCKIO_SEMI = 0
3841 22:10:28.452493 PLL_FREQ = 2288
3842 22:10:28.456405 DQ_UI_PI_RATIO = 32
3843 22:10:28.459325 CA_UI_PI_RATIO = 0
3844 22:10:28.462635 ===================================
3845 22:10:28.466244 ===================================
3846 22:10:28.466344 memory_type:LPDDR4
3847 22:10:28.469073 GP_NUM : 10
3848 22:10:28.472316 SRAM_EN : 1
3849 22:10:28.472402 MD32_EN : 0
3850 22:10:28.475932 ===================================
3851 22:10:28.479131 [ANA_INIT] >>>>>>>>>>>>>>
3852 22:10:28.482527 <<<<<< [CONFIGURE PHASE]: ANA_TX
3853 22:10:28.485578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3854 22:10:28.489103 ===================================
3855 22:10:28.492738 data_rate = 1200,PCW = 0X5800
3856 22:10:28.495903 ===================================
3857 22:10:28.499629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3858 22:10:28.502651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 22:10:28.509037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 22:10:28.512401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3861 22:10:28.515944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3862 22:10:28.519140 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3863 22:10:28.522706 [ANA_INIT] flow start
3864 22:10:28.525867 [ANA_INIT] PLL >>>>>>>>
3865 22:10:28.525951 [ANA_INIT] PLL <<<<<<<<
3866 22:10:28.528896 [ANA_INIT] MIDPI >>>>>>>>
3867 22:10:28.532198 [ANA_INIT] MIDPI <<<<<<<<
3868 22:10:28.535528 [ANA_INIT] DLL >>>>>>>>
3869 22:10:28.535676 [ANA_INIT] flow end
3870 22:10:28.539118 ============ LP4 DIFF to SE enter ============
3871 22:10:28.545416 ============ LP4 DIFF to SE exit ============
3872 22:10:28.545520 [ANA_INIT] <<<<<<<<<<<<<
3873 22:10:28.548708 [Flow] Enable top DCM control >>>>>
3874 22:10:28.552211 [Flow] Enable top DCM control <<<<<
3875 22:10:28.555237 Enable DLL master slave shuffle
3876 22:10:28.562252 ==============================================================
3877 22:10:28.562340 Gating Mode config
3878 22:10:28.568640 ==============================================================
3879 22:10:28.571783 Config description:
3880 22:10:28.581872 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3881 22:10:28.588790 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3882 22:10:28.592111 SELPH_MODE 0: By rank 1: By Phase
3883 22:10:28.598531 ==============================================================
3884 22:10:28.601755 GAT_TRACK_EN = 1
3885 22:10:28.605227 RX_GATING_MODE = 2
3886 22:10:28.605322 RX_GATING_TRACK_MODE = 2
3887 22:10:28.608559 SELPH_MODE = 1
3888 22:10:28.611920 PICG_EARLY_EN = 1
3889 22:10:28.615280 VALID_LAT_VALUE = 1
3890 22:10:28.621630 ==============================================================
3891 22:10:28.625065 Enter into Gating configuration >>>>
3892 22:10:28.628291 Exit from Gating configuration <<<<
3893 22:10:28.631586 Enter into DVFS_PRE_config >>>>>
3894 22:10:28.642131 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3895 22:10:28.645147 Exit from DVFS_PRE_config <<<<<
3896 22:10:28.648091 Enter into PICG configuration >>>>
3897 22:10:28.651570 Exit from PICG configuration <<<<
3898 22:10:28.655174 [RX_INPUT] configuration >>>>>
3899 22:10:28.658288 [RX_INPUT] configuration <<<<<
3900 22:10:28.661778 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3901 22:10:28.668231 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3902 22:10:28.675023 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3903 22:10:28.678251 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3904 22:10:28.685023 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3905 22:10:28.691625 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3906 22:10:28.694865 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3907 22:10:28.701360 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3908 22:10:28.705156 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3909 22:10:28.708167 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3910 22:10:28.711510 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3911 22:10:28.718340 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3912 22:10:28.721549 ===================================
3913 22:10:28.721633 LPDDR4 DRAM CONFIGURATION
3914 22:10:28.724928 ===================================
3915 22:10:28.728227 EX_ROW_EN[0] = 0x0
3916 22:10:28.731349 EX_ROW_EN[1] = 0x0
3917 22:10:28.731440 LP4Y_EN = 0x0
3918 22:10:28.734788 WORK_FSP = 0x0
3919 22:10:28.734872 WL = 0x2
3920 22:10:28.738114 RL = 0x2
3921 22:10:28.738197 BL = 0x2
3922 22:10:28.741632 RPST = 0x0
3923 22:10:28.741733 RD_PRE = 0x0
3924 22:10:28.745097 WR_PRE = 0x1
3925 22:10:28.745181 WR_PST = 0x0
3926 22:10:28.748725 DBI_WR = 0x0
3927 22:10:28.748865 DBI_RD = 0x0
3928 22:10:28.751606 OTF = 0x1
3929 22:10:28.754614 ===================================
3930 22:10:28.758026 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3931 22:10:28.761626 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3932 22:10:28.768340 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3933 22:10:28.771482 ===================================
3934 22:10:28.771569 LPDDR4 DRAM CONFIGURATION
3935 22:10:28.774866 ===================================
3936 22:10:28.778134 EX_ROW_EN[0] = 0x10
3937 22:10:28.778217 EX_ROW_EN[1] = 0x0
3938 22:10:28.781498 LP4Y_EN = 0x0
3939 22:10:28.781582 WORK_FSP = 0x0
3940 22:10:28.784790 WL = 0x2
3941 22:10:28.788462 RL = 0x2
3942 22:10:28.788574 BL = 0x2
3943 22:10:28.791497 RPST = 0x0
3944 22:10:28.791608 RD_PRE = 0x0
3945 22:10:28.794874 WR_PRE = 0x1
3946 22:10:28.794956 WR_PST = 0x0
3947 22:10:28.798036 DBI_WR = 0x0
3948 22:10:28.798120 DBI_RD = 0x0
3949 22:10:28.801240 OTF = 0x1
3950 22:10:28.804602 ===================================
3951 22:10:28.811080 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3952 22:10:28.814527 nWR fixed to 30
3953 22:10:28.814611 [ModeRegInit_LP4] CH0 RK0
3954 22:10:28.818208 [ModeRegInit_LP4] CH0 RK1
3955 22:10:28.821050 [ModeRegInit_LP4] CH1 RK0
3956 22:10:28.821133 [ModeRegInit_LP4] CH1 RK1
3957 22:10:28.824400 match AC timing 17
3958 22:10:28.827846 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3959 22:10:28.831144 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3960 22:10:28.837796 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3961 22:10:28.841346 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3962 22:10:28.848222 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3963 22:10:28.848328 ==
3964 22:10:28.851397 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 22:10:28.854984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 22:10:28.855084 ==
3967 22:10:28.861367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 22:10:28.864252 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3969 22:10:28.868714 [CA 0] Center 36 (6~67) winsize 62
3970 22:10:28.872970 [CA 1] Center 36 (6~67) winsize 62
3971 22:10:28.875501 [CA 2] Center 34 (4~65) winsize 62
3972 22:10:28.878633 [CA 3] Center 34 (3~65) winsize 63
3973 22:10:28.882315 [CA 4] Center 33 (3~64) winsize 62
3974 22:10:28.885642 [CA 5] Center 33 (3~64) winsize 62
3975 22:10:28.885723
3976 22:10:28.888601 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3977 22:10:28.888711
3978 22:10:28.892126 [CATrainingPosCal] consider 1 rank data
3979 22:10:28.895879 u2DelayCellTimex100 = 270/100 ps
3980 22:10:28.899026 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3981 22:10:28.905812 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3982 22:10:28.908558 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3983 22:10:28.911984 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3984 22:10:28.915283 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3985 22:10:28.918698 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3986 22:10:28.918826
3987 22:10:28.922060 CA PerBit enable=1, Macro0, CA PI delay=33
3988 22:10:28.922169
3989 22:10:28.925102 [CBTSetCACLKResult] CA Dly = 33
3990 22:10:28.925228 CS Dly: 5 (0~36)
3991 22:10:28.928573 ==
3992 22:10:28.928705 Dram Type= 6, Freq= 0, CH_0, rank 1
3993 22:10:28.935337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 22:10:28.935466 ==
3995 22:10:28.938359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3996 22:10:28.945224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3997 22:10:28.949010 [CA 0] Center 36 (6~67) winsize 62
3998 22:10:28.952083 [CA 1] Center 36 (6~67) winsize 62
3999 22:10:28.955447 [CA 2] Center 35 (5~66) winsize 62
4000 22:10:28.958856 [CA 3] Center 35 (4~66) winsize 63
4001 22:10:28.962128 [CA 4] Center 34 (3~65) winsize 63
4002 22:10:28.965510 [CA 5] Center 34 (3~65) winsize 63
4003 22:10:28.965611
4004 22:10:28.968684 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4005 22:10:28.968772
4006 22:10:28.972014 [CATrainingPosCal] consider 2 rank data
4007 22:10:28.975487 u2DelayCellTimex100 = 270/100 ps
4008 22:10:28.978743 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4009 22:10:28.985365 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4010 22:10:28.989024 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4011 22:10:28.991888 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4012 22:10:28.995276 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4013 22:10:28.998723 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4014 22:10:28.998832
4015 22:10:29.001871 CA PerBit enable=1, Macro0, CA PI delay=33
4016 22:10:29.001954
4017 22:10:29.005123 [CBTSetCACLKResult] CA Dly = 33
4018 22:10:29.008817 CS Dly: 5 (0~37)
4019 22:10:29.008901
4020 22:10:29.011922 ----->DramcWriteLeveling(PI) begin...
4021 22:10:29.012006 ==
4022 22:10:29.015328 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 22:10:29.018395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 22:10:29.018479 ==
4025 22:10:29.021851 Write leveling (Byte 0): 34 => 34
4026 22:10:29.025291 Write leveling (Byte 1): 29 => 29
4027 22:10:29.028557 DramcWriteLeveling(PI) end<-----
4028 22:10:29.028640
4029 22:10:29.028705 ==
4030 22:10:29.032105 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 22:10:29.035042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 22:10:29.035125 ==
4033 22:10:29.038617 [Gating] SW mode calibration
4034 22:10:29.045093 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4035 22:10:29.051945 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4036 22:10:29.054792 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 22:10:29.058274 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 22:10:29.065372 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 22:10:29.068135 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4040 22:10:29.071444 0 9 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 1) (0 0)
4041 22:10:29.078508 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 22:10:29.081713 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 22:10:29.084825 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 22:10:29.091371 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 22:10:29.094773 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 22:10:29.098224 0 10 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
4047 22:10:29.101567 0 10 12 | B1->B0 | 2626 3f3f | 0 0 | (0 0) (0 0)
4048 22:10:29.108228 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4049 22:10:29.111467 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 22:10:29.115260 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 22:10:29.121635 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 22:10:29.124972 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 22:10:29.128456 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 22:10:29.134761 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 22:10:29.138460 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4056 22:10:29.141411 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4057 22:10:29.148192 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 22:10:29.151534 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 22:10:29.154731 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 22:10:29.161657 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 22:10:29.164627 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 22:10:29.167891 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 22:10:29.174750 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 22:10:29.178190 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 22:10:29.181723 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 22:10:29.187805 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 22:10:29.191277 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 22:10:29.194688 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 22:10:29.201257 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 22:10:29.204721 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4071 22:10:29.207680 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4072 22:10:29.214331 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 22:10:29.214413 Total UI for P1: 0, mck2ui 16
4074 22:10:29.220899 best dqsien dly found for B0: ( 0, 13, 10)
4075 22:10:29.220981 Total UI for P1: 0, mck2ui 16
4076 22:10:29.224544 best dqsien dly found for B1: ( 0, 13, 12)
4077 22:10:29.231045 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4078 22:10:29.234711 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4079 22:10:29.234792
4080 22:10:29.237405 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4081 22:10:29.240870 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4082 22:10:29.244085 [Gating] SW calibration Done
4083 22:10:29.244168 ==
4084 22:10:29.247726 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 22:10:29.250702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 22:10:29.250786 ==
4087 22:10:29.254369 RX Vref Scan: 0
4088 22:10:29.254452
4089 22:10:29.254517 RX Vref 0 -> 0, step: 1
4090 22:10:29.254578
4091 22:10:29.257543 RX Delay -230 -> 252, step: 16
4092 22:10:29.260705 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4093 22:10:29.267536 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4094 22:10:29.270859 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4095 22:10:29.274749 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4096 22:10:29.277483 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4097 22:10:29.284112 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4098 22:10:29.287852 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4099 22:10:29.290791 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4100 22:10:29.294393 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4101 22:10:29.297369 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4102 22:10:29.304470 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4103 22:10:29.307686 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4104 22:10:29.310892 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4105 22:10:29.314117 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4106 22:10:29.321021 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4107 22:10:29.324355 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4108 22:10:29.324491 ==
4109 22:10:29.327479 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 22:10:29.330899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 22:10:29.331023 ==
4112 22:10:29.334080 DQS Delay:
4113 22:10:29.334204 DQS0 = 0, DQS1 = 0
4114 22:10:29.334313 DQM Delay:
4115 22:10:29.337824 DQM0 = 53, DQM1 = 44
4116 22:10:29.337944 DQ Delay:
4117 22:10:29.340780 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4118 22:10:29.344375 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4119 22:10:29.347496 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4120 22:10:29.350653 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4121 22:10:29.350776
4122 22:10:29.350889
4123 22:10:29.350998 ==
4124 22:10:29.354350 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 22:10:29.360726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 22:10:29.360828 ==
4127 22:10:29.360893
4128 22:10:29.360953
4129 22:10:29.361011 TX Vref Scan disable
4130 22:10:29.364423 == TX Byte 0 ==
4131 22:10:29.367594 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4132 22:10:29.374345 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4133 22:10:29.374427 == TX Byte 1 ==
4134 22:10:29.377769 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4135 22:10:29.384434 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4136 22:10:29.384517 ==
4137 22:10:29.387619 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 22:10:29.391434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 22:10:29.391518 ==
4140 22:10:29.391584
4141 22:10:29.391643
4142 22:10:29.394149 TX Vref Scan disable
4143 22:10:29.397672 == TX Byte 0 ==
4144 22:10:29.401000 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4145 22:10:29.404137 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4146 22:10:29.407582 == TX Byte 1 ==
4147 22:10:29.410977 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4148 22:10:29.414085 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4149 22:10:29.414167
4150 22:10:29.414233 [DATLAT]
4151 22:10:29.417502 Freq=600, CH0 RK0
4152 22:10:29.417585
4153 22:10:29.417650 DATLAT Default: 0x9
4154 22:10:29.420795 0, 0xFFFF, sum = 0
4155 22:10:29.424308 1, 0xFFFF, sum = 0
4156 22:10:29.424407 2, 0xFFFF, sum = 0
4157 22:10:29.427451 3, 0xFFFF, sum = 0
4158 22:10:29.427538 4, 0xFFFF, sum = 0
4159 22:10:29.430603 5, 0xFFFF, sum = 0
4160 22:10:29.430718 6, 0xFFFF, sum = 0
4161 22:10:29.433892 7, 0xFFFF, sum = 0
4162 22:10:29.433976 8, 0x0, sum = 1
4163 22:10:29.437644 9, 0x0, sum = 2
4164 22:10:29.437774 10, 0x0, sum = 3
4165 22:10:29.437891 11, 0x0, sum = 4
4166 22:10:29.440870 best_step = 9
4167 22:10:29.440990
4168 22:10:29.441105 ==
4169 22:10:29.443831 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 22:10:29.447219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 22:10:29.447339 ==
4172 22:10:29.450726 RX Vref Scan: 1
4173 22:10:29.450848
4174 22:10:29.450999 RX Vref 0 -> 0, step: 1
4175 22:10:29.454085
4176 22:10:29.454205 RX Delay -179 -> 252, step: 8
4177 22:10:29.454315
4178 22:10:29.457368 Set Vref, RX VrefLevel [Byte0]: 61
4179 22:10:29.460471 [Byte1]: 51
4180 22:10:29.464915
4181 22:10:29.465037 Final RX Vref Byte 0 = 61 to rank0
4182 22:10:29.468138 Final RX Vref Byte 1 = 51 to rank0
4183 22:10:29.471419 Final RX Vref Byte 0 = 61 to rank1
4184 22:10:29.475028 Final RX Vref Byte 1 = 51 to rank1==
4185 22:10:29.478228 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 22:10:29.484711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 22:10:29.484845 ==
4188 22:10:29.484941 DQS Delay:
4189 22:10:29.488181 DQS0 = 0, DQS1 = 0
4190 22:10:29.488264 DQM Delay:
4191 22:10:29.488328 DQM0 = 47, DQM1 = 40
4192 22:10:29.491376 DQ Delay:
4193 22:10:29.494890 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4194 22:10:29.497947 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4195 22:10:29.501086 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4196 22:10:29.504520 DQ12 =48, DQ13 =40, DQ14 =52, DQ15 =44
4197 22:10:29.504627
4198 22:10:29.504721
4199 22:10:29.511239 [DQSOSCAuto] RK0, (LSB)MR18= 0x605a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4200 22:10:29.514919 CH0 RK0: MR19=808, MR18=605A
4201 22:10:29.521526 CH0_RK0: MR19=0x808, MR18=0x605A, DQSOSC=391, MR23=63, INC=171, DEC=114
4202 22:10:29.521641
4203 22:10:29.524375 ----->DramcWriteLeveling(PI) begin...
4204 22:10:29.524497 ==
4205 22:10:29.528299 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 22:10:29.531109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 22:10:29.531251 ==
4208 22:10:29.534493 Write leveling (Byte 0): 34 => 34
4209 22:10:29.537915 Write leveling (Byte 1): 30 => 30
4210 22:10:29.541134 DramcWriteLeveling(PI) end<-----
4211 22:10:29.541264
4212 22:10:29.541378 ==
4213 22:10:29.544511 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 22:10:29.547687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 22:10:29.547824 ==
4216 22:10:29.551206 [Gating] SW mode calibration
4217 22:10:29.557897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4218 22:10:29.564716 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4219 22:10:29.568200 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 22:10:29.574266 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 22:10:29.577563 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 22:10:29.580905 0 9 12 | B1->B0 | 3232 3131 | 0 1 | (0 0) (1 0)
4223 22:10:29.584265 0 9 16 | B1->B0 | 2828 2727 | 0 0 | (0 0) (0 0)
4224 22:10:29.590971 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 22:10:29.594289 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 22:10:29.597752 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 22:10:29.604329 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 22:10:29.607871 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 22:10:29.611004 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 22:10:29.617965 0 10 12 | B1->B0 | 2b2b 3333 | 0 1 | (0 0) (1 1)
4231 22:10:29.621187 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4232 22:10:29.624687 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 22:10:29.631164 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 22:10:29.634114 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 22:10:29.637653 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 22:10:29.644329 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 22:10:29.647588 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 22:10:29.651121 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4239 22:10:29.657388 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4240 22:10:29.661053 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 22:10:29.664397 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 22:10:29.671065 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 22:10:29.674681 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 22:10:29.677652 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 22:10:29.684460 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 22:10:29.687525 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 22:10:29.690787 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 22:10:29.697438 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 22:10:29.700859 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 22:10:29.704065 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 22:10:29.707547 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 22:10:29.714382 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 22:10:29.717495 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 22:10:29.720673 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 22:10:29.724033 Total UI for P1: 0, mck2ui 16
4256 22:10:29.727423 best dqsien dly found for B0: ( 0, 13, 10)
4257 22:10:29.731004 Total UI for P1: 0, mck2ui 16
4258 22:10:29.734023 best dqsien dly found for B1: ( 0, 13, 10)
4259 22:10:29.737472 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4260 22:10:29.740844 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4261 22:10:29.743828
4262 22:10:29.747511 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4263 22:10:29.750547 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4264 22:10:29.754289 [Gating] SW calibration Done
4265 22:10:29.754386 ==
4266 22:10:29.757547 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 22:10:29.760452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 22:10:29.760526 ==
4269 22:10:29.760636 RX Vref Scan: 0
4270 22:10:29.764242
4271 22:10:29.764312 RX Vref 0 -> 0, step: 1
4272 22:10:29.764372
4273 22:10:29.767250 RX Delay -230 -> 252, step: 16
4274 22:10:29.770726 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4275 22:10:29.777215 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4276 22:10:29.780629 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4277 22:10:29.783991 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4278 22:10:29.787263 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4279 22:10:29.790585 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4280 22:10:29.797443 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4281 22:10:29.801029 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4282 22:10:29.803894 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4283 22:10:29.807845 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4284 22:10:29.810600 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4285 22:10:29.817486 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4286 22:10:29.820621 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4287 22:10:29.824168 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4288 22:10:29.827404 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4289 22:10:29.833880 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4290 22:10:29.833963 ==
4291 22:10:29.837421 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 22:10:29.840526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 22:10:29.840612 ==
4294 22:10:29.840678 DQS Delay:
4295 22:10:29.843852 DQS0 = 0, DQS1 = 0
4296 22:10:29.843933 DQM Delay:
4297 22:10:29.847155 DQM0 = 51, DQM1 = 42
4298 22:10:29.847265 DQ Delay:
4299 22:10:29.850539 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4300 22:10:29.854006 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4301 22:10:29.857212 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4302 22:10:29.860603 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4303 22:10:29.860684
4304 22:10:29.860749
4305 22:10:29.860853 ==
4306 22:10:29.864023 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 22:10:29.867275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 22:10:29.867357 ==
4309 22:10:29.867422
4310 22:10:29.870495
4311 22:10:29.870576 TX Vref Scan disable
4312 22:10:29.874004 == TX Byte 0 ==
4313 22:10:29.877230 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4314 22:10:29.880428 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4315 22:10:29.884329 == TX Byte 1 ==
4316 22:10:29.887202 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4317 22:10:29.890397 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4318 22:10:29.890468 ==
4319 22:10:29.893809 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 22:10:29.900469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 22:10:29.900551 ==
4322 22:10:29.900616
4323 22:10:29.900675
4324 22:10:29.900732 TX Vref Scan disable
4325 22:10:29.905301 == TX Byte 0 ==
4326 22:10:29.908280 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4327 22:10:29.915055 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4328 22:10:29.915137 == TX Byte 1 ==
4329 22:10:29.918205 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4330 22:10:29.924983 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4331 22:10:29.925064
4332 22:10:29.925130 [DATLAT]
4333 22:10:29.925190 Freq=600, CH0 RK1
4334 22:10:29.925249
4335 22:10:29.928438 DATLAT Default: 0x9
4336 22:10:29.928518 0, 0xFFFF, sum = 0
4337 22:10:29.931952 1, 0xFFFF, sum = 0
4338 22:10:29.932035 2, 0xFFFF, sum = 0
4339 22:10:29.935139 3, 0xFFFF, sum = 0
4340 22:10:29.938384 4, 0xFFFF, sum = 0
4341 22:10:29.938466 5, 0xFFFF, sum = 0
4342 22:10:29.941672 6, 0xFFFF, sum = 0
4343 22:10:29.941757 7, 0xFFFF, sum = 0
4344 22:10:29.944831 8, 0x0, sum = 1
4345 22:10:29.944905 9, 0x0, sum = 2
4346 22:10:29.944967 10, 0x0, sum = 3
4347 22:10:29.948144 11, 0x0, sum = 4
4348 22:10:29.948214 best_step = 9
4349 22:10:29.948271
4350 22:10:29.948326 ==
4351 22:10:29.951658 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 22:10:29.958594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 22:10:29.958705 ==
4354 22:10:29.958796 RX Vref Scan: 0
4355 22:10:29.958884
4356 22:10:29.961611 RX Vref 0 -> 0, step: 1
4357 22:10:29.961690
4358 22:10:29.964870 RX Delay -179 -> 252, step: 8
4359 22:10:29.968381 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4360 22:10:29.975207 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4361 22:10:29.978321 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4362 22:10:29.981676 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4363 22:10:29.984857 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4364 22:10:29.988081 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4365 22:10:29.994748 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4366 22:10:29.998404 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4367 22:10:30.001594 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4368 22:10:30.004612 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4369 22:10:30.008113 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4370 22:10:30.014659 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4371 22:10:30.018039 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4372 22:10:30.021373 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4373 22:10:30.024623 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4374 22:10:30.031544 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4375 22:10:30.031623 ==
4376 22:10:30.034504 Dram Type= 6, Freq= 0, CH_0, rank 1
4377 22:10:30.038225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 22:10:30.038360 ==
4379 22:10:30.038466 DQS Delay:
4380 22:10:30.041065 DQS0 = 0, DQS1 = 0
4381 22:10:30.041163 DQM Delay:
4382 22:10:30.044700 DQM0 = 48, DQM1 = 39
4383 22:10:30.044801 DQ Delay:
4384 22:10:30.048205 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4385 22:10:30.051208 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4386 22:10:30.054461 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4387 22:10:30.057790 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =48
4388 22:10:30.057888
4389 22:10:30.057981
4390 22:10:30.064373 [DQSOSCAuto] RK1, (LSB)MR18= 0x6836, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4391 22:10:30.068003 CH0 RK1: MR19=808, MR18=6836
4392 22:10:30.074632 CH0_RK1: MR19=0x808, MR18=0x6836, DQSOSC=390, MR23=63, INC=172, DEC=114
4393 22:10:30.077787 [RxdqsGatingPostProcess] freq 600
4394 22:10:30.084609 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4395 22:10:30.088014 Pre-setting of DQS Precalculation
4396 22:10:30.091243 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4397 22:10:30.091323 ==
4398 22:10:30.094233 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 22:10:30.097679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 22:10:30.097762 ==
4401 22:10:30.105019 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4402 22:10:30.111267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4403 22:10:30.114350 [CA 0] Center 35 (5~66) winsize 62
4404 22:10:30.117681 [CA 1] Center 35 (5~66) winsize 62
4405 22:10:30.120733 [CA 2] Center 34 (4~65) winsize 62
4406 22:10:30.124421 [CA 3] Center 33 (3~64) winsize 62
4407 22:10:30.127768 [CA 4] Center 34 (3~65) winsize 63
4408 22:10:30.131193 [CA 5] Center 33 (3~64) winsize 62
4409 22:10:30.131291
4410 22:10:30.134235 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4411 22:10:30.134314
4412 22:10:30.137649 [CATrainingPosCal] consider 1 rank data
4413 22:10:30.141242 u2DelayCellTimex100 = 270/100 ps
4414 22:10:30.144687 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4415 22:10:30.147887 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4416 22:10:30.151140 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4417 22:10:30.154661 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 22:10:30.157912 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4419 22:10:30.161156 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 22:10:30.161238
4421 22:10:30.167994 CA PerBit enable=1, Macro0, CA PI delay=33
4422 22:10:30.168103
4423 22:10:30.171024 [CBTSetCACLKResult] CA Dly = 33
4424 22:10:30.171106 CS Dly: 4 (0~35)
4425 22:10:30.171170 ==
4426 22:10:30.174638 Dram Type= 6, Freq= 0, CH_1, rank 1
4427 22:10:30.178312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 22:10:30.178394 ==
4429 22:10:30.184338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4430 22:10:30.191197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4431 22:10:30.194304 [CA 0] Center 35 (5~66) winsize 62
4432 22:10:30.197810 [CA 1] Center 35 (5~66) winsize 62
4433 22:10:30.201564 [CA 2] Center 34 (4~65) winsize 62
4434 22:10:30.204647 [CA 3] Center 34 (4~65) winsize 62
4435 22:10:30.207831 [CA 4] Center 34 (4~65) winsize 62
4436 22:10:30.211147 [CA 5] Center 33 (3~64) winsize 62
4437 22:10:30.211230
4438 22:10:30.214368 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4439 22:10:30.214453
4440 22:10:30.217441 [CATrainingPosCal] consider 2 rank data
4441 22:10:30.220997 u2DelayCellTimex100 = 270/100 ps
4442 22:10:30.224095 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4443 22:10:30.227465 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4444 22:10:30.230799 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4445 22:10:30.234361 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4446 22:10:30.237592 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4447 22:10:30.243960 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4448 22:10:30.244043
4449 22:10:30.247399 CA PerBit enable=1, Macro0, CA PI delay=33
4450 22:10:30.247482
4451 22:10:30.251088 [CBTSetCACLKResult] CA Dly = 33
4452 22:10:30.251171 CS Dly: 4 (0~36)
4453 22:10:30.251238
4454 22:10:30.254425 ----->DramcWriteLeveling(PI) begin...
4455 22:10:30.254509 ==
4456 22:10:30.257629 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 22:10:30.261101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 22:10:30.264324 ==
4459 22:10:30.267484 Write leveling (Byte 0): 30 => 30
4460 22:10:30.267614 Write leveling (Byte 1): 30 => 30
4461 22:10:30.270735 DramcWriteLeveling(PI) end<-----
4462 22:10:30.270817
4463 22:10:30.270881 ==
4464 22:10:30.273976 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 22:10:30.280431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 22:10:30.280513 ==
4467 22:10:30.283832 [Gating] SW mode calibration
4468 22:10:30.290510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4469 22:10:30.293792 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4470 22:10:30.300558 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4471 22:10:30.303817 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4472 22:10:30.307043 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4473 22:10:30.313902 0 9 12 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
4474 22:10:30.317136 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 22:10:30.320319 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 22:10:30.323808 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 22:10:30.330746 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 22:10:30.333875 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 22:10:30.337420 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 22:10:30.343862 0 10 8 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
4481 22:10:30.347412 0 10 12 | B1->B0 | 3838 3c3c | 0 0 | (1 1) (1 1)
4482 22:10:30.350443 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 22:10:30.357283 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 22:10:30.360448 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 22:10:30.363707 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 22:10:30.370576 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 22:10:30.373787 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 22:10:30.377344 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 22:10:30.383948 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4490 22:10:30.387200 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 22:10:30.390235 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 22:10:30.397099 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 22:10:30.400372 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 22:10:30.403950 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 22:10:30.410128 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 22:10:30.413780 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 22:10:30.417229 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 22:10:30.423598 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 22:10:30.426966 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 22:10:30.430739 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 22:10:30.434271 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 22:10:30.440591 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 22:10:30.443749 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 22:10:30.447190 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 22:10:30.453472 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4506 22:10:30.457266 Total UI for P1: 0, mck2ui 16
4507 22:10:30.460163 best dqsien dly found for B0: ( 0, 13, 10)
4508 22:10:30.463683 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 22:10:30.466727 Total UI for P1: 0, mck2ui 16
4510 22:10:30.470177 best dqsien dly found for B1: ( 0, 13, 12)
4511 22:10:30.473452 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4512 22:10:30.476934 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4513 22:10:30.477016
4514 22:10:30.480202 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4515 22:10:30.486784 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4516 22:10:30.486866 [Gating] SW calibration Done
4517 22:10:30.486932 ==
4518 22:10:30.490155 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 22:10:30.496660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 22:10:30.496741 ==
4521 22:10:30.496828 RX Vref Scan: 0
4522 22:10:30.496889
4523 22:10:30.500058 RX Vref 0 -> 0, step: 1
4524 22:10:30.500122
4525 22:10:30.503360 RX Delay -230 -> 252, step: 16
4526 22:10:30.506557 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4527 22:10:30.510080 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4528 22:10:30.513421 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4529 22:10:30.519911 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4530 22:10:30.523277 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4531 22:10:30.526537 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4532 22:10:30.530086 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4533 22:10:30.536655 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4534 22:10:30.539725 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4535 22:10:30.543442 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4536 22:10:30.546283 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4537 22:10:30.550034 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4538 22:10:30.556428 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4539 22:10:30.559848 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4540 22:10:30.563036 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4541 22:10:30.566617 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4542 22:10:30.569977 ==
4543 22:10:30.570083 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 22:10:30.576603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 22:10:30.576708 ==
4546 22:10:30.576847 DQS Delay:
4547 22:10:30.580107 DQS0 = 0, DQS1 = 0
4548 22:10:30.580277 DQM Delay:
4549 22:10:30.583124 DQM0 = 49, DQM1 = 43
4550 22:10:30.583253 DQ Delay:
4551 22:10:30.586564 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4552 22:10:30.589792 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =49
4553 22:10:30.593082 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4554 22:10:30.596499 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =57
4555 22:10:30.596633
4556 22:10:30.596749
4557 22:10:30.596876 ==
4558 22:10:30.599829 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 22:10:30.603076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 22:10:30.603178 ==
4561 22:10:30.603270
4562 22:10:30.603358
4563 22:10:30.606323 TX Vref Scan disable
4564 22:10:30.609929 == TX Byte 0 ==
4565 22:10:30.613137 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4566 22:10:30.616261 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4567 22:10:30.619553 == TX Byte 1 ==
4568 22:10:30.623133 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4569 22:10:30.626597 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4570 22:10:30.626680 ==
4571 22:10:30.629607 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 22:10:30.633500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 22:10:30.636316 ==
4574 22:10:30.636397
4575 22:10:30.636462
4576 22:10:30.636522 TX Vref Scan disable
4577 22:10:30.640074 == TX Byte 0 ==
4578 22:10:30.643529 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4579 22:10:30.650075 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4580 22:10:30.650158 == TX Byte 1 ==
4581 22:10:30.653567 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4582 22:10:30.659941 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4583 22:10:30.660024
4584 22:10:30.660089 [DATLAT]
4585 22:10:30.660148 Freq=600, CH1 RK0
4586 22:10:30.660207
4587 22:10:30.663481 DATLAT Default: 0x9
4588 22:10:30.663564 0, 0xFFFF, sum = 0
4589 22:10:30.666463 1, 0xFFFF, sum = 0
4590 22:10:30.669756 2, 0xFFFF, sum = 0
4591 22:10:30.669839 3, 0xFFFF, sum = 0
4592 22:10:30.673355 4, 0xFFFF, sum = 0
4593 22:10:30.673439 5, 0xFFFF, sum = 0
4594 22:10:30.676266 6, 0xFFFF, sum = 0
4595 22:10:30.676351 7, 0xFFFF, sum = 0
4596 22:10:30.679729 8, 0x0, sum = 1
4597 22:10:30.679814 9, 0x0, sum = 2
4598 22:10:30.679881 10, 0x0, sum = 3
4599 22:10:30.683093 11, 0x0, sum = 4
4600 22:10:30.683177 best_step = 9
4601 22:10:30.683243
4602 22:10:30.683304 ==
4603 22:10:30.686691 Dram Type= 6, Freq= 0, CH_1, rank 0
4604 22:10:30.693020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 22:10:30.693105 ==
4606 22:10:30.693171 RX Vref Scan: 1
4607 22:10:30.693234
4608 22:10:30.696225 RX Vref 0 -> 0, step: 1
4609 22:10:30.696335
4610 22:10:30.699576 RX Delay -179 -> 252, step: 8
4611 22:10:30.699673
4612 22:10:30.702971 Set Vref, RX VrefLevel [Byte0]: 52
4613 22:10:30.706467 [Byte1]: 52
4614 22:10:30.706549
4615 22:10:30.709743 Final RX Vref Byte 0 = 52 to rank0
4616 22:10:30.713493 Final RX Vref Byte 1 = 52 to rank0
4617 22:10:30.716319 Final RX Vref Byte 0 = 52 to rank1
4618 22:10:30.719951 Final RX Vref Byte 1 = 52 to rank1==
4619 22:10:30.723164 Dram Type= 6, Freq= 0, CH_1, rank 0
4620 22:10:30.726317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 22:10:30.726399 ==
4622 22:10:30.730105 DQS Delay:
4623 22:10:30.730185 DQS0 = 0, DQS1 = 0
4624 22:10:30.732927 DQM Delay:
4625 22:10:30.733008 DQM0 = 48, DQM1 = 41
4626 22:10:30.733072 DQ Delay:
4627 22:10:30.736257 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4628 22:10:30.739512 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4629 22:10:30.742843 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4630 22:10:30.746105 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4631 22:10:30.746186
4632 22:10:30.746250
4633 22:10:30.756034 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4634 22:10:30.759870 CH1 RK0: MR19=808, MR18=4D73
4635 22:10:30.763218 CH1_RK0: MR19=0x808, MR18=0x4D73, DQSOSC=388, MR23=63, INC=174, DEC=116
4636 22:10:30.766543
4637 22:10:30.769256 ----->DramcWriteLeveling(PI) begin...
4638 22:10:30.769340 ==
4639 22:10:30.772932 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 22:10:30.776248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 22:10:30.776330 ==
4642 22:10:30.779361 Write leveling (Byte 0): 31 => 31
4643 22:10:30.782736 Write leveling (Byte 1): 29 => 29
4644 22:10:30.786074 DramcWriteLeveling(PI) end<-----
4645 22:10:30.786155
4646 22:10:30.786266 ==
4647 22:10:30.789639 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 22:10:30.792679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 22:10:30.792772 ==
4650 22:10:30.796090 [Gating] SW mode calibration
4651 22:10:30.802815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4652 22:10:30.809378 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4653 22:10:30.812663 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4654 22:10:30.815830 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4655 22:10:30.822765 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4656 22:10:30.826132 0 9 12 | B1->B0 | 2525 3232 | 0 1 | (0 0) (1 0)
4657 22:10:30.829019 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4658 22:10:30.835446 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 22:10:30.839154 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 22:10:30.842807 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 22:10:30.849026 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 22:10:30.852246 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 22:10:30.855541 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4664 22:10:30.862424 0 10 12 | B1->B0 | 3939 2b2b | 0 0 | (0 0) (0 0)
4665 22:10:30.865720 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 22:10:30.869194 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 22:10:30.872230 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 22:10:30.878637 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 22:10:30.881923 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 22:10:30.888721 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 22:10:30.892135 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4672 22:10:30.895588 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4673 22:10:30.898516 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 22:10:30.905188 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 22:10:30.908594 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 22:10:30.911843 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 22:10:30.918445 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 22:10:30.921621 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 22:10:30.925127 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 22:10:30.931826 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 22:10:30.935071 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 22:10:30.938434 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 22:10:30.945053 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 22:10:30.948648 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 22:10:30.951700 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 22:10:30.958869 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 22:10:30.962094 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4688 22:10:30.965200 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 22:10:30.968469 Total UI for P1: 0, mck2ui 16
4690 22:10:30.971924 best dqsien dly found for B0: ( 0, 13, 8)
4691 22:10:30.975287 Total UI for P1: 0, mck2ui 16
4692 22:10:30.978662 best dqsien dly found for B1: ( 0, 13, 10)
4693 22:10:30.981838 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4694 22:10:30.985050 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4695 22:10:30.985132
4696 22:10:30.991680 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4697 22:10:30.995114 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4698 22:10:30.995198 [Gating] SW calibration Done
4699 22:10:30.998356 ==
4700 22:10:31.002006 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 22:10:31.004952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 22:10:31.005036 ==
4703 22:10:31.005101 RX Vref Scan: 0
4704 22:10:31.005161
4705 22:10:31.008299 RX Vref 0 -> 0, step: 1
4706 22:10:31.008381
4707 22:10:31.011868 RX Delay -230 -> 252, step: 16
4708 22:10:31.014879 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4709 22:10:31.018016 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4710 22:10:31.024881 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4711 22:10:31.028326 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4712 22:10:31.031842 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4713 22:10:31.035033 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4714 22:10:31.038170 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4715 22:10:31.044845 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4716 22:10:31.048011 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4717 22:10:31.051286 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4718 22:10:31.054812 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4719 22:10:31.061419 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4720 22:10:31.064576 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4721 22:10:31.067945 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4722 22:10:31.071400 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4723 22:10:31.078076 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4724 22:10:31.078159 ==
4725 22:10:31.081295 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 22:10:31.084699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 22:10:31.084843 ==
4728 22:10:31.084910 DQS Delay:
4729 22:10:31.087754 DQS0 = 0, DQS1 = 0
4730 22:10:31.087836 DQM Delay:
4731 22:10:31.091405 DQM0 = 50, DQM1 = 45
4732 22:10:31.091487 DQ Delay:
4733 22:10:31.094485 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4734 22:10:31.097685 DQ4 =49, DQ5 =65, DQ6 =49, DQ7 =49
4735 22:10:31.101275 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4736 22:10:31.104710 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4737 22:10:31.104839
4738 22:10:31.104905
4739 22:10:31.104965 ==
4740 22:10:31.107817 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 22:10:31.111151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 22:10:31.111235 ==
4743 22:10:31.111301
4744 22:10:31.114630
4745 22:10:31.114713 TX Vref Scan disable
4746 22:10:31.118152 == TX Byte 0 ==
4747 22:10:31.121534 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4748 22:10:31.124696 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4749 22:10:31.127843 == TX Byte 1 ==
4750 22:10:31.131110 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4751 22:10:31.134453 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4752 22:10:31.134537 ==
4753 22:10:31.137697 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 22:10:31.144646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 22:10:31.144783 ==
4756 22:10:31.144870
4757 22:10:31.144931
4758 22:10:31.144991 TX Vref Scan disable
4759 22:10:31.148849 == TX Byte 0 ==
4760 22:10:31.152376 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4761 22:10:31.155834 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4762 22:10:31.159203 == TX Byte 1 ==
4763 22:10:31.162115 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4764 22:10:31.165609 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4765 22:10:31.169176
4766 22:10:31.169258 [DATLAT]
4767 22:10:31.169323 Freq=600, CH1 RK1
4768 22:10:31.169383
4769 22:10:31.172663 DATLAT Default: 0x9
4770 22:10:31.172795 0, 0xFFFF, sum = 0
4771 22:10:31.175440 1, 0xFFFF, sum = 0
4772 22:10:31.175525 2, 0xFFFF, sum = 0
4773 22:10:31.178939 3, 0xFFFF, sum = 0
4774 22:10:31.179023 4, 0xFFFF, sum = 0
4775 22:10:31.182103 5, 0xFFFF, sum = 0
4776 22:10:31.182188 6, 0xFFFF, sum = 0
4777 22:10:31.185776 7, 0xFFFF, sum = 0
4778 22:10:31.185862 8, 0x0, sum = 1
4779 22:10:31.189184 9, 0x0, sum = 2
4780 22:10:31.189270 10, 0x0, sum = 3
4781 22:10:31.192103 11, 0x0, sum = 4
4782 22:10:31.192189 best_step = 9
4783 22:10:31.192273
4784 22:10:31.192351 ==
4785 22:10:31.195602 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 22:10:31.202099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 22:10:31.202184 ==
4788 22:10:31.202269 RX Vref Scan: 0
4789 22:10:31.202348
4790 22:10:31.205565 RX Vref 0 -> 0, step: 1
4791 22:10:31.205648
4792 22:10:31.208884 RX Delay -163 -> 252, step: 8
4793 22:10:31.212051 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4794 22:10:31.215659 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4795 22:10:31.222496 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4796 22:10:31.225322 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4797 22:10:31.228674 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4798 22:10:31.232402 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4799 22:10:31.238358 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4800 22:10:31.241744 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4801 22:10:31.245107 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4802 22:10:31.248416 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4803 22:10:31.251905 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4804 22:10:31.258136 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4805 22:10:31.261501 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4806 22:10:31.264831 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4807 22:10:31.268443 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4808 22:10:31.274814 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4809 22:10:31.274888 ==
4810 22:10:31.278189 Dram Type= 6, Freq= 0, CH_1, rank 1
4811 22:10:31.281532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4812 22:10:31.281602 ==
4813 22:10:31.281669 DQS Delay:
4814 22:10:31.284843 DQS0 = 0, DQS1 = 0
4815 22:10:31.284916 DQM Delay:
4816 22:10:31.288105 DQM0 = 48, DQM1 = 44
4817 22:10:31.288176 DQ Delay:
4818 22:10:31.291617 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4819 22:10:31.295209 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4820 22:10:31.298181 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4821 22:10:31.301583 DQ12 =48, DQ13 =52, DQ14 =48, DQ15 =56
4822 22:10:31.301653
4823 22:10:31.301712
4824 22:10:31.307925 [DQSOSCAuto] RK1, (LSB)MR18= 0x581f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4825 22:10:31.311644 CH1 RK1: MR19=808, MR18=581F
4826 22:10:31.318449 CH1_RK1: MR19=0x808, MR18=0x581F, DQSOSC=393, MR23=63, INC=169, DEC=113
4827 22:10:31.321355 [RxdqsGatingPostProcess] freq 600
4828 22:10:31.328045 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4829 22:10:31.331158 Pre-setting of DQS Precalculation
4830 22:10:31.334624 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4831 22:10:31.341489 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4832 22:10:31.347690 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4833 22:10:31.347792
4834 22:10:31.347892
4835 22:10:31.351549 [Calibration Summary] 1200 Mbps
4836 22:10:31.354751 CH 0, Rank 0
4837 22:10:31.354821 SW Impedance : PASS
4838 22:10:31.357748 DUTY Scan : NO K
4839 22:10:31.361062 ZQ Calibration : PASS
4840 22:10:31.361133 Jitter Meter : NO K
4841 22:10:31.364557 CBT Training : PASS
4842 22:10:31.367813 Write leveling : PASS
4843 22:10:31.367920 RX DQS gating : PASS
4844 22:10:31.371649 RX DQ/DQS(RDDQC) : PASS
4845 22:10:31.371779 TX DQ/DQS : PASS
4846 22:10:31.374375 RX DATLAT : PASS
4847 22:10:31.377618 RX DQ/DQS(Engine): PASS
4848 22:10:31.377741 TX OE : NO K
4849 22:10:31.380862 All Pass.
4850 22:10:31.380987
4851 22:10:31.381098 CH 0, Rank 1
4852 22:10:31.384388 SW Impedance : PASS
4853 22:10:31.384513 DUTY Scan : NO K
4854 22:10:31.388072 ZQ Calibration : PASS
4855 22:10:31.391066 Jitter Meter : NO K
4856 22:10:31.391195 CBT Training : PASS
4857 22:10:31.394608 Write leveling : PASS
4858 22:10:31.397608 RX DQS gating : PASS
4859 22:10:31.397738 RX DQ/DQS(RDDQC) : PASS
4860 22:10:31.400643 TX DQ/DQS : PASS
4861 22:10:31.404047 RX DATLAT : PASS
4862 22:10:31.404172 RX DQ/DQS(Engine): PASS
4863 22:10:31.407428 TX OE : NO K
4864 22:10:31.407557 All Pass.
4865 22:10:31.407672
4866 22:10:31.410815 CH 1, Rank 0
4867 22:10:31.410930 SW Impedance : PASS
4868 22:10:31.414058 DUTY Scan : NO K
4869 22:10:31.417601 ZQ Calibration : PASS
4870 22:10:31.417722 Jitter Meter : NO K
4871 22:10:31.420840 CBT Training : PASS
4872 22:10:31.424178 Write leveling : PASS
4873 22:10:31.424305 RX DQS gating : PASS
4874 22:10:31.427394 RX DQ/DQS(RDDQC) : PASS
4875 22:10:31.427481 TX DQ/DQS : PASS
4876 22:10:31.431076 RX DATLAT : PASS
4877 22:10:31.434158 RX DQ/DQS(Engine): PASS
4878 22:10:31.434243 TX OE : NO K
4879 22:10:31.437338 All Pass.
4880 22:10:31.437423
4881 22:10:31.437527 CH 1, Rank 1
4882 22:10:31.440891 SW Impedance : PASS
4883 22:10:31.441016 DUTY Scan : NO K
4884 22:10:31.444253 ZQ Calibration : PASS
4885 22:10:31.447718 Jitter Meter : NO K
4886 22:10:31.447800 CBT Training : PASS
4887 22:10:31.450754 Write leveling : PASS
4888 22:10:31.454141 RX DQS gating : PASS
4889 22:10:31.454224 RX DQ/DQS(RDDQC) : PASS
4890 22:10:31.457128 TX DQ/DQS : PASS
4891 22:10:31.460720 RX DATLAT : PASS
4892 22:10:31.460842 RX DQ/DQS(Engine): PASS
4893 22:10:31.464194 TX OE : NO K
4894 22:10:31.464275 All Pass.
4895 22:10:31.464340
4896 22:10:31.467593 DramC Write-DBI off
4897 22:10:31.470926 PER_BANK_REFRESH: Hybrid Mode
4898 22:10:31.471008 TX_TRACKING: ON
4899 22:10:31.480909 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4900 22:10:31.484043 [FAST_K] Save calibration result to emmc
4901 22:10:31.487462 dramc_set_vcore_voltage set vcore to 662500
4902 22:10:31.490845 Read voltage for 933, 3
4903 22:10:31.490926 Vio18 = 0
4904 22:10:31.490989 Vcore = 662500
4905 22:10:31.493813 Vdram = 0
4906 22:10:31.493894 Vddq = 0
4907 22:10:31.493959 Vmddr = 0
4908 22:10:31.501038 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4909 22:10:31.504118 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4910 22:10:31.507308 MEM_TYPE=3, freq_sel=17
4911 22:10:31.510746 sv_algorithm_assistance_LP4_1600
4912 22:10:31.514031 ============ PULL DRAM RESETB DOWN ============
4913 22:10:31.517586 ========== PULL DRAM RESETB DOWN end =========
4914 22:10:31.523840 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4915 22:10:31.527133 ===================================
4916 22:10:31.527213 LPDDR4 DRAM CONFIGURATION
4917 22:10:31.530723 ===================================
4918 22:10:31.534223 EX_ROW_EN[0] = 0x0
4919 22:10:31.537642 EX_ROW_EN[1] = 0x0
4920 22:10:31.537752 LP4Y_EN = 0x0
4921 22:10:31.540478 WORK_FSP = 0x0
4922 22:10:31.540576 WL = 0x3
4923 22:10:31.544623 RL = 0x3
4924 22:10:31.544709 BL = 0x2
4925 22:10:31.547037 RPST = 0x0
4926 22:10:31.547111 RD_PRE = 0x0
4927 22:10:31.551133 WR_PRE = 0x1
4928 22:10:31.551231 WR_PST = 0x0
4929 22:10:31.553848 DBI_WR = 0x0
4930 22:10:31.553930 DBI_RD = 0x0
4931 22:10:31.557237 OTF = 0x1
4932 22:10:31.560216 ===================================
4933 22:10:31.563730 ===================================
4934 22:10:31.563854 ANA top config
4935 22:10:31.567168 ===================================
4936 22:10:31.570424 DLL_ASYNC_EN = 0
4937 22:10:31.573870 ALL_SLAVE_EN = 1
4938 22:10:31.573953 NEW_RANK_MODE = 1
4939 22:10:31.577849 DLL_IDLE_MODE = 1
4940 22:10:31.580425 LP45_APHY_COMB_EN = 1
4941 22:10:31.583777 TX_ODT_DIS = 1
4942 22:10:31.587014 NEW_8X_MODE = 1
4943 22:10:31.590640 ===================================
4944 22:10:31.593713 ===================================
4945 22:10:31.593796 data_rate = 1866
4946 22:10:31.597014 CKR = 1
4947 22:10:31.601079 DQ_P2S_RATIO = 8
4948 22:10:31.603523 ===================================
4949 22:10:31.607047 CA_P2S_RATIO = 8
4950 22:10:31.610721 DQ_CA_OPEN = 0
4951 22:10:31.613794 DQ_SEMI_OPEN = 0
4952 22:10:31.613878 CA_SEMI_OPEN = 0
4953 22:10:31.617047 CA_FULL_RATE = 0
4954 22:10:31.620261 DQ_CKDIV4_EN = 1
4955 22:10:31.623622 CA_CKDIV4_EN = 1
4956 22:10:31.626893 CA_PREDIV_EN = 0
4957 22:10:31.630723 PH8_DLY = 0
4958 22:10:31.630807 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4959 22:10:31.633506 DQ_AAMCK_DIV = 4
4960 22:10:31.637172 CA_AAMCK_DIV = 4
4961 22:10:31.640389 CA_ADMCK_DIV = 4
4962 22:10:31.643763 DQ_TRACK_CA_EN = 0
4963 22:10:31.646839 CA_PICK = 933
4964 22:10:31.646922 CA_MCKIO = 933
4965 22:10:31.650011 MCKIO_SEMI = 0
4966 22:10:31.653379 PLL_FREQ = 3732
4967 22:10:31.657026 DQ_UI_PI_RATIO = 32
4968 22:10:31.660370 CA_UI_PI_RATIO = 0
4969 22:10:31.663437 ===================================
4970 22:10:31.666641 ===================================
4971 22:10:31.670097 memory_type:LPDDR4
4972 22:10:31.670181 GP_NUM : 10
4973 22:10:31.673606 SRAM_EN : 1
4974 22:10:31.673691 MD32_EN : 0
4975 22:10:31.676934 ===================================
4976 22:10:31.679910 [ANA_INIT] >>>>>>>>>>>>>>
4977 22:10:31.683530 <<<<<< [CONFIGURE PHASE]: ANA_TX
4978 22:10:31.687046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4979 22:10:31.689962 ===================================
4980 22:10:31.693508 data_rate = 1866,PCW = 0X8f00
4981 22:10:31.696720 ===================================
4982 22:10:31.700317 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4983 22:10:31.706862 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4984 22:10:31.709964 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4985 22:10:31.716448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4986 22:10:31.720078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4987 22:10:31.723265 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4988 22:10:31.723397 [ANA_INIT] flow start
4989 22:10:31.726552 [ANA_INIT] PLL >>>>>>>>
4990 22:10:31.729933 [ANA_INIT] PLL <<<<<<<<
4991 22:10:31.730052 [ANA_INIT] MIDPI >>>>>>>>
4992 22:10:31.733015 [ANA_INIT] MIDPI <<<<<<<<
4993 22:10:31.736397 [ANA_INIT] DLL >>>>>>>>
4994 22:10:31.736518 [ANA_INIT] flow end
4995 22:10:31.743150 ============ LP4 DIFF to SE enter ============
4996 22:10:31.746443 ============ LP4 DIFF to SE exit ============
4997 22:10:31.749720 [ANA_INIT] <<<<<<<<<<<<<
4998 22:10:31.752997 [Flow] Enable top DCM control >>>>>
4999 22:10:31.756619 [Flow] Enable top DCM control <<<<<
5000 22:10:31.756741 Enable DLL master slave shuffle
5001 22:10:31.762994 ==============================================================
5002 22:10:31.766682 Gating Mode config
5003 22:10:31.769777 ==============================================================
5004 22:10:31.773187 Config description:
5005 22:10:31.782871 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5006 22:10:31.789828 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5007 22:10:31.793467 SELPH_MODE 0: By rank 1: By Phase
5008 22:10:31.799694 ==============================================================
5009 22:10:31.803236 GAT_TRACK_EN = 1
5010 22:10:31.806148 RX_GATING_MODE = 2
5011 22:10:31.809585 RX_GATING_TRACK_MODE = 2
5012 22:10:31.809706 SELPH_MODE = 1
5013 22:10:31.813113 PICG_EARLY_EN = 1
5014 22:10:31.816491 VALID_LAT_VALUE = 1
5015 22:10:31.823134 ==============================================================
5016 22:10:31.826720 Enter into Gating configuration >>>>
5017 22:10:31.829698 Exit from Gating configuration <<<<
5018 22:10:31.833055 Enter into DVFS_PRE_config >>>>>
5019 22:10:31.842984 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5020 22:10:31.846152 Exit from DVFS_PRE_config <<<<<
5021 22:10:31.849452 Enter into PICG configuration >>>>
5022 22:10:31.852788 Exit from PICG configuration <<<<
5023 22:10:31.856111 [RX_INPUT] configuration >>>>>
5024 22:10:31.859613 [RX_INPUT] configuration <<<<<
5025 22:10:31.862901 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5026 22:10:31.869355 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5027 22:10:31.876069 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 22:10:31.882717 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 22:10:31.886164 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5030 22:10:31.892359 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5031 22:10:31.899041 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5032 22:10:31.902330 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5033 22:10:31.905852 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5034 22:10:31.909019 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5035 22:10:31.912264 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5036 22:10:31.918955 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5037 22:10:31.922749 ===================================
5038 22:10:31.925918 LPDDR4 DRAM CONFIGURATION
5039 22:10:31.929232 ===================================
5040 22:10:31.929317 EX_ROW_EN[0] = 0x0
5041 22:10:31.932586 EX_ROW_EN[1] = 0x0
5042 22:10:31.932694 LP4Y_EN = 0x0
5043 22:10:31.935606 WORK_FSP = 0x0
5044 22:10:31.935706 WL = 0x3
5045 22:10:31.939246 RL = 0x3
5046 22:10:31.939328 BL = 0x2
5047 22:10:31.942275 RPST = 0x0
5048 22:10:31.942373 RD_PRE = 0x0
5049 22:10:31.945846 WR_PRE = 0x1
5050 22:10:31.945942 WR_PST = 0x0
5051 22:10:31.949170 DBI_WR = 0x0
5052 22:10:31.949251 DBI_RD = 0x0
5053 22:10:31.952276 OTF = 0x1
5054 22:10:31.955625 ===================================
5055 22:10:31.958872 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5056 22:10:31.962292 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5057 22:10:31.968572 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5058 22:10:31.972538 ===================================
5059 22:10:31.975400 LPDDR4 DRAM CONFIGURATION
5060 22:10:31.978649 ===================================
5061 22:10:31.978730 EX_ROW_EN[0] = 0x10
5062 22:10:31.982382 EX_ROW_EN[1] = 0x0
5063 22:10:31.982478 LP4Y_EN = 0x0
5064 22:10:31.985287 WORK_FSP = 0x0
5065 22:10:31.985368 WL = 0x3
5066 22:10:31.988637 RL = 0x3
5067 22:10:31.988750 BL = 0x2
5068 22:10:31.991975 RPST = 0x0
5069 22:10:31.992056 RD_PRE = 0x0
5070 22:10:31.995271 WR_PRE = 0x1
5071 22:10:31.995353 WR_PST = 0x0
5072 22:10:31.998745 DBI_WR = 0x0
5073 22:10:31.998825 DBI_RD = 0x0
5074 22:10:32.002492 OTF = 0x1
5075 22:10:32.005208 ===================================
5076 22:10:32.011958 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5077 22:10:32.015532 nWR fixed to 30
5078 22:10:32.018809 [ModeRegInit_LP4] CH0 RK0
5079 22:10:32.018889 [ModeRegInit_LP4] CH0 RK1
5080 22:10:32.021838 [ModeRegInit_LP4] CH1 RK0
5081 22:10:32.025134 [ModeRegInit_LP4] CH1 RK1
5082 22:10:32.025216 match AC timing 9
5083 22:10:32.031676 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5084 22:10:32.035256 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5085 22:10:32.038318 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5086 22:10:32.045227 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5087 22:10:32.048311 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5088 22:10:32.048418 ==
5089 22:10:32.051585 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 22:10:32.055247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 22:10:32.055345 ==
5092 22:10:32.062052 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5093 22:10:32.068499 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5094 22:10:32.071884 [CA 0] Center 37 (7~68) winsize 62
5095 22:10:32.075591 [CA 1] Center 38 (8~69) winsize 62
5096 22:10:32.078842 [CA 2] Center 35 (5~65) winsize 61
5097 22:10:32.081748 [CA 3] Center 35 (5~65) winsize 61
5098 22:10:32.084927 [CA 4] Center 34 (4~64) winsize 61
5099 22:10:32.088460 [CA 5] Center 33 (3~64) winsize 62
5100 22:10:32.088557
5101 22:10:32.092097 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5102 22:10:32.092179
5103 22:10:32.095125 [CATrainingPosCal] consider 1 rank data
5104 22:10:32.098218 u2DelayCellTimex100 = 270/100 ps
5105 22:10:32.101713 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5106 22:10:32.105129 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5107 22:10:32.108489 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5108 22:10:32.112247 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5109 22:10:32.115577 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5110 22:10:32.118411 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5111 22:10:32.118492
5112 22:10:32.125046 CA PerBit enable=1, Macro0, CA PI delay=33
5113 22:10:32.125127
5114 22:10:32.128235 [CBTSetCACLKResult] CA Dly = 33
5115 22:10:32.128319 CS Dly: 6 (0~37)
5116 22:10:32.128383 ==
5117 22:10:32.131616 Dram Type= 6, Freq= 0, CH_0, rank 1
5118 22:10:32.135007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 22:10:32.135089 ==
5120 22:10:32.141451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5121 22:10:32.148319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5122 22:10:32.151454 [CA 0] Center 38 (7~69) winsize 63
5123 22:10:32.154580 [CA 1] Center 38 (8~69) winsize 62
5124 22:10:32.158114 [CA 2] Center 36 (6~66) winsize 61
5125 22:10:32.161208 [CA 3] Center 35 (5~66) winsize 62
5126 22:10:32.164889 [CA 4] Center 34 (4~65) winsize 62
5127 22:10:32.168260 [CA 5] Center 34 (4~65) winsize 62
5128 22:10:32.168341
5129 22:10:32.171139 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5130 22:10:32.171220
5131 22:10:32.174580 [CATrainingPosCal] consider 2 rank data
5132 22:10:32.177969 u2DelayCellTimex100 = 270/100 ps
5133 22:10:32.181085 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5134 22:10:32.184644 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5135 22:10:32.187887 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5136 22:10:32.191151 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5137 22:10:32.194345 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5138 22:10:32.201083 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5139 22:10:32.201165
5140 22:10:32.204526 CA PerBit enable=1, Macro0, CA PI delay=34
5141 22:10:32.204607
5142 22:10:32.207964 [CBTSetCACLKResult] CA Dly = 34
5143 22:10:32.208052 CS Dly: 7 (0~39)
5144 22:10:32.208157
5145 22:10:32.211101 ----->DramcWriteLeveling(PI) begin...
5146 22:10:32.211211 ==
5147 22:10:32.214291 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 22:10:32.221063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 22:10:32.221145 ==
5150 22:10:32.224219 Write leveling (Byte 0): 32 => 32
5151 22:10:32.224300 Write leveling (Byte 1): 29 => 29
5152 22:10:32.228048 DramcWriteLeveling(PI) end<-----
5153 22:10:32.228129
5154 22:10:32.228193 ==
5155 22:10:32.231174 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 22:10:32.237711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 22:10:32.237818 ==
5158 22:10:32.241193 [Gating] SW mode calibration
5159 22:10:32.247534 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5160 22:10:32.250852 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5161 22:10:32.257755 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5162 22:10:32.260791 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 22:10:32.264507 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 22:10:32.268212 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 22:10:32.274569 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 22:10:32.277688 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 22:10:32.281030 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5168 22:10:32.287668 0 14 28 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
5169 22:10:32.291060 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5170 22:10:32.294422 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 22:10:32.301111 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 22:10:32.304425 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 22:10:32.307717 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 22:10:32.314326 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 22:10:32.317463 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5176 22:10:32.321216 0 15 28 | B1->B0 | 2c2c 4444 | 1 0 | (0 0) (0 0)
5177 22:10:32.327445 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 22:10:32.330929 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 22:10:32.334202 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 22:10:32.340823 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 22:10:32.344049 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 22:10:32.347574 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 22:10:32.354015 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5184 22:10:32.357643 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5185 22:10:32.360608 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 22:10:32.367044 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 22:10:32.370742 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 22:10:32.374030 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 22:10:32.380742 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 22:10:32.383862 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 22:10:32.387242 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 22:10:32.393775 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 22:10:32.397037 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 22:10:32.400914 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 22:10:32.407086 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 22:10:32.410576 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 22:10:32.414003 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 22:10:32.417403 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 22:10:32.424007 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5200 22:10:32.427161 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5201 22:10:32.430511 Total UI for P1: 0, mck2ui 16
5202 22:10:32.434147 best dqsien dly found for B0: ( 1, 2, 24)
5203 22:10:32.437198 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 22:10:32.441055 Total UI for P1: 0, mck2ui 16
5205 22:10:32.443990 best dqsien dly found for B1: ( 1, 2, 28)
5206 22:10:32.447358 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5207 22:10:32.450833 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5208 22:10:32.450915
5209 22:10:32.457390 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5210 22:10:32.460836 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5211 22:10:32.460922 [Gating] SW calibration Done
5212 22:10:32.463893 ==
5213 22:10:32.467213 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 22:10:32.470739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 22:10:32.470823 ==
5216 22:10:32.470889 RX Vref Scan: 0
5217 22:10:32.470948
5218 22:10:32.474102 RX Vref 0 -> 0, step: 1
5219 22:10:32.474184
5220 22:10:32.477475 RX Delay -80 -> 252, step: 8
5221 22:10:32.480746 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5222 22:10:32.483902 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5223 22:10:32.490836 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5224 22:10:32.494184 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5225 22:10:32.497266 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5226 22:10:32.500347 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5227 22:10:32.503847 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5228 22:10:32.507195 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5229 22:10:32.513906 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5230 22:10:32.517031 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5231 22:10:32.520413 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5232 22:10:32.523680 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5233 22:10:32.526882 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5234 22:10:32.530175 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5235 22:10:32.537025 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5236 22:10:32.540430 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5237 22:10:32.540512 ==
5238 22:10:32.543919 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 22:10:32.546892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 22:10:32.547000 ==
5241 22:10:32.550287 DQS Delay:
5242 22:10:32.550397 DQS0 = 0, DQS1 = 0
5243 22:10:32.550462 DQM Delay:
5244 22:10:32.553833 DQM0 = 106, DQM1 = 90
5245 22:10:32.553914 DQ Delay:
5246 22:10:32.556881 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5247 22:10:32.560614 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5248 22:10:32.563839 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5249 22:10:32.566860 DQ12 =91, DQ13 =91, DQ14 =103, DQ15 =99
5250 22:10:32.566942
5251 22:10:32.567006
5252 22:10:32.570314 ==
5253 22:10:32.573418 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 22:10:32.577130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 22:10:32.577254 ==
5256 22:10:32.577365
5257 22:10:32.577477
5258 22:10:32.580115 TX Vref Scan disable
5259 22:10:32.580234 == TX Byte 0 ==
5260 22:10:32.583728 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5261 22:10:32.590620 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5262 22:10:32.590741 == TX Byte 1 ==
5263 22:10:32.593691 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5264 22:10:32.600075 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5265 22:10:32.600213 ==
5266 22:10:32.603443 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 22:10:32.606845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 22:10:32.606968 ==
5269 22:10:32.607077
5270 22:10:32.607187
5271 22:10:32.609898 TX Vref Scan disable
5272 22:10:32.613247 == TX Byte 0 ==
5273 22:10:32.616861 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5274 22:10:32.620133 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5275 22:10:32.623298 == TX Byte 1 ==
5276 22:10:32.626591 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5277 22:10:32.629927 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5278 22:10:32.630047
5279 22:10:32.633415 [DATLAT]
5280 22:10:32.633552 Freq=933, CH0 RK0
5281 22:10:32.633694
5282 22:10:32.636668 DATLAT Default: 0xd
5283 22:10:32.636809 0, 0xFFFF, sum = 0
5284 22:10:32.640236 1, 0xFFFF, sum = 0
5285 22:10:32.640388 2, 0xFFFF, sum = 0
5286 22:10:32.643241 3, 0xFFFF, sum = 0
5287 22:10:32.643361 4, 0xFFFF, sum = 0
5288 22:10:32.646464 5, 0xFFFF, sum = 0
5289 22:10:32.646562 6, 0xFFFF, sum = 0
5290 22:10:32.649863 7, 0xFFFF, sum = 0
5291 22:10:32.649960 8, 0xFFFF, sum = 0
5292 22:10:32.653247 9, 0xFFFF, sum = 0
5293 22:10:32.653330 10, 0x0, sum = 1
5294 22:10:32.656652 11, 0x0, sum = 2
5295 22:10:32.656738 12, 0x0, sum = 3
5296 22:10:32.659901 13, 0x0, sum = 4
5297 22:10:32.659984 best_step = 11
5298 22:10:32.660049
5299 22:10:32.660108 ==
5300 22:10:32.663241 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 22:10:32.666740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 22:10:32.669998 ==
5303 22:10:32.670081 RX Vref Scan: 1
5304 22:10:32.670146
5305 22:10:32.673141 RX Vref 0 -> 0, step: 1
5306 22:10:32.673223
5307 22:10:32.676314 RX Delay -53 -> 252, step: 4
5308 22:10:32.676396
5309 22:10:32.679795 Set Vref, RX VrefLevel [Byte0]: 61
5310 22:10:32.679878 [Byte1]: 51
5311 22:10:32.685172
5312 22:10:32.685254 Final RX Vref Byte 0 = 61 to rank0
5313 22:10:32.688342 Final RX Vref Byte 1 = 51 to rank0
5314 22:10:32.691812 Final RX Vref Byte 0 = 61 to rank1
5315 22:10:32.695644 Final RX Vref Byte 1 = 51 to rank1==
5316 22:10:32.698519 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 22:10:32.705030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 22:10:32.705112 ==
5319 22:10:32.705177 DQS Delay:
5320 22:10:32.705238 DQS0 = 0, DQS1 = 0
5321 22:10:32.708495 DQM Delay:
5322 22:10:32.708576 DQM0 = 107, DQM1 = 91
5323 22:10:32.711639 DQ Delay:
5324 22:10:32.715014 DQ0 =106, DQ1 =106, DQ2 =106, DQ3 =104
5325 22:10:32.718069 DQ4 =108, DQ5 =100, DQ6 =116, DQ7 =116
5326 22:10:32.721850 DQ8 =88, DQ9 =76, DQ10 =92, DQ11 =90
5327 22:10:32.724862 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =98
5328 22:10:32.724943
5329 22:10:32.725031
5330 22:10:32.731576 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
5331 22:10:32.734758 CH0 RK0: MR19=505, MR18=241F
5332 22:10:32.741593 CH0_RK0: MR19=0x505, MR18=0x241F, DQSOSC=410, MR23=63, INC=64, DEC=42
5333 22:10:32.741718
5334 22:10:32.744596 ----->DramcWriteLeveling(PI) begin...
5335 22:10:32.744733 ==
5336 22:10:32.748120 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 22:10:32.751495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 22:10:32.751615 ==
5339 22:10:32.754886 Write leveling (Byte 0): 33 => 33
5340 22:10:32.758192 Write leveling (Byte 1): 29 => 29
5341 22:10:32.761841 DramcWriteLeveling(PI) end<-----
5342 22:10:32.761963
5343 22:10:32.762070 ==
5344 22:10:32.764604 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 22:10:32.768209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 22:10:32.771336 ==
5347 22:10:32.771455 [Gating] SW mode calibration
5348 22:10:32.778020 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5349 22:10:32.784618 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5350 22:10:32.788090 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 22:10:32.794685 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 22:10:32.797768 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 22:10:32.801346 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 22:10:32.807836 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 22:10:32.811254 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 22:10:32.814711 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5357 22:10:32.821125 0 14 28 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
5358 22:10:32.824499 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5359 22:10:32.827842 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 22:10:32.834148 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 22:10:32.837625 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 22:10:32.841223 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 22:10:32.847655 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 22:10:32.850616 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 22:10:32.854012 0 15 28 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
5366 22:10:32.860747 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 22:10:32.864300 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 22:10:32.867534 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 22:10:32.874340 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 22:10:32.877150 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 22:10:32.880522 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 22:10:32.887276 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 22:10:32.890691 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5374 22:10:32.893978 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 22:10:32.900488 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 22:10:32.904255 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 22:10:32.907446 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 22:10:32.914038 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 22:10:32.916854 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 22:10:32.920302 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 22:10:32.927146 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 22:10:32.930320 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 22:10:32.933653 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 22:10:32.937267 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 22:10:32.943472 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 22:10:32.946816 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 22:10:32.950429 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 22:10:32.957200 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 22:10:32.960288 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5390 22:10:32.963391 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 22:10:32.966863 Total UI for P1: 0, mck2ui 16
5392 22:10:32.970129 best dqsien dly found for B0: ( 1, 2, 28)
5393 22:10:32.973830 Total UI for P1: 0, mck2ui 16
5394 22:10:32.976812 best dqsien dly found for B1: ( 1, 2, 28)
5395 22:10:32.980122 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5396 22:10:32.983677 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5397 22:10:32.983757
5398 22:10:32.990515 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5399 22:10:32.993633 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5400 22:10:32.997096 [Gating] SW calibration Done
5401 22:10:32.997227 ==
5402 22:10:33.000077 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 22:10:33.003450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 22:10:33.003577 ==
5405 22:10:33.003698 RX Vref Scan: 0
5406 22:10:33.003817
5407 22:10:33.006786 RX Vref 0 -> 0, step: 1
5408 22:10:33.006919
5409 22:10:33.010226 RX Delay -80 -> 252, step: 8
5410 22:10:33.013410 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5411 22:10:33.016694 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5412 22:10:33.023522 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5413 22:10:33.026687 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5414 22:10:33.030214 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5415 22:10:33.033385 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5416 22:10:33.036688 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5417 22:10:33.040128 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5418 22:10:33.043482 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5419 22:10:33.050102 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5420 22:10:33.053243 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5421 22:10:33.056570 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5422 22:10:33.059880 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5423 22:10:33.063461 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5424 22:10:33.066765 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5425 22:10:33.073185 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5426 22:10:33.073268 ==
5427 22:10:33.076867 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 22:10:33.079964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 22:10:33.080048 ==
5430 22:10:33.080116 DQS Delay:
5431 22:10:33.083757 DQS0 = 0, DQS1 = 0
5432 22:10:33.083839 DQM Delay:
5433 22:10:33.086530 DQM0 = 103, DQM1 = 90
5434 22:10:33.086612 DQ Delay:
5435 22:10:33.089920 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5436 22:10:33.093473 DQ4 =103, DQ5 =91, DQ6 =115, DQ7 =111
5437 22:10:33.096710 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5438 22:10:33.099897 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5439 22:10:33.099978
5440 22:10:33.100042
5441 22:10:33.100102 ==
5442 22:10:33.103468 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 22:10:33.106799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 22:10:33.109906 ==
5445 22:10:33.110002
5446 22:10:33.110090
5447 22:10:33.110177 TX Vref Scan disable
5448 22:10:33.113234 == TX Byte 0 ==
5449 22:10:33.116627 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5450 22:10:33.120506 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5451 22:10:33.123123 == TX Byte 1 ==
5452 22:10:33.127084 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5453 22:10:33.129854 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5454 22:10:33.133174 ==
5455 22:10:33.133271 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 22:10:33.139854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 22:10:33.140006 ==
5458 22:10:33.140110
5459 22:10:33.140171
5460 22:10:33.143301 TX Vref Scan disable
5461 22:10:33.143378 == TX Byte 0 ==
5462 22:10:33.150098 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5463 22:10:33.153167 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5464 22:10:33.153248 == TX Byte 1 ==
5465 22:10:33.159926 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5466 22:10:33.163260 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5467 22:10:33.163384
5468 22:10:33.163500 [DATLAT]
5469 22:10:33.166639 Freq=933, CH0 RK1
5470 22:10:33.166774
5471 22:10:33.166885 DATLAT Default: 0xb
5472 22:10:33.169963 0, 0xFFFF, sum = 0
5473 22:10:33.170097 1, 0xFFFF, sum = 0
5474 22:10:33.173325 2, 0xFFFF, sum = 0
5475 22:10:33.173429 3, 0xFFFF, sum = 0
5476 22:10:33.176804 4, 0xFFFF, sum = 0
5477 22:10:33.176879 5, 0xFFFF, sum = 0
5478 22:10:33.179783 6, 0xFFFF, sum = 0
5479 22:10:33.179881 7, 0xFFFF, sum = 0
5480 22:10:33.183205 8, 0xFFFF, sum = 0
5481 22:10:33.183280 9, 0xFFFF, sum = 0
5482 22:10:33.186531 10, 0x0, sum = 1
5483 22:10:33.186607 11, 0x0, sum = 2
5484 22:10:33.190192 12, 0x0, sum = 3
5485 22:10:33.190262 13, 0x0, sum = 4
5486 22:10:33.193387 best_step = 11
5487 22:10:33.193460
5488 22:10:33.193541 ==
5489 22:10:33.196324 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 22:10:33.199986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 22:10:33.200064 ==
5492 22:10:33.203175 RX Vref Scan: 0
5493 22:10:33.203253
5494 22:10:33.203355 RX Vref 0 -> 0, step: 1
5495 22:10:33.203413
5496 22:10:33.206557 RX Delay -53 -> 252, step: 4
5497 22:10:33.213576 iDelay=203, Bit 0, Center 106 (19 ~ 194) 176
5498 22:10:33.216764 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5499 22:10:33.220035 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5500 22:10:33.223674 iDelay=203, Bit 3, Center 100 (15 ~ 186) 172
5501 22:10:33.226743 iDelay=203, Bit 4, Center 106 (19 ~ 194) 176
5502 22:10:33.233428 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5503 22:10:33.236616 iDelay=203, Bit 6, Center 112 (23 ~ 202) 180
5504 22:10:33.240364 iDelay=203, Bit 7, Center 112 (27 ~ 198) 172
5505 22:10:33.243535 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5506 22:10:33.246817 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5507 22:10:33.253263 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5508 22:10:33.257172 iDelay=203, Bit 11, Center 90 (7 ~ 174) 168
5509 22:10:33.260223 iDelay=203, Bit 12, Center 98 (15 ~ 182) 168
5510 22:10:33.263004 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5511 22:10:33.266469 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5512 22:10:33.273094 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5513 22:10:33.273219 ==
5514 22:10:33.276623 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 22:10:33.279825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 22:10:33.279931 ==
5517 22:10:33.280026 DQS Delay:
5518 22:10:33.283116 DQS0 = 0, DQS1 = 0
5519 22:10:33.283199 DQM Delay:
5520 22:10:33.286551 DQM0 = 105, DQM1 = 92
5521 22:10:33.286650 DQ Delay:
5522 22:10:33.290032 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =100
5523 22:10:33.293614 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5524 22:10:33.296505 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90
5525 22:10:33.299843 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5526 22:10:33.299928
5527 22:10:33.299994
5528 22:10:33.310044 [DQSOSCAuto] RK1, (LSB)MR18= 0x2809, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5529 22:10:33.310128 CH0 RK1: MR19=505, MR18=2809
5530 22:10:33.316962 CH0_RK1: MR19=0x505, MR18=0x2809, DQSOSC=409, MR23=63, INC=64, DEC=43
5531 22:10:33.320034 [RxdqsGatingPostProcess] freq 933
5532 22:10:33.326630 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5533 22:10:33.330046 best DQS0 dly(2T, 0.5T) = (0, 10)
5534 22:10:33.333033 best DQS1 dly(2T, 0.5T) = (0, 10)
5535 22:10:33.336341 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5536 22:10:33.339867 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5537 22:10:33.339950 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 22:10:33.343245 best DQS1 dly(2T, 0.5T) = (0, 10)
5539 22:10:33.346280 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 22:10:33.349829 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5541 22:10:33.352966 Pre-setting of DQS Precalculation
5542 22:10:33.359950 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5543 22:10:33.360034 ==
5544 22:10:33.363091 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 22:10:33.366425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 22:10:33.366509 ==
5547 22:10:33.373203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 22:10:33.379704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5549 22:10:33.383080 [CA 0] Center 37 (7~68) winsize 62
5550 22:10:33.386208 [CA 1] Center 37 (7~68) winsize 62
5551 22:10:33.389670 [CA 2] Center 35 (5~66) winsize 62
5552 22:10:33.392724 [CA 3] Center 34 (4~65) winsize 62
5553 22:10:33.396155 [CA 4] Center 34 (4~65) winsize 62
5554 22:10:33.396237 [CA 5] Center 34 (4~65) winsize 62
5555 22:10:33.399455
5556 22:10:33.402935 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5557 22:10:33.403018
5558 22:10:33.406205 [CATrainingPosCal] consider 1 rank data
5559 22:10:33.409701 u2DelayCellTimex100 = 270/100 ps
5560 22:10:33.412803 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5561 22:10:33.416412 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5562 22:10:33.419538 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5563 22:10:33.422820 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5564 22:10:33.426081 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5565 22:10:33.429153 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5566 22:10:33.429235
5567 22:10:33.432644 CA PerBit enable=1, Macro0, CA PI delay=34
5568 22:10:33.435794
5569 22:10:33.435895 [CBTSetCACLKResult] CA Dly = 34
5570 22:10:33.439270 CS Dly: 6 (0~37)
5571 22:10:33.439352 ==
5572 22:10:33.442657 Dram Type= 6, Freq= 0, CH_1, rank 1
5573 22:10:33.446003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 22:10:33.446088 ==
5575 22:10:33.452629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5576 22:10:33.459304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5577 22:10:33.462734 [CA 0] Center 38 (7~69) winsize 63
5578 22:10:33.465920 [CA 1] Center 38 (8~69) winsize 62
5579 22:10:33.469152 [CA 2] Center 36 (6~66) winsize 61
5580 22:10:33.472859 [CA 3] Center 35 (5~65) winsize 61
5581 22:10:33.476256 [CA 4] Center 35 (6~65) winsize 60
5582 22:10:33.479531 [CA 5] Center 34 (4~65) winsize 62
5583 22:10:33.479654
5584 22:10:33.482512 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5585 22:10:33.482632
5586 22:10:33.485772 [CATrainingPosCal] consider 2 rank data
5587 22:10:33.489113 u2DelayCellTimex100 = 270/100 ps
5588 22:10:33.492290 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5589 22:10:33.495723 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5590 22:10:33.499175 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5591 22:10:33.502539 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5592 22:10:33.506015 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5593 22:10:33.509025 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5594 22:10:33.509108
5595 22:10:33.515818 CA PerBit enable=1, Macro0, CA PI delay=34
5596 22:10:33.515926
5597 22:10:33.516023 [CBTSetCACLKResult] CA Dly = 34
5598 22:10:33.519030 CS Dly: 7 (0~39)
5599 22:10:33.519129
5600 22:10:33.522588 ----->DramcWriteLeveling(PI) begin...
5601 22:10:33.522671 ==
5602 22:10:33.525716 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 22:10:33.529010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 22:10:33.529121 ==
5605 22:10:33.532489 Write leveling (Byte 0): 27 => 27
5606 22:10:33.535849 Write leveling (Byte 1): 28 => 28
5607 22:10:33.539293 DramcWriteLeveling(PI) end<-----
5608 22:10:33.539376
5609 22:10:33.539442 ==
5610 22:10:33.542334 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 22:10:33.545963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 22:10:33.548891 ==
5613 22:10:33.548974 [Gating] SW mode calibration
5614 22:10:33.555491 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5615 22:10:33.562194 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5616 22:10:33.565961 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 22:10:33.572386 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 22:10:33.575546 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 22:10:33.579026 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 22:10:33.585497 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 22:10:33.588776 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 22:10:33.592124 0 14 24 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 0)
5623 22:10:33.599258 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5624 22:10:33.601886 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 22:10:33.605344 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 22:10:33.612008 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 22:10:33.615342 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 22:10:33.618582 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 22:10:33.625067 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 22:10:33.628522 0 15 24 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
5631 22:10:33.632124 0 15 28 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
5632 22:10:33.638834 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 22:10:33.642083 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 22:10:33.645244 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 22:10:33.648759 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 22:10:33.655235 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 22:10:33.658965 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5638 22:10:33.662053 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5639 22:10:33.668889 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 22:10:33.671710 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 22:10:33.675053 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 22:10:33.681858 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 22:10:33.685021 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 22:10:33.688560 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 22:10:33.695143 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 22:10:33.698919 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 22:10:33.701870 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 22:10:33.708256 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 22:10:33.711517 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 22:10:33.715169 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 22:10:33.721831 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 22:10:33.725031 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 22:10:33.728484 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5654 22:10:33.735065 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5655 22:10:33.738567 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 22:10:33.741784 Total UI for P1: 0, mck2ui 16
5657 22:10:33.745119 best dqsien dly found for B0: ( 1, 2, 22)
5658 22:10:33.748514 Total UI for P1: 0, mck2ui 16
5659 22:10:33.751817 best dqsien dly found for B1: ( 1, 2, 24)
5660 22:10:33.755007 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5661 22:10:33.758506 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5662 22:10:33.758614
5663 22:10:33.761642 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5664 22:10:33.765094 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5665 22:10:33.768250 [Gating] SW calibration Done
5666 22:10:33.768323 ==
5667 22:10:33.771797 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 22:10:33.774950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 22:10:33.775049 ==
5670 22:10:33.778415 RX Vref Scan: 0
5671 22:10:33.778486
5672 22:10:33.781357 RX Vref 0 -> 0, step: 1
5673 22:10:33.781431
5674 22:10:33.781498 RX Delay -80 -> 252, step: 8
5675 22:10:33.788567 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5676 22:10:33.791734 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5677 22:10:33.795340 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5678 22:10:33.798435 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5679 22:10:33.801490 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5680 22:10:33.804787 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5681 22:10:33.811476 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5682 22:10:33.814896 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5683 22:10:33.818113 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5684 22:10:33.821511 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5685 22:10:33.825167 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5686 22:10:33.828615 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5687 22:10:33.834916 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5688 22:10:33.838709 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5689 22:10:33.841705 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5690 22:10:33.844742 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5691 22:10:33.844872 ==
5692 22:10:33.848019 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 22:10:33.851472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 22:10:33.855092 ==
5695 22:10:33.855175 DQS Delay:
5696 22:10:33.855241 DQS0 = 0, DQS1 = 0
5697 22:10:33.857885 DQM Delay:
5698 22:10:33.857969 DQM0 = 101, DQM1 = 96
5699 22:10:33.861531 DQ Delay:
5700 22:10:33.864945 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5701 22:10:33.868204 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5702 22:10:33.871523 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =95
5703 22:10:33.874955 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5704 22:10:33.875048
5705 22:10:33.875117
5706 22:10:33.875178 ==
5707 22:10:33.878099 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 22:10:33.881607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 22:10:33.881690 ==
5710 22:10:33.881756
5711 22:10:33.881817
5712 22:10:33.884453 TX Vref Scan disable
5713 22:10:33.887795 == TX Byte 0 ==
5714 22:10:33.891356 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5715 22:10:33.894573 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5716 22:10:33.897798 == TX Byte 1 ==
5717 22:10:33.901076 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5718 22:10:33.904501 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5719 22:10:33.904583 ==
5720 22:10:33.907878 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 22:10:33.911227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 22:10:33.911310 ==
5723 22:10:33.914297
5724 22:10:33.914379
5725 22:10:33.914445 TX Vref Scan disable
5726 22:10:33.917952 == TX Byte 0 ==
5727 22:10:33.921272 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5728 22:10:33.927614 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5729 22:10:33.927698 == TX Byte 1 ==
5730 22:10:33.931193 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5731 22:10:33.937887 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5732 22:10:33.937969
5733 22:10:33.938034 [DATLAT]
5734 22:10:33.938094 Freq=933, CH1 RK0
5735 22:10:33.938153
5736 22:10:33.941124 DATLAT Default: 0xd
5737 22:10:33.941205 0, 0xFFFF, sum = 0
5738 22:10:33.944210 1, 0xFFFF, sum = 0
5739 22:10:33.944293 2, 0xFFFF, sum = 0
5740 22:10:33.947568 3, 0xFFFF, sum = 0
5741 22:10:33.950959 4, 0xFFFF, sum = 0
5742 22:10:33.951042 5, 0xFFFF, sum = 0
5743 22:10:33.954156 6, 0xFFFF, sum = 0
5744 22:10:33.954239 7, 0xFFFF, sum = 0
5745 22:10:33.957574 8, 0xFFFF, sum = 0
5746 22:10:33.957657 9, 0xFFFF, sum = 0
5747 22:10:33.960773 10, 0x0, sum = 1
5748 22:10:33.960870 11, 0x0, sum = 2
5749 22:10:33.964377 12, 0x0, sum = 3
5750 22:10:33.964460 13, 0x0, sum = 4
5751 22:10:33.964527 best_step = 11
5752 22:10:33.964604
5753 22:10:33.967672 ==
5754 22:10:33.970694 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 22:10:33.974172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 22:10:33.974255 ==
5757 22:10:33.974321 RX Vref Scan: 1
5758 22:10:33.974382
5759 22:10:33.977684 RX Vref 0 -> 0, step: 1
5760 22:10:33.977766
5761 22:10:33.980971 RX Delay -53 -> 252, step: 4
5762 22:10:33.981053
5763 22:10:33.984267 Set Vref, RX VrefLevel [Byte0]: 52
5764 22:10:33.987571 [Byte1]: 52
5765 22:10:33.987653
5766 22:10:33.990874 Final RX Vref Byte 0 = 52 to rank0
5767 22:10:33.994496 Final RX Vref Byte 1 = 52 to rank0
5768 22:10:33.997627 Final RX Vref Byte 0 = 52 to rank1
5769 22:10:34.000987 Final RX Vref Byte 1 = 52 to rank1==
5770 22:10:34.004076 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 22:10:34.007424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 22:10:34.007508 ==
5773 22:10:34.010824 DQS Delay:
5774 22:10:34.010930 DQS0 = 0, DQS1 = 0
5775 22:10:34.014706 DQM Delay:
5776 22:10:34.014821 DQM0 = 104, DQM1 = 96
5777 22:10:34.014885 DQ Delay:
5778 22:10:34.017345 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5779 22:10:34.020830 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5780 22:10:34.024177 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =92
5781 22:10:34.030920 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5782 22:10:34.030999
5783 22:10:34.031070
5784 22:10:34.037694 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5785 22:10:34.040909 CH1 RK0: MR19=505, MR18=1C34
5786 22:10:34.047864 CH1_RK0: MR19=0x505, MR18=0x1C34, DQSOSC=405, MR23=63, INC=66, DEC=44
5787 22:10:34.047953
5788 22:10:34.050724 ----->DramcWriteLeveling(PI) begin...
5789 22:10:34.050797 ==
5790 22:10:34.053909 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 22:10:34.057759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 22:10:34.057843 ==
5793 22:10:34.060629 Write leveling (Byte 0): 27 => 27
5794 22:10:34.064387 Write leveling (Byte 1): 29 => 29
5795 22:10:34.067329 DramcWriteLeveling(PI) end<-----
5796 22:10:34.067457
5797 22:10:34.067574 ==
5798 22:10:34.070789 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 22:10:34.074462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 22:10:34.074589 ==
5801 22:10:34.077596 [Gating] SW mode calibration
5802 22:10:34.084126 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5803 22:10:34.090740 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5804 22:10:34.094260 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5805 22:10:34.100884 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 22:10:34.104348 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 22:10:34.107449 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 22:10:34.111166 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 22:10:34.117551 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 22:10:34.120884 0 14 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 0)
5811 22:10:34.124316 0 14 28 | B1->B0 | 2323 2b2b | 0 1 | (1 0) (1 0)
5812 22:10:34.130867 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 22:10:34.133811 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 22:10:34.137300 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 22:10:34.144300 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 22:10:34.147348 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 22:10:34.150820 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 22:10:34.157442 0 15 24 | B1->B0 | 2929 2424 | 0 0 | (0 0) (1 1)
5819 22:10:34.160812 0 15 28 | B1->B0 | 4040 3838 | 0 0 | (0 0) (1 1)
5820 22:10:34.164018 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5821 22:10:34.170755 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 22:10:34.173970 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 22:10:34.177550 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 22:10:34.183888 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 22:10:34.187564 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 22:10:34.190807 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5827 22:10:34.197137 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5828 22:10:34.200626 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 22:10:34.203969 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 22:10:34.210803 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 22:10:34.213825 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 22:10:34.217151 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 22:10:34.220393 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 22:10:34.227512 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 22:10:34.230521 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 22:10:34.233884 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 22:10:34.240850 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 22:10:34.243877 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 22:10:34.247206 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 22:10:34.253876 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 22:10:34.257209 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 22:10:34.260837 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5843 22:10:34.267382 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 22:10:34.267465 Total UI for P1: 0, mck2ui 16
5845 22:10:34.274253 best dqsien dly found for B0: ( 1, 2, 24)
5846 22:10:34.274336 Total UI for P1: 0, mck2ui 16
5847 22:10:34.280486 best dqsien dly found for B1: ( 1, 2, 24)
5848 22:10:34.283843 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5849 22:10:34.287308 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5850 22:10:34.287430
5851 22:10:34.290936 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5852 22:10:34.293613 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5853 22:10:34.296856 [Gating] SW calibration Done
5854 22:10:34.296939 ==
5855 22:10:34.300200 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 22:10:34.303914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 22:10:34.303998 ==
5858 22:10:34.307470 RX Vref Scan: 0
5859 22:10:34.307552
5860 22:10:34.307618 RX Vref 0 -> 0, step: 1
5861 22:10:34.307678
5862 22:10:34.310539 RX Delay -80 -> 252, step: 8
5863 22:10:34.313800 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5864 22:10:34.320493 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5865 22:10:34.323801 iDelay=208, Bit 2, Center 91 (8 ~ 175) 168
5866 22:10:34.327143 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5867 22:10:34.331315 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5868 22:10:34.333797 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5869 22:10:34.337203 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5870 22:10:34.343759 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5871 22:10:34.346950 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5872 22:10:34.350283 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5873 22:10:34.353843 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5874 22:10:34.357049 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5875 22:10:34.363715 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5876 22:10:34.366735 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5877 22:10:34.370560 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5878 22:10:34.373535 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5879 22:10:34.373618 ==
5880 22:10:34.376733 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 22:10:34.383595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 22:10:34.383679 ==
5883 22:10:34.383746 DQS Delay:
5884 22:10:34.383807 DQS0 = 0, DQS1 = 0
5885 22:10:34.387024 DQM Delay:
5886 22:10:34.387111 DQM0 = 103, DQM1 = 97
5887 22:10:34.390164 DQ Delay:
5888 22:10:34.393309 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5889 22:10:34.396628 DQ4 =103, DQ5 =115, DQ6 =107, DQ7 =103
5890 22:10:34.400377 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =87
5891 22:10:34.403385 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5892 22:10:34.403468
5893 22:10:34.403533
5894 22:10:34.403592 ==
5895 22:10:34.406392 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 22:10:34.409827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 22:10:34.409910 ==
5898 22:10:34.409976
5899 22:10:34.410035
5900 22:10:34.413193 TX Vref Scan disable
5901 22:10:34.416566 == TX Byte 0 ==
5902 22:10:34.420157 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5903 22:10:34.423397 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5904 22:10:34.426712 == TX Byte 1 ==
5905 22:10:34.429988 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5906 22:10:34.433542 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5907 22:10:34.433624 ==
5908 22:10:34.436996 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 22:10:34.440335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 22:10:34.443285 ==
5911 22:10:34.443380
5912 22:10:34.443445
5913 22:10:34.443506 TX Vref Scan disable
5914 22:10:34.446824 == TX Byte 0 ==
5915 22:10:34.450286 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5916 22:10:34.453818 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5917 22:10:34.457126 == TX Byte 1 ==
5918 22:10:34.460172 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5919 22:10:34.466960 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5920 22:10:34.467084
5921 22:10:34.467193 [DATLAT]
5922 22:10:34.467303 Freq=933, CH1 RK1
5923 22:10:34.467413
5924 22:10:34.470037 DATLAT Default: 0xb
5925 22:10:34.470159 0, 0xFFFF, sum = 0
5926 22:10:34.473646 1, 0xFFFF, sum = 0
5927 22:10:34.473768 2, 0xFFFF, sum = 0
5928 22:10:34.476783 3, 0xFFFF, sum = 0
5929 22:10:34.480260 4, 0xFFFF, sum = 0
5930 22:10:34.480390 5, 0xFFFF, sum = 0
5931 22:10:34.483520 6, 0xFFFF, sum = 0
5932 22:10:34.483644 7, 0xFFFF, sum = 0
5933 22:10:34.486840 8, 0xFFFF, sum = 0
5934 22:10:34.486964 9, 0xFFFF, sum = 0
5935 22:10:34.489942 10, 0x0, sum = 1
5936 22:10:34.490066 11, 0x0, sum = 2
5937 22:10:34.493229 12, 0x0, sum = 3
5938 22:10:34.493351 13, 0x0, sum = 4
5939 22:10:34.493468 best_step = 11
5940 22:10:34.493577
5941 22:10:34.496700 ==
5942 22:10:34.496828 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 22:10:34.503530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 22:10:34.503652 ==
5945 22:10:34.503768 RX Vref Scan: 0
5946 22:10:34.503876
5947 22:10:34.506598 RX Vref 0 -> 0, step: 1
5948 22:10:34.506719
5949 22:10:34.510264 RX Delay -53 -> 252, step: 4
5950 22:10:34.513656 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5951 22:10:34.520089 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5952 22:10:34.523748 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5953 22:10:34.526717 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5954 22:10:34.530001 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5955 22:10:34.533528 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5956 22:10:34.540224 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5957 22:10:34.543414 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5958 22:10:34.546579 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5959 22:10:34.550113 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5960 22:10:34.553388 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5961 22:10:34.556735 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5962 22:10:34.563346 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5963 22:10:34.567114 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5964 22:10:34.570023 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5965 22:10:34.573402 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5966 22:10:34.573486 ==
5967 22:10:34.576946 Dram Type= 6, Freq= 0, CH_1, rank 1
5968 22:10:34.580096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5969 22:10:34.584210 ==
5970 22:10:34.584291 DQS Delay:
5971 22:10:34.584354 DQS0 = 0, DQS1 = 0
5972 22:10:34.587062 DQM Delay:
5973 22:10:34.587143 DQM0 = 105, DQM1 = 97
5974 22:10:34.590231 DQ Delay:
5975 22:10:34.593438 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =104
5976 22:10:34.596612 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5977 22:10:34.600414 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =92
5978 22:10:34.603471 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =106
5979 22:10:34.603553
5980 22:10:34.603618
5981 22:10:34.610027 [DQSOSCAuto] RK1, (LSB)MR18= 0x2300, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5982 22:10:34.613429 CH1 RK1: MR19=505, MR18=2300
5983 22:10:34.620196 CH1_RK1: MR19=0x505, MR18=0x2300, DQSOSC=410, MR23=63, INC=64, DEC=42
5984 22:10:34.623347 [RxdqsGatingPostProcess] freq 933
5985 22:10:34.630065 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5986 22:10:34.630146 best DQS0 dly(2T, 0.5T) = (0, 10)
5987 22:10:34.633542 best DQS1 dly(2T, 0.5T) = (0, 10)
5988 22:10:34.636611 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5989 22:10:34.639938 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5990 22:10:34.643591 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 22:10:34.646799 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 22:10:34.649915 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 22:10:34.653150 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 22:10:34.656362 Pre-setting of DQS Precalculation
5995 22:10:34.663080 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5996 22:10:34.669905 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5997 22:10:34.676276 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5998 22:10:34.676354
5999 22:10:34.676417
6000 22:10:34.680031 [Calibration Summary] 1866 Mbps
6001 22:10:34.680104 CH 0, Rank 0
6002 22:10:34.683076 SW Impedance : PASS
6003 22:10:34.686665 DUTY Scan : NO K
6004 22:10:34.686738 ZQ Calibration : PASS
6005 22:10:34.689456 Jitter Meter : NO K
6006 22:10:34.693267 CBT Training : PASS
6007 22:10:34.693339 Write leveling : PASS
6008 22:10:34.696777 RX DQS gating : PASS
6009 22:10:34.696862 RX DQ/DQS(RDDQC) : PASS
6010 22:10:34.699763 TX DQ/DQS : PASS
6011 22:10:34.703154 RX DATLAT : PASS
6012 22:10:34.703226 RX DQ/DQS(Engine): PASS
6013 22:10:34.706106 TX OE : NO K
6014 22:10:34.706177 All Pass.
6015 22:10:34.706252
6016 22:10:34.709454 CH 0, Rank 1
6017 22:10:34.709549 SW Impedance : PASS
6018 22:10:34.713142 DUTY Scan : NO K
6019 22:10:34.716170 ZQ Calibration : PASS
6020 22:10:34.716242 Jitter Meter : NO K
6021 22:10:34.719638 CBT Training : PASS
6022 22:10:34.722927 Write leveling : PASS
6023 22:10:34.723023 RX DQS gating : PASS
6024 22:10:34.726264 RX DQ/DQS(RDDQC) : PASS
6025 22:10:34.729660 TX DQ/DQS : PASS
6026 22:10:34.729732 RX DATLAT : PASS
6027 22:10:34.732989 RX DQ/DQS(Engine): PASS
6028 22:10:34.733061 TX OE : NO K
6029 22:10:34.736100 All Pass.
6030 22:10:34.736185
6031 22:10:34.736259 CH 1, Rank 0
6032 22:10:34.739573 SW Impedance : PASS
6033 22:10:34.739660 DUTY Scan : NO K
6034 22:10:34.742866 ZQ Calibration : PASS
6035 22:10:34.746053 Jitter Meter : NO K
6036 22:10:34.746140 CBT Training : PASS
6037 22:10:34.749855 Write leveling : PASS
6038 22:10:34.752724 RX DQS gating : PASS
6039 22:10:34.752814 RX DQ/DQS(RDDQC) : PASS
6040 22:10:34.756064 TX DQ/DQS : PASS
6041 22:10:34.759245 RX DATLAT : PASS
6042 22:10:34.759356 RX DQ/DQS(Engine): PASS
6043 22:10:34.762817 TX OE : NO K
6044 22:10:34.762898 All Pass.
6045 22:10:34.762962
6046 22:10:34.766186 CH 1, Rank 1
6047 22:10:34.766270 SW Impedance : PASS
6048 22:10:34.769593 DUTY Scan : NO K
6049 22:10:34.772875 ZQ Calibration : PASS
6050 22:10:34.772959 Jitter Meter : NO K
6051 22:10:34.776156 CBT Training : PASS
6052 22:10:34.779852 Write leveling : PASS
6053 22:10:34.779935 RX DQS gating : PASS
6054 22:10:34.782906 RX DQ/DQS(RDDQC) : PASS
6055 22:10:34.782989 TX DQ/DQS : PASS
6056 22:10:34.786182 RX DATLAT : PASS
6057 22:10:34.789732 RX DQ/DQS(Engine): PASS
6058 22:10:34.789816 TX OE : NO K
6059 22:10:34.793094 All Pass.
6060 22:10:34.793178
6061 22:10:34.793261 DramC Write-DBI off
6062 22:10:34.796276 PER_BANK_REFRESH: Hybrid Mode
6063 22:10:34.799430 TX_TRACKING: ON
6064 22:10:34.806168 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6065 22:10:34.809129 [FAST_K] Save calibration result to emmc
6066 22:10:34.816017 dramc_set_vcore_voltage set vcore to 650000
6067 22:10:34.816140 Read voltage for 400, 6
6068 22:10:34.816249 Vio18 = 0
6069 22:10:34.819334 Vcore = 650000
6070 22:10:34.819458 Vdram = 0
6071 22:10:34.819565 Vddq = 0
6072 22:10:34.822815 Vmddr = 0
6073 22:10:34.825789 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6074 22:10:34.832388 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6075 22:10:34.835744 MEM_TYPE=3, freq_sel=20
6076 22:10:34.835865 sv_algorithm_assistance_LP4_800
6077 22:10:34.842171 ============ PULL DRAM RESETB DOWN ============
6078 22:10:34.845736 ========== PULL DRAM RESETB DOWN end =========
6079 22:10:34.849274 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6080 22:10:34.852381 ===================================
6081 22:10:34.855614 LPDDR4 DRAM CONFIGURATION
6082 22:10:34.858804 ===================================
6083 22:10:34.862039 EX_ROW_EN[0] = 0x0
6084 22:10:34.862159 EX_ROW_EN[1] = 0x0
6085 22:10:34.865356 LP4Y_EN = 0x0
6086 22:10:34.865492 WORK_FSP = 0x0
6087 22:10:34.868641 WL = 0x2
6088 22:10:34.868781 RL = 0x2
6089 22:10:34.871966 BL = 0x2
6090 22:10:34.872097 RPST = 0x0
6091 22:10:34.875240 RD_PRE = 0x0
6092 22:10:34.875360 WR_PRE = 0x1
6093 22:10:34.878588 WR_PST = 0x0
6094 22:10:34.878707 DBI_WR = 0x0
6095 22:10:34.882007 DBI_RD = 0x0
6096 22:10:34.882123 OTF = 0x1
6097 22:10:34.885228 ===================================
6098 22:10:34.888831 ===================================
6099 22:10:34.891940 ANA top config
6100 22:10:34.895277 ===================================
6101 22:10:34.898601 DLL_ASYNC_EN = 0
6102 22:10:34.898724 ALL_SLAVE_EN = 1
6103 22:10:34.902105 NEW_RANK_MODE = 1
6104 22:10:34.905281 DLL_IDLE_MODE = 1
6105 22:10:34.908376 LP45_APHY_COMB_EN = 1
6106 22:10:34.911760 TX_ODT_DIS = 1
6107 22:10:34.911880 NEW_8X_MODE = 1
6108 22:10:34.914885 ===================================
6109 22:10:34.918508 ===================================
6110 22:10:34.921688 data_rate = 800
6111 22:10:34.924980 CKR = 1
6112 22:10:34.928595 DQ_P2S_RATIO = 4
6113 22:10:34.931895 ===================================
6114 22:10:34.935053 CA_P2S_RATIO = 4
6115 22:10:34.935174 DQ_CA_OPEN = 0
6116 22:10:34.938627 DQ_SEMI_OPEN = 1
6117 22:10:34.941718 CA_SEMI_OPEN = 1
6118 22:10:34.945453 CA_FULL_RATE = 0
6119 22:10:34.948472 DQ_CKDIV4_EN = 0
6120 22:10:34.951732 CA_CKDIV4_EN = 1
6121 22:10:34.951855 CA_PREDIV_EN = 0
6122 22:10:34.955136 PH8_DLY = 0
6123 22:10:34.958805 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6124 22:10:34.962013 DQ_AAMCK_DIV = 0
6125 22:10:34.965374 CA_AAMCK_DIV = 0
6126 22:10:34.968565 CA_ADMCK_DIV = 4
6127 22:10:34.968647 DQ_TRACK_CA_EN = 0
6128 22:10:34.972159 CA_PICK = 800
6129 22:10:34.975253 CA_MCKIO = 400
6130 22:10:34.978396 MCKIO_SEMI = 400
6131 22:10:34.981800 PLL_FREQ = 3016
6132 22:10:34.985059 DQ_UI_PI_RATIO = 32
6133 22:10:34.988326 CA_UI_PI_RATIO = 32
6134 22:10:34.992174 ===================================
6135 22:10:34.995465 ===================================
6136 22:10:34.995576 memory_type:LPDDR4
6137 22:10:34.998505 GP_NUM : 10
6138 22:10:35.002039 SRAM_EN : 1
6139 22:10:35.002138 MD32_EN : 0
6140 22:10:35.004967 ===================================
6141 22:10:35.008249 [ANA_INIT] >>>>>>>>>>>>>>
6142 22:10:35.011829 <<<<<< [CONFIGURE PHASE]: ANA_TX
6143 22:10:35.015322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6144 22:10:35.018443 ===================================
6145 22:10:35.021907 data_rate = 800,PCW = 0X7400
6146 22:10:35.025259 ===================================
6147 22:10:35.028859 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6148 22:10:35.031833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6149 22:10:35.044999 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 22:10:35.048691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6151 22:10:35.051571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6152 22:10:35.055130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6153 22:10:35.058248 [ANA_INIT] flow start
6154 22:10:35.058339 [ANA_INIT] PLL >>>>>>>>
6155 22:10:35.061776 [ANA_INIT] PLL <<<<<<<<
6156 22:10:35.064723 [ANA_INIT] MIDPI >>>>>>>>
6157 22:10:35.068343 [ANA_INIT] MIDPI <<<<<<<<
6158 22:10:35.068443 [ANA_INIT] DLL >>>>>>>>
6159 22:10:35.071305 [ANA_INIT] flow end
6160 22:10:35.074850 ============ LP4 DIFF to SE enter ============
6161 22:10:35.078274 ============ LP4 DIFF to SE exit ============
6162 22:10:35.081294 [ANA_INIT] <<<<<<<<<<<<<
6163 22:10:35.084829 [Flow] Enable top DCM control >>>>>
6164 22:10:35.088095 [Flow] Enable top DCM control <<<<<
6165 22:10:35.091522 Enable DLL master slave shuffle
6166 22:10:35.098121 ==============================================================
6167 22:10:35.098220 Gating Mode config
6168 22:10:35.104560 ==============================================================
6169 22:10:35.104645 Config description:
6170 22:10:35.114549 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6171 22:10:35.121316 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6172 22:10:35.128042 SELPH_MODE 0: By rank 1: By Phase
6173 22:10:35.131083 ==============================================================
6174 22:10:35.134631 GAT_TRACK_EN = 0
6175 22:10:35.138075 RX_GATING_MODE = 2
6176 22:10:35.141345 RX_GATING_TRACK_MODE = 2
6177 22:10:35.144637 SELPH_MODE = 1
6178 22:10:35.148318 PICG_EARLY_EN = 1
6179 22:10:35.151529 VALID_LAT_VALUE = 1
6180 22:10:35.154899 ==============================================================
6181 22:10:35.158419 Enter into Gating configuration >>>>
6182 22:10:35.161302 Exit from Gating configuration <<<<
6183 22:10:35.164857 Enter into DVFS_PRE_config >>>>>
6184 22:10:35.178186 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6185 22:10:35.181311 Exit from DVFS_PRE_config <<<<<
6186 22:10:35.184670 Enter into PICG configuration >>>>
6187 22:10:35.184814 Exit from PICG configuration <<<<
6188 22:10:35.188445 [RX_INPUT] configuration >>>>>
6189 22:10:35.191369 [RX_INPUT] configuration <<<<<
6190 22:10:35.198158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6191 22:10:35.201279 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6192 22:10:35.208182 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6193 22:10:35.214705 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6194 22:10:35.221324 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6195 22:10:35.228075 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6196 22:10:35.231165 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6197 22:10:35.234641 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6198 22:10:35.237951 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6199 22:10:35.244382 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6200 22:10:35.247855 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6201 22:10:35.251091 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6202 22:10:35.254331 ===================================
6203 22:10:35.258343 LPDDR4 DRAM CONFIGURATION
6204 22:10:35.261227 ===================================
6205 22:10:35.264218 EX_ROW_EN[0] = 0x0
6206 22:10:35.264299 EX_ROW_EN[1] = 0x0
6207 22:10:35.267814 LP4Y_EN = 0x0
6208 22:10:35.267974 WORK_FSP = 0x0
6209 22:10:35.271490 WL = 0x2
6210 22:10:35.271611 RL = 0x2
6211 22:10:35.274139 BL = 0x2
6212 22:10:35.274242 RPST = 0x0
6213 22:10:35.278017 RD_PRE = 0x0
6214 22:10:35.278113 WR_PRE = 0x1
6215 22:10:35.281097 WR_PST = 0x0
6216 22:10:35.281179 DBI_WR = 0x0
6217 22:10:35.284307 DBI_RD = 0x0
6218 22:10:35.284388 OTF = 0x1
6219 22:10:35.287551 ===================================
6220 22:10:35.294442 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6221 22:10:35.297470 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6222 22:10:35.300740 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 22:10:35.304442 ===================================
6224 22:10:35.307268 LPDDR4 DRAM CONFIGURATION
6225 22:10:35.310547 ===================================
6226 22:10:35.314042 EX_ROW_EN[0] = 0x10
6227 22:10:35.314139 EX_ROW_EN[1] = 0x0
6228 22:10:35.317489 LP4Y_EN = 0x0
6229 22:10:35.317571 WORK_FSP = 0x0
6230 22:10:35.320908 WL = 0x2
6231 22:10:35.320989 RL = 0x2
6232 22:10:35.324375 BL = 0x2
6233 22:10:35.324471 RPST = 0x0
6234 22:10:35.327709 RD_PRE = 0x0
6235 22:10:35.327805 WR_PRE = 0x1
6236 22:10:35.330778 WR_PST = 0x0
6237 22:10:35.330861 DBI_WR = 0x0
6238 22:10:35.334319 DBI_RD = 0x0
6239 22:10:35.334389 OTF = 0x1
6240 22:10:35.337923 ===================================
6241 22:10:35.344471 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6242 22:10:35.348646 nWR fixed to 30
6243 22:10:35.351639 [ModeRegInit_LP4] CH0 RK0
6244 22:10:35.351721 [ModeRegInit_LP4] CH0 RK1
6245 22:10:35.355103 [ModeRegInit_LP4] CH1 RK0
6246 22:10:35.358534 [ModeRegInit_LP4] CH1 RK1
6247 22:10:35.358616 match AC timing 19
6248 22:10:35.365119 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6249 22:10:35.369119 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6250 22:10:35.371892 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6251 22:10:35.378423 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6252 22:10:35.381819 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6253 22:10:35.381901 ==
6254 22:10:35.385227 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 22:10:35.388352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 22:10:35.388435 ==
6257 22:10:35.395179 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6258 22:10:35.401677 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6259 22:10:35.405108 [CA 0] Center 36 (8~64) winsize 57
6260 22:10:35.408145 [CA 1] Center 36 (8~64) winsize 57
6261 22:10:35.411646 [CA 2] Center 36 (8~64) winsize 57
6262 22:10:35.411730 [CA 3] Center 36 (8~64) winsize 57
6263 22:10:35.415003 [CA 4] Center 36 (8~64) winsize 57
6264 22:10:35.418309 [CA 5] Center 36 (8~64) winsize 57
6265 22:10:35.418395
6266 22:10:35.421682 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6267 22:10:35.421764
6268 22:10:35.428500 [CATrainingPosCal] consider 1 rank data
6269 22:10:35.428583 u2DelayCellTimex100 = 270/100 ps
6270 22:10:35.435029 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 22:10:35.438605 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 22:10:35.441855 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 22:10:35.444920 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 22:10:35.448563 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 22:10:35.451534 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 22:10:35.451616
6277 22:10:35.454961 CA PerBit enable=1, Macro0, CA PI delay=36
6278 22:10:35.455044
6279 22:10:35.458291 [CBTSetCACLKResult] CA Dly = 36
6280 22:10:35.461900 CS Dly: 1 (0~32)
6281 22:10:35.461983 ==
6282 22:10:35.465028 Dram Type= 6, Freq= 0, CH_0, rank 1
6283 22:10:35.468725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 22:10:35.468843 ==
6285 22:10:35.475405 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6286 22:10:35.478281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6287 22:10:35.481559 [CA 0] Center 36 (8~64) winsize 57
6288 22:10:35.484871 [CA 1] Center 36 (8~64) winsize 57
6289 22:10:35.487936 [CA 2] Center 36 (8~64) winsize 57
6290 22:10:35.491407 [CA 3] Center 36 (8~64) winsize 57
6291 22:10:35.494687 [CA 4] Center 36 (8~64) winsize 57
6292 22:10:35.498419 [CA 5] Center 36 (8~64) winsize 57
6293 22:10:35.498500
6294 22:10:35.501356 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6295 22:10:35.501438
6296 22:10:35.504715 [CATrainingPosCal] consider 2 rank data
6297 22:10:35.508142 u2DelayCellTimex100 = 270/100 ps
6298 22:10:35.511678 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 22:10:35.514898 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 22:10:35.517926 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 22:10:35.521343 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 22:10:35.528114 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 22:10:35.531289 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 22:10:35.531371
6305 22:10:35.534710 CA PerBit enable=1, Macro0, CA PI delay=36
6306 22:10:35.534792
6307 22:10:35.537883 [CBTSetCACLKResult] CA Dly = 36
6308 22:10:35.537965 CS Dly: 1 (0~32)
6309 22:10:35.538030
6310 22:10:35.541370 ----->DramcWriteLeveling(PI) begin...
6311 22:10:35.541454 ==
6312 22:10:35.544547 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 22:10:35.551193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 22:10:35.551276 ==
6315 22:10:35.554659 Write leveling (Byte 0): 40 => 8
6316 22:10:35.558069 Write leveling (Byte 1): 32 => 0
6317 22:10:35.558154 DramcWriteLeveling(PI) end<-----
6318 22:10:35.558220
6319 22:10:35.561261 ==
6320 22:10:35.564561 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 22:10:35.567879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 22:10:35.567961 ==
6323 22:10:35.571053 [Gating] SW mode calibration
6324 22:10:35.577828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6325 22:10:35.581055 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6326 22:10:35.587617 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6327 22:10:35.590983 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 22:10:35.594040 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 22:10:35.600867 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 22:10:35.604653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 22:10:35.607340 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 22:10:35.614245 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 22:10:35.617467 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 22:10:35.620540 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 22:10:35.623923 Total UI for P1: 0, mck2ui 16
6336 22:10:35.627206 best dqsien dly found for B0: ( 0, 14, 24)
6337 22:10:35.630872 Total UI for P1: 0, mck2ui 16
6338 22:10:35.633878 best dqsien dly found for B1: ( 0, 14, 24)
6339 22:10:35.637364 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6340 22:10:35.640544 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6341 22:10:35.640666
6342 22:10:35.647132 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6343 22:10:35.650567 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 22:10:35.654112 [Gating] SW calibration Done
6345 22:10:35.654231 ==
6346 22:10:35.657291 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 22:10:35.660441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 22:10:35.660560 ==
6349 22:10:35.660668 RX Vref Scan: 0
6350 22:10:35.660801
6351 22:10:35.663994 RX Vref 0 -> 0, step: 1
6352 22:10:35.664111
6353 22:10:35.667449 RX Delay -410 -> 252, step: 16
6354 22:10:35.670487 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6355 22:10:35.677045 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6356 22:10:35.680301 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6357 22:10:35.683581 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6358 22:10:35.687209 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6359 22:10:35.693936 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6360 22:10:35.697225 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6361 22:10:35.700539 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6362 22:10:35.703912 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6363 22:10:35.706915 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6364 22:10:35.713823 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6365 22:10:35.716929 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6366 22:10:35.720485 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6367 22:10:35.724011 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6368 22:10:35.730575 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6369 22:10:35.733822 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6370 22:10:35.733904 ==
6371 22:10:35.737236 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 22:10:35.740673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 22:10:35.740760 ==
6374 22:10:35.743962 DQS Delay:
6375 22:10:35.744041 DQS0 = 27, DQS1 = 43
6376 22:10:35.747000 DQM Delay:
6377 22:10:35.747079 DQM0 = 12, DQM1 = 13
6378 22:10:35.747142 DQ Delay:
6379 22:10:35.750354 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6380 22:10:35.753760 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6381 22:10:35.757249 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6382 22:10:35.760329 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6383 22:10:35.760409
6384 22:10:35.760471
6385 22:10:35.760529 ==
6386 22:10:35.764049 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 22:10:35.770244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 22:10:35.770325 ==
6389 22:10:35.770388
6390 22:10:35.770446
6391 22:10:35.770502 TX Vref Scan disable
6392 22:10:35.773901 == TX Byte 0 ==
6393 22:10:35.776771 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6394 22:10:35.780480 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6395 22:10:35.783612 == TX Byte 1 ==
6396 22:10:35.787119 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6397 22:10:35.790634 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6398 22:10:35.793453 ==
6399 22:10:35.796791 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 22:10:35.800487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 22:10:35.800567 ==
6402 22:10:35.800631
6403 22:10:35.800689
6404 22:10:35.803322 TX Vref Scan disable
6405 22:10:35.803401 == TX Byte 0 ==
6406 22:10:35.806660 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 22:10:35.813369 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 22:10:35.813449 == TX Byte 1 ==
6409 22:10:35.816759 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6410 22:10:35.823109 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6411 22:10:35.823189
6412 22:10:35.823252 [DATLAT]
6413 22:10:35.823310 Freq=400, CH0 RK0
6414 22:10:35.823367
6415 22:10:35.826368 DATLAT Default: 0xf
6416 22:10:35.829602 0, 0xFFFF, sum = 0
6417 22:10:35.829684 1, 0xFFFF, sum = 0
6418 22:10:35.833468 2, 0xFFFF, sum = 0
6419 22:10:35.833549 3, 0xFFFF, sum = 0
6420 22:10:35.836195 4, 0xFFFF, sum = 0
6421 22:10:35.836306 5, 0xFFFF, sum = 0
6422 22:10:35.839849 6, 0xFFFF, sum = 0
6423 22:10:35.839929 7, 0xFFFF, sum = 0
6424 22:10:35.843340 8, 0xFFFF, sum = 0
6425 22:10:35.843435 9, 0xFFFF, sum = 0
6426 22:10:35.847011 10, 0xFFFF, sum = 0
6427 22:10:35.847091 11, 0xFFFF, sum = 0
6428 22:10:35.849521 12, 0xFFFF, sum = 0
6429 22:10:35.849607 13, 0x0, sum = 1
6430 22:10:35.852942 14, 0x0, sum = 2
6431 22:10:35.853023 15, 0x0, sum = 3
6432 22:10:35.856084 16, 0x0, sum = 4
6433 22:10:35.856164 best_step = 14
6434 22:10:35.856232
6435 22:10:35.856290 ==
6436 22:10:35.859565 Dram Type= 6, Freq= 0, CH_0, rank 0
6437 22:10:35.866287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 22:10:35.866369 ==
6439 22:10:35.866433 RX Vref Scan: 1
6440 22:10:35.866494
6441 22:10:35.869558 RX Vref 0 -> 0, step: 1
6442 22:10:35.869638
6443 22:10:35.872791 RX Delay -327 -> 252, step: 8
6444 22:10:35.872887
6445 22:10:35.876337 Set Vref, RX VrefLevel [Byte0]: 61
6446 22:10:35.879382 [Byte1]: 51
6447 22:10:35.879463
6448 22:10:35.882849 Final RX Vref Byte 0 = 61 to rank0
6449 22:10:35.886072 Final RX Vref Byte 1 = 51 to rank0
6450 22:10:35.889080 Final RX Vref Byte 0 = 61 to rank1
6451 22:10:35.892461 Final RX Vref Byte 1 = 51 to rank1==
6452 22:10:35.895659 Dram Type= 6, Freq= 0, CH_0, rank 0
6453 22:10:35.899144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 22:10:35.902627 ==
6455 22:10:35.902710 DQS Delay:
6456 22:10:35.902775 DQS0 = 28, DQS1 = 48
6457 22:10:35.905662 DQM Delay:
6458 22:10:35.905744 DQM0 = 12, DQM1 = 15
6459 22:10:35.909190 DQ Delay:
6460 22:10:35.909273 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6461 22:10:35.912685 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6462 22:10:35.915786 DQ8 =12, DQ9 =0, DQ10 =12, DQ11 =8
6463 22:10:35.919188 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6464 22:10:35.919270
6465 22:10:35.919335
6466 22:10:35.929006 [DQSOSCAuto] RK0, (LSB)MR18= 0xaea5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6467 22:10:35.932078 CH0 RK0: MR19=C0C, MR18=AEA5
6468 22:10:35.938984 CH0_RK0: MR19=0xC0C, MR18=0xAEA5, DQSOSC=388, MR23=63, INC=392, DEC=261
6469 22:10:35.939083 ==
6470 22:10:35.941961 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 22:10:35.945433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 22:10:35.945522 ==
6473 22:10:35.949419 [Gating] SW mode calibration
6474 22:10:35.955573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6475 22:10:35.962094 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6476 22:10:35.965249 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6477 22:10:35.968449 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 22:10:35.971880 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 22:10:35.978481 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 22:10:35.981996 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 22:10:35.985656 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 22:10:35.991814 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 22:10:35.995199 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 22:10:35.998337 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 22:10:36.002025 Total UI for P1: 0, mck2ui 16
6486 22:10:36.005079 best dqsien dly found for B0: ( 0, 14, 24)
6487 22:10:36.008672 Total UI for P1: 0, mck2ui 16
6488 22:10:36.011716 best dqsien dly found for B1: ( 0, 14, 24)
6489 22:10:36.015198 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6490 22:10:36.018369 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6491 22:10:36.021905
6492 22:10:36.025191 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6493 22:10:36.028630 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 22:10:36.031788 [Gating] SW calibration Done
6495 22:10:36.031870 ==
6496 22:10:36.035093 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 22:10:36.038463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 22:10:36.038587 ==
6499 22:10:36.038694 RX Vref Scan: 0
6500 22:10:36.038804
6501 22:10:36.042219 RX Vref 0 -> 0, step: 1
6502 22:10:36.042340
6503 22:10:36.045010 RX Delay -410 -> 252, step: 16
6504 22:10:36.048517 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6505 22:10:36.055387 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6506 22:10:36.058591 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6507 22:10:36.061783 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6508 22:10:36.065559 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6509 22:10:36.071826 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6510 22:10:36.075029 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6511 22:10:36.078577 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6512 22:10:36.081788 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6513 22:10:36.088371 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6514 22:10:36.091819 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6515 22:10:36.095127 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6516 22:10:36.099149 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6517 22:10:36.105405 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6518 22:10:36.108452 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6519 22:10:36.111850 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6520 22:10:36.111962 ==
6521 22:10:36.115291 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 22:10:36.118320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 22:10:36.121839 ==
6524 22:10:36.121921 DQS Delay:
6525 22:10:36.121986 DQS0 = 27, DQS1 = 43
6526 22:10:36.125059 DQM Delay:
6527 22:10:36.125141 DQM0 = 9, DQM1 = 14
6528 22:10:36.128262 DQ Delay:
6529 22:10:36.128344 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6530 22:10:36.131969 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6531 22:10:36.135244 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6532 22:10:36.138257 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6533 22:10:36.138366
6534 22:10:36.138460
6535 22:10:36.138550 ==
6536 22:10:36.141506 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 22:10:36.148381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 22:10:36.148465 ==
6539 22:10:36.148530
6540 22:10:36.148590
6541 22:10:36.148647 TX Vref Scan disable
6542 22:10:36.151774 == TX Byte 0 ==
6543 22:10:36.154906 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6544 22:10:36.158384 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6545 22:10:36.161681 == TX Byte 1 ==
6546 22:10:36.165147 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6547 22:10:36.168221 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6548 22:10:36.168302 ==
6549 22:10:36.172043 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 22:10:36.178122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 22:10:36.178205 ==
6552 22:10:36.178269
6553 22:10:36.178329
6554 22:10:36.178387 TX Vref Scan disable
6555 22:10:36.181478 == TX Byte 0 ==
6556 22:10:36.184844 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6557 22:10:36.188287 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6558 22:10:36.191465 == TX Byte 1 ==
6559 22:10:36.195057 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6560 22:10:36.198274 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6561 22:10:36.198356
6562 22:10:36.201570 [DATLAT]
6563 22:10:36.201652 Freq=400, CH0 RK1
6564 22:10:36.201717
6565 22:10:36.205076 DATLAT Default: 0xe
6566 22:10:36.205157 0, 0xFFFF, sum = 0
6567 22:10:36.208555 1, 0xFFFF, sum = 0
6568 22:10:36.208639 2, 0xFFFF, sum = 0
6569 22:10:36.211663 3, 0xFFFF, sum = 0
6570 22:10:36.211747 4, 0xFFFF, sum = 0
6571 22:10:36.215203 5, 0xFFFF, sum = 0
6572 22:10:36.215287 6, 0xFFFF, sum = 0
6573 22:10:36.218174 7, 0xFFFF, sum = 0
6574 22:10:36.218257 8, 0xFFFF, sum = 0
6575 22:10:36.221894 9, 0xFFFF, sum = 0
6576 22:10:36.221978 10, 0xFFFF, sum = 0
6577 22:10:36.224710 11, 0xFFFF, sum = 0
6578 22:10:36.228446 12, 0xFFFF, sum = 0
6579 22:10:36.228530 13, 0x0, sum = 1
6580 22:10:36.228597 14, 0x0, sum = 2
6581 22:10:36.231448 15, 0x0, sum = 3
6582 22:10:36.231532 16, 0x0, sum = 4
6583 22:10:36.235047 best_step = 14
6584 22:10:36.235129
6585 22:10:36.235195 ==
6586 22:10:36.238065 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 22:10:36.241416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 22:10:36.241521 ==
6589 22:10:36.244656 RX Vref Scan: 0
6590 22:10:36.244739
6591 22:10:36.244840 RX Vref 0 -> 0, step: 1
6592 22:10:36.244902
6593 22:10:36.248107 RX Delay -327 -> 252, step: 8
6594 22:10:36.256359 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6595 22:10:36.259847 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6596 22:10:36.263008 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6597 22:10:36.266607 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6598 22:10:36.273163 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6599 22:10:36.276529 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6600 22:10:36.280011 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6601 22:10:36.283050 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6602 22:10:36.290050 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6603 22:10:36.293323 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6604 22:10:36.296375 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6605 22:10:36.299975 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6606 22:10:36.306650 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6607 22:10:36.309714 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6608 22:10:36.313146 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6609 22:10:36.316283 iDelay=217, Bit 15, Center -20 (-247 ~ 208) 456
6610 22:10:36.319659 ==
6611 22:10:36.322846 Dram Type= 6, Freq= 0, CH_0, rank 1
6612 22:10:36.326061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 22:10:36.326145 ==
6614 22:10:36.326210 DQS Delay:
6615 22:10:36.329853 DQS0 = 28, DQS1 = 44
6616 22:10:36.329935 DQM Delay:
6617 22:10:36.332721 DQM0 = 10, DQM1 = 15
6618 22:10:36.332825 DQ Delay:
6619 22:10:36.336221 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6620 22:10:36.339496 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6621 22:10:36.342969 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6622 22:10:36.346112 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6623 22:10:36.346194
6624 22:10:36.346259
6625 22:10:36.352750 [DQSOSCAuto] RK1, (LSB)MR18= 0xb56b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6626 22:10:36.356122 CH0 RK1: MR19=C0C, MR18=B56B
6627 22:10:36.362718 CH0_RK1: MR19=0xC0C, MR18=0xB56B, DQSOSC=387, MR23=63, INC=394, DEC=262
6628 22:10:36.366050 [RxdqsGatingPostProcess] freq 400
6629 22:10:36.369483 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6630 22:10:36.372942 best DQS0 dly(2T, 0.5T) = (0, 10)
6631 22:10:36.376558 best DQS1 dly(2T, 0.5T) = (0, 10)
6632 22:10:36.379281 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6633 22:10:36.382620 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6634 22:10:36.385970 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 22:10:36.389275 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 22:10:36.392581 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 22:10:36.395921 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 22:10:36.399238 Pre-setting of DQS Precalculation
6639 22:10:36.402489 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6640 22:10:36.406138 ==
6641 22:10:36.409305 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 22:10:36.412902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 22:10:36.412984 ==
6644 22:10:36.415850 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6645 22:10:36.422812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6646 22:10:36.426041 [CA 0] Center 36 (8~64) winsize 57
6647 22:10:36.429384 [CA 1] Center 36 (8~64) winsize 57
6648 22:10:36.432692 [CA 2] Center 36 (8~64) winsize 57
6649 22:10:36.435973 [CA 3] Center 36 (8~64) winsize 57
6650 22:10:36.439319 [CA 4] Center 36 (8~64) winsize 57
6651 22:10:36.442711 [CA 5] Center 36 (8~64) winsize 57
6652 22:10:36.442795
6653 22:10:36.446265 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6654 22:10:36.446348
6655 22:10:36.449162 [CATrainingPosCal] consider 1 rank data
6656 22:10:36.452674 u2DelayCellTimex100 = 270/100 ps
6657 22:10:36.455867 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 22:10:36.459178 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 22:10:36.462416 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 22:10:36.466163 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 22:10:36.469563 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 22:10:36.475773 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 22:10:36.475855
6664 22:10:36.479078 CA PerBit enable=1, Macro0, CA PI delay=36
6665 22:10:36.479161
6666 22:10:36.482500 [CBTSetCACLKResult] CA Dly = 36
6667 22:10:36.482582 CS Dly: 1 (0~32)
6668 22:10:36.482649 ==
6669 22:10:36.485816 Dram Type= 6, Freq= 0, CH_1, rank 1
6670 22:10:36.489046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 22:10:36.492640 ==
6672 22:10:36.495845 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6673 22:10:36.502305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6674 22:10:36.505753 [CA 0] Center 36 (8~64) winsize 57
6675 22:10:36.509288 [CA 1] Center 36 (8~64) winsize 57
6676 22:10:36.512286 [CA 2] Center 36 (8~64) winsize 57
6677 22:10:36.515713 [CA 3] Center 36 (8~64) winsize 57
6678 22:10:36.519137 [CA 4] Center 36 (8~64) winsize 57
6679 22:10:36.522566 [CA 5] Center 36 (8~64) winsize 57
6680 22:10:36.522648
6681 22:10:36.526374 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6682 22:10:36.526457
6683 22:10:36.528935 [CATrainingPosCal] consider 2 rank data
6684 22:10:36.532311 u2DelayCellTimex100 = 270/100 ps
6685 22:10:36.535952 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 22:10:36.539163 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 22:10:36.542722 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 22:10:36.545805 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 22:10:36.549181 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 22:10:36.552323 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 22:10:36.552405
6692 22:10:36.555487 CA PerBit enable=1, Macro0, CA PI delay=36
6693 22:10:36.555569
6694 22:10:36.558833 [CBTSetCACLKResult] CA Dly = 36
6695 22:10:36.562308 CS Dly: 1 (0~32)
6696 22:10:36.562390
6697 22:10:36.565856 ----->DramcWriteLeveling(PI) begin...
6698 22:10:36.565953 ==
6699 22:10:36.568890 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 22:10:36.573315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 22:10:36.573398 ==
6702 22:10:36.575704 Write leveling (Byte 0): 40 => 8
6703 22:10:36.579504 Write leveling (Byte 1): 32 => 0
6704 22:10:36.582322 DramcWriteLeveling(PI) end<-----
6705 22:10:36.582404
6706 22:10:36.582468 ==
6707 22:10:36.585700 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 22:10:36.588920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 22:10:36.589002 ==
6710 22:10:36.592151 [Gating] SW mode calibration
6711 22:10:36.598779 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6712 22:10:36.605450 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6713 22:10:36.609318 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6714 22:10:36.612195 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 22:10:36.618569 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 22:10:36.622399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 22:10:36.625313 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 22:10:36.632039 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 22:10:36.635465 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 22:10:36.638698 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 22:10:36.645471 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 22:10:36.645554 Total UI for P1: 0, mck2ui 16
6723 22:10:36.652269 best dqsien dly found for B0: ( 0, 14, 24)
6724 22:10:36.652351 Total UI for P1: 0, mck2ui 16
6725 22:10:36.659023 best dqsien dly found for B1: ( 0, 14, 24)
6726 22:10:36.662264 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6727 22:10:36.665616 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6728 22:10:36.665699
6729 22:10:36.668862 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6730 22:10:36.672032 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 22:10:36.675463 [Gating] SW calibration Done
6732 22:10:36.675545 ==
6733 22:10:36.678703 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 22:10:36.682415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 22:10:36.682498 ==
6736 22:10:36.685443 RX Vref Scan: 0
6737 22:10:36.685525
6738 22:10:36.685590 RX Vref 0 -> 0, step: 1
6739 22:10:36.688754
6740 22:10:36.688851 RX Delay -410 -> 252, step: 16
6741 22:10:36.695410 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6742 22:10:36.698441 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6743 22:10:36.701868 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6744 22:10:36.705299 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6745 22:10:36.712119 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6746 22:10:36.715303 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6747 22:10:36.718575 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6748 22:10:36.721597 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6749 22:10:36.728217 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6750 22:10:36.731993 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6751 22:10:36.735141 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6752 22:10:36.738641 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6753 22:10:36.745324 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6754 22:10:36.748188 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6755 22:10:36.751883 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6756 22:10:36.758198 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6757 22:10:36.758280 ==
6758 22:10:36.761610 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 22:10:36.764960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 22:10:36.765044 ==
6761 22:10:36.765109 DQS Delay:
6762 22:10:36.768093 DQS0 = 27, DQS1 = 43
6763 22:10:36.768174 DQM Delay:
6764 22:10:36.771628 DQM0 = 8, DQM1 = 16
6765 22:10:36.771709 DQ Delay:
6766 22:10:36.775039 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6767 22:10:36.778307 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6768 22:10:36.781874 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6769 22:10:36.784890 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6770 22:10:36.784972
6771 22:10:36.785037
6772 22:10:36.785097 ==
6773 22:10:36.788536 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 22:10:36.791474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 22:10:36.791557 ==
6776 22:10:36.791623
6777 22:10:36.791683
6778 22:10:36.795193 TX Vref Scan disable
6779 22:10:36.795275 == TX Byte 0 ==
6780 22:10:36.801540 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 22:10:36.805091 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 22:10:36.805174 == TX Byte 1 ==
6783 22:10:36.811374 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6784 22:10:36.814842 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6785 22:10:36.814944 ==
6786 22:10:36.818306 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 22:10:36.821562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 22:10:36.821645 ==
6789 22:10:36.821711
6790 22:10:36.821771
6791 22:10:36.824698 TX Vref Scan disable
6792 22:10:36.824802 == TX Byte 0 ==
6793 22:10:36.831668 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 22:10:36.835408 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 22:10:36.835490 == TX Byte 1 ==
6796 22:10:36.841956 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6797 22:10:36.844873 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6798 22:10:36.844995
6799 22:10:36.845071 [DATLAT]
6800 22:10:36.848348 Freq=400, CH1 RK0
6801 22:10:36.848430
6802 22:10:36.848495 DATLAT Default: 0xf
6803 22:10:36.851701 0, 0xFFFF, sum = 0
6804 22:10:36.851785 1, 0xFFFF, sum = 0
6805 22:10:36.855427 2, 0xFFFF, sum = 0
6806 22:10:36.855511 3, 0xFFFF, sum = 0
6807 22:10:36.858600 4, 0xFFFF, sum = 0
6808 22:10:36.858684 5, 0xFFFF, sum = 0
6809 22:10:36.861657 6, 0xFFFF, sum = 0
6810 22:10:36.861741 7, 0xFFFF, sum = 0
6811 22:10:36.864716 8, 0xFFFF, sum = 0
6812 22:10:36.864826 9, 0xFFFF, sum = 0
6813 22:10:36.868314 10, 0xFFFF, sum = 0
6814 22:10:36.871521 11, 0xFFFF, sum = 0
6815 22:10:36.871605 12, 0xFFFF, sum = 0
6816 22:10:36.875017 13, 0x0, sum = 1
6817 22:10:36.875100 14, 0x0, sum = 2
6818 22:10:36.877915 15, 0x0, sum = 3
6819 22:10:36.877998 16, 0x0, sum = 4
6820 22:10:36.878066 best_step = 14
6821 22:10:36.878126
6822 22:10:36.881857 ==
6823 22:10:36.881938 Dram Type= 6, Freq= 0, CH_1, rank 0
6824 22:10:36.888095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 22:10:36.888178 ==
6826 22:10:36.888243 RX Vref Scan: 1
6827 22:10:36.888303
6828 22:10:36.891663 RX Vref 0 -> 0, step: 1
6829 22:10:36.891744
6830 22:10:36.894861 RX Delay -327 -> 252, step: 8
6831 22:10:36.894943
6832 22:10:36.898273 Set Vref, RX VrefLevel [Byte0]: 52
6833 22:10:36.901343 [Byte1]: 52
6834 22:10:36.905138
6835 22:10:36.905220 Final RX Vref Byte 0 = 52 to rank0
6836 22:10:36.908343 Final RX Vref Byte 1 = 52 to rank0
6837 22:10:36.911434 Final RX Vref Byte 0 = 52 to rank1
6838 22:10:36.914978 Final RX Vref Byte 1 = 52 to rank1==
6839 22:10:36.917936 Dram Type= 6, Freq= 0, CH_1, rank 0
6840 22:10:36.924892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 22:10:36.924974 ==
6842 22:10:36.925041 DQS Delay:
6843 22:10:36.928086 DQS0 = 28, DQS1 = 40
6844 22:10:36.928191 DQM Delay:
6845 22:10:36.928278 DQM0 = 7, DQM1 = 12
6846 22:10:36.931402 DQ Delay:
6847 22:10:36.934684 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6848 22:10:36.934767 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6849 22:10:36.938114 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6850 22:10:36.941353 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6851 22:10:36.941435
6852 22:10:36.941500
6853 22:10:36.951483 [DQSOSCAuto] RK0, (LSB)MR18= 0x99d4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6854 22:10:36.954538 CH1 RK0: MR19=C0C, MR18=99D4
6855 22:10:36.961150 CH1_RK0: MR19=0xC0C, MR18=0x99D4, DQSOSC=383, MR23=63, INC=402, DEC=268
6856 22:10:36.961232 ==
6857 22:10:36.964773 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 22:10:36.968085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 22:10:36.968167 ==
6860 22:10:36.971443 [Gating] SW mode calibration
6861 22:10:36.978321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6862 22:10:36.981158 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6863 22:10:36.988207 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6864 22:10:36.991596 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 22:10:36.994923 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 22:10:37.001127 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 22:10:37.004576 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 22:10:37.007852 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 22:10:37.014444 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 22:10:37.017571 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 22:10:37.021196 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 22:10:37.024407 Total UI for P1: 0, mck2ui 16
6873 22:10:37.027869 best dqsien dly found for B0: ( 0, 14, 24)
6874 22:10:37.030988 Total UI for P1: 0, mck2ui 16
6875 22:10:37.034390 best dqsien dly found for B1: ( 0, 14, 24)
6876 22:10:37.037964 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6877 22:10:37.041284 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6878 22:10:37.041367
6879 22:10:37.048020 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6880 22:10:37.051465 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 22:10:37.054535 [Gating] SW calibration Done
6882 22:10:37.054617 ==
6883 22:10:37.057804 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 22:10:37.061318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 22:10:37.061401 ==
6886 22:10:37.061466 RX Vref Scan: 0
6887 22:10:37.061526
6888 22:10:37.064411 RX Vref 0 -> 0, step: 1
6889 22:10:37.064493
6890 22:10:37.067793 RX Delay -410 -> 252, step: 16
6891 22:10:37.070933 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6892 22:10:37.078070 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6893 22:10:37.081211 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6894 22:10:37.084427 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6895 22:10:37.088541 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6896 22:10:37.090924 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6897 22:10:37.097698 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6898 22:10:37.101224 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6899 22:10:37.104502 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6900 22:10:37.107648 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6901 22:10:37.114507 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6902 22:10:37.117615 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6903 22:10:37.121020 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6904 22:10:37.127332 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6905 22:10:37.130698 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6906 22:10:37.134254 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6907 22:10:37.134336 ==
6908 22:10:37.137635 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 22:10:37.140773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 22:10:37.140887 ==
6911 22:10:37.144512 DQS Delay:
6912 22:10:37.144653 DQS0 = 35, DQS1 = 43
6913 22:10:37.147810 DQM Delay:
6914 22:10:37.147939 DQM0 = 18, DQM1 = 18
6915 22:10:37.148053 DQ Delay:
6916 22:10:37.151265 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6917 22:10:37.154436 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6918 22:10:37.157581 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6919 22:10:37.161339 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6920 22:10:37.161421
6921 22:10:37.161486
6922 22:10:37.164131 ==
6923 22:10:37.164213 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 22:10:37.170921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 22:10:37.171004 ==
6926 22:10:37.171070
6927 22:10:37.171130
6928 22:10:37.174452 TX Vref Scan disable
6929 22:10:37.174534 == TX Byte 0 ==
6930 22:10:37.177607 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6931 22:10:37.181069 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6932 22:10:37.184877 == TX Byte 1 ==
6933 22:10:37.187841 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6934 22:10:37.191033 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6935 22:10:37.191116 ==
6936 22:10:37.195023 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 22:10:37.201366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 22:10:37.201474 ==
6939 22:10:37.201568
6940 22:10:37.201656
6941 22:10:37.201743 TX Vref Scan disable
6942 22:10:37.204427 == TX Byte 0 ==
6943 22:10:37.207902 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6944 22:10:37.210730 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6945 22:10:37.214062 == TX Byte 1 ==
6946 22:10:37.217531 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6947 22:10:37.220694 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6948 22:10:37.220795
6949 22:10:37.224218 [DATLAT]
6950 22:10:37.224299 Freq=400, CH1 RK1
6951 22:10:37.224364
6952 22:10:37.227335 DATLAT Default: 0xe
6953 22:10:37.227416 0, 0xFFFF, sum = 0
6954 22:10:37.230766 1, 0xFFFF, sum = 0
6955 22:10:37.230851 2, 0xFFFF, sum = 0
6956 22:10:37.234236 3, 0xFFFF, sum = 0
6957 22:10:37.234319 4, 0xFFFF, sum = 0
6958 22:10:37.237323 5, 0xFFFF, sum = 0
6959 22:10:37.237421 6, 0xFFFF, sum = 0
6960 22:10:37.241027 7, 0xFFFF, sum = 0
6961 22:10:37.243642 8, 0xFFFF, sum = 0
6962 22:10:37.243769 9, 0xFFFF, sum = 0
6963 22:10:37.247605 10, 0xFFFF, sum = 0
6964 22:10:37.247739 11, 0xFFFF, sum = 0
6965 22:10:37.250459 12, 0xFFFF, sum = 0
6966 22:10:37.250658 13, 0x0, sum = 1
6967 22:10:37.253843 14, 0x0, sum = 2
6968 22:10:37.253970 15, 0x0, sum = 3
6969 22:10:37.257200 16, 0x0, sum = 4
6970 22:10:37.257310 best_step = 14
6971 22:10:37.257402
6972 22:10:37.257490 ==
6973 22:10:37.260623 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 22:10:37.263678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 22:10:37.263760 ==
6976 22:10:37.266941 RX Vref Scan: 0
6977 22:10:37.267023
6978 22:10:37.270328 RX Vref 0 -> 0, step: 1
6979 22:10:37.270409
6980 22:10:37.270474 RX Delay -327 -> 252, step: 8
6981 22:10:37.279021 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6982 22:10:37.282354 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6983 22:10:37.285666 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6984 22:10:37.289125 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6985 22:10:37.295843 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6986 22:10:37.299466 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6987 22:10:37.302561 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6988 22:10:37.305883 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6989 22:10:37.312729 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6990 22:10:37.315729 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6991 22:10:37.319625 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6992 22:10:37.322495 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6993 22:10:37.329055 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6994 22:10:37.332640 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6995 22:10:37.335831 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6996 22:10:37.342512 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6997 22:10:37.342629 ==
6998 22:10:37.345618 Dram Type= 6, Freq= 0, CH_1, rank 1
6999 22:10:37.349155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7000 22:10:37.349237 ==
7001 22:10:37.349303 DQS Delay:
7002 22:10:37.352693 DQS0 = 28, DQS1 = 36
7003 22:10:37.352826 DQM Delay:
7004 22:10:37.356165 DQM0 = 8, DQM1 = 11
7005 22:10:37.356253 DQ Delay:
7006 22:10:37.359098 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
7007 22:10:37.362353 DQ4 =12, DQ5 =16, DQ6 =12, DQ7 =4
7008 22:10:37.365677 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7009 22:10:37.369223 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7010 22:10:37.369305
7011 22:10:37.369370
7012 22:10:37.375963 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf57, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
7013 22:10:37.379266 CH1 RK1: MR19=C0C, MR18=AF57
7014 22:10:37.385868 CH1_RK1: MR19=0xC0C, MR18=0xAF57, DQSOSC=388, MR23=63, INC=392, DEC=261
7015 22:10:37.389228 [RxdqsGatingPostProcess] freq 400
7016 22:10:37.392396 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7017 22:10:37.395936 best DQS0 dly(2T, 0.5T) = (0, 10)
7018 22:10:37.399079 best DQS1 dly(2T, 0.5T) = (0, 10)
7019 22:10:37.402812 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7020 22:10:37.405996 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7021 22:10:37.409092 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 22:10:37.412235 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 22:10:37.415711 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 22:10:37.418950 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 22:10:37.422751 Pre-setting of DQS Precalculation
7026 22:10:37.425820 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7027 22:10:37.435733 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7028 22:10:37.442143 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7029 22:10:37.442250
7030 22:10:37.442343
7031 22:10:37.445395 [Calibration Summary] 800 Mbps
7032 22:10:37.445477 CH 0, Rank 0
7033 22:10:37.448882 SW Impedance : PASS
7034 22:10:37.449000 DUTY Scan : NO K
7035 22:10:37.451916 ZQ Calibration : PASS
7036 22:10:37.455589 Jitter Meter : NO K
7037 22:10:37.455673 CBT Training : PASS
7038 22:10:37.458737 Write leveling : PASS
7039 22:10:37.462028 RX DQS gating : PASS
7040 22:10:37.462111 RX DQ/DQS(RDDQC) : PASS
7041 22:10:37.465224 TX DQ/DQS : PASS
7042 22:10:37.468633 RX DATLAT : PASS
7043 22:10:37.468744 RX DQ/DQS(Engine): PASS
7044 22:10:37.472013 TX OE : NO K
7045 22:10:37.472096 All Pass.
7046 22:10:37.472161
7047 22:10:37.475077 CH 0, Rank 1
7048 22:10:37.475159 SW Impedance : PASS
7049 22:10:37.478739 DUTY Scan : NO K
7050 22:10:37.481684 ZQ Calibration : PASS
7051 22:10:37.481767 Jitter Meter : NO K
7052 22:10:37.485132 CBT Training : PASS
7053 22:10:37.488466 Write leveling : NO K
7054 22:10:37.488548 RX DQS gating : PASS
7055 22:10:37.491748 RX DQ/DQS(RDDQC) : PASS
7056 22:10:37.491860 TX DQ/DQS : PASS
7057 22:10:37.494992 RX DATLAT : PASS
7058 22:10:37.498996 RX DQ/DQS(Engine): PASS
7059 22:10:37.499078 TX OE : NO K
7060 22:10:37.501667 All Pass.
7061 22:10:37.501749
7062 22:10:37.501815 CH 1, Rank 0
7063 22:10:37.505024 SW Impedance : PASS
7064 22:10:37.505106 DUTY Scan : NO K
7065 22:10:37.508436 ZQ Calibration : PASS
7066 22:10:37.511444 Jitter Meter : NO K
7067 22:10:37.511527 CBT Training : PASS
7068 22:10:37.514873 Write leveling : PASS
7069 22:10:37.518206 RX DQS gating : PASS
7070 22:10:37.518289 RX DQ/DQS(RDDQC) : PASS
7071 22:10:37.521374 TX DQ/DQS : PASS
7072 22:10:37.524677 RX DATLAT : PASS
7073 22:10:37.524780 RX DQ/DQS(Engine): PASS
7074 22:10:37.528045 TX OE : NO K
7075 22:10:37.528128 All Pass.
7076 22:10:37.528194
7077 22:10:37.531453 CH 1, Rank 1
7078 22:10:37.531536 SW Impedance : PASS
7079 22:10:37.534856 DUTY Scan : NO K
7080 22:10:37.537967 ZQ Calibration : PASS
7081 22:10:37.538049 Jitter Meter : NO K
7082 22:10:37.541227 CBT Training : PASS
7083 22:10:37.544452 Write leveling : NO K
7084 22:10:37.544561 RX DQS gating : PASS
7085 22:10:37.547858 RX DQ/DQS(RDDQC) : PASS
7086 22:10:37.551303 TX DQ/DQS : PASS
7087 22:10:37.551386 RX DATLAT : PASS
7088 22:10:37.554389 RX DQ/DQS(Engine): PASS
7089 22:10:37.554472 TX OE : NO K
7090 22:10:37.557724 All Pass.
7091 22:10:37.557816
7092 22:10:37.557882 DramC Write-DBI off
7093 22:10:37.561161 PER_BANK_REFRESH: Hybrid Mode
7094 22:10:37.564498 TX_TRACKING: ON
7095 22:10:37.571277 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7096 22:10:37.574542 [FAST_K] Save calibration result to emmc
7097 22:10:37.581018 dramc_set_vcore_voltage set vcore to 725000
7098 22:10:37.581100 Read voltage for 1600, 0
7099 22:10:37.581167 Vio18 = 0
7100 22:10:37.584335 Vcore = 725000
7101 22:10:37.584417 Vdram = 0
7102 22:10:37.584482 Vddq = 0
7103 22:10:37.587853 Vmddr = 0
7104 22:10:37.591325 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7105 22:10:37.597645 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7106 22:10:37.601151 MEM_TYPE=3, freq_sel=13
7107 22:10:37.601233 sv_algorithm_assistance_LP4_3733
7108 22:10:37.607976 ============ PULL DRAM RESETB DOWN ============
7109 22:10:37.611057 ========== PULL DRAM RESETB DOWN end =========
7110 22:10:37.614386 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7111 22:10:37.617551 ===================================
7112 22:10:37.620854 LPDDR4 DRAM CONFIGURATION
7113 22:10:37.624622 ===================================
7114 22:10:37.627980 EX_ROW_EN[0] = 0x0
7115 22:10:37.628061 EX_ROW_EN[1] = 0x0
7116 22:10:37.631096 LP4Y_EN = 0x0
7117 22:10:37.631184 WORK_FSP = 0x1
7118 22:10:37.634406 WL = 0x5
7119 22:10:37.634487 RL = 0x5
7120 22:10:37.637895 BL = 0x2
7121 22:10:37.637976 RPST = 0x0
7122 22:10:37.640974 RD_PRE = 0x0
7123 22:10:37.641055 WR_PRE = 0x1
7124 22:10:37.644048 WR_PST = 0x1
7125 22:10:37.644130 DBI_WR = 0x0
7126 22:10:37.647749 DBI_RD = 0x0
7127 22:10:37.647831 OTF = 0x1
7128 22:10:37.651033 ===================================
7129 22:10:37.654369 ===================================
7130 22:10:37.657842 ANA top config
7131 22:10:37.660627 ===================================
7132 22:10:37.664000 DLL_ASYNC_EN = 0
7133 22:10:37.664082 ALL_SLAVE_EN = 0
7134 22:10:37.667362 NEW_RANK_MODE = 1
7135 22:10:37.670823 DLL_IDLE_MODE = 1
7136 22:10:37.674371 LP45_APHY_COMB_EN = 1
7137 22:10:37.674452 TX_ODT_DIS = 0
7138 22:10:37.677452 NEW_8X_MODE = 1
7139 22:10:37.680982 ===================================
7140 22:10:37.684077 ===================================
7141 22:10:37.687698 data_rate = 3200
7142 22:10:37.690979 CKR = 1
7143 22:10:37.694004 DQ_P2S_RATIO = 8
7144 22:10:37.697442 ===================================
7145 22:10:37.700797 CA_P2S_RATIO = 8
7146 22:10:37.700878 DQ_CA_OPEN = 0
7147 22:10:37.704255 DQ_SEMI_OPEN = 0
7148 22:10:37.707560 CA_SEMI_OPEN = 0
7149 22:10:37.710841 CA_FULL_RATE = 0
7150 22:10:37.714102 DQ_CKDIV4_EN = 0
7151 22:10:37.717778 CA_CKDIV4_EN = 0
7152 22:10:37.717860 CA_PREDIV_EN = 0
7153 22:10:37.720920 PH8_DLY = 12
7154 22:10:37.724086 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7155 22:10:37.727695 DQ_AAMCK_DIV = 4
7156 22:10:37.731041 CA_AAMCK_DIV = 4
7157 22:10:37.733894 CA_ADMCK_DIV = 4
7158 22:10:37.734013 DQ_TRACK_CA_EN = 0
7159 22:10:37.737315 CA_PICK = 1600
7160 22:10:37.740531 CA_MCKIO = 1600
7161 22:10:37.743988 MCKIO_SEMI = 0
7162 22:10:37.747122 PLL_FREQ = 3068
7163 22:10:37.750708 DQ_UI_PI_RATIO = 32
7164 22:10:37.754339 CA_UI_PI_RATIO = 0
7165 22:10:37.757447 ===================================
7166 22:10:37.760550 ===================================
7167 22:10:37.760633 memory_type:LPDDR4
7168 22:10:37.764146 GP_NUM : 10
7169 22:10:37.767390 SRAM_EN : 1
7170 22:10:37.767472 MD32_EN : 0
7171 22:10:37.770462 ===================================
7172 22:10:37.773725 [ANA_INIT] >>>>>>>>>>>>>>
7173 22:10:37.777905 <<<<<< [CONFIGURE PHASE]: ANA_TX
7174 22:10:37.780433 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7175 22:10:37.783829 ===================================
7176 22:10:37.787030 data_rate = 3200,PCW = 0X7600
7177 22:10:37.790269 ===================================
7178 22:10:37.793825 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7179 22:10:37.797030 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7180 22:10:37.803693 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 22:10:37.807083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7182 22:10:37.810514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7183 22:10:37.813701 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7184 22:10:37.817185 [ANA_INIT] flow start
7185 22:10:37.820451 [ANA_INIT] PLL >>>>>>>>
7186 22:10:37.820585 [ANA_INIT] PLL <<<<<<<<
7187 22:10:37.823703 [ANA_INIT] MIDPI >>>>>>>>
7188 22:10:37.827000 [ANA_INIT] MIDPI <<<<<<<<
7189 22:10:37.830602 [ANA_INIT] DLL >>>>>>>>
7190 22:10:37.830721 [ANA_INIT] DLL <<<<<<<<
7191 22:10:37.833655 [ANA_INIT] flow end
7192 22:10:37.837168 ============ LP4 DIFF to SE enter ============
7193 22:10:37.840860 ============ LP4 DIFF to SE exit ============
7194 22:10:37.843813 [ANA_INIT] <<<<<<<<<<<<<
7195 22:10:37.846825 [Flow] Enable top DCM control >>>>>
7196 22:10:37.850528 [Flow] Enable top DCM control <<<<<
7197 22:10:37.853536 Enable DLL master slave shuffle
7198 22:10:37.857063 ==============================================================
7199 22:10:37.860504 Gating Mode config
7200 22:10:37.867241 ==============================================================
7201 22:10:37.867359 Config description:
7202 22:10:37.876956 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7203 22:10:37.883462 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7204 22:10:37.886949 SELPH_MODE 0: By rank 1: By Phase
7205 22:10:37.893509 ==============================================================
7206 22:10:37.896877 GAT_TRACK_EN = 1
7207 22:10:37.900419 RX_GATING_MODE = 2
7208 22:10:37.903403 RX_GATING_TRACK_MODE = 2
7209 22:10:37.906674 SELPH_MODE = 1
7210 22:10:37.910025 PICG_EARLY_EN = 1
7211 22:10:37.913463 VALID_LAT_VALUE = 1
7212 22:10:37.916649 ==============================================================
7213 22:10:37.920515 Enter into Gating configuration >>>>
7214 22:10:37.923348 Exit from Gating configuration <<<<
7215 22:10:37.927014 Enter into DVFS_PRE_config >>>>>
7216 22:10:37.940177 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7217 22:10:37.940316 Exit from DVFS_PRE_config <<<<<
7218 22:10:37.943597 Enter into PICG configuration >>>>
7219 22:10:37.946772 Exit from PICG configuration <<<<
7220 22:10:37.950201 [RX_INPUT] configuration >>>>>
7221 22:10:37.953356 [RX_INPUT] configuration <<<<<
7222 22:10:37.959961 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7223 22:10:37.963323 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7224 22:10:37.969836 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7225 22:10:37.976666 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7226 22:10:37.983076 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7227 22:10:37.989731 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7228 22:10:37.993761 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7229 22:10:37.996511 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7230 22:10:37.999758 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7231 22:10:38.006447 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7232 22:10:38.009607 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7233 22:10:38.012899 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7234 22:10:38.016522 ===================================
7235 22:10:38.019474 LPDDR4 DRAM CONFIGURATION
7236 22:10:38.022945 ===================================
7237 22:10:38.026082 EX_ROW_EN[0] = 0x0
7238 22:10:38.026154 EX_ROW_EN[1] = 0x0
7239 22:10:38.029770 LP4Y_EN = 0x0
7240 22:10:38.029841 WORK_FSP = 0x1
7241 22:10:38.032998 WL = 0x5
7242 22:10:38.033071 RL = 0x5
7243 22:10:38.036089 BL = 0x2
7244 22:10:38.036157 RPST = 0x0
7245 22:10:38.039515 RD_PRE = 0x0
7246 22:10:38.039586 WR_PRE = 0x1
7247 22:10:38.042955 WR_PST = 0x1
7248 22:10:38.043026 DBI_WR = 0x0
7249 22:10:38.046076 DBI_RD = 0x0
7250 22:10:38.046197 OTF = 0x1
7251 22:10:38.049621 ===================================
7252 22:10:38.052983 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7253 22:10:38.059745 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7254 22:10:38.062787 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 22:10:38.066070 ===================================
7256 22:10:38.069986 LPDDR4 DRAM CONFIGURATION
7257 22:10:38.073175 ===================================
7258 22:10:38.073246 EX_ROW_EN[0] = 0x10
7259 22:10:38.076221 EX_ROW_EN[1] = 0x0
7260 22:10:38.079535 LP4Y_EN = 0x0
7261 22:10:38.079615 WORK_FSP = 0x1
7262 22:10:38.082995 WL = 0x5
7263 22:10:38.083098 RL = 0x5
7264 22:10:38.086675 BL = 0x2
7265 22:10:38.086744 RPST = 0x0
7266 22:10:38.089654 RD_PRE = 0x0
7267 22:10:38.089764 WR_PRE = 0x1
7268 22:10:38.092942 WR_PST = 0x1
7269 22:10:38.093041 DBI_WR = 0x0
7270 22:10:38.096221 DBI_RD = 0x0
7271 22:10:38.096292 OTF = 0x1
7272 22:10:38.099769 ===================================
7273 22:10:38.106347 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7274 22:10:38.106430 ==
7275 22:10:38.109370 Dram Type= 6, Freq= 0, CH_0, rank 0
7276 22:10:38.112748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7277 22:10:38.112843 ==
7278 22:10:38.116017 [Duty_Offset_Calibration]
7279 22:10:38.119614 B0:2 B1:0 CA:1
7280 22:10:38.119702
7281 22:10:38.122374 [DutyScan_Calibration_Flow] k_type=0
7282 22:10:38.130787
7283 22:10:38.130857 ==CLK 0==
7284 22:10:38.133593 Final CLK duty delay cell = -4
7285 22:10:38.137222 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7286 22:10:38.140395 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7287 22:10:38.143764 [-4] AVG Duty = 4922%(X100)
7288 22:10:38.143838
7289 22:10:38.147453 CH0 CLK Duty spec in!! Max-Min= 156%
7290 22:10:38.150366 [DutyScan_Calibration_Flow] ====Done====
7291 22:10:38.150438
7292 22:10:38.153768 [DutyScan_Calibration_Flow] k_type=1
7293 22:10:38.169948
7294 22:10:38.170025 ==DQS 0 ==
7295 22:10:38.173530 Final DQS duty delay cell = 0
7296 22:10:38.176460 [0] MAX Duty = 5249%(X100), DQS PI = 32
7297 22:10:38.179897 [0] MIN Duty = 4969%(X100), DQS PI = 0
7298 22:10:38.179973 [0] AVG Duty = 5109%(X100)
7299 22:10:38.183372
7300 22:10:38.183469 ==DQS 1 ==
7301 22:10:38.186623 Final DQS duty delay cell = -4
7302 22:10:38.190137 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7303 22:10:38.193025 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7304 22:10:38.196283 [-4] AVG Duty = 5000%(X100)
7305 22:10:38.196355
7306 22:10:38.199656 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7307 22:10:38.199765
7308 22:10:38.202959 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7309 22:10:38.206423 [DutyScan_Calibration_Flow] ====Done====
7310 22:10:38.206496
7311 22:10:38.209422 [DutyScan_Calibration_Flow] k_type=3
7312 22:10:38.227186
7313 22:10:38.227281 ==DQM 0 ==
7314 22:10:38.230650 Final DQM duty delay cell = 0
7315 22:10:38.234042 [0] MAX Duty = 5124%(X100), DQS PI = 26
7316 22:10:38.237622 [0] MIN Duty = 4813%(X100), DQS PI = 52
7317 22:10:38.237700 [0] AVG Duty = 4968%(X100)
7318 22:10:38.240454
7319 22:10:38.240520 ==DQM 1 ==
7320 22:10:38.243787 Final DQM duty delay cell = 0
7321 22:10:38.247233 [0] MAX Duty = 5249%(X100), DQS PI = 30
7322 22:10:38.250602 [0] MIN Duty = 5000%(X100), DQS PI = 20
7323 22:10:38.253963 [0] AVG Duty = 5124%(X100)
7324 22:10:38.254044
7325 22:10:38.257155 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7326 22:10:38.257232
7327 22:10:38.260462 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7328 22:10:38.263719 [DutyScan_Calibration_Flow] ====Done====
7329 22:10:38.263793
7330 22:10:38.267154 [DutyScan_Calibration_Flow] k_type=2
7331 22:10:38.284316
7332 22:10:38.284390 ==DQ 0 ==
7333 22:10:38.287910 Final DQ duty delay cell = 0
7334 22:10:38.291048 [0] MAX Duty = 5124%(X100), DQS PI = 32
7335 22:10:38.294401 [0] MIN Duty = 5000%(X100), DQS PI = 16
7336 22:10:38.294476 [0] AVG Duty = 5062%(X100)
7337 22:10:38.298313
7338 22:10:38.298384 ==DQ 1 ==
7339 22:10:38.300888 Final DQ duty delay cell = 0
7340 22:10:38.304249 [0] MAX Duty = 4969%(X100), DQS PI = 44
7341 22:10:38.307660 [0] MIN Duty = 4875%(X100), DQS PI = 10
7342 22:10:38.307767 [0] AVG Duty = 4922%(X100)
7343 22:10:38.310868
7344 22:10:38.314339 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7345 22:10:38.314415
7346 22:10:38.317572 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7347 22:10:38.320973 [DutyScan_Calibration_Flow] ====Done====
7348 22:10:38.321047 ==
7349 22:10:38.324195 Dram Type= 6, Freq= 0, CH_1, rank 0
7350 22:10:38.327686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7351 22:10:38.327767 ==
7352 22:10:38.331056 [Duty_Offset_Calibration]
7353 22:10:38.331137 B0:0 B1:-1 CA:2
7354 22:10:38.331200
7355 22:10:38.334150 [DutyScan_Calibration_Flow] k_type=0
7356 22:10:38.344564
7357 22:10:38.344643 ==CLK 0==
7358 22:10:38.348062 Final CLK duty delay cell = 0
7359 22:10:38.351228 [0] MAX Duty = 5156%(X100), DQS PI = 12
7360 22:10:38.354731 [0] MIN Duty = 4906%(X100), DQS PI = 46
7361 22:10:38.357800 [0] AVG Duty = 5031%(X100)
7362 22:10:38.357925
7363 22:10:38.361369 CH1 CLK Duty spec in!! Max-Min= 250%
7364 22:10:38.364806 [DutyScan_Calibration_Flow] ====Done====
7365 22:10:38.364928
7366 22:10:38.368011 [DutyScan_Calibration_Flow] k_type=1
7367 22:10:38.384720
7368 22:10:38.384860 ==DQS 0 ==
7369 22:10:38.387844 Final DQS duty delay cell = 0
7370 22:10:38.390970 [0] MAX Duty = 5093%(X100), DQS PI = 26
7371 22:10:38.394625 [0] MIN Duty = 5000%(X100), DQS PI = 0
7372 22:10:38.394705 [0] AVG Duty = 5046%(X100)
7373 22:10:38.398151
7374 22:10:38.398230 ==DQS 1 ==
7375 22:10:38.401146 Final DQS duty delay cell = 0
7376 22:10:38.404318 [0] MAX Duty = 5187%(X100), DQS PI = 60
7377 22:10:38.407699 [0] MIN Duty = 4844%(X100), DQS PI = 32
7378 22:10:38.407770 [0] AVG Duty = 5015%(X100)
7379 22:10:38.411055
7380 22:10:38.414406 CH1 DQS 0 Duty spec in!! Max-Min= 93%
7381 22:10:38.414526
7382 22:10:38.417670 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7383 22:10:38.421111 [DutyScan_Calibration_Flow] ====Done====
7384 22:10:38.421231
7385 22:10:38.424250 [DutyScan_Calibration_Flow] k_type=3
7386 22:10:38.442187
7387 22:10:38.442266 ==DQM 0 ==
7388 22:10:38.445154 Final DQM duty delay cell = 4
7389 22:10:38.448534 [4] MAX Duty = 5125%(X100), DQS PI = 8
7390 22:10:38.451970 [4] MIN Duty = 4938%(X100), DQS PI = 48
7391 22:10:38.452050 [4] AVG Duty = 5031%(X100)
7392 22:10:38.455490
7393 22:10:38.455569 ==DQM 1 ==
7394 22:10:38.458814 Final DQM duty delay cell = 0
7395 22:10:38.461745 [0] MAX Duty = 5281%(X100), DQS PI = 58
7396 22:10:38.465521 [0] MIN Duty = 4876%(X100), DQS PI = 34
7397 22:10:38.465619 [0] AVG Duty = 5078%(X100)
7398 22:10:38.468729
7399 22:10:38.472040 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7400 22:10:38.472160
7401 22:10:38.475301 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7402 22:10:38.478404 [DutyScan_Calibration_Flow] ====Done====
7403 22:10:38.478510
7404 22:10:38.481869 [DutyScan_Calibration_Flow] k_type=2
7405 22:10:38.498933
7406 22:10:38.499014 ==DQ 0 ==
7407 22:10:38.502255 Final DQ duty delay cell = 0
7408 22:10:38.505362 [0] MAX Duty = 5093%(X100), DQS PI = 18
7409 22:10:38.508732 [0] MIN Duty = 4969%(X100), DQS PI = 46
7410 22:10:38.508861 [0] AVG Duty = 5031%(X100)
7411 22:10:38.512119
7412 22:10:38.512242 ==DQ 1 ==
7413 22:10:38.515352 Final DQ duty delay cell = 0
7414 22:10:38.518998 [0] MAX Duty = 5062%(X100), DQS PI = 2
7415 22:10:38.522307 [0] MIN Duty = 4844%(X100), DQS PI = 32
7416 22:10:38.522451 [0] AVG Duty = 4953%(X100)
7417 22:10:38.522528
7418 22:10:38.525510 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7419 22:10:38.529100
7420 22:10:38.531965 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7421 22:10:38.535282 [DutyScan_Calibration_Flow] ====Done====
7422 22:10:38.538499 nWR fixed to 30
7423 22:10:38.538598 [ModeRegInit_LP4] CH0 RK0
7424 22:10:38.541876 [ModeRegInit_LP4] CH0 RK1
7425 22:10:38.545128 [ModeRegInit_LP4] CH1 RK0
7426 22:10:38.548321 [ModeRegInit_LP4] CH1 RK1
7427 22:10:38.548483 match AC timing 5
7428 22:10:38.551752 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7429 22:10:38.558521 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7430 22:10:38.561833 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7431 22:10:38.565252 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7432 22:10:38.571809 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7433 22:10:38.571930 [MiockJmeterHQA]
7434 22:10:38.572040
7435 22:10:38.575075 [DramcMiockJmeter] u1RxGatingPI = 0
7436 22:10:38.578682 0 : 4253, 4026
7437 22:10:38.578803 4 : 4367, 4140
7438 22:10:38.578915 8 : 4257, 4029
7439 22:10:38.581793 12 : 4253, 4026
7440 22:10:38.581913 16 : 4363, 4137
7441 22:10:38.585157 20 : 4253, 4026
7442 22:10:38.585275 24 : 4252, 4027
7443 22:10:38.588597 28 : 4253, 4026
7444 22:10:38.588712 32 : 4255, 4030
7445 22:10:38.591862 36 : 4253, 4027
7446 22:10:38.591978 40 : 4363, 4137
7447 22:10:38.592088 44 : 4363, 4138
7448 22:10:38.595221 48 : 4253, 4026
7449 22:10:38.595341 52 : 4253, 4027
7450 22:10:38.598695 56 : 4253, 4026
7451 22:10:38.598813 60 : 4252, 4027
7452 22:10:38.601581 64 : 4250, 4027
7453 22:10:38.601702 68 : 4250, 4027
7454 22:10:38.605094 72 : 4257, 4029
7455 22:10:38.605214 76 : 4250, 4026
7456 22:10:38.605326 80 : 4250, 4026
7457 22:10:38.608372 84 : 4252, 4030
7458 22:10:38.608492 88 : 4250, 3522
7459 22:10:38.611727 92 : 4363, 0
7460 22:10:38.611850 96 : 4363, 0
7461 22:10:38.611963 100 : 4252, 0
7462 22:10:38.615055 104 : 4250, 0
7463 22:10:38.615172 108 : 4250, 0
7464 22:10:38.618494 112 : 4250, 0
7465 22:10:38.618616 116 : 4250, 0
7466 22:10:38.618733 120 : 4253, 0
7467 22:10:38.621711 124 : 4255, 0
7468 22:10:38.621830 128 : 4249, 0
7469 22:10:38.625272 132 : 4363, 0
7470 22:10:38.625395 136 : 4255, 0
7471 22:10:38.625513 140 : 4250, 0
7472 22:10:38.628319 144 : 4250, 0
7473 22:10:38.628441 148 : 4252, 0
7474 22:10:38.628555 152 : 4250, 0
7475 22:10:38.631951 156 : 4250, 0
7476 22:10:38.632070 160 : 4252, 0
7477 22:10:38.635104 164 : 4361, 0
7478 22:10:38.635226 168 : 4250, 0
7479 22:10:38.635337 172 : 4250, 0
7480 22:10:38.638221 176 : 4250, 0
7481 22:10:38.638344 180 : 4250, 0
7482 22:10:38.641726 184 : 4363, 0
7483 22:10:38.641847 188 : 4250, 0
7484 22:10:38.641960 192 : 4250, 0
7485 22:10:38.645082 196 : 4250, 0
7486 22:10:38.645204 200 : 4252, 1
7487 22:10:38.648204 204 : 4249, 2210
7488 22:10:38.648383 208 : 4250, 4027
7489 22:10:38.651998 212 : 4250, 4026
7490 22:10:38.652120 216 : 4253, 4029
7491 22:10:38.652230 220 : 4250, 4027
7492 22:10:38.655059 224 : 4255, 4029
7493 22:10:38.655180 228 : 4250, 4027
7494 22:10:38.658235 232 : 4252, 4030
7495 22:10:38.658355 236 : 4250, 4027
7496 22:10:38.661757 240 : 4361, 4137
7497 22:10:38.661875 244 : 4250, 4026
7498 22:10:38.665109 248 : 4361, 4137
7499 22:10:38.665225 252 : 4250, 4027
7500 22:10:38.668124 256 : 4250, 4027
7501 22:10:38.668242 260 : 4250, 4026
7502 22:10:38.672096 264 : 4250, 4027
7503 22:10:38.672211 268 : 4250, 4027
7504 22:10:38.674735 272 : 4254, 4030
7505 22:10:38.674851 276 : 4250, 4026
7506 22:10:38.674958 280 : 4253, 4029
7507 22:10:38.678032 284 : 4250, 4027
7508 22:10:38.678151 288 : 4254, 4030
7509 22:10:38.681659 292 : 4361, 4137
7510 22:10:38.681781 296 : 4250, 4026
7511 22:10:38.684912 300 : 4361, 4137
7512 22:10:38.685027 304 : 4256, 4030
7513 22:10:38.688178 308 : 4250, 4027
7514 22:10:38.688299 312 : 4250, 3920
7515 22:10:38.691630 316 : 4250, 2000
7516 22:10:38.691747
7517 22:10:38.691856 MIOCK jitter meter ch=0
7518 22:10:38.691965
7519 22:10:38.694913 1T = (316-92) = 224 dly cells
7520 22:10:38.701310 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7521 22:10:38.701427 ==
7522 22:10:38.704786 Dram Type= 6, Freq= 0, CH_0, rank 0
7523 22:10:38.708131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 22:10:38.708249 ==
7525 22:10:38.714793 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 22:10:38.718718 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 22:10:38.721354 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 22:10:38.728042 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 22:10:38.737776 [CA 0] Center 43 (13~73) winsize 61
7530 22:10:38.741243 [CA 1] Center 43 (13~73) winsize 61
7531 22:10:38.744226 [CA 2] Center 38 (8~68) winsize 61
7532 22:10:38.747557 [CA 3] Center 37 (8~67) winsize 60
7533 22:10:38.750946 [CA 4] Center 36 (6~66) winsize 61
7534 22:10:38.754495 [CA 5] Center 35 (5~65) winsize 61
7535 22:10:38.754618
7536 22:10:38.757680 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7537 22:10:38.757804
7538 22:10:38.760743 [CATrainingPosCal] consider 1 rank data
7539 22:10:38.764152 u2DelayCellTimex100 = 290/100 ps
7540 22:10:38.767522 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7541 22:10:38.774317 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7542 22:10:38.777676 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7543 22:10:38.780684 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7544 22:10:38.784225 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7545 22:10:38.787506 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7546 22:10:38.787624
7547 22:10:38.790805 CA PerBit enable=1, Macro0, CA PI delay=35
7548 22:10:38.790923
7549 22:10:38.794113 [CBTSetCACLKResult] CA Dly = 35
7550 22:10:38.797412 CS Dly: 9 (0~40)
7551 22:10:38.800876 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 22:10:38.804070 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 22:10:38.804187 ==
7554 22:10:38.807571 Dram Type= 6, Freq= 0, CH_0, rank 1
7555 22:10:38.810707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 22:10:38.810828 ==
7557 22:10:38.817420 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7558 22:10:38.821251 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7559 22:10:38.827302 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7560 22:10:38.830583 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7561 22:10:38.841155 [CA 0] Center 43 (13~74) winsize 62
7562 22:10:38.844102 [CA 1] Center 43 (13~73) winsize 61
7563 22:10:38.848275 [CA 2] Center 38 (9~68) winsize 60
7564 22:10:38.851012 [CA 3] Center 38 (9~68) winsize 60
7565 22:10:38.854212 [CA 4] Center 37 (7~67) winsize 61
7566 22:10:38.857428 [CA 5] Center 36 (6~66) winsize 61
7567 22:10:38.857548
7568 22:10:38.860705 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7569 22:10:38.860855
7570 22:10:38.864139 [CATrainingPosCal] consider 2 rank data
7571 22:10:38.867491 u2DelayCellTimex100 = 290/100 ps
7572 22:10:38.870748 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7573 22:10:38.877479 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7574 22:10:38.880587 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7575 22:10:38.884081 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7576 22:10:38.887655 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7577 22:10:38.890773 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7578 22:10:38.890892
7579 22:10:38.894269 CA PerBit enable=1, Macro0, CA PI delay=35
7580 22:10:38.894389
7581 22:10:38.897485 [CBTSetCACLKResult] CA Dly = 35
7582 22:10:38.900814 CS Dly: 10 (0~43)
7583 22:10:38.904240 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7584 22:10:38.907652 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7585 22:10:38.907772
7586 22:10:38.910719 ----->DramcWriteLeveling(PI) begin...
7587 22:10:38.910840 ==
7588 22:10:38.914024 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 22:10:38.920998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 22:10:38.921118 ==
7591 22:10:38.923761 Write leveling (Byte 0): 37 => 37
7592 22:10:38.923879 Write leveling (Byte 1): 31 => 31
7593 22:10:38.927252 DramcWriteLeveling(PI) end<-----
7594 22:10:38.927369
7595 22:10:38.927475 ==
7596 22:10:38.930534 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 22:10:38.937183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 22:10:38.937304 ==
7599 22:10:38.940399 [Gating] SW mode calibration
7600 22:10:38.947097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7601 22:10:38.950661 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7602 22:10:38.957059 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 22:10:38.960458 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 22:10:38.963699 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7605 22:10:38.970362 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7606 22:10:38.973584 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7607 22:10:38.976960 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7608 22:10:38.983790 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 22:10:38.986847 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 22:10:38.990223 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 22:10:38.996806 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 22:10:39.000278 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
7613 22:10:39.003629 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7614 22:10:39.007389 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7615 22:10:39.013701 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
7616 22:10:39.016975 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 22:10:39.020109 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 22:10:39.026856 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 22:10:39.030386 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7620 22:10:39.033427 1 6 8 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7621 22:10:39.040146 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7622 22:10:39.043890 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7623 22:10:39.047186 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7624 22:10:39.053742 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 22:10:39.056973 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 22:10:39.060149 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 22:10:39.066607 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 22:10:39.070041 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7629 22:10:39.073309 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 22:10:39.080089 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 22:10:39.083398 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7632 22:10:39.086675 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 22:10:39.093247 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 22:10:39.096641 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 22:10:39.100207 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 22:10:39.106457 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 22:10:39.110177 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 22:10:39.113619 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 22:10:39.120000 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 22:10:39.123143 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 22:10:39.126637 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 22:10:39.133275 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 22:10:39.136700 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 22:10:39.140358 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 22:10:39.143679 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 22:10:39.149969 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7647 22:10:39.153334 Total UI for P1: 0, mck2ui 16
7648 22:10:39.156805 best dqsien dly found for B0: ( 1, 9, 10)
7649 22:10:39.160259 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 22:10:39.163287 Total UI for P1: 0, mck2ui 16
7651 22:10:39.166878 best dqsien dly found for B1: ( 1, 9, 18)
7652 22:10:39.170725 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7653 22:10:39.173338 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7654 22:10:39.173445
7655 22:10:39.176505 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7656 22:10:39.180178 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7657 22:10:39.183267 [Gating] SW calibration Done
7658 22:10:39.183351 ==
7659 22:10:39.186679 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 22:10:39.193148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 22:10:39.193232 ==
7662 22:10:39.193331 RX Vref Scan: 0
7663 22:10:39.193392
7664 22:10:39.196468 RX Vref 0 -> 0, step: 1
7665 22:10:39.196550
7666 22:10:39.199913 RX Delay 0 -> 252, step: 8
7667 22:10:39.203284 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7668 22:10:39.206542 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7669 22:10:39.209857 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7670 22:10:39.212966 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7671 22:10:39.219696 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7672 22:10:39.223183 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7673 22:10:39.226468 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7674 22:10:39.229598 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7675 22:10:39.233327 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7676 22:10:39.236533 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7677 22:10:39.243191 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7678 22:10:39.246626 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7679 22:10:39.250379 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7680 22:10:39.252956 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7681 22:10:39.259931 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7682 22:10:39.263344 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7683 22:10:39.263418 ==
7684 22:10:39.266122 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 22:10:39.269789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 22:10:39.269869 ==
7687 22:10:39.269934 DQS Delay:
7688 22:10:39.272909 DQS0 = 0, DQS1 = 0
7689 22:10:39.272994 DQM Delay:
7690 22:10:39.276298 DQM0 = 138, DQM1 = 126
7691 22:10:39.276429 DQ Delay:
7692 22:10:39.279406 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7693 22:10:39.282854 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7694 22:10:39.286031 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7695 22:10:39.293002 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7696 22:10:39.293134
7697 22:10:39.293249
7698 22:10:39.293361 ==
7699 22:10:39.296131 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 22:10:39.299600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 22:10:39.299684 ==
7702 22:10:39.299750
7703 22:10:39.299827
7704 22:10:39.302671 TX Vref Scan disable
7705 22:10:39.302768 == TX Byte 0 ==
7706 22:10:39.309446 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7707 22:10:39.312575 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7708 22:10:39.312658 == TX Byte 1 ==
7709 22:10:39.319322 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7710 22:10:39.322943 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7711 22:10:39.323073 ==
7712 22:10:39.326262 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 22:10:39.329338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 22:10:39.329421 ==
7715 22:10:39.343303
7716 22:10:39.346833 TX Vref early break, caculate TX vref
7717 22:10:39.349961 TX Vref=16, minBit 7, minWin=22, winSum=378
7718 22:10:39.353191 TX Vref=18, minBit 8, minWin=23, winSum=389
7719 22:10:39.356644 TX Vref=20, minBit 6, minWin=24, winSum=399
7720 22:10:39.359792 TX Vref=22, minBit 12, minWin=24, winSum=406
7721 22:10:39.363483 TX Vref=24, minBit 2, minWin=25, winSum=417
7722 22:10:39.369862 TX Vref=26, minBit 12, minWin=25, winSum=423
7723 22:10:39.373519 TX Vref=28, minBit 2, minWin=26, winSum=429
7724 22:10:39.376503 TX Vref=30, minBit 0, minWin=26, winSum=426
7725 22:10:39.379872 TX Vref=32, minBit 0, minWin=25, winSum=414
7726 22:10:39.383232 TX Vref=34, minBit 1, minWin=24, winSum=403
7727 22:10:39.390098 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 28
7728 22:10:39.390181
7729 22:10:39.393538 Final TX Range 0 Vref 28
7730 22:10:39.393622
7731 22:10:39.393688 ==
7732 22:10:39.396542 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 22:10:39.400029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 22:10:39.400112 ==
7735 22:10:39.400177
7736 22:10:39.400238
7737 22:10:39.403155 TX Vref Scan disable
7738 22:10:39.409967 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7739 22:10:39.410046 == TX Byte 0 ==
7740 22:10:39.413204 u2DelayCellOfst[0]=10 cells (3 PI)
7741 22:10:39.416385 u2DelayCellOfst[1]=16 cells (5 PI)
7742 22:10:39.419833 u2DelayCellOfst[2]=10 cells (3 PI)
7743 22:10:39.423574 u2DelayCellOfst[3]=10 cells (3 PI)
7744 22:10:39.426575 u2DelayCellOfst[4]=6 cells (2 PI)
7745 22:10:39.430179 u2DelayCellOfst[5]=0 cells (0 PI)
7746 22:10:39.433345 u2DelayCellOfst[6]=16 cells (5 PI)
7747 22:10:39.433418 u2DelayCellOfst[7]=13 cells (4 PI)
7748 22:10:39.440227 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7749 22:10:39.443504 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7750 22:10:39.443578 == TX Byte 1 ==
7751 22:10:39.446471 u2DelayCellOfst[8]=0 cells (0 PI)
7752 22:10:39.450149 u2DelayCellOfst[9]=0 cells (0 PI)
7753 22:10:39.453237 u2DelayCellOfst[10]=6 cells (2 PI)
7754 22:10:39.456613 u2DelayCellOfst[11]=3 cells (1 PI)
7755 22:10:39.459661 u2DelayCellOfst[12]=13 cells (4 PI)
7756 22:10:39.463126 u2DelayCellOfst[13]=13 cells (4 PI)
7757 22:10:39.466587 u2DelayCellOfst[14]=13 cells (4 PI)
7758 22:10:39.469804 u2DelayCellOfst[15]=10 cells (3 PI)
7759 22:10:39.473217 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7760 22:10:39.479840 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7761 22:10:39.479923 DramC Write-DBI on
7762 22:10:39.479989 ==
7763 22:10:39.483182 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 22:10:39.486505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 22:10:39.486588 ==
7766 22:10:39.489764
7767 22:10:39.489845
7768 22:10:39.489911 TX Vref Scan disable
7769 22:10:39.493203 == TX Byte 0 ==
7770 22:10:39.496242 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7771 22:10:39.499903 == TX Byte 1 ==
7772 22:10:39.502859 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7773 22:10:39.506690 DramC Write-DBI off
7774 22:10:39.506772
7775 22:10:39.506837 [DATLAT]
7776 22:10:39.506898 Freq=1600, CH0 RK0
7777 22:10:39.506958
7778 22:10:39.509799 DATLAT Default: 0xf
7779 22:10:39.509881 0, 0xFFFF, sum = 0
7780 22:10:39.513019 1, 0xFFFF, sum = 0
7781 22:10:39.513103 2, 0xFFFF, sum = 0
7782 22:10:39.516494 3, 0xFFFF, sum = 0
7783 22:10:39.519847 4, 0xFFFF, sum = 0
7784 22:10:39.519971 5, 0xFFFF, sum = 0
7785 22:10:39.523035 6, 0xFFFF, sum = 0
7786 22:10:39.523150 7, 0xFFFF, sum = 0
7787 22:10:39.526060 8, 0xFFFF, sum = 0
7788 22:10:39.526144 9, 0xFFFF, sum = 0
7789 22:10:39.529557 10, 0xFFFF, sum = 0
7790 22:10:39.529642 11, 0xFFFF, sum = 0
7791 22:10:39.533102 12, 0xFFFF, sum = 0
7792 22:10:39.533186 13, 0xFFFF, sum = 0
7793 22:10:39.536126 14, 0x0, sum = 1
7794 22:10:39.536210 15, 0x0, sum = 2
7795 22:10:39.539591 16, 0x0, sum = 3
7796 22:10:39.539674 17, 0x0, sum = 4
7797 22:10:39.543193 best_step = 15
7798 22:10:39.543275
7799 22:10:39.543340 ==
7800 22:10:39.546397 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 22:10:39.549830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 22:10:39.549939 ==
7803 22:10:39.550043 RX Vref Scan: 1
7804 22:10:39.552757
7805 22:10:39.552868 Set Vref Range= 24 -> 127
7806 22:10:39.552957
7807 22:10:39.556453 RX Vref 24 -> 127, step: 1
7808 22:10:39.556536
7809 22:10:39.559297 RX Delay 19 -> 252, step: 4
7810 22:10:39.559381
7811 22:10:39.562894 Set Vref, RX VrefLevel [Byte0]: 24
7812 22:10:39.565854 [Byte1]: 24
7813 22:10:39.565936
7814 22:10:39.569369 Set Vref, RX VrefLevel [Byte0]: 25
7815 22:10:39.572641 [Byte1]: 25
7816 22:10:39.572749
7817 22:10:39.576058 Set Vref, RX VrefLevel [Byte0]: 26
7818 22:10:39.579841 [Byte1]: 26
7819 22:10:39.583107
7820 22:10:39.583194 Set Vref, RX VrefLevel [Byte0]: 27
7821 22:10:39.586420 [Byte1]: 27
7822 22:10:39.590786
7823 22:10:39.590868 Set Vref, RX VrefLevel [Byte0]: 28
7824 22:10:39.594386 [Byte1]: 28
7825 22:10:39.598292
7826 22:10:39.598375 Set Vref, RX VrefLevel [Byte0]: 29
7827 22:10:39.601707 [Byte1]: 29
7828 22:10:39.605921
7829 22:10:39.606003 Set Vref, RX VrefLevel [Byte0]: 30
7830 22:10:39.609335 [Byte1]: 30
7831 22:10:39.613698
7832 22:10:39.613781 Set Vref, RX VrefLevel [Byte0]: 31
7833 22:10:39.616655 [Byte1]: 31
7834 22:10:39.621025
7835 22:10:39.621107 Set Vref, RX VrefLevel [Byte0]: 32
7836 22:10:39.624373 [Byte1]: 32
7837 22:10:39.628665
7838 22:10:39.628750 Set Vref, RX VrefLevel [Byte0]: 33
7839 22:10:39.631767 [Byte1]: 33
7840 22:10:39.636569
7841 22:10:39.636652 Set Vref, RX VrefLevel [Byte0]: 34
7842 22:10:39.639758 [Byte1]: 34
7843 22:10:39.643851
7844 22:10:39.643934 Set Vref, RX VrefLevel [Byte0]: 35
7845 22:10:39.647131 [Byte1]: 35
7846 22:10:39.651582
7847 22:10:39.651691 Set Vref, RX VrefLevel [Byte0]: 36
7848 22:10:39.654457 [Byte1]: 36
7849 22:10:39.658978
7850 22:10:39.659065 Set Vref, RX VrefLevel [Byte0]: 37
7851 22:10:39.662286 [Byte1]: 37
7852 22:10:39.666367
7853 22:10:39.666449 Set Vref, RX VrefLevel [Byte0]: 38
7854 22:10:39.669688 [Byte1]: 38
7855 22:10:39.674005
7856 22:10:39.674086 Set Vref, RX VrefLevel [Byte0]: 39
7857 22:10:39.677685 [Byte1]: 39
7858 22:10:39.681522
7859 22:10:39.681604 Set Vref, RX VrefLevel [Byte0]: 40
7860 22:10:39.685022 [Byte1]: 40
7861 22:10:39.689512
7862 22:10:39.689594 Set Vref, RX VrefLevel [Byte0]: 41
7863 22:10:39.692534 [Byte1]: 41
7864 22:10:39.696933
7865 22:10:39.697028 Set Vref, RX VrefLevel [Byte0]: 42
7866 22:10:39.700099 [Byte1]: 42
7867 22:10:39.704359
7868 22:10:39.704467 Set Vref, RX VrefLevel [Byte0]: 43
7869 22:10:39.707800 [Byte1]: 43
7870 22:10:39.712036
7871 22:10:39.712118 Set Vref, RX VrefLevel [Byte0]: 44
7872 22:10:39.715249 [Byte1]: 44
7873 22:10:39.719761
7874 22:10:39.719842 Set Vref, RX VrefLevel [Byte0]: 45
7875 22:10:39.723050 [Byte1]: 45
7876 22:10:39.727298
7877 22:10:39.727380 Set Vref, RX VrefLevel [Byte0]: 46
7878 22:10:39.730692 [Byte1]: 46
7879 22:10:39.734721
7880 22:10:39.734803 Set Vref, RX VrefLevel [Byte0]: 47
7881 22:10:39.738086 [Byte1]: 47
7882 22:10:39.742283
7883 22:10:39.742398 Set Vref, RX VrefLevel [Byte0]: 48
7884 22:10:39.745754 [Byte1]: 48
7885 22:10:39.749867
7886 22:10:39.749961 Set Vref, RX VrefLevel [Byte0]: 49
7887 22:10:39.753107 [Byte1]: 49
7888 22:10:39.757873
7889 22:10:39.757955 Set Vref, RX VrefLevel [Byte0]: 50
7890 22:10:39.760521 [Byte1]: 50
7891 22:10:39.764987
7892 22:10:39.765069 Set Vref, RX VrefLevel [Byte0]: 51
7893 22:10:39.768429 [Byte1]: 51
7894 22:10:39.772743
7895 22:10:39.772861 Set Vref, RX VrefLevel [Byte0]: 52
7896 22:10:39.775948 [Byte1]: 52
7897 22:10:39.780129
7898 22:10:39.780211 Set Vref, RX VrefLevel [Byte0]: 53
7899 22:10:39.783585 [Byte1]: 53
7900 22:10:39.787643
7901 22:10:39.787763 Set Vref, RX VrefLevel [Byte0]: 54
7902 22:10:39.790807 [Byte1]: 54
7903 22:10:39.795332
7904 22:10:39.795453 Set Vref, RX VrefLevel [Byte0]: 55
7905 22:10:39.798776 [Byte1]: 55
7906 22:10:39.802788
7907 22:10:39.802870 Set Vref, RX VrefLevel [Byte0]: 56
7908 22:10:39.806000 [Byte1]: 56
7909 22:10:39.810326
7910 22:10:39.810408 Set Vref, RX VrefLevel [Byte0]: 57
7911 22:10:39.813689 [Byte1]: 57
7912 22:10:39.817958
7913 22:10:39.818043 Set Vref, RX VrefLevel [Byte0]: 58
7914 22:10:39.821174 [Byte1]: 58
7915 22:10:39.825631
7916 22:10:39.825713 Set Vref, RX VrefLevel [Byte0]: 59
7917 22:10:39.828643 [Byte1]: 59
7918 22:10:39.832932
7919 22:10:39.833013 Set Vref, RX VrefLevel [Byte0]: 60
7920 22:10:39.836411 [Byte1]: 60
7921 22:10:39.840686
7922 22:10:39.840793 Set Vref, RX VrefLevel [Byte0]: 61
7923 22:10:39.843845 [Byte1]: 61
7924 22:10:39.848233
7925 22:10:39.848316 Set Vref, RX VrefLevel [Byte0]: 62
7926 22:10:39.851570 [Byte1]: 62
7927 22:10:39.855733
7928 22:10:39.855816 Set Vref, RX VrefLevel [Byte0]: 63
7929 22:10:39.859275 [Byte1]: 63
7930 22:10:39.863583
7931 22:10:39.863665 Set Vref, RX VrefLevel [Byte0]: 64
7932 22:10:39.866573 [Byte1]: 64
7933 22:10:39.870785
7934 22:10:39.870867 Set Vref, RX VrefLevel [Byte0]: 65
7935 22:10:39.874290 [Byte1]: 65
7936 22:10:39.878389
7937 22:10:39.878472 Set Vref, RX VrefLevel [Byte0]: 66
7938 22:10:39.881858 [Byte1]: 66
7939 22:10:39.885855
7940 22:10:39.889786 Set Vref, RX VrefLevel [Byte0]: 67
7941 22:10:39.889907 [Byte1]: 67
7942 22:10:39.893642
7943 22:10:39.893768 Set Vref, RX VrefLevel [Byte0]: 68
7944 22:10:39.896925 [Byte1]: 68
7945 22:10:39.901027
7946 22:10:39.901148 Set Vref, RX VrefLevel [Byte0]: 69
7947 22:10:39.904459 [Byte1]: 69
7948 22:10:39.908606
7949 22:10:39.908721 Set Vref, RX VrefLevel [Byte0]: 70
7950 22:10:39.911986 [Byte1]: 70
7951 22:10:39.916537
7952 22:10:39.916652 Set Vref, RX VrefLevel [Byte0]: 71
7953 22:10:39.919733 [Byte1]: 71
7954 22:10:39.923813
7955 22:10:39.923933 Set Vref, RX VrefLevel [Byte0]: 72
7956 22:10:39.927415 [Byte1]: 72
7957 22:10:39.932108
7958 22:10:39.932225 Set Vref, RX VrefLevel [Byte0]: 73
7959 22:10:39.934909 [Byte1]: 73
7960 22:10:39.939145
7961 22:10:39.939267 Set Vref, RX VrefLevel [Byte0]: 74
7962 22:10:39.942597 [Byte1]: 74
7963 22:10:39.946653
7964 22:10:39.946776 Set Vref, RX VrefLevel [Byte0]: 75
7965 22:10:39.949856 [Byte1]: 75
7966 22:10:39.954308
7967 22:10:39.954423 Set Vref, RX VrefLevel [Byte0]: 76
7968 22:10:39.957301 [Byte1]: 76
7969 22:10:39.961736
7970 22:10:39.961862 Set Vref, RX VrefLevel [Byte0]: 77
7971 22:10:39.965192 [Byte1]: 77
7972 22:10:39.969348
7973 22:10:39.969470 Set Vref, RX VrefLevel [Byte0]: 78
7974 22:10:39.972642 [Byte1]: 78
7975 22:10:39.977002
7976 22:10:39.977126 Set Vref, RX VrefLevel [Byte0]: 79
7977 22:10:39.980368 [Byte1]: 79
7978 22:10:39.984462
7979 22:10:39.984582 Final RX Vref Byte 0 = 64 to rank0
7980 22:10:39.987734 Final RX Vref Byte 1 = 61 to rank0
7981 22:10:39.991194 Final RX Vref Byte 0 = 64 to rank1
7982 22:10:39.994384 Final RX Vref Byte 1 = 61 to rank1==
7983 22:10:39.997730 Dram Type= 6, Freq= 0, CH_0, rank 0
7984 22:10:40.004569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 22:10:40.004692 ==
7986 22:10:40.004842 DQS Delay:
7987 22:10:40.004954 DQS0 = 0, DQS1 = 0
7988 22:10:40.007814 DQM Delay:
7989 22:10:40.007938 DQM0 = 136, DQM1 = 124
7990 22:10:40.011217 DQ Delay:
7991 22:10:40.014553 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7992 22:10:40.017537 DQ4 =138, DQ5 =126, DQ6 =144, DQ7 =142
7993 22:10:40.020961 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7994 22:10:40.024409 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7995 22:10:40.024506
7996 22:10:40.024571
7997 22:10:40.024631
7998 22:10:40.027925 [DramC_TX_OE_Calibration] TA2
7999 22:10:40.030934 Original DQ_B0 (3 6) =30, OEN = 27
8000 22:10:40.034177 Original DQ_B1 (3 6) =30, OEN = 27
8001 22:10:40.037469 24, 0x0, End_B0=24 End_B1=24
8002 22:10:40.037552 25, 0x0, End_B0=25 End_B1=25
8003 22:10:40.040767 26, 0x0, End_B0=26 End_B1=26
8004 22:10:40.044295 27, 0x0, End_B0=27 End_B1=27
8005 22:10:40.048068 28, 0x0, End_B0=28 End_B1=28
8006 22:10:40.051529 29, 0x0, End_B0=29 End_B1=29
8007 22:10:40.051612 30, 0x0, End_B0=30 End_B1=30
8008 22:10:40.054022 31, 0x4141, End_B0=30 End_B1=30
8009 22:10:40.057581 Byte0 end_step=30 best_step=27
8010 22:10:40.061032 Byte1 end_step=30 best_step=27
8011 22:10:40.064141 Byte0 TX OE(2T, 0.5T) = (3, 3)
8012 22:10:40.067270 Byte1 TX OE(2T, 0.5T) = (3, 3)
8013 22:10:40.067388
8014 22:10:40.067481
8015 22:10:40.074094 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8016 22:10:40.077454 CH0 RK0: MR19=303, MR18=1E1C
8017 22:10:40.084056 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
8018 22:10:40.084147
8019 22:10:40.087869 ----->DramcWriteLeveling(PI) begin...
8020 22:10:40.087952 ==
8021 22:10:40.090302 Dram Type= 6, Freq= 0, CH_0, rank 1
8022 22:10:40.094163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8023 22:10:40.094246 ==
8024 22:10:40.097370 Write leveling (Byte 0): 39 => 39
8025 22:10:40.100706 Write leveling (Byte 1): 30 => 30
8026 22:10:40.103874 DramcWriteLeveling(PI) end<-----
8027 22:10:40.103949
8028 22:10:40.104010 ==
8029 22:10:40.107504 Dram Type= 6, Freq= 0, CH_0, rank 1
8030 22:10:40.110557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 22:10:40.110627 ==
8032 22:10:40.113890 [Gating] SW mode calibration
8033 22:10:40.120422 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8034 22:10:40.127216 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8035 22:10:40.130284 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 22:10:40.137102 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 22:10:40.140440 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8038 22:10:40.143552 1 4 12 | B1->B0 | 2828 3030 | 1 1 | (1 1) (1 1)
8039 22:10:40.150130 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8040 22:10:40.153630 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 22:10:40.157021 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 22:10:40.160576 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 22:10:40.166721 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 22:10:40.170025 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 22:10:40.173381 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8046 22:10:40.180068 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
8047 22:10:40.183251 1 5 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
8048 22:10:40.187114 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 22:10:40.193193 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 22:10:40.196537 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 22:10:40.199820 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 22:10:40.206863 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 22:10:40.209747 1 6 8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
8054 22:10:40.213172 1 6 12 | B1->B0 | 2a2a 4242 | 0 0 | (0 0) (0 0)
8055 22:10:40.220255 1 6 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8056 22:10:40.223223 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 22:10:40.226139 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 22:10:40.232975 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 22:10:40.236353 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 22:10:40.239513 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 22:10:40.246350 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 22:10:40.249870 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8063 22:10:40.252790 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8064 22:10:40.259532 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 22:10:40.263017 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 22:10:40.266115 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 22:10:40.272924 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 22:10:40.276071 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 22:10:40.279245 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 22:10:40.286180 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 22:10:40.289212 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 22:10:40.292605 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 22:10:40.299440 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 22:10:40.302634 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 22:10:40.306017 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 22:10:40.312715 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 22:10:40.316318 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8078 22:10:40.319513 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8079 22:10:40.326151 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8080 22:10:40.329128 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 22:10:40.332516 Total UI for P1: 0, mck2ui 16
8082 22:10:40.336009 best dqsien dly found for B0: ( 1, 9, 12)
8083 22:10:40.339163 Total UI for P1: 0, mck2ui 16
8084 22:10:40.342576 best dqsien dly found for B1: ( 1, 9, 14)
8085 22:10:40.346123 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8086 22:10:40.349240 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8087 22:10:40.349367
8088 22:10:40.352570 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8089 22:10:40.356628 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8090 22:10:40.359455 [Gating] SW calibration Done
8091 22:10:40.359574 ==
8092 22:10:40.362448 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 22:10:40.366245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 22:10:40.366365 ==
8095 22:10:40.369390 RX Vref Scan: 0
8096 22:10:40.369508
8097 22:10:40.372551 RX Vref 0 -> 0, step: 1
8098 22:10:40.372670
8099 22:10:40.372829 RX Delay 0 -> 252, step: 8
8100 22:10:40.379036 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8101 22:10:40.382618 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8102 22:10:40.386057 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8103 22:10:40.389129 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8104 22:10:40.392513 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8105 22:10:40.399384 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8106 22:10:40.402328 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8107 22:10:40.406100 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8108 22:10:40.408963 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8109 22:10:40.412756 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8110 22:10:40.415990 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8111 22:10:40.422522 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8112 22:10:40.426026 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8113 22:10:40.429580 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8114 22:10:40.432871 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8115 22:10:40.439223 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8116 22:10:40.439304 ==
8117 22:10:40.442667 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 22:10:40.445878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 22:10:40.445960 ==
8120 22:10:40.446025 DQS Delay:
8121 22:10:40.449198 DQS0 = 0, DQS1 = 0
8122 22:10:40.449279 DQM Delay:
8123 22:10:40.452534 DQM0 = 136, DQM1 = 125
8124 22:10:40.452614 DQ Delay:
8125 22:10:40.455881 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8126 22:10:40.459349 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8127 22:10:40.462280 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8128 22:10:40.465611 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8129 22:10:40.465693
8130 22:10:40.465757
8131 22:10:40.469723 ==
8132 22:10:40.472361 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 22:10:40.475599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 22:10:40.475680 ==
8135 22:10:40.475745
8136 22:10:40.475803
8137 22:10:40.478807 TX Vref Scan disable
8138 22:10:40.478888 == TX Byte 0 ==
8139 22:10:40.482173 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8140 22:10:40.488741 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8141 22:10:40.488878 == TX Byte 1 ==
8142 22:10:40.492202 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8143 22:10:40.498818 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8144 22:10:40.498901 ==
8145 22:10:40.502132 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 22:10:40.505281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 22:10:40.505405 ==
8148 22:10:40.520957
8149 22:10:40.523913 TX Vref early break, caculate TX vref
8150 22:10:40.527737 TX Vref=16, minBit 8, minWin=23, winSum=389
8151 22:10:40.530705 TX Vref=18, minBit 11, minWin=23, winSum=396
8152 22:10:40.534010 TX Vref=20, minBit 4, minWin=24, winSum=404
8153 22:10:40.537683 TX Vref=22, minBit 8, minWin=24, winSum=417
8154 22:10:40.540978 TX Vref=24, minBit 0, minWin=25, winSum=420
8155 22:10:40.547234 TX Vref=26, minBit 8, minWin=25, winSum=429
8156 22:10:40.550867 TX Vref=28, minBit 0, minWin=26, winSum=432
8157 22:10:40.553930 TX Vref=30, minBit 0, minWin=26, winSum=428
8158 22:10:40.557234 TX Vref=32, minBit 13, minWin=25, winSum=420
8159 22:10:40.560660 TX Vref=34, minBit 3, minWin=25, winSum=412
8160 22:10:40.564058 TX Vref=36, minBit 4, minWin=24, winSum=401
8161 22:10:40.570977 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8162 22:10:40.571057
8163 22:10:40.573878 Final TX Range 0 Vref 28
8164 22:10:40.573954
8165 22:10:40.574015 ==
8166 22:10:40.577379 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 22:10:40.581125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 22:10:40.581199 ==
8169 22:10:40.581283
8170 22:10:40.581346
8171 22:10:40.584116 TX Vref Scan disable
8172 22:10:40.590779 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8173 22:10:40.590976 == TX Byte 0 ==
8174 22:10:40.593939 u2DelayCellOfst[0]=13 cells (4 PI)
8175 22:10:40.597309 u2DelayCellOfst[1]=20 cells (6 PI)
8176 22:10:40.600684 u2DelayCellOfst[2]=13 cells (4 PI)
8177 22:10:40.603779 u2DelayCellOfst[3]=13 cells (4 PI)
8178 22:10:40.607233 u2DelayCellOfst[4]=10 cells (3 PI)
8179 22:10:40.610761 u2DelayCellOfst[5]=0 cells (0 PI)
8180 22:10:40.614023 u2DelayCellOfst[6]=20 cells (6 PI)
8181 22:10:40.617456 u2DelayCellOfst[7]=16 cells (5 PI)
8182 22:10:40.620581 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8183 22:10:40.623937 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8184 22:10:40.627466 == TX Byte 1 ==
8185 22:10:40.630875 u2DelayCellOfst[8]=0 cells (0 PI)
8186 22:10:40.633877 u2DelayCellOfst[9]=0 cells (0 PI)
8187 22:10:40.633983 u2DelayCellOfst[10]=3 cells (1 PI)
8188 22:10:40.637153 u2DelayCellOfst[11]=0 cells (0 PI)
8189 22:10:40.640356 u2DelayCellOfst[12]=10 cells (3 PI)
8190 22:10:40.643884 u2DelayCellOfst[13]=6 cells (2 PI)
8191 22:10:40.646918 u2DelayCellOfst[14]=10 cells (3 PI)
8192 22:10:40.650319 u2DelayCellOfst[15]=6 cells (2 PI)
8193 22:10:40.653879 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8194 22:10:40.660464 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8195 22:10:40.660590 DramC Write-DBI on
8196 22:10:40.660684 ==
8197 22:10:40.664418 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 22:10:40.670291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 22:10:40.670375 ==
8200 22:10:40.670441
8201 22:10:40.670502
8202 22:10:40.670560 TX Vref Scan disable
8203 22:10:40.674537 == TX Byte 0 ==
8204 22:10:40.678194 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8205 22:10:40.681216 == TX Byte 1 ==
8206 22:10:40.684692 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8207 22:10:40.684814 DramC Write-DBI off
8208 22:10:40.688101
8209 22:10:40.688183 [DATLAT]
8210 22:10:40.688250 Freq=1600, CH0 RK1
8211 22:10:40.688311
8212 22:10:40.690874 DATLAT Default: 0xf
8213 22:10:40.690957 0, 0xFFFF, sum = 0
8214 22:10:40.694362 1, 0xFFFF, sum = 0
8215 22:10:40.694447 2, 0xFFFF, sum = 0
8216 22:10:40.697731 3, 0xFFFF, sum = 0
8217 22:10:40.700884 4, 0xFFFF, sum = 0
8218 22:10:40.700970 5, 0xFFFF, sum = 0
8219 22:10:40.704282 6, 0xFFFF, sum = 0
8220 22:10:40.704410 7, 0xFFFF, sum = 0
8221 22:10:40.707645 8, 0xFFFF, sum = 0
8222 22:10:40.707731 9, 0xFFFF, sum = 0
8223 22:10:40.711211 10, 0xFFFF, sum = 0
8224 22:10:40.711291 11, 0xFFFF, sum = 0
8225 22:10:40.714441 12, 0xFFFF, sum = 0
8226 22:10:40.714525 13, 0xFFFF, sum = 0
8227 22:10:40.718102 14, 0x0, sum = 1
8228 22:10:40.718187 15, 0x0, sum = 2
8229 22:10:40.721432 16, 0x0, sum = 3
8230 22:10:40.721517 17, 0x0, sum = 4
8231 22:10:40.724343 best_step = 15
8232 22:10:40.724428
8233 22:10:40.724495 ==
8234 22:10:40.728119 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 22:10:40.731288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 22:10:40.731396 ==
8237 22:10:40.731490 RX Vref Scan: 0
8238 22:10:40.731587
8239 22:10:40.734281 RX Vref 0 -> 0, step: 1
8240 22:10:40.734356
8241 22:10:40.737971 RX Delay 11 -> 252, step: 4
8242 22:10:40.741519 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8243 22:10:40.747545 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8244 22:10:40.751189 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8245 22:10:40.754098 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8246 22:10:40.757479 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8247 22:10:40.761198 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8248 22:10:40.767529 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8249 22:10:40.771038 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8250 22:10:40.774238 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8251 22:10:40.777293 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8252 22:10:40.780674 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8253 22:10:40.787333 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8254 22:10:40.791247 iDelay=191, Bit 12, Center 130 (79 ~ 182) 104
8255 22:10:40.794056 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8256 22:10:40.797308 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8257 22:10:40.800666 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8258 22:10:40.804179 ==
8259 22:10:40.807321 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 22:10:40.810730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 22:10:40.810804 ==
8262 22:10:40.810877 DQS Delay:
8263 22:10:40.814191 DQS0 = 0, DQS1 = 0
8264 22:10:40.814265 DQM Delay:
8265 22:10:40.817667 DQM0 = 133, DQM1 = 123
8266 22:10:40.817739 DQ Delay:
8267 22:10:40.820702 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =128
8268 22:10:40.824065 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8269 22:10:40.827353 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8270 22:10:40.830660 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =128
8271 22:10:40.830731
8272 22:10:40.830791
8273 22:10:40.830848
8274 22:10:40.833695 [DramC_TX_OE_Calibration] TA2
8275 22:10:40.836988 Original DQ_B0 (3 6) =30, OEN = 27
8276 22:10:40.840599 Original DQ_B1 (3 6) =30, OEN = 27
8277 22:10:40.843821 24, 0x0, End_B0=24 End_B1=24
8278 22:10:40.847182 25, 0x0, End_B0=25 End_B1=25
8279 22:10:40.847266 26, 0x0, End_B0=26 End_B1=26
8280 22:10:40.850284 27, 0x0, End_B0=27 End_B1=27
8281 22:10:40.853620 28, 0x0, End_B0=28 End_B1=28
8282 22:10:40.857207 29, 0x0, End_B0=29 End_B1=29
8283 22:10:40.860285 30, 0x0, End_B0=30 End_B1=30
8284 22:10:40.860369 31, 0x4141, End_B0=30 End_B1=30
8285 22:10:40.863636 Byte0 end_step=30 best_step=27
8286 22:10:40.867379 Byte1 end_step=30 best_step=27
8287 22:10:40.870653 Byte0 TX OE(2T, 0.5T) = (3, 3)
8288 22:10:40.873618 Byte1 TX OE(2T, 0.5T) = (3, 3)
8289 22:10:40.873701
8290 22:10:40.873767
8291 22:10:40.880591 [DQSOSCAuto] RK1, (LSB)MR18= 0x200e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8292 22:10:40.883763 CH0 RK1: MR19=303, MR18=200E
8293 22:10:40.890431 CH0_RK1: MR19=0x303, MR18=0x200E, DQSOSC=393, MR23=63, INC=23, DEC=15
8294 22:10:40.893761 [RxdqsGatingPostProcess] freq 1600
8295 22:10:40.896962 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8296 22:10:40.900550 best DQS0 dly(2T, 0.5T) = (1, 1)
8297 22:10:40.903952 best DQS1 dly(2T, 0.5T) = (1, 1)
8298 22:10:40.907251 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8299 22:10:40.910703 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8300 22:10:40.913615 best DQS0 dly(2T, 0.5T) = (1, 1)
8301 22:10:40.917060 best DQS1 dly(2T, 0.5T) = (1, 1)
8302 22:10:40.920505 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8303 22:10:40.923542 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8304 22:10:40.927112 Pre-setting of DQS Precalculation
8305 22:10:40.930358 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8306 22:10:40.930432 ==
8307 22:10:40.933428 Dram Type= 6, Freq= 0, CH_1, rank 0
8308 22:10:40.940369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 22:10:40.940500 ==
8310 22:10:40.943570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8311 22:10:40.950187 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8312 22:10:40.953483 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8313 22:10:40.960367 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8314 22:10:40.967502 [CA 0] Center 40 (11~70) winsize 60
8315 22:10:40.970868 [CA 1] Center 41 (11~71) winsize 61
8316 22:10:40.974241 [CA 2] Center 37 (8~66) winsize 59
8317 22:10:40.977450 [CA 3] Center 36 (7~66) winsize 60
8318 22:10:40.981069 [CA 4] Center 36 (7~66) winsize 60
8319 22:10:40.984081 [CA 5] Center 36 (6~66) winsize 61
8320 22:10:40.984203
8321 22:10:40.987473 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8322 22:10:40.987597
8323 22:10:40.990505 [CATrainingPosCal] consider 1 rank data
8324 22:10:40.994094 u2DelayCellTimex100 = 290/100 ps
8325 22:10:40.997389 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8326 22:10:41.003877 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8327 22:10:41.007308 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8328 22:10:41.010495 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8329 22:10:41.014182 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8330 22:10:41.017151 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8331 22:10:41.017273
8332 22:10:41.020477 CA PerBit enable=1, Macro0, CA PI delay=36
8333 22:10:41.020595
8334 22:10:41.023891 [CBTSetCACLKResult] CA Dly = 36
8335 22:10:41.027083 CS Dly: 8 (0~39)
8336 22:10:41.030374 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8337 22:10:41.033761 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8338 22:10:41.033844 ==
8339 22:10:41.037138 Dram Type= 6, Freq= 0, CH_1, rank 1
8340 22:10:41.040563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 22:10:41.043923 ==
8342 22:10:41.047186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8343 22:10:41.050393 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8344 22:10:41.057118 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8345 22:10:41.060556 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8346 22:10:41.070613 [CA 0] Center 42 (13~72) winsize 60
8347 22:10:41.073880 [CA 1] Center 41 (11~72) winsize 62
8348 22:10:41.077135 [CA 2] Center 37 (8~67) winsize 60
8349 22:10:41.080597 [CA 3] Center 37 (8~66) winsize 59
8350 22:10:41.083674 [CA 4] Center 37 (8~67) winsize 60
8351 22:10:41.087106 [CA 5] Center 36 (7~66) winsize 60
8352 22:10:41.087219
8353 22:10:41.090635 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8354 22:10:41.090715
8355 22:10:41.094441 [CATrainingPosCal] consider 2 rank data
8356 22:10:41.097208 u2DelayCellTimex100 = 290/100 ps
8357 22:10:41.100344 CA0 delay=41 (13~70),Diff = 5 PI (16 cell)
8358 22:10:41.107019 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8359 22:10:41.110659 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8360 22:10:41.113922 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8361 22:10:41.117110 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8362 22:10:41.120449 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8363 22:10:41.120544
8364 22:10:41.123969 CA PerBit enable=1, Macro0, CA PI delay=36
8365 22:10:41.124051
8366 22:10:41.126983 [CBTSetCACLKResult] CA Dly = 36
8367 22:10:41.127063 CS Dly: 9 (0~42)
8368 22:10:41.133724 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8369 22:10:41.137230 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8370 22:10:41.137316
8371 22:10:41.140505 ----->DramcWriteLeveling(PI) begin...
8372 22:10:41.140586 ==
8373 22:10:41.143825 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 22:10:41.147152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 22:10:41.147275 ==
8376 22:10:41.150420 Write leveling (Byte 0): 24 => 24
8377 22:10:41.154059 Write leveling (Byte 1): 29 => 29
8378 22:10:41.157384 DramcWriteLeveling(PI) end<-----
8379 22:10:41.157506
8380 22:10:41.157617 ==
8381 22:10:41.160542 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 22:10:41.167209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 22:10:41.167317 ==
8384 22:10:41.167384 [Gating] SW mode calibration
8385 22:10:41.176750 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8386 22:10:41.180723 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8387 22:10:41.183610 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 22:10:41.190335 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 22:10:41.193673 1 4 8 | B1->B0 | 3131 3131 | 0 1 | (0 0) (1 1)
8390 22:10:41.196761 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 22:10:41.203659 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 22:10:41.206719 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 22:10:41.210537 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 22:10:41.216623 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 22:10:41.220188 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 22:10:41.223718 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 22:10:41.229977 1 5 8 | B1->B0 | 2d2d 2727 | 0 0 | (0 0) (1 0)
8398 22:10:41.233340 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8399 22:10:41.236739 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 22:10:41.243154 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 22:10:41.246420 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 22:10:41.249750 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 22:10:41.256307 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 22:10:41.259808 1 6 4 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
8405 22:10:41.263290 1 6 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8406 22:10:41.269716 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 22:10:41.272994 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 22:10:41.276571 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 22:10:41.282950 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 22:10:41.286259 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 22:10:41.289641 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 22:10:41.296554 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8413 22:10:41.299847 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8414 22:10:41.302975 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8415 22:10:41.310023 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 22:10:41.313057 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 22:10:41.316426 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 22:10:41.323256 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 22:10:41.326435 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 22:10:41.329816 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 22:10:41.332941 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 22:10:41.339605 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 22:10:41.343018 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 22:10:41.346759 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 22:10:41.352997 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 22:10:41.356285 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 22:10:41.359698 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 22:10:41.366361 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8429 22:10:41.369764 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8430 22:10:41.373021 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8431 22:10:41.376356 Total UI for P1: 0, mck2ui 16
8432 22:10:41.379573 best dqsien dly found for B0: ( 1, 9, 6)
8433 22:10:41.386271 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 22:10:41.386353 Total UI for P1: 0, mck2ui 16
8435 22:10:41.393088 best dqsien dly found for B1: ( 1, 9, 10)
8436 22:10:41.396477 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8437 22:10:41.399889 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8438 22:10:41.399971
8439 22:10:41.402905 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8440 22:10:41.406310 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8441 22:10:41.409956 [Gating] SW calibration Done
8442 22:10:41.410038 ==
8443 22:10:41.412978 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 22:10:41.416470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 22:10:41.416566 ==
8446 22:10:41.419331 RX Vref Scan: 0
8447 22:10:41.419412
8448 22:10:41.419476 RX Vref 0 -> 0, step: 1
8449 22:10:41.419536
8450 22:10:41.422904 RX Delay 0 -> 252, step: 8
8451 22:10:41.426059 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8452 22:10:41.429404 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8453 22:10:41.436017 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8454 22:10:41.439821 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8455 22:10:41.442571 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8456 22:10:41.446844 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8457 22:10:41.449442 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8458 22:10:41.456106 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8459 22:10:41.459375 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8460 22:10:41.463158 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8461 22:10:41.466132 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8462 22:10:41.469493 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8463 22:10:41.476066 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8464 22:10:41.479560 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8465 22:10:41.482450 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8466 22:10:41.485828 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8467 22:10:41.485949 ==
8468 22:10:41.489466 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 22:10:41.495956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 22:10:41.496083 ==
8471 22:10:41.496194 DQS Delay:
8472 22:10:41.496304 DQS0 = 0, DQS1 = 0
8473 22:10:41.499407 DQM Delay:
8474 22:10:41.499522 DQM0 = 138, DQM1 = 130
8475 22:10:41.502436 DQ Delay:
8476 22:10:41.506129 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8477 22:10:41.509027 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8478 22:10:41.512431 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8479 22:10:41.515988 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8480 22:10:41.516105
8481 22:10:41.516215
8482 22:10:41.516320 ==
8483 22:10:41.519101 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 22:10:41.522396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 22:10:41.525820 ==
8486 22:10:41.525937
8487 22:10:41.526050
8488 22:10:41.526155 TX Vref Scan disable
8489 22:10:41.529206 == TX Byte 0 ==
8490 22:10:41.532613 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8491 22:10:41.535711 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8492 22:10:41.539103 == TX Byte 1 ==
8493 22:10:41.542602 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8494 22:10:41.545692 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8495 22:10:41.545816 ==
8496 22:10:41.549375 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 22:10:41.555593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 22:10:41.555728 ==
8499 22:10:41.567592
8500 22:10:41.570968 TX Vref early break, caculate TX vref
8501 22:10:41.574197 TX Vref=16, minBit 10, minWin=21, winSum=366
8502 22:10:41.578128 TX Vref=18, minBit 10, minWin=21, winSum=377
8503 22:10:41.581233 TX Vref=20, minBit 10, minWin=23, winSum=390
8504 22:10:41.584323 TX Vref=22, minBit 9, minWin=23, winSum=391
8505 22:10:41.587517 TX Vref=24, minBit 10, minWin=24, winSum=401
8506 22:10:41.594171 TX Vref=26, minBit 13, minWin=24, winSum=411
8507 22:10:41.597664 TX Vref=28, minBit 14, minWin=24, winSum=420
8508 22:10:41.600932 TX Vref=30, minBit 8, minWin=24, winSum=413
8509 22:10:41.604245 TX Vref=32, minBit 13, minWin=23, winSum=401
8510 22:10:41.608158 TX Vref=34, minBit 8, minWin=23, winSum=393
8511 22:10:41.614379 [TxChooseVref] Worse bit 14, Min win 24, Win sum 420, Final Vref 28
8512 22:10:41.614497
8513 22:10:41.617367 Final TX Range 0 Vref 28
8514 22:10:41.617468
8515 22:10:41.617559 ==
8516 22:10:41.620719 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 22:10:41.624454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 22:10:41.624562 ==
8519 22:10:41.624654
8520 22:10:41.624742
8521 22:10:41.627543 TX Vref Scan disable
8522 22:10:41.634681 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8523 22:10:41.634762 == TX Byte 0 ==
8524 22:10:41.637803 u2DelayCellOfst[0]=13 cells (4 PI)
8525 22:10:41.640827 u2DelayCellOfst[1]=10 cells (3 PI)
8526 22:10:41.644199 u2DelayCellOfst[2]=0 cells (0 PI)
8527 22:10:41.647512 u2DelayCellOfst[3]=6 cells (2 PI)
8528 22:10:41.650618 u2DelayCellOfst[4]=6 cells (2 PI)
8529 22:10:41.654019 u2DelayCellOfst[5]=16 cells (5 PI)
8530 22:10:41.657522 u2DelayCellOfst[6]=16 cells (5 PI)
8531 22:10:41.660686 u2DelayCellOfst[7]=6 cells (2 PI)
8532 22:10:41.664740 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8533 22:10:41.667388 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8534 22:10:41.670749 == TX Byte 1 ==
8535 22:10:41.670870 u2DelayCellOfst[8]=0 cells (0 PI)
8536 22:10:41.674164 u2DelayCellOfst[9]=3 cells (1 PI)
8537 22:10:41.677682 u2DelayCellOfst[10]=10 cells (3 PI)
8538 22:10:41.680830 u2DelayCellOfst[11]=3 cells (1 PI)
8539 22:10:41.684170 u2DelayCellOfst[12]=13 cells (4 PI)
8540 22:10:41.687654 u2DelayCellOfst[13]=16 cells (5 PI)
8541 22:10:41.691224 u2DelayCellOfst[14]=16 cells (5 PI)
8542 22:10:41.694676 u2DelayCellOfst[15]=16 cells (5 PI)
8543 22:10:41.697256 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8544 22:10:41.704024 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8545 22:10:41.704147 DramC Write-DBI on
8546 22:10:41.704254 ==
8547 22:10:41.707246 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 22:10:41.710698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 22:10:41.714028 ==
8550 22:10:41.714148
8551 22:10:41.714259
8552 22:10:41.714366 TX Vref Scan disable
8553 22:10:41.717732 == TX Byte 0 ==
8554 22:10:41.720871 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8555 22:10:41.724629 == TX Byte 1 ==
8556 22:10:41.727994 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8557 22:10:41.730689 DramC Write-DBI off
8558 22:10:41.730787
8559 22:10:41.730876 [DATLAT]
8560 22:10:41.730963 Freq=1600, CH1 RK0
8561 22:10:41.731049
8562 22:10:41.734099 DATLAT Default: 0xf
8563 22:10:41.734191 0, 0xFFFF, sum = 0
8564 22:10:41.737861 1, 0xFFFF, sum = 0
8565 22:10:41.737954 2, 0xFFFF, sum = 0
8566 22:10:41.740545 3, 0xFFFF, sum = 0
8567 22:10:41.744223 4, 0xFFFF, sum = 0
8568 22:10:41.744347 5, 0xFFFF, sum = 0
8569 22:10:41.747376 6, 0xFFFF, sum = 0
8570 22:10:41.747472 7, 0xFFFF, sum = 0
8571 22:10:41.750742 8, 0xFFFF, sum = 0
8572 22:10:41.750825 9, 0xFFFF, sum = 0
8573 22:10:41.754184 10, 0xFFFF, sum = 0
8574 22:10:41.754280 11, 0xFFFF, sum = 0
8575 22:10:41.757237 12, 0xFFFF, sum = 0
8576 22:10:41.757319 13, 0xFFFF, sum = 0
8577 22:10:41.760594 14, 0x0, sum = 1
8578 22:10:41.760677 15, 0x0, sum = 2
8579 22:10:41.764189 16, 0x0, sum = 3
8580 22:10:41.764272 17, 0x0, sum = 4
8581 22:10:41.767431 best_step = 15
8582 22:10:41.767512
8583 22:10:41.767604 ==
8584 22:10:41.770560 Dram Type= 6, Freq= 0, CH_1, rank 0
8585 22:10:41.773984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8586 22:10:41.774066 ==
8587 22:10:41.774130 RX Vref Scan: 1
8588 22:10:41.777468
8589 22:10:41.777549 Set Vref Range= 24 -> 127
8590 22:10:41.777614
8591 22:10:41.780492 RX Vref 24 -> 127, step: 1
8592 22:10:41.780573
8593 22:10:41.783849 RX Delay 19 -> 252, step: 4
8594 22:10:41.783931
8595 22:10:41.787465 Set Vref, RX VrefLevel [Byte0]: 24
8596 22:10:41.790685 [Byte1]: 24
8597 22:10:41.790766
8598 22:10:41.793663 Set Vref, RX VrefLevel [Byte0]: 25
8599 22:10:41.797123 [Byte1]: 25
8600 22:10:41.797245
8601 22:10:41.800583 Set Vref, RX VrefLevel [Byte0]: 26
8602 22:10:41.803806 [Byte1]: 26
8603 22:10:41.807861
8604 22:10:41.807979 Set Vref, RX VrefLevel [Byte0]: 27
8605 22:10:41.811055 [Byte1]: 27
8606 22:10:41.815321
8607 22:10:41.815438 Set Vref, RX VrefLevel [Byte0]: 28
8608 22:10:41.818903 [Byte1]: 28
8609 22:10:41.823163
8610 22:10:41.823287 Set Vref, RX VrefLevel [Byte0]: 29
8611 22:10:41.826465 [Byte1]: 29
8612 22:10:41.830775
8613 22:10:41.830892 Set Vref, RX VrefLevel [Byte0]: 30
8614 22:10:41.833755 [Byte1]: 30
8615 22:10:41.838085
8616 22:10:41.838204 Set Vref, RX VrefLevel [Byte0]: 31
8617 22:10:41.841579 [Byte1]: 31
8618 22:10:41.845688
8619 22:10:41.845807 Set Vref, RX VrefLevel [Byte0]: 32
8620 22:10:41.848963 [Byte1]: 32
8621 22:10:41.853109
8622 22:10:41.853228 Set Vref, RX VrefLevel [Byte0]: 33
8623 22:10:41.856540 [Byte1]: 33
8624 22:10:41.860650
8625 22:10:41.860780 Set Vref, RX VrefLevel [Byte0]: 34
8626 22:10:41.864097 [Byte1]: 34
8627 22:10:41.868501
8628 22:10:41.868604 Set Vref, RX VrefLevel [Byte0]: 35
8629 22:10:41.871725 [Byte1]: 35
8630 22:10:41.876061
8631 22:10:41.876162 Set Vref, RX VrefLevel [Byte0]: 36
8632 22:10:41.879262 [Byte1]: 36
8633 22:10:41.883517
8634 22:10:41.883616 Set Vref, RX VrefLevel [Byte0]: 37
8635 22:10:41.886873 [Byte1]: 37
8636 22:10:41.891575
8637 22:10:41.891674 Set Vref, RX VrefLevel [Byte0]: 38
8638 22:10:41.894297 [Byte1]: 38
8639 22:10:41.898639
8640 22:10:41.898744 Set Vref, RX VrefLevel [Byte0]: 39
8641 22:10:41.902244 [Byte1]: 39
8642 22:10:41.906170
8643 22:10:41.906253 Set Vref, RX VrefLevel [Byte0]: 40
8644 22:10:41.909432 [Byte1]: 40
8645 22:10:41.913981
8646 22:10:41.914062 Set Vref, RX VrefLevel [Byte0]: 41
8647 22:10:41.917010 [Byte1]: 41
8648 22:10:41.921302
8649 22:10:41.921383 Set Vref, RX VrefLevel [Byte0]: 42
8650 22:10:41.925440 [Byte1]: 42
8651 22:10:41.929027
8652 22:10:41.929108 Set Vref, RX VrefLevel [Byte0]: 43
8653 22:10:41.932442 [Byte1]: 43
8654 22:10:41.936534
8655 22:10:41.936615 Set Vref, RX VrefLevel [Byte0]: 44
8656 22:10:41.939770 [Byte1]: 44
8657 22:10:41.944098
8658 22:10:41.944180 Set Vref, RX VrefLevel [Byte0]: 45
8659 22:10:41.947220 [Byte1]: 45
8660 22:10:41.951529
8661 22:10:41.951610 Set Vref, RX VrefLevel [Byte0]: 46
8662 22:10:41.954999 [Byte1]: 46
8663 22:10:41.959199
8664 22:10:41.959281 Set Vref, RX VrefLevel [Byte0]: 47
8665 22:10:41.962673 [Byte1]: 47
8666 22:10:41.967187
8667 22:10:41.967269 Set Vref, RX VrefLevel [Byte0]: 48
8668 22:10:41.970093 [Byte1]: 48
8669 22:10:41.974353
8670 22:10:41.974435 Set Vref, RX VrefLevel [Byte0]: 49
8671 22:10:41.977802 [Byte1]: 49
8672 22:10:41.982013
8673 22:10:41.982095 Set Vref, RX VrefLevel [Byte0]: 50
8674 22:10:41.985097 [Byte1]: 50
8675 22:10:41.989725
8676 22:10:41.989806 Set Vref, RX VrefLevel [Byte0]: 51
8677 22:10:41.992804 [Byte1]: 51
8678 22:10:41.997079
8679 22:10:41.997160 Set Vref, RX VrefLevel [Byte0]: 52
8680 22:10:42.000561 [Byte1]: 52
8681 22:10:42.004870
8682 22:10:42.004951 Set Vref, RX VrefLevel [Byte0]: 53
8683 22:10:42.008126 [Byte1]: 53
8684 22:10:42.012088
8685 22:10:42.012170 Set Vref, RX VrefLevel [Byte0]: 54
8686 22:10:42.016015 [Byte1]: 54
8687 22:10:42.019679
8688 22:10:42.019765 Set Vref, RX VrefLevel [Byte0]: 55
8689 22:10:42.023810 [Byte1]: 55
8690 22:10:42.027214
8691 22:10:42.027336 Set Vref, RX VrefLevel [Byte0]: 56
8692 22:10:42.030556 [Byte1]: 56
8693 22:10:42.034800
8694 22:10:42.034883 Set Vref, RX VrefLevel [Byte0]: 57
8695 22:10:42.038256 [Byte1]: 57
8696 22:10:42.042874
8697 22:10:42.042956 Set Vref, RX VrefLevel [Byte0]: 58
8698 22:10:42.045857 [Byte1]: 58
8699 22:10:42.049937
8700 22:10:42.050020 Set Vref, RX VrefLevel [Byte0]: 59
8701 22:10:42.053288 [Byte1]: 59
8702 22:10:42.057953
8703 22:10:42.058035 Set Vref, RX VrefLevel [Byte0]: 60
8704 22:10:42.060999 [Byte1]: 60
8705 22:10:42.065362
8706 22:10:42.065443 Set Vref, RX VrefLevel [Byte0]: 61
8707 22:10:42.069009 [Byte1]: 61
8708 22:10:42.072942
8709 22:10:42.073023 Set Vref, RX VrefLevel [Byte0]: 62
8710 22:10:42.076208 [Byte1]: 62
8711 22:10:42.080627
8712 22:10:42.080710 Set Vref, RX VrefLevel [Byte0]: 63
8713 22:10:42.083827 [Byte1]: 63
8714 22:10:42.087985
8715 22:10:42.088067 Set Vref, RX VrefLevel [Byte0]: 64
8716 22:10:42.091090 [Byte1]: 64
8717 22:10:42.095460
8718 22:10:42.095542 Set Vref, RX VrefLevel [Byte0]: 65
8719 22:10:42.099459 [Byte1]: 65
8720 22:10:42.103233
8721 22:10:42.103319 Set Vref, RX VrefLevel [Byte0]: 66
8722 22:10:42.106501 [Byte1]: 66
8723 22:10:42.110946
8724 22:10:42.111038 Set Vref, RX VrefLevel [Byte0]: 67
8725 22:10:42.114037 [Byte1]: 67
8726 22:10:42.118369
8727 22:10:42.118470 Set Vref, RX VrefLevel [Byte0]: 68
8728 22:10:42.121591 [Byte1]: 68
8729 22:10:42.126274
8730 22:10:42.126446 Set Vref, RX VrefLevel [Byte0]: 69
8731 22:10:42.129022 [Byte1]: 69
8732 22:10:42.133400
8733 22:10:42.133484 Set Vref, RX VrefLevel [Byte0]: 70
8734 22:10:42.136867 [Byte1]: 70
8735 22:10:42.140722
8736 22:10:42.140841 Set Vref, RX VrefLevel [Byte0]: 71
8737 22:10:42.144463 [Byte1]: 71
8738 22:10:42.148530
8739 22:10:42.148612 Set Vref, RX VrefLevel [Byte0]: 72
8740 22:10:42.151727 [Byte1]: 72
8741 22:10:42.156360
8742 22:10:42.156526 Set Vref, RX VrefLevel [Byte0]: 73
8743 22:10:42.159215 [Byte1]: 73
8744 22:10:42.163728
8745 22:10:42.163810 Set Vref, RX VrefLevel [Byte0]: 74
8746 22:10:42.166991 [Byte1]: 74
8747 22:10:42.171228
8748 22:10:42.171309 Set Vref, RX VrefLevel [Byte0]: 75
8749 22:10:42.174868 [Byte1]: 75
8750 22:10:42.178719
8751 22:10:42.178835 Final RX Vref Byte 0 = 55 to rank0
8752 22:10:42.182112 Final RX Vref Byte 1 = 60 to rank0
8753 22:10:42.185529 Final RX Vref Byte 0 = 55 to rank1
8754 22:10:42.188927 Final RX Vref Byte 1 = 60 to rank1==
8755 22:10:42.192162 Dram Type= 6, Freq= 0, CH_1, rank 0
8756 22:10:42.199018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 22:10:42.199101 ==
8758 22:10:42.199167 DQS Delay:
8759 22:10:42.199227 DQS0 = 0, DQS1 = 0
8760 22:10:42.202207 DQM Delay:
8761 22:10:42.202288 DQM0 = 133, DQM1 = 128
8762 22:10:42.205356 DQ Delay:
8763 22:10:42.208789 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8764 22:10:42.212299 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8765 22:10:42.215918 DQ8 =116, DQ9 =116, DQ10 =132, DQ11 =122
8766 22:10:42.218674 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =136
8767 22:10:42.218756
8768 22:10:42.218821
8769 22:10:42.218881
8770 22:10:42.221962 [DramC_TX_OE_Calibration] TA2
8771 22:10:42.225160 Original DQ_B0 (3 6) =30, OEN = 27
8772 22:10:42.228899 Original DQ_B1 (3 6) =30, OEN = 27
8773 22:10:42.232266 24, 0x0, End_B0=24 End_B1=24
8774 22:10:42.232399 25, 0x0, End_B0=25 End_B1=25
8775 22:10:42.235437 26, 0x0, End_B0=26 End_B1=26
8776 22:10:42.238365 27, 0x0, End_B0=27 End_B1=27
8777 22:10:42.241762 28, 0x0, End_B0=28 End_B1=28
8778 22:10:42.245622 29, 0x0, End_B0=29 End_B1=29
8779 22:10:42.245732 30, 0x0, End_B0=30 End_B1=30
8780 22:10:42.248462 31, 0x4141, End_B0=30 End_B1=30
8781 22:10:42.251884 Byte0 end_step=30 best_step=27
8782 22:10:42.255382 Byte1 end_step=30 best_step=27
8783 22:10:42.258591 Byte0 TX OE(2T, 0.5T) = (3, 3)
8784 22:10:42.258674 Byte1 TX OE(2T, 0.5T) = (3, 3)
8785 22:10:42.261767
8786 22:10:42.261849
8787 22:10:42.268662 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b29, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8788 22:10:42.272261 CH1 RK0: MR19=303, MR18=1B29
8789 22:10:42.278839 CH1_RK0: MR19=0x303, MR18=0x1B29, DQSOSC=389, MR23=63, INC=24, DEC=16
8790 22:10:42.278923
8791 22:10:42.282155 ----->DramcWriteLeveling(PI) begin...
8792 22:10:42.282287 ==
8793 22:10:42.285039 Dram Type= 6, Freq= 0, CH_1, rank 1
8794 22:10:42.288774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 22:10:42.288879 ==
8796 22:10:42.291801 Write leveling (Byte 0): 25 => 25
8797 22:10:42.295306 Write leveling (Byte 1): 31 => 31
8798 22:10:42.298312 DramcWriteLeveling(PI) end<-----
8799 22:10:42.298394
8800 22:10:42.298460 ==
8801 22:10:42.301895 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 22:10:42.304916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 22:10:42.305036 ==
8804 22:10:42.308245 [Gating] SW mode calibration
8805 22:10:42.315234 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8806 22:10:42.322088 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8807 22:10:42.325242 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 22:10:42.328420 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 22:10:42.335458 1 4 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8810 22:10:42.338149 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
8811 22:10:42.341995 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 22:10:42.348203 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 22:10:42.352056 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 22:10:42.354934 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 22:10:42.361622 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 22:10:42.364778 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 22:10:42.368438 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (0 1) (1 0)
8818 22:10:42.374806 1 5 12 | B1->B0 | 2323 3131 | 0 1 | (1 0) (1 0)
8819 22:10:42.378243 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 22:10:42.381970 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 22:10:42.388477 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 22:10:42.391517 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 22:10:42.394805 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 22:10:42.401563 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8825 22:10:42.404786 1 6 8 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8826 22:10:42.407956 1 6 12 | B1->B0 | 4646 4141 | 0 0 | (0 0) (1 1)
8827 22:10:42.414845 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 22:10:42.417911 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 22:10:42.421225 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 22:10:42.428053 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 22:10:42.431352 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 22:10:42.434607 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 22:10:42.438117 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8834 22:10:42.444444 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8835 22:10:42.448191 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 22:10:42.451186 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 22:10:42.457943 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 22:10:42.461483 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 22:10:42.464646 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 22:10:42.471453 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 22:10:42.474789 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 22:10:42.478216 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 22:10:42.484944 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 22:10:42.488092 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 22:10:42.491541 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 22:10:42.498177 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 22:10:42.501794 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 22:10:42.505019 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 22:10:42.511375 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8850 22:10:42.514861 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 22:10:42.518113 Total UI for P1: 0, mck2ui 16
8852 22:10:42.521297 best dqsien dly found for B0: ( 1, 9, 10)
8853 22:10:42.524655 Total UI for P1: 0, mck2ui 16
8854 22:10:42.528239 best dqsien dly found for B1: ( 1, 9, 8)
8855 22:10:42.531218 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8856 22:10:42.534684 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8857 22:10:42.534765
8858 22:10:42.538557 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8859 22:10:42.541315 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8860 22:10:42.544441 [Gating] SW calibration Done
8861 22:10:42.544522 ==
8862 22:10:42.547883 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 22:10:42.551079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 22:10:42.551161 ==
8865 22:10:42.554585 RX Vref Scan: 0
8866 22:10:42.554665
8867 22:10:42.558212 RX Vref 0 -> 0, step: 1
8868 22:10:42.558293
8869 22:10:42.558357 RX Delay 0 -> 252, step: 8
8870 22:10:42.564876 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8871 22:10:42.567863 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8872 22:10:42.571472 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8873 22:10:42.574345 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8874 22:10:42.577801 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8875 22:10:42.584394 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8876 22:10:42.587651 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8877 22:10:42.591197 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8878 22:10:42.594689 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8879 22:10:42.598187 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8880 22:10:42.604603 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8881 22:10:42.607791 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8882 22:10:42.611149 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8883 22:10:42.614352 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8884 22:10:42.617878 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8885 22:10:42.624266 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8886 22:10:42.624349 ==
8887 22:10:42.627743 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 22:10:42.630847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 22:10:42.630929 ==
8890 22:10:42.630994 DQS Delay:
8891 22:10:42.634431 DQS0 = 0, DQS1 = 0
8892 22:10:42.634512 DQM Delay:
8893 22:10:42.637752 DQM0 = 136, DQM1 = 133
8894 22:10:42.637833 DQ Delay:
8895 22:10:42.640993 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8896 22:10:42.644193 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8897 22:10:42.647649 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8898 22:10:42.650864 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8899 22:10:42.650945
8900 22:10:42.654305
8901 22:10:42.654386 ==
8902 22:10:42.657904 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 22:10:42.660952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 22:10:42.661033 ==
8905 22:10:42.661097
8906 22:10:42.661155
8907 22:10:42.664090 TX Vref Scan disable
8908 22:10:42.664171 == TX Byte 0 ==
8909 22:10:42.667449 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8910 22:10:42.674201 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8911 22:10:42.674282 == TX Byte 1 ==
8912 22:10:42.677554 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8913 22:10:42.684094 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8914 22:10:42.684179 ==
8915 22:10:42.687688 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 22:10:42.690798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 22:10:42.690883 ==
8918 22:10:42.704448
8919 22:10:42.707827 TX Vref early break, caculate TX vref
8920 22:10:42.711043 TX Vref=16, minBit 9, minWin=21, winSum=377
8921 22:10:42.714183 TX Vref=18, minBit 11, minWin=22, winSum=390
8922 22:10:42.717748 TX Vref=20, minBit 8, minWin=23, winSum=400
8923 22:10:42.720780 TX Vref=22, minBit 9, minWin=22, winSum=407
8924 22:10:42.724264 TX Vref=24, minBit 9, minWin=24, winSum=415
8925 22:10:42.730979 TX Vref=26, minBit 8, minWin=24, winSum=418
8926 22:10:42.734085 TX Vref=28, minBit 15, minWin=24, winSum=416
8927 22:10:42.737764 TX Vref=30, minBit 10, minWin=24, winSum=416
8928 22:10:42.740739 TX Vref=32, minBit 8, minWin=23, winSum=401
8929 22:10:42.744133 TX Vref=34, minBit 8, minWin=23, winSum=394
8930 22:10:42.751126 [TxChooseVref] Worse bit 8, Min win 24, Win sum 418, Final Vref 26
8931 22:10:42.751212
8932 22:10:42.754121 Final TX Range 0 Vref 26
8933 22:10:42.754206
8934 22:10:42.754290 ==
8935 22:10:42.757512 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 22:10:42.760890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 22:10:42.760976 ==
8938 22:10:42.761060
8939 22:10:42.761139
8940 22:10:42.764281 TX Vref Scan disable
8941 22:10:42.770771 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8942 22:10:42.770854 == TX Byte 0 ==
8943 22:10:42.774486 u2DelayCellOfst[0]=16 cells (5 PI)
8944 22:10:42.777272 u2DelayCellOfst[1]=13 cells (4 PI)
8945 22:10:42.780715 u2DelayCellOfst[2]=0 cells (0 PI)
8946 22:10:42.783895 u2DelayCellOfst[3]=6 cells (2 PI)
8947 22:10:42.787167 u2DelayCellOfst[4]=10 cells (3 PI)
8948 22:10:42.790693 u2DelayCellOfst[5]=20 cells (6 PI)
8949 22:10:42.793943 u2DelayCellOfst[6]=20 cells (6 PI)
8950 22:10:42.797426 u2DelayCellOfst[7]=6 cells (2 PI)
8951 22:10:42.800416 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8952 22:10:42.803993 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8953 22:10:42.807654 == TX Byte 1 ==
8954 22:10:42.807737 u2DelayCellOfst[8]=0 cells (0 PI)
8955 22:10:42.810576 u2DelayCellOfst[9]=3 cells (1 PI)
8956 22:10:42.813808 u2DelayCellOfst[10]=10 cells (3 PI)
8957 22:10:42.817098 u2DelayCellOfst[11]=3 cells (1 PI)
8958 22:10:42.820801 u2DelayCellOfst[12]=13 cells (4 PI)
8959 22:10:42.823857 u2DelayCellOfst[13]=16 cells (5 PI)
8960 22:10:42.827295 u2DelayCellOfst[14]=16 cells (5 PI)
8961 22:10:42.830702 u2DelayCellOfst[15]=16 cells (5 PI)
8962 22:10:42.833993 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8963 22:10:42.840673 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8964 22:10:42.840822 DramC Write-DBI on
8965 22:10:42.840907 ==
8966 22:10:42.844154 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 22:10:42.847243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 22:10:42.850501 ==
8969 22:10:42.850586
8970 22:10:42.850671
8971 22:10:42.850750 TX Vref Scan disable
8972 22:10:42.853968 == TX Byte 0 ==
8973 22:10:42.857201 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8974 22:10:42.860572 == TX Byte 1 ==
8975 22:10:42.864051 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8976 22:10:42.867584 DramC Write-DBI off
8977 22:10:42.867668
8978 22:10:42.867753 [DATLAT]
8979 22:10:42.867833 Freq=1600, CH1 RK1
8980 22:10:42.867912
8981 22:10:42.870550 DATLAT Default: 0xf
8982 22:10:42.870649 0, 0xFFFF, sum = 0
8983 22:10:42.874235 1, 0xFFFF, sum = 0
8984 22:10:42.874321 2, 0xFFFF, sum = 0
8985 22:10:42.877105 3, 0xFFFF, sum = 0
8986 22:10:42.880670 4, 0xFFFF, sum = 0
8987 22:10:42.880763 5, 0xFFFF, sum = 0
8988 22:10:42.884028 6, 0xFFFF, sum = 0
8989 22:10:42.884114 7, 0xFFFF, sum = 0
8990 22:10:42.887257 8, 0xFFFF, sum = 0
8991 22:10:42.887343 9, 0xFFFF, sum = 0
8992 22:10:42.890586 10, 0xFFFF, sum = 0
8993 22:10:42.890672 11, 0xFFFF, sum = 0
8994 22:10:42.894049 12, 0xFFFF, sum = 0
8995 22:10:42.894135 13, 0xFFFF, sum = 0
8996 22:10:42.897104 14, 0x0, sum = 1
8997 22:10:42.897190 15, 0x0, sum = 2
8998 22:10:42.900556 16, 0x0, sum = 3
8999 22:10:42.900642 17, 0x0, sum = 4
9000 22:10:42.903773 best_step = 15
9001 22:10:42.903857
9002 22:10:42.903941 ==
9003 22:10:42.907284 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 22:10:42.910347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 22:10:42.910433 ==
9006 22:10:42.913995 RX Vref Scan: 0
9007 22:10:42.914079
9008 22:10:42.914164 RX Vref 0 -> 0, step: 1
9009 22:10:42.914244
9010 22:10:42.917107 RX Delay 19 -> 252, step: 4
9011 22:10:42.920465 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9012 22:10:42.927041 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9013 22:10:42.930293 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9014 22:10:42.933722 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9015 22:10:42.937224 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9016 22:10:42.940653 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9017 22:10:42.943864 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9018 22:10:42.950439 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9019 22:10:42.954298 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9020 22:10:42.956881 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9021 22:10:42.960295 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9022 22:10:42.963669 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9023 22:10:42.970267 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9024 22:10:42.973458 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9025 22:10:42.977094 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9026 22:10:42.980226 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9027 22:10:42.980307 ==
9028 22:10:42.983582 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 22:10:42.990082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 22:10:42.990164 ==
9031 22:10:42.990228 DQS Delay:
9032 22:10:42.993506 DQS0 = 0, DQS1 = 0
9033 22:10:42.993587 DQM Delay:
9034 22:10:42.993652 DQM0 = 133, DQM1 = 129
9035 22:10:42.996760 DQ Delay:
9036 22:10:43.000035 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9037 22:10:43.003291 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9038 22:10:43.006859 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9039 22:10:43.010256 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =140
9040 22:10:43.010340
9041 22:10:43.010408
9042 22:10:43.010473
9043 22:10:43.013719 [DramC_TX_OE_Calibration] TA2
9044 22:10:43.016611 Original DQ_B0 (3 6) =30, OEN = 27
9045 22:10:43.020041 Original DQ_B1 (3 6) =30, OEN = 27
9046 22:10:43.023463 24, 0x0, End_B0=24 End_B1=24
9047 22:10:43.023546 25, 0x0, End_B0=25 End_B1=25
9048 22:10:43.026752 26, 0x0, End_B0=26 End_B1=26
9049 22:10:43.030079 27, 0x0, End_B0=27 End_B1=27
9050 22:10:43.033505 28, 0x0, End_B0=28 End_B1=28
9051 22:10:43.036964 29, 0x0, End_B0=29 End_B1=29
9052 22:10:43.037063 30, 0x0, End_B0=30 End_B1=30
9053 22:10:43.039868 31, 0x4141, End_B0=30 End_B1=30
9054 22:10:43.043392 Byte0 end_step=30 best_step=27
9055 22:10:43.046426 Byte1 end_step=30 best_step=27
9056 22:10:43.050211 Byte0 TX OE(2T, 0.5T) = (3, 3)
9057 22:10:43.053247 Byte1 TX OE(2T, 0.5T) = (3, 3)
9058 22:10:43.053329
9059 22:10:43.053392
9060 22:10:43.059766 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9061 22:10:43.063158 CH1 RK1: MR19=303, MR18=1D07
9062 22:10:43.070369 CH1_RK1: MR19=0x303, MR18=0x1D07, DQSOSC=395, MR23=63, INC=23, DEC=15
9063 22:10:43.073153 [RxdqsGatingPostProcess] freq 1600
9064 22:10:43.076741 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9065 22:10:43.079994 best DQS0 dly(2T, 0.5T) = (1, 1)
9066 22:10:43.083095 best DQS1 dly(2T, 0.5T) = (1, 1)
9067 22:10:43.086575 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9068 22:10:43.090130 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9069 22:10:43.093069 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 22:10:43.096367 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 22:10:43.099830 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 22:10:43.102925 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 22:10:43.106599 Pre-setting of DQS Precalculation
9074 22:10:43.109763 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9075 22:10:43.116335 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9076 22:10:43.126282 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9077 22:10:43.126390
9078 22:10:43.126482
9079 22:10:43.126570 [Calibration Summary] 3200 Mbps
9080 22:10:43.129598 CH 0, Rank 0
9081 22:10:43.129678 SW Impedance : PASS
9082 22:10:43.133015 DUTY Scan : NO K
9083 22:10:43.136181 ZQ Calibration : PASS
9084 22:10:43.136262 Jitter Meter : NO K
9085 22:10:43.139397 CBT Training : PASS
9086 22:10:43.143134 Write leveling : PASS
9087 22:10:43.143215 RX DQS gating : PASS
9088 22:10:43.146105 RX DQ/DQS(RDDQC) : PASS
9089 22:10:43.149893 TX DQ/DQS : PASS
9090 22:10:43.149974 RX DATLAT : PASS
9091 22:10:43.152932 RX DQ/DQS(Engine): PASS
9092 22:10:43.156113 TX OE : PASS
9093 22:10:43.156194 All Pass.
9094 22:10:43.156262
9095 22:10:43.156322 CH 0, Rank 1
9096 22:10:43.159545 SW Impedance : PASS
9097 22:10:43.162996 DUTY Scan : NO K
9098 22:10:43.163077 ZQ Calibration : PASS
9099 22:10:43.166003 Jitter Meter : NO K
9100 22:10:43.169427 CBT Training : PASS
9101 22:10:43.169509 Write leveling : PASS
9102 22:10:43.173000 RX DQS gating : PASS
9103 22:10:43.173082 RX DQ/DQS(RDDQC) : PASS
9104 22:10:43.176098 TX DQ/DQS : PASS
9105 22:10:43.179411 RX DATLAT : PASS
9106 22:10:43.179492 RX DQ/DQS(Engine): PASS
9107 22:10:43.182829 TX OE : PASS
9108 22:10:43.182911 All Pass.
9109 22:10:43.182974
9110 22:10:43.186661 CH 1, Rank 0
9111 22:10:43.186742 SW Impedance : PASS
9112 22:10:43.189555 DUTY Scan : NO K
9113 22:10:43.192588 ZQ Calibration : PASS
9114 22:10:43.192668 Jitter Meter : NO K
9115 22:10:43.195927 CBT Training : PASS
9116 22:10:43.199445 Write leveling : PASS
9117 22:10:43.199526 RX DQS gating : PASS
9118 22:10:43.203087 RX DQ/DQS(RDDQC) : PASS
9119 22:10:43.205918 TX DQ/DQS : PASS
9120 22:10:43.205999 RX DATLAT : PASS
9121 22:10:43.209177 RX DQ/DQS(Engine): PASS
9122 22:10:43.212710 TX OE : PASS
9123 22:10:43.212797 All Pass.
9124 22:10:43.212861
9125 22:10:43.212920 CH 1, Rank 1
9126 22:10:43.215808 SW Impedance : PASS
9127 22:10:43.219333 DUTY Scan : NO K
9128 22:10:43.219415 ZQ Calibration : PASS
9129 22:10:43.222670 Jitter Meter : NO K
9130 22:10:43.226039 CBT Training : PASS
9131 22:10:43.226120 Write leveling : PASS
9132 22:10:43.229277 RX DQS gating : PASS
9133 22:10:43.229358 RX DQ/DQS(RDDQC) : PASS
9134 22:10:43.232900 TX DQ/DQS : PASS
9135 22:10:43.236212 RX DATLAT : PASS
9136 22:10:43.236293 RX DQ/DQS(Engine): PASS
9137 22:10:43.239752 TX OE : PASS
9138 22:10:43.239834 All Pass.
9139 22:10:43.239898
9140 22:10:43.242656 DramC Write-DBI on
9141 22:10:43.245879 PER_BANK_REFRESH: Hybrid Mode
9142 22:10:43.245960 TX_TRACKING: ON
9143 22:10:43.256047 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9144 22:10:43.262658 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9145 22:10:43.269212 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9146 22:10:43.272633 [FAST_K] Save calibration result to emmc
9147 22:10:43.275806 sync common calibartion params.
9148 22:10:43.279490 sync cbt_mode0:1, 1:1
9149 22:10:43.282570 dram_init: ddr_geometry: 2
9150 22:10:43.282652 dram_init: ddr_geometry: 2
9151 22:10:43.286561 dram_init: ddr_geometry: 2
9152 22:10:43.289456 0:dram_rank_size:100000000
9153 22:10:43.292621 1:dram_rank_size:100000000
9154 22:10:43.296091 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9155 22:10:43.299682 DFS_SHUFFLE_HW_MODE: ON
9156 22:10:43.302651 dramc_set_vcore_voltage set vcore to 725000
9157 22:10:43.306414 Read voltage for 1600, 0
9158 22:10:43.306495 Vio18 = 0
9159 22:10:43.306559 Vcore = 725000
9160 22:10:43.309586 Vdram = 0
9161 22:10:43.309667 Vddq = 0
9162 22:10:43.309731 Vmddr = 0
9163 22:10:43.312623 switch to 3200 Mbps bootup
9164 22:10:43.316080 [DramcRunTimeConfig]
9165 22:10:43.316161 PHYPLL
9166 22:10:43.316225 DPM_CONTROL_AFTERK: ON
9167 22:10:43.319325 PER_BANK_REFRESH: ON
9168 22:10:43.323311 REFRESH_OVERHEAD_REDUCTION: ON
9169 22:10:43.323392 CMD_PICG_NEW_MODE: OFF
9170 22:10:43.326062 XRTWTW_NEW_MODE: ON
9171 22:10:43.326143 XRTRTR_NEW_MODE: ON
9172 22:10:43.329306 TX_TRACKING: ON
9173 22:10:43.329388 RDSEL_TRACKING: OFF
9174 22:10:43.332440 DQS Precalculation for DVFS: ON
9175 22:10:43.335731 RX_TRACKING: OFF
9176 22:10:43.335812 HW_GATING DBG: ON
9177 22:10:43.339153 ZQCS_ENABLE_LP4: ON
9178 22:10:43.339234 RX_PICG_NEW_MODE: ON
9179 22:10:43.342502 TX_PICG_NEW_MODE: ON
9180 22:10:43.345587 ENABLE_RX_DCM_DPHY: ON
9181 22:10:43.349294 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9182 22:10:43.349375 DUMMY_READ_FOR_TRACKING: OFF
9183 22:10:43.352293 !!! SPM_CONTROL_AFTERK: OFF
9184 22:10:43.355536 !!! SPM could not control APHY
9185 22:10:43.355637 IMPEDANCE_TRACKING: ON
9186 22:10:43.359041 TEMP_SENSOR: ON
9187 22:10:43.359147 HW_SAVE_FOR_SR: OFF
9188 22:10:43.362353 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9189 22:10:43.369194 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9190 22:10:43.369276 Read ODT Tracking: ON
9191 22:10:43.372232 Refresh Rate DeBounce: ON
9192 22:10:43.372313 DFS_NO_QUEUE_FLUSH: ON
9193 22:10:43.375588 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9194 22:10:43.379164 ENABLE_DFS_RUNTIME_MRW: OFF
9195 22:10:43.382517 DDR_RESERVE_NEW_MODE: ON
9196 22:10:43.382598 MR_CBT_SWITCH_FREQ: ON
9197 22:10:43.385915 =========================
9198 22:10:43.404912 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9199 22:10:43.408435 dram_init: ddr_geometry: 2
9200 22:10:43.426241 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9201 22:10:43.429790 dram_init: dram init end (result: 0)
9202 22:10:43.436418 DRAM-K: Full calibration passed in 24493 msecs
9203 22:10:43.439625 MRC: failed to locate region type 0.
9204 22:10:43.439706 DRAM rank0 size:0x100000000,
9205 22:10:43.443202 DRAM rank1 size=0x100000000
9206 22:10:43.452720 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9207 22:10:43.459867 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9208 22:10:43.466045 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9209 22:10:43.473048 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9210 22:10:43.476328 DRAM rank0 size:0x100000000,
9211 22:10:43.479462 DRAM rank1 size=0x100000000
9212 22:10:43.479585 CBMEM:
9213 22:10:43.483090 IMD: root @ 0xfffff000 254 entries.
9214 22:10:43.486033 IMD: root @ 0xffffec00 62 entries.
9215 22:10:43.489461 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9216 22:10:43.493027 WARNING: RO_VPD is uninitialized or empty.
9217 22:10:43.499189 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9218 22:10:43.506915 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9219 22:10:43.519426 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9220 22:10:43.530550 BS: romstage times (exec / console): total (unknown) / 23988 ms
9221 22:10:43.530673
9222 22:10:43.530787
9223 22:10:43.540615 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9224 22:10:43.544104 ARM64: Exception handlers installed.
9225 22:10:43.547331 ARM64: Testing exception
9226 22:10:43.550804 ARM64: Done test exception
9227 22:10:43.550886 Enumerating buses...
9228 22:10:43.553750 Show all devs... Before device enumeration.
9229 22:10:43.557274 Root Device: enabled 1
9230 22:10:43.560351 CPU_CLUSTER: 0: enabled 1
9231 22:10:43.560433 CPU: 00: enabled 1
9232 22:10:43.563638 Compare with tree...
9233 22:10:43.563720 Root Device: enabled 1
9234 22:10:43.567016 CPU_CLUSTER: 0: enabled 1
9235 22:10:43.570450 CPU: 00: enabled 1
9236 22:10:43.570531 Root Device scanning...
9237 22:10:43.573746 scan_static_bus for Root Device
9238 22:10:43.577068 CPU_CLUSTER: 0 enabled
9239 22:10:43.580320 scan_static_bus for Root Device done
9240 22:10:43.583621 scan_bus: bus Root Device finished in 8 msecs
9241 22:10:43.583703 done
9242 22:10:43.590252 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9243 22:10:43.593824 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9244 22:10:43.600166 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9245 22:10:43.603734 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9246 22:10:43.606871 Allocating resources...
9247 22:10:43.610358 Reading resources...
9248 22:10:43.613694 Root Device read_resources bus 0 link: 0
9249 22:10:43.613775 DRAM rank0 size:0x100000000,
9250 22:10:43.617163 DRAM rank1 size=0x100000000
9251 22:10:43.620952 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9252 22:10:43.623530 CPU: 00 missing read_resources
9253 22:10:43.626948 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9254 22:10:43.633654 Root Device read_resources bus 0 link: 0 done
9255 22:10:43.633735 Done reading resources.
9256 22:10:43.640565 Show resources in subtree (Root Device)...After reading.
9257 22:10:43.643788 Root Device child on link 0 CPU_CLUSTER: 0
9258 22:10:43.646797 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 22:10:43.656718 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 22:10:43.656852 CPU: 00
9261 22:10:43.660351 Root Device assign_resources, bus 0 link: 0
9262 22:10:43.663609 CPU_CLUSTER: 0 missing set_resources
9263 22:10:43.666711 Root Device assign_resources, bus 0 link: 0 done
9264 22:10:43.670053 Done setting resources.
9265 22:10:43.677465 Show resources in subtree (Root Device)...After assigning values.
9266 22:10:43.679879 Root Device child on link 0 CPU_CLUSTER: 0
9267 22:10:43.683022 CPU_CLUSTER: 0 child on link 0 CPU: 00
9268 22:10:43.692952 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9269 22:10:43.693036 CPU: 00
9270 22:10:43.696538 Done allocating resources.
9271 22:10:43.699817 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9272 22:10:43.703115 Enabling resources...
9273 22:10:43.703197 done.
9274 22:10:43.709820 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9275 22:10:43.709903 Initializing devices...
9276 22:10:43.713352 Root Device init
9277 22:10:43.713433 init hardware done!
9278 22:10:43.716160 0x00000018: ctrlr->caps
9279 22:10:43.719757 52.000 MHz: ctrlr->f_max
9280 22:10:43.719842 0.400 MHz: ctrlr->f_min
9281 22:10:43.723416 0x40ff8080: ctrlr->voltages
9282 22:10:43.723500 sclk: 390625
9283 22:10:43.726478 Bus Width = 1
9284 22:10:43.726579 sclk: 390625
9285 22:10:43.729779 Bus Width = 1
9286 22:10:43.729860 Early init status = 3
9287 22:10:43.736408 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9288 22:10:43.739513 in-header: 03 fc 00 00 01 00 00 00
9289 22:10:43.742833 in-data: 00
9290 22:10:43.746024 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9291 22:10:43.751676 in-header: 03 fd 00 00 00 00 00 00
9292 22:10:43.754775 in-data:
9293 22:10:43.757881 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9294 22:10:43.762485 in-header: 03 fc 00 00 01 00 00 00
9295 22:10:43.765697 in-data: 00
9296 22:10:43.768720 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9297 22:10:43.774750 in-header: 03 fd 00 00 00 00 00 00
9298 22:10:43.777990 in-data:
9299 22:10:43.781345 [SSUSB] Setting up USB HOST controller...
9300 22:10:43.784638 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9301 22:10:43.788211 [SSUSB] phy power-on done.
9302 22:10:43.791451 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9303 22:10:43.797950 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9304 22:10:43.801188 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9305 22:10:43.808051 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9306 22:10:43.815221 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9307 22:10:43.821340 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9308 22:10:43.827795 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9309 22:10:43.834521 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9310 22:10:43.837892 SPM: binary array size = 0x9dc
9311 22:10:43.841133 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9312 22:10:43.847760 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9313 22:10:43.854686 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9314 22:10:43.857970 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9315 22:10:43.861255 configure_display: Starting display init
9316 22:10:43.898226 anx7625_power_on_init: Init interface.
9317 22:10:43.901096 anx7625_disable_pd_protocol: Disabled PD feature.
9318 22:10:43.904625 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9319 22:10:43.932299 anx7625_start_dp_work: Secure OCM version=00
9320 22:10:43.935666 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9321 22:10:43.950698 sp_tx_get_edid_block: EDID Block = 1
9322 22:10:44.052808 Extracted contents:
9323 22:10:44.056315 header: 00 ff ff ff ff ff ff 00
9324 22:10:44.059770 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9325 22:10:44.063881 version: 01 04
9326 22:10:44.066348 basic params: 95 1f 11 78 0a
9327 22:10:44.069684 chroma info: 76 90 94 55 54 90 27 21 50 54
9328 22:10:44.072655 established: 00 00 00
9329 22:10:44.079380 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9330 22:10:44.082488 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9331 22:10:44.089316 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9332 22:10:44.095979 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9333 22:10:44.102551 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9334 22:10:44.105979 extensions: 00
9335 22:10:44.106061 checksum: fb
9336 22:10:44.106127
9337 22:10:44.109409 Manufacturer: IVO Model 57d Serial Number 0
9338 22:10:44.112209 Made week 0 of 2020
9339 22:10:44.115545 EDID version: 1.4
9340 22:10:44.115633 Digital display
9341 22:10:44.119143 6 bits per primary color channel
9342 22:10:44.119228 DisplayPort interface
9343 22:10:44.122363 Maximum image size: 31 cm x 17 cm
9344 22:10:44.125567 Gamma: 220%
9345 22:10:44.125650 Check DPMS levels
9346 22:10:44.129384 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9347 22:10:44.135545 First detailed timing is preferred timing
9348 22:10:44.135709 Established timings supported:
9349 22:10:44.138878 Standard timings supported:
9350 22:10:44.142017 Detailed timings
9351 22:10:44.145574 Hex of detail: 383680a07038204018303c0035ae10000019
9352 22:10:44.152176 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9353 22:10:44.155229 0780 0798 07c8 0820 hborder 0
9354 22:10:44.158659 0438 043b 0447 0458 vborder 0
9355 22:10:44.162221 -hsync -vsync
9356 22:10:44.162341 Did detailed timing
9357 22:10:44.168522 Hex of detail: 000000000000000000000000000000000000
9358 22:10:44.172119 Manufacturer-specified data, tag 0
9359 22:10:44.175148 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9360 22:10:44.179050 ASCII string: InfoVision
9361 22:10:44.182119 Hex of detail: 000000fe00523134304e574635205248200a
9362 22:10:44.185397 ASCII string: R140NWF5 RH
9363 22:10:44.185476 Checksum
9364 22:10:44.188498 Checksum: 0xfb (valid)
9365 22:10:44.192269 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9366 22:10:44.195412 DSI data_rate: 832800000 bps
9367 22:10:44.202178 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9368 22:10:44.205301 anx7625_parse_edid: pixelclock(138800).
9369 22:10:44.208775 hactive(1920), hsync(48), hfp(24), hbp(88)
9370 22:10:44.211971 vactive(1080), vsync(12), vfp(3), vbp(17)
9371 22:10:44.215516 anx7625_dsi_config: config dsi.
9372 22:10:44.221958 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9373 22:10:44.234914 anx7625_dsi_config: success to config DSI
9374 22:10:44.238311 anx7625_dp_start: MIPI phy setup OK.
9375 22:10:44.241650 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9376 22:10:44.244842 mtk_ddp_mode_set invalid vrefresh 60
9377 22:10:44.248481 main_disp_path_setup
9378 22:10:44.248600 ovl_layer_smi_id_en
9379 22:10:44.251759 ovl_layer_smi_id_en
9380 22:10:44.251879 ccorr_config
9381 22:10:44.251988 aal_config
9382 22:10:44.255115 gamma_config
9383 22:10:44.255234 postmask_config
9384 22:10:44.258557 dither_config
9385 22:10:44.261604 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9386 22:10:44.268535 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9387 22:10:44.271540 Root Device init finished in 555 msecs
9388 22:10:44.274847 CPU_CLUSTER: 0 init
9389 22:10:44.281819 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9390 22:10:44.284666 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9391 22:10:44.288002 APU_MBOX 0x190000b0 = 0x10001
9392 22:10:44.291704 APU_MBOX 0x190001b0 = 0x10001
9393 22:10:44.294894 APU_MBOX 0x190005b0 = 0x10001
9394 22:10:44.298202 APU_MBOX 0x190006b0 = 0x10001
9395 22:10:44.301242 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9396 22:10:44.313986 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9397 22:10:44.326198 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9398 22:10:44.332737 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9399 22:10:44.344599 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9400 22:10:44.353814 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9401 22:10:44.357197 CPU_CLUSTER: 0 init finished in 81 msecs
9402 22:10:44.360956 Devices initialized
9403 22:10:44.363604 Show all devs... After init.
9404 22:10:44.363726 Root Device: enabled 1
9405 22:10:44.366984 CPU_CLUSTER: 0: enabled 1
9406 22:10:44.370446 CPU: 00: enabled 1
9407 22:10:44.373820 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9408 22:10:44.376919 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9409 22:10:44.380525 ELOG: NV offset 0x57f000 size 0x1000
9410 22:10:44.386980 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9411 22:10:44.393701 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9412 22:10:44.397017 ELOG: Event(17) added with size 13 at 2023-09-05 22:10:41 UTC
9413 22:10:44.400376 out: cmd=0x121: 03 db 21 01 00 00 00 00
9414 22:10:44.404355 in-header: 03 3a 00 00 2c 00 00 00
9415 22:10:44.417271 in-data: 25 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9416 22:10:44.423784 ELOG: Event(A1) added with size 10 at 2023-09-05 22:10:41 UTC
9417 22:10:44.430571 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9418 22:10:44.437726 ELOG: Event(A0) added with size 9 at 2023-09-05 22:10:41 UTC
9419 22:10:44.440548 elog_add_boot_reason: Logged dev mode boot
9420 22:10:44.444248 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9421 22:10:44.447252 Finalize devices...
9422 22:10:44.447324 Devices finalized
9423 22:10:44.453771 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9424 22:10:44.457436 Writing coreboot table at 0xffe64000
9425 22:10:44.460346 0. 000000000010a000-0000000000113fff: RAMSTAGE
9426 22:10:44.463810 1. 0000000040000000-00000000400fffff: RAM
9427 22:10:44.467182 2. 0000000040100000-000000004032afff: RAMSTAGE
9428 22:10:44.473752 3. 000000004032b000-00000000545fffff: RAM
9429 22:10:44.477373 4. 0000000054600000-000000005465ffff: BL31
9430 22:10:44.480484 5. 0000000054660000-00000000ffe63fff: RAM
9431 22:10:44.486964 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9432 22:10:44.490939 7. 0000000100000000-000000023fffffff: RAM
9433 22:10:44.491024 Passing 5 GPIOs to payload:
9434 22:10:44.496979 NAME | PORT | POLARITY | VALUE
9435 22:10:44.500250 EC in RW | 0x000000aa | low | undefined
9436 22:10:44.507031 EC interrupt | 0x00000005 | low | undefined
9437 22:10:44.510271 TPM interrupt | 0x000000ab | high | undefined
9438 22:10:44.513975 SD card detect | 0x00000011 | high | undefined
9439 22:10:44.520437 speaker enable | 0x00000093 | high | undefined
9440 22:10:44.523335 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9441 22:10:44.527069 in-header: 03 f9 00 00 02 00 00 00
9442 22:10:44.527153 in-data: 02 00
9443 22:10:44.530386 ADC[4]: Raw value=901401 ID=7
9444 22:10:44.533423 ADC[3]: Raw value=213179 ID=1
9445 22:10:44.533540 RAM Code: 0x71
9446 22:10:44.536821 ADC[6]: Raw value=74502 ID=0
9447 22:10:44.540043 ADC[5]: Raw value=212072 ID=1
9448 22:10:44.540128 SKU Code: 0x1
9449 22:10:44.546911 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5be8
9450 22:10:44.550473 coreboot table: 964 bytes.
9451 22:10:44.553714 IMD ROOT 0. 0xfffff000 0x00001000
9452 22:10:44.556906 IMD SMALL 1. 0xffffe000 0x00001000
9453 22:10:44.560511 RO MCACHE 2. 0xffffc000 0x00001104
9454 22:10:44.563668 CONSOLE 3. 0xfff7c000 0x00080000
9455 22:10:44.566845 FMAP 4. 0xfff7b000 0x00000452
9456 22:10:44.570221 TIME STAMP 5. 0xfff7a000 0x00000910
9457 22:10:44.573340 VBOOT WORK 6. 0xfff66000 0x00014000
9458 22:10:44.576814 RAMOOPS 7. 0xffe66000 0x00100000
9459 22:10:44.580078 COREBOOT 8. 0xffe64000 0x00002000
9460 22:10:44.580204 IMD small region:
9461 22:10:44.583607 IMD ROOT 0. 0xffffec00 0x00000400
9462 22:10:44.586912 VPD 1. 0xffffeb80 0x0000006c
9463 22:10:44.589983 MMC STATUS 2. 0xffffeb60 0x00000004
9464 22:10:44.597079 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9465 22:10:44.597165 Probing TPM: done!
9466 22:10:44.603985 Connected to device vid:did:rid of 1ae0:0028:00
9467 22:10:44.610355 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9468 22:10:44.617926 Initialized TPM device CR50 revision 0
9469 22:10:44.618011 Checking cr50 for pending updates
9470 22:10:44.623777 Reading cr50 TPM mode
9471 22:10:44.632241 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9472 22:10:44.638964 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9473 22:10:44.678526 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9474 22:10:44.682182 Checking segment from ROM address 0x40100000
9475 22:10:44.685484 Checking segment from ROM address 0x4010001c
9476 22:10:44.691873 Loading segment from ROM address 0x40100000
9477 22:10:44.691983 code (compression=0)
9478 22:10:44.702027 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9479 22:10:44.708839 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9480 22:10:44.708915 it's not compressed!
9481 22:10:44.715379 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9482 22:10:44.719184 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9483 22:10:44.739411 Loading segment from ROM address 0x4010001c
9484 22:10:44.739508 Entry Point 0x80000000
9485 22:10:44.742620 Loaded segments
9486 22:10:44.746093 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9487 22:10:44.752693 Jumping to boot code at 0x80000000(0xffe64000)
9488 22:10:44.759448 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9489 22:10:44.765821 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9490 22:10:44.773676 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9491 22:10:44.777268 Checking segment from ROM address 0x40100000
9492 22:10:44.780418 Checking segment from ROM address 0x4010001c
9493 22:10:44.787000 Loading segment from ROM address 0x40100000
9494 22:10:44.787084 code (compression=1)
9495 22:10:44.793742 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9496 22:10:44.803555 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9497 22:10:44.803641 using LZMA
9498 22:10:44.811976 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9499 22:10:44.818537 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9500 22:10:44.821890 Loading segment from ROM address 0x4010001c
9501 22:10:44.821975 Entry Point 0x54601000
9502 22:10:44.825353 Loaded segments
9503 22:10:44.828523 NOTICE: MT8192 bl31_setup
9504 22:10:44.835440 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9505 22:10:44.839230 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9506 22:10:44.841978 WARNING: region 0:
9507 22:10:44.845589 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 22:10:44.845688 WARNING: region 1:
9509 22:10:44.852324 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9510 22:10:44.855591 WARNING: region 2:
9511 22:10:44.858870 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9512 22:10:44.862396 WARNING: region 3:
9513 22:10:44.865476 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9514 22:10:44.868817 WARNING: region 4:
9515 22:10:44.875382 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9516 22:10:44.875492 WARNING: region 5:
9517 22:10:44.879121 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 22:10:44.882160 WARNING: region 6:
9519 22:10:44.885434 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9520 22:10:44.888937 WARNING: region 7:
9521 22:10:44.892286 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 22:10:44.899213 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9523 22:10:44.902460 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9524 22:10:44.905639 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9525 22:10:44.912647 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9526 22:10:44.915521 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9527 22:10:44.919256 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9528 22:10:44.925596 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9529 22:10:44.929025 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9530 22:10:44.932295 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9531 22:10:44.939022 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9532 22:10:44.942350 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9533 22:10:44.949255 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9534 22:10:44.952196 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9535 22:10:44.955582 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9536 22:10:44.962615 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9537 22:10:44.965610 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9538 22:10:44.969402 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9539 22:10:44.976603 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9540 22:10:44.979235 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9541 22:10:44.982373 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9542 22:10:44.989348 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9543 22:10:44.992772 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9544 22:10:44.999173 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9545 22:10:45.002577 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9546 22:10:45.005720 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9547 22:10:45.012937 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9548 22:10:45.015831 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9549 22:10:45.023019 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9550 22:10:45.026064 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9551 22:10:45.029517 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9552 22:10:45.035979 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9553 22:10:45.039410 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9554 22:10:45.042515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9555 22:10:45.049497 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9556 22:10:45.052554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9557 22:10:45.055999 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9558 22:10:45.059402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9559 22:10:45.066160 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9560 22:10:45.069311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9561 22:10:45.072486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9562 22:10:45.075815 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9563 22:10:45.082749 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9564 22:10:45.085921 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9565 22:10:45.089208 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9566 22:10:45.092919 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9567 22:10:45.099108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9568 22:10:45.102626 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9569 22:10:45.105939 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9570 22:10:45.112650 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9571 22:10:45.115972 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9572 22:10:45.119744 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9573 22:10:45.126155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9574 22:10:45.129216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9575 22:10:45.135826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9576 22:10:45.139163 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9577 22:10:45.146057 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9578 22:10:45.149318 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9579 22:10:45.152737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9580 22:10:45.159242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9581 22:10:45.162678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9582 22:10:45.169279 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9583 22:10:45.172886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9584 22:10:45.179777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9585 22:10:45.182546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9586 22:10:45.189257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9587 22:10:45.192633 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9588 22:10:45.195995 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9589 22:10:45.202679 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9590 22:10:45.205974 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9591 22:10:45.212551 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9592 22:10:45.215991 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9593 22:10:45.219385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9594 22:10:45.226195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9595 22:10:45.229291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9596 22:10:45.235747 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9597 22:10:45.239442 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9598 22:10:45.245976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9599 22:10:45.249191 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9600 22:10:45.256067 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9601 22:10:45.259350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9602 22:10:45.263071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9603 22:10:45.269440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9604 22:10:45.272801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9605 22:10:45.279270 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9606 22:10:45.282899 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9607 22:10:45.286557 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9608 22:10:45.293072 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9609 22:10:45.296507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9610 22:10:45.302994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9611 22:10:45.306745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9612 22:10:45.313080 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9613 22:10:45.316067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9614 22:10:45.319428 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9615 22:10:45.326278 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9616 22:10:45.329530 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9617 22:10:45.336559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9618 22:10:45.339640 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9619 22:10:45.343019 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9620 22:10:45.349933 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9621 22:10:45.352995 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9622 22:10:45.356461 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9623 22:10:45.359539 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9624 22:10:45.366613 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9625 22:10:45.370005 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9626 22:10:45.376826 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9627 22:10:45.379534 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9628 22:10:45.383011 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9629 22:10:45.389820 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9630 22:10:45.393223 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9631 22:10:45.399892 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9632 22:10:45.403221 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9633 22:10:45.406611 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9634 22:10:45.413060 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9635 22:10:45.416217 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9636 22:10:45.423270 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9637 22:10:45.426550 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9638 22:10:45.429756 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9639 22:10:45.433170 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9640 22:10:45.439789 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9641 22:10:45.443743 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9642 22:10:45.446650 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9643 22:10:45.449786 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9644 22:10:45.456611 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9645 22:10:45.460439 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9646 22:10:45.463610 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9647 22:10:45.470155 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9648 22:10:45.473203 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9649 22:10:45.480317 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9650 22:10:45.483408 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9651 22:10:45.486892 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9652 22:10:45.493367 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9653 22:10:45.496655 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9654 22:10:45.500474 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9655 22:10:45.506892 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9656 22:10:45.510278 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9657 22:10:45.516930 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9658 22:10:45.520078 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9659 22:10:45.523511 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9660 22:10:45.530205 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9661 22:10:45.533647 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9662 22:10:45.537249 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9663 22:10:45.543924 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9664 22:10:45.546990 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9665 22:10:45.553699 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9666 22:10:45.557046 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9667 22:10:45.560337 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9668 22:10:45.567301 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9669 22:10:45.570454 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9670 22:10:45.573738 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9671 22:10:45.580695 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9672 22:10:45.584278 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9673 22:10:45.590659 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9674 22:10:45.594211 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9675 22:10:45.597277 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9676 22:10:45.603955 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9677 22:10:45.607317 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9678 22:10:45.610442 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9679 22:10:45.617621 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9680 22:10:45.620942 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9681 22:10:45.627814 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9682 22:10:45.630807 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9683 22:10:45.634333 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9684 22:10:45.640271 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9685 22:10:45.643769 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9686 22:10:45.650289 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9687 22:10:45.653855 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9688 22:10:45.657157 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9689 22:10:45.664169 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9690 22:10:45.666998 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9691 22:10:45.673580 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9692 22:10:45.676935 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9693 22:10:45.680324 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9694 22:10:45.686867 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9695 22:10:45.690487 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9696 22:10:45.697177 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9697 22:10:45.700263 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9698 22:10:45.703758 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9699 22:10:45.710516 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9700 22:10:45.713899 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9701 22:10:45.717320 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9702 22:10:45.723779 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9703 22:10:45.727029 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9704 22:10:45.733985 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9705 22:10:45.737007 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9706 22:10:45.740413 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9707 22:10:45.747347 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9708 22:10:45.750464 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9709 22:10:45.753742 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9710 22:10:45.760698 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9711 22:10:45.763617 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9712 22:10:45.770634 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9713 22:10:45.774409 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9714 22:10:45.780499 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9715 22:10:45.783848 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9716 22:10:45.787235 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9717 22:10:45.793793 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9718 22:10:45.797234 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9719 22:10:45.803495 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9720 22:10:45.807445 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9721 22:10:45.810543 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9722 22:10:45.816974 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9723 22:10:45.820600 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9724 22:10:45.826971 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9725 22:10:45.830625 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9726 22:10:45.833933 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9727 22:10:45.840526 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9728 22:10:45.843752 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9729 22:10:45.850622 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9730 22:10:45.853798 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9731 22:10:45.860668 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9732 22:10:45.863475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9733 22:10:45.867035 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9734 22:10:45.873761 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9735 22:10:45.876962 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9736 22:10:45.883502 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9737 22:10:45.887157 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9738 22:10:45.890199 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9739 22:10:45.896522 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9740 22:10:45.900007 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9741 22:10:45.906775 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9742 22:10:45.910458 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9743 22:10:45.916590 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9744 22:10:45.920155 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9745 22:10:45.923327 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9746 22:10:45.929895 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9747 22:10:45.933419 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9748 22:10:45.939685 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9749 22:10:45.942977 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9750 22:10:45.950119 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9751 22:10:45.953069 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9752 22:10:45.956300 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9753 22:10:45.959995 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9754 22:10:45.963049 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9755 22:10:45.969872 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9756 22:10:45.973046 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9757 22:10:45.976505 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9758 22:10:45.983084 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9759 22:10:45.986456 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9760 22:10:45.990169 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9761 22:10:45.996409 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9762 22:10:45.999831 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9763 22:10:46.006456 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9764 22:10:46.009912 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9765 22:10:46.013397 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9766 22:10:46.019779 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9767 22:10:46.023192 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9768 22:10:46.026459 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9769 22:10:46.033013 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9770 22:10:46.036509 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9771 22:10:46.039626 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9772 22:10:46.046203 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9773 22:10:46.049976 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9774 22:10:46.056463 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9775 22:10:46.059940 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9776 22:10:46.063047 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9777 22:10:46.069755 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9778 22:10:46.072945 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9779 22:10:46.077024 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9780 22:10:46.083391 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9781 22:10:46.086227 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9782 22:10:46.090023 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9783 22:10:46.096538 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9784 22:10:46.099545 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9785 22:10:46.102994 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9786 22:10:46.109820 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9787 22:10:46.113158 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9788 22:10:46.119832 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9789 22:10:46.123279 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9790 22:10:46.125983 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9791 22:10:46.129666 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9792 22:10:46.136136 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9793 22:10:46.139408 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9794 22:10:46.142629 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9795 22:10:46.146252 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9796 22:10:46.152722 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9797 22:10:46.156449 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9798 22:10:46.159611 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9799 22:10:46.162496 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9800 22:10:46.169143 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9801 22:10:46.173106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9802 22:10:46.176191 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9803 22:10:46.179361 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9804 22:10:46.186214 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9805 22:10:46.189139 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9806 22:10:46.195803 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9807 22:10:46.199285 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9808 22:10:46.206330 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9809 22:10:46.209113 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9810 22:10:46.212551 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9811 22:10:46.219413 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9812 22:10:46.222452 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9813 22:10:46.229113 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9814 22:10:46.232687 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9815 22:10:46.235900 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9816 22:10:46.242728 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9817 22:10:46.246090 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9818 22:10:46.252542 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9819 22:10:46.255846 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9820 22:10:46.259194 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9821 22:10:46.266367 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9822 22:10:46.269584 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9823 22:10:46.275989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9824 22:10:46.279642 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9825 22:10:46.282653 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9826 22:10:46.289152 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9827 22:10:46.292918 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9828 22:10:46.298932 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9829 22:10:46.302783 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9830 22:10:46.305970 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9831 22:10:46.312397 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9832 22:10:46.315524 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9833 22:10:46.322219 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9834 22:10:46.325678 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9835 22:10:46.329024 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9836 22:10:46.335455 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9837 22:10:46.339067 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9838 22:10:46.345853 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9839 22:10:46.348942 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9840 22:10:46.355443 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9841 22:10:46.358931 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9842 22:10:46.361951 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9843 22:10:46.368679 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9844 22:10:46.372000 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9845 22:10:46.378705 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9846 22:10:46.382057 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9847 22:10:46.385455 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9848 22:10:46.392115 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9849 22:10:46.395529 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9850 22:10:46.402053 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9851 22:10:46.405380 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9852 22:10:46.409088 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9853 22:10:46.415432 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9854 22:10:46.418978 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9855 22:10:46.425462 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9856 22:10:46.428637 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9857 22:10:46.435136 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9858 22:10:46.438365 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9859 22:10:46.441836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9860 22:10:46.448357 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9861 22:10:46.451536 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9862 22:10:46.458148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9863 22:10:46.461425 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9864 22:10:46.464676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9865 22:10:46.471596 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9866 22:10:46.475021 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9867 22:10:46.482170 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9868 22:10:46.484857 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9869 22:10:46.488284 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9870 22:10:46.494580 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9871 22:10:46.498004 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9872 22:10:46.504602 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9873 22:10:46.507860 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9874 22:10:46.514584 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9875 22:10:46.518065 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9876 22:10:46.521237 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9877 22:10:46.527656 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9878 22:10:46.531122 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9879 22:10:46.537518 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9880 22:10:46.540902 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9881 22:10:46.547589 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9882 22:10:46.551182 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9883 22:10:46.554298 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9884 22:10:46.561036 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9885 22:10:46.564140 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9886 22:10:46.571142 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9887 22:10:46.574799 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9888 22:10:46.581381 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9889 22:10:46.584597 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9890 22:10:46.587654 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9891 22:10:46.594158 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9892 22:10:46.597579 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9893 22:10:46.604110 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9894 22:10:46.607717 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9895 22:10:46.614568 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9896 22:10:46.617946 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9897 22:10:46.621013 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9898 22:10:46.627575 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9899 22:10:46.631026 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9900 22:10:46.637411 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9901 22:10:46.640855 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9902 22:10:46.647487 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9903 22:10:46.651002 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9904 22:10:46.654393 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9905 22:10:46.660895 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9906 22:10:46.664096 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9907 22:10:46.670685 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9908 22:10:46.673977 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9909 22:10:46.680634 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9910 22:10:46.684180 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9911 22:10:46.690593 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9912 22:10:46.694339 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9913 22:10:46.697307 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9914 22:10:46.704073 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9915 22:10:46.707316 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9916 22:10:46.713971 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9917 22:10:46.717157 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9918 22:10:46.721601 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9919 22:10:46.727707 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9920 22:10:46.730405 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9921 22:10:46.737612 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9922 22:10:46.740683 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9923 22:10:46.747420 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9924 22:10:46.750625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9925 22:10:46.754225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9926 22:10:46.760733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9927 22:10:46.764351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9928 22:10:46.770736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9929 22:10:46.773764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9930 22:10:46.780595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9931 22:10:46.783801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9932 22:10:46.790393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9933 22:10:46.793661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9934 22:10:46.800232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9935 22:10:46.803743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9936 22:10:46.810615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9937 22:10:46.813938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9938 22:10:46.820278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9939 22:10:46.824235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9940 22:10:46.830432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9941 22:10:46.833882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9942 22:10:46.837137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9943 22:10:46.843844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9944 22:10:46.847079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9945 22:10:46.853646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9946 22:10:46.857052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9947 22:10:46.863640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9948 22:10:46.867077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9949 22:10:46.873445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9950 22:10:46.876847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9951 22:10:46.883462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9952 22:10:46.887079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9953 22:10:46.893367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9954 22:10:46.897096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9955 22:10:46.903701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9956 22:10:46.906959 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9957 22:10:46.909958 INFO: [APUAPC] vio 0
9958 22:10:46.913409 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9959 22:10:46.920198 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9960 22:10:46.923537 INFO: [APUAPC] D0_APC_0: 0x400510
9961 22:10:46.927073 INFO: [APUAPC] D0_APC_1: 0x0
9962 22:10:46.930231 INFO: [APUAPC] D0_APC_2: 0x1540
9963 22:10:46.930321 INFO: [APUAPC] D0_APC_3: 0x0
9964 22:10:46.933353 INFO: [APUAPC] D1_APC_0: 0xffffffff
9965 22:10:46.936887 INFO: [APUAPC] D1_APC_1: 0xffffffff
9966 22:10:46.940046 INFO: [APUAPC] D1_APC_2: 0x3fffff
9967 22:10:46.943383 INFO: [APUAPC] D1_APC_3: 0x0
9968 22:10:46.946680 INFO: [APUAPC] D2_APC_0: 0xffffffff
9969 22:10:46.950422 INFO: [APUAPC] D2_APC_1: 0xffffffff
9970 22:10:46.953344 INFO: [APUAPC] D2_APC_2: 0x3fffff
9971 22:10:46.956680 INFO: [APUAPC] D2_APC_3: 0x0
9972 22:10:46.960163 INFO: [APUAPC] D3_APC_0: 0xffffffff
9973 22:10:46.963325 INFO: [APUAPC] D3_APC_1: 0xffffffff
9974 22:10:46.966592 INFO: [APUAPC] D3_APC_2: 0x3fffff
9975 22:10:46.969852 INFO: [APUAPC] D3_APC_3: 0x0
9976 22:10:46.973416 INFO: [APUAPC] D4_APC_0: 0xffffffff
9977 22:10:46.976870 INFO: [APUAPC] D4_APC_1: 0xffffffff
9978 22:10:46.979992 INFO: [APUAPC] D4_APC_2: 0x3fffff
9979 22:10:46.983280 INFO: [APUAPC] D4_APC_3: 0x0
9980 22:10:46.986537 INFO: [APUAPC] D5_APC_0: 0xffffffff
9981 22:10:46.990170 INFO: [APUAPC] D5_APC_1: 0xffffffff
9982 22:10:46.993230 INFO: [APUAPC] D5_APC_2: 0x3fffff
9983 22:10:46.996404 INFO: [APUAPC] D5_APC_3: 0x0
9984 22:10:46.999967 INFO: [APUAPC] D6_APC_0: 0xffffffff
9985 22:10:47.003213 INFO: [APUAPC] D6_APC_1: 0xffffffff
9986 22:10:47.006336 INFO: [APUAPC] D6_APC_2: 0x3fffff
9987 22:10:47.009863 INFO: [APUAPC] D6_APC_3: 0x0
9988 22:10:47.013168 INFO: [APUAPC] D7_APC_0: 0xffffffff
9989 22:10:47.016420 INFO: [APUAPC] D7_APC_1: 0xffffffff
9990 22:10:47.019727 INFO: [APUAPC] D7_APC_2: 0x3fffff
9991 22:10:47.023444 INFO: [APUAPC] D7_APC_3: 0x0
9992 22:10:47.026394 INFO: [APUAPC] D8_APC_0: 0xffffffff
9993 22:10:47.029669 INFO: [APUAPC] D8_APC_1: 0xffffffff
9994 22:10:47.032923 INFO: [APUAPC] D8_APC_2: 0x3fffff
9995 22:10:47.036640 INFO: [APUAPC] D8_APC_3: 0x0
9996 22:10:47.039673 INFO: [APUAPC] D9_APC_0: 0xffffffff
9997 22:10:47.043344 INFO: [APUAPC] D9_APC_1: 0xffffffff
9998 22:10:47.046546 INFO: [APUAPC] D9_APC_2: 0x3fffff
9999 22:10:47.049829 INFO: [APUAPC] D9_APC_3: 0x0
10000 22:10:47.053129 INFO: [APUAPC] D10_APC_0: 0xffffffff
10001 22:10:47.056555 INFO: [APUAPC] D10_APC_1: 0xffffffff
10002 22:10:47.060261 INFO: [APUAPC] D10_APC_2: 0x3fffff
10003 22:10:47.063181 INFO: [APUAPC] D10_APC_3: 0x0
10004 22:10:47.066888 INFO: [APUAPC] D11_APC_0: 0xffffffff
10005 22:10:47.069809 INFO: [APUAPC] D11_APC_1: 0xffffffff
10006 22:10:47.073010 INFO: [APUAPC] D11_APC_2: 0x3fffff
10007 22:10:47.076123 INFO: [APUAPC] D11_APC_3: 0x0
10008 22:10:47.079628 INFO: [APUAPC] D12_APC_0: 0xffffffff
10009 22:10:47.083158 INFO: [APUAPC] D12_APC_1: 0xffffffff
10010 22:10:47.086340 INFO: [APUAPC] D12_APC_2: 0x3fffff
10011 22:10:47.089575 INFO: [APUAPC] D12_APC_3: 0x0
10012 22:10:47.092952 INFO: [APUAPC] D13_APC_0: 0xffffffff
10013 22:10:47.096088 INFO: [APUAPC] D13_APC_1: 0xffffffff
10014 22:10:47.099543 INFO: [APUAPC] D13_APC_2: 0x3fffff
10015 22:10:47.102733 INFO: [APUAPC] D13_APC_3: 0x0
10016 22:10:47.106116 INFO: [APUAPC] D14_APC_0: 0xffffffff
10017 22:10:47.109507 INFO: [APUAPC] D14_APC_1: 0xffffffff
10018 22:10:47.112651 INFO: [APUAPC] D14_APC_2: 0x3fffff
10019 22:10:47.116025 INFO: [APUAPC] D14_APC_3: 0x0
10020 22:10:47.119250 INFO: [APUAPC] D15_APC_0: 0xffffffff
10021 22:10:47.122683 INFO: [APUAPC] D15_APC_1: 0xffffffff
10022 22:10:47.125874 INFO: [APUAPC] D15_APC_2: 0x3fffff
10023 22:10:47.129131 INFO: [APUAPC] D15_APC_3: 0x0
10024 22:10:47.132560 INFO: [APUAPC] APC_CON: 0x4
10025 22:10:47.132662 INFO: [NOCDAPC] D0_APC_0: 0x0
10026 22:10:47.136070 INFO: [NOCDAPC] D0_APC_1: 0x0
10027 22:10:47.139339 INFO: [NOCDAPC] D1_APC_0: 0x0
10028 22:10:47.142574 INFO: [NOCDAPC] D1_APC_1: 0xfff
10029 22:10:47.146026 INFO: [NOCDAPC] D2_APC_0: 0x0
10030 22:10:47.149248 INFO: [NOCDAPC] D2_APC_1: 0xfff
10031 22:10:47.152547 INFO: [NOCDAPC] D3_APC_0: 0x0
10032 22:10:47.156184 INFO: [NOCDAPC] D3_APC_1: 0xfff
10033 22:10:47.159531 INFO: [NOCDAPC] D4_APC_0: 0x0
10034 22:10:47.162304 INFO: [NOCDAPC] D4_APC_1: 0xfff
10035 22:10:47.165856 INFO: [NOCDAPC] D5_APC_0: 0x0
10036 22:10:47.165941 INFO: [NOCDAPC] D5_APC_1: 0xfff
10037 22:10:47.169104 INFO: [NOCDAPC] D6_APC_0: 0x0
10038 22:10:47.172375 INFO: [NOCDAPC] D6_APC_1: 0xfff
10039 22:10:47.175656 INFO: [NOCDAPC] D7_APC_0: 0x0
10040 22:10:47.179164 INFO: [NOCDAPC] D7_APC_1: 0xfff
10041 22:10:47.182795 INFO: [NOCDAPC] D8_APC_0: 0x0
10042 22:10:47.185841 INFO: [NOCDAPC] D8_APC_1: 0xfff
10043 22:10:47.188979 INFO: [NOCDAPC] D9_APC_0: 0x0
10044 22:10:47.192567 INFO: [NOCDAPC] D9_APC_1: 0xfff
10045 22:10:47.195716 INFO: [NOCDAPC] D10_APC_0: 0x0
10046 22:10:47.199122 INFO: [NOCDAPC] D10_APC_1: 0xfff
10047 22:10:47.202487 INFO: [NOCDAPC] D11_APC_0: 0x0
10048 22:10:47.202572 INFO: [NOCDAPC] D11_APC_1: 0xfff
10049 22:10:47.205756 INFO: [NOCDAPC] D12_APC_0: 0x0
10050 22:10:47.209028 INFO: [NOCDAPC] D12_APC_1: 0xfff
10051 22:10:47.212288 INFO: [NOCDAPC] D13_APC_0: 0x0
10052 22:10:47.215562 INFO: [NOCDAPC] D13_APC_1: 0xfff
10053 22:10:47.218728 INFO: [NOCDAPC] D14_APC_0: 0x0
10054 22:10:47.222448 INFO: [NOCDAPC] D14_APC_1: 0xfff
10055 22:10:47.225426 INFO: [NOCDAPC] D15_APC_0: 0x0
10056 22:10:47.228746 INFO: [NOCDAPC] D15_APC_1: 0xfff
10057 22:10:47.232847 INFO: [NOCDAPC] APC_CON: 0x4
10058 22:10:47.235598 INFO: [APUAPC] set_apusys_apc done
10059 22:10:47.238967 INFO: [DEVAPC] devapc_init done
10060 22:10:47.241983 INFO: GICv3 without legacy support detected.
10061 22:10:47.245297 INFO: ARM GICv3 driver initialized in EL3
10062 22:10:47.249361 INFO: Maximum SPI INTID supported: 639
10063 22:10:47.255269 INFO: BL31: Initializing runtime services
10064 22:10:47.258606 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10065 22:10:47.262205 INFO: SPM: enable CPC mode
10066 22:10:47.268505 INFO: mcdi ready for mcusys-off-idle and system suspend
10067 22:10:47.272443 INFO: BL31: Preparing for EL3 exit to normal world
10068 22:10:47.275262 INFO: Entry point address = 0x80000000
10069 22:10:47.278531 INFO: SPSR = 0x8
10070 22:10:47.283574
10071 22:10:47.283656
10072 22:10:47.283721
10073 22:10:47.286953 Starting depthcharge on Spherion...
10074 22:10:47.287035
10075 22:10:47.287100 Wipe memory regions:
10076 22:10:47.287159
10077 22:10:47.287787 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10078 22:10:47.287891 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10079 22:10:47.288220 Setting prompt string to ['asurada:']
10080 22:10:47.288304 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10081 22:10:47.290396 [0x00000040000000, 0x00000054600000)
10082 22:10:47.412993
10083 22:10:47.413090 [0x00000054660000, 0x00000080000000)
10084 22:10:47.673486
10085 22:10:47.673610 [0x000000821a7280, 0x000000ffe64000)
10086 22:10:48.418064
10087 22:10:48.418203 [0x00000100000000, 0x00000240000000)
10088 22:10:50.308340
10089 22:10:50.311752 Initializing XHCI USB controller at 0x11200000.
10090 22:10:51.349463
10091 22:10:51.352523 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10092 22:10:51.352615
10093 22:10:51.352681
10094 22:10:51.352742
10095 22:10:51.353065 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10097 22:10:51.453381 asurada: tftpboot 192.168.201.1 11440304/tftp-deploy-fbu5alh4/kernel/image.itb 11440304/tftp-deploy-fbu5alh4/kernel/cmdline
10098 22:10:51.453491 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10099 22:10:51.453573 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10100 22:10:51.457786 tftpboot 192.168.201.1 11440304/tftp-deploy-fbu5alh4/kernel/image.ittp-deploy-fbu5alh4/kernel/cmdline
10101 22:10:51.457870
10102 22:10:51.457937 Waiting for link
10103 22:10:51.617999
10104 22:10:51.618149 R8152: Initializing
10105 22:10:51.618265
10106 22:10:51.621335 Version 9 (ocp_data = 6010)
10107 22:10:51.621457
10108 22:10:51.624774 R8152: Done initializing
10109 22:10:51.624916
10110 22:10:51.625027 Adding net device
10111 22:10:53.507985
10112 22:10:53.508197 done.
10113 22:10:53.508318
10114 22:10:53.508431 MAC: 00:e0:4c:72:2d:d6
10115 22:10:53.508543
10116 22:10:53.511088 Sending DHCP discover... done.
10117 22:10:53.511211
10118 22:10:57.249551 Waiting for reply... done.
10119 22:10:57.249702
10120 22:10:57.249774 Sending DHCP request... done.
10121 22:10:57.252745
10122 22:10:57.252849 Waiting for reply... done.
10123 22:10:57.252915
10124 22:10:57.255889 My ip is 192.168.201.21
10125 22:10:57.255970
10126 22:10:57.259090 The DHCP server ip is 192.168.201.1
10127 22:10:57.259172
10128 22:10:57.262762 TFTP server IP predefined by user: 192.168.201.1
10129 22:10:57.262843
10130 22:10:57.269376 Bootfile predefined by user: 11440304/tftp-deploy-fbu5alh4/kernel/image.itb
10131 22:10:57.269482
10132 22:10:57.272898 Sending tftp read request... done.
10133 22:10:57.272979
10134 22:10:57.275986 Waiting for the transfer...
10135 22:10:57.276071
10136 22:10:57.561209 00000000 ################################################################
10137 22:10:57.561405
10138 22:10:57.845046 00080000 ################################################################
10139 22:10:57.845245
10140 22:10:58.122048 00100000 ################################################################
10141 22:10:58.122184
10142 22:10:58.412365 00180000 ################################################################
10143 22:10:58.412552
10144 22:10:58.698683 00200000 ################################################################
10145 22:10:58.698847
10146 22:10:58.973288 00280000 ################################################################
10147 22:10:58.973484
10148 22:10:59.257667 00300000 ################################################################
10149 22:10:59.257802
10150 22:10:59.527931 00380000 ################################################################
10151 22:10:59.528122
10152 22:10:59.815557 00400000 ################################################################
10153 22:10:59.815704
10154 22:11:00.103978 00480000 ################################################################
10155 22:11:00.104118
10156 22:11:00.400941 00500000 ################################################################
10157 22:11:00.401080
10158 22:11:00.694018 00580000 ################################################################
10159 22:11:00.694217
10160 22:11:00.989152 00600000 ################################################################
10161 22:11:00.989352
10162 22:11:01.285411 00680000 ################################################################
10163 22:11:01.285548
10164 22:11:01.581123 00700000 ################################################################
10165 22:11:01.581261
10166 22:11:01.868377 00780000 ################################################################
10167 22:11:01.868515
10168 22:11:02.159285 00800000 ################################################################
10169 22:11:02.159429
10170 22:11:02.439401 00880000 ################################################################
10171 22:11:02.439603
10172 22:11:02.717175 00900000 ################################################################
10173 22:11:02.717317
10174 22:11:02.990340 00980000 ################################################################
10175 22:11:02.990539
10176 22:11:03.263188 00a00000 ################################################################
10177 22:11:03.263324
10178 22:11:03.538053 00a80000 ################################################################
10179 22:11:03.538251
10180 22:11:03.809642 00b00000 ################################################################
10181 22:11:03.809780
10182 22:11:04.073521 00b80000 ################################################################
10183 22:11:04.073681
10184 22:11:04.334748 00c00000 ################################################################
10185 22:11:04.334879
10186 22:11:04.599011 00c80000 ################################################################
10187 22:11:04.599168
10188 22:11:04.858511 00d00000 ################################################################
10189 22:11:04.858648
10190 22:11:05.120127 00d80000 ################################################################
10191 22:11:05.120254
10192 22:11:05.377447 00e00000 ################################################################
10193 22:11:05.377575
10194 22:11:05.633229 00e80000 ################################################################
10195 22:11:05.633364
10196 22:11:05.895872 00f00000 ################################################################
10197 22:11:05.896016
10198 22:11:06.158812 00f80000 ################################################################
10199 22:11:06.158997
10200 22:11:06.422950 01000000 ################################################################
10201 22:11:06.423080
10202 22:11:06.676419 01080000 ################################################################
10203 22:11:06.676549
10204 22:11:06.928915 01100000 ################################################################
10205 22:11:06.929053
10206 22:11:07.179501 01180000 ################################################################
10207 22:11:07.179636
10208 22:11:07.441245 01200000 ################################################################
10209 22:11:07.441385
10210 22:11:07.696412 01280000 ################################################################
10211 22:11:07.696554
10212 22:11:07.952953 01300000 ################################################################
10213 22:11:07.953111
10214 22:11:08.220331 01380000 ################################################################
10215 22:11:08.220462
10216 22:11:08.488719 01400000 ################################################################
10217 22:11:08.488881
10218 22:11:08.746068 01480000 ################################################################
10219 22:11:08.746258
10220 22:11:09.022202 01500000 ################################################################
10221 22:11:09.022345
10222 22:11:09.316083 01580000 ################################################################
10223 22:11:09.316247
10224 22:11:09.612721 01600000 ################################################################
10225 22:11:09.612875
10226 22:11:09.884197 01680000 ################################################################
10227 22:11:09.884337
10228 22:11:10.148864 01700000 ################################################################
10229 22:11:10.148999
10230 22:11:10.425949 01780000 ################################################################
10231 22:11:10.426090
10232 22:11:10.711646 01800000 ################################################################
10233 22:11:10.711787
10234 22:11:10.992943 01880000 ################################################################
10235 22:11:10.993083
10236 22:11:11.285848 01900000 ################################################################
10237 22:11:11.285994
10238 22:11:11.569972 01980000 ################################################################
10239 22:11:11.570150
10240 22:11:11.827924 01a00000 ################################################################
10241 22:11:11.828055
10242 22:11:12.084454 01a80000 ################################################################
10243 22:11:12.084587
10244 22:11:12.340026 01b00000 ################################################################
10245 22:11:12.340171
10246 22:11:12.356415 01b80000 ##### done.
10247 22:11:12.356501
10248 22:11:12.359887 The bootfile was 28871514 bytes long.
10249 22:11:12.359971
10250 22:11:12.363528 Sending tftp read request... done.
10251 22:11:12.363611
10252 22:11:12.366331 Waiting for the transfer...
10253 22:11:12.366413
10254 22:11:12.366479 00000000 # done.
10255 22:11:12.366540
10256 22:11:12.376343 Command line loaded dynamically from TFTP file: 11440304/tftp-deploy-fbu5alh4/kernel/cmdline
10257 22:11:12.376426
10258 22:11:12.396560 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11440304/extract-nfsrootfs-i13_qaj1,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10259 22:11:12.396648
10260 22:11:12.399763 Loading FIT.
10261 22:11:12.399846
10262 22:11:12.403128 Image ramdisk-1 has 17784206 bytes.
10263 22:11:12.403234
10264 22:11:12.403315 Image fdt-1 has 47278 bytes.
10265 22:11:12.403374
10266 22:11:12.406869 Image kernel-1 has 11037994 bytes.
10267 22:11:12.406952
10268 22:11:12.416486 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10269 22:11:12.416571
10270 22:11:12.432813 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10271 22:11:12.432905
10272 22:11:12.439542 Choosing best match conf-1 for compat google,spherion-rev2.
10273 22:11:12.443334
10274 22:11:12.448136 Connected to device vid:did:rid of 1ae0:0028:00
10275 22:11:12.456277
10276 22:11:12.459560 tpm_get_response: command 0x17b, return code 0x0
10277 22:11:12.459641
10278 22:11:12.462932 ec_init: CrosEC protocol v3 supported (256, 248)
10279 22:11:12.466759
10280 22:11:12.470565 tpm_cleanup: add release locality here.
10281 22:11:12.470646
10282 22:11:12.470711 Shutting down all USB controllers.
10283 22:11:12.470771
10284 22:11:12.473666 Removing current net device
10285 22:11:12.473747
10286 22:11:12.480083 Exiting depthcharge with code 4 at timestamp: 54486822
10287 22:11:12.480168
10288 22:11:12.483580 LZMA decompressing kernel-1 to 0x821a6718
10289 22:11:12.483666
10290 22:11:12.487261 LZMA decompressing kernel-1 to 0x40000000
10291 22:11:13.874434
10292 22:11:13.874621 jumping to kernel
10293 22:11:13.875093 end: 2.2.4 bootloader-commands (duration 00:00:27) [common]
10294 22:11:13.875207 start: 2.2.5 auto-login-action (timeout 00:03:59) [common]
10295 22:11:13.875296 Setting prompt string to ['Linux version [0-9]']
10296 22:11:13.875381 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10297 22:11:13.875464 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10298 22:11:13.956121
10299 22:11:13.959540 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10300 22:11:13.963169 start: 2.2.5.1 login-action (timeout 00:03:59) [common]
10301 22:11:13.963272 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10302 22:11:13.963355 Setting prompt string to []
10303 22:11:13.963453 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10304 22:11:13.963540 Using line separator: #'\n'#
10305 22:11:13.963613 No login prompt set.
10306 22:11:13.963694 Parsing kernel messages
10307 22:11:13.963766 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10308 22:11:13.963950 [login-action] Waiting for messages, (timeout 00:03:59)
10309 22:11:13.982867 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j35911-arm64-gcc-10-defconfig-arm64-chromebook-zzzh4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Sep 5 21:54:53 UTC 2023
10310 22:11:13.985912 [ 0.000000] random: crng init done
10311 22:11:13.992668 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10312 22:11:13.992761 [ 0.000000] efi: UEFI not found.
10313 22:11:14.002747 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10314 22:11:14.009404 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10315 22:11:14.019508 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10316 22:11:14.029267 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10317 22:11:14.036111 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10318 22:11:14.039308 [ 0.000000] printk: bootconsole [mtk8250] enabled
10319 22:11:14.047958 [ 0.000000] NUMA: No NUMA configuration found
10320 22:11:14.054535 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10321 22:11:14.061375 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10322 22:11:14.061462 [ 0.000000] Zone ranges:
10323 22:11:14.068026 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10324 22:11:14.071115 [ 0.000000] DMA32 empty
10325 22:11:14.077918 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10326 22:11:14.081316 [ 0.000000] Movable zone start for each node
10327 22:11:14.084876 [ 0.000000] Early memory node ranges
10328 22:11:14.091422 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10329 22:11:14.097828 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10330 22:11:14.104424 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10331 22:11:14.111562 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10332 22:11:14.117868 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10333 22:11:14.124724 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10334 22:11:14.180420 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10335 22:11:14.187186 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10336 22:11:14.193648 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10337 22:11:14.197046 [ 0.000000] psci: probing for conduit method from DT.
10338 22:11:14.203653 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10339 22:11:14.206891 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10340 22:11:14.213794 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10341 22:11:14.216881 [ 0.000000] psci: SMC Calling Convention v1.2
10342 22:11:14.223998 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10343 22:11:14.226828 [ 0.000000] Detected VIPT I-cache on CPU0
10344 22:11:14.233479 [ 0.000000] CPU features: detected: GIC system register CPU interface
10345 22:11:14.240039 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10346 22:11:14.246927 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10347 22:11:14.253229 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10348 22:11:14.259885 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10349 22:11:14.266807 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10350 22:11:14.273317 [ 0.000000] alternatives: applying boot alternatives
10351 22:11:14.276472 [ 0.000000] Fallback order for Node 0: 0
10352 22:11:14.286311 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10353 22:11:14.286442 [ 0.000000] Policy zone: Normal
10354 22:11:14.309901 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11440304/extract-nfsrootfs-i13_qaj1,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10355 22:11:14.323047 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10356 22:11:14.332946 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10357 22:11:14.342978 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10358 22:11:14.349361 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10359 22:11:14.352607 <6>[ 0.000000] software IO TLB: area num 8.
10360 22:11:14.409233 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10361 22:11:14.558593 <6>[ 0.000000] Memory: 7952184K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 400584K reserved, 32768K cma-reserved)
10362 22:11:14.565046 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10363 22:11:14.571445 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10364 22:11:14.575097 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10365 22:11:14.581649 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10366 22:11:14.588208 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10367 22:11:14.591932 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10368 22:11:14.601395 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10369 22:11:14.608169 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10370 22:11:14.614584 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10371 22:11:14.621267 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10372 22:11:14.624627 <6>[ 0.000000] GICv3: 608 SPIs implemented
10373 22:11:14.628117 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10374 22:11:14.634616 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10375 22:11:14.637797 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10376 22:11:14.644539 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10377 22:11:14.657641 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10378 22:11:14.667537 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10379 22:11:14.678003 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10380 22:11:14.684754 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10381 22:11:14.698013 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10382 22:11:14.704868 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10383 22:11:14.711272 <6>[ 0.009185] Console: colour dummy device 80x25
10384 22:11:14.721350 <6>[ 0.013912] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10385 22:11:14.727907 <6>[ 0.024354] pid_max: default: 32768 minimum: 301
10386 22:11:14.731093 <6>[ 0.029250] LSM: Security Framework initializing
10387 22:11:14.737958 <6>[ 0.034189] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10388 22:11:14.747750 <6>[ 0.042001] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10389 22:11:14.757939 <6>[ 0.051480] cblist_init_generic: Setting adjustable number of callback queues.
10390 22:11:14.761211 <6>[ 0.058925] cblist_init_generic: Setting shift to 3 and lim to 1.
10391 22:11:14.771165 <6>[ 0.065265] cblist_init_generic: Setting adjustable number of callback queues.
10392 22:11:14.777917 <6>[ 0.072691] cblist_init_generic: Setting shift to 3 and lim to 1.
10393 22:11:14.781314 <6>[ 0.079090] rcu: Hierarchical SRCU implementation.
10394 22:11:14.788190 <6>[ 0.084103] rcu: Max phase no-delay instances is 1000.
10395 22:11:14.794313 <6>[ 0.091171] EFI services will not be available.
10396 22:11:14.797878 <6>[ 0.096143] smp: Bringing up secondary CPUs ...
10397 22:11:14.805717 <6>[ 0.101198] Detected VIPT I-cache on CPU1
10398 22:11:14.812350 <6>[ 0.101270] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10399 22:11:14.818817 <6>[ 0.101301] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10400 22:11:14.822439 <6>[ 0.101632] Detected VIPT I-cache on CPU2
10401 22:11:14.829238 <6>[ 0.101681] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10402 22:11:14.835726 <6>[ 0.101696] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10403 22:11:14.842270 <6>[ 0.101952] Detected VIPT I-cache on CPU3
10404 22:11:14.848878 <6>[ 0.101999] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10405 22:11:14.855553 <6>[ 0.102012] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10406 22:11:14.859021 <6>[ 0.102318] CPU features: detected: Spectre-v4
10407 22:11:14.865511 <6>[ 0.102324] CPU features: detected: Spectre-BHB
10408 22:11:14.868895 <6>[ 0.102328] Detected PIPT I-cache on CPU4
10409 22:11:14.875636 <6>[ 0.102385] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10410 22:11:14.881910 <6>[ 0.102402] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10411 22:11:14.888479 <6>[ 0.102695] Detected PIPT I-cache on CPU5
10412 22:11:14.894969 <6>[ 0.102757] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10413 22:11:14.901617 <6>[ 0.102774] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10414 22:11:14.905151 <6>[ 0.103060] Detected PIPT I-cache on CPU6
10415 22:11:14.911694 <6>[ 0.103121] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10416 22:11:14.918288 <6>[ 0.103138] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10417 22:11:14.924976 <6>[ 0.103437] Detected PIPT I-cache on CPU7
10418 22:11:14.931726 <6>[ 0.103502] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10419 22:11:14.938211 <6>[ 0.103519] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10420 22:11:14.941590 <6>[ 0.103564] smp: Brought up 1 node, 8 CPUs
10421 22:11:14.948049 <6>[ 0.244769] SMP: Total of 8 processors activated.
10422 22:11:14.951373 <6>[ 0.249690] CPU features: detected: 32-bit EL0 Support
10423 22:11:14.961752 <6>[ 0.255052] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10424 22:11:14.968157 <6>[ 0.263852] CPU features: detected: Common not Private translations
10425 22:11:14.971482 <6>[ 0.270368] CPU features: detected: CRC32 instructions
10426 22:11:14.978255 <6>[ 0.275719] CPU features: detected: RCpc load-acquire (LDAPR)
10427 22:11:14.984575 <6>[ 0.281715] CPU features: detected: LSE atomic instructions
10428 22:11:14.991429 <6>[ 0.287496] CPU features: detected: Privileged Access Never
10429 22:11:14.994832 <6>[ 0.293276] CPU features: detected: RAS Extension Support
10430 22:11:15.004644 <6>[ 0.298919] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10431 22:11:15.008092 <6>[ 0.306139] CPU: All CPU(s) started at EL2
10432 22:11:15.014599 <6>[ 0.310456] alternatives: applying system-wide alternatives
10433 22:11:15.023247 <6>[ 0.321148] devtmpfs: initialized
10434 22:11:15.038718 <6>[ 0.330046] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10435 22:11:15.045305 <6>[ 0.340007] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10436 22:11:15.051780 <6>[ 0.347834] pinctrl core: initialized pinctrl subsystem
10437 22:11:15.055533 <6>[ 0.354475] DMI not present or invalid.
10438 22:11:15.061735 <6>[ 0.358881] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10439 22:11:15.071455 <6>[ 0.365745] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10440 22:11:15.078209 <6>[ 0.373327] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10441 22:11:15.088184 <6>[ 0.381536] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10442 22:11:15.091681 <6>[ 0.389777] audit: initializing netlink subsys (disabled)
10443 22:11:15.101666 <5>[ 0.395469] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10444 22:11:15.108213 <6>[ 0.396171] thermal_sys: Registered thermal governor 'step_wise'
10445 22:11:15.115302 <6>[ 0.403436] thermal_sys: Registered thermal governor 'power_allocator'
10446 22:11:15.118475 <6>[ 0.409690] cpuidle: using governor menu
10447 22:11:15.124999 <6>[ 0.420649] NET: Registered PF_QIPCRTR protocol family
10448 22:11:15.131537 <6>[ 0.426144] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10449 22:11:15.134639 <6>[ 0.433252] ASID allocator initialised with 32768 entries
10450 22:11:15.142130 <6>[ 0.439806] Serial: AMBA PL011 UART driver
10451 22:11:15.150496 <4>[ 0.448503] Trying to register duplicate clock ID: 134
10452 22:11:15.204706 <6>[ 0.505858] KASLR enabled
10453 22:11:15.219337 <6>[ 0.513564] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10454 22:11:15.225744 <6>[ 0.520579] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10455 22:11:15.232160 <6>[ 0.527069] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10456 22:11:15.239427 <6>[ 0.534074] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10457 22:11:15.245525 <6>[ 0.540559] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10458 22:11:15.252287 <6>[ 0.547561] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10459 22:11:15.258863 <6>[ 0.554048] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10460 22:11:15.265277 <6>[ 0.561053] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10461 22:11:15.269163 <6>[ 0.568545] ACPI: Interpreter disabled.
10462 22:11:15.276910 <6>[ 0.574930] iommu: Default domain type: Translated
10463 22:11:15.283700 <6>[ 0.580042] iommu: DMA domain TLB invalidation policy: strict mode
10464 22:11:15.287189 <5>[ 0.586693] SCSI subsystem initialized
10465 22:11:15.293866 <6>[ 0.590860] usbcore: registered new interface driver usbfs
10466 22:11:15.300006 <6>[ 0.596594] usbcore: registered new interface driver hub
10467 22:11:15.303628 <6>[ 0.602147] usbcore: registered new device driver usb
10468 22:11:15.310643 <6>[ 0.608233] pps_core: LinuxPPS API ver. 1 registered
10469 22:11:15.320473 <6>[ 0.613429] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10470 22:11:15.323550 <6>[ 0.622772] PTP clock support registered
10471 22:11:15.326860 <6>[ 0.627014] EDAC MC: Ver: 3.0.0
10472 22:11:15.334065 <6>[ 0.632164] FPGA manager framework
10473 22:11:15.337983 <6>[ 0.635842] Advanced Linux Sound Architecture Driver Initialized.
10474 22:11:15.341331 <6>[ 0.642612] vgaarb: loaded
10475 22:11:15.347956 <6>[ 0.645801] clocksource: Switched to clocksource arch_sys_counter
10476 22:11:15.354661 <5>[ 0.652234] VFS: Disk quotas dquot_6.6.0
10477 22:11:15.361565 <6>[ 0.656416] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10478 22:11:15.364539 <6>[ 0.663605] pnp: PnP ACPI: disabled
10479 22:11:15.372897 <6>[ 0.670272] NET: Registered PF_INET protocol family
10480 22:11:15.382404 <6>[ 0.675856] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10481 22:11:15.393669 <6>[ 0.688132] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10482 22:11:15.403406 <6>[ 0.696949] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10483 22:11:15.410319 <6>[ 0.704920] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10484 22:11:15.417089 <6>[ 0.713620] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10485 22:11:15.428890 <6>[ 0.723368] TCP: Hash tables configured (established 65536 bind 65536)
10486 22:11:15.435403 <6>[ 0.730225] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10487 22:11:15.442007 <6>[ 0.737426] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10488 22:11:15.448565 <6>[ 0.745126] NET: Registered PF_UNIX/PF_LOCAL protocol family
10489 22:11:15.455235 <6>[ 0.751298] RPC: Registered named UNIX socket transport module.
10490 22:11:15.458750 <6>[ 0.757453] RPC: Registered udp transport module.
10491 22:11:15.465304 <6>[ 0.762384] RPC: Registered tcp transport module.
10492 22:11:15.471744 <6>[ 0.767318] RPC: Registered tcp NFSv4.1 backchannel transport module.
10493 22:11:15.475158 <6>[ 0.773984] PCI: CLS 0 bytes, default 64
10494 22:11:15.478758 <6>[ 0.778384] Unpacking initramfs...
10495 22:11:15.503470 <6>[ 0.797889] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10496 22:11:15.513078 <6>[ 0.806547] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10497 22:11:15.516364 <6>[ 0.815403] kvm [1]: IPA Size Limit: 40 bits
10498 22:11:15.523021 <6>[ 0.819934] kvm [1]: GICv3: no GICV resource entry
10499 22:11:15.526447 <6>[ 0.824955] kvm [1]: disabling GICv2 emulation
10500 22:11:15.532954 <6>[ 0.829644] kvm [1]: GIC system register CPU interface enabled
10501 22:11:15.536414 <6>[ 0.835810] kvm [1]: vgic interrupt IRQ18
10502 22:11:15.542938 <6>[ 0.840163] kvm [1]: VHE mode initialized successfully
10503 22:11:15.549869 <5>[ 0.846558] Initialise system trusted keyrings
10504 22:11:15.555967 <6>[ 0.851343] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10505 22:11:15.563348 <6>[ 0.861292] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10506 22:11:15.570264 <5>[ 0.867648] NFS: Registering the id_resolver key type
10507 22:11:15.573346 <5>[ 0.872947] Key type id_resolver registered
10508 22:11:15.580086 <5>[ 0.877363] Key type id_legacy registered
10509 22:11:15.586838 <6>[ 0.881641] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10510 22:11:15.593319 <6>[ 0.888565] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10511 22:11:15.599749 <6>[ 0.896263] 9p: Installing v9fs 9p2000 file system support
10512 22:11:15.635979 <5>[ 0.933818] Key type asymmetric registered
10513 22:11:15.639226 <5>[ 0.938149] Asymmetric key parser 'x509' registered
10514 22:11:15.649209 <6>[ 0.943303] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10515 22:11:15.652432 <6>[ 0.950923] io scheduler mq-deadline registered
10516 22:11:15.655748 <6>[ 0.955699] io scheduler kyber registered
10517 22:11:15.675077 <6>[ 0.972696] EINJ: ACPI disabled.
10518 22:11:15.707794 <4>[ 0.998963] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10519 22:11:15.717459 <4>[ 1.009601] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10520 22:11:15.732304 <6>[ 1.030452] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10521 22:11:15.740705 <6>[ 1.038620] printk: console [ttyS0] disabled
10522 22:11:15.768813 <6>[ 1.063268] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10523 22:11:15.775248 <6>[ 1.072745] printk: console [ttyS0] enabled
10524 22:11:15.779016 <6>[ 1.072745] printk: console [ttyS0] enabled
10525 22:11:15.785494 <6>[ 1.081644] printk: bootconsole [mtk8250] disabled
10526 22:11:15.788498 <6>[ 1.081644] printk: bootconsole [mtk8250] disabled
10527 22:11:15.795306 <6>[ 1.092925] SuperH (H)SCI(F) driver initialized
10528 22:11:15.798405 <6>[ 1.098215] msm_serial: driver initialized
10529 22:11:15.812729 <6>[ 1.107188] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10530 22:11:15.822472 <6>[ 1.115734] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10531 22:11:15.829170 <6>[ 1.124278] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10532 22:11:15.839211 <6>[ 1.132906] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10533 22:11:15.846016 <6>[ 1.141612] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10534 22:11:15.855484 <6>[ 1.150329] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10535 22:11:15.865484 <6>[ 1.158870] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10536 22:11:15.872330 <6>[ 1.167697] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10537 22:11:15.882153 <6>[ 1.176240] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10538 22:11:15.893985 <6>[ 1.191948] loop: module loaded
10539 22:11:15.900718 <6>[ 1.197963] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10540 22:11:15.923478 <4>[ 1.221253] mtk-pmic-keys: Failed to locate of_node [id: -1]
10541 22:11:15.930007 <6>[ 1.228096] megasas: 07.719.03.00-rc1
10542 22:11:15.939755 <6>[ 1.237748] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10543 22:11:15.947356 <6>[ 1.245187] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10544 22:11:15.964235 <6>[ 1.262107] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10545 22:11:16.021298 <6>[ 1.312399] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10546 22:11:16.220433 <6>[ 1.518293] Freeing initrd memory: 17364K
10547 22:11:16.230554 <6>[ 1.528561] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10548 22:11:16.241522 <6>[ 1.539562] tun: Universal TUN/TAP device driver, 1.6
10549 22:11:16.244718 <6>[ 1.545639] thunder_xcv, ver 1.0
10550 22:11:16.248045 <6>[ 1.549145] thunder_bgx, ver 1.0
10551 22:11:16.251871 <6>[ 1.552643] nicpf, ver 1.0
10552 22:11:16.262295 <6>[ 1.556668] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10553 22:11:16.265313 <6>[ 1.564143] hns3: Copyright (c) 2017 Huawei Corporation.
10554 22:11:16.269027 <6>[ 1.569732] hclge is initializing
10555 22:11:16.275722 <6>[ 1.573314] e1000: Intel(R) PRO/1000 Network Driver
10556 22:11:16.282082 <6>[ 1.578444] e1000: Copyright (c) 1999-2006 Intel Corporation.
10557 22:11:16.285661 <6>[ 1.584455] e1000e: Intel(R) PRO/1000 Network Driver
10558 22:11:16.292150 <6>[ 1.589670] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10559 22:11:16.298688 <6>[ 1.595858] igb: Intel(R) Gigabit Ethernet Network Driver
10560 22:11:16.305294 <6>[ 1.601508] igb: Copyright (c) 2007-2014 Intel Corporation.
10561 22:11:16.312397 <6>[ 1.607346] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10562 22:11:16.318859 <6>[ 1.613864] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10563 22:11:16.322142 <6>[ 1.620323] sky2: driver version 1.30
10564 22:11:16.328641 <6>[ 1.625322] VFIO - User Level meta-driver version: 0.3
10565 22:11:16.335691 <6>[ 1.633572] usbcore: registered new interface driver usb-storage
10566 22:11:16.342313 <6>[ 1.640021] usbcore: registered new device driver onboard-usb-hub
10567 22:11:16.351370 <6>[ 1.649131] mt6397-rtc mt6359-rtc: registered as rtc0
10568 22:11:16.361404 <6>[ 1.654593] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-05T22:11:13 UTC (1693951873)
10569 22:11:16.364627 <6>[ 1.664161] i2c_dev: i2c /dev entries driver
10570 22:11:16.381090 <6>[ 1.675863] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10571 22:11:16.400958 <6>[ 1.698847] cpu cpu0: EM: created perf domain
10572 22:11:16.404114 <6>[ 1.703870] cpu cpu4: EM: created perf domain
10573 22:11:16.411390 <6>[ 1.709548] sdhci: Secure Digital Host Controller Interface driver
10574 22:11:16.418056 <6>[ 1.715980] sdhci: Copyright(c) Pierre Ossman
10575 22:11:16.424782 <6>[ 1.720939] Synopsys Designware Multimedia Card Interface Driver
10576 22:11:16.431337 <6>[ 1.727573] sdhci-pltfm: SDHCI platform and OF driver helper
10577 22:11:16.434782 <6>[ 1.727626] mmc0: CQHCI version 5.10
10578 22:11:16.441517 <6>[ 1.737833] ledtrig-cpu: registered to indicate activity on CPUs
10579 22:11:16.448182 <6>[ 1.744905] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10580 22:11:16.454786 <6>[ 1.751964] usbcore: registered new interface driver usbhid
10581 22:11:16.458103 <6>[ 1.757787] usbhid: USB HID core driver
10582 22:11:16.464960 <6>[ 1.762014] spi_master spi0: will run message pump with realtime priority
10583 22:11:16.508149 <6>[ 1.799866] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10584 22:11:16.527409 <6>[ 1.814745] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10585 22:11:16.530867 <6>[ 1.828850] mmc0: Command Queue Engine enabled
10586 22:11:16.537369 <6>[ 1.833600] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10587 22:11:16.544182 <6>[ 1.840320] cros-ec-spi spi0.0: Chrome EC device registered
10588 22:11:16.547435 <6>[ 1.840933] mmcblk0: mmc0:0001 DA4128 116 GiB
10589 22:11:16.557099 <6>[ 1.855216] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10590 22:11:16.565053 <6>[ 1.863082] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10591 22:11:16.571715 <6>[ 1.868917] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10592 22:11:16.578259 <6>[ 1.875000] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10593 22:11:16.593541 <6>[ 1.888476] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10594 22:11:16.600658 <6>[ 1.898899] NET: Registered PF_PACKET protocol family
10595 22:11:16.604314 <6>[ 1.904284] 9pnet: Installing 9P2000 support
10596 22:11:16.610808 <5>[ 1.908847] Key type dns_resolver registered
10597 22:11:16.614239 <6>[ 1.913855] registered taskstats version 1
10598 22:11:16.620734 <5>[ 1.918230] Loading compiled-in X.509 certificates
10599 22:11:16.650592 <4>[ 1.941896] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10600 22:11:16.660486 <4>[ 1.952731] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 22:11:16.667269 <3>[ 1.963265] debugfs: File 'uA_load' in directory '/' already present!
10602 22:11:16.674140 <3>[ 1.969987] debugfs: File 'min_uV' in directory '/' already present!
10603 22:11:16.680449 <3>[ 1.976602] debugfs: File 'max_uV' in directory '/' already present!
10604 22:11:16.687083 <3>[ 1.983208] debugfs: File 'constraint_flags' in directory '/' already present!
10605 22:11:16.698578 <3>[ 1.993100] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10606 22:11:16.707461 <6>[ 2.005334] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10607 22:11:16.714227 <6>[ 2.012130] xhci-mtk 11200000.usb: xHCI Host Controller
10608 22:11:16.720724 <6>[ 2.017660] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10609 22:11:16.731162 <6>[ 2.025498] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10610 22:11:16.737445 <6>[ 2.034946] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10611 22:11:16.744261 <6>[ 2.041016] xhci-mtk 11200000.usb: xHCI Host Controller
10612 22:11:16.750863 <6>[ 2.046493] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10613 22:11:16.757478 <6>[ 2.054138] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10614 22:11:16.764381 <6>[ 2.061989] hub 1-0:1.0: USB hub found
10615 22:11:16.768025 <6>[ 2.066008] hub 1-0:1.0: 1 port detected
10616 22:11:16.774199 <6>[ 2.070291] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10617 22:11:16.781233 <6>[ 2.079010] hub 2-0:1.0: USB hub found
10618 22:11:16.784373 <6>[ 2.083029] hub 2-0:1.0: 1 port detected
10619 22:11:16.792568 <6>[ 2.090552] mtk-msdc 11f70000.mmc: Got CD GPIO
10620 22:11:16.802755 <6>[ 2.097436] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10621 22:11:16.809510 <6>[ 2.105463] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10622 22:11:16.819254 <4>[ 2.113350] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10623 22:11:16.829801 <6>[ 2.122875] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10624 22:11:16.836010 <6>[ 2.130953] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10625 22:11:16.842928 <6>[ 2.139077] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10626 22:11:16.852659 <6>[ 2.147003] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10627 22:11:16.859240 <6>[ 2.154820] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10628 22:11:16.869311 <6>[ 2.162637] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10629 22:11:16.879543 <6>[ 2.173171] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10630 22:11:16.885909 <6>[ 2.181557] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10631 22:11:16.895867 <6>[ 2.189898] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10632 22:11:16.902419 <6>[ 2.198237] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10633 22:11:16.912421 <6>[ 2.206576] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10634 22:11:16.919399 <6>[ 2.214914] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10635 22:11:16.929214 <6>[ 2.223255] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10636 22:11:16.936077 <6>[ 2.231593] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10637 22:11:16.946192 <6>[ 2.239931] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10638 22:11:16.952582 <6>[ 2.248270] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10639 22:11:16.962684 <6>[ 2.256617] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10640 22:11:16.969076 <6>[ 2.264956] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10641 22:11:16.979204 <6>[ 2.273293] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10642 22:11:16.985760 <6>[ 2.281631] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10643 22:11:16.995659 <6>[ 2.289985] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10644 22:11:17.002577 <6>[ 2.298801] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10645 22:11:17.008989 <6>[ 2.306001] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10646 22:11:17.015729 <6>[ 2.312767] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10647 22:11:17.022378 <6>[ 2.319530] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10648 22:11:17.029530 <6>[ 2.326473] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10649 22:11:17.039190 <6>[ 2.333318] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10650 22:11:17.048798 <6>[ 2.342451] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10651 22:11:17.058748 <6>[ 2.351571] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10652 22:11:17.068595 <6>[ 2.360865] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10653 22:11:17.075628 <6>[ 2.370333] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10654 22:11:17.085228 <6>[ 2.379800] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10655 22:11:17.095675 <6>[ 2.388919] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10656 22:11:17.105205 <6>[ 2.398388] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10657 22:11:17.115062 <6>[ 2.407508] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10658 22:11:17.125041 <6>[ 2.416804] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10659 22:11:17.135009 <6>[ 2.426963] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10660 22:11:17.144920 <6>[ 2.438866] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10661 22:11:17.151603 <6>[ 2.448560] Trying to probe devices needed for running init ...
10662 22:11:17.175610 <6>[ 2.470360] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10663 22:11:17.203341 <6>[ 2.501606] hub 2-1:1.0: USB hub found
10664 22:11:17.207004 <6>[ 2.506095] hub 2-1:1.0: 3 ports detected
10665 22:11:17.327287 <6>[ 2.622069] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10666 22:11:17.482454 <6>[ 2.780191] hub 1-1:1.0: USB hub found
10667 22:11:17.485451 <6>[ 2.784701] hub 1-1:1.0: 4 ports detected
10668 22:11:17.560011 <6>[ 2.854377] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10669 22:11:17.807126 <6>[ 3.102122] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10670 22:11:17.940487 <6>[ 3.238083] hub 1-1.4:1.0: USB hub found
10671 22:11:17.943162 <6>[ 3.242752] hub 1-1.4:1.0: 2 ports detected
10672 22:11:18.239146 <6>[ 3.534105] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10673 22:11:18.431073 <6>[ 3.726103] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10674 22:11:29.432291 <6>[ 14.735081] ALSA device list:
10675 22:11:29.438974 <6>[ 14.738376] No soundcards found.
10676 22:11:29.446866 <6>[ 14.746316] Freeing unused kernel memory: 8384K
10677 22:11:29.450135 <6>[ 14.751339] Run /init as init process
10678 22:11:29.461610 Loading, please wait...
10679 22:11:29.482059 Starting version 247.3-7+deb11u2
10680 22:11:29.721488 <6>[ 15.017249] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10681 22:11:29.733061 <6>[ 15.032635] remoteproc remoteproc0: scp is available
10682 22:11:29.739617 <6>[ 15.038127] remoteproc remoteproc0: powering up scp
10683 22:11:29.746456 <6>[ 15.043270] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10684 22:11:29.752917 <6>[ 15.051724] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10685 22:11:29.787529 <3>[ 15.083780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 22:11:29.794251 <6>[ 15.088150] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10687 22:11:29.804162 <3>[ 15.091916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 22:11:29.810875 <4>[ 15.092778] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10689 22:11:29.817339 <4>[ 15.099061] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10690 22:11:29.827318 <6>[ 15.099606] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10691 22:11:29.830889 <6>[ 15.101416] mc: Linux media interface: v0.10
10692 22:11:29.837464 <6>[ 15.103808] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10693 22:11:29.848066 <3>[ 15.107615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 22:11:29.854567 <4>[ 15.124514] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10695 22:11:29.861096 <4>[ 15.124514] Fallback method does not support PEC.
10696 22:11:29.867852 <6>[ 15.131065] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10697 22:11:29.877889 <3>[ 15.137575] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 22:11:29.884622 <6>[ 15.140405] usbcore: registered new interface driver r8152
10699 22:11:29.891301 <3>[ 15.164957] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10700 22:11:29.901175 <3>[ 15.174105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 22:11:29.904461 <6>[ 15.175134] videodev: Linux video capture interface: v2.00
10702 22:11:29.914268 <6>[ 15.182678] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10703 22:11:29.921084 <6>[ 15.182701] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10704 22:11:29.930622 <3>[ 15.187739] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 22:11:29.937372 <6>[ 15.196387] remoteproc remoteproc0: remote processor scp is now up
10706 22:11:29.944088 <6>[ 15.197681] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10707 22:11:29.954221 <6>[ 15.199573] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10708 22:11:29.961008 <3>[ 15.204534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 22:11:29.971183 <6>[ 15.212266] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10710 22:11:29.978259 <3>[ 15.218980] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 22:11:29.984642 <3>[ 15.219048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 22:11:29.994897 <3>[ 15.219084] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 22:11:30.004427 <6>[ 15.234387] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10714 22:11:30.011152 <3>[ 15.240625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 22:11:30.020936 <3>[ 15.240628] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 22:11:30.027651 <3>[ 15.240668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 22:11:30.037534 <6>[ 15.249243] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10718 22:11:30.044156 <3>[ 15.257136] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 22:11:30.054196 <3>[ 15.257139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 22:11:30.060974 <3>[ 15.257142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 22:11:30.070996 <3>[ 15.257144] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 22:11:30.077521 <3>[ 15.257158] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 22:11:30.084490 <6>[ 15.263124] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10724 22:11:30.091036 <6>[ 15.263129] pci_bus 0000:00: root bus resource [bus 00-ff]
10725 22:11:30.097564 <6>[ 15.263133] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10726 22:11:30.107272 <6>[ 15.263136] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10727 22:11:30.113935 <6>[ 15.263166] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10728 22:11:30.120483 <6>[ 15.263180] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10729 22:11:30.127302 <6>[ 15.263243] pci 0000:00:00.0: supports D1 D2
10730 22:11:30.134147 <6>[ 15.263244] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10731 22:11:30.140568 <6>[ 15.264158] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10732 22:11:30.147143 <6>[ 15.264227] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10733 22:11:30.153691 <6>[ 15.264251] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10734 22:11:30.163744 <6>[ 15.264267] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10735 22:11:30.170433 <6>[ 15.264282] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10736 22:11:30.173714 <6>[ 15.264384] pci 0000:01:00.0: supports D1 D2
10737 22:11:30.180440 <6>[ 15.264385] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10738 22:11:30.187285 <6>[ 15.270011] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10739 22:11:30.197049 <6>[ 15.273920] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10740 22:11:30.203774 <6>[ 15.273955] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10741 22:11:30.210130 <6>[ 15.273962] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10742 22:11:30.220196 <6>[ 15.273975] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10743 22:11:30.227389 <6>[ 15.273992] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10744 22:11:30.236402 <6>[ 15.274008] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10745 22:11:30.239974 <6>[ 15.274024] pci 0000:00:00.0: PCI bridge to [bus 01]
10746 22:11:30.249787 <6>[ 15.274033] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10747 22:11:30.256514 <6>[ 15.274192] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10748 22:11:30.260079 <6>[ 15.275244] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10749 22:11:30.269920 <3>[ 15.282615] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10750 22:11:30.276104 <6>[ 15.291090] usbcore: registered new interface driver cdc_ether
10751 22:11:30.282898 <6>[ 15.291395] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10752 22:11:30.286218 <6>[ 15.318387] Bluetooth: Core ver 2.22
10753 22:11:30.292912 <5>[ 15.320320] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10754 22:11:30.302592 <4>[ 15.321523] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10755 22:11:30.309541 <4>[ 15.321530] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10756 22:11:30.316388 <5>[ 15.331829] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10757 22:11:30.322875 <6>[ 15.333234] NET: Registered PF_BLUETOOTH protocol family
10758 22:11:30.329081 <6>[ 15.333509] usbcore: registered new interface driver r8153_ecm
10759 22:11:30.339243 <4>[ 15.342309] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10760 22:11:30.345537 <6>[ 15.350271] Bluetooth: HCI device and connection manager initialized
10761 22:11:30.349074 <6>[ 15.350293] Bluetooth: HCI socket layer initialized
10762 22:11:30.355712 <6>[ 15.350297] Bluetooth: L2CAP socket layer initialized
10763 22:11:30.358981 <6>[ 15.350304] Bluetooth: SCO socket layer initialized
10764 22:11:30.365891 <6>[ 15.358525] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10765 22:11:30.372115 <6>[ 15.366589] cfg80211: failed to load regulatory.db
10766 22:11:30.378772 <6>[ 15.384923] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10767 22:11:30.385694 <6>[ 15.391140] usbcore: registered new interface driver btusb
10768 22:11:30.395549 <4>[ 15.391903] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10769 22:11:30.402111 <3>[ 15.391915] Bluetooth: hci0: Failed to load firmware file (-2)
10770 22:11:30.405580 <3>[ 15.391919] Bluetooth: hci0: Failed to set up firmware (-2)
10771 22:11:30.418444 <4>[ 15.391922] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10772 22:11:30.428432 <6>[ 15.391980] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10773 22:11:30.434927 <6>[ 15.392058] usbcore: registered new interface driver uvcvideo
10774 22:11:30.438353 <6>[ 15.412595] r8152 2-1.3:1.0 eth0: v1.12.13
10775 22:11:30.448277 <6>[ 15.452961] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10776 22:11:30.454989 <6>[ 15.476912] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10777 22:11:30.458251 <6>[ 15.479428] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10778 22:11:30.485050 <6>[ 15.784732] mt7921e 0000:01:00.0: ASIC revision: 79610010
10779 22:11:30.592177 <4>[ 15.885386] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 22:11:30.595801 Begin: Loading essential drivers ... done.
10781 22:11:30.604045 Begin: Running /scripts/init-premount ... done.
10782 22:11:30.610553 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10783 22:11:30.620354 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10784 22:11:30.623709 Device /sys/class/net/enx00e04c722dd6 found
10785 22:11:30.623829 done.
10786 22:11:30.681490 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10787 22:11:30.710854 <4>[ 16.004008] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 22:11:30.826056 <4>[ 16.119250] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10789 22:11:30.941819 <4>[ 16.235022] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 22:11:31.057999 <4>[ 16.350915] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 22:11:31.173920 <4>[ 16.466888] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 22:11:31.289785 <4>[ 16.582801] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 22:11:31.406193 <4>[ 16.698749] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 22:11:31.521440 <4>[ 16.814697] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 22:11:31.637532 <4>[ 16.930682] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 22:11:31.711462 <6>[ 17.010925] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10797 22:11:31.744689 <3>[ 17.044551] mt7921e 0000:01:00.0: hardware init failed
10798 22:11:31.855152 IP-Config: no response after 2 secs - giving up
10799 22:11:31.897725 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10800 22:11:31.900916 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10801 22:11:31.907357 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10802 22:11:31.914036 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10803 22:11:31.920878 host : mt8192-asurada-spherion-r0-cbg-1
10804 22:11:31.927392 domain : lava-rack
10805 22:11:31.934104 rootserver: 192.168.201.1 rootpath:
10806 22:11:31.934189 filename :
10807 22:11:31.978213 done.
10808 22:11:31.985682 Begin: Running /scripts/nfs-bottom ... done.
10809 22:11:32.001602 Begin: Running /scripts/init-bottom ... done.
10810 22:11:33.175424 <6>[ 18.475155] NET: Registered PF_INET6 protocol family
10811 22:11:33.182016 <6>[ 18.481962] Segment Routing with IPv6
10812 22:11:33.185372 <6>[ 18.485920] In-situ OAM (IOAM) with IPv6
10813 22:11:33.293040 <30>[ 18.576383] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10814 22:11:33.300956 <30>[ 18.600790] systemd[1]: Detected architecture arm64.
10815 22:11:33.319791
10816 22:11:33.323470 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10817 22:11:33.323556
10818 22:11:33.339718 <30>[ 18.639846] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10819 22:11:34.116376 <30>[ 19.413311] systemd[1]: Queued start job for default target Graphical Interface.
10820 22:11:34.144416 <30>[ 19.444497] systemd[1]: Created slice system-getty.slice.
10821 22:11:34.150937 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10822 22:11:34.167254 <30>[ 19.467554] systemd[1]: Created slice system-modprobe.slice.
10823 22:11:34.174102 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10824 22:11:34.191242 <30>[ 19.491341] systemd[1]: Created slice system-serial\x2dgetty.slice.
10825 22:11:34.201694 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10826 22:11:34.214909 <30>[ 19.515134] systemd[1]: Created slice User and Session Slice.
10827 22:11:34.221628 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10828 22:11:34.242121 <30>[ 19.538843] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10829 22:11:34.252275 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10830 22:11:34.270189 <30>[ 19.566847] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10831 22:11:34.277314 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10832 22:11:34.300778 <30>[ 19.594224] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10833 22:11:34.307333 <30>[ 19.606371] systemd[1]: Reached target Local Encrypted Volumes.
10834 22:11:34.314138 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10835 22:11:34.330379 <30>[ 19.630524] systemd[1]: Reached target Paths.
10836 22:11:34.333933 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10837 22:11:34.350099 <30>[ 19.650085] systemd[1]: Reached target Remote File Systems.
10838 22:11:34.356708 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10839 22:11:34.374258 <30>[ 19.674461] systemd[1]: Reached target Slices.
10840 22:11:34.380818 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10841 22:11:34.393904 <30>[ 19.694092] systemd[1]: Reached target Swap.
10842 22:11:34.397309 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10843 22:11:34.417790 <30>[ 19.714624] systemd[1]: Listening on initctl Compatibility Named Pipe.
10844 22:11:34.424217 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10845 22:11:34.431109 <30>[ 19.730688] systemd[1]: Listening on Journal Audit Socket.
10846 22:11:34.437763 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10847 22:11:34.455305 <30>[ 19.755267] systemd[1]: Listening on Journal Socket (/dev/log).
10848 22:11:34.461881 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10849 22:11:34.478531 <30>[ 19.778658] systemd[1]: Listening on Journal Socket.
10850 22:11:34.485283 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10851 22:11:34.502805 <30>[ 19.799405] systemd[1]: Listening on Network Service Netlink Socket.
10852 22:11:34.509020 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10853 22:11:34.524388 <30>[ 19.824439] systemd[1]: Listening on udev Control Socket.
10854 22:11:34.530835 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10855 22:11:34.546531 <30>[ 19.846535] systemd[1]: Listening on udev Kernel Socket.
10856 22:11:34.552879 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10857 22:11:34.594143 <30>[ 19.894159] systemd[1]: Mounting Huge Pages File System...
10858 22:11:34.600776 Mounting [0;1;39mHuge Pages File System[0m...
10859 22:11:34.617926 <30>[ 19.917813] systemd[1]: Mounting POSIX Message Queue File System...
10860 22:11:34.624625 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10861 22:11:34.674990 <30>[ 19.974424] systemd[1]: Mounting Kernel Debug File System...
10862 22:11:34.680762 Mounting [0;1;39mKernel Debug File System[0m...
10863 22:11:34.697854 <30>[ 19.994668] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10864 22:11:34.711183 <30>[ 20.007833] systemd[1]: Starting Create list of static device nodes for the current kernel...
10865 22:11:34.717351 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10866 22:11:34.739097 <30>[ 20.039067] systemd[1]: Starting Load Kernel Module configfs...
10867 22:11:34.745461 Starting [0;1;39mLoad Kernel Module configfs[0m...
10868 22:11:34.767302 <30>[ 20.067315] systemd[1]: Starting Load Kernel Module drm...
10869 22:11:34.773902 Starting [0;1;39mLoad Kernel Module drm[0m...
10870 22:11:34.795257 <30>[ 20.095335] systemd[1]: Starting Load Kernel Module fuse...
10871 22:11:34.801704 Starting [0;1;39mLoad Kernel Module fuse[0m...
10872 22:11:34.835787 <30>[ 20.132676] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10873 22:11:34.843060 <6>[ 20.133125] fuse: init (API version 7.37)
10874 22:11:34.871319 <30>[ 20.170872] systemd[1]: Starting Journal Service...
10875 22:11:34.877230 Starting [0;1;39mJournal Service[0m...
10876 22:11:34.898619 <30>[ 20.198833] systemd[1]: Starting Load Kernel Modules...
10877 22:11:34.905535 Starting [0;1;39mLoad Kernel Modules[0m...
10878 22:11:34.926860 <30>[ 20.223501] systemd[1]: Starting Remount Root and Kernel File Systems...
10879 22:11:34.933632 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10880 22:11:34.951054 <30>[ 20.250825] systemd[1]: Starting Coldplug All udev Devices...
10881 22:11:34.957681 Starting [0;1;39mColdplug All udev Devices[0m...
10882 22:11:34.975282 <30>[ 20.275504] systemd[1]: Mounted Huge Pages File System.
10883 22:11:34.981867 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10884 22:11:35.000316 <3>[ 20.296914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 22:11:35.007160 <30>[ 20.307053] systemd[1]: Mounted POSIX Message Queue File System.
10886 22:11:35.013683 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10887 22:11:35.031027 <30>[ 20.330697] systemd[1]: Mounted Kernel Debug File System.
10888 22:11:35.041205 <3>[ 20.335151] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 22:11:35.047357 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10890 22:11:35.070694 <30>[ 20.366940] systemd[1]: Finished Create list of static device nodes for the current kernel.
10891 22:11:35.080543 <3>[ 20.372556] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 22:11:35.087416 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10893 22:11:35.104071 <30>[ 20.403867] systemd[1]: modprobe@configfs.service: Succeeded.
10894 22:11:35.114364 <3>[ 20.405184] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 22:11:35.120764 <30>[ 20.410651] systemd[1]: Finished Load Kernel Module configfs.
10896 22:11:35.127185 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10897 22:11:35.143657 <3>[ 20.440491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 22:11:35.151781 <30>[ 20.452026] systemd[1]: modprobe@drm.service: Succeeded.
10899 22:11:35.158966 <30>[ 20.458802] systemd[1]: Finished Load Kernel Module drm.
10900 22:11:35.165509 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10901 22:11:35.185073 <3>[ 20.481937] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 22:11:35.192278 <30>[ 20.492715] systemd[1]: modprobe@fuse.service: Succeeded.
10903 22:11:35.200016 <30>[ 20.499793] systemd[1]: Finished Load Kernel Module fuse.
10904 22:11:35.206120 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10905 22:11:35.223484 <30>[ 20.523483] systemd[1]: Finished Load Kernel Modules.
10906 22:11:35.233104 <3>[ 20.525149] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 22:11:35.239490 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10908 22:11:35.255365 <30>[ 20.555182] systemd[1]: Finished Remount Root and Kernel File Systems.
10909 22:11:35.265316 <3>[ 20.558783] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 22:11:35.271661 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10911 22:11:35.297232 <3>[ 20.594224] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 22:11:35.329168 <3>[ 20.625567] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 22:11:35.335575 <30>[ 20.626087] systemd[1]: Mounting FUSE Control File System...
10914 22:11:35.342075 Mounting [0;1;39mFUSE Control File System[0m...
10915 22:11:35.360988 <30>[ 20.658055] systemd[1]: Mounting Kernel Configuration File System...
10916 22:11:35.364406 Mounting [0;1;39mKernel Configuration File System[0m...
10917 22:11:35.392816 <30>[ 20.689610] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10918 22:11:35.402914 <30>[ 20.698706] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10919 22:11:35.443159 <30>[ 20.743171] systemd[1]: Starting Load/Save Random Seed...
10920 22:11:35.449546 Starting [0;1;39mLoad/Save Random Seed[0m...
10921 22:11:35.474179 <4>[ 20.764306] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10922 22:11:35.480840 <30>[ 20.764810] systemd[1]: Starting Apply Kernel Variables...
10923 22:11:35.487360 <3>[ 20.780009] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10924 22:11:35.494134 Starting [0;1;39mApply Kernel Variables[0m...
10925 22:11:35.514615 <30>[ 20.814649] systemd[1]: Starting Create System Users...
10926 22:11:35.521267 Starting [0;1;39mCreate System Users[0m...
10927 22:11:35.537258 <30>[ 20.837392] systemd[1]: Started Journal Service.
10928 22:11:35.543897 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10929 22:11:35.571525 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10930 22:11:35.586384 See 'systemctl status systemd-udev-trigger.service' for details.
10931 22:11:35.606976 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10932 22:11:35.626527 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10933 22:11:35.647691 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10934 22:11:35.663502 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10935 22:11:35.679803 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10936 22:11:35.734530 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10937 22:11:35.756749 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10938 22:11:35.789570 <46>[ 21.086692] systemd-journald[294]: Received client request to flush runtime journal.
10939 22:11:35.816022 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10940 22:11:35.831075 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10941 22:11:35.845969 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10942 22:11:35.903015 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10943 22:11:37.182195 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10944 22:11:37.226402 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10945 22:11:37.250534 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10946 22:11:37.271337 Starting [0;1;39mNetwork Service[0m...
10947 22:11:37.659201 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10948 22:11:37.691300 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10949 22:11:37.730520 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10950 22:11:37.927721 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10951 22:11:37.949751 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10952 22:11:37.982726 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10953 22:11:38.002527 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10954 22:11:38.026379 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10955 22:11:38.042889 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10956 22:11:38.069610 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10957 22:11:38.138741 Starting [0;1;39mNetwork Name Resolution[0m...
10958 22:11:38.166044 Starting [0;1;39mNetwork Time Synchronization[0m...
10959 22:11:38.187557 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10960 22:11:38.232781 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10961 22:11:38.361453 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10962 22:11:38.378066 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10963 22:11:38.396682 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10964 22:11:38.409848 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10965 22:11:38.424282 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10966 22:11:38.568267 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10967 22:11:38.603966 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10968 22:11:38.632939 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10969 22:11:38.659158 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10970 22:11:38.677659 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10971 22:11:38.708554 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10972 22:11:38.722597 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10973 22:11:38.737924 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10974 22:11:38.798789 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10975 22:11:39.486236 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10976 22:11:39.843573 Starting [0;1;39mUser Login Management[0m...
10977 22:11:39.860231 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10978 22:11:39.881868 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10979 22:11:39.901376 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10980 22:11:39.955616 Starting [0;1;39mPermit User Sessions[0m...
10981 22:11:40.078533 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10982 22:11:40.110419 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10983 22:11:40.129507 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10984 22:11:40.151189 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10985 22:11:40.173611 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10986 22:11:40.192485 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10987 22:11:40.216251 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10988 22:11:40.238957 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10989 22:11:40.285242 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10990 22:11:40.330683 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10991 22:11:40.437967
10992 22:11:40.438081
10993 22:11:40.441219 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10994 22:11:40.441302
10995 22:11:40.444462 debian-bullseye-arm64 login: root (automatic login)
10996 22:11:40.444599
10997 22:11:40.444694
10998 22:11:40.718695 Linux debian-bullseye-arm64 6.1.46-cip4 #1 SMP PREEMPT Tue Sep 5 21:54:53 UTC 2023 aarch64
10999 22:11:40.718908
11000 22:11:40.725089 The programs included with the Debian GNU/Linux system are free software;
11001 22:11:40.732100 the exact distribution terms for each program are described in the
11002 22:11:40.735138 individual files in /usr/share/doc/*/copyright.
11003 22:11:40.735221
11004 22:11:40.741614 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11005 22:11:40.744871 permitted by applicable law.
11006 22:11:40.786722 Matched prompt #10: / #
11008 22:11:40.786941 Setting prompt string to ['/ #']
11009 22:11:40.787036 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11011 22:11:40.787231 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11012 22:11:40.787319 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
11013 22:11:40.787388 Setting prompt string to ['/ #']
11014 22:11:40.787447 Forcing a shell prompt, looking for ['/ #']
11016 22:11:40.837655 / #
11017 22:11:40.837755 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11018 22:11:40.837829 Waiting using forced prompt support (timeout 00:02:30)
11019 22:11:40.842433
11020 22:11:40.842734 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11021 22:11:40.842825 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
11023 22:11:40.943173 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11440304/extract-nfsrootfs-i13_qaj1'
11024 22:11:40.948316 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11440304/extract-nfsrootfs-i13_qaj1'
11026 22:11:41.048829 / # export NFS_SERVER_IP='192.168.201.1'
11027 22:11:41.053950 export NFS_SERVER_IP='192.168.201.1'
11028 22:11:41.054231 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11029 22:11:41.054329 end: 2.2 depthcharge-retry (duration 00:01:29) [common]
11030 22:11:41.054417 end: 2 depthcharge-action (duration 00:01:29) [common]
11031 22:11:41.054506 start: 3 lava-test-retry (timeout 00:01:00) [common]
11032 22:11:41.054590 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11033 22:11:41.054663 Using namespace: common
11035 22:11:41.154956 / # #
11036 22:11:41.155064 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11037 22:11:41.160494 #
11038 22:11:41.160781 Using /lava-11440304
11040 22:11:41.261096 / # export SHELL=/bin/sh
11041 22:11:41.266185 export SHELL=/bin/sh
11043 22:11:41.366726 / # . /lava-11440304/environment
11044 22:11:41.372002 . /lava-11440304/environment
11046 22:11:41.476919 / # /lava-11440304/bin/lava-test-runner /lava-11440304/0
11047 22:11:41.477026 Test shell timeout: 10s (minimum of the action and connection timeout)
11048 22:11:41.482021 /lava-11440304/bin/lava-test-runner /lava-11440304/0
11049 22:11:41.682173 + export TESTRUN_ID=0_dmesg
11050 22:11:41.685639 + cd /lava-11440304/0/tests/0_dmesg
11051 22:11:41.688540 + cat uuid
11052 22:11:41.698820 + UUID=11440304_<8>[ 26.995950] <LAVA_SIGNAL_STARTRUN 0_dmesg 11440304_1.6.2.3.1>
11053 22:11:41.698906 1.6.2.3.1
11054 22:11:41.698973 + set +x
11055 22:11:41.699214 Received signal: <STARTRUN> 0_dmesg 11440304_1.6.2.3.1
11056 22:11:41.699286 Starting test lava.0_dmesg (11440304_1.6.2.3.1)
11057 22:11:41.699370 Skipping test definition patterns.
11058 22:11:41.705532 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11059 22:11:41.778710 <8>[ 27.076456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11060 22:11:41.779018 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11062 22:11:41.829275 <8>[ 27.126901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11063 22:11:41.829591 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11065 22:11:41.881221 <8>[ 27.178937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11066 22:11:41.881484 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11068 22:11:41.885014 + set +x
11069 22:11:41.888237 <8>[ 27.188618] <LAVA_SIGNAL_ENDRUN 0_dmesg 11440304_1.6.2.3.1>
11070 22:11:41.888490 Received signal: <ENDRUN> 0_dmesg 11440304_1.6.2.3.1
11071 22:11:41.888575 Ending use of test pattern.
11072 22:11:41.888637 Ending test lava.0_dmesg (11440304_1.6.2.3.1), duration 0.19
11074 22:11:41.893021 <LAVA_TEST_RUNNER EXIT>
11075 22:11:41.893291 ok: lava_test_shell seems to have completed
11076 22:11:41.893394 alert: pass
crit: pass
emerg: pass
11077 22:11:41.893484 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11078 22:11:41.893566 end: 3 lava-test-retry (duration 00:00:01) [common]
11079 22:11:41.893647 start: 4 lava-test-retry (timeout 00:01:00) [common]
11080 22:11:41.893727 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11081 22:11:41.893791 Using namespace: common
11083 22:11:41.994105 / # #
11084 22:11:41.994283 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11085 22:11:41.994402 Using /lava-11440304
11087 22:11:42.094695 export SHELL=/bin/sh
11088 22:11:42.094835 #
11090 22:11:42.195371 / # export SHELL=/bin/sh. /lava-11440304/environment
11091 22:11:42.195507
11093 22:11:42.296043 / # . /lava-11440304/environment/lava-11440304/bin/lava-test-runner /lava-11440304/1
11094 22:11:42.296157 Test shell timeout: 10s (minimum of the action and connection timeout)
11095 22:11:42.296282
11096 22:11:42.301447 / # /lava-11440304/bin/lava-test-runner /lava-11440304/1
11097 22:11:42.396666 + export TESTRUN_ID=1_bootrr
11098 22:11:42.400318 + cd /lava-11440304/1/tests/1_bootrr
11099 22:11:42.403361 + cat uuid
11100 22:11:42.410206 + UUID=11440304_1.<8>[ 27.710014] <LAVA_SIGNAL_STARTRUN 1_bootrr 11440304_1.6.2.3.5>
11101 22:11:42.410464 Received signal: <STARTRUN> 1_bootrr 11440304_1.6.2.3.5
11102 22:11:42.410536 Starting test lava.1_bootrr (11440304_1.6.2.3.5)
11103 22:11:42.410651 Skipping test definition patterns.
11104 22:11:42.413462 6.2.3.5
11105 22:11:42.413547 + set +x
11106 22:11:42.423413 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11440304/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11107 22:11:42.426357 + cd /opt/bootrr/libexec/bootrr
11108 22:11:42.430104 + sh helpers/bootrr-auto
11109 22:11:42.471490 /lava-11440304/1/../bin/lava-test-case
11110 22:11:42.495786 <8>[ 27.793366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11111 22:11:42.496047 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11113 22:11:42.528314 /lava-11440304/1/../bin/lava-test-case
11114 22:11:42.551640 <8>[ 27.849488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11115 22:11:42.551969 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11117 22:11:42.572000 /lava-11440304/1/../bin/lava-test-case
11118 22:11:42.591193 <8>[ 27.888817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11119 22:11:42.591448 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11121 22:11:42.636675 /lava-11440304/1/../bin/lava-test-case
11122 22:11:42.656360 <8>[ 27.954152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11123 22:11:42.656624 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11125 22:11:42.684619 /lava-11440304/1/../bin/lava-test-case
11126 22:11:42.707751 <8>[ 28.005692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11127 22:11:42.708013 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11129 22:11:42.739286 /lava-11440304/1/../bin/lava-test-case
11130 22:11:42.763733 <8>[ 28.061500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11131 22:11:42.764008 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11133 22:11:42.794483 /lava-11440304/1/../bin/lava-test-case
11134 22:11:42.815629 <8>[ 28.112972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11135 22:11:42.815945 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11137 22:11:42.842659 /lava-11440304/1/../bin/lava-test-case
11138 22:11:42.865300 <8>[ 28.163005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11139 22:11:42.865562 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11141 22:11:42.885267 /lava-11440304/1/../bin/lava-test-case
11142 22:11:42.907513 <8>[ 28.205456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11143 22:11:42.907818 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11145 22:11:42.935072 /lava-11440304/1/../bin/lava-test-case
11146 22:11:42.958936 <8>[ 28.256802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11147 22:11:42.959247 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11149 22:11:42.977258 /lava-11440304/1/../bin/lava-test-case
11150 22:11:42.996001 <8>[ 28.293949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11151 22:11:42.996302 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11153 22:11:43.024275 /lava-11440304/1/../bin/lava-test-case
11154 22:11:43.046036 <8>[ 28.343768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11155 22:11:43.046347 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11157 22:11:43.084682 /lava-11440304/1/../bin/lava-test-case
11158 22:11:43.103610 <8>[ 28.401464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11159 22:11:43.103916 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11161 22:11:43.127456 /lava-11440304/1/../bin/lava-test-case
11162 22:11:43.147206 <8>[ 28.445061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11163 22:11:43.147491 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11165 22:11:43.175702 /lava-11440304/1/../bin/lava-test-case
11166 22:11:43.196049 <8>[ 28.493732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11167 22:11:43.196306 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11169 22:11:43.214295 /lava-11440304/1/../bin/lava-test-case
11170 22:11:43.234009 <8>[ 28.531635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11171 22:11:43.234264 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11173 22:11:43.261943 /lava-11440304/1/../bin/lava-test-case
11174 22:11:43.284054 <8>[ 28.581401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11175 22:11:43.284314 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11177 22:11:43.299644 /lava-11440304/1/../bin/lava-test-case
11178 22:11:43.321051 <8>[ 28.618826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11179 22:11:43.321323 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11181 22:11:43.362367 /lava-11440304/1/../bin/lava-test-case
11182 22:11:43.387356 <8>[ 28.685210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11183 22:11:43.387618 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11185 22:11:43.407507 /lava-11440304/1/../bin/lava-test-case
11186 22:11:43.430517 <8>[ 28.728478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11187 22:11:43.430775 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11189 22:11:43.460455 /lava-11440304/1/../bin/lava-test-case
11190 22:11:43.482512 <8>[ 28.780208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11191 22:11:43.482770 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11193 22:11:43.502417 /lava-11440304/1/../bin/lava-test-case
11194 22:11:43.524261 <8>[ 28.822362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11195 22:11:43.524523 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11197 22:11:43.554756 /lava-11440304/1/../bin/lava-test-case
11198 22:11:43.579979 <8>[ 28.877904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11199 22:11:43.580234 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11201 22:11:43.599355 /lava-11440304/1/../bin/lava-test-case
11202 22:11:43.621913 <8>[ 28.919875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11203 22:11:43.622170 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11205 22:11:43.649497 /lava-11440304/1/../bin/lava-test-case
11206 22:11:43.673563 <8>[ 28.971624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11207 22:11:43.673822 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11209 22:11:43.708309 /lava-11440304/1/../bin/lava-test-case
11210 22:11:43.726906 <8>[ 29.024768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11211 22:11:43.727191 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11213 22:11:43.744511 /lava-11440304/1/../bin/lava-test-case
11214 22:11:43.763958 <8>[ 29.061833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11215 22:11:43.764212 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11217 22:11:43.791805 /lava-11440304/1/../bin/lava-test-case
11218 22:11:43.813044 <8>[ 29.110861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11219 22:11:43.813305 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11221 22:11:43.829212 /lava-11440304/1/../bin/lava-test-case
11222 22:11:43.851712 <8>[ 29.149721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11223 22:11:43.852040 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11225 22:11:43.880238 /lava-11440304/1/../bin/lava-test-case
11226 22:11:43.903508 <8>[ 29.200915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11227 22:11:43.903818 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11229 22:11:43.928273 /lava-11440304/1/../bin/lava-test-case
11230 22:11:43.951434 <8>[ 29.249263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11231 22:11:43.951728 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11233 22:11:43.976941 /lava-11440304/1/../bin/lava-test-case
11234 22:11:43.996216 <8>[ 29.294329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11235 22:11:43.996472 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11237 22:11:44.032189 /lava-11440304/1/../bin/lava-test-case
11238 22:11:44.052881 <8>[ 29.350825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11239 22:11:44.053145 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11241 22:11:44.071730 /lava-11440304/1/../bin/lava-test-case
11242 22:11:44.091790 <8>[ 29.389784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11243 22:11:44.092048 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11245 22:11:44.116928 /lava-11440304/1/../bin/lava-test-case
11246 22:11:44.139512 <8>[ 29.437696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11247 22:11:44.139780 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11249 22:11:44.164528 /lava-11440304/1/../bin/lava-test-case
11250 22:11:44.183839 <8>[ 29.482026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11251 22:11:44.184145 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11253 22:11:44.202789 /lava-11440304/1/../bin/lava-test-case
11254 22:11:44.223059 <8>[ 29.521107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11255 22:11:44.223362 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11257 22:11:44.249834 /lava-11440304/1/../bin/lava-test-case
11258 22:11:44.271012 <8>[ 29.568956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11259 22:11:44.271322 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11261 22:11:44.288780 /lava-11440304/1/../bin/lava-test-case
11262 22:11:44.312403 <8>[ 29.610633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11263 22:11:44.312698 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11265 22:11:44.349135 /lava-11440304/1/../bin/lava-test-case
11266 22:11:44.368548 <8>[ 29.666209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11267 22:11:44.368853 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11269 22:11:44.386065 /lava-11440304/1/../bin/lava-test-case
11270 22:11:44.404925 <8>[ 29.703016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11271 22:11:44.405229 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11273 22:11:44.431823 /lava-11440304/1/../bin/lava-test-case
11274 22:11:44.450057 <8>[ 29.748160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11275 22:11:44.450314 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11277 22:11:44.470428 /lava-11440304/1/../bin/lava-test-case
11278 22:11:44.489036 <8>[ 29.787058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11279 22:11:44.489292 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11281 22:11:44.518150 /lava-11440304/1/../bin/lava-test-case
11282 22:11:44.542139 <8>[ 29.839998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11283 22:11:44.542450 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11285 22:11:44.560338 /lava-11440304/1/../bin/lava-test-case
11286 22:11:44.581765 <8>[ 29.879536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11287 22:11:44.582069 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11289 22:11:44.606878 /lava-11440304/1/../bin/lava-test-case
11290 22:11:44.628351 <8>[ 29.926178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11291 22:11:44.628605 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11293 22:11:44.651493 /lava-11440304/1/../bin/lava-test-case
11294 22:11:44.671146 <8>[ 29.969192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11295 22:11:44.671416 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11297 22:11:44.701382 /lava-11440304/1/../bin/lava-test-case
11298 22:11:44.726443 <8>[ 30.024692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11299 22:11:44.726751 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11301 22:11:44.746570 /lava-11440304/1/../bin/lava-test-case
11302 22:11:44.768922 <8>[ 30.066705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11303 22:11:44.769229 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11305 22:11:44.797195 /lava-11440304/1/../bin/lava-test-case
11306 22:11:44.820560 <8>[ 30.118647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11307 22:11:44.820864 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11309 22:11:44.847335 /lava-11440304/1/../bin/lava-test-case
11310 22:11:44.868687 <8>[ 30.166296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11311 22:11:44.869035 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11313 22:11:44.887803 /lava-11440304/1/../bin/lava-test-case
11314 22:11:44.912944 <8>[ 30.211086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11315 22:11:44.913256 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11317 22:11:44.947185 /lava-11440304/1/../bin/lava-test-case
11318 22:11:44.971781 <8>[ 30.270082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11319 22:11:44.972062 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11321 22:11:44.999208 /lava-11440304/1/../bin/lava-test-case
11322 22:11:45.021556 <8>[ 30.319586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11323 22:11:45.021820 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11325 22:11:45.050546 /lava-11440304/1/../bin/lava-test-case
11326 22:11:45.073655 <8>[ 30.371479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11327 22:11:45.073912 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11329 22:11:45.099444 /lava-11440304/1/../bin/lava-test-case
11330 22:11:45.119939 <8>[ 30.418182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11331 22:11:45.120244 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11333 22:11:45.146978 /lava-11440304/1/../bin/lava-test-case
11334 22:11:45.169743 <8>[ 30.467858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11335 22:11:45.170000 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11337 22:11:45.196388 /lava-11440304/1/../bin/lava-test-case
11338 22:11:45.216878 <8>[ 30.515009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11339 22:11:45.217183 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11341 22:11:45.244340 /lava-11440304/1/../bin/lava-test-case
11342 22:11:45.264589 <8>[ 30.562839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11343 22:11:45.264862 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11345 22:11:45.281394 /lava-11440304/1/../bin/lava-test-case
11346 22:11:45.299775 <8>[ 30.597915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11347 22:11:45.300029 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11349 22:11:45.331946 /lava-11440304/1/../bin/lava-test-case
11350 22:11:45.350655 <8>[ 30.648827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11351 22:11:45.350929 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11353 22:11:45.377311 /lava-11440304/1/../bin/lava-test-case
11354 22:11:45.397173 <8>[ 30.695536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11355 22:11:45.397430 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11357 22:11:45.415025 /lava-11440304/1/../bin/lava-test-case
11358 22:11:45.434433 <8>[ 30.732494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11359 22:11:45.434748 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11361 22:11:45.465677 /lava-11440304/1/../bin/lava-test-case
11362 22:11:45.487997 <8>[ 30.786060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11363 22:11:45.488264 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11365 22:11:45.506139 /lava-11440304/1/../bin/lava-test-case
11366 22:11:45.526424 <8>[ 30.824685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11367 22:11:45.526706 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11369 22:11:45.556654 /lava-11440304/1/../bin/lava-test-case
11370 22:11:45.582597 <8>[ 30.880554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11371 22:11:45.582858 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11373 22:11:45.600209 /lava-11440304/1/../bin/lava-test-case
11374 22:11:45.623734 <8>[ 30.921851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11375 22:11:45.623996 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11377 22:11:45.660480 /lava-11440304/1/../bin/lava-test-case
11378 22:11:45.684697 <8>[ 30.983052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11379 22:11:45.684999 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11381 22:11:45.713897 /lava-11440304/1/../bin/lava-test-case
11382 22:11:45.735515 <8>[ 31.033802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11383 22:11:45.735769 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11385 22:11:45.763473 /lava-11440304/1/../bin/lava-test-case
11386 22:11:45.788121 <8>[ 31.086341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11387 22:11:45.788380 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11389 22:11:45.815808 /lava-11440304/1/../bin/lava-test-case
11390 22:11:45.837155 <8>[ 31.135196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11391 22:11:45.837410 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11393 22:11:45.863495 /lava-11440304/1/../bin/lava-test-case
11394 22:11:45.886823 <8>[ 31.185119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11395 22:11:45.887079 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11397 22:11:45.916413 /lava-11440304/1/../bin/lava-test-case
11398 22:11:45.936634 <8>[ 31.234675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11399 22:11:45.936892 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11401 22:11:45.971205 /lava-11440304/1/../bin/lava-test-case
11402 22:11:45.992395 <8>[ 31.290342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11403 22:11:45.992690 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11405 22:11:46.025285 /lava-11440304/1/../bin/lava-test-case
11406 22:11:46.047802 <8>[ 31.345948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11407 22:11:46.048061 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11409 22:11:46.078128 /lava-11440304/1/../bin/lava-test-case
11410 22:11:46.101069 <8>[ 31.398934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11411 22:11:46.101378 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11413 22:11:46.130246 /lava-11440304/1/../bin/lava-test-case
11414 22:11:46.155562 <8>[ 31.453938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11415 22:11:46.155823 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11417 22:11:46.185525 /lava-11440304/1/../bin/lava-test-case
11418 22:11:46.211210 <8>[ 31.509542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11419 22:11:46.211466 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11421 22:11:46.239878 /lava-11440304/1/../bin/lava-test-case
11422 22:11:46.261797 <8>[ 31.559756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11423 22:11:46.262055 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11425 22:11:46.296618 /lava-11440304/1/../bin/lava-test-case
11426 22:11:46.315979 <8>[ 31.613887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11427 22:11:46.316267 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11429 22:11:46.344669 /lava-11440304/1/../bin/lava-test-case
11430 22:11:46.367879 <8>[ 31.665821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11431 22:11:46.368198 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11433 22:11:46.392060 /lava-11440304/1/../bin/lava-test-case
11434 22:11:46.414563 <8>[ 31.712790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11435 22:11:46.414870 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11437 22:11:46.432407 /lava-11440304/1/../bin/lava-test-case
11438 22:11:46.451849 <8>[ 31.750029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11439 22:11:46.452160 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11441 22:11:46.478508 /lava-11440304/1/../bin/lava-test-case
11442 22:11:46.500463 <8>[ 31.798623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11443 22:11:46.500818 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11445 22:11:46.517757 /lava-11440304/1/../bin/lava-test-case
11446 22:11:46.538466 <8>[ 31.836671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11447 22:11:46.538772 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11449 22:11:46.568133 /lava-11440304/1/../bin/lava-test-case
11450 22:11:46.590671 <8>[ 31.888996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11451 22:11:46.590932 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11453 22:11:46.618203 /lava-11440304/1/../bin/lava-test-case
11454 22:11:46.640411 <8>[ 31.938810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11455 22:11:46.640669 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11457 22:11:46.671405 /lava-11440304/1/../bin/lava-test-case
11458 22:11:46.693843 <8>[ 31.992078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11459 22:11:46.694103 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11461 22:11:46.713368 /lava-11440304/1/../bin/lava-test-case
11462 22:11:46.734652 <8>[ 32.032934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11463 22:11:46.734907 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11465 22:11:46.762210 /lava-11440304/1/../bin/lava-test-case
11466 22:11:46.783246 <8>[ 32.081715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11467 22:11:46.783503 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11469 22:11:46.801161 /lava-11440304/1/../bin/lava-test-case
11470 22:11:46.822660 <8>[ 32.121001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11471 22:11:46.822926 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11473 22:11:46.848169 /lava-11440304/1/../bin/lava-test-case
11474 22:11:46.869176 <8>[ 32.167514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11475 22:11:46.869494 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11477 22:11:46.890492 /lava-11440304/1/../bin/lava-test-case
11478 22:11:46.912224 <8>[ 32.210182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11479 22:11:46.912526 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11481 22:11:46.949798 /lava-11440304/1/../bin/lava-test-case
11482 22:11:46.970683 <8>[ 32.268949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11483 22:11:46.970943 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11485 22:11:46.999495 /lava-11440304/1/../bin/lava-test-case
11486 22:11:47.019439 <8>[ 32.317809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11487 22:11:47.019707 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11489 22:11:47.037703 /lava-11440304/1/../bin/lava-test-case
11490 22:11:47.056955 <8>[ 32.355112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11491 22:11:47.057270 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11493 22:11:47.083040 /lava-11440304/1/../bin/lava-test-case
11494 22:11:47.102324 <8>[ 32.400773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11495 22:11:47.102580 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11497 22:11:47.124592 /lava-11440304/1/../bin/lava-test-case
11498 22:11:47.147266 <8>[ 32.445258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11499 22:11:47.147524 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11501 22:11:47.178609 /lava-11440304/1/../bin/lava-test-case
11502 22:11:47.207489 <8>[ 32.505570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11503 22:11:47.207748 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11505 22:11:47.226403 /lava-11440304/1/../bin/lava-test-case
11506 22:11:47.251530 <8>[ 32.549775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11507 22:11:47.251787 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11509 22:11:48.304669 /lava-11440304/1/../bin/lava-test-case
11510 22:11:48.329576 <8>[ 33.627762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11511 22:11:48.329847 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11513 22:11:48.346965 /lava-11440304/1/../bin/lava-test-case
11514 22:11:48.368328 <8>[ 33.666542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11515 22:11:48.368594 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11517 22:11:49.403930 /lava-11440304/1/../bin/lava-test-case
11518 22:11:49.429649 <8>[ 34.728260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11519 22:11:49.429931 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11521 22:11:49.450838 /lava-11440304/1/../bin/lava-test-case
11522 22:11:49.475071 <8>[ 34.773691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11523 22:11:49.475391 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11525 22:11:50.515596 /lava-11440304/1/../bin/lava-test-case
11526 22:11:50.537363 <8>[ 35.836218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11527 22:11:50.537642 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11529 22:11:50.558930 /lava-11440304/1/../bin/lava-test-case
11530 22:11:50.576592 <8>[ 35.875066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11531 22:11:50.576846 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11533 22:11:51.610712 /lava-11440304/1/../bin/lava-test-case
11534 22:11:51.638670 <8>[ 36.937550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11535 22:11:51.638943 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11537 22:11:51.655891 /lava-11440304/1/../bin/lava-test-case
11538 22:11:51.674878 <8>[ 36.973993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11539 22:11:51.675137 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11541 22:11:52.706630 /lava-11440304/1/../bin/lava-test-case
11542 22:11:52.733667 <8>[ 38.032776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11543 22:11:52.733942 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11545 22:11:52.752431 /lava-11440304/1/../bin/lava-test-case
11546 22:11:52.774647 <8>[ 38.073303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11547 22:11:52.774913 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11549 22:11:53.816255 /lava-11440304/1/../bin/lava-test-case
11550 22:11:53.844051 <8>[ 39.143059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11551 22:11:53.844332 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11553 22:11:53.862373 /lava-11440304/1/../bin/lava-test-case
11554 22:11:53.882081 <8>[ 39.181332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11555 22:11:53.882338 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11557 22:11:54.915906 /lava-11440304/1/../bin/lava-test-case
11558 22:11:54.940765 <8>[ 40.240171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11559 22:11:54.941061 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11561 22:11:54.959310 /lava-11440304/1/../bin/lava-test-case
11562 22:11:54.981740 <8>[ 40.280750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11563 22:11:54.982003 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11565 22:11:55.002704 /lava-11440304/1/../bin/lava-test-case
11566 22:11:55.024515 <8>[ 40.323600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11567 22:11:55.024774 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11569 22:11:56.060165 /lava-11440304/1/../bin/lava-test-case
11570 22:11:56.089606 <8>[ 41.388763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11571 22:11:56.089949 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11573 22:11:56.108587 /lava-11440304/1/../bin/lava-test-case
11574 22:11:56.128904 <8>[ 41.428167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11575 22:11:56.129177 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11577 22:11:56.154752 /lava-11440304/1/../bin/lava-test-case
11578 22:11:56.174529 <8>[ 41.473952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11579 22:11:56.174797 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11581 22:11:56.193013 /lava-11440304/1/../bin/lava-test-case
11582 22:11:56.213924 <8>[ 41.513239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11583 22:11:56.214183 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11585 22:11:56.240370 /lava-11440304/1/../bin/lava-test-case
11586 22:11:56.260167 <8>[ 41.559536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11587 22:11:56.260428 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11589 22:11:56.286622 /lava-11440304/1/../bin/lava-test-case
11590 22:11:56.309788 <8>[ 41.609320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11591 22:11:56.310050 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11593 22:11:56.338489 /lava-11440304/1/../bin/lava-test-case
11594 22:11:56.358887 <8>[ 41.658227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11595 22:11:56.359148 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11597 22:11:56.385479 /lava-11440304/1/../bin/lava-test-case
11598 22:11:56.406533 <8>[ 41.705818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11599 22:11:56.406795 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11601 22:11:56.437350 /lava-11440304/1/../bin/lava-test-case
11602 22:11:56.457512 <8>[ 41.757055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11603 22:11:56.457776 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11605 22:11:56.483512 /lava-11440304/1/../bin/lava-test-case
11606 22:11:56.505023 <8>[ 41.803974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11607 22:11:56.505291 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11609 22:11:56.521517 /lava-11440304/1/../bin/lava-test-case
11610 22:11:56.545641 <8>[ 41.844646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11611 22:11:56.545928 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11613 22:11:56.574731 /lava-11440304/1/../bin/lava-test-case
11614 22:11:56.599669 <8>[ 41.899174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11615 22:11:56.599934 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11617 22:11:56.619599 /lava-11440304/1/../bin/lava-test-case
11618 22:11:56.639202 <8>[ 41.938761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11619 22:11:56.639459 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11621 22:11:56.665837 /lava-11440304/1/../bin/lava-test-case
11622 22:11:56.689197 <8>[ 41.988922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11623 22:11:56.689458 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11625 22:11:56.716121 /lava-11440304/1/../bin/lava-test-case
11626 22:11:56.739070 <8>[ 42.038139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11627 22:11:56.739327 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11629 22:11:56.766871 /lava-11440304/1/../bin/lava-test-case
11630 22:11:56.789411 <8>[ 42.088881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11631 22:11:56.789695 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11633 22:11:56.806721 /lava-11440304/1/../bin/lava-test-case
11634 22:11:56.831091 <8>[ 42.130382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11635 22:11:56.831347 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11637 22:11:56.859455 /lava-11440304/1/../bin/lava-test-case
11638 22:11:56.878848 <8>[ 42.178282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11639 22:11:56.879104 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11641 22:11:56.901733 /lava-11440304/1/../bin/lava-test-case
11642 22:11:56.924709 <8>[ 42.224416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11643 22:11:56.925020 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11645 22:11:56.953662 /lava-11440304/1/../bin/lava-test-case
11646 22:11:56.974673 <8>[ 42.274037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11647 22:11:56.974933 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11649 22:11:56.993967 /lava-11440304/1/../bin/lava-test-case
11650 22:11:57.014705 <8>[ 42.314134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11651 22:11:57.014960 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11653 22:11:58.066109 /lava-11440304/1/../bin/lava-test-case
11654 22:11:58.090468 <8>[ 43.390269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11655 22:11:58.090743 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11657 22:11:59.127280 /lava-11440304/1/../bin/lava-test-case
11658 22:11:59.153805 <8>[ 44.453729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11659 22:11:59.154077 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11661 22:11:59.173067 /lava-11440304/1/../bin/lava-test-case
11662 22:11:59.197036 <8>[ 44.496903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11663 22:11:59.197332 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11665 22:11:59.226520 /lava-11440304/1/../bin/lava-test-case
11666 22:11:59.250325 <8>[ 44.549753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11667 22:11:59.250581 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11669 22:11:59.266968 /lava-11440304/1/../bin/lava-test-case
11670 22:11:59.293582 <8>[ 44.593069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11671 22:11:59.293846 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11673 22:11:59.323043 /lava-11440304/1/../bin/lava-test-case
11674 22:11:59.347205 <8>[ 44.646999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11675 22:11:59.347467 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11677 22:11:59.367943 /lava-11440304/1/../bin/lava-test-case
11678 22:11:59.392223 <8>[ 44.692086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11679 22:11:59.392481 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11681 22:11:59.418915 /lava-11440304/1/../bin/lava-test-case
11682 22:11:59.440671 <8>[ 44.740669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11683 22:11:59.440976 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11685 22:11:59.468146 /lava-11440304/1/../bin/lava-test-case
11686 22:11:59.489476 <8>[ 44.789489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11687 22:11:59.489745 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11689 22:11:59.518073 /lava-11440304/1/../bin/lava-test-case
11690 22:11:59.540654 <8>[ 44.840101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11691 22:11:59.540913 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11693 22:11:59.558223 /lava-11440304/1/../bin/lava-test-case
11694 22:11:59.579966 <8>[ 44.879862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11695 22:11:59.580255 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11697 22:11:59.609466 /lava-11440304/1/../bin/lava-test-case
11698 22:11:59.631030 <8>[ 44.930744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11699 22:11:59.631301 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11701 22:11:59.647093 /lava-11440304/1/../bin/lava-test-case
11702 22:11:59.665529 <8>[ 44.965100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11703 22:11:59.665785 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11705 22:11:59.688578 /lava-11440304/1/../bin/lava-test-case
11706 22:11:59.706639 <8>[ 45.006294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11707 22:11:59.706898 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11709 22:11:59.725166 /lava-11440304/1/../bin/lava-test-case
11710 22:11:59.745328 <8>[ 45.045234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11711 22:11:59.745585 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11713 22:11:59.781850 /lava-11440304/1/../bin/lava-test-case
11714 22:11:59.802318 <8>[ 45.101975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11715 22:11:59.802576 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11717 22:11:59.818560 /lava-11440304/1/../bin/lava-test-case
11718 22:11:59.837943 <8>[ 45.137740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11719 22:11:59.838197 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11721 22:11:59.863377 /lava-11440304/1/../bin/lava-test-case
11722 22:11:59.882207 <8>[ 45.182095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11723 22:11:59.882464 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11725 22:11:59.896415 /lava-11440304/1/../bin/lava-test-case
11726 22:11:59.916188 <8>[ 45.215865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11727 22:11:59.916442 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11729 22:11:59.941349 /lava-11440304/1/../bin/lava-test-case
11730 22:11:59.962279 <8>[ 45.262032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11731 22:11:59.962547 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11733 22:11:59.985749 /lava-11440304/1/../bin/lava-test-case
11734 22:12:00.007282 <8>[ 45.307179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11735 22:12:00.007537 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11737 22:12:00.038134 /lava-11440304/1/../bin/lava-test-case
11738 22:12:00.058612 <8>[ 45.358474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11739 22:12:00.058871 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11741 22:12:00.851716 <6>[ 46.158276] vpu: disabling
11742 22:12:00.854872 <6>[ 46.161394] vproc2: disabling
11743 22:12:00.858155 <6>[ 46.164824] vproc1: disabling
11744 22:12:00.861855 <6>[ 46.168132] vaud18: disabling
11745 22:12:00.868567 <6>[ 46.171642] vsram_others: disabling
11746 22:12:00.871592 <6>[ 46.175604] va09: disabling
11747 22:12:00.874804 <6>[ 46.178769] vsram_md: disabling
11748 22:12:00.878708 <6>[ 46.182328] Vgpu: disabling
11749 22:12:01.093626 /lava-11440304/1/../bin/lava-test-case
11750 22:12:01.121619 <8>[ 46.421307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11751 22:12:01.121948 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11753 22:12:02.162143 /lava-11440304/1/../bin/lava-test-case
11754 22:12:02.185571 <8>[ 47.485690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11755 22:12:02.185860 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11756 22:12:02.185961 Bad test result: blocked
11757 22:12:02.204833 /lava-11440304/1/../bin/lava-test-case
11758 22:12:02.226991 <8>[ 47.527100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11759 22:12:02.227300 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11761 22:12:03.267325 /lava-11440304/1/../bin/lava-test-case
11762 22:12:03.293148 <8>[ 48.593388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11763 22:12:03.293484 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11765 22:12:03.310862 /lava-11440304/1/../bin/lava-test-case
11766 22:12:03.333408 <8>[ 48.633505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11767 22:12:03.333721 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11769 22:12:03.359127 /lava-11440304/1/../bin/lava-test-case
11770 22:12:03.378940 <8>[ 48.679222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11771 22:12:03.379256 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11773 22:12:03.403158 /lava-11440304/1/../bin/lava-test-case
11774 22:12:03.422617 <8>[ 48.722758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11775 22:12:03.422927 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11777 22:12:03.440185 /lava-11440304/1/../bin/lava-test-case
11778 22:12:03.461653 <8>[ 48.762033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11779 22:12:03.461962 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11781 22:12:03.486880 /lava-11440304/1/../bin/lava-test-case
11782 22:12:03.505698 <8>[ 48.806025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11783 22:12:03.505959 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11785 22:12:03.523142 /lava-11440304/1/../bin/lava-test-case
11786 22:12:03.543857 <8>[ 48.844258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11787 22:12:03.544112 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11789 22:12:04.591533 /lava-11440304/1/../bin/lava-test-case
11790 22:12:04.617399 <8>[ 49.917838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11791 22:12:04.617729 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11793 22:12:04.634578 /lava-11440304/1/../bin/lava-test-case
11794 22:12:04.655772 <8>[ 49.956002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11795 22:12:04.656049 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11797 22:12:05.689078 /lava-11440304/1/../bin/lava-test-case
11798 22:12:05.716978 <8>[ 51.017489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11799 22:12:05.717259 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11801 22:12:05.736794 /lava-11440304/1/../bin/lava-test-case
11802 22:12:05.760052 <8>[ 51.060326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11803 22:12:05.760337 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11805 22:12:06.798691 /lava-11440304/1/../bin/lava-test-case
11806 22:12:06.823113 <8>[ 52.123997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11807 22:12:06.823399 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11809 22:12:06.842623 /lava-11440304/1/../bin/lava-test-case
11810 22:12:06.862901 <8>[ 52.162887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11811 22:12:06.863154 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11813 22:12:07.898424 /lava-11440304/1/../bin/lava-test-case
11814 22:12:07.921074 <8>[ 53.221780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11815 22:12:07.921353 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11817 22:12:07.937813 /lava-11440304/1/../bin/lava-test-case
11818 22:12:07.958229 <8>[ 53.259143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11819 22:12:07.958485 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11821 22:12:07.988727 /lava-11440304/1/../bin/lava-test-case
11822 22:12:08.011236 <8>[ 53.312021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11823 22:12:08.011514 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11825 22:12:08.038424 /lava-11440304/1/../bin/lava-test-case
11826 22:12:08.055682 <8>[ 53.356492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11827 22:12:08.055937 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11829 22:12:08.072906 /lava-11440304/1/../bin/lava-test-case
11830 22:12:08.092258 <8>[ 53.393107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11831 22:12:08.092513 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11833 22:12:08.119064 /lava-11440304/1/../bin/lava-test-case
11834 22:12:08.141361 <8>[ 53.442080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11835 22:12:08.141677 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11837 22:12:08.160451 /lava-11440304/1/../bin/lava-test-case
11838 22:12:08.183518 <8>[ 53.484343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11839 22:12:08.183777 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11841 22:12:08.218498 /lava-11440304/1/../bin/lava-test-case
11842 22:12:08.239218 <8>[ 53.539904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11843 22:12:08.239475 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11845 22:12:08.256652 /lava-11440304/1/../bin/lava-test-case
11846 22:12:08.278935 <8>[ 53.579514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11847 22:12:08.279190 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11849 22:12:08.303363 /lava-11440304/1/../bin/lava-test-case
11850 22:12:08.323432 <8>[ 53.623905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11851 22:12:08.323691 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11853 22:12:08.331707 + <8>[ 53.635272] <LAVA_SIGNAL_ENDRUN 1_bootrr 11440304_1.6.2.3.5>
11854 22:12:08.331962 Received signal: <ENDRUN> 1_bootrr 11440304_1.6.2.3.5
11855 22:12:08.332038 Ending use of test pattern.
11856 22:12:08.332101 Ending test lava.1_bootrr (11440304_1.6.2.3.5), duration 25.92
11858 22:12:08.334356 set +x
11859 22:12:08.338033 <LAVA_TEST_RUNNER EXIT>
11860 22:12:08.338284 ok: lava_test_shell seems to have completed
11861 22:12:08.339309 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11862 22:12:08.339456 end: 4.1 lava-test-shell (duration 00:00:26) [common]
11863 22:12:08.339544 end: 4 lava-test-retry (duration 00:00:26) [common]
11864 22:12:08.339633 start: 5 finalize (timeout 00:07:38) [common]
11865 22:12:08.339724 start: 5.1 power-off (timeout 00:00:30) [common]
11866 22:12:08.339878 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11867 22:12:08.416669 >> Command sent successfully.
11868 22:12:08.419229 Returned 0 in 0 seconds
11869 22:12:08.519584 end: 5.1 power-off (duration 00:00:00) [common]
11871 22:12:08.519889 start: 5.2 read-feedback (timeout 00:07:38) [common]
11872 22:12:08.520152 Listened to connection for namespace 'common' for up to 1s
11873 22:12:09.520868 Finalising connection for namespace 'common'
11874 22:12:09.521053 Disconnecting from shell: Finalise
11875 22:12:09.521140 / #
11876 22:12:09.621461 end: 5.2 read-feedback (duration 00:00:01) [common]
11877 22:12:09.621607 end: 5 finalize (duration 00:00:01) [common]
11878 22:12:09.621722 Cleaning after the job
11879 22:12:09.621822 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/ramdisk
11880 22:12:09.623932 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/kernel
11881 22:12:09.633337 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/dtb
11882 22:12:09.633497 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/nfsrootfs
11883 22:12:09.686917 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440304/tftp-deploy-fbu5alh4/modules
11884 22:12:09.692328 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11440304
11885 22:12:10.007138 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11440304
11886 22:12:10.007322 Job finished correctly