Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 23
1 22:09:34.278247 lava-dispatcher, installed at version: 2023.06
2 22:09:34.278460 start: 0 validate
3 22:09:34.278600 Start time: 2023-09-05 22:09:34.278584+00:00 (UTC)
4 22:09:34.278731 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:09:34.278879 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 22:09:34.545866 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:09:34.546050 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:10:11.310237 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:10:11.310992 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:10:11.581262 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:10:11.581964 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:10:14.353679 validate duration: 40.08
14 22:10:14.354846 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:10:14.355361 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:10:14.355816 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:10:14.356422 Not decompressing ramdisk as can be used compressed.
18 22:10:14.356875 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 22:10:14.357264 saving as /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/ramdisk/rootfs.cpio.gz
20 22:10:14.357791 total size: 34390042 (32 MB)
21 22:10:14.630102 progress 0 % (0 MB)
22 22:10:14.639702 progress 5 % (1 MB)
23 22:10:14.649242 progress 10 % (3 MB)
24 22:10:14.658301 progress 15 % (4 MB)
25 22:10:14.667273 progress 20 % (6 MB)
26 22:10:14.676464 progress 25 % (8 MB)
27 22:10:14.685432 progress 30 % (9 MB)
28 22:10:14.694584 progress 35 % (11 MB)
29 22:10:14.703640 progress 40 % (13 MB)
30 22:10:14.713057 progress 45 % (14 MB)
31 22:10:14.722132 progress 50 % (16 MB)
32 22:10:14.731537 progress 55 % (18 MB)
33 22:10:14.740465 progress 60 % (19 MB)
34 22:10:14.749629 progress 65 % (21 MB)
35 22:10:14.759063 progress 70 % (22 MB)
36 22:10:14.768643 progress 75 % (24 MB)
37 22:10:14.778452 progress 80 % (26 MB)
38 22:10:14.788168 progress 85 % (27 MB)
39 22:10:14.797243 progress 90 % (29 MB)
40 22:10:14.806175 progress 95 % (31 MB)
41 22:10:14.815129 progress 100 % (32 MB)
42 22:10:14.815336 32 MB downloaded in 0.46 s (71.68 MB/s)
43 22:10:14.815493 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:10:14.815732 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:10:14.815817 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:10:14.815899 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:10:14.816047 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:10:14.816122 saving as /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/kernel/Image
50 22:10:14.816184 total size: 49220096 (46 MB)
51 22:10:14.816245 No compression specified
52 22:10:14.817396 progress 0 % (0 MB)
53 22:10:14.830113 progress 5 % (2 MB)
54 22:10:14.842987 progress 10 % (4 MB)
55 22:10:14.855731 progress 15 % (7 MB)
56 22:10:14.868554 progress 20 % (9 MB)
57 22:10:14.881572 progress 25 % (11 MB)
58 22:10:14.894784 progress 30 % (14 MB)
59 22:10:14.907851 progress 35 % (16 MB)
60 22:10:14.920867 progress 40 % (18 MB)
61 22:10:14.933828 progress 45 % (21 MB)
62 22:10:14.947329 progress 50 % (23 MB)
63 22:10:14.960247 progress 55 % (25 MB)
64 22:10:14.973245 progress 60 % (28 MB)
65 22:10:14.986167 progress 65 % (30 MB)
66 22:10:14.999248 progress 70 % (32 MB)
67 22:10:15.012535 progress 75 % (35 MB)
68 22:10:15.025626 progress 80 % (37 MB)
69 22:10:15.038797 progress 85 % (39 MB)
70 22:10:15.051644 progress 90 % (42 MB)
71 22:10:15.064297 progress 95 % (44 MB)
72 22:10:15.077079 progress 100 % (46 MB)
73 22:10:15.077224 46 MB downloaded in 0.26 s (179.82 MB/s)
74 22:10:15.077376 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:10:15.077602 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:10:15.077687 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:10:15.077777 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:10:15.077921 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:10:15.077991 saving as /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/dtb/mt8192-asurada-spherion-r0.dtb
81 22:10:15.078053 total size: 47278 (0 MB)
82 22:10:15.078114 No compression specified
83 22:10:15.079289 progress 69 % (0 MB)
84 22:10:15.079565 progress 100 % (0 MB)
85 22:10:15.079723 0 MB downloaded in 0.00 s (27.03 MB/s)
86 22:10:15.079845 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:10:15.080066 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:10:15.080150 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:10:15.080231 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:10:15.080348 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:10:15.080416 saving as /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/modules/modules.tar
93 22:10:15.080477 total size: 8619808 (8 MB)
94 22:10:15.080538 Using unxz to decompress xz
95 22:10:15.084786 progress 0 % (0 MB)
96 22:10:15.107300 progress 5 % (0 MB)
97 22:10:15.130180 progress 10 % (0 MB)
98 22:10:15.158249 progress 15 % (1 MB)
99 22:10:15.184677 progress 20 % (1 MB)
100 22:10:15.211825 progress 25 % (2 MB)
101 22:10:15.238841 progress 30 % (2 MB)
102 22:10:15.266842 progress 35 % (2 MB)
103 22:10:15.294020 progress 40 % (3 MB)
104 22:10:15.319530 progress 45 % (3 MB)
105 22:10:15.346797 progress 50 % (4 MB)
106 22:10:15.371752 progress 55 % (4 MB)
107 22:10:15.396367 progress 60 % (4 MB)
108 22:10:15.419211 progress 65 % (5 MB)
109 22:10:15.449045 progress 70 % (5 MB)
110 22:10:15.474863 progress 75 % (6 MB)
111 22:10:15.503915 progress 80 % (6 MB)
112 22:10:15.534783 progress 85 % (7 MB)
113 22:10:15.563684 progress 90 % (7 MB)
114 22:10:15.589990 progress 95 % (7 MB)
115 22:10:15.616890 progress 100 % (8 MB)
116 22:10:15.621720 8 MB downloaded in 0.54 s (15.19 MB/s)
117 22:10:15.621963 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:10:15.622222 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:10:15.622315 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:10:15.622419 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:10:15.622501 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:10:15.622605 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:10:15.622913 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp
125 22:10:15.623093 makedir: /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin
126 22:10:15.623236 makedir: /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/tests
127 22:10:15.623370 makedir: /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/results
128 22:10:15.623519 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-add-keys
129 22:10:15.623675 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-add-sources
130 22:10:15.623811 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-background-process-start
131 22:10:15.623943 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-background-process-stop
132 22:10:15.624070 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-common-functions
133 22:10:15.624210 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-echo-ipv4
134 22:10:15.624347 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-install-packages
135 22:10:15.624475 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-installed-packages
136 22:10:15.624612 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-os-build
137 22:10:15.624742 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-probe-channel
138 22:10:15.624868 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-probe-ip
139 22:10:15.624997 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-target-ip
140 22:10:15.625142 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-target-mac
141 22:10:15.625305 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-target-storage
142 22:10:15.625470 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-test-case
143 22:10:15.625629 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-test-event
144 22:10:15.625778 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-test-feedback
145 22:10:15.625905 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-test-raise
146 22:10:15.626033 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-test-reference
147 22:10:15.626166 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-test-runner
148 22:10:15.626292 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-test-set
149 22:10:15.626423 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-test-shell
150 22:10:15.626556 Updating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-install-packages (oe)
151 22:10:15.626755 Updating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/bin/lava-installed-packages (oe)
152 22:10:15.626879 Creating /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/environment
153 22:10:15.626980 LAVA metadata
154 22:10:15.627062 - LAVA_JOB_ID=11440297
155 22:10:15.627137 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:10:15.627278 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:10:15.627373 skipped lava-vland-overlay
158 22:10:15.627478 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:10:15.627590 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:10:15.627684 skipped lava-multinode-overlay
161 22:10:15.627790 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:10:15.627908 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:10:15.628025 Loading test definitions
164 22:10:15.628150 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:10:15.628255 Using /lava-11440297 at stage 0
166 22:10:15.628693 uuid=11440297_1.5.2.3.1 testdef=None
167 22:10:15.628811 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:10:15.628924 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:10:15.629516 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:10:15.629750 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:10:15.630531 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:10:15.630827 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:10:15.631432 runner path: /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/0/tests/0_cros-ec test_uuid 11440297_1.5.2.3.1
176 22:10:15.631588 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:10:15.631795 Creating lava-test-runner.conf files
179 22:10:15.631860 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11440297/lava-overlay-_vf4rpjp/lava-11440297/0 for stage 0
180 22:10:15.631955 - 0_cros-ec
181 22:10:15.632050 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:10:15.632133 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:10:15.639364 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:10:15.639474 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:10:15.639562 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:10:15.639648 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:10:15.639734 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:10:16.644012 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:10:16.644392 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:10:16.644511 extracting modules file /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11440297/extract-overlay-ramdisk-1l1st9eq/ramdisk
191 22:10:16.887730 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:10:16.887901 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 22:10:16.887998 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11440297/compress-overlay-68nb1h3f/overlay-1.5.2.4.tar.gz to ramdisk
194 22:10:16.888071 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11440297/compress-overlay-68nb1h3f/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11440297/extract-overlay-ramdisk-1l1st9eq/ramdisk
195 22:10:16.894914 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:10:16.895026 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 22:10:16.895132 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:10:16.895261 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 22:10:16.895339 Building ramdisk /var/lib/lava/dispatcher/tmp/11440297/extract-overlay-ramdisk-1l1st9eq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11440297/extract-overlay-ramdisk-1l1st9eq/ramdisk
200 22:10:17.762897 >> 270924 blocks
201 22:10:22.523095 rename /var/lib/lava/dispatcher/tmp/11440297/extract-overlay-ramdisk-1l1st9eq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/ramdisk/ramdisk.cpio.gz
202 22:10:22.523673 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 22:10:22.523851 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 22:10:22.523998 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 22:10:22.524160 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/kernel/Image'
206 22:10:35.474027 Returned 0 in 12 seconds
207 22:10:35.575065 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/kernel/image.itb
208 22:10:36.303575 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:10:36.303963 output: Created: Tue Sep 5 23:10:36 2023
210 22:10:36.304044 output: Image 0 (kernel-1)
211 22:10:36.304108 output: Description:
212 22:10:36.304172 output: Created: Tue Sep 5 23:10:36 2023
213 22:10:36.304236 output: Type: Kernel Image
214 22:10:36.304298 output: Compression: lzma compressed
215 22:10:36.304361 output: Data Size: 11037994 Bytes = 10779.29 KiB = 10.53 MiB
216 22:10:36.304422 output: Architecture: AArch64
217 22:10:36.304478 output: OS: Linux
218 22:10:36.304535 output: Load Address: 0x00000000
219 22:10:36.304588 output: Entry Point: 0x00000000
220 22:10:36.304641 output: Hash algo: crc32
221 22:10:36.304694 output: Hash value: 9d08b3de
222 22:10:36.304747 output: Image 1 (fdt-1)
223 22:10:36.304799 output: Description: mt8192-asurada-spherion-r0
224 22:10:36.304852 output: Created: Tue Sep 5 23:10:36 2023
225 22:10:36.304905 output: Type: Flat Device Tree
226 22:10:36.304957 output: Compression: uncompressed
227 22:10:36.305010 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 22:10:36.305064 output: Architecture: AArch64
229 22:10:36.305116 output: Hash algo: crc32
230 22:10:36.305169 output: Hash value: cc4352de
231 22:10:36.305221 output: Image 2 (ramdisk-1)
232 22:10:36.305274 output: Description: unavailable
233 22:10:36.305326 output: Created: Tue Sep 5 23:10:36 2023
234 22:10:36.305379 output: Type: RAMDisk Image
235 22:10:36.305431 output: Compression: Unknown Compression
236 22:10:36.305483 output: Data Size: 47519328 Bytes = 46405.59 KiB = 45.32 MiB
237 22:10:36.305536 output: Architecture: AArch64
238 22:10:36.305615 output: OS: Linux
239 22:10:36.305671 output: Load Address: unavailable
240 22:10:36.305725 output: Entry Point: unavailable
241 22:10:36.305777 output: Hash algo: crc32
242 22:10:36.305830 output: Hash value: d3068379
243 22:10:36.305882 output: Default Configuration: 'conf-1'
244 22:10:36.305935 output: Configuration 0 (conf-1)
245 22:10:36.305988 output: Description: mt8192-asurada-spherion-r0
246 22:10:36.306044 output: Kernel: kernel-1
247 22:10:36.306099 output: Init Ramdisk: ramdisk-1
248 22:10:36.306152 output: FDT: fdt-1
249 22:10:36.306204 output: Loadables: kernel-1
250 22:10:36.306256 output:
251 22:10:36.306463 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 22:10:36.306561 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 22:10:36.306713 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 22:10:36.306809 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 22:10:36.306893 No LXC device requested
256 22:10:36.306972 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:10:36.307061 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 22:10:36.307136 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:10:36.307206 Checking files for TFTP limit of 4294967296 bytes.
260 22:10:36.307708 end: 1 tftp-deploy (duration 00:00:22) [common]
261 22:10:36.307816 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:10:36.307909 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:10:36.308035 substitutions:
264 22:10:36.308104 - {DTB}: 11440297/tftp-deploy-jjlpmr50/dtb/mt8192-asurada-spherion-r0.dtb
265 22:10:36.308170 - {INITRD}: 11440297/tftp-deploy-jjlpmr50/ramdisk/ramdisk.cpio.gz
266 22:10:36.308232 - {KERNEL}: 11440297/tftp-deploy-jjlpmr50/kernel/Image
267 22:10:36.308294 - {LAVA_MAC}: None
268 22:10:36.308352 - {PRESEED_CONFIG}: None
269 22:10:36.308407 - {PRESEED_LOCAL}: None
270 22:10:36.308462 - {RAMDISK}: 11440297/tftp-deploy-jjlpmr50/ramdisk/ramdisk.cpio.gz
271 22:10:36.308517 - {ROOT_PART}: None
272 22:10:36.308571 - {ROOT}: None
273 22:10:36.308624 - {SERVER_IP}: 192.168.201.1
274 22:10:36.308678 - {TEE}: None
275 22:10:36.308731 Parsed boot commands:
276 22:10:36.308786 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:10:36.308975 Parsed boot commands: tftpboot 192.168.201.1 11440297/tftp-deploy-jjlpmr50/kernel/image.itb 11440297/tftp-deploy-jjlpmr50/kernel/cmdline
278 22:10:36.309067 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:10:36.309172 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:10:36.309269 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:10:36.309356 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:10:36.309428 Not connected, no need to disconnect.
283 22:10:36.309503 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:10:36.309582 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:10:36.309651 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 22:10:36.313846 Setting prompt string to ['lava-test: # ']
287 22:10:36.314218 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:10:36.314333 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:10:36.314468 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:10:36.314614 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:10:36.314917 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 22:10:41.468730 >> Command sent successfully.
293 22:10:41.480101 Returned 0 in 5 seconds
294 22:10:41.581271 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:10:41.582769 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:10:41.583267 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:10:41.583735 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:10:41.584122 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:10:41.584477 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:10:41.585831 [Enter `^Ec?' for help]
302 22:10:41.744554
303 22:10:41.745069
304 22:10:41.745411 F0: 102B 0000
305 22:10:41.745725
306 22:10:41.746056 F3: 1001 0000 [0200]
307 22:10:41.746356
308 22:10:41.748222 F3: 1001 0000
309 22:10:41.748652
310 22:10:41.748987 F7: 102D 0000
311 22:10:41.749341
312 22:10:41.751824 F1: 0000 0000
313 22:10:41.752251
314 22:10:41.752598 V0: 0000 0000 [0001]
315 22:10:41.752912
316 22:10:41.753211 00: 0007 8000
317 22:10:41.753515
318 22:10:41.755486 01: 0000 0000
319 22:10:41.755993
320 22:10:41.756496 BP: 0C00 0209 [0000]
321 22:10:41.756864
322 22:10:41.759179 G0: 1182 0000
323 22:10:41.759606
324 22:10:41.759944 EC: 0000 0021 [4000]
325 22:10:41.760294
326 22:10:41.762848 S7: 0000 0000 [0000]
327 22:10:41.763302
328 22:10:41.763754 CC: 0000 0000 [0001]
329 22:10:41.764092
330 22:10:41.766368 T0: 0000 0040 [010F]
331 22:10:41.766914
332 22:10:41.767273 Jump to BL
333 22:10:41.767605
334 22:10:41.791407
335 22:10:41.791840
336 22:10:41.792226
337 22:10:41.798567 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:10:41.802293 ARM64: Exception handlers installed.
339 22:10:41.805709 ARM64: Testing exception
340 22:10:41.809439 ARM64: Done test exception
341 22:10:41.816549 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:10:41.827587 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:10:41.834725 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:10:41.841920 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:10:41.848627 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:10:41.859263 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:10:41.869182 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:10:41.875536 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:10:41.894876 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:10:41.897351 WDT: Last reset was cold boot
351 22:10:41.900694 SPI1(PAD0) initialized at 2873684 Hz
352 22:10:41.903885 SPI5(PAD0) initialized at 992727 Hz
353 22:10:41.907412 VBOOT: Loading verstage.
354 22:10:41.913760 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:10:41.917151 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:10:41.920731 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:10:41.924061 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:10:41.931501 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:10:41.938106 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:10:41.949262 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 22:10:41.949961
362 22:10:41.950553
363 22:10:41.959037 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:10:41.962152 ARM64: Exception handlers installed.
365 22:10:41.966117 ARM64: Testing exception
366 22:10:41.966706 ARM64: Done test exception
367 22:10:41.972369 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:10:41.975744 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:10:41.989569 Probing TPM: . done!
370 22:10:41.989896 TPM ready after 0 ms
371 22:10:41.996390 Connected to device vid:did:rid of 1ae0:0028:00
372 22:10:42.006298 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 22:10:42.045224 Initialized TPM device CR50 revision 0
374 22:10:42.056662 tlcl_send_startup: Startup return code is 0
375 22:10:42.056776 TPM: setup succeeded
376 22:10:42.068061 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:10:42.076910 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:10:42.084240 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:10:42.095294 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:10:42.098993 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:10:42.102428 in-header: 03 07 00 00 08 00 00 00
382 22:10:42.105483 in-data: aa e4 47 04 13 02 00 00
383 22:10:42.108766 Chrome EC: UHEPI supported
384 22:10:42.115712 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:10:42.118562 in-header: 03 ad 00 00 08 00 00 00
386 22:10:42.122385 in-data: 00 20 20 08 00 00 00 00
387 22:10:42.125663 Phase 1
388 22:10:42.128793 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:10:42.135806 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:10:42.139044 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:10:42.142198 Recovery requested (1009000e)
392 22:10:42.150022 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:10:42.155246 tlcl_extend: response is 0
394 22:10:42.163641 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:10:42.168773 tlcl_extend: response is 0
396 22:10:42.175702 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:10:42.195883 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:10:42.202523 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:10:42.202646
400 22:10:42.202713
401 22:10:42.212823 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:10:42.216106 ARM64: Exception handlers installed.
403 22:10:42.219495 ARM64: Testing exception
404 22:10:42.219576 ARM64: Done test exception
405 22:10:42.241648 pmic_efuse_setting: Set efuses in 11 msecs
406 22:10:42.245268 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:10:42.249257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:10:42.255488 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:10:42.258872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:10:42.265861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:10:42.268792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:10:42.275803 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:10:42.279283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:10:42.286059 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:10:42.288898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:10:42.292331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:10:42.299258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:10:42.302747 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:10:42.305831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:10:42.312827 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:10:42.319350 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:10:42.326245 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:10:42.329212 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:10:42.336201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:10:42.342956 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:10:42.349497 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:10:42.352891 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:10:42.359911 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:10:42.363414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:10:42.370298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:10:42.373123 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:10:42.379958 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:10:42.387201 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:10:42.390702 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:10:42.393947 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:10:42.400795 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:10:42.404284 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:10:42.411814 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:10:42.414999 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:10:42.421758 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:10:42.425014 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:10:42.431871 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:10:42.435193 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:10:42.442452 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:10:42.445748 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:10:42.448888 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:10:42.452611 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:10:42.456256 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:10:42.463435 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:10:42.466758 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:10:42.470266 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:10:42.476376 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:10:42.480213 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:10:42.483279 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:10:42.486811 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:10:42.493246 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:10:42.496487 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:10:42.502958 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:10:42.513064 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:10:42.516674 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:10:42.526454 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:10:42.533345 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:10:42.539717 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:10:42.542870 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:10:42.546471 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:10:42.553947 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x13
467 22:10:42.560892 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:10:42.563779 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 22:10:42.567514 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:10:42.578930 [RTC]rtc_get_frequency_meter,154: input=15, output=835
471 22:10:42.587959 [RTC]rtc_get_frequency_meter,154: input=7, output=708
472 22:10:42.597716 [RTC]rtc_get_frequency_meter,154: input=11, output=772
473 22:10:42.607341 [RTC]rtc_get_frequency_meter,154: input=13, output=804
474 22:10:42.616634 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 22:10:42.625813 [RTC]rtc_get_frequency_meter,154: input=12, output=788
476 22:10:42.635449 [RTC]rtc_get_frequency_meter,154: input=13, output=804
477 22:10:42.638754 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 22:10:42.645886 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 22:10:42.649042 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:10:42.652628 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:10:42.659511 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:10:42.662542 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:10:42.665748 ADC[4]: Raw value=905988 ID=7
484 22:10:42.665827 ADC[3]: Raw value=213652 ID=1
485 22:10:42.669102 RAM Code: 0x71
486 22:10:42.672592 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:10:42.679349 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:10:42.685607 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 22:10:42.692390 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 22:10:42.695709 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:10:42.698898 in-header: 03 07 00 00 08 00 00 00
492 22:10:42.702075 in-data: aa e4 47 04 13 02 00 00
493 22:10:42.705579 Chrome EC: UHEPI supported
494 22:10:42.712217 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:10:42.715881 in-header: 03 dd 00 00 08 00 00 00
496 22:10:42.718799 in-data: 90 20 60 08 00 00 00 00
497 22:10:42.722140 MRC: failed to locate region type 0.
498 22:10:42.729122 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:10:42.732231 DRAM-K: Running full calibration
500 22:10:42.738832 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 22:10:42.738910 header.status = 0x0
502 22:10:42.741841 header.version = 0x6 (expected: 0x6)
503 22:10:42.745525 header.size = 0xd00 (expected: 0xd00)
504 22:10:42.748570 header.flags = 0x0
505 22:10:42.754951 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:10:42.772087 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 22:10:42.778619 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:10:42.782101 dram_init: ddr_geometry: 2
509 22:10:42.785953 [EMI] MDL number = 2
510 22:10:42.786043 [EMI] Get MDL freq = 0
511 22:10:42.788997 dram_init: ddr_type: 0
512 22:10:42.789078 is_discrete_lpddr4: 1
513 22:10:42.791941 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:10:42.792022
515 22:10:42.792086
516 22:10:42.795833 [Bian_co] ETT version 0.0.0.1
517 22:10:42.802388 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 22:10:42.802498
519 22:10:42.805546 dramc_set_vcore_voltage set vcore to 650000
520 22:10:42.808467 Read voltage for 800, 4
521 22:10:42.808543 Vio18 = 0
522 22:10:42.808606 Vcore = 650000
523 22:10:42.812360 Vdram = 0
524 22:10:42.812431 Vddq = 0
525 22:10:42.812491 Vmddr = 0
526 22:10:42.815826 dram_init: config_dvfs: 1
527 22:10:42.819158 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:10:42.825679 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:10:42.829349 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 22:10:42.832134 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 22:10:42.835743 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 22:10:42.838686 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 22:10:42.842080 MEM_TYPE=3, freq_sel=18
534 22:10:42.845548 sv_algorithm_assistance_LP4_1600
535 22:10:42.848630 ============ PULL DRAM RESETB DOWN ============
536 22:10:42.855236 ========== PULL DRAM RESETB DOWN end =========
537 22:10:42.858748 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:10:42.862029 ===================================
539 22:10:42.864992 LPDDR4 DRAM CONFIGURATION
540 22:10:42.868551 ===================================
541 22:10:42.868633 EX_ROW_EN[0] = 0x0
542 22:10:42.871611 EX_ROW_EN[1] = 0x0
543 22:10:42.871693 LP4Y_EN = 0x0
544 22:10:42.875280 WORK_FSP = 0x0
545 22:10:42.875361 WL = 0x2
546 22:10:42.878686 RL = 0x2
547 22:10:42.878767 BL = 0x2
548 22:10:42.881509 RPST = 0x0
549 22:10:42.881618 RD_PRE = 0x0
550 22:10:42.884758 WR_PRE = 0x1
551 22:10:42.888622 WR_PST = 0x0
552 22:10:42.888724 DBI_WR = 0x0
553 22:10:42.891727 DBI_RD = 0x0
554 22:10:42.891805 OTF = 0x1
555 22:10:42.894751 ===================================
556 22:10:42.898600 ===================================
557 22:10:42.898717 ANA top config
558 22:10:42.901474 ===================================
559 22:10:42.904984 DLL_ASYNC_EN = 0
560 22:10:42.908431 ALL_SLAVE_EN = 1
561 22:10:42.911407 NEW_RANK_MODE = 1
562 22:10:42.914713 DLL_IDLE_MODE = 1
563 22:10:42.914822 LP45_APHY_COMB_EN = 1
564 22:10:42.918279 TX_ODT_DIS = 1
565 22:10:42.921457 NEW_8X_MODE = 1
566 22:10:42.924957 ===================================
567 22:10:42.928029 ===================================
568 22:10:42.931295 data_rate = 1600
569 22:10:42.934479 CKR = 1
570 22:10:42.934563 DQ_P2S_RATIO = 8
571 22:10:42.937860 ===================================
572 22:10:42.941542 CA_P2S_RATIO = 8
573 22:10:42.944368 DQ_CA_OPEN = 0
574 22:10:42.947985 DQ_SEMI_OPEN = 0
575 22:10:42.951193 CA_SEMI_OPEN = 0
576 22:10:42.954968 CA_FULL_RATE = 0
577 22:10:42.955086 DQ_CKDIV4_EN = 1
578 22:10:42.957771 CA_CKDIV4_EN = 1
579 22:10:42.961108 CA_PREDIV_EN = 0
580 22:10:42.964619 PH8_DLY = 0
581 22:10:42.967792 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:10:42.970760 DQ_AAMCK_DIV = 4
583 22:10:42.970867 CA_AAMCK_DIV = 4
584 22:10:42.974409 CA_ADMCK_DIV = 4
585 22:10:42.977496 DQ_TRACK_CA_EN = 0
586 22:10:42.981428 CA_PICK = 800
587 22:10:42.984321 CA_MCKIO = 800
588 22:10:42.987327 MCKIO_SEMI = 0
589 22:10:42.990791 PLL_FREQ = 3068
590 22:10:42.990873 DQ_UI_PI_RATIO = 32
591 22:10:42.994102 CA_UI_PI_RATIO = 0
592 22:10:42.997472 ===================================
593 22:10:43.000821 ===================================
594 22:10:43.003903 memory_type:LPDDR4
595 22:10:43.007263 GP_NUM : 10
596 22:10:43.007342 SRAM_EN : 1
597 22:10:43.010548 MD32_EN : 0
598 22:10:43.014256 ===================================
599 22:10:43.017575 [ANA_INIT] >>>>>>>>>>>>>>
600 22:10:43.017679 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:10:43.023879 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:10:43.023986 ===================================
603 22:10:43.027901 data_rate = 1600,PCW = 0X7600
604 22:10:43.030569 ===================================
605 22:10:43.034292 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:10:43.040883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:10:43.047394 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:10:43.050494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:10:43.053940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:10:43.057578 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:10:43.061205 [ANA_INIT] flow start
612 22:10:43.061309 [ANA_INIT] PLL >>>>>>>>
613 22:10:43.063734 [ANA_INIT] PLL <<<<<<<<
614 22:10:43.067605 [ANA_INIT] MIDPI >>>>>>>>
615 22:10:43.070255 [ANA_INIT] MIDPI <<<<<<<<
616 22:10:43.070362 [ANA_INIT] DLL >>>>>>>>
617 22:10:43.073580 [ANA_INIT] flow end
618 22:10:43.076895 ============ LP4 DIFF to SE enter ============
619 22:10:43.080905 ============ LP4 DIFF to SE exit ============
620 22:10:43.083857 [ANA_INIT] <<<<<<<<<<<<<
621 22:10:43.086730 [Flow] Enable top DCM control >>>>>
622 22:10:43.090293 [Flow] Enable top DCM control <<<<<
623 22:10:43.093410 Enable DLL master slave shuffle
624 22:10:43.100216 ==============================================================
625 22:10:43.100323 Gating Mode config
626 22:10:43.106851 ==============================================================
627 22:10:43.106965 Config description:
628 22:10:43.116996 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:10:43.123336 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:10:43.130486 SELPH_MODE 0: By rank 1: By Phase
631 22:10:43.133542 ==============================================================
632 22:10:43.137094 GAT_TRACK_EN = 1
633 22:10:43.139839 RX_GATING_MODE = 2
634 22:10:43.143186 RX_GATING_TRACK_MODE = 2
635 22:10:43.146451 SELPH_MODE = 1
636 22:10:43.149738 PICG_EARLY_EN = 1
637 22:10:43.153321 VALID_LAT_VALUE = 1
638 22:10:43.160314 ==============================================================
639 22:10:43.163772 Enter into Gating configuration >>>>
640 22:10:43.163879 Exit from Gating configuration <<<<
641 22:10:43.166750 Enter into DVFS_PRE_config >>>>>
642 22:10:43.179611 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:10:43.182851 Exit from DVFS_PRE_config <<<<<
644 22:10:43.186096 Enter into PICG configuration >>>>
645 22:10:43.189262 Exit from PICG configuration <<<<
646 22:10:43.192696 [RX_INPUT] configuration >>>>>
647 22:10:43.192804 [RX_INPUT] configuration <<<<<
648 22:10:43.199350 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:10:43.203405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:10:43.210224 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:10:43.217648 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:10:43.224451 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:10:43.228017 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:10:43.235056 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:10:43.238763 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:10:43.242278 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:10:43.246161 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:10:43.249381 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:10:43.253250 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:10:43.256728 ===================================
661 22:10:43.260115 LPDDR4 DRAM CONFIGURATION
662 22:10:43.264102 ===================================
663 22:10:43.264241 EX_ROW_EN[0] = 0x0
664 22:10:43.267440 EX_ROW_EN[1] = 0x0
665 22:10:43.267544 LP4Y_EN = 0x0
666 22:10:43.270598 WORK_FSP = 0x0
667 22:10:43.270687 WL = 0x2
668 22:10:43.274518 RL = 0x2
669 22:10:43.274658 BL = 0x2
670 22:10:43.278133 RPST = 0x0
671 22:10:43.278246 RD_PRE = 0x0
672 22:10:43.282004 WR_PRE = 0x1
673 22:10:43.282105 WR_PST = 0x0
674 22:10:43.285458 DBI_WR = 0x0
675 22:10:43.285573 DBI_RD = 0x0
676 22:10:43.289496 OTF = 0x1
677 22:10:43.293271 ===================================
678 22:10:43.293381 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:10:43.300395 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:10:43.304010 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:10:43.308130 ===================================
682 22:10:43.308245 LPDDR4 DRAM CONFIGURATION
683 22:10:43.311561 ===================================
684 22:10:43.314661 EX_ROW_EN[0] = 0x10
685 22:10:43.318761 EX_ROW_EN[1] = 0x0
686 22:10:43.318837 LP4Y_EN = 0x0
687 22:10:43.318907 WORK_FSP = 0x0
688 22:10:43.322170 WL = 0x2
689 22:10:43.322246 RL = 0x2
690 22:10:43.325707 BL = 0x2
691 22:10:43.325784 RPST = 0x0
692 22:10:43.329425 RD_PRE = 0x0
693 22:10:43.329527 WR_PRE = 0x1
694 22:10:43.333059 WR_PST = 0x0
695 22:10:43.333160 DBI_WR = 0x0
696 22:10:43.337394 DBI_RD = 0x0
697 22:10:43.337512 OTF = 0x1
698 22:10:43.340689 ===================================
699 22:10:43.347442 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:10:43.351302 nWR fixed to 40
701 22:10:43.351412 [ModeRegInit_LP4] CH0 RK0
702 22:10:43.354920 [ModeRegInit_LP4] CH0 RK1
703 22:10:43.358196 [ModeRegInit_LP4] CH1 RK0
704 22:10:43.358302 [ModeRegInit_LP4] CH1 RK1
705 22:10:43.361771 match AC timing 13
706 22:10:43.366439 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 22:10:43.369496 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:10:43.376155 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:10:43.379538 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:10:43.382857 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:10:43.386388 [EMI DOE] emi_dcm 0
712 22:10:43.389417 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:10:43.389496 ==
714 22:10:43.392746 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:10:43.396165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 22:10:43.396272 ==
717 22:10:43.402634 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:10:43.409394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:10:43.417836 [CA 0] Center 37 (6~68) winsize 63
720 22:10:43.421159 [CA 1] Center 36 (6~67) winsize 62
721 22:10:43.424564 [CA 2] Center 34 (4~65) winsize 62
722 22:10:43.427820 [CA 3] Center 34 (4~65) winsize 62
723 22:10:43.431660 [CA 4] Center 33 (3~64) winsize 62
724 22:10:43.435411 [CA 5] Center 33 (3~64) winsize 62
725 22:10:43.435512
726 22:10:43.438964 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 22:10:43.439067
728 22:10:43.442102 [CATrainingPosCal] consider 1 rank data
729 22:10:43.445147 u2DelayCellTimex100 = 270/100 ps
730 22:10:43.448518 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 22:10:43.451899 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
732 22:10:43.455298 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 22:10:43.458743 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 22:10:43.465207 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 22:10:43.468662 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 22:10:43.468742
737 22:10:43.471843 CA PerBit enable=1, Macro0, CA PI delay=33
738 22:10:43.471943
739 22:10:43.474803 [CBTSetCACLKResult] CA Dly = 33
740 22:10:43.474903 CS Dly: 6 (0~37)
741 22:10:43.475001 ==
742 22:10:43.478383 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:10:43.485348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 22:10:43.485425 ==
745 22:10:43.488344 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:10:43.494817 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:10:43.504362 [CA 0] Center 37 (6~68) winsize 63
748 22:10:43.507482 [CA 1] Center 37 (7~68) winsize 62
749 22:10:43.510737 [CA 2] Center 34 (4~65) winsize 62
750 22:10:43.514355 [CA 3] Center 34 (4~65) winsize 62
751 22:10:43.517764 [CA 4] Center 33 (3~64) winsize 62
752 22:10:43.520780 [CA 5] Center 33 (3~64) winsize 62
753 22:10:43.520886
754 22:10:43.524234 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 22:10:43.524347
756 22:10:43.527557 [CATrainingPosCal] consider 2 rank data
757 22:10:43.530745 u2DelayCellTimex100 = 270/100 ps
758 22:10:43.534149 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
759 22:10:43.540443 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
760 22:10:43.544101 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 22:10:43.547913 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 22:10:43.551774 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 22:10:43.555217 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 22:10:43.555294
765 22:10:43.558608 CA PerBit enable=1, Macro0, CA PI delay=33
766 22:10:43.558689
767 22:10:43.562354 [CBTSetCACLKResult] CA Dly = 33
768 22:10:43.562456 CS Dly: 6 (0~38)
769 22:10:43.562560
770 22:10:43.566082 ----->DramcWriteLeveling(PI) begin...
771 22:10:43.566192 ==
772 22:10:43.569540 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:10:43.572894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:10:43.572997 ==
775 22:10:43.576948 Write leveling (Byte 0): 33 => 33
776 22:10:43.580368 Write leveling (Byte 1): 31 => 31
777 22:10:43.583645 DramcWriteLeveling(PI) end<-----
778 22:10:43.583751
779 22:10:43.583845 ==
780 22:10:43.586651 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:10:43.590049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:10:43.590155 ==
783 22:10:43.593415 [Gating] SW mode calibration
784 22:10:43.599899 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:10:43.606644 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:10:43.610021 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:10:43.613110 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 22:10:43.619822 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 22:10:43.622921 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 22:10:43.626903 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:10:43.633094 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:10:43.636884 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:10:43.640084 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:10:43.646322 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:10:43.649904 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:10:43.653139 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:10:43.659807 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:10:43.662966 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:10:43.666430 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:10:43.672971 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:10:43.676403 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:10:43.679760 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:10:43.685996 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 22:10:43.689857 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 22:10:43.692867 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
806 22:10:43.699703 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:10:43.702454 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:10:43.705885 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:10:43.712780 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:10:43.716157 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:10:43.719162 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:10:43.722659 0 9 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
813 22:10:43.729220 0 9 12 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
814 22:10:43.732793 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:10:43.736187 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:10:43.742337 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:10:43.745679 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:10:43.748955 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:10:43.755728 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
820 22:10:43.759199 0 10 8 | B1->B0 | 3434 2929 | 0 0 | (0 1) (0 0)
821 22:10:43.762196 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
822 22:10:43.769269 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:10:43.772775 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:10:43.776547 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:10:43.779807 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:10:43.787020 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:10:43.790282 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
828 22:10:43.793828 0 11 8 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
829 22:10:43.797873 0 11 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
830 22:10:43.805212 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:10:43.808284 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:10:43.812279 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:10:43.815554 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:10:43.819279 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 22:10:43.826843 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 22:10:43.830465 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 22:10:43.833599 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:10:43.837307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:10:43.843637 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:10:43.847075 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:10:43.850562 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:10:43.856896 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:10:43.860550 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:10:43.863903 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:10:43.870405 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:10:43.873882 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:10:43.877065 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:10:43.883653 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:10:43.887146 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:10:43.891304 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:10:43.895081 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 22:10:43.898307 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 22:10:43.905515 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 22:10:43.905622 Total UI for P1: 0, mck2ui 16
855 22:10:43.909404 best dqsien dly found for B0: ( 0, 14, 8)
856 22:10:43.915980 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 22:10:43.919455 Total UI for P1: 0, mck2ui 16
858 22:10:43.922939 best dqsien dly found for B1: ( 0, 14, 10)
859 22:10:43.926255 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
860 22:10:43.929599 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 22:10:43.929701
862 22:10:43.933390 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 22:10:43.936589 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 22:10:43.940048 [Gating] SW calibration Done
865 22:10:43.940165 ==
866 22:10:43.943362 Dram Type= 6, Freq= 0, CH_0, rank 0
867 22:10:43.946680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 22:10:43.946763 ==
869 22:10:43.950327 RX Vref Scan: 0
870 22:10:43.950434
871 22:10:43.950545 RX Vref 0 -> 0, step: 1
872 22:10:43.950652
873 22:10:43.953201 RX Delay -130 -> 252, step: 16
874 22:10:43.956680 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 22:10:43.963453 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 22:10:43.966804 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 22:10:43.970201 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 22:10:43.973476 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 22:10:43.976269 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 22:10:43.983127 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
881 22:10:43.986391 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
882 22:10:43.989755 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
883 22:10:43.993277 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
884 22:10:43.996654 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 22:10:44.003543 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
886 22:10:44.006771 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 22:10:44.010098 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 22:10:44.012959 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 22:10:44.016250 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 22:10:44.019619 ==
891 22:10:44.019700 Dram Type= 6, Freq= 0, CH_0, rank 0
892 22:10:44.026808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 22:10:44.026892 ==
894 22:10:44.026956 DQS Delay:
895 22:10:44.029783 DQS0 = 0, DQS1 = 0
896 22:10:44.029875 DQM Delay:
897 22:10:44.033197 DQM0 = 87, DQM1 = 77
898 22:10:44.033277 DQ Delay:
899 22:10:44.036584 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 22:10:44.039560 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
901 22:10:44.043268 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =77
902 22:10:44.046310 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
903 22:10:44.046392
904 22:10:44.046457
905 22:10:44.046516 ==
906 22:10:44.049650 Dram Type= 6, Freq= 0, CH_0, rank 0
907 22:10:44.052772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 22:10:44.052854 ==
909 22:10:44.052919
910 22:10:44.053016
911 22:10:44.056414 TX Vref Scan disable
912 22:10:44.059749 == TX Byte 0 ==
913 22:10:44.062833 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 22:10:44.066204 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 22:10:44.069569 == TX Byte 1 ==
916 22:10:44.073051 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
917 22:10:44.076199 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
918 22:10:44.076302 ==
919 22:10:44.079463 Dram Type= 6, Freq= 0, CH_0, rank 0
920 22:10:44.083013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 22:10:44.085763 ==
922 22:10:44.097338 TX Vref=22, minBit 3, minWin=27, winSum=443
923 22:10:44.100763 TX Vref=24, minBit 8, minWin=27, winSum=446
924 22:10:44.104148 TX Vref=26, minBit 8, minWin=27, winSum=447
925 22:10:44.107733 TX Vref=28, minBit 10, minWin=27, winSum=450
926 22:10:44.110890 TX Vref=30, minBit 7, minWin=27, winSum=450
927 22:10:44.117520 TX Vref=32, minBit 9, minWin=26, winSum=444
928 22:10:44.120866 [TxChooseVref] Worse bit 10, Min win 27, Win sum 450, Final Vref 28
929 22:10:44.121006
930 22:10:44.123963 Final TX Range 1 Vref 28
931 22:10:44.124074
932 22:10:44.124170 ==
933 22:10:44.127489 Dram Type= 6, Freq= 0, CH_0, rank 0
934 22:10:44.130429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 22:10:44.133745 ==
936 22:10:44.133851
937 22:10:44.133948
938 22:10:44.134039 TX Vref Scan disable
939 22:10:44.137455 == TX Byte 0 ==
940 22:10:44.140862 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
941 22:10:44.147444 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
942 22:10:44.147556 == TX Byte 1 ==
943 22:10:44.151193 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
944 22:10:44.157384 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
945 22:10:44.157489
946 22:10:44.157584 [DATLAT]
947 22:10:44.157674 Freq=800, CH0 RK0
948 22:10:44.157762
949 22:10:44.161021 DATLAT Default: 0xa
950 22:10:44.161137 0, 0xFFFF, sum = 0
951 22:10:44.164127 1, 0xFFFF, sum = 0
952 22:10:44.164241 2, 0xFFFF, sum = 0
953 22:10:44.167720 3, 0xFFFF, sum = 0
954 22:10:44.170738 4, 0xFFFF, sum = 0
955 22:10:44.170818 5, 0xFFFF, sum = 0
956 22:10:44.174253 6, 0xFFFF, sum = 0
957 22:10:44.174354 7, 0xFFFF, sum = 0
958 22:10:44.177180 8, 0xFFFF, sum = 0
959 22:10:44.177283 9, 0x0, sum = 1
960 22:10:44.180697 10, 0x0, sum = 2
961 22:10:44.180802 11, 0x0, sum = 3
962 22:10:44.180900 12, 0x0, sum = 4
963 22:10:44.183902 best_step = 10
964 22:10:44.184012
965 22:10:44.184104 ==
966 22:10:44.187194 Dram Type= 6, Freq= 0, CH_0, rank 0
967 22:10:44.190855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 22:10:44.190932 ==
969 22:10:44.194080 RX Vref Scan: 1
970 22:10:44.194193
971 22:10:44.197325 Set Vref Range= 32 -> 127
972 22:10:44.197427
973 22:10:44.197519 RX Vref 32 -> 127, step: 1
974 22:10:44.197617
975 22:10:44.200815 RX Delay -111 -> 252, step: 8
976 22:10:44.200916
977 22:10:44.203840 Set Vref, RX VrefLevel [Byte0]: 32
978 22:10:44.207290 [Byte1]: 32
979 22:10:44.210469
980 22:10:44.210572 Set Vref, RX VrefLevel [Byte0]: 33
981 22:10:44.213876 [Byte1]: 33
982 22:10:44.217993
983 22:10:44.218095 Set Vref, RX VrefLevel [Byte0]: 34
984 22:10:44.221290 [Byte1]: 34
985 22:10:44.225964
986 22:10:44.226038 Set Vref, RX VrefLevel [Byte0]: 35
987 22:10:44.229639 [Byte1]: 35
988 22:10:44.233888
989 22:10:44.233990 Set Vref, RX VrefLevel [Byte0]: 36
990 22:10:44.237298 [Byte1]: 36
991 22:10:44.241249
992 22:10:44.241355 Set Vref, RX VrefLevel [Byte0]: 37
993 22:10:44.244940 [Byte1]: 37
994 22:10:44.248892
995 22:10:44.248997 Set Vref, RX VrefLevel [Byte0]: 38
996 22:10:44.252772 [Byte1]: 38
997 22:10:44.256515
998 22:10:44.256619 Set Vref, RX VrefLevel [Byte0]: 39
999 22:10:44.259801 [Byte1]: 39
1000 22:10:44.264648
1001 22:10:44.264754 Set Vref, RX VrefLevel [Byte0]: 40
1002 22:10:44.267988 [Byte1]: 40
1003 22:10:44.271816
1004 22:10:44.271892 Set Vref, RX VrefLevel [Byte0]: 41
1005 22:10:44.275455 [Byte1]: 41
1006 22:10:44.279835
1007 22:10:44.279933 Set Vref, RX VrefLevel [Byte0]: 42
1008 22:10:44.283098 [Byte1]: 42
1009 22:10:44.287167
1010 22:10:44.287269 Set Vref, RX VrefLevel [Byte0]: 43
1011 22:10:44.290346 [Byte1]: 43
1012 22:10:44.295130
1013 22:10:44.295244 Set Vref, RX VrefLevel [Byte0]: 44
1014 22:10:44.298156 [Byte1]: 44
1015 22:10:44.302034
1016 22:10:44.305607 Set Vref, RX VrefLevel [Byte0]: 45
1017 22:10:44.305710 [Byte1]: 45
1018 22:10:44.309726
1019 22:10:44.313346 Set Vref, RX VrefLevel [Byte0]: 46
1020 22:10:44.313453 [Byte1]: 46
1021 22:10:44.317870
1022 22:10:44.317960 Set Vref, RX VrefLevel [Byte0]: 47
1023 22:10:44.321285 [Byte1]: 47
1024 22:10:44.325309
1025 22:10:44.325419 Set Vref, RX VrefLevel [Byte0]: 48
1026 22:10:44.328826 [Byte1]: 48
1027 22:10:44.332697
1028 22:10:44.332797 Set Vref, RX VrefLevel [Byte0]: 49
1029 22:10:44.336064 [Byte1]: 49
1030 22:10:44.340906
1031 22:10:44.341009 Set Vref, RX VrefLevel [Byte0]: 50
1032 22:10:44.344037 [Byte1]: 50
1033 22:10:44.348446
1034 22:10:44.348547 Set Vref, RX VrefLevel [Byte0]: 51
1035 22:10:44.351741 [Byte1]: 51
1036 22:10:44.355940
1037 22:10:44.356040 Set Vref, RX VrefLevel [Byte0]: 52
1038 22:10:44.359595 [Byte1]: 52
1039 22:10:44.364211
1040 22:10:44.364387 Set Vref, RX VrefLevel [Byte0]: 53
1041 22:10:44.367086 [Byte1]: 53
1042 22:10:44.371146
1043 22:10:44.374681 Set Vref, RX VrefLevel [Byte0]: 54
1044 22:10:44.374771 [Byte1]: 54
1045 22:10:44.378924
1046 22:10:44.379006 Set Vref, RX VrefLevel [Byte0]: 55
1047 22:10:44.382065 [Byte1]: 55
1048 22:10:44.386981
1049 22:10:44.387065 Set Vref, RX VrefLevel [Byte0]: 56
1050 22:10:44.389854 [Byte1]: 56
1051 22:10:44.394104
1052 22:10:44.394194 Set Vref, RX VrefLevel [Byte0]: 57
1053 22:10:44.397246 [Byte1]: 57
1054 22:10:44.402562
1055 22:10:44.402685 Set Vref, RX VrefLevel [Byte0]: 58
1056 22:10:44.404946 [Byte1]: 58
1057 22:10:44.409413
1058 22:10:44.409497 Set Vref, RX VrefLevel [Byte0]: 59
1059 22:10:44.413325 [Byte1]: 59
1060 22:10:44.417059
1061 22:10:44.417163 Set Vref, RX VrefLevel [Byte0]: 60
1062 22:10:44.421085 [Byte1]: 60
1063 22:10:44.424749
1064 22:10:44.424833 Set Vref, RX VrefLevel [Byte0]: 61
1065 22:10:44.428433 [Byte1]: 61
1066 22:10:44.432166
1067 22:10:44.432272 Set Vref, RX VrefLevel [Byte0]: 62
1068 22:10:44.436112 [Byte1]: 62
1069 22:10:44.440097
1070 22:10:44.440200 Set Vref, RX VrefLevel [Byte0]: 63
1071 22:10:44.443298 [Byte1]: 63
1072 22:10:44.447403
1073 22:10:44.450840 Set Vref, RX VrefLevel [Byte0]: 64
1074 22:10:44.450914 [Byte1]: 64
1075 22:10:44.455203
1076 22:10:44.455276 Set Vref, RX VrefLevel [Byte0]: 65
1077 22:10:44.459116 [Byte1]: 65
1078 22:10:44.462740
1079 22:10:44.466354 Set Vref, RX VrefLevel [Byte0]: 66
1080 22:10:44.466458 [Byte1]: 66
1081 22:10:44.470314
1082 22:10:44.470411 Set Vref, RX VrefLevel [Byte0]: 67
1083 22:10:44.473717 [Byte1]: 67
1084 22:10:44.478075
1085 22:10:44.478152 Set Vref, RX VrefLevel [Byte0]: 68
1086 22:10:44.481599 [Byte1]: 68
1087 22:10:44.485900
1088 22:10:44.485996 Set Vref, RX VrefLevel [Byte0]: 69
1089 22:10:44.489659 [Byte1]: 69
1090 22:10:44.493641
1091 22:10:44.493719 Set Vref, RX VrefLevel [Byte0]: 70
1092 22:10:44.496922 [Byte1]: 70
1093 22:10:44.500632
1094 22:10:44.504223 Set Vref, RX VrefLevel [Byte0]: 71
1095 22:10:44.504318 [Byte1]: 71
1096 22:10:44.508819
1097 22:10:44.508916 Set Vref, RX VrefLevel [Byte0]: 72
1098 22:10:44.512187 [Byte1]: 72
1099 22:10:44.516221
1100 22:10:44.516327 Set Vref, RX VrefLevel [Byte0]: 73
1101 22:10:44.519838 [Byte1]: 73
1102 22:10:44.524757
1103 22:10:44.524859 Set Vref, RX VrefLevel [Byte0]: 74
1104 22:10:44.527702 [Byte1]: 74
1105 22:10:44.531134
1106 22:10:44.534595 Set Vref, RX VrefLevel [Byte0]: 75
1107 22:10:44.538722 [Byte1]: 75
1108 22:10:44.538810
1109 22:10:44.541592 Set Vref, RX VrefLevel [Byte0]: 76
1110 22:10:44.545036 [Byte1]: 76
1111 22:10:44.545140
1112 22:10:44.548657 Set Vref, RX VrefLevel [Byte0]: 77
1113 22:10:44.551979 [Byte1]: 77
1114 22:10:44.552080
1115 22:10:44.555291 Set Vref, RX VrefLevel [Byte0]: 78
1116 22:10:44.559269 [Byte1]: 78
1117 22:10:44.559391
1118 22:10:44.562756 Set Vref, RX VrefLevel [Byte0]: 79
1119 22:10:44.566191 [Byte1]: 79
1120 22:10:44.569912
1121 22:10:44.570016 Final RX Vref Byte 0 = 63 to rank0
1122 22:10:44.573435 Final RX Vref Byte 1 = 60 to rank0
1123 22:10:44.577222 Final RX Vref Byte 0 = 63 to rank1
1124 22:10:44.580997 Final RX Vref Byte 1 = 60 to rank1==
1125 22:10:44.584789 Dram Type= 6, Freq= 0, CH_0, rank 0
1126 22:10:44.588318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1127 22:10:44.588430 ==
1128 22:10:44.588524 DQS Delay:
1129 22:10:44.592311 DQS0 = 0, DQS1 = 0
1130 22:10:44.592408 DQM Delay:
1131 22:10:44.595869 DQM0 = 86, DQM1 = 74
1132 22:10:44.595958 DQ Delay:
1133 22:10:44.599238 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1134 22:10:44.603155 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1135 22:10:44.603301 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1136 22:10:44.606611 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =80
1137 22:10:44.606758
1138 22:10:44.610600
1139 22:10:44.617665 [DQSOSCAuto] RK0, (LSB)MR18= 0x4527, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1140 22:10:44.617762 CH0 RK0: MR19=606, MR18=4527
1141 22:10:44.625146 CH0_RK0: MR19=0x606, MR18=0x4527, DQSOSC=392, MR23=63, INC=96, DEC=64
1142 22:10:44.625229
1143 22:10:44.628426 ----->DramcWriteLeveling(PI) begin...
1144 22:10:44.628508 ==
1145 22:10:44.632205 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 22:10:44.636014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 22:10:44.636129 ==
1148 22:10:44.639910 Write leveling (Byte 0): 33 => 33
1149 22:10:44.643151 Write leveling (Byte 1): 29 => 29
1150 22:10:44.647004 DramcWriteLeveling(PI) end<-----
1151 22:10:44.647086
1152 22:10:44.647150 ==
1153 22:10:44.651127 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 22:10:44.654352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1155 22:10:44.654487 ==
1156 22:10:44.658286 [Gating] SW mode calibration
1157 22:10:44.665088 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1158 22:10:44.709318 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1159 22:10:44.709611 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1160 22:10:44.709688 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1161 22:10:44.709752 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1162 22:10:44.709823 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:10:44.709885 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:10:44.710130 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:10:44.710193 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:10:44.710433 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:10:44.710681 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:10:44.753494 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:10:44.754106 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:10:44.754192 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:10:44.754439 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:10:44.755119 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:10:44.755383 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:10:44.755453 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:10:44.755517 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:10:44.755592 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1177 22:10:44.755661 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1178 22:10:44.797408 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1179 22:10:44.797815 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:10:44.797899 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:10:44.798457 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 22:10:44.798730 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 22:10:44.798810 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 22:10:44.799054 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 22:10:44.799137 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1186 22:10:44.799262 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1187 22:10:44.799355 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 22:10:44.805955 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 22:10:44.809443 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 22:10:44.809525 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 22:10:44.813223 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 22:10:44.819617 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1193 22:10:44.822851 0 10 8 | B1->B0 | 3333 2525 | 0 0 | (0 1) (0 0)
1194 22:10:44.825854 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1195 22:10:44.832498 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:10:44.836171 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:10:44.839254 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 22:10:44.846114 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 22:10:44.849380 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 22:10:44.852584 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1201 22:10:44.859037 0 11 8 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (1 1)
1202 22:10:44.862456 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1203 22:10:44.865736 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 22:10:44.872447 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 22:10:44.875950 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 22:10:44.878885 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 22:10:44.885507 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 22:10:44.888867 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 22:10:44.892176 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1210 22:10:44.898820 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:10:44.902367 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:10:44.905837 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:10:44.909134 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:10:44.915635 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:10:44.918666 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:10:44.921997 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:10:44.928784 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:10:44.932309 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:10:44.935184 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:10:44.941837 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 22:10:44.945334 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 22:10:44.948777 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 22:10:44.954945 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 22:10:44.958537 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 22:10:44.962002 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1226 22:10:44.965505 Total UI for P1: 0, mck2ui 16
1227 22:10:44.968418 best dqsien dly found for B0: ( 0, 14, 6)
1228 22:10:44.975364 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1229 22:10:44.978256 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 22:10:44.982011 Total UI for P1: 0, mck2ui 16
1231 22:10:44.984950 best dqsien dly found for B1: ( 0, 14, 10)
1232 22:10:44.988199 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1233 22:10:44.991711 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1234 22:10:44.991792
1235 22:10:44.995130 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1236 22:10:44.998350 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1237 22:10:45.001408 [Gating] SW calibration Done
1238 22:10:45.001493 ==
1239 22:10:45.004799 Dram Type= 6, Freq= 0, CH_0, rank 1
1240 22:10:45.011318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1241 22:10:45.011401 ==
1242 22:10:45.011465 RX Vref Scan: 0
1243 22:10:45.011532
1244 22:10:45.014663 RX Vref 0 -> 0, step: 1
1245 22:10:45.014763
1246 22:10:45.018028 RX Delay -130 -> 252, step: 16
1247 22:10:45.021711 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1248 22:10:45.024804 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1249 22:10:45.028096 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1250 22:10:45.031710 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1251 22:10:45.037876 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1252 22:10:45.041157 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1253 22:10:45.044508 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1254 22:10:45.047820 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1255 22:10:45.051337 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1256 22:10:45.057960 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1257 22:10:45.061517 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1258 22:10:45.064859 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1259 22:10:45.067735 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1260 22:10:45.074470 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1261 22:10:45.077957 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1262 22:10:45.081173 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1263 22:10:45.081255 ==
1264 22:10:45.084314 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 22:10:45.087406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 22:10:45.087484 ==
1267 22:10:45.090649 DQS Delay:
1268 22:10:45.090747 DQS0 = 0, DQS1 = 0
1269 22:10:45.094613 DQM Delay:
1270 22:10:45.094705 DQM0 = 86, DQM1 = 78
1271 22:10:45.094774 DQ Delay:
1272 22:10:45.097383 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1273 22:10:45.100743 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1274 22:10:45.103932 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =69
1275 22:10:45.107321 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1276 22:10:45.107424
1277 22:10:45.107514
1278 22:10:45.110779 ==
1279 22:10:45.113766 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 22:10:45.117295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 22:10:45.117397 ==
1282 22:10:45.117487
1283 22:10:45.117577
1284 22:10:45.120535 TX Vref Scan disable
1285 22:10:45.120635 == TX Byte 0 ==
1286 22:10:45.127422 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1287 22:10:45.130447 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1288 22:10:45.130561 == TX Byte 1 ==
1289 22:10:45.137417 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1290 22:10:45.140216 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1291 22:10:45.140316 ==
1292 22:10:45.143738 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 22:10:45.146910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 22:10:45.146985 ==
1295 22:10:45.161164 TX Vref=22, minBit 5, minWin=27, winSum=444
1296 22:10:45.164170 TX Vref=24, minBit 3, minWin=27, winSum=444
1297 22:10:45.167564 TX Vref=26, minBit 11, minWin=27, winSum=450
1298 22:10:45.170923 TX Vref=28, minBit 9, minWin=27, winSum=447
1299 22:10:45.173753 TX Vref=30, minBit 9, minWin=27, winSum=446
1300 22:10:45.181266 TX Vref=32, minBit 9, minWin=27, winSum=444
1301 22:10:45.183948 [TxChooseVref] Worse bit 11, Min win 27, Win sum 450, Final Vref 26
1302 22:10:45.184056
1303 22:10:45.187790 Final TX Range 1 Vref 26
1304 22:10:45.187889
1305 22:10:45.187953 ==
1306 22:10:45.190818 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 22:10:45.194100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 22:10:45.197495 ==
1309 22:10:45.197642
1310 22:10:45.197725
1311 22:10:45.197786 TX Vref Scan disable
1312 22:10:45.201357 == TX Byte 0 ==
1313 22:10:45.204268 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1314 22:10:45.207920 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1315 22:10:45.211395 == TX Byte 1 ==
1316 22:10:45.214250 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1317 22:10:45.218080 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1318 22:10:45.221340
1319 22:10:45.221420 [DATLAT]
1320 22:10:45.221484 Freq=800, CH0 RK1
1321 22:10:45.221542
1322 22:10:45.224848 DATLAT Default: 0xa
1323 22:10:45.224954 0, 0xFFFF, sum = 0
1324 22:10:45.227836 1, 0xFFFF, sum = 0
1325 22:10:45.227940 2, 0xFFFF, sum = 0
1326 22:10:45.231160 3, 0xFFFF, sum = 0
1327 22:10:45.234414 4, 0xFFFF, sum = 0
1328 22:10:45.234531 5, 0xFFFF, sum = 0
1329 22:10:45.237991 6, 0xFFFF, sum = 0
1330 22:10:45.238104 7, 0xFFFF, sum = 0
1331 22:10:45.240850 8, 0xFFFF, sum = 0
1332 22:10:45.240959 9, 0x0, sum = 1
1333 22:10:45.241053 10, 0x0, sum = 2
1334 22:10:45.244630 11, 0x0, sum = 3
1335 22:10:45.244739 12, 0x0, sum = 4
1336 22:10:45.247813 best_step = 10
1337 22:10:45.247913
1338 22:10:45.248002 ==
1339 22:10:45.251264 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 22:10:45.254168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 22:10:45.254250 ==
1342 22:10:45.257529 RX Vref Scan: 0
1343 22:10:45.257602
1344 22:10:45.257668 RX Vref 0 -> 0, step: 1
1345 22:10:45.260724
1346 22:10:45.260822 RX Delay -95 -> 252, step: 8
1347 22:10:45.267848 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1348 22:10:45.270901 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1349 22:10:45.274095 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1350 22:10:45.277495 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1351 22:10:45.280978 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1352 22:10:45.287699 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1353 22:10:45.290619 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1354 22:10:45.294668 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1355 22:10:45.297369 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1356 22:10:45.300777 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1357 22:10:45.307319 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1358 22:10:45.310666 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1359 22:10:45.314056 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1360 22:10:45.317266 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1361 22:10:45.324131 iDelay=209, Bit 14, Center 88 (-31 ~ 208) 240
1362 22:10:45.327476 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1363 22:10:45.327573 ==
1364 22:10:45.330775 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 22:10:45.334231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 22:10:45.334329 ==
1367 22:10:45.334419 DQS Delay:
1368 22:10:45.337375 DQS0 = 0, DQS1 = 0
1369 22:10:45.337474 DQM Delay:
1370 22:10:45.340620 DQM0 = 84, DQM1 = 77
1371 22:10:45.340723 DQ Delay:
1372 22:10:45.344277 DQ0 =80, DQ1 =92, DQ2 =76, DQ3 =84
1373 22:10:45.347421 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1374 22:10:45.350969 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1375 22:10:45.353939 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =84
1376 22:10:45.354038
1377 22:10:45.354128
1378 22:10:45.364051 [DQSOSCAuto] RK1, (LSB)MR18= 0x450b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
1379 22:10:45.364159 CH0 RK1: MR19=606, MR18=450B
1380 22:10:45.370895 CH0_RK1: MR19=0x606, MR18=0x450B, DQSOSC=392, MR23=63, INC=96, DEC=64
1381 22:10:45.374148 [RxdqsGatingPostProcess] freq 800
1382 22:10:45.380374 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1383 22:10:45.383569 Pre-setting of DQS Precalculation
1384 22:10:45.387212 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1385 22:10:45.387287 ==
1386 22:10:45.390307 Dram Type= 6, Freq= 0, CH_1, rank 0
1387 22:10:45.396953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 22:10:45.397059 ==
1389 22:10:45.400512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1390 22:10:45.407315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1391 22:10:45.416175 [CA 0] Center 36 (6~67) winsize 62
1392 22:10:45.419207 [CA 1] Center 36 (6~67) winsize 62
1393 22:10:45.422727 [CA 2] Center 34 (4~65) winsize 62
1394 22:10:45.426291 [CA 3] Center 34 (4~65) winsize 62
1395 22:10:45.429041 [CA 4] Center 34 (4~65) winsize 62
1396 22:10:45.432614 [CA 5] Center 34 (3~65) winsize 63
1397 22:10:45.432719
1398 22:10:45.435782 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1399 22:10:45.435889
1400 22:10:45.439339 [CATrainingPosCal] consider 1 rank data
1401 22:10:45.442324 u2DelayCellTimex100 = 270/100 ps
1402 22:10:45.445873 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1403 22:10:45.452295 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1404 22:10:45.455722 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1405 22:10:45.458901 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1406 22:10:45.462388 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1407 22:10:45.465382 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1408 22:10:45.465487
1409 22:10:45.468520 CA PerBit enable=1, Macro0, CA PI delay=34
1410 22:10:45.468620
1411 22:10:45.471750 [CBTSetCACLKResult] CA Dly = 34
1412 22:10:45.474955 CS Dly: 5 (0~36)
1413 22:10:45.475054 ==
1414 22:10:45.478201 Dram Type= 6, Freq= 0, CH_1, rank 1
1415 22:10:45.482180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 22:10:45.482280 ==
1417 22:10:45.488538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1418 22:10:45.491670 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1419 22:10:45.502263 [CA 0] Center 36 (6~67) winsize 62
1420 22:10:45.505476 [CA 1] Center 36 (6~67) winsize 62
1421 22:10:45.508967 [CA 2] Center 34 (4~65) winsize 62
1422 22:10:45.512198 [CA 3] Center 34 (3~65) winsize 63
1423 22:10:45.515616 [CA 4] Center 34 (4~65) winsize 62
1424 22:10:45.519064 [CA 5] Center 34 (3~65) winsize 63
1425 22:10:45.519139
1426 22:10:45.522401 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1427 22:10:45.522503
1428 22:10:45.525326 [CATrainingPosCal] consider 2 rank data
1429 22:10:45.528770 u2DelayCellTimex100 = 270/100 ps
1430 22:10:45.532074 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1431 22:10:45.535390 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 22:10:45.542273 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1433 22:10:45.545343 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1434 22:10:45.548768 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 22:10:45.552269 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1436 22:10:45.552374
1437 22:10:45.555428 CA PerBit enable=1, Macro0, CA PI delay=34
1438 22:10:45.555533
1439 22:10:45.558306 [CBTSetCACLKResult] CA Dly = 34
1440 22:10:45.558407 CS Dly: 6 (0~38)
1441 22:10:45.561763
1442 22:10:45.565513 ----->DramcWriteLeveling(PI) begin...
1443 22:10:45.565620 ==
1444 22:10:45.568697 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 22:10:45.572221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 22:10:45.572323 ==
1447 22:10:45.574990 Write leveling (Byte 0): 28 => 28
1448 22:10:45.578307 Write leveling (Byte 1): 28 => 28
1449 22:10:45.581986 DramcWriteLeveling(PI) end<-----
1450 22:10:45.582063
1451 22:10:45.582157 ==
1452 22:10:45.585020 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 22:10:45.588543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1454 22:10:45.588648 ==
1455 22:10:45.592039 [Gating] SW mode calibration
1456 22:10:45.598691 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1457 22:10:45.605344 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1458 22:10:45.608315 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1459 22:10:45.611510 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1460 22:10:45.618687 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:10:45.621506 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:10:45.624608 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:10:45.631466 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:10:45.634996 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:10:45.638253 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:10:45.641273 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:10:45.648049 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:10:45.651266 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:10:45.654656 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:10:45.661744 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:10:45.665107 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:10:45.668215 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:10:45.674912 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:10:45.678087 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:10:45.681076 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1476 22:10:45.688340 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1477 22:10:45.691511 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:10:45.694742 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:10:45.701195 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 22:10:45.704481 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 22:10:45.707879 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 22:10:45.714490 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:10:45.718111 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 22:10:45.721656 0 9 8 | B1->B0 | 2d2d 2e2e | 0 1 | (1 1) (1 1)
1485 22:10:45.727720 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 22:10:45.731477 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 22:10:45.734492 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 22:10:45.741064 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 22:10:45.744540 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 22:10:45.747523 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 22:10:45.754358 0 10 4 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
1492 22:10:45.757539 0 10 8 | B1->B0 | 2a2a 2727 | 0 0 | (1 1) (0 0)
1493 22:10:45.760764 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:10:45.767536 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 22:10:45.770801 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 22:10:45.774421 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 22:10:45.780737 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 22:10:45.784590 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 22:10:45.787544 0 11 4 | B1->B0 | 2323 2525 | 1 0 | (0 0) (0 0)
1500 22:10:45.793975 0 11 8 | B1->B0 | 3636 4040 | 1 1 | (0 0) (0 0)
1501 22:10:45.797378 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 22:10:45.800531 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 22:10:45.807112 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 22:10:45.810773 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 22:10:45.814074 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 22:10:45.817305 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 22:10:45.824038 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1508 22:10:45.827337 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:10:45.830534 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:10:45.837264 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:10:45.840718 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:10:45.844399 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:10:45.850545 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:10:45.854152 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:10:45.857510 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:10:45.863712 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:10:45.867022 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 22:10:45.870257 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 22:10:45.876811 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 22:10:45.880329 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 22:10:45.883695 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 22:10:45.890129 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 22:10:45.893796 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1524 22:10:45.896813 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1525 22:10:45.900306 Total UI for P1: 0, mck2ui 16
1526 22:10:45.903731 best dqsien dly found for B0: ( 0, 14, 4)
1527 22:10:45.910254 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 22:10:45.910357 Total UI for P1: 0, mck2ui 16
1529 22:10:45.917103 best dqsien dly found for B1: ( 0, 14, 6)
1530 22:10:45.920375 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1531 22:10:45.923567 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1532 22:10:45.923670
1533 22:10:45.926747 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1534 22:10:45.929945 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1535 22:10:45.933291 [Gating] SW calibration Done
1536 22:10:45.933396 ==
1537 22:10:45.936816 Dram Type= 6, Freq= 0, CH_1, rank 0
1538 22:10:45.940029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1539 22:10:45.940132 ==
1540 22:10:45.943272 RX Vref Scan: 0
1541 22:10:45.943374
1542 22:10:45.943469 RX Vref 0 -> 0, step: 1
1543 22:10:45.943557
1544 22:10:45.946815 RX Delay -130 -> 252, step: 16
1545 22:10:45.949994 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1546 22:10:45.956766 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1547 22:10:45.960199 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1548 22:10:45.963498 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1549 22:10:45.966921 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1550 22:10:45.970056 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1551 22:10:45.976322 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1552 22:10:45.979822 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1553 22:10:45.983082 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1554 22:10:45.986685 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1555 22:10:45.989559 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1556 22:10:45.996172 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1557 22:10:45.999502 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1558 22:10:46.003094 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1559 22:10:46.006309 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1560 22:10:46.012697 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1561 22:10:46.012802 ==
1562 22:10:46.015932 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 22:10:46.019792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 22:10:46.019893 ==
1565 22:10:46.019983 DQS Delay:
1566 22:10:46.023013 DQS0 = 0, DQS1 = 0
1567 22:10:46.023087 DQM Delay:
1568 22:10:46.026434 DQM0 = 89, DQM1 = 79
1569 22:10:46.026534 DQ Delay:
1570 22:10:46.029220 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1571 22:10:46.032538 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1572 22:10:46.036018 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1573 22:10:46.039117 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1574 22:10:46.039195
1575 22:10:46.039287
1576 22:10:46.039374 ==
1577 22:10:46.042925 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 22:10:46.045983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 22:10:46.046061 ==
1580 22:10:46.049211
1581 22:10:46.049310
1582 22:10:46.049400 TX Vref Scan disable
1583 22:10:46.052532 == TX Byte 0 ==
1584 22:10:46.056246 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1585 22:10:46.059350 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1586 22:10:46.062827 == TX Byte 1 ==
1587 22:10:46.065618 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1588 22:10:46.069430 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1589 22:10:46.069539 ==
1590 22:10:46.072468 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 22:10:46.079115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 22:10:46.079192 ==
1593 22:10:46.091012 TX Vref=22, minBit 8, minWin=27, winSum=443
1594 22:10:46.094522 TX Vref=24, minBit 15, minWin=26, winSum=447
1595 22:10:46.097940 TX Vref=26, minBit 8, minWin=27, winSum=448
1596 22:10:46.100944 TX Vref=28, minBit 9, minWin=27, winSum=451
1597 22:10:46.104646 TX Vref=30, minBit 9, minWin=27, winSum=450
1598 22:10:46.111132 TX Vref=32, minBit 9, minWin=27, winSum=446
1599 22:10:46.114065 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 28
1600 22:10:46.114167
1601 22:10:46.117436 Final TX Range 1 Vref 28
1602 22:10:46.117535
1603 22:10:46.117628 ==
1604 22:10:46.120727 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 22:10:46.123902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 22:10:46.127193 ==
1607 22:10:46.127292
1608 22:10:46.127384
1609 22:10:46.127472 TX Vref Scan disable
1610 22:10:46.131234 == TX Byte 0 ==
1611 22:10:46.134267 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1612 22:10:46.137536 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1613 22:10:46.141330 == TX Byte 1 ==
1614 22:10:46.144224 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1615 22:10:46.147821 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1616 22:10:46.151238
1617 22:10:46.151317 [DATLAT]
1618 22:10:46.151380 Freq=800, CH1 RK0
1619 22:10:46.151439
1620 22:10:46.154135 DATLAT Default: 0xa
1621 22:10:46.154207 0, 0xFFFF, sum = 0
1622 22:10:46.157883 1, 0xFFFF, sum = 0
1623 22:10:46.157957 2, 0xFFFF, sum = 0
1624 22:10:46.161390 3, 0xFFFF, sum = 0
1625 22:10:46.161488 4, 0xFFFF, sum = 0
1626 22:10:46.164320 5, 0xFFFF, sum = 0
1627 22:10:46.167952 6, 0xFFFF, sum = 0
1628 22:10:46.168027 7, 0xFFFF, sum = 0
1629 22:10:46.170829 8, 0xFFFF, sum = 0
1630 22:10:46.170903 9, 0x0, sum = 1
1631 22:10:46.170969 10, 0x0, sum = 2
1632 22:10:46.174197 11, 0x0, sum = 3
1633 22:10:46.174299 12, 0x0, sum = 4
1634 22:10:46.177446 best_step = 10
1635 22:10:46.177517
1636 22:10:46.177576 ==
1637 22:10:46.180871 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 22:10:46.184411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 22:10:46.184488 ==
1640 22:10:46.187486 RX Vref Scan: 1
1641 22:10:46.187558
1642 22:10:46.187618 Set Vref Range= 32 -> 127
1643 22:10:46.190765
1644 22:10:46.190835 RX Vref 32 -> 127, step: 1
1645 22:10:46.190899
1646 22:10:46.194265 RX Delay -95 -> 252, step: 8
1647 22:10:46.194361
1648 22:10:46.197376 Set Vref, RX VrefLevel [Byte0]: 32
1649 22:10:46.201070 [Byte1]: 32
1650 22:10:46.201168
1651 22:10:46.204132 Set Vref, RX VrefLevel [Byte0]: 33
1652 22:10:46.207523 [Byte1]: 33
1653 22:10:46.211600
1654 22:10:46.211672 Set Vref, RX VrefLevel [Byte0]: 34
1655 22:10:46.214432 [Byte1]: 34
1656 22:10:46.218828
1657 22:10:46.218905 Set Vref, RX VrefLevel [Byte0]: 35
1658 22:10:46.222194 [Byte1]: 35
1659 22:10:46.226760
1660 22:10:46.226838 Set Vref, RX VrefLevel [Byte0]: 36
1661 22:10:46.230115 [Byte1]: 36
1662 22:10:46.234111
1663 22:10:46.234209 Set Vref, RX VrefLevel [Byte0]: 37
1664 22:10:46.237403 [Byte1]: 37
1665 22:10:46.241757
1666 22:10:46.241860 Set Vref, RX VrefLevel [Byte0]: 38
1667 22:10:46.245164 [Byte1]: 38
1668 22:10:46.249387
1669 22:10:46.249488 Set Vref, RX VrefLevel [Byte0]: 39
1670 22:10:46.252595 [Byte1]: 39
1671 22:10:46.256899
1672 22:10:46.257001 Set Vref, RX VrefLevel [Byte0]: 40
1673 22:10:46.260402 [Byte1]: 40
1674 22:10:46.264570
1675 22:10:46.264675 Set Vref, RX VrefLevel [Byte0]: 41
1676 22:10:46.268083 [Byte1]: 41
1677 22:10:46.272261
1678 22:10:46.272362 Set Vref, RX VrefLevel [Byte0]: 42
1679 22:10:46.276040 [Byte1]: 42
1680 22:10:46.279814
1681 22:10:46.279918 Set Vref, RX VrefLevel [Byte0]: 43
1682 22:10:46.283182 [Byte1]: 43
1683 22:10:46.287193
1684 22:10:46.287268 Set Vref, RX VrefLevel [Byte0]: 44
1685 22:10:46.290899 [Byte1]: 44
1686 22:10:46.295078
1687 22:10:46.295203 Set Vref, RX VrefLevel [Byte0]: 45
1688 22:10:46.298552 [Byte1]: 45
1689 22:10:46.302640
1690 22:10:46.302722 Set Vref, RX VrefLevel [Byte0]: 46
1691 22:10:46.305947 [Byte1]: 46
1692 22:10:46.310159
1693 22:10:46.310240 Set Vref, RX VrefLevel [Byte0]: 47
1694 22:10:46.313364 [Byte1]: 47
1695 22:10:46.317956
1696 22:10:46.318036 Set Vref, RX VrefLevel [Byte0]: 48
1697 22:10:46.321388 [Byte1]: 48
1698 22:10:46.325120
1699 22:10:46.325200 Set Vref, RX VrefLevel [Byte0]: 49
1700 22:10:46.328618 [Byte1]: 49
1701 22:10:46.333227
1702 22:10:46.333308 Set Vref, RX VrefLevel [Byte0]: 50
1703 22:10:46.336058 [Byte1]: 50
1704 22:10:46.340393
1705 22:10:46.340474 Set Vref, RX VrefLevel [Byte0]: 51
1706 22:10:46.343686 [Byte1]: 51
1707 22:10:46.347990
1708 22:10:46.348093 Set Vref, RX VrefLevel [Byte0]: 52
1709 22:10:46.351363 [Byte1]: 52
1710 22:10:46.355618
1711 22:10:46.355718 Set Vref, RX VrefLevel [Byte0]: 53
1712 22:10:46.358742 [Byte1]: 53
1713 22:10:46.363699
1714 22:10:46.363804 Set Vref, RX VrefLevel [Byte0]: 54
1715 22:10:46.366691 [Byte1]: 54
1716 22:10:46.370762
1717 22:10:46.370839 Set Vref, RX VrefLevel [Byte0]: 55
1718 22:10:46.373975 [Byte1]: 55
1719 22:10:46.378468
1720 22:10:46.378572 Set Vref, RX VrefLevel [Byte0]: 56
1721 22:10:46.381692 [Byte1]: 56
1722 22:10:46.386233
1723 22:10:46.386342 Set Vref, RX VrefLevel [Byte0]: 57
1724 22:10:46.389527 [Byte1]: 57
1725 22:10:46.393673
1726 22:10:46.393773 Set Vref, RX VrefLevel [Byte0]: 58
1727 22:10:46.396935 [Byte1]: 58
1728 22:10:46.401269
1729 22:10:46.401380 Set Vref, RX VrefLevel [Byte0]: 59
1730 22:10:46.404548 [Byte1]: 59
1731 22:10:46.409220
1732 22:10:46.409321 Set Vref, RX VrefLevel [Byte0]: 60
1733 22:10:46.412084 [Byte1]: 60
1734 22:10:46.416296
1735 22:10:46.416395 Set Vref, RX VrefLevel [Byte0]: 61
1736 22:10:46.419862 [Byte1]: 61
1737 22:10:46.423778
1738 22:10:46.423879 Set Vref, RX VrefLevel [Byte0]: 62
1739 22:10:46.427318 [Byte1]: 62
1740 22:10:46.431732
1741 22:10:46.431804 Set Vref, RX VrefLevel [Byte0]: 63
1742 22:10:46.434997 [Byte1]: 63
1743 22:10:46.439165
1744 22:10:46.439270 Set Vref, RX VrefLevel [Byte0]: 64
1745 22:10:46.442370 [Byte1]: 64
1746 22:10:46.446752
1747 22:10:46.446852 Set Vref, RX VrefLevel [Byte0]: 65
1748 22:10:46.450358 [Byte1]: 65
1749 22:10:46.454701
1750 22:10:46.454775 Set Vref, RX VrefLevel [Byte0]: 66
1751 22:10:46.457536 [Byte1]: 66
1752 22:10:46.462015
1753 22:10:46.462119 Set Vref, RX VrefLevel [Byte0]: 67
1754 22:10:46.465433 [Byte1]: 67
1755 22:10:46.469771
1756 22:10:46.469865 Set Vref, RX VrefLevel [Byte0]: 68
1757 22:10:46.473043 [Byte1]: 68
1758 22:10:46.477479
1759 22:10:46.477582 Set Vref, RX VrefLevel [Byte0]: 69
1760 22:10:46.480425 [Byte1]: 69
1761 22:10:46.484972
1762 22:10:46.485075 Set Vref, RX VrefLevel [Byte0]: 70
1763 22:10:46.488122 [Byte1]: 70
1764 22:10:46.492682
1765 22:10:46.492781 Set Vref, RX VrefLevel [Byte0]: 71
1766 22:10:46.495965 [Byte1]: 71
1767 22:10:46.500141
1768 22:10:46.500242 Set Vref, RX VrefLevel [Byte0]: 72
1769 22:10:46.503461 [Byte1]: 72
1770 22:10:46.507402
1771 22:10:46.507477 Set Vref, RX VrefLevel [Byte0]: 73
1772 22:10:46.510877 [Byte1]: 73
1773 22:10:46.515255
1774 22:10:46.515357 Set Vref, RX VrefLevel [Byte0]: 74
1775 22:10:46.518687 [Byte1]: 74
1776 22:10:46.522743
1777 22:10:46.522844 Final RX Vref Byte 0 = 56 to rank0
1778 22:10:46.526077 Final RX Vref Byte 1 = 63 to rank0
1779 22:10:46.530018 Final RX Vref Byte 0 = 56 to rank1
1780 22:10:46.532738 Final RX Vref Byte 1 = 63 to rank1==
1781 22:10:46.536344 Dram Type= 6, Freq= 0, CH_1, rank 0
1782 22:10:46.542791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 22:10:46.542896 ==
1784 22:10:46.542990 DQS Delay:
1785 22:10:46.543054 DQS0 = 0, DQS1 = 0
1786 22:10:46.546321 DQM Delay:
1787 22:10:46.546420 DQM0 = 86, DQM1 = 79
1788 22:10:46.549537 DQ Delay:
1789 22:10:46.552943 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1790 22:10:46.555787 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1791 22:10:46.559071 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1792 22:10:46.562753 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1793 22:10:46.562855
1794 22:10:46.562944
1795 22:10:46.569248 [DQSOSCAuto] RK0, (LSB)MR18= 0x331f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1796 22:10:46.572460 CH1 RK0: MR19=606, MR18=331F
1797 22:10:46.579255 CH1_RK0: MR19=0x606, MR18=0x331F, DQSOSC=396, MR23=63, INC=94, DEC=62
1798 22:10:46.579363
1799 22:10:46.582314 ----->DramcWriteLeveling(PI) begin...
1800 22:10:46.582424 ==
1801 22:10:46.585753 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 22:10:46.589015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 22:10:46.589125 ==
1804 22:10:46.592155 Write leveling (Byte 0): 26 => 26
1805 22:10:46.595591 Write leveling (Byte 1): 31 => 31
1806 22:10:46.599381 DramcWriteLeveling(PI) end<-----
1807 22:10:46.599459
1808 22:10:46.599543 ==
1809 22:10:46.602113 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 22:10:46.605620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 22:10:46.605723 ==
1812 22:10:46.608746 [Gating] SW mode calibration
1813 22:10:46.615617 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1814 22:10:46.622409 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1815 22:10:46.625722 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1816 22:10:46.631893 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1817 22:10:46.635659 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:10:46.638480 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:10:46.645420 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:10:46.648908 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:10:46.652141 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:10:46.658745 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:10:46.661976 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:10:46.665228 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:10:46.668699 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:10:46.675154 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:10:46.678376 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:10:46.682223 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:10:46.688789 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:10:46.691802 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:10:46.695427 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:10:46.702262 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1833 22:10:46.705043 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:10:46.708780 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:10:46.715139 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:10:46.718630 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:10:46.722173 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:10:46.728725 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:10:46.731840 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:10:46.735290 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:10:46.741802 0 9 8 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 1)
1842 22:10:46.744959 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 22:10:46.748525 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 22:10:46.755060 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 22:10:46.758415 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 22:10:46.761621 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 22:10:46.768479 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1848 22:10:46.771494 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
1849 22:10:46.775031 0 10 8 | B1->B0 | 2828 2f2f | 0 0 | (1 1) (0 1)
1850 22:10:46.781445 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:10:46.785061 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 22:10:46.788509 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 22:10:46.794803 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:10:46.798148 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:10:46.801350 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 22:10:46.807880 0 11 4 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
1857 22:10:46.811120 0 11 8 | B1->B0 | 4545 3939 | 0 0 | (0 0) (0 0)
1858 22:10:46.814815 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 22:10:46.821175 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 22:10:46.824405 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 22:10:46.827787 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 22:10:46.831291 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 22:10:46.838611 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 22:10:46.841649 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1865 22:10:46.844546 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 22:10:46.851162 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 22:10:46.854569 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 22:10:46.857776 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 22:10:46.864519 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:10:46.867798 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:10:46.870970 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:10:46.878003 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:10:46.880852 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:10:46.884244 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:10:46.891109 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:10:46.894416 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:10:46.897705 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:10:46.904591 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 22:10:46.907895 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1880 22:10:46.910743 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1881 22:10:46.917859 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1882 22:10:46.920893 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 22:10:46.924299 Total UI for P1: 0, mck2ui 16
1884 22:10:46.927410 best dqsien dly found for B0: ( 0, 14, 8)
1885 22:10:46.930938 Total UI for P1: 0, mck2ui 16
1886 22:10:46.934137 best dqsien dly found for B1: ( 0, 14, 4)
1887 22:10:46.937326 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1888 22:10:46.941058 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1889 22:10:46.941162
1890 22:10:46.944043 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1891 22:10:46.950528 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1892 22:10:46.950650 [Gating] SW calibration Done
1893 22:10:46.950716 ==
1894 22:10:46.954413 Dram Type= 6, Freq= 0, CH_1, rank 1
1895 22:10:46.957103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1896 22:10:46.960809 ==
1897 22:10:46.960889 RX Vref Scan: 0
1898 22:10:46.960953
1899 22:10:46.964439 RX Vref 0 -> 0, step: 1
1900 22:10:46.964520
1901 22:10:46.967312 RX Delay -130 -> 252, step: 16
1902 22:10:46.970805 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1903 22:10:46.974067 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1904 22:10:46.977227 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1905 22:10:46.980449 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1906 22:10:46.986899 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1907 22:10:46.990434 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1908 22:10:46.993885 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1909 22:10:46.997233 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1910 22:10:47.000231 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1911 22:10:47.006877 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1912 22:10:47.010353 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1913 22:10:47.013510 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1914 22:10:47.016751 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1915 22:10:47.023467 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1916 22:10:47.026499 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1917 22:10:47.030275 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1918 22:10:47.030356 ==
1919 22:10:47.032994 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 22:10:47.036564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 22:10:47.036646 ==
1922 22:10:47.039857 DQS Delay:
1923 22:10:47.039937 DQS0 = 0, DQS1 = 0
1924 22:10:47.042864 DQM Delay:
1925 22:10:47.042945 DQM0 = 89, DQM1 = 80
1926 22:10:47.043009 DQ Delay:
1927 22:10:47.046222 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1928 22:10:47.049658 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1929 22:10:47.053151 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1930 22:10:47.056178 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1931 22:10:47.056258
1932 22:10:47.056321
1933 22:10:47.059731 ==
1934 22:10:47.063181 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 22:10:47.066344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 22:10:47.066425 ==
1937 22:10:47.066489
1938 22:10:47.066548
1939 22:10:47.069249 TX Vref Scan disable
1940 22:10:47.069346 == TX Byte 0 ==
1941 22:10:47.076001 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1942 22:10:47.079380 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1943 22:10:47.079468 == TX Byte 1 ==
1944 22:10:47.086059 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1945 22:10:47.089353 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1946 22:10:47.089434 ==
1947 22:10:47.092991 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 22:10:47.096317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 22:10:47.096398 ==
1950 22:10:47.110106 TX Vref=22, minBit 8, minWin=26, winSum=441
1951 22:10:47.113412 TX Vref=24, minBit 8, minWin=27, winSum=448
1952 22:10:47.116612 TX Vref=26, minBit 8, minWin=27, winSum=451
1953 22:10:47.120097 TX Vref=28, minBit 8, minWin=27, winSum=448
1954 22:10:47.123499 TX Vref=30, minBit 8, minWin=27, winSum=450
1955 22:10:47.126820 TX Vref=32, minBit 8, minWin=27, winSum=451
1956 22:10:47.133572 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 26
1957 22:10:47.133654
1958 22:10:47.136598 Final TX Range 1 Vref 26
1959 22:10:47.136679
1960 22:10:47.136743 ==
1961 22:10:47.140082 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 22:10:47.143439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 22:10:47.143529 ==
1964 22:10:47.146835
1965 22:10:47.146915
1966 22:10:47.146979 TX Vref Scan disable
1967 22:10:47.149873 == TX Byte 0 ==
1968 22:10:47.153532 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1969 22:10:47.159899 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1970 22:10:47.159996 == TX Byte 1 ==
1971 22:10:47.163175 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1972 22:10:47.169733 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1973 22:10:47.169840
1974 22:10:47.169937 [DATLAT]
1975 22:10:47.170031 Freq=800, CH1 RK1
1976 22:10:47.170120
1977 22:10:47.173309 DATLAT Default: 0xa
1978 22:10:47.173409 0, 0xFFFF, sum = 0
1979 22:10:47.176218 1, 0xFFFF, sum = 0
1980 22:10:47.176320 2, 0xFFFF, sum = 0
1981 22:10:47.179591 3, 0xFFFF, sum = 0
1982 22:10:47.182976 4, 0xFFFF, sum = 0
1983 22:10:47.183078 5, 0xFFFF, sum = 0
1984 22:10:47.186752 6, 0xFFFF, sum = 0
1985 22:10:47.186891 7, 0xFFFF, sum = 0
1986 22:10:47.189917 8, 0xFFFF, sum = 0
1987 22:10:47.189994 9, 0x0, sum = 1
1988 22:10:47.190057 10, 0x0, sum = 2
1989 22:10:47.192931 11, 0x0, sum = 3
1990 22:10:47.193033 12, 0x0, sum = 4
1991 22:10:47.196669 best_step = 10
1992 22:10:47.196766
1993 22:10:47.196856 ==
1994 22:10:47.200117 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 22:10:47.202842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 22:10:47.202919 ==
1997 22:10:47.206221 RX Vref Scan: 0
1998 22:10:47.206291
1999 22:10:47.206372 RX Vref 0 -> 0, step: 1
2000 22:10:47.206459
2001 22:10:47.209824 RX Delay -95 -> 252, step: 8
2002 22:10:47.216528 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2003 22:10:47.220133 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2004 22:10:47.223357 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2005 22:10:47.226391 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2006 22:10:47.229802 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2007 22:10:47.236458 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2008 22:10:47.239793 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2009 22:10:47.243232 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2010 22:10:47.246779 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2011 22:10:47.249654 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2012 22:10:47.256938 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2013 22:10:47.259538 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2014 22:10:47.263152 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2015 22:10:47.266360 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2016 22:10:47.273206 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2017 22:10:47.276169 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2018 22:10:47.276271 ==
2019 22:10:47.279607 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 22:10:47.283068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 22:10:47.283184 ==
2022 22:10:47.283280 DQS Delay:
2023 22:10:47.286474 DQS0 = 0, DQS1 = 0
2024 22:10:47.286557 DQM Delay:
2025 22:10:47.289893 DQM0 = 87, DQM1 = 78
2026 22:10:47.289973 DQ Delay:
2027 22:10:47.293062 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2028 22:10:47.296763 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2029 22:10:47.299691 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2030 22:10:47.303003 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2031 22:10:47.303083
2032 22:10:47.303148
2033 22:10:47.312842 [DQSOSCAuto] RK1, (LSB)MR18= 0x1810, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2034 22:10:47.312925 CH1 RK1: MR19=606, MR18=1810
2035 22:10:47.319696 CH1_RK1: MR19=0x606, MR18=0x1810, DQSOSC=403, MR23=63, INC=90, DEC=60
2036 22:10:47.322527 [RxdqsGatingPostProcess] freq 800
2037 22:10:47.329348 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2038 22:10:47.332687 Pre-setting of DQS Precalculation
2039 22:10:47.335818 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2040 22:10:47.342728 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2041 22:10:47.352998 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2042 22:10:47.353080
2043 22:10:47.353142
2044 22:10:47.356177 [Calibration Summary] 1600 Mbps
2045 22:10:47.356258 CH 0, Rank 0
2046 22:10:47.359612 SW Impedance : PASS
2047 22:10:47.359693 DUTY Scan : NO K
2048 22:10:47.362614 ZQ Calibration : PASS
2049 22:10:47.366085 Jitter Meter : NO K
2050 22:10:47.366166 CBT Training : PASS
2051 22:10:47.369452 Write leveling : PASS
2052 22:10:47.369533 RX DQS gating : PASS
2053 22:10:47.372829 RX DQ/DQS(RDDQC) : PASS
2054 22:10:47.375878 TX DQ/DQS : PASS
2055 22:10:47.375959 RX DATLAT : PASS
2056 22:10:47.379295 RX DQ/DQS(Engine): PASS
2057 22:10:47.382496 TX OE : NO K
2058 22:10:47.382601 All Pass.
2059 22:10:47.382683
2060 22:10:47.382744 CH 0, Rank 1
2061 22:10:47.385828 SW Impedance : PASS
2062 22:10:47.389255 DUTY Scan : NO K
2063 22:10:47.389336 ZQ Calibration : PASS
2064 22:10:47.392663 Jitter Meter : NO K
2065 22:10:47.395875 CBT Training : PASS
2066 22:10:47.395955 Write leveling : PASS
2067 22:10:47.399439 RX DQS gating : PASS
2068 22:10:47.402401 RX DQ/DQS(RDDQC) : PASS
2069 22:10:47.402482 TX DQ/DQS : PASS
2070 22:10:47.406020 RX DATLAT : PASS
2071 22:10:47.409729 RX DQ/DQS(Engine): PASS
2072 22:10:47.409810 TX OE : NO K
2073 22:10:47.409875 All Pass.
2074 22:10:47.412693
2075 22:10:47.412773 CH 1, Rank 0
2076 22:10:47.415598 SW Impedance : PASS
2077 22:10:47.415679 DUTY Scan : NO K
2078 22:10:47.419068 ZQ Calibration : PASS
2079 22:10:47.422469 Jitter Meter : NO K
2080 22:10:47.422550 CBT Training : PASS
2081 22:10:47.426001 Write leveling : PASS
2082 22:10:47.426082 RX DQS gating : PASS
2083 22:10:47.428919 RX DQ/DQS(RDDQC) : PASS
2084 22:10:47.432368 TX DQ/DQS : PASS
2085 22:10:47.432449 RX DATLAT : PASS
2086 22:10:47.435401 RX DQ/DQS(Engine): PASS
2087 22:10:47.439020 TX OE : NO K
2088 22:10:47.439150 All Pass.
2089 22:10:47.439216
2090 22:10:47.439277 CH 1, Rank 1
2091 22:10:47.442342 SW Impedance : PASS
2092 22:10:47.445763 DUTY Scan : NO K
2093 22:10:47.445844 ZQ Calibration : PASS
2094 22:10:47.448951 Jitter Meter : NO K
2095 22:10:47.452201 CBT Training : PASS
2096 22:10:47.452282 Write leveling : PASS
2097 22:10:47.455371 RX DQS gating : PASS
2098 22:10:47.458629 RX DQ/DQS(RDDQC) : PASS
2099 22:10:47.458723 TX DQ/DQS : PASS
2100 22:10:47.461970 RX DATLAT : PASS
2101 22:10:47.465435 RX DQ/DQS(Engine): PASS
2102 22:10:47.465515 TX OE : NO K
2103 22:10:47.465580 All Pass.
2104 22:10:47.468971
2105 22:10:47.469051 DramC Write-DBI off
2106 22:10:47.471819 PER_BANK_REFRESH: Hybrid Mode
2107 22:10:47.471901 TX_TRACKING: ON
2108 22:10:47.475034 [GetDramInforAfterCalByMRR] Vendor 6.
2109 22:10:47.481943 [GetDramInforAfterCalByMRR] Revision 606.
2110 22:10:47.485232 [GetDramInforAfterCalByMRR] Revision 2 0.
2111 22:10:47.485313 MR0 0x3b3b
2112 22:10:47.485376 MR8 0x5151
2113 22:10:47.488646 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 22:10:47.488727
2115 22:10:47.491953 MR0 0x3b3b
2116 22:10:47.492033 MR8 0x5151
2117 22:10:47.495416 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 22:10:47.495497
2119 22:10:47.505357 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2120 22:10:47.508429 [FAST_K] Save calibration result to emmc
2121 22:10:47.511660 [FAST_K] Save calibration result to emmc
2122 22:10:47.515359 dram_init: config_dvfs: 1
2123 22:10:47.518464 dramc_set_vcore_voltage set vcore to 662500
2124 22:10:47.521556 Read voltage for 1200, 2
2125 22:10:47.521637 Vio18 = 0
2126 22:10:47.521701 Vcore = 662500
2127 22:10:47.524863 Vdram = 0
2128 22:10:47.524947 Vddq = 0
2129 22:10:47.525011 Vmddr = 0
2130 22:10:47.531759 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2131 22:10:47.534696 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2132 22:10:47.538395 MEM_TYPE=3, freq_sel=15
2133 22:10:47.541782 sv_algorithm_assistance_LP4_1600
2134 22:10:47.544579 ============ PULL DRAM RESETB DOWN ============
2135 22:10:47.547757 ========== PULL DRAM RESETB DOWN end =========
2136 22:10:47.554405 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 22:10:47.557842 ===================================
2138 22:10:47.561169 LPDDR4 DRAM CONFIGURATION
2139 22:10:47.564629 ===================================
2140 22:10:47.564711 EX_ROW_EN[0] = 0x0
2141 22:10:47.568096 EX_ROW_EN[1] = 0x0
2142 22:10:47.568176 LP4Y_EN = 0x0
2143 22:10:47.570940 WORK_FSP = 0x0
2144 22:10:47.571020 WL = 0x4
2145 22:10:47.574837 RL = 0x4
2146 22:10:47.574918 BL = 0x2
2147 22:10:47.577579 RPST = 0x0
2148 22:10:47.577660 RD_PRE = 0x0
2149 22:10:47.581052 WR_PRE = 0x1
2150 22:10:47.581132 WR_PST = 0x0
2151 22:10:47.584651 DBI_WR = 0x0
2152 22:10:47.584745 DBI_RD = 0x0
2153 22:10:47.587867 OTF = 0x1
2154 22:10:47.591346 ===================================
2155 22:10:47.594788 ===================================
2156 22:10:47.594895 ANA top config
2157 22:10:47.598204 ===================================
2158 22:10:47.601056 DLL_ASYNC_EN = 0
2159 22:10:47.604253 ALL_SLAVE_EN = 0
2160 22:10:47.607856 NEW_RANK_MODE = 1
2161 22:10:47.607957 DLL_IDLE_MODE = 1
2162 22:10:47.611338 LP45_APHY_COMB_EN = 1
2163 22:10:47.614506 TX_ODT_DIS = 1
2164 22:10:47.618250 NEW_8X_MODE = 1
2165 22:10:47.620898 ===================================
2166 22:10:47.624141 ===================================
2167 22:10:47.627883 data_rate = 2400
2168 22:10:47.627989 CKR = 1
2169 22:10:47.631041 DQ_P2S_RATIO = 8
2170 22:10:47.634309 ===================================
2171 22:10:47.637783 CA_P2S_RATIO = 8
2172 22:10:47.641016 DQ_CA_OPEN = 0
2173 22:10:47.644711 DQ_SEMI_OPEN = 0
2174 22:10:47.648018 CA_SEMI_OPEN = 0
2175 22:10:47.648121 CA_FULL_RATE = 0
2176 22:10:47.650997 DQ_CKDIV4_EN = 0
2177 22:10:47.654443 CA_CKDIV4_EN = 0
2178 22:10:47.657703 CA_PREDIV_EN = 0
2179 22:10:47.661132 PH8_DLY = 17
2180 22:10:47.664281 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2181 22:10:47.664381 DQ_AAMCK_DIV = 4
2182 22:10:47.667510 CA_AAMCK_DIV = 4
2183 22:10:47.671007 CA_ADMCK_DIV = 4
2184 22:10:47.674500 DQ_TRACK_CA_EN = 0
2185 22:10:47.677450 CA_PICK = 1200
2186 22:10:47.680773 CA_MCKIO = 1200
2187 22:10:47.684232 MCKIO_SEMI = 0
2188 22:10:47.684335 PLL_FREQ = 2366
2189 22:10:47.687536 DQ_UI_PI_RATIO = 32
2190 22:10:47.690793 CA_UI_PI_RATIO = 0
2191 22:10:47.693795 ===================================
2192 22:10:47.697686 ===================================
2193 22:10:47.701052 memory_type:LPDDR4
2194 22:10:47.704374 GP_NUM : 10
2195 22:10:47.704471 SRAM_EN : 1
2196 22:10:47.707083 MD32_EN : 0
2197 22:10:47.710500 ===================================
2198 22:10:47.710574 [ANA_INIT] >>>>>>>>>>>>>>
2199 22:10:47.713913 <<<<<< [CONFIGURE PHASE]: ANA_TX
2200 22:10:47.717490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2201 22:10:47.720293 ===================================
2202 22:10:47.723702 data_rate = 2400,PCW = 0X5b00
2203 22:10:47.727030 ===================================
2204 22:10:47.730712 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2205 22:10:47.737395 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 22:10:47.740488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 22:10:47.746971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2208 22:10:47.749998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2209 22:10:47.753327 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2210 22:10:47.757129 [ANA_INIT] flow start
2211 22:10:47.757231 [ANA_INIT] PLL >>>>>>>>
2212 22:10:47.759966 [ANA_INIT] PLL <<<<<<<<
2213 22:10:47.763867 [ANA_INIT] MIDPI >>>>>>>>
2214 22:10:47.763951 [ANA_INIT] MIDPI <<<<<<<<
2215 22:10:47.766633 [ANA_INIT] DLL >>>>>>>>
2216 22:10:47.769934 [ANA_INIT] DLL <<<<<<<<
2217 22:10:47.770016 [ANA_INIT] flow end
2218 22:10:47.776951 ============ LP4 DIFF to SE enter ============
2219 22:10:47.779910 ============ LP4 DIFF to SE exit ============
2220 22:10:47.783356 [ANA_INIT] <<<<<<<<<<<<<
2221 22:10:47.786473 [Flow] Enable top DCM control >>>>>
2222 22:10:47.789910 [Flow] Enable top DCM control <<<<<
2223 22:10:47.789989 Enable DLL master slave shuffle
2224 22:10:47.796594 ==============================================================
2225 22:10:47.800084 Gating Mode config
2226 22:10:47.803383 ==============================================================
2227 22:10:47.806773 Config description:
2228 22:10:47.816614 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2229 22:10:47.823036 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2230 22:10:47.826331 SELPH_MODE 0: By rank 1: By Phase
2231 22:10:47.832935 ==============================================================
2232 22:10:47.836097 GAT_TRACK_EN = 1
2233 22:10:47.839414 RX_GATING_MODE = 2
2234 22:10:47.843053 RX_GATING_TRACK_MODE = 2
2235 22:10:47.846313 SELPH_MODE = 1
2236 22:10:47.849130 PICG_EARLY_EN = 1
2237 22:10:47.849229 VALID_LAT_VALUE = 1
2238 22:10:47.855960 ==============================================================
2239 22:10:47.859196 Enter into Gating configuration >>>>
2240 22:10:47.862392 Exit from Gating configuration <<<<
2241 22:10:47.865907 Enter into DVFS_PRE_config >>>>>
2242 22:10:47.875907 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2243 22:10:47.879127 Exit from DVFS_PRE_config <<<<<
2244 22:10:47.882429 Enter into PICG configuration >>>>
2245 22:10:47.885792 Exit from PICG configuration <<<<
2246 22:10:47.888826 [RX_INPUT] configuration >>>>>
2247 22:10:47.892401 [RX_INPUT] configuration <<<<<
2248 22:10:47.899070 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2249 22:10:47.902329 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2250 22:10:47.909228 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 22:10:47.915415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 22:10:47.921911 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 22:10:47.928405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 22:10:47.931686 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2255 22:10:47.935353 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2256 22:10:47.938311 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2257 22:10:47.945289 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2258 22:10:47.948181 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2259 22:10:47.951720 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 22:10:47.955062 ===================================
2261 22:10:47.958559 LPDDR4 DRAM CONFIGURATION
2262 22:10:47.961745 ===================================
2263 22:10:47.961823 EX_ROW_EN[0] = 0x0
2264 22:10:47.964931 EX_ROW_EN[1] = 0x0
2265 22:10:47.968213 LP4Y_EN = 0x0
2266 22:10:47.968314 WORK_FSP = 0x0
2267 22:10:47.971734 WL = 0x4
2268 22:10:47.971836 RL = 0x4
2269 22:10:47.974920 BL = 0x2
2270 22:10:47.974993 RPST = 0x0
2271 22:10:47.978250 RD_PRE = 0x0
2272 22:10:47.978348 WR_PRE = 0x1
2273 22:10:47.981382 WR_PST = 0x0
2274 22:10:47.981485 DBI_WR = 0x0
2275 22:10:47.984744 DBI_RD = 0x0
2276 22:10:47.984842 OTF = 0x1
2277 22:10:47.988344 ===================================
2278 22:10:47.991460 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2279 22:10:47.997849 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2280 22:10:48.001347 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2281 22:10:48.004600 ===================================
2282 22:10:48.007892 LPDDR4 DRAM CONFIGURATION
2283 22:10:48.011249 ===================================
2284 22:10:48.011325 EX_ROW_EN[0] = 0x10
2285 22:10:48.014821 EX_ROW_EN[1] = 0x0
2286 22:10:48.017603 LP4Y_EN = 0x0
2287 22:10:48.017682 WORK_FSP = 0x0
2288 22:10:48.020997 WL = 0x4
2289 22:10:48.021111 RL = 0x4
2290 22:10:48.024372 BL = 0x2
2291 22:10:48.024508 RPST = 0x0
2292 22:10:48.027932 RD_PRE = 0x0
2293 22:10:48.028036 WR_PRE = 0x1
2294 22:10:48.031125 WR_PST = 0x0
2295 22:10:48.031200 DBI_WR = 0x0
2296 22:10:48.034432 DBI_RD = 0x0
2297 22:10:48.034532 OTF = 0x1
2298 22:10:48.037674 ===================================
2299 22:10:48.044599 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2300 22:10:48.044710 ==
2301 22:10:48.047763 Dram Type= 6, Freq= 0, CH_0, rank 0
2302 22:10:48.051105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2303 22:10:48.054182 ==
2304 22:10:48.054290 [Duty_Offset_Calibration]
2305 22:10:48.057588 B0:1 B1:-1 CA:0
2306 22:10:48.057694
2307 22:10:48.061109 [DutyScan_Calibration_Flow] k_type=0
2308 22:10:48.069326
2309 22:10:48.069428 ==CLK 0==
2310 22:10:48.073197 Final CLK duty delay cell = 0
2311 22:10:48.076050 [0] MAX Duty = 5125%(X100), DQS PI = 24
2312 22:10:48.079433 [0] MIN Duty = 4875%(X100), DQS PI = 8
2313 22:10:48.079536 [0] AVG Duty = 5000%(X100)
2314 22:10:48.079630
2315 22:10:48.083059 CH0 CLK Duty spec in!! Max-Min= 250%
2316 22:10:48.089601 [DutyScan_Calibration_Flow] ====Done====
2317 22:10:48.089705
2318 22:10:48.092581 [DutyScan_Calibration_Flow] k_type=1
2319 22:10:48.107034
2320 22:10:48.107109 ==DQS 0 ==
2321 22:10:48.110412 Final DQS duty delay cell = -4
2322 22:10:48.113827 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2323 22:10:48.117061 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2324 22:10:48.120529 [-4] AVG Duty = 4968%(X100)
2325 22:10:48.120607
2326 22:10:48.120691 ==DQS 1 ==
2327 22:10:48.124104 Final DQS duty delay cell = -4
2328 22:10:48.126926 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2329 22:10:48.130334 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2330 22:10:48.133453 [-4] AVG Duty = 4938%(X100)
2331 22:10:48.133528
2332 22:10:48.137081 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2333 22:10:48.137181
2334 22:10:48.140094 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2335 22:10:48.143380 [DutyScan_Calibration_Flow] ====Done====
2336 22:10:48.143480
2337 22:10:48.146994 [DutyScan_Calibration_Flow] k_type=3
2338 22:10:48.165102
2339 22:10:48.165206 ==DQM 0 ==
2340 22:10:48.168469 Final DQM duty delay cell = 0
2341 22:10:48.171832 [0] MAX Duty = 5062%(X100), DQS PI = 18
2342 22:10:48.174821 [0] MIN Duty = 4875%(X100), DQS PI = 8
2343 22:10:48.174895 [0] AVG Duty = 4968%(X100)
2344 22:10:48.178487
2345 22:10:48.178585 ==DQM 1 ==
2346 22:10:48.182283 Final DQM duty delay cell = 4
2347 22:10:48.184806 [4] MAX Duty = 5187%(X100), DQS PI = 14
2348 22:10:48.188339 [4] MIN Duty = 5031%(X100), DQS PI = 22
2349 22:10:48.191785 [4] AVG Duty = 5109%(X100)
2350 22:10:48.191894
2351 22:10:48.195137 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2352 22:10:48.195212
2353 22:10:48.198103 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2354 22:10:48.201829 [DutyScan_Calibration_Flow] ====Done====
2355 22:10:48.201918
2356 22:10:48.204668 [DutyScan_Calibration_Flow] k_type=2
2357 22:10:48.220667
2358 22:10:48.220755 ==DQ 0 ==
2359 22:10:48.224099 Final DQ duty delay cell = -4
2360 22:10:48.227432 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2361 22:10:48.230744 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2362 22:10:48.234291 [-4] AVG Duty = 4969%(X100)
2363 22:10:48.234400
2364 22:10:48.234505 ==DQ 1 ==
2365 22:10:48.237697 Final DQ duty delay cell = 0
2366 22:10:48.240670 [0] MAX Duty = 5093%(X100), DQS PI = 2
2367 22:10:48.244596 [0] MIN Duty = 5000%(X100), DQS PI = 22
2368 22:10:48.244699 [0] AVG Duty = 5046%(X100)
2369 22:10:48.247716
2370 22:10:48.250965 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2371 22:10:48.251046
2372 22:10:48.254413 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2373 22:10:48.257812 [DutyScan_Calibration_Flow] ====Done====
2374 22:10:48.257913 ==
2375 22:10:48.261149 Dram Type= 6, Freq= 0, CH_1, rank 0
2376 22:10:48.263865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 22:10:48.263938 ==
2378 22:10:48.267653 [Duty_Offset_Calibration]
2379 22:10:48.267731 B0:-1 B1:1 CA:1
2380 22:10:48.267794
2381 22:10:48.271063 [DutyScan_Calibration_Flow] k_type=0
2382 22:10:48.280974
2383 22:10:48.281074 ==CLK 0==
2384 22:10:48.284284 Final CLK duty delay cell = 0
2385 22:10:48.287684 [0] MAX Duty = 5156%(X100), DQS PI = 22
2386 22:10:48.290947 [0] MIN Duty = 4969%(X100), DQS PI = 60
2387 22:10:48.294166 [0] AVG Duty = 5062%(X100)
2388 22:10:48.294266
2389 22:10:48.297626 CH1 CLK Duty spec in!! Max-Min= 187%
2390 22:10:48.300553 [DutyScan_Calibration_Flow] ====Done====
2391 22:10:48.300655
2392 22:10:48.303832 [DutyScan_Calibration_Flow] k_type=1
2393 22:10:48.320198
2394 22:10:48.320304 ==DQS 0 ==
2395 22:10:48.324095 Final DQS duty delay cell = 0
2396 22:10:48.326782 [0] MAX Duty = 5125%(X100), DQS PI = 48
2397 22:10:48.330019 [0] MIN Duty = 4907%(X100), DQS PI = 6
2398 22:10:48.330123 [0] AVG Duty = 5016%(X100)
2399 22:10:48.333479
2400 22:10:48.333582 ==DQS 1 ==
2401 22:10:48.337361 Final DQS duty delay cell = 0
2402 22:10:48.340514 [0] MAX Duty = 5062%(X100), DQS PI = 8
2403 22:10:48.343704 [0] MIN Duty = 4969%(X100), DQS PI = 58
2404 22:10:48.343803 [0] AVG Duty = 5015%(X100)
2405 22:10:48.343897
2406 22:10:48.350066 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2407 22:10:48.350170
2408 22:10:48.353441 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2409 22:10:48.356757 [DutyScan_Calibration_Flow] ====Done====
2410 22:10:48.356869
2411 22:10:48.360147 [DutyScan_Calibration_Flow] k_type=3
2412 22:10:48.375939
2413 22:10:48.376054 ==DQM 0 ==
2414 22:10:48.378951 Final DQM duty delay cell = -4
2415 22:10:48.382186 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2416 22:10:48.385618 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2417 22:10:48.388841 [-4] AVG Duty = 4969%(X100)
2418 22:10:48.388950
2419 22:10:48.389041 ==DQM 1 ==
2420 22:10:48.392386 Final DQM duty delay cell = 0
2421 22:10:48.395463 [0] MAX Duty = 5156%(X100), DQS PI = 2
2422 22:10:48.398966 [0] MIN Duty = 5000%(X100), DQS PI = 28
2423 22:10:48.402511 [0] AVG Duty = 5078%(X100)
2424 22:10:48.402618
2425 22:10:48.405415 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2426 22:10:48.405515
2427 22:10:48.408704 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2428 22:10:48.412264 [DutyScan_Calibration_Flow] ====Done====
2429 22:10:48.412371
2430 22:10:48.415478 [DutyScan_Calibration_Flow] k_type=2
2431 22:10:48.432435
2432 22:10:48.432512 ==DQ 0 ==
2433 22:10:48.435428 Final DQ duty delay cell = 0
2434 22:10:48.438802 [0] MAX Duty = 5156%(X100), DQS PI = 28
2435 22:10:48.442117 [0] MIN Duty = 4907%(X100), DQS PI = 6
2436 22:10:48.442224 [0] AVG Duty = 5031%(X100)
2437 22:10:48.445801
2438 22:10:48.445878 ==DQ 1 ==
2439 22:10:48.449382 Final DQ duty delay cell = 0
2440 22:10:48.452063 [0] MAX Duty = 5124%(X100), DQS PI = 10
2441 22:10:48.455445 [0] MIN Duty = 4969%(X100), DQS PI = 60
2442 22:10:48.455547 [0] AVG Duty = 5046%(X100)
2443 22:10:48.458770
2444 22:10:48.461938 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2445 22:10:48.462038
2446 22:10:48.465602 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2447 22:10:48.468609 [DutyScan_Calibration_Flow] ====Done====
2448 22:10:48.471871 nWR fixed to 30
2449 22:10:48.471947 [ModeRegInit_LP4] CH0 RK0
2450 22:10:48.475307 [ModeRegInit_LP4] CH0 RK1
2451 22:10:48.478719 [ModeRegInit_LP4] CH1 RK0
2452 22:10:48.481903 [ModeRegInit_LP4] CH1 RK1
2453 22:10:48.481977 match AC timing 7
2454 22:10:48.488873 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2455 22:10:48.491816 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2456 22:10:48.495587 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2457 22:10:48.502537 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2458 22:10:48.505053 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2459 22:10:48.505153 ==
2460 22:10:48.508426 Dram Type= 6, Freq= 0, CH_0, rank 0
2461 22:10:48.511892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2462 22:10:48.511996 ==
2463 22:10:48.518317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2464 22:10:48.525025 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2465 22:10:48.532643 [CA 0] Center 39 (9~70) winsize 62
2466 22:10:48.535777 [CA 1] Center 39 (9~69) winsize 61
2467 22:10:48.539082 [CA 2] Center 35 (5~66) winsize 62
2468 22:10:48.542413 [CA 3] Center 35 (5~66) winsize 62
2469 22:10:48.545401 [CA 4] Center 33 (4~63) winsize 60
2470 22:10:48.549121 [CA 5] Center 33 (3~63) winsize 61
2471 22:10:48.549223
2472 22:10:48.552476 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2473 22:10:48.552574
2474 22:10:48.555821 [CATrainingPosCal] consider 1 rank data
2475 22:10:48.558837 u2DelayCellTimex100 = 270/100 ps
2476 22:10:48.562117 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2477 22:10:48.568579 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2478 22:10:48.572027 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2479 22:10:48.575548 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2480 22:10:48.578821 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2481 22:10:48.582162 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2482 22:10:48.582262
2483 22:10:48.585613 CA PerBit enable=1, Macro0, CA PI delay=33
2484 22:10:48.585713
2485 22:10:48.588591 [CBTSetCACLKResult] CA Dly = 33
2486 22:10:48.588698 CS Dly: 8 (0~39)
2487 22:10:48.591875 ==
2488 22:10:48.595065 Dram Type= 6, Freq= 0, CH_0, rank 1
2489 22:10:48.598673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 22:10:48.598784 ==
2491 22:10:48.602342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 22:10:48.608399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2493 22:10:48.617810 [CA 0] Center 39 (9~70) winsize 62
2494 22:10:48.621151 [CA 1] Center 39 (9~70) winsize 62
2495 22:10:48.624463 [CA 2] Center 35 (5~66) winsize 62
2496 22:10:48.627809 [CA 3] Center 34 (4~65) winsize 62
2497 22:10:48.631604 [CA 4] Center 33 (3~64) winsize 62
2498 22:10:48.634745 [CA 5] Center 33 (3~63) winsize 61
2499 22:10:48.634829
2500 22:10:48.637773 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2501 22:10:48.637847
2502 22:10:48.641150 [CATrainingPosCal] consider 2 rank data
2503 22:10:48.644446 u2DelayCellTimex100 = 270/100 ps
2504 22:10:48.647922 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2505 22:10:48.654508 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2506 22:10:48.657812 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2507 22:10:48.661657 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2508 22:10:48.664152 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2509 22:10:48.667835 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2510 22:10:48.667940
2511 22:10:48.671130 CA PerBit enable=1, Macro0, CA PI delay=33
2512 22:10:48.671230
2513 22:10:48.674348 [CBTSetCACLKResult] CA Dly = 33
2514 22:10:48.674451 CS Dly: 8 (0~40)
2515 22:10:48.677751
2516 22:10:48.680887 ----->DramcWriteLeveling(PI) begin...
2517 22:10:48.680993 ==
2518 22:10:48.684486 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 22:10:48.687528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 22:10:48.687630 ==
2521 22:10:48.690865 Write leveling (Byte 0): 34 => 34
2522 22:10:48.694185 Write leveling (Byte 1): 29 => 29
2523 22:10:48.697541 DramcWriteLeveling(PI) end<-----
2524 22:10:48.697645
2525 22:10:48.697735 ==
2526 22:10:48.701028 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 22:10:48.703916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 22:10:48.704016 ==
2529 22:10:48.707365 [Gating] SW mode calibration
2530 22:10:48.714318 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2531 22:10:48.721265 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2532 22:10:48.724042 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2533 22:10:48.727191 0 15 4 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
2534 22:10:48.733785 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 22:10:48.737206 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 22:10:48.740389 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 22:10:48.747150 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 22:10:48.750565 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 22:10:48.753836 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
2540 22:10:48.760423 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2541 22:10:48.763746 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2542 22:10:48.767159 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 22:10:48.773941 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 22:10:48.777064 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 22:10:48.780209 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 22:10:48.783775 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 22:10:48.790125 1 0 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2548 22:10:48.793552 1 1 0 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2549 22:10:48.796905 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2550 22:10:48.803801 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 22:10:48.807186 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 22:10:48.810532 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 22:10:48.816756 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 22:10:48.819978 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 22:10:48.823264 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2556 22:10:48.830413 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2557 22:10:48.833381 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 22:10:48.836833 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 22:10:48.843150 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 22:10:48.846985 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:10:48.849718 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:10:48.856416 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:10:48.859855 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:10:48.863356 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:10:48.869437 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:10:48.872850 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:10:48.876292 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:10:48.882789 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:10:48.886216 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 22:10:48.889692 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 22:10:48.895718 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2572 22:10:48.899437 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2573 22:10:48.902368 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 22:10:48.906072 Total UI for P1: 0, mck2ui 16
2575 22:10:48.909458 best dqsien dly found for B0: ( 1, 3, 30)
2576 22:10:48.912848 Total UI for P1: 0, mck2ui 16
2577 22:10:48.916059 best dqsien dly found for B1: ( 1, 3, 30)
2578 22:10:48.919445 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2579 22:10:48.922229 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2580 22:10:48.925669
2581 22:10:48.928885 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2582 22:10:48.932378 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2583 22:10:48.935505 [Gating] SW calibration Done
2584 22:10:48.935605 ==
2585 22:10:48.939188 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 22:10:48.941913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 22:10:48.942013 ==
2588 22:10:48.945507 RX Vref Scan: 0
2589 22:10:48.945580
2590 22:10:48.945641 RX Vref 0 -> 0, step: 1
2591 22:10:48.945698
2592 22:10:48.948810 RX Delay -40 -> 252, step: 8
2593 22:10:48.952120 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2594 22:10:48.958504 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2595 22:10:48.962395 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2596 22:10:48.965194 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2597 22:10:48.968662 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2598 22:10:48.971962 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2599 22:10:48.975299 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2600 22:10:48.981906 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2601 22:10:48.985330 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2602 22:10:48.988603 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2603 22:10:48.991949 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2604 22:10:48.995258 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2605 22:10:49.001921 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2606 22:10:49.005083 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2607 22:10:49.008331 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2608 22:10:49.011770 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2609 22:10:49.011869 ==
2610 22:10:49.014850 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 22:10:49.021883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 22:10:49.021990 ==
2613 22:10:49.022080 DQS Delay:
2614 22:10:49.024724 DQS0 = 0, DQS1 = 0
2615 22:10:49.024823 DQM Delay:
2616 22:10:49.028587 DQM0 = 119, DQM1 = 107
2617 22:10:49.028693 DQ Delay:
2618 22:10:49.031392 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2619 22:10:49.034822 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2620 22:10:49.038349 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2621 22:10:49.041397 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2622 22:10:49.041517
2623 22:10:49.041668
2624 22:10:49.041781 ==
2625 22:10:49.044872 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 22:10:49.051362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 22:10:49.051446 ==
2628 22:10:49.051507
2629 22:10:49.051582
2630 22:10:49.051669 TX Vref Scan disable
2631 22:10:49.054998 == TX Byte 0 ==
2632 22:10:49.057689 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2633 22:10:49.061294 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2634 22:10:49.064559 == TX Byte 1 ==
2635 22:10:49.067901 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2636 22:10:49.074756 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2637 22:10:49.074838 ==
2638 22:10:49.078114 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 22:10:49.080956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 22:10:49.081037 ==
2641 22:10:49.092829 TX Vref=22, minBit 5, minWin=25, winSum=416
2642 22:10:49.096199 TX Vref=24, minBit 1, minWin=25, winSum=423
2643 22:10:49.099568 TX Vref=26, minBit 13, minWin=26, winSum=432
2644 22:10:49.102449 TX Vref=28, minBit 10, minWin=26, winSum=435
2645 22:10:49.105954 TX Vref=30, minBit 4, minWin=26, winSum=433
2646 22:10:49.112451 TX Vref=32, minBit 4, minWin=26, winSum=427
2647 22:10:49.115813 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
2648 22:10:49.115895
2649 22:10:49.119477 Final TX Range 1 Vref 28
2650 22:10:49.119558
2651 22:10:49.119621 ==
2652 22:10:49.122349 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 22:10:49.125768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 22:10:49.129142 ==
2655 22:10:49.129223
2656 22:10:49.129287
2657 22:10:49.129346 TX Vref Scan disable
2658 22:10:49.133078 == TX Byte 0 ==
2659 22:10:49.136337 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2660 22:10:49.142994 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2661 22:10:49.143075 == TX Byte 1 ==
2662 22:10:49.146021 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2663 22:10:49.152832 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2664 22:10:49.152935
2665 22:10:49.153032 [DATLAT]
2666 22:10:49.153122 Freq=1200, CH0 RK0
2667 22:10:49.153208
2668 22:10:49.156288 DATLAT Default: 0xd
2669 22:10:49.156391 0, 0xFFFF, sum = 0
2670 22:10:49.159011 1, 0xFFFF, sum = 0
2671 22:10:49.162567 2, 0xFFFF, sum = 0
2672 22:10:49.162688 3, 0xFFFF, sum = 0
2673 22:10:49.165696 4, 0xFFFF, sum = 0
2674 22:10:49.165800 5, 0xFFFF, sum = 0
2675 22:10:49.169113 6, 0xFFFF, sum = 0
2676 22:10:49.169186 7, 0xFFFF, sum = 0
2677 22:10:49.172578 8, 0xFFFF, sum = 0
2678 22:10:49.172651 9, 0xFFFF, sum = 0
2679 22:10:49.175852 10, 0xFFFF, sum = 0
2680 22:10:49.175924 11, 0xFFFF, sum = 0
2681 22:10:49.179022 12, 0x0, sum = 1
2682 22:10:49.179101 13, 0x0, sum = 2
2683 22:10:49.182517 14, 0x0, sum = 3
2684 22:10:49.182668 15, 0x0, sum = 4
2685 22:10:49.185994 best_step = 13
2686 22:10:49.186063
2687 22:10:49.186122 ==
2688 22:10:49.188774 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 22:10:49.192161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 22:10:49.192236 ==
2691 22:10:49.192298 RX Vref Scan: 1
2692 22:10:49.195670
2693 22:10:49.195738 Set Vref Range= 32 -> 127
2694 22:10:49.195796
2695 22:10:49.198906 RX Vref 32 -> 127, step: 1
2696 22:10:49.198980
2697 22:10:49.202189 RX Delay -21 -> 252, step: 4
2698 22:10:49.202261
2699 22:10:49.205563 Set Vref, RX VrefLevel [Byte0]: 32
2700 22:10:49.208815 [Byte1]: 32
2701 22:10:49.208899
2702 22:10:49.212057 Set Vref, RX VrefLevel [Byte0]: 33
2703 22:10:49.215533 [Byte1]: 33
2704 22:10:49.219571
2705 22:10:49.219670 Set Vref, RX VrefLevel [Byte0]: 34
2706 22:10:49.223200 [Byte1]: 34
2707 22:10:49.227091
2708 22:10:49.227207 Set Vref, RX VrefLevel [Byte0]: 35
2709 22:10:49.230427 [Byte1]: 35
2710 22:10:49.235188
2711 22:10:49.235292 Set Vref, RX VrefLevel [Byte0]: 36
2712 22:10:49.238191 [Byte1]: 36
2713 22:10:49.243338
2714 22:10:49.243418 Set Vref, RX VrefLevel [Byte0]: 37
2715 22:10:49.246501 [Byte1]: 37
2716 22:10:49.251292
2717 22:10:49.251391 Set Vref, RX VrefLevel [Byte0]: 38
2718 22:10:49.254440 [Byte1]: 38
2719 22:10:49.258922
2720 22:10:49.258996 Set Vref, RX VrefLevel [Byte0]: 39
2721 22:10:49.262345 [Byte1]: 39
2722 22:10:49.267042
2723 22:10:49.267122 Set Vref, RX VrefLevel [Byte0]: 40
2724 22:10:49.270454 [Byte1]: 40
2725 22:10:49.274934
2726 22:10:49.275005 Set Vref, RX VrefLevel [Byte0]: 41
2727 22:10:49.277786 [Byte1]: 41
2728 22:10:49.282797
2729 22:10:49.282912 Set Vref, RX VrefLevel [Byte0]: 42
2730 22:10:49.285837 [Byte1]: 42
2731 22:10:49.290374
2732 22:10:49.290477 Set Vref, RX VrefLevel [Byte0]: 43
2733 22:10:49.294050 [Byte1]: 43
2734 22:10:49.299008
2735 22:10:49.299105 Set Vref, RX VrefLevel [Byte0]: 44
2736 22:10:49.301675 [Byte1]: 44
2737 22:10:49.306318
2738 22:10:49.306426 Set Vref, RX VrefLevel [Byte0]: 45
2739 22:10:49.309541 [Byte1]: 45
2740 22:10:49.314491
2741 22:10:49.314629 Set Vref, RX VrefLevel [Byte0]: 46
2742 22:10:49.317373 [Byte1]: 46
2743 22:10:49.322306
2744 22:10:49.322405 Set Vref, RX VrefLevel [Byte0]: 47
2745 22:10:49.325445 [Byte1]: 47
2746 22:10:49.330217
2747 22:10:49.330298 Set Vref, RX VrefLevel [Byte0]: 48
2748 22:10:49.333275 [Byte1]: 48
2749 22:10:49.338348
2750 22:10:49.338430 Set Vref, RX VrefLevel [Byte0]: 49
2751 22:10:49.341161 [Byte1]: 49
2752 22:10:49.346448
2753 22:10:49.346550 Set Vref, RX VrefLevel [Byte0]: 50
2754 22:10:49.349305 [Byte1]: 50
2755 22:10:49.354086
2756 22:10:49.354234 Set Vref, RX VrefLevel [Byte0]: 51
2757 22:10:49.357208 [Byte1]: 51
2758 22:10:49.362348
2759 22:10:49.362453 Set Vref, RX VrefLevel [Byte0]: 52
2760 22:10:49.365002 [Byte1]: 52
2761 22:10:49.370059
2762 22:10:49.370179 Set Vref, RX VrefLevel [Byte0]: 53
2763 22:10:49.372918 [Byte1]: 53
2764 22:10:49.377789
2765 22:10:49.377883 Set Vref, RX VrefLevel [Byte0]: 54
2766 22:10:49.381255 [Byte1]: 54
2767 22:10:49.385528
2768 22:10:49.385617 Set Vref, RX VrefLevel [Byte0]: 55
2769 22:10:49.388775 [Byte1]: 55
2770 22:10:49.393705
2771 22:10:49.393775 Set Vref, RX VrefLevel [Byte0]: 56
2772 22:10:49.396822 [Byte1]: 56
2773 22:10:49.401490
2774 22:10:49.401559 Set Vref, RX VrefLevel [Byte0]: 57
2775 22:10:49.405240 [Byte1]: 57
2776 22:10:49.409395
2777 22:10:49.409465 Set Vref, RX VrefLevel [Byte0]: 58
2778 22:10:49.412914 [Byte1]: 58
2779 22:10:49.417461
2780 22:10:49.417541 Set Vref, RX VrefLevel [Byte0]: 59
2781 22:10:49.420722 [Byte1]: 59
2782 22:10:49.425306
2783 22:10:49.425377 Set Vref, RX VrefLevel [Byte0]: 60
2784 22:10:49.428683 [Byte1]: 60
2785 22:10:49.433093
2786 22:10:49.433166 Set Vref, RX VrefLevel [Byte0]: 61
2787 22:10:49.436737 [Byte1]: 61
2788 22:10:49.441209
2789 22:10:49.441286 Set Vref, RX VrefLevel [Byte0]: 62
2790 22:10:49.444261 [Byte1]: 62
2791 22:10:49.448948
2792 22:10:49.449030 Set Vref, RX VrefLevel [Byte0]: 63
2793 22:10:49.452507 [Byte1]: 63
2794 22:10:49.457052
2795 22:10:49.457126 Set Vref, RX VrefLevel [Byte0]: 64
2796 22:10:49.460152 [Byte1]: 64
2797 22:10:49.465166
2798 22:10:49.465248 Set Vref, RX VrefLevel [Byte0]: 65
2799 22:10:49.468132 [Byte1]: 65
2800 22:10:49.473007
2801 22:10:49.473084 Set Vref, RX VrefLevel [Byte0]: 66
2802 22:10:49.476539 [Byte1]: 66
2803 22:10:49.480913
2804 22:10:49.480988 Set Vref, RX VrefLevel [Byte0]: 67
2805 22:10:49.484406 [Byte1]: 67
2806 22:10:49.488588
2807 22:10:49.488663 Set Vref, RX VrefLevel [Byte0]: 68
2808 22:10:49.491913 [Byte1]: 68
2809 22:10:49.496434
2810 22:10:49.496502 Set Vref, RX VrefLevel [Byte0]: 69
2811 22:10:49.499816 [Byte1]: 69
2812 22:10:49.504784
2813 22:10:49.504854 Set Vref, RX VrefLevel [Byte0]: 70
2814 22:10:49.507702 [Byte1]: 70
2815 22:10:49.512526
2816 22:10:49.512599 Set Vref, RX VrefLevel [Byte0]: 71
2817 22:10:49.516112 [Byte1]: 71
2818 22:10:49.520693
2819 22:10:49.520773 Set Vref, RX VrefLevel [Byte0]: 72
2820 22:10:49.523771 [Byte1]: 72
2821 22:10:49.528449
2822 22:10:49.528521 Set Vref, RX VrefLevel [Byte0]: 73
2823 22:10:49.531768 [Byte1]: 73
2824 22:10:49.536385
2825 22:10:49.536457 Set Vref, RX VrefLevel [Byte0]: 74
2826 22:10:49.539798 [Byte1]: 74
2827 22:10:49.543980
2828 22:10:49.544089 Set Vref, RX VrefLevel [Byte0]: 75
2829 22:10:49.547397 [Byte1]: 75
2830 22:10:49.551959
2831 22:10:49.552036 Set Vref, RX VrefLevel [Byte0]: 76
2832 22:10:49.555255 [Byte1]: 76
2833 22:10:49.559954
2834 22:10:49.560049 Set Vref, RX VrefLevel [Byte0]: 77
2835 22:10:49.566488 [Byte1]: 77
2836 22:10:49.566568
2837 22:10:49.569660 Set Vref, RX VrefLevel [Byte0]: 78
2838 22:10:49.573237 [Byte1]: 78
2839 22:10:49.573317
2840 22:10:49.576598 Final RX Vref Byte 0 = 58 to rank0
2841 22:10:49.579769 Final RX Vref Byte 1 = 57 to rank0
2842 22:10:49.582776 Final RX Vref Byte 0 = 58 to rank1
2843 22:10:49.586144 Final RX Vref Byte 1 = 57 to rank1==
2844 22:10:49.589455 Dram Type= 6, Freq= 0, CH_0, rank 0
2845 22:10:49.592756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 22:10:49.596244 ==
2847 22:10:49.596324 DQS Delay:
2848 22:10:49.596387 DQS0 = 0, DQS1 = 0
2849 22:10:49.599514 DQM Delay:
2850 22:10:49.599594 DQM0 = 118, DQM1 = 107
2851 22:10:49.603272 DQ Delay:
2852 22:10:49.606109 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2853 22:10:49.609594 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =124
2854 22:10:49.612937 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2855 22:10:49.616366 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =114
2856 22:10:49.616462
2857 22:10:49.616534
2858 22:10:49.622770 [DQSOSCAuto] RK0, (LSB)MR18= 0xefa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2859 22:10:49.626041 CH0 RK0: MR19=403, MR18=EFA
2860 22:10:49.633108 CH0_RK0: MR19=0x403, MR18=0xEFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2861 22:10:49.633185
2862 22:10:49.635948 ----->DramcWriteLeveling(PI) begin...
2863 22:10:49.636019 ==
2864 22:10:49.639355 Dram Type= 6, Freq= 0, CH_0, rank 1
2865 22:10:49.642624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2866 22:10:49.642708 ==
2867 22:10:49.645892 Write leveling (Byte 0): 30 => 30
2868 22:10:49.649388 Write leveling (Byte 1): 29 => 29
2869 22:10:49.652460 DramcWriteLeveling(PI) end<-----
2870 22:10:49.652542
2871 22:10:49.652606 ==
2872 22:10:49.655777 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 22:10:49.659156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 22:10:49.662832 ==
2875 22:10:49.662902 [Gating] SW mode calibration
2876 22:10:49.672503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2877 22:10:49.675856 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2878 22:10:49.679200 0 15 0 | B1->B0 | 2424 3333 | 1 1 | (1 1) (1 1)
2879 22:10:49.685667 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2880 22:10:49.689111 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 22:10:49.692838 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 22:10:49.698902 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 22:10:49.702282 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 22:10:49.705825 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 22:10:49.712010 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
2886 22:10:49.715392 1 0 0 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
2887 22:10:49.718955 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 22:10:49.725145 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 22:10:49.728758 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 22:10:49.731801 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 22:10:49.738695 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 22:10:49.741701 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 22:10:49.745372 1 0 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2894 22:10:49.751976 1 1 0 | B1->B0 | 3f3e 4646 | 1 0 | (0 0) (0 0)
2895 22:10:49.755490 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 22:10:49.758374 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 22:10:49.765232 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 22:10:49.768792 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 22:10:49.771831 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 22:10:49.778163 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 22:10:49.781555 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2902 22:10:49.785093 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2903 22:10:49.791944 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 22:10:49.795121 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 22:10:49.798043 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 22:10:49.804917 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 22:10:49.808218 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 22:10:49.811415 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 22:10:49.818488 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 22:10:49.821348 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 22:10:49.824510 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 22:10:49.831434 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 22:10:49.834709 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 22:10:49.837537 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 22:10:49.844346 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 22:10:49.847840 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2917 22:10:49.851389 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2918 22:10:49.857723 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2919 22:10:49.857838 Total UI for P1: 0, mck2ui 16
2920 22:10:49.861019 best dqsien dly found for B0: ( 1, 3, 26)
2921 22:10:49.867461 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 22:10:49.871425 Total UI for P1: 0, mck2ui 16
2923 22:10:49.874779 best dqsien dly found for B1: ( 1, 3, 30)
2924 22:10:49.877574 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2925 22:10:49.880715 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2926 22:10:49.880848
2927 22:10:49.884019 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2928 22:10:49.887975 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2929 22:10:49.890678 [Gating] SW calibration Done
2930 22:10:49.890857 ==
2931 22:10:49.894140 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 22:10:49.897370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 22:10:49.897516 ==
2934 22:10:49.900705 RX Vref Scan: 0
2935 22:10:49.900841
2936 22:10:49.904438 RX Vref 0 -> 0, step: 1
2937 22:10:49.904548
2938 22:10:49.904642 RX Delay -40 -> 252, step: 8
2939 22:10:49.910536 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2940 22:10:49.913854 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2941 22:10:49.917519 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2942 22:10:49.920715 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2943 22:10:49.924076 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2944 22:10:49.930762 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2945 22:10:49.933967 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2946 22:10:49.937492 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2947 22:10:49.940369 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2948 22:10:49.943974 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2949 22:10:49.950583 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2950 22:10:49.953983 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2951 22:10:49.957082 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2952 22:10:49.960466 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2953 22:10:49.967158 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2954 22:10:49.970524 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2955 22:10:49.970666 ==
2956 22:10:49.973706 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 22:10:49.977020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 22:10:49.977103 ==
2959 22:10:49.977166 DQS Delay:
2960 22:10:49.980237 DQS0 = 0, DQS1 = 0
2961 22:10:49.980320 DQM Delay:
2962 22:10:49.983968 DQM0 = 117, DQM1 = 109
2963 22:10:49.984046 DQ Delay:
2964 22:10:49.987020 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2965 22:10:49.990300 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2966 22:10:49.993708 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2967 22:10:49.997154 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
2968 22:10:50.000662
2969 22:10:50.000758
2970 22:10:50.000864 ==
2971 22:10:50.003271 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 22:10:50.006801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 22:10:50.006891 ==
2974 22:10:50.006955
2975 22:10:50.007015
2976 22:10:50.010610 TX Vref Scan disable
2977 22:10:50.010692 == TX Byte 0 ==
2978 22:10:50.017217 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2979 22:10:50.020227 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2980 22:10:50.020310 == TX Byte 1 ==
2981 22:10:50.026523 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2982 22:10:50.030105 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2983 22:10:50.030212 ==
2984 22:10:50.033484 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 22:10:50.036927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 22:10:50.037001 ==
2987 22:10:50.049048 TX Vref=22, minBit 3, minWin=25, winSum=409
2988 22:10:50.052322 TX Vref=24, minBit 3, minWin=25, winSum=413
2989 22:10:50.055399 TX Vref=26, minBit 4, minWin=25, winSum=418
2990 22:10:50.059199 TX Vref=28, minBit 13, minWin=25, winSum=423
2991 22:10:50.062130 TX Vref=30, minBit 13, minWin=25, winSum=426
2992 22:10:50.068800 TX Vref=32, minBit 12, minWin=25, winSum=423
2993 22:10:50.072470 [TxChooseVref] Worse bit 13, Min win 25, Win sum 426, Final Vref 30
2994 22:10:50.072579
2995 22:10:50.075695 Final TX Range 1 Vref 30
2996 22:10:50.075778
2997 22:10:50.075843 ==
2998 22:10:50.078944 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 22:10:50.082344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 22:10:50.085796 ==
3001 22:10:50.085877
3002 22:10:50.085940
3003 22:10:50.086000 TX Vref Scan disable
3004 22:10:50.089325 == TX Byte 0 ==
3005 22:10:50.092971 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3006 22:10:50.099484 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3007 22:10:50.099565 == TX Byte 1 ==
3008 22:10:50.102209 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3009 22:10:50.109181 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3010 22:10:50.109262
3011 22:10:50.109325 [DATLAT]
3012 22:10:50.109384 Freq=1200, CH0 RK1
3013 22:10:50.109440
3014 22:10:50.112623 DATLAT Default: 0xd
3015 22:10:50.112703 0, 0xFFFF, sum = 0
3016 22:10:50.115942 1, 0xFFFF, sum = 0
3017 22:10:50.116024 2, 0xFFFF, sum = 0
3018 22:10:50.119344 3, 0xFFFF, sum = 0
3019 22:10:50.122689 4, 0xFFFF, sum = 0
3020 22:10:50.122763 5, 0xFFFF, sum = 0
3021 22:10:50.125865 6, 0xFFFF, sum = 0
3022 22:10:50.125975 7, 0xFFFF, sum = 0
3023 22:10:50.128991 8, 0xFFFF, sum = 0
3024 22:10:50.129070 9, 0xFFFF, sum = 0
3025 22:10:50.132453 10, 0xFFFF, sum = 0
3026 22:10:50.132538 11, 0xFFFF, sum = 0
3027 22:10:50.135666 12, 0x0, sum = 1
3028 22:10:50.135741 13, 0x0, sum = 2
3029 22:10:50.139117 14, 0x0, sum = 3
3030 22:10:50.139186 15, 0x0, sum = 4
3031 22:10:50.141986 best_step = 13
3032 22:10:50.142052
3033 22:10:50.142108 ==
3034 22:10:50.145304 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 22:10:50.148911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 22:10:50.149017 ==
3037 22:10:50.149109 RX Vref Scan: 0
3038 22:10:50.149196
3039 22:10:50.152043 RX Vref 0 -> 0, step: 1
3040 22:10:50.152155
3041 22:10:50.155388 RX Delay -21 -> 252, step: 4
3042 22:10:50.158756 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3043 22:10:50.165568 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3044 22:10:50.168910 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3045 22:10:50.172005 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3046 22:10:50.175040 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3047 22:10:50.182036 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3048 22:10:50.185378 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3049 22:10:50.188776 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3050 22:10:50.192205 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3051 22:10:50.195489 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3052 22:10:50.198513 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3053 22:10:50.205014 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3054 22:10:50.208562 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3055 22:10:50.211869 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3056 22:10:50.214836 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3057 22:10:50.221456 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3058 22:10:50.221536 ==
3059 22:10:50.224863 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 22:10:50.228438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 22:10:50.228525 ==
3062 22:10:50.228589 DQS Delay:
3063 22:10:50.231589 DQS0 = 0, DQS1 = 0
3064 22:10:50.231668 DQM Delay:
3065 22:10:50.234983 DQM0 = 116, DQM1 = 108
3066 22:10:50.235065 DQ Delay:
3067 22:10:50.237906 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3068 22:10:50.241271 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3069 22:10:50.244772 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3070 22:10:50.247877 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =116
3071 22:10:50.247963
3072 22:10:50.248027
3073 22:10:50.258069 [DQSOSCAuto] RK1, (LSB)MR18= 0xde7, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3074 22:10:50.261282 CH0 RK1: MR19=403, MR18=DE7
3075 22:10:50.264989 CH0_RK1: MR19=0x403, MR18=0xDE7, DQSOSC=405, MR23=63, INC=39, DEC=26
3076 22:10:50.267733 [RxdqsGatingPostProcess] freq 1200
3077 22:10:50.274242 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3078 22:10:50.277735 best DQS0 dly(2T, 0.5T) = (0, 11)
3079 22:10:50.281438 best DQS1 dly(2T, 0.5T) = (0, 11)
3080 22:10:50.284430 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3081 22:10:50.287722 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3082 22:10:50.290977 best DQS0 dly(2T, 0.5T) = (0, 11)
3083 22:10:50.294158 best DQS1 dly(2T, 0.5T) = (0, 11)
3084 22:10:50.297842 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3085 22:10:50.301127 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3086 22:10:50.304562 Pre-setting of DQS Precalculation
3087 22:10:50.307766 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3088 22:10:50.307879 ==
3089 22:10:50.310823 Dram Type= 6, Freq= 0, CH_1, rank 0
3090 22:10:50.314112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 22:10:50.314216 ==
3092 22:10:50.320844 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3093 22:10:50.327335 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3094 22:10:50.335596 [CA 0] Center 37 (7~68) winsize 62
3095 22:10:50.338940 [CA 1] Center 37 (7~68) winsize 62
3096 22:10:50.341810 [CA 2] Center 34 (4~64) winsize 61
3097 22:10:50.345231 [CA 3] Center 33 (3~64) winsize 62
3098 22:10:50.348522 [CA 4] Center 34 (4~64) winsize 61
3099 22:10:50.351774 [CA 5] Center 33 (3~64) winsize 62
3100 22:10:50.351856
3101 22:10:50.355082 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3102 22:10:50.355181
3103 22:10:50.358369 [CATrainingPosCal] consider 1 rank data
3104 22:10:50.361856 u2DelayCellTimex100 = 270/100 ps
3105 22:10:50.365149 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3106 22:10:50.372149 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3107 22:10:50.374986 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 22:10:50.378418 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3109 22:10:50.381824 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3110 22:10:50.384942 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3111 22:10:50.385023
3112 22:10:50.388234 CA PerBit enable=1, Macro0, CA PI delay=33
3113 22:10:50.388326
3114 22:10:50.391613 [CBTSetCACLKResult] CA Dly = 33
3115 22:10:50.391689 CS Dly: 5 (0~36)
3116 22:10:50.395015 ==
3117 22:10:50.398118 Dram Type= 6, Freq= 0, CH_1, rank 1
3118 22:10:50.401517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 22:10:50.401617 ==
3120 22:10:50.404861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3121 22:10:50.411288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3122 22:10:50.420907 [CA 0] Center 37 (7~68) winsize 62
3123 22:10:50.424083 [CA 1] Center 38 (8~68) winsize 61
3124 22:10:50.427640 [CA 2] Center 34 (4~65) winsize 62
3125 22:10:50.430870 [CA 3] Center 33 (3~64) winsize 62
3126 22:10:50.434197 [CA 4] Center 34 (3~65) winsize 63
3127 22:10:50.437492 [CA 5] Center 33 (3~64) winsize 62
3128 22:10:50.437606
3129 22:10:50.440901 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3130 22:10:50.441024
3131 22:10:50.444336 [CATrainingPosCal] consider 2 rank data
3132 22:10:50.447021 u2DelayCellTimex100 = 270/100 ps
3133 22:10:50.450365 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3134 22:10:50.457262 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3135 22:10:50.460257 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3136 22:10:50.463701 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3137 22:10:50.467100 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3138 22:10:50.470427 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3139 22:10:50.470533
3140 22:10:50.473492 CA PerBit enable=1, Macro0, CA PI delay=33
3141 22:10:50.473572
3142 22:10:50.476770 [CBTSetCACLKResult] CA Dly = 33
3143 22:10:50.480364 CS Dly: 7 (0~40)
3144 22:10:50.480442
3145 22:10:50.483703 ----->DramcWriteLeveling(PI) begin...
3146 22:10:50.483777 ==
3147 22:10:50.487066 Dram Type= 6, Freq= 0, CH_1, rank 0
3148 22:10:50.490267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3149 22:10:50.490347 ==
3150 22:10:50.493899 Write leveling (Byte 0): 25 => 25
3151 22:10:50.496986 Write leveling (Byte 1): 26 => 26
3152 22:10:50.500083 DramcWriteLeveling(PI) end<-----
3153 22:10:50.500166
3154 22:10:50.500229 ==
3155 22:10:50.503842 Dram Type= 6, Freq= 0, CH_1, rank 0
3156 22:10:50.507060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 22:10:50.507132 ==
3158 22:10:50.509972 [Gating] SW mode calibration
3159 22:10:50.516713 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3160 22:10:50.523112 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3161 22:10:50.526512 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3162 22:10:50.529589 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 22:10:50.536481 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 22:10:50.539601 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 22:10:50.543278 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 22:10:50.549784 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 22:10:50.552610 0 15 24 | B1->B0 | 3333 2c2c | 1 1 | (1 0) (1 0)
3168 22:10:50.556132 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 1) (1 0)
3169 22:10:50.562913 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 22:10:50.565889 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 22:10:50.569066 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 22:10:50.575676 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 22:10:50.578930 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 22:10:50.582759 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 22:10:50.588944 1 0 24 | B1->B0 | 2525 3535 | 1 0 | (0 0) (0 0)
3176 22:10:50.592579 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 22:10:50.596156 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 22:10:50.602273 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 22:10:50.606205 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 22:10:50.608990 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 22:10:50.615582 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 22:10:50.619226 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 22:10:50.622206 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3184 22:10:50.629562 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3185 22:10:50.632699 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 22:10:50.635778 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 22:10:50.642271 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 22:10:50.645671 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 22:10:50.649113 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 22:10:50.656022 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 22:10:50.659364 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 22:10:50.662246 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 22:10:50.669050 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 22:10:50.672344 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 22:10:50.675656 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 22:10:50.682439 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 22:10:50.685413 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 22:10:50.688739 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 22:10:50.695373 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3200 22:10:50.699173 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3201 22:10:50.702151 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 22:10:50.705480 Total UI for P1: 0, mck2ui 16
3203 22:10:50.708755 best dqsien dly found for B0: ( 1, 3, 26)
3204 22:10:50.712062 Total UI for P1: 0, mck2ui 16
3205 22:10:50.715730 best dqsien dly found for B1: ( 1, 3, 26)
3206 22:10:50.718888 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3207 22:10:50.722035 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3208 22:10:50.722115
3209 22:10:50.725859 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3210 22:10:50.728791 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3211 22:10:50.731945 [Gating] SW calibration Done
3212 22:10:50.732026 ==
3213 22:10:50.735080 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 22:10:50.741806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 22:10:50.741887 ==
3216 22:10:50.741951 RX Vref Scan: 0
3217 22:10:50.742011
3218 22:10:50.745089 RX Vref 0 -> 0, step: 1
3219 22:10:50.745170
3220 22:10:50.748349 RX Delay -40 -> 252, step: 8
3221 22:10:50.751922 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3222 22:10:50.755008 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3223 22:10:50.758554 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3224 22:10:50.765516 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3225 22:10:50.768376 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3226 22:10:50.771813 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3227 22:10:50.775243 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3228 22:10:50.778367 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3229 22:10:50.781911 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3230 22:10:50.788332 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3231 22:10:50.791845 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3232 22:10:50.795130 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3233 22:10:50.798488 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3234 22:10:50.801822 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3235 22:10:50.808686 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3236 22:10:50.811655 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3237 22:10:50.811736 ==
3238 22:10:50.815178 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 22:10:50.818191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 22:10:50.818271 ==
3241 22:10:50.821522 DQS Delay:
3242 22:10:50.821604 DQS0 = 0, DQS1 = 0
3243 22:10:50.821668 DQM Delay:
3244 22:10:50.824809 DQM0 = 117, DQM1 = 108
3245 22:10:50.824890 DQ Delay:
3246 22:10:50.828321 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3247 22:10:50.831713 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3248 22:10:50.834812 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3249 22:10:50.841618 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3250 22:10:50.841700
3251 22:10:50.841764
3252 22:10:50.841856 ==
3253 22:10:50.844893 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 22:10:50.847942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 22:10:50.848024 ==
3256 22:10:50.848088
3257 22:10:50.848147
3258 22:10:50.851862 TX Vref Scan disable
3259 22:10:50.851943 == TX Byte 0 ==
3260 22:10:50.858176 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3261 22:10:50.861818 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3262 22:10:50.861900 == TX Byte 1 ==
3263 22:10:50.868058 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3264 22:10:50.871150 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3265 22:10:50.871232 ==
3266 22:10:50.874511 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 22:10:50.877935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 22:10:50.878022 ==
3269 22:10:50.890619 TX Vref=22, minBit 10, minWin=25, winSum=418
3270 22:10:50.894127 TX Vref=24, minBit 10, minWin=25, winSum=423
3271 22:10:50.897354 TX Vref=26, minBit 9, minWin=25, winSum=426
3272 22:10:50.900758 TX Vref=28, minBit 11, minWin=25, winSum=429
3273 22:10:50.904384 TX Vref=30, minBit 9, minWin=25, winSum=432
3274 22:10:50.910469 TX Vref=32, minBit 9, minWin=25, winSum=427
3275 22:10:50.913810 [TxChooseVref] Worse bit 9, Min win 25, Win sum 432, Final Vref 30
3276 22:10:50.913917
3277 22:10:50.917202 Final TX Range 1 Vref 30
3278 22:10:50.917310
3279 22:10:50.917402 ==
3280 22:10:50.920707 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 22:10:50.924011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 22:10:50.927317 ==
3283 22:10:50.927415
3284 22:10:50.927514
3285 22:10:50.927589 TX Vref Scan disable
3286 22:10:50.930489 == TX Byte 0 ==
3287 22:10:50.934266 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3288 22:10:50.937167 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3289 22:10:50.941005 == TX Byte 1 ==
3290 22:10:50.944237 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3291 22:10:50.947398 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3292 22:10:50.950941
3293 22:10:50.951080 [DATLAT]
3294 22:10:50.951174 Freq=1200, CH1 RK0
3295 22:10:50.951266
3296 22:10:50.954046 DATLAT Default: 0xd
3297 22:10:50.954120 0, 0xFFFF, sum = 0
3298 22:10:50.957719 1, 0xFFFF, sum = 0
3299 22:10:50.957825 2, 0xFFFF, sum = 0
3300 22:10:50.960917 3, 0xFFFF, sum = 0
3301 22:10:50.961024 4, 0xFFFF, sum = 0
3302 22:10:50.964099 5, 0xFFFF, sum = 0
3303 22:10:50.967064 6, 0xFFFF, sum = 0
3304 22:10:50.967146 7, 0xFFFF, sum = 0
3305 22:10:50.970951 8, 0xFFFF, sum = 0
3306 22:10:50.971048 9, 0xFFFF, sum = 0
3307 22:10:50.973830 10, 0xFFFF, sum = 0
3308 22:10:50.973951 11, 0xFFFF, sum = 0
3309 22:10:50.977523 12, 0x0, sum = 1
3310 22:10:50.977623 13, 0x0, sum = 2
3311 22:10:50.980690 14, 0x0, sum = 3
3312 22:10:50.980768 15, 0x0, sum = 4
3313 22:10:50.980851 best_step = 13
3314 22:10:50.983891
3315 22:10:50.983989 ==
3316 22:10:50.987081 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 22:10:50.990704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 22:10:50.990777 ==
3319 22:10:50.990838 RX Vref Scan: 1
3320 22:10:50.990896
3321 22:10:50.993712 Set Vref Range= 32 -> 127
3322 22:10:50.993809
3323 22:10:50.997044 RX Vref 32 -> 127, step: 1
3324 22:10:50.997145
3325 22:10:51.000557 RX Delay -21 -> 252, step: 4
3326 22:10:51.000650
3327 22:10:51.004075 Set Vref, RX VrefLevel [Byte0]: 32
3328 22:10:51.007418 [Byte1]: 32
3329 22:10:51.007511
3330 22:10:51.010353 Set Vref, RX VrefLevel [Byte0]: 33
3331 22:10:51.013642 [Byte1]: 33
3332 22:10:51.017188
3333 22:10:51.017293 Set Vref, RX VrefLevel [Byte0]: 34
3334 22:10:51.020414 [Byte1]: 34
3335 22:10:51.024835
3336 22:10:51.024940 Set Vref, RX VrefLevel [Byte0]: 35
3337 22:10:51.028362 [Byte1]: 35
3338 22:10:51.032795
3339 22:10:51.032873 Set Vref, RX VrefLevel [Byte0]: 36
3340 22:10:51.036489 [Byte1]: 36
3341 22:10:51.041028
3342 22:10:51.041113 Set Vref, RX VrefLevel [Byte0]: 37
3343 22:10:51.044217 [Byte1]: 37
3344 22:10:51.049229
3345 22:10:51.049308 Set Vref, RX VrefLevel [Byte0]: 38
3346 22:10:51.052260 [Byte1]: 38
3347 22:10:51.056637
3348 22:10:51.056721 Set Vref, RX VrefLevel [Byte0]: 39
3349 22:10:51.060275 [Byte1]: 39
3350 22:10:51.064746
3351 22:10:51.064852 Set Vref, RX VrefLevel [Byte0]: 40
3352 22:10:51.067986 [Byte1]: 40
3353 22:10:51.072557
3354 22:10:51.072664 Set Vref, RX VrefLevel [Byte0]: 41
3355 22:10:51.075922 [Byte1]: 41
3356 22:10:51.080529
3357 22:10:51.080641 Set Vref, RX VrefLevel [Byte0]: 42
3358 22:10:51.083853 [Byte1]: 42
3359 22:10:51.088520
3360 22:10:51.088625 Set Vref, RX VrefLevel [Byte0]: 43
3361 22:10:51.091866 [Byte1]: 43
3362 22:10:51.096147
3363 22:10:51.096248 Set Vref, RX VrefLevel [Byte0]: 44
3364 22:10:51.099599 [Byte1]: 44
3365 22:10:51.104054
3366 22:10:51.104154 Set Vref, RX VrefLevel [Byte0]: 45
3367 22:10:51.107423 [Byte1]: 45
3368 22:10:51.111983
3369 22:10:51.112087 Set Vref, RX VrefLevel [Byte0]: 46
3370 22:10:51.115447 [Byte1]: 46
3371 22:10:51.120262
3372 22:10:51.120336 Set Vref, RX VrefLevel [Byte0]: 47
3373 22:10:51.123299 [Byte1]: 47
3374 22:10:51.128310
3375 22:10:51.128402 Set Vref, RX VrefLevel [Byte0]: 48
3376 22:10:51.131155 [Byte1]: 48
3377 22:10:51.136052
3378 22:10:51.136128 Set Vref, RX VrefLevel [Byte0]: 49
3379 22:10:51.139362 [Byte1]: 49
3380 22:10:51.143694
3381 22:10:51.143803 Set Vref, RX VrefLevel [Byte0]: 50
3382 22:10:51.147118 [Byte1]: 50
3383 22:10:51.151661
3384 22:10:51.151764 Set Vref, RX VrefLevel [Byte0]: 51
3385 22:10:51.155022 [Byte1]: 51
3386 22:10:51.159878
3387 22:10:51.159988 Set Vref, RX VrefLevel [Byte0]: 52
3388 22:10:51.163024 [Byte1]: 52
3389 22:10:51.167579
3390 22:10:51.167656 Set Vref, RX VrefLevel [Byte0]: 53
3391 22:10:51.170716 [Byte1]: 53
3392 22:10:51.175459
3393 22:10:51.175536 Set Vref, RX VrefLevel [Byte0]: 54
3394 22:10:51.178829 [Byte1]: 54
3395 22:10:51.183341
3396 22:10:51.186549 Set Vref, RX VrefLevel [Byte0]: 55
3397 22:10:51.186680 [Byte1]: 55
3398 22:10:51.191138
3399 22:10:51.191211 Set Vref, RX VrefLevel [Byte0]: 56
3400 22:10:51.194520 [Byte1]: 56
3401 22:10:51.199406
3402 22:10:51.199494 Set Vref, RX VrefLevel [Byte0]: 57
3403 22:10:51.202780 [Byte1]: 57
3404 22:10:51.207304
3405 22:10:51.207379 Set Vref, RX VrefLevel [Byte0]: 58
3406 22:10:51.210274 [Byte1]: 58
3407 22:10:51.215258
3408 22:10:51.215348 Set Vref, RX VrefLevel [Byte0]: 59
3409 22:10:51.218675 [Byte1]: 59
3410 22:10:51.223262
3411 22:10:51.223336 Set Vref, RX VrefLevel [Byte0]: 60
3412 22:10:51.226619 [Byte1]: 60
3413 22:10:51.231106
3414 22:10:51.231216 Set Vref, RX VrefLevel [Byte0]: 61
3415 22:10:51.234580 [Byte1]: 61
3416 22:10:51.239116
3417 22:10:51.239190 Set Vref, RX VrefLevel [Byte0]: 62
3418 22:10:51.242379 [Byte1]: 62
3419 22:10:51.246907
3420 22:10:51.247006 Set Vref, RX VrefLevel [Byte0]: 63
3421 22:10:51.249884 [Byte1]: 63
3422 22:10:51.254547
3423 22:10:51.254671 Set Vref, RX VrefLevel [Byte0]: 64
3424 22:10:51.258044 [Byte1]: 64
3425 22:10:51.262359
3426 22:10:51.262462 Set Vref, RX VrefLevel [Byte0]: 65
3427 22:10:51.265951 [Byte1]: 65
3428 22:10:51.270394
3429 22:10:51.270494 Set Vref, RX VrefLevel [Byte0]: 66
3430 22:10:51.273581 [Byte1]: 66
3431 22:10:51.278358
3432 22:10:51.278461 Set Vref, RX VrefLevel [Byte0]: 67
3433 22:10:51.281525 [Byte1]: 67
3434 22:10:51.286178
3435 22:10:51.286282 Final RX Vref Byte 0 = 50 to rank0
3436 22:10:51.289753 Final RX Vref Byte 1 = 52 to rank0
3437 22:10:51.292736 Final RX Vref Byte 0 = 50 to rank1
3438 22:10:51.296252 Final RX Vref Byte 1 = 52 to rank1==
3439 22:10:51.299606 Dram Type= 6, Freq= 0, CH_1, rank 0
3440 22:10:51.306144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 22:10:51.306248 ==
3442 22:10:51.306314 DQS Delay:
3443 22:10:51.306382 DQS0 = 0, DQS1 = 0
3444 22:10:51.309606 DQM Delay:
3445 22:10:51.309703 DQM0 = 115, DQM1 = 110
3446 22:10:51.312770 DQ Delay:
3447 22:10:51.316301 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3448 22:10:51.319378 DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =112
3449 22:10:51.323071 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =98
3450 22:10:51.325802 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3451 22:10:51.325905
3452 22:10:51.326001
3453 22:10:51.333110 [DQSOSCAuto] RK0, (LSB)MR18= 0x7fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3454 22:10:51.335892 CH1 RK0: MR19=403, MR18=7FA
3455 22:10:51.342706 CH1_RK0: MR19=0x403, MR18=0x7FA, DQSOSC=407, MR23=63, INC=39, DEC=26
3456 22:10:51.342787
3457 22:10:51.346221 ----->DramcWriteLeveling(PI) begin...
3458 22:10:51.346302 ==
3459 22:10:51.349369 Dram Type= 6, Freq= 0, CH_1, rank 1
3460 22:10:51.353125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3461 22:10:51.353200 ==
3462 22:10:51.356067 Write leveling (Byte 0): 24 => 24
3463 22:10:51.359470 Write leveling (Byte 1): 27 => 27
3464 22:10:51.362577 DramcWriteLeveling(PI) end<-----
3465 22:10:51.362696
3466 22:10:51.362774 ==
3467 22:10:51.366056 Dram Type= 6, Freq= 0, CH_1, rank 1
3468 22:10:51.372600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 22:10:51.372681 ==
3470 22:10:51.372794 [Gating] SW mode calibration
3471 22:10:51.382737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3472 22:10:51.386015 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3473 22:10:51.389466 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 22:10:51.395742 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 22:10:51.399241 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 22:10:51.402527 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 22:10:51.408969 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 22:10:51.412248 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3479 22:10:51.415555 0 15 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 0)
3480 22:10:51.422556 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (1 0) (1 0)
3481 22:10:51.425591 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 22:10:51.429189 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 22:10:51.435443 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 22:10:51.438985 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 22:10:51.442332 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 22:10:51.448829 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 22:10:51.452248 1 0 24 | B1->B0 | 4141 3131 | 0 0 | (0 0) (0 0)
3488 22:10:51.455577 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (1 1)
3489 22:10:51.461910 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 22:10:51.465299 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 22:10:51.468795 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 22:10:51.474960 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 22:10:51.478113 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 22:10:51.481413 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 22:10:51.488381 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3496 22:10:51.491560 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3497 22:10:51.495019 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 22:10:51.501437 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 22:10:51.504593 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 22:10:51.508350 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 22:10:51.515070 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 22:10:51.517908 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 22:10:51.521445 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 22:10:51.527771 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 22:10:51.531264 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 22:10:51.534250 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 22:10:51.541138 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 22:10:51.544372 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 22:10:51.547753 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 22:10:51.554063 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 22:10:51.557625 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3512 22:10:51.560754 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3513 22:10:51.567127 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 22:10:51.570571 Total UI for P1: 0, mck2ui 16
3515 22:10:51.574004 best dqsien dly found for B0: ( 1, 3, 26)
3516 22:10:51.577394 Total UI for P1: 0, mck2ui 16
3517 22:10:51.580932 best dqsien dly found for B1: ( 1, 3, 26)
3518 22:10:51.583674 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3519 22:10:51.587320 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3520 22:10:51.587404
3521 22:10:51.590734 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3522 22:10:51.593478 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3523 22:10:51.597044 [Gating] SW calibration Done
3524 22:10:51.597160 ==
3525 22:10:51.600130 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 22:10:51.603780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 22:10:51.603884 ==
3528 22:10:51.607116 RX Vref Scan: 0
3529 22:10:51.607192
3530 22:10:51.610194 RX Vref 0 -> 0, step: 1
3531 22:10:51.610293
3532 22:10:51.610383 RX Delay -40 -> 252, step: 8
3533 22:10:51.617022 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3534 22:10:51.620149 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3535 22:10:51.623195 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3536 22:10:51.626491 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3537 22:10:51.629797 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3538 22:10:51.636630 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3539 22:10:51.639781 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3540 22:10:51.643456 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3541 22:10:51.646706 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3542 22:10:51.650016 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3543 22:10:51.656003 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3544 22:10:51.659769 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3545 22:10:51.663077 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3546 22:10:51.666358 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3547 22:10:51.672551 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3548 22:10:51.675897 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3549 22:10:51.676028 ==
3550 22:10:51.679424 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 22:10:51.682261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 22:10:51.682359 ==
3553 22:10:51.685434 DQS Delay:
3554 22:10:51.685507 DQS0 = 0, DQS1 = 0
3555 22:10:51.685576 DQM Delay:
3556 22:10:51.688745 DQM0 = 116, DQM1 = 109
3557 22:10:51.688843 DQ Delay:
3558 22:10:51.692151 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3559 22:10:51.695624 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3560 22:10:51.702599 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3561 22:10:51.705711 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3562 22:10:51.705815
3563 22:10:51.705898
3564 22:10:51.705989 ==
3565 22:10:51.708746 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 22:10:51.711961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 22:10:51.712082 ==
3568 22:10:51.712179
3569 22:10:51.712256
3570 22:10:51.715617 TX Vref Scan disable
3571 22:10:51.718537 == TX Byte 0 ==
3572 22:10:51.722034 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3573 22:10:51.725262 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3574 22:10:51.728695 == TX Byte 1 ==
3575 22:10:51.731889 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3576 22:10:51.735171 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3577 22:10:51.735250 ==
3578 22:10:51.738503 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 22:10:51.742134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 22:10:51.744990 ==
3581 22:10:51.755153 TX Vref=22, minBit 9, minWin=25, winSum=427
3582 22:10:51.758380 TX Vref=24, minBit 8, minWin=26, winSum=430
3583 22:10:51.761916 TX Vref=26, minBit 9, minWin=26, winSum=437
3584 22:10:51.764831 TX Vref=28, minBit 9, minWin=26, winSum=437
3585 22:10:51.768218 TX Vref=30, minBit 9, minWin=26, winSum=438
3586 22:10:51.775014 TX Vref=32, minBit 3, minWin=26, winSum=433
3587 22:10:51.777950 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 30
3588 22:10:51.778039
3589 22:10:51.781230 Final TX Range 1 Vref 30
3590 22:10:51.781331
3591 22:10:51.781421 ==
3592 22:10:51.784637 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 22:10:51.787870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 22:10:51.791124 ==
3595 22:10:51.791199
3596 22:10:51.791269
3597 22:10:51.791349 TX Vref Scan disable
3598 22:10:51.794994 == TX Byte 0 ==
3599 22:10:51.798347 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3600 22:10:51.804620 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3601 22:10:51.804698 == TX Byte 1 ==
3602 22:10:51.808020 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3603 22:10:51.814953 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3604 22:10:51.815044
3605 22:10:51.815110 [DATLAT]
3606 22:10:51.815170 Freq=1200, CH1 RK1
3607 22:10:51.815246
3608 22:10:51.817743 DATLAT Default: 0xd
3609 22:10:51.821455 0, 0xFFFF, sum = 0
3610 22:10:51.821564 1, 0xFFFF, sum = 0
3611 22:10:51.824784 2, 0xFFFF, sum = 0
3612 22:10:51.824873 3, 0xFFFF, sum = 0
3613 22:10:51.827675 4, 0xFFFF, sum = 0
3614 22:10:51.827752 5, 0xFFFF, sum = 0
3615 22:10:51.831101 6, 0xFFFF, sum = 0
3616 22:10:51.831213 7, 0xFFFF, sum = 0
3617 22:10:51.834503 8, 0xFFFF, sum = 0
3618 22:10:51.834643 9, 0xFFFF, sum = 0
3619 22:10:51.837828 10, 0xFFFF, sum = 0
3620 22:10:51.837937 11, 0xFFFF, sum = 0
3621 22:10:51.841188 12, 0x0, sum = 1
3622 22:10:51.841264 13, 0x0, sum = 2
3623 22:10:51.844855 14, 0x0, sum = 3
3624 22:10:51.844958 15, 0x0, sum = 4
3625 22:10:51.847838 best_step = 13
3626 22:10:51.847930
3627 22:10:51.847993 ==
3628 22:10:51.851323 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 22:10:51.854136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 22:10:51.854239 ==
3631 22:10:51.854336 RX Vref Scan: 0
3632 22:10:51.857797
3633 22:10:51.857873 RX Vref 0 -> 0, step: 1
3634 22:10:51.857936
3635 22:10:51.860988 RX Delay -21 -> 252, step: 4
3636 22:10:51.867448 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3637 22:10:51.870984 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3638 22:10:51.874309 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3639 22:10:51.877490 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3640 22:10:51.880900 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3641 22:10:51.887479 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3642 22:10:51.890399 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3643 22:10:51.894196 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3644 22:10:51.897550 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3645 22:10:51.900281 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3646 22:10:51.907640 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3647 22:10:51.910463 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3648 22:10:51.913798 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3649 22:10:51.917076 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3650 22:10:51.920391 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3651 22:10:51.927093 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3652 22:10:51.927171 ==
3653 22:10:51.930437 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 22:10:51.933430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 22:10:51.933506 ==
3656 22:10:51.933576 DQS Delay:
3657 22:10:51.936614 DQS0 = 0, DQS1 = 0
3658 22:10:51.936713 DQM Delay:
3659 22:10:51.940355 DQM0 = 116, DQM1 = 109
3660 22:10:51.940458 DQ Delay:
3661 22:10:51.943500 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3662 22:10:51.946764 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =114
3663 22:10:51.949986 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3664 22:10:51.956578 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =118
3665 22:10:51.956686
3666 22:10:51.956811
3667 22:10:51.963538 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3668 22:10:51.966518 CH1 RK1: MR19=303, MR18=F3EE
3669 22:10:51.972869 CH1_RK1: MR19=0x303, MR18=0xF3EE, DQSOSC=415, MR23=63, INC=38, DEC=25
3670 22:10:51.976165 [RxdqsGatingPostProcess] freq 1200
3671 22:10:51.980063 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3672 22:10:51.983177 best DQS0 dly(2T, 0.5T) = (0, 11)
3673 22:10:51.986102 best DQS1 dly(2T, 0.5T) = (0, 11)
3674 22:10:51.989438 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3675 22:10:51.993010 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3676 22:10:51.996314 best DQS0 dly(2T, 0.5T) = (0, 11)
3677 22:10:51.999334 best DQS1 dly(2T, 0.5T) = (0, 11)
3678 22:10:52.003341 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3679 22:10:52.005839 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3680 22:10:52.009382 Pre-setting of DQS Precalculation
3681 22:10:52.012736 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3682 22:10:52.022519 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3683 22:10:52.029423 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3684 22:10:52.029533
3685 22:10:52.029662
3686 22:10:52.032803 [Calibration Summary] 2400 Mbps
3687 22:10:52.032938 CH 0, Rank 0
3688 22:10:52.036178 SW Impedance : PASS
3689 22:10:52.036284 DUTY Scan : NO K
3690 22:10:52.039292 ZQ Calibration : PASS
3691 22:10:52.042170 Jitter Meter : NO K
3692 22:10:52.042286 CBT Training : PASS
3693 22:10:52.045576 Write leveling : PASS
3694 22:10:52.048858 RX DQS gating : PASS
3695 22:10:52.048959 RX DQ/DQS(RDDQC) : PASS
3696 22:10:52.052261 TX DQ/DQS : PASS
3697 22:10:52.055748 RX DATLAT : PASS
3698 22:10:52.055861 RX DQ/DQS(Engine): PASS
3699 22:10:52.059202 TX OE : NO K
3700 22:10:52.059303 All Pass.
3701 22:10:52.059378
3702 22:10:52.062322 CH 0, Rank 1
3703 22:10:52.062420 SW Impedance : PASS
3704 22:10:52.065391 DUTY Scan : NO K
3705 22:10:52.068761 ZQ Calibration : PASS
3706 22:10:52.068860 Jitter Meter : NO K
3707 22:10:52.072140 CBT Training : PASS
3708 22:10:52.075341 Write leveling : PASS
3709 22:10:52.075444 RX DQS gating : PASS
3710 22:10:52.078834 RX DQ/DQS(RDDQC) : PASS
3711 22:10:52.081907 TX DQ/DQS : PASS
3712 22:10:52.082017 RX DATLAT : PASS
3713 22:10:52.085426 RX DQ/DQS(Engine): PASS
3714 22:10:52.088194 TX OE : NO K
3715 22:10:52.088299 All Pass.
3716 22:10:52.088397
3717 22:10:52.088493 CH 1, Rank 0
3718 22:10:52.091303 SW Impedance : PASS
3719 22:10:52.094730 DUTY Scan : NO K
3720 22:10:52.094804 ZQ Calibration : PASS
3721 22:10:52.097900 Jitter Meter : NO K
3722 22:10:52.101854 CBT Training : PASS
3723 22:10:52.101928 Write leveling : PASS
3724 22:10:52.105145 RX DQS gating : PASS
3725 22:10:52.107967 RX DQ/DQS(RDDQC) : PASS
3726 22:10:52.108069 TX DQ/DQS : PASS
3727 22:10:52.111278 RX DATLAT : PASS
3728 22:10:52.114349 RX DQ/DQS(Engine): PASS
3729 22:10:52.114449 TX OE : NO K
3730 22:10:52.114541 All Pass.
3731 22:10:52.117718
3732 22:10:52.117790 CH 1, Rank 1
3733 22:10:52.120957 SW Impedance : PASS
3734 22:10:52.121056 DUTY Scan : NO K
3735 22:10:52.124456 ZQ Calibration : PASS
3736 22:10:52.127737 Jitter Meter : NO K
3737 22:10:52.127839 CBT Training : PASS
3738 22:10:52.130895 Write leveling : PASS
3739 22:10:52.130968 RX DQS gating : PASS
3740 22:10:52.134715 RX DQ/DQS(RDDQC) : PASS
3741 22:10:52.138006 TX DQ/DQS : PASS
3742 22:10:52.138080 RX DATLAT : PASS
3743 22:10:52.141176 RX DQ/DQS(Engine): PASS
3744 22:10:52.144329 TX OE : NO K
3745 22:10:52.144431 All Pass.
3746 22:10:52.144521
3747 22:10:52.147764 DramC Write-DBI off
3748 22:10:52.147862 PER_BANK_REFRESH: Hybrid Mode
3749 22:10:52.150740 TX_TRACKING: ON
3750 22:10:52.160589 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3751 22:10:52.164125 [FAST_K] Save calibration result to emmc
3752 22:10:52.167390 dramc_set_vcore_voltage set vcore to 650000
3753 22:10:52.167493 Read voltage for 600, 5
3754 22:10:52.170741 Vio18 = 0
3755 22:10:52.170840 Vcore = 650000
3756 22:10:52.170930 Vdram = 0
3757 22:10:52.173865 Vddq = 0
3758 22:10:52.173941 Vmddr = 0
3759 22:10:52.180246 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3760 22:10:52.183725 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3761 22:10:52.187085 MEM_TYPE=3, freq_sel=19
3762 22:10:52.190184 sv_algorithm_assistance_LP4_1600
3763 22:10:52.193628 ============ PULL DRAM RESETB DOWN ============
3764 22:10:52.196766 ========== PULL DRAM RESETB DOWN end =========
3765 22:10:52.203334 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3766 22:10:52.207113 ===================================
3767 22:10:52.207193 LPDDR4 DRAM CONFIGURATION
3768 22:10:52.210061 ===================================
3769 22:10:52.213224 EX_ROW_EN[0] = 0x0
3770 22:10:52.216710 EX_ROW_EN[1] = 0x0
3771 22:10:52.216786 LP4Y_EN = 0x0
3772 22:10:52.220204 WORK_FSP = 0x0
3773 22:10:52.220279 WL = 0x2
3774 22:10:52.223537 RL = 0x2
3775 22:10:52.223609 BL = 0x2
3776 22:10:52.226434 RPST = 0x0
3777 22:10:52.226509 RD_PRE = 0x0
3778 22:10:52.229772 WR_PRE = 0x1
3779 22:10:52.229875 WR_PST = 0x0
3780 22:10:52.233624 DBI_WR = 0x0
3781 22:10:52.233699 DBI_RD = 0x0
3782 22:10:52.236893 OTF = 0x1
3783 22:10:52.239850 ===================================
3784 22:10:52.243296 ===================================
3785 22:10:52.243372 ANA top config
3786 22:10:52.246288 ===================================
3787 22:10:52.249594 DLL_ASYNC_EN = 0
3788 22:10:52.253330 ALL_SLAVE_EN = 1
3789 22:10:52.256388 NEW_RANK_MODE = 1
3790 22:10:52.256469 DLL_IDLE_MODE = 1
3791 22:10:52.259583 LP45_APHY_COMB_EN = 1
3792 22:10:52.263190 TX_ODT_DIS = 1
3793 22:10:52.266342 NEW_8X_MODE = 1
3794 22:10:52.269582 ===================================
3795 22:10:52.272879 ===================================
3796 22:10:52.276471 data_rate = 1200
3797 22:10:52.276575 CKR = 1
3798 22:10:52.279737 DQ_P2S_RATIO = 8
3799 22:10:52.282796 ===================================
3800 22:10:52.286275 CA_P2S_RATIO = 8
3801 22:10:52.289708 DQ_CA_OPEN = 0
3802 22:10:52.292454 DQ_SEMI_OPEN = 0
3803 22:10:52.295947 CA_SEMI_OPEN = 0
3804 22:10:52.296020 CA_FULL_RATE = 0
3805 22:10:52.299171 DQ_CKDIV4_EN = 1
3806 22:10:52.302686 CA_CKDIV4_EN = 1
3807 22:10:52.306066 CA_PREDIV_EN = 0
3808 22:10:52.309013 PH8_DLY = 0
3809 22:10:52.312574 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3810 22:10:52.312676 DQ_AAMCK_DIV = 4
3811 22:10:52.315678 CA_AAMCK_DIV = 4
3812 22:10:52.319068 CA_ADMCK_DIV = 4
3813 22:10:52.322462 DQ_TRACK_CA_EN = 0
3814 22:10:52.326075 CA_PICK = 600
3815 22:10:52.329068 CA_MCKIO = 600
3816 22:10:52.332400 MCKIO_SEMI = 0
3817 22:10:52.332479 PLL_FREQ = 2288
3818 22:10:52.335717 DQ_UI_PI_RATIO = 32
3819 22:10:52.338727 CA_UI_PI_RATIO = 0
3820 22:10:52.342254 ===================================
3821 22:10:52.345774 ===================================
3822 22:10:52.348649 memory_type:LPDDR4
3823 22:10:52.351935 GP_NUM : 10
3824 22:10:52.352016 SRAM_EN : 1
3825 22:10:52.355411 MD32_EN : 0
3826 22:10:52.358786 ===================================
3827 22:10:52.358892 [ANA_INIT] >>>>>>>>>>>>>>
3828 22:10:52.362146 <<<<<< [CONFIGURE PHASE]: ANA_TX
3829 22:10:52.365173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3830 22:10:52.368689 ===================================
3831 22:10:52.371863 data_rate = 1200,PCW = 0X5800
3832 22:10:52.375002 ===================================
3833 22:10:52.378387 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3834 22:10:52.384806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3835 22:10:52.391354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 22:10:52.394727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3837 22:10:52.398205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3838 22:10:52.401462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3839 22:10:52.404660 [ANA_INIT] flow start
3840 22:10:52.404761 [ANA_INIT] PLL >>>>>>>>
3841 22:10:52.407790 [ANA_INIT] PLL <<<<<<<<
3842 22:10:52.411342 [ANA_INIT] MIDPI >>>>>>>>
3843 22:10:52.414803 [ANA_INIT] MIDPI <<<<<<<<
3844 22:10:52.414882 [ANA_INIT] DLL >>>>>>>>
3845 22:10:52.418004 [ANA_INIT] flow end
3846 22:10:52.421310 ============ LP4 DIFF to SE enter ============
3847 22:10:52.424441 ============ LP4 DIFF to SE exit ============
3848 22:10:52.427474 [ANA_INIT] <<<<<<<<<<<<<
3849 22:10:52.430809 [Flow] Enable top DCM control >>>>>
3850 22:10:52.434042 [Flow] Enable top DCM control <<<<<
3851 22:10:52.437700 Enable DLL master slave shuffle
3852 22:10:52.444381 ==============================================================
3853 22:10:52.444485 Gating Mode config
3854 22:10:52.450776 ==============================================================
3855 22:10:52.450860 Config description:
3856 22:10:52.460540 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3857 22:10:52.467348 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3858 22:10:52.473760 SELPH_MODE 0: By rank 1: By Phase
3859 22:10:52.477388 ==============================================================
3860 22:10:52.480496 GAT_TRACK_EN = 1
3861 22:10:52.483981 RX_GATING_MODE = 2
3862 22:10:52.487186 RX_GATING_TRACK_MODE = 2
3863 22:10:52.490531 SELPH_MODE = 1
3864 22:10:52.493670 PICG_EARLY_EN = 1
3865 22:10:52.496986 VALID_LAT_VALUE = 1
3866 22:10:52.503528 ==============================================================
3867 22:10:52.506840 Enter into Gating configuration >>>>
3868 22:10:52.510161 Exit from Gating configuration <<<<
3869 22:10:52.513276 Enter into DVFS_PRE_config >>>>>
3870 22:10:52.523819 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3871 22:10:52.527101 Exit from DVFS_PRE_config <<<<<
3872 22:10:52.529794 Enter into PICG configuration >>>>
3873 22:10:52.533190 Exit from PICG configuration <<<<
3874 22:10:52.536787 [RX_INPUT] configuration >>>>>
3875 22:10:52.536887 [RX_INPUT] configuration <<<<<
3876 22:10:52.543160 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3877 22:10:52.549964 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3878 22:10:52.556405 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3879 22:10:52.560149 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3880 22:10:52.566528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3881 22:10:52.573220 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3882 22:10:52.576643 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3883 22:10:52.579837 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3884 22:10:52.586252 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3885 22:10:52.589875 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3886 22:10:52.593061 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3887 22:10:52.599952 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3888 22:10:52.602615 ===================================
3889 22:10:52.602704 LPDDR4 DRAM CONFIGURATION
3890 22:10:52.605909 ===================================
3891 22:10:52.609297 EX_ROW_EN[0] = 0x0
3892 22:10:52.612673 EX_ROW_EN[1] = 0x0
3893 22:10:52.612771 LP4Y_EN = 0x0
3894 22:10:52.615700 WORK_FSP = 0x0
3895 22:10:52.615773 WL = 0x2
3896 22:10:52.619228 RL = 0x2
3897 22:10:52.619304 BL = 0x2
3898 22:10:52.622717 RPST = 0x0
3899 22:10:52.622790 RD_PRE = 0x0
3900 22:10:52.625853 WR_PRE = 0x1
3901 22:10:52.625950 WR_PST = 0x0
3902 22:10:52.629338 DBI_WR = 0x0
3903 22:10:52.629410 DBI_RD = 0x0
3904 22:10:52.632631 OTF = 0x1
3905 22:10:52.635951 ===================================
3906 22:10:52.639391 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3907 22:10:52.642342 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3908 22:10:52.648944 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3909 22:10:52.652517 ===================================
3910 22:10:52.652620 LPDDR4 DRAM CONFIGURATION
3911 22:10:52.655363 ===================================
3912 22:10:52.658768 EX_ROW_EN[0] = 0x10
3913 22:10:52.662007 EX_ROW_EN[1] = 0x0
3914 22:10:52.662083 LP4Y_EN = 0x0
3915 22:10:52.665327 WORK_FSP = 0x0
3916 22:10:52.665426 WL = 0x2
3917 22:10:52.669093 RL = 0x2
3918 22:10:52.669195 BL = 0x2
3919 22:10:52.672425 RPST = 0x0
3920 22:10:52.672522 RD_PRE = 0x0
3921 22:10:52.675109 WR_PRE = 0x1
3922 22:10:52.675183 WR_PST = 0x0
3923 22:10:52.678559 DBI_WR = 0x0
3924 22:10:52.678651 DBI_RD = 0x0
3925 22:10:52.681896 OTF = 0x1
3926 22:10:52.684969 ===================================
3927 22:10:52.691949 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3928 22:10:52.694783 nWR fixed to 30
3929 22:10:52.698295 [ModeRegInit_LP4] CH0 RK0
3930 22:10:52.698397 [ModeRegInit_LP4] CH0 RK1
3931 22:10:52.701462 [ModeRegInit_LP4] CH1 RK0
3932 22:10:52.705353 [ModeRegInit_LP4] CH1 RK1
3933 22:10:52.705495 match AC timing 17
3934 22:10:52.711497 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3935 22:10:52.715023 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3936 22:10:52.718064 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3937 22:10:52.724869 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3938 22:10:52.728143 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3939 22:10:52.728271 ==
3940 22:10:52.731413 Dram Type= 6, Freq= 0, CH_0, rank 0
3941 22:10:52.734538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3942 22:10:52.734689 ==
3943 22:10:52.741467 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3944 22:10:52.747729 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3945 22:10:52.751157 [CA 0] Center 36 (6~67) winsize 62
3946 22:10:52.754452 [CA 1] Center 36 (6~66) winsize 61
3947 22:10:52.757681 [CA 2] Center 34 (4~65) winsize 62
3948 22:10:52.760967 [CA 3] Center 34 (4~65) winsize 62
3949 22:10:52.764366 [CA 4] Center 33 (3~64) winsize 62
3950 22:10:52.767904 [CA 5] Center 33 (3~64) winsize 62
3951 22:10:52.767981
3952 22:10:52.771317 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3953 22:10:52.771418
3954 22:10:52.774335 [CATrainingPosCal] consider 1 rank data
3955 22:10:52.777387 u2DelayCellTimex100 = 270/100 ps
3956 22:10:52.781065 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3957 22:10:52.784446 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3958 22:10:52.787164 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3959 22:10:52.790546 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 22:10:52.797003 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 22:10:52.800398 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 22:10:52.800478
3963 22:10:52.803568 CA PerBit enable=1, Macro0, CA PI delay=33
3964 22:10:52.803674
3965 22:10:52.806992 [CBTSetCACLKResult] CA Dly = 33
3966 22:10:52.807083 CS Dly: 4 (0~35)
3967 22:10:52.807145 ==
3968 22:10:52.810173 Dram Type= 6, Freq= 0, CH_0, rank 1
3969 22:10:52.817262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 22:10:52.817374 ==
3971 22:10:52.820310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3972 22:10:52.827070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3973 22:10:52.830011 [CA 0] Center 36 (6~66) winsize 61
3974 22:10:52.833421 [CA 1] Center 36 (6~66) winsize 61
3975 22:10:52.836689 [CA 2] Center 34 (4~65) winsize 62
3976 22:10:52.840349 [CA 3] Center 34 (4~65) winsize 62
3977 22:10:52.843283 [CA 4] Center 33 (3~64) winsize 62
3978 22:10:52.847012 [CA 5] Center 33 (2~64) winsize 63
3979 22:10:52.847112
3980 22:10:52.850165 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3981 22:10:52.850241
3982 22:10:52.853754 [CATrainingPosCal] consider 2 rank data
3983 22:10:52.856425 u2DelayCellTimex100 = 270/100 ps
3984 22:10:52.859912 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3985 22:10:52.866651 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3986 22:10:52.869899 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3987 22:10:52.872945 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3988 22:10:52.876583 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3989 22:10:52.879810 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 22:10:52.879915
3991 22:10:52.883130 CA PerBit enable=1, Macro0, CA PI delay=33
3992 22:10:52.883232
3993 22:10:52.886350 [CBTSetCACLKResult] CA Dly = 33
3994 22:10:52.886435 CS Dly: 4 (0~36)
3995 22:10:52.889778
3996 22:10:52.893047 ----->DramcWriteLeveling(PI) begin...
3997 22:10:52.893224 ==
3998 22:10:52.896188 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 22:10:52.899538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 22:10:52.899625 ==
4001 22:10:52.902822 Write leveling (Byte 0): 33 => 33
4002 22:10:52.905984 Write leveling (Byte 1): 30 => 30
4003 22:10:52.909761 DramcWriteLeveling(PI) end<-----
4004 22:10:52.909866
4005 22:10:52.909957 ==
4006 22:10:52.912981 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 22:10:52.915996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 22:10:52.916108 ==
4009 22:10:52.919767 [Gating] SW mode calibration
4010 22:10:52.926144 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4011 22:10:52.932905 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4012 22:10:52.936023 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 22:10:52.939395 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 22:10:52.945915 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 22:10:52.949135 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4016 22:10:52.952551 0 9 16 | B1->B0 | 3030 2626 | 0 0 | (1 1) (0 0)
4017 22:10:52.959297 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 22:10:52.962392 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 22:10:52.965634 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 22:10:52.972437 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 22:10:52.975853 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 22:10:52.978581 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 22:10:52.985165 0 10 12 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
4024 22:10:52.988427 0 10 16 | B1->B0 | 3333 4343 | 0 0 | (0 0) (0 0)
4025 22:10:52.992206 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 22:10:52.998543 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 22:10:53.001764 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 22:10:53.005134 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 22:10:53.011697 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 22:10:53.015163 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 22:10:53.018403 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4032 22:10:53.025062 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4033 22:10:53.027936 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 22:10:53.031409 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 22:10:53.037911 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 22:10:53.041301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 22:10:53.044312 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 22:10:53.051018 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 22:10:53.054457 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 22:10:53.058000 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 22:10:53.064361 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 22:10:53.067877 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 22:10:53.070911 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 22:10:53.078069 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 22:10:53.081272 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 22:10:53.084127 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 22:10:53.091268 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4048 22:10:53.094069 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4049 22:10:53.097842 Total UI for P1: 0, mck2ui 16
4050 22:10:53.100721 best dqsien dly found for B0: ( 0, 13, 12)
4051 22:10:53.104650 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 22:10:53.107413 Total UI for P1: 0, mck2ui 16
4053 22:10:53.110927 best dqsien dly found for B1: ( 0, 13, 14)
4054 22:10:53.114196 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4055 22:10:53.117505 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4056 22:10:53.117580
4057 22:10:53.123966 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4058 22:10:53.127386 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4059 22:10:53.130510 [Gating] SW calibration Done
4060 22:10:53.130633 ==
4061 22:10:53.133877 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 22:10:53.136950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 22:10:53.137024 ==
4064 22:10:53.137085 RX Vref Scan: 0
4065 22:10:53.137150
4066 22:10:53.140827 RX Vref 0 -> 0, step: 1
4067 22:10:53.140901
4068 22:10:53.143884 RX Delay -230 -> 252, step: 16
4069 22:10:53.147488 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4070 22:10:53.150754 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4071 22:10:53.156998 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4072 22:10:53.160211 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4073 22:10:53.163697 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4074 22:10:53.166736 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4075 22:10:53.173337 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4076 22:10:53.176815 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4077 22:10:53.180245 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4078 22:10:53.183067 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4079 22:10:53.189567 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4080 22:10:53.193016 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4081 22:10:53.196307 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4082 22:10:53.199541 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4083 22:10:53.206246 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4084 22:10:53.209575 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4085 22:10:53.209650 ==
4086 22:10:53.212730 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 22:10:53.216310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 22:10:53.216388 ==
4089 22:10:53.219794 DQS Delay:
4090 22:10:53.219866 DQS0 = 0, DQS1 = 0
4091 22:10:53.219928 DQM Delay:
4092 22:10:53.223103 DQM0 = 41, DQM1 = 29
4093 22:10:53.223180 DQ Delay:
4094 22:10:53.226340 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4095 22:10:53.229171 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4096 22:10:53.232617 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4097 22:10:53.236099 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4098 22:10:53.236171
4099 22:10:53.236233
4100 22:10:53.236291 ==
4101 22:10:53.239475 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 22:10:53.245781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 22:10:53.245858 ==
4104 22:10:53.245920
4105 22:10:53.245979
4106 22:10:53.246043 TX Vref Scan disable
4107 22:10:53.249786 == TX Byte 0 ==
4108 22:10:53.252800 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4109 22:10:53.259902 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4110 22:10:53.259976 == TX Byte 1 ==
4111 22:10:53.262533 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4112 22:10:53.269588 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4113 22:10:53.269666 ==
4114 22:10:53.273010 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 22:10:53.276190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 22:10:53.276274 ==
4117 22:10:53.276339
4118 22:10:53.276398
4119 22:10:53.279021 TX Vref Scan disable
4120 22:10:53.282322 == TX Byte 0 ==
4121 22:10:53.285810 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4122 22:10:53.289624 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4123 22:10:53.292466 == TX Byte 1 ==
4124 22:10:53.295785 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4125 22:10:53.299283 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4126 22:10:53.299355
4127 22:10:53.302201 [DATLAT]
4128 22:10:53.302271 Freq=600, CH0 RK0
4129 22:10:53.302337
4130 22:10:53.305475 DATLAT Default: 0x9
4131 22:10:53.305550 0, 0xFFFF, sum = 0
4132 22:10:53.308826 1, 0xFFFF, sum = 0
4133 22:10:53.308896 2, 0xFFFF, sum = 0
4134 22:10:53.312222 3, 0xFFFF, sum = 0
4135 22:10:53.312292 4, 0xFFFF, sum = 0
4136 22:10:53.315683 5, 0xFFFF, sum = 0
4137 22:10:53.315758 6, 0xFFFF, sum = 0
4138 22:10:53.318825 7, 0xFFFF, sum = 0
4139 22:10:53.318898 8, 0x0, sum = 1
4140 22:10:53.321944 9, 0x0, sum = 2
4141 22:10:53.322020 10, 0x0, sum = 3
4142 22:10:53.325318 11, 0x0, sum = 4
4143 22:10:53.325390 best_step = 9
4144 22:10:53.325456
4145 22:10:53.325514 ==
4146 22:10:53.328614 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 22:10:53.332347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 22:10:53.332420 ==
4149 22:10:53.335857 RX Vref Scan: 1
4150 22:10:53.335931
4151 22:10:53.339020 RX Vref 0 -> 0, step: 1
4152 22:10:53.339091
4153 22:10:53.339150 RX Delay -195 -> 252, step: 8
4154 22:10:53.342297
4155 22:10:53.342374 Set Vref, RX VrefLevel [Byte0]: 58
4156 22:10:53.345545 [Byte1]: 57
4157 22:10:53.350369
4158 22:10:53.350460 Final RX Vref Byte 0 = 58 to rank0
4159 22:10:53.353256 Final RX Vref Byte 1 = 57 to rank0
4160 22:10:53.357266 Final RX Vref Byte 0 = 58 to rank1
4161 22:10:53.360149 Final RX Vref Byte 1 = 57 to rank1==
4162 22:10:53.363411 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 22:10:53.370050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 22:10:53.370135 ==
4165 22:10:53.370207 DQS Delay:
4166 22:10:53.370307 DQS0 = 0, DQS1 = 0
4167 22:10:53.373558 DQM Delay:
4168 22:10:53.373647 DQM0 = 41, DQM1 = 33
4169 22:10:53.377025 DQ Delay:
4170 22:10:53.379851 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =40
4171 22:10:53.383634 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4172 22:10:53.386492 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4173 22:10:53.389921 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4174 22:10:53.390002
4175 22:10:53.390079
4176 22:10:53.396618 [DQSOSCAuto] RK0, (LSB)MR18= 0x673e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4177 22:10:53.400092 CH0 RK0: MR19=808, MR18=673E
4178 22:10:53.406678 CH0_RK0: MR19=0x808, MR18=0x673E, DQSOSC=390, MR23=63, INC=172, DEC=114
4179 22:10:53.406759
4180 22:10:53.409998 ----->DramcWriteLeveling(PI) begin...
4181 22:10:53.410080 ==
4182 22:10:53.413451 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 22:10:53.416924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 22:10:53.417031 ==
4185 22:10:53.419964 Write leveling (Byte 0): 32 => 32
4186 22:10:53.422804 Write leveling (Byte 1): 31 => 31
4187 22:10:53.426483 DramcWriteLeveling(PI) end<-----
4188 22:10:53.426565
4189 22:10:53.426654 ==
4190 22:10:53.429423 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 22:10:53.432791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 22:10:53.436217 ==
4193 22:10:53.436321 [Gating] SW mode calibration
4194 22:10:53.446234 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4195 22:10:53.449102 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4196 22:10:53.452788 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 22:10:53.459225 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 22:10:53.462569 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 22:10:53.465978 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4200 22:10:53.472267 0 9 16 | B1->B0 | 2f2f 2c2c | 1 0 | (0 0) (0 0)
4201 22:10:53.476013 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 22:10:53.479377 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 22:10:53.485366 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 22:10:53.488804 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 22:10:53.492322 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 22:10:53.498476 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 22:10:53.501913 0 10 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4208 22:10:53.505376 0 10 16 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
4209 22:10:53.511720 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 22:10:53.515189 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 22:10:53.518548 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 22:10:53.525476 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 22:10:53.528817 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 22:10:53.531836 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 22:10:53.538564 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4216 22:10:53.541800 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 22:10:53.545187 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 22:10:53.551601 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 22:10:53.554915 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 22:10:53.558671 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 22:10:53.564992 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 22:10:53.568229 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 22:10:53.571652 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 22:10:53.577943 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 22:10:53.581520 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 22:10:53.584515 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 22:10:53.591395 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 22:10:53.594714 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 22:10:53.597715 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 22:10:53.604717 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 22:10:53.608009 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4232 22:10:53.611248 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 22:10:53.614530 Total UI for P1: 0, mck2ui 16
4234 22:10:53.617689 best dqsien dly found for B0: ( 0, 13, 12)
4235 22:10:53.621592 Total UI for P1: 0, mck2ui 16
4236 22:10:53.624378 best dqsien dly found for B1: ( 0, 13, 12)
4237 22:10:53.627629 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4238 22:10:53.631086 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4239 22:10:53.631167
4240 22:10:53.637902 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4241 22:10:53.640924 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4242 22:10:53.641006 [Gating] SW calibration Done
4243 22:10:53.644046 ==
4244 22:10:53.647344 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 22:10:53.650685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 22:10:53.650762 ==
4247 22:10:53.650825 RX Vref Scan: 0
4248 22:10:53.650884
4249 22:10:53.653890 RX Vref 0 -> 0, step: 1
4250 22:10:53.653975
4251 22:10:53.657287 RX Delay -230 -> 252, step: 16
4252 22:10:53.660619 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4253 22:10:53.664160 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4254 22:10:53.670519 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4255 22:10:53.673861 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4256 22:10:53.677076 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4257 22:10:53.680739 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4258 22:10:53.687057 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4259 22:10:53.690520 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4260 22:10:53.693963 iDelay=218, Bit 8, Center 33 (-134 ~ 201) 336
4261 22:10:53.697098 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4262 22:10:53.700945 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4263 22:10:53.706902 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4264 22:10:53.710388 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4265 22:10:53.713707 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4266 22:10:53.716806 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4267 22:10:53.724005 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4268 22:10:53.724083 ==
4269 22:10:53.726756 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 22:10:53.730152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 22:10:53.730225 ==
4272 22:10:53.730287 DQS Delay:
4273 22:10:53.733546 DQS0 = 0, DQS1 = 0
4274 22:10:53.733647 DQM Delay:
4275 22:10:53.736756 DQM0 = 42, DQM1 = 36
4276 22:10:53.736826 DQ Delay:
4277 22:10:53.740156 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4278 22:10:53.743240 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4279 22:10:53.746883 DQ8 =33, DQ9 =17, DQ10 =33, DQ11 =33
4280 22:10:53.749949 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4281 22:10:53.750047
4282 22:10:53.750139
4283 22:10:53.750224 ==
4284 22:10:53.753256 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 22:10:53.759824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 22:10:53.759906 ==
4287 22:10:53.759981
4288 22:10:53.760041
4289 22:10:53.760097 TX Vref Scan disable
4290 22:10:53.763085 == TX Byte 0 ==
4291 22:10:53.766565 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4292 22:10:53.772986 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4293 22:10:53.773087 == TX Byte 1 ==
4294 22:10:53.776422 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4295 22:10:53.782947 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4296 22:10:53.783030 ==
4297 22:10:53.786742 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 22:10:53.789866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 22:10:53.789934 ==
4300 22:10:53.789999
4301 22:10:53.790057
4302 22:10:53.792909 TX Vref Scan disable
4303 22:10:53.796134 == TX Byte 0 ==
4304 22:10:53.799709 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4305 22:10:53.802950 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4306 22:10:53.806166 == TX Byte 1 ==
4307 22:10:53.809608 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4308 22:10:53.812673 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4309 22:10:53.812743
4310 22:10:53.812807 [DATLAT]
4311 22:10:53.816012 Freq=600, CH0 RK1
4312 22:10:53.816085
4313 22:10:53.819157 DATLAT Default: 0x9
4314 22:10:53.819228 0, 0xFFFF, sum = 0
4315 22:10:53.822852 1, 0xFFFF, sum = 0
4316 22:10:53.822930 2, 0xFFFF, sum = 0
4317 22:10:53.826074 3, 0xFFFF, sum = 0
4318 22:10:53.826142 4, 0xFFFF, sum = 0
4319 22:10:53.828958 5, 0xFFFF, sum = 0
4320 22:10:53.829035 6, 0xFFFF, sum = 0
4321 22:10:53.832526 7, 0xFFFF, sum = 0
4322 22:10:53.832605 8, 0x0, sum = 1
4323 22:10:53.835637 9, 0x0, sum = 2
4324 22:10:53.835739 10, 0x0, sum = 3
4325 22:10:53.838959 11, 0x0, sum = 4
4326 22:10:53.839030 best_step = 9
4327 22:10:53.839090
4328 22:10:53.839154 ==
4329 22:10:53.842215 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 22:10:53.845655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 22:10:53.848810 ==
4332 22:10:53.848882 RX Vref Scan: 0
4333 22:10:53.848941
4334 22:10:53.851951 RX Vref 0 -> 0, step: 1
4335 22:10:53.852024
4336 22:10:53.855588 RX Delay -195 -> 252, step: 8
4337 22:10:53.858533 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4338 22:10:53.861812 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4339 22:10:53.868525 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4340 22:10:53.871775 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4341 22:10:53.875279 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4342 22:10:53.878424 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4343 22:10:53.884850 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4344 22:10:53.888267 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4345 22:10:53.891687 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4346 22:10:53.894911 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4347 22:10:53.901522 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4348 22:10:53.904749 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4349 22:10:53.908101 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4350 22:10:53.911125 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4351 22:10:53.917969 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4352 22:10:53.921236 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4353 22:10:53.921313 ==
4354 22:10:53.924371 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 22:10:53.927462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 22:10:53.927533 ==
4357 22:10:53.930797 DQS Delay:
4358 22:10:53.930865 DQS0 = 0, DQS1 = 0
4359 22:10:53.930929 DQM Delay:
4360 22:10:53.934093 DQM0 = 41, DQM1 = 33
4361 22:10:53.934196 DQ Delay:
4362 22:10:53.937823 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4363 22:10:53.940715 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4364 22:10:53.944111 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4365 22:10:53.947529 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4366 22:10:53.947601
4367 22:10:53.947662
4368 22:10:53.957201 [DQSOSCAuto] RK1, (LSB)MR18= 0x6013, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4369 22:10:53.960461 CH0 RK1: MR19=808, MR18=6013
4370 22:10:53.967447 CH0_RK1: MR19=0x808, MR18=0x6013, DQSOSC=391, MR23=63, INC=171, DEC=114
4371 22:10:53.967526 [RxdqsGatingPostProcess] freq 600
4372 22:10:53.973921 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4373 22:10:53.977161 Pre-setting of DQS Precalculation
4374 22:10:53.980514 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4375 22:10:53.983441 ==
4376 22:10:53.986726 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 22:10:53.990151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 22:10:53.990222 ==
4379 22:10:53.993605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4380 22:10:53.999870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4381 22:10:54.003843 [CA 0] Center 35 (5~66) winsize 62
4382 22:10:54.007002 [CA 1] Center 35 (5~66) winsize 62
4383 22:10:54.010409 [CA 2] Center 34 (3~65) winsize 63
4384 22:10:54.013594 [CA 3] Center 33 (3~64) winsize 62
4385 22:10:54.017207 [CA 4] Center 34 (4~64) winsize 61
4386 22:10:54.020337 [CA 5] Center 33 (3~64) winsize 62
4387 22:10:54.020410
4388 22:10:54.023931 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4389 22:10:54.024029
4390 22:10:54.027042 [CATrainingPosCal] consider 1 rank data
4391 22:10:54.030294 u2DelayCellTimex100 = 270/100 ps
4392 22:10:54.033832 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4393 22:10:54.040236 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 22:10:54.043483 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4395 22:10:54.047406 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4396 22:10:54.050108 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4397 22:10:54.053697 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4398 22:10:54.053800
4399 22:10:54.057023 CA PerBit enable=1, Macro0, CA PI delay=33
4400 22:10:54.057124
4401 22:10:54.060107 [CBTSetCACLKResult] CA Dly = 33
4402 22:10:54.063490 CS Dly: 5 (0~36)
4403 22:10:54.063574 ==
4404 22:10:54.066741 Dram Type= 6, Freq= 0, CH_1, rank 1
4405 22:10:54.070148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 22:10:54.070231 ==
4407 22:10:54.076663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4408 22:10:54.079892 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4409 22:10:54.083887 [CA 0] Center 35 (5~66) winsize 62
4410 22:10:54.087450 [CA 1] Center 36 (6~66) winsize 61
4411 22:10:54.090832 [CA 2] Center 34 (4~65) winsize 62
4412 22:10:54.094345 [CA 3] Center 33 (3~64) winsize 62
4413 22:10:54.097580 [CA 4] Center 34 (3~65) winsize 63
4414 22:10:54.100960 [CA 5] Center 33 (3~64) winsize 62
4415 22:10:54.101029
4416 22:10:54.103759 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4417 22:10:54.103827
4418 22:10:54.107225 [CATrainingPosCal] consider 2 rank data
4419 22:10:54.110411 u2DelayCellTimex100 = 270/100 ps
4420 22:10:54.113794 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4421 22:10:54.120663 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4422 22:10:54.123920 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4423 22:10:54.126846 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4424 22:10:54.130116 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4425 22:10:54.133442 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4426 22:10:54.133522
4427 22:10:54.136970 CA PerBit enable=1, Macro0, CA PI delay=33
4428 22:10:54.137050
4429 22:10:54.140285 [CBTSetCACLKResult] CA Dly = 33
4430 22:10:54.143387 CS Dly: 5 (0~36)
4431 22:10:54.143467
4432 22:10:54.146731 ----->DramcWriteLeveling(PI) begin...
4433 22:10:54.146812 ==
4434 22:10:54.149626 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 22:10:54.153232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 22:10:54.153313 ==
4437 22:10:54.156233 Write leveling (Byte 0): 29 => 29
4438 22:10:54.159657 Write leveling (Byte 1): 31 => 31
4439 22:10:54.162934 DramcWriteLeveling(PI) end<-----
4440 22:10:54.163010
4441 22:10:54.163077 ==
4442 22:10:54.166600 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 22:10:54.169541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 22:10:54.169613 ==
4445 22:10:54.173144 [Gating] SW mode calibration
4446 22:10:54.179687 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4447 22:10:54.186181 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4448 22:10:54.189498 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 22:10:54.192712 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 22:10:54.199122 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4451 22:10:54.202494 0 9 12 | B1->B0 | 3030 2b2b | 1 0 | (1 1) (1 0)
4452 22:10:54.206050 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4453 22:10:54.212844 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 22:10:54.215898 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 22:10:54.218844 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 22:10:54.225710 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 22:10:54.228981 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 22:10:54.232122 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4459 22:10:54.238838 0 10 12 | B1->B0 | 2b2b 3b3b | 0 1 | (0 0) (0 0)
4460 22:10:54.242148 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 22:10:54.245636 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 22:10:54.251857 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 22:10:54.255304 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 22:10:54.258784 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 22:10:54.265349 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 22:10:54.268550 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 22:10:54.272074 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4468 22:10:54.278563 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 22:10:54.281786 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 22:10:54.285002 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 22:10:54.291767 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 22:10:54.294784 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 22:10:54.298090 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 22:10:54.304984 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 22:10:54.308199 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 22:10:54.311536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 22:10:54.317942 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 22:10:54.321289 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 22:10:54.324637 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 22:10:54.331427 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 22:10:54.334587 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 22:10:54.337727 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 22:10:54.344456 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4484 22:10:54.347846 Total UI for P1: 0, mck2ui 16
4485 22:10:54.351002 best dqsien dly found for B0: ( 0, 13, 10)
4486 22:10:54.354373 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 22:10:54.357451 Total UI for P1: 0, mck2ui 16
4488 22:10:54.360755 best dqsien dly found for B1: ( 0, 13, 12)
4489 22:10:54.364426 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4490 22:10:54.367467 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4491 22:10:54.367543
4492 22:10:54.370862 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4493 22:10:54.377342 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4494 22:10:54.377419 [Gating] SW calibration Done
4495 22:10:54.377485 ==
4496 22:10:54.380657 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 22:10:54.387362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 22:10:54.387458 ==
4499 22:10:54.387522 RX Vref Scan: 0
4500 22:10:54.387581
4501 22:10:54.390917 RX Vref 0 -> 0, step: 1
4502 22:10:54.390997
4503 22:10:54.393688 RX Delay -230 -> 252, step: 16
4504 22:10:54.397579 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4505 22:10:54.400438 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4506 22:10:54.407345 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4507 22:10:54.410250 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4508 22:10:54.413516 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4509 22:10:54.416953 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4510 22:10:54.420295 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4511 22:10:54.427055 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4512 22:10:54.430379 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4513 22:10:54.433785 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4514 22:10:54.436531 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4515 22:10:54.443366 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4516 22:10:54.446765 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4517 22:10:54.449791 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4518 22:10:54.453320 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4519 22:10:54.459663 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4520 22:10:54.459740 ==
4521 22:10:54.463170 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 22:10:54.466726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 22:10:54.466808 ==
4524 22:10:54.466872 DQS Delay:
4525 22:10:54.469607 DQS0 = 0, DQS1 = 0
4526 22:10:54.469687 DQM Delay:
4527 22:10:54.473201 DQM0 = 43, DQM1 = 35
4528 22:10:54.473280 DQ Delay:
4529 22:10:54.476069 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4530 22:10:54.479848 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4531 22:10:54.483073 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4532 22:10:54.486216 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4533 22:10:54.486316
4534 22:10:54.486457
4535 22:10:54.486545 ==
4536 22:10:54.489678 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 22:10:54.492568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 22:10:54.496033 ==
4539 22:10:54.496103
4540 22:10:54.496164
4541 22:10:54.496221 TX Vref Scan disable
4542 22:10:54.499499 == TX Byte 0 ==
4543 22:10:54.502421 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4544 22:10:54.505797 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4545 22:10:54.509382 == TX Byte 1 ==
4546 22:10:54.512732 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4547 22:10:54.518925 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4548 22:10:54.519009 ==
4549 22:10:54.522243 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 22:10:54.525603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 22:10:54.525685 ==
4552 22:10:54.525748
4553 22:10:54.525806
4554 22:10:54.528998 TX Vref Scan disable
4555 22:10:54.532540 == TX Byte 0 ==
4556 22:10:54.535839 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4557 22:10:54.538795 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4558 22:10:54.542224 == TX Byte 1 ==
4559 22:10:54.545353 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4560 22:10:54.548660 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4561 22:10:54.548741
4562 22:10:54.552085 [DATLAT]
4563 22:10:54.552165 Freq=600, CH1 RK0
4564 22:10:54.552234
4565 22:10:54.555388 DATLAT Default: 0x9
4566 22:10:54.555461 0, 0xFFFF, sum = 0
4567 22:10:54.558362 1, 0xFFFF, sum = 0
4568 22:10:54.558431 2, 0xFFFF, sum = 0
4569 22:10:54.561868 3, 0xFFFF, sum = 0
4570 22:10:54.561940 4, 0xFFFF, sum = 0
4571 22:10:54.565227 5, 0xFFFF, sum = 0
4572 22:10:54.565316 6, 0xFFFF, sum = 0
4573 22:10:54.568534 7, 0xFFFF, sum = 0
4574 22:10:54.568602 8, 0x0, sum = 1
4575 22:10:54.571495 9, 0x0, sum = 2
4576 22:10:54.571568 10, 0x0, sum = 3
4577 22:10:54.574777 11, 0x0, sum = 4
4578 22:10:54.574843 best_step = 9
4579 22:10:54.574900
4580 22:10:54.574954 ==
4581 22:10:54.578249 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 22:10:54.581789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 22:10:54.584706 ==
4584 22:10:54.584841 RX Vref Scan: 1
4585 22:10:54.584935
4586 22:10:54.587867 RX Vref 0 -> 0, step: 1
4587 22:10:54.587948
4588 22:10:54.591601 RX Delay -195 -> 252, step: 8
4589 22:10:54.591681
4590 22:10:54.595013 Set Vref, RX VrefLevel [Byte0]: 50
4591 22:10:54.595102 [Byte1]: 52
4592 22:10:54.600130
4593 22:10:54.600207 Final RX Vref Byte 0 = 50 to rank0
4594 22:10:54.603148 Final RX Vref Byte 1 = 52 to rank0
4595 22:10:54.606512 Final RX Vref Byte 0 = 50 to rank1
4596 22:10:54.609895 Final RX Vref Byte 1 = 52 to rank1==
4597 22:10:54.613230 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 22:10:54.619308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 22:10:54.619393 ==
4600 22:10:54.619459 DQS Delay:
4601 22:10:54.622550 DQS0 = 0, DQS1 = 0
4602 22:10:54.622675 DQM Delay:
4603 22:10:54.622739 DQM0 = 45, DQM1 = 35
4604 22:10:54.625994 DQ Delay:
4605 22:10:54.629421 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4606 22:10:54.632639 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =40
4607 22:10:54.635769 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4608 22:10:54.639124 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4609 22:10:54.639192
4610 22:10:54.639251
4611 22:10:54.646035 [DQSOSCAuto] RK0, (LSB)MR18= 0x5539, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
4612 22:10:54.649400 CH1 RK0: MR19=808, MR18=5539
4613 22:10:54.655989 CH1_RK0: MR19=0x808, MR18=0x5539, DQSOSC=393, MR23=63, INC=169, DEC=113
4614 22:10:54.656088
4615 22:10:54.659453 ----->DramcWriteLeveling(PI) begin...
4616 22:10:54.659568 ==
4617 22:10:54.662233 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 22:10:54.665888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 22:10:54.665980 ==
4620 22:10:54.668809 Write leveling (Byte 0): 30 => 30
4621 22:10:54.672744 Write leveling (Byte 1): 31 => 31
4622 22:10:54.675676 DramcWriteLeveling(PI) end<-----
4623 22:10:54.675756
4624 22:10:54.675818 ==
4625 22:10:54.678966 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 22:10:54.682172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 22:10:54.685234 ==
4628 22:10:54.685314 [Gating] SW mode calibration
4629 22:10:54.695471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4630 22:10:54.698811 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4631 22:10:54.702131 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4632 22:10:54.708711 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4633 22:10:54.711932 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4634 22:10:54.715200 0 9 12 | B1->B0 | 2f2f 3333 | 0 1 | (0 0) (1 0)
4635 22:10:54.721812 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4636 22:10:54.725127 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 22:10:54.728282 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 22:10:54.734874 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 22:10:54.738055 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 22:10:54.741435 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 22:10:54.748109 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 22:10:54.751335 0 10 12 | B1->B0 | 3737 2d2d | 0 1 | (0 0) (0 0)
4643 22:10:54.754769 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4644 22:10:54.761537 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 22:10:54.765016 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 22:10:54.767741 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 22:10:54.774747 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 22:10:54.777764 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 22:10:54.781373 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 22:10:54.787967 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 22:10:54.791227 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 22:10:54.794551 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 22:10:54.800780 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 22:10:54.804080 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 22:10:54.807299 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 22:10:54.814132 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 22:10:54.817137 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 22:10:54.820274 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 22:10:54.826852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 22:10:54.830183 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 22:10:54.833422 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 22:10:54.840013 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 22:10:54.843371 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 22:10:54.846840 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 22:10:54.853319 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 22:10:54.856865 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4667 22:10:54.863239 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 22:10:54.863320 Total UI for P1: 0, mck2ui 16
4669 22:10:54.866533 best dqsien dly found for B0: ( 0, 13, 12)
4670 22:10:54.869702 Total UI for P1: 0, mck2ui 16
4671 22:10:54.873000 best dqsien dly found for B1: ( 0, 13, 12)
4672 22:10:54.879851 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4673 22:10:54.882978 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4674 22:10:54.883059
4675 22:10:54.886454 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4676 22:10:54.889337 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4677 22:10:54.892750 [Gating] SW calibration Done
4678 22:10:54.892831 ==
4679 22:10:54.896313 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 22:10:54.899792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 22:10:54.899874 ==
4682 22:10:54.902576 RX Vref Scan: 0
4683 22:10:54.902698
4684 22:10:54.902761 RX Vref 0 -> 0, step: 1
4685 22:10:54.902821
4686 22:10:54.905800 RX Delay -230 -> 252, step: 16
4687 22:10:54.909130 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4688 22:10:54.916402 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4689 22:10:54.919226 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4690 22:10:54.922644 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4691 22:10:54.925819 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4692 22:10:54.932248 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4693 22:10:54.935814 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4694 22:10:54.939087 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4695 22:10:54.942268 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4696 22:10:54.948822 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4697 22:10:54.952056 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4698 22:10:54.955951 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4699 22:10:54.958789 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4700 22:10:54.965309 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4701 22:10:54.969129 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4702 22:10:54.972035 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4703 22:10:54.972115 ==
4704 22:10:54.975116 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 22:10:54.978501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 22:10:54.981689 ==
4707 22:10:54.981770 DQS Delay:
4708 22:10:54.981833 DQS0 = 0, DQS1 = 0
4709 22:10:54.985137 DQM Delay:
4710 22:10:54.985234 DQM0 = 40, DQM1 = 34
4711 22:10:54.988299 DQ Delay:
4712 22:10:54.988379 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4713 22:10:54.991944 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4714 22:10:54.995047 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4715 22:10:54.998298 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4716 22:10:54.998379
4717 22:10:54.998442
4718 22:10:55.001590 ==
4719 22:10:55.004881 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 22:10:55.008456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 22:10:55.008537 ==
4722 22:10:55.008600
4723 22:10:55.008659
4724 22:10:55.012092 TX Vref Scan disable
4725 22:10:55.012176 == TX Byte 0 ==
4726 22:10:55.018354 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4727 22:10:55.021799 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4728 22:10:55.021880 == TX Byte 1 ==
4729 22:10:55.028340 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4730 22:10:55.031821 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4731 22:10:55.031902 ==
4732 22:10:55.035078 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 22:10:55.038013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 22:10:55.038094 ==
4735 22:10:55.038158
4736 22:10:55.038217
4737 22:10:55.041263 TX Vref Scan disable
4738 22:10:55.044666 == TX Byte 0 ==
4739 22:10:55.047871 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4740 22:10:55.051119 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4741 22:10:55.055322 == TX Byte 1 ==
4742 22:10:55.058061 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4743 22:10:55.061403 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4744 22:10:55.061484
4745 22:10:55.064803 [DATLAT]
4746 22:10:55.064884 Freq=600, CH1 RK1
4747 22:10:55.064948
4748 22:10:55.068243 DATLAT Default: 0x9
4749 22:10:55.068324 0, 0xFFFF, sum = 0
4750 22:10:55.070994 1, 0xFFFF, sum = 0
4751 22:10:55.071076 2, 0xFFFF, sum = 0
4752 22:10:55.074407 3, 0xFFFF, sum = 0
4753 22:10:55.074489 4, 0xFFFF, sum = 0
4754 22:10:55.077668 5, 0xFFFF, sum = 0
4755 22:10:55.080963 6, 0xFFFF, sum = 0
4756 22:10:55.081045 7, 0xFFFF, sum = 0
4757 22:10:55.081142 8, 0x0, sum = 1
4758 22:10:55.084405 9, 0x0, sum = 2
4759 22:10:55.084487 10, 0x0, sum = 3
4760 22:10:55.087358 11, 0x0, sum = 4
4761 22:10:55.087440 best_step = 9
4762 22:10:55.087505
4763 22:10:55.087563 ==
4764 22:10:55.090808 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 22:10:55.097324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 22:10:55.097406 ==
4767 22:10:55.097511 RX Vref Scan: 0
4768 22:10:55.097571
4769 22:10:55.100772 RX Vref 0 -> 0, step: 1
4770 22:10:55.100853
4771 22:10:55.103802 RX Delay -195 -> 252, step: 8
4772 22:10:55.107782 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4773 22:10:55.113880 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4774 22:10:55.117319 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4775 22:10:55.120580 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4776 22:10:55.124096 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4777 22:10:55.130519 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4778 22:10:55.133557 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4779 22:10:55.136857 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4780 22:10:55.140272 iDelay=213, Bit 8, Center 20 (-139 ~ 180) 320
4781 22:10:55.143551 iDelay=213, Bit 9, Center 20 (-139 ~ 180) 320
4782 22:10:55.150263 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4783 22:10:55.153542 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4784 22:10:55.156761 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4785 22:10:55.160168 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4786 22:10:55.166890 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4787 22:10:55.169935 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4788 22:10:55.170030 ==
4789 22:10:55.173151 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 22:10:55.176608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 22:10:55.176689 ==
4792 22:10:55.180434 DQS Delay:
4793 22:10:55.180515 DQS0 = 0, DQS1 = 0
4794 22:10:55.183329 DQM Delay:
4795 22:10:55.183410 DQM0 = 42, DQM1 = 35
4796 22:10:55.183475 DQ Delay:
4797 22:10:55.186386 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4798 22:10:55.189434 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4799 22:10:55.192843 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4800 22:10:55.196550 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4801 22:10:55.196631
4802 22:10:55.199794
4803 22:10:55.206210 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4804 22:10:55.209210 CH1 RK1: MR19=808, MR18=2D22
4805 22:10:55.216192 CH1_RK1: MR19=0x808, MR18=0x2D22, DQSOSC=401, MR23=63, INC=163, DEC=108
4806 22:10:55.219155 [RxdqsGatingPostProcess] freq 600
4807 22:10:55.222401 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4808 22:10:55.225868 Pre-setting of DQS Precalculation
4809 22:10:55.232823 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4810 22:10:55.239071 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4811 22:10:55.245882 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4812 22:10:55.245964
4813 22:10:55.246028
4814 22:10:55.249148 [Calibration Summary] 1200 Mbps
4815 22:10:55.249229 CH 0, Rank 0
4816 22:10:55.252128 SW Impedance : PASS
4817 22:10:55.255760 DUTY Scan : NO K
4818 22:10:55.255841 ZQ Calibration : PASS
4819 22:10:55.258761 Jitter Meter : NO K
4820 22:10:55.262190 CBT Training : PASS
4821 22:10:55.262271 Write leveling : PASS
4822 22:10:55.265246 RX DQS gating : PASS
4823 22:10:55.268525 RX DQ/DQS(RDDQC) : PASS
4824 22:10:55.268647 TX DQ/DQS : PASS
4825 22:10:55.271957 RX DATLAT : PASS
4826 22:10:55.275111 RX DQ/DQS(Engine): PASS
4827 22:10:55.275192 TX OE : NO K
4828 22:10:55.275256 All Pass.
4829 22:10:55.278409
4830 22:10:55.278515 CH 0, Rank 1
4831 22:10:55.281874 SW Impedance : PASS
4832 22:10:55.281985 DUTY Scan : NO K
4833 22:10:55.285425 ZQ Calibration : PASS
4834 22:10:55.285506 Jitter Meter : NO K
4835 22:10:55.288814 CBT Training : PASS
4836 22:10:55.291646 Write leveling : PASS
4837 22:10:55.291727 RX DQS gating : PASS
4838 22:10:55.294890 RX DQ/DQS(RDDQC) : PASS
4839 22:10:55.298405 TX DQ/DQS : PASS
4840 22:10:55.298486 RX DATLAT : PASS
4841 22:10:55.301865 RX DQ/DQS(Engine): PASS
4842 22:10:55.305020 TX OE : NO K
4843 22:10:55.305102 All Pass.
4844 22:10:55.305203
4845 22:10:55.305297 CH 1, Rank 0
4846 22:10:55.308098 SW Impedance : PASS
4847 22:10:55.311789 DUTY Scan : NO K
4848 22:10:55.311870 ZQ Calibration : PASS
4849 22:10:55.314863 Jitter Meter : NO K
4850 22:10:55.318438 CBT Training : PASS
4851 22:10:55.318519 Write leveling : PASS
4852 22:10:55.321302 RX DQS gating : PASS
4853 22:10:55.324868 RX DQ/DQS(RDDQC) : PASS
4854 22:10:55.324949 TX DQ/DQS : PASS
4855 22:10:55.327873 RX DATLAT : PASS
4856 22:10:55.331558 RX DQ/DQS(Engine): PASS
4857 22:10:55.331639 TX OE : NO K
4858 22:10:55.334772 All Pass.
4859 22:10:55.334890
4860 22:10:55.334952 CH 1, Rank 1
4861 22:10:55.337946 SW Impedance : PASS
4862 22:10:55.338026 DUTY Scan : NO K
4863 22:10:55.341488 ZQ Calibration : PASS
4864 22:10:55.344808 Jitter Meter : NO K
4865 22:10:55.344889 CBT Training : PASS
4866 22:10:55.348019 Write leveling : PASS
4867 22:10:55.351047 RX DQS gating : PASS
4868 22:10:55.351128 RX DQ/DQS(RDDQC) : PASS
4869 22:10:55.354252 TX DQ/DQS : PASS
4870 22:10:55.354365 RX DATLAT : PASS
4871 22:10:55.357799 RX DQ/DQS(Engine): PASS
4872 22:10:55.361143 TX OE : NO K
4873 22:10:55.361224 All Pass.
4874 22:10:55.361289
4875 22:10:55.364134 DramC Write-DBI off
4876 22:10:55.367685 PER_BANK_REFRESH: Hybrid Mode
4877 22:10:55.367766 TX_TRACKING: ON
4878 22:10:55.377288 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4879 22:10:55.380925 [FAST_K] Save calibration result to emmc
4880 22:10:55.384165 dramc_set_vcore_voltage set vcore to 662500
4881 22:10:55.387510 Read voltage for 933, 3
4882 22:10:55.387590 Vio18 = 0
4883 22:10:55.387654 Vcore = 662500
4884 22:10:55.390761 Vdram = 0
4885 22:10:55.390841 Vddq = 0
4886 22:10:55.390905 Vmddr = 0
4887 22:10:55.397046 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4888 22:10:55.400315 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4889 22:10:55.403836 MEM_TYPE=3, freq_sel=17
4890 22:10:55.407248 sv_algorithm_assistance_LP4_1600
4891 22:10:55.410799 ============ PULL DRAM RESETB DOWN ============
4892 22:10:55.413491 ========== PULL DRAM RESETB DOWN end =========
4893 22:10:55.420125 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4894 22:10:55.423501 ===================================
4895 22:10:55.427168 LPDDR4 DRAM CONFIGURATION
4896 22:10:55.429969 ===================================
4897 22:10:55.430051 EX_ROW_EN[0] = 0x0
4898 22:10:55.433304 EX_ROW_EN[1] = 0x0
4899 22:10:55.433384 LP4Y_EN = 0x0
4900 22:10:55.436827 WORK_FSP = 0x0
4901 22:10:55.436908 WL = 0x3
4902 22:10:55.439783 RL = 0x3
4903 22:10:55.439864 BL = 0x2
4904 22:10:55.443160 RPST = 0x0
4905 22:10:55.443240 RD_PRE = 0x0
4906 22:10:55.446641 WR_PRE = 0x1
4907 22:10:55.446723 WR_PST = 0x0
4908 22:10:55.449902 DBI_WR = 0x0
4909 22:10:55.449982 DBI_RD = 0x0
4910 22:10:55.453032 OTF = 0x1
4911 22:10:55.456885 ===================================
4912 22:10:55.459819 ===================================
4913 22:10:55.459917 ANA top config
4914 22:10:55.463127 ===================================
4915 22:10:55.466353 DLL_ASYNC_EN = 0
4916 22:10:55.469354 ALL_SLAVE_EN = 1
4917 22:10:55.473092 NEW_RANK_MODE = 1
4918 22:10:55.476039 DLL_IDLE_MODE = 1
4919 22:10:55.476119 LP45_APHY_COMB_EN = 1
4920 22:10:55.479863 TX_ODT_DIS = 1
4921 22:10:55.483069 NEW_8X_MODE = 1
4922 22:10:55.486204 ===================================
4923 22:10:55.489604 ===================================
4924 22:10:55.492665 data_rate = 1866
4925 22:10:55.495604 CKR = 1
4926 22:10:55.495686 DQ_P2S_RATIO = 8
4927 22:10:55.499237 ===================================
4928 22:10:55.502657 CA_P2S_RATIO = 8
4929 22:10:55.505916 DQ_CA_OPEN = 0
4930 22:10:55.508781 DQ_SEMI_OPEN = 0
4931 22:10:55.512311 CA_SEMI_OPEN = 0
4932 22:10:55.515590 CA_FULL_RATE = 0
4933 22:10:55.515671 DQ_CKDIV4_EN = 1
4934 22:10:55.519308 CA_CKDIV4_EN = 1
4935 22:10:55.522603 CA_PREDIV_EN = 0
4936 22:10:55.525428 PH8_DLY = 0
4937 22:10:55.528822 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4938 22:10:55.532085 DQ_AAMCK_DIV = 4
4939 22:10:55.532189 CA_AAMCK_DIV = 4
4940 22:10:55.535931 CA_ADMCK_DIV = 4
4941 22:10:55.538579 DQ_TRACK_CA_EN = 0
4942 22:10:55.542302 CA_PICK = 933
4943 22:10:55.545392 CA_MCKIO = 933
4944 22:10:55.548759 MCKIO_SEMI = 0
4945 22:10:55.552115 PLL_FREQ = 3732
4946 22:10:55.555327 DQ_UI_PI_RATIO = 32
4947 22:10:55.555448 CA_UI_PI_RATIO = 0
4948 22:10:55.558620 ===================================
4949 22:10:55.561902 ===================================
4950 22:10:55.565142 memory_type:LPDDR4
4951 22:10:55.568660 GP_NUM : 10
4952 22:10:55.568743 SRAM_EN : 1
4953 22:10:55.572079 MD32_EN : 0
4954 22:10:55.575321 ===================================
4955 22:10:55.578723 [ANA_INIT] >>>>>>>>>>>>>>
4956 22:10:55.581793 <<<<<< [CONFIGURE PHASE]: ANA_TX
4957 22:10:55.584790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4958 22:10:55.588423 ===================================
4959 22:10:55.588507 data_rate = 1866,PCW = 0X8f00
4960 22:10:55.591596 ===================================
4961 22:10:55.595573 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4962 22:10:55.601580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 22:10:55.608380 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4964 22:10:55.611290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4965 22:10:55.614913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4966 22:10:55.617904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4967 22:10:55.621162 [ANA_INIT] flow start
4968 22:10:55.624907 [ANA_INIT] PLL >>>>>>>>
4969 22:10:55.624988 [ANA_INIT] PLL <<<<<<<<
4970 22:10:55.627714 [ANA_INIT] MIDPI >>>>>>>>
4971 22:10:55.631178 [ANA_INIT] MIDPI <<<<<<<<
4972 22:10:55.631259 [ANA_INIT] DLL >>>>>>>>
4973 22:10:55.634518 [ANA_INIT] flow end
4974 22:10:55.637927 ============ LP4 DIFF to SE enter ============
4975 22:10:55.641278 ============ LP4 DIFF to SE exit ============
4976 22:10:55.644452 [ANA_INIT] <<<<<<<<<<<<<
4977 22:10:55.647725 [Flow] Enable top DCM control >>>>>
4978 22:10:55.650888 [Flow] Enable top DCM control <<<<<
4979 22:10:55.654285 Enable DLL master slave shuffle
4980 22:10:55.660900 ==============================================================
4981 22:10:55.661000 Gating Mode config
4982 22:10:55.667843 ==============================================================
4983 22:10:55.670894 Config description:
4984 22:10:55.677276 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4985 22:10:55.684310 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4986 22:10:55.690728 SELPH_MODE 0: By rank 1: By Phase
4987 22:10:55.697072 ==============================================================
4988 22:10:55.697228 GAT_TRACK_EN = 1
4989 22:10:55.701105 RX_GATING_MODE = 2
4990 22:10:55.703540 RX_GATING_TRACK_MODE = 2
4991 22:10:55.707304 SELPH_MODE = 1
4992 22:10:55.710527 PICG_EARLY_EN = 1
4993 22:10:55.713475 VALID_LAT_VALUE = 1
4994 22:10:55.720337 ==============================================================
4995 22:10:55.723511 Enter into Gating configuration >>>>
4996 22:10:55.727058 Exit from Gating configuration <<<<
4997 22:10:55.730091 Enter into DVFS_PRE_config >>>>>
4998 22:10:55.740368 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4999 22:10:55.743103 Exit from DVFS_PRE_config <<<<<
5000 22:10:55.746578 Enter into PICG configuration >>>>
5001 22:10:55.749900 Exit from PICG configuration <<<<
5002 22:10:55.753163 [RX_INPUT] configuration >>>>>
5003 22:10:55.756865 [RX_INPUT] configuration <<<<<
5004 22:10:55.760105 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5005 22:10:55.766609 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5006 22:10:55.773384 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5007 22:10:55.780162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5008 22:10:55.782812 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5009 22:10:55.789813 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5010 22:10:55.793119 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5011 22:10:55.799552 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5012 22:10:55.802832 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5013 22:10:55.806534 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5014 22:10:55.809483 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5015 22:10:55.816162 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 22:10:55.819797 ===================================
5017 22:10:55.819874 LPDDR4 DRAM CONFIGURATION
5018 22:10:55.822822 ===================================
5019 22:10:55.826102 EX_ROW_EN[0] = 0x0
5020 22:10:55.829846 EX_ROW_EN[1] = 0x0
5021 22:10:55.829946 LP4Y_EN = 0x0
5022 22:10:55.832763 WORK_FSP = 0x0
5023 22:10:55.832873 WL = 0x3
5024 22:10:55.835986 RL = 0x3
5025 22:10:55.836079 BL = 0x2
5026 22:10:55.839328 RPST = 0x0
5027 22:10:55.839408 RD_PRE = 0x0
5028 22:10:55.842883 WR_PRE = 0x1
5029 22:10:55.842967 WR_PST = 0x0
5030 22:10:55.845776 DBI_WR = 0x0
5031 22:10:55.845855 DBI_RD = 0x0
5032 22:10:55.849354 OTF = 0x1
5033 22:10:55.852785 ===================================
5034 22:10:55.855857 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5035 22:10:55.859221 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5036 22:10:55.866004 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5037 22:10:55.868995 ===================================
5038 22:10:55.869076 LPDDR4 DRAM CONFIGURATION
5039 22:10:55.872210 ===================================
5040 22:10:55.875875 EX_ROW_EN[0] = 0x10
5041 22:10:55.879029 EX_ROW_EN[1] = 0x0
5042 22:10:55.879112 LP4Y_EN = 0x0
5043 22:10:55.882568 WORK_FSP = 0x0
5044 22:10:55.882691 WL = 0x3
5045 22:10:55.885389 RL = 0x3
5046 22:10:55.885469 BL = 0x2
5047 22:10:55.888724 RPST = 0x0
5048 22:10:55.888804 RD_PRE = 0x0
5049 22:10:55.891753 WR_PRE = 0x1
5050 22:10:55.891837 WR_PST = 0x0
5051 22:10:55.895265 DBI_WR = 0x0
5052 22:10:55.895345 DBI_RD = 0x0
5053 22:10:55.898326 OTF = 0x1
5054 22:10:55.901705 ===================================
5055 22:10:55.908461 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5056 22:10:55.912033 nWR fixed to 30
5057 22:10:55.915504 [ModeRegInit_LP4] CH0 RK0
5058 22:10:55.915585 [ModeRegInit_LP4] CH0 RK1
5059 22:10:55.918560 [ModeRegInit_LP4] CH1 RK0
5060 22:10:55.921750 [ModeRegInit_LP4] CH1 RK1
5061 22:10:55.921830 match AC timing 9
5062 22:10:55.928154 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5063 22:10:55.931768 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5064 22:10:55.934918 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5065 22:10:55.941460 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5066 22:10:55.944855 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5067 22:10:55.944954 ==
5068 22:10:55.948061 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 22:10:55.951613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 22:10:55.951711 ==
5071 22:10:55.958253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5072 22:10:55.964408 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5073 22:10:55.968188 [CA 0] Center 37 (7~68) winsize 62
5074 22:10:55.970933 [CA 1] Center 37 (7~68) winsize 62
5075 22:10:55.974520 [CA 2] Center 34 (4~65) winsize 62
5076 22:10:55.977554 [CA 3] Center 35 (5~65) winsize 61
5077 22:10:55.980749 [CA 4] Center 33 (3~64) winsize 62
5078 22:10:55.984099 [CA 5] Center 33 (3~63) winsize 61
5079 22:10:55.984184
5080 22:10:55.987651 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5081 22:10:55.987738
5082 22:10:55.991006 [CATrainingPosCal] consider 1 rank data
5083 22:10:55.994313 u2DelayCellTimex100 = 270/100 ps
5084 22:10:55.997494 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5085 22:10:56.000933 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5086 22:10:56.003972 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5087 22:10:56.007552 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5088 22:10:56.014736 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5089 22:10:56.017485 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5090 22:10:56.017566
5091 22:10:56.020694 CA PerBit enable=1, Macro0, CA PI delay=33
5092 22:10:56.020775
5093 22:10:56.023793 [CBTSetCACLKResult] CA Dly = 33
5094 22:10:56.023874 CS Dly: 7 (0~38)
5095 22:10:56.023938 ==
5096 22:10:56.027155 Dram Type= 6, Freq= 0, CH_0, rank 1
5097 22:10:56.033966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 22:10:56.034048 ==
5099 22:10:56.037337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5100 22:10:56.043579 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5101 22:10:56.046985 [CA 0] Center 37 (7~68) winsize 62
5102 22:10:56.050299 [CA 1] Center 37 (7~68) winsize 62
5103 22:10:56.053568 [CA 2] Center 34 (4~65) winsize 62
5104 22:10:56.056727 [CA 3] Center 34 (4~65) winsize 62
5105 22:10:56.060217 [CA 4] Center 33 (3~64) winsize 62
5106 22:10:56.063709 [CA 5] Center 33 (3~63) winsize 61
5107 22:10:56.063808
5108 22:10:56.066807 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5109 22:10:56.066902
5110 22:10:56.070337 [CATrainingPosCal] consider 2 rank data
5111 22:10:56.073558 u2DelayCellTimex100 = 270/100 ps
5112 22:10:56.076940 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5113 22:10:56.083392 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5114 22:10:56.086925 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5115 22:10:56.089766 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5116 22:10:56.093529 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5117 22:10:56.096308 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5118 22:10:56.096389
5119 22:10:56.099741 CA PerBit enable=1, Macro0, CA PI delay=33
5120 22:10:56.099822
5121 22:10:56.103292 [CBTSetCACLKResult] CA Dly = 33
5122 22:10:56.107232 CS Dly: 7 (0~39)
5123 22:10:56.107313
5124 22:10:56.109497 ----->DramcWriteLeveling(PI) begin...
5125 22:10:56.109581 ==
5126 22:10:56.113251 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 22:10:56.116031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 22:10:56.116113 ==
5129 22:10:56.119831 Write leveling (Byte 0): 31 => 31
5130 22:10:56.123015 Write leveling (Byte 1): 30 => 30
5131 22:10:56.126162 DramcWriteLeveling(PI) end<-----
5132 22:10:56.126242
5133 22:10:56.126306 ==
5134 22:10:56.129624 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 22:10:56.133046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 22:10:56.133128 ==
5137 22:10:56.136553 [Gating] SW mode calibration
5138 22:10:56.142909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5139 22:10:56.149461 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5140 22:10:56.152310 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5141 22:10:56.155574 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5142 22:10:56.162379 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 22:10:56.165580 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 22:10:56.168827 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 22:10:56.175847 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 22:10:56.178847 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 22:10:56.182241 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5148 22:10:56.189033 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
5149 22:10:56.192319 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 22:10:56.195458 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 22:10:56.202056 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 22:10:56.205504 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 22:10:56.208989 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 22:10:56.215230 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 22:10:56.218861 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5156 22:10:56.221784 1 0 0 | B1->B0 | 3131 4444 | 0 0 | (0 0) (0 0)
5157 22:10:56.228701 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 22:10:56.231755 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 22:10:56.235134 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 22:10:56.241999 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 22:10:56.244816 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 22:10:56.248082 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 22:10:56.254898 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 22:10:56.258146 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5165 22:10:56.261630 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 22:10:56.268221 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 22:10:56.271496 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 22:10:56.274817 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 22:10:56.281401 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 22:10:56.284878 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 22:10:56.287796 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 22:10:56.294739 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 22:10:56.297827 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 22:10:56.300995 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 22:10:56.307858 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 22:10:56.310794 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 22:10:56.314426 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 22:10:56.320645 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5179 22:10:56.324188 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5180 22:10:56.327785 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5181 22:10:56.330953 Total UI for P1: 0, mck2ui 16
5182 22:10:56.333679 best dqsien dly found for B0: ( 1, 2, 26)
5183 22:10:56.340333 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 22:10:56.340407 Total UI for P1: 0, mck2ui 16
5185 22:10:56.346928 best dqsien dly found for B1: ( 1, 3, 0)
5186 22:10:56.350301 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5187 22:10:56.353738 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5188 22:10:56.353816
5189 22:10:56.356901 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5190 22:10:56.360439 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5191 22:10:56.363760 [Gating] SW calibration Done
5192 22:10:56.363835 ==
5193 22:10:56.366829 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 22:10:56.370501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 22:10:56.370636 ==
5196 22:10:56.373725 RX Vref Scan: 0
5197 22:10:56.373822
5198 22:10:56.373887 RX Vref 0 -> 0, step: 1
5199 22:10:56.373946
5200 22:10:56.376918 RX Delay -80 -> 252, step: 8
5201 22:10:56.380312 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5202 22:10:56.387072 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5203 22:10:56.389987 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5204 22:10:56.393469 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5205 22:10:56.396759 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5206 22:10:56.400157 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5207 22:10:56.403165 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5208 22:10:56.409757 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5209 22:10:56.413321 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5210 22:10:56.416842 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5211 22:10:56.420210 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5212 22:10:56.423070 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5213 22:10:56.429722 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5214 22:10:56.433008 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5215 22:10:56.436420 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5216 22:10:56.439831 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5217 22:10:56.439935 ==
5218 22:10:56.443181 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 22:10:56.449460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 22:10:56.449577 ==
5221 22:10:56.449671 DQS Delay:
5222 22:10:56.452576 DQS0 = 0, DQS1 = 0
5223 22:10:56.452684 DQM Delay:
5224 22:10:56.452776 DQM0 = 96, DQM1 = 86
5225 22:10:56.456337 DQ Delay:
5226 22:10:56.460383 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5227 22:10:56.462570 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5228 22:10:56.465870 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5229 22:10:56.469206 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5230 22:10:56.469311
5231 22:10:56.469405
5232 22:10:56.469499 ==
5233 22:10:56.472875 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 22:10:56.475877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 22:10:56.475976 ==
5236 22:10:56.476066
5237 22:10:56.476152
5238 22:10:56.479185 TX Vref Scan disable
5239 22:10:56.482432 == TX Byte 0 ==
5240 22:10:56.486261 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5241 22:10:56.489460 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5242 22:10:56.492754 == TX Byte 1 ==
5243 22:10:56.495727 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5244 22:10:56.499335 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5245 22:10:56.499412 ==
5246 22:10:56.502303 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 22:10:56.505720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 22:10:56.509217 ==
5249 22:10:56.509288
5250 22:10:56.509355
5251 22:10:56.509411 TX Vref Scan disable
5252 22:10:56.512470 == TX Byte 0 ==
5253 22:10:56.515654 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5254 22:10:56.522261 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5255 22:10:56.522342 == TX Byte 1 ==
5256 22:10:56.525700 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5257 22:10:56.532639 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5258 22:10:56.532713
5259 22:10:56.532780 [DATLAT]
5260 22:10:56.532847 Freq=933, CH0 RK0
5261 22:10:56.532906
5262 22:10:56.535455 DATLAT Default: 0xd
5263 22:10:56.535524 0, 0xFFFF, sum = 0
5264 22:10:56.538887 1, 0xFFFF, sum = 0
5265 22:10:56.542268 2, 0xFFFF, sum = 0
5266 22:10:56.542338 3, 0xFFFF, sum = 0
5267 22:10:56.545673 4, 0xFFFF, sum = 0
5268 22:10:56.545743 5, 0xFFFF, sum = 0
5269 22:10:56.548992 6, 0xFFFF, sum = 0
5270 22:10:56.549062 7, 0xFFFF, sum = 0
5271 22:10:56.552295 8, 0xFFFF, sum = 0
5272 22:10:56.552396 9, 0xFFFF, sum = 0
5273 22:10:56.555717 10, 0x0, sum = 1
5274 22:10:56.555789 11, 0x0, sum = 2
5275 22:10:56.558508 12, 0x0, sum = 3
5276 22:10:56.558629 13, 0x0, sum = 4
5277 22:10:56.558721 best_step = 11
5278 22:10:56.562336
5279 22:10:56.562448 ==
5280 22:10:56.565622 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 22:10:56.569466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 22:10:56.569553 ==
5283 22:10:56.569614 RX Vref Scan: 1
5284 22:10:56.569672
5285 22:10:56.571749 RX Vref 0 -> 0, step: 1
5286 22:10:56.571816
5287 22:10:56.575161 RX Delay -61 -> 252, step: 4
5288 22:10:56.575234
5289 22:10:56.578496 Set Vref, RX VrefLevel [Byte0]: 58
5290 22:10:56.581896 [Byte1]: 57
5291 22:10:56.585036
5292 22:10:56.585135 Final RX Vref Byte 0 = 58 to rank0
5293 22:10:56.588091 Final RX Vref Byte 1 = 57 to rank0
5294 22:10:56.591671 Final RX Vref Byte 0 = 58 to rank1
5295 22:10:56.594744 Final RX Vref Byte 1 = 57 to rank1==
5296 22:10:56.598408 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 22:10:56.604683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 22:10:56.604766 ==
5299 22:10:56.604830 DQS Delay:
5300 22:10:56.608278 DQS0 = 0, DQS1 = 0
5301 22:10:56.608354 DQM Delay:
5302 22:10:56.608417 DQM0 = 96, DQM1 = 87
5303 22:10:56.611306 DQ Delay:
5304 22:10:56.614754 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5305 22:10:56.618016 DQ4 =96, DQ5 =88, DQ6 =104, DQ7 =106
5306 22:10:56.621496 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =84
5307 22:10:56.624795 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =94
5308 22:10:56.624877
5309 22:10:56.624938
5310 22:10:56.631067 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 407 ps
5311 22:10:56.634457 CH0 RK0: MR19=505, MR18=2F16
5312 22:10:56.641071 CH0_RK0: MR19=0x505, MR18=0x2F16, DQSOSC=407, MR23=63, INC=65, DEC=43
5313 22:10:56.641151
5314 22:10:56.644528 ----->DramcWriteLeveling(PI) begin...
5315 22:10:56.644609 ==
5316 22:10:56.647529 Dram Type= 6, Freq= 0, CH_0, rank 1
5317 22:10:56.650802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 22:10:56.650906 ==
5319 22:10:56.654119 Write leveling (Byte 0): 33 => 33
5320 22:10:56.657443 Write leveling (Byte 1): 32 => 32
5321 22:10:56.660950 DramcWriteLeveling(PI) end<-----
5322 22:10:56.661056
5323 22:10:56.661146 ==
5324 22:10:56.664323 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 22:10:56.670523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 22:10:56.670660 ==
5327 22:10:56.670742 [Gating] SW mode calibration
5328 22:10:56.680378 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5329 22:10:56.683868 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5330 22:10:56.687073 0 14 0 | B1->B0 | 2828 3232 | 0 0 | (0 0) (1 1)
5331 22:10:56.693599 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 22:10:56.696897 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 22:10:56.703422 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 22:10:56.706529 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 22:10:56.710182 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 22:10:56.713598 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 22:10:56.719801 0 14 28 | B1->B0 | 3333 2c2c | 1 0 | (1 1) (1 0)
5338 22:10:56.723180 0 15 0 | B1->B0 | 2f2f 2525 | 0 0 | (0 1) (0 0)
5339 22:10:56.726397 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5340 22:10:56.733174 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 22:10:56.736398 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 22:10:56.740109 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 22:10:56.746758 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 22:10:56.749665 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 22:10:56.753121 0 15 28 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
5346 22:10:56.759768 1 0 0 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
5347 22:10:56.762905 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 22:10:56.766417 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 22:10:56.772711 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 22:10:56.775876 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 22:10:56.779231 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 22:10:56.786097 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 22:10:56.789339 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 22:10:56.792527 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5355 22:10:56.799568 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 22:10:56.802400 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 22:10:56.806051 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 22:10:56.812271 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 22:10:56.815841 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 22:10:56.819457 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 22:10:56.825639 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 22:10:56.828997 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 22:10:56.832499 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 22:10:56.838922 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 22:10:56.841949 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 22:10:56.845380 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 22:10:56.852033 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 22:10:56.855268 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 22:10:56.858713 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 22:10:56.865146 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 22:10:56.868259 Total UI for P1: 0, mck2ui 16
5372 22:10:56.871607 best dqsien dly found for B0: ( 1, 2, 30)
5373 22:10:56.875120 Total UI for P1: 0, mck2ui 16
5374 22:10:56.878499 best dqsien dly found for B1: ( 1, 2, 30)
5375 22:10:56.882239 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5376 22:10:56.885245 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5377 22:10:56.885328
5378 22:10:56.888030 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5379 22:10:56.891497 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5380 22:10:56.895123 [Gating] SW calibration Done
5381 22:10:56.895206 ==
5382 22:10:56.898425 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 22:10:56.901576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 22:10:56.901659 ==
5385 22:10:56.904582 RX Vref Scan: 0
5386 22:10:56.904664
5387 22:10:56.907850 RX Vref 0 -> 0, step: 1
5388 22:10:56.907932
5389 22:10:56.907997 RX Delay -80 -> 252, step: 8
5390 22:10:56.914496 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5391 22:10:56.917799 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5392 22:10:56.921399 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5393 22:10:56.924669 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5394 22:10:56.928256 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5395 22:10:56.931374 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5396 22:10:56.938157 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5397 22:10:56.941766 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5398 22:10:56.944479 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5399 22:10:56.951276 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5400 22:10:56.951359 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5401 22:10:56.957528 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5402 22:10:56.960729 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5403 22:10:56.964667 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5404 22:10:56.967553 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5405 22:10:56.971071 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5406 22:10:56.971153 ==
5407 22:10:56.974148 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 22:10:56.980747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 22:10:56.980831 ==
5410 22:10:56.980895 DQS Delay:
5411 22:10:56.984020 DQS0 = 0, DQS1 = 0
5412 22:10:56.984103 DQM Delay:
5413 22:10:56.984168 DQM0 = 97, DQM1 = 89
5414 22:10:56.987266 DQ Delay:
5415 22:10:56.990635 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5416 22:10:56.994151 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5417 22:10:56.997411 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5418 22:10:57.000392 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5419 22:10:57.000473
5420 22:10:57.000536
5421 22:10:57.000596 ==
5422 22:10:57.003778 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 22:10:57.007126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 22:10:57.007207 ==
5425 22:10:57.007271
5426 22:10:57.007330
5427 22:10:57.010599 TX Vref Scan disable
5428 22:10:57.013683 == TX Byte 0 ==
5429 22:10:57.017248 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5430 22:10:57.020344 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5431 22:10:57.023624 == TX Byte 1 ==
5432 22:10:57.027098 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5433 22:10:57.030580 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5434 22:10:57.030700 ==
5435 22:10:57.033518 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 22:10:57.036841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 22:10:57.040164 ==
5438 22:10:57.040270
5439 22:10:57.040361
5440 22:10:57.040449 TX Vref Scan disable
5441 22:10:57.043722 == TX Byte 0 ==
5442 22:10:57.047041 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5443 22:10:57.053463 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5444 22:10:57.053574 == TX Byte 1 ==
5445 22:10:57.056862 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5446 22:10:57.063582 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5447 22:10:57.063664
5448 22:10:57.063728 [DATLAT]
5449 22:10:57.063787 Freq=933, CH0 RK1
5450 22:10:57.063871
5451 22:10:57.067003 DATLAT Default: 0xb
5452 22:10:57.067083 0, 0xFFFF, sum = 0
5453 22:10:57.070243 1, 0xFFFF, sum = 0
5454 22:10:57.073569 2, 0xFFFF, sum = 0
5455 22:10:57.073651 3, 0xFFFF, sum = 0
5456 22:10:57.076830 4, 0xFFFF, sum = 0
5457 22:10:57.076913 5, 0xFFFF, sum = 0
5458 22:10:57.080098 6, 0xFFFF, sum = 0
5459 22:10:57.080180 7, 0xFFFF, sum = 0
5460 22:10:57.083447 8, 0xFFFF, sum = 0
5461 22:10:57.083529 9, 0xFFFF, sum = 0
5462 22:10:57.086606 10, 0x0, sum = 1
5463 22:10:57.086703 11, 0x0, sum = 2
5464 22:10:57.089799 12, 0x0, sum = 3
5465 22:10:57.089881 13, 0x0, sum = 4
5466 22:10:57.089977 best_step = 11
5467 22:10:57.093062
5468 22:10:57.093159 ==
5469 22:10:57.096453 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 22:10:57.099706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 22:10:57.099787 ==
5472 22:10:57.099876 RX Vref Scan: 0
5473 22:10:57.099967
5474 22:10:57.103201 RX Vref 0 -> 0, step: 1
5475 22:10:57.103281
5476 22:10:57.106840 RX Delay -61 -> 252, step: 4
5477 22:10:57.112977 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5478 22:10:57.116322 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5479 22:10:57.119492 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5480 22:10:57.122932 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5481 22:10:57.126203 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5482 22:10:57.129478 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5483 22:10:57.136187 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5484 22:10:57.139673 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5485 22:10:57.142685 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5486 22:10:57.145890 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5487 22:10:57.149555 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5488 22:10:57.156317 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5489 22:10:57.159179 iDelay=203, Bit 12, Center 92 (-5 ~ 190) 196
5490 22:10:57.162432 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5491 22:10:57.165798 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5492 22:10:57.169502 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5493 22:10:57.169610 ==
5494 22:10:57.172504 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 22:10:57.178956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 22:10:57.179062 ==
5497 22:10:57.179161 DQS Delay:
5498 22:10:57.182266 DQS0 = 0, DQS1 = 0
5499 22:10:57.182340 DQM Delay:
5500 22:10:57.182402 DQM0 = 95, DQM1 = 88
5501 22:10:57.185957 DQ Delay:
5502 22:10:57.189175 DQ0 =94, DQ1 =96, DQ2 =90, DQ3 =94
5503 22:10:57.192518 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5504 22:10:57.195679 DQ8 =82, DQ9 =78, DQ10 =90, DQ11 =82
5505 22:10:57.199002 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5506 22:10:57.199102
5507 22:10:57.199205
5508 22:10:57.205726 [DQSOSCAuto] RK1, (LSB)MR18= 0x27f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5509 22:10:57.209169 CH0 RK1: MR19=504, MR18=27F6
5510 22:10:57.215592 CH0_RK1: MR19=0x504, MR18=0x27F6, DQSOSC=409, MR23=63, INC=64, DEC=43
5511 22:10:57.218815 [RxdqsGatingPostProcess] freq 933
5512 22:10:57.222186 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5513 22:10:57.225252 best DQS0 dly(2T, 0.5T) = (0, 10)
5514 22:10:57.228655 best DQS1 dly(2T, 0.5T) = (0, 11)
5515 22:10:57.231818 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5516 22:10:57.235221 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5517 22:10:57.238733 best DQS0 dly(2T, 0.5T) = (0, 10)
5518 22:10:57.241969 best DQS1 dly(2T, 0.5T) = (0, 10)
5519 22:10:57.245192 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5520 22:10:57.248426 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5521 22:10:57.251729 Pre-setting of DQS Precalculation
5522 22:10:57.258270 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5523 22:10:57.258369 ==
5524 22:10:57.261461 Dram Type= 6, Freq= 0, CH_1, rank 0
5525 22:10:57.264936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 22:10:57.265039 ==
5527 22:10:57.271451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5528 22:10:57.274904 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5529 22:10:57.278516 [CA 0] Center 36 (6~67) winsize 62
5530 22:10:57.282216 [CA 1] Center 36 (6~67) winsize 62
5531 22:10:57.285308 [CA 2] Center 34 (4~65) winsize 62
5532 22:10:57.288782 [CA 3] Center 33 (3~64) winsize 62
5533 22:10:57.292192 [CA 4] Center 34 (4~64) winsize 61
5534 22:10:57.295171 [CA 5] Center 33 (3~64) winsize 62
5535 22:10:57.295248
5536 22:10:57.298722 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5537 22:10:57.298794
5538 22:10:57.301723 [CATrainingPosCal] consider 1 rank data
5539 22:10:57.305090 u2DelayCellTimex100 = 270/100 ps
5540 22:10:57.308317 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5541 22:10:57.315053 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5542 22:10:57.318414 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5543 22:10:57.321760 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5544 22:10:57.325165 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5545 22:10:57.328048 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5546 22:10:57.328145
5547 22:10:57.331372 CA PerBit enable=1, Macro0, CA PI delay=33
5548 22:10:57.331453
5549 22:10:57.334617 [CBTSetCACLKResult] CA Dly = 33
5550 22:10:57.337907 CS Dly: 6 (0~37)
5551 22:10:57.338004 ==
5552 22:10:57.341082 Dram Type= 6, Freq= 0, CH_1, rank 1
5553 22:10:57.344684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 22:10:57.344790 ==
5555 22:10:57.351343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5556 22:10:57.354296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5557 22:10:57.359122 [CA 0] Center 36 (6~67) winsize 62
5558 22:10:57.361882 [CA 1] Center 37 (7~67) winsize 61
5559 22:10:57.365455 [CA 2] Center 34 (4~65) winsize 62
5560 22:10:57.368305 [CA 3] Center 33 (3~64) winsize 62
5561 22:10:57.371667 [CA 4] Center 34 (3~65) winsize 63
5562 22:10:57.375098 [CA 5] Center 33 (3~64) winsize 62
5563 22:10:57.375179
5564 22:10:57.378479 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5565 22:10:57.378560
5566 22:10:57.381690 [CATrainingPosCal] consider 2 rank data
5567 22:10:57.385072 u2DelayCellTimex100 = 270/100 ps
5568 22:10:57.391442 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5569 22:10:57.394918 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5570 22:10:57.397954 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5571 22:10:57.401566 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5572 22:10:57.405201 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5573 22:10:57.407908 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5574 22:10:57.407988
5575 22:10:57.411289 CA PerBit enable=1, Macro0, CA PI delay=33
5576 22:10:57.411414
5577 22:10:57.414770 [CBTSetCACLKResult] CA Dly = 33
5578 22:10:57.418057 CS Dly: 7 (0~39)
5579 22:10:57.418137
5580 22:10:57.421342 ----->DramcWriteLeveling(PI) begin...
5581 22:10:57.421424 ==
5582 22:10:57.424423 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 22:10:57.428177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 22:10:57.428259 ==
5585 22:10:57.430915 Write leveling (Byte 0): 24 => 24
5586 22:10:57.434411 Write leveling (Byte 1): 25 => 25
5587 22:10:57.437889 DramcWriteLeveling(PI) end<-----
5588 22:10:57.437987
5589 22:10:57.438082 ==
5590 22:10:57.441158 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 22:10:57.444167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 22:10:57.444265 ==
5593 22:10:57.447600 [Gating] SW mode calibration
5594 22:10:57.454268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5595 22:10:57.460743 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5596 22:10:57.463821 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 22:10:57.470553 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 22:10:57.473951 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 22:10:57.477616 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 22:10:57.484103 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 22:10:57.486922 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5602 22:10:57.490384 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5603 22:10:57.496774 0 14 28 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (0 0)
5604 22:10:57.500321 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
5605 22:10:57.503797 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 22:10:57.506916 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 22:10:57.513837 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 22:10:57.517006 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 22:10:57.520046 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 22:10:57.526575 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5611 22:10:57.529848 0 15 28 | B1->B0 | 3535 3939 | 0 0 | (0 0) (0 0)
5612 22:10:57.533687 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 22:10:57.539958 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 22:10:57.543098 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 22:10:57.546430 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 22:10:57.553123 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 22:10:57.556918 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 22:10:57.560170 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 22:10:57.566429 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5620 22:10:57.569723 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5621 22:10:57.573145 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 22:10:57.579354 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 22:10:57.582967 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 22:10:57.586410 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 22:10:57.592749 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 22:10:57.596040 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 22:10:57.599792 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 22:10:57.605895 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 22:10:57.609304 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 22:10:57.612388 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 22:10:57.619047 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 22:10:57.622326 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 22:10:57.625623 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5634 22:10:57.632775 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5635 22:10:57.635615 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5636 22:10:57.639048 Total UI for P1: 0, mck2ui 16
5637 22:10:57.642072 best dqsien dly found for B0: ( 1, 2, 22)
5638 22:10:57.645341 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 22:10:57.648803 Total UI for P1: 0, mck2ui 16
5640 22:10:57.652517 best dqsien dly found for B1: ( 1, 2, 28)
5641 22:10:57.655487 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5642 22:10:57.658628 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5643 22:10:57.662126
5644 22:10:57.665277 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5645 22:10:57.668568 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5646 22:10:57.671983 [Gating] SW calibration Done
5647 22:10:57.672065 ==
5648 22:10:57.675555 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 22:10:57.679216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 22:10:57.679297 ==
5651 22:10:57.679361 RX Vref Scan: 0
5652 22:10:57.682115
5653 22:10:57.682195 RX Vref 0 -> 0, step: 1
5654 22:10:57.682276
5655 22:10:57.685216 RX Delay -80 -> 252, step: 8
5656 22:10:57.688637 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5657 22:10:57.692135 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5658 22:10:57.698420 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5659 22:10:57.701984 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5660 22:10:57.704839 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5661 22:10:57.708460 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5662 22:10:57.711766 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5663 22:10:57.714552 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5664 22:10:57.721674 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5665 22:10:57.724898 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5666 22:10:57.728247 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5667 22:10:57.731661 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5668 22:10:57.734494 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5669 22:10:57.741362 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5670 22:10:57.744887 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5671 22:10:57.747802 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5672 22:10:57.747883 ==
5673 22:10:57.751025 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 22:10:57.754325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 22:10:57.754407 ==
5676 22:10:57.757516 DQS Delay:
5677 22:10:57.757597 DQS0 = 0, DQS1 = 0
5678 22:10:57.761344 DQM Delay:
5679 22:10:57.761425 DQM0 = 100, DQM1 = 91
5680 22:10:57.761489 DQ Delay:
5681 22:10:57.764360 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =95
5682 22:10:57.767543 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5683 22:10:57.770981 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5684 22:10:57.774611 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5685 22:10:57.774708
5686 22:10:57.777732
5687 22:10:57.777812 ==
5688 22:10:57.781059 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 22:10:57.784386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 22:10:57.784472 ==
5691 22:10:57.784537
5692 22:10:57.784597
5693 22:10:57.787849 TX Vref Scan disable
5694 22:10:57.787931 == TX Byte 0 ==
5695 22:10:57.794289 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5696 22:10:57.797477 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5697 22:10:57.797559 == TX Byte 1 ==
5698 22:10:57.803827 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5699 22:10:57.807190 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5700 22:10:57.807272 ==
5701 22:10:57.810857 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 22:10:57.814064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 22:10:57.814146 ==
5704 22:10:57.814210
5705 22:10:57.814269
5706 22:10:57.817294 TX Vref Scan disable
5707 22:10:57.820552 == TX Byte 0 ==
5708 22:10:57.823759 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5709 22:10:57.827262 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5710 22:10:57.830389 == TX Byte 1 ==
5711 22:10:57.833806 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5712 22:10:57.836835 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5713 22:10:57.836916
5714 22:10:57.840574 [DATLAT]
5715 22:10:57.840655 Freq=933, CH1 RK0
5716 22:10:57.840720
5717 22:10:57.843955 DATLAT Default: 0xd
5718 22:10:57.844036 0, 0xFFFF, sum = 0
5719 22:10:57.847201 1, 0xFFFF, sum = 0
5720 22:10:57.847284 2, 0xFFFF, sum = 0
5721 22:10:57.850011 3, 0xFFFF, sum = 0
5722 22:10:57.850094 4, 0xFFFF, sum = 0
5723 22:10:57.853207 5, 0xFFFF, sum = 0
5724 22:10:57.853289 6, 0xFFFF, sum = 0
5725 22:10:57.856830 7, 0xFFFF, sum = 0
5726 22:10:57.859994 8, 0xFFFF, sum = 0
5727 22:10:57.860077 9, 0xFFFF, sum = 0
5728 22:10:57.863609 10, 0x0, sum = 1
5729 22:10:57.863692 11, 0x0, sum = 2
5730 22:10:57.863757 12, 0x0, sum = 3
5731 22:10:57.866846 13, 0x0, sum = 4
5732 22:10:57.866929 best_step = 11
5733 22:10:57.867067
5734 22:10:57.867155 ==
5735 22:10:57.869785 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 22:10:57.876695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 22:10:57.876778 ==
5738 22:10:57.876842 RX Vref Scan: 1
5739 22:10:57.876901
5740 22:10:57.879832 RX Vref 0 -> 0, step: 1
5741 22:10:57.879913
5742 22:10:57.883311 RX Delay -61 -> 252, step: 4
5743 22:10:57.883392
5744 22:10:57.886224 Set Vref, RX VrefLevel [Byte0]: 50
5745 22:10:57.889586 [Byte1]: 52
5746 22:10:57.889667
5747 22:10:57.892849 Final RX Vref Byte 0 = 50 to rank0
5748 22:10:57.896420 Final RX Vref Byte 1 = 52 to rank0
5749 22:10:57.899948 Final RX Vref Byte 0 = 50 to rank1
5750 22:10:57.903143 Final RX Vref Byte 1 = 52 to rank1==
5751 22:10:57.906313 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 22:10:57.909355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 22:10:57.909437 ==
5754 22:10:57.912772 DQS Delay:
5755 22:10:57.912854 DQS0 = 0, DQS1 = 0
5756 22:10:57.916371 DQM Delay:
5757 22:10:57.916470 DQM0 = 101, DQM1 = 93
5758 22:10:57.919949 DQ Delay:
5759 22:10:57.922738 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5760 22:10:57.922819 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5761 22:10:57.926254 DQ8 =82, DQ9 =88, DQ10 =94, DQ11 =82
5762 22:10:57.932611 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =102
5763 22:10:57.932693
5764 22:10:57.932757
5765 22:10:57.939462 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5766 22:10:57.942833 CH1 RK0: MR19=505, MR18=1E0E
5767 22:10:57.949423 CH1_RK0: MR19=0x505, MR18=0x1E0E, DQSOSC=412, MR23=63, INC=63, DEC=42
5768 22:10:57.949505
5769 22:10:57.952158 ----->DramcWriteLeveling(PI) begin...
5770 22:10:57.952242 ==
5771 22:10:57.955512 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 22:10:57.958846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 22:10:57.958929 ==
5774 22:10:57.963297 Write leveling (Byte 0): 29 => 29
5775 22:10:57.965619 Write leveling (Byte 1): 30 => 30
5776 22:10:57.968782 DramcWriteLeveling(PI) end<-----
5777 22:10:57.968890
5778 22:10:57.968982 ==
5779 22:10:57.972549 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 22:10:57.975638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 22:10:57.978708 ==
5782 22:10:57.978816 [Gating] SW mode calibration
5783 22:10:57.985358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5784 22:10:57.991688 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5785 22:10:57.994985 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5786 22:10:58.001679 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 22:10:58.005121 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 22:10:58.008528 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 22:10:58.015216 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 22:10:58.018256 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5791 22:10:58.021769 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5792 22:10:58.028161 0 14 28 | B1->B0 | 2727 2e2e | 0 0 | (1 1) (0 1)
5793 22:10:58.031313 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5794 22:10:58.034615 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 22:10:58.041357 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 22:10:58.044746 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 22:10:58.048131 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 22:10:58.054454 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 22:10:58.057907 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5800 22:10:58.061224 0 15 28 | B1->B0 | 3c3b 3434 | 1 0 | (0 0) (0 0)
5801 22:10:58.067719 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 22:10:58.071096 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 22:10:58.074520 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 22:10:58.080784 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 22:10:58.084152 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 22:10:58.087439 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 22:10:58.094192 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 22:10:58.097451 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5809 22:10:58.100807 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 22:10:58.107616 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 22:10:58.110772 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 22:10:58.114063 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 22:10:58.121028 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 22:10:58.124258 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 22:10:58.127471 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 22:10:58.134211 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 22:10:58.137253 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 22:10:58.140321 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 22:10:58.147096 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 22:10:58.150250 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 22:10:58.153559 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 22:10:58.160719 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 22:10:58.163560 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5824 22:10:58.167015 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5825 22:10:58.173361 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 22:10:58.173440 Total UI for P1: 0, mck2ui 16
5827 22:10:58.179979 best dqsien dly found for B0: ( 1, 2, 28)
5828 22:10:58.180051 Total UI for P1: 0, mck2ui 16
5829 22:10:58.186797 best dqsien dly found for B1: ( 1, 2, 26)
5830 22:10:58.189868 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5831 22:10:58.193143 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5832 22:10:58.193257
5833 22:10:58.196704 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5834 22:10:58.200092 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5835 22:10:58.203045 [Gating] SW calibration Done
5836 22:10:58.203148 ==
5837 22:10:58.206545 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 22:10:58.210257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 22:10:58.210717 ==
5840 22:10:58.213393 RX Vref Scan: 0
5841 22:10:58.213807
5842 22:10:58.214135 RX Vref 0 -> 0, step: 1
5843 22:10:58.214440
5844 22:10:58.216653 RX Delay -80 -> 252, step: 8
5845 22:10:58.223340 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5846 22:10:58.226815 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5847 22:10:58.229926 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5848 22:10:58.233687 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5849 22:10:58.236822 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5850 22:10:58.239675 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5851 22:10:58.246980 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5852 22:10:58.250100 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5853 22:10:58.252830 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5854 22:10:58.256118 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5855 22:10:58.260170 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5856 22:10:58.263036 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5857 22:10:58.269436 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5858 22:10:58.272910 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5859 22:10:58.275827 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5860 22:10:58.279436 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5861 22:10:58.279984 ==
5862 22:10:58.282295 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 22:10:58.289022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 22:10:58.289572 ==
5865 22:10:58.290044 DQS Delay:
5866 22:10:58.290497 DQS0 = 0, DQS1 = 0
5867 22:10:58.292404 DQM Delay:
5868 22:10:58.292960 DQM0 = 99, DQM1 = 91
5869 22:10:58.295624 DQ Delay:
5870 22:10:58.298899 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =95
5871 22:10:58.302338 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5872 22:10:58.306033 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5873 22:10:58.308916 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5874 22:10:58.309464
5875 22:10:58.309947
5876 22:10:58.310435 ==
5877 22:10:58.312677 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 22:10:58.315890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 22:10:58.316521 ==
5880 22:10:58.317075
5881 22:10:58.317649
5882 22:10:58.318619 TX Vref Scan disable
5883 22:10:58.319213 == TX Byte 0 ==
5884 22:10:58.325456 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5885 22:10:58.329098 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5886 22:10:58.329517 == TX Byte 1 ==
5887 22:10:58.335224 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5888 22:10:58.338562 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5889 22:10:58.339147 ==
5890 22:10:58.342299 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 22:10:58.345492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 22:10:58.345917 ==
5893 22:10:58.348898
5894 22:10:58.349315
5895 22:10:58.349641 TX Vref Scan disable
5896 22:10:58.351639 == TX Byte 0 ==
5897 22:10:58.355514 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5898 22:10:58.361565 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5899 22:10:58.361992 == TX Byte 1 ==
5900 22:10:58.365131 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5901 22:10:58.371741 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5902 22:10:58.372223
5903 22:10:58.372557 [DATLAT]
5904 22:10:58.372864 Freq=933, CH1 RK1
5905 22:10:58.373161
5906 22:10:58.374721 DATLAT Default: 0xb
5907 22:10:58.377985 0, 0xFFFF, sum = 0
5908 22:10:58.378519 1, 0xFFFF, sum = 0
5909 22:10:58.381645 2, 0xFFFF, sum = 0
5910 22:10:58.382115 3, 0xFFFF, sum = 0
5911 22:10:58.384496 4, 0xFFFF, sum = 0
5912 22:10:58.385044 5, 0xFFFF, sum = 0
5913 22:10:58.388050 6, 0xFFFF, sum = 0
5914 22:10:58.388605 7, 0xFFFF, sum = 0
5915 22:10:58.391248 8, 0xFFFF, sum = 0
5916 22:10:58.391808 9, 0xFFFF, sum = 0
5917 22:10:58.394659 10, 0x0, sum = 1
5918 22:10:58.395085 11, 0x0, sum = 2
5919 22:10:58.397973 12, 0x0, sum = 3
5920 22:10:58.398556 13, 0x0, sum = 4
5921 22:10:58.401440 best_step = 11
5922 22:10:58.402002
5923 22:10:58.402490 ==
5924 22:10:58.404313 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 22:10:58.407584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 22:10:58.408175 ==
5927 22:10:58.408686 RX Vref Scan: 0
5928 22:10:58.410966
5929 22:10:58.411502 RX Vref 0 -> 0, step: 1
5930 22:10:58.411986
5931 22:10:58.414346 RX Delay -61 -> 252, step: 4
5932 22:10:58.420799 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5933 22:10:58.424941 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5934 22:10:58.427955 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5935 22:10:58.431717 iDelay=207, Bit 3, Center 96 (11 ~ 182) 172
5936 22:10:58.434573 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5937 22:10:58.440657 iDelay=207, Bit 5, Center 110 (19 ~ 202) 184
5938 22:10:58.444141 iDelay=207, Bit 6, Center 112 (19 ~ 206) 188
5939 22:10:58.447321 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
5940 22:10:58.450638 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5941 22:10:58.454288 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5942 22:10:58.457630 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5943 22:10:58.464095 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5944 22:10:58.467354 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5945 22:10:58.470761 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
5946 22:10:58.474166 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5947 22:10:58.477440 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5948 22:10:58.480673 ==
5949 22:10:58.483703 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 22:10:58.487220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 22:10:58.487648 ==
5952 22:10:58.488171 DQS Delay:
5953 22:10:58.490462 DQS0 = 0, DQS1 = 0
5954 22:10:58.491062 DQM Delay:
5955 22:10:58.493562 DQM0 = 100, DQM1 = 94
5956 22:10:58.494070 DQ Delay:
5957 22:10:58.497084 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =96
5958 22:10:58.500369 DQ4 =98, DQ5 =110, DQ6 =112, DQ7 =96
5959 22:10:58.503406 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
5960 22:10:58.506722 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5961 22:10:58.507144
5962 22:10:58.507475
5963 22:10:58.517043 [DQSOSCAuto] RK1, (LSB)MR18= 0x700, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 419 ps
5964 22:10:58.517553 CH1 RK1: MR19=505, MR18=700
5965 22:10:58.523653 CH1_RK1: MR19=0x505, MR18=0x700, DQSOSC=419, MR23=63, INC=61, DEC=41
5966 22:10:58.526532 [RxdqsGatingPostProcess] freq 933
5967 22:10:58.533793 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5968 22:10:58.536582 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 22:10:58.539965 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 22:10:58.543651 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 22:10:58.546657 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 22:10:58.547109 best DQS0 dly(2T, 0.5T) = (0, 10)
5973 22:10:58.550142 best DQS1 dly(2T, 0.5T) = (0, 10)
5974 22:10:58.552938 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5975 22:10:58.556276 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5976 22:10:58.559645 Pre-setting of DQS Precalculation
5977 22:10:58.566736 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5978 22:10:58.572821 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5979 22:10:58.579229 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5980 22:10:58.579647
5981 22:10:58.579971
5982 22:10:58.582536 [Calibration Summary] 1866 Mbps
5983 22:10:58.586003 CH 0, Rank 0
5984 22:10:58.586429 SW Impedance : PASS
5985 22:10:58.589403 DUTY Scan : NO K
5986 22:10:58.589888 ZQ Calibration : PASS
5987 22:10:58.592328 Jitter Meter : NO K
5988 22:10:58.595855 CBT Training : PASS
5989 22:10:58.596414 Write leveling : PASS
5990 22:10:58.599076 RX DQS gating : PASS
5991 22:10:58.602847 RX DQ/DQS(RDDQC) : PASS
5992 22:10:58.603260 TX DQ/DQS : PASS
5993 22:10:58.605457 RX DATLAT : PASS
5994 22:10:58.609580 RX DQ/DQS(Engine): PASS
5995 22:10:58.610103 TX OE : NO K
5996 22:10:58.612252 All Pass.
5997 22:10:58.612663
5998 22:10:58.612986 CH 0, Rank 1
5999 22:10:58.615675 SW Impedance : PASS
6000 22:10:58.616114 DUTY Scan : NO K
6001 22:10:58.619113 ZQ Calibration : PASS
6002 22:10:58.622295 Jitter Meter : NO K
6003 22:10:58.622908 CBT Training : PASS
6004 22:10:58.625719 Write leveling : PASS
6005 22:10:58.628861 RX DQS gating : PASS
6006 22:10:58.629417 RX DQ/DQS(RDDQC) : PASS
6007 22:10:58.632182 TX DQ/DQS : PASS
6008 22:10:58.635541 RX DATLAT : PASS
6009 22:10:58.635954 RX DQ/DQS(Engine): PASS
6010 22:10:58.638763 TX OE : NO K
6011 22:10:58.639180 All Pass.
6012 22:10:58.639508
6013 22:10:58.642181 CH 1, Rank 0
6014 22:10:58.642618 SW Impedance : PASS
6015 22:10:58.645529 DUTY Scan : NO K
6016 22:10:58.648532 ZQ Calibration : PASS
6017 22:10:58.648948 Jitter Meter : NO K
6018 22:10:58.652252 CBT Training : PASS
6019 22:10:58.655529 Write leveling : PASS
6020 22:10:58.655942 RX DQS gating : PASS
6021 22:10:58.658682 RX DQ/DQS(RDDQC) : PASS
6022 22:10:58.659096 TX DQ/DQS : PASS
6023 22:10:58.661892 RX DATLAT : PASS
6024 22:10:58.665318 RX DQ/DQS(Engine): PASS
6025 22:10:58.665754 TX OE : NO K
6026 22:10:58.668553 All Pass.
6027 22:10:58.668969
6028 22:10:58.669294 CH 1, Rank 1
6029 22:10:58.671588 SW Impedance : PASS
6030 22:10:58.672179 DUTY Scan : NO K
6031 22:10:58.675176 ZQ Calibration : PASS
6032 22:10:58.678496 Jitter Meter : NO K
6033 22:10:58.678958 CBT Training : PASS
6034 22:10:58.681745 Write leveling : PASS
6035 22:10:58.684847 RX DQS gating : PASS
6036 22:10:58.685264 RX DQ/DQS(RDDQC) : PASS
6037 22:10:58.688367 TX DQ/DQS : PASS
6038 22:10:58.691613 RX DATLAT : PASS
6039 22:10:58.692027 RX DQ/DQS(Engine): PASS
6040 22:10:58.694768 TX OE : NO K
6041 22:10:58.695357 All Pass.
6042 22:10:58.695899
6043 22:10:58.698121 DramC Write-DBI off
6044 22:10:58.701207 PER_BANK_REFRESH: Hybrid Mode
6045 22:10:58.701825 TX_TRACKING: ON
6046 22:10:58.711422 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6047 22:10:58.714400 [FAST_K] Save calibration result to emmc
6048 22:10:58.718044 dramc_set_vcore_voltage set vcore to 650000
6049 22:10:58.721001 Read voltage for 400, 6
6050 22:10:58.721428 Vio18 = 0
6051 22:10:58.721807 Vcore = 650000
6052 22:10:58.724536 Vdram = 0
6053 22:10:58.724951 Vddq = 0
6054 22:10:58.725276 Vmddr = 0
6055 22:10:58.731454 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6056 22:10:58.734198 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6057 22:10:58.737439 MEM_TYPE=3, freq_sel=20
6058 22:10:58.741298 sv_algorithm_assistance_LP4_800
6059 22:10:58.744565 ============ PULL DRAM RESETB DOWN ============
6060 22:10:58.750832 ========== PULL DRAM RESETB DOWN end =========
6061 22:10:58.754023 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6062 22:10:58.757395 ===================================
6063 22:10:58.761150 LPDDR4 DRAM CONFIGURATION
6064 22:10:58.764455 ===================================
6065 22:10:58.764871 EX_ROW_EN[0] = 0x0
6066 22:10:58.767779 EX_ROW_EN[1] = 0x0
6067 22:10:58.768214 LP4Y_EN = 0x0
6068 22:10:58.770553 WORK_FSP = 0x0
6069 22:10:58.771012 WL = 0x2
6070 22:10:58.774220 RL = 0x2
6071 22:10:58.774671 BL = 0x2
6072 22:10:58.777316 RPST = 0x0
6073 22:10:58.777761 RD_PRE = 0x0
6074 22:10:58.780733 WR_PRE = 0x1
6075 22:10:58.781167 WR_PST = 0x0
6076 22:10:58.783805 DBI_WR = 0x0
6077 22:10:58.787422 DBI_RD = 0x0
6078 22:10:58.787858 OTF = 0x1
6079 22:10:58.790871 ===================================
6080 22:10:58.794678 ===================================
6081 22:10:58.795109 ANA top config
6082 22:10:58.797203 ===================================
6083 22:10:58.800639 DLL_ASYNC_EN = 0
6084 22:10:58.803786 ALL_SLAVE_EN = 1
6085 22:10:58.807234 NEW_RANK_MODE = 1
6086 22:10:58.810742 DLL_IDLE_MODE = 1
6087 22:10:58.811157 LP45_APHY_COMB_EN = 1
6088 22:10:58.813718 TX_ODT_DIS = 1
6089 22:10:58.816778 NEW_8X_MODE = 1
6090 22:10:58.820150 ===================================
6091 22:10:58.823106 ===================================
6092 22:10:58.826525 data_rate = 800
6093 22:10:58.830267 CKR = 1
6094 22:10:58.833389 DQ_P2S_RATIO = 4
6095 22:10:58.836696 ===================================
6096 22:10:58.837115 CA_P2S_RATIO = 4
6097 22:10:58.839913 DQ_CA_OPEN = 0
6098 22:10:58.843483 DQ_SEMI_OPEN = 1
6099 22:10:58.846761 CA_SEMI_OPEN = 1
6100 22:10:58.850329 CA_FULL_RATE = 0
6101 22:10:58.853795 DQ_CKDIV4_EN = 0
6102 22:10:58.854317 CA_CKDIV4_EN = 1
6103 22:10:58.856633 CA_PREDIV_EN = 0
6104 22:10:58.860061 PH8_DLY = 0
6105 22:10:58.863389 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6106 22:10:58.866566 DQ_AAMCK_DIV = 0
6107 22:10:58.870102 CA_AAMCK_DIV = 0
6108 22:10:58.870707 CA_ADMCK_DIV = 4
6109 22:10:58.872874 DQ_TRACK_CA_EN = 0
6110 22:10:58.876349 CA_PICK = 800
6111 22:10:58.880219 CA_MCKIO = 400
6112 22:10:58.882778 MCKIO_SEMI = 400
6113 22:10:58.886450 PLL_FREQ = 3016
6114 22:10:58.889261 DQ_UI_PI_RATIO = 32
6115 22:10:58.892930 CA_UI_PI_RATIO = 32
6116 22:10:58.895877 ===================================
6117 22:10:58.899349 ===================================
6118 22:10:58.899812 memory_type:LPDDR4
6119 22:10:58.902681 GP_NUM : 10
6120 22:10:58.906065 SRAM_EN : 1
6121 22:10:58.906523 MD32_EN : 0
6122 22:10:58.909324 ===================================
6123 22:10:58.912668 [ANA_INIT] >>>>>>>>>>>>>>
6124 22:10:58.915836 <<<<<< [CONFIGURE PHASE]: ANA_TX
6125 22:10:58.919329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6126 22:10:58.922274 ===================================
6127 22:10:58.926020 data_rate = 800,PCW = 0X7400
6128 22:10:58.929216 ===================================
6129 22:10:58.932366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6130 22:10:58.935388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 22:10:58.948916 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6132 22:10:58.952426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6133 22:10:58.955068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6134 22:10:58.958452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6135 22:10:58.961997 [ANA_INIT] flow start
6136 22:10:58.965363 [ANA_INIT] PLL >>>>>>>>
6137 22:10:58.965919 [ANA_INIT] PLL <<<<<<<<
6138 22:10:58.968865 [ANA_INIT] MIDPI >>>>>>>>
6139 22:10:58.972028 [ANA_INIT] MIDPI <<<<<<<<
6140 22:10:58.972465 [ANA_INIT] DLL >>>>>>>>
6141 22:10:58.975459 [ANA_INIT] flow end
6142 22:10:58.978564 ============ LP4 DIFF to SE enter ============
6143 22:10:58.981942 ============ LP4 DIFF to SE exit ============
6144 22:10:58.984942 [ANA_INIT] <<<<<<<<<<<<<
6145 22:10:58.988440 [Flow] Enable top DCM control >>>>>
6146 22:10:58.991698 [Flow] Enable top DCM control <<<<<
6147 22:10:58.995014 Enable DLL master slave shuffle
6148 22:10:59.001333 ==============================================================
6149 22:10:59.001770 Gating Mode config
6150 22:10:59.008039 ==============================================================
6151 22:10:59.011136 Config description:
6152 22:10:59.017764 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6153 22:10:59.024368 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6154 22:10:59.030900 SELPH_MODE 0: By rank 1: By Phase
6155 22:10:59.037401 ==============================================================
6156 22:10:59.037512 GAT_TRACK_EN = 0
6157 22:10:59.040945 RX_GATING_MODE = 2
6158 22:10:59.044394 RX_GATING_TRACK_MODE = 2
6159 22:10:59.047632 SELPH_MODE = 1
6160 22:10:59.050891 PICG_EARLY_EN = 1
6161 22:10:59.054169 VALID_LAT_VALUE = 1
6162 22:10:59.060714 ==============================================================
6163 22:10:59.064030 Enter into Gating configuration >>>>
6164 22:10:59.067532 Exit from Gating configuration <<<<
6165 22:10:59.070885 Enter into DVFS_PRE_config >>>>>
6166 22:10:59.080690 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6167 22:10:59.084593 Exit from DVFS_PRE_config <<<<<
6168 22:10:59.087402 Enter into PICG configuration >>>>
6169 22:10:59.090838 Exit from PICG configuration <<<<
6170 22:10:59.093868 [RX_INPUT] configuration >>>>>
6171 22:10:59.097254 [RX_INPUT] configuration <<<<<
6172 22:10:59.100803 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6173 22:10:59.107251 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6174 22:10:59.114004 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6175 22:10:59.117579 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6176 22:10:59.123945 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6177 22:10:59.130095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6178 22:10:59.133496 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6179 22:10:59.139812 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6180 22:10:59.143782 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6181 22:10:59.146778 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6182 22:10:59.150071 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6183 22:10:59.156591 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6184 22:10:59.159980 ===================================
6185 22:10:59.163156 LPDDR4 DRAM CONFIGURATION
6186 22:10:59.163573 ===================================
6187 22:10:59.166311 EX_ROW_EN[0] = 0x0
6188 22:10:59.169938 EX_ROW_EN[1] = 0x0
6189 22:10:59.170351 LP4Y_EN = 0x0
6190 22:10:59.173275 WORK_FSP = 0x0
6191 22:10:59.173689 WL = 0x2
6192 22:10:59.176516 RL = 0x2
6193 22:10:59.176933 BL = 0x2
6194 22:10:59.179846 RPST = 0x0
6195 22:10:59.180293 RD_PRE = 0x0
6196 22:10:59.183091 WR_PRE = 0x1
6197 22:10:59.183576 WR_PST = 0x0
6198 22:10:59.186319 DBI_WR = 0x0
6199 22:10:59.186803 DBI_RD = 0x0
6200 22:10:59.189729 OTF = 0x1
6201 22:10:59.192878 ===================================
6202 22:10:59.196469 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6203 22:10:59.199352 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6204 22:10:59.206006 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6205 22:10:59.209547 ===================================
6206 22:10:59.209972 LPDDR4 DRAM CONFIGURATION
6207 22:10:59.213042 ===================================
6208 22:10:59.215993 EX_ROW_EN[0] = 0x10
6209 22:10:59.219324 EX_ROW_EN[1] = 0x0
6210 22:10:59.219740 LP4Y_EN = 0x0
6211 22:10:59.222534 WORK_FSP = 0x0
6212 22:10:59.223021 WL = 0x2
6213 22:10:59.225928 RL = 0x2
6214 22:10:59.226346 BL = 0x2
6215 22:10:59.229316 RPST = 0x0
6216 22:10:59.229736 RD_PRE = 0x0
6217 22:10:59.232055 WR_PRE = 0x1
6218 22:10:59.232605 WR_PST = 0x0
6219 22:10:59.235673 DBI_WR = 0x0
6220 22:10:59.236109 DBI_RD = 0x0
6221 22:10:59.238906 OTF = 0x1
6222 22:10:59.242185 ===================================
6223 22:10:59.248859 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6224 22:10:59.252867 nWR fixed to 30
6225 22:10:59.255444 [ModeRegInit_LP4] CH0 RK0
6226 22:10:59.255862 [ModeRegInit_LP4] CH0 RK1
6227 22:10:59.259253 [ModeRegInit_LP4] CH1 RK0
6228 22:10:59.262156 [ModeRegInit_LP4] CH1 RK1
6229 22:10:59.262574 match AC timing 19
6230 22:10:59.268365 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6231 22:10:59.271787 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6232 22:10:59.275240 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6233 22:10:59.281800 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6234 22:10:59.285322 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6235 22:10:59.285743 ==
6236 22:10:59.288869 Dram Type= 6, Freq= 0, CH_0, rank 0
6237 22:10:59.292144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 22:10:59.292766 ==
6239 22:10:59.298527 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 22:10:59.305155 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6241 22:10:59.308813 [CA 0] Center 36 (8~64) winsize 57
6242 22:10:59.312068 [CA 1] Center 36 (8~64) winsize 57
6243 22:10:59.314920 [CA 2] Center 36 (8~64) winsize 57
6244 22:10:59.318494 [CA 3] Center 36 (8~64) winsize 57
6245 22:10:59.321791 [CA 4] Center 36 (8~64) winsize 57
6246 22:10:59.322253 [CA 5] Center 36 (8~64) winsize 57
6247 22:10:59.324895
6248 22:10:59.328188 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6249 22:10:59.328632
6250 22:10:59.331557 [CATrainingPosCal] consider 1 rank data
6251 22:10:59.334885 u2DelayCellTimex100 = 270/100 ps
6252 22:10:59.338293 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 22:10:59.341638 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 22:10:59.344704 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 22:10:59.347876 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 22:10:59.351342 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 22:10:59.354989 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 22:10:59.355410
6259 22:10:59.357623 CA PerBit enable=1, Macro0, CA PI delay=36
6260 22:10:59.361328
6261 22:10:59.361770 [CBTSetCACLKResult] CA Dly = 36
6262 22:10:59.364388 CS Dly: 1 (0~32)
6263 22:10:59.364807 ==
6264 22:10:59.367694 Dram Type= 6, Freq= 0, CH_0, rank 1
6265 22:10:59.371158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 22:10:59.371582 ==
6267 22:10:59.377523 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6268 22:10:59.383958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6269 22:10:59.387501 [CA 0] Center 36 (8~64) winsize 57
6270 22:10:59.390622 [CA 1] Center 36 (8~64) winsize 57
6271 22:10:59.393615 [CA 2] Center 36 (8~64) winsize 57
6272 22:10:59.393723 [CA 3] Center 36 (8~64) winsize 57
6273 22:10:59.397036 [CA 4] Center 36 (8~64) winsize 57
6274 22:10:59.401326 [CA 5] Center 36 (8~64) winsize 57
6275 22:10:59.401851
6276 22:10:59.407672 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6277 22:10:59.408268
6278 22:10:59.410412 [CATrainingPosCal] consider 2 rank data
6279 22:10:59.414041 u2DelayCellTimex100 = 270/100 ps
6280 22:10:59.417008 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 22:10:59.420384 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 22:10:59.423634 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 22:10:59.427303 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 22:10:59.430274 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 22:10:59.433872 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 22:10:59.434344
6287 22:10:59.436706 CA PerBit enable=1, Macro0, CA PI delay=36
6288 22:10:59.437279
6289 22:10:59.440328 [CBTSetCACLKResult] CA Dly = 36
6290 22:10:59.443758 CS Dly: 1 (0~32)
6291 22:10:59.444176
6292 22:10:59.446990 ----->DramcWriteLeveling(PI) begin...
6293 22:10:59.447546 ==
6294 22:10:59.450246 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 22:10:59.453555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 22:10:59.453976 ==
6297 22:10:59.456820 Write leveling (Byte 0): 40 => 8
6298 22:10:59.459910 Write leveling (Byte 1): 32 => 0
6299 22:10:59.463625 DramcWriteLeveling(PI) end<-----
6300 22:10:59.464041
6301 22:10:59.464416 ==
6302 22:10:59.466850 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 22:10:59.470024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 22:10:59.470481 ==
6305 22:10:59.473941 [Gating] SW mode calibration
6306 22:10:59.479938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6307 22:10:59.486700 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6308 22:10:59.490056 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 22:10:59.496698 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6310 22:10:59.499643 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 22:10:59.503531 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 22:10:59.509693 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 22:10:59.512866 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 22:10:59.516148 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 22:10:59.522804 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 22:10:59.526271 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 22:10:59.529528 Total UI for P1: 0, mck2ui 16
6318 22:10:59.533021 best dqsien dly found for B0: ( 0, 14, 24)
6319 22:10:59.536521 Total UI for P1: 0, mck2ui 16
6320 22:10:59.539787 best dqsien dly found for B1: ( 0, 14, 24)
6321 22:10:59.542672 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6322 22:10:59.546001 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6323 22:10:59.546414
6324 22:10:59.549488 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 22:10:59.552945 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6326 22:10:59.556260 [Gating] SW calibration Done
6327 22:10:59.556685 ==
6328 22:10:59.559491 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 22:10:59.562900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 22:10:59.563317 ==
6331 22:10:59.566081 RX Vref Scan: 0
6332 22:10:59.566492
6333 22:10:59.569324 RX Vref 0 -> 0, step: 1
6334 22:10:59.569731
6335 22:10:59.572392 RX Delay -410 -> 252, step: 16
6336 22:10:59.575975 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6337 22:10:59.579119 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6338 22:10:59.582684 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6339 22:10:59.588773 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6340 22:10:59.592405 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6341 22:10:59.595685 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6342 22:10:59.598700 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6343 22:10:59.605527 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6344 22:10:59.608787 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6345 22:10:59.612882 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6346 22:10:59.616303 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6347 22:10:59.622395 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6348 22:10:59.625478 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6349 22:10:59.628655 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6350 22:10:59.635509 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6351 22:10:59.638622 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6352 22:10:59.639102 ==
6353 22:10:59.641934 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 22:10:59.645382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 22:10:59.645865 ==
6356 22:10:59.648421 DQS Delay:
6357 22:10:59.649041 DQS0 = 43, DQS1 = 59
6358 22:10:59.649567 DQM Delay:
6359 22:10:59.651790 DQM0 = 10, DQM1 = 12
6360 22:10:59.652369 DQ Delay:
6361 22:10:59.655096 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6362 22:10:59.658382 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6363 22:10:59.661827 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6364 22:10:59.664738 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6365 22:10:59.665324
6366 22:10:59.665851
6367 22:10:59.666260 ==
6368 22:10:59.668169 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 22:10:59.671749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 22:10:59.672320 ==
6371 22:10:59.675114
6372 22:10:59.675549
6373 22:10:59.675921 TX Vref Scan disable
6374 22:10:59.678121 == TX Byte 0 ==
6375 22:10:59.681859 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 22:10:59.684822 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 22:10:59.687946 == TX Byte 1 ==
6378 22:10:59.691606 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6379 22:10:59.694685 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6380 22:10:59.695160 ==
6381 22:10:59.698253 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 22:10:59.704533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 22:10:59.705062 ==
6384 22:10:59.705427
6385 22:10:59.705745
6386 22:10:59.706087 TX Vref Scan disable
6387 22:10:59.707864 == TX Byte 0 ==
6388 22:10:59.711081 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 22:10:59.714329 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 22:10:59.717822 == TX Byte 1 ==
6391 22:10:59.720961 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6392 22:10:59.724319 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6393 22:10:59.727623
6394 22:10:59.728044 [DATLAT]
6395 22:10:59.728404 Freq=400, CH0 RK0
6396 22:10:59.728732
6397 22:10:59.730812 DATLAT Default: 0xf
6398 22:10:59.731232 0, 0xFFFF, sum = 0
6399 22:10:59.734402 1, 0xFFFF, sum = 0
6400 22:10:59.734882 2, 0xFFFF, sum = 0
6401 22:10:59.737834 3, 0xFFFF, sum = 0
6402 22:10:59.738286 4, 0xFFFF, sum = 0
6403 22:10:59.741321 5, 0xFFFF, sum = 0
6404 22:10:59.743904 6, 0xFFFF, sum = 0
6405 22:10:59.744439 7, 0xFFFF, sum = 0
6406 22:10:59.747152 8, 0xFFFF, sum = 0
6407 22:10:59.747580 9, 0xFFFF, sum = 0
6408 22:10:59.750649 10, 0xFFFF, sum = 0
6409 22:10:59.751079 11, 0xFFFF, sum = 0
6410 22:10:59.754395 12, 0xFFFF, sum = 0
6411 22:10:59.755036 13, 0x0, sum = 1
6412 22:10:59.757504 14, 0x0, sum = 2
6413 22:10:59.757950 15, 0x0, sum = 3
6414 22:10:59.761031 16, 0x0, sum = 4
6415 22:10:59.761454 best_step = 14
6416 22:10:59.761781
6417 22:10:59.762088 ==
6418 22:10:59.763800 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 22:10:59.767514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 22:10:59.771009 ==
6421 22:10:59.771425 RX Vref Scan: 1
6422 22:10:59.771753
6423 22:10:59.773680 RX Vref 0 -> 0, step: 1
6424 22:10:59.774139
6425 22:10:59.777269 RX Delay -359 -> 252, step: 8
6426 22:10:59.777684
6427 22:10:59.780420 Set Vref, RX VrefLevel [Byte0]: 58
6428 22:10:59.783794 [Byte1]: 57
6429 22:10:59.784209
6430 22:10:59.787211 Final RX Vref Byte 0 = 58 to rank0
6431 22:10:59.789996 Final RX Vref Byte 1 = 57 to rank0
6432 22:10:59.793627 Final RX Vref Byte 0 = 58 to rank1
6433 22:10:59.796560 Final RX Vref Byte 1 = 57 to rank1==
6434 22:10:59.800129 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 22:10:59.803514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 22:10:59.804046 ==
6437 22:10:59.806936 DQS Delay:
6438 22:10:59.807355 DQS0 = 44, DQS1 = 56
6439 22:10:59.810302 DQM Delay:
6440 22:10:59.810790 DQM0 = 8, DQM1 = 8
6441 22:10:59.811238 DQ Delay:
6442 22:10:59.813107 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6443 22:10:59.816489 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6444 22:10:59.820248 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6445 22:10:59.823322 DQ12 =16, DQ13 =12, DQ14 =16, DQ15 =16
6446 22:10:59.823758
6447 22:10:59.824198
6448 22:10:59.833444 [DQSOSCAuto] RK0, (LSB)MR18= 0xc084, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6449 22:10:59.833910 CH0 RK0: MR19=C0C, MR18=C084
6450 22:10:59.839609 CH0_RK0: MR19=0xC0C, MR18=0xC084, DQSOSC=386, MR23=63, INC=396, DEC=264
6451 22:10:59.840200 ==
6452 22:10:59.843124 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 22:10:59.850179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 22:10:59.850647 ==
6455 22:10:59.852890 [Gating] SW mode calibration
6456 22:10:59.859397 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6457 22:10:59.863046 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6458 22:10:59.869400 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 22:10:59.872591 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 22:10:59.876186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 22:10:59.882464 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 22:10:59.885860 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 22:10:59.889171 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 22:10:59.895576 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 22:10:59.898977 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 22:10:59.902236 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 22:10:59.906039 Total UI for P1: 0, mck2ui 16
6468 22:10:59.909458 best dqsien dly found for B0: ( 0, 14, 24)
6469 22:10:59.912559 Total UI for P1: 0, mck2ui 16
6470 22:10:59.915501 best dqsien dly found for B1: ( 0, 14, 24)
6471 22:10:59.919025 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6472 22:10:59.922418 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6473 22:10:59.922940
6474 22:10:59.928757 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 22:10:59.931963 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6476 22:10:59.935381 [Gating] SW calibration Done
6477 22:10:59.935828 ==
6478 22:10:59.938888 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 22:10:59.942362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 22:10:59.942888 ==
6481 22:10:59.943218 RX Vref Scan: 0
6482 22:10:59.943657
6483 22:10:59.945806 RX Vref 0 -> 0, step: 1
6484 22:10:59.946214
6485 22:10:59.948719 RX Delay -410 -> 252, step: 16
6486 22:10:59.952535 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6487 22:10:59.958677 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6488 22:10:59.962144 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6489 22:10:59.965844 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6490 22:10:59.968451 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6491 22:10:59.975489 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6492 22:10:59.978917 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6493 22:10:59.981645 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6494 22:10:59.984937 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6495 22:10:59.991434 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6496 22:10:59.995238 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6497 22:10:59.998137 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6498 22:11:00.001844 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6499 22:11:00.008301 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6500 22:11:00.011706 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6501 22:11:00.014970 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6502 22:11:00.015412 ==
6503 22:11:00.018067 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 22:11:00.024758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 22:11:00.025224 ==
6506 22:11:00.025575 DQS Delay:
6507 22:11:00.028577 DQS0 = 43, DQS1 = 51
6508 22:11:00.029015 DQM Delay:
6509 22:11:00.029348 DQM0 = 10, DQM1 = 9
6510 22:11:00.031800 DQ Delay:
6511 22:11:00.035190 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6512 22:11:00.035605 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6513 22:11:00.037954 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6514 22:11:00.041620 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6515 22:11:00.042065
6516 22:11:00.042428
6517 22:11:00.044999 ==
6518 22:11:00.047820 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 22:11:00.051171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 22:11:00.051616 ==
6521 22:11:00.051949
6522 22:11:00.052277
6523 22:11:00.054398 TX Vref Scan disable
6524 22:11:00.054870 == TX Byte 0 ==
6525 22:11:00.057816 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6526 22:11:00.064536 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6527 22:11:00.064953 == TX Byte 1 ==
6528 22:11:00.067969 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6529 22:11:00.074150 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6530 22:11:00.074708 ==
6531 22:11:00.077869 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 22:11:00.081117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 22:11:00.081637 ==
6534 22:11:00.081966
6535 22:11:00.082271
6536 22:11:00.084097 TX Vref Scan disable
6537 22:11:00.084515 == TX Byte 0 ==
6538 22:11:00.087591 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6539 22:11:00.094273 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6540 22:11:00.094767 == TX Byte 1 ==
6541 22:11:00.097683 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6542 22:11:00.103876 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6543 22:11:00.104292
6544 22:11:00.104618 [DATLAT]
6545 22:11:00.107346 Freq=400, CH0 RK1
6546 22:11:00.107764
6547 22:11:00.108089 DATLAT Default: 0xe
6548 22:11:00.110568 0, 0xFFFF, sum = 0
6549 22:11:00.111034 1, 0xFFFF, sum = 0
6550 22:11:00.113681 2, 0xFFFF, sum = 0
6551 22:11:00.114096 3, 0xFFFF, sum = 0
6552 22:11:00.117094 4, 0xFFFF, sum = 0
6553 22:11:00.117564 5, 0xFFFF, sum = 0
6554 22:11:00.120371 6, 0xFFFF, sum = 0
6555 22:11:00.120849 7, 0xFFFF, sum = 0
6556 22:11:00.123688 8, 0xFFFF, sum = 0
6557 22:11:00.124226 9, 0xFFFF, sum = 0
6558 22:11:00.126921 10, 0xFFFF, sum = 0
6559 22:11:00.127406 11, 0xFFFF, sum = 0
6560 22:11:00.130500 12, 0xFFFF, sum = 0
6561 22:11:00.130966 13, 0x0, sum = 1
6562 22:11:00.133685 14, 0x0, sum = 2
6563 22:11:00.134100 15, 0x0, sum = 3
6564 22:11:00.137083 16, 0x0, sum = 4
6565 22:11:00.137504 best_step = 14
6566 22:11:00.137831
6567 22:11:00.138133 ==
6568 22:11:00.140238 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 22:11:00.147022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 22:11:00.147493 ==
6571 22:11:00.147823 RX Vref Scan: 0
6572 22:11:00.148132
6573 22:11:00.150556 RX Vref 0 -> 0, step: 1
6574 22:11:00.151026
6575 22:11:00.153357 RX Delay -343 -> 252, step: 8
6576 22:11:00.160066 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6577 22:11:00.163295 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6578 22:11:00.166565 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6579 22:11:00.170192 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6580 22:11:00.176668 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6581 22:11:00.179519 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6582 22:11:00.183303 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6583 22:11:00.189726 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6584 22:11:00.192960 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6585 22:11:00.196303 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6586 22:11:00.199400 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6587 22:11:00.206290 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6588 22:11:00.209815 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6589 22:11:00.212678 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6590 22:11:00.216136 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6591 22:11:00.222739 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6592 22:11:00.223433 ==
6593 22:11:00.226369 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 22:11:00.229516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 22:11:00.230130 ==
6596 22:11:00.230706 DQS Delay:
6597 22:11:00.232278 DQS0 = 44, DQS1 = 56
6598 22:11:00.232769 DQM Delay:
6599 22:11:00.235768 DQM0 = 8, DQM1 = 12
6600 22:11:00.236244 DQ Delay:
6601 22:11:00.238817 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6602 22:11:00.242301 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6603 22:11:00.246070 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6604 22:11:00.248795 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =16
6605 22:11:00.249247
6606 22:11:00.249670
6607 22:11:00.256016 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe49, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6608 22:11:00.259449 CH0 RK1: MR19=C0C, MR18=BE49
6609 22:11:00.265371 CH0_RK1: MR19=0xC0C, MR18=0xBE49, DQSOSC=386, MR23=63, INC=396, DEC=264
6610 22:11:00.268698 [RxdqsGatingPostProcess] freq 400
6611 22:11:00.275299 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6612 22:11:00.278519 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 22:11:00.281682 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 22:11:00.284845 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 22:11:00.288202 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 22:11:00.288521 best DQS0 dly(2T, 0.5T) = (0, 10)
6617 22:11:00.291803 best DQS1 dly(2T, 0.5T) = (0, 10)
6618 22:11:00.294897 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6619 22:11:00.298438 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6620 22:11:00.301877 Pre-setting of DQS Precalculation
6621 22:11:00.308305 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6622 22:11:00.308414 ==
6623 22:11:00.311466 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 22:11:00.314696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 22:11:00.314776 ==
6626 22:11:00.321178 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 22:11:00.327769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6628 22:11:00.331373 [CA 0] Center 36 (8~64) winsize 57
6629 22:11:00.331487 [CA 1] Center 36 (8~64) winsize 57
6630 22:11:00.334710 [CA 2] Center 36 (8~64) winsize 57
6631 22:11:00.338332 [CA 3] Center 36 (8~64) winsize 57
6632 22:11:00.341597 [CA 4] Center 36 (8~64) winsize 57
6633 22:11:00.344834 [CA 5] Center 36 (8~64) winsize 57
6634 22:11:00.344925
6635 22:11:00.347997 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6636 22:11:00.348090
6637 22:11:00.351392 [CATrainingPosCal] consider 1 rank data
6638 22:11:00.354207 u2DelayCellTimex100 = 270/100 ps
6639 22:11:00.358333 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 22:11:00.364329 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 22:11:00.368023 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 22:11:00.371209 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 22:11:00.374260 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 22:11:00.377671 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 22:11:00.377827
6646 22:11:00.381010 CA PerBit enable=1, Macro0, CA PI delay=36
6647 22:11:00.381260
6648 22:11:00.384342 [CBTSetCACLKResult] CA Dly = 36
6649 22:11:00.388059 CS Dly: 1 (0~32)
6650 22:11:00.388296 ==
6651 22:11:00.390848 Dram Type= 6, Freq= 0, CH_1, rank 1
6652 22:11:00.394098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 22:11:00.394392 ==
6654 22:11:00.401125 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6655 22:11:00.404800 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6656 22:11:00.407729 [CA 0] Center 36 (8~64) winsize 57
6657 22:11:00.410564 [CA 1] Center 36 (8~64) winsize 57
6658 22:11:00.413938 [CA 2] Center 36 (8~64) winsize 57
6659 22:11:00.417634 [CA 3] Center 36 (8~64) winsize 57
6660 22:11:00.420834 [CA 4] Center 36 (8~64) winsize 57
6661 22:11:00.424014 [CA 5] Center 36 (8~64) winsize 57
6662 22:11:00.424342
6663 22:11:00.427450 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6664 22:11:00.427690
6665 22:11:00.430628 [CATrainingPosCal] consider 2 rank data
6666 22:11:00.434080 u2DelayCellTimex100 = 270/100 ps
6667 22:11:00.436917 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 22:11:00.440294 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 22:11:00.447057 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 22:11:00.450539 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 22:11:00.453286 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 22:11:00.456930 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 22:11:00.457169
6674 22:11:00.460453 CA PerBit enable=1, Macro0, CA PI delay=36
6675 22:11:00.460690
6676 22:11:00.463273 [CBTSetCACLKResult] CA Dly = 36
6677 22:11:00.463512 CS Dly: 1 (0~32)
6678 22:11:00.463700
6679 22:11:00.466774 ----->DramcWriteLeveling(PI) begin...
6680 22:11:00.470132 ==
6681 22:11:00.473453 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 22:11:00.476904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 22:11:00.477121 ==
6684 22:11:00.480132 Write leveling (Byte 0): 40 => 8
6685 22:11:00.483497 Write leveling (Byte 1): 32 => 0
6686 22:11:00.486785 DramcWriteLeveling(PI) end<-----
6687 22:11:00.486999
6688 22:11:00.487178 ==
6689 22:11:00.490165 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 22:11:00.493331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 22:11:00.493567 ==
6692 22:11:00.496998 [Gating] SW mode calibration
6693 22:11:00.502940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6694 22:11:00.510014 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6695 22:11:00.513591 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6696 22:11:00.516421 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6697 22:11:00.523061 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 22:11:00.526231 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 22:11:00.529481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 22:11:00.536448 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 22:11:00.539701 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 22:11:00.542738 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 22:11:00.549316 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 22:11:00.549732 Total UI for P1: 0, mck2ui 16
6705 22:11:00.552719 best dqsien dly found for B0: ( 0, 14, 24)
6706 22:11:00.556327 Total UI for P1: 0, mck2ui 16
6707 22:11:00.559344 best dqsien dly found for B1: ( 0, 14, 24)
6708 22:11:00.566277 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6709 22:11:00.569461 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6710 22:11:00.569989
6711 22:11:00.572633 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 22:11:00.575941 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6713 22:11:00.579239 [Gating] SW calibration Done
6714 22:11:00.579665 ==
6715 22:11:00.582367 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 22:11:00.585663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 22:11:00.586265 ==
6718 22:11:00.588998 RX Vref Scan: 0
6719 22:11:00.589491
6720 22:11:00.589891 RX Vref 0 -> 0, step: 1
6721 22:11:00.590299
6722 22:11:00.592645 RX Delay -410 -> 252, step: 16
6723 22:11:00.598885 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6724 22:11:00.602047 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6725 22:11:00.605288 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6726 22:11:00.608727 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6727 22:11:00.615498 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6728 22:11:00.618841 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6729 22:11:00.622125 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6730 22:11:00.625344 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6731 22:11:00.631522 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6732 22:11:00.634659 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6733 22:11:00.638021 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6734 22:11:00.641576 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6735 22:11:00.647930 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6736 22:11:00.651620 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6737 22:11:00.655061 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6738 22:11:00.661237 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6739 22:11:00.661406 ==
6740 22:11:00.664707 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 22:11:00.667995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 22:11:00.668220 ==
6743 22:11:00.668421 DQS Delay:
6744 22:11:00.671219 DQS0 = 43, DQS1 = 51
6745 22:11:00.671478 DQM Delay:
6746 22:11:00.674262 DQM0 = 12, DQM1 = 14
6747 22:11:00.674458 DQ Delay:
6748 22:11:00.677499 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6749 22:11:00.681179 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6750 22:11:00.684358 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6751 22:11:00.687649 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6752 22:11:00.688100
6753 22:11:00.688404
6754 22:11:00.688703 ==
6755 22:11:00.690975 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 22:11:00.694274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 22:11:00.694793 ==
6758 22:11:00.695148
6759 22:11:00.695575
6760 22:11:00.697487 TX Vref Scan disable
6761 22:11:00.701041 == TX Byte 0 ==
6762 22:11:00.704209 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 22:11:00.707318 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 22:11:00.707819 == TX Byte 1 ==
6765 22:11:00.714448 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6766 22:11:00.717292 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6767 22:11:00.717682 ==
6768 22:11:00.720480 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 22:11:00.724137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 22:11:00.724590 ==
6771 22:11:00.727086
6772 22:11:00.727389
6773 22:11:00.727631 TX Vref Scan disable
6774 22:11:00.730386 == TX Byte 0 ==
6775 22:11:00.733739 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 22:11:00.736738 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 22:11:00.740013 == TX Byte 1 ==
6778 22:11:00.743421 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6779 22:11:00.746948 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6780 22:11:00.747032
6781 22:11:00.750239 [DATLAT]
6782 22:11:00.750322 Freq=400, CH1 RK0
6783 22:11:00.750387
6784 22:11:00.753507 DATLAT Default: 0xf
6785 22:11:00.753617 0, 0xFFFF, sum = 0
6786 22:11:00.756553 1, 0xFFFF, sum = 0
6787 22:11:00.756641 2, 0xFFFF, sum = 0
6788 22:11:00.760061 3, 0xFFFF, sum = 0
6789 22:11:00.760173 4, 0xFFFF, sum = 0
6790 22:11:00.763298 5, 0xFFFF, sum = 0
6791 22:11:00.763383 6, 0xFFFF, sum = 0
6792 22:11:00.766497 7, 0xFFFF, sum = 0
6793 22:11:00.766615 8, 0xFFFF, sum = 0
6794 22:11:00.769772 9, 0xFFFF, sum = 0
6795 22:11:00.769858 10, 0xFFFF, sum = 0
6796 22:11:00.773246 11, 0xFFFF, sum = 0
6797 22:11:00.776562 12, 0xFFFF, sum = 0
6798 22:11:00.776646 13, 0x0, sum = 1
6799 22:11:00.776712 14, 0x0, sum = 2
6800 22:11:00.779876 15, 0x0, sum = 3
6801 22:11:00.779988 16, 0x0, sum = 4
6802 22:11:00.783412 best_step = 14
6803 22:11:00.783494
6804 22:11:00.783559 ==
6805 22:11:00.786319 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 22:11:00.789681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 22:11:00.789766 ==
6808 22:11:00.793233 RX Vref Scan: 1
6809 22:11:00.793342
6810 22:11:00.793436 RX Vref 0 -> 0, step: 1
6811 22:11:00.793526
6812 22:11:00.796086 RX Delay -343 -> 252, step: 8
6813 22:11:00.796201
6814 22:11:00.799599 Set Vref, RX VrefLevel [Byte0]: 50
6815 22:11:00.802643 [Byte1]: 52
6816 22:11:00.807850
6817 22:11:00.807938 Final RX Vref Byte 0 = 50 to rank0
6818 22:11:00.811220 Final RX Vref Byte 1 = 52 to rank0
6819 22:11:00.814233 Final RX Vref Byte 0 = 50 to rank1
6820 22:11:00.817532 Final RX Vref Byte 1 = 52 to rank1==
6821 22:11:00.820968 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 22:11:00.827794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 22:11:00.827882 ==
6824 22:11:00.827971 DQS Delay:
6825 22:11:00.830644 DQS0 = 44, DQS1 = 56
6826 22:11:00.830731 DQM Delay:
6827 22:11:00.830819 DQM0 = 8, DQM1 = 13
6828 22:11:00.834323 DQ Delay:
6829 22:11:00.837614 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6830 22:11:00.837725 DQ4 =4, DQ5 =20, DQ6 =20, DQ7 =4
6831 22:11:00.841025 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6832 22:11:00.843937 DQ12 =28, DQ13 =16, DQ14 =16, DQ15 =24
6833 22:11:00.847339
6834 22:11:00.847424
6835 22:11:00.854129 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6836 22:11:00.857176 CH1 RK0: MR19=C0C, MR18=9B72
6837 22:11:00.864048 CH1_RK0: MR19=0xC0C, MR18=0x9B72, DQSOSC=390, MR23=63, INC=388, DEC=258
6838 22:11:00.864147 ==
6839 22:11:00.867397 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 22:11:00.870797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 22:11:00.870885 ==
6842 22:11:00.873733 [Gating] SW mode calibration
6843 22:11:00.880498 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6844 22:11:00.886710 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6845 22:11:00.890523 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 22:11:00.893274 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6847 22:11:00.900219 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 22:11:00.903640 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 22:11:00.906576 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 22:11:00.913285 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 22:11:00.916721 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 22:11:00.920056 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 22:11:00.926412 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 22:11:00.926495 Total UI for P1: 0, mck2ui 16
6855 22:11:00.933261 best dqsien dly found for B0: ( 0, 14, 24)
6856 22:11:00.933345 Total UI for P1: 0, mck2ui 16
6857 22:11:00.939369 best dqsien dly found for B1: ( 0, 14, 24)
6858 22:11:00.942885 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6859 22:11:00.946180 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6860 22:11:00.946256
6861 22:11:00.949447 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 22:11:00.952734 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6863 22:11:00.956390 [Gating] SW calibration Done
6864 22:11:00.956465 ==
6865 22:11:00.959656 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 22:11:00.963063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 22:11:00.963155 ==
6868 22:11:00.966071 RX Vref Scan: 0
6869 22:11:00.966180
6870 22:11:00.966274 RX Vref 0 -> 0, step: 1
6871 22:11:00.969222
6872 22:11:00.969331 RX Delay -410 -> 252, step: 16
6873 22:11:00.976105 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6874 22:11:00.979433 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6875 22:11:00.982488 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6876 22:11:00.985939 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6877 22:11:00.992911 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6878 22:11:00.995746 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6879 22:11:00.999687 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6880 22:11:01.002394 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6881 22:11:01.009000 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6882 22:11:01.012444 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6883 22:11:01.015882 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6884 22:11:01.022095 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6885 22:11:01.026086 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6886 22:11:01.029104 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6887 22:11:01.032439 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6888 22:11:01.039186 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6889 22:11:01.039273 ==
6890 22:11:01.042503 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 22:11:01.045243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 22:11:01.045347 ==
6893 22:11:01.045439 DQS Delay:
6894 22:11:01.048849 DQS0 = 43, DQS1 = 51
6895 22:11:01.048942 DQM Delay:
6896 22:11:01.052087 DQM0 = 12, DQM1 = 14
6897 22:11:01.052163 DQ Delay:
6898 22:11:01.055472 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6899 22:11:01.058960 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6900 22:11:01.062343 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6901 22:11:01.065653 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6902 22:11:01.065743
6903 22:11:01.065807
6904 22:11:01.065866 ==
6905 22:11:01.068539 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 22:11:01.072311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 22:11:01.072391 ==
6908 22:11:01.072456
6909 22:11:01.072542
6910 22:11:01.075686 TX Vref Scan disable
6911 22:11:01.075760 == TX Byte 0 ==
6912 22:11:01.082207 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6913 22:11:01.085141 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6914 22:11:01.085248 == TX Byte 1 ==
6915 22:11:01.091651 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6916 22:11:01.095116 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6917 22:11:01.095279 ==
6918 22:11:01.098268 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 22:11:01.101603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 22:11:01.101755 ==
6921 22:11:01.101881
6922 22:11:01.105078
6923 22:11:01.105230 TX Vref Scan disable
6924 22:11:01.108462 == TX Byte 0 ==
6925 22:11:01.111883 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6926 22:11:01.115298 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6927 22:11:01.117916 == TX Byte 1 ==
6928 22:11:01.121302 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6929 22:11:01.124984 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6930 22:11:01.125268
6931 22:11:01.125472 [DATLAT]
6932 22:11:01.128364 Freq=400, CH1 RK1
6933 22:11:01.128624
6934 22:11:01.131347 DATLAT Default: 0xe
6935 22:11:01.131713 0, 0xFFFF, sum = 0
6936 22:11:01.135177 1, 0xFFFF, sum = 0
6937 22:11:01.135643 2, 0xFFFF, sum = 0
6938 22:11:01.138357 3, 0xFFFF, sum = 0
6939 22:11:01.138838 4, 0xFFFF, sum = 0
6940 22:11:01.141676 5, 0xFFFF, sum = 0
6941 22:11:01.142101 6, 0xFFFF, sum = 0
6942 22:11:01.144460 7, 0xFFFF, sum = 0
6943 22:11:01.144966 8, 0xFFFF, sum = 0
6944 22:11:01.147966 9, 0xFFFF, sum = 0
6945 22:11:01.148531 10, 0xFFFF, sum = 0
6946 22:11:01.151818 11, 0xFFFF, sum = 0
6947 22:11:01.152253 12, 0xFFFF, sum = 0
6948 22:11:01.154625 13, 0x0, sum = 1
6949 22:11:01.155112 14, 0x0, sum = 2
6950 22:11:01.158029 15, 0x0, sum = 3
6951 22:11:01.158529 16, 0x0, sum = 4
6952 22:11:01.161363 best_step = 14
6953 22:11:01.161867
6954 22:11:01.162203 ==
6955 22:11:01.164684 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 22:11:01.167557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 22:11:01.167642 ==
6958 22:11:01.170940 RX Vref Scan: 0
6959 22:11:01.171024
6960 22:11:01.171088 RX Vref 0 -> 0, step: 1
6961 22:11:01.171148
6962 22:11:01.174005 RX Delay -343 -> 252, step: 8
6963 22:11:01.181985 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6964 22:11:01.185428 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6965 22:11:01.188475 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6966 22:11:01.195144 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6967 22:11:01.198827 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6968 22:11:01.201520 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6969 22:11:01.205024 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6970 22:11:01.212284 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6971 22:11:01.214785 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6972 22:11:01.218301 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6973 22:11:01.221670 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6974 22:11:01.228040 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6975 22:11:01.231527 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6976 22:11:01.235037 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6977 22:11:01.238035 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6978 22:11:01.244727 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6979 22:11:01.244809 ==
6980 22:11:01.247973 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 22:11:01.250907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 22:11:01.250990 ==
6983 22:11:01.254827 DQS Delay:
6984 22:11:01.254908 DQS0 = 44, DQS1 = 56
6985 22:11:01.255003 DQM Delay:
6986 22:11:01.257595 DQM0 = 9, DQM1 = 11
6987 22:11:01.257677 DQ Delay:
6988 22:11:01.261052 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6989 22:11:01.264294 DQ4 =4, DQ5 =20, DQ6 =20, DQ7 =4
6990 22:11:01.267879 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6991 22:11:01.271251 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6992 22:11:01.271350
6993 22:11:01.271425
6994 22:11:01.277254 [DQSOSCAuto] RK1, (LSB)MR18= 0x6857, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
6995 22:11:01.280926 CH1 RK1: MR19=C0C, MR18=6857
6996 22:11:01.287650 CH1_RK1: MR19=0xC0C, MR18=0x6857, DQSOSC=396, MR23=63, INC=376, DEC=251
6997 22:11:01.290830 [RxdqsGatingPostProcess] freq 400
6998 22:11:01.297588 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6999 22:11:01.300721 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 22:11:01.304040 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 22:11:01.307402 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 22:11:01.310475 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 22:11:01.313908 best DQS0 dly(2T, 0.5T) = (0, 10)
7004 22:11:01.314016 best DQS1 dly(2T, 0.5T) = (0, 10)
7005 22:11:01.316857 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7006 22:11:01.320203 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7007 22:11:01.323517 Pre-setting of DQS Precalculation
7008 22:11:01.330367 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7009 22:11:01.336876 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7010 22:11:01.343559 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7011 22:11:01.343642
7012 22:11:01.343726
7013 22:11:01.346659 [Calibration Summary] 800 Mbps
7014 22:11:01.350157 CH 0, Rank 0
7015 22:11:01.350264 SW Impedance : PASS
7016 22:11:01.353569 DUTY Scan : NO K
7017 22:11:01.353655 ZQ Calibration : PASS
7018 22:11:01.356934 Jitter Meter : NO K
7019 22:11:01.359804 CBT Training : PASS
7020 22:11:01.359884 Write leveling : PASS
7021 22:11:01.363219 RX DQS gating : PASS
7022 22:11:01.366734 RX DQ/DQS(RDDQC) : PASS
7023 22:11:01.366815 TX DQ/DQS : PASS
7024 22:11:01.369929 RX DATLAT : PASS
7025 22:11:01.373230 RX DQ/DQS(Engine): PASS
7026 22:11:01.373316 TX OE : NO K
7027 22:11:01.376865 All Pass.
7028 22:11:01.376946
7029 22:11:01.377009 CH 0, Rank 1
7030 22:11:01.379844 SW Impedance : PASS
7031 22:11:01.379924 DUTY Scan : NO K
7032 22:11:01.382856 ZQ Calibration : PASS
7033 22:11:01.386322 Jitter Meter : NO K
7034 22:11:01.386403 CBT Training : PASS
7035 22:11:01.389955 Write leveling : NO K
7036 22:11:01.393186 RX DQS gating : PASS
7037 22:11:01.393267 RX DQ/DQS(RDDQC) : PASS
7038 22:11:01.396336 TX DQ/DQS : PASS
7039 22:11:01.399744 RX DATLAT : PASS
7040 22:11:01.399826 RX DQ/DQS(Engine): PASS
7041 22:11:01.403011 TX OE : NO K
7042 22:11:01.403091 All Pass.
7043 22:11:01.403155
7044 22:11:01.406407 CH 1, Rank 0
7045 22:11:01.406488 SW Impedance : PASS
7046 22:11:01.409436 DUTY Scan : NO K
7047 22:11:01.412788 ZQ Calibration : PASS
7048 22:11:01.412885 Jitter Meter : NO K
7049 22:11:01.416062 CBT Training : PASS
7050 22:11:01.416143 Write leveling : PASS
7051 22:11:01.419369 RX DQS gating : PASS
7052 22:11:01.422545 RX DQ/DQS(RDDQC) : PASS
7053 22:11:01.422668 TX DQ/DQS : PASS
7054 22:11:01.425789 RX DATLAT : PASS
7055 22:11:01.429509 RX DQ/DQS(Engine): PASS
7056 22:11:01.429659 TX OE : NO K
7057 22:11:01.432591 All Pass.
7058 22:11:01.432663
7059 22:11:01.432723 CH 1, Rank 1
7060 22:11:01.435890 SW Impedance : PASS
7061 22:11:01.435972 DUTY Scan : NO K
7062 22:11:01.439099 ZQ Calibration : PASS
7063 22:11:01.442244 Jitter Meter : NO K
7064 22:11:01.442326 CBT Training : PASS
7065 22:11:01.445811 Write leveling : NO K
7066 22:11:01.449038 RX DQS gating : PASS
7067 22:11:01.449119 RX DQ/DQS(RDDQC) : PASS
7068 22:11:01.452359 TX DQ/DQS : PASS
7069 22:11:01.455360 RX DATLAT : PASS
7070 22:11:01.455441 RX DQ/DQS(Engine): PASS
7071 22:11:01.458918 TX OE : NO K
7072 22:11:01.458999 All Pass.
7073 22:11:01.459063
7074 22:11:01.462378 DramC Write-DBI off
7075 22:11:01.465619 PER_BANK_REFRESH: Hybrid Mode
7076 22:11:01.465725 TX_TRACKING: ON
7077 22:11:01.475710 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7078 22:11:01.478576 [FAST_K] Save calibration result to emmc
7079 22:11:01.481806 dramc_set_vcore_voltage set vcore to 725000
7080 22:11:01.485356 Read voltage for 1600, 0
7081 22:11:01.485436 Vio18 = 0
7082 22:11:01.485499 Vcore = 725000
7083 22:11:01.489173 Vdram = 0
7084 22:11:01.489254 Vddq = 0
7085 22:11:01.489317 Vmddr = 0
7086 22:11:01.494953 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7087 22:11:01.501518 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7088 22:11:01.501599 MEM_TYPE=3, freq_sel=13
7089 22:11:01.505042 sv_algorithm_assistance_LP4_3733
7090 22:11:01.508274 ============ PULL DRAM RESETB DOWN ============
7091 22:11:01.515158 ========== PULL DRAM RESETB DOWN end =========
7092 22:11:01.518492 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7093 22:11:01.522195 ===================================
7094 22:11:01.525247 LPDDR4 DRAM CONFIGURATION
7095 22:11:01.528587 ===================================
7096 22:11:01.529052 EX_ROW_EN[0] = 0x0
7097 22:11:01.532140 EX_ROW_EN[1] = 0x0
7098 22:11:01.532578 LP4Y_EN = 0x0
7099 22:11:01.534907 WORK_FSP = 0x1
7100 22:11:01.535326 WL = 0x5
7101 22:11:01.538239 RL = 0x5
7102 22:11:01.541336 BL = 0x2
7103 22:11:01.541752 RPST = 0x0
7104 22:11:01.544888 RD_PRE = 0x0
7105 22:11:01.545306 WR_PRE = 0x1
7106 22:11:01.548271 WR_PST = 0x1
7107 22:11:01.548689 DBI_WR = 0x0
7108 22:11:01.551124 DBI_RD = 0x0
7109 22:11:01.551553 OTF = 0x1
7110 22:11:01.555097 ===================================
7111 22:11:01.558245 ===================================
7112 22:11:01.561410 ANA top config
7113 22:11:01.564533 ===================================
7114 22:11:01.564955 DLL_ASYNC_EN = 0
7115 22:11:01.568138 ALL_SLAVE_EN = 0
7116 22:11:01.571091 NEW_RANK_MODE = 1
7117 22:11:01.574487 DLL_IDLE_MODE = 1
7118 22:11:01.577461 LP45_APHY_COMB_EN = 1
7119 22:11:01.577838 TX_ODT_DIS = 0
7120 22:11:01.581034 NEW_8X_MODE = 1
7121 22:11:01.584094 ===================================
7122 22:11:01.587770 ===================================
7123 22:11:01.590813 data_rate = 3200
7124 22:11:01.594019 CKR = 1
7125 22:11:01.597364 DQ_P2S_RATIO = 8
7126 22:11:01.600922 ===================================
7127 22:11:01.601147 CA_P2S_RATIO = 8
7128 22:11:01.603922 DQ_CA_OPEN = 0
7129 22:11:01.607580 DQ_SEMI_OPEN = 0
7130 22:11:01.610994 CA_SEMI_OPEN = 0
7131 22:11:01.614309 CA_FULL_RATE = 0
7132 22:11:01.617099 DQ_CKDIV4_EN = 0
7133 22:11:01.617323 CA_CKDIV4_EN = 0
7134 22:11:01.620920 CA_PREDIV_EN = 0
7135 22:11:01.624228 PH8_DLY = 12
7136 22:11:01.627089 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7137 22:11:01.630408 DQ_AAMCK_DIV = 4
7138 22:11:01.634079 CA_AAMCK_DIV = 4
7139 22:11:01.634373 CA_ADMCK_DIV = 4
7140 22:11:01.637387 DQ_TRACK_CA_EN = 0
7141 22:11:01.640550 CA_PICK = 1600
7142 22:11:01.644104 CA_MCKIO = 1600
7143 22:11:01.646881 MCKIO_SEMI = 0
7144 22:11:01.650340 PLL_FREQ = 3068
7145 22:11:01.653422 DQ_UI_PI_RATIO = 32
7146 22:11:01.656977 CA_UI_PI_RATIO = 0
7147 22:11:01.660387 ===================================
7148 22:11:01.663896 ===================================
7149 22:11:01.664171 memory_type:LPDDR4
7150 22:11:01.666629 GP_NUM : 10
7151 22:11:01.669878 SRAM_EN : 1
7152 22:11:01.669963 MD32_EN : 0
7153 22:11:01.673363 ===================================
7154 22:11:01.676616 [ANA_INIT] >>>>>>>>>>>>>>
7155 22:11:01.679878 <<<<<< [CONFIGURE PHASE]: ANA_TX
7156 22:11:01.683067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7157 22:11:01.686509 ===================================
7158 22:11:01.689545 data_rate = 3200,PCW = 0X7600
7159 22:11:01.693265 ===================================
7160 22:11:01.696071 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7161 22:11:01.699865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 22:11:01.706438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7163 22:11:01.709364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7164 22:11:01.712807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7165 22:11:01.716235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7166 22:11:01.720277 [ANA_INIT] flow start
7167 22:11:01.722719 [ANA_INIT] PLL >>>>>>>>
7168 22:11:01.723136 [ANA_INIT] PLL <<<<<<<<
7169 22:11:01.726564 [ANA_INIT] MIDPI >>>>>>>>
7170 22:11:01.729632 [ANA_INIT] MIDPI <<<<<<<<
7171 22:11:01.733041 [ANA_INIT] DLL >>>>>>>>
7172 22:11:01.733456 [ANA_INIT] DLL <<<<<<<<
7173 22:11:01.736317 [ANA_INIT] flow end
7174 22:11:01.739753 ============ LP4 DIFF to SE enter ============
7175 22:11:01.742696 ============ LP4 DIFF to SE exit ============
7176 22:11:01.746089 [ANA_INIT] <<<<<<<<<<<<<
7177 22:11:01.749644 [Flow] Enable top DCM control >>>>>
7178 22:11:01.753119 [Flow] Enable top DCM control <<<<<
7179 22:11:01.756158 Enable DLL master slave shuffle
7180 22:11:01.762495 ==============================================================
7181 22:11:01.762948 Gating Mode config
7182 22:11:01.769291 ==============================================================
7183 22:11:01.769708 Config description:
7184 22:11:01.779017 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7185 22:11:01.785724 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7186 22:11:01.792360 SELPH_MODE 0: By rank 1: By Phase
7187 22:11:01.795706 ==============================================================
7188 22:11:01.799240 GAT_TRACK_EN = 1
7189 22:11:01.802346 RX_GATING_MODE = 2
7190 22:11:01.805919 RX_GATING_TRACK_MODE = 2
7191 22:11:01.808889 SELPH_MODE = 1
7192 22:11:01.812175 PICG_EARLY_EN = 1
7193 22:11:01.816019 VALID_LAT_VALUE = 1
7194 22:11:01.822002 ==============================================================
7195 22:11:01.825290 Enter into Gating configuration >>>>
7196 22:11:01.828607 Exit from Gating configuration <<<<
7197 22:11:01.832302 Enter into DVFS_PRE_config >>>>>
7198 22:11:01.841982 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7199 22:11:01.845438 Exit from DVFS_PRE_config <<<<<
7200 22:11:01.848825 Enter into PICG configuration >>>>
7201 22:11:01.851639 Exit from PICG configuration <<<<
7202 22:11:01.854860 [RX_INPUT] configuration >>>>>
7203 22:11:01.855304 [RX_INPUT] configuration <<<<<
7204 22:11:01.861477 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7205 22:11:01.868624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7206 22:11:01.874699 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7207 22:11:01.877916 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7208 22:11:01.884643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7209 22:11:01.891486 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7210 22:11:01.894882 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7211 22:11:01.901558 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7212 22:11:01.904723 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7213 22:11:01.908094 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7214 22:11:01.911391 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7215 22:11:01.917563 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7216 22:11:01.920874 ===================================
7217 22:11:01.921335 LPDDR4 DRAM CONFIGURATION
7218 22:11:01.924513 ===================================
7219 22:11:01.927714 EX_ROW_EN[0] = 0x0
7220 22:11:01.930841 EX_ROW_EN[1] = 0x0
7221 22:11:01.931257 LP4Y_EN = 0x0
7222 22:11:01.934253 WORK_FSP = 0x1
7223 22:11:01.934716 WL = 0x5
7224 22:11:01.938153 RL = 0x5
7225 22:11:01.938750 BL = 0x2
7226 22:11:01.940915 RPST = 0x0
7227 22:11:01.941372 RD_PRE = 0x0
7228 22:11:01.943908 WR_PRE = 0x1
7229 22:11:01.944321 WR_PST = 0x1
7230 22:11:01.947126 DBI_WR = 0x0
7231 22:11:01.947729 DBI_RD = 0x0
7232 22:11:01.951633 OTF = 0x1
7233 22:11:01.953951 ===================================
7234 22:11:01.957591 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7235 22:11:01.960730 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7236 22:11:01.967219 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7237 22:11:01.970103 ===================================
7238 22:11:01.970752 LPDDR4 DRAM CONFIGURATION
7239 22:11:01.973968 ===================================
7240 22:11:01.977087 EX_ROW_EN[0] = 0x10
7241 22:11:01.980182 EX_ROW_EN[1] = 0x0
7242 22:11:01.980603 LP4Y_EN = 0x0
7243 22:11:01.983397 WORK_FSP = 0x1
7244 22:11:01.983816 WL = 0x5
7245 22:11:01.986588 RL = 0x5
7246 22:11:01.987231 BL = 0x2
7247 22:11:01.990167 RPST = 0x0
7248 22:11:01.990639 RD_PRE = 0x0
7249 22:11:01.993262 WR_PRE = 0x1
7250 22:11:01.993679 WR_PST = 0x1
7251 22:11:01.997030 DBI_WR = 0x0
7252 22:11:01.997555 DBI_RD = 0x0
7253 22:11:01.999740 OTF = 0x1
7254 22:11:02.003351 ===================================
7255 22:11:02.009978 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7256 22:11:02.010402 ==
7257 22:11:02.013751 Dram Type= 6, Freq= 0, CH_0, rank 0
7258 22:11:02.016260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7259 22:11:02.016714 ==
7260 22:11:02.020356 [Duty_Offset_Calibration]
7261 22:11:02.020811 B0:1 B1:-1 CA:0
7262 22:11:02.021316
7263 22:11:02.022913 [DutyScan_Calibration_Flow] k_type=0
7264 22:11:02.035465
7265 22:11:02.035914 ==CLK 0==
7266 22:11:02.038049 Final CLK duty delay cell = 0
7267 22:11:02.040939 [0] MAX Duty = 5125%(X100), DQS PI = 20
7268 22:11:02.044620 [0] MIN Duty = 4907%(X100), DQS PI = 4
7269 22:11:02.045038 [0] AVG Duty = 5016%(X100)
7270 22:11:02.047926
7271 22:11:02.051256 CH0 CLK Duty spec in!! Max-Min= 218%
7272 22:11:02.054453 [DutyScan_Calibration_Flow] ====Done====
7273 22:11:02.054944
7274 22:11:02.057553 [DutyScan_Calibration_Flow] k_type=1
7275 22:11:02.073399
7276 22:11:02.073978 ==DQS 0 ==
7277 22:11:02.076754 Final DQS duty delay cell = -4
7278 22:11:02.080195 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7279 22:11:02.083500 [-4] MIN Duty = 4844%(X100), DQS PI = 10
7280 22:11:02.086785 [-4] AVG Duty = 4906%(X100)
7281 22:11:02.087218
7282 22:11:02.087554 ==DQS 1 ==
7283 22:11:02.090038 Final DQS duty delay cell = 0
7284 22:11:02.093481 [0] MAX Duty = 5156%(X100), DQS PI = 0
7285 22:11:02.096946 [0] MIN Duty = 5031%(X100), DQS PI = 18
7286 22:11:02.099840 [0] AVG Duty = 5093%(X100)
7287 22:11:02.100261
7288 22:11:02.103156 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7289 22:11:02.103573
7290 22:11:02.106805 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7291 22:11:02.109568 [DutyScan_Calibration_Flow] ====Done====
7292 22:11:02.109989
7293 22:11:02.113012 [DutyScan_Calibration_Flow] k_type=3
7294 22:11:02.130895
7295 22:11:02.131311 ==DQM 0 ==
7296 22:11:02.134201 Final DQM duty delay cell = 0
7297 22:11:02.137769 [0] MAX Duty = 5124%(X100), DQS PI = 24
7298 22:11:02.140880 [0] MIN Duty = 4907%(X100), DQS PI = 10
7299 22:11:02.144060 [0] AVG Duty = 5015%(X100)
7300 22:11:02.144378
7301 22:11:02.144610 ==DQM 1 ==
7302 22:11:02.146978 Final DQM duty delay cell = 0
7303 22:11:02.150257 [0] MAX Duty = 5031%(X100), DQS PI = 6
7304 22:11:02.154029 [0] MIN Duty = 4813%(X100), DQS PI = 22
7305 22:11:02.157342 [0] AVG Duty = 4922%(X100)
7306 22:11:02.157602
7307 22:11:02.160383 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7308 22:11:02.160678
7309 22:11:02.163556 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7310 22:11:02.167201 [DutyScan_Calibration_Flow] ====Done====
7311 22:11:02.167514
7312 22:11:02.170042 [DutyScan_Calibration_Flow] k_type=2
7313 22:11:02.186357
7314 22:11:02.186802 ==DQ 0 ==
7315 22:11:02.189732 Final DQ duty delay cell = -4
7316 22:11:02.192974 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7317 22:11:02.196432 [-4] MIN Duty = 4876%(X100), DQS PI = 56
7318 22:11:02.199873 [-4] AVG Duty = 4953%(X100)
7319 22:11:02.200346
7320 22:11:02.200692 ==DQ 1 ==
7321 22:11:02.202694 Final DQ duty delay cell = -4
7322 22:11:02.206661 [-4] MAX Duty = 4969%(X100), DQS PI = 50
7323 22:11:02.209402 [-4] MIN Duty = 4875%(X100), DQS PI = 10
7324 22:11:02.213096 [-4] AVG Duty = 4922%(X100)
7325 22:11:02.213489
7326 22:11:02.216245 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7327 22:11:02.216631
7328 22:11:02.219307 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7329 22:11:02.222897 [DutyScan_Calibration_Flow] ====Done====
7330 22:11:02.223314 ==
7331 22:11:02.225943 Dram Type= 6, Freq= 0, CH_1, rank 0
7332 22:11:02.230090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7333 22:11:02.230429 ==
7334 22:11:02.232606 [Duty_Offset_Calibration]
7335 22:11:02.235731 B0:-1 B1:1 CA:1
7336 22:11:02.236146
7337 22:11:02.239438 [DutyScan_Calibration_Flow] k_type=0
7338 22:11:02.247259
7339 22:11:02.247554 ==CLK 0==
7340 22:11:02.250855 Final CLK duty delay cell = 0
7341 22:11:02.254040 [0] MAX Duty = 5187%(X100), DQS PI = 22
7342 22:11:02.257039 [0] MIN Duty = 5000%(X100), DQS PI = 0
7343 22:11:02.257115 [0] AVG Duty = 5093%(X100)
7344 22:11:02.260831
7345 22:11:02.263782 CH1 CLK Duty spec in!! Max-Min= 187%
7346 22:11:02.266809 [DutyScan_Calibration_Flow] ====Done====
7347 22:11:02.266910
7348 22:11:02.270015 [DutyScan_Calibration_Flow] k_type=1
7349 22:11:02.286911
7350 22:11:02.286998 ==DQS 0 ==
7351 22:11:02.289905 Final DQS duty delay cell = 0
7352 22:11:02.293334 [0] MAX Duty = 5124%(X100), DQS PI = 18
7353 22:11:02.296596 [0] MIN Duty = 4907%(X100), DQS PI = 10
7354 22:11:02.300199 [0] AVG Duty = 5015%(X100)
7355 22:11:02.300270
7356 22:11:02.300329 ==DQS 1 ==
7357 22:11:02.303117 Final DQS duty delay cell = 0
7358 22:11:02.306746 [0] MAX Duty = 5093%(X100), DQS PI = 26
7359 22:11:02.310107 [0] MIN Duty = 4938%(X100), DQS PI = 58
7360 22:11:02.313299 [0] AVG Duty = 5015%(X100)
7361 22:11:02.313386
7362 22:11:02.317146 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7363 22:11:02.317239
7364 22:11:02.320477 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7365 22:11:02.323059 [DutyScan_Calibration_Flow] ====Done====
7366 22:11:02.323164
7367 22:11:02.326691 [DutyScan_Calibration_Flow] k_type=3
7368 22:11:02.343190
7369 22:11:02.343340 ==DQM 0 ==
7370 22:11:02.346585 Final DQM duty delay cell = -4
7371 22:11:02.349911 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7372 22:11:02.353080 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7373 22:11:02.356543 [-4] AVG Duty = 4922%(X100)
7374 22:11:02.356752
7375 22:11:02.356929 ==DQM 1 ==
7376 22:11:02.359866 Final DQM duty delay cell = 0
7377 22:11:02.362639 [0] MAX Duty = 5156%(X100), DQS PI = 6
7378 22:11:02.366298 [0] MIN Duty = 4969%(X100), DQS PI = 32
7379 22:11:02.369460 [0] AVG Duty = 5062%(X100)
7380 22:11:02.369917
7381 22:11:02.372990 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7382 22:11:02.373410
7383 22:11:02.376248 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7384 22:11:02.380087 [DutyScan_Calibration_Flow] ====Done====
7385 22:11:02.380516
7386 22:11:02.383006 [DutyScan_Calibration_Flow] k_type=2
7387 22:11:02.400531
7388 22:11:02.401133 ==DQ 0 ==
7389 22:11:02.403646 Final DQ duty delay cell = 0
7390 22:11:02.407175 [0] MAX Duty = 5187%(X100), DQS PI = 32
7391 22:11:02.410407 [0] MIN Duty = 4906%(X100), DQS PI = 10
7392 22:11:02.411011 [0] AVG Duty = 5046%(X100)
7393 22:11:02.413821
7394 22:11:02.414259 ==DQ 1 ==
7395 22:11:02.416987 Final DQ duty delay cell = 0
7396 22:11:02.420518 [0] MAX Duty = 5156%(X100), DQS PI = 8
7397 22:11:02.423592 [0] MIN Duty = 4969%(X100), DQS PI = 56
7398 22:11:02.424213 [0] AVG Duty = 5062%(X100)
7399 22:11:02.426663
7400 22:11:02.430089 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7401 22:11:02.430531
7402 22:11:02.433189 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7403 22:11:02.436625 [DutyScan_Calibration_Flow] ====Done====
7404 22:11:02.440132 nWR fixed to 30
7405 22:11:02.440682 [ModeRegInit_LP4] CH0 RK0
7406 22:11:02.443433 [ModeRegInit_LP4] CH0 RK1
7407 22:11:02.446466 [ModeRegInit_LP4] CH1 RK0
7408 22:11:02.449903 [ModeRegInit_LP4] CH1 RK1
7409 22:11:02.450480 match AC timing 5
7410 22:11:02.456494 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7411 22:11:02.459421 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7412 22:11:02.463333 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7413 22:11:02.469456 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7414 22:11:02.473271 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7415 22:11:02.473422 [MiockJmeterHQA]
7416 22:11:02.473540
7417 22:11:02.476269 [DramcMiockJmeter] u1RxGatingPI = 0
7418 22:11:02.479468 0 : 4252, 4027
7419 22:11:02.479599 4 : 4252, 4027
7420 22:11:02.482514 8 : 4252, 4027
7421 22:11:02.482681 12 : 4252, 4027
7422 22:11:02.482787 16 : 4363, 4137
7423 22:11:02.485844 20 : 4365, 4140
7424 22:11:02.485974 24 : 4252, 4027
7425 22:11:02.489395 28 : 4253, 4027
7426 22:11:02.489526 32 : 4252, 4027
7427 22:11:02.492460 36 : 4363, 4138
7428 22:11:02.492591 40 : 4253, 4027
7429 22:11:02.495881 44 : 4363, 4137
7430 22:11:02.496012 48 : 4252, 4029
7431 22:11:02.496115 52 : 4253, 4026
7432 22:11:02.499507 56 : 4250, 4027
7433 22:11:02.499637 60 : 4253, 4029
7434 22:11:02.502851 64 : 4360, 4138
7435 22:11:02.502982 68 : 4250, 4027
7436 22:11:02.505904 72 : 4363, 4140
7437 22:11:02.506035 76 : 4250, 4027
7438 22:11:02.509195 80 : 4250, 4027
7439 22:11:02.509326 84 : 4249, 4027
7440 22:11:02.509431 88 : 4360, 4138
7441 22:11:02.512503 92 : 4250, 201
7442 22:11:02.512635 96 : 4250, 0
7443 22:11:02.515725 100 : 4363, 0
7444 22:11:02.515857 104 : 4252, 0
7445 22:11:02.515960 108 : 4250, 0
7446 22:11:02.519228 112 : 4250, 0
7447 22:11:02.519359 116 : 4250, 0
7448 22:11:02.522710 120 : 4252, 0
7449 22:11:02.522885 124 : 4253, 0
7450 22:11:02.523036 128 : 4250, 0
7451 22:11:02.525562 132 : 4252, 0
7452 22:11:02.525651 136 : 4360, 0
7453 22:11:02.529140 140 : 4250, 0
7454 22:11:02.529223 144 : 4250, 0
7455 22:11:02.529289 148 : 4250, 0
7456 22:11:02.532594 152 : 4361, 0
7457 22:11:02.532677 156 : 4360, 0
7458 22:11:02.535449 160 : 4250, 0
7459 22:11:02.535532 164 : 4250, 0
7460 22:11:02.535598 168 : 4250, 0
7461 22:11:02.538745 172 : 4253, 0
7462 22:11:02.538935 176 : 4250, 0
7463 22:11:02.539045 180 : 4250, 0
7464 22:11:02.542529 184 : 4253, 0
7465 22:11:02.543176 188 : 4360, 0
7466 22:11:02.546191 192 : 4250, 0
7467 22:11:02.546804 196 : 4250, 0
7468 22:11:02.547270 200 : 4250, 0
7469 22:11:02.548863 204 : 4361, 0
7470 22:11:02.549360 208 : 4360, 0
7471 22:11:02.552335 212 : 4250, 0
7472 22:11:02.552897 216 : 4360, 0
7473 22:11:02.553384 220 : 4250, 0
7474 22:11:02.555523 224 : 4250, 452
7475 22:11:02.555943 228 : 4249, 3423
7476 22:11:02.559003 232 : 4250, 4027
7477 22:11:02.559429 236 : 4360, 4137
7478 22:11:02.562272 240 : 4249, 4027
7479 22:11:02.562755 244 : 4249, 4027
7480 22:11:02.565377 248 : 4360, 4137
7481 22:11:02.565796 252 : 4360, 4137
7482 22:11:02.569177 256 : 4247, 4025
7483 22:11:02.569697 260 : 4363, 4140
7484 22:11:02.572558 264 : 4360, 4137
7485 22:11:02.572980 268 : 4250, 4027
7486 22:11:02.573328 272 : 4250, 4027
7487 22:11:02.575569 276 : 4252, 4030
7488 22:11:02.576020 280 : 4249, 4027
7489 22:11:02.578671 284 : 4250, 4027
7490 22:11:02.579140 288 : 4250, 4027
7491 22:11:02.582390 292 : 4253, 4029
7492 22:11:02.583006 296 : 4250, 4026
7493 22:11:02.585238 300 : 4360, 4137
7494 22:11:02.585658 304 : 4360, 4138
7495 22:11:02.588662 308 : 4250, 4027
7496 22:11:02.589087 312 : 4363, 4140
7497 22:11:02.591723 316 : 4360, 4137
7498 22:11:02.592144 320 : 4250, 4027
7499 22:11:02.595393 324 : 4250, 4027
7500 22:11:02.595832 328 : 4252, 4029
7501 22:11:02.596166 332 : 4250, 4026
7502 22:11:02.598476 336 : 4249, 3674
7503 22:11:02.598965 340 : 4250, 1753
7504 22:11:02.599306
7505 22:11:02.602068 MIOCK jitter meter ch=0
7506 22:11:02.602663
7507 22:11:02.605296 1T = (340-92) = 248 dly cells
7508 22:11:02.611817 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7509 22:11:02.612235 ==
7510 22:11:02.615257 Dram Type= 6, Freq= 0, CH_0, rank 0
7511 22:11:02.618748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7512 22:11:02.619276 ==
7513 22:11:02.624823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7514 22:11:02.628126 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7515 22:11:02.632147 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7516 22:11:02.638150 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7517 22:11:02.647418 [CA 0] Center 43 (12~74) winsize 63
7518 22:11:02.650785 [CA 1] Center 43 (13~73) winsize 61
7519 22:11:02.654053 [CA 2] Center 38 (9~68) winsize 60
7520 22:11:02.657428 [CA 3] Center 38 (9~68) winsize 60
7521 22:11:02.660934 [CA 4] Center 36 (7~66) winsize 60
7522 22:11:02.664265 [CA 5] Center 36 (6~66) winsize 61
7523 22:11:02.664681
7524 22:11:02.667700 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7525 22:11:02.668116
7526 22:11:02.671072 [CATrainingPosCal] consider 1 rank data
7527 22:11:02.673898 u2DelayCellTimex100 = 262/100 ps
7528 22:11:02.677681 CA0 delay=43 (12~74),Diff = 7 PI (26 cell)
7529 22:11:02.684076 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7530 22:11:02.687587 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7531 22:11:02.690720 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7532 22:11:02.694155 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7533 22:11:02.697454 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7534 22:11:02.697919
7535 22:11:02.700696 CA PerBit enable=1, Macro0, CA PI delay=36
7536 22:11:02.701135
7537 22:11:02.704148 [CBTSetCACLKResult] CA Dly = 36
7538 22:11:02.707265 CS Dly: 12 (0~43)
7539 22:11:02.710427 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7540 22:11:02.713676 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7541 22:11:02.714134 ==
7542 22:11:02.717521 Dram Type= 6, Freq= 0, CH_0, rank 1
7543 22:11:02.723552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 22:11:02.723969 ==
7545 22:11:02.726884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7546 22:11:02.730218 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7547 22:11:02.737282 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7548 22:11:02.743707 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7549 22:11:02.751546 [CA 0] Center 42 (12~73) winsize 62
7550 22:11:02.754314 [CA 1] Center 43 (13~73) winsize 61
7551 22:11:02.757488 [CA 2] Center 37 (8~67) winsize 60
7552 22:11:02.760693 [CA 3] Center 37 (7~67) winsize 61
7553 22:11:02.764285 [CA 4] Center 35 (6~65) winsize 60
7554 22:11:02.767572 [CA 5] Center 35 (5~65) winsize 61
7555 22:11:02.768083
7556 22:11:02.771128 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7557 22:11:02.771589
7558 22:11:02.773905 [CATrainingPosCal] consider 2 rank data
7559 22:11:02.777477 u2DelayCellTimex100 = 262/100 ps
7560 22:11:02.783977 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7561 22:11:02.787439 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7562 22:11:02.790491 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7563 22:11:02.793834 CA3 delay=38 (9~67),Diff = 3 PI (11 cell)
7564 22:11:02.796932 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7565 22:11:02.800428 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7566 22:11:02.800882
7567 22:11:02.804013 CA PerBit enable=1, Macro0, CA PI delay=35
7568 22:11:02.804456
7569 22:11:02.806918 [CBTSetCACLKResult] CA Dly = 35
7570 22:11:02.810359 CS Dly: 12 (0~44)
7571 22:11:02.813494 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7572 22:11:02.816817 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7573 22:11:02.817229
7574 22:11:02.820146 ----->DramcWriteLeveling(PI) begin...
7575 22:11:02.820584 ==
7576 22:11:02.823349 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 22:11:02.830279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 22:11:02.830773 ==
7579 22:11:02.833666 Write leveling (Byte 0): 36 => 36
7580 22:11:02.836743 Write leveling (Byte 1): 28 => 28
7581 22:11:02.837278 DramcWriteLeveling(PI) end<-----
7582 22:11:02.839911
7583 22:11:02.840432 ==
7584 22:11:02.843920 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 22:11:02.847217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 22:11:02.847633 ==
7587 22:11:02.850498 [Gating] SW mode calibration
7588 22:11:02.857134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7589 22:11:02.860011 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7590 22:11:02.866377 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 22:11:02.869761 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 22:11:02.873235 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 22:11:02.879713 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7594 22:11:02.883156 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7595 22:11:02.886650 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7596 22:11:02.892902 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 22:11:02.896244 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 22:11:02.899294 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 22:11:02.906188 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 22:11:02.909478 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 22:11:02.913143 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
7602 22:11:02.918915 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7603 22:11:02.922401 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7604 22:11:02.925756 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7605 22:11:02.932086 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 22:11:02.935706 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 22:11:02.942015 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 22:11:02.945395 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 22:11:02.949281 1 6 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
7610 22:11:02.955617 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7611 22:11:02.958765 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (1 1) (0 0)
7612 22:11:02.962042 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7613 22:11:02.965359 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 22:11:02.972133 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 22:11:02.975269 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 22:11:02.978574 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7617 22:11:02.985241 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7618 22:11:02.988670 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7619 22:11:02.991866 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7620 22:11:02.998372 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7621 22:11:03.001701 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 22:11:03.005004 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 22:11:03.011359 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 22:11:03.014995 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 22:11:03.017843 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 22:11:03.024687 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 22:11:03.028024 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 22:11:03.031200 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 22:11:03.038171 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 22:11:03.041457 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 22:11:03.044752 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 22:11:03.050900 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7633 22:11:03.054355 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7634 22:11:03.057677 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7635 22:11:03.060880 Total UI for P1: 0, mck2ui 16
7636 22:11:03.064238 best dqsien dly found for B0: ( 1, 9, 10)
7637 22:11:03.071259 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7638 22:11:03.074196 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7639 22:11:03.077530 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 22:11:03.080710 Total UI for P1: 0, mck2ui 16
7641 22:11:03.084077 best dqsien dly found for B1: ( 1, 9, 22)
7642 22:11:03.087203 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7643 22:11:03.093689 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7644 22:11:03.094119
7645 22:11:03.097075 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7646 22:11:03.100444 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7647 22:11:03.103922 [Gating] SW calibration Done
7648 22:11:03.104475 ==
7649 22:11:03.107087 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 22:11:03.110371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 22:11:03.110852 ==
7652 22:11:03.113748 RX Vref Scan: 0
7653 22:11:03.114172
7654 22:11:03.114634 RX Vref 0 -> 0, step: 1
7655 22:11:03.115051
7656 22:11:03.117124 RX Delay 0 -> 252, step: 8
7657 22:11:03.120338 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7658 22:11:03.123931 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7659 22:11:03.130283 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7660 22:11:03.133510 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7661 22:11:03.136879 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7662 22:11:03.139745 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7663 22:11:03.143030 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7664 22:11:03.150088 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7665 22:11:03.153234 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7666 22:11:03.156524 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7667 22:11:03.159523 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7668 22:11:03.166329 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7669 22:11:03.169613 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7670 22:11:03.172959 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7671 22:11:03.176178 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7672 22:11:03.179699 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7673 22:11:03.182565 ==
7674 22:11:03.182765 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 22:11:03.189282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 22:11:03.189435 ==
7677 22:11:03.189556 DQS Delay:
7678 22:11:03.192820 DQS0 = 0, DQS1 = 0
7679 22:11:03.193099 DQM Delay:
7680 22:11:03.196219 DQM0 = 136, DQM1 = 126
7681 22:11:03.196406 DQ Delay:
7682 22:11:03.199675 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7683 22:11:03.202449 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7684 22:11:03.205871 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7685 22:11:03.209410 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7686 22:11:03.209570
7687 22:11:03.209692
7688 22:11:03.209871 ==
7689 22:11:03.212490 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 22:11:03.219146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 22:11:03.219231 ==
7692 22:11:03.219297
7693 22:11:03.219358
7694 22:11:03.219417 TX Vref Scan disable
7695 22:11:03.222750 == TX Byte 0 ==
7696 22:11:03.226228 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7697 22:11:03.232559 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7698 22:11:03.232640 == TX Byte 1 ==
7699 22:11:03.235611 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7700 22:11:03.242186 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7701 22:11:03.242269 ==
7702 22:11:03.245423 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 22:11:03.249152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 22:11:03.249249 ==
7705 22:11:03.262036
7706 22:11:03.265334 TX Vref early break, caculate TX vref
7707 22:11:03.268547 TX Vref=16, minBit 9, minWin=22, winSum=367
7708 22:11:03.271864 TX Vref=18, minBit 10, minWin=22, winSum=373
7709 22:11:03.275131 TX Vref=20, minBit 1, minWin=23, winSum=383
7710 22:11:03.278420 TX Vref=22, minBit 4, minWin=24, winSum=396
7711 22:11:03.285555 TX Vref=24, minBit 0, minWin=24, winSum=401
7712 22:11:03.288406 TX Vref=26, minBit 0, minWin=24, winSum=413
7713 22:11:03.291750 TX Vref=28, minBit 4, minWin=24, winSum=414
7714 22:11:03.294695 TX Vref=30, minBit 0, minWin=24, winSum=406
7715 22:11:03.298506 TX Vref=32, minBit 5, minWin=23, winSum=399
7716 22:11:03.301357 TX Vref=34, minBit 4, minWin=23, winSum=388
7717 22:11:03.308234 [TxChooseVref] Worse bit 4, Min win 24, Win sum 414, Final Vref 28
7718 22:11:03.308348
7719 22:11:03.311549 Final TX Range 0 Vref 28
7720 22:11:03.311631
7721 22:11:03.311695 ==
7722 22:11:03.314529 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 22:11:03.318058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 22:11:03.318140 ==
7725 22:11:03.318205
7726 22:11:03.318265
7727 22:11:03.321228 TX Vref Scan disable
7728 22:11:03.328276 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7729 22:11:03.328364 == TX Byte 0 ==
7730 22:11:03.331322 u2DelayCellOfst[0]=14 cells (4 PI)
7731 22:11:03.334550 u2DelayCellOfst[1]=18 cells (5 PI)
7732 22:11:03.337992 u2DelayCellOfst[2]=14 cells (4 PI)
7733 22:11:03.341119 u2DelayCellOfst[3]=14 cells (4 PI)
7734 22:11:03.344271 u2DelayCellOfst[4]=11 cells (3 PI)
7735 22:11:03.347920 u2DelayCellOfst[5]=0 cells (0 PI)
7736 22:11:03.351374 u2DelayCellOfst[6]=18 cells (5 PI)
7737 22:11:03.354400 u2DelayCellOfst[7]=18 cells (5 PI)
7738 22:11:03.357754 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7739 22:11:03.361030 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7740 22:11:03.364214 == TX Byte 1 ==
7741 22:11:03.367753 u2DelayCellOfst[8]=0 cells (0 PI)
7742 22:11:03.370786 u2DelayCellOfst[9]=0 cells (0 PI)
7743 22:11:03.374029 u2DelayCellOfst[10]=3 cells (1 PI)
7744 22:11:03.377530 u2DelayCellOfst[11]=0 cells (0 PI)
7745 22:11:03.380630 u2DelayCellOfst[12]=11 cells (3 PI)
7746 22:11:03.380741 u2DelayCellOfst[13]=11 cells (3 PI)
7747 22:11:03.384640 u2DelayCellOfst[14]=14 cells (4 PI)
7748 22:11:03.387493 u2DelayCellOfst[15]=7 cells (2 PI)
7749 22:11:03.394270 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7750 22:11:03.397975 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7751 22:11:03.398147 DramC Write-DBI on
7752 22:11:03.400767 ==
7753 22:11:03.404187 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 22:11:03.407108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 22:11:03.407310 ==
7756 22:11:03.407469
7757 22:11:03.407618
7758 22:11:03.411080 TX Vref Scan disable
7759 22:11:03.411321 == TX Byte 0 ==
7760 22:11:03.417569 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7761 22:11:03.417941 == TX Byte 1 ==
7762 22:11:03.421055 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7763 22:11:03.423844 DramC Write-DBI off
7764 22:11:03.424411
7765 22:11:03.424932 [DATLAT]
7766 22:11:03.427530 Freq=1600, CH0 RK0
7767 22:11:03.427952
7768 22:11:03.428286 DATLAT Default: 0xf
7769 22:11:03.430474 0, 0xFFFF, sum = 0
7770 22:11:03.430936 1, 0xFFFF, sum = 0
7771 22:11:03.434039 2, 0xFFFF, sum = 0
7772 22:11:03.434464 3, 0xFFFF, sum = 0
7773 22:11:03.437181 4, 0xFFFF, sum = 0
7774 22:11:03.440600 5, 0xFFFF, sum = 0
7775 22:11:03.441028 6, 0xFFFF, sum = 0
7776 22:11:03.444000 7, 0xFFFF, sum = 0
7777 22:11:03.444483 8, 0xFFFF, sum = 0
7778 22:11:03.447347 9, 0xFFFF, sum = 0
7779 22:11:03.447775 10, 0xFFFF, sum = 0
7780 22:11:03.450821 11, 0xFFFF, sum = 0
7781 22:11:03.451247 12, 0xFFFF, sum = 0
7782 22:11:03.453816 13, 0xFFFF, sum = 0
7783 22:11:03.454245 14, 0x0, sum = 1
7784 22:11:03.457411 15, 0x0, sum = 2
7785 22:11:03.457838 16, 0x0, sum = 3
7786 22:11:03.460399 17, 0x0, sum = 4
7787 22:11:03.460829 best_step = 15
7788 22:11:03.461163
7789 22:11:03.461473 ==
7790 22:11:03.463866 Dram Type= 6, Freq= 0, CH_0, rank 0
7791 22:11:03.467014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7792 22:11:03.470398 ==
7793 22:11:03.470924 RX Vref Scan: 1
7794 22:11:03.471262
7795 22:11:03.473920 Set Vref Range= 24 -> 127
7796 22:11:03.474342
7797 22:11:03.476748 RX Vref 24 -> 127, step: 1
7798 22:11:03.477169
7799 22:11:03.477497 RX Delay 19 -> 252, step: 4
7800 22:11:03.477805
7801 22:11:03.480261 Set Vref, RX VrefLevel [Byte0]: 24
7802 22:11:03.483366 [Byte1]: 24
7803 22:11:03.487502
7804 22:11:03.487920 Set Vref, RX VrefLevel [Byte0]: 25
7805 22:11:03.490334 [Byte1]: 25
7806 22:11:03.495012
7807 22:11:03.495431 Set Vref, RX VrefLevel [Byte0]: 26
7808 22:11:03.498074 [Byte1]: 26
7809 22:11:03.502204
7810 22:11:03.502747 Set Vref, RX VrefLevel [Byte0]: 27
7811 22:11:03.505507 [Byte1]: 27
7812 22:11:03.510336
7813 22:11:03.510929 Set Vref, RX VrefLevel [Byte0]: 28
7814 22:11:03.513457 [Byte1]: 28
7815 22:11:03.517427
7816 22:11:03.517848 Set Vref, RX VrefLevel [Byte0]: 29
7817 22:11:03.521084 [Byte1]: 29
7818 22:11:03.525030
7819 22:11:03.525509 Set Vref, RX VrefLevel [Byte0]: 30
7820 22:11:03.528208 [Byte1]: 30
7821 22:11:03.532706
7822 22:11:03.532935 Set Vref, RX VrefLevel [Byte0]: 31
7823 22:11:03.535874 [Byte1]: 31
7824 22:11:03.539817
7825 22:11:03.540043 Set Vref, RX VrefLevel [Byte0]: 32
7826 22:11:03.543419 [Byte1]: 32
7827 22:11:03.547554
7828 22:11:03.547779 Set Vref, RX VrefLevel [Byte0]: 33
7829 22:11:03.550806 [Byte1]: 33
7830 22:11:03.555267
7831 22:11:03.555527 Set Vref, RX VrefLevel [Byte0]: 34
7832 22:11:03.558350 [Byte1]: 34
7833 22:11:03.562528
7834 22:11:03.562830 Set Vref, RX VrefLevel [Byte0]: 35
7835 22:11:03.566030 [Byte1]: 35
7836 22:11:03.570033
7837 22:11:03.570127 Set Vref, RX VrefLevel [Byte0]: 36
7838 22:11:03.573356 [Byte1]: 36
7839 22:11:03.578208
7840 22:11:03.578313 Set Vref, RX VrefLevel [Byte0]: 37
7841 22:11:03.581185 [Byte1]: 37
7842 22:11:03.585377
7843 22:11:03.585463 Set Vref, RX VrefLevel [Byte0]: 38
7844 22:11:03.588757 [Byte1]: 38
7845 22:11:03.592783
7846 22:11:03.596546 Set Vref, RX VrefLevel [Byte0]: 39
7847 22:11:03.599210 [Byte1]: 39
7848 22:11:03.599307
7849 22:11:03.602909 Set Vref, RX VrefLevel [Byte0]: 40
7850 22:11:03.606069 [Byte1]: 40
7851 22:11:03.606153
7852 22:11:03.609601 Set Vref, RX VrefLevel [Byte0]: 41
7853 22:11:03.612881 [Byte1]: 41
7854 22:11:03.612983
7855 22:11:03.616310 Set Vref, RX VrefLevel [Byte0]: 42
7856 22:11:03.619093 [Byte1]: 42
7857 22:11:03.623106
7858 22:11:03.623211 Set Vref, RX VrefLevel [Byte0]: 43
7859 22:11:03.626404 [Byte1]: 43
7860 22:11:03.630572
7861 22:11:03.630712 Set Vref, RX VrefLevel [Byte0]: 44
7862 22:11:03.634497 [Byte1]: 44
7863 22:11:03.638229
7864 22:11:03.638370 Set Vref, RX VrefLevel [Byte0]: 45
7865 22:11:03.642035 [Byte1]: 45
7866 22:11:03.645812
7867 22:11:03.645991 Set Vref, RX VrefLevel [Byte0]: 46
7868 22:11:03.649129 [Byte1]: 46
7869 22:11:03.653529
7870 22:11:03.653764 Set Vref, RX VrefLevel [Byte0]: 47
7871 22:11:03.656931 [Byte1]: 47
7872 22:11:03.661302
7873 22:11:03.661594 Set Vref, RX VrefLevel [Byte0]: 48
7874 22:11:03.664890 [Byte1]: 48
7875 22:11:03.669111
7876 22:11:03.669616 Set Vref, RX VrefLevel [Byte0]: 49
7877 22:11:03.672548 [Byte1]: 49
7878 22:11:03.676451
7879 22:11:03.676979 Set Vref, RX VrefLevel [Byte0]: 50
7880 22:11:03.679836 [Byte1]: 50
7881 22:11:03.684459
7882 22:11:03.684888 Set Vref, RX VrefLevel [Byte0]: 51
7883 22:11:03.687567 [Byte1]: 51
7884 22:11:03.691932
7885 22:11:03.692473 Set Vref, RX VrefLevel [Byte0]: 52
7886 22:11:03.695010 [Byte1]: 52
7887 22:11:03.698987
7888 22:11:03.699083 Set Vref, RX VrefLevel [Byte0]: 53
7889 22:11:03.702019 [Byte1]: 53
7890 22:11:03.706695
7891 22:11:03.706783 Set Vref, RX VrefLevel [Byte0]: 54
7892 22:11:03.709864 [Byte1]: 54
7893 22:11:03.714025
7894 22:11:03.714113 Set Vref, RX VrefLevel [Byte0]: 55
7895 22:11:03.717514 [Byte1]: 55
7896 22:11:03.721616
7897 22:11:03.721712 Set Vref, RX VrefLevel [Byte0]: 56
7898 22:11:03.725343 [Byte1]: 56
7899 22:11:03.729310
7900 22:11:03.729422 Set Vref, RX VrefLevel [Byte0]: 57
7901 22:11:03.732618 [Byte1]: 57
7902 22:11:03.737200
7903 22:11:03.737323 Set Vref, RX VrefLevel [Byte0]: 58
7904 22:11:03.740021 [Byte1]: 58
7905 22:11:03.745016
7906 22:11:03.745171 Set Vref, RX VrefLevel [Byte0]: 59
7907 22:11:03.747576 [Byte1]: 59
7908 22:11:03.752235
7909 22:11:03.752397 Set Vref, RX VrefLevel [Byte0]: 60
7910 22:11:03.755436 [Byte1]: 60
7911 22:11:03.760246
7912 22:11:03.760466 Set Vref, RX VrefLevel [Byte0]: 61
7913 22:11:03.762900 [Byte1]: 61
7914 22:11:03.767264
7915 22:11:03.767532 Set Vref, RX VrefLevel [Byte0]: 62
7916 22:11:03.770689 [Byte1]: 62
7917 22:11:03.775267
7918 22:11:03.775666 Set Vref, RX VrefLevel [Byte0]: 63
7919 22:11:03.778292 [Byte1]: 63
7920 22:11:03.782884
7921 22:11:03.783302 Set Vref, RX VrefLevel [Byte0]: 64
7922 22:11:03.786139 [Byte1]: 64
7923 22:11:03.790372
7924 22:11:03.790826 Set Vref, RX VrefLevel [Byte0]: 65
7925 22:11:03.793824 [Byte1]: 65
7926 22:11:03.798248
7927 22:11:03.798822 Set Vref, RX VrefLevel [Byte0]: 66
7928 22:11:03.800908 [Byte1]: 66
7929 22:11:03.805739
7930 22:11:03.806383 Set Vref, RX VrefLevel [Byte0]: 67
7931 22:11:03.808841 [Byte1]: 67
7932 22:11:03.812753
7933 22:11:03.813334 Set Vref, RX VrefLevel [Byte0]: 68
7934 22:11:03.816076 [Byte1]: 68
7935 22:11:03.820517
7936 22:11:03.820938 Set Vref, RX VrefLevel [Byte0]: 69
7937 22:11:03.827055 [Byte1]: 69
7938 22:11:03.827475
7939 22:11:03.830449 Set Vref, RX VrefLevel [Byte0]: 70
7940 22:11:03.833460 [Byte1]: 70
7941 22:11:03.833881
7942 22:11:03.836836 Set Vref, RX VrefLevel [Byte0]: 71
7943 22:11:03.840516 [Byte1]: 71
7944 22:11:03.840983
7945 22:11:03.843723 Set Vref, RX VrefLevel [Byte0]: 72
7946 22:11:03.847082 [Byte1]: 72
7947 22:11:03.850697
7948 22:11:03.851115 Set Vref, RX VrefLevel [Byte0]: 73
7949 22:11:03.854054 [Byte1]: 73
7950 22:11:03.858333
7951 22:11:03.858796 Set Vref, RX VrefLevel [Byte0]: 74
7952 22:11:03.861728 [Byte1]: 74
7953 22:11:03.866004
7954 22:11:03.866425 Set Vref, RX VrefLevel [Byte0]: 75
7955 22:11:03.869157 [Byte1]: 75
7956 22:11:03.873859
7957 22:11:03.874277 Set Vref, RX VrefLevel [Byte0]: 76
7958 22:11:03.876996 [Byte1]: 76
7959 22:11:03.880922
7960 22:11:03.881341 Set Vref, RX VrefLevel [Byte0]: 77
7961 22:11:03.884376 [Byte1]: 77
7962 22:11:03.888890
7963 22:11:03.889309 Set Vref, RX VrefLevel [Byte0]: 78
7964 22:11:03.891839 [Byte1]: 78
7965 22:11:03.896602
7966 22:11:03.897025 Set Vref, RX VrefLevel [Byte0]: 79
7967 22:11:03.899240 [Byte1]: 79
7968 22:11:03.903583
7969 22:11:03.904002 Set Vref, RX VrefLevel [Byte0]: 80
7970 22:11:03.906724 [Byte1]: 80
7971 22:11:03.911514
7972 22:11:03.911934 Final RX Vref Byte 0 = 62 to rank0
7973 22:11:03.914540 Final RX Vref Byte 1 = 56 to rank0
7974 22:11:03.918077 Final RX Vref Byte 0 = 62 to rank1
7975 22:11:03.920980 Final RX Vref Byte 1 = 56 to rank1==
7976 22:11:03.924582 Dram Type= 6, Freq= 0, CH_0, rank 0
7977 22:11:03.931368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 22:11:03.931790 ==
7979 22:11:03.932121 DQS Delay:
7980 22:11:03.934358 DQS0 = 0, DQS1 = 0
7981 22:11:03.934847 DQM Delay:
7982 22:11:03.935188 DQM0 = 133, DQM1 = 123
7983 22:11:03.937600 DQ Delay:
7984 22:11:03.941167 DQ0 =130, DQ1 =134, DQ2 =130, DQ3 =132
7985 22:11:03.944162 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
7986 22:11:03.947526 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
7987 22:11:03.951070 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
7988 22:11:03.951490
7989 22:11:03.951954
7990 22:11:03.952320
7991 22:11:03.954233 [DramC_TX_OE_Calibration] TA2
7992 22:11:03.957524 Original DQ_B0 (3 6) =30, OEN = 27
7993 22:11:03.960742 Original DQ_B1 (3 6) =30, OEN = 27
7994 22:11:03.964252 24, 0x0, End_B0=24 End_B1=24
7995 22:11:03.967551 25, 0x0, End_B0=25 End_B1=25
7996 22:11:03.967980 26, 0x0, End_B0=26 End_B1=26
7997 22:11:03.970460 27, 0x0, End_B0=27 End_B1=27
7998 22:11:03.974057 28, 0x0, End_B0=28 End_B1=28
7999 22:11:03.976583 29, 0x0, End_B0=29 End_B1=29
8000 22:11:03.976666 30, 0x0, End_B0=30 End_B1=30
8001 22:11:03.980031 31, 0x4141, End_B0=30 End_B1=30
8002 22:11:03.983824 Byte0 end_step=30 best_step=27
8003 22:11:03.986860 Byte1 end_step=30 best_step=27
8004 22:11:03.990244 Byte0 TX OE(2T, 0.5T) = (3, 3)
8005 22:11:03.993436 Byte1 TX OE(2T, 0.5T) = (3, 3)
8006 22:11:03.993604
8007 22:11:03.993697
8008 22:11:04.000423 [DQSOSCAuto] RK0, (LSB)MR18= 0x2314, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8009 22:11:04.003329 CH0 RK0: MR19=303, MR18=2314
8010 22:11:04.010141 CH0_RK0: MR19=0x303, MR18=0x2314, DQSOSC=392, MR23=63, INC=24, DEC=16
8011 22:11:04.010326
8012 22:11:04.013052 ----->DramcWriteLeveling(PI) begin...
8013 22:11:04.013190 ==
8014 22:11:04.016936 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 22:11:04.020441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 22:11:04.020679 ==
8017 22:11:04.023583 Write leveling (Byte 0): 37 => 37
8018 22:11:04.026608 Write leveling (Byte 1): 28 => 28
8019 22:11:04.029795 DramcWriteLeveling(PI) end<-----
8020 22:11:04.030089
8021 22:11:04.030264 ==
8022 22:11:04.033141 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 22:11:04.036832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 22:11:04.040100 ==
8025 22:11:04.040502 [Gating] SW mode calibration
8026 22:11:04.050439 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8027 22:11:04.053229 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8028 22:11:04.056488 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 22:11:04.063362 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 22:11:04.066244 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 22:11:04.069911 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 22:11:04.076524 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
8033 22:11:04.079519 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8034 22:11:04.083400 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 22:11:04.090116 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 22:11:04.093479 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 22:11:04.096658 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 22:11:04.102804 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8039 22:11:04.105960 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8040 22:11:04.109605 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 1)
8041 22:11:04.116158 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8042 22:11:04.119514 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 22:11:04.122683 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 22:11:04.129501 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 22:11:04.132507 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 22:11:04.136182 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 22:11:04.142093 1 6 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8048 22:11:04.145510 1 6 16 | B1->B0 | 2c2b 4545 | 1 0 | (0 0) (0 0)
8049 22:11:04.149003 1 6 20 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
8050 22:11:04.155582 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 22:11:04.158230 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 22:11:04.161245 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 22:11:04.168065 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 22:11:04.171315 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8055 22:11:04.174833 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8056 22:11:04.181459 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8057 22:11:04.184811 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8058 22:11:04.188285 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 22:11:04.194673 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 22:11:04.197941 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 22:11:04.201173 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 22:11:04.207890 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 22:11:04.210906 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 22:11:04.214259 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 22:11:04.221134 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 22:11:04.224398 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 22:11:04.228091 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 22:11:04.234696 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 22:11:04.237950 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 22:11:04.241217 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 22:11:04.247461 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8072 22:11:04.251254 Total UI for P1: 0, mck2ui 16
8073 22:11:04.254524 best dqsien dly found for B0: ( 1, 9, 10)
8074 22:11:04.257923 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8075 22:11:04.260964 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8076 22:11:04.267657 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 22:11:04.268156 Total UI for P1: 0, mck2ui 16
8078 22:11:04.273920 best dqsien dly found for B1: ( 1, 9, 18)
8079 22:11:04.277324 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8080 22:11:04.280530 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8081 22:11:04.280613
8082 22:11:04.283799 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8083 22:11:04.286853 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8084 22:11:04.290279 [Gating] SW calibration Done
8085 22:11:04.290350 ==
8086 22:11:04.293621 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 22:11:04.297260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 22:11:04.297342 ==
8089 22:11:04.300712 RX Vref Scan: 0
8090 22:11:04.300793
8091 22:11:04.303562 RX Vref 0 -> 0, step: 1
8092 22:11:04.303649
8093 22:11:04.303718 RX Delay 0 -> 252, step: 8
8094 22:11:04.310206 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8095 22:11:04.313622 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8096 22:11:04.317207 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8097 22:11:04.320528 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8098 22:11:04.323550 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8099 22:11:04.329957 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8100 22:11:04.333326 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8101 22:11:04.336725 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8102 22:11:04.340039 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8103 22:11:04.343595 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8104 22:11:04.349955 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8105 22:11:04.353228 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8106 22:11:04.356782 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8107 22:11:04.360599 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8108 22:11:04.363309 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8109 22:11:04.370162 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8110 22:11:04.370584 ==
8111 22:11:04.373560 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 22:11:04.376436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 22:11:04.376863 ==
8114 22:11:04.377197 DQS Delay:
8115 22:11:04.379713 DQS0 = 0, DQS1 = 0
8116 22:11:04.380290 DQM Delay:
8117 22:11:04.383372 DQM0 = 133, DQM1 = 129
8118 22:11:04.383891 DQ Delay:
8119 22:11:04.386645 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8120 22:11:04.390314 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8121 22:11:04.393136 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8122 22:11:04.396289 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8123 22:11:04.396836
8124 22:11:04.399956
8125 22:11:04.400452 ==
8126 22:11:04.402923 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 22:11:04.406351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 22:11:04.406932 ==
8129 22:11:04.407360
8130 22:11:04.407741
8131 22:11:04.409497 TX Vref Scan disable
8132 22:11:04.409904 == TX Byte 0 ==
8133 22:11:04.416342 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8134 22:11:04.419737 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8135 22:11:04.420250 == TX Byte 1 ==
8136 22:11:04.426359 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8137 22:11:04.429261 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8138 22:11:04.429761 ==
8139 22:11:04.432593 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 22:11:04.435803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 22:11:04.436238 ==
8142 22:11:04.451919
8143 22:11:04.455228 TX Vref early break, caculate TX vref
8144 22:11:04.458695 TX Vref=16, minBit 8, minWin=22, winSum=373
8145 22:11:04.461626 TX Vref=18, minBit 5, minWin=22, winSum=381
8146 22:11:04.464952 TX Vref=20, minBit 2, minWin=23, winSum=391
8147 22:11:04.468631 TX Vref=22, minBit 1, minWin=24, winSum=399
8148 22:11:04.472041 TX Vref=24, minBit 4, minWin=24, winSum=406
8149 22:11:04.478390 TX Vref=26, minBit 4, minWin=24, winSum=410
8150 22:11:04.481538 TX Vref=28, minBit 0, minWin=24, winSum=411
8151 22:11:04.484770 TX Vref=30, minBit 0, minWin=24, winSum=403
8152 22:11:04.488062 TX Vref=32, minBit 0, minWin=24, winSum=400
8153 22:11:04.491530 TX Vref=34, minBit 2, minWin=23, winSum=391
8154 22:11:04.497893 TX Vref=36, minBit 0, minWin=23, winSum=382
8155 22:11:04.501761 [TxChooseVref] Worse bit 0, Min win 24, Win sum 411, Final Vref 28
8156 22:11:04.502316
8157 22:11:04.505180 Final TX Range 0 Vref 28
8158 22:11:04.505653
8159 22:11:04.505993 ==
8160 22:11:04.507871 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 22:11:04.511003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 22:11:04.511425 ==
8163 22:11:04.514693
8164 22:11:04.515106
8165 22:11:04.515435 TX Vref Scan disable
8166 22:11:04.521221 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8167 22:11:04.521640 == TX Byte 0 ==
8168 22:11:04.525026 u2DelayCellOfst[0]=14 cells (4 PI)
8169 22:11:04.527815 u2DelayCellOfst[1]=18 cells (5 PI)
8170 22:11:04.531293 u2DelayCellOfst[2]=14 cells (4 PI)
8171 22:11:04.534668 u2DelayCellOfst[3]=14 cells (4 PI)
8172 22:11:04.537591 u2DelayCellOfst[4]=11 cells (3 PI)
8173 22:11:04.540761 u2DelayCellOfst[5]=0 cells (0 PI)
8174 22:11:04.544070 u2DelayCellOfst[6]=18 cells (5 PI)
8175 22:11:04.547626 u2DelayCellOfst[7]=22 cells (6 PI)
8176 22:11:04.550338 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8177 22:11:04.553812 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8178 22:11:04.557404 == TX Byte 1 ==
8179 22:11:04.560938 u2DelayCellOfst[8]=0 cells (0 PI)
8180 22:11:04.563425 u2DelayCellOfst[9]=3 cells (1 PI)
8181 22:11:04.566803 u2DelayCellOfst[10]=7 cells (2 PI)
8182 22:11:04.570079 u2DelayCellOfst[11]=3 cells (1 PI)
8183 22:11:04.573332 u2DelayCellOfst[12]=11 cells (3 PI)
8184 22:11:04.576877 u2DelayCellOfst[13]=14 cells (4 PI)
8185 22:11:04.576959 u2DelayCellOfst[14]=18 cells (5 PI)
8186 22:11:04.580612 u2DelayCellOfst[15]=11 cells (3 PI)
8187 22:11:04.586962 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8188 22:11:04.590304 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8189 22:11:04.593795 DramC Write-DBI on
8190 22:11:04.593877 ==
8191 22:11:04.596885 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 22:11:04.599914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 22:11:04.599995 ==
8194 22:11:04.600059
8195 22:11:04.600118
8196 22:11:04.603709 TX Vref Scan disable
8197 22:11:04.603790 == TX Byte 0 ==
8198 22:11:04.610462 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8199 22:11:04.610572 == TX Byte 1 ==
8200 22:11:04.613756 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8201 22:11:04.616912 DramC Write-DBI off
8202 22:11:04.616993
8203 22:11:04.617057 [DATLAT]
8204 22:11:04.619998 Freq=1600, CH0 RK1
8205 22:11:04.620079
8206 22:11:04.620143 DATLAT Default: 0xf
8207 22:11:04.623643 0, 0xFFFF, sum = 0
8208 22:11:04.623730 1, 0xFFFF, sum = 0
8209 22:11:04.626452 2, 0xFFFF, sum = 0
8210 22:11:04.626555 3, 0xFFFF, sum = 0
8211 22:11:04.629806 4, 0xFFFF, sum = 0
8212 22:11:04.633417 5, 0xFFFF, sum = 0
8213 22:11:04.633520 6, 0xFFFF, sum = 0
8214 22:11:04.636378 7, 0xFFFF, sum = 0
8215 22:11:04.636476 8, 0xFFFF, sum = 0
8216 22:11:04.639951 9, 0xFFFF, sum = 0
8217 22:11:04.640029 10, 0xFFFF, sum = 0
8218 22:11:04.643418 11, 0xFFFF, sum = 0
8219 22:11:04.643488 12, 0xFFFF, sum = 0
8220 22:11:04.646856 13, 0xFFFF, sum = 0
8221 22:11:04.646925 14, 0x0, sum = 1
8222 22:11:04.649750 15, 0x0, sum = 2
8223 22:11:04.649822 16, 0x0, sum = 3
8224 22:11:04.653203 17, 0x0, sum = 4
8225 22:11:04.653271 best_step = 15
8226 22:11:04.653329
8227 22:11:04.653385 ==
8228 22:11:04.656467 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 22:11:04.659947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 22:11:04.663520 ==
8231 22:11:04.663608 RX Vref Scan: 0
8232 22:11:04.663681
8233 22:11:04.666357 RX Vref 0 -> 0, step: 1
8234 22:11:04.666441
8235 22:11:04.669888 RX Delay 11 -> 252, step: 4
8236 22:11:04.673489 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8237 22:11:04.676696 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8238 22:11:04.679933 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8239 22:11:04.686819 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8240 22:11:04.690250 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8241 22:11:04.692925 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8242 22:11:04.696628 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8243 22:11:04.700026 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8244 22:11:04.706684 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8245 22:11:04.709748 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8246 22:11:04.712948 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8247 22:11:04.715991 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8248 22:11:04.722585 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8249 22:11:04.725958 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8250 22:11:04.729580 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8251 22:11:04.732487 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8252 22:11:04.732945 ==
8253 22:11:04.736396 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 22:11:04.739230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 22:11:04.742696 ==
8256 22:11:04.743190 DQS Delay:
8257 22:11:04.743597 DQS0 = 0, DQS1 = 0
8258 22:11:04.745959 DQM Delay:
8259 22:11:04.746331 DQM0 = 130, DQM1 = 125
8260 22:11:04.749236 DQ Delay:
8261 22:11:04.752602 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8262 22:11:04.755663 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8263 22:11:04.759060 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8264 22:11:04.762350 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8265 22:11:04.762881
8266 22:11:04.763216
8267 22:11:04.763523
8268 22:11:04.765938 [DramC_TX_OE_Calibration] TA2
8269 22:11:04.769202 Original DQ_B0 (3 6) =30, OEN = 27
8270 22:11:04.772866 Original DQ_B1 (3 6) =30, OEN = 27
8271 22:11:04.775820 24, 0x0, End_B0=24 End_B1=24
8272 22:11:04.776270 25, 0x0, End_B0=25 End_B1=25
8273 22:11:04.778881 26, 0x0, End_B0=26 End_B1=26
8274 22:11:04.782669 27, 0x0, End_B0=27 End_B1=27
8275 22:11:04.785934 28, 0x0, End_B0=28 End_B1=28
8276 22:11:04.786359 29, 0x0, End_B0=29 End_B1=29
8277 22:11:04.789262 30, 0x0, End_B0=30 End_B1=30
8278 22:11:04.792139 31, 0x4545, End_B0=30 End_B1=30
8279 22:11:04.795742 Byte0 end_step=30 best_step=27
8280 22:11:04.799100 Byte1 end_step=30 best_step=27
8281 22:11:04.802483 Byte0 TX OE(2T, 0.5T) = (3, 3)
8282 22:11:04.802945 Byte1 TX OE(2T, 0.5T) = (3, 3)
8283 22:11:04.805340
8284 22:11:04.805753
8285 22:11:04.812072 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 395 ps
8286 22:11:04.815738 CH0 RK1: MR19=303, MR18=1D01
8287 22:11:04.822538 CH0_RK1: MR19=0x303, MR18=0x1D01, DQSOSC=395, MR23=63, INC=23, DEC=15
8288 22:11:04.825519 [RxdqsGatingPostProcess] freq 1600
8289 22:11:04.829056 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8290 22:11:04.831842 best DQS0 dly(2T, 0.5T) = (1, 1)
8291 22:11:04.835324 best DQS1 dly(2T, 0.5T) = (1, 1)
8292 22:11:04.838522 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8293 22:11:04.841967 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8294 22:11:04.844903 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 22:11:04.848678 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 22:11:04.851808 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 22:11:04.855003 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 22:11:04.858397 Pre-setting of DQS Precalculation
8299 22:11:04.861743 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8300 22:11:04.862033 ==
8301 22:11:04.865025 Dram Type= 6, Freq= 0, CH_1, rank 0
8302 22:11:04.868211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 22:11:04.871535 ==
8304 22:11:04.875069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8305 22:11:04.878499 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8306 22:11:04.885037 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8307 22:11:04.891232 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8308 22:11:04.898724 [CA 0] Center 41 (12~71) winsize 60
8309 22:11:04.902129 [CA 1] Center 41 (12~71) winsize 60
8310 22:11:04.904941 [CA 2] Center 37 (8~66) winsize 59
8311 22:11:04.908244 [CA 3] Center 36 (7~65) winsize 59
8312 22:11:04.911693 [CA 4] Center 36 (7~66) winsize 60
8313 22:11:04.915385 [CA 5] Center 36 (7~66) winsize 60
8314 22:11:04.915805
8315 22:11:04.918421 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8316 22:11:04.918865
8317 22:11:04.921646 [CATrainingPosCal] consider 1 rank data
8318 22:11:04.925013 u2DelayCellTimex100 = 262/100 ps
8319 22:11:04.931778 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8320 22:11:04.934681 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8321 22:11:04.937948 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8322 22:11:04.941659 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8323 22:11:04.944528 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8324 22:11:04.948271 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8325 22:11:04.948687
8326 22:11:04.951369 CA PerBit enable=1, Macro0, CA PI delay=36
8327 22:11:04.951786
8328 22:11:04.954501 [CBTSetCACLKResult] CA Dly = 36
8329 22:11:04.958295 CS Dly: 9 (0~40)
8330 22:11:04.961136 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8331 22:11:04.964406 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8332 22:11:04.964842 ==
8333 22:11:04.967577 Dram Type= 6, Freq= 0, CH_1, rank 1
8334 22:11:04.974395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 22:11:04.974933 ==
8336 22:11:04.977619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 22:11:04.980958 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 22:11:04.987871 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 22:11:04.993874 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 22:11:05.001501 [CA 0] Center 42 (12~72) winsize 61
8341 22:11:05.004793 [CA 1] Center 42 (13~72) winsize 60
8342 22:11:05.008303 [CA 2] Center 37 (8~67) winsize 60
8343 22:11:05.011589 [CA 3] Center 36 (7~66) winsize 60
8344 22:11:05.015096 [CA 4] Center 37 (8~67) winsize 60
8345 22:11:05.018176 [CA 5] Center 37 (7~67) winsize 61
8346 22:11:05.018617
8347 22:11:05.021766 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8348 22:11:05.022187
8349 22:11:05.024849 [CATrainingPosCal] consider 2 rank data
8350 22:11:05.027991 u2DelayCellTimex100 = 262/100 ps
8351 22:11:05.034674 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8352 22:11:05.037790 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8353 22:11:05.041164 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8354 22:11:05.044615 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8355 22:11:05.047977 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8356 22:11:05.051229 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8357 22:11:05.051653
8358 22:11:05.054236 CA PerBit enable=1, Macro0, CA PI delay=36
8359 22:11:05.054698
8360 22:11:05.057417 [CBTSetCACLKResult] CA Dly = 36
8361 22:11:05.060716 CS Dly: 11 (0~44)
8362 22:11:05.064542 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 22:11:05.067717 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 22:11:05.068137
8365 22:11:05.070887 ----->DramcWriteLeveling(PI) begin...
8366 22:11:05.071325 ==
8367 22:11:05.074354 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 22:11:05.080885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 22:11:05.081335 ==
8370 22:11:05.083648 Write leveling (Byte 0): 23 => 23
8371 22:11:05.087103 Write leveling (Byte 1): 28 => 28
8372 22:11:05.090521 DramcWriteLeveling(PI) end<-----
8373 22:11:05.090970
8374 22:11:05.091299 ==
8375 22:11:05.094244 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 22:11:05.097269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 22:11:05.097692 ==
8378 22:11:05.100910 [Gating] SW mode calibration
8379 22:11:05.107338 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8380 22:11:05.110567 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8381 22:11:05.117328 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 22:11:05.120677 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 22:11:05.123618 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 22:11:05.130494 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8385 22:11:05.133943 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 22:11:05.137150 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 22:11:05.143411 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 22:11:05.146824 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 22:11:05.150231 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 22:11:05.156781 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 22:11:05.160222 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8392 22:11:05.163339 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8393 22:11:05.169909 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8394 22:11:05.172927 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 22:11:05.176611 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 22:11:05.183039 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 22:11:05.186734 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 22:11:05.189829 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 22:11:05.196246 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8400 22:11:05.199833 1 6 12 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
8401 22:11:05.203113 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 22:11:05.209345 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 22:11:05.212697 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 22:11:05.216445 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 22:11:05.223235 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 22:11:05.226325 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 22:11:05.229187 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8408 22:11:05.235859 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8409 22:11:05.239454 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8410 22:11:05.242704 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 22:11:05.248775 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 22:11:05.252246 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 22:11:05.255191 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 22:11:05.261870 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 22:11:05.265344 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 22:11:05.268795 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 22:11:05.275799 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 22:11:05.279288 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 22:11:05.281868 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 22:11:05.288464 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 22:11:05.291535 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 22:11:05.295022 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 22:11:05.301867 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8424 22:11:05.304953 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8425 22:11:05.308386 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8426 22:11:05.311840 Total UI for P1: 0, mck2ui 16
8427 22:11:05.315112 best dqsien dly found for B0: ( 1, 9, 10)
8428 22:11:05.321395 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 22:11:05.324733 Total UI for P1: 0, mck2ui 16
8430 22:11:05.328318 best dqsien dly found for B1: ( 1, 9, 14)
8431 22:11:05.331360 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8432 22:11:05.334484 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8433 22:11:05.334941
8434 22:11:05.338183 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8435 22:11:05.341345 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8436 22:11:05.344553 [Gating] SW calibration Done
8437 22:11:05.345083 ==
8438 22:11:05.347762 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 22:11:05.351097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 22:11:05.351543 ==
8441 22:11:05.354270 RX Vref Scan: 0
8442 22:11:05.354735
8443 22:11:05.357616 RX Vref 0 -> 0, step: 1
8444 22:11:05.358042
8445 22:11:05.358375 RX Delay 0 -> 252, step: 8
8446 22:11:05.364437 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8447 22:11:05.367764 iDelay=208, Bit 1, Center 135 (88 ~ 183) 96
8448 22:11:05.371251 iDelay=208, Bit 2, Center 131 (80 ~ 183) 104
8449 22:11:05.374447 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8450 22:11:05.377327 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8451 22:11:05.384252 iDelay=208, Bit 5, Center 155 (104 ~ 207) 104
8452 22:11:05.387308 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8453 22:11:05.390629 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8454 22:11:05.393813 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8455 22:11:05.396946 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8456 22:11:05.403848 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8457 22:11:05.407336 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8458 22:11:05.410375 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8459 22:11:05.413960 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8460 22:11:05.420459 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8461 22:11:05.423622 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8462 22:11:05.424039 ==
8463 22:11:05.427068 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 22:11:05.430547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 22:11:05.431026 ==
8466 22:11:05.433885 DQS Delay:
8467 22:11:05.434303 DQS0 = 0, DQS1 = 0
8468 22:11:05.434668 DQM Delay:
8469 22:11:05.436774 DQM0 = 140, DQM1 = 129
8470 22:11:05.437191 DQ Delay:
8471 22:11:05.440130 DQ0 =143, DQ1 =135, DQ2 =131, DQ3 =139
8472 22:11:05.443522 DQ4 =135, DQ5 =155, DQ6 =147, DQ7 =135
8473 22:11:05.447213 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8474 22:11:05.453289 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8475 22:11:05.453705
8476 22:11:05.454038
8477 22:11:05.454343 ==
8478 22:11:05.456878 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 22:11:05.459932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 22:11:05.460368 ==
8481 22:11:05.460702
8482 22:11:05.461012
8483 22:11:05.463027 TX Vref Scan disable
8484 22:11:05.463449 == TX Byte 0 ==
8485 22:11:05.470085 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8486 22:11:05.473162 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8487 22:11:05.476543 == TX Byte 1 ==
8488 22:11:05.479948 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8489 22:11:05.483338 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8490 22:11:05.483761 ==
8491 22:11:05.486527 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 22:11:05.489828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 22:11:05.492826 ==
8494 22:11:05.504109
8495 22:11:05.507094 TX Vref early break, caculate TX vref
8496 22:11:05.510570 TX Vref=16, minBit 0, minWin=21, winSum=371
8497 22:11:05.513564 TX Vref=18, minBit 5, minWin=22, winSum=381
8498 22:11:05.517184 TX Vref=20, minBit 0, minWin=22, winSum=393
8499 22:11:05.520529 TX Vref=22, minBit 0, minWin=24, winSum=401
8500 22:11:05.523525 TX Vref=24, minBit 0, minWin=25, winSum=413
8501 22:11:05.530296 TX Vref=26, minBit 0, minWin=24, winSum=418
8502 22:11:05.533708 TX Vref=28, minBit 0, minWin=25, winSum=423
8503 22:11:05.537026 TX Vref=30, minBit 1, minWin=24, winSum=413
8504 22:11:05.540432 TX Vref=32, minBit 1, minWin=24, winSum=405
8505 22:11:05.543266 TX Vref=34, minBit 0, minWin=23, winSum=394
8506 22:11:05.550193 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8507 22:11:05.550642
8508 22:11:05.553597 Final TX Range 0 Vref 28
8509 22:11:05.554119
8510 22:11:05.554457 ==
8511 22:11:05.556642 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 22:11:05.559789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 22:11:05.560214 ==
8514 22:11:05.560574
8515 22:11:05.562938
8516 22:11:05.563522 TX Vref Scan disable
8517 22:11:05.569596 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8518 22:11:05.570127 == TX Byte 0 ==
8519 22:11:05.572678 u2DelayCellOfst[0]=18 cells (5 PI)
8520 22:11:05.576080 u2DelayCellOfst[1]=14 cells (4 PI)
8521 22:11:05.579478 u2DelayCellOfst[2]=0 cells (0 PI)
8522 22:11:05.582657 u2DelayCellOfst[3]=7 cells (2 PI)
8523 22:11:05.586507 u2DelayCellOfst[4]=11 cells (3 PI)
8524 22:11:05.589150 u2DelayCellOfst[5]=22 cells (6 PI)
8525 22:11:05.592532 u2DelayCellOfst[6]=22 cells (6 PI)
8526 22:11:05.595849 u2DelayCellOfst[7]=7 cells (2 PI)
8527 22:11:05.599308 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8528 22:11:05.602661 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8529 22:11:05.605537 == TX Byte 1 ==
8530 22:11:05.609516 u2DelayCellOfst[8]=0 cells (0 PI)
8531 22:11:05.612510 u2DelayCellOfst[9]=3 cells (1 PI)
8532 22:11:05.615500 u2DelayCellOfst[10]=11 cells (3 PI)
8533 22:11:05.619326 u2DelayCellOfst[11]=3 cells (1 PI)
8534 22:11:05.622187 u2DelayCellOfst[12]=14 cells (4 PI)
8535 22:11:05.626246 u2DelayCellOfst[13]=18 cells (5 PI)
8536 22:11:05.629236 u2DelayCellOfst[14]=18 cells (5 PI)
8537 22:11:05.629820 u2DelayCellOfst[15]=14 cells (4 PI)
8538 22:11:05.635529 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8539 22:11:05.638451 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8540 22:11:05.641581 DramC Write-DBI on
8541 22:11:05.641994 ==
8542 22:11:05.645052 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 22:11:05.648562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 22:11:05.648981 ==
8545 22:11:05.649309
8546 22:11:05.649617
8547 22:11:05.651896 TX Vref Scan disable
8548 22:11:05.652312 == TX Byte 0 ==
8549 22:11:05.658654 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8550 22:11:05.659076 == TX Byte 1 ==
8551 22:11:05.664652 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8552 22:11:05.665073 DramC Write-DBI off
8553 22:11:05.665399
8554 22:11:05.665705 [DATLAT]
8555 22:11:05.668450 Freq=1600, CH1 RK0
8556 22:11:05.668868
8557 22:11:05.671417 DATLAT Default: 0xf
8558 22:11:05.671832 0, 0xFFFF, sum = 0
8559 22:11:05.674705 1, 0xFFFF, sum = 0
8560 22:11:05.675130 2, 0xFFFF, sum = 0
8561 22:11:05.678048 3, 0xFFFF, sum = 0
8562 22:11:05.678470 4, 0xFFFF, sum = 0
8563 22:11:05.681209 5, 0xFFFF, sum = 0
8564 22:11:05.681643 6, 0xFFFF, sum = 0
8565 22:11:05.684850 7, 0xFFFF, sum = 0
8566 22:11:05.685272 8, 0xFFFF, sum = 0
8567 22:11:05.688100 9, 0xFFFF, sum = 0
8568 22:11:05.688523 10, 0xFFFF, sum = 0
8569 22:11:05.691302 11, 0xFFFF, sum = 0
8570 22:11:05.691724 12, 0xFFFF, sum = 0
8571 22:11:05.694569 13, 0xFFFF, sum = 0
8572 22:11:05.695025 14, 0x0, sum = 1
8573 22:11:05.697710 15, 0x0, sum = 2
8574 22:11:05.698133 16, 0x0, sum = 3
8575 22:11:05.700848 17, 0x0, sum = 4
8576 22:11:05.701270 best_step = 15
8577 22:11:05.701597
8578 22:11:05.701902 ==
8579 22:11:05.704947 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 22:11:05.710886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 22:11:05.711305 ==
8582 22:11:05.711635 RX Vref Scan: 1
8583 22:11:05.711940
8584 22:11:05.714198 Set Vref Range= 24 -> 127
8585 22:11:05.714662
8586 22:11:05.717666 RX Vref 24 -> 127, step: 1
8587 22:11:05.718081
8588 22:11:05.721328 RX Delay 11 -> 252, step: 4
8589 22:11:05.721857
8590 22:11:05.724184 Set Vref, RX VrefLevel [Byte0]: 24
8591 22:11:05.727694 [Byte1]: 24
8592 22:11:05.728109
8593 22:11:05.731048 Set Vref, RX VrefLevel [Byte0]: 25
8594 22:11:05.734055 [Byte1]: 25
8595 22:11:05.734571
8596 22:11:05.737265 Set Vref, RX VrefLevel [Byte0]: 26
8597 22:11:05.740411 [Byte1]: 26
8598 22:11:05.744079
8599 22:11:05.744643 Set Vref, RX VrefLevel [Byte0]: 27
8600 22:11:05.747631 [Byte1]: 27
8601 22:11:05.751294
8602 22:11:05.751709 Set Vref, RX VrefLevel [Byte0]: 28
8603 22:11:05.754729 [Byte1]: 28
8604 22:11:05.759099
8605 22:11:05.759514 Set Vref, RX VrefLevel [Byte0]: 29
8606 22:11:05.762473 [Byte1]: 29
8607 22:11:05.766437
8608 22:11:05.766930 Set Vref, RX VrefLevel [Byte0]: 30
8609 22:11:05.770188 [Byte1]: 30
8610 22:11:05.774190
8611 22:11:05.774649 Set Vref, RX VrefLevel [Byte0]: 31
8612 22:11:05.777726 [Byte1]: 31
8613 22:11:05.782194
8614 22:11:05.782656 Set Vref, RX VrefLevel [Byte0]: 32
8615 22:11:05.785135 [Byte1]: 32
8616 22:11:05.789341
8617 22:11:05.789756 Set Vref, RX VrefLevel [Byte0]: 33
8618 22:11:05.792640 [Byte1]: 33
8619 22:11:05.797247
8620 22:11:05.797661 Set Vref, RX VrefLevel [Byte0]: 34
8621 22:11:05.800605 [Byte1]: 34
8622 22:11:05.804728
8623 22:11:05.805143 Set Vref, RX VrefLevel [Byte0]: 35
8624 22:11:05.807884 [Byte1]: 35
8625 22:11:05.812239
8626 22:11:05.812655 Set Vref, RX VrefLevel [Byte0]: 36
8627 22:11:05.815457 [Byte1]: 36
8628 22:11:05.820412
8629 22:11:05.820921 Set Vref, RX VrefLevel [Byte0]: 37
8630 22:11:05.823278 [Byte1]: 37
8631 22:11:05.827651
8632 22:11:05.828071 Set Vref, RX VrefLevel [Byte0]: 38
8633 22:11:05.830684 [Byte1]: 38
8634 22:11:05.835350
8635 22:11:05.835773 Set Vref, RX VrefLevel [Byte0]: 39
8636 22:11:05.838222 [Byte1]: 39
8637 22:11:05.842707
8638 22:11:05.843126 Set Vref, RX VrefLevel [Byte0]: 40
8639 22:11:05.846381 [Byte1]: 40
8640 22:11:05.850228
8641 22:11:05.850713 Set Vref, RX VrefLevel [Byte0]: 41
8642 22:11:05.853812 [Byte1]: 41
8643 22:11:05.858256
8644 22:11:05.858862 Set Vref, RX VrefLevel [Byte0]: 42
8645 22:11:05.861608 [Byte1]: 42
8646 22:11:05.866013
8647 22:11:05.866574 Set Vref, RX VrefLevel [Byte0]: 43
8648 22:11:05.868973 [Byte1]: 43
8649 22:11:05.873265
8650 22:11:05.873706 Set Vref, RX VrefLevel [Byte0]: 44
8651 22:11:05.876506 [Byte1]: 44
8652 22:11:05.881081
8653 22:11:05.881557 Set Vref, RX VrefLevel [Byte0]: 45
8654 22:11:05.884357 [Byte1]: 45
8655 22:11:05.888402
8656 22:11:05.888861 Set Vref, RX VrefLevel [Byte0]: 46
8657 22:11:05.891563 [Byte1]: 46
8658 22:11:05.896098
8659 22:11:05.896585 Set Vref, RX VrefLevel [Byte0]: 47
8660 22:11:05.899225 [Byte1]: 47
8661 22:11:05.903706
8662 22:11:05.904323 Set Vref, RX VrefLevel [Byte0]: 48
8663 22:11:05.906960 [Byte1]: 48
8664 22:11:05.911764
8665 22:11:05.912234 Set Vref, RX VrefLevel [Byte0]: 49
8666 22:11:05.914472 [Byte1]: 49
8667 22:11:05.919010
8668 22:11:05.919433 Set Vref, RX VrefLevel [Byte0]: 50
8669 22:11:05.922197 [Byte1]: 50
8670 22:11:05.926528
8671 22:11:05.927147 Set Vref, RX VrefLevel [Byte0]: 51
8672 22:11:05.929658 [Byte1]: 51
8673 22:11:05.933943
8674 22:11:05.934626 Set Vref, RX VrefLevel [Byte0]: 52
8675 22:11:05.937571 [Byte1]: 52
8676 22:11:05.941734
8677 22:11:05.942354 Set Vref, RX VrefLevel [Byte0]: 53
8678 22:11:05.944973 [Byte1]: 53
8679 22:11:05.949492
8680 22:11:05.950142 Set Vref, RX VrefLevel [Byte0]: 54
8681 22:11:05.952792 [Byte1]: 54
8682 22:11:05.957137
8683 22:11:05.957688 Set Vref, RX VrefLevel [Byte0]: 55
8684 22:11:05.960043 [Byte1]: 55
8685 22:11:05.964383
8686 22:11:05.964803 Set Vref, RX VrefLevel [Byte0]: 56
8687 22:11:05.967877 [Byte1]: 56
8688 22:11:05.972389
8689 22:11:05.972808 Set Vref, RX VrefLevel [Byte0]: 57
8690 22:11:05.975415 [Byte1]: 57
8691 22:11:05.979922
8692 22:11:05.980340 Set Vref, RX VrefLevel [Byte0]: 58
8693 22:11:05.983228 [Byte1]: 58
8694 22:11:05.987724
8695 22:11:05.988210 Set Vref, RX VrefLevel [Byte0]: 59
8696 22:11:05.990669 [Byte1]: 59
8697 22:11:05.995481
8698 22:11:05.995899 Set Vref, RX VrefLevel [Byte0]: 60
8699 22:11:05.998087 [Byte1]: 60
8700 22:11:06.002758
8701 22:11:06.003179 Set Vref, RX VrefLevel [Byte0]: 61
8702 22:11:06.006491 [Byte1]: 61
8703 22:11:06.010137
8704 22:11:06.010556 Set Vref, RX VrefLevel [Byte0]: 62
8705 22:11:06.013698 [Byte1]: 62
8706 22:11:06.017731
8707 22:11:06.018298 Set Vref, RX VrefLevel [Byte0]: 63
8708 22:11:06.021650 [Byte1]: 63
8709 22:11:06.025743
8710 22:11:06.026167 Set Vref, RX VrefLevel [Byte0]: 64
8711 22:11:06.028927 [Byte1]: 64
8712 22:11:06.033030
8713 22:11:06.033546 Set Vref, RX VrefLevel [Byte0]: 65
8714 22:11:06.036739 [Byte1]: 65
8715 22:11:06.040529
8716 22:11:06.040948 Set Vref, RX VrefLevel [Byte0]: 66
8717 22:11:06.044272 [Byte1]: 66
8718 22:11:06.048496
8719 22:11:06.048914 Set Vref, RX VrefLevel [Byte0]: 67
8720 22:11:06.051562 [Byte1]: 67
8721 22:11:06.056045
8722 22:11:06.056460 Set Vref, RX VrefLevel [Byte0]: 68
8723 22:11:06.059444 [Byte1]: 68
8724 22:11:06.063272
8725 22:11:06.063852 Set Vref, RX VrefLevel [Byte0]: 69
8726 22:11:06.066766 [Byte1]: 69
8727 22:11:06.071015
8728 22:11:06.071438 Set Vref, RX VrefLevel [Byte0]: 70
8729 22:11:06.074679 [Byte1]: 70
8730 22:11:06.079168
8731 22:11:06.079673 Set Vref, RX VrefLevel [Byte0]: 71
8732 22:11:06.082198 [Byte1]: 71
8733 22:11:06.086505
8734 22:11:06.087075 Set Vref, RX VrefLevel [Byte0]: 72
8735 22:11:06.089874 [Byte1]: 72
8736 22:11:06.094033
8737 22:11:06.094480 Final RX Vref Byte 0 = 54 to rank0
8738 22:11:06.097225 Final RX Vref Byte 1 = 60 to rank0
8739 22:11:06.100622 Final RX Vref Byte 0 = 54 to rank1
8740 22:11:06.103920 Final RX Vref Byte 1 = 60 to rank1==
8741 22:11:06.106832 Dram Type= 6, Freq= 0, CH_1, rank 0
8742 22:11:06.113523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 22:11:06.113947 ==
8744 22:11:06.114284 DQS Delay:
8745 22:11:06.116909 DQS0 = 0, DQS1 = 0
8746 22:11:06.117346 DQM Delay:
8747 22:11:06.119965 DQM0 = 135, DQM1 = 128
8748 22:11:06.120386 DQ Delay:
8749 22:11:06.123161 DQ0 =142, DQ1 =128, DQ2 =126, DQ3 =132
8750 22:11:06.126640 DQ4 =132, DQ5 =148, DQ6 =146, DQ7 =130
8751 22:11:06.129746 DQ8 =116, DQ9 =116, DQ10 =130, DQ11 =120
8752 22:11:06.132909 DQ12 =136, DQ13 =138, DQ14 =136, DQ15 =138
8753 22:11:06.133389
8754 22:11:06.133812
8755 22:11:06.134130
8756 22:11:06.137103 [DramC_TX_OE_Calibration] TA2
8757 22:11:06.140119 Original DQ_B0 (3 6) =30, OEN = 27
8758 22:11:06.143002 Original DQ_B1 (3 6) =30, OEN = 27
8759 22:11:06.146362 24, 0x0, End_B0=24 End_B1=24
8760 22:11:06.149879 25, 0x0, End_B0=25 End_B1=25
8761 22:11:06.150323 26, 0x0, End_B0=26 End_B1=26
8762 22:11:06.152885 27, 0x0, End_B0=27 End_B1=27
8763 22:11:06.156540 28, 0x0, End_B0=28 End_B1=28
8764 22:11:06.159323 29, 0x0, End_B0=29 End_B1=29
8765 22:11:06.162695 30, 0x0, End_B0=30 End_B1=30
8766 22:11:06.163136 31, 0x4141, End_B0=30 End_B1=30
8767 22:11:06.166159 Byte0 end_step=30 best_step=27
8768 22:11:06.169525 Byte1 end_step=30 best_step=27
8769 22:11:06.172978 Byte0 TX OE(2T, 0.5T) = (3, 3)
8770 22:11:06.176803 Byte1 TX OE(2T, 0.5T) = (3, 3)
8771 22:11:06.177221
8772 22:11:06.177550
8773 22:11:06.182860 [DQSOSCAuto] RK0, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8774 22:11:06.185812 CH1 RK0: MR19=303, MR18=190F
8775 22:11:06.192591 CH1_RK0: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8776 22:11:06.193018
8777 22:11:06.196378 ----->DramcWriteLeveling(PI) begin...
8778 22:11:06.196802 ==
8779 22:11:06.199530 Dram Type= 6, Freq= 0, CH_1, rank 1
8780 22:11:06.202864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 22:11:06.203285 ==
8782 22:11:06.205944 Write leveling (Byte 0): 23 => 23
8783 22:11:06.209496 Write leveling (Byte 1): 27 => 27
8784 22:11:06.212589 DramcWriteLeveling(PI) end<-----
8785 22:11:06.213008
8786 22:11:06.213337 ==
8787 22:11:06.216175 Dram Type= 6, Freq= 0, CH_1, rank 1
8788 22:11:06.219017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 22:11:06.222452 ==
8790 22:11:06.222944 [Gating] SW mode calibration
8791 22:11:06.232745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8792 22:11:06.235604 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8793 22:11:06.239056 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 22:11:06.245393 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 22:11:06.249198 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 22:11:06.252063 1 4 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8797 22:11:06.258658 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 22:11:06.262291 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 22:11:06.265645 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 22:11:06.272719 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 22:11:06.275454 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 22:11:06.278683 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 22:11:06.285592 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8804 22:11:06.288171 1 5 12 | B1->B0 | 2e2e 3333 | 0 1 | (0 1) (1 0)
8805 22:11:06.291653 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 22:11:06.298090 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 22:11:06.301556 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 22:11:06.304936 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 22:11:06.311476 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 22:11:06.314939 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 22:11:06.318342 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 22:11:06.324801 1 6 12 | B1->B0 | 4444 3535 | 0 0 | (0 0) (0 0)
8813 22:11:06.328051 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 22:11:06.331423 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 22:11:06.337579 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 22:11:06.341083 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 22:11:06.344322 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 22:11:06.350823 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 22:11:06.354200 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 22:11:06.357572 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8821 22:11:06.364323 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8822 22:11:06.367905 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 22:11:06.370915 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 22:11:06.377432 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 22:11:06.380722 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 22:11:06.384071 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 22:11:06.391230 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 22:11:06.393928 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 22:11:06.397127 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 22:11:06.403949 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 22:11:06.407338 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 22:11:06.410576 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 22:11:06.417724 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 22:11:06.420560 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 22:11:06.423956 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8836 22:11:06.430664 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8837 22:11:06.431082 Total UI for P1: 0, mck2ui 16
8838 22:11:06.437561 best dqsien dly found for B0: ( 1, 9, 8)
8839 22:11:06.440708 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 22:11:06.443758 Total UI for P1: 0, mck2ui 16
8841 22:11:06.446951 best dqsien dly found for B1: ( 1, 9, 12)
8842 22:11:06.450692 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8843 22:11:06.453619 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8844 22:11:06.454030
8845 22:11:06.456865 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8846 22:11:06.460129 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8847 22:11:06.463578 [Gating] SW calibration Done
8848 22:11:06.463990 ==
8849 22:11:06.467036 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 22:11:06.470321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 22:11:06.473336 ==
8852 22:11:06.473753 RX Vref Scan: 0
8853 22:11:06.474081
8854 22:11:06.477046 RX Vref 0 -> 0, step: 1
8855 22:11:06.477463
8856 22:11:06.480135 RX Delay 0 -> 252, step: 8
8857 22:11:06.483368 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8858 22:11:06.486578 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8859 22:11:06.489969 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8860 22:11:06.493387 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8861 22:11:06.499808 iDelay=208, Bit 4, Center 139 (80 ~ 199) 120
8862 22:11:06.503254 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8863 22:11:06.506753 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8864 22:11:06.509992 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8865 22:11:06.513678 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8866 22:11:06.520104 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8867 22:11:06.523321 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8868 22:11:06.526509 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8869 22:11:06.529854 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8870 22:11:06.532931 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8871 22:11:06.539422 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8872 22:11:06.542651 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8873 22:11:06.543072 ==
8874 22:11:06.546043 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 22:11:06.549394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 22:11:06.549814 ==
8877 22:11:06.552773 DQS Delay:
8878 22:11:06.553188 DQS0 = 0, DQS1 = 0
8879 22:11:06.553563 DQM Delay:
8880 22:11:06.555897 DQM0 = 138, DQM1 = 130
8881 22:11:06.556418 DQ Delay:
8882 22:11:06.559159 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8883 22:11:06.565830 DQ4 =139, DQ5 =151, DQ6 =147, DQ7 =135
8884 22:11:06.569686 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8885 22:11:06.572657 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8886 22:11:06.573075
8887 22:11:06.573406
8888 22:11:06.573711 ==
8889 22:11:06.576217 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 22:11:06.579035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 22:11:06.579451 ==
8892 22:11:06.579779
8893 22:11:06.580083
8894 22:11:06.582460 TX Vref Scan disable
8895 22:11:06.585770 == TX Byte 0 ==
8896 22:11:06.589228 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8897 22:11:06.592471 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8898 22:11:06.595365 == TX Byte 1 ==
8899 22:11:06.598758 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8900 22:11:06.602060 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8901 22:11:06.602538 ==
8902 22:11:06.605253 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 22:11:06.611920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 22:11:06.612342 ==
8905 22:11:06.624149
8906 22:11:06.626777 TX Vref early break, caculate TX vref
8907 22:11:06.630147 TX Vref=16, minBit 1, minWin=22, winSum=384
8908 22:11:06.633394 TX Vref=18, minBit 0, minWin=22, winSum=396
8909 22:11:06.636761 TX Vref=20, minBit 0, minWin=24, winSum=403
8910 22:11:06.639809 TX Vref=22, minBit 0, minWin=24, winSum=412
8911 22:11:06.643134 TX Vref=24, minBit 0, minWin=25, winSum=422
8912 22:11:06.649710 TX Vref=26, minBit 0, minWin=25, winSum=423
8913 22:11:06.653343 TX Vref=28, minBit 5, minWin=24, winSum=421
8914 22:11:06.656617 TX Vref=30, minBit 0, minWin=23, winSum=417
8915 22:11:06.659791 TX Vref=32, minBit 0, minWin=23, winSum=406
8916 22:11:06.663434 TX Vref=34, minBit 0, minWin=23, winSum=397
8917 22:11:06.669776 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
8918 22:11:06.670196
8919 22:11:06.673298 Final TX Range 0 Vref 26
8920 22:11:06.673718
8921 22:11:06.674046 ==
8922 22:11:06.676277 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 22:11:06.679409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 22:11:06.679830 ==
8925 22:11:06.680161
8926 22:11:06.680537
8927 22:11:06.682694 TX Vref Scan disable
8928 22:11:06.689386 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8929 22:11:06.689803 == TX Byte 0 ==
8930 22:11:06.693024 u2DelayCellOfst[0]=22 cells (6 PI)
8931 22:11:06.696166 u2DelayCellOfst[1]=14 cells (4 PI)
8932 22:11:06.699793 u2DelayCellOfst[2]=0 cells (0 PI)
8933 22:11:06.702956 u2DelayCellOfst[3]=7 cells (2 PI)
8934 22:11:06.706319 u2DelayCellOfst[4]=11 cells (3 PI)
8935 22:11:06.709501 u2DelayCellOfst[5]=22 cells (6 PI)
8936 22:11:06.712797 u2DelayCellOfst[6]=22 cells (6 PI)
8937 22:11:06.715714 u2DelayCellOfst[7]=7 cells (2 PI)
8938 22:11:06.719650 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8939 22:11:06.722488 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8940 22:11:06.725900 == TX Byte 1 ==
8941 22:11:06.729368 u2DelayCellOfst[8]=0 cells (0 PI)
8942 22:11:06.732611 u2DelayCellOfst[9]=3 cells (1 PI)
8943 22:11:06.733057 u2DelayCellOfst[10]=11 cells (3 PI)
8944 22:11:06.735772 u2DelayCellOfst[11]=7 cells (2 PI)
8945 22:11:06.739105 u2DelayCellOfst[12]=14 cells (4 PI)
8946 22:11:06.742419 u2DelayCellOfst[13]=14 cells (4 PI)
8947 22:11:06.745663 u2DelayCellOfst[14]=18 cells (5 PI)
8948 22:11:06.749113 u2DelayCellOfst[15]=18 cells (5 PI)
8949 22:11:06.755947 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8950 22:11:06.758713 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8951 22:11:06.759157 DramC Write-DBI on
8952 22:11:06.759506 ==
8953 22:11:06.762191 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 22:11:06.768981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 22:11:06.769440 ==
8956 22:11:06.769817
8957 22:11:06.770295
8958 22:11:06.770809 TX Vref Scan disable
8959 22:11:06.772798 == TX Byte 0 ==
8960 22:11:06.776674 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8961 22:11:06.779884 == TX Byte 1 ==
8962 22:11:06.782483 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8963 22:11:06.785896 DramC Write-DBI off
8964 22:11:06.786403
8965 22:11:06.786855 [DATLAT]
8966 22:11:06.787209 Freq=1600, CH1 RK1
8967 22:11:06.787514
8968 22:11:06.789302 DATLAT Default: 0xf
8969 22:11:06.793028 0, 0xFFFF, sum = 0
8970 22:11:06.793453 1, 0xFFFF, sum = 0
8971 22:11:06.796255 2, 0xFFFF, sum = 0
8972 22:11:06.796846 3, 0xFFFF, sum = 0
8973 22:11:06.799436 4, 0xFFFF, sum = 0
8974 22:11:06.800021 5, 0xFFFF, sum = 0
8975 22:11:06.802414 6, 0xFFFF, sum = 0
8976 22:11:06.802993 7, 0xFFFF, sum = 0
8977 22:11:06.805820 8, 0xFFFF, sum = 0
8978 22:11:06.806441 9, 0xFFFF, sum = 0
8979 22:11:06.809318 10, 0xFFFF, sum = 0
8980 22:11:06.809884 11, 0xFFFF, sum = 0
8981 22:11:06.812336 12, 0xFFFF, sum = 0
8982 22:11:06.812950 13, 0xFFFF, sum = 0
8983 22:11:06.816034 14, 0x0, sum = 1
8984 22:11:06.816477 15, 0x0, sum = 2
8985 22:11:06.819237 16, 0x0, sum = 3
8986 22:11:06.819666 17, 0x0, sum = 4
8987 22:11:06.822226 best_step = 15
8988 22:11:06.822829
8989 22:11:06.823183 ==
8990 22:11:06.825898 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 22:11:06.829361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 22:11:06.829785 ==
8993 22:11:06.833078 RX Vref Scan: 0
8994 22:11:06.833607
8995 22:11:06.833945 RX Vref 0 -> 0, step: 1
8996 22:11:06.834263
8997 22:11:06.836172 RX Delay 11 -> 252, step: 4
8998 22:11:06.842337 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
8999 22:11:06.846159 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9000 22:11:06.848937 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9001 22:11:06.852652 iDelay=203, Bit 3, Center 132 (83 ~ 182) 100
9002 22:11:06.855503 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9003 22:11:06.862176 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9004 22:11:06.865597 iDelay=203, Bit 6, Center 148 (95 ~ 202) 108
9005 22:11:06.868885 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9006 22:11:06.872223 iDelay=203, Bit 8, Center 110 (51 ~ 170) 120
9007 22:11:06.875355 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9008 22:11:06.881948 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9009 22:11:06.885092 iDelay=203, Bit 11, Center 118 (63 ~ 174) 112
9010 22:11:06.888603 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9011 22:11:06.891544 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9012 22:11:06.898395 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9013 22:11:06.901864 iDelay=203, Bit 15, Center 136 (79 ~ 194) 116
9014 22:11:06.902428 ==
9015 22:11:06.904833 Dram Type= 6, Freq= 0, CH_1, rank 1
9016 22:11:06.907964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9017 22:11:06.908568 ==
9018 22:11:06.911585 DQS Delay:
9019 22:11:06.912148 DQS0 = 0, DQS1 = 0
9020 22:11:06.912653 DQM Delay:
9021 22:11:06.914587 DQM0 = 135, DQM1 = 125
9022 22:11:06.915279 DQ Delay:
9023 22:11:06.918370 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =132
9024 22:11:06.921378 DQ4 =134, DQ5 =146, DQ6 =148, DQ7 =130
9025 22:11:06.924813 DQ8 =110, DQ9 =114, DQ10 =126, DQ11 =118
9026 22:11:06.931311 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =136
9027 22:11:06.931779
9028 22:11:06.932135
9029 22:11:06.932610
9030 22:11:06.934558 [DramC_TX_OE_Calibration] TA2
9031 22:11:06.935230 Original DQ_B0 (3 6) =30, OEN = 27
9032 22:11:06.938030 Original DQ_B1 (3 6) =30, OEN = 27
9033 22:11:06.941283 24, 0x0, End_B0=24 End_B1=24
9034 22:11:06.944378 25, 0x0, End_B0=25 End_B1=25
9035 22:11:06.948124 26, 0x0, End_B0=26 End_B1=26
9036 22:11:06.952920 27, 0x0, End_B0=27 End_B1=27
9037 22:11:06.953569 28, 0x0, End_B0=28 End_B1=28
9038 22:11:06.954551 29, 0x0, End_B0=29 End_B1=29
9039 22:11:06.957946 30, 0x0, End_B0=30 End_B1=30
9040 22:11:06.961297 31, 0x4141, End_B0=30 End_B1=30
9041 22:11:06.964624 Byte0 end_step=30 best_step=27
9042 22:11:06.965195 Byte1 end_step=30 best_step=27
9043 22:11:06.968150 Byte0 TX OE(2T, 0.5T) = (3, 3)
9044 22:11:06.971316 Byte1 TX OE(2T, 0.5T) = (3, 3)
9045 22:11:06.971958
9046 22:11:06.972479
9047 22:11:06.980995 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9048 22:11:06.981563 CH1 RK1: MR19=303, MR18=E0B
9049 22:11:06.987628 CH1_RK1: MR19=0x303, MR18=0xE0B, DQSOSC=402, MR23=63, INC=22, DEC=15
9050 22:11:06.991080 [RxdqsGatingPostProcess] freq 1600
9051 22:11:06.997525 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9052 22:11:07.001016 best DQS0 dly(2T, 0.5T) = (1, 1)
9053 22:11:07.004380 best DQS1 dly(2T, 0.5T) = (1, 1)
9054 22:11:07.007441 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9055 22:11:07.011050 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9056 22:11:07.011507 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 22:11:07.014559 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 22:11:07.017891 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 22:11:07.020807 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 22:11:07.023815 Pre-setting of DQS Precalculation
9061 22:11:07.030552 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9062 22:11:07.037261 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9063 22:11:07.043471 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9064 22:11:07.043892
9065 22:11:07.044234
9066 22:11:07.047225 [Calibration Summary] 3200 Mbps
9067 22:11:07.047750 CH 0, Rank 0
9068 22:11:07.050320 SW Impedance : PASS
9069 22:11:07.053762 DUTY Scan : NO K
9070 22:11:07.054177 ZQ Calibration : PASS
9071 22:11:07.056655 Jitter Meter : NO K
9072 22:11:07.060592 CBT Training : PASS
9073 22:11:07.061009 Write leveling : PASS
9074 22:11:07.063683 RX DQS gating : PASS
9075 22:11:07.066525 RX DQ/DQS(RDDQC) : PASS
9076 22:11:07.067224 TX DQ/DQS : PASS
9077 22:11:07.069961 RX DATLAT : PASS
9078 22:11:07.073596 RX DQ/DQS(Engine): PASS
9079 22:11:07.074028 TX OE : PASS
9080 22:11:07.076795 All Pass.
9081 22:11:07.077247
9082 22:11:07.077582 CH 0, Rank 1
9083 22:11:07.080154 SW Impedance : PASS
9084 22:11:07.080568 DUTY Scan : NO K
9085 22:11:07.083271 ZQ Calibration : PASS
9086 22:11:07.086574 Jitter Meter : NO K
9087 22:11:07.087030 CBT Training : PASS
9088 22:11:07.090087 Write leveling : PASS
9089 22:11:07.093086 RX DQS gating : PASS
9090 22:11:07.093505 RX DQ/DQS(RDDQC) : PASS
9091 22:11:07.096606 TX DQ/DQS : PASS
9092 22:11:07.100007 RX DATLAT : PASS
9093 22:11:07.100458 RX DQ/DQS(Engine): PASS
9094 22:11:07.103102 TX OE : PASS
9095 22:11:07.103540 All Pass.
9096 22:11:07.103882
9097 22:11:07.106238 CH 1, Rank 0
9098 22:11:07.106742 SW Impedance : PASS
9099 22:11:07.109384 DUTY Scan : NO K
9100 22:11:07.109466 ZQ Calibration : PASS
9101 22:11:07.112507 Jitter Meter : NO K
9102 22:11:07.115652 CBT Training : PASS
9103 22:11:07.115734 Write leveling : PASS
9104 22:11:07.119514 RX DQS gating : PASS
9105 22:11:07.122306 RX DQ/DQS(RDDQC) : PASS
9106 22:11:07.122380 TX DQ/DQS : PASS
9107 22:11:07.125800 RX DATLAT : PASS
9108 22:11:07.129283 RX DQ/DQS(Engine): PASS
9109 22:11:07.129370 TX OE : PASS
9110 22:11:07.132655 All Pass.
9111 22:11:07.132832
9112 22:11:07.132917 CH 1, Rank 1
9113 22:11:07.136075 SW Impedance : PASS
9114 22:11:07.136255 DUTY Scan : NO K
9115 22:11:07.138941 ZQ Calibration : PASS
9116 22:11:07.142782 Jitter Meter : NO K
9117 22:11:07.142921 CBT Training : PASS
9118 22:11:07.145660 Write leveling : PASS
9119 22:11:07.148759 RX DQS gating : PASS
9120 22:11:07.148956 RX DQ/DQS(RDDQC) : PASS
9121 22:11:07.151966 TX DQ/DQS : PASS
9122 22:11:07.155334 RX DATLAT : PASS
9123 22:11:07.155471 RX DQ/DQS(Engine): PASS
9124 22:11:07.158787 TX OE : PASS
9125 22:11:07.159023 All Pass.
9126 22:11:07.159157
9127 22:11:07.162206 DramC Write-DBI on
9128 22:11:07.165535 PER_BANK_REFRESH: Hybrid Mode
9129 22:11:07.165712 TX_TRACKING: ON
9130 22:11:07.175447 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9131 22:11:07.182352 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9132 22:11:07.188928 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9133 22:11:07.192228 [FAST_K] Save calibration result to emmc
9134 22:11:07.195233 sync common calibartion params.
9135 22:11:07.198656 sync cbt_mode0:1, 1:1
9136 22:11:07.202237 dram_init: ddr_geometry: 2
9137 22:11:07.202760 dram_init: ddr_geometry: 2
9138 22:11:07.205517 dram_init: ddr_geometry: 2
9139 22:11:07.208353 0:dram_rank_size:100000000
9140 22:11:07.211656 1:dram_rank_size:100000000
9141 22:11:07.215020 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9142 22:11:07.218283 DFS_SHUFFLE_HW_MODE: ON
9143 22:11:07.221739 dramc_set_vcore_voltage set vcore to 725000
9144 22:11:07.225277 Read voltage for 1600, 0
9145 22:11:07.225768 Vio18 = 0
9146 22:11:07.228082 Vcore = 725000
9147 22:11:07.228650 Vdram = 0
9148 22:11:07.229232 Vddq = 0
9149 22:11:07.229745 Vmddr = 0
9150 22:11:07.231269 switch to 3200 Mbps bootup
9151 22:11:07.234844 [DramcRunTimeConfig]
9152 22:11:07.235262 PHYPLL
9153 22:11:07.235591 DPM_CONTROL_AFTERK: ON
9154 22:11:07.238175 PER_BANK_REFRESH: ON
9155 22:11:07.241390 REFRESH_OVERHEAD_REDUCTION: ON
9156 22:11:07.244876 CMD_PICG_NEW_MODE: OFF
9157 22:11:07.245322 XRTWTW_NEW_MODE: ON
9158 22:11:07.247737 XRTRTR_NEW_MODE: ON
9159 22:11:07.248152 TX_TRACKING: ON
9160 22:11:07.251237 RDSEL_TRACKING: OFF
9161 22:11:07.251809 DQS Precalculation for DVFS: ON
9162 22:11:07.254537 RX_TRACKING: OFF
9163 22:11:07.255112 HW_GATING DBG: ON
9164 22:11:07.257874 ZQCS_ENABLE_LP4: ON
9165 22:11:07.261476 RX_PICG_NEW_MODE: ON
9166 22:11:07.261893 TX_PICG_NEW_MODE: ON
9167 22:11:07.264285 ENABLE_RX_DCM_DPHY: ON
9168 22:11:07.268103 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9169 22:11:07.270754 DUMMY_READ_FOR_TRACKING: OFF
9170 22:11:07.271173 !!! SPM_CONTROL_AFTERK: OFF
9171 22:11:07.274090 !!! SPM could not control APHY
9172 22:11:07.277887 IMPEDANCE_TRACKING: ON
9173 22:11:07.278310 TEMP_SENSOR: ON
9174 22:11:07.280777 HW_SAVE_FOR_SR: OFF
9175 22:11:07.284417 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9176 22:11:07.287288 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9177 22:11:07.287732 Read ODT Tracking: ON
9178 22:11:07.290826 Refresh Rate DeBounce: ON
9179 22:11:07.293887 DFS_NO_QUEUE_FLUSH: ON
9180 22:11:07.297137 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9181 22:11:07.297553 ENABLE_DFS_RUNTIME_MRW: OFF
9182 22:11:07.300862 DDR_RESERVE_NEW_MODE: ON
9183 22:11:07.304133 MR_CBT_SWITCH_FREQ: ON
9184 22:11:07.304570 =========================
9185 22:11:07.324521 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9186 22:11:07.327378 dram_init: ddr_geometry: 2
9187 22:11:07.345563 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9188 22:11:07.349152 dram_init: dram init end (result: 0)
9189 22:11:07.355476 DRAM-K: Full calibration passed in 24611 msecs
9190 22:11:07.358950 MRC: failed to locate region type 0.
9191 22:11:07.359372 DRAM rank0 size:0x100000000,
9192 22:11:07.362237 DRAM rank1 size=0x100000000
9193 22:11:07.372449 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9194 22:11:07.378701 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9195 22:11:07.385679 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9196 22:11:07.392543 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9197 22:11:07.395503 DRAM rank0 size:0x100000000,
9198 22:11:07.398298 DRAM rank1 size=0x100000000
9199 22:11:07.398805 CBMEM:
9200 22:11:07.401508 IMD: root @ 0xfffff000 254 entries.
9201 22:11:07.405190 IMD: root @ 0xffffec00 62 entries.
9202 22:11:07.408248 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9203 22:11:07.415099 WARNING: RO_VPD is uninitialized or empty.
9204 22:11:07.418275 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9205 22:11:07.425551 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9206 22:11:07.438315 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9207 22:11:07.450074 BS: romstage times (exec / console): total (unknown) / 24108 ms
9208 22:11:07.450648
9209 22:11:07.451076
9210 22:11:07.460108 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9211 22:11:07.463435 ARM64: Exception handlers installed.
9212 22:11:07.466498 ARM64: Testing exception
9213 22:11:07.469919 ARM64: Done test exception
9214 22:11:07.470562 Enumerating buses...
9215 22:11:07.473272 Show all devs... Before device enumeration.
9216 22:11:07.476218 Root Device: enabled 1
9217 22:11:07.479795 CPU_CLUSTER: 0: enabled 1
9218 22:11:07.480210 CPU: 00: enabled 1
9219 22:11:07.483190 Compare with tree...
9220 22:11:07.483890 Root Device: enabled 1
9221 22:11:07.486527 CPU_CLUSTER: 0: enabled 1
9222 22:11:07.489725 CPU: 00: enabled 1
9223 22:11:07.490221 Root Device scanning...
9224 22:11:07.493132 scan_static_bus for Root Device
9225 22:11:07.496364 CPU_CLUSTER: 0 enabled
9226 22:11:07.499872 scan_static_bus for Root Device done
9227 22:11:07.502886 scan_bus: bus Root Device finished in 8 msecs
9228 22:11:07.503308 done
9229 22:11:07.509465 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9230 22:11:07.512930 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9231 22:11:07.519608 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9232 22:11:07.522782 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9233 22:11:07.525738 Allocating resources...
9234 22:11:07.529174 Reading resources...
9235 22:11:07.532758 Root Device read_resources bus 0 link: 0
9236 22:11:07.536187 DRAM rank0 size:0x100000000,
9237 22:11:07.536606 DRAM rank1 size=0x100000000
9238 22:11:07.539130 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9239 22:11:07.542383 CPU: 00 missing read_resources
9240 22:11:07.549051 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9241 22:11:07.552734 Root Device read_resources bus 0 link: 0 done
9242 22:11:07.553162 Done reading resources.
9243 22:11:07.559102 Show resources in subtree (Root Device)...After reading.
9244 22:11:07.561955 Root Device child on link 0 CPU_CLUSTER: 0
9245 22:11:07.565384 CPU_CLUSTER: 0 child on link 0 CPU: 00
9246 22:11:07.575240 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9247 22:11:07.575809 CPU: 00
9248 22:11:07.578469 Root Device assign_resources, bus 0 link: 0
9249 22:11:07.582092 CPU_CLUSTER: 0 missing set_resources
9250 22:11:07.588774 Root Device assign_resources, bus 0 link: 0 done
9251 22:11:07.589381 Done setting resources.
9252 22:11:07.595554 Show resources in subtree (Root Device)...After assigning values.
9253 22:11:07.598329 Root Device child on link 0 CPU_CLUSTER: 0
9254 22:11:07.601626 CPU_CLUSTER: 0 child on link 0 CPU: 00
9255 22:11:07.611588 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9256 22:11:07.612173 CPU: 00
9257 22:11:07.614896 Done allocating resources.
9258 22:11:07.621843 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9259 22:11:07.622334 Enabling resources...
9260 22:11:07.622738 done.
9261 22:11:07.628127 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9262 22:11:07.631756 Initializing devices...
9263 22:11:07.632169 Root Device init
9264 22:11:07.635123 init hardware done!
9265 22:11:07.635585 0x00000018: ctrlr->caps
9266 22:11:07.638322 52.000 MHz: ctrlr->f_max
9267 22:11:07.641533 0.400 MHz: ctrlr->f_min
9268 22:11:07.641987 0x40ff8080: ctrlr->voltages
9269 22:11:07.644571 sclk: 390625
9270 22:11:07.644992 Bus Width = 1
9271 22:11:07.645391 sclk: 390625
9272 22:11:07.648124 Bus Width = 1
9273 22:11:07.651640 Early init status = 3
9274 22:11:07.655016 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9275 22:11:07.658115 in-header: 03 fc 00 00 01 00 00 00
9276 22:11:07.661133 in-data: 00
9277 22:11:07.664541 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9278 22:11:07.668702 in-header: 03 fd 00 00 00 00 00 00
9279 22:11:07.672027 in-data:
9280 22:11:07.675370 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9281 22:11:07.678510 in-header: 03 fc 00 00 01 00 00 00
9282 22:11:07.682009 in-data: 00
9283 22:11:07.685434 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9284 22:11:07.689807 in-header: 03 fd 00 00 00 00 00 00
9285 22:11:07.693520 in-data:
9286 22:11:07.696445 [SSUSB] Setting up USB HOST controller...
9287 22:11:07.699683 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9288 22:11:07.703143 [SSUSB] phy power-on done.
9289 22:11:07.706522 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9290 22:11:07.712888 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9291 22:11:07.716339 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9292 22:11:07.722682 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9293 22:11:07.729257 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9294 22:11:07.735801 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9295 22:11:07.742677 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9296 22:11:07.749479 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9297 22:11:07.752655 SPM: binary array size = 0x9dc
9298 22:11:07.755675 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9299 22:11:07.762428 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9300 22:11:07.768698 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9301 22:11:07.775692 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9302 22:11:07.778859 configure_display: Starting display init
9303 22:11:07.813152 anx7625_power_on_init: Init interface.
9304 22:11:07.816497 anx7625_disable_pd_protocol: Disabled PD feature.
9305 22:11:07.819556 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9306 22:11:07.847656 anx7625_start_dp_work: Secure OCM version=00
9307 22:11:07.850747 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9308 22:11:07.865657 sp_tx_get_edid_block: EDID Block = 1
9309 22:11:07.968168 Extracted contents:
9310 22:11:07.971588 header: 00 ff ff ff ff ff ff 00
9311 22:11:07.974755 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9312 22:11:07.978137 version: 01 04
9313 22:11:07.981318 basic params: 95 1f 11 78 0a
9314 22:11:07.984565 chroma info: 76 90 94 55 54 90 27 21 50 54
9315 22:11:07.988271 established: 00 00 00
9316 22:11:07.994873 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9317 22:11:07.997963 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9318 22:11:08.004891 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9319 22:11:08.011391 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9320 22:11:08.017943 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9321 22:11:08.021381 extensions: 00
9322 22:11:08.021792 checksum: fb
9323 22:11:08.022118
9324 22:11:08.024429 Manufacturer: IVO Model 57d Serial Number 0
9325 22:11:08.027847 Made week 0 of 2020
9326 22:11:08.028407 EDID version: 1.4
9327 22:11:08.031003 Digital display
9328 22:11:08.034560 6 bits per primary color channel
9329 22:11:08.035025 DisplayPort interface
9330 22:11:08.037869 Maximum image size: 31 cm x 17 cm
9331 22:11:08.040933 Gamma: 220%
9332 22:11:08.041531 Check DPMS levels
9333 22:11:08.044400 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9334 22:11:08.051026 First detailed timing is preferred timing
9335 22:11:08.051442 Established timings supported:
9336 22:11:08.054074 Standard timings supported:
9337 22:11:08.057412 Detailed timings
9338 22:11:08.060792 Hex of detail: 383680a07038204018303c0035ae10000019
9339 22:11:08.067444 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9340 22:11:08.070414 0780 0798 07c8 0820 hborder 0
9341 22:11:08.074569 0438 043b 0447 0458 vborder 0
9342 22:11:08.077235 -hsync -vsync
9343 22:11:08.077757 Did detailed timing
9344 22:11:08.083638 Hex of detail: 000000000000000000000000000000000000
9345 22:11:08.087380 Manufacturer-specified data, tag 0
9346 22:11:08.090534 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9347 22:11:08.093444 ASCII string: InfoVision
9348 22:11:08.096676 Hex of detail: 000000fe00523134304e574635205248200a
9349 22:11:08.100385 ASCII string: R140NWF5 RH
9350 22:11:08.100852 Checksum
9351 22:11:08.103393 Checksum: 0xfb (valid)
9352 22:11:08.106728 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9353 22:11:08.110193 DSI data_rate: 832800000 bps
9354 22:11:08.117131 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9355 22:11:08.120165 anx7625_parse_edid: pixelclock(138800).
9356 22:11:08.123236 hactive(1920), hsync(48), hfp(24), hbp(88)
9357 22:11:08.126662 vactive(1080), vsync(12), vfp(3), vbp(17)
9358 22:11:08.129890 anx7625_dsi_config: config dsi.
9359 22:11:08.136521 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9360 22:11:08.150642 anx7625_dsi_config: success to config DSI
9361 22:11:08.153514 anx7625_dp_start: MIPI phy setup OK.
9362 22:11:08.157182 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9363 22:11:08.160195 mtk_ddp_mode_set invalid vrefresh 60
9364 22:11:08.163537 main_disp_path_setup
9365 22:11:08.163951 ovl_layer_smi_id_en
9366 22:11:08.166390 ovl_layer_smi_id_en
9367 22:11:08.166850 ccorr_config
9368 22:11:08.167179 aal_config
9369 22:11:08.169870 gamma_config
9370 22:11:08.170285 postmask_config
9371 22:11:08.173313 dither_config
9372 22:11:08.176727 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9373 22:11:08.182744 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9374 22:11:08.186342 Root Device init finished in 551 msecs
9375 22:11:08.189574 CPU_CLUSTER: 0 init
9376 22:11:08.196022 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9377 22:11:08.202393 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9378 22:11:08.202894 APU_MBOX 0x190000b0 = 0x10001
9379 22:11:08.206359 APU_MBOX 0x190001b0 = 0x10001
9380 22:11:08.209148 APU_MBOX 0x190005b0 = 0x10001
9381 22:11:08.213280 APU_MBOX 0x190006b0 = 0x10001
9382 22:11:08.219163 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9383 22:11:08.229317 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9384 22:11:08.241714 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9385 22:11:08.248436 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9386 22:11:08.259775 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9387 22:11:08.269069 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9388 22:11:08.272213 CPU_CLUSTER: 0 init finished in 81 msecs
9389 22:11:08.275804 Devices initialized
9390 22:11:08.278571 Show all devs... After init.
9391 22:11:08.279029 Root Device: enabled 1
9392 22:11:08.282134 CPU_CLUSTER: 0: enabled 1
9393 22:11:08.286023 CPU: 00: enabled 1
9394 22:11:08.288558 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9395 22:11:08.291743 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9396 22:11:08.295124 ELOG: NV offset 0x57f000 size 0x1000
9397 22:11:08.302263 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9398 22:11:08.308863 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9399 22:11:08.311670 ELOG: Event(17) added with size 13 at 2023-09-05 22:11:08 UTC
9400 22:11:08.318304 out: cmd=0x121: 03 db 21 01 00 00 00 00
9401 22:11:08.321553 in-header: 03 d3 00 00 2c 00 00 00
9402 22:11:08.334777 in-data: 8c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9403 22:11:08.338158 ELOG: Event(A1) added with size 10 at 2023-09-05 22:11:08 UTC
9404 22:11:08.345187 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9405 22:11:08.351361 ELOG: Event(A0) added with size 9 at 2023-09-05 22:11:08 UTC
9406 22:11:08.355200 elog_add_boot_reason: Logged dev mode boot
9407 22:11:08.360908 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9408 22:11:08.361420 Finalize devices...
9409 22:11:08.364380 Devices finalized
9410 22:11:08.367595 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9411 22:11:08.371075 Writing coreboot table at 0xffe64000
9412 22:11:08.377469 0. 000000000010a000-0000000000113fff: RAMSTAGE
9413 22:11:08.380978 1. 0000000040000000-00000000400fffff: RAM
9414 22:11:08.384479 2. 0000000040100000-000000004032afff: RAMSTAGE
9415 22:11:08.387918 3. 000000004032b000-00000000545fffff: RAM
9416 22:11:08.390749 4. 0000000054600000-000000005465ffff: BL31
9417 22:11:08.394478 5. 0000000054660000-00000000ffe63fff: RAM
9418 22:11:08.400923 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9419 22:11:08.404424 7. 0000000100000000-000000023fffffff: RAM
9420 22:11:08.407672 Passing 5 GPIOs to payload:
9421 22:11:08.411099 NAME | PORT | POLARITY | VALUE
9422 22:11:08.417185 EC in RW | 0x000000aa | low | undefined
9423 22:11:08.420676 EC interrupt | 0x00000005 | low | undefined
9424 22:11:08.427395 TPM interrupt | 0x000000ab | high | undefined
9425 22:11:08.430680 SD card detect | 0x00000011 | high | undefined
9426 22:11:08.434100 speaker enable | 0x00000093 | high | undefined
9427 22:11:08.437121 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9428 22:11:08.440704 in-header: 03 f9 00 00 02 00 00 00
9429 22:11:08.444071 in-data: 02 00
9430 22:11:08.447221 ADC[4]: Raw value=901182 ID=7
9431 22:11:08.450518 ADC[3]: Raw value=213652 ID=1
9432 22:11:08.450961 RAM Code: 0x71
9433 22:11:08.453922 ADC[6]: Raw value=75036 ID=0
9434 22:11:08.457242 ADC[5]: Raw value=214021 ID=1
9435 22:11:08.457658 SKU Code: 0x1
9436 22:11:08.463467 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a16d
9437 22:11:08.463936 coreboot table: 964 bytes.
9438 22:11:08.467142 IMD ROOT 0. 0xfffff000 0x00001000
9439 22:11:08.470010 IMD SMALL 1. 0xffffe000 0x00001000
9440 22:11:08.473460 RO MCACHE 2. 0xffffc000 0x00001104
9441 22:11:08.476801 CONSOLE 3. 0xfff7c000 0x00080000
9442 22:11:08.479978 FMAP 4. 0xfff7b000 0x00000452
9443 22:11:08.483365 TIME STAMP 5. 0xfff7a000 0x00000910
9444 22:11:08.487179 VBOOT WORK 6. 0xfff66000 0x00014000
9445 22:11:08.490020 RAMOOPS 7. 0xffe66000 0x00100000
9446 22:11:08.493395 COREBOOT 8. 0xffe64000 0x00002000
9447 22:11:08.496783 IMD small region:
9448 22:11:08.500104 IMD ROOT 0. 0xffffec00 0x00000400
9449 22:11:08.503114 VPD 1. 0xffffeb80 0x0000006c
9450 22:11:08.507047 MMC STATUS 2. 0xffffeb60 0x00000004
9451 22:11:08.513091 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9452 22:11:08.513556 Probing TPM: done!
9453 22:11:08.520307 Connected to device vid:did:rid of 1ae0:0028:00
9454 22:11:08.526929 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9455 22:11:08.529814 Initialized TPM device CR50 revision 0
9456 22:11:08.533728 Checking cr50 for pending updates
9457 22:11:08.538753 Reading cr50 TPM mode
9458 22:11:08.547430 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9459 22:11:08.554215 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9460 22:11:08.593484 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9461 22:11:08.596918 Checking segment from ROM address 0x40100000
9462 22:11:08.600307 Checking segment from ROM address 0x4010001c
9463 22:11:08.606897 Loading segment from ROM address 0x40100000
9464 22:11:08.606985 code (compression=0)
9465 22:11:08.616681 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9466 22:11:08.623489 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9467 22:11:08.623646 it's not compressed!
9468 22:11:08.630299 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9469 22:11:08.636756 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9470 22:11:08.654133 Loading segment from ROM address 0x4010001c
9471 22:11:08.654219 Entry Point 0x80000000
9472 22:11:08.657758 Loaded segments
9473 22:11:08.660703 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9474 22:11:08.667302 Jumping to boot code at 0x80000000(0xffe64000)
9475 22:11:08.674271 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9476 22:11:08.680415 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9477 22:11:08.688648 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9478 22:11:08.691585 Checking segment from ROM address 0x40100000
9479 22:11:08.694910 Checking segment from ROM address 0x4010001c
9480 22:11:08.701709 Loading segment from ROM address 0x40100000
9481 22:11:08.701817 code (compression=1)
9482 22:11:08.707865 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9483 22:11:08.718228 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9484 22:11:08.718353 using LZMA
9485 22:11:08.727242 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9486 22:11:08.733507 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9487 22:11:08.737049 Loading segment from ROM address 0x4010001c
9488 22:11:08.737475 Entry Point 0x54601000
9489 22:11:08.740413 Loaded segments
9490 22:11:08.743703 NOTICE: MT8192 bl31_setup
9491 22:11:08.750652 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9492 22:11:08.754247 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9493 22:11:08.757344 WARNING: region 0:
9494 22:11:08.760952 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 22:11:08.761373 WARNING: region 1:
9496 22:11:08.767138 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9497 22:11:08.770793 WARNING: region 2:
9498 22:11:08.773842 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9499 22:11:08.777017 WARNING: region 3:
9500 22:11:08.780394 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9501 22:11:08.783842 WARNING: region 4:
9502 22:11:08.790379 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9503 22:11:08.790856 WARNING: region 5:
9504 22:11:08.793797 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 22:11:08.797057 WARNING: region 6:
9506 22:11:08.800461 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 22:11:08.803701 WARNING: region 7:
9508 22:11:08.807183 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 22:11:08.813902 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9510 22:11:08.817167 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9511 22:11:08.820551 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9512 22:11:08.827179 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9513 22:11:08.830196 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9514 22:11:08.837009 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9515 22:11:08.840455 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9516 22:11:08.843648 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9517 22:11:08.849744 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9518 22:11:08.853258 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9519 22:11:08.856246 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9520 22:11:08.863240 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9521 22:11:08.866319 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9522 22:11:08.872900 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9523 22:11:08.876414 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9524 22:11:08.879600 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9525 22:11:08.886397 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9526 22:11:08.889303 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9527 22:11:08.896155 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9528 22:11:08.899547 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9529 22:11:08.902944 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9530 22:11:08.909463 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9531 22:11:08.912865 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9532 22:11:08.915673 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9533 22:11:08.922399 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9534 22:11:08.926239 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9535 22:11:08.933211 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9536 22:11:08.936353 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9537 22:11:08.942659 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9538 22:11:08.946557 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9539 22:11:08.949847 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9540 22:11:08.956259 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9541 22:11:08.959522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9542 22:11:08.962730 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9543 22:11:08.966298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9544 22:11:08.972366 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9545 22:11:08.975739 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9546 22:11:08.979103 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9547 22:11:08.986348 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9548 22:11:08.988838 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9549 22:11:08.992376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9550 22:11:08.995389 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9551 22:11:09.002328 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9552 22:11:09.005412 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9553 22:11:09.008875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9554 22:11:09.012189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9555 22:11:09.018907 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9556 22:11:09.022337 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9557 22:11:09.025807 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9558 22:11:09.032274 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9559 22:11:09.035689 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9560 22:11:09.042467 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9561 22:11:09.045610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9562 22:11:09.048619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9563 22:11:09.055661 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9564 22:11:09.058963 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9565 22:11:09.065457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9566 22:11:09.069144 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9567 22:11:09.075427 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9568 22:11:09.078558 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9569 22:11:09.085396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9570 22:11:09.088590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9571 22:11:09.092542 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9572 22:11:09.098414 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9573 22:11:09.101934 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9574 22:11:09.108714 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9575 22:11:09.111643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9576 22:11:09.118580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9577 22:11:09.121844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9578 22:11:09.127993 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9579 22:11:09.131288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9580 22:11:09.134681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9581 22:11:09.141395 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9582 22:11:09.144433 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9583 22:11:09.151527 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9584 22:11:09.155013 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9585 22:11:09.161435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9586 22:11:09.164507 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9587 22:11:09.171562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9588 22:11:09.175071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9589 22:11:09.177872 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9590 22:11:09.184467 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9591 22:11:09.188035 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9592 22:11:09.194471 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9593 22:11:09.198130 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9594 22:11:09.204174 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9595 22:11:09.207725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9596 22:11:09.210918 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9597 22:11:09.217393 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9598 22:11:09.221245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9599 22:11:09.227572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9600 22:11:09.230985 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9601 22:11:09.237717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9602 22:11:09.241129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9603 22:11:09.247492 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9604 22:11:09.250921 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9605 22:11:09.254420 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9606 22:11:09.260682 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9607 22:11:09.264010 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9608 22:11:09.267060 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9609 22:11:09.270848 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9610 22:11:09.277214 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9611 22:11:09.280897 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9612 22:11:09.287119 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9613 22:11:09.290519 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9614 22:11:09.293457 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9615 22:11:09.300088 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9616 22:11:09.303258 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9617 22:11:09.309883 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9618 22:11:09.313723 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9619 22:11:09.316617 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9620 22:11:09.323419 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9621 22:11:09.326648 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9622 22:11:09.332958 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9623 22:11:09.336505 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9624 22:11:09.340058 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9625 22:11:09.346330 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9626 22:11:09.349750 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9627 22:11:09.353183 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9628 22:11:09.359749 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9629 22:11:09.363131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9630 22:11:09.366159 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9631 22:11:09.369542 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9632 22:11:09.376556 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9633 22:11:09.379682 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9634 22:11:09.383354 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9635 22:11:09.390067 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9636 22:11:09.393235 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9637 22:11:09.399869 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9638 22:11:09.402967 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9639 22:11:09.406113 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9640 22:11:09.413091 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9641 22:11:09.416366 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9642 22:11:09.422931 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9643 22:11:09.426287 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9644 22:11:09.429323 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9645 22:11:09.436192 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9646 22:11:09.439440 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9647 22:11:09.442641 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9648 22:11:09.449496 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9649 22:11:09.452729 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9650 22:11:09.459277 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9651 22:11:09.463097 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9652 22:11:09.466006 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9653 22:11:09.472663 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9654 22:11:09.475898 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9655 22:11:09.482403 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9656 22:11:09.486030 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9657 22:11:09.489502 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9658 22:11:09.496396 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9659 22:11:09.499191 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9660 22:11:09.506049 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9661 22:11:09.509193 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9662 22:11:09.512696 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9663 22:11:09.519303 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9664 22:11:09.522412 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9665 22:11:09.529216 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9666 22:11:09.532669 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9667 22:11:09.535799 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9668 22:11:09.542101 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9669 22:11:09.545498 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9670 22:11:09.551874 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9671 22:11:09.555535 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9672 22:11:09.558432 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9673 22:11:09.565701 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9674 22:11:09.568745 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9675 22:11:09.574897 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9676 22:11:09.578455 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9677 22:11:09.581571 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9678 22:11:09.588744 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9679 22:11:09.591859 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9680 22:11:09.597917 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9681 22:11:09.601797 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9682 22:11:09.605063 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9683 22:11:09.611397 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9684 22:11:09.614627 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9685 22:11:09.621164 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9686 22:11:09.624603 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9687 22:11:09.627825 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9688 22:11:09.634476 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9689 22:11:09.637863 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9690 22:11:09.644328 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9691 22:11:09.647499 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9692 22:11:09.651148 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9693 22:11:09.657594 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9694 22:11:09.660916 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9695 22:11:09.667315 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9696 22:11:09.670707 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9697 22:11:09.674064 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9698 22:11:09.680743 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9699 22:11:09.684146 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9700 22:11:09.690501 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9701 22:11:09.693672 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9702 22:11:09.700647 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9703 22:11:09.703694 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9704 22:11:09.707057 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9705 22:11:09.713552 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9706 22:11:09.716614 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9707 22:11:09.723690 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9708 22:11:09.726674 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9709 22:11:09.732943 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9710 22:11:09.736708 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9711 22:11:09.740073 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9712 22:11:09.746292 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9713 22:11:09.750150 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9714 22:11:09.756228 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9715 22:11:09.760285 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9716 22:11:09.766434 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9717 22:11:09.769274 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9718 22:11:09.772905 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9719 22:11:09.779177 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9720 22:11:09.782808 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9721 22:11:09.788949 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9722 22:11:09.792441 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9723 22:11:09.799303 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9724 22:11:09.802082 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9725 22:11:09.805443 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9726 22:11:09.812337 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9727 22:11:09.815141 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9728 22:11:09.822219 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9729 22:11:09.825435 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9730 22:11:09.829261 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9731 22:11:09.835265 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9732 22:11:09.838589 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9733 22:11:09.845552 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9734 22:11:09.848430 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9735 22:11:09.855147 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9736 22:11:09.858812 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9737 22:11:09.861771 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9738 22:11:09.868866 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9739 22:11:09.872360 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9740 22:11:09.875089 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9741 22:11:09.878350 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9742 22:11:09.884803 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9743 22:11:09.888144 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9744 22:11:09.891230 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9745 22:11:09.898214 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9746 22:11:09.901310 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9747 22:11:09.904557 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9748 22:11:09.911223 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9749 22:11:09.914787 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9750 22:11:09.921407 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9751 22:11:09.924639 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9752 22:11:09.928187 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9753 22:11:09.934566 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9754 22:11:09.938363 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9755 22:11:09.944472 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9756 22:11:09.947993 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9757 22:11:09.951555 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9758 22:11:09.957618 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9759 22:11:09.960933 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9760 22:11:09.964175 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9761 22:11:09.971327 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9762 22:11:09.974302 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9763 22:11:09.977404 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9764 22:11:09.984325 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9765 22:11:09.987163 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9766 22:11:09.993987 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9767 22:11:09.997298 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9768 22:11:10.000625 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9769 22:11:10.007500 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9770 22:11:10.010410 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9771 22:11:10.014099 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9772 22:11:10.021027 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9773 22:11:10.023869 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9774 22:11:10.030661 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9775 22:11:10.033619 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9776 22:11:10.037023 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9777 22:11:10.044069 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9778 22:11:10.046768 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9779 22:11:10.050413 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9780 22:11:10.053472 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9781 22:11:10.057227 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9782 22:11:10.063503 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9783 22:11:10.066415 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9784 22:11:10.069887 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9785 22:11:10.076305 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9786 22:11:10.079971 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9787 22:11:10.083070 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9788 22:11:10.086975 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9789 22:11:10.093162 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9790 22:11:10.096444 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9791 22:11:10.099783 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9792 22:11:10.106510 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9793 22:11:10.110012 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9794 22:11:10.116313 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9795 22:11:10.119716 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9796 22:11:10.122749 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9797 22:11:10.129247 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9798 22:11:10.133070 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9799 22:11:10.139075 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9800 22:11:10.142741 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9801 22:11:10.149449 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9802 22:11:10.152634 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9803 22:11:10.155871 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9804 22:11:10.162454 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9805 22:11:10.165596 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9806 22:11:10.172347 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9807 22:11:10.175706 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9808 22:11:10.179063 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9809 22:11:10.185481 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9810 22:11:10.189146 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9811 22:11:10.195533 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9812 22:11:10.198948 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9813 22:11:10.205295 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9814 22:11:10.208427 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9815 22:11:10.211832 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9816 22:11:10.218484 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9817 22:11:10.221763 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9818 22:11:10.228435 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9819 22:11:10.232012 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9820 22:11:10.235101 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9821 22:11:10.241929 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9822 22:11:10.245171 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9823 22:11:10.251528 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9824 22:11:10.254721 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9825 22:11:10.258065 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9826 22:11:10.264634 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9827 22:11:10.268037 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9828 22:11:10.274689 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9829 22:11:10.277762 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9830 22:11:10.284477 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9831 22:11:10.287882 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9832 22:11:10.291238 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9833 22:11:10.298404 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9834 22:11:10.301070 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9835 22:11:10.307560 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9836 22:11:10.310934 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9837 22:11:10.317826 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9838 22:11:10.320961 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9839 22:11:10.324287 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9840 22:11:10.330762 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9841 22:11:10.333895 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9842 22:11:10.340945 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9843 22:11:10.344158 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9844 22:11:10.347082 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9845 22:11:10.354132 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9846 22:11:10.357023 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9847 22:11:10.363486 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9848 22:11:10.367272 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9849 22:11:10.373524 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9850 22:11:10.376732 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9851 22:11:10.380572 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9852 22:11:10.386579 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9853 22:11:10.390419 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9854 22:11:10.397151 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9855 22:11:10.400126 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9856 22:11:10.403458 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9857 22:11:10.409960 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9858 22:11:10.413065 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9859 22:11:10.419876 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9860 22:11:10.423446 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9861 22:11:10.429560 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9862 22:11:10.432957 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9863 22:11:10.436183 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9864 22:11:10.442964 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9865 22:11:10.446254 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9866 22:11:10.452564 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9867 22:11:10.456460 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9868 22:11:10.463003 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9869 22:11:10.466154 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9870 22:11:10.469191 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9871 22:11:10.475966 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9872 22:11:10.479472 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9873 22:11:10.486148 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9874 22:11:10.489436 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9875 22:11:10.496029 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9876 22:11:10.499061 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9877 22:11:10.505798 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9878 22:11:10.509239 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9879 22:11:10.512089 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9880 22:11:10.518856 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9881 22:11:10.522362 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9882 22:11:10.528848 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9883 22:11:10.532205 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9884 22:11:10.538361 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9885 22:11:10.541860 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9886 22:11:10.545193 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9887 22:11:10.551508 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9888 22:11:10.555336 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9889 22:11:10.561706 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9890 22:11:10.564922 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9891 22:11:10.571473 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9892 22:11:10.575261 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9893 22:11:10.581541 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9894 22:11:10.585041 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9895 22:11:10.588238 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9896 22:11:10.595087 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9897 22:11:10.598204 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9898 22:11:10.604644 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9899 22:11:10.607957 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9900 22:11:10.614651 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9901 22:11:10.618259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9902 22:11:10.624824 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9903 22:11:10.628103 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9904 22:11:10.631166 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9905 22:11:10.637719 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9906 22:11:10.641329 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9907 22:11:10.647681 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9908 22:11:10.650742 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9909 22:11:10.657677 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9910 22:11:10.661123 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9911 22:11:10.664214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9912 22:11:10.671032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9913 22:11:10.673937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9914 22:11:10.680781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9915 22:11:10.683681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9916 22:11:10.690667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9917 22:11:10.693823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9918 22:11:10.700622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9919 22:11:10.703887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9920 22:11:10.710698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9921 22:11:10.713801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9922 22:11:10.720043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9923 22:11:10.723609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9924 22:11:10.730280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9925 22:11:10.733624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9926 22:11:10.739724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9927 22:11:10.743580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9928 22:11:10.750103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9929 22:11:10.753350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9930 22:11:10.759678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9931 22:11:10.763492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9932 22:11:10.769911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9933 22:11:10.772833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9934 22:11:10.779918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9935 22:11:10.782716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9936 22:11:10.789489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9937 22:11:10.792608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9938 22:11:10.799388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9939 22:11:10.802764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9940 22:11:10.809322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9941 22:11:10.812555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9942 22:11:10.819054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9943 22:11:10.822707 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9944 22:11:10.825656 INFO: [APUAPC] vio 0
9945 22:11:10.829237 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9946 22:11:10.835909 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9947 22:11:10.839111 INFO: [APUAPC] D0_APC_0: 0x400510
9948 22:11:10.839542 INFO: [APUAPC] D0_APC_1: 0x0
9949 22:11:10.842512 INFO: [APUAPC] D0_APC_2: 0x1540
9950 22:11:10.845985 INFO: [APUAPC] D0_APC_3: 0x0
9951 22:11:10.849074 INFO: [APUAPC] D1_APC_0: 0xffffffff
9952 22:11:10.852239 INFO: [APUAPC] D1_APC_1: 0xffffffff
9953 22:11:10.855961 INFO: [APUAPC] D1_APC_2: 0x3fffff
9954 22:11:10.858883 INFO: [APUAPC] D1_APC_3: 0x0
9955 22:11:10.862505 INFO: [APUAPC] D2_APC_0: 0xffffffff
9956 22:11:10.865344 INFO: [APUAPC] D2_APC_1: 0xffffffff
9957 22:11:10.868630 INFO: [APUAPC] D2_APC_2: 0x3fffff
9958 22:11:10.872196 INFO: [APUAPC] D2_APC_3: 0x0
9959 22:11:10.875150 INFO: [APUAPC] D3_APC_0: 0xffffffff
9960 22:11:10.878919 INFO: [APUAPC] D3_APC_1: 0xffffffff
9961 22:11:10.882096 INFO: [APUAPC] D3_APC_2: 0x3fffff
9962 22:11:10.885216 INFO: [APUAPC] D3_APC_3: 0x0
9963 22:11:10.888696 INFO: [APUAPC] D4_APC_0: 0xffffffff
9964 22:11:10.891875 INFO: [APUAPC] D4_APC_1: 0xffffffff
9965 22:11:10.895220 INFO: [APUAPC] D4_APC_2: 0x3fffff
9966 22:11:10.898770 INFO: [APUAPC] D4_APC_3: 0x0
9967 22:11:10.902057 INFO: [APUAPC] D5_APC_0: 0xffffffff
9968 22:11:10.905322 INFO: [APUAPC] D5_APC_1: 0xffffffff
9969 22:11:10.908265 INFO: [APUAPC] D5_APC_2: 0x3fffff
9970 22:11:10.911698 INFO: [APUAPC] D5_APC_3: 0x0
9971 22:11:10.914884 INFO: [APUAPC] D6_APC_0: 0xffffffff
9972 22:11:10.918145 INFO: [APUAPC] D6_APC_1: 0xffffffff
9973 22:11:10.921774 INFO: [APUAPC] D6_APC_2: 0x3fffff
9974 22:11:10.925184 INFO: [APUAPC] D6_APC_3: 0x0
9975 22:11:10.928336 INFO: [APUAPC] D7_APC_0: 0xffffffff
9976 22:11:10.931735 INFO: [APUAPC] D7_APC_1: 0xffffffff
9977 22:11:10.934897 INFO: [APUAPC] D7_APC_2: 0x3fffff
9978 22:11:10.938048 INFO: [APUAPC] D7_APC_3: 0x0
9979 22:11:10.941324 INFO: [APUAPC] D8_APC_0: 0xffffffff
9980 22:11:10.945202 INFO: [APUAPC] D8_APC_1: 0xffffffff
9981 22:11:10.948436 INFO: [APUAPC] D8_APC_2: 0x3fffff
9982 22:11:10.951474 INFO: [APUAPC] D8_APC_3: 0x0
9983 22:11:10.954621 INFO: [APUAPC] D9_APC_0: 0xffffffff
9984 22:11:10.957813 INFO: [APUAPC] D9_APC_1: 0xffffffff
9985 22:11:10.961163 INFO: [APUAPC] D9_APC_2: 0x3fffff
9986 22:11:10.964445 INFO: [APUAPC] D9_APC_3: 0x0
9987 22:11:10.967710 INFO: [APUAPC] D10_APC_0: 0xffffffff
9988 22:11:10.971102 INFO: [APUAPC] D10_APC_1: 0xffffffff
9989 22:11:10.974062 INFO: [APUAPC] D10_APC_2: 0x3fffff
9990 22:11:10.977924 INFO: [APUAPC] D10_APC_3: 0x0
9991 22:11:10.981325 INFO: [APUAPC] D11_APC_0: 0xffffffff
9992 22:11:10.984641 INFO: [APUAPC] D11_APC_1: 0xffffffff
9993 22:11:10.987348 INFO: [APUAPC] D11_APC_2: 0x3fffff
9994 22:11:10.990738 INFO: [APUAPC] D11_APC_3: 0x0
9995 22:11:10.994034 INFO: [APUAPC] D12_APC_0: 0xffffffff
9996 22:11:10.997323 INFO: [APUAPC] D12_APC_1: 0xffffffff
9997 22:11:11.000886 INFO: [APUAPC] D12_APC_2: 0x3fffff
9998 22:11:11.003803 INFO: [APUAPC] D12_APC_3: 0x0
9999 22:11:11.007626 INFO: [APUAPC] D13_APC_0: 0xffffffff
10000 22:11:11.010718 INFO: [APUAPC] D13_APC_1: 0xffffffff
10001 22:11:11.013921 INFO: [APUAPC] D13_APC_2: 0x3fffff
10002 22:11:11.017162 INFO: [APUAPC] D13_APC_3: 0x0
10003 22:11:11.020415 INFO: [APUAPC] D14_APC_0: 0xffffffff
10004 22:11:11.023359 INFO: [APUAPC] D14_APC_1: 0xffffffff
10005 22:11:11.027400 INFO: [APUAPC] D14_APC_2: 0x3fffff
10006 22:11:11.030252 INFO: [APUAPC] D14_APC_3: 0x0
10007 22:11:11.033756 INFO: [APUAPC] D15_APC_0: 0xffffffff
10008 22:11:11.037099 INFO: [APUAPC] D15_APC_1: 0xffffffff
10009 22:11:11.040189 INFO: [APUAPC] D15_APC_2: 0x3fffff
10010 22:11:11.043657 INFO: [APUAPC] D15_APC_3: 0x0
10011 22:11:11.047151 INFO: [APUAPC] APC_CON: 0x4
10012 22:11:11.049965 INFO: [NOCDAPC] D0_APC_0: 0x0
10013 22:11:11.053781 INFO: [NOCDAPC] D0_APC_1: 0x0
10014 22:11:11.056604 INFO: [NOCDAPC] D1_APC_0: 0x0
10015 22:11:11.060255 INFO: [NOCDAPC] D1_APC_1: 0xfff
10016 22:11:11.060680 INFO: [NOCDAPC] D2_APC_0: 0x0
10017 22:11:11.063147 INFO: [NOCDAPC] D2_APC_1: 0xfff
10018 22:11:11.066646 INFO: [NOCDAPC] D3_APC_0: 0x0
10019 22:11:11.069994 INFO: [NOCDAPC] D3_APC_1: 0xfff
10020 22:11:11.073085 INFO: [NOCDAPC] D4_APC_0: 0x0
10021 22:11:11.076524 INFO: [NOCDAPC] D4_APC_1: 0xfff
10022 22:11:11.080137 INFO: [NOCDAPC] D5_APC_0: 0x0
10023 22:11:11.083086 INFO: [NOCDAPC] D5_APC_1: 0xfff
10024 22:11:11.086808 INFO: [NOCDAPC] D6_APC_0: 0x0
10025 22:11:11.090277 INFO: [NOCDAPC] D6_APC_1: 0xfff
10026 22:11:11.090748 INFO: [NOCDAPC] D7_APC_0: 0x0
10027 22:11:11.093169 INFO: [NOCDAPC] D7_APC_1: 0xfff
10028 22:11:11.096655 INFO: [NOCDAPC] D8_APC_0: 0x0
10029 22:11:11.100200 INFO: [NOCDAPC] D8_APC_1: 0xfff
10030 22:11:11.103326 INFO: [NOCDAPC] D9_APC_0: 0x0
10031 22:11:11.106449 INFO: [NOCDAPC] D9_APC_1: 0xfff
10032 22:11:11.109883 INFO: [NOCDAPC] D10_APC_0: 0x0
10033 22:11:11.113013 INFO: [NOCDAPC] D10_APC_1: 0xfff
10034 22:11:11.116123 INFO: [NOCDAPC] D11_APC_0: 0x0
10035 22:11:11.119734 INFO: [NOCDAPC] D11_APC_1: 0xfff
10036 22:11:11.122975 INFO: [NOCDAPC] D12_APC_0: 0x0
10037 22:11:11.126349 INFO: [NOCDAPC] D12_APC_1: 0xfff
10038 22:11:11.129773 INFO: [NOCDAPC] D13_APC_0: 0x0
10039 22:11:11.132709 INFO: [NOCDAPC] D13_APC_1: 0xfff
10040 22:11:11.136279 INFO: [NOCDAPC] D14_APC_0: 0x0
10041 22:11:11.136701 INFO: [NOCDAPC] D14_APC_1: 0xfff
10042 22:11:11.139636 INFO: [NOCDAPC] D15_APC_0: 0x0
10043 22:11:11.142865 INFO: [NOCDAPC] D15_APC_1: 0xfff
10044 22:11:11.146009 INFO: [NOCDAPC] APC_CON: 0x4
10045 22:11:11.149194 INFO: [APUAPC] set_apusys_apc done
10046 22:11:11.152923 INFO: [DEVAPC] devapc_init done
10047 22:11:11.155720 INFO: GICv3 without legacy support detected.
10048 22:11:11.162446 INFO: ARM GICv3 driver initialized in EL3
10049 22:11:11.165713 INFO: Maximum SPI INTID supported: 639
10050 22:11:11.168671 INFO: BL31: Initializing runtime services
10051 22:11:11.175463 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10052 22:11:11.179084 INFO: SPM: enable CPC mode
10053 22:11:11.182141 INFO: mcdi ready for mcusys-off-idle and system suspend
10054 22:11:11.188527 INFO: BL31: Preparing for EL3 exit to normal world
10055 22:11:11.192015 INFO: Entry point address = 0x80000000
10056 22:11:11.192435 INFO: SPSR = 0x8
10057 22:11:11.198983
10058 22:11:11.199404
10059 22:11:11.199735
10060 22:11:11.202078 Starting depthcharge on Spherion...
10061 22:11:11.202716
10062 22:11:11.203072 Wipe memory regions:
10063 22:11:11.203418
10064 22:11:11.205834 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10065 22:11:11.206361 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10066 22:11:11.207051 Setting prompt string to ['asurada:']
10067 22:11:11.207491 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10068 22:11:11.208167 [0x00000040000000, 0x00000054600000)
10069 22:11:11.327592
10070 22:11:11.328080 [0x00000054660000, 0x00000080000000)
10071 22:11:11.588695
10072 22:11:11.589219 [0x000000821a7280, 0x000000ffe64000)
10073 22:11:12.332982
10074 22:11:12.333511 [0x00000100000000, 0x00000240000000)
10075 22:11:14.222670
10076 22:11:14.225909 Initializing XHCI USB controller at 0x11200000.
10077 22:11:15.207804
10078 22:11:15.208327 R8152: Initializing
10079 22:11:15.208684
10080 22:11:15.210575 Version 9 (ocp_data = 6010)
10081 22:11:15.211095
10082 22:11:15.213988 R8152: Done initializing
10083 22:11:15.214402
10084 22:11:15.214778 Adding net device
10085 22:11:15.735933
10086 22:11:15.739100 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10087 22:11:15.739566
10088 22:11:15.739954
10089 22:11:15.740363
10090 22:11:15.741162 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10092 22:11:15.842509 asurada: tftpboot 192.168.201.1 11440297/tftp-deploy-jjlpmr50/kernel/image.itb 11440297/tftp-deploy-jjlpmr50/kernel/cmdline
10093 22:11:15.843231 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10094 22:11:15.843671 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10095 22:11:15.848294 tftpboot 192.168.201.1 11440297/tftp-deploy-jjlpmr50/kernel/image.itp-deploy-jjlpmr50/kernel/cmdline
10096 22:11:15.848765
10097 22:11:15.849129 Waiting for link
10098 22:11:16.050805
10099 22:11:16.051324 done.
10100 22:11:16.051656
10101 22:11:16.051959 MAC: f4:f5:e8:50:de:0a
10102 22:11:16.052320
10103 22:11:16.054045 Sending DHCP discover... done.
10104 22:11:16.054458
10105 22:11:16.056968 Waiting for reply... done.
10106 22:11:16.057427
10107 22:11:16.060589 Sending DHCP request... done.
10108 22:11:16.061079
10109 22:11:16.065875 Waiting for reply... done.
10110 22:11:16.066290
10111 22:11:16.066640 My ip is 192.168.201.14
10112 22:11:16.066955
10113 22:11:16.069206 The DHCP server ip is 192.168.201.1
10114 22:11:16.069623
10115 22:11:16.076155 TFTP server IP predefined by user: 192.168.201.1
10116 22:11:16.076572
10117 22:11:16.082815 Bootfile predefined by user: 11440297/tftp-deploy-jjlpmr50/kernel/image.itb
10118 22:11:16.083234
10119 22:11:16.085769 Sending tftp read request... done.
10120 22:11:16.086200
10121 22:11:16.091833 Waiting for the transfer...
10122 22:11:16.092249
10123 22:11:16.344599 00000000 ################################################################
10124 22:11:16.344742
10125 22:11:16.584523 00080000 ################################################################
10126 22:11:16.584669
10127 22:11:16.815774 00100000 ################################################################
10128 22:11:16.815910
10129 22:11:17.056489 00180000 ################################################################
10130 22:11:17.056658
10131 22:11:17.306953 00200000 ################################################################
10132 22:11:17.307102
10133 22:11:17.544802 00280000 ################################################################
10134 22:11:17.544951
10135 22:11:17.773907 00300000 ################################################################
10136 22:11:17.774057
10137 22:11:18.015486 00380000 ################################################################
10138 22:11:18.015634
10139 22:11:18.268128 00400000 ################################################################
10140 22:11:18.268284
10141 22:11:18.523654 00480000 ################################################################
10142 22:11:18.523801
10143 22:11:18.781834 00500000 ################################################################
10144 22:11:18.781979
10145 22:11:19.039568 00580000 ################################################################
10146 22:11:19.039708
10147 22:11:19.289113 00600000 ################################################################
10148 22:11:19.289265
10149 22:11:19.539221 00680000 ################################################################
10150 22:11:19.539374
10151 22:11:19.791893 00700000 ################################################################
10152 22:11:19.792028
10153 22:11:20.046507 00780000 ################################################################
10154 22:11:20.046683
10155 22:11:20.295191 00800000 ################################################################
10156 22:11:20.295389
10157 22:11:20.534077 00880000 ################################################################
10158 22:11:20.534217
10159 22:11:20.800486 00900000 ################################################################
10160 22:11:20.800659
10161 22:11:21.054082 00980000 ################################################################
10162 22:11:21.054230
10163 22:11:21.309831 00a00000 ################################################################
10164 22:11:21.309974
10165 22:11:21.561263 00a80000 ################################################################
10166 22:11:21.561400
10167 22:11:21.811267 00b00000 ################################################################
10168 22:11:21.811409
10169 22:11:22.076478 00b80000 ################################################################
10170 22:11:22.076640
10171 22:11:22.337456 00c00000 ################################################################
10172 22:11:22.337609
10173 22:11:22.603632 00c80000 ################################################################
10174 22:11:22.603767
10175 22:11:22.867425 00d00000 ################################################################
10176 22:11:22.867575
10177 22:11:23.113712 00d80000 ################################################################
10178 22:11:23.113857
10179 22:11:23.370817 00e00000 ################################################################
10180 22:11:23.370964
10181 22:11:23.626688 00e80000 ################################################################
10182 22:11:23.626852
10183 22:11:23.894072 00f00000 ################################################################
10184 22:11:23.894242
10185 22:11:24.164728 00f80000 ################################################################
10186 22:11:24.164878
10187 22:11:24.422068 01000000 ################################################################
10188 22:11:24.422244
10189 22:11:24.685331 01080000 ################################################################
10190 22:11:24.685482
10191 22:11:24.942789 01100000 ################################################################
10192 22:11:24.942937
10193 22:11:25.191315 01180000 ################################################################
10194 22:11:25.191466
10195 22:11:25.458879 01200000 ################################################################
10196 22:11:25.459026
10197 22:11:25.710985 01280000 ################################################################
10198 22:11:25.711133
10199 22:11:25.959857 01300000 ################################################################
10200 22:11:25.960006
10201 22:11:26.200263 01380000 ################################################################
10202 22:11:26.200411
10203 22:11:26.447611 01400000 ################################################################
10204 22:11:26.447761
10205 22:11:26.696670 01480000 ################################################################
10206 22:11:26.696834
10207 22:11:26.944175 01500000 ################################################################
10208 22:11:26.944341
10209 22:11:27.185668 01580000 ################################################################
10210 22:11:27.185813
10211 22:11:27.412686 01600000 ################################################################
10212 22:11:27.412834
10213 22:11:27.651573 01680000 ################################################################
10214 22:11:27.651725
10215 22:11:27.912852 01700000 ################################################################
10216 22:11:27.913000
10217 22:11:28.184086 01780000 ################################################################
10218 22:11:28.184234
10219 22:11:28.430825 01800000 ################################################################
10220 22:11:28.430974
10221 22:11:28.685637 01880000 ################################################################
10222 22:11:28.685781
10223 22:11:28.933481 01900000 ################################################################
10224 22:11:28.933621
10225 22:11:29.191050 01980000 ################################################################
10226 22:11:29.191200
10227 22:11:29.454557 01a00000 ################################################################
10228 22:11:29.454743
10229 22:11:29.711985 01a80000 ################################################################
10230 22:11:29.712165
10231 22:11:29.948805 01b00000 ################################################################
10232 22:11:29.948964
10233 22:11:30.185118 01b80000 ################################################################
10234 22:11:30.185291
10235 22:11:30.446567 01c00000 ################################################################
10236 22:11:30.446719
10237 22:11:30.715286 01c80000 ################################################################
10238 22:11:30.715434
10239 22:11:30.957095 01d00000 ################################################################
10240 22:11:30.957268
10241 22:11:31.198795 01d80000 ################################################################
10242 22:11:31.198934
10243 22:11:31.450887 01e00000 ################################################################
10244 22:11:31.451029
10245 22:11:31.707539 01e80000 ################################################################
10246 22:11:31.707698
10247 22:11:31.955445 01f00000 ################################################################
10248 22:11:31.955626
10249 22:11:32.188437 01f80000 ################################################################
10250 22:11:32.188608
10251 22:11:32.449794 02000000 ################################################################
10252 22:11:32.449947
10253 22:11:32.694491 02080000 ################################################################
10254 22:11:32.694655
10255 22:11:32.926773 02100000 ################################################################
10256 22:11:32.926910
10257 22:11:33.183832 02180000 ################################################################
10258 22:11:33.183971
10259 22:11:33.423113 02200000 ################################################################
10260 22:11:33.423278
10261 22:11:33.669577 02280000 ################################################################
10262 22:11:33.669730
10263 22:11:33.904893 02300000 ################################################################
10264 22:11:33.905040
10265 22:11:34.145307 02380000 ################################################################
10266 22:11:34.145453
10267 22:11:34.377103 02400000 ################################################################
10268 22:11:34.377311
10269 22:11:34.621206 02480000 ################################################################
10270 22:11:34.621351
10271 22:11:34.875592 02500000 ################################################################
10272 22:11:34.875738
10273 22:11:35.132070 02580000 ################################################################
10274 22:11:35.132226
10275 22:11:35.372765 02600000 ################################################################
10276 22:11:35.372914
10277 22:11:35.601015 02680000 ################################################################
10278 22:11:35.601160
10279 22:11:35.843872 02700000 ################################################################
10280 22:11:35.844022
10281 22:11:36.073017 02780000 ################################################################
10282 22:11:36.073167
10283 22:11:36.304103 02800000 ################################################################
10284 22:11:36.304252
10285 22:11:36.535042 02880000 ################################################################
10286 22:11:36.535189
10287 22:11:36.761984 02900000 ################################################################
10288 22:11:36.762135
10289 22:11:36.991239 02980000 ################################################################
10290 22:11:36.991378
10291 22:11:37.235597 02a00000 ################################################################
10292 22:11:37.235788
10293 22:11:37.464336 02a80000 ################################################################
10294 22:11:37.464489
10295 22:11:37.705054 02b00000 ################################################################
10296 22:11:37.705205
10297 22:11:37.938687 02b80000 ################################################################
10298 22:11:37.938845
10299 22:11:38.172007 02c00000 ################################################################
10300 22:11:38.172160
10301 22:11:38.401727 02c80000 ################################################################
10302 22:11:38.401877
10303 22:11:38.631079 02d00000 ################################################################
10304 22:11:38.631220
10305 22:11:38.861385 02d80000 ################################################################
10306 22:11:38.861533
10307 22:11:39.101699 02e00000 ################################################################
10308 22:11:39.101844
10309 22:11:39.328989 02e80000 ################################################################
10310 22:11:39.329129
10311 22:11:39.574140 02f00000 ################################################################
10312 22:11:39.574315
10313 22:11:39.828581 02f80000 ################################################################
10314 22:11:39.828748
10315 22:11:40.081556 03000000 ################################################################
10316 22:11:40.081729
10317 22:11:40.349191 03080000 ################################################################
10318 22:11:40.349322
10319 22:11:40.589360 03100000 ################################################################
10320 22:11:40.589535
10321 22:11:40.851263 03180000 ################################################################
10322 22:11:40.851410
10323 22:11:41.106926 03200000 ################################################################
10324 22:11:41.107080
10325 22:11:41.372788 03280000 ################################################################
10326 22:11:41.372940
10327 22:11:41.625505 03300000 ################################################################
10328 22:11:41.625655
10329 22:11:41.885854 03380000 ################################################################
10330 22:11:41.886020
10331 22:11:42.135275 03400000 ################################################################
10332 22:11:42.135452
10333 22:11:42.392785 03480000 ################################################################
10334 22:11:42.392958
10335 22:11:42.649892 03500000 ################################################################
10336 22:11:42.650045
10337 22:11:42.906322 03580000 ################################################################
10338 22:11:42.906486
10339 22:11:43.158027 03600000 ################################################################
10340 22:11:43.158204
10341 22:11:43.409025 03680000 ################################################################
10342 22:11:43.409177
10343 22:11:43.667198 03700000 ################################################################
10344 22:11:43.667345
10345 22:11:43.860827 03780000 ################################################### done.
10346 22:11:43.860967
10347 22:11:43.864079 The bootfile was 58606634 bytes long.
10348 22:11:43.864166
10349 22:11:43.867349 Sending tftp read request... done.
10350 22:11:43.867463
10351 22:11:43.870661 Waiting for the transfer...
10352 22:11:43.870756
10353 22:11:43.870830 00000000 # done.
10354 22:11:43.870902
10355 22:11:43.877107 Command line loaded dynamically from TFTP file: 11440297/tftp-deploy-jjlpmr50/kernel/cmdline
10356 22:11:43.880625
10357 22:11:43.894073 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10358 22:11:43.894213
10359 22:11:43.894388 Loading FIT.
10360 22:11:43.894563
10361 22:11:43.897051 Image ramdisk-1 has 47519328 bytes.
10362 22:11:43.897256
10363 22:11:43.900792 Image fdt-1 has 47278 bytes.
10364 22:11:43.901027
10365 22:11:43.903938 Image kernel-1 has 11037994 bytes.
10366 22:11:43.904183
10367 22:11:43.910548 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10368 22:11:43.910844
10369 22:11:43.930300 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10370 22:11:43.930775
10371 22:11:43.934088 Choosing best match conf-1 for compat google,spherion-rev2.
10372 22:11:43.938493
10373 22:11:43.942836 Connected to device vid:did:rid of 1ae0:0028:00
10374 22:11:43.950304
10375 22:11:43.953504 tpm_get_response: command 0x17b, return code 0x0
10376 22:11:43.953952
10377 22:11:43.960709 ec_init: CrosEC protocol v3 supported (256, 248)
10378 22:11:43.961125
10379 22:11:43.963655 tpm_cleanup: add release locality here.
10380 22:11:43.964071
10381 22:11:43.966816 Shutting down all USB controllers.
10382 22:11:43.967260
10383 22:11:43.970418 Removing current net device
10384 22:11:43.970866
10385 22:11:43.973348 Exiting depthcharge with code 4 at timestamp: 62180543
10386 22:11:43.973758
10387 22:11:43.976769 LZMA decompressing kernel-1 to 0x821a6718
10388 22:11:43.977210
10389 22:11:43.983471 LZMA decompressing kernel-1 to 0x40000000
10390 22:11:45.369575
10391 22:11:45.370083 jumping to kernel
10392 22:11:45.371689 end: 2.2.4 bootloader-commands (duration 00:00:34) [common]
10393 22:11:45.372234 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10394 22:11:45.372618 Setting prompt string to ['Linux version [0-9]']
10395 22:11:45.373031 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10396 22:11:45.373527 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10397 22:11:45.451524
10398 22:11:45.455073 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10399 22:11:45.458040 start: 2.2.5.1 login-action (timeout 00:03:51) [common]
10400 22:11:45.458132 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10401 22:11:45.458203 Setting prompt string to []
10402 22:11:45.458314 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10403 22:11:45.458420 Using line separator: #'\n'#
10404 22:11:45.458507 No login prompt set.
10405 22:11:45.458621 Parsing kernel messages
10406 22:11:45.458697 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10407 22:11:45.458802 [login-action] Waiting for messages, (timeout 00:03:51)
10408 22:11:45.477795 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j35911-arm64-gcc-10-defconfig-arm64-chromebook-zzzh4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Sep 5 21:54:53 UTC 2023
10409 22:11:45.480821 [ 0.000000] random: crng init done
10410 22:11:45.487489 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10411 22:11:45.490433 [ 0.000000] efi: UEFI not found.
10412 22:11:45.497556 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10413 22:11:45.504111 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10414 22:11:45.513743 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10415 22:11:45.523712 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10416 22:11:45.530138 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10417 22:11:45.536616 [ 0.000000] printk: bootconsole [mtk8250] enabled
10418 22:11:45.543389 [ 0.000000] NUMA: No NUMA configuration found
10419 22:11:45.550079 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10420 22:11:45.553168 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10421 22:11:45.556981 [ 0.000000] Zone ranges:
10422 22:11:45.563317 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10423 22:11:45.566705 [ 0.000000] DMA32 empty
10424 22:11:45.573428 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10425 22:11:45.576866 [ 0.000000] Movable zone start for each node
10426 22:11:45.579618 [ 0.000000] Early memory node ranges
10427 22:11:45.586701 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10428 22:11:45.592947 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10429 22:11:45.600042 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10430 22:11:45.606198 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10431 22:11:45.613253 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10432 22:11:45.619226 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10433 22:11:45.675710 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10434 22:11:45.682757 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10435 22:11:45.689051 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10436 22:11:45.692503 [ 0.000000] psci: probing for conduit method from DT.
10437 22:11:45.699046 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10438 22:11:45.702027 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10439 22:11:45.709425 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10440 22:11:45.712715 [ 0.000000] psci: SMC Calling Convention v1.2
10441 22:11:45.718921 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10442 22:11:45.722144 [ 0.000000] Detected VIPT I-cache on CPU0
10443 22:11:45.728519 [ 0.000000] CPU features: detected: GIC system register CPU interface
10444 22:11:45.735092 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10445 22:11:45.741436 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10446 22:11:45.748579 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10447 22:11:45.758481 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10448 22:11:45.765482 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10449 22:11:45.768172 [ 0.000000] alternatives: applying boot alternatives
10450 22:11:45.774869 [ 0.000000] Fallback order for Node 0: 0
10451 22:11:45.781340 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10452 22:11:45.784730 [ 0.000000] Policy zone: Normal
10453 22:11:45.797888 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10454 22:11:45.808010 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10455 22:11:45.820550 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10456 22:11:45.830350 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10457 22:11:45.836626 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10458 22:11:45.840298 <6>[ 0.000000] software IO TLB: area num 8.
10459 22:11:45.897190 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10460 22:11:46.046260 <6>[ 0.000000] Memory: 7923152K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 429616K reserved, 32768K cma-reserved)
10461 22:11:46.052746 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10462 22:11:46.059504 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10463 22:11:46.062398 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10464 22:11:46.068910 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10465 22:11:46.075634 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10466 22:11:46.081887 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10467 22:11:46.088466 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10468 22:11:46.095409 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10469 22:11:46.102269 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10470 22:11:46.108134 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10471 22:11:46.111431 <6>[ 0.000000] GICv3: 608 SPIs implemented
10472 22:11:46.115280 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10473 22:11:46.122159 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10474 22:11:46.125250 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10475 22:11:46.131970 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10476 22:11:46.145054 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10477 22:11:46.157772 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10478 22:11:46.164074 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10479 22:11:46.172913 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10480 22:11:46.185450 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10481 22:11:46.191947 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10482 22:11:46.198984 <6>[ 0.009183] Console: colour dummy device 80x25
10483 22:11:46.208732 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10484 22:11:46.215319 <6>[ 0.024341] pid_max: default: 32768 minimum: 301
10485 22:11:46.218543 <6>[ 0.029212] LSM: Security Framework initializing
10486 22:11:46.225734 <6>[ 0.034150] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10487 22:11:46.235289 <6>[ 0.041963] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10488 22:11:46.245412 <6>[ 0.051391] cblist_init_generic: Setting adjustable number of callback queues.
10489 22:11:46.248563 <6>[ 0.058837] cblist_init_generic: Setting shift to 3 and lim to 1.
10490 22:11:46.258284 <6>[ 0.065175] cblist_init_generic: Setting adjustable number of callback queues.
10491 22:11:46.264829 <6>[ 0.072601] cblist_init_generic: Setting shift to 3 and lim to 1.
10492 22:11:46.268529 <6>[ 0.078999] rcu: Hierarchical SRCU implementation.
10493 22:11:46.274944 <6>[ 0.084013] rcu: Max phase no-delay instances is 1000.
10494 22:11:46.281756 <6>[ 0.091049] EFI services will not be available.
10495 22:11:46.285286 <6>[ 0.096018] smp: Bringing up secondary CPUs ...
10496 22:11:46.293656 <6>[ 0.101072] Detected VIPT I-cache on CPU1
10497 22:11:46.300521 <6>[ 0.101141] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10498 22:11:46.306535 <6>[ 0.101175] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10499 22:11:46.309867 <6>[ 0.101514] Detected VIPT I-cache on CPU2
10500 22:11:46.316592 <6>[ 0.101564] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10501 22:11:46.326337 <6>[ 0.101579] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10502 22:11:46.329414 <6>[ 0.101840] Detected VIPT I-cache on CPU3
10503 22:11:46.336408 <6>[ 0.101886] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10504 22:11:46.342617 <6>[ 0.101899] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10505 22:11:46.349540 <6>[ 0.102206] CPU features: detected: Spectre-v4
10506 22:11:46.353100 <6>[ 0.102213] CPU features: detected: Spectre-BHB
10507 22:11:46.356082 <6>[ 0.102218] Detected PIPT I-cache on CPU4
10508 22:11:46.363113 <6>[ 0.102274] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10509 22:11:46.372865 <6>[ 0.102291] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10510 22:11:46.376593 <6>[ 0.102584] Detected PIPT I-cache on CPU5
10511 22:11:46.382736 <6>[ 0.102647] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10512 22:11:46.388884 <6>[ 0.102663] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10513 22:11:46.392203 <6>[ 0.102947] Detected PIPT I-cache on CPU6
10514 22:11:46.402355 <6>[ 0.103011] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10515 22:11:46.409022 <6>[ 0.103027] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10516 22:11:46.412666 <6>[ 0.103327] Detected PIPT I-cache on CPU7
10517 22:11:46.418568 <6>[ 0.103391] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10518 22:11:46.425275 <6>[ 0.103408] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10519 22:11:46.428647 <6>[ 0.103455] smp: Brought up 1 node, 8 CPUs
10520 22:11:46.435055 <6>[ 0.244830] SMP: Total of 8 processors activated.
10521 22:11:46.442039 <6>[ 0.249781] CPU features: detected: 32-bit EL0 Support
10522 22:11:46.448676 <6>[ 0.255143] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10523 22:11:46.455117 <6>[ 0.263998] CPU features: detected: Common not Private translations
10524 22:11:46.461862 <6>[ 0.270513] CPU features: detected: CRC32 instructions
10525 22:11:46.468177 <6>[ 0.275865] CPU features: detected: RCpc load-acquire (LDAPR)
10526 22:11:46.471967 <6>[ 0.281824] CPU features: detected: LSE atomic instructions
10527 22:11:46.478147 <6>[ 0.287605] CPU features: detected: Privileged Access Never
10528 22:11:46.484966 <6>[ 0.293385] CPU features: detected: RAS Extension Support
10529 22:11:46.491351 <6>[ 0.298993] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10530 22:11:46.495361 <6>[ 0.306215] CPU: All CPU(s) started at EL2
10531 22:11:46.501536 <6>[ 0.310532] alternatives: applying system-wide alternatives
10532 22:11:46.511533 <6>[ 0.321230] devtmpfs: initialized
10533 22:11:46.526729 <6>[ 0.330127] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10534 22:11:46.533718 <6>[ 0.340086] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10535 22:11:46.540500 <6>[ 0.348099] pinctrl core: initialized pinctrl subsystem
10536 22:11:46.543540 <6>[ 0.354740] DMI not present or invalid.
10537 22:11:46.549813 <6>[ 0.359146] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10538 22:11:46.559597 <6>[ 0.365956] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10539 22:11:46.566370 <6>[ 0.373536] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10540 22:11:46.576211 <6>[ 0.381749] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10541 22:11:46.579774 <6>[ 0.389993] audit: initializing netlink subsys (disabled)
10542 22:11:46.589639 <5>[ 0.395685] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10543 22:11:46.596246 <6>[ 0.396388] thermal_sys: Registered thermal governor 'step_wise'
10544 22:11:46.602649 <6>[ 0.403654] thermal_sys: Registered thermal governor 'power_allocator'
10545 22:11:46.605837 <6>[ 0.409910] cpuidle: using governor menu
10546 22:11:46.612599 <6>[ 0.420875] NET: Registered PF_QIPCRTR protocol family
10547 22:11:46.619031 <6>[ 0.426356] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10548 22:11:46.625809 <6>[ 0.433464] ASID allocator initialised with 32768 entries
10549 22:11:46.629064 <6>[ 0.440021] Serial: AMBA PL011 UART driver
10550 22:11:46.638653 <4>[ 0.448727] Trying to register duplicate clock ID: 134
10551 22:11:46.693635 <6>[ 0.505992] KASLR enabled
10552 22:11:46.707046 <6>[ 0.513656] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10553 22:11:46.713482 <6>[ 0.520669] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10554 22:11:46.720020 <6>[ 0.527157] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10555 22:11:46.726939 <6>[ 0.534161] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10556 22:11:46.733251 <6>[ 0.540650] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10557 22:11:46.739914 <6>[ 0.547655] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10558 22:11:46.746332 <6>[ 0.554142] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10559 22:11:46.752961 <6>[ 0.561148] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10560 22:11:46.756124 <6>[ 0.568588] ACPI: Interpreter disabled.
10561 22:11:46.765179 <6>[ 0.575026] iommu: Default domain type: Translated
10562 22:11:46.772230 <6>[ 0.580140] iommu: DMA domain TLB invalidation policy: strict mode
10563 22:11:46.775168 <5>[ 0.586801] SCSI subsystem initialized
10564 22:11:46.782109 <6>[ 0.591047] usbcore: registered new interface driver usbfs
10565 22:11:46.788237 <6>[ 0.596779] usbcore: registered new interface driver hub
10566 22:11:46.791419 <6>[ 0.602332] usbcore: registered new device driver usb
10567 22:11:46.798486 <6>[ 0.608448] pps_core: LinuxPPS API ver. 1 registered
10568 22:11:46.808707 <6>[ 0.613643] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10569 22:11:46.812054 <6>[ 0.622987] PTP clock support registered
10570 22:11:46.815088 <6>[ 0.627229] EDAC MC: Ver: 3.0.0
10571 22:11:46.822171 <6>[ 0.632420] FPGA manager framework
10572 22:11:46.828804 <6>[ 0.636096] Advanced Linux Sound Architecture Driver Initialized.
10573 22:11:46.831751 <6>[ 0.642861] vgaarb: loaded
10574 22:11:46.838170 <6>[ 0.646026] clocksource: Switched to clocksource arch_sys_counter
10575 22:11:46.841656 <5>[ 0.652471] VFS: Disk quotas dquot_6.6.0
10576 22:11:46.848344 <6>[ 0.656657] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10577 22:11:46.851369 <6>[ 0.663845] pnp: PnP ACPI: disabled
10578 22:11:46.860263 <6>[ 0.670489] NET: Registered PF_INET protocol family
10579 22:11:46.869895 <6>[ 0.676076] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10580 22:11:46.881722 <6>[ 0.688382] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10581 22:11:46.891649 <6>[ 0.697200] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10582 22:11:46.897985 <6>[ 0.705170] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10583 22:11:46.907632 <6>[ 0.713867] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10584 22:11:46.914543 <6>[ 0.723612] TCP: Hash tables configured (established 65536 bind 65536)
10585 22:11:46.921464 <6>[ 0.730476] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10586 22:11:46.931312 <6>[ 0.737674] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10587 22:11:46.937475 <6>[ 0.745374] NET: Registered PF_UNIX/PF_LOCAL protocol family
10588 22:11:46.944181 <6>[ 0.751473] RPC: Registered named UNIX socket transport module.
10589 22:11:46.947516 <6>[ 0.757627] RPC: Registered udp transport module.
10590 22:11:46.954130 <6>[ 0.762559] RPC: Registered tcp transport module.
10591 22:11:46.960590 <6>[ 0.767490] RPC: Registered tcp NFSv4.1 backchannel transport module.
10592 22:11:46.964209 <6>[ 0.774157] PCI: CLS 0 bytes, default 64
10593 22:11:46.967535 <6>[ 0.778553] Unpacking initramfs...
10594 22:11:46.977104 <6>[ 0.782346] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10595 22:11:46.983786 <6>[ 0.790985] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10596 22:11:46.990393 <6>[ 0.799813] kvm [1]: IPA Size Limit: 40 bits
10597 22:11:46.993914 <6>[ 0.804343] kvm [1]: GICv3: no GICV resource entry
10598 22:11:47.000221 <6>[ 0.809364] kvm [1]: disabling GICv2 emulation
10599 22:11:47.003394 <6>[ 0.814050] kvm [1]: GIC system register CPU interface enabled
10600 22:11:47.010490 <6>[ 0.820213] kvm [1]: vgic interrupt IRQ18
10601 22:11:47.017021 <6>[ 0.826094] kvm [1]: VHE mode initialized successfully
10602 22:11:47.024228 <5>[ 0.832460] Initialise system trusted keyrings
10603 22:11:47.030323 <6>[ 0.837227] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10604 22:11:47.037550 <6>[ 0.847185] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10605 22:11:47.044009 <5>[ 0.853558] NFS: Registering the id_resolver key type
10606 22:11:47.047043 <5>[ 0.858858] Key type id_resolver registered
10607 22:11:47.053587 <5>[ 0.863274] Key type id_legacy registered
10608 22:11:47.060322 <6>[ 0.867554] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10609 22:11:47.067249 <6>[ 0.874476] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10610 22:11:47.073098 <6>[ 0.882180] 9p: Installing v9fs 9p2000 file system support
10611 22:11:47.110217 <5>[ 0.920373] Key type asymmetric registered
10612 22:11:47.113686 <5>[ 0.924704] Asymmetric key parser 'x509' registered
10613 22:11:47.123531 <6>[ 0.929837] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10614 22:11:47.126812 <6>[ 0.937453] io scheduler mq-deadline registered
10615 22:11:47.130206 <6>[ 0.942214] io scheduler kyber registered
10616 22:11:47.148833 <6>[ 0.959098] EINJ: ACPI disabled.
10617 22:11:47.181779 <4>[ 0.984592] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10618 22:11:47.191103 <4>[ 0.995199] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10619 22:11:47.205672 <6>[ 1.015761] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10620 22:11:47.213618 <6>[ 1.023646] printk: console [ttyS0] disabled
10621 22:11:47.241806 <6>[ 1.048290] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10622 22:11:47.248298 <6>[ 1.057761] printk: console [ttyS0] enabled
10623 22:11:47.251758 <6>[ 1.057761] printk: console [ttyS0] enabled
10624 22:11:47.258440 <6>[ 1.066656] printk: bootconsole [mtk8250] disabled
10625 22:11:47.261637 <6>[ 1.066656] printk: bootconsole [mtk8250] disabled
10626 22:11:47.268346 <6>[ 1.077640] SuperH (H)SCI(F) driver initialized
10627 22:11:47.271363 <6>[ 1.082900] msm_serial: driver initialized
10628 22:11:47.285336 <6>[ 1.091817] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10629 22:11:47.295443 <6>[ 1.100366] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10630 22:11:47.301578 <6>[ 1.108907] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10631 22:11:47.311610 <6>[ 1.117534] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10632 22:11:47.321769 <6>[ 1.126241] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10633 22:11:47.328178 <6>[ 1.134960] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10634 22:11:47.338122 <6>[ 1.143500] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10635 22:11:47.344770 <6>[ 1.152315] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10636 22:11:47.354545 <6>[ 1.160856] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10637 22:11:47.366297 <6>[ 1.176286] loop: module loaded
10638 22:11:47.372911 <6>[ 1.182270] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10639 22:11:47.395039 <4>[ 1.205288] mtk-pmic-keys: Failed to locate of_node [id: -1]
10640 22:11:47.401791 <6>[ 1.212027] megasas: 07.719.03.00-rc1
10641 22:11:47.411384 <6>[ 1.221533] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10642 22:11:47.423867 <6>[ 1.233403] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10643 22:11:47.440310 <6>[ 1.250073] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10644 22:11:47.500982 <6>[ 1.304051] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10645 22:11:48.967068 <6>[ 2.777025] Freeing initrd memory: 46400K
10646 22:11:48.977248 <6>[ 2.787283] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10647 22:11:48.988229 <6>[ 2.798193] tun: Universal TUN/TAP device driver, 1.6
10648 22:11:48.991456 <6>[ 2.804247] thunder_xcv, ver 1.0
10649 22:11:48.994942 <6>[ 2.807751] thunder_bgx, ver 1.0
10650 22:11:48.997729 <6>[ 2.811246] nicpf, ver 1.0
10651 22:11:49.008312 <6>[ 2.815259] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10652 22:11:49.011768 <6>[ 2.822735] hns3: Copyright (c) 2017 Huawei Corporation.
10653 22:11:49.018286 <6>[ 2.828322] hclge is initializing
10654 22:11:49.021523 <6>[ 2.831901] e1000: Intel(R) PRO/1000 Network Driver
10655 22:11:49.028102 <6>[ 2.837030] e1000: Copyright (c) 1999-2006 Intel Corporation.
10656 22:11:49.031640 <6>[ 2.843041] e1000e: Intel(R) PRO/1000 Network Driver
10657 22:11:49.038142 <6>[ 2.848257] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10658 22:11:49.045213 <6>[ 2.854458] igb: Intel(R) Gigabit Ethernet Network Driver
10659 22:11:49.051668 <6>[ 2.860108] igb: Copyright (c) 2007-2014 Intel Corporation.
10660 22:11:49.057986 <6>[ 2.865944] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10661 22:11:49.064795 <6>[ 2.872462] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10662 22:11:49.067941 <6>[ 2.878920] sky2: driver version 1.30
10663 22:11:49.074237 <6>[ 2.883911] VFIO - User Level meta-driver version: 0.3
10664 22:11:49.082069 <6>[ 2.892157] usbcore: registered new interface driver usb-storage
10665 22:11:49.088482 <6>[ 2.898600] usbcore: registered new device driver onboard-usb-hub
10666 22:11:49.097651 <6>[ 2.907670] mt6397-rtc mt6359-rtc: registered as rtc0
10667 22:11:49.107713 <6>[ 2.913132] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-05T22:11:49 UTC (1693951909)
10668 22:11:49.110943 <6>[ 2.922693] i2c_dev: i2c /dev entries driver
10669 22:11:49.127668 <6>[ 2.934421] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10670 22:11:49.146634 <6>[ 2.957420] cpu cpu0: EM: created perf domain
10671 22:11:49.150561 <6>[ 2.962421] cpu cpu4: EM: created perf domain
10672 22:11:49.157305 <6>[ 2.968014] sdhci: Secure Digital Host Controller Interface driver
10673 22:11:49.163886 <6>[ 2.974447] sdhci: Copyright(c) Pierre Ossman
10674 22:11:49.170367 <6>[ 2.979403] Synopsys Designware Multimedia Card Interface Driver
10675 22:11:49.177444 <6>[ 2.986038] sdhci-pltfm: SDHCI platform and OF driver helper
10676 22:11:49.180504 <6>[ 2.986160] mmc0: CQHCI version 5.10
10677 22:11:49.187308 <6>[ 2.996080] ledtrig-cpu: registered to indicate activity on CPUs
10678 22:11:49.193930 <6>[ 3.003134] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10679 22:11:49.199894 <6>[ 3.010223] usbcore: registered new interface driver usbhid
10680 22:11:49.203727 <6>[ 3.016047] usbhid: USB HID core driver
10681 22:11:49.213396 <6>[ 3.020244] spi_master spi0: will run message pump with realtime priority
10682 22:11:49.259178 <6>[ 3.062798] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10683 22:11:49.278896 <6>[ 3.078790] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10684 22:11:49.281993 <6>[ 3.093244] mmc0: Command Queue Engine enabled
10685 22:11:49.289226 <6>[ 3.093726] cros-ec-spi spi0.0: Chrome EC device registered
10686 22:11:49.295917 <6>[ 3.098000] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10687 22:11:49.302676 <6>[ 3.111374] mmcblk0: mmc0:0001 DA4128 116 GiB
10688 22:11:49.312753 <6>[ 3.117754] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10689 22:11:49.319096 <6>[ 3.121977] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10690 22:11:49.322482 <6>[ 3.128268] NET: Registered PF_PACKET protocol family
10691 22:11:49.329039 <6>[ 3.134203] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10692 22:11:49.332106 <6>[ 3.138371] 9pnet: Installing 9P2000 support
10693 22:11:49.338956 <6>[ 3.144292] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10694 22:11:49.342144 <5>[ 3.148043] Key type dns_resolver registered
10695 22:11:49.349328 <6>[ 3.153852] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10696 22:11:49.351943 <6>[ 3.158270] registered taskstats version 1
10697 22:11:49.358486 <5>[ 3.168659] Loading compiled-in X.509 certificates
10698 22:11:49.386097 <4>[ 3.189473] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10699 22:11:49.395930 <4>[ 3.200205] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10700 22:11:49.402400 <3>[ 3.210748] debugfs: File 'uA_load' in directory '/' already present!
10701 22:11:49.408841 <3>[ 3.217449] debugfs: File 'min_uV' in directory '/' already present!
10702 22:11:49.415957 <3>[ 3.224061] debugfs: File 'max_uV' in directory '/' already present!
10703 22:11:49.422378 <3>[ 3.230727] debugfs: File 'constraint_flags' in directory '/' already present!
10704 22:11:49.434476 <3>[ 3.241030] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10705 22:11:49.446492 <6>[ 3.256823] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10706 22:11:49.453926 <6>[ 3.263721] xhci-mtk 11200000.usb: xHCI Host Controller
10707 22:11:49.459996 <6>[ 3.269234] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10708 22:11:49.470265 <6>[ 3.277256] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10709 22:11:49.477072 <6>[ 3.286705] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10710 22:11:49.483331 <6>[ 3.292878] xhci-mtk 11200000.usb: xHCI Host Controller
10711 22:11:49.490380 <6>[ 3.298373] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10712 22:11:49.496736 <6>[ 3.306025] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10713 22:11:49.503763 <6>[ 3.313859] hub 1-0:1.0: USB hub found
10714 22:11:49.506917 <6>[ 3.317903] hub 1-0:1.0: 1 port detected
10715 22:11:49.516818 <6>[ 3.322236] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10716 22:11:49.520137 <6>[ 3.330979] hub 2-0:1.0: USB hub found
10717 22:11:49.523100 <6>[ 3.335023] hub 2-0:1.0: 1 port detected
10718 22:11:49.532053 <6>[ 3.342121] mtk-msdc 11f70000.mmc: Got CD GPIO
10719 22:11:49.542474 <6>[ 3.349342] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10720 22:11:49.549297 <6>[ 3.357391] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10721 22:11:49.558925 <4>[ 3.365316] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10722 22:11:49.568909 <6>[ 3.374854] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10723 22:11:49.575538 <6>[ 3.382934] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10724 22:11:49.582172 <6>[ 3.390950] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10725 22:11:49.591962 <6>[ 3.398870] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10726 22:11:49.598684 <6>[ 3.406688] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10727 22:11:49.608778 <6>[ 3.414511] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10728 22:11:49.618404 <6>[ 3.424919] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10729 22:11:49.624934 <6>[ 3.433276] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10730 22:11:49.635168 <6>[ 3.441620] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10731 22:11:49.641329 <6>[ 3.449962] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10732 22:11:49.651286 <6>[ 3.458300] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10733 22:11:49.661180 <6>[ 3.466638] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10734 22:11:49.668287 <6>[ 3.474976] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10735 22:11:49.678350 <6>[ 3.483314] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10736 22:11:49.685266 <6>[ 3.491657] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10737 22:11:49.694946 <6>[ 3.499996] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10738 22:11:49.700851 <6>[ 3.508335] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10739 22:11:49.710966 <6>[ 3.516674] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10740 22:11:49.717716 <6>[ 3.525013] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10741 22:11:49.727622 <6>[ 3.533352] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10742 22:11:49.734045 <6>[ 3.541689] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10743 22:11:49.740453 <6>[ 3.550258] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10744 22:11:49.747133 <6>[ 3.557417] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10745 22:11:49.753810 <6>[ 3.564178] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10746 22:11:49.764305 <6>[ 3.570942] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10747 22:11:49.770506 <6>[ 3.577879] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10748 22:11:49.777021 <6>[ 3.584736] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10749 22:11:49.787391 <6>[ 3.593871] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10750 22:11:49.797257 <6>[ 3.602991] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10751 22:11:49.807114 <6>[ 3.612286] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10752 22:11:49.817009 <6>[ 3.621753] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10753 22:11:49.826536 <6>[ 3.631222] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10754 22:11:49.833402 <6>[ 3.640342] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10755 22:11:49.843180 <6>[ 3.649808] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10756 22:11:49.853214 <6>[ 3.658927] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10757 22:11:49.863083 <6>[ 3.668234] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10758 22:11:49.872883 <6>[ 3.678396] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10759 22:11:49.882820 <6>[ 3.689920] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10760 22:11:49.931403 <6>[ 3.738389] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10761 22:11:50.086402 <6>[ 3.896435] hub 1-1:1.0: USB hub found
10762 22:11:50.089440 <6>[ 3.900993] hub 1-1:1.0: 4 ports detected
10763 22:11:50.212081 <6>[ 4.018374] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10764 22:11:50.237790 <6>[ 4.047903] hub 2-1:1.0: USB hub found
10765 22:11:50.241249 <6>[ 4.052409] hub 2-1:1.0: 3 ports detected
10766 22:11:50.411195 <6>[ 4.218346] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10767 22:11:50.542330 <6>[ 4.352554] hub 1-1.1:1.0: USB hub found
10768 22:11:50.545577 <6>[ 4.356897] hub 1-1.1:1.0: 4 ports detected
10769 22:11:50.659243 <6>[ 4.466385] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10770 22:11:50.791782 <6>[ 4.602204] hub 1-1.4:1.0: USB hub found
10771 22:11:50.795170 <6>[ 4.606877] hub 1-1.4:1.0: 2 ports detected
10772 22:11:50.875310 <6>[ 4.682349] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10773 22:11:51.063374 <6>[ 4.870298] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10774 22:11:51.148118 <3>[ 4.958474] usb 1-1.1.4: device descriptor read/64, error -32
10775 22:11:51.340292 <3>[ 5.150486] usb 1-1.1.4: device descriptor read/64, error -32
10776 22:11:51.535297 <6>[ 5.342321] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10777 22:11:51.723307 <6>[ 5.530323] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10778 22:11:51.807887 <3>[ 5.618476] usb 1-1.1.4: device descriptor read/64, error -32
10779 22:11:51.999984 <3>[ 5.810511] usb 1-1.1.4: device descriptor read/64, error -32
10780 22:11:52.112688 <6>[ 5.922821] usb 1-1.1-port4: attempt power cycle
10781 22:11:52.199268 <6>[ 6.006328] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10782 22:11:52.722796 <6>[ 6.530328] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10783 22:11:52.729204 <4>[ 6.537890] usb 1-1.1.4: Device not responding to setup address.
10784 22:11:52.940034 <4>[ 6.750552] usb 1-1.1.4: Device not responding to setup address.
10785 22:11:53.151784 <3>[ 6.962314] usb 1-1.1.4: device not accepting address 10, error -71
10786 22:11:53.239333 <6>[ 7.046345] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10787 22:11:53.245502 <4>[ 7.053752] usb 1-1.1.4: Device not responding to setup address.
10788 22:11:53.455792 <4>[ 7.266582] usb 1-1.1.4: Device not responding to setup address.
10789 22:11:53.667816 <3>[ 7.478338] usb 1-1.1.4: device not accepting address 11, error -71
10790 22:11:53.674252 <3>[ 7.485368] usb 1-1.1-port4: unable to enumerate USB device
10791 22:12:02.168852 <6>[ 15.983358] ALSA device list:
10792 22:12:02.175517 <6>[ 15.986648] No soundcards found.
10793 22:12:02.183077 <6>[ 15.994593] Freeing unused kernel memory: 8384K
10794 22:12:02.186408 <6>[ 15.999598] Run /init as init process
10795 22:12:02.236744 <6>[ 16.048246] NET: Registered PF_INET6 protocol family
10796 22:12:02.243183 <6>[ 16.054698] Segment Routing with IPv6
10797 22:12:02.246349 <6>[ 16.058661] In-situ OAM (IOAM) with IPv6
10798 22:12:02.281953 <30>[ 16.073870] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10799 22:12:02.285431 <30>[ 16.097591] systemd[1]: Detected architecture arm64.
10800 22:12:02.285959
10801 22:12:02.292124 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10802 22:12:02.292555
10803 22:12:02.306391 <30>[ 16.118289] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10804 22:12:02.464288 <30>[ 16.272640] systemd[1]: Queued start job for default target Graphical Interface.
10805 22:12:02.511564 <30>[ 16.323111] systemd[1]: Created slice system-getty.slice.
10806 22:12:02.518329 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10807 22:12:02.535170 <30>[ 16.346878] systemd[1]: Created slice system-modprobe.slice.
10808 22:12:02.541792 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10809 22:12:02.559870 <30>[ 16.371537] systemd[1]: Created slice system-serial\x2dgetty.slice.
10810 22:12:02.570403 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10811 22:12:02.584300 <30>[ 16.395518] systemd[1]: Created slice User and Session Slice.
10812 22:12:02.590896 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10813 22:12:02.610701 <30>[ 16.418950] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10814 22:12:02.620613 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10815 22:12:02.638678 <30>[ 16.446979] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10816 22:12:02.645508 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10817 22:12:02.669868 <30>[ 16.474847] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10818 22:12:02.676232 <30>[ 16.487089] systemd[1]: Reached target Local Encrypted Volumes.
10819 22:12:02.682823 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10820 22:12:02.699138 <30>[ 16.510837] systemd[1]: Reached target Paths.
10821 22:12:02.705626 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10822 22:12:02.718976 <30>[ 16.530318] systemd[1]: Reached target Remote File Systems.
10823 22:12:02.725562 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10824 22:12:02.743207 <30>[ 16.554688] systemd[1]: Reached target Slices.
10825 22:12:02.749763 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10826 22:12:02.763036 <30>[ 16.574356] systemd[1]: Reached target Swap.
10827 22:12:02.765702 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10828 22:12:02.786658 <30>[ 16.594841] systemd[1]: Listening on initctl Compatibility Named Pipe.
10829 22:12:02.793133 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10830 22:12:02.799963 <30>[ 16.610160] systemd[1]: Listening on Journal Audit Socket.
10831 22:12:02.806550 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10832 22:12:02.819296 <30>[ 16.630777] systemd[1]: Listening on Journal Socket (/dev/log).
10833 22:12:02.825575 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10834 22:12:02.844226 <30>[ 16.655571] systemd[1]: Listening on Journal Socket.
10835 22:12:02.850509 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10836 22:12:02.866827 <30>[ 16.675026] systemd[1]: Listening on Network Service Netlink Socket.
10837 22:12:02.873566 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10838 22:12:02.887928 <30>[ 16.699540] systemd[1]: Listening on udev Control Socket.
10839 22:12:02.894723 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10840 22:12:02.911904 <30>[ 16.723410] systemd[1]: Listening on udev Kernel Socket.
10841 22:12:02.918579 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10842 22:12:02.967011 <30>[ 16.778479] systemd[1]: Mounting Huge Pages File System...
10843 22:12:02.973292 Mounting [0;1;39mHuge Pages File System[0m...
10844 22:12:02.988560 <30>[ 16.800160] systemd[1]: Mounting POSIX Message Queue File System...
10845 22:12:02.995765 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10846 22:12:03.012620 <30>[ 16.824313] systemd[1]: Mounting Kernel Debug File System...
10847 22:12:03.019330 Mounting [0;1;39mKernel Debug File System[0m...
10848 22:12:03.038236 <30>[ 16.846500] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10849 22:12:03.049046 <30>[ 16.857508] systemd[1]: Starting Create list of static device nodes for the current kernel...
10850 22:12:03.055455 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10851 22:12:03.073538 <30>[ 16.885139] systemd[1]: Starting Load Kernel Module configfs...
10852 22:12:03.079750 Starting [0;1;39mLoad Kernel Module configfs[0m...
10853 22:12:03.099035 <30>[ 16.910277] systemd[1]: Starting Load Kernel Module drm...
10854 22:12:03.105157 Starting [0;1;39mLoad Kernel Module drm[0m...
10855 22:12:03.122651 <30>[ 16.930578] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10856 22:12:03.175438 <30>[ 16.986975] systemd[1]: Starting Journal Service...
10857 22:12:03.178563 Starting [0;1;39mJournal Service[0m...
10858 22:12:03.197623 <30>[ 17.009418] systemd[1]: Starting Load Kernel Modules...
10859 22:12:03.204350 Starting [0;1;39mLoad Kernel Modules[0m...
10860 22:12:03.224687 <30>[ 17.033003] systemd[1]: Starting Remount Root and Kernel File Systems...
10861 22:12:03.230975 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10862 22:12:03.246166 <30>[ 17.057625] systemd[1]: Starting Coldplug All udev Devices...
10863 22:12:03.252272 Starting [0;1;39mColdplug All udev Devices[0m...
10864 22:12:03.269828 <30>[ 17.081832] systemd[1]: Started Journal Service.
10865 22:12:03.276771 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10866 22:12:03.292883 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10867 22:12:03.299897 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10868 22:12:03.315910 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10869 22:12:03.339275 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10870 22:12:03.357868 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10871 22:12:03.380880 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10872 22:12:03.404699 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10873 22:12:03.429147 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10874 22:12:03.447015 See 'systemctl status systemd-remount-fs.service' for details.
10875 22:12:03.515624 Mounting [0;1;39mKernel Configuration File System[0m...
10876 22:12:03.534752 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10877 22:12:03.548324 <46>[ 17.357305] systemd-journald[182]: Received client request to flush runtime journal.
10878 22:12:03.558551 Starting [0;1;39mLoad/Save Random Seed[0m...
10879 22:12:03.578542 Starting [0;1;39mApply Kernel Variables[0m...
10880 22:12:03.599537 Starting [0;1;39mCreate System Users[0m...
10881 22:12:03.618452 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10882 22:12:03.635533 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10883 22:12:03.655470 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10884 22:12:03.668110 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10885 22:12:03.684384 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10886 22:12:03.700256 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10887 22:12:03.746979 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10888 22:12:03.769032 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10889 22:12:03.782640 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10890 22:12:03.798644 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10891 22:12:03.818465 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10892 22:12:03.843307 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10893 22:12:03.865314 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10894 22:12:03.887530 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10895 22:12:03.947856 Starting [0;1;39mNetwork Service[0m...
10896 22:12:03.975574 Starting [0;1;39mNetwork Time Synchronization[0m...
10897 22:12:03.999088 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10898 22:12:04.017751 <6>[ 17.826390] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10899 22:12:04.027503 [[0;32m OK [0m] Started [0;<6>[ 17.836706] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10900 22:12:04.037325 1;39mNetwork Ser<6>[ 17.845652] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10901 22:12:04.037758 vice[0m.
10902 22:12:04.047167 <6>[ 17.855161] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10903 22:12:04.079799 [[0;32m OK [0m] Started [0;<6>[ 17.889588] remoteproc remoteproc0: scp is available
10904 22:12:04.085626 <6>[ 17.895671] usbcore: registered new interface driver r8152
10905 22:12:04.092124 1;39mNetwork Tim<6>[ 17.895938] remoteproc remoteproc0: powering up scp
10906 22:12:04.102135 e Synchronizatio<6>[ 17.907950] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10907 22:12:04.102562 n[0m.
10908 22:12:04.108632 <6>[ 17.917901] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10909 22:12:04.119090 <4>[ 17.927725] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10910 22:12:04.125875 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10911 22:12:04.132017 <4>[ 17.941732] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10912 22:12:04.145918 <3>[ 17.954386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10913 22:12:04.152543 <3>[ 17.962526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10914 22:12:04.161963 <3>[ 17.962530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 22:12:04.171957 [[0;32m OK [<3>[ 17.980324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10916 22:12:04.181748 0m] Finished [0<3>[ 17.989369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10917 22:12:04.191564 ;1;39mUpdate UTM<3>[ 17.998090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10918 22:12:04.198290 P about System B<6>[ 18.000235] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10919 22:12:04.205002 <6>[ 18.001542] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10920 22:12:04.211524 oot/Shutdown[0m<6>[ 18.001556] pci_bus 0000:00: root bus resource [bus 00-ff]
10921 22:12:04.215349 .
10922 22:12:04.221783 <6>[ 18.001565] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10923 22:12:04.231702 <6>[ 18.001571] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10924 22:12:04.237751 <6>[ 18.001617] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10925 22:12:04.244657 <6>[ 18.001645] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10926 22:12:04.248217 <6>[ 18.001752] pci 0000:00:00.0: supports D1 D2
10927 22:12:04.254296 <6>[ 18.001758] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10928 22:12:04.264493 <6>[ 18.003663] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10929 22:12:04.271082 <3>[ 18.007563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10930 22:12:04.278212 <6>[ 18.019819] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10931 22:12:04.288227 <3>[ 18.023104] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10932 22:12:04.294535 <3>[ 18.034688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10933 22:12:04.304674 <6>[ 18.037761] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10934 22:12:04.311331 <6>[ 18.049864] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10935 22:12:04.317871 <6>[ 18.053998] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10936 22:12:04.324815 <6>[ 18.054039] remoteproc remoteproc0: remote processor scp is now up
10937 22:12:04.331483 <6>[ 18.054093] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10938 22:12:04.341477 <3>[ 18.056945] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10939 22:12:04.348049 <3>[ 18.056957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10940 22:12:04.357598 <3>[ 18.056961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10941 22:12:04.364515 <3>[ 18.058564] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10942 22:12:04.374484 <3>[ 18.058591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10943 22:12:04.381027 <3>[ 18.058597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10944 22:12:04.391104 <3>[ 18.058607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10945 22:12:04.397329 <3>[ 18.058611] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10946 22:12:04.400836 <6>[ 18.060087] mc: Linux media interface: v0.10
10947 22:12:04.410733 <3>[ 18.061181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10948 22:12:04.420694 <6>[ 18.064569] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10949 22:12:04.427909 <6>[ 18.066342] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10950 22:12:04.437009 <6>[ 18.082839] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10951 22:12:04.446513 <6>[ 18.087885] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10952 22:12:04.453170 <6>[ 18.088036] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10953 22:12:04.460012 <6>[ 18.090588] pci 0000:01:00.0: supports D1 D2
10954 22:12:04.463522 <6>[ 18.122985] videodev: Linux video capture interface: v2.00
10955 22:12:04.469929 <6>[ 18.127339] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10956 22:12:04.476143 <6>[ 18.206622] usbcore: registered new interface driver cdc_ether
10957 22:12:04.486465 <4>[ 18.227286] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10958 22:12:04.489920 <4>[ 18.227286] Fallback method does not support PEC.
10959 22:12:04.496338 <6>[ 18.244180] usbcore: registered new interface driver r8153_ecm
10960 22:12:04.503018 <6>[ 18.254707] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10961 22:12:04.509688 <6>[ 18.261142] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10962 22:12:04.523012 <6>[ 18.262218] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10963 22:12:04.529755 <6>[ 18.262314] usbcore: registered new interface driver uvcvideo
10964 22:12:04.532590 <6>[ 18.264858] Bluetooth: Core ver 2.22
10965 22:12:04.539442 <6>[ 18.267253] r8152 1-1.1.1:1.0: load rtl8153b-2 v1 10/23/19 successfully
10966 22:12:04.549647 <6>[ 18.271486] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10967 22:12:04.553016 <6>[ 18.275918] NET: Registered PF_BLUETOOTH protocol family
10968 22:12:04.562565 <6>[ 18.281334] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10969 22:12:04.569863 <6>[ 18.283597] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10970 22:12:04.576888 <6>[ 18.288245] Bluetooth: HCI device and connection manager initialized
10971 22:12:04.579781 <6>[ 18.288283] Bluetooth: HCI socket layer initialized
10972 22:12:04.589973 <6>[ 18.294786] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10973 22:12:04.593597 <6>[ 18.308145] Bluetooth: L2CAP socket layer initialized
10974 22:12:04.603268 <6>[ 18.314957] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10975 22:12:04.606418 <6>[ 18.321081] Bluetooth: SCO socket layer initialized
10976 22:12:04.613595 <6>[ 18.366345] usbcore: registered new interface driver btusb
10977 22:12:04.619712 <6>[ 18.371435] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10978 22:12:04.626321 <6>[ 18.371559] r8152 1-1.1.1:1.0 eth0: v1.12.13
10979 22:12:04.635843 <4>[ 18.371907] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10980 22:12:04.642863 <3>[ 18.371924] Bluetooth: hci0: Failed to load firmware file (-2)
10981 22:12:04.649517 <3>[ 18.371928] Bluetooth: hci0: Failed to set up firmware (-2)
10982 22:12:04.659480 <4>[ 18.371934] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10983 22:12:04.665710 <6>[ 18.372782] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10984 22:12:04.675552 <6>[ 18.375226] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10985 22:12:04.682514 <6>[ 18.389349] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10986 22:12:04.685540 <6>[ 18.392580] pci 0000:00:00.0: PCI bridge to [bus 01]
10987 22:12:04.695314 <3>[ 18.403400] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 22:12:04.702191 <3>[ 18.404053] power_supply sbs-5-000b: driver failed to report `health' property: -6
10989 22:12:04.712420 <6>[ 18.405767] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10990 22:12:04.718970 [[0;32m OK [<6>[ 18.528373] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10991 22:12:04.725876 0m] Created slic<6>[ 18.536989] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10992 22:12:04.732715 e [0;1;39msyste<6>[ 18.544039] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10993 22:12:04.735879 m-systemd\x2dbacklight.slice[0m.
10994 22:12:04.749522 <3>[ 18.557969] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 22:12:04.755898 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10996 22:12:04.766906 <5>[ 18.575372] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10997 22:12:04.773475 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10998 22:12:04.781606 <5>[ 18.592960] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10999 22:12:04.791212 <4>[ 18.600002] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11000 22:12:04.797905 <6>[ 18.608927] cfg80211: failed to load regulatory.db
11001 22:12:04.809036 <3>[ 18.617334] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 22:12:04.818361 <3>[ 18.618344] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11003 22:12:04.838383 Starting [0;1;39mLoad/Save Screen …o<3>[ 18.646542] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 22:12:04.842450 f leds:white:kbd_backlight[0m...
11005 22:12:04.867848 Starting [0;1;39mNetwork Name Resolution[0m...
11006 22:12:04.879989 <3>[ 18.688475] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 22:12:04.886379 <6>[ 18.688694] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11008 22:12:04.893222 <6>[ 18.704845] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11009 22:12:04.903337 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11010 22:12:04.918218 <6>[ 18.730090] mt7921e 0000:01:00.0: ASIC revision: 79610010
11011 22:12:04.927930 <3>[ 18.736669] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 22:12:04.963373 <3>[ 18.771965] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11013 22:12:04.973901 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11014 22:12:04.993756 <3>[ 18.801949] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11015 22:12:05.029842 <4>[ 18.835315] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11016 22:12:05.094140 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11017 22:12:05.110763 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11018 22:12:05.129926 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11019 22:12:05.153161 [[0;32m OK [0m] Reached targ<4>[ 18.956792] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11020 22:12:05.157683 et [0;1;39mSystem Initialization[0m.
11021 22:12:05.175360 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11022 22:12:05.189755 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11023 22:12:05.203317 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11024 22:12:05.222699 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11025 22:12:05.239158 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11026 22:12:05.255555 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11027 22:12:05.271606 <4>[ 19.076938] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11028 22:12:05.282330 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11029 22:12:05.331398 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11030 22:12:05.363366 Starting [0;1;39mUser Login Management[0m...
11031 22:12:05.392735 <4>[ 19.197817] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11032 22:12:05.399080 Starting [0;1;39mPermit User Sessions[0m...
11033 22:12:05.419016 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11034 22:12:05.440607 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11035 22:12:05.458902 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11036 22:12:05.474417 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11037 22:12:05.514550 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m..<4>[ 19.317913] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11038 22:12:05.515056 .
11039 22:12:05.534687 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11040 22:12:05.551569 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11041 22:12:05.559400 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11042 22:12:05.575274 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11043 22:12:05.631190 <4>[ 19.436767] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11044 22:12:05.638115 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11045 22:12:05.671518 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11046 22:12:05.742064
11047 22:12:05.742626
11048 22:12:05.755200 Debian GNU/Linux 11 debian-bu<4>[ 19.558989] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11049 22:12:05.755628 llseye-arm64 ttyS0
11050 22:12:05.755999
11051 22:12:05.761695 debian-bullseye-arm64 login: root (automatic login)
11052 22:12:05.762113
11053 22:12:05.762441
11054 22:12:05.782807 Linux debian-bullseye-arm64 6.1.46-cip4 #1 SMP PREEMPT Tue Sep 5 21:54:53 UTC 2023 aarch64
11055 22:12:05.783327
11056 22:12:05.789736 The programs included with the Debian GNU/Linux system are free software;
11057 22:12:05.796188 the exact distribution terms for each program are described in the
11058 22:12:05.799284 individual files in /usr/share/doc/*/copyright.
11059 22:12:05.799703
11060 22:12:05.806284 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11061 22:12:05.809218 permitted by applicable law.
11062 22:12:05.810323 Matched prompt #10: / #
11064 22:12:05.811360 Setting prompt string to ['/ #']
11065 22:12:05.811788 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11067 22:12:05.812744 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11068 22:12:05.813189 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
11069 22:12:05.813542 Setting prompt string to ['/ #']
11070 22:12:05.813852 Forcing a shell prompt, looking for ['/ #']
11072 22:12:05.864662 / #
11073 22:12:05.865264 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11074 22:12:05.865649 Waiting using forced prompt support (timeout 00:02:30)
11075 22:12:05.875652 <4>[ 19.681155] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11076 22:12:05.876084
11077 22:12:05.881287 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11078 22:12:05.881907 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
11079 22:12:05.882397 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11080 22:12:05.882872 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
11081 22:12:05.883304 end: 2 depthcharge-action (duration 00:01:30) [common]
11082 22:12:05.883746 start: 3 lava-test-retry (timeout 00:05:00) [common]
11083 22:12:05.884175 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11084 22:12:05.884545 Using namespace: common
11086 22:12:05.985577 / # #
11087 22:12:05.986095 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11088 22:12:06.031132 #<4>[ 19.801037] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11089 22:12:06.031699
11090 22:12:06.032447 Using /lava-11440297
11092 22:12:06.133767 / # export SHELL=/bin/sh
11093 22:12:06.134660 export SHELL=/bin/sh<4>[ 19.920861] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11094 22:12:06.140275
11096 22:12:06.241840 / # . /lava-11440297/environment
11097 22:12:06.242508 . /lava-11440297/environment<3>[ 20.038747] mt7921e 0000:01:00.0: hardware init failed
11098 22:12:06.247818
11100 22:12:06.349312 / # /lava-11440297/bin/lava-test-runner /lava-11440297/0
11101 22:12:06.349820 Test shell timeout: 10s (minimum of the action and connection timeout)
11102 22:12:06.359584 /lava-11440297/bin/lava-test-runner /lava-11440297/0<6>[ 20.168037] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
11103 22:12:06.360033
11104 22:12:06.365990 <6>[ 20.176079] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
11105 22:12:06.390172 + export TESTRUN_ID=0_cros-ec
11106 22:12:06.396522 + c<8>[ 20.207739] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11440297_1.5.2.3.1>
11107 22:12:06.397296 Received signal: <STARTRUN> 0_cros-ec 11440297_1.5.2.3.1
11108 22:12:06.397712 Starting test lava.0_cros-ec (11440297_1.5.2.3.1)
11109 22:12:06.398115 Skipping test definition patterns.
11110 22:12:06.400242 d /lava-11440297/0/tests/0_cros-ec
11111 22:12:06.403731 + cat uuid
11112 22:12:06.404258 + UUID=11440297_1.5.2.3.1
11113 22:12:06.406989 + set +x
11114 22:12:06.409881 + python3 -m cros.runners.lava_runner -v
11115 22:12:06.788556 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11116 22:12:06.798563 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11117 22:12:06.799174
11118 22:12:06.805086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11119 22:12:06.805923 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11121 22:12:06.811955 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11122 22:12:06.818048 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11123 22:12:06.821588
11124 22:12:06.828818 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8
11125 22:12:06.829378 Bad test result: ski<8
11126 22:12:06.831756 Received signal: <ENDRUN> 0_cros-ec 11440297_1.5.2.3.1
11127 22:12:06.832213 Ending use of test pattern.
11128 22:12:06.832545 Ending test lava.0_cros-ec (11440297_1.5.2.3.1), duration 0.43
11130 22:12:06.834900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8>[ 20.643130] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11440297_1.5.2.3.1>
11131 22:12:06.835324 p>
11132 22:12:06.837931 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11133 22:12:06.844769 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11134 22:12:06.845286
11135 22:12:06.851504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11136 22:12:06.852185 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11138 22:12:06.857789 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11139 22:12:06.865012 Checks the standard ABI for the main Embedded Controller. ... ok
11140 22:12:06.865538
11141 22:12:06.867834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11142 22:12:06.868633 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11144 22:12:06.874369 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11145 22:12:06.880857 Checks the main Embedded controller character device. ... ok
11146 22:12:06.881329
11147 22:12:06.887704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11148 22:12:06.888556 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11150 22:12:06.891152 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11151 22:12:06.897893 Checks basic comunication with the main Embedded controller. ... ok
11152 22:12:06.898469
11153 22:12:06.904089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11154 22:12:06.904783 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11156 22:12:06.907163 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11157 22:12:06.917209 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11158 22:12:06.917895
11159 22:12:06.920790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11160 22:12:06.921524 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11162 22:12:06.927517 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11163 22:12:06.937147 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11164 22:12:06.937838
11165 22:12:06.940345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11166 22:12:06.941035 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11168 22:12:06.947239 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11169 22:12:06.953608 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11170 22:12:06.954036
11171 22:12:06.960596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11172 22:12:06.961279 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11174 22:12:06.963485 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11175 22:12:06.973651 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11176 22:12:06.974079
11177 22:12:06.977289 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11179 22:12:06.980235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11180 22:12:06.983670 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11181 22:12:06.993113 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11182 22:12:06.993556
11183 22:12:06.997300 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11185 22:12:06.999818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11186 22:12:07.003415 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11187 22:12:07.009495 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11188 22:12:07.009922
11189 22:12:07.016467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11190 22:12:07.017146 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11192 22:12:07.023135 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11193 22:12:07.029668 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11194 22:12:07.030092
11195 22:12:07.036371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11196 22:12:07.037051 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11198 22:12:07.043031 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11199 22:12:07.049379 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11200 22:12:07.049801
11201 22:12:07.056108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11202 22:12:07.056791 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11204 22:12:07.062521 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11205 22:12:07.069297 Check the cros battery ABI. ... skipped 'No BAT found'
11206 22:12:07.069720
11207 22:12:07.075706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11208 22:12:07.076384 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11210 22:12:07.082272 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11211 22:12:07.089121 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11212 22:12:07.089548
11213 22:12:07.095455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11214 22:12:07.096141 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11216 22:12:07.101573 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11217 22:12:07.108391 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11218 22:12:07.108473
11219 22:12:07.111482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11220 22:12:07.111735 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11222 22:12:07.118097 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11223 22:12:07.125094 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11224 22:12:07.125177
11225 22:12:07.131482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11226 22:12:07.131563
11227 22:12:07.131798 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11229 22:12:07.138112 ----------------------------------------------------------------------
11230 22:12:07.141576 Ran 18 tests in 0.007s
11231 22:12:07.141657
11232 22:12:07.141720 OK (skipped=15)
11233 22:12:07.145188 + set +x
11234 22:12:07.145609 <LAVA_TEST_RUNNER EXIT>
11235 22:12:07.146200 ok: lava_test_shell seems to have completed
11236 22:12:07.147062 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11237 22:12:07.147518 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11238 22:12:07.147933 end: 3 lava-test-retry (duration 00:00:01) [common]
11239 22:12:07.148371 start: 4 finalize (timeout 00:08:07) [common]
11240 22:12:07.148816 start: 4.1 power-off (timeout 00:00:30) [common]
11241 22:12:07.149562 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11242 22:12:07.239622 >> Command sent successfully.
11243 22:12:07.244190 Returned 0 in 0 seconds
11244 22:12:07.345118 end: 4.1 power-off (duration 00:00:00) [common]
11246 22:12:07.346633 start: 4.2 read-feedback (timeout 00:08:07) [common]
11247 22:12:07.347838 Listened to connection for namespace 'common' for up to 1s
11248 22:12:08.348502 Finalising connection for namespace 'common'
11249 22:12:08.349185 Disconnecting from shell: Finalise
11250 22:12:08.349622 / #
11251 22:12:08.450469 end: 4.2 read-feedback (duration 00:00:01) [common]
11252 22:12:08.451015 end: 4 finalize (duration 00:00:01) [common]
11253 22:12:08.451402 Cleaning after the job
11254 22:12:08.451759 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/ramdisk
11255 22:12:08.473170 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/kernel
11256 22:12:08.489442 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/dtb
11257 22:12:08.489635 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440297/tftp-deploy-jjlpmr50/modules
11258 22:12:08.497117 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11440297
11259 22:12:08.617562 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11440297
11260 22:12:08.617746 Job finished correctly