Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 132
- Boot result: PASS
- Warnings: 1
- Errors: 0
- Kernel Warnings: 22
1 22:10:42.495846 lava-dispatcher, installed at version: 2023.06
2 22:10:42.496079 start: 0 validate
3 22:10:42.496231 Start time: 2023-09-05 22:10:42.496221+00:00 (UTC)
4 22:10:42.496381 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:10:42.496539 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 22:10:42.766294 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:10:42.766481 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:10:55.533204 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:10:55.533464 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:10:55.799843 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:10:55.800087 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:10:59.064730 validate duration: 16.57
14 22:10:59.065145 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:10:59.065315 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:10:59.065469 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:10:59.065663 Not decompressing ramdisk as can be used compressed.
18 22:10:59.065815 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 22:10:59.065931 saving as /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/ramdisk/rootfs.cpio.gz
20 22:10:59.066052 total size: 84918747 (80 MB)
21 22:10:59.333084 progress 0 % (0 MB)
22 22:10:59.355370 progress 5 % (4 MB)
23 22:10:59.379043 progress 10 % (8 MB)
24 22:10:59.401658 progress 15 % (12 MB)
25 22:10:59.424730 progress 20 % (16 MB)
26 22:10:59.446890 progress 25 % (20 MB)
27 22:10:59.469191 progress 30 % (24 MB)
28 22:10:59.492095 progress 35 % (28 MB)
29 22:10:59.515398 progress 40 % (32 MB)
30 22:10:59.537924 progress 45 % (36 MB)
31 22:10:59.560120 progress 50 % (40 MB)
32 22:10:59.582048 progress 55 % (44 MB)
33 22:10:59.604209 progress 60 % (48 MB)
34 22:10:59.626672 progress 65 % (52 MB)
35 22:10:59.648998 progress 70 % (56 MB)
36 22:10:59.670906 progress 75 % (60 MB)
37 22:10:59.692991 progress 80 % (64 MB)
38 22:10:59.715248 progress 85 % (68 MB)
39 22:10:59.738286 progress 90 % (72 MB)
40 22:10:59.761064 progress 95 % (76 MB)
41 22:10:59.784369 progress 100 % (80 MB)
42 22:10:59.784608 80 MB downloaded in 0.72 s (112.70 MB/s)
43 22:10:59.784785 end: 1.1.1 http-download (duration 00:00:01) [common]
45 22:10:59.785043 end: 1.1 download-retry (duration 00:00:01) [common]
46 22:10:59.785134 start: 1.2 download-retry (timeout 00:09:59) [common]
47 22:10:59.785235 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 22:10:59.785395 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:10:59.785467 saving as /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/kernel/Image
50 22:10:59.785529 total size: 49220096 (46 MB)
51 22:10:59.785592 No compression specified
52 22:10:59.786830 progress 0 % (0 MB)
53 22:10:59.800717 progress 5 % (2 MB)
54 22:10:59.813933 progress 10 % (4 MB)
55 22:10:59.827396 progress 15 % (7 MB)
56 22:10:59.840780 progress 20 % (9 MB)
57 22:10:59.854495 progress 25 % (11 MB)
58 22:10:59.868146 progress 30 % (14 MB)
59 22:10:59.881111 progress 35 % (16 MB)
60 22:10:59.894065 progress 40 % (18 MB)
61 22:10:59.907106 progress 45 % (21 MB)
62 22:10:59.920552 progress 50 % (23 MB)
63 22:10:59.933613 progress 55 % (25 MB)
64 22:10:59.946661 progress 60 % (28 MB)
65 22:10:59.959736 progress 65 % (30 MB)
66 22:10:59.972731 progress 70 % (32 MB)
67 22:10:59.985730 progress 75 % (35 MB)
68 22:10:59.998602 progress 80 % (37 MB)
69 22:11:00.011548 progress 85 % (39 MB)
70 22:11:00.024925 progress 90 % (42 MB)
71 22:11:00.037995 progress 95 % (44 MB)
72 22:11:00.051009 progress 100 % (46 MB)
73 22:11:00.051188 46 MB downloaded in 0.27 s (176.70 MB/s)
74 22:11:00.051389 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:11:00.051677 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:11:00.051796 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:11:00.051890 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:11:00.052039 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:11:00.052111 saving as /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/dtb/mt8192-asurada-spherion-r0.dtb
81 22:11:00.052174 total size: 47278 (0 MB)
82 22:11:00.052237 No compression specified
83 22:11:00.053378 progress 69 % (0 MB)
84 22:11:00.053665 progress 100 % (0 MB)
85 22:11:00.053840 0 MB downloaded in 0.00 s (27.10 MB/s)
86 22:11:00.053980 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:11:00.054206 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:11:00.054322 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:11:00.054436 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:11:00.054599 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:11:00.054684 saving as /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/modules/modules.tar
93 22:11:00.054744 total size: 8619808 (8 MB)
94 22:11:00.054806 Using unxz to decompress xz
95 22:11:00.059005 progress 0 % (0 MB)
96 22:11:00.084436 progress 5 % (0 MB)
97 22:11:00.115109 progress 10 % (0 MB)
98 22:11:00.142496 progress 15 % (1 MB)
99 22:11:00.168535 progress 20 % (1 MB)
100 22:11:00.194205 progress 25 % (2 MB)
101 22:11:00.222455 progress 30 % (2 MB)
102 22:11:00.251791 progress 35 % (2 MB)
103 22:11:00.278757 progress 40 % (3 MB)
104 22:11:00.307926 progress 45 % (3 MB)
105 22:11:00.345272 progress 50 % (4 MB)
106 22:11:00.380946 progress 55 % (4 MB)
107 22:11:00.410657 progress 60 % (4 MB)
108 22:11:00.440849 progress 65 % (5 MB)
109 22:11:00.480135 progress 70 % (5 MB)
110 22:11:00.505129 progress 75 % (6 MB)
111 22:11:00.536536 progress 80 % (6 MB)
112 22:11:00.570465 progress 85 % (7 MB)
113 22:11:00.600326 progress 90 % (7 MB)
114 22:11:00.627200 progress 95 % (7 MB)
115 22:11:00.654777 progress 100 % (8 MB)
116 22:11:00.659637 8 MB downloaded in 0.60 s (13.59 MB/s)
117 22:11:00.659913 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:11:00.660229 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:11:00.660328 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 22:11:00.660428 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 22:11:00.660546 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:11:00.660671 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 22:11:00.660957 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst
125 22:11:00.661130 makedir: /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin
126 22:11:00.661257 makedir: /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/tests
127 22:11:00.661360 makedir: /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/results
128 22:11:00.661485 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-add-keys
129 22:11:00.661641 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-add-sources
130 22:11:00.661785 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-background-process-start
131 22:11:00.661937 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-background-process-stop
132 22:11:00.662086 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-common-functions
133 22:11:00.662218 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-echo-ipv4
134 22:11:00.662350 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-install-packages
135 22:11:00.662499 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-installed-packages
136 22:11:00.662627 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-os-build
137 22:11:00.662755 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-probe-channel
138 22:11:00.662882 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-probe-ip
139 22:11:00.663012 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-target-ip
140 22:11:00.663138 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-target-mac
141 22:11:00.663294 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-target-storage
142 22:11:00.663429 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-test-case
143 22:11:00.663558 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-test-event
144 22:11:00.663727 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-test-feedback
145 22:11:00.663857 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-test-raise
146 22:11:00.663986 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-test-reference
147 22:11:00.664114 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-test-runner
148 22:11:00.664241 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-test-set
149 22:11:00.664372 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-test-shell
150 22:11:00.664538 Updating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-install-packages (oe)
151 22:11:00.664696 Updating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/bin/lava-installed-packages (oe)
152 22:11:00.664821 Creating /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/environment
153 22:11:00.664925 LAVA metadata
154 22:11:00.665022 - LAVA_JOB_ID=11440293
155 22:11:00.665119 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:11:00.665225 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 22:11:00.665294 skipped lava-vland-overlay
158 22:11:00.665369 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:11:00.665452 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 22:11:00.665516 skipped lava-multinode-overlay
161 22:11:00.665620 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:11:00.665719 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 22:11:00.665795 Loading test definitions
164 22:11:00.665886 start: 1.5.2.3.1 git-repo-action (timeout 00:09:58) [common]
165 22:11:00.665966 Using /lava-11440293 at stage 0
166 22:11:00.666080 Fetching tests from https://github.com/kernelci/kernelci-core
167 22:11:00.666227 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/0/tests/0_sleep'
168 22:11:01.384055 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/0/tests/0_sleep
169 22:11:01.386086 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 22:11:01.386722 uuid=11440293_1.5.2.3.1 testdef=None
171 22:11:01.386945 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 22:11:01.387393 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 22:11:01.388411 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 22:11:01.388822 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 22:11:01.390040 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 22:11:01.390464 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 22:11:01.391676 runner path: /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/0/tests/0_sleep test_uuid 11440293_1.5.2.3.1
181 22:11:01.391812 sleep_params='mem freeze'
182 22:11:01.392037 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 22:11:01.392437 Creating lava-test-runner.conf files
185 22:11:01.392555 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11440293/lava-overlay-wsbubcst/lava-11440293/0 for stage 0
186 22:11:01.392715 - 0_sleep
187 22:11:01.392890 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 22:11:01.393037 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 22:11:01.540525 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 22:11:01.540690 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 22:11:01.540789 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 22:11:01.540893 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 22:11:01.540983 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 22:11:07.029045 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:05) [common]
195 22:11:07.029537 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
196 22:11:07.029708 extracting modules file /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11440293/extract-overlay-ramdisk-4laps346/ramdisk
197 22:11:07.268061 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 22:11:07.268260 start: 1.5.5 apply-overlay-tftp (timeout 00:09:52) [common]
199 22:11:07.268409 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11440293/compress-overlay-wj2rtzaw/overlay-1.5.2.4.tar.gz to ramdisk
200 22:11:07.268482 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11440293/compress-overlay-wj2rtzaw/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11440293/extract-overlay-ramdisk-4laps346/ramdisk
201 22:11:07.363485 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 22:11:07.363689 start: 1.5.6 configure-preseed-file (timeout 00:09:52) [common]
203 22:11:07.363789 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 22:11:07.363882 start: 1.5.7 compress-ramdisk (timeout 00:09:52) [common]
205 22:11:07.363965 Building ramdisk /var/lib/lava/dispatcher/tmp/11440293/extract-overlay-ramdisk-4laps346/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11440293/extract-overlay-ramdisk-4laps346/ramdisk
206 22:11:08.972175 >> 563347 blocks
207 22:11:19.230453 rename /var/lib/lava/dispatcher/tmp/11440293/extract-overlay-ramdisk-4laps346/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/ramdisk/ramdisk.cpio.gz
208 22:11:19.230942 end: 1.5.7 compress-ramdisk (duration 00:00:12) [common]
209 22:11:19.231130 start: 1.5.8 prepare-kernel (timeout 00:09:40) [common]
210 22:11:19.231286 start: 1.5.8.1 prepare-fit (timeout 00:09:40) [common]
211 22:11:19.231458 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/kernel/Image'
212 22:11:32.007016 Returned 0 in 12 seconds
213 22:11:32.107687 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/kernel/image.itb
214 22:11:33.457216 output: FIT description: Kernel Image image with one or more FDT blobs
215 22:11:33.457599 output: Created: Tue Sep 5 23:11:33 2023
216 22:11:33.457676 output: Image 0 (kernel-1)
217 22:11:33.457742 output: Description:
218 22:11:33.457805 output: Created: Tue Sep 5 23:11:33 2023
219 22:11:33.457871 output: Type: Kernel Image
220 22:11:33.457933 output: Compression: lzma compressed
221 22:11:33.457993 output: Data Size: 11037994 Bytes = 10779.29 KiB = 10.53 MiB
222 22:11:33.458053 output: Architecture: AArch64
223 22:11:33.458112 output: OS: Linux
224 22:11:33.458171 output: Load Address: 0x00000000
225 22:11:33.458225 output: Entry Point: 0x00000000
226 22:11:33.458278 output: Hash algo: crc32
227 22:11:33.458331 output: Hash value: 9d08b3de
228 22:11:33.458384 output: Image 1 (fdt-1)
229 22:11:33.458438 output: Description: mt8192-asurada-spherion-r0
230 22:11:33.458491 output: Created: Tue Sep 5 23:11:33 2023
231 22:11:33.458544 output: Type: Flat Device Tree
232 22:11:33.458597 output: Compression: uncompressed
233 22:11:33.458650 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 22:11:33.458703 output: Architecture: AArch64
235 22:11:33.458755 output: Hash algo: crc32
236 22:11:33.458809 output: Hash value: cc4352de
237 22:11:33.458862 output: Image 2 (ramdisk-1)
238 22:11:33.458915 output: Description: unavailable
239 22:11:33.458968 output: Created: Tue Sep 5 23:11:33 2023
240 22:11:33.459021 output: Type: RAMDisk Image
241 22:11:33.459074 output: Compression: Unknown Compression
242 22:11:33.459127 output: Data Size: 98311238 Bytes = 96007.07 KiB = 93.76 MiB
243 22:11:33.459181 output: Architecture: AArch64
244 22:11:33.459233 output: OS: Linux
245 22:11:33.459286 output: Load Address: unavailable
246 22:11:33.459339 output: Entry Point: unavailable
247 22:11:33.459391 output: Hash algo: crc32
248 22:11:33.459444 output: Hash value: 94fb9b0d
249 22:11:33.459497 output: Default Configuration: 'conf-1'
250 22:11:33.459573 output: Configuration 0 (conf-1)
251 22:11:33.459678 output: Description: mt8192-asurada-spherion-r0
252 22:11:33.459733 output: Kernel: kernel-1
253 22:11:33.459787 output: Init Ramdisk: ramdisk-1
254 22:11:33.459840 output: FDT: fdt-1
255 22:11:33.459894 output: Loadables: kernel-1
256 22:11:33.459947 output:
257 22:11:33.460157 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 22:11:33.460252 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 22:11:33.460362 end: 1.5 prepare-tftp-overlay (duration 00:00:33) [common]
260 22:11:33.460461 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:26) [common]
261 22:11:33.460539 No LXC device requested
262 22:11:33.460623 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 22:11:33.460720 start: 1.7 deploy-device-env (timeout 00:09:26) [common]
264 22:11:33.460821 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 22:11:33.460897 Checking files for TFTP limit of 4294967296 bytes.
266 22:11:33.461466 end: 1 tftp-deploy (duration 00:00:34) [common]
267 22:11:33.461575 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 22:11:33.461665 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 22:11:33.461790 substitutions:
270 22:11:33.461861 - {DTB}: 11440293/tftp-deploy-480emkml/dtb/mt8192-asurada-spherion-r0.dtb
271 22:11:33.461928 - {INITRD}: 11440293/tftp-deploy-480emkml/ramdisk/ramdisk.cpio.gz
272 22:11:33.461988 - {KERNEL}: 11440293/tftp-deploy-480emkml/kernel/Image
273 22:11:33.462047 - {LAVA_MAC}: None
274 22:11:33.462104 - {PRESEED_CONFIG}: None
275 22:11:33.462161 - {PRESEED_LOCAL}: None
276 22:11:33.462217 - {RAMDISK}: 11440293/tftp-deploy-480emkml/ramdisk/ramdisk.cpio.gz
277 22:11:33.462272 - {ROOT_PART}: None
278 22:11:33.462327 - {ROOT}: None
279 22:11:33.462382 - {SERVER_IP}: 192.168.201.1
280 22:11:33.462436 - {TEE}: None
281 22:11:33.462492 Parsed boot commands:
282 22:11:33.462548 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 22:11:33.462730 Parsed boot commands: tftpboot 192.168.201.1 11440293/tftp-deploy-480emkml/kernel/image.itb 11440293/tftp-deploy-480emkml/kernel/cmdline
284 22:11:33.462825 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 22:11:33.462912 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 22:11:33.463009 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 22:11:33.463096 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 22:11:33.463170 Not connected, no need to disconnect.
289 22:11:33.463245 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 22:11:33.463326 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 22:11:33.463397 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
292 22:11:33.467531 Setting prompt string to ['lava-test: # ']
293 22:11:33.467970 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 22:11:33.468099 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 22:11:33.468223 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 22:11:33.468316 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 22:11:33.468537 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
298 22:11:38.616114 >> Command sent successfully.
299 22:11:38.618539 Returned 0 in 5 seconds
300 22:11:38.718942 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 22:11:38.719265 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 22:11:38.719402 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 22:11:38.719493 Setting prompt string to 'Starting depthcharge on Spherion...'
305 22:11:38.719566 Changing prompt to 'Starting depthcharge on Spherion...'
306 22:11:38.719678 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 22:11:38.719985 [Enter `^Ec?' for help]
308 22:11:38.892151
309 22:11:38.892315
310 22:11:38.892401 F0: 102B 0000
311 22:11:38.892480
312 22:11:38.895189 F3: 1001 0000 [0200]
313 22:11:38.895336
314 22:11:38.895452 F3: 1001 0000
315 22:11:38.895561
316 22:11:38.895664 F7: 102D 0000
317 22:11:38.895727
318 22:11:38.898349 F1: 0000 0000
319 22:11:38.898449
320 22:11:38.898530 V0: 0000 0000 [0001]
321 22:11:38.898594
322 22:11:38.901998 00: 0007 8000
323 22:11:38.902088
324 22:11:38.902154 01: 0000 0000
325 22:11:38.902217
326 22:11:38.905345 BP: 0C00 0209 [0000]
327 22:11:38.905429
328 22:11:38.905495 G0: 1182 0000
329 22:11:38.905557
330 22:11:38.908956 EC: 0000 0021 [4000]
331 22:11:38.909041
332 22:11:38.909106 S7: 0000 0000 [0000]
333 22:11:38.909168
334 22:11:38.912376 CC: 0000 0000 [0001]
335 22:11:38.912460
336 22:11:38.912526 T0: 0000 0040 [010F]
337 22:11:38.912587
338 22:11:38.912645 Jump to BL
339 22:11:38.912703
340 22:11:38.939555
341 22:11:38.939659
342 22:11:38.939726
343 22:11:38.946922 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 22:11:38.951112 ARM64: Exception handlers installed.
345 22:11:38.954419 ARM64: Testing exception
346 22:11:38.957549 ARM64: Done test exception
347 22:11:38.964556 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 22:11:38.974918 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 22:11:38.981531 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 22:11:38.991663 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 22:11:38.998547 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 22:11:39.004991 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 22:11:39.016029 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 22:11:39.022964 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 22:11:39.041672 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 22:11:39.045373 WDT: Last reset was cold boot
357 22:11:39.048522 SPI1(PAD0) initialized at 2873684 Hz
358 22:11:39.051779 SPI5(PAD0) initialized at 992727 Hz
359 22:11:39.055295 VBOOT: Loading verstage.
360 22:11:39.061916 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 22:11:39.065736 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 22:11:39.069034 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 22:11:39.072293 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 22:11:39.079304 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 22:11:39.085935 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 22:11:39.097133 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 22:11:39.097223
368 22:11:39.097291
369 22:11:39.107589 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 22:11:39.111281 ARM64: Exception handlers installed.
371 22:11:39.111362 ARM64: Testing exception
372 22:11:39.114509 ARM64: Done test exception
373 22:11:39.117780 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 22:11:39.124448 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 22:11:39.137990 Probing TPM: . done!
376 22:11:39.138077 TPM ready after 0 ms
377 22:11:39.145121 Connected to device vid:did:rid of 1ae0:0028:00
378 22:11:39.152192 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 22:11:39.211830 Initialized TPM device CR50 revision 0
380 22:11:39.223120 tlcl_send_startup: Startup return code is 0
381 22:11:39.223209 TPM: setup succeeded
382 22:11:39.235016 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 22:11:39.243749 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 22:11:39.255922 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 22:11:39.266525 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 22:11:39.269741 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 22:11:39.273369 in-header: 03 07 00 00 08 00 00 00
388 22:11:39.277203 in-data: aa e4 47 04 13 02 00 00
389 22:11:39.277350 Chrome EC: UHEPI supported
390 22:11:39.284135 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 22:11:39.288905 in-header: 03 95 00 00 08 00 00 00
392 22:11:39.292176 in-data: 18 20 20 08 00 00 00 00
393 22:11:39.292261 Phase 1
394 22:11:39.296073 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 22:11:39.303034 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 22:11:39.310690 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 22:11:39.310775 Recovery requested (1009000e)
398 22:11:39.321479 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 22:11:39.326756 tlcl_extend: response is 0
400 22:11:39.336344 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 22:11:39.342152 tlcl_extend: response is 0
402 22:11:39.348662 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 22:11:39.368533 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 22:11:39.375484 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 22:11:39.375569
406 22:11:39.375673
407 22:11:39.385355 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 22:11:39.388733 ARM64: Exception handlers installed.
409 22:11:39.392012 ARM64: Testing exception
410 22:11:39.392098 ARM64: Done test exception
411 22:11:39.414607 pmic_efuse_setting: Set efuses in 11 msecs
412 22:11:39.417728 pmwrap_interface_init: Select PMIF_VLD_RDY
413 22:11:39.424228 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 22:11:39.428401 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 22:11:39.431872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 22:11:39.438833 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 22:11:39.442588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 22:11:39.449751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 22:11:39.453511 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 22:11:39.457100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 22:11:39.460979 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 22:11:39.468413 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 22:11:39.472457 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 22:11:39.475546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 22:11:39.478865 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 22:11:39.486638 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 22:11:39.494065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 22:11:39.497993 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 22:11:39.505539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 22:11:39.509146 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 22:11:39.516655 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 22:11:39.519967 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 22:11:39.527187 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 22:11:39.530938 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 22:11:39.538487 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 22:11:39.542247 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 22:11:39.549575 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 22:11:39.552901 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 22:11:39.561051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 22:11:39.564183 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 22:11:39.568023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 22:11:39.571463 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 22:11:39.578956 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 22:11:39.582492 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 22:11:39.590161 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 22:11:39.593458 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 22:11:39.597258 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 22:11:39.604606 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 22:11:39.608328 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 22:11:39.612062 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 22:11:39.615908 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 22:11:39.623560 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 22:11:39.627027 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 22:11:39.630697 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 22:11:39.634410 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 22:11:39.642094 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 22:11:39.645461 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 22:11:39.649107 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 22:11:39.652890 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 22:11:39.656331 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 22:11:39.660035 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 22:11:39.667047 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 22:11:39.671081 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 22:11:39.678629 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 22:11:39.685981 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 22:11:39.690010 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 22:11:39.697400 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 22:11:39.708239 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 22:11:39.711867 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 22:11:39.715433 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 22:11:39.718698 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 22:11:39.726976 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1e
473 22:11:39.734595 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 22:11:39.738228 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 22:11:39.741859 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 22:11:39.752260 [RTC]rtc_get_frequency_meter,154: input=15, output=759
477 22:11:39.761376 [RTC]rtc_get_frequency_meter,154: input=23, output=941
478 22:11:39.770677 [RTC]rtc_get_frequency_meter,154: input=19, output=851
479 22:11:39.780498 [RTC]rtc_get_frequency_meter,154: input=17, output=803
480 22:11:39.790043 [RTC]rtc_get_frequency_meter,154: input=16, output=782
481 22:11:39.799709 [RTC]rtc_get_frequency_meter,154: input=16, output=782
482 22:11:39.809582 [RTC]rtc_get_frequency_meter,154: input=17, output=806
483 22:11:39.813209 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 22:11:39.816750 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 22:11:39.820209 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 22:11:39.827711 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 22:11:39.831418 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 22:11:39.835233 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 22:11:39.838871 ADC[4]: Raw value=906203 ID=7
490 22:11:39.838971 ADC[3]: Raw value=213441 ID=1
491 22:11:39.842907 RAM Code: 0x71
492 22:11:39.846699 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 22:11:39.853756 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 22:11:39.861133 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 22:11:39.868457 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 22:11:39.868542 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 22:11:39.872260 in-header: 03 07 00 00 08 00 00 00
498 22:11:39.875414 in-data: aa e4 47 04 13 02 00 00
499 22:11:39.879399 Chrome EC: UHEPI supported
500 22:11:39.887140 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 22:11:39.890525 in-header: 03 95 00 00 08 00 00 00
502 22:11:39.894120 in-data: 18 20 20 08 00 00 00 00
503 22:11:39.897680 MRC: failed to locate region type 0.
504 22:11:39.905397 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 22:11:39.905486 DRAM-K: Running full calibration
506 22:11:39.912925 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 22:11:39.917015 header.status = 0x0
508 22:11:39.917101 header.version = 0x6 (expected: 0x6)
509 22:11:39.920183 header.size = 0xd00 (expected: 0xd00)
510 22:11:39.924319 header.flags = 0x0
511 22:11:39.927637 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 22:11:39.947995 read SPI 0x72590 0x1c583: 12496 us, 9290 KB/s, 74.320 Mbps
513 22:11:39.955890 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 22:11:39.955978 dram_init: ddr_geometry: 2
515 22:11:39.959520 [EMI] MDL number = 2
516 22:11:39.959668 [EMI] Get MDL freq = 0
517 22:11:39.963032 dram_init: ddr_type: 0
518 22:11:39.966380 is_discrete_lpddr4: 1
519 22:11:39.966467 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 22:11:39.966554
521 22:11:39.970158
522 22:11:39.970290 [Bian_co] ETT version 0.0.0.1
523 22:11:39.977603 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 22:11:39.977728
525 22:11:39.981398 dramc_set_vcore_voltage set vcore to 650000
526 22:11:39.981485 Read voltage for 800, 4
527 22:11:39.981572 Vio18 = 0
528 22:11:39.985057 Vcore = 650000
529 22:11:39.985143 Vdram = 0
530 22:11:39.985248 Vddq = 0
531 22:11:39.988650 Vmddr = 0
532 22:11:39.988736 dram_init: config_dvfs: 1
533 22:11:39.992386 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 22:11:39.999864 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 22:11:40.003357 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
536 22:11:40.006915 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
537 22:11:40.010772 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
538 22:11:40.014322 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
539 22:11:40.017084 MEM_TYPE=3, freq_sel=18
540 22:11:40.020665 sv_algorithm_assistance_LP4_1600
541 22:11:40.023747 ============ PULL DRAM RESETB DOWN ============
542 22:11:40.027520 ========== PULL DRAM RESETB DOWN end =========
543 22:11:40.034892 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 22:11:40.034976 ===================================
545 22:11:40.038704 LPDDR4 DRAM CONFIGURATION
546 22:11:40.041960 ===================================
547 22:11:40.045802 EX_ROW_EN[0] = 0x0
548 22:11:40.045886 EX_ROW_EN[1] = 0x0
549 22:11:40.049540 LP4Y_EN = 0x0
550 22:11:40.049641 WORK_FSP = 0x0
551 22:11:40.049765 WL = 0x2
552 22:11:40.053313 RL = 0x2
553 22:11:40.053396 BL = 0x2
554 22:11:40.056485 RPST = 0x0
555 22:11:40.059573 RD_PRE = 0x0
556 22:11:40.059682 WR_PRE = 0x1
557 22:11:40.063249 WR_PST = 0x0
558 22:11:40.063349 DBI_WR = 0x0
559 22:11:40.066481 DBI_RD = 0x0
560 22:11:40.066565 OTF = 0x1
561 22:11:40.069848 ===================================
562 22:11:40.073543 ===================================
563 22:11:40.073627 ANA top config
564 22:11:40.076864 ===================================
565 22:11:40.079965 DLL_ASYNC_EN = 0
566 22:11:40.083785 ALL_SLAVE_EN = 1
567 22:11:40.086868 NEW_RANK_MODE = 1
568 22:11:40.086953 DLL_IDLE_MODE = 1
569 22:11:40.090018 LP45_APHY_COMB_EN = 1
570 22:11:40.093752 TX_ODT_DIS = 1
571 22:11:40.096967 NEW_8X_MODE = 1
572 22:11:40.100659 ===================================
573 22:11:40.103480 ===================================
574 22:11:40.107537 data_rate = 1600
575 22:11:40.107659 CKR = 1
576 22:11:40.109951 DQ_P2S_RATIO = 8
577 22:11:40.113720 ===================================
578 22:11:40.116604 CA_P2S_RATIO = 8
579 22:11:40.119923 DQ_CA_OPEN = 0
580 22:11:40.123437 DQ_SEMI_OPEN = 0
581 22:11:40.126724 CA_SEMI_OPEN = 0
582 22:11:40.126808 CA_FULL_RATE = 0
583 22:11:40.130132 DQ_CKDIV4_EN = 1
584 22:11:40.133616 CA_CKDIV4_EN = 1
585 22:11:40.136836 CA_PREDIV_EN = 0
586 22:11:40.140328 PH8_DLY = 0
587 22:11:40.140412 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 22:11:40.143306 DQ_AAMCK_DIV = 4
589 22:11:40.147192 CA_AAMCK_DIV = 4
590 22:11:40.150402 CA_ADMCK_DIV = 4
591 22:11:40.153921 DQ_TRACK_CA_EN = 0
592 22:11:40.157296 CA_PICK = 800
593 22:11:40.161196 CA_MCKIO = 800
594 22:11:40.161299 MCKIO_SEMI = 0
595 22:11:40.164577 PLL_FREQ = 3068
596 22:11:40.168987 DQ_UI_PI_RATIO = 32
597 22:11:40.171879 CA_UI_PI_RATIO = 0
598 22:11:40.171963 ===================================
599 22:11:40.176536 ===================================
600 22:11:40.180040 memory_type:LPDDR4
601 22:11:40.180123 GP_NUM : 10
602 22:11:40.184194 SRAM_EN : 1
603 22:11:40.184278 MD32_EN : 0
604 22:11:40.187849 ===================================
605 22:11:40.191031 [ANA_INIT] >>>>>>>>>>>>>>
606 22:11:40.195052 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 22:11:40.197948 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 22:11:40.201597 ===================================
609 22:11:40.204836 data_rate = 1600,PCW = 0X7600
610 22:11:40.204920 ===================================
611 22:11:40.211560 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 22:11:40.214841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 22:11:40.221559 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 22:11:40.224599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 22:11:40.228358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 22:11:40.231578 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 22:11:40.234652 [ANA_INIT] flow start
618 22:11:40.238549 [ANA_INIT] PLL >>>>>>>>
619 22:11:40.238632 [ANA_INIT] PLL <<<<<<<<
620 22:11:40.241606 [ANA_INIT] MIDPI >>>>>>>>
621 22:11:40.245250 [ANA_INIT] MIDPI <<<<<<<<
622 22:11:40.245338 [ANA_INIT] DLL >>>>>>>>
623 22:11:40.248709 [ANA_INIT] flow end
624 22:11:40.252492 ============ LP4 DIFF to SE enter ============
625 22:11:40.255051 ============ LP4 DIFF to SE exit ============
626 22:11:40.258673 [ANA_INIT] <<<<<<<<<<<<<
627 22:11:40.262112 [Flow] Enable top DCM control >>>>>
628 22:11:40.265404 [Flow] Enable top DCM control <<<<<
629 22:11:40.268544 Enable DLL master slave shuffle
630 22:11:40.271760 ==============================================================
631 22:11:40.275263 Gating Mode config
632 22:11:40.282216 ==============================================================
633 22:11:40.282301 Config description:
634 22:11:40.292228 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 22:11:40.298839 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 22:11:40.302336 SELPH_MODE 0: By rank 1: By Phase
637 22:11:40.308955 ==============================================================
638 22:11:40.312211 GAT_TRACK_EN = 1
639 22:11:40.315610 RX_GATING_MODE = 2
640 22:11:40.319028 RX_GATING_TRACK_MODE = 2
641 22:11:40.322238 SELPH_MODE = 1
642 22:11:40.325578 PICG_EARLY_EN = 1
643 22:11:40.328733 VALID_LAT_VALUE = 1
644 22:11:40.332396 ==============================================================
645 22:11:40.335545 Enter into Gating configuration >>>>
646 22:11:40.338857 Exit from Gating configuration <<<<
647 22:11:40.342177 Enter into DVFS_PRE_config >>>>>
648 22:11:40.352236 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 22:11:40.355546 Exit from DVFS_PRE_config <<<<<
650 22:11:40.358887 Enter into PICG configuration >>>>
651 22:11:40.362567 Exit from PICG configuration <<<<
652 22:11:40.365796 [RX_INPUT] configuration >>>>>
653 22:11:40.368933 [RX_INPUT] configuration <<<<<
654 22:11:40.375761 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 22:11:40.379012 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 22:11:40.385792 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 22:11:40.392424 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 22:11:40.399447 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 22:11:40.402624 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 22:11:40.409150 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 22:11:40.412620 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 22:11:40.415773 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 22:11:40.419412 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 22:11:40.425944 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 22:11:40.429235 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 22:11:40.432729 ===================================
667 22:11:40.436015 LPDDR4 DRAM CONFIGURATION
668 22:11:40.439285 ===================================
669 22:11:40.439368 EX_ROW_EN[0] = 0x0
670 22:11:40.442792 EX_ROW_EN[1] = 0x0
671 22:11:40.442876 LP4Y_EN = 0x0
672 22:11:40.446462 WORK_FSP = 0x0
673 22:11:40.446545 WL = 0x2
674 22:11:40.449339 RL = 0x2
675 22:11:40.449423 BL = 0x2
676 22:11:40.452940 RPST = 0x0
677 22:11:40.453023 RD_PRE = 0x0
678 22:11:40.456097 WR_PRE = 0x1
679 22:11:40.456207 WR_PST = 0x0
680 22:11:40.459366 DBI_WR = 0x0
681 22:11:40.459458 DBI_RD = 0x0
682 22:11:40.462829 OTF = 0x1
683 22:11:40.466344 ===================================
684 22:11:40.469542 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 22:11:40.472750 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 22:11:40.479690 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 22:11:40.482876 ===================================
688 22:11:40.482960 LPDDR4 DRAM CONFIGURATION
689 22:11:40.486063 ===================================
690 22:11:40.489505 EX_ROW_EN[0] = 0x10
691 22:11:40.492858 EX_ROW_EN[1] = 0x0
692 22:11:40.492942 LP4Y_EN = 0x0
693 22:11:40.496124 WORK_FSP = 0x0
694 22:11:40.496208 WL = 0x2
695 22:11:40.499844 RL = 0x2
696 22:11:40.499928 BL = 0x2
697 22:11:40.503079 RPST = 0x0
698 22:11:40.503162 RD_PRE = 0x0
699 22:11:40.506804 WR_PRE = 0x1
700 22:11:40.506888 WR_PST = 0x0
701 22:11:40.509911 DBI_WR = 0x0
702 22:11:40.510040 DBI_RD = 0x0
703 22:11:40.513284 OTF = 0x1
704 22:11:40.516189 ===================================
705 22:11:40.523043 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 22:11:40.526169 nWR fixed to 40
707 22:11:40.526253 [ModeRegInit_LP4] CH0 RK0
708 22:11:40.529373 [ModeRegInit_LP4] CH0 RK1
709 22:11:40.532702 [ModeRegInit_LP4] CH1 RK0
710 22:11:40.532786 [ModeRegInit_LP4] CH1 RK1
711 22:11:40.536172 match AC timing 13
712 22:11:40.539912 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 22:11:40.542851 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 22:11:40.549667 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 22:11:40.552915 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 22:11:40.559936 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 22:11:40.560020 [EMI DOE] emi_dcm 0
718 22:11:40.563117 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 22:11:40.566154 ==
720 22:11:40.566238 Dram Type= 6, Freq= 0, CH_0, rank 0
721 22:11:40.573162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 22:11:40.573246 ==
723 22:11:40.576113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 22:11:40.583184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 22:11:40.592904 [CA 0] Center 36 (6~67) winsize 62
726 22:11:40.596028 [CA 1] Center 36 (6~67) winsize 62
727 22:11:40.599492 [CA 2] Center 34 (4~65) winsize 62
728 22:11:40.602804 [CA 3] Center 33 (3~64) winsize 62
729 22:11:40.606111 [CA 4] Center 33 (3~64) winsize 62
730 22:11:40.609351 [CA 5] Center 33 (3~63) winsize 61
731 22:11:40.609434
732 22:11:40.612623 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 22:11:40.612707
734 22:11:40.616210 [CATrainingPosCal] consider 1 rank data
735 22:11:40.619493 u2DelayCellTimex100 = 270/100 ps
736 22:11:40.622776 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
737 22:11:40.626014 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
738 22:11:40.629418 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
739 22:11:40.636243 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
740 22:11:40.639746 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
741 22:11:40.643099 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
742 22:11:40.643182
743 22:11:40.646376 CA PerBit enable=1, Macro0, CA PI delay=33
744 22:11:40.646460
745 22:11:40.650077 [CBTSetCACLKResult] CA Dly = 33
746 22:11:40.650160 CS Dly: 4 (0~35)
747 22:11:40.650224 ==
748 22:11:40.653200 Dram Type= 6, Freq= 0, CH_0, rank 1
749 22:11:40.660037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 22:11:40.660121 ==
751 22:11:40.663255 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 22:11:40.669950 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 22:11:40.679011 [CA 0] Center 36 (6~67) winsize 62
754 22:11:40.681991 [CA 1] Center 36 (6~67) winsize 62
755 22:11:40.685568 [CA 2] Center 34 (4~65) winsize 62
756 22:11:40.688927 [CA 3] Center 33 (3~64) winsize 62
757 22:11:40.692218 [CA 4] Center 32 (2~63) winsize 62
758 22:11:40.695472 [CA 5] Center 32 (2~63) winsize 62
759 22:11:40.695570
760 22:11:40.698686 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 22:11:40.698797
762 22:11:40.702168 [CATrainingPosCal] consider 2 rank data
763 22:11:40.705395 u2DelayCellTimex100 = 270/100 ps
764 22:11:40.708926 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
765 22:11:40.712519 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
766 22:11:40.715960 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
767 22:11:40.722302 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
768 22:11:40.725661 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
769 22:11:40.728953 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
770 22:11:40.729032
771 22:11:40.732655 CA PerBit enable=1, Macro0, CA PI delay=33
772 22:11:40.732744
773 22:11:40.736072 [CBTSetCACLKResult] CA Dly = 33
774 22:11:40.736163 CS Dly: 5 (0~37)
775 22:11:40.736239
776 22:11:40.739262 ----->DramcWriteLeveling(PI) begin...
777 22:11:40.739339 ==
778 22:11:40.743190 Dram Type= 6, Freq= 0, CH_0, rank 0
779 22:11:40.747398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 22:11:40.747482 ==
781 22:11:40.751118 Write leveling (Byte 0): 35 => 35
782 22:11:40.754996 Write leveling (Byte 1): 31 => 31
783 22:11:40.757978 DramcWriteLeveling(PI) end<-----
784 22:11:40.758072
785 22:11:40.758138 ==
786 22:11:40.761383 Dram Type= 6, Freq= 0, CH_0, rank 0
787 22:11:40.765192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 22:11:40.765277 ==
789 22:11:40.769092 [Gating] SW mode calibration
790 22:11:40.775945 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 22:11:40.779253 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 22:11:40.785914 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 22:11:40.789362 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 22:11:40.792583 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 22:11:40.799175 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:11:40.802841 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:11:40.806007 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:11:40.809099 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:11:40.815865 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:11:40.819679 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:11:40.822977 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:11:40.829384 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:11:40.832757 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:11:40.836044 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:11:40.842952 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:11:40.846278 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:11:40.849404 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:11:40.856406 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:11:40.859531 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 22:11:40.863143 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
811 22:11:40.866585 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:11:40.873089 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 22:11:40.876235 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 22:11:40.880046 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 22:11:40.886620 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 22:11:40.889926 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 22:11:40.892954 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 22:11:40.899922 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
819 22:11:40.903345 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
820 22:11:40.906542 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 22:11:40.913097 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 22:11:40.916974 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 22:11:40.919900 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 22:11:40.926868 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 22:11:40.930038 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
826 22:11:40.933843 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
827 22:11:40.937030 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
828 22:11:40.943501 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 22:11:40.946872 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 22:11:40.950062 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 22:11:40.956974 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 22:11:40.960436 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 22:11:40.963479 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 22:11:40.970609 0 11 8 | B1->B0 | 2a2a 3b3b | 0 1 | (0 0) (0 0)
835 22:11:40.973640 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
836 22:11:40.976705 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 22:11:40.983585 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 22:11:40.986693 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 22:11:40.989988 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 22:11:40.997201 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 22:11:41.000385 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
842 22:11:41.003602 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
843 22:11:41.010170 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
844 22:11:41.013455 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:11:41.016856 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:11:41.020515 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:11:41.026875 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:11:41.030125 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:11:41.033641 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:11:41.040059 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:11:41.043353 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 22:11:41.047053 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 22:11:41.053457 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 22:11:41.057130 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 22:11:41.060348 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 22:11:41.066825 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 22:11:41.070560 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 22:11:41.073839 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 22:11:41.077128 Total UI for P1: 0, mck2ui 16
860 22:11:41.080828 best dqsien dly found for B0: ( 0, 14, 6)
861 22:11:41.083938 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 22:11:41.087103 Total UI for P1: 0, mck2ui 16
863 22:11:41.090618 best dqsien dly found for B1: ( 0, 14, 8)
864 22:11:41.094707 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
865 22:11:41.098462 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 22:11:41.098547
867 22:11:41.101934 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
868 22:11:41.105141 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 22:11:41.108580 [Gating] SW calibration Done
870 22:11:41.108663 ==
871 22:11:41.111793 Dram Type= 6, Freq= 0, CH_0, rank 0
872 22:11:41.118257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 22:11:41.118342 ==
874 22:11:41.118408 RX Vref Scan: 0
875 22:11:41.118469
876 22:11:41.122033 RX Vref 0 -> 0, step: 1
877 22:11:41.122117
878 22:11:41.124996 RX Delay -130 -> 252, step: 16
879 22:11:41.128666 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
880 22:11:41.131959 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
881 22:11:41.135100 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
882 22:11:41.138392 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
883 22:11:41.145103 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 22:11:41.148432 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
885 22:11:41.151691 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
886 22:11:41.155031 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
887 22:11:41.158440 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
888 22:11:41.165097 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
889 22:11:41.168458 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
890 22:11:41.172148 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
891 22:11:41.175380 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
892 22:11:41.178624 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
893 22:11:41.185253 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
894 22:11:41.188880 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
895 22:11:41.188963 ==
896 22:11:41.191931 Dram Type= 6, Freq= 0, CH_0, rank 0
897 22:11:41.195328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 22:11:41.195412 ==
899 22:11:41.198920 DQS Delay:
900 22:11:41.199004 DQS0 = 0, DQS1 = 0
901 22:11:41.199070 DQM Delay:
902 22:11:41.202039 DQM0 = 92, DQM1 = 84
903 22:11:41.202123 DQ Delay:
904 22:11:41.205562 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
905 22:11:41.208550 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
906 22:11:41.212074 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
907 22:11:41.215393 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
908 22:11:41.215477
909 22:11:41.215542
910 22:11:41.215625 ==
911 22:11:41.218854 Dram Type= 6, Freq= 0, CH_0, rank 0
912 22:11:41.222311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 22:11:41.225470 ==
914 22:11:41.225553
915 22:11:41.225618
916 22:11:41.225678 TX Vref Scan disable
917 22:11:41.228754 == TX Byte 0 ==
918 22:11:41.231873 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
919 22:11:41.235259 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
920 22:11:41.238566 == TX Byte 1 ==
921 22:11:41.242292 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
922 22:11:41.245208 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
923 22:11:41.248932 ==
924 22:11:41.252144 Dram Type= 6, Freq= 0, CH_0, rank 0
925 22:11:41.255009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 22:11:41.255113 ==
927 22:11:41.267985 TX Vref=22, minBit 8, minWin=27, winSum=449
928 22:11:41.271089 TX Vref=24, minBit 14, minWin=27, winSum=452
929 22:11:41.274609 TX Vref=26, minBit 8, minWin=27, winSum=454
930 22:11:41.277850 TX Vref=28, minBit 5, minWin=28, winSum=456
931 22:11:41.281348 TX Vref=30, minBit 5, minWin=28, winSum=456
932 22:11:41.288208 TX Vref=32, minBit 10, minWin=27, winSum=453
933 22:11:41.291447 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 28
934 22:11:41.291534
935 22:11:41.294566 Final TX Range 1 Vref 28
936 22:11:41.294649
937 22:11:41.294713 ==
938 22:11:41.297815 Dram Type= 6, Freq= 0, CH_0, rank 0
939 22:11:41.301409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 22:11:41.301493 ==
941 22:11:41.304383
942 22:11:41.304466
943 22:11:41.304531 TX Vref Scan disable
944 22:11:41.308235 == TX Byte 0 ==
945 22:11:41.311415 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
946 22:11:41.314733 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
947 22:11:41.318398 == TX Byte 1 ==
948 22:11:41.321406 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 22:11:41.324667 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 22:11:41.328120
951 22:11:41.328203 [DATLAT]
952 22:11:41.328268 Freq=800, CH0 RK0
953 22:11:41.328329
954 22:11:41.331747 DATLAT Default: 0xa
955 22:11:41.331830 0, 0xFFFF, sum = 0
956 22:11:41.335095 1, 0xFFFF, sum = 0
957 22:11:41.335195 2, 0xFFFF, sum = 0
958 22:11:41.338449 3, 0xFFFF, sum = 0
959 22:11:41.338549 4, 0xFFFF, sum = 0
960 22:11:41.341857 5, 0xFFFF, sum = 0
961 22:11:41.341942 6, 0xFFFF, sum = 0
962 22:11:41.344993 7, 0xFFFF, sum = 0
963 22:11:41.345077 8, 0xFFFF, sum = 0
964 22:11:41.348686 9, 0x0, sum = 1
965 22:11:41.348770 10, 0x0, sum = 2
966 22:11:41.351751 11, 0x0, sum = 3
967 22:11:41.351836 12, 0x0, sum = 4
968 22:11:41.354897 best_step = 10
969 22:11:41.354996
970 22:11:41.355075 ==
971 22:11:41.358624 Dram Type= 6, Freq= 0, CH_0, rank 0
972 22:11:41.361707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 22:11:41.361791 ==
974 22:11:41.364922 RX Vref Scan: 1
975 22:11:41.365017
976 22:11:41.365082 Set Vref Range= 32 -> 127
977 22:11:41.365143
978 22:11:41.368555 RX Vref 32 -> 127, step: 1
979 22:11:41.368638
980 22:11:41.371900 RX Delay -95 -> 252, step: 8
981 22:11:41.371983
982 22:11:41.375158 Set Vref, RX VrefLevel [Byte0]: 32
983 22:11:41.378511 [Byte1]: 32
984 22:11:41.378594
985 22:11:41.381701 Set Vref, RX VrefLevel [Byte0]: 33
986 22:11:41.385045 [Byte1]: 33
987 22:11:41.388497
988 22:11:41.388580 Set Vref, RX VrefLevel [Byte0]: 34
989 22:11:41.392004 [Byte1]: 34
990 22:11:41.396225
991 22:11:41.396308 Set Vref, RX VrefLevel [Byte0]: 35
992 22:11:41.399315 [Byte1]: 35
993 22:11:41.404096
994 22:11:41.404196 Set Vref, RX VrefLevel [Byte0]: 36
995 22:11:41.407239 [Byte1]: 36
996 22:11:41.412191
997 22:11:41.412290 Set Vref, RX VrefLevel [Byte0]: 37
998 22:11:41.415423 [Byte1]: 37
999 22:11:41.419320
1000 22:11:41.419418 Set Vref, RX VrefLevel [Byte0]: 38
1001 22:11:41.422441 [Byte1]: 38
1002 22:11:41.426954
1003 22:11:41.427058 Set Vref, RX VrefLevel [Byte0]: 39
1004 22:11:41.430514 [Byte1]: 39
1005 22:11:41.434081
1006 22:11:41.434180 Set Vref, RX VrefLevel [Byte0]: 40
1007 22:11:41.437526 [Byte1]: 40
1008 22:11:41.441873
1009 22:11:41.441956 Set Vref, RX VrefLevel [Byte0]: 41
1010 22:11:41.444944 [Byte1]: 41
1011 22:11:41.449327
1012 22:11:41.449449 Set Vref, RX VrefLevel [Byte0]: 42
1013 22:11:41.452446 [Byte1]: 42
1014 22:11:41.456684
1015 22:11:41.456767 Set Vref, RX VrefLevel [Byte0]: 43
1016 22:11:41.460491 [Byte1]: 43
1017 22:11:41.464625
1018 22:11:41.464712 Set Vref, RX VrefLevel [Byte0]: 44
1019 22:11:41.467910 [Byte1]: 44
1020 22:11:41.471815
1021 22:11:41.471897 Set Vref, RX VrefLevel [Byte0]: 45
1022 22:11:41.475556 [Byte1]: 45
1023 22:11:41.479525
1024 22:11:41.479646 Set Vref, RX VrefLevel [Byte0]: 46
1025 22:11:41.483143 [Byte1]: 46
1026 22:11:41.487483
1027 22:11:41.487565 Set Vref, RX VrefLevel [Byte0]: 47
1028 22:11:41.490396 [Byte1]: 47
1029 22:11:41.494574
1030 22:11:41.494656 Set Vref, RX VrefLevel [Byte0]: 48
1031 22:11:41.498469 [Byte1]: 48
1032 22:11:41.502574
1033 22:11:41.502657 Set Vref, RX VrefLevel [Byte0]: 49
1034 22:11:41.505826 [Byte1]: 49
1035 22:11:41.510088
1036 22:11:41.510170 Set Vref, RX VrefLevel [Byte0]: 50
1037 22:11:41.513336 [Byte1]: 50
1038 22:11:41.517503
1039 22:11:41.517584 Set Vref, RX VrefLevel [Byte0]: 51
1040 22:11:41.520929 [Byte1]: 51
1041 22:11:41.525285
1042 22:11:41.525366 Set Vref, RX VrefLevel [Byte0]: 52
1043 22:11:41.528675 [Byte1]: 52
1044 22:11:41.532915
1045 22:11:41.532997 Set Vref, RX VrefLevel [Byte0]: 53
1046 22:11:41.535950 [Byte1]: 53
1047 22:11:41.540124
1048 22:11:41.540206 Set Vref, RX VrefLevel [Byte0]: 54
1049 22:11:41.543733 [Byte1]: 54
1050 22:11:41.547893
1051 22:11:41.548014 Set Vref, RX VrefLevel [Byte0]: 55
1052 22:11:41.551334 [Byte1]: 55
1053 22:11:41.555385
1054 22:11:41.555511 Set Vref, RX VrefLevel [Byte0]: 56
1055 22:11:41.559056 [Byte1]: 56
1056 22:11:41.563319
1057 22:11:41.563440 Set Vref, RX VrefLevel [Byte0]: 57
1058 22:11:41.566394 [Byte1]: 57
1059 22:11:41.570671
1060 22:11:41.570791 Set Vref, RX VrefLevel [Byte0]: 58
1061 22:11:41.573918 [Byte1]: 58
1062 22:11:41.578163
1063 22:11:41.578284 Set Vref, RX VrefLevel [Byte0]: 59
1064 22:11:41.581747 [Byte1]: 59
1065 22:11:41.585836
1066 22:11:41.585941 Set Vref, RX VrefLevel [Byte0]: 60
1067 22:11:41.589392 [Byte1]: 60
1068 22:11:41.593875
1069 22:11:41.593956 Set Vref, RX VrefLevel [Byte0]: 61
1070 22:11:41.596888 [Byte1]: 61
1071 22:11:41.601339
1072 22:11:41.601436 Set Vref, RX VrefLevel [Byte0]: 62
1073 22:11:41.604326 [Byte1]: 62
1074 22:11:41.608868
1075 22:11:41.608949 Set Vref, RX VrefLevel [Byte0]: 63
1076 22:11:41.612203 [Byte1]: 63
1077 22:11:41.616356
1078 22:11:41.616438 Set Vref, RX VrefLevel [Byte0]: 64
1079 22:11:41.619768 [Byte1]: 64
1080 22:11:41.623895
1081 22:11:41.623977 Set Vref, RX VrefLevel [Byte0]: 65
1082 22:11:41.627500 [Byte1]: 65
1083 22:11:41.631436
1084 22:11:41.631531 Set Vref, RX VrefLevel [Byte0]: 66
1085 22:11:41.635034 [Byte1]: 66
1086 22:11:41.639502
1087 22:11:41.639606 Set Vref, RX VrefLevel [Byte0]: 67
1088 22:11:41.642907 [Byte1]: 67
1089 22:11:41.646923
1090 22:11:41.647005 Set Vref, RX VrefLevel [Byte0]: 68
1091 22:11:41.650172 [Byte1]: 68
1092 22:11:41.654286
1093 22:11:41.654367 Set Vref, RX VrefLevel [Byte0]: 69
1094 22:11:41.657805 [Byte1]: 69
1095 22:11:41.662258
1096 22:11:41.662339 Set Vref, RX VrefLevel [Byte0]: 70
1097 22:11:41.665237 [Byte1]: 70
1098 22:11:41.669579
1099 22:11:41.669661 Set Vref, RX VrefLevel [Byte0]: 71
1100 22:11:41.673033 [Byte1]: 71
1101 22:11:41.677468
1102 22:11:41.677552 Set Vref, RX VrefLevel [Byte0]: 72
1103 22:11:41.680495 [Byte1]: 72
1104 22:11:41.684566
1105 22:11:41.684647 Set Vref, RX VrefLevel [Byte0]: 73
1106 22:11:41.688139 [Byte1]: 73
1107 22:11:41.692815
1108 22:11:41.692896 Set Vref, RX VrefLevel [Byte0]: 74
1109 22:11:41.695981 [Byte1]: 74
1110 22:11:41.700182
1111 22:11:41.700277 Set Vref, RX VrefLevel [Byte0]: 75
1112 22:11:41.703312 [Byte1]: 75
1113 22:11:41.707616
1114 22:11:41.707711 Final RX Vref Byte 0 = 58 to rank0
1115 22:11:41.710936 Final RX Vref Byte 1 = 59 to rank0
1116 22:11:41.714133 Final RX Vref Byte 0 = 58 to rank1
1117 22:11:41.717900 Final RX Vref Byte 1 = 59 to rank1==
1118 22:11:41.720810 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 22:11:41.724549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 22:11:41.727949 ==
1121 22:11:41.728031 DQS Delay:
1122 22:11:41.728096 DQS0 = 0, DQS1 = 0
1123 22:11:41.731312 DQM Delay:
1124 22:11:41.731394 DQM0 = 92, DQM1 = 85
1125 22:11:41.734353 DQ Delay:
1126 22:11:41.734434 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1127 22:11:41.737934 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1128 22:11:41.741134 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1129 22:11:41.744568 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1130 22:11:41.744651
1131 22:11:41.747695
1132 22:11:41.754495 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d44, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1133 22:11:41.757913 CH0 RK0: MR19=606, MR18=4D44
1134 22:11:41.764950 CH0_RK0: MR19=0x606, MR18=0x4D44, DQSOSC=390, MR23=63, INC=97, DEC=64
1135 22:11:41.765035
1136 22:11:41.767946 ----->DramcWriteLeveling(PI) begin...
1137 22:11:41.768057 ==
1138 22:11:41.771422 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 22:11:41.774443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 22:11:41.774526 ==
1141 22:11:41.778068 Write leveling (Byte 0): 32 => 32
1142 22:11:41.781202 Write leveling (Byte 1): 31 => 31
1143 22:11:41.784533 DramcWriteLeveling(PI) end<-----
1144 22:11:41.784616
1145 22:11:41.784679 ==
1146 22:11:41.788124 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 22:11:41.791560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 22:11:41.791665 ==
1149 22:11:41.794691 [Gating] SW mode calibration
1150 22:11:41.801506 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 22:11:41.807991 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 22:11:41.811260 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 22:11:41.855407 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 22:11:41.855687 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 22:11:41.855952 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:11:41.856019 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:11:41.856615 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:11:41.856950 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:11:41.857026 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:11:41.857116 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:11:41.857210 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:11:41.857569 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:11:41.899656 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:11:41.900437 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:11:41.900821 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:11:41.900896 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:11:41.900960 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:11:41.901211 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:11:41.901863 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1170 22:11:41.902038 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 22:11:41.902431 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:11:41.902554 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:11:41.928622 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:11:41.929332 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:11:41.929407 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:11:41.929517 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:11:41.929791 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:11:41.929860 0 9 8 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
1179 22:11:41.933210 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 22:11:41.933297 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 22:11:41.940007 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 22:11:41.942964 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 22:11:41.946645 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 22:11:41.952956 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 22:11:41.956428 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1186 22:11:41.959574 0 10 8 | B1->B0 | 2626 2727 | 0 0 | (1 0) (1 0)
1187 22:11:41.966659 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:11:41.969710 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:11:41.973087 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 22:11:41.976547 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 22:11:41.983686 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 22:11:41.987149 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:11:41.990980 0 11 4 | B1->B0 | 2a2a 2828 | 1 0 | (0 0) (0 0)
1194 22:11:41.995706 0 11 8 | B1->B0 | 4343 3c3c | 0 0 | (0 0) (1 1)
1195 22:11:41.998823 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 22:11:42.005298 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 22:11:42.009061 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 22:11:42.012832 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 22:11:42.015976 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 22:11:42.022838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 22:11:42.026015 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 22:11:42.029473 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 22:11:42.036187 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 22:11:42.039535 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:11:42.042764 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:11:42.049778 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:11:42.052924 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:11:42.056022 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:11:42.062803 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:11:42.066223 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:11:42.069752 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:11:42.076166 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:11:42.079820 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:11:42.083227 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:11:42.086268 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:11:42.093131 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:11:42.096655 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:11:42.100014 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 22:11:42.106367 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 22:11:42.109532 Total UI for P1: 0, mck2ui 16
1221 22:11:42.113504 best dqsien dly found for B0: ( 0, 14, 8)
1222 22:11:42.113624 Total UI for P1: 0, mck2ui 16
1223 22:11:42.120025 best dqsien dly found for B1: ( 0, 14, 8)
1224 22:11:42.122878 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1225 22:11:42.126628 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 22:11:42.126748
1227 22:11:42.129848 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 22:11:42.133061 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 22:11:42.136366 [Gating] SW calibration Done
1230 22:11:42.136488 ==
1231 22:11:42.139659 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 22:11:42.143342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 22:11:42.143464 ==
1234 22:11:42.146698 RX Vref Scan: 0
1235 22:11:42.146819
1236 22:11:42.146925 RX Vref 0 -> 0, step: 1
1237 22:11:42.147034
1238 22:11:42.149970 RX Delay -130 -> 252, step: 16
1239 22:11:42.153224 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1240 22:11:42.159935 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1241 22:11:42.163178 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1242 22:11:42.166797 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1243 22:11:42.169593 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1244 22:11:42.173382 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1245 22:11:42.179637 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1246 22:11:42.182895 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1247 22:11:42.186273 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1248 22:11:42.189661 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1249 22:11:42.193063 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1250 22:11:42.199676 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1251 22:11:42.203250 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1252 22:11:42.206256 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1253 22:11:42.209867 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1254 22:11:42.212980 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1255 22:11:42.216302 ==
1256 22:11:42.216385 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 22:11:42.223189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 22:11:42.223273 ==
1259 22:11:42.223338 DQS Delay:
1260 22:11:42.226312 DQS0 = 0, DQS1 = 0
1261 22:11:42.226394 DQM Delay:
1262 22:11:42.226480 DQM0 = 93, DQM1 = 83
1263 22:11:42.229876 DQ Delay:
1264 22:11:42.233221 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1265 22:11:42.236398 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1266 22:11:42.240207 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1267 22:11:42.243398 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1268 22:11:42.243506
1269 22:11:42.243624
1270 22:11:42.243704 ==
1271 22:11:42.246815 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 22:11:42.250145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 22:11:42.250228 ==
1274 22:11:42.250293
1275 22:11:42.250352
1276 22:11:42.253254 TX Vref Scan disable
1277 22:11:42.256589 == TX Byte 0 ==
1278 22:11:42.259865 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1279 22:11:42.263419 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1280 22:11:42.266681 == TX Byte 1 ==
1281 22:11:42.269933 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1282 22:11:42.273443 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1283 22:11:42.273526 ==
1284 22:11:42.276601 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 22:11:42.280004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 22:11:42.280087 ==
1287 22:11:42.294281 TX Vref=22, minBit 9, minWin=27, winSum=449
1288 22:11:42.297427 TX Vref=24, minBit 1, minWin=28, winSum=456
1289 22:11:42.300891 TX Vref=26, minBit 1, minWin=28, winSum=455
1290 22:11:42.304373 TX Vref=28, minBit 4, minWin=28, winSum=459
1291 22:11:42.307488 TX Vref=30, minBit 10, minWin=27, winSum=454
1292 22:11:42.314040 TX Vref=32, minBit 8, minWin=27, winSum=453
1293 22:11:42.317346 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 28
1294 22:11:42.317433
1295 22:11:42.321143 Final TX Range 1 Vref 28
1296 22:11:42.321226
1297 22:11:42.321292 ==
1298 22:11:42.324250 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 22:11:42.327509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 22:11:42.327643 ==
1301 22:11:42.327710
1302 22:11:42.330959
1303 22:11:42.331040 TX Vref Scan disable
1304 22:11:42.334162 == TX Byte 0 ==
1305 22:11:42.337614 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1306 22:11:42.340654 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1307 22:11:42.344431 == TX Byte 1 ==
1308 22:11:42.347397 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1309 22:11:42.351217 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1310 22:11:42.354480
1311 22:11:42.354561 [DATLAT]
1312 22:11:42.354637 Freq=800, CH0 RK1
1313 22:11:42.354711
1314 22:11:42.357668 DATLAT Default: 0xa
1315 22:11:42.357753 0, 0xFFFF, sum = 0
1316 22:11:42.360995 1, 0xFFFF, sum = 0
1317 22:11:42.361078 2, 0xFFFF, sum = 0
1318 22:11:42.364200 3, 0xFFFF, sum = 0
1319 22:11:42.364283 4, 0xFFFF, sum = 0
1320 22:11:42.367739 5, 0xFFFF, sum = 0
1321 22:11:42.367822 6, 0xFFFF, sum = 0
1322 22:11:42.371084 7, 0xFFFF, sum = 0
1323 22:11:42.374342 8, 0xFFFF, sum = 0
1324 22:11:42.374425 9, 0x0, sum = 1
1325 22:11:42.374523 10, 0x0, sum = 2
1326 22:11:42.377648 11, 0x0, sum = 3
1327 22:11:42.377732 12, 0x0, sum = 4
1328 22:11:42.380936 best_step = 10
1329 22:11:42.381017
1330 22:11:42.381082 ==
1331 22:11:42.384171 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 22:11:42.388005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 22:11:42.388127 ==
1334 22:11:42.390874 RX Vref Scan: 0
1335 22:11:42.390991
1336 22:11:42.391101 RX Vref 0 -> 0, step: 1
1337 22:11:42.391208
1338 22:11:42.394444 RX Delay -79 -> 252, step: 8
1339 22:11:42.401105 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1340 22:11:42.404624 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1341 22:11:42.407911 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1342 22:11:42.410957 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1343 22:11:42.414370 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1344 22:11:42.421427 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1345 22:11:42.424339 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1346 22:11:42.427806 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 22:11:42.431110 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1348 22:11:42.435357 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1349 22:11:42.437906 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1350 22:11:42.444605 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1351 22:11:42.447787 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1352 22:11:42.451432 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1353 22:11:42.454938 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1354 22:11:42.461481 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1355 22:11:42.461562 ==
1356 22:11:42.464638 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 22:11:42.467985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 22:11:42.468066 ==
1359 22:11:42.468130 DQS Delay:
1360 22:11:42.471436 DQS0 = 0, DQS1 = 0
1361 22:11:42.471517 DQM Delay:
1362 22:11:42.474897 DQM0 = 94, DQM1 = 83
1363 22:11:42.474977 DQ Delay:
1364 22:11:42.478103 DQ0 =92, DQ1 =92, DQ2 =92, DQ3 =92
1365 22:11:42.481509 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1366 22:11:42.484718 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1367 22:11:42.488252 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1368 22:11:42.488333
1369 22:11:42.488395
1370 22:11:42.494840 [DQSOSCAuto] RK1, (LSB)MR18= 0x4212, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1371 22:11:42.498133 CH0 RK1: MR19=606, MR18=4212
1372 22:11:42.504583 CH0_RK1: MR19=0x606, MR18=0x4212, DQSOSC=393, MR23=63, INC=95, DEC=63
1373 22:11:42.508133 [RxdqsGatingPostProcess] freq 800
1374 22:11:42.515060 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 22:11:42.515182 Pre-setting of DQS Precalculation
1376 22:11:42.521257 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 22:11:42.521378 ==
1378 22:11:42.524598 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 22:11:42.528268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 22:11:42.528391 ==
1381 22:11:42.535135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 22:11:42.541374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 22:11:42.549106 [CA 0] Center 36 (6~67) winsize 62
1384 22:11:42.552730 [CA 1] Center 36 (6~67) winsize 62
1385 22:11:42.555528 [CA 2] Center 35 (5~65) winsize 61
1386 22:11:42.558938 [CA 3] Center 34 (4~65) winsize 62
1387 22:11:42.562568 [CA 4] Center 35 (5~65) winsize 61
1388 22:11:42.566024 [CA 5] Center 34 (4~64) winsize 61
1389 22:11:42.566143
1390 22:11:42.569480 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 22:11:42.569599
1392 22:11:42.572803 [CATrainingPosCal] consider 1 rank data
1393 22:11:42.576125 u2DelayCellTimex100 = 270/100 ps
1394 22:11:42.579467 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 22:11:42.582662 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 22:11:42.589177 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1397 22:11:42.592375 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 22:11:42.595766 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1399 22:11:42.598969 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 22:11:42.599087
1401 22:11:42.602780 CA PerBit enable=1, Macro0, CA PI delay=34
1402 22:11:42.602903
1403 22:11:42.605953 [CBTSetCACLKResult] CA Dly = 34
1404 22:11:42.606072 CS Dly: 6 (0~37)
1405 22:11:42.606184 ==
1406 22:11:42.609547 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 22:11:42.615860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 22:11:42.615985 ==
1409 22:11:42.619324 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 22:11:42.625941 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 22:11:42.635705 [CA 0] Center 36 (6~67) winsize 62
1412 22:11:42.638986 [CA 1] Center 36 (6~67) winsize 62
1413 22:11:42.642077 [CA 2] Center 34 (4~65) winsize 62
1414 22:11:42.645391 [CA 3] Center 34 (4~65) winsize 62
1415 22:11:42.649213 [CA 4] Center 34 (4~65) winsize 62
1416 22:11:42.653183 [CA 5] Center 34 (4~65) winsize 62
1417 22:11:42.653305
1418 22:11:42.656739 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1419 22:11:42.656857
1420 22:11:42.660558 [CATrainingPosCal] consider 2 rank data
1421 22:11:42.664139 u2DelayCellTimex100 = 270/100 ps
1422 22:11:42.668162 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 22:11:42.671640 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 22:11:42.675627 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 22:11:42.679049 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 22:11:42.682937 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 22:11:42.686122 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 22:11:42.686247
1429 22:11:42.689355 CA PerBit enable=1, Macro0, CA PI delay=34
1430 22:11:42.689475
1431 22:11:42.692630 [CBTSetCACLKResult] CA Dly = 34
1432 22:11:42.692751 CS Dly: 6 (0~38)
1433 22:11:42.692864
1434 22:11:42.696283 ----->DramcWriteLeveling(PI) begin...
1435 22:11:42.696418 ==
1436 22:11:42.699805 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 22:11:42.702906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 22:11:42.706299 ==
1439 22:11:42.706419 Write leveling (Byte 0): 28 => 28
1440 22:11:42.709610 Write leveling (Byte 1): 27 => 27
1441 22:11:42.712633 DramcWriteLeveling(PI) end<-----
1442 22:11:42.712753
1443 22:11:42.712863 ==
1444 22:11:42.716446 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 22:11:42.722880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 22:11:42.723001 ==
1447 22:11:42.723115 [Gating] SW mode calibration
1448 22:11:42.733261 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 22:11:42.736446 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 22:11:42.739581 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 22:11:42.746324 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1452 22:11:42.749824 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1453 22:11:42.753121 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:11:42.759960 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 22:11:42.762889 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:11:42.766223 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:11:42.773190 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:11:42.776468 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:11:42.779813 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:11:42.786879 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:11:42.790157 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:11:42.793273 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:11:42.796508 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:11:42.803146 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:11:42.806368 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:11:42.810155 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:11:42.816590 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1468 22:11:42.819931 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:11:42.823159 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:11:42.830277 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:11:42.833341 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:11:42.836931 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:11:42.843305 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:11:42.846750 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:11:42.849862 0 9 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
1476 22:11:42.856705 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1477 22:11:42.860298 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 22:11:42.863588 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 22:11:42.870008 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 22:11:42.873537 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 22:11:42.876750 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:11:42.880510 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1483 22:11:42.886677 0 10 4 | B1->B0 | 3131 2d2d | 1 0 | (0 1) (1 0)
1484 22:11:42.890057 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1485 22:11:42.893442 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:11:42.900117 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:11:42.903417 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:11:42.906616 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:11:42.913695 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:11:42.917031 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1491 22:11:42.920261 0 11 4 | B1->B0 | 2727 3636 | 0 0 | (0 0) (1 1)
1492 22:11:42.927139 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1493 22:11:42.930322 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 22:11:42.933588 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 22:11:42.940200 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 22:11:42.943394 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 22:11:42.946979 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:11:42.953320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1499 22:11:42.956894 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 22:11:42.960250 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1501 22:11:42.966881 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:11:42.970625 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:11:42.973849 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:11:42.977004 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:11:42.983839 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:11:42.987201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:11:42.990302 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:11:42.997293 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:11:43.000287 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:11:43.003567 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:11:43.010297 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:11:43.013528 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:11:43.017152 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:11:43.023760 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1515 22:11:43.027399 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 22:11:43.030664 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 22:11:43.033970 Total UI for P1: 0, mck2ui 16
1518 22:11:43.037076 best dqsien dly found for B0: ( 0, 14, 4)
1519 22:11:43.040959 Total UI for P1: 0, mck2ui 16
1520 22:11:43.044198 best dqsien dly found for B1: ( 0, 14, 2)
1521 22:11:43.047252 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1522 22:11:43.050248 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1523 22:11:43.050329
1524 22:11:43.054121 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1525 22:11:43.057200 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1526 22:11:43.060451 [Gating] SW calibration Done
1527 22:11:43.060532 ==
1528 22:11:43.063932 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 22:11:43.070577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 22:11:43.070651 ==
1531 22:11:43.070712 RX Vref Scan: 0
1532 22:11:43.070834
1533 22:11:43.073732 RX Vref 0 -> 0, step: 1
1534 22:11:43.073801
1535 22:11:43.076948 RX Delay -130 -> 252, step: 16
1536 22:11:43.080580 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1537 22:11:43.083965 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 22:11:43.087544 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1539 22:11:43.090938 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 22:11:43.097168 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 22:11:43.100698 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1542 22:11:43.104011 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1543 22:11:43.107124 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 22:11:43.110760 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1545 22:11:43.117430 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1546 22:11:43.120419 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1547 22:11:43.123649 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1548 22:11:43.127356 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1549 22:11:43.130611 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1550 22:11:43.137090 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 22:11:43.140392 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1552 22:11:43.140497 ==
1553 22:11:43.144221 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 22:11:43.147392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 22:11:43.147469 ==
1556 22:11:43.150497 DQS Delay:
1557 22:11:43.150576 DQS0 = 0, DQS1 = 0
1558 22:11:43.150647 DQM Delay:
1559 22:11:43.154421 DQM0 = 93, DQM1 = 89
1560 22:11:43.154497 DQ Delay:
1561 22:11:43.157501 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1562 22:11:43.160687 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1563 22:11:43.164255 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1564 22:11:43.167224 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1565 22:11:43.167298
1566 22:11:43.167368
1567 22:11:43.167431 ==
1568 22:11:43.170511 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 22:11:43.177379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 22:11:43.177504 ==
1571 22:11:43.177611
1572 22:11:43.177721
1573 22:11:43.177827 TX Vref Scan disable
1574 22:11:43.181087 == TX Byte 0 ==
1575 22:11:43.184042 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1576 22:11:43.190914 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1577 22:11:43.191036 == TX Byte 1 ==
1578 22:11:43.194241 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1579 22:11:43.197411 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1580 22:11:43.200759 ==
1581 22:11:43.204610 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 22:11:43.207580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 22:11:43.207723 ==
1584 22:11:43.220049 TX Vref=22, minBit 1, minWin=26, winSum=439
1585 22:11:43.223467 TX Vref=24, minBit 1, minWin=27, winSum=445
1586 22:11:43.227006 TX Vref=26, minBit 1, minWin=27, winSum=442
1587 22:11:43.230693 TX Vref=28, minBit 1, minWin=27, winSum=449
1588 22:11:43.234236 TX Vref=30, minBit 1, minWin=27, winSum=450
1589 22:11:43.237448 TX Vref=32, minBit 1, minWin=27, winSum=447
1590 22:11:43.244459 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
1591 22:11:43.244576
1592 22:11:43.247713 Final TX Range 1 Vref 30
1593 22:11:43.247831
1594 22:11:43.247942 ==
1595 22:11:43.250843 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 22:11:43.254182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 22:11:43.254303 ==
1598 22:11:43.254411
1599 22:11:43.254519
1600 22:11:43.257716 TX Vref Scan disable
1601 22:11:43.260902 == TX Byte 0 ==
1602 22:11:43.264379 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1603 22:11:43.267584 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1604 22:11:43.270849 == TX Byte 1 ==
1605 22:11:43.274408 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1606 22:11:43.277654 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1607 22:11:43.277775
1608 22:11:43.277884 [DATLAT]
1609 22:11:43.280906 Freq=800, CH1 RK0
1610 22:11:43.281022
1611 22:11:43.284291 DATLAT Default: 0xa
1612 22:11:43.284406 0, 0xFFFF, sum = 0
1613 22:11:43.287702 1, 0xFFFF, sum = 0
1614 22:11:43.287824 2, 0xFFFF, sum = 0
1615 22:11:43.290889 3, 0xFFFF, sum = 0
1616 22:11:43.291007 4, 0xFFFF, sum = 0
1617 22:11:43.294041 5, 0xFFFF, sum = 0
1618 22:11:43.294162 6, 0xFFFF, sum = 0
1619 22:11:43.297411 7, 0xFFFF, sum = 0
1620 22:11:43.297533 8, 0xFFFF, sum = 0
1621 22:11:43.301256 9, 0x0, sum = 1
1622 22:11:43.301378 10, 0x0, sum = 2
1623 22:11:43.304361 11, 0x0, sum = 3
1624 22:11:43.304486 12, 0x0, sum = 4
1625 22:11:43.304596 best_step = 10
1626 22:11:43.307244
1627 22:11:43.307364 ==
1628 22:11:43.311155 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 22:11:43.314143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 22:11:43.314264 ==
1631 22:11:43.314392 RX Vref Scan: 1
1632 22:11:43.314541
1633 22:11:43.317326 Set Vref Range= 32 -> 127
1634 22:11:43.317444
1635 22:11:43.320910 RX Vref 32 -> 127, step: 1
1636 22:11:43.321028
1637 22:11:43.324087 RX Delay -79 -> 252, step: 8
1638 22:11:43.324206
1639 22:11:43.327771 Set Vref, RX VrefLevel [Byte0]: 32
1640 22:11:43.330758 [Byte1]: 32
1641 22:11:43.330878
1642 22:11:43.334331 Set Vref, RX VrefLevel [Byte0]: 33
1643 22:11:43.337893 [Byte1]: 33
1644 22:11:43.338012
1645 22:11:43.340981 Set Vref, RX VrefLevel [Byte0]: 34
1646 22:11:43.344029 [Byte1]: 34
1647 22:11:43.347382
1648 22:11:43.347501 Set Vref, RX VrefLevel [Byte0]: 35
1649 22:11:43.351091 [Byte1]: 35
1650 22:11:43.354956
1651 22:11:43.355075 Set Vref, RX VrefLevel [Byte0]: 36
1652 22:11:43.358289 [Byte1]: 36
1653 22:11:43.362917
1654 22:11:43.363036 Set Vref, RX VrefLevel [Byte0]: 37
1655 22:11:43.366060 [Byte1]: 37
1656 22:11:43.370102
1657 22:11:43.370221 Set Vref, RX VrefLevel [Byte0]: 38
1658 22:11:43.373627 [Byte1]: 38
1659 22:11:43.378040
1660 22:11:43.378157 Set Vref, RX VrefLevel [Byte0]: 39
1661 22:11:43.381305 [Byte1]: 39
1662 22:11:43.385383
1663 22:11:43.385504 Set Vref, RX VrefLevel [Byte0]: 40
1664 22:11:43.388456 [Byte1]: 40
1665 22:11:43.392768
1666 22:11:43.392904 Set Vref, RX VrefLevel [Byte0]: 41
1667 22:11:43.395966 [Byte1]: 41
1668 22:11:43.400531
1669 22:11:43.400651 Set Vref, RX VrefLevel [Byte0]: 42
1670 22:11:43.403779 [Byte1]: 42
1671 22:11:43.408042
1672 22:11:43.408162 Set Vref, RX VrefLevel [Byte0]: 43
1673 22:11:43.411206 [Byte1]: 43
1674 22:11:43.415485
1675 22:11:43.415629 Set Vref, RX VrefLevel [Byte0]: 44
1676 22:11:43.418767 [Byte1]: 44
1677 22:11:43.423264
1678 22:11:43.423383 Set Vref, RX VrefLevel [Byte0]: 45
1679 22:11:43.426404 [Byte1]: 45
1680 22:11:43.430673
1681 22:11:43.430789 Set Vref, RX VrefLevel [Byte0]: 46
1682 22:11:43.434051 [Byte1]: 46
1683 22:11:43.438272
1684 22:11:43.438392 Set Vref, RX VrefLevel [Byte0]: 47
1685 22:11:43.441215 [Byte1]: 47
1686 22:11:43.445816
1687 22:11:43.445934 Set Vref, RX VrefLevel [Byte0]: 48
1688 22:11:43.449086 [Byte1]: 48
1689 22:11:43.453424
1690 22:11:43.453542 Set Vref, RX VrefLevel [Byte0]: 49
1691 22:11:43.456359 [Byte1]: 49
1692 22:11:43.460853
1693 22:11:43.460974 Set Vref, RX VrefLevel [Byte0]: 50
1694 22:11:43.464312 [Byte1]: 50
1695 22:11:43.468528
1696 22:11:43.468650 Set Vref, RX VrefLevel [Byte0]: 51
1697 22:11:43.471532 [Byte1]: 51
1698 22:11:43.476139
1699 22:11:43.476221 Set Vref, RX VrefLevel [Byte0]: 52
1700 22:11:43.482179 [Byte1]: 52
1701 22:11:43.482329
1702 22:11:43.485545 Set Vref, RX VrefLevel [Byte0]: 53
1703 22:11:43.489337 [Byte1]: 53
1704 22:11:43.489436
1705 22:11:43.492696 Set Vref, RX VrefLevel [Byte0]: 54
1706 22:11:43.495688 [Byte1]: 54
1707 22:11:43.495779
1708 22:11:43.498867 Set Vref, RX VrefLevel [Byte0]: 55
1709 22:11:43.502067 [Byte1]: 55
1710 22:11:43.506163
1711 22:11:43.506309 Set Vref, RX VrefLevel [Byte0]: 56
1712 22:11:43.509344 [Byte1]: 56
1713 22:11:43.513392
1714 22:11:43.513490 Set Vref, RX VrefLevel [Byte0]: 57
1715 22:11:43.517022 [Byte1]: 57
1716 22:11:43.521314
1717 22:11:43.521416 Set Vref, RX VrefLevel [Byte0]: 58
1718 22:11:43.524842 [Byte1]: 58
1719 22:11:43.528536
1720 22:11:43.528611 Set Vref, RX VrefLevel [Byte0]: 59
1721 22:11:43.531803 [Byte1]: 59
1722 22:11:43.536088
1723 22:11:43.536159 Set Vref, RX VrefLevel [Byte0]: 60
1724 22:11:43.539781 [Byte1]: 60
1725 22:11:43.543823
1726 22:11:43.543919 Set Vref, RX VrefLevel [Byte0]: 61
1727 22:11:43.547034 [Byte1]: 61
1728 22:11:43.551356
1729 22:11:43.551452 Set Vref, RX VrefLevel [Byte0]: 62
1730 22:11:43.554909 [Byte1]: 62
1731 22:11:43.558700
1732 22:11:43.558803 Set Vref, RX VrefLevel [Byte0]: 63
1733 22:11:43.562453 [Byte1]: 63
1734 22:11:43.566253
1735 22:11:43.566358 Set Vref, RX VrefLevel [Byte0]: 64
1736 22:11:43.569981 [Byte1]: 64
1737 22:11:43.573741
1738 22:11:43.573849 Set Vref, RX VrefLevel [Byte0]: 65
1739 22:11:43.577465 [Byte1]: 65
1740 22:11:43.581565
1741 22:11:43.581689 Set Vref, RX VrefLevel [Byte0]: 66
1742 22:11:43.584813 [Byte1]: 66
1743 22:11:43.588820
1744 22:11:43.588942 Set Vref, RX VrefLevel [Byte0]: 67
1745 22:11:43.592576 [Byte1]: 67
1746 22:11:43.596826
1747 22:11:43.596903 Set Vref, RX VrefLevel [Byte0]: 68
1748 22:11:43.599918 [Byte1]: 68
1749 22:11:43.604091
1750 22:11:43.604176 Set Vref, RX VrefLevel [Byte0]: 69
1751 22:11:43.607172 [Byte1]: 69
1752 22:11:43.611569
1753 22:11:43.611657 Set Vref, RX VrefLevel [Byte0]: 70
1754 22:11:43.614908 [Byte1]: 70
1755 22:11:43.619314
1756 22:11:43.619394 Set Vref, RX VrefLevel [Byte0]: 71
1757 22:11:43.622694 [Byte1]: 71
1758 22:11:43.626906
1759 22:11:43.627009 Set Vref, RX VrefLevel [Byte0]: 72
1760 22:11:43.630177 [Byte1]: 72
1761 22:11:43.634260
1762 22:11:43.634361 Final RX Vref Byte 0 = 58 to rank0
1763 22:11:43.637647 Final RX Vref Byte 1 = 56 to rank0
1764 22:11:43.641246 Final RX Vref Byte 0 = 58 to rank1
1765 22:11:43.644594 Final RX Vref Byte 1 = 56 to rank1==
1766 22:11:43.648158 Dram Type= 6, Freq= 0, CH_1, rank 0
1767 22:11:43.651346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1768 22:11:43.654460 ==
1769 22:11:43.654541 DQS Delay:
1770 22:11:43.654608 DQS0 = 0, DQS1 = 0
1771 22:11:43.658144 DQM Delay:
1772 22:11:43.658233 DQM0 = 94, DQM1 = 89
1773 22:11:43.661206 DQ Delay:
1774 22:11:43.661282 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1775 22:11:43.664472 DQ4 =92, DQ5 =108, DQ6 =104, DQ7 =92
1776 22:11:43.667864 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1777 22:11:43.671093 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1778 22:11:43.674439
1779 22:11:43.674545
1780 22:11:43.681555 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1781 22:11:43.684662 CH1 RK0: MR19=606, MR18=2D49
1782 22:11:43.691454 CH1_RK0: MR19=0x606, MR18=0x2D49, DQSOSC=391, MR23=63, INC=96, DEC=64
1783 22:11:43.691565
1784 22:11:43.694825 ----->DramcWriteLeveling(PI) begin...
1785 22:11:43.694899 ==
1786 22:11:43.698151 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 22:11:43.701367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 22:11:43.701456 ==
1789 22:11:43.705005 Write leveling (Byte 0): 26 => 26
1790 22:11:43.708226 Write leveling (Byte 1): 31 => 31
1791 22:11:43.711341 DramcWriteLeveling(PI) end<-----
1792 22:11:43.711440
1793 22:11:43.711530 ==
1794 22:11:43.714934 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 22:11:43.718184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 22:11:43.718261 ==
1797 22:11:43.721389 [Gating] SW mode calibration
1798 22:11:43.728009 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1799 22:11:43.734688 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1800 22:11:43.737913 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1801 22:11:43.741471 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1802 22:11:43.748431 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 22:11:43.751981 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 22:11:43.754716 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 22:11:43.758075 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 22:11:43.765194 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 22:11:43.768346 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 22:11:43.771764 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 22:11:43.778023 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 22:11:43.781782 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 22:11:43.784949 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 22:11:43.791535 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 22:11:43.795006 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 22:11:43.798168 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 22:11:43.804663 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1816 22:11:43.808047 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1817 22:11:43.811436 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:11:43.818630 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:11:43.822076 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:11:43.825069 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:11:43.831803 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:11:43.834845 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:11:43.838197 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:11:43.844943 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:11:43.847937 0 9 4 | B1->B0 | 2b2b 2323 | 1 1 | (1 1) (1 1)
1826 22:11:43.851472 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1827 22:11:43.854979 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 22:11:43.861842 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 22:11:43.865112 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 22:11:43.868217 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 22:11:43.874866 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 22:11:43.878345 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1833 22:11:43.881387 0 10 4 | B1->B0 | 2828 2f2f | 0 0 | (1 0) (0 0)
1834 22:11:43.888068 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:11:43.891827 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:11:43.895050 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:11:43.901959 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:11:43.905108 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:11:43.908511 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:11:43.914632 0 11 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1841 22:11:43.918328 0 11 4 | B1->B0 | 3a3a 3030 | 0 0 | (0 0) (0 0)
1842 22:11:43.921897 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 22:11:43.928320 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 22:11:43.931602 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 22:11:43.934841 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 22:11:43.938417 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 22:11:43.945299 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 22:11:43.948334 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 22:11:43.951450 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1850 22:11:43.958150 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 22:11:43.961492 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 22:11:43.965056 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 22:11:43.971753 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 22:11:43.975249 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 22:11:43.978323 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 22:11:43.985028 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 22:11:43.988606 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 22:11:43.991821 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 22:11:43.998669 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 22:11:44.001906 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 22:11:44.005295 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 22:11:44.011655 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 22:11:44.014870 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:11:44.018461 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 22:11:44.021742 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 22:11:44.025142 Total UI for P1: 0, mck2ui 16
1867 22:11:44.028559 best dqsien dly found for B0: ( 0, 14, 2)
1868 22:11:44.031935 Total UI for P1: 0, mck2ui 16
1869 22:11:44.035422 best dqsien dly found for B1: ( 0, 14, 2)
1870 22:11:44.038498 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1871 22:11:44.041843 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1872 22:11:44.044948
1873 22:11:44.048708 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1874 22:11:44.051868 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1875 22:11:44.051940 [Gating] SW calibration Done
1876 22:11:44.055048 ==
1877 22:11:44.058406 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 22:11:44.061775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 22:11:44.061863 ==
1880 22:11:44.061928 RX Vref Scan: 0
1881 22:11:44.061988
1882 22:11:44.065140 RX Vref 0 -> 0, step: 1
1883 22:11:44.065211
1884 22:11:44.068697 RX Delay -130 -> 252, step: 16
1885 22:11:44.072055 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1886 22:11:44.075399 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1887 22:11:44.078947 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1888 22:11:44.085633 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1889 22:11:44.089105 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1890 22:11:44.092313 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1891 22:11:44.095364 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1892 22:11:44.098790 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1893 22:11:44.105415 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1894 22:11:44.108649 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1895 22:11:44.111877 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1896 22:11:44.115420 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1897 22:11:44.118817 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1898 22:11:44.125196 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1899 22:11:44.128442 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1900 22:11:44.131970 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1901 22:11:44.132048 ==
1902 22:11:44.135527 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 22:11:44.138862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 22:11:44.138973 ==
1905 22:11:44.142372 DQS Delay:
1906 22:11:44.142463 DQS0 = 0, DQS1 = 0
1907 22:11:44.145483 DQM Delay:
1908 22:11:44.145558 DQM0 = 94, DQM1 = 93
1909 22:11:44.145620 DQ Delay:
1910 22:11:44.148934 DQ0 =101, DQ1 =93, DQ2 =85, DQ3 =85
1911 22:11:44.151984 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1912 22:11:44.155695 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1913 22:11:44.158738 DQ12 =101, DQ13 =101, DQ14 =93, DQ15 =101
1914 22:11:44.161980
1915 22:11:44.162054
1916 22:11:44.162117 ==
1917 22:11:44.165643 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 22:11:44.168856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 22:11:44.168934 ==
1920 22:11:44.168997
1921 22:11:44.169056
1922 22:11:44.172120 TX Vref Scan disable
1923 22:11:44.172192 == TX Byte 0 ==
1924 22:11:44.178850 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1925 22:11:44.182341 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1926 22:11:44.182424 == TX Byte 1 ==
1927 22:11:44.189124 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1928 22:11:44.192449 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1929 22:11:44.192526 ==
1930 22:11:44.195541 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 22:11:44.198910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 22:11:44.198983 ==
1933 22:11:44.213095 TX Vref=22, minBit 0, minWin=27, winSum=440
1934 22:11:44.216342 TX Vref=24, minBit 1, minWin=26, winSum=441
1935 22:11:44.219393 TX Vref=26, minBit 5, minWin=26, winSum=445
1936 22:11:44.222780 TX Vref=28, minBit 2, minWin=27, winSum=451
1937 22:11:44.226194 TX Vref=30, minBit 2, minWin=27, winSum=450
1938 22:11:44.229529 TX Vref=32, minBit 0, minWin=27, winSum=447
1939 22:11:44.235940 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
1940 22:11:44.236020
1941 22:11:44.239485 Final TX Range 1 Vref 28
1942 22:11:44.239589
1943 22:11:44.239664 ==
1944 22:11:44.242948 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 22:11:44.246214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 22:11:44.246293 ==
1947 22:11:44.246359
1948 22:11:44.249257
1949 22:11:44.249360 TX Vref Scan disable
1950 22:11:44.252776 == TX Byte 0 ==
1951 22:11:44.256328 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1952 22:11:44.259392 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1953 22:11:44.262626 == TX Byte 1 ==
1954 22:11:44.266196 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1955 22:11:44.269560 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1956 22:11:44.272757
1957 22:11:44.272834 [DATLAT]
1958 22:11:44.272897 Freq=800, CH1 RK1
1959 22:11:44.272956
1960 22:11:44.276367 DATLAT Default: 0xa
1961 22:11:44.276441 0, 0xFFFF, sum = 0
1962 22:11:44.279377 1, 0xFFFF, sum = 0
1963 22:11:44.279491 2, 0xFFFF, sum = 0
1964 22:11:44.282799 3, 0xFFFF, sum = 0
1965 22:11:44.282903 4, 0xFFFF, sum = 0
1966 22:11:44.286325 5, 0xFFFF, sum = 0
1967 22:11:44.286426 6, 0xFFFF, sum = 0
1968 22:11:44.289824 7, 0xFFFF, sum = 0
1969 22:11:44.289897 8, 0xFFFF, sum = 0
1970 22:11:44.293101 9, 0x0, sum = 1
1971 22:11:44.293177 10, 0x0, sum = 2
1972 22:11:44.296158 11, 0x0, sum = 3
1973 22:11:44.296232 12, 0x0, sum = 4
1974 22:11:44.299495 best_step = 10
1975 22:11:44.299589
1976 22:11:44.299663 ==
1977 22:11:44.303180 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 22:11:44.306316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 22:11:44.306411 ==
1980 22:11:44.309661 RX Vref Scan: 0
1981 22:11:44.309757
1982 22:11:44.309847 RX Vref 0 -> 0, step: 1
1983 22:11:44.309934
1984 22:11:44.313198 RX Delay -63 -> 252, step: 8
1985 22:11:44.319589 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
1986 22:11:44.322810 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1987 22:11:44.327023 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1988 22:11:44.329658 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1989 22:11:44.333340 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1990 22:11:44.336578 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1991 22:11:44.339825 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1992 22:11:44.346411 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1993 22:11:44.349933 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1994 22:11:44.353079 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1995 22:11:44.356974 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
1996 22:11:44.360006 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1997 22:11:44.366843 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1998 22:11:44.369913 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1999 22:11:44.373078 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2000 22:11:44.376431 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2001 22:11:44.376529 ==
2002 22:11:44.380074 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 22:11:44.386800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 22:11:44.386903 ==
2005 22:11:44.386989 DQS Delay:
2006 22:11:44.387050 DQS0 = 0, DQS1 = 0
2007 22:11:44.390060 DQM Delay:
2008 22:11:44.390160 DQM0 = 96, DQM1 = 91
2009 22:11:44.393486 DQ Delay:
2010 22:11:44.396600 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2011 22:11:44.400443 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2012 22:11:44.403537 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2013 22:11:44.406675 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2014 22:11:44.406753
2015 22:11:44.406823
2016 22:11:44.413455 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
2017 22:11:44.416816 CH1 RK1: MR19=606, MR18=4A14
2018 22:11:44.424013 CH1_RK1: MR19=0x606, MR18=0x4A14, DQSOSC=391, MR23=63, INC=96, DEC=64
2019 22:11:44.427150 [RxdqsGatingPostProcess] freq 800
2020 22:11:44.430350 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2021 22:11:44.433650 Pre-setting of DQS Precalculation
2022 22:11:44.440155 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2023 22:11:44.447168 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2024 22:11:44.454001 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2025 22:11:44.454092
2026 22:11:44.454157
2027 22:11:44.457104 [Calibration Summary] 1600 Mbps
2028 22:11:44.457181 CH 0, Rank 0
2029 22:11:44.460283 SW Impedance : PASS
2030 22:11:44.463696 DUTY Scan : NO K
2031 22:11:44.463771 ZQ Calibration : PASS
2032 22:11:44.467029 Jitter Meter : NO K
2033 22:11:44.467104 CBT Training : PASS
2034 22:11:44.470785 Write leveling : PASS
2035 22:11:44.473742 RX DQS gating : PASS
2036 22:11:44.473818 RX DQ/DQS(RDDQC) : PASS
2037 22:11:44.477739 TX DQ/DQS : PASS
2038 22:11:44.480832 RX DATLAT : PASS
2039 22:11:44.480937 RX DQ/DQS(Engine): PASS
2040 22:11:44.484228 TX OE : NO K
2041 22:11:44.484305 All Pass.
2042 22:11:44.484368
2043 22:11:44.487318 CH 0, Rank 1
2044 22:11:44.487394 SW Impedance : PASS
2045 22:11:44.491107 DUTY Scan : NO K
2046 22:11:44.494060 ZQ Calibration : PASS
2047 22:11:44.494160 Jitter Meter : NO K
2048 22:11:44.497167 CBT Training : PASS
2049 22:11:44.497241 Write leveling : PASS
2050 22:11:44.500887 RX DQS gating : PASS
2051 22:11:44.504190 RX DQ/DQS(RDDQC) : PASS
2052 22:11:44.504267 TX DQ/DQS : PASS
2053 22:11:44.507685 RX DATLAT : PASS
2054 22:11:44.510610 RX DQ/DQS(Engine): PASS
2055 22:11:44.510695 TX OE : NO K
2056 22:11:44.513916 All Pass.
2057 22:11:44.514015
2058 22:11:44.514105 CH 1, Rank 0
2059 22:11:44.517454 SW Impedance : PASS
2060 22:11:44.517553 DUTY Scan : NO K
2061 22:11:44.520646 ZQ Calibration : PASS
2062 22:11:44.523976 Jitter Meter : NO K
2063 22:11:44.524050 CBT Training : PASS
2064 22:11:44.527876 Write leveling : PASS
2065 22:11:44.530757 RX DQS gating : PASS
2066 22:11:44.530854 RX DQ/DQS(RDDQC) : PASS
2067 22:11:44.534435 TX DQ/DQS : PASS
2068 22:11:44.534538 RX DATLAT : PASS
2069 22:11:44.537616 RX DQ/DQS(Engine): PASS
2070 22:11:44.540810 TX OE : NO K
2071 22:11:44.540884 All Pass.
2072 22:11:44.540947
2073 22:11:44.541005 CH 1, Rank 1
2074 22:11:44.544179 SW Impedance : PASS
2075 22:11:44.547573 DUTY Scan : NO K
2076 22:11:44.547681 ZQ Calibration : PASS
2077 22:11:44.551267 Jitter Meter : NO K
2078 22:11:44.554351 CBT Training : PASS
2079 22:11:44.554431 Write leveling : PASS
2080 22:11:44.557576 RX DQS gating : PASS
2081 22:11:44.561016 RX DQ/DQS(RDDQC) : PASS
2082 22:11:44.561091 TX DQ/DQS : PASS
2083 22:11:44.564289 RX DATLAT : PASS
2084 22:11:44.567552 RX DQ/DQS(Engine): PASS
2085 22:11:44.567647 TX OE : NO K
2086 22:11:44.567711 All Pass.
2087 22:11:44.571389
2088 22:11:44.571464 DramC Write-DBI off
2089 22:11:44.574287 PER_BANK_REFRESH: Hybrid Mode
2090 22:11:44.574362 TX_TRACKING: ON
2091 22:11:44.577977 [GetDramInforAfterCalByMRR] Vendor 6.
2092 22:11:44.580907 [GetDramInforAfterCalByMRR] Revision 606.
2093 22:11:44.588141 [GetDramInforAfterCalByMRR] Revision 2 0.
2094 22:11:44.588220 MR0 0x3b3b
2095 22:11:44.588297 MR8 0x5151
2096 22:11:44.590868 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2097 22:11:44.590965
2098 22:11:44.594614 MR0 0x3b3b
2099 22:11:44.594698 MR8 0x5151
2100 22:11:44.598007 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 22:11:44.598081
2102 22:11:44.607807 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2103 22:11:44.611087 [FAST_K] Save calibration result to emmc
2104 22:11:44.614518 [FAST_K] Save calibration result to emmc
2105 22:11:44.617558 dram_init: config_dvfs: 1
2106 22:11:44.621257 dramc_set_vcore_voltage set vcore to 662500
2107 22:11:44.621347 Read voltage for 1200, 2
2108 22:11:44.624445 Vio18 = 0
2109 22:11:44.624519 Vcore = 662500
2110 22:11:44.624600 Vdram = 0
2111 22:11:44.628175 Vddq = 0
2112 22:11:44.628248 Vmddr = 0
2113 22:11:44.631349 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2114 22:11:44.637757 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2115 22:11:44.640954 MEM_TYPE=3, freq_sel=15
2116 22:11:44.644579 sv_algorithm_assistance_LP4_1600
2117 22:11:44.647828 ============ PULL DRAM RESETB DOWN ============
2118 22:11:44.651110 ========== PULL DRAM RESETB DOWN end =========
2119 22:11:44.657955 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2120 22:11:44.661084 ===================================
2121 22:11:44.661158 LPDDR4 DRAM CONFIGURATION
2122 22:11:44.664418 ===================================
2123 22:11:44.667676 EX_ROW_EN[0] = 0x0
2124 22:11:44.667750 EX_ROW_EN[1] = 0x0
2125 22:11:44.671382 LP4Y_EN = 0x0
2126 22:11:44.671454 WORK_FSP = 0x0
2127 22:11:44.674606 WL = 0x4
2128 22:11:44.674688 RL = 0x4
2129 22:11:44.677951 BL = 0x2
2130 22:11:44.678048 RPST = 0x0
2131 22:11:44.681260 RD_PRE = 0x0
2132 22:11:44.681359 WR_PRE = 0x1
2133 22:11:44.684669 WR_PST = 0x0
2134 22:11:44.687969 DBI_WR = 0x0
2135 22:11:44.688045 DBI_RD = 0x0
2136 22:11:44.690989 OTF = 0x1
2137 22:11:44.694878 ===================================
2138 22:11:44.698135 ===================================
2139 22:11:44.698238 ANA top config
2140 22:11:44.701296 ===================================
2141 22:11:44.704662 DLL_ASYNC_EN = 0
2142 22:11:44.704735 ALL_SLAVE_EN = 0
2143 22:11:44.708094 NEW_RANK_MODE = 1
2144 22:11:44.711216 DLL_IDLE_MODE = 1
2145 22:11:44.714626 LP45_APHY_COMB_EN = 1
2146 22:11:44.717673 TX_ODT_DIS = 1
2147 22:11:44.717773 NEW_8X_MODE = 1
2148 22:11:44.721320 ===================================
2149 22:11:44.724520 ===================================
2150 22:11:44.728082 data_rate = 2400
2151 22:11:44.731234 CKR = 1
2152 22:11:44.735197 DQ_P2S_RATIO = 8
2153 22:11:44.738377 ===================================
2154 22:11:44.741696 CA_P2S_RATIO = 8
2155 22:11:44.741767 DQ_CA_OPEN = 0
2156 22:11:44.744872 DQ_SEMI_OPEN = 0
2157 22:11:44.748242 CA_SEMI_OPEN = 0
2158 22:11:44.751425 CA_FULL_RATE = 0
2159 22:11:44.754855 DQ_CKDIV4_EN = 0
2160 22:11:44.758405 CA_CKDIV4_EN = 0
2161 22:11:44.758516 CA_PREDIV_EN = 0
2162 22:11:44.762143 PH8_DLY = 17
2163 22:11:44.765228 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2164 22:11:44.768275 DQ_AAMCK_DIV = 4
2165 22:11:44.771443 CA_AAMCK_DIV = 4
2166 22:11:44.775186 CA_ADMCK_DIV = 4
2167 22:11:44.775268 DQ_TRACK_CA_EN = 0
2168 22:11:44.778373 CA_PICK = 1200
2169 22:11:44.781626 CA_MCKIO = 1200
2170 22:11:44.785334 MCKIO_SEMI = 0
2171 22:11:44.788703 PLL_FREQ = 2366
2172 22:11:44.791625 DQ_UI_PI_RATIO = 32
2173 22:11:44.794998 CA_UI_PI_RATIO = 0
2174 22:11:44.795080 ===================================
2175 22:11:44.798821 ===================================
2176 22:11:44.801599 memory_type:LPDDR4
2177 22:11:44.804852 GP_NUM : 10
2178 22:11:44.804963 SRAM_EN : 1
2179 22:11:44.808560 MD32_EN : 0
2180 22:11:44.811996 ===================================
2181 22:11:44.814998 [ANA_INIT] >>>>>>>>>>>>>>
2182 22:11:44.818618 <<<<<< [CONFIGURE PHASE]: ANA_TX
2183 22:11:44.822132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2184 22:11:44.825223 ===================================
2185 22:11:44.825331 data_rate = 2400,PCW = 0X5b00
2186 22:11:44.828320 ===================================
2187 22:11:44.831850 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2188 22:11:44.838813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2189 22:11:44.845276 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 22:11:44.848564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2191 22:11:44.852030 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2192 22:11:44.855482 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2193 22:11:44.858885 [ANA_INIT] flow start
2194 22:11:44.858960 [ANA_INIT] PLL >>>>>>>>
2195 22:11:44.861896 [ANA_INIT] PLL <<<<<<<<
2196 22:11:44.865400 [ANA_INIT] MIDPI >>>>>>>>
2197 22:11:44.868440 [ANA_INIT] MIDPI <<<<<<<<
2198 22:11:44.868512 [ANA_INIT] DLL >>>>>>>>
2199 22:11:44.871920 [ANA_INIT] DLL <<<<<<<<
2200 22:11:44.871996 [ANA_INIT] flow end
2201 22:11:44.878757 ============ LP4 DIFF to SE enter ============
2202 22:11:44.881915 ============ LP4 DIFF to SE exit ============
2203 22:11:44.885193 [ANA_INIT] <<<<<<<<<<<<<
2204 22:11:44.888940 [Flow] Enable top DCM control >>>>>
2205 22:11:44.891875 [Flow] Enable top DCM control <<<<<
2206 22:11:44.891974 Enable DLL master slave shuffle
2207 22:11:44.898493 ==============================================================
2208 22:11:44.902002 Gating Mode config
2209 22:11:44.905500 ==============================================================
2210 22:11:44.908851 Config description:
2211 22:11:44.918845 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2212 22:11:44.925505 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2213 22:11:44.928927 SELPH_MODE 0: By rank 1: By Phase
2214 22:11:44.935470 ==============================================================
2215 22:11:44.938637 GAT_TRACK_EN = 1
2216 22:11:44.941973 RX_GATING_MODE = 2
2217 22:11:44.945193 RX_GATING_TRACK_MODE = 2
2218 22:11:44.945269 SELPH_MODE = 1
2219 22:11:44.948929 PICG_EARLY_EN = 1
2220 22:11:44.952209 VALID_LAT_VALUE = 1
2221 22:11:44.958830 ==============================================================
2222 22:11:44.962287 Enter into Gating configuration >>>>
2223 22:11:44.965856 Exit from Gating configuration <<<<
2224 22:11:44.968842 Enter into DVFS_PRE_config >>>>>
2225 22:11:44.978818 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2226 22:11:44.982129 Exit from DVFS_PRE_config <<<<<
2227 22:11:44.985756 Enter into PICG configuration >>>>
2228 22:11:44.989335 Exit from PICG configuration <<<<
2229 22:11:44.992595 [RX_INPUT] configuration >>>>>
2230 22:11:44.995269 [RX_INPUT] configuration <<<<<
2231 22:11:44.998686 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2232 22:11:45.005474 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2233 22:11:45.012052 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 22:11:45.019031 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 22:11:45.022094 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2236 22:11:45.029023 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2237 22:11:45.032245 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2238 22:11:45.038918 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2239 22:11:45.042028 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2240 22:11:45.045615 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2241 22:11:45.049212 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2242 22:11:45.055746 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2243 22:11:45.058940 ===================================
2244 22:11:45.059045 LPDDR4 DRAM CONFIGURATION
2245 22:11:45.062173 ===================================
2246 22:11:45.065866 EX_ROW_EN[0] = 0x0
2247 22:11:45.068855 EX_ROW_EN[1] = 0x0
2248 22:11:45.068956 LP4Y_EN = 0x0
2249 22:11:45.072500 WORK_FSP = 0x0
2250 22:11:45.072573 WL = 0x4
2251 22:11:45.075352 RL = 0x4
2252 22:11:45.075454 BL = 0x2
2253 22:11:45.079096 RPST = 0x0
2254 22:11:45.079201 RD_PRE = 0x0
2255 22:11:45.082398 WR_PRE = 0x1
2256 22:11:45.082503 WR_PST = 0x0
2257 22:11:45.085440 DBI_WR = 0x0
2258 22:11:45.085543 DBI_RD = 0x0
2259 22:11:45.088914 OTF = 0x1
2260 22:11:45.092345 ===================================
2261 22:11:45.095815 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2262 22:11:45.099096 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2263 22:11:45.105388 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 22:11:45.108999 ===================================
2265 22:11:45.109105 LPDDR4 DRAM CONFIGURATION
2266 22:11:45.112314 ===================================
2267 22:11:45.115821 EX_ROW_EN[0] = 0x10
2268 22:11:45.115923 EX_ROW_EN[1] = 0x0
2269 22:11:45.118881 LP4Y_EN = 0x0
2270 22:11:45.118983 WORK_FSP = 0x0
2271 22:11:45.122265 WL = 0x4
2272 22:11:45.122366 RL = 0x4
2273 22:11:45.125852 BL = 0x2
2274 22:11:45.125928 RPST = 0x0
2275 22:11:45.129012 RD_PRE = 0x0
2276 22:11:45.132767 WR_PRE = 0x1
2277 22:11:45.132845 WR_PST = 0x0
2278 22:11:45.135992 DBI_WR = 0x0
2279 22:11:45.136066 DBI_RD = 0x0
2280 22:11:45.139065 OTF = 0x1
2281 22:11:45.142350 ===================================
2282 22:11:45.145546 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2283 22:11:45.145624 ==
2284 22:11:45.149097 Dram Type= 6, Freq= 0, CH_0, rank 0
2285 22:11:45.155811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2286 22:11:45.155889 ==
2287 22:11:45.155952 [Duty_Offset_Calibration]
2288 22:11:45.158986 B0:2 B1:1 CA:1
2289 22:11:45.159063
2290 22:11:45.162257 [DutyScan_Calibration_Flow] k_type=0
2291 22:11:45.171456
2292 22:11:45.171534 ==CLK 0==
2293 22:11:45.174798 Final CLK duty delay cell = 0
2294 22:11:45.178176 [0] MAX Duty = 5187%(X100), DQS PI = 24
2295 22:11:45.181394 [0] MIN Duty = 4844%(X100), DQS PI = 48
2296 22:11:45.181506 [0] AVG Duty = 5015%(X100)
2297 22:11:45.185055
2298 22:11:45.188297 CH0 CLK Duty spec in!! Max-Min= 343%
2299 22:11:45.191466 [DutyScan_Calibration_Flow] ====Done====
2300 22:11:45.191575
2301 22:11:45.195169 [DutyScan_Calibration_Flow] k_type=1
2302 22:11:45.210268
2303 22:11:45.210357 ==DQS 0 ==
2304 22:11:45.213941 Final DQS duty delay cell = -4
2305 22:11:45.217184 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2306 22:11:45.220183 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2307 22:11:45.223751 [-4] AVG Duty = 4937%(X100)
2308 22:11:45.223825
2309 22:11:45.223888 ==DQS 1 ==
2310 22:11:45.227069 Final DQS duty delay cell = 0
2311 22:11:45.230291 [0] MAX Duty = 5156%(X100), DQS PI = 0
2312 22:11:45.233462 [0] MIN Duty = 5000%(X100), DQS PI = 34
2313 22:11:45.237253 [0] AVG Duty = 5078%(X100)
2314 22:11:45.237329
2315 22:11:45.240522 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2316 22:11:45.240609
2317 22:11:45.243849 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2318 22:11:45.247051 [DutyScan_Calibration_Flow] ====Done====
2319 22:11:45.247127
2320 22:11:45.250313 [DutyScan_Calibration_Flow] k_type=3
2321 22:11:45.267084
2322 22:11:45.267220 ==DQM 0 ==
2323 22:11:45.270398 Final DQM duty delay cell = 0
2324 22:11:45.273863 [0] MAX Duty = 5156%(X100), DQS PI = 30
2325 22:11:45.276921 [0] MIN Duty = 4906%(X100), DQS PI = 58
2326 22:11:45.280535 [0] AVG Duty = 5031%(X100)
2327 22:11:45.280638
2328 22:11:45.280731 ==DQM 1 ==
2329 22:11:45.283708 Final DQM duty delay cell = 0
2330 22:11:45.286896 [0] MAX Duty = 5125%(X100), DQS PI = 24
2331 22:11:45.290169 [0] MIN Duty = 5031%(X100), DQS PI = 36
2332 22:11:45.293913 [0] AVG Duty = 5078%(X100)
2333 22:11:45.294018
2334 22:11:45.297024 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2335 22:11:45.297135
2336 22:11:45.300648 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2337 22:11:45.303853 [DutyScan_Calibration_Flow] ====Done====
2338 22:11:45.303959
2339 22:11:45.306788 [DutyScan_Calibration_Flow] k_type=2
2340 22:11:45.323305
2341 22:11:45.323416 ==DQ 0 ==
2342 22:11:45.326714 Final DQ duty delay cell = 0
2343 22:11:45.330421 [0] MAX Duty = 5062%(X100), DQS PI = 32
2344 22:11:45.333452 [0] MIN Duty = 4906%(X100), DQS PI = 0
2345 22:11:45.333570 [0] AVG Duty = 4984%(X100)
2346 22:11:45.333670
2347 22:11:45.337031 ==DQ 1 ==
2348 22:11:45.340299 Final DQ duty delay cell = 0
2349 22:11:45.343566 [0] MAX Duty = 5093%(X100), DQS PI = 10
2350 22:11:45.346952 [0] MIN Duty = 4907%(X100), DQS PI = 36
2351 22:11:45.347062 [0] AVG Duty = 5000%(X100)
2352 22:11:45.347157
2353 22:11:45.350501 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2354 22:11:45.350601
2355 22:11:45.353877 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2356 22:11:45.360429 [DutyScan_Calibration_Flow] ====Done====
2357 22:11:45.360533 ==
2358 22:11:45.363865 Dram Type= 6, Freq= 0, CH_1, rank 0
2359 22:11:45.367721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2360 22:11:45.367806 ==
2361 22:11:45.370642 [Duty_Offset_Calibration]
2362 22:11:45.370719 B0:1 B1:0 CA:0
2363 22:11:45.370782
2364 22:11:45.373768 [DutyScan_Calibration_Flow] k_type=0
2365 22:11:45.382912
2366 22:11:45.382995 ==CLK 0==
2367 22:11:45.385941 Final CLK duty delay cell = -4
2368 22:11:45.389485 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2369 22:11:45.392597 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2370 22:11:45.396321 [-4] AVG Duty = 4953%(X100)
2371 22:11:45.396400
2372 22:11:45.399648 CH1 CLK Duty spec in!! Max-Min= 156%
2373 22:11:45.402836 [DutyScan_Calibration_Flow] ====Done====
2374 22:11:45.402940
2375 22:11:45.405966 [DutyScan_Calibration_Flow] k_type=1
2376 22:11:45.422721
2377 22:11:45.422807 ==DQS 0 ==
2378 22:11:45.425657 Final DQS duty delay cell = 0
2379 22:11:45.429173 [0] MAX Duty = 5094%(X100), DQS PI = 26
2380 22:11:45.432378 [0] MIN Duty = 4875%(X100), DQS PI = 0
2381 22:11:45.432463 [0] AVG Duty = 4984%(X100)
2382 22:11:45.435743
2383 22:11:45.435849 ==DQS 1 ==
2384 22:11:45.439184 Final DQS duty delay cell = 0
2385 22:11:45.442402 [0] MAX Duty = 5218%(X100), DQS PI = 20
2386 22:11:45.445677 [0] MIN Duty = 4969%(X100), DQS PI = 10
2387 22:11:45.445778 [0] AVG Duty = 5093%(X100)
2388 22:11:45.448933
2389 22:11:45.452594 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2390 22:11:45.452671
2391 22:11:45.455776 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2392 22:11:45.458901 [DutyScan_Calibration_Flow] ====Done====
2393 22:11:45.459002
2394 22:11:45.462425 [DutyScan_Calibration_Flow] k_type=3
2395 22:11:45.479202
2396 22:11:45.479314 ==DQM 0 ==
2397 22:11:45.482578 Final DQM duty delay cell = 0
2398 22:11:45.485749 [0] MAX Duty = 5156%(X100), DQS PI = 6
2399 22:11:45.488876 [0] MIN Duty = 5031%(X100), DQS PI = 0
2400 22:11:45.488978 [0] AVG Duty = 5093%(X100)
2401 22:11:45.492504
2402 22:11:45.492621 ==DQM 1 ==
2403 22:11:45.495787 Final DQM duty delay cell = 0
2404 22:11:45.499378 [0] MAX Duty = 5062%(X100), DQS PI = 44
2405 22:11:45.502736 [0] MIN Duty = 4907%(X100), DQS PI = 52
2406 22:11:45.502810 [0] AVG Duty = 4984%(X100)
2407 22:11:45.502895
2408 22:11:45.508888 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2409 22:11:45.509026
2410 22:11:45.512503 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2411 22:11:45.516083 [DutyScan_Calibration_Flow] ====Done====
2412 22:11:45.516197
2413 22:11:45.519314 [DutyScan_Calibration_Flow] k_type=2
2414 22:11:45.534747
2415 22:11:45.534858 ==DQ 0 ==
2416 22:11:45.538123 Final DQ duty delay cell = -4
2417 22:11:45.541316 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2418 22:11:45.544917 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2419 22:11:45.548195 [-4] AVG Duty = 5000%(X100)
2420 22:11:45.548281
2421 22:11:45.548372 ==DQ 1 ==
2422 22:11:45.551301 Final DQ duty delay cell = 0
2423 22:11:45.554531 [0] MAX Duty = 5125%(X100), DQS PI = 20
2424 22:11:45.557789 [0] MIN Duty = 4969%(X100), DQS PI = 10
2425 22:11:45.557900 [0] AVG Duty = 5047%(X100)
2426 22:11:45.561154
2427 22:11:45.564822 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2428 22:11:45.564925
2429 22:11:45.568146 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2430 22:11:45.571135 [DutyScan_Calibration_Flow] ====Done====
2431 22:11:45.574558 nWR fixed to 30
2432 22:11:45.574672 [ModeRegInit_LP4] CH0 RK0
2433 22:11:45.577782 [ModeRegInit_LP4] CH0 RK1
2434 22:11:45.581136 [ModeRegInit_LP4] CH1 RK0
2435 22:11:45.584786 [ModeRegInit_LP4] CH1 RK1
2436 22:11:45.584899 match AC timing 7
2437 22:11:45.588145 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2438 22:11:45.594517 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2439 22:11:45.597989 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2440 22:11:45.604394 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2441 22:11:45.608042 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2442 22:11:45.608159 ==
2443 22:11:45.611348 Dram Type= 6, Freq= 0, CH_0, rank 0
2444 22:11:45.614370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 22:11:45.614477 ==
2446 22:11:45.621628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2447 22:11:45.628021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2448 22:11:45.634860 [CA 0] Center 39 (8~70) winsize 63
2449 22:11:45.638478 [CA 1] Center 39 (8~70) winsize 63
2450 22:11:45.641488 [CA 2] Center 35 (4~66) winsize 63
2451 22:11:45.645190 [CA 3] Center 34 (4~65) winsize 62
2452 22:11:45.648251 [CA 4] Center 33 (3~64) winsize 62
2453 22:11:45.651989 [CA 5] Center 32 (3~62) winsize 60
2454 22:11:45.652070
2455 22:11:45.654979 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2456 22:11:45.655081
2457 22:11:45.658217 [CATrainingPosCal] consider 1 rank data
2458 22:11:45.661460 u2DelayCellTimex100 = 270/100 ps
2459 22:11:45.665213 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2460 22:11:45.668353 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2461 22:11:45.674904 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2462 22:11:45.678477 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2463 22:11:45.681950 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2464 22:11:45.684899 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2465 22:11:45.684995
2466 22:11:45.688350 CA PerBit enable=1, Macro0, CA PI delay=32
2467 22:11:45.688432
2468 22:11:45.692050 [CBTSetCACLKResult] CA Dly = 32
2469 22:11:45.692135 CS Dly: 6 (0~37)
2470 22:11:45.692200 ==
2471 22:11:45.695333 Dram Type= 6, Freq= 0, CH_0, rank 1
2472 22:11:45.701942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2473 22:11:45.702025 ==
2474 22:11:45.705461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2475 22:11:45.711513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2476 22:11:45.720434 [CA 0] Center 38 (8~69) winsize 62
2477 22:11:45.724034 [CA 1] Center 38 (8~69) winsize 62
2478 22:11:45.727137 [CA 2] Center 35 (4~66) winsize 63
2479 22:11:45.730341 [CA 3] Center 34 (4~65) winsize 62
2480 22:11:45.734090 [CA 4] Center 33 (3~64) winsize 62
2481 22:11:45.737247 [CA 5] Center 32 (3~62) winsize 60
2482 22:11:45.737356
2483 22:11:45.740375 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2484 22:11:45.740459
2485 22:11:45.744096 [CATrainingPosCal] consider 2 rank data
2486 22:11:45.747166 u2DelayCellTimex100 = 270/100 ps
2487 22:11:45.750794 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2488 22:11:45.753897 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2489 22:11:45.760436 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2490 22:11:45.764392 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2491 22:11:45.767262 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2492 22:11:45.770611 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2493 22:11:45.770716
2494 22:11:45.774085 CA PerBit enable=1, Macro0, CA PI delay=32
2495 22:11:45.774163
2496 22:11:45.777300 [CBTSetCACLKResult] CA Dly = 32
2497 22:11:45.777374 CS Dly: 6 (0~38)
2498 22:11:45.777437
2499 22:11:45.780849 ----->DramcWriteLeveling(PI) begin...
2500 22:11:45.783871 ==
2501 22:11:45.787310 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 22:11:45.790743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 22:11:45.790853 ==
2504 22:11:45.794424 Write leveling (Byte 0): 35 => 35
2505 22:11:45.797597 Write leveling (Byte 1): 29 => 29
2506 22:11:45.800762 DramcWriteLeveling(PI) end<-----
2507 22:11:45.800872
2508 22:11:45.800964 ==
2509 22:11:45.803885 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 22:11:45.807543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 22:11:45.807677 ==
2512 22:11:45.810787 [Gating] SW mode calibration
2513 22:11:45.817852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2514 22:11:45.821220 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2515 22:11:45.827807 0 15 0 | B1->B0 | 2323 3333 | 1 1 | (1 1) (1 1)
2516 22:11:45.830960 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2517 22:11:45.834124 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 22:11:45.840756 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 22:11:45.844382 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 22:11:45.847580 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 22:11:45.854316 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2522 22:11:45.857704 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
2523 22:11:45.861043 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
2524 22:11:45.867656 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 22:11:45.871129 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 22:11:45.874296 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 22:11:45.880899 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 22:11:45.884098 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 22:11:45.887780 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2530 22:11:45.891081 1 0 28 | B1->B0 | 2b2b 4545 | 0 0 | (1 1) (0 0)
2531 22:11:45.897924 1 1 0 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
2532 22:11:45.901234 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 22:11:45.904123 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 22:11:45.910800 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 22:11:45.914147 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 22:11:45.917990 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 22:11:45.924477 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2538 22:11:45.927496 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2539 22:11:45.930936 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2540 22:11:45.938114 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2541 22:11:45.941358 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 22:11:45.944994 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 22:11:45.947914 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 22:11:45.954657 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 22:11:45.958326 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 22:11:45.961473 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 22:11:45.968197 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 22:11:45.971377 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 22:11:45.974972 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 22:11:45.981215 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 22:11:45.984588 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 22:11:45.987657 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 22:11:45.994942 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2554 22:11:45.998310 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2555 22:11:46.001453 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2556 22:11:46.008219 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 22:11:46.008353 Total UI for P1: 0, mck2ui 16
2558 22:11:46.015124 best dqsien dly found for B0: ( 1, 3, 28)
2559 22:11:46.015235 Total UI for P1: 0, mck2ui 16
2560 22:11:46.018347 best dqsien dly found for B1: ( 1, 3, 30)
2561 22:11:46.021796 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2562 22:11:46.028186 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2563 22:11:46.028292
2564 22:11:46.031396 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2565 22:11:46.034851 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2566 22:11:46.038312 [Gating] SW calibration Done
2567 22:11:46.038418 ==
2568 22:11:46.041572 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 22:11:46.044887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 22:11:46.045020 ==
2571 22:11:46.045137 RX Vref Scan: 0
2572 22:11:46.048064
2573 22:11:46.048193 RX Vref 0 -> 0, step: 1
2574 22:11:46.048308
2575 22:11:46.051819 RX Delay -40 -> 252, step: 8
2576 22:11:46.054939 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2577 22:11:46.058160 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2578 22:11:46.064769 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2579 22:11:46.067914 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2580 22:11:46.071639 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2581 22:11:46.074656 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2582 22:11:46.078287 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2583 22:11:46.085125 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2584 22:11:46.088060 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2585 22:11:46.091636 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2586 22:11:46.094772 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2587 22:11:46.097976 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2588 22:11:46.105012 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2589 22:11:46.108160 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2590 22:11:46.111932 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2591 22:11:46.114988 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2592 22:11:46.115112 ==
2593 22:11:46.118255 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 22:11:46.125155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 22:11:46.125285 ==
2596 22:11:46.125406 DQS Delay:
2597 22:11:46.125516 DQS0 = 0, DQS1 = 0
2598 22:11:46.128471 DQM Delay:
2599 22:11:46.128597 DQM0 = 121, DQM1 = 113
2600 22:11:46.131552 DQ Delay:
2601 22:11:46.135252 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2602 22:11:46.138169 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2603 22:11:46.141943 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2604 22:11:46.144882 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2605 22:11:46.144959
2606 22:11:46.145023
2607 22:11:46.145083 ==
2608 22:11:46.148418 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 22:11:46.152176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 22:11:46.152280 ==
2611 22:11:46.152365
2612 22:11:46.152433
2613 22:11:46.154852 TX Vref Scan disable
2614 22:11:46.158629 == TX Byte 0 ==
2615 22:11:46.161934 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2616 22:11:46.165051 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2617 22:11:46.168761 == TX Byte 1 ==
2618 22:11:46.172089 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2619 22:11:46.175304 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2620 22:11:46.175403 ==
2621 22:11:46.178262 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 22:11:46.181935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 22:11:46.185364 ==
2624 22:11:46.196022 TX Vref=22, minBit 4, minWin=24, winSum=404
2625 22:11:46.199475 TX Vref=24, minBit 4, minWin=24, winSum=405
2626 22:11:46.202626 TX Vref=26, minBit 4, minWin=25, winSum=415
2627 22:11:46.205875 TX Vref=28, minBit 13, minWin=25, winSum=420
2628 22:11:46.208954 TX Vref=30, minBit 1, minWin=26, winSum=421
2629 22:11:46.215690 TX Vref=32, minBit 10, minWin=25, winSum=418
2630 22:11:46.219368 [TxChooseVref] Worse bit 1, Min win 26, Win sum 421, Final Vref 30
2631 22:11:46.219474
2632 22:11:46.222641 Final TX Range 1 Vref 30
2633 22:11:46.222718
2634 22:11:46.222780 ==
2635 22:11:46.225637 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 22:11:46.228989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 22:11:46.229092 ==
2638 22:11:46.232195
2639 22:11:46.232271
2640 22:11:46.232333 TX Vref Scan disable
2641 22:11:46.235767 == TX Byte 0 ==
2642 22:11:46.238946 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2643 22:11:46.242649 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2644 22:11:46.245686 == TX Byte 1 ==
2645 22:11:46.249382 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2646 22:11:46.252263 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2647 22:11:46.255908
2648 22:11:46.256009 [DATLAT]
2649 22:11:46.256100 Freq=1200, CH0 RK0
2650 22:11:46.256168
2651 22:11:46.259230 DATLAT Default: 0xd
2652 22:11:46.259325 0, 0xFFFF, sum = 0
2653 22:11:46.262402 1, 0xFFFF, sum = 0
2654 22:11:46.262508 2, 0xFFFF, sum = 0
2655 22:11:46.265615 3, 0xFFFF, sum = 0
2656 22:11:46.265698 4, 0xFFFF, sum = 0
2657 22:11:46.269347 5, 0xFFFF, sum = 0
2658 22:11:46.272465 6, 0xFFFF, sum = 0
2659 22:11:46.272551 7, 0xFFFF, sum = 0
2660 22:11:46.275686 8, 0xFFFF, sum = 0
2661 22:11:46.275800 9, 0xFFFF, sum = 0
2662 22:11:46.279437 10, 0xFFFF, sum = 0
2663 22:11:46.279540 11, 0xFFFF, sum = 0
2664 22:11:46.282732 12, 0x0, sum = 1
2665 22:11:46.282809 13, 0x0, sum = 2
2666 22:11:46.282873 14, 0x0, sum = 3
2667 22:11:46.285937 15, 0x0, sum = 4
2668 22:11:46.286050 best_step = 13
2669 22:11:46.286141
2670 22:11:46.289310 ==
2671 22:11:46.289387 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 22:11:46.295741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 22:11:46.295839 ==
2674 22:11:46.295933 RX Vref Scan: 1
2675 22:11:46.296022
2676 22:11:46.299671 Set Vref Range= 32 -> 127
2677 22:11:46.299747
2678 22:11:46.302628 RX Vref 32 -> 127, step: 1
2679 22:11:46.302731
2680 22:11:46.305844 RX Delay -13 -> 252, step: 4
2681 22:11:46.305945
2682 22:11:46.309122 Set Vref, RX VrefLevel [Byte0]: 32
2683 22:11:46.312525 [Byte1]: 32
2684 22:11:46.312642
2685 22:11:46.315895 Set Vref, RX VrefLevel [Byte0]: 33
2686 22:11:46.319243 [Byte1]: 33
2687 22:11:46.319346
2688 22:11:46.322645 Set Vref, RX VrefLevel [Byte0]: 34
2689 22:11:46.325807 [Byte1]: 34
2690 22:11:46.329999
2691 22:11:46.330099 Set Vref, RX VrefLevel [Byte0]: 35
2692 22:11:46.333516 [Byte1]: 35
2693 22:11:46.337617
2694 22:11:46.337751 Set Vref, RX VrefLevel [Byte0]: 36
2695 22:11:46.341302 [Byte1]: 36
2696 22:11:46.345592
2697 22:11:46.345698 Set Vref, RX VrefLevel [Byte0]: 37
2698 22:11:46.349092 [Byte1]: 37
2699 22:11:46.353448
2700 22:11:46.353533 Set Vref, RX VrefLevel [Byte0]: 38
2701 22:11:46.356735 [Byte1]: 38
2702 22:11:46.361692
2703 22:11:46.361798 Set Vref, RX VrefLevel [Byte0]: 39
2704 22:11:46.364610 [Byte1]: 39
2705 22:11:46.369501
2706 22:11:46.369636 Set Vref, RX VrefLevel [Byte0]: 40
2707 22:11:46.372660 [Byte1]: 40
2708 22:11:46.377582
2709 22:11:46.377709 Set Vref, RX VrefLevel [Byte0]: 41
2710 22:11:46.380534 [Byte1]: 41
2711 22:11:46.385004
2712 22:11:46.385128 Set Vref, RX VrefLevel [Byte0]: 42
2713 22:11:46.388545 [Byte1]: 42
2714 22:11:46.392891
2715 22:11:46.393014 Set Vref, RX VrefLevel [Byte0]: 43
2716 22:11:46.396694 [Byte1]: 43
2717 22:11:46.400942
2718 22:11:46.401068 Set Vref, RX VrefLevel [Byte0]: 44
2719 22:11:46.404503 [Byte1]: 44
2720 22:11:46.409167
2721 22:11:46.409296 Set Vref, RX VrefLevel [Byte0]: 45
2722 22:11:46.412321 [Byte1]: 45
2723 22:11:46.417259
2724 22:11:46.417383 Set Vref, RX VrefLevel [Byte0]: 46
2725 22:11:46.420071 [Byte1]: 46
2726 22:11:46.424703
2727 22:11:46.424829 Set Vref, RX VrefLevel [Byte0]: 47
2728 22:11:46.428322 [Byte1]: 47
2729 22:11:46.432569
2730 22:11:46.432693 Set Vref, RX VrefLevel [Byte0]: 48
2731 22:11:46.435707 [Byte1]: 48
2732 22:11:46.440574
2733 22:11:46.440702 Set Vref, RX VrefLevel [Byte0]: 49
2734 22:11:46.443567 [Byte1]: 49
2735 22:11:46.448326
2736 22:11:46.448450 Set Vref, RX VrefLevel [Byte0]: 50
2737 22:11:46.451683 [Byte1]: 50
2738 22:11:46.456117
2739 22:11:46.456241 Set Vref, RX VrefLevel [Byte0]: 51
2740 22:11:46.459323 [Byte1]: 51
2741 22:11:46.464316
2742 22:11:46.464440 Set Vref, RX VrefLevel [Byte0]: 52
2743 22:11:46.467482 [Byte1]: 52
2744 22:11:46.471830
2745 22:11:46.471957 Set Vref, RX VrefLevel [Byte0]: 53
2746 22:11:46.475521 [Byte1]: 53
2747 22:11:46.480071
2748 22:11:46.480229 Set Vref, RX VrefLevel [Byte0]: 54
2749 22:11:46.483130 [Byte1]: 54
2750 22:11:46.487946
2751 22:11:46.488067 Set Vref, RX VrefLevel [Byte0]: 55
2752 22:11:46.491408 [Byte1]: 55
2753 22:11:46.496041
2754 22:11:46.496220 Set Vref, RX VrefLevel [Byte0]: 56
2755 22:11:46.498995 [Byte1]: 56
2756 22:11:46.503946
2757 22:11:46.504072 Set Vref, RX VrefLevel [Byte0]: 57
2758 22:11:46.506850 [Byte1]: 57
2759 22:11:46.511489
2760 22:11:46.511635 Set Vref, RX VrefLevel [Byte0]: 58
2761 22:11:46.515026 [Byte1]: 58
2762 22:11:46.519900
2763 22:11:46.520038 Set Vref, RX VrefLevel [Byte0]: 59
2764 22:11:46.522834 [Byte1]: 59
2765 22:11:46.527130
2766 22:11:46.527331 Set Vref, RX VrefLevel [Byte0]: 60
2767 22:11:46.530682 [Byte1]: 60
2768 22:11:46.535206
2769 22:11:46.535337 Set Vref, RX VrefLevel [Byte0]: 61
2770 22:11:46.538619 [Byte1]: 61
2771 22:11:46.542993
2772 22:11:46.543117 Set Vref, RX VrefLevel [Byte0]: 62
2773 22:11:46.546542 [Byte1]: 62
2774 22:11:46.551147
2775 22:11:46.551264 Set Vref, RX VrefLevel [Byte0]: 63
2776 22:11:46.554261 [Byte1]: 63
2777 22:11:46.558943
2778 22:11:46.559067 Set Vref, RX VrefLevel [Byte0]: 64
2779 22:11:46.562193 [Byte1]: 64
2780 22:11:46.566838
2781 22:11:46.566961 Set Vref, RX VrefLevel [Byte0]: 65
2782 22:11:46.570312 [Byte1]: 65
2783 22:11:46.574728
2784 22:11:46.574851 Set Vref, RX VrefLevel [Byte0]: 66
2785 22:11:46.578006 [Byte1]: 66
2786 22:11:46.582537
2787 22:11:46.582662 Set Vref, RX VrefLevel [Byte0]: 67
2788 22:11:46.585817 [Byte1]: 67
2789 22:11:46.590331
2790 22:11:46.590455 Set Vref, RX VrefLevel [Byte0]: 68
2791 22:11:46.593670 [Byte1]: 68
2792 22:11:46.598448
2793 22:11:46.598576 Set Vref, RX VrefLevel [Byte0]: 69
2794 22:11:46.601742 [Byte1]: 69
2795 22:11:46.606039
2796 22:11:46.606142 Set Vref, RX VrefLevel [Byte0]: 70
2797 22:11:46.609443 [Byte1]: 70
2798 22:11:46.614095
2799 22:11:46.614178 Final RX Vref Byte 0 = 54 to rank0
2800 22:11:46.617437 Final RX Vref Byte 1 = 53 to rank0
2801 22:11:46.620906 Final RX Vref Byte 0 = 54 to rank1
2802 22:11:46.624414 Final RX Vref Byte 1 = 53 to rank1==
2803 22:11:46.627351 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 22:11:46.634287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 22:11:46.634376 ==
2806 22:11:46.634443 DQS Delay:
2807 22:11:46.634504 DQS0 = 0, DQS1 = 0
2808 22:11:46.637496 DQM Delay:
2809 22:11:46.637579 DQM0 = 120, DQM1 = 112
2810 22:11:46.640953 DQ Delay:
2811 22:11:46.643838 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2812 22:11:46.647292 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2813 22:11:46.650696 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2814 22:11:46.653882 DQ12 =120, DQ13 =116, DQ14 =124, DQ15 =122
2815 22:11:46.653966
2816 22:11:46.654032
2817 22:11:46.664066 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2818 22:11:46.664152 CH0 RK0: MR19=404, MR18=160F
2819 22:11:46.670400 CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27
2820 22:11:46.670488
2821 22:11:46.674249 ----->DramcWriteLeveling(PI) begin...
2822 22:11:46.674332 ==
2823 22:11:46.677330 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 22:11:46.680654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 22:11:46.684444 ==
2826 22:11:46.684540 Write leveling (Byte 0): 36 => 36
2827 22:11:46.687236 Write leveling (Byte 1): 31 => 31
2828 22:11:46.690873 DramcWriteLeveling(PI) end<-----
2829 22:11:46.690986
2830 22:11:46.691077 ==
2831 22:11:46.694158 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 22:11:46.700811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 22:11:46.700897 ==
2834 22:11:46.700993 [Gating] SW mode calibration
2835 22:11:46.710594 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 22:11:46.714163 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 22:11:46.720587 0 15 0 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (1 1)
2838 22:11:46.724352 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 22:11:46.727393 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 22:11:46.730866 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 22:11:46.737624 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 22:11:46.740909 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 22:11:46.744390 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
2844 22:11:46.750681 0 15 28 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 0)
2845 22:11:46.753921 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 22:11:46.757795 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 22:11:46.763874 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 22:11:46.767363 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 22:11:46.770869 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 22:11:46.777752 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 22:11:46.780849 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 22:11:46.784252 1 0 28 | B1->B0 | 3a3a 3939 | 0 1 | (0 0) (1 1)
2853 22:11:46.790619 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 22:11:46.794417 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 22:11:46.797862 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 22:11:46.800821 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 22:11:46.807465 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 22:11:46.810658 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 22:11:46.814181 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 22:11:46.820626 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2861 22:11:46.824353 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2862 22:11:46.827586 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 22:11:46.834156 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 22:11:46.837843 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 22:11:46.840887 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 22:11:46.847777 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 22:11:46.851038 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 22:11:46.854361 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 22:11:46.861075 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 22:11:46.864394 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 22:11:46.867865 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 22:11:46.874608 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 22:11:46.877704 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 22:11:46.881313 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 22:11:46.884520 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 22:11:46.891341 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2877 22:11:46.894754 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2878 22:11:46.898020 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 22:11:46.901365 Total UI for P1: 0, mck2ui 16
2880 22:11:46.905028 best dqsien dly found for B0: ( 1, 3, 30)
2881 22:11:46.908099 Total UI for P1: 0, mck2ui 16
2882 22:11:46.911217 best dqsien dly found for B1: ( 1, 3, 30)
2883 22:11:46.914928 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2884 22:11:46.917894 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2885 22:11:46.917973
2886 22:11:46.921809 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2887 22:11:46.927986 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2888 22:11:46.928074 [Gating] SW calibration Done
2889 22:11:46.928139 ==
2890 22:11:46.931755 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 22:11:46.938257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 22:11:46.938367 ==
2893 22:11:46.938469 RX Vref Scan: 0
2894 22:11:46.938561
2895 22:11:46.941666 RX Vref 0 -> 0, step: 1
2896 22:11:46.941793
2897 22:11:46.944812 RX Delay -40 -> 252, step: 8
2898 22:11:46.948145 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2899 22:11:46.951407 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2900 22:11:46.955076 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2901 22:11:46.961767 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2902 22:11:46.964877 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2903 22:11:46.968094 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2904 22:11:46.971434 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
2905 22:11:46.975243 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2906 22:11:46.978126 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2907 22:11:46.984873 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2908 22:11:46.988348 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2909 22:11:46.991704 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2910 22:11:46.995182 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2911 22:11:46.998578 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2912 22:11:47.004958 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2913 22:11:47.008291 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2914 22:11:47.008411 ==
2915 22:11:47.012038 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 22:11:47.015244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 22:11:47.015345 ==
2918 22:11:47.018412 DQS Delay:
2919 22:11:47.018508 DQS0 = 0, DQS1 = 0
2920 22:11:47.018596 DQM Delay:
2921 22:11:47.021652 DQM0 = 123, DQM1 = 113
2922 22:11:47.021734 DQ Delay:
2923 22:11:47.024871 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2924 22:11:47.028278 DQ4 =127, DQ5 =119, DQ6 =131, DQ7 =127
2925 22:11:47.031570 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2926 22:11:47.038379 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2927 22:11:47.038461
2928 22:11:47.038525
2929 22:11:47.038584 ==
2930 22:11:47.041692 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 22:11:47.045388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 22:11:47.045470 ==
2933 22:11:47.045536
2934 22:11:47.045595
2935 22:11:47.048573 TX Vref Scan disable
2936 22:11:47.048655 == TX Byte 0 ==
2937 22:11:47.055211 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2938 22:11:47.058442 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2939 22:11:47.058525 == TX Byte 1 ==
2940 22:11:47.065105 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2941 22:11:47.068248 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2942 22:11:47.068331 ==
2943 22:11:47.071923 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 22:11:47.075112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 22:11:47.075196 ==
2946 22:11:47.088196 TX Vref=22, minBit 7, minWin=25, winSum=417
2947 22:11:47.091902 TX Vref=24, minBit 10, minWin=25, winSum=417
2948 22:11:47.095183 TX Vref=26, minBit 10, minWin=25, winSum=418
2949 22:11:47.098428 TX Vref=28, minBit 1, minWin=25, winSum=417
2950 22:11:47.101685 TX Vref=30, minBit 0, minWin=26, winSum=420
2951 22:11:47.108310 TX Vref=32, minBit 5, minWin=25, winSum=420
2952 22:11:47.111808 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 30
2953 22:11:47.111895
2954 22:11:47.115161 Final TX Range 1 Vref 30
2955 22:11:47.115271
2956 22:11:47.115365 ==
2957 22:11:47.118657 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 22:11:47.121897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 22:11:47.122009 ==
2960 22:11:47.125116
2961 22:11:47.125199
2962 22:11:47.125265 TX Vref Scan disable
2963 22:11:47.128405 == TX Byte 0 ==
2964 22:11:47.131801 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2965 22:11:47.135351 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2966 22:11:47.138034 == TX Byte 1 ==
2967 22:11:47.141638 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2968 22:11:47.148260 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2969 22:11:47.148352
2970 22:11:47.148417 [DATLAT]
2971 22:11:47.148476 Freq=1200, CH0 RK1
2972 22:11:47.148548
2973 22:11:47.151501 DATLAT Default: 0xd
2974 22:11:47.151610 0, 0xFFFF, sum = 0
2975 22:11:47.154624 1, 0xFFFF, sum = 0
2976 22:11:47.154700 2, 0xFFFF, sum = 0
2977 22:11:47.158252 3, 0xFFFF, sum = 0
2978 22:11:47.161487 4, 0xFFFF, sum = 0
2979 22:11:47.161564 5, 0xFFFF, sum = 0
2980 22:11:47.164712 6, 0xFFFF, sum = 0
2981 22:11:47.164819 7, 0xFFFF, sum = 0
2982 22:11:47.168558 8, 0xFFFF, sum = 0
2983 22:11:47.168646 9, 0xFFFF, sum = 0
2984 22:11:47.171197 10, 0xFFFF, sum = 0
2985 22:11:47.171304 11, 0xFFFF, sum = 0
2986 22:11:47.174578 12, 0x0, sum = 1
2987 22:11:47.174679 13, 0x0, sum = 2
2988 22:11:47.177878 14, 0x0, sum = 3
2989 22:11:47.177997 15, 0x0, sum = 4
2990 22:11:47.181586 best_step = 13
2991 22:11:47.181693
2992 22:11:47.181785 ==
2993 22:11:47.184856 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 22:11:47.188113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 22:11:47.188189 ==
2996 22:11:47.188253 RX Vref Scan: 0
2997 22:11:47.188314
2998 22:11:47.191327 RX Vref 0 -> 0, step: 1
2999 22:11:47.191422
3000 22:11:47.194860 RX Delay -13 -> 252, step: 4
3001 22:11:47.198146 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3002 22:11:47.204924 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3003 22:11:47.208066 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3004 22:11:47.211283 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3005 22:11:47.214943 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3006 22:11:47.218083 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3007 22:11:47.224901 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3008 22:11:47.228236 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3009 22:11:47.231552 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3010 22:11:47.234948 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3011 22:11:47.237961 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3012 22:11:47.244945 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3013 22:11:47.248342 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3014 22:11:47.251330 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3015 22:11:47.254829 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3016 22:11:47.258220 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3017 22:11:47.258327 ==
3018 22:11:47.261434 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 22:11:47.268446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 22:11:47.268575 ==
3021 22:11:47.268691 DQS Delay:
3022 22:11:47.272051 DQS0 = 0, DQS1 = 0
3023 22:11:47.272172 DQM Delay:
3024 22:11:47.272288 DQM0 = 121, DQM1 = 111
3025 22:11:47.274783 DQ Delay:
3026 22:11:47.278466 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3027 22:11:47.281698 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3028 22:11:47.285032 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
3029 22:11:47.288400 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =118
3030 22:11:47.288522
3031 22:11:47.288636
3032 22:11:47.298304 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3033 22:11:47.298433 CH0 RK1: MR19=403, MR18=12F3
3034 22:11:47.304618 CH0_RK1: MR19=0x403, MR18=0x12F3, DQSOSC=403, MR23=63, INC=40, DEC=26
3035 22:11:47.308240 [RxdqsGatingPostProcess] freq 1200
3036 22:11:47.315079 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3037 22:11:47.318339 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 22:11:47.321499 best DQS1 dly(2T, 0.5T) = (0, 11)
3039 22:11:47.324905 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 22:11:47.328029 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3041 22:11:47.331685 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 22:11:47.331810 best DQS1 dly(2T, 0.5T) = (0, 11)
3043 22:11:47.334950 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 22:11:47.338118 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3045 22:11:47.341679 Pre-setting of DQS Precalculation
3046 22:11:47.348304 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3047 22:11:47.348413 ==
3048 22:11:47.351370 Dram Type= 6, Freq= 0, CH_1, rank 0
3049 22:11:47.355132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 22:11:47.355231 ==
3051 22:11:47.361761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3052 22:11:47.368333 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3053 22:11:47.374946 [CA 0] Center 37 (7~68) winsize 62
3054 22:11:47.378243 [CA 1] Center 37 (7~68) winsize 62
3055 22:11:47.381684 [CA 2] Center 35 (5~65) winsize 61
3056 22:11:47.385141 [CA 3] Center 34 (4~64) winsize 61
3057 22:11:47.388241 [CA 4] Center 34 (4~64) winsize 61
3058 22:11:47.391551 [CA 5] Center 33 (3~63) winsize 61
3059 22:11:47.391677
3060 22:11:47.394947 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3061 22:11:47.395020
3062 22:11:47.398310 [CATrainingPosCal] consider 1 rank data
3063 22:11:47.401924 u2DelayCellTimex100 = 270/100 ps
3064 22:11:47.405046 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 22:11:47.408278 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3066 22:11:47.411885 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3067 22:11:47.418786 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3068 22:11:47.422046 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3069 22:11:47.425016 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3070 22:11:47.425097
3071 22:11:47.428359 CA PerBit enable=1, Macro0, CA PI delay=33
3072 22:11:47.428433
3073 22:11:47.431981 [CBTSetCACLKResult] CA Dly = 33
3074 22:11:47.432059 CS Dly: 8 (0~39)
3075 22:11:47.432124 ==
3076 22:11:47.435076 Dram Type= 6, Freq= 0, CH_1, rank 1
3077 22:11:47.441582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 22:11:47.441666 ==
3079 22:11:47.445078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3080 22:11:47.451738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3081 22:11:47.461053 [CA 0] Center 37 (7~68) winsize 62
3082 22:11:47.464187 [CA 1] Center 38 (8~68) winsize 61
3083 22:11:47.467484 [CA 2] Center 35 (5~65) winsize 61
3084 22:11:47.470541 [CA 3] Center 34 (4~65) winsize 62
3085 22:11:47.473918 [CA 4] Center 34 (4~65) winsize 62
3086 22:11:47.477129 [CA 5] Center 34 (4~64) winsize 61
3087 22:11:47.477235
3088 22:11:47.480761 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3089 22:11:47.480843
3090 22:11:47.483810 [CATrainingPosCal] consider 2 rank data
3091 22:11:47.487263 u2DelayCellTimex100 = 270/100 ps
3092 22:11:47.490416 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 22:11:47.494014 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3094 22:11:47.500856 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3095 22:11:47.503912 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 22:11:47.507568 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 22:11:47.510724 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3098 22:11:47.510831
3099 22:11:47.513992 CA PerBit enable=1, Macro0, CA PI delay=33
3100 22:11:47.514074
3101 22:11:47.517765 [CBTSetCACLKResult] CA Dly = 33
3102 22:11:47.517859 CS Dly: 8 (0~40)
3103 22:11:47.517923
3104 22:11:47.520825 ----->DramcWriteLeveling(PI) begin...
3105 22:11:47.520901 ==
3106 22:11:47.523977 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 22:11:47.531002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 22:11:47.531109 ==
3109 22:11:47.534367 Write leveling (Byte 0): 24 => 24
3110 22:11:47.537444 Write leveling (Byte 1): 28 => 28
3111 22:11:47.540339 DramcWriteLeveling(PI) end<-----
3112 22:11:47.540457
3113 22:11:47.540550 ==
3114 22:11:47.544119 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 22:11:47.547464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 22:11:47.547564 ==
3117 22:11:47.550580 [Gating] SW mode calibration
3118 22:11:47.557303 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3119 22:11:47.560408 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3120 22:11:47.567162 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3121 22:11:47.570306 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 22:11:47.573680 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 22:11:47.580389 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 22:11:47.583616 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 22:11:47.587406 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 22:11:47.594203 0 15 24 | B1->B0 | 3333 3131 | 1 0 | (1 0) (0 0)
3127 22:11:47.597173 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3128 22:11:47.600738 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 22:11:47.607005 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 22:11:47.610873 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 22:11:47.614082 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 22:11:47.620448 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 22:11:47.623890 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 22:11:47.627466 1 0 24 | B1->B0 | 3737 4545 | 0 0 | (1 1) (0 0)
3135 22:11:47.633941 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 22:11:47.637303 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 22:11:47.640907 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 22:11:47.643999 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 22:11:47.651045 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 22:11:47.654169 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 22:11:47.657829 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 22:11:47.663841 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 22:11:47.667233 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3144 22:11:47.670536 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 22:11:47.677820 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 22:11:47.681231 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 22:11:47.684065 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 22:11:47.690958 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 22:11:47.694182 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 22:11:47.697407 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 22:11:47.704112 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 22:11:47.707473 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 22:11:47.710958 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 22:11:47.717592 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 22:11:47.721019 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 22:11:47.724153 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 22:11:47.727540 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 22:11:47.734128 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3159 22:11:47.737816 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3160 22:11:47.740989 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 22:11:47.744158 Total UI for P1: 0, mck2ui 16
3162 22:11:47.747841 best dqsien dly found for B0: ( 1, 3, 26)
3163 22:11:47.750994 Total UI for P1: 0, mck2ui 16
3164 22:11:47.754630 best dqsien dly found for B1: ( 1, 3, 26)
3165 22:11:47.757842 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3166 22:11:47.761340 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3167 22:11:47.761423
3168 22:11:47.767647 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3169 22:11:47.770859 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3170 22:11:47.770966 [Gating] SW calibration Done
3171 22:11:47.774211 ==
3172 22:11:47.777504 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 22:11:47.781000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 22:11:47.781082 ==
3175 22:11:47.781153 RX Vref Scan: 0
3176 22:11:47.781217
3177 22:11:47.784142 RX Vref 0 -> 0, step: 1
3178 22:11:47.784222
3179 22:11:47.788196 RX Delay -40 -> 252, step: 8
3180 22:11:47.791265 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3181 22:11:47.794450 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3182 22:11:47.797705 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3183 22:11:47.804751 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3184 22:11:47.807651 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3185 22:11:47.811067 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3186 22:11:47.814353 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3187 22:11:47.817621 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3188 22:11:47.824176 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3189 22:11:47.827900 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3190 22:11:47.830825 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3191 22:11:47.834120 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3192 22:11:47.837800 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3193 22:11:47.844419 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3194 22:11:47.847692 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3195 22:11:47.851079 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3196 22:11:47.851184 ==
3197 22:11:47.854433 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 22:11:47.857450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 22:11:47.857583 ==
3200 22:11:47.861162 DQS Delay:
3201 22:11:47.861294 DQS0 = 0, DQS1 = 0
3202 22:11:47.864487 DQM Delay:
3203 22:11:47.864598 DQM0 = 120, DQM1 = 116
3204 22:11:47.867917 DQ Delay:
3205 22:11:47.870956 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3206 22:11:47.874106 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3207 22:11:47.877401 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3208 22:11:47.880995 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3209 22:11:47.881072
3210 22:11:47.881139
3211 22:11:47.881199 ==
3212 22:11:47.883989 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 22:11:47.887407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 22:11:47.887516 ==
3215 22:11:47.887617
3216 22:11:47.887712
3217 22:11:47.890737 TX Vref Scan disable
3218 22:11:47.894095 == TX Byte 0 ==
3219 22:11:47.897293 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3220 22:11:47.901183 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3221 22:11:47.904389 == TX Byte 1 ==
3222 22:11:47.907481 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3223 22:11:47.910883 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3224 22:11:47.910967 ==
3225 22:11:47.914010 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 22:11:47.918021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 22:11:47.920859 ==
3228 22:11:47.931194 TX Vref=22, minBit 9, minWin=24, winSum=410
3229 22:11:47.934775 TX Vref=24, minBit 9, minWin=24, winSum=417
3230 22:11:47.937854 TX Vref=26, minBit 9, minWin=25, winSum=422
3231 22:11:47.941440 TX Vref=28, minBit 1, minWin=26, winSum=426
3232 22:11:47.944484 TX Vref=30, minBit 2, minWin=26, winSum=432
3233 22:11:47.948163 TX Vref=32, minBit 9, minWin=26, winSum=434
3234 22:11:47.954409 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3235 22:11:47.954498
3236 22:11:47.958119 Final TX Range 1 Vref 32
3237 22:11:47.958220
3238 22:11:47.958312 ==
3239 22:11:47.961553 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 22:11:47.964459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 22:11:47.964560 ==
3242 22:11:47.964667
3243 22:11:47.964756
3244 22:11:47.967797 TX Vref Scan disable
3245 22:11:47.971177 == TX Byte 0 ==
3246 22:11:47.974552 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3247 22:11:47.978095 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3248 22:11:47.981489 == TX Byte 1 ==
3249 22:11:47.984842 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3250 22:11:47.988079 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3251 22:11:47.988163
3252 22:11:47.991779 [DATLAT]
3253 22:11:47.991855 Freq=1200, CH1 RK0
3254 22:11:47.991958
3255 22:11:47.994706 DATLAT Default: 0xd
3256 22:11:47.994781 0, 0xFFFF, sum = 0
3257 22:11:47.998075 1, 0xFFFF, sum = 0
3258 22:11:47.998182 2, 0xFFFF, sum = 0
3259 22:11:48.001179 3, 0xFFFF, sum = 0
3260 22:11:48.001289 4, 0xFFFF, sum = 0
3261 22:11:48.004473 5, 0xFFFF, sum = 0
3262 22:11:48.004603 6, 0xFFFF, sum = 0
3263 22:11:48.007740 7, 0xFFFF, sum = 0
3264 22:11:48.007820 8, 0xFFFF, sum = 0
3265 22:11:48.011434 9, 0xFFFF, sum = 0
3266 22:11:48.014798 10, 0xFFFF, sum = 0
3267 22:11:48.014878 11, 0xFFFF, sum = 0
3268 22:11:48.017915 12, 0x0, sum = 1
3269 22:11:48.017996 13, 0x0, sum = 2
3270 22:11:48.018061 14, 0x0, sum = 3
3271 22:11:48.020992 15, 0x0, sum = 4
3272 22:11:48.021076 best_step = 13
3273 22:11:48.021174
3274 22:11:48.021261 ==
3275 22:11:48.024447 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 22:11:48.031638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 22:11:48.031717 ==
3278 22:11:48.031785 RX Vref Scan: 1
3279 22:11:48.031846
3280 22:11:48.034846 Set Vref Range= 32 -> 127
3281 22:11:48.034919
3282 22:11:48.038018 RX Vref 32 -> 127, step: 1
3283 22:11:48.038098
3284 22:11:48.038161 RX Delay -5 -> 252, step: 4
3285 22:11:48.038222
3286 22:11:48.041424 Set Vref, RX VrefLevel [Byte0]: 32
3287 22:11:48.045070 [Byte1]: 32
3288 22:11:48.049033
3289 22:11:48.049108 Set Vref, RX VrefLevel [Byte0]: 33
3290 22:11:48.052551 [Byte1]: 33
3291 22:11:48.057313
3292 22:11:48.057391 Set Vref, RX VrefLevel [Byte0]: 34
3293 22:11:48.060486 [Byte1]: 34
3294 22:11:48.065406
3295 22:11:48.065514 Set Vref, RX VrefLevel [Byte0]: 35
3296 22:11:48.068153 [Byte1]: 35
3297 22:11:48.072650
3298 22:11:48.072724 Set Vref, RX VrefLevel [Byte0]: 36
3299 22:11:48.076184 [Byte1]: 36
3300 22:11:48.080638
3301 22:11:48.080770 Set Vref, RX VrefLevel [Byte0]: 37
3302 22:11:48.083908 [Byte1]: 37
3303 22:11:48.088447
3304 22:11:48.088528 Set Vref, RX VrefLevel [Byte0]: 38
3305 22:11:48.092182 [Byte1]: 38
3306 22:11:48.096333
3307 22:11:48.096434 Set Vref, RX VrefLevel [Byte0]: 39
3308 22:11:48.099917 [Byte1]: 39
3309 22:11:48.104138
3310 22:11:48.104242 Set Vref, RX VrefLevel [Byte0]: 40
3311 22:11:48.107727 [Byte1]: 40
3312 22:11:48.112086
3313 22:11:48.112219 Set Vref, RX VrefLevel [Byte0]: 41
3314 22:11:48.115322 [Byte1]: 41
3315 22:11:48.120230
3316 22:11:48.120340 Set Vref, RX VrefLevel [Byte0]: 42
3317 22:11:48.123180 [Byte1]: 42
3318 22:11:48.127371
3319 22:11:48.131074 Set Vref, RX VrefLevel [Byte0]: 43
3320 22:11:48.131162 [Byte1]: 43
3321 22:11:48.135487
3322 22:11:48.135561 Set Vref, RX VrefLevel [Byte0]: 44
3323 22:11:48.138654 [Byte1]: 44
3324 22:11:48.143803
3325 22:11:48.143899 Set Vref, RX VrefLevel [Byte0]: 45
3326 22:11:48.147144 [Byte1]: 45
3327 22:11:48.151451
3328 22:11:48.151530 Set Vref, RX VrefLevel [Byte0]: 46
3329 22:11:48.154756 [Byte1]: 46
3330 22:11:48.159142
3331 22:11:48.159273 Set Vref, RX VrefLevel [Byte0]: 47
3332 22:11:48.162524 [Byte1]: 47
3333 22:11:48.167227
3334 22:11:48.167345 Set Vref, RX VrefLevel [Byte0]: 48
3335 22:11:48.170336 [Byte1]: 48
3336 22:11:48.175184
3337 22:11:48.175315 Set Vref, RX VrefLevel [Byte0]: 49
3338 22:11:48.178430 [Byte1]: 49
3339 22:11:48.182503
3340 22:11:48.182633 Set Vref, RX VrefLevel [Byte0]: 50
3341 22:11:48.185992 [Byte1]: 50
3342 22:11:48.190605
3343 22:11:48.190738 Set Vref, RX VrefLevel [Byte0]: 51
3344 22:11:48.194334 [Byte1]: 51
3345 22:11:48.198808
3346 22:11:48.198932 Set Vref, RX VrefLevel [Byte0]: 52
3347 22:11:48.201987 [Byte1]: 52
3348 22:11:48.206744
3349 22:11:48.206868 Set Vref, RX VrefLevel [Byte0]: 53
3350 22:11:48.209403 [Byte1]: 53
3351 22:11:48.214024
3352 22:11:48.214148 Set Vref, RX VrefLevel [Byte0]: 54
3353 22:11:48.217366 [Byte1]: 54
3354 22:11:48.221920
3355 22:11:48.222052 Set Vref, RX VrefLevel [Byte0]: 55
3356 22:11:48.225114 [Byte1]: 55
3357 22:11:48.229915
3358 22:11:48.230042 Set Vref, RX VrefLevel [Byte0]: 56
3359 22:11:48.233028 [Byte1]: 56
3360 22:11:48.237614
3361 22:11:48.237737 Set Vref, RX VrefLevel [Byte0]: 57
3362 22:11:48.240857 [Byte1]: 57
3363 22:11:48.245624
3364 22:11:48.245743 Set Vref, RX VrefLevel [Byte0]: 58
3365 22:11:48.248646 [Byte1]: 58
3366 22:11:48.253148
3367 22:11:48.253281 Set Vref, RX VrefLevel [Byte0]: 59
3368 22:11:48.256957 [Byte1]: 59
3369 22:11:48.260960
3370 22:11:48.261089 Set Vref, RX VrefLevel [Byte0]: 60
3371 22:11:48.264919 [Byte1]: 60
3372 22:11:48.269145
3373 22:11:48.269275 Set Vref, RX VrefLevel [Byte0]: 61
3374 22:11:48.272286 [Byte1]: 61
3375 22:11:48.277127
3376 22:11:48.277248 Set Vref, RX VrefLevel [Byte0]: 62
3377 22:11:48.280019 [Byte1]: 62
3378 22:11:48.284641
3379 22:11:48.284772 Set Vref, RX VrefLevel [Byte0]: 63
3380 22:11:48.288299 [Byte1]: 63
3381 22:11:48.292368
3382 22:11:48.292490 Set Vref, RX VrefLevel [Byte0]: 64
3383 22:11:48.295763 [Byte1]: 64
3384 22:11:48.300933
3385 22:11:48.301063 Set Vref, RX VrefLevel [Byte0]: 65
3386 22:11:48.303946 [Byte1]: 65
3387 22:11:48.308064
3388 22:11:48.308195 Set Vref, RX VrefLevel [Byte0]: 66
3389 22:11:48.311932 [Byte1]: 66
3390 22:11:48.316177
3391 22:11:48.316305 Set Vref, RX VrefLevel [Byte0]: 67
3392 22:11:48.319810 [Byte1]: 67
3393 22:11:48.323929
3394 22:11:48.324060 Set Vref, RX VrefLevel [Byte0]: 68
3395 22:11:48.327149 [Byte1]: 68
3396 22:11:48.332064
3397 22:11:48.332188 Set Vref, RX VrefLevel [Byte0]: 69
3398 22:11:48.335162 [Byte1]: 69
3399 22:11:48.339891
3400 22:11:48.340027 Set Vref, RX VrefLevel [Byte0]: 70
3401 22:11:48.342842 [Byte1]: 70
3402 22:11:48.347631
3403 22:11:48.347756 Final RX Vref Byte 0 = 50 to rank0
3404 22:11:48.350852 Final RX Vref Byte 1 = 52 to rank0
3405 22:11:48.354292 Final RX Vref Byte 0 = 50 to rank1
3406 22:11:48.357628 Final RX Vref Byte 1 = 52 to rank1==
3407 22:11:48.361284 Dram Type= 6, Freq= 0, CH_1, rank 0
3408 22:11:48.364482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3409 22:11:48.367930 ==
3410 22:11:48.368064 DQS Delay:
3411 22:11:48.368174 DQS0 = 0, DQS1 = 0
3412 22:11:48.371356 DQM Delay:
3413 22:11:48.371480 DQM0 = 119, DQM1 = 117
3414 22:11:48.374455 DQ Delay:
3415 22:11:48.377876 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =114
3416 22:11:48.381149 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3417 22:11:48.384388 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3418 22:11:48.387625 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3419 22:11:48.387740
3420 22:11:48.387829
3421 22:11:48.394493 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3422 22:11:48.398000 CH1 RK0: MR19=404, MR18=417
3423 22:11:48.404018 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3424 22:11:48.404113
3425 22:11:48.407695 ----->DramcWriteLeveling(PI) begin...
3426 22:11:48.407816 ==
3427 22:11:48.410782 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 22:11:48.414483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 22:11:48.414566 ==
3430 22:11:48.417587 Write leveling (Byte 0): 25 => 25
3431 22:11:48.421147 Write leveling (Byte 1): 27 => 27
3432 22:11:48.424642 DramcWriteLeveling(PI) end<-----
3433 22:11:48.424744
3434 22:11:48.424832 ==
3435 22:11:48.427915 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 22:11:48.434644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 22:11:48.434815 ==
3438 22:11:48.434928 [Gating] SW mode calibration
3439 22:11:48.444525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3440 22:11:48.447838 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3441 22:11:48.451099 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 22:11:48.458110 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 22:11:48.461399 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 22:11:48.464333 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 22:11:48.471514 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 22:11:48.474950 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 22:11:48.478091 0 15 24 | B1->B0 | 2929 3434 | 0 1 | (1 0) (1 1)
3448 22:11:48.484361 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)
3449 22:11:48.488165 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 22:11:48.491520 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 22:11:48.494675 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 22:11:48.501380 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 22:11:48.504543 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 22:11:48.508081 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3455 22:11:48.514883 1 0 24 | B1->B0 | 4646 3232 | 0 0 | (0 0) (0 0)
3456 22:11:48.517857 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 22:11:48.521422 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 22:11:48.527870 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 22:11:48.531529 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 22:11:48.534479 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 22:11:48.541239 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 22:11:48.545044 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3463 22:11:48.547749 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3464 22:11:48.554599 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3465 22:11:48.558180 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 22:11:48.561414 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 22:11:48.567901 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 22:11:48.571370 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 22:11:48.574366 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 22:11:48.581458 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 22:11:48.584546 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 22:11:48.587634 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 22:11:48.594621 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 22:11:48.597901 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 22:11:48.601277 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 22:11:48.607879 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 22:11:48.611036 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 22:11:48.614592 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3479 22:11:48.617793 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3480 22:11:48.625069 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3481 22:11:48.628076 Total UI for P1: 0, mck2ui 16
3482 22:11:48.631193 best dqsien dly found for B1: ( 1, 3, 22)
3483 22:11:48.634532 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3484 22:11:48.638197 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 22:11:48.641610 Total UI for P1: 0, mck2ui 16
3486 22:11:48.644855 best dqsien dly found for B0: ( 1, 3, 28)
3487 22:11:48.648241 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3488 22:11:48.651330 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3489 22:11:48.651410
3490 22:11:48.658145 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3491 22:11:48.661295 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3492 22:11:48.661373 [Gating] SW calibration Done
3493 22:11:48.664827 ==
3494 22:11:48.664905 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 22:11:48.671403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 22:11:48.671483 ==
3497 22:11:48.671553 RX Vref Scan: 0
3498 22:11:48.671624
3499 22:11:48.674772 RX Vref 0 -> 0, step: 1
3500 22:11:48.674844
3501 22:11:48.677954 RX Delay -40 -> 252, step: 8
3502 22:11:48.681460 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3503 22:11:48.684709 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3504 22:11:48.690941 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3505 22:11:48.694162 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3506 22:11:48.697554 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3507 22:11:48.701162 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3508 22:11:48.704529 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3509 22:11:48.707666 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3510 22:11:48.714384 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3511 22:11:48.717806 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3512 22:11:48.721344 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3513 22:11:48.724643 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3514 22:11:48.728045 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3515 22:11:48.734368 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3516 22:11:48.737631 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3517 22:11:48.740847 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3518 22:11:48.740974 ==
3519 22:11:48.744162 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 22:11:48.747816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 22:11:48.750996 ==
3522 22:11:48.751115 DQS Delay:
3523 22:11:48.751240 DQS0 = 0, DQS1 = 0
3524 22:11:48.754231 DQM Delay:
3525 22:11:48.754347 DQM0 = 121, DQM1 = 118
3526 22:11:48.757811 DQ Delay:
3527 22:11:48.760915 DQ0 =127, DQ1 =115, DQ2 =111, DQ3 =115
3528 22:11:48.764661 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3529 22:11:48.767828 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3530 22:11:48.771262 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3531 22:11:48.771380
3532 22:11:48.771501
3533 22:11:48.771614 ==
3534 22:11:48.774314 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 22:11:48.778042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 22:11:48.778172 ==
3537 22:11:48.778289
3538 22:11:48.778406
3539 22:11:48.781080 TX Vref Scan disable
3540 22:11:48.784696 == TX Byte 0 ==
3541 22:11:48.787924 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3542 22:11:48.791036 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3543 22:11:48.794268 == TX Byte 1 ==
3544 22:11:48.797588 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3545 22:11:48.800845 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3546 22:11:48.800967 ==
3547 22:11:48.804094 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 22:11:48.807808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 22:11:48.810910 ==
3550 22:11:48.820975 TX Vref=22, minBit 13, minWin=25, winSum=418
3551 22:11:48.824497 TX Vref=24, minBit 10, minWin=25, winSum=423
3552 22:11:48.828176 TX Vref=26, minBit 10, minWin=25, winSum=426
3553 22:11:48.831376 TX Vref=28, minBit 2, minWin=26, winSum=432
3554 22:11:48.834604 TX Vref=30, minBit 9, minWin=26, winSum=435
3555 22:11:48.841468 TX Vref=32, minBit 9, minWin=26, winSum=434
3556 22:11:48.844655 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3557 22:11:48.844794
3558 22:11:48.847769 Final TX Range 1 Vref 30
3559 22:11:48.847895
3560 22:11:48.848013 ==
3561 22:11:48.850950 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 22:11:48.854280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 22:11:48.854410 ==
3564 22:11:48.858015
3565 22:11:48.858141
3566 22:11:48.858253 TX Vref Scan disable
3567 22:11:48.861214 == TX Byte 0 ==
3568 22:11:48.864345 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3569 22:11:48.870895 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3570 22:11:48.871024 == TX Byte 1 ==
3571 22:11:48.874816 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3572 22:11:48.877589 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3573 22:11:48.880992
3574 22:11:48.881119 [DATLAT]
3575 22:11:48.881233 Freq=1200, CH1 RK1
3576 22:11:48.881418
3577 22:11:48.884287 DATLAT Default: 0xd
3578 22:11:48.884424 0, 0xFFFF, sum = 0
3579 22:11:48.887428 1, 0xFFFF, sum = 0
3580 22:11:48.887582 2, 0xFFFF, sum = 0
3581 22:11:48.891173 3, 0xFFFF, sum = 0
3582 22:11:48.894227 4, 0xFFFF, sum = 0
3583 22:11:48.894337 5, 0xFFFF, sum = 0
3584 22:11:48.897685 6, 0xFFFF, sum = 0
3585 22:11:48.897813 7, 0xFFFF, sum = 0
3586 22:11:48.900878 8, 0xFFFF, sum = 0
3587 22:11:48.901018 9, 0xFFFF, sum = 0
3588 22:11:48.904183 10, 0xFFFF, sum = 0
3589 22:11:48.904354 11, 0xFFFF, sum = 0
3590 22:11:48.907490 12, 0x0, sum = 1
3591 22:11:48.907654 13, 0x0, sum = 2
3592 22:11:48.910698 14, 0x0, sum = 3
3593 22:11:48.910839 15, 0x0, sum = 4
3594 22:11:48.910957 best_step = 13
3595 22:11:48.914224
3596 22:11:48.914345 ==
3597 22:11:48.917724 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 22:11:48.920860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 22:11:48.920974 ==
3600 22:11:48.921070 RX Vref Scan: 0
3601 22:11:48.921136
3602 22:11:48.924423 RX Vref 0 -> 0, step: 1
3603 22:11:48.924538
3604 22:11:48.927365 RX Delay -5 -> 252, step: 4
3605 22:11:48.931188 iDelay=195, Bit 0, Center 120 (59 ~ 182) 124
3606 22:11:48.937737 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3607 22:11:48.940643 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3608 22:11:48.944114 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3609 22:11:48.947814 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3610 22:11:48.951100 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3611 22:11:48.954255 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3612 22:11:48.961003 iDelay=195, Bit 7, Center 118 (55 ~ 182) 128
3613 22:11:48.964459 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3614 22:11:48.967456 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3615 22:11:48.970731 iDelay=195, Bit 10, Center 118 (55 ~ 182) 128
3616 22:11:48.977578 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3617 22:11:48.980560 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3618 22:11:48.984025 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3619 22:11:48.987457 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3620 22:11:48.990846 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3621 22:11:48.990955 ==
3622 22:11:48.994147 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 22:11:49.000664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 22:11:49.000750 ==
3625 22:11:49.000817 DQS Delay:
3626 22:11:49.004174 DQS0 = 0, DQS1 = 0
3627 22:11:49.004279 DQM Delay:
3628 22:11:49.007400 DQM0 = 119, DQM1 = 118
3629 22:11:49.007500 DQ Delay:
3630 22:11:49.010897 DQ0 =120, DQ1 =116, DQ2 =110, DQ3 =116
3631 22:11:49.014118 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =118
3632 22:11:49.017322 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3633 22:11:49.020952 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =128
3634 22:11:49.021079
3635 22:11:49.021189
3636 22:11:49.030733 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3637 22:11:49.030862 CH1 RK1: MR19=403, MR18=10ED
3638 22:11:49.037556 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3639 22:11:49.040776 [RxdqsGatingPostProcess] freq 1200
3640 22:11:49.047373 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3641 22:11:49.050817 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 22:11:49.054111 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 22:11:49.057311 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 22:11:49.060520 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 22:11:49.063636 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 22:11:49.067467 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 22:11:49.070544 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 22:11:49.070645 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 22:11:49.073906 Pre-setting of DQS Precalculation
3650 22:11:49.081017 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3651 22:11:49.087301 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3652 22:11:49.093464 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3653 22:11:49.093549
3654 22:11:49.093615
3655 22:11:49.096838 [Calibration Summary] 2400 Mbps
3656 22:11:49.100013 CH 0, Rank 0
3657 22:11:49.100096 SW Impedance : PASS
3658 22:11:49.103555 DUTY Scan : NO K
3659 22:11:49.106817 ZQ Calibration : PASS
3660 22:11:49.106902 Jitter Meter : NO K
3661 22:11:49.110302 CBT Training : PASS
3662 22:11:49.113314 Write leveling : PASS
3663 22:11:49.113399 RX DQS gating : PASS
3664 22:11:49.117004 RX DQ/DQS(RDDQC) : PASS
3665 22:11:49.117088 TX DQ/DQS : PASS
3666 22:11:49.120331 RX DATLAT : PASS
3667 22:11:49.123573 RX DQ/DQS(Engine): PASS
3668 22:11:49.123660 TX OE : NO K
3669 22:11:49.126982 All Pass.
3670 22:11:49.127058
3671 22:11:49.127121 CH 0, Rank 1
3672 22:11:49.130365 SW Impedance : PASS
3673 22:11:49.130440 DUTY Scan : NO K
3674 22:11:49.133342 ZQ Calibration : PASS
3675 22:11:49.136514 Jitter Meter : NO K
3676 22:11:49.136598 CBT Training : PASS
3677 22:11:49.140266 Write leveling : PASS
3678 22:11:49.143440 RX DQS gating : PASS
3679 22:11:49.143526 RX DQ/DQS(RDDQC) : PASS
3680 22:11:49.146925 TX DQ/DQS : PASS
3681 22:11:49.150291 RX DATLAT : PASS
3682 22:11:49.150375 RX DQ/DQS(Engine): PASS
3683 22:11:49.153586 TX OE : NO K
3684 22:11:49.153670 All Pass.
3685 22:11:49.153736
3686 22:11:49.156797 CH 1, Rank 0
3687 22:11:49.156886 SW Impedance : PASS
3688 22:11:49.160354 DUTY Scan : NO K
3689 22:11:49.163495 ZQ Calibration : PASS
3690 22:11:49.163612 Jitter Meter : NO K
3691 22:11:49.166666 CBT Training : PASS
3692 22:11:49.166749 Write leveling : PASS
3693 22:11:49.170301 RX DQS gating : PASS
3694 22:11:49.173667 RX DQ/DQS(RDDQC) : PASS
3695 22:11:49.173794 TX DQ/DQS : PASS
3696 22:11:49.176820 RX DATLAT : PASS
3697 22:11:49.180005 RX DQ/DQS(Engine): PASS
3698 22:11:49.180132 TX OE : NO K
3699 22:11:49.183598 All Pass.
3700 22:11:49.183704
3701 22:11:49.183797 CH 1, Rank 1
3702 22:11:49.186958 SW Impedance : PASS
3703 22:11:49.187060 DUTY Scan : NO K
3704 22:11:49.190235 ZQ Calibration : PASS
3705 22:11:49.193618 Jitter Meter : NO K
3706 22:11:49.193713 CBT Training : PASS
3707 22:11:49.196880 Write leveling : PASS
3708 22:11:49.199883 RX DQS gating : PASS
3709 22:11:49.199969 RX DQ/DQS(RDDQC) : PASS
3710 22:11:49.203240 TX DQ/DQS : PASS
3711 22:11:49.206815 RX DATLAT : PASS
3712 22:11:49.206900 RX DQ/DQS(Engine): PASS
3713 22:11:49.210325 TX OE : NO K
3714 22:11:49.210410 All Pass.
3715 22:11:49.210475
3716 22:11:49.213191 DramC Write-DBI off
3717 22:11:49.216626 PER_BANK_REFRESH: Hybrid Mode
3718 22:11:49.216710 TX_TRACKING: ON
3719 22:11:49.226742 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3720 22:11:49.230067 [FAST_K] Save calibration result to emmc
3721 22:11:49.233044 dramc_set_vcore_voltage set vcore to 650000
3722 22:11:49.236774 Read voltage for 600, 5
3723 22:11:49.236884 Vio18 = 0
3724 22:11:49.236977 Vcore = 650000
3725 22:11:49.237070 Vdram = 0
3726 22:11:49.240155 Vddq = 0
3727 22:11:49.240232 Vmddr = 0
3728 22:11:49.246422 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3729 22:11:49.249802 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3730 22:11:49.253178 MEM_TYPE=3, freq_sel=19
3731 22:11:49.256480 sv_algorithm_assistance_LP4_1600
3732 22:11:49.259944 ============ PULL DRAM RESETB DOWN ============
3733 22:11:49.263289 ========== PULL DRAM RESETB DOWN end =========
3734 22:11:49.269915 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3735 22:11:49.273185 ===================================
3736 22:11:49.273299 LPDDR4 DRAM CONFIGURATION
3737 22:11:49.276488 ===================================
3738 22:11:49.279761 EX_ROW_EN[0] = 0x0
3739 22:11:49.283144 EX_ROW_EN[1] = 0x0
3740 22:11:49.283228 LP4Y_EN = 0x0
3741 22:11:49.286265 WORK_FSP = 0x0
3742 22:11:49.286391 WL = 0x2
3743 22:11:49.289442 RL = 0x2
3744 22:11:49.289551 BL = 0x2
3745 22:11:49.292805 RPST = 0x0
3746 22:11:49.292916 RD_PRE = 0x0
3747 22:11:49.296083 WR_PRE = 0x1
3748 22:11:49.296167 WR_PST = 0x0
3749 22:11:49.299695 DBI_WR = 0x0
3750 22:11:49.299779 DBI_RD = 0x0
3751 22:11:49.303031 OTF = 0x1
3752 22:11:49.306279 ===================================
3753 22:11:49.309609 ===================================
3754 22:11:49.309693 ANA top config
3755 22:11:49.313125 ===================================
3756 22:11:49.316302 DLL_ASYNC_EN = 0
3757 22:11:49.319757 ALL_SLAVE_EN = 1
3758 22:11:49.319882 NEW_RANK_MODE = 1
3759 22:11:49.322990 DLL_IDLE_MODE = 1
3760 22:11:49.326167 LP45_APHY_COMB_EN = 1
3761 22:11:49.329272 TX_ODT_DIS = 1
3762 22:11:49.332663 NEW_8X_MODE = 1
3763 22:11:49.336335 ===================================
3764 22:11:49.339618 ===================================
3765 22:11:49.339744 data_rate = 1200
3766 22:11:49.342919 CKR = 1
3767 22:11:49.346208 DQ_P2S_RATIO = 8
3768 22:11:49.349464 ===================================
3769 22:11:49.352625 CA_P2S_RATIO = 8
3770 22:11:49.356051 DQ_CA_OPEN = 0
3771 22:11:49.359645 DQ_SEMI_OPEN = 0
3772 22:11:49.359771 CA_SEMI_OPEN = 0
3773 22:11:49.362593 CA_FULL_RATE = 0
3774 22:11:49.366022 DQ_CKDIV4_EN = 1
3775 22:11:49.369013 CA_CKDIV4_EN = 1
3776 22:11:49.372797 CA_PREDIV_EN = 0
3777 22:11:49.376004 PH8_DLY = 0
3778 22:11:49.376127 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3779 22:11:49.378935 DQ_AAMCK_DIV = 4
3780 22:11:49.382674 CA_AAMCK_DIV = 4
3781 22:11:49.385810 CA_ADMCK_DIV = 4
3782 22:11:49.389347 DQ_TRACK_CA_EN = 0
3783 22:11:49.392435 CA_PICK = 600
3784 22:11:49.395567 CA_MCKIO = 600
3785 22:11:49.395675 MCKIO_SEMI = 0
3786 22:11:49.398929 PLL_FREQ = 2288
3787 22:11:49.402713 DQ_UI_PI_RATIO = 32
3788 22:11:49.406100 CA_UI_PI_RATIO = 0
3789 22:11:49.409317 ===================================
3790 22:11:49.412511 ===================================
3791 22:11:49.415970 memory_type:LPDDR4
3792 22:11:49.416054 GP_NUM : 10
3793 22:11:49.419257 SRAM_EN : 1
3794 22:11:49.419340 MD32_EN : 0
3795 22:11:49.422541 ===================================
3796 22:11:49.425620 [ANA_INIT] >>>>>>>>>>>>>>
3797 22:11:49.428971 <<<<<< [CONFIGURE PHASE]: ANA_TX
3798 22:11:49.432484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3799 22:11:49.435809 ===================================
3800 22:11:49.438844 data_rate = 1200,PCW = 0X5800
3801 22:11:49.442447 ===================================
3802 22:11:49.445707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3803 22:11:49.452686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 22:11:49.456070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 22:11:49.462534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3806 22:11:49.465697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3807 22:11:49.469154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3808 22:11:49.469236 [ANA_INIT] flow start
3809 22:11:49.472443 [ANA_INIT] PLL >>>>>>>>
3810 22:11:49.475812 [ANA_INIT] PLL <<<<<<<<
3811 22:11:49.475897 [ANA_INIT] MIDPI >>>>>>>>
3812 22:11:49.479264 [ANA_INIT] MIDPI <<<<<<<<
3813 22:11:49.482477 [ANA_INIT] DLL >>>>>>>>
3814 22:11:49.482563 [ANA_INIT] flow end
3815 22:11:49.488868 ============ LP4 DIFF to SE enter ============
3816 22:11:49.492671 ============ LP4 DIFF to SE exit ============
3817 22:11:49.495835 [ANA_INIT] <<<<<<<<<<<<<
3818 22:11:49.499190 [Flow] Enable top DCM control >>>>>
3819 22:11:49.499277 [Flow] Enable top DCM control <<<<<
3820 22:11:49.502310 Enable DLL master slave shuffle
3821 22:11:49.508830 ==============================================================
3822 22:11:49.512703 Gating Mode config
3823 22:11:49.515691 ==============================================================
3824 22:11:49.518930 Config description:
3825 22:11:49.529226 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3826 22:11:49.535907 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3827 22:11:49.539194 SELPH_MODE 0: By rank 1: By Phase
3828 22:11:49.545489 ==============================================================
3829 22:11:49.548676 GAT_TRACK_EN = 1
3830 22:11:49.552102 RX_GATING_MODE = 2
3831 22:11:49.555290 RX_GATING_TRACK_MODE = 2
3832 22:11:49.555375 SELPH_MODE = 1
3833 22:11:49.559005 PICG_EARLY_EN = 1
3834 22:11:49.562395 VALID_LAT_VALUE = 1
3835 22:11:49.568870 ==============================================================
3836 22:11:49.572234 Enter into Gating configuration >>>>
3837 22:11:49.575360 Exit from Gating configuration <<<<
3838 22:11:49.578664 Enter into DVFS_PRE_config >>>>>
3839 22:11:49.588644 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3840 22:11:49.592135 Exit from DVFS_PRE_config <<<<<
3841 22:11:49.595135 Enter into PICG configuration >>>>
3842 22:11:49.598934 Exit from PICG configuration <<<<
3843 22:11:49.602330 [RX_INPUT] configuration >>>>>
3844 22:11:49.605447 [RX_INPUT] configuration <<<<<
3845 22:11:49.608743 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3846 22:11:49.615228 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3847 22:11:49.622094 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 22:11:49.628302 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 22:11:49.635040 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 22:11:49.638249 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 22:11:49.645071 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3852 22:11:49.648371 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3853 22:11:49.651770 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3854 22:11:49.654906 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3855 22:11:49.658209 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3856 22:11:49.664979 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 22:11:49.667959 ===================================
3858 22:11:49.671643 LPDDR4 DRAM CONFIGURATION
3859 22:11:49.675182 ===================================
3860 22:11:49.675269 EX_ROW_EN[0] = 0x0
3861 22:11:49.678228 EX_ROW_EN[1] = 0x0
3862 22:11:49.678316 LP4Y_EN = 0x0
3863 22:11:49.681411 WORK_FSP = 0x0
3864 22:11:49.681502 WL = 0x2
3865 22:11:49.685028 RL = 0x2
3866 22:11:49.685116 BL = 0x2
3867 22:11:49.688236 RPST = 0x0
3868 22:11:49.688347 RD_PRE = 0x0
3869 22:11:49.691294 WR_PRE = 0x1
3870 22:11:49.691378 WR_PST = 0x0
3871 22:11:49.694925 DBI_WR = 0x0
3872 22:11:49.695039 DBI_RD = 0x0
3873 22:11:49.698597 OTF = 0x1
3874 22:11:49.701442 ===================================
3875 22:11:49.704779 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3876 22:11:49.708217 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3877 22:11:49.714655 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 22:11:49.718305 ===================================
3879 22:11:49.718431 LPDDR4 DRAM CONFIGURATION
3880 22:11:49.721622 ===================================
3881 22:11:49.724776 EX_ROW_EN[0] = 0x10
3882 22:11:49.727827 EX_ROW_EN[1] = 0x0
3883 22:11:49.727932 LP4Y_EN = 0x0
3884 22:11:49.731488 WORK_FSP = 0x0
3885 22:11:49.731600 WL = 0x2
3886 22:11:49.734930 RL = 0x2
3887 22:11:49.735030 BL = 0x2
3888 22:11:49.738237 RPST = 0x0
3889 22:11:49.738323 RD_PRE = 0x0
3890 22:11:49.741428 WR_PRE = 0x1
3891 22:11:49.741512 WR_PST = 0x0
3892 22:11:49.744649 DBI_WR = 0x0
3893 22:11:49.744734 DBI_RD = 0x0
3894 22:11:49.748155 OTF = 0x1
3895 22:11:49.751142 ===================================
3896 22:11:49.757904 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3897 22:11:49.761229 nWR fixed to 30
3898 22:11:49.764447 [ModeRegInit_LP4] CH0 RK0
3899 22:11:49.764536 [ModeRegInit_LP4] CH0 RK1
3900 22:11:49.767969 [ModeRegInit_LP4] CH1 RK0
3901 22:11:49.771256 [ModeRegInit_LP4] CH1 RK1
3902 22:11:49.771352 match AC timing 17
3903 22:11:49.777850 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3904 22:11:49.780924 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3905 22:11:49.784342 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3906 22:11:49.790725 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3907 22:11:49.794222 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3908 22:11:49.794326 ==
3909 22:11:49.797653 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 22:11:49.801095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 22:11:49.801172 ==
3912 22:11:49.807821 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 22:11:49.814143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3914 22:11:49.817265 [CA 0] Center 35 (5~66) winsize 62
3915 22:11:49.820607 [CA 1] Center 35 (5~66) winsize 62
3916 22:11:49.823927 [CA 2] Center 33 (3~64) winsize 62
3917 22:11:49.827546 [CA 3] Center 33 (2~64) winsize 63
3918 22:11:49.830759 [CA 4] Center 33 (2~64) winsize 63
3919 22:11:49.834405 [CA 5] Center 32 (2~63) winsize 62
3920 22:11:49.834481
3921 22:11:49.837325 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3922 22:11:49.837400
3923 22:11:49.840546 [CATrainingPosCal] consider 1 rank data
3924 22:11:49.843790 u2DelayCellTimex100 = 270/100 ps
3925 22:11:49.847126 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3926 22:11:49.850998 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3927 22:11:49.854042 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3928 22:11:49.857236 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3929 22:11:49.860933 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3930 22:11:49.863727 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3931 22:11:49.867452
3932 22:11:49.870465 CA PerBit enable=1, Macro0, CA PI delay=32
3933 22:11:49.870543
3934 22:11:49.873922 [CBTSetCACLKResult] CA Dly = 32
3935 22:11:49.874000 CS Dly: 4 (0~35)
3936 22:11:49.874064 ==
3937 22:11:49.877357 Dram Type= 6, Freq= 0, CH_0, rank 1
3938 22:11:49.880511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 22:11:49.880590 ==
3940 22:11:49.887078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 22:11:49.894143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3942 22:11:49.897239 [CA 0] Center 35 (5~66) winsize 62
3943 22:11:49.900370 [CA 1] Center 35 (5~66) winsize 62
3944 22:11:49.903718 [CA 2] Center 34 (3~65) winsize 63
3945 22:11:49.907197 [CA 3] Center 34 (3~65) winsize 63
3946 22:11:49.910331 [CA 4] Center 33 (2~64) winsize 63
3947 22:11:49.913920 [CA 5] Center 32 (2~63) winsize 62
3948 22:11:49.914000
3949 22:11:49.916988 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3950 22:11:49.917086
3951 22:11:49.920282 [CATrainingPosCal] consider 2 rank data
3952 22:11:49.923842 u2DelayCellTimex100 = 270/100 ps
3953 22:11:49.927337 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3954 22:11:49.930690 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3955 22:11:49.933913 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3956 22:11:49.937031 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3957 22:11:49.940527 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3958 22:11:49.946723 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3959 22:11:49.946811
3960 22:11:49.950016 CA PerBit enable=1, Macro0, CA PI delay=32
3961 22:11:49.950097
3962 22:11:49.953641 [CBTSetCACLKResult] CA Dly = 32
3963 22:11:49.953715 CS Dly: 4 (0~36)
3964 22:11:49.953778
3965 22:11:49.956829 ----->DramcWriteLeveling(PI) begin...
3966 22:11:49.956938 ==
3967 22:11:49.960070 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 22:11:49.966591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 22:11:49.966699 ==
3970 22:11:49.969846 Write leveling (Byte 0): 32 => 32
3971 22:11:49.969947 Write leveling (Byte 1): 32 => 32
3972 22:11:49.973339 DramcWriteLeveling(PI) end<-----
3973 22:11:49.973444
3974 22:11:49.976813 ==
3975 22:11:49.980191 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 22:11:49.983239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 22:11:49.983328 ==
3978 22:11:49.986538 [Gating] SW mode calibration
3979 22:11:49.993194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3980 22:11:49.996265 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3981 22:11:50.003014 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 22:11:50.006689 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 22:11:50.009868 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 22:11:50.016385 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
3985 22:11:50.019480 0 9 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
3986 22:11:50.022792 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 22:11:50.029650 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 22:11:50.033199 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 22:11:50.036499 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 22:11:50.042940 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 22:11:50.046064 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3992 22:11:50.049643 0 10 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (1 1)
3993 22:11:50.056471 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
3994 22:11:50.059626 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 22:11:50.062608 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 22:11:50.069427 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 22:11:50.072869 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 22:11:50.076006 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 22:11:50.079653 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 22:11:50.086185 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4001 22:11:50.089302 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 22:11:50.092895 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 22:11:50.099154 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 22:11:50.102637 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 22:11:50.106300 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 22:11:50.112712 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 22:11:50.115876 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 22:11:50.119625 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 22:11:50.125929 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 22:11:50.129072 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 22:11:50.132372 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 22:11:50.139076 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 22:11:50.142388 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 22:11:50.145668 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:11:50.152606 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4016 22:11:50.155786 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4017 22:11:50.159046 Total UI for P1: 0, mck2ui 16
4018 22:11:50.162825 best dqsien dly found for B0: ( 0, 13, 8)
4019 22:11:50.165777 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 22:11:50.169426 Total UI for P1: 0, mck2ui 16
4021 22:11:50.172607 best dqsien dly found for B1: ( 0, 13, 14)
4022 22:11:50.175960 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4023 22:11:50.179517 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4024 22:11:50.179637
4025 22:11:50.182436 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4026 22:11:50.188907 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4027 22:11:50.188992 [Gating] SW calibration Done
4028 22:11:50.192757 ==
4029 22:11:50.192841 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 22:11:50.199249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 22:11:50.199359 ==
4032 22:11:50.199454 RX Vref Scan: 0
4033 22:11:50.199545
4034 22:11:50.202363 RX Vref 0 -> 0, step: 1
4035 22:11:50.202459
4036 22:11:50.205775 RX Delay -230 -> 252, step: 16
4037 22:11:50.209119 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4038 22:11:50.212597 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4039 22:11:50.219192 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4040 22:11:50.222552 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4041 22:11:50.225996 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4042 22:11:50.229023 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4043 22:11:50.232536 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4044 22:11:50.239597 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4045 22:11:50.242590 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4046 22:11:50.246116 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4047 22:11:50.249113 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4048 22:11:50.255854 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4049 22:11:50.259443 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4050 22:11:50.262644 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4051 22:11:50.265794 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4052 22:11:50.272253 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4053 22:11:50.272338 ==
4054 22:11:50.275916 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 22:11:50.279209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 22:11:50.279293 ==
4057 22:11:50.279360 DQS Delay:
4058 22:11:50.282609 DQS0 = 0, DQS1 = 0
4059 22:11:50.282693 DQM Delay:
4060 22:11:50.285693 DQM0 = 49, DQM1 = 44
4061 22:11:50.285780 DQ Delay:
4062 22:11:50.289313 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4063 22:11:50.292696 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4064 22:11:50.296157 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4065 22:11:50.299296 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4066 22:11:50.299380
4067 22:11:50.299446
4068 22:11:50.299506 ==
4069 22:11:50.302484 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 22:11:50.305809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 22:11:50.305893 ==
4072 22:11:50.305959
4073 22:11:50.306020
4074 22:11:50.308814 TX Vref Scan disable
4075 22:11:50.312628 == TX Byte 0 ==
4076 22:11:50.315612 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4077 22:11:50.318974 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4078 22:11:50.322173 == TX Byte 1 ==
4079 22:11:50.325500 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4080 22:11:50.328839 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4081 22:11:50.328923 ==
4082 22:11:50.332062 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 22:11:50.338866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 22:11:50.338952 ==
4085 22:11:50.339018
4086 22:11:50.339079
4087 22:11:50.339138 TX Vref Scan disable
4088 22:11:50.342959 == TX Byte 0 ==
4089 22:11:50.346185 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4090 22:11:50.349778 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4091 22:11:50.353231 == TX Byte 1 ==
4092 22:11:50.356134 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4093 22:11:50.363155 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4094 22:11:50.363240
4095 22:11:50.363306 [DATLAT]
4096 22:11:50.363367 Freq=600, CH0 RK0
4097 22:11:50.363430
4098 22:11:50.366156 DATLAT Default: 0x9
4099 22:11:50.366240 0, 0xFFFF, sum = 0
4100 22:11:50.369393 1, 0xFFFF, sum = 0
4101 22:11:50.369479 2, 0xFFFF, sum = 0
4102 22:11:50.373016 3, 0xFFFF, sum = 0
4103 22:11:50.376054 4, 0xFFFF, sum = 0
4104 22:11:50.376139 5, 0xFFFF, sum = 0
4105 22:11:50.379537 6, 0xFFFF, sum = 0
4106 22:11:50.379629 7, 0xFFFF, sum = 0
4107 22:11:50.382790 8, 0x0, sum = 1
4108 22:11:50.382876 9, 0x0, sum = 2
4109 22:11:50.382942 10, 0x0, sum = 3
4110 22:11:50.385969 11, 0x0, sum = 4
4111 22:11:50.386090 best_step = 9
4112 22:11:50.386187
4113 22:11:50.386278 ==
4114 22:11:50.389752 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 22:11:50.395914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 22:11:50.396025 ==
4117 22:11:50.396129 RX Vref Scan: 1
4118 22:11:50.396223
4119 22:11:50.399351 RX Vref 0 -> 0, step: 1
4120 22:11:50.399450
4121 22:11:50.403261 RX Delay -179 -> 252, step: 8
4122 22:11:50.403369
4123 22:11:50.406297 Set Vref, RX VrefLevel [Byte0]: 54
4124 22:11:50.409572 [Byte1]: 53
4125 22:11:50.409676
4126 22:11:50.412997 Final RX Vref Byte 0 = 54 to rank0
4127 22:11:50.416092 Final RX Vref Byte 1 = 53 to rank0
4128 22:11:50.419867 Final RX Vref Byte 0 = 54 to rank1
4129 22:11:50.423042 Final RX Vref Byte 1 = 53 to rank1==
4130 22:11:50.426207 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 22:11:50.429584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 22:11:50.429714 ==
4133 22:11:50.432745 DQS Delay:
4134 22:11:50.432871 DQS0 = 0, DQS1 = 0
4135 22:11:50.432986 DQM Delay:
4136 22:11:50.436173 DQM0 = 53, DQM1 = 45
4137 22:11:50.436299 DQ Delay:
4138 22:11:50.439377 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4139 22:11:50.442552 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4140 22:11:50.446081 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4141 22:11:50.449142 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4142 22:11:50.449226
4143 22:11:50.449302
4144 22:11:50.459296 [DQSOSCAuto] RK0, (LSB)MR18= 0x7568, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 387 ps
4145 22:11:50.459430 CH0 RK0: MR19=808, MR18=7568
4146 22:11:50.465795 CH0_RK0: MR19=0x808, MR18=0x7568, DQSOSC=387, MR23=63, INC=175, DEC=116
4147 22:11:50.465923
4148 22:11:50.469519 ----->DramcWriteLeveling(PI) begin...
4149 22:11:50.472965 ==
4150 22:11:50.476184 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 22:11:50.479080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 22:11:50.479209 ==
4153 22:11:50.482618 Write leveling (Byte 0): 34 => 34
4154 22:11:50.485956 Write leveling (Byte 1): 33 => 33
4155 22:11:50.489237 DramcWriteLeveling(PI) end<-----
4156 22:11:50.489359
4157 22:11:50.489489 ==
4158 22:11:50.492806 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 22:11:50.495951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 22:11:50.496076 ==
4161 22:11:50.499323 [Gating] SW mode calibration
4162 22:11:50.506253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4163 22:11:50.509029 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4164 22:11:50.515915 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 22:11:50.519228 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 22:11:50.522854 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4167 22:11:50.529490 0 9 12 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 1)
4168 22:11:50.532670 0 9 16 | B1->B0 | 2e2e 2d2d | 1 0 | (1 0) (1 1)
4169 22:11:50.535796 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 22:11:50.542682 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 22:11:50.545651 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 22:11:50.549257 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 22:11:50.556052 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 22:11:50.559170 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 22:11:50.562553 0 10 12 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
4176 22:11:50.569294 0 10 16 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
4177 22:11:50.572361 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 22:11:50.576297 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 22:11:50.582533 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 22:11:50.586089 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 22:11:50.589042 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 22:11:50.595616 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 22:11:50.599226 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4184 22:11:50.602551 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4185 22:11:50.609583 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 22:11:50.612190 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 22:11:50.616130 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 22:11:50.619394 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 22:11:50.625588 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 22:11:50.629378 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 22:11:50.632687 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 22:11:50.639164 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 22:11:50.642254 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 22:11:50.645422 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 22:11:50.652078 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 22:11:50.655766 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 22:11:50.658956 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 22:11:50.665642 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 22:11:50.669018 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 22:11:50.672115 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 22:11:50.675935 Total UI for P1: 0, mck2ui 16
4202 22:11:50.679071 best dqsien dly found for B0: ( 0, 13, 14)
4203 22:11:50.682094 Total UI for P1: 0, mck2ui 16
4204 22:11:50.685599 best dqsien dly found for B1: ( 0, 13, 14)
4205 22:11:50.689261 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4206 22:11:50.692286 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4207 22:11:50.692369
4208 22:11:50.698731 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4209 22:11:50.702220 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4210 22:11:50.705147 [Gating] SW calibration Done
4211 22:11:50.705230 ==
4212 22:11:50.708698 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 22:11:50.711993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 22:11:50.712123 ==
4215 22:11:50.712239 RX Vref Scan: 0
4216 22:11:50.712351
4217 22:11:50.715316 RX Vref 0 -> 0, step: 1
4218 22:11:50.715438
4219 22:11:50.718609 RX Delay -230 -> 252, step: 16
4220 22:11:50.722172 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4221 22:11:50.725346 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4222 22:11:50.731913 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4223 22:11:50.735315 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4224 22:11:50.738814 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4225 22:11:50.742068 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4226 22:11:50.748512 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4227 22:11:50.751765 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4228 22:11:50.755351 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4229 22:11:50.758805 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4230 22:11:50.762229 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4231 22:11:50.768898 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4232 22:11:50.771993 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4233 22:11:50.775329 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4234 22:11:50.778431 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4235 22:11:50.785537 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4236 22:11:50.785644 ==
4237 22:11:50.788608 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 22:11:50.791878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 22:11:50.791956 ==
4240 22:11:50.792020 DQS Delay:
4241 22:11:50.795140 DQS0 = 0, DQS1 = 0
4242 22:11:50.795214 DQM Delay:
4243 22:11:50.798208 DQM0 = 54, DQM1 = 43
4244 22:11:50.798291 DQ Delay:
4245 22:11:50.801777 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4246 22:11:50.805199 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4247 22:11:50.808339 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =33
4248 22:11:50.811451 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4249 22:11:50.811537
4250 22:11:50.811638
4251 22:11:50.811721 ==
4252 22:11:50.814806 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 22:11:50.818305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 22:11:50.821727 ==
4255 22:11:50.821836
4256 22:11:50.821929
4257 22:11:50.822018 TX Vref Scan disable
4258 22:11:50.824943 == TX Byte 0 ==
4259 22:11:50.827949 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4260 22:11:50.831233 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4261 22:11:50.834480 == TX Byte 1 ==
4262 22:11:50.838422 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4263 22:11:50.841325 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4264 22:11:50.844660 ==
4265 22:11:50.844748 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 22:11:50.851595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 22:11:50.851683 ==
4268 22:11:50.851771
4269 22:11:50.851855
4270 22:11:50.854776 TX Vref Scan disable
4271 22:11:50.854862 == TX Byte 0 ==
4272 22:11:50.861257 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4273 22:11:50.864885 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4274 22:11:50.864969 == TX Byte 1 ==
4275 22:11:50.871009 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4276 22:11:50.874307 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4277 22:11:50.874409
4278 22:11:50.874512 [DATLAT]
4279 22:11:50.877961 Freq=600, CH0 RK1
4280 22:11:50.878037
4281 22:11:50.878118 DATLAT Default: 0x9
4282 22:11:50.881433 0, 0xFFFF, sum = 0
4283 22:11:50.881548 1, 0xFFFF, sum = 0
4284 22:11:50.884831 2, 0xFFFF, sum = 0
4285 22:11:50.884932 3, 0xFFFF, sum = 0
4286 22:11:50.888050 4, 0xFFFF, sum = 0
4287 22:11:50.888182 5, 0xFFFF, sum = 0
4288 22:11:50.891179 6, 0xFFFF, sum = 0
4289 22:11:50.894330 7, 0xFFFF, sum = 0
4290 22:11:50.894436 8, 0x0, sum = 1
4291 22:11:50.894538 9, 0x0, sum = 2
4292 22:11:50.897526 10, 0x0, sum = 3
4293 22:11:50.897649 11, 0x0, sum = 4
4294 22:11:50.900997 best_step = 9
4295 22:11:50.901096
4296 22:11:50.901188 ==
4297 22:11:50.904215 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 22:11:50.907588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 22:11:50.907711 ==
4300 22:11:50.911088 RX Vref Scan: 0
4301 22:11:50.911200
4302 22:11:50.911288 RX Vref 0 -> 0, step: 1
4303 22:11:50.911377
4304 22:11:50.914259 RX Delay -179 -> 252, step: 8
4305 22:11:50.921666 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4306 22:11:50.924982 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4307 22:11:50.928024 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4308 22:11:50.931391 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4309 22:11:50.934764 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4310 22:11:50.941096 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4311 22:11:50.944861 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4312 22:11:50.947782 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4313 22:11:50.951496 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4314 22:11:50.957922 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4315 22:11:50.961091 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4316 22:11:50.964298 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4317 22:11:50.967881 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4318 22:11:50.971004 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4319 22:11:50.977797 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4320 22:11:50.980962 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4321 22:11:50.981037 ==
4322 22:11:50.984554 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 22:11:50.987555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 22:11:50.987651 ==
4325 22:11:50.991123 DQS Delay:
4326 22:11:50.991215 DQS0 = 0, DQS1 = 0
4327 22:11:50.991288 DQM Delay:
4328 22:11:50.994872 DQM0 = 53, DQM1 = 46
4329 22:11:50.994956 DQ Delay:
4330 22:11:50.998027 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4331 22:11:51.001356 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4332 22:11:51.004595 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4333 22:11:51.007972 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4334 22:11:51.008056
4335 22:11:51.008121
4336 22:11:51.017819 [DQSOSCAuto] RK1, (LSB)MR18= 0x6526, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4337 22:11:51.017911 CH0 RK1: MR19=808, MR18=6526
4338 22:11:51.024443 CH0_RK1: MR19=0x808, MR18=0x6526, DQSOSC=390, MR23=63, INC=172, DEC=114
4339 22:11:51.027444 [RxdqsGatingPostProcess] freq 600
4340 22:11:51.034228 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4341 22:11:51.037547 Pre-setting of DQS Precalculation
4342 22:11:51.041117 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4343 22:11:51.041202 ==
4344 22:11:51.044478 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 22:11:51.047941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 22:11:51.051216 ==
4347 22:11:51.054390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4348 22:11:51.060884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4349 22:11:51.064138 [CA 0] Center 36 (5~67) winsize 63
4350 22:11:51.067256 [CA 1] Center 36 (6~67) winsize 62
4351 22:11:51.070852 [CA 2] Center 35 (5~65) winsize 61
4352 22:11:51.074242 [CA 3] Center 34 (4~65) winsize 62
4353 22:11:51.077450 [CA 4] Center 34 (4~65) winsize 62
4354 22:11:51.080571 [CA 5] Center 34 (4~64) winsize 61
4355 22:11:51.080656
4356 22:11:51.084204 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4357 22:11:51.084288
4358 22:11:51.087605 [CATrainingPosCal] consider 1 rank data
4359 22:11:51.090677 u2DelayCellTimex100 = 270/100 ps
4360 22:11:51.094205 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4361 22:11:51.097677 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4362 22:11:51.100826 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4363 22:11:51.107675 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4364 22:11:51.110728 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4365 22:11:51.114364 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4366 22:11:51.114452
4367 22:11:51.117758 CA PerBit enable=1, Macro0, CA PI delay=34
4368 22:11:51.117865
4369 22:11:51.120976 [CBTSetCACLKResult] CA Dly = 34
4370 22:11:51.121077 CS Dly: 6 (0~37)
4371 22:11:51.121172 ==
4372 22:11:51.124012 Dram Type= 6, Freq= 0, CH_1, rank 1
4373 22:11:51.130971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 22:11:51.131058 ==
4375 22:11:51.134158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 22:11:51.140984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4377 22:11:51.144112 [CA 0] Center 36 (5~67) winsize 63
4378 22:11:51.147783 [CA 1] Center 36 (5~67) winsize 63
4379 22:11:51.151337 [CA 2] Center 35 (4~66) winsize 63
4380 22:11:51.154179 [CA 3] Center 34 (4~65) winsize 62
4381 22:11:51.157784 [CA 4] Center 35 (4~66) winsize 63
4382 22:11:51.160937 [CA 5] Center 34 (3~65) winsize 63
4383 22:11:51.161026
4384 22:11:51.164244 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4385 22:11:51.164329
4386 22:11:51.167896 [CATrainingPosCal] consider 2 rank data
4387 22:11:51.171116 u2DelayCellTimex100 = 270/100 ps
4388 22:11:51.174251 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4389 22:11:51.178205 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4390 22:11:51.180720 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4391 22:11:51.187213 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 22:11:51.190794 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4393 22:11:51.193915 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4394 22:11:51.194042
4395 22:11:51.197805 CA PerBit enable=1, Macro0, CA PI delay=34
4396 22:11:51.197879
4397 22:11:51.200785 [CBTSetCACLKResult] CA Dly = 34
4398 22:11:51.200861 CS Dly: 6 (0~38)
4399 22:11:51.200926
4400 22:11:51.204490 ----->DramcWriteLeveling(PI) begin...
4401 22:11:51.204576 ==
4402 22:11:51.207296 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 22:11:51.214308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 22:11:51.214464 ==
4405 22:11:51.217208 Write leveling (Byte 0): 29 => 29
4406 22:11:51.220515 Write leveling (Byte 1): 32 => 32
4407 22:11:51.223750 DramcWriteLeveling(PI) end<-----
4408 22:11:51.223833
4409 22:11:51.223898 ==
4410 22:11:51.227359 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 22:11:51.230509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 22:11:51.230592 ==
4413 22:11:51.234026 [Gating] SW mode calibration
4414 22:11:51.240664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4415 22:11:51.243575 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4416 22:11:51.250617 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 22:11:51.253969 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 22:11:51.257220 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4419 22:11:51.263653 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (1 1) (1 1)
4420 22:11:51.266974 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 22:11:51.270647 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 22:11:51.277148 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 22:11:51.280708 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 22:11:51.284016 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 22:11:51.290876 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 22:11:51.294380 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4427 22:11:51.297406 0 10 12 | B1->B0 | 3939 3b3b | 0 0 | (0 0) (0 0)
4428 22:11:51.304026 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 22:11:51.307299 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 22:11:51.310648 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 22:11:51.317415 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 22:11:51.320687 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 22:11:51.323835 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 22:11:51.327545 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4435 22:11:51.333963 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4436 22:11:51.337603 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 22:11:51.340502 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 22:11:51.347284 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 22:11:51.350764 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 22:11:51.354152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 22:11:51.360627 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 22:11:51.364043 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 22:11:51.367603 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 22:11:51.373811 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 22:11:51.377042 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 22:11:51.380182 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 22:11:51.386934 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 22:11:51.390739 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 22:11:51.394063 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 22:11:51.400626 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:11:51.403964 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4452 22:11:51.407104 Total UI for P1: 0, mck2ui 16
4453 22:11:51.410402 best dqsien dly found for B0: ( 0, 13, 10)
4454 22:11:51.413620 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 22:11:51.416766 Total UI for P1: 0, mck2ui 16
4456 22:11:51.420637 best dqsien dly found for B1: ( 0, 13, 12)
4457 22:11:51.423654 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4458 22:11:51.426803 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4459 22:11:51.426885
4460 22:11:51.433779 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4461 22:11:51.437001 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4462 22:11:51.437083 [Gating] SW calibration Done
4463 22:11:51.440690 ==
4464 22:11:51.440775 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 22:11:51.446770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 22:11:51.446855 ==
4467 22:11:51.446921 RX Vref Scan: 0
4468 22:11:51.446984
4469 22:11:51.450559 RX Vref 0 -> 0, step: 1
4470 22:11:51.450641
4471 22:11:51.453918 RX Delay -230 -> 252, step: 16
4472 22:11:51.457035 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4473 22:11:51.460488 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4474 22:11:51.466857 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4475 22:11:51.470041 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4476 22:11:51.473571 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4477 22:11:51.476914 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4478 22:11:51.480077 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4479 22:11:51.486765 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4480 22:11:51.490111 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4481 22:11:51.493360 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4482 22:11:51.497197 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4483 22:11:51.503750 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4484 22:11:51.506770 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4485 22:11:51.510106 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4486 22:11:51.513772 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4487 22:11:51.520015 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4488 22:11:51.520100 ==
4489 22:11:51.523249 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 22:11:51.526570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 22:11:51.526659 ==
4492 22:11:51.526726 DQS Delay:
4493 22:11:51.530100 DQS0 = 0, DQS1 = 0
4494 22:11:51.530184 DQM Delay:
4495 22:11:51.533369 DQM0 = 49, DQM1 = 46
4496 22:11:51.533453 DQ Delay:
4497 22:11:51.536959 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4498 22:11:51.539782 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4499 22:11:51.543390 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4500 22:11:51.547059 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4501 22:11:51.547138
4502 22:11:51.547203
4503 22:11:51.547264 ==
4504 22:11:51.550137 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 22:11:51.553266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 22:11:51.553377 ==
4507 22:11:51.553453
4508 22:11:51.553514
4509 22:11:51.556630 TX Vref Scan disable
4510 22:11:51.559877 == TX Byte 0 ==
4511 22:11:51.563373 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4512 22:11:51.566695 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4513 22:11:51.569926 == TX Byte 1 ==
4514 22:11:51.573503 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4515 22:11:51.576596 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4516 22:11:51.576680 ==
4517 22:11:51.580005 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 22:11:51.586375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 22:11:51.586460 ==
4520 22:11:51.586526
4521 22:11:51.586587
4522 22:11:51.586645 TX Vref Scan disable
4523 22:11:51.591001 == TX Byte 0 ==
4524 22:11:51.594216 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4525 22:11:51.597438 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4526 22:11:51.601206 == TX Byte 1 ==
4527 22:11:51.604422 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4528 22:11:51.607728 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4529 22:11:51.611120
4530 22:11:51.611203 [DATLAT]
4531 22:11:51.611268 Freq=600, CH1 RK0
4532 22:11:51.611329
4533 22:11:51.614131 DATLAT Default: 0x9
4534 22:11:51.614215 0, 0xFFFF, sum = 0
4535 22:11:51.617453 1, 0xFFFF, sum = 0
4536 22:11:51.617538 2, 0xFFFF, sum = 0
4537 22:11:51.620618 3, 0xFFFF, sum = 0
4538 22:11:51.624386 4, 0xFFFF, sum = 0
4539 22:11:51.624471 5, 0xFFFF, sum = 0
4540 22:11:51.627570 6, 0xFFFF, sum = 0
4541 22:11:51.627663 7, 0xFFFF, sum = 0
4542 22:11:51.630811 8, 0x0, sum = 1
4543 22:11:51.630896 9, 0x0, sum = 2
4544 22:11:51.630963 10, 0x0, sum = 3
4545 22:11:51.634136 11, 0x0, sum = 4
4546 22:11:51.634221 best_step = 9
4547 22:11:51.634287
4548 22:11:51.634348 ==
4549 22:11:51.637290 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 22:11:51.643882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 22:11:51.643967 ==
4552 22:11:51.644033 RX Vref Scan: 1
4553 22:11:51.644094
4554 22:11:51.647118 RX Vref 0 -> 0, step: 1
4555 22:11:51.647201
4556 22:11:51.650496 RX Delay -163 -> 252, step: 8
4557 22:11:51.650594
4558 22:11:51.653982 Set Vref, RX VrefLevel [Byte0]: 50
4559 22:11:51.657030 [Byte1]: 52
4560 22:11:51.657139
4561 22:11:51.660422 Final RX Vref Byte 0 = 50 to rank0
4562 22:11:51.663605 Final RX Vref Byte 1 = 52 to rank0
4563 22:11:51.667293 Final RX Vref Byte 0 = 50 to rank1
4564 22:11:51.670408 Final RX Vref Byte 1 = 52 to rank1==
4565 22:11:51.674016 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 22:11:51.677031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 22:11:51.677137 ==
4568 22:11:51.680297 DQS Delay:
4569 22:11:51.680410 DQS0 = 0, DQS1 = 0
4570 22:11:51.680504 DQM Delay:
4571 22:11:51.683630 DQM0 = 48, DQM1 = 46
4572 22:11:51.683714 DQ Delay:
4573 22:11:51.686925 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4574 22:11:51.690275 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4575 22:11:51.693648 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4576 22:11:51.697125 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =56
4577 22:11:51.697209
4578 22:11:51.697275
4579 22:11:51.707168 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4580 22:11:51.710408 CH1 RK0: MR19=808, MR18=4D72
4581 22:11:51.717216 CH1_RK0: MR19=0x808, MR18=0x4D72, DQSOSC=388, MR23=63, INC=174, DEC=116
4582 22:11:51.717302
4583 22:11:51.720300 ----->DramcWriteLeveling(PI) begin...
4584 22:11:51.720386 ==
4585 22:11:51.723354 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 22:11:51.726602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 22:11:51.726713 ==
4588 22:11:51.730286 Write leveling (Byte 0): 30 => 30
4589 22:11:51.733630 Write leveling (Byte 1): 30 => 30
4590 22:11:51.736793 DramcWriteLeveling(PI) end<-----
4591 22:11:51.736876
4592 22:11:51.736942 ==
4593 22:11:51.740176 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 22:11:51.743326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 22:11:51.743410 ==
4596 22:11:51.746959 [Gating] SW mode calibration
4597 22:11:51.753630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4598 22:11:51.760283 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4599 22:11:51.763764 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 22:11:51.766554 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 22:11:51.773454 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4602 22:11:51.777112 0 9 12 | B1->B0 | 2d2d 2f2f | 0 0 | (1 1) (0 0)
4603 22:11:51.780440 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 22:11:51.786569 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 22:11:51.790462 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 22:11:51.793321 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 22:11:51.796508 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 22:11:51.803107 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 22:11:51.806822 0 10 8 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
4610 22:11:51.810354 0 10 12 | B1->B0 | 3737 3737 | 0 0 | (0 0) (0 0)
4611 22:11:51.816744 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 22:11:51.819981 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 22:11:51.823012 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 22:11:51.830098 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 22:11:51.833244 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 22:11:51.836658 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 22:11:51.843143 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 22:11:51.846441 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 22:11:51.850013 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 22:11:51.856393 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 22:11:51.859623 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 22:11:51.863074 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 22:11:51.869669 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 22:11:51.873028 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 22:11:51.876465 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 22:11:51.883142 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 22:11:51.886326 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 22:11:51.890058 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 22:11:51.896317 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 22:11:51.899631 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 22:11:51.903212 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 22:11:51.909601 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 22:11:51.913336 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 22:11:51.916011 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4635 22:11:51.920075 Total UI for P1: 0, mck2ui 16
4636 22:11:51.923129 best dqsien dly found for B1: ( 0, 13, 10)
4637 22:11:51.926041 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 22:11:51.929635 Total UI for P1: 0, mck2ui 16
4639 22:11:51.932732 best dqsien dly found for B0: ( 0, 13, 12)
4640 22:11:51.939576 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4641 22:11:51.942932 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4642 22:11:51.943028
4643 22:11:51.946184 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4644 22:11:51.949372 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4645 22:11:51.952645 [Gating] SW calibration Done
4646 22:11:51.952744 ==
4647 22:11:51.956124 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 22:11:51.959359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 22:11:51.959505 ==
4650 22:11:51.962592 RX Vref Scan: 0
4651 22:11:51.962744
4652 22:11:51.962849 RX Vref 0 -> 0, step: 1
4653 22:11:51.962996
4654 22:11:51.965969 RX Delay -230 -> 252, step: 16
4655 22:11:51.969058 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4656 22:11:51.975984 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4657 22:11:51.979419 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4658 22:11:51.982795 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4659 22:11:51.986035 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4660 22:11:51.992435 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4661 22:11:51.995907 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4662 22:11:51.999296 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4663 22:11:52.002334 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4664 22:11:52.006026 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4665 22:11:52.012516 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4666 22:11:52.015772 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4667 22:11:52.019529 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4668 22:11:52.022811 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4669 22:11:52.029721 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4670 22:11:52.032527 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4671 22:11:52.032612 ==
4672 22:11:52.036069 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 22:11:52.039439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 22:11:52.039566 ==
4675 22:11:52.042921 DQS Delay:
4676 22:11:52.043047 DQS0 = 0, DQS1 = 0
4677 22:11:52.043159 DQM Delay:
4678 22:11:52.046097 DQM0 = 49, DQM1 = 47
4679 22:11:52.046221 DQ Delay:
4680 22:11:52.049346 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4681 22:11:52.052653 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4682 22:11:52.055963 DQ8 =33, DQ9 =41, DQ10 =41, DQ11 =41
4683 22:11:52.059026 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4684 22:11:52.059147
4685 22:11:52.059261
4686 22:11:52.059368 ==
4687 22:11:52.062881 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 22:11:52.069262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 22:11:52.069385 ==
4690 22:11:52.069503
4691 22:11:52.069617
4692 22:11:52.069729 TX Vref Scan disable
4693 22:11:52.072464 == TX Byte 0 ==
4694 22:11:52.075768 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4695 22:11:52.082506 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4696 22:11:52.082635 == TX Byte 1 ==
4697 22:11:52.085551 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4698 22:11:52.092074 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4699 22:11:52.092206 ==
4700 22:11:52.095590 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 22:11:52.098962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 22:11:52.099088 ==
4703 22:11:52.099202
4704 22:11:52.099315
4705 22:11:52.102396 TX Vref Scan disable
4706 22:11:52.105517 == TX Byte 0 ==
4707 22:11:52.109068 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4708 22:11:52.112536 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4709 22:11:52.115790 == TX Byte 1 ==
4710 22:11:52.118846 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4711 22:11:52.121985 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4712 22:11:52.122110
4713 22:11:52.122223 [DATLAT]
4714 22:11:52.125514 Freq=600, CH1 RK1
4715 22:11:52.125620
4716 22:11:52.128571 DATLAT Default: 0x9
4717 22:11:52.128673 0, 0xFFFF, sum = 0
4718 22:11:52.132114 1, 0xFFFF, sum = 0
4719 22:11:52.132204 2, 0xFFFF, sum = 0
4720 22:11:52.135464 3, 0xFFFF, sum = 0
4721 22:11:52.135604 4, 0xFFFF, sum = 0
4722 22:11:52.138572 5, 0xFFFF, sum = 0
4723 22:11:52.138696 6, 0xFFFF, sum = 0
4724 22:11:52.141806 7, 0xFFFF, sum = 0
4725 22:11:52.141932 8, 0x0, sum = 1
4726 22:11:52.145195 9, 0x0, sum = 2
4727 22:11:52.145323 10, 0x0, sum = 3
4728 22:11:52.148418 11, 0x0, sum = 4
4729 22:11:52.148549 best_step = 9
4730 22:11:52.148666
4731 22:11:52.148774 ==
4732 22:11:52.152180 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 22:11:52.155403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 22:11:52.155525 ==
4735 22:11:52.158596 RX Vref Scan: 0
4736 22:11:52.158715
4737 22:11:52.161763 RX Vref 0 -> 0, step: 1
4738 22:11:52.161887
4739 22:11:52.162001 RX Delay -163 -> 252, step: 8
4740 22:11:52.169584 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4741 22:11:52.172963 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4742 22:11:52.176146 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4743 22:11:52.179292 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4744 22:11:52.185925 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4745 22:11:52.189457 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4746 22:11:52.192856 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4747 22:11:52.195886 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4748 22:11:52.199349 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4749 22:11:52.205998 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4750 22:11:52.209505 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4751 22:11:52.212700 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4752 22:11:52.216056 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4753 22:11:52.219399 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4754 22:11:52.225945 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4755 22:11:52.229342 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4756 22:11:52.229468 ==
4757 22:11:52.232635 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 22:11:52.235875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 22:11:52.236002 ==
4760 22:11:52.239213 DQS Delay:
4761 22:11:52.239335 DQS0 = 0, DQS1 = 0
4762 22:11:52.239454 DQM Delay:
4763 22:11:52.242501 DQM0 = 48, DQM1 = 44
4764 22:11:52.242627 DQ Delay:
4765 22:11:52.245734 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4766 22:11:52.249039 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4767 22:11:52.252583 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4768 22:11:52.255843 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4769 22:11:52.255968
4770 22:11:52.256084
4771 22:11:52.265509 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4772 22:11:52.269048 CH1 RK1: MR19=808, MR18=6D24
4773 22:11:52.272243 CH1_RK1: MR19=0x808, MR18=0x6D24, DQSOSC=389, MR23=63, INC=173, DEC=115
4774 22:11:52.275600 [RxdqsGatingPostProcess] freq 600
4775 22:11:52.282060 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4776 22:11:52.285570 Pre-setting of DQS Precalculation
4777 22:11:52.288929 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4778 22:11:52.299179 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4779 22:11:52.305327 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4780 22:11:52.305455
4781 22:11:52.305568
4782 22:11:52.308855 [Calibration Summary] 1200 Mbps
4783 22:11:52.308981 CH 0, Rank 0
4784 22:11:52.312041 SW Impedance : PASS
4785 22:11:52.312166 DUTY Scan : NO K
4786 22:11:52.315602 ZQ Calibration : PASS
4787 22:11:52.318455 Jitter Meter : NO K
4788 22:11:52.318572 CBT Training : PASS
4789 22:11:52.322101 Write leveling : PASS
4790 22:11:52.325556 RX DQS gating : PASS
4791 22:11:52.325677 RX DQ/DQS(RDDQC) : PASS
4792 22:11:52.328725 TX DQ/DQS : PASS
4793 22:11:52.328851 RX DATLAT : PASS
4794 22:11:52.331779 RX DQ/DQS(Engine): PASS
4795 22:11:52.335427 TX OE : NO K
4796 22:11:52.335551 All Pass.
4797 22:11:52.335674
4798 22:11:52.335782 CH 0, Rank 1
4799 22:11:52.338582 SW Impedance : PASS
4800 22:11:52.342156 DUTY Scan : NO K
4801 22:11:52.342282 ZQ Calibration : PASS
4802 22:11:52.345249 Jitter Meter : NO K
4803 22:11:52.349084 CBT Training : PASS
4804 22:11:52.349209 Write leveling : PASS
4805 22:11:52.352392 RX DQS gating : PASS
4806 22:11:52.355220 RX DQ/DQS(RDDQC) : PASS
4807 22:11:52.355342 TX DQ/DQS : PASS
4808 22:11:52.358620 RX DATLAT : PASS
4809 22:11:52.361779 RX DQ/DQS(Engine): PASS
4810 22:11:52.361904 TX OE : NO K
4811 22:11:52.365676 All Pass.
4812 22:11:52.365801
4813 22:11:52.365915 CH 1, Rank 0
4814 22:11:52.368486 SW Impedance : PASS
4815 22:11:52.368612 DUTY Scan : NO K
4816 22:11:52.372072 ZQ Calibration : PASS
4817 22:11:52.375210 Jitter Meter : NO K
4818 22:11:52.375293 CBT Training : PASS
4819 22:11:52.379100 Write leveling : PASS
4820 22:11:52.379182 RX DQS gating : PASS
4821 22:11:52.382210 RX DQ/DQS(RDDQC) : PASS
4822 22:11:52.385335 TX DQ/DQS : PASS
4823 22:11:52.385418 RX DATLAT : PASS
4824 22:11:52.388703 RX DQ/DQS(Engine): PASS
4825 22:11:52.391815 TX OE : NO K
4826 22:11:52.391897 All Pass.
4827 22:11:52.391961
4828 22:11:52.392021 CH 1, Rank 1
4829 22:11:52.395088 SW Impedance : PASS
4830 22:11:52.398311 DUTY Scan : NO K
4831 22:11:52.398434 ZQ Calibration : PASS
4832 22:11:52.401614 Jitter Meter : NO K
4833 22:11:52.405202 CBT Training : PASS
4834 22:11:52.405321 Write leveling : PASS
4835 22:11:52.408284 RX DQS gating : PASS
4836 22:11:52.412032 RX DQ/DQS(RDDQC) : PASS
4837 22:11:52.412155 TX DQ/DQS : PASS
4838 22:11:52.415137 RX DATLAT : PASS
4839 22:11:52.418433 RX DQ/DQS(Engine): PASS
4840 22:11:52.418587 TX OE : NO K
4841 22:11:52.418700 All Pass.
4842 22:11:52.422051
4843 22:11:52.422166 DramC Write-DBI off
4844 22:11:52.425141 PER_BANK_REFRESH: Hybrid Mode
4845 22:11:52.425260 TX_TRACKING: ON
4846 22:11:52.434972 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4847 22:11:52.438270 [FAST_K] Save calibration result to emmc
4848 22:11:52.441515 dramc_set_vcore_voltage set vcore to 662500
4849 22:11:52.445006 Read voltage for 933, 3
4850 22:11:52.445089 Vio18 = 0
4851 22:11:52.448083 Vcore = 662500
4852 22:11:52.448166 Vdram = 0
4853 22:11:52.448230 Vddq = 0
4854 22:11:52.448291 Vmddr = 0
4855 22:11:52.454773 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4856 22:11:52.461524 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4857 22:11:52.461631 MEM_TYPE=3, freq_sel=17
4858 22:11:52.464761 sv_algorithm_assistance_LP4_1600
4859 22:11:52.467977 ============ PULL DRAM RESETB DOWN ============
4860 22:11:52.474815 ========== PULL DRAM RESETB DOWN end =========
4861 22:11:52.477852 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 22:11:52.481213 ===================================
4863 22:11:52.484389 LPDDR4 DRAM CONFIGURATION
4864 22:11:52.487737 ===================================
4865 22:11:52.487821 EX_ROW_EN[0] = 0x0
4866 22:11:52.491411 EX_ROW_EN[1] = 0x0
4867 22:11:52.494938 LP4Y_EN = 0x0
4868 22:11:52.495020 WORK_FSP = 0x0
4869 22:11:52.498016 WL = 0x3
4870 22:11:52.498099 RL = 0x3
4871 22:11:52.501176 BL = 0x2
4872 22:11:52.501258 RPST = 0x0
4873 22:11:52.504365 RD_PRE = 0x0
4874 22:11:52.504448 WR_PRE = 0x1
4875 22:11:52.507574 WR_PST = 0x0
4876 22:11:52.507707 DBI_WR = 0x0
4877 22:11:52.511087 DBI_RD = 0x0
4878 22:11:52.511244 OTF = 0x1
4879 22:11:52.514301 ===================================
4880 22:11:52.518076 ===================================
4881 22:11:52.520862 ANA top config
4882 22:11:52.524536 ===================================
4883 22:11:52.524620 DLL_ASYNC_EN = 0
4884 22:11:52.527825 ALL_SLAVE_EN = 1
4885 22:11:52.531149 NEW_RANK_MODE = 1
4886 22:11:52.534198 DLL_IDLE_MODE = 1
4887 22:11:52.534280 LP45_APHY_COMB_EN = 1
4888 22:11:52.537581 TX_ODT_DIS = 1
4889 22:11:52.541098 NEW_8X_MODE = 1
4890 22:11:52.544215 ===================================
4891 22:11:52.547509 ===================================
4892 22:11:52.551157 data_rate = 1866
4893 22:11:52.554139 CKR = 1
4894 22:11:52.557775 DQ_P2S_RATIO = 8
4895 22:11:52.560787 ===================================
4896 22:11:52.560884 CA_P2S_RATIO = 8
4897 22:11:52.564140 DQ_CA_OPEN = 0
4898 22:11:52.567602 DQ_SEMI_OPEN = 0
4899 22:11:52.571010 CA_SEMI_OPEN = 0
4900 22:11:52.574259 CA_FULL_RATE = 0
4901 22:11:52.577459 DQ_CKDIV4_EN = 1
4902 22:11:52.577543 CA_CKDIV4_EN = 1
4903 22:11:52.580783 CA_PREDIV_EN = 0
4904 22:11:52.584549 PH8_DLY = 0
4905 22:11:52.587294 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4906 22:11:52.590855 DQ_AAMCK_DIV = 4
4907 22:11:52.594060 CA_AAMCK_DIV = 4
4908 22:11:52.594148 CA_ADMCK_DIV = 4
4909 22:11:52.597314 DQ_TRACK_CA_EN = 0
4910 22:11:52.601082 CA_PICK = 933
4911 22:11:52.604356 CA_MCKIO = 933
4912 22:11:52.607539 MCKIO_SEMI = 0
4913 22:11:52.610722 PLL_FREQ = 3732
4914 22:11:52.614007 DQ_UI_PI_RATIO = 32
4915 22:11:52.614092 CA_UI_PI_RATIO = 0
4916 22:11:52.617248 ===================================
4917 22:11:52.620978 ===================================
4918 22:11:52.623913 memory_type:LPDDR4
4919 22:11:52.627353 GP_NUM : 10
4920 22:11:52.627477 SRAM_EN : 1
4921 22:11:52.630684 MD32_EN : 0
4922 22:11:52.633963 ===================================
4923 22:11:52.637343 [ANA_INIT] >>>>>>>>>>>>>>
4924 22:11:52.640441 <<<<<< [CONFIGURE PHASE]: ANA_TX
4925 22:11:52.644031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4926 22:11:52.647776 ===================================
4927 22:11:52.647895 data_rate = 1866,PCW = 0X8f00
4928 22:11:52.650490 ===================================
4929 22:11:52.653817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4930 22:11:52.660640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 22:11:52.667179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 22:11:52.670442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4933 22:11:52.673796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4934 22:11:52.677415 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4935 22:11:52.680794 [ANA_INIT] flow start
4936 22:11:52.680878 [ANA_INIT] PLL >>>>>>>>
4937 22:11:52.684151 [ANA_INIT] PLL <<<<<<<<
4938 22:11:52.687192 [ANA_INIT] MIDPI >>>>>>>>
4939 22:11:52.690684 [ANA_INIT] MIDPI <<<<<<<<
4940 22:11:52.690769 [ANA_INIT] DLL >>>>>>>>
4941 22:11:52.694280 [ANA_INIT] flow end
4942 22:11:52.697045 ============ LP4 DIFF to SE enter ============
4943 22:11:52.700885 ============ LP4 DIFF to SE exit ============
4944 22:11:52.703706 [ANA_INIT] <<<<<<<<<<<<<
4945 22:11:52.707321 [Flow] Enable top DCM control >>>>>
4946 22:11:52.710518 [Flow] Enable top DCM control <<<<<
4947 22:11:52.713760 Enable DLL master slave shuffle
4948 22:11:52.717301 ==============================================================
4949 22:11:52.720475 Gating Mode config
4950 22:11:52.727116 ==============================================================
4951 22:11:52.727203 Config description:
4952 22:11:52.736858 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4953 22:11:52.743439 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4954 22:11:52.750425 SELPH_MODE 0: By rank 1: By Phase
4955 22:11:52.753720 ==============================================================
4956 22:11:52.757004 GAT_TRACK_EN = 1
4957 22:11:52.760057 RX_GATING_MODE = 2
4958 22:11:52.763789 RX_GATING_TRACK_MODE = 2
4959 22:11:52.767023 SELPH_MODE = 1
4960 22:11:52.770215 PICG_EARLY_EN = 1
4961 22:11:52.773632 VALID_LAT_VALUE = 1
4962 22:11:52.776944 ==============================================================
4963 22:11:52.780310 Enter into Gating configuration >>>>
4964 22:11:52.783611 Exit from Gating configuration <<<<
4965 22:11:52.786678 Enter into DVFS_PRE_config >>>>>
4966 22:11:52.800196 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4967 22:11:52.803226 Exit from DVFS_PRE_config <<<<<
4968 22:11:52.807036 Enter into PICG configuration >>>>
4969 22:11:52.807112 Exit from PICG configuration <<<<
4970 22:11:52.809945 [RX_INPUT] configuration >>>>>
4971 22:11:52.813902 [RX_INPUT] configuration <<<<<
4972 22:11:52.820266 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4973 22:11:52.823566 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4974 22:11:52.830248 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 22:11:52.837685 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 22:11:52.843520 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 22:11:52.849895 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 22:11:52.853207 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4979 22:11:52.856868 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4980 22:11:52.859881 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4981 22:11:52.866525 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4982 22:11:52.869797 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4983 22:11:52.873211 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 22:11:52.876504 ===================================
4985 22:11:52.880148 LPDDR4 DRAM CONFIGURATION
4986 22:11:52.883280 ===================================
4987 22:11:52.886380 EX_ROW_EN[0] = 0x0
4988 22:11:52.886464 EX_ROW_EN[1] = 0x0
4989 22:11:52.890136 LP4Y_EN = 0x0
4990 22:11:52.890219 WORK_FSP = 0x0
4991 22:11:52.893550 WL = 0x3
4992 22:11:52.893634 RL = 0x3
4993 22:11:52.896303 BL = 0x2
4994 22:11:52.896412 RPST = 0x0
4995 22:11:52.899962 RD_PRE = 0x0
4996 22:11:52.900066 WR_PRE = 0x1
4997 22:11:52.903084 WR_PST = 0x0
4998 22:11:52.903216 DBI_WR = 0x0
4999 22:11:52.906673 DBI_RD = 0x0
5000 22:11:52.906799 OTF = 0x1
5001 22:11:52.909890 ===================================
5002 22:11:52.916626 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5003 22:11:52.919756 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5004 22:11:52.923462 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 22:11:52.926278 ===================================
5006 22:11:52.929542 LPDDR4 DRAM CONFIGURATION
5007 22:11:52.933125 ===================================
5008 22:11:52.933250 EX_ROW_EN[0] = 0x10
5009 22:11:52.936514 EX_ROW_EN[1] = 0x0
5010 22:11:52.939634 LP4Y_EN = 0x0
5011 22:11:52.939755 WORK_FSP = 0x0
5012 22:11:52.942798 WL = 0x3
5013 22:11:52.942924 RL = 0x3
5014 22:11:52.946111 BL = 0x2
5015 22:11:52.946241 RPST = 0x0
5016 22:11:52.949329 RD_PRE = 0x0
5017 22:11:52.949457 WR_PRE = 0x1
5018 22:11:52.952791 WR_PST = 0x0
5019 22:11:52.952924 DBI_WR = 0x0
5020 22:11:52.956040 DBI_RD = 0x0
5021 22:11:52.956174 OTF = 0x1
5022 22:11:52.959355 ===================================
5023 22:11:52.966278 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5024 22:11:52.970553 nWR fixed to 30
5025 22:11:52.973920 [ModeRegInit_LP4] CH0 RK0
5026 22:11:52.974046 [ModeRegInit_LP4] CH0 RK1
5027 22:11:52.977170 [ModeRegInit_LP4] CH1 RK0
5028 22:11:52.980311 [ModeRegInit_LP4] CH1 RK1
5029 22:11:52.980442 match AC timing 9
5030 22:11:52.987305 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5031 22:11:52.990357 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5032 22:11:52.993659 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5033 22:11:53.000467 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5034 22:11:53.003695 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5035 22:11:53.003821 ==
5036 22:11:53.007001 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 22:11:53.010388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5038 22:11:53.010514 ==
5039 22:11:53.016789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5040 22:11:53.023453 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5041 22:11:53.026725 [CA 0] Center 37 (7~68) winsize 62
5042 22:11:53.030081 [CA 1] Center 37 (7~68) winsize 62
5043 22:11:53.033425 [CA 2] Center 34 (4~65) winsize 62
5044 22:11:53.037194 [CA 3] Center 34 (3~65) winsize 63
5045 22:11:53.040345 [CA 4] Center 33 (3~64) winsize 62
5046 22:11:53.043776 [CA 5] Center 32 (2~62) winsize 61
5047 22:11:53.043862
5048 22:11:53.046578 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5049 22:11:53.046661
5050 22:11:53.050369 [CATrainingPosCal] consider 1 rank data
5051 22:11:53.053484 u2DelayCellTimex100 = 270/100 ps
5052 22:11:53.056568 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5053 22:11:53.060163 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5054 22:11:53.063300 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5055 22:11:53.066606 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5056 22:11:53.070344 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5057 22:11:53.073568 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5058 22:11:53.076812
5059 22:11:53.080390 CA PerBit enable=1, Macro0, CA PI delay=32
5060 22:11:53.080475
5061 22:11:53.083817 [CBTSetCACLKResult] CA Dly = 32
5062 22:11:53.083900 CS Dly: 5 (0~36)
5063 22:11:53.083990 ==
5064 22:11:53.086773 Dram Type= 6, Freq= 0, CH_0, rank 1
5065 22:11:53.090071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 22:11:53.090161 ==
5067 22:11:53.096820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 22:11:53.103041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5069 22:11:53.106370 [CA 0] Center 37 (7~68) winsize 62
5070 22:11:53.109713 [CA 1] Center 37 (7~68) winsize 62
5071 22:11:53.113092 [CA 2] Center 34 (4~65) winsize 62
5072 22:11:53.116585 [CA 3] Center 33 (3~64) winsize 62
5073 22:11:53.119991 [CA 4] Center 33 (3~63) winsize 61
5074 22:11:53.123208 [CA 5] Center 32 (2~62) winsize 61
5075 22:11:53.123319
5076 22:11:53.126748 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5077 22:11:53.126833
5078 22:11:53.129589 [CATrainingPosCal] consider 2 rank data
5079 22:11:53.133065 u2DelayCellTimex100 = 270/100 ps
5080 22:11:53.136364 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5081 22:11:53.139544 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5082 22:11:53.142859 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5083 22:11:53.149281 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5084 22:11:53.153087 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5085 22:11:53.156019 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5086 22:11:53.156098
5087 22:11:53.159425 CA PerBit enable=1, Macro0, CA PI delay=32
5088 22:11:53.159532
5089 22:11:53.162972 [CBTSetCACLKResult] CA Dly = 32
5090 22:11:53.163050 CS Dly: 5 (0~37)
5091 22:11:53.163133
5092 22:11:53.166092 ----->DramcWriteLeveling(PI) begin...
5093 22:11:53.166173 ==
5094 22:11:53.169269 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 22:11:53.176038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 22:11:53.176117 ==
5097 22:11:53.179014 Write leveling (Byte 0): 32 => 32
5098 22:11:53.182262 Write leveling (Byte 1): 29 => 29
5099 22:11:53.185605 DramcWriteLeveling(PI) end<-----
5100 22:11:53.185696
5101 22:11:53.185775 ==
5102 22:11:53.189189 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 22:11:53.192535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 22:11:53.192647 ==
5105 22:11:53.196024 [Gating] SW mode calibration
5106 22:11:53.202423 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5107 22:11:53.205785 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5108 22:11:53.212097 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5109 22:11:53.215282 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 22:11:53.219016 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 22:11:53.225770 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 22:11:53.229014 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 22:11:53.232231 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 22:11:53.239104 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5115 22:11:53.242035 0 14 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
5116 22:11:53.245330 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5117 22:11:53.252363 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 22:11:53.255308 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 22:11:53.259147 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 22:11:53.265858 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 22:11:53.268895 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 22:11:53.271931 0 15 24 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
5123 22:11:53.278942 0 15 28 | B1->B0 | 2626 4040 | 0 0 | (0 0) (0 0)
5124 22:11:53.282585 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5125 22:11:53.285476 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 22:11:53.292153 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 22:11:53.295770 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 22:11:53.298658 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 22:11:53.305583 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 22:11:53.308673 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 22:11:53.312319 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5132 22:11:53.318877 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5133 22:11:53.321971 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 22:11:53.325785 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 22:11:53.331900 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 22:11:53.335052 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 22:11:53.338441 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 22:11:53.342270 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 22:11:53.348441 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 22:11:53.351727 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 22:11:53.355049 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 22:11:53.361956 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 22:11:53.365515 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 22:11:53.368466 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 22:11:53.375137 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 22:11:53.378399 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5147 22:11:53.381755 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5148 22:11:53.388459 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5149 22:11:53.388539 Total UI for P1: 0, mck2ui 16
5150 22:11:53.394988 best dqsien dly found for B0: ( 1, 2, 26)
5151 22:11:53.398247 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 22:11:53.401662 Total UI for P1: 0, mck2ui 16
5153 22:11:53.404783 best dqsien dly found for B1: ( 1, 3, 0)
5154 22:11:53.408462 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5155 22:11:53.411360 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5156 22:11:53.411470
5157 22:11:53.415005 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5158 22:11:53.417941 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5159 22:11:53.421545 [Gating] SW calibration Done
5160 22:11:53.421630 ==
5161 22:11:53.424633 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 22:11:53.428323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 22:11:53.431544 ==
5164 22:11:53.431685 RX Vref Scan: 0
5165 22:11:53.431785
5166 22:11:53.434719 RX Vref 0 -> 0, step: 1
5167 22:11:53.434797
5168 22:11:53.437783 RX Delay -80 -> 252, step: 8
5169 22:11:53.441205 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5170 22:11:53.444804 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5171 22:11:53.447934 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5172 22:11:53.451713 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5173 22:11:53.454566 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5174 22:11:53.461566 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5175 22:11:53.464769 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5176 22:11:53.467856 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5177 22:11:53.471430 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5178 22:11:53.474520 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5179 22:11:53.478056 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5180 22:11:53.484412 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5181 22:11:53.488302 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5182 22:11:53.491338 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5183 22:11:53.494493 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5184 22:11:53.497767 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5185 22:11:53.497859 ==
5186 22:11:53.501002 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 22:11:53.507985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 22:11:53.508067 ==
5189 22:11:53.508131 DQS Delay:
5190 22:11:53.511303 DQS0 = 0, DQS1 = 0
5191 22:11:53.511398 DQM Delay:
5192 22:11:53.511472 DQM0 = 105, DQM1 = 92
5193 22:11:53.514441 DQ Delay:
5194 22:11:53.517648 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5195 22:11:53.521249 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5196 22:11:53.524787 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5197 22:11:53.527785 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5198 22:11:53.527891
5199 22:11:53.527970
5200 22:11:53.528028 ==
5201 22:11:53.531078 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 22:11:53.534531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 22:11:53.534635 ==
5204 22:11:53.534722
5205 22:11:53.534800
5206 22:11:53.537745 TX Vref Scan disable
5207 22:11:53.540864 == TX Byte 0 ==
5208 22:11:53.544360 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5209 22:11:53.547839 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5210 22:11:53.550982 == TX Byte 1 ==
5211 22:11:53.554604 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5212 22:11:53.558006 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5213 22:11:53.558079 ==
5214 22:11:53.560693 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 22:11:53.564381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 22:11:53.567767 ==
5217 22:11:53.567839
5218 22:11:53.567903
5219 22:11:53.567963 TX Vref Scan disable
5220 22:11:53.571389 == TX Byte 0 ==
5221 22:11:53.574578 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5222 22:11:53.581092 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5223 22:11:53.581169 == TX Byte 1 ==
5224 22:11:53.584351 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5225 22:11:53.591280 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5226 22:11:53.591352
5227 22:11:53.591413 [DATLAT]
5228 22:11:53.591470 Freq=933, CH0 RK0
5229 22:11:53.591531
5230 22:11:53.594561 DATLAT Default: 0xd
5231 22:11:53.594668 0, 0xFFFF, sum = 0
5232 22:11:53.598058 1, 0xFFFF, sum = 0
5233 22:11:53.598162 2, 0xFFFF, sum = 0
5234 22:11:53.601164 3, 0xFFFF, sum = 0
5235 22:11:53.601281 4, 0xFFFF, sum = 0
5236 22:11:53.604471 5, 0xFFFF, sum = 0
5237 22:11:53.607703 6, 0xFFFF, sum = 0
5238 22:11:53.607772 7, 0xFFFF, sum = 0
5239 22:11:53.611289 8, 0xFFFF, sum = 0
5240 22:11:53.611378 9, 0xFFFF, sum = 0
5241 22:11:53.614491 10, 0x0, sum = 1
5242 22:11:53.614564 11, 0x0, sum = 2
5243 22:11:53.614629 12, 0x0, sum = 3
5244 22:11:53.618926 13, 0x0, sum = 4
5245 22:11:53.619032 best_step = 11
5246 22:11:53.619141
5247 22:11:53.619209 ==
5248 22:11:53.621332 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 22:11:53.628121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 22:11:53.628228 ==
5251 22:11:53.628320 RX Vref Scan: 1
5252 22:11:53.628405
5253 22:11:53.631386 RX Vref 0 -> 0, step: 1
5254 22:11:53.631483
5255 22:11:53.634597 RX Delay -53 -> 252, step: 4
5256 22:11:53.634699
5257 22:11:53.637741 Set Vref, RX VrefLevel [Byte0]: 54
5258 22:11:53.640744 [Byte1]: 53
5259 22:11:53.640818
5260 22:11:53.644360 Final RX Vref Byte 0 = 54 to rank0
5261 22:11:53.647451 Final RX Vref Byte 1 = 53 to rank0
5262 22:11:53.650844 Final RX Vref Byte 0 = 54 to rank1
5263 22:11:53.654438 Final RX Vref Byte 1 = 53 to rank1==
5264 22:11:53.657719 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 22:11:53.660874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 22:11:53.660958 ==
5267 22:11:53.664004 DQS Delay:
5268 22:11:53.664082 DQS0 = 0, DQS1 = 0
5269 22:11:53.667563 DQM Delay:
5270 22:11:53.667692 DQM0 = 104, DQM1 = 96
5271 22:11:53.671038 DQ Delay:
5272 22:11:53.674215 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5273 22:11:53.677183 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5274 22:11:53.681026 DQ8 =86, DQ9 =86, DQ10 =96, DQ11 =92
5275 22:11:53.684104 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =104
5276 22:11:53.684181
5277 22:11:53.684266
5278 22:11:53.690847 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5279 22:11:53.694058 CH0 RK0: MR19=505, MR18=2F26
5280 22:11:53.701191 CH0_RK0: MR19=0x505, MR18=0x2F26, DQSOSC=407, MR23=63, INC=65, DEC=43
5281 22:11:53.701276
5282 22:11:53.703973 ----->DramcWriteLeveling(PI) begin...
5283 22:11:53.704059 ==
5284 22:11:53.707205 Dram Type= 6, Freq= 0, CH_0, rank 1
5285 22:11:53.710940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 22:11:53.711026 ==
5287 22:11:53.714229 Write leveling (Byte 0): 32 => 32
5288 22:11:53.717329 Write leveling (Byte 1): 31 => 31
5289 22:11:53.720866 DramcWriteLeveling(PI) end<-----
5290 22:11:53.720951
5291 22:11:53.721016 ==
5292 22:11:53.724095 Dram Type= 6, Freq= 0, CH_0, rank 1
5293 22:11:53.727006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 22:11:53.730348 ==
5295 22:11:53.730433 [Gating] SW mode calibration
5296 22:11:53.737273 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5297 22:11:53.744166 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5298 22:11:53.747404 0 14 0 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
5299 22:11:53.753936 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 22:11:53.757320 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 22:11:53.760323 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 22:11:53.767257 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 22:11:53.770479 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 22:11:53.773856 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 22:11:53.780365 0 14 28 | B1->B0 | 2e2e 2b2b | 0 0 | (0 0) (0 0)
5306 22:11:53.783832 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (1 0)
5307 22:11:53.787388 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 22:11:53.793823 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 22:11:53.796920 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 22:11:53.800853 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 22:11:53.804202 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 22:11:53.810258 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
5313 22:11:53.813654 0 15 28 | B1->B0 | 3939 3736 | 1 1 | (0 0) (0 0)
5314 22:11:53.816834 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5315 22:11:53.823882 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 22:11:53.827003 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 22:11:53.830050 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 22:11:53.837203 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 22:11:53.840319 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 22:11:53.843851 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5321 22:11:53.850322 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5322 22:11:53.853589 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5323 22:11:53.857190 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 22:11:53.863462 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 22:11:53.866789 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 22:11:53.870429 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 22:11:53.876850 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 22:11:53.879980 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 22:11:53.883487 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 22:11:53.890007 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 22:11:53.893471 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 22:11:53.896841 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 22:11:53.903561 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 22:11:53.906638 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 22:11:53.910113 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 22:11:53.916500 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5337 22:11:53.920439 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5338 22:11:53.923210 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5339 22:11:53.926922 Total UI for P1: 0, mck2ui 16
5340 22:11:53.930194 best dqsien dly found for B1: ( 1, 2, 30)
5341 22:11:53.933317 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 22:11:53.936718 Total UI for P1: 0, mck2ui 16
5343 22:11:53.939916 best dqsien dly found for B0: ( 1, 2, 28)
5344 22:11:53.943587 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5345 22:11:53.949964 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5346 22:11:53.950060
5347 22:11:53.953225 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5348 22:11:53.956474 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5349 22:11:53.960224 [Gating] SW calibration Done
5350 22:11:53.960294 ==
5351 22:11:53.963366 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 22:11:53.966613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 22:11:53.966686 ==
5354 22:11:53.966748 RX Vref Scan: 0
5355 22:11:53.970170
5356 22:11:53.970244 RX Vref 0 -> 0, step: 1
5357 22:11:53.970334
5358 22:11:53.973313 RX Delay -80 -> 252, step: 8
5359 22:11:53.976497 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5360 22:11:53.979777 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5361 22:11:53.986796 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5362 22:11:53.989951 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5363 22:11:53.993220 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5364 22:11:53.996800 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5365 22:11:53.999941 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5366 22:11:54.003512 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5367 22:11:54.009920 iDelay=208, Bit 8, Center 91 (8 ~ 175) 168
5368 22:11:54.013031 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5369 22:11:54.016530 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5370 22:11:54.020288 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5371 22:11:54.023718 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5372 22:11:54.026166 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5373 22:11:54.032772 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5374 22:11:54.036188 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5375 22:11:54.036316 ==
5376 22:11:54.039659 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 22:11:54.043114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 22:11:54.043247 ==
5379 22:11:54.043361 DQS Delay:
5380 22:11:54.046420 DQS0 = 0, DQS1 = 0
5381 22:11:54.046510 DQM Delay:
5382 22:11:54.049988 DQM0 = 104, DQM1 = 95
5383 22:11:54.050073 DQ Delay:
5384 22:11:54.053135 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5385 22:11:54.056257 DQ4 =103, DQ5 =99, DQ6 =107, DQ7 =111
5386 22:11:54.060053 DQ8 =91, DQ9 =87, DQ10 =95, DQ11 =91
5387 22:11:54.063149 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5388 22:11:54.063237
5389 22:11:54.063325
5390 22:11:54.063408 ==
5391 22:11:54.066322 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 22:11:54.073212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 22:11:54.073305 ==
5394 22:11:54.073389
5395 22:11:54.073452
5396 22:11:54.073511 TX Vref Scan disable
5397 22:11:54.076412 == TX Byte 0 ==
5398 22:11:54.080075 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5399 22:11:54.086455 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5400 22:11:54.086581 == TX Byte 1 ==
5401 22:11:54.089802 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5402 22:11:54.096378 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5403 22:11:54.096510 ==
5404 22:11:54.099689 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 22:11:54.102827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 22:11:54.102957 ==
5407 22:11:54.103073
5408 22:11:54.103189
5409 22:11:54.106132 TX Vref Scan disable
5410 22:11:54.106260 == TX Byte 0 ==
5411 22:11:54.112640 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5412 22:11:54.116178 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5413 22:11:54.116290 == TX Byte 1 ==
5414 22:11:54.122762 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5415 22:11:54.126100 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5416 22:11:54.126222
5417 22:11:54.126343 [DATLAT]
5418 22:11:54.129360 Freq=933, CH0 RK1
5419 22:11:54.129480
5420 22:11:54.129600 DATLAT Default: 0xb
5421 22:11:54.132796 0, 0xFFFF, sum = 0
5422 22:11:54.132916 1, 0xFFFF, sum = 0
5423 22:11:54.136031 2, 0xFFFF, sum = 0
5424 22:11:54.136141 3, 0xFFFF, sum = 0
5425 22:11:54.139638 4, 0xFFFF, sum = 0
5426 22:11:54.143116 5, 0xFFFF, sum = 0
5427 22:11:54.143248 6, 0xFFFF, sum = 0
5428 22:11:54.146058 7, 0xFFFF, sum = 0
5429 22:11:54.146185 8, 0xFFFF, sum = 0
5430 22:11:54.149232 9, 0xFFFF, sum = 0
5431 22:11:54.149365 10, 0x0, sum = 1
5432 22:11:54.153145 11, 0x0, sum = 2
5433 22:11:54.153231 12, 0x0, sum = 3
5434 22:11:54.153297 13, 0x0, sum = 4
5435 22:11:54.156079 best_step = 11
5436 22:11:54.156162
5437 22:11:54.156228 ==
5438 22:11:54.159264 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 22:11:54.162619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 22:11:54.162704 ==
5441 22:11:54.165996 RX Vref Scan: 0
5442 22:11:54.166080
5443 22:11:54.166146 RX Vref 0 -> 0, step: 1
5444 22:11:54.169192
5445 22:11:54.169276 RX Delay -45 -> 252, step: 4
5446 22:11:54.176953 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5447 22:11:54.180226 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5448 22:11:54.183364 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5449 22:11:54.187000 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5450 22:11:54.189902 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5451 22:11:54.197058 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5452 22:11:54.199886 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5453 22:11:54.203665 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5454 22:11:54.206701 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5455 22:11:54.210027 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5456 22:11:54.216497 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5457 22:11:54.219898 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5458 22:11:54.223408 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5459 22:11:54.226736 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5460 22:11:54.230270 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5461 22:11:54.236898 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5462 22:11:54.237025 ==
5463 22:11:54.239927 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 22:11:54.243468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 22:11:54.243598 ==
5466 22:11:54.243715 DQS Delay:
5467 22:11:54.246374 DQS0 = 0, DQS1 = 0
5468 22:11:54.246498 DQM Delay:
5469 22:11:54.250207 DQM0 = 104, DQM1 = 94
5470 22:11:54.250330 DQ Delay:
5471 22:11:54.253379 DQ0 =100, DQ1 =108, DQ2 =102, DQ3 =100
5472 22:11:54.256381 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5473 22:11:54.259583 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =90
5474 22:11:54.263476 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5475 22:11:54.263604
5476 22:11:54.263724
5477 22:11:54.273071 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 407 ps
5478 22:11:54.273204 CH0 RK1: MR19=505, MR18=2D05
5479 22:11:54.279853 CH0_RK1: MR19=0x505, MR18=0x2D05, DQSOSC=407, MR23=63, INC=65, DEC=43
5480 22:11:54.283159 [RxdqsGatingPostProcess] freq 933
5481 22:11:54.289823 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5482 22:11:54.293015 best DQS0 dly(2T, 0.5T) = (0, 10)
5483 22:11:54.296292 best DQS1 dly(2T, 0.5T) = (0, 11)
5484 22:11:54.299495 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5485 22:11:54.302990 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5486 22:11:54.306310 best DQS0 dly(2T, 0.5T) = (0, 10)
5487 22:11:54.309493 best DQS1 dly(2T, 0.5T) = (0, 10)
5488 22:11:54.313086 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5489 22:11:54.316535 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5490 22:11:54.316657 Pre-setting of DQS Precalculation
5491 22:11:54.322830 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5492 22:11:54.322936 ==
5493 22:11:54.326353 Dram Type= 6, Freq= 0, CH_1, rank 0
5494 22:11:54.329389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 22:11:54.329475 ==
5496 22:11:54.336215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5497 22:11:54.343056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5498 22:11:54.346041 [CA 0] Center 36 (6~67) winsize 62
5499 22:11:54.349777 [CA 1] Center 36 (6~67) winsize 62
5500 22:11:54.352816 [CA 2] Center 34 (4~65) winsize 62
5501 22:11:54.356589 [CA 3] Center 34 (4~65) winsize 62
5502 22:11:54.359702 [CA 4] Center 34 (4~64) winsize 61
5503 22:11:54.362805 [CA 5] Center 33 (3~64) winsize 62
5504 22:11:54.362950
5505 22:11:54.366673 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5506 22:11:54.366809
5507 22:11:54.370101 [CATrainingPosCal] consider 1 rank data
5508 22:11:54.373021 u2DelayCellTimex100 = 270/100 ps
5509 22:11:54.376556 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5510 22:11:54.379968 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5511 22:11:54.382958 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5512 22:11:54.386458 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5513 22:11:54.389605 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5514 22:11:54.393180 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5515 22:11:54.393302
5516 22:11:54.399520 CA PerBit enable=1, Macro0, CA PI delay=33
5517 22:11:54.399649
5518 22:11:54.399765 [CBTSetCACLKResult] CA Dly = 33
5519 22:11:54.402801 CS Dly: 6 (0~37)
5520 22:11:54.402929 ==
5521 22:11:54.405925 Dram Type= 6, Freq= 0, CH_1, rank 1
5522 22:11:54.409775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 22:11:54.409904 ==
5524 22:11:54.416061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 22:11:54.422567 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5526 22:11:54.425871 [CA 0] Center 37 (6~68) winsize 63
5527 22:11:54.429088 [CA 1] Center 37 (6~68) winsize 63
5528 22:11:54.432605 [CA 2] Center 35 (5~66) winsize 62
5529 22:11:54.435842 [CA 3] Center 34 (4~65) winsize 62
5530 22:11:54.439445 [CA 4] Center 34 (4~65) winsize 62
5531 22:11:54.442732 [CA 5] Center 33 (3~64) winsize 62
5532 22:11:54.442808
5533 22:11:54.445905 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5534 22:11:54.445989
5535 22:11:54.449078 [CATrainingPosCal] consider 2 rank data
5536 22:11:54.452625 u2DelayCellTimex100 = 270/100 ps
5537 22:11:54.456016 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5538 22:11:54.459097 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5539 22:11:54.462424 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5540 22:11:54.466069 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5541 22:11:54.469291 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5542 22:11:54.472505 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5543 22:11:54.472579
5544 22:11:54.479466 CA PerBit enable=1, Macro0, CA PI delay=33
5545 22:11:54.479576
5546 22:11:54.482708 [CBTSetCACLKResult] CA Dly = 33
5547 22:11:54.482814 CS Dly: 7 (0~40)
5548 22:11:54.482905
5549 22:11:54.485763 ----->DramcWriteLeveling(PI) begin...
5550 22:11:54.485838 ==
5551 22:11:54.488863 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 22:11:54.492370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 22:11:54.495262 ==
5554 22:11:54.495390 Write leveling (Byte 0): 27 => 27
5555 22:11:54.498913 Write leveling (Byte 1): 29 => 29
5556 22:11:54.502057 DramcWriteLeveling(PI) end<-----
5557 22:11:54.502182
5558 22:11:54.502300 ==
5559 22:11:54.505255 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 22:11:54.512384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 22:11:54.512519 ==
5562 22:11:54.515171 [Gating] SW mode calibration
5563 22:11:54.521551 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5564 22:11:54.525175 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5565 22:11:54.531814 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 22:11:54.534993 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 22:11:54.538217 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 22:11:54.545081 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 22:11:54.548473 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 22:11:54.551892 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 22:11:54.558255 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5572 22:11:54.561785 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5573 22:11:54.564972 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 22:11:54.571888 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 22:11:54.575170 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 22:11:54.578385 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 22:11:54.584876 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 22:11:54.588139 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 22:11:54.591848 0 15 24 | B1->B0 | 2929 3636 | 0 0 | (0 0) (0 0)
5580 22:11:54.594968 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5581 22:11:54.601448 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 22:11:54.604825 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 22:11:54.607949 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 22:11:54.614894 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 22:11:54.618324 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 22:11:54.621739 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 22:11:54.628010 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5588 22:11:54.631339 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 22:11:54.634564 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 22:11:54.641422 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 22:11:54.644563 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 22:11:54.648165 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 22:11:54.654766 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 22:11:54.658202 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 22:11:54.661147 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 22:11:54.668065 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 22:11:54.671403 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 22:11:54.674954 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 22:11:54.681549 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 22:11:54.684816 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 22:11:54.688067 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 22:11:54.694553 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 22:11:54.698321 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5604 22:11:54.701467 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 22:11:54.704705 Total UI for P1: 0, mck2ui 16
5606 22:11:54.707779 best dqsien dly found for B0: ( 1, 2, 24)
5607 22:11:54.711448 Total UI for P1: 0, mck2ui 16
5608 22:11:54.714385 best dqsien dly found for B1: ( 1, 2, 24)
5609 22:11:54.717969 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5610 22:11:54.721220 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5611 22:11:54.721299
5612 22:11:54.724317 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5613 22:11:54.730923 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5614 22:11:54.731046 [Gating] SW calibration Done
5615 22:11:54.731111 ==
5616 22:11:54.734316 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 22:11:54.741175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 22:11:54.741286 ==
5619 22:11:54.741350 RX Vref Scan: 0
5620 22:11:54.741410
5621 22:11:54.744566 RX Vref 0 -> 0, step: 1
5622 22:11:54.744639
5623 22:11:54.747568 RX Delay -80 -> 252, step: 8
5624 22:11:54.751360 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5625 22:11:54.754385 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5626 22:11:54.757549 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5627 22:11:54.760934 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5628 22:11:54.764420 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5629 22:11:54.771025 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5630 22:11:54.774757 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5631 22:11:54.778156 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5632 22:11:54.781030 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5633 22:11:54.784592 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5634 22:11:54.787943 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5635 22:11:54.794379 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5636 22:11:54.797567 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5637 22:11:54.800695 iDelay=208, Bit 13, Center 107 (24 ~ 191) 168
5638 22:11:54.804048 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5639 22:11:54.810556 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5640 22:11:54.810629 ==
5641 22:11:54.814215 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 22:11:54.817409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 22:11:54.817481 ==
5644 22:11:54.817546 DQS Delay:
5645 22:11:54.820690 DQS0 = 0, DQS1 = 0
5646 22:11:54.820767 DQM Delay:
5647 22:11:54.824279 DQM0 = 102, DQM1 = 98
5648 22:11:54.824387 DQ Delay:
5649 22:11:54.827402 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5650 22:11:54.830435 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5651 22:11:54.834317 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5652 22:11:54.837201 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5653 22:11:54.837306
5654 22:11:54.837373
5655 22:11:54.837433 ==
5656 22:11:54.840486 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 22:11:54.847573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 22:11:54.847661 ==
5659 22:11:54.847725
5660 22:11:54.847788
5661 22:11:54.847845 TX Vref Scan disable
5662 22:11:54.850363 == TX Byte 0 ==
5663 22:11:54.854117 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5664 22:11:54.857093 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5665 22:11:54.860770 == TX Byte 1 ==
5666 22:11:54.863861 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5667 22:11:54.867440 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5668 22:11:54.870532 ==
5669 22:11:54.873947 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 22:11:54.877111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 22:11:54.877185 ==
5672 22:11:54.877250
5673 22:11:54.877308
5674 22:11:54.880626 TX Vref Scan disable
5675 22:11:54.880698 == TX Byte 0 ==
5676 22:11:54.887227 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5677 22:11:54.890711 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5678 22:11:54.890792 == TX Byte 1 ==
5679 22:11:54.897367 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5680 22:11:54.900494 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5681 22:11:54.900568
5682 22:11:54.900629 [DATLAT]
5683 22:11:54.903726 Freq=933, CH1 RK0
5684 22:11:54.903801
5685 22:11:54.903863 DATLAT Default: 0xd
5686 22:11:54.907063 0, 0xFFFF, sum = 0
5687 22:11:54.907167 1, 0xFFFF, sum = 0
5688 22:11:54.910285 2, 0xFFFF, sum = 0
5689 22:11:54.910360 3, 0xFFFF, sum = 0
5690 22:11:54.913942 4, 0xFFFF, sum = 0
5691 22:11:54.914019 5, 0xFFFF, sum = 0
5692 22:11:54.917222 6, 0xFFFF, sum = 0
5693 22:11:54.920540 7, 0xFFFF, sum = 0
5694 22:11:54.920614 8, 0xFFFF, sum = 0
5695 22:11:54.923705 9, 0xFFFF, sum = 0
5696 22:11:54.923815 10, 0x0, sum = 1
5697 22:11:54.923880 11, 0x0, sum = 2
5698 22:11:54.926865 12, 0x0, sum = 3
5699 22:11:54.926968 13, 0x0, sum = 4
5700 22:11:54.930193 best_step = 11
5701 22:11:54.930269
5702 22:11:54.930372 ==
5703 22:11:54.933942 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 22:11:54.937438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 22:11:54.937565 ==
5706 22:11:54.940267 RX Vref Scan: 1
5707 22:11:54.940390
5708 22:11:54.940499 RX Vref 0 -> 0, step: 1
5709 22:11:54.940634
5710 22:11:54.943796 RX Delay -45 -> 252, step: 4
5711 22:11:54.943915
5712 22:11:54.946948 Set Vref, RX VrefLevel [Byte0]: 50
5713 22:11:54.950603 [Byte1]: 52
5714 22:11:54.954250
5715 22:11:54.954373 Final RX Vref Byte 0 = 50 to rank0
5716 22:11:54.957716 Final RX Vref Byte 1 = 52 to rank0
5717 22:11:54.961129 Final RX Vref Byte 0 = 50 to rank1
5718 22:11:54.964569 Final RX Vref Byte 1 = 52 to rank1==
5719 22:11:54.967765 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 22:11:54.974410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 22:11:54.974495 ==
5722 22:11:54.974561 DQS Delay:
5723 22:11:54.974627 DQS0 = 0, DQS1 = 0
5724 22:11:54.977814 DQM Delay:
5725 22:11:54.977944 DQM0 = 103, DQM1 = 100
5726 22:11:54.980862 DQ Delay:
5727 22:11:54.984186 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5728 22:11:54.987981 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5729 22:11:54.991189 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5730 22:11:54.994054 DQ12 =106, DQ13 =106, DQ14 =110, DQ15 =110
5731 22:11:54.994181
5732 22:11:54.994296
5733 22:11:55.000941 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5734 22:11:55.004298 CH1 RK0: MR19=505, MR18=1C33
5735 22:11:55.010715 CH1_RK0: MR19=0x505, MR18=0x1C33, DQSOSC=405, MR23=63, INC=66, DEC=44
5736 22:11:55.010841
5737 22:11:55.013988 ----->DramcWriteLeveling(PI) begin...
5738 22:11:55.014113 ==
5739 22:11:55.017385 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 22:11:55.021058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 22:11:55.024292 ==
5742 22:11:55.024414 Write leveling (Byte 0): 26 => 26
5743 22:11:55.027608 Write leveling (Byte 1): 29 => 29
5744 22:11:55.030591 DramcWriteLeveling(PI) end<-----
5745 22:11:55.030715
5746 22:11:55.030821 ==
5747 22:11:55.034358 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 22:11:55.040757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 22:11:55.040885 ==
5750 22:11:55.041002 [Gating] SW mode calibration
5751 22:11:55.050778 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5752 22:11:55.054088 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5753 22:11:55.060453 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 22:11:55.063913 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 22:11:55.067446 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 22:11:55.070493 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 22:11:55.077107 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 22:11:55.080946 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 22:11:55.083795 0 14 24 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 0)
5760 22:11:55.090377 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (1 0)
5761 22:11:55.093765 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 22:11:55.097391 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 22:11:55.103576 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 22:11:55.107044 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 22:11:55.110296 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 22:11:55.116925 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 22:11:55.120072 0 15 24 | B1->B0 | 3838 2b2b | 0 0 | (0 0) (0 0)
5768 22:11:55.123431 0 15 28 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
5769 22:11:55.130439 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 22:11:55.133563 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 22:11:55.136691 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 22:11:55.143573 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 22:11:55.146888 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 22:11:55.150049 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 22:11:55.156853 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 22:11:55.160214 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5777 22:11:55.163438 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 22:11:55.170242 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 22:11:55.173526 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 22:11:55.176770 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 22:11:55.183510 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 22:11:55.186854 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 22:11:55.189838 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 22:11:55.196656 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 22:11:55.200046 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 22:11:55.203667 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 22:11:55.210033 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 22:11:55.213271 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 22:11:55.216837 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 22:11:55.220358 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5791 22:11:55.226742 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5792 22:11:55.230079 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 22:11:55.233199 Total UI for P1: 0, mck2ui 16
5794 22:11:55.236962 best dqsien dly found for B0: ( 1, 2, 24)
5795 22:11:55.239961 Total UI for P1: 0, mck2ui 16
5796 22:11:55.243248 best dqsien dly found for B1: ( 1, 2, 22)
5797 22:11:55.246489 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5798 22:11:55.249754 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5799 22:11:55.249839
5800 22:11:55.253477 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5801 22:11:55.256452 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5802 22:11:55.259842 [Gating] SW calibration Done
5803 22:11:55.259927 ==
5804 22:11:55.263606 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 22:11:55.270296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 22:11:55.270382 ==
5807 22:11:55.270447 RX Vref Scan: 0
5808 22:11:55.270509
5809 22:11:55.273345 RX Vref 0 -> 0, step: 1
5810 22:11:55.273429
5811 22:11:55.276624 RX Delay -80 -> 252, step: 8
5812 22:11:55.280132 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5813 22:11:55.283300 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5814 22:11:55.286493 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5815 22:11:55.289729 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5816 22:11:55.293476 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5817 22:11:55.299639 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5818 22:11:55.303280 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5819 22:11:55.306448 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5820 22:11:55.309817 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5821 22:11:55.313453 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5822 22:11:55.316317 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5823 22:11:55.323122 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5824 22:11:55.326703 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5825 22:11:55.329623 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5826 22:11:55.333142 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5827 22:11:55.336575 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5828 22:11:55.339676 ==
5829 22:11:55.343303 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 22:11:55.346587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 22:11:55.346712 ==
5832 22:11:55.346823 DQS Delay:
5833 22:11:55.349697 DQS0 = 0, DQS1 = 0
5834 22:11:55.349819 DQM Delay:
5835 22:11:55.353033 DQM0 = 102, DQM1 = 99
5836 22:11:55.353157 DQ Delay:
5837 22:11:55.356656 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5838 22:11:55.359801 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =99
5839 22:11:55.362955 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5840 22:11:55.366345 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5841 22:11:55.366429
5842 22:11:55.366494
5843 22:11:55.366556 ==
5844 22:11:55.370114 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 22:11:55.373285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 22:11:55.373412 ==
5847 22:11:55.373526
5848 22:11:55.373638
5849 22:11:55.376595 TX Vref Scan disable
5850 22:11:55.379785 == TX Byte 0 ==
5851 22:11:55.383004 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5852 22:11:55.386655 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5853 22:11:55.389957 == TX Byte 1 ==
5854 22:11:55.393180 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5855 22:11:55.396322 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5856 22:11:55.396450 ==
5857 22:11:55.399873 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 22:11:55.406277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 22:11:55.406404 ==
5860 22:11:55.406519
5861 22:11:55.406627
5862 22:11:55.406739 TX Vref Scan disable
5863 22:11:55.410288 == TX Byte 0 ==
5864 22:11:55.413716 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5865 22:11:55.420258 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5866 22:11:55.420384 == TX Byte 1 ==
5867 22:11:55.423630 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5868 22:11:55.427404 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5869 22:11:55.430609
5870 22:11:55.430732 [DATLAT]
5871 22:11:55.430846 Freq=933, CH1 RK1
5872 22:11:55.430957
5873 22:11:55.433498 DATLAT Default: 0xb
5874 22:11:55.433602 0, 0xFFFF, sum = 0
5875 22:11:55.437200 1, 0xFFFF, sum = 0
5876 22:11:55.437325 2, 0xFFFF, sum = 0
5877 22:11:55.440444 3, 0xFFFF, sum = 0
5878 22:11:55.440566 4, 0xFFFF, sum = 0
5879 22:11:55.443817 5, 0xFFFF, sum = 0
5880 22:11:55.443942 6, 0xFFFF, sum = 0
5881 22:11:55.447028 7, 0xFFFF, sum = 0
5882 22:11:55.447153 8, 0xFFFF, sum = 0
5883 22:11:55.450703 9, 0xFFFF, sum = 0
5884 22:11:55.450827 10, 0x0, sum = 1
5885 22:11:55.453793 11, 0x0, sum = 2
5886 22:11:55.453918 12, 0x0, sum = 3
5887 22:11:55.457239 13, 0x0, sum = 4
5888 22:11:55.457365 best_step = 11
5889 22:11:55.457476
5890 22:11:55.457588 ==
5891 22:11:55.460445 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 22:11:55.467312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 22:11:55.467442 ==
5894 22:11:55.467558 RX Vref Scan: 0
5895 22:11:55.467678
5896 22:11:55.470526 RX Vref 0 -> 0, step: 1
5897 22:11:55.470651
5898 22:11:55.473735 RX Delay -45 -> 252, step: 4
5899 22:11:55.477027 iDelay=199, Bit 0, Center 108 (27 ~ 190) 164
5900 22:11:55.483546 iDelay=199, Bit 1, Center 100 (19 ~ 182) 164
5901 22:11:55.486922 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5902 22:11:55.490437 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5903 22:11:55.493535 iDelay=199, Bit 4, Center 98 (19 ~ 178) 160
5904 22:11:55.496972 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5905 22:11:55.500735 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5906 22:11:55.507056 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5907 22:11:55.510443 iDelay=199, Bit 8, Center 90 (7 ~ 174) 168
5908 22:11:55.513685 iDelay=199, Bit 9, Center 92 (7 ~ 178) 172
5909 22:11:55.517120 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5910 22:11:55.520277 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5911 22:11:55.526828 iDelay=199, Bit 12, Center 108 (19 ~ 198) 180
5912 22:11:55.530275 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5913 22:11:55.533565 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5914 22:11:55.536794 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5915 22:11:55.536921 ==
5916 22:11:55.539957 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 22:11:55.546475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 22:11:55.546599 ==
5919 22:11:55.546715 DQS Delay:
5920 22:11:55.549982 DQS0 = 0, DQS1 = 0
5921 22:11:55.550105 DQM Delay:
5922 22:11:55.550215 DQM0 = 104, DQM1 = 99
5923 22:11:55.553136 DQ Delay:
5924 22:11:55.556631 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5925 22:11:55.559690 DQ4 =98, DQ5 =116, DQ6 =114, DQ7 =102
5926 22:11:55.563312 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =94
5927 22:11:55.566600 DQ12 =108, DQ13 =106, DQ14 =102, DQ15 =106
5928 22:11:55.566723
5929 22:11:55.566833
5930 22:11:55.573304 [DQSOSCAuto] RK1, (LSB)MR18= 0x3104, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 406 ps
5931 22:11:55.576602 CH1 RK1: MR19=505, MR18=3104
5932 22:11:55.583032 CH1_RK1: MR19=0x505, MR18=0x3104, DQSOSC=406, MR23=63, INC=65, DEC=43
5933 22:11:55.586322 [RxdqsGatingPostProcess] freq 933
5934 22:11:55.593661 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5935 22:11:55.596696 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 22:11:55.596822 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 22:11:55.599907 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 22:11:55.602837 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 22:11:55.606188 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 22:11:55.610089 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 22:11:55.612930 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 22:11:55.616574 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 22:11:55.619682 Pre-setting of DQS Precalculation
5944 22:11:55.626547 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5945 22:11:55.632867 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5946 22:11:55.640081 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5947 22:11:55.640164
5948 22:11:55.640228
5949 22:11:55.643078 [Calibration Summary] 1866 Mbps
5950 22:11:55.643160 CH 0, Rank 0
5951 22:11:55.646147 SW Impedance : PASS
5952 22:11:55.649893 DUTY Scan : NO K
5953 22:11:55.649976 ZQ Calibration : PASS
5954 22:11:55.653133 Jitter Meter : NO K
5955 22:11:55.653216 CBT Training : PASS
5956 22:11:55.656255 Write leveling : PASS
5957 22:11:55.659848 RX DQS gating : PASS
5958 22:11:55.659930 RX DQ/DQS(RDDQC) : PASS
5959 22:11:55.663049 TX DQ/DQS : PASS
5960 22:11:55.666303 RX DATLAT : PASS
5961 22:11:55.666429 RX DQ/DQS(Engine): PASS
5962 22:11:55.669401 TX OE : NO K
5963 22:11:55.669538 All Pass.
5964 22:11:55.669655
5965 22:11:55.672997 CH 0, Rank 1
5966 22:11:55.673133 SW Impedance : PASS
5967 22:11:55.676072 DUTY Scan : NO K
5968 22:11:55.679402 ZQ Calibration : PASS
5969 22:11:55.679523 Jitter Meter : NO K
5970 22:11:55.682868 CBT Training : PASS
5971 22:11:55.686376 Write leveling : PASS
5972 22:11:55.686497 RX DQS gating : PASS
5973 22:11:55.689370 RX DQ/DQS(RDDQC) : PASS
5974 22:11:55.692961 TX DQ/DQS : PASS
5975 22:11:55.693085 RX DATLAT : PASS
5976 22:11:55.696229 RX DQ/DQS(Engine): PASS
5977 22:11:55.699301 TX OE : NO K
5978 22:11:55.699424 All Pass.
5979 22:11:55.699539
5980 22:11:55.699649 CH 1, Rank 0
5981 22:11:55.702647 SW Impedance : PASS
5982 22:11:55.705931 DUTY Scan : NO K
5983 22:11:55.706052 ZQ Calibration : PASS
5984 22:11:55.709803 Jitter Meter : NO K
5985 22:11:55.709925 CBT Training : PASS
5986 22:11:55.712910 Write leveling : PASS
5987 22:11:55.716562 RX DQS gating : PASS
5988 22:11:55.716687 RX DQ/DQS(RDDQC) : PASS
5989 22:11:55.719289 TX DQ/DQS : PASS
5990 22:11:55.722911 RX DATLAT : PASS
5991 22:11:55.723040 RX DQ/DQS(Engine): PASS
5992 22:11:55.726207 TX OE : NO K
5993 22:11:55.726333 All Pass.
5994 22:11:55.726448
5995 22:11:55.729382 CH 1, Rank 1
5996 22:11:55.729507 SW Impedance : PASS
5997 22:11:55.732787 DUTY Scan : NO K
5998 22:11:55.735928 ZQ Calibration : PASS
5999 22:11:55.736007 Jitter Meter : NO K
6000 22:11:55.739224 CBT Training : PASS
6001 22:11:55.742711 Write leveling : PASS
6002 22:11:55.742788 RX DQS gating : PASS
6003 22:11:55.745895 RX DQ/DQS(RDDQC) : PASS
6004 22:11:55.749649 TX DQ/DQS : PASS
6005 22:11:55.749776 RX DATLAT : PASS
6006 22:11:55.752874 RX DQ/DQS(Engine): PASS
6007 22:11:55.752996 TX OE : NO K
6008 22:11:55.755938 All Pass.
6009 22:11:55.756062
6010 22:11:55.756169 DramC Write-DBI off
6011 22:11:55.759314 PER_BANK_REFRESH: Hybrid Mode
6012 22:11:55.762877 TX_TRACKING: ON
6013 22:11:55.769691 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6014 22:11:55.772932 [FAST_K] Save calibration result to emmc
6015 22:11:55.779233 dramc_set_vcore_voltage set vcore to 650000
6016 22:11:55.779366 Read voltage for 400, 6
6017 22:11:55.779480 Vio18 = 0
6018 22:11:55.782375 Vcore = 650000
6019 22:11:55.782492 Vdram = 0
6020 22:11:55.782604 Vddq = 0
6021 22:11:55.785829 Vmddr = 0
6022 22:11:55.789208 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6023 22:11:55.795766 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6024 22:11:55.795890 MEM_TYPE=3, freq_sel=20
6025 22:11:55.799079 sv_algorithm_assistance_LP4_800
6026 22:11:55.806071 ============ PULL DRAM RESETB DOWN ============
6027 22:11:55.809200 ========== PULL DRAM RESETB DOWN end =========
6028 22:11:55.812868 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6029 22:11:55.815788 ===================================
6030 22:11:55.819527 LPDDR4 DRAM CONFIGURATION
6031 22:11:55.822791 ===================================
6032 22:11:55.825814 EX_ROW_EN[0] = 0x0
6033 22:11:55.825935 EX_ROW_EN[1] = 0x0
6034 22:11:55.829362 LP4Y_EN = 0x0
6035 22:11:55.829483 WORK_FSP = 0x0
6036 22:11:55.832553 WL = 0x2
6037 22:11:55.832665 RL = 0x2
6038 22:11:55.836055 BL = 0x2
6039 22:11:55.836177 RPST = 0x0
6040 22:11:55.839763 RD_PRE = 0x0
6041 22:11:55.839884 WR_PRE = 0x1
6042 22:11:55.842982 WR_PST = 0x0
6043 22:11:55.843100 DBI_WR = 0x0
6044 22:11:55.845918 DBI_RD = 0x0
6045 22:11:55.846088 OTF = 0x1
6046 22:11:55.849456 ===================================
6047 22:11:55.852957 ===================================
6048 22:11:55.856201 ANA top config
6049 22:11:55.859576 ===================================
6050 22:11:55.859680 DLL_ASYNC_EN = 0
6051 22:11:55.862786 ALL_SLAVE_EN = 1
6052 22:11:55.866302 NEW_RANK_MODE = 1
6053 22:11:55.869585 DLL_IDLE_MODE = 1
6054 22:11:55.872895 LP45_APHY_COMB_EN = 1
6055 22:11:55.873006 TX_ODT_DIS = 1
6056 22:11:55.876018 NEW_8X_MODE = 1
6057 22:11:55.879094 ===================================
6058 22:11:55.882456 ===================================
6059 22:11:55.885747 data_rate = 800
6060 22:11:55.888975 CKR = 1
6061 22:11:55.892673 DQ_P2S_RATIO = 4
6062 22:11:55.895812 ===================================
6063 22:11:55.895937 CA_P2S_RATIO = 4
6064 22:11:55.898989 DQ_CA_OPEN = 0
6065 22:11:55.902144 DQ_SEMI_OPEN = 1
6066 22:11:55.905772 CA_SEMI_OPEN = 1
6067 22:11:55.909024 CA_FULL_RATE = 0
6068 22:11:55.912361 DQ_CKDIV4_EN = 0
6069 22:11:55.912434 CA_CKDIV4_EN = 1
6070 22:11:55.915464 CA_PREDIV_EN = 0
6071 22:11:55.918925 PH8_DLY = 0
6072 22:11:55.922293 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6073 22:11:55.925641 DQ_AAMCK_DIV = 0
6074 22:11:55.928773 CA_AAMCK_DIV = 0
6075 22:11:55.928849 CA_ADMCK_DIV = 4
6076 22:11:55.932434 DQ_TRACK_CA_EN = 0
6077 22:11:55.935533 CA_PICK = 800
6078 22:11:55.938690 CA_MCKIO = 400
6079 22:11:55.942256 MCKIO_SEMI = 400
6080 22:11:55.945505 PLL_FREQ = 3016
6081 22:11:55.948858 DQ_UI_PI_RATIO = 32
6082 22:11:55.951934 CA_UI_PI_RATIO = 32
6083 22:11:55.955292 ===================================
6084 22:11:55.958988 ===================================
6085 22:11:55.959075 memory_type:LPDDR4
6086 22:11:55.962222 GP_NUM : 10
6087 22:11:55.965425 SRAM_EN : 1
6088 22:11:55.965500 MD32_EN : 0
6089 22:11:55.969011 ===================================
6090 22:11:55.972072 [ANA_INIT] >>>>>>>>>>>>>>
6091 22:11:55.975440 <<<<<< [CONFIGURE PHASE]: ANA_TX
6092 22:11:55.978768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6093 22:11:55.982347 ===================================
6094 22:11:55.982421 data_rate = 800,PCW = 0X7400
6095 22:11:55.985458 ===================================
6096 22:11:55.988672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6097 22:11:55.995551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 22:11:56.008606 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 22:11:56.012263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6100 22:11:56.015168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6101 22:11:56.018749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6102 22:11:56.022017 [ANA_INIT] flow start
6103 22:11:56.022099 [ANA_INIT] PLL >>>>>>>>
6104 22:11:56.025293 [ANA_INIT] PLL <<<<<<<<
6105 22:11:56.028925 [ANA_INIT] MIDPI >>>>>>>>
6106 22:11:56.031962 [ANA_INIT] MIDPI <<<<<<<<
6107 22:11:56.032041 [ANA_INIT] DLL >>>>>>>>
6108 22:11:56.035148 [ANA_INIT] flow end
6109 22:11:56.038457 ============ LP4 DIFF to SE enter ============
6110 22:11:56.041779 ============ LP4 DIFF to SE exit ============
6111 22:11:56.045188 [ANA_INIT] <<<<<<<<<<<<<
6112 22:11:56.048344 [Flow] Enable top DCM control >>>>>
6113 22:11:56.051769 [Flow] Enable top DCM control <<<<<
6114 22:11:56.054924 Enable DLL master slave shuffle
6115 22:11:56.058196 ==============================================================
6116 22:11:56.061716 Gating Mode config
6117 22:11:56.068426 ==============================================================
6118 22:11:56.068511 Config description:
6119 22:11:56.078586 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6120 22:11:56.085002 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6121 22:11:56.091815 SELPH_MODE 0: By rank 1: By Phase
6122 22:11:56.095043 ==============================================================
6123 22:11:56.098067 GAT_TRACK_EN = 0
6124 22:11:56.101731 RX_GATING_MODE = 2
6125 22:11:56.104964 RX_GATING_TRACK_MODE = 2
6126 22:11:56.108314 SELPH_MODE = 1
6127 22:11:56.111303 PICG_EARLY_EN = 1
6128 22:11:56.115023 VALID_LAT_VALUE = 1
6129 22:11:56.118074 ==============================================================
6130 22:11:56.121549 Enter into Gating configuration >>>>
6131 22:11:56.124776 Exit from Gating configuration <<<<
6132 22:11:56.128034 Enter into DVFS_PRE_config >>>>>
6133 22:11:56.141351 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6134 22:11:56.144950 Exit from DVFS_PRE_config <<<<<
6135 22:11:56.148269 Enter into PICG configuration >>>>
6136 22:11:56.148395 Exit from PICG configuration <<<<
6137 22:11:56.151636 [RX_INPUT] configuration >>>>>
6138 22:11:56.154739 [RX_INPUT] configuration <<<<<
6139 22:11:56.161682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6140 22:11:56.164727 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6141 22:11:56.171106 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 22:11:56.177914 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 22:11:56.184828 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 22:11:56.190957 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 22:11:56.194638 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6146 22:11:56.197837 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6147 22:11:56.201128 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6148 22:11:56.207922 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6149 22:11:56.211300 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6150 22:11:56.214817 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6151 22:11:56.217916 ===================================
6152 22:11:56.221115 LPDDR4 DRAM CONFIGURATION
6153 22:11:56.224409 ===================================
6154 22:11:56.228115 EX_ROW_EN[0] = 0x0
6155 22:11:56.228244 EX_ROW_EN[1] = 0x0
6156 22:11:56.231498 LP4Y_EN = 0x0
6157 22:11:56.231636 WORK_FSP = 0x0
6158 22:11:56.234776 WL = 0x2
6159 22:11:56.234922 RL = 0x2
6160 22:11:56.237909 BL = 0x2
6161 22:11:56.238040 RPST = 0x0
6162 22:11:56.241136 RD_PRE = 0x0
6163 22:11:56.241261 WR_PRE = 0x1
6164 22:11:56.244508 WR_PST = 0x0
6165 22:11:56.244615 DBI_WR = 0x0
6166 22:11:56.248302 DBI_RD = 0x0
6167 22:11:56.248426 OTF = 0x1
6168 22:11:56.251499 ===================================
6169 22:11:56.254588 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6170 22:11:56.261190 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6171 22:11:56.264518 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 22:11:56.268347 ===================================
6173 22:11:56.271270 LPDDR4 DRAM CONFIGURATION
6174 22:11:56.274910 ===================================
6175 22:11:56.275032 EX_ROW_EN[0] = 0x10
6176 22:11:56.278123 EX_ROW_EN[1] = 0x0
6177 22:11:56.278247 LP4Y_EN = 0x0
6178 22:11:56.281347 WORK_FSP = 0x0
6179 22:11:56.284780 WL = 0x2
6180 22:11:56.284906 RL = 0x2
6181 22:11:56.287970 BL = 0x2
6182 22:11:56.288095 RPST = 0x0
6183 22:11:56.291114 RD_PRE = 0x0
6184 22:11:56.291239 WR_PRE = 0x1
6185 22:11:56.294810 WR_PST = 0x0
6186 22:11:56.294933 DBI_WR = 0x0
6187 22:11:56.297899 DBI_RD = 0x0
6188 22:11:56.297988 OTF = 0x1
6189 22:11:56.301247 ===================================
6190 22:11:56.307642 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6191 22:11:56.311690 nWR fixed to 30
6192 22:11:56.315234 [ModeRegInit_LP4] CH0 RK0
6193 22:11:56.315361 [ModeRegInit_LP4] CH0 RK1
6194 22:11:56.318466 [ModeRegInit_LP4] CH1 RK0
6195 22:11:56.321899 [ModeRegInit_LP4] CH1 RK1
6196 22:11:56.322011 match AC timing 19
6197 22:11:56.328458 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6198 22:11:56.332124 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6199 22:11:56.335023 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6200 22:11:56.341855 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6201 22:11:56.345285 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6202 22:11:56.345361 ==
6203 22:11:56.348441 Dram Type= 6, Freq= 0, CH_0, rank 0
6204 22:11:56.352068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6205 22:11:56.352144 ==
6206 22:11:56.358703 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6207 22:11:56.365445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6208 22:11:56.368786 [CA 0] Center 36 (8~64) winsize 57
6209 22:11:56.371911 [CA 1] Center 36 (8~64) winsize 57
6210 22:11:56.372036 [CA 2] Center 36 (8~64) winsize 57
6211 22:11:56.374995 [CA 3] Center 36 (8~64) winsize 57
6212 22:11:56.378683 [CA 4] Center 36 (8~64) winsize 57
6213 22:11:56.381986 [CA 5] Center 36 (8~64) winsize 57
6214 22:11:56.382110
6215 22:11:56.385216 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6216 22:11:56.388549
6217 22:11:56.391780 [CATrainingPosCal] consider 1 rank data
6218 22:11:56.391904 u2DelayCellTimex100 = 270/100 ps
6219 22:11:56.398131 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 22:11:56.401570 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 22:11:56.404791 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 22:11:56.408131 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 22:11:56.411520 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 22:11:56.414918 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 22:11:56.415040
6226 22:11:56.418651 CA PerBit enable=1, Macro0, CA PI delay=36
6227 22:11:56.418772
6228 22:11:56.421560 [CBTSetCACLKResult] CA Dly = 36
6229 22:11:56.425138 CS Dly: 1 (0~32)
6230 22:11:56.425265 ==
6231 22:11:56.428369 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 22:11:56.431564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 22:11:56.431696 ==
6234 22:11:56.438419 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 22:11:56.441545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 22:11:56.444790 [CA 0] Center 36 (8~64) winsize 57
6237 22:11:56.448278 [CA 1] Center 36 (8~64) winsize 57
6238 22:11:56.451640 [CA 2] Center 36 (8~64) winsize 57
6239 22:11:56.454810 [CA 3] Center 36 (8~64) winsize 57
6240 22:11:56.458399 [CA 4] Center 36 (8~64) winsize 57
6241 22:11:56.461514 [CA 5] Center 36 (8~64) winsize 57
6242 22:11:56.461597
6243 22:11:56.464738 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 22:11:56.464818
6245 22:11:56.468090 [CATrainingPosCal] consider 2 rank data
6246 22:11:56.471287 u2DelayCellTimex100 = 270/100 ps
6247 22:11:56.474607 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 22:11:56.478396 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 22:11:56.481323 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 22:11:56.488516 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 22:11:56.491880 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 22:11:56.494819 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 22:11:56.494904
6254 22:11:56.497959 CA PerBit enable=1, Macro0, CA PI delay=36
6255 22:11:56.498044
6256 22:11:56.501452 [CBTSetCACLKResult] CA Dly = 36
6257 22:11:56.501582 CS Dly: 1 (0~32)
6258 22:11:56.501699
6259 22:11:56.504657 ----->DramcWriteLeveling(PI) begin...
6260 22:11:56.504782 ==
6261 22:11:56.507941 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 22:11:56.514399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 22:11:56.514529 ==
6264 22:11:56.517934 Write leveling (Byte 0): 40 => 8
6265 22:11:56.521562 Write leveling (Byte 1): 40 => 8
6266 22:11:56.521690 DramcWriteLeveling(PI) end<-----
6267 22:11:56.521803
6268 22:11:56.524605 ==
6269 22:11:56.527811 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 22:11:56.530991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 22:11:56.531118 ==
6272 22:11:56.534654 [Gating] SW mode calibration
6273 22:11:56.540945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6274 22:11:56.544283 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6275 22:11:56.551299 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 22:11:56.554477 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 22:11:56.557833 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 22:11:56.564543 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 22:11:56.567796 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 22:11:56.571207 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 22:11:56.577743 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 22:11:56.580970 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 22:11:56.584196 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 22:11:56.587795 Total UI for P1: 0, mck2ui 16
6285 22:11:56.591160 best dqsien dly found for B0: ( 0, 14, 24)
6286 22:11:56.594314 Total UI for P1: 0, mck2ui 16
6287 22:11:56.597652 best dqsien dly found for B1: ( 0, 14, 24)
6288 22:11:56.600923 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6289 22:11:56.604307 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6290 22:11:56.604429
6291 22:11:56.610729 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 22:11:56.613903 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 22:11:56.614021 [Gating] SW calibration Done
6294 22:11:56.617811 ==
6295 22:11:56.620953 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 22:11:56.624104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 22:11:56.624237 ==
6298 22:11:56.624350 RX Vref Scan: 0
6299 22:11:56.624464
6300 22:11:56.627483 RX Vref 0 -> 0, step: 1
6301 22:11:56.627615
6302 22:11:56.630699 RX Delay -410 -> 252, step: 16
6303 22:11:56.633897 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6304 22:11:56.637482 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6305 22:11:56.643929 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6306 22:11:56.647116 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6307 22:11:56.650689 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6308 22:11:56.653909 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6309 22:11:56.660417 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6310 22:11:56.664043 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6311 22:11:56.666984 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6312 22:11:56.670615 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6313 22:11:56.676983 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6314 22:11:56.680470 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6315 22:11:56.683899 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6316 22:11:56.690681 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6317 22:11:56.694171 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6318 22:11:56.697225 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6319 22:11:56.697321 ==
6320 22:11:56.700339 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 22:11:56.704165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 22:11:56.704243 ==
6323 22:11:56.707480 DQS Delay:
6324 22:11:56.707585 DQS0 = 27, DQS1 = 35
6325 22:11:56.710464 DQM Delay:
6326 22:11:56.710537 DQM0 = 10, DQM1 = 12
6327 22:11:56.710604 DQ Delay:
6328 22:11:56.713938 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6329 22:11:56.717301 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6330 22:11:56.720603 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6331 22:11:56.723893 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6332 22:11:56.724022
6333 22:11:56.724135
6334 22:11:56.724247 ==
6335 22:11:56.727111 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 22:11:56.733743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 22:11:56.733866 ==
6338 22:11:56.733982
6339 22:11:56.734091
6340 22:11:56.734201 TX Vref Scan disable
6341 22:11:56.736829 == TX Byte 0 ==
6342 22:11:56.740732 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 22:11:56.743634 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 22:11:56.746898 == TX Byte 1 ==
6345 22:11:56.750054 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 22:11:56.753898 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 22:11:56.754022 ==
6348 22:11:56.757036 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 22:11:56.763491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 22:11:56.763620 ==
6351 22:11:56.763736
6352 22:11:56.763843
6353 22:11:56.763955 TX Vref Scan disable
6354 22:11:56.766722 == TX Byte 0 ==
6355 22:11:56.770345 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 22:11:56.773600 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 22:11:56.776854 == TX Byte 1 ==
6358 22:11:56.780397 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 22:11:56.783507 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 22:11:56.783633
6361 22:11:56.787097 [DATLAT]
6362 22:11:56.787220 Freq=400, CH0 RK0
6363 22:11:56.787332
6364 22:11:56.790078 DATLAT Default: 0xf
6365 22:11:56.790198 0, 0xFFFF, sum = 0
6366 22:11:56.793221 1, 0xFFFF, sum = 0
6367 22:11:56.793342 2, 0xFFFF, sum = 0
6368 22:11:56.796990 3, 0xFFFF, sum = 0
6369 22:11:56.797118 4, 0xFFFF, sum = 0
6370 22:11:56.800152 5, 0xFFFF, sum = 0
6371 22:11:56.800274 6, 0xFFFF, sum = 0
6372 22:11:56.803729 7, 0xFFFF, sum = 0
6373 22:11:56.803855 8, 0xFFFF, sum = 0
6374 22:11:56.806966 9, 0xFFFF, sum = 0
6375 22:11:56.807074 10, 0xFFFF, sum = 0
6376 22:11:56.810489 11, 0xFFFF, sum = 0
6377 22:11:56.813486 12, 0xFFFF, sum = 0
6378 22:11:56.813613 13, 0x0, sum = 1
6379 22:11:56.817045 14, 0x0, sum = 2
6380 22:11:56.817170 15, 0x0, sum = 3
6381 22:11:56.817286 16, 0x0, sum = 4
6382 22:11:56.820275 best_step = 14
6383 22:11:56.820403
6384 22:11:56.820517 ==
6385 22:11:56.823467 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 22:11:56.826725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 22:11:56.826853 ==
6388 22:11:56.829976 RX Vref Scan: 1
6389 22:11:56.830099
6390 22:11:56.830212 RX Vref 0 -> 0, step: 1
6391 22:11:56.833245
6392 22:11:56.833370 RX Delay -311 -> 252, step: 8
6393 22:11:56.833482
6394 22:11:56.836773 Set Vref, RX VrefLevel [Byte0]: 54
6395 22:11:56.839907 [Byte1]: 53
6396 22:11:56.845119
6397 22:11:56.845244 Final RX Vref Byte 0 = 54 to rank0
6398 22:11:56.848413 Final RX Vref Byte 1 = 53 to rank0
6399 22:11:56.851636 Final RX Vref Byte 0 = 54 to rank1
6400 22:11:56.854905 Final RX Vref Byte 1 = 53 to rank1==
6401 22:11:56.858423 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 22:11:56.864854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 22:11:56.864983 ==
6404 22:11:56.865098 DQS Delay:
6405 22:11:56.868093 DQS0 = 28, DQS1 = 36
6406 22:11:56.868216 DQM Delay:
6407 22:11:56.868329 DQM0 = 11, DQM1 = 12
6408 22:11:56.871782 DQ Delay:
6409 22:11:56.874845 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6410 22:11:56.874971 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6411 22:11:56.878556 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6412 22:11:56.881696 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6413 22:11:56.881820
6414 22:11:56.884786
6415 22:11:56.891801 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6416 22:11:56.894690 CH0 RK0: MR19=C0C, MR18=CBB8
6417 22:11:56.901165 CH0_RK0: MR19=0xC0C, MR18=0xCBB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6418 22:11:56.901293 ==
6419 22:11:56.904952 Dram Type= 6, Freq= 0, CH_0, rank 1
6420 22:11:56.907745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 22:11:56.907870 ==
6422 22:11:56.911418 [Gating] SW mode calibration
6423 22:11:56.918016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6424 22:11:56.924748 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6425 22:11:56.927685 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 22:11:56.931290 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 22:11:56.937947 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 22:11:56.941195 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 22:11:56.944228 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 22:11:56.950990 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 22:11:56.954526 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 22:11:56.957925 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 22:11:56.964185 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 22:11:56.964268 Total UI for P1: 0, mck2ui 16
6435 22:11:56.970689 best dqsien dly found for B0: ( 0, 14, 24)
6436 22:11:56.970765 Total UI for P1: 0, mck2ui 16
6437 22:11:56.974425 best dqsien dly found for B1: ( 0, 14, 24)
6438 22:11:56.980747 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6439 22:11:56.983992 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6440 22:11:56.984118
6441 22:11:56.987474 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 22:11:56.990721 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 22:11:56.994397 [Gating] SW calibration Done
6444 22:11:56.994523 ==
6445 22:11:56.997309 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 22:11:57.000888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 22:11:57.001014 ==
6448 22:11:57.004283 RX Vref Scan: 0
6449 22:11:57.004406
6450 22:11:57.004517 RX Vref 0 -> 0, step: 1
6451 22:11:57.004629
6452 22:11:57.007550 RX Delay -410 -> 252, step: 16
6453 22:11:57.013978 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6454 22:11:57.017182 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6455 22:11:57.020839 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6456 22:11:57.023968 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6457 22:11:57.030740 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6458 22:11:57.034091 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6459 22:11:57.037539 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6460 22:11:57.040519 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6461 22:11:57.044136 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6462 22:11:57.050418 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6463 22:11:57.053892 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6464 22:11:57.057406 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6465 22:11:57.063535 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6466 22:11:57.067189 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6467 22:11:57.070604 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6468 22:11:57.073703 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6469 22:11:57.073780 ==
6470 22:11:57.077028 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 22:11:57.083765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 22:11:57.083879 ==
6473 22:11:57.083953 DQS Delay:
6474 22:11:57.087214 DQS0 = 27, DQS1 = 35
6475 22:11:57.087287 DQM Delay:
6476 22:11:57.087348 DQM0 = 12, DQM1 = 11
6477 22:11:57.090218 DQ Delay:
6478 22:11:57.094000 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6479 22:11:57.094078 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6480 22:11:57.096918 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6481 22:11:57.100573 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6482 22:11:57.103675
6483 22:11:57.103758
6484 22:11:57.103821 ==
6485 22:11:57.106823 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 22:11:57.110055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 22:11:57.110134 ==
6488 22:11:57.110198
6489 22:11:57.110258
6490 22:11:57.113754 TX Vref Scan disable
6491 22:11:57.113829 == TX Byte 0 ==
6492 22:11:57.116901 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6493 22:11:57.123474 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6494 22:11:57.123559 == TX Byte 1 ==
6495 22:11:57.126787 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6496 22:11:57.133761 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6497 22:11:57.133846 ==
6498 22:11:57.136983 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 22:11:57.140126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 22:11:57.140212 ==
6501 22:11:57.140277
6502 22:11:57.140337
6503 22:11:57.143266 TX Vref Scan disable
6504 22:11:57.143349 == TX Byte 0 ==
6505 22:11:57.146997 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6506 22:11:57.153292 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6507 22:11:57.153376 == TX Byte 1 ==
6508 22:11:57.156730 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6509 22:11:57.163241 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6510 22:11:57.163328
6511 22:11:57.163393 [DATLAT]
6512 22:11:57.163454 Freq=400, CH0 RK1
6513 22:11:57.167038
6514 22:11:57.167121 DATLAT Default: 0xe
6515 22:11:57.170213 0, 0xFFFF, sum = 0
6516 22:11:57.170298 1, 0xFFFF, sum = 0
6517 22:11:57.173372 2, 0xFFFF, sum = 0
6518 22:11:57.173457 3, 0xFFFF, sum = 0
6519 22:11:57.176609 4, 0xFFFF, sum = 0
6520 22:11:57.176694 5, 0xFFFF, sum = 0
6521 22:11:57.180015 6, 0xFFFF, sum = 0
6522 22:11:57.180100 7, 0xFFFF, sum = 0
6523 22:11:57.183154 8, 0xFFFF, sum = 0
6524 22:11:57.183239 9, 0xFFFF, sum = 0
6525 22:11:57.186868 10, 0xFFFF, sum = 0
6526 22:11:57.186953 11, 0xFFFF, sum = 0
6527 22:11:57.189824 12, 0xFFFF, sum = 0
6528 22:11:57.189909 13, 0x0, sum = 1
6529 22:11:57.193070 14, 0x0, sum = 2
6530 22:11:57.193155 15, 0x0, sum = 3
6531 22:11:57.196532 16, 0x0, sum = 4
6532 22:11:57.196645 best_step = 14
6533 22:11:57.196739
6534 22:11:57.196833 ==
6535 22:11:57.199751 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 22:11:57.206524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 22:11:57.206636 ==
6538 22:11:57.206731 RX Vref Scan: 0
6539 22:11:57.206820
6540 22:11:57.210094 RX Vref 0 -> 0, step: 1
6541 22:11:57.210177
6542 22:11:57.213425 RX Delay -311 -> 252, step: 8
6543 22:11:57.219885 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6544 22:11:57.223012 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6545 22:11:57.226318 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6546 22:11:57.229577 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6547 22:11:57.236588 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6548 22:11:57.239602 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6549 22:11:57.243105 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6550 22:11:57.246280 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6551 22:11:57.249599 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6552 22:11:57.256419 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6553 22:11:57.259374 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6554 22:11:57.263132 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6555 22:11:57.269492 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6556 22:11:57.273247 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6557 22:11:57.276176 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6558 22:11:57.279396 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6559 22:11:57.279480 ==
6560 22:11:57.282819 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 22:11:57.289658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 22:11:57.289774 ==
6563 22:11:57.289844 DQS Delay:
6564 22:11:57.292819 DQS0 = 24, DQS1 = 32
6565 22:11:57.292906 DQM Delay:
6566 22:11:57.292973 DQM0 = 9, DQM1 = 9
6567 22:11:57.296108 DQ Delay:
6568 22:11:57.299652 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6569 22:11:57.302801 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6570 22:11:57.302885 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6571 22:11:57.305907 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6572 22:11:57.309825
6573 22:11:57.309901
6574 22:11:57.315937 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf5e, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6575 22:11:57.319139 CH0 RK1: MR19=C0C, MR18=BF5E
6576 22:11:57.326100 CH0_RK1: MR19=0xC0C, MR18=0xBF5E, DQSOSC=386, MR23=63, INC=396, DEC=264
6577 22:11:57.329343 [RxdqsGatingPostProcess] freq 400
6578 22:11:57.332777 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6579 22:11:57.336004 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 22:11:57.339266 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 22:11:57.342934 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 22:11:57.346130 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 22:11:57.349249 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 22:11:57.352449 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 22:11:57.355802 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 22:11:57.359076 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 22:11:57.362481 Pre-setting of DQS Precalculation
6588 22:11:57.365747 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6589 22:11:57.365832 ==
6590 22:11:57.369007 Dram Type= 6, Freq= 0, CH_1, rank 0
6591 22:11:57.375689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 22:11:57.375773 ==
6593 22:11:57.378879 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6594 22:11:57.385800 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6595 22:11:57.389035 [CA 0] Center 36 (8~64) winsize 57
6596 22:11:57.392592 [CA 1] Center 36 (8~64) winsize 57
6597 22:11:57.395697 [CA 2] Center 36 (8~64) winsize 57
6598 22:11:57.399322 [CA 3] Center 36 (8~64) winsize 57
6599 22:11:57.402474 [CA 4] Center 36 (8~64) winsize 57
6600 22:11:57.405925 [CA 5] Center 36 (8~64) winsize 57
6601 22:11:57.406012
6602 22:11:57.408947 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6603 22:11:57.409021
6604 22:11:57.412611 [CATrainingPosCal] consider 1 rank data
6605 22:11:57.415775 u2DelayCellTimex100 = 270/100 ps
6606 22:11:57.419424 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 22:11:57.422198 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 22:11:57.425427 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 22:11:57.429161 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 22:11:57.432427 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 22:11:57.435711 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 22:11:57.435814
6613 22:11:57.442176 CA PerBit enable=1, Macro0, CA PI delay=36
6614 22:11:57.442261
6615 22:11:57.442327 [CBTSetCACLKResult] CA Dly = 36
6616 22:11:57.445921 CS Dly: 1 (0~32)
6617 22:11:57.446004 ==
6618 22:11:57.448738 Dram Type= 6, Freq= 0, CH_1, rank 1
6619 22:11:57.452447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 22:11:57.452535 ==
6621 22:11:57.458849 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 22:11:57.465380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6623 22:11:57.469105 [CA 0] Center 36 (8~64) winsize 57
6624 22:11:57.472122 [CA 1] Center 36 (8~64) winsize 57
6625 22:11:57.475424 [CA 2] Center 36 (8~64) winsize 57
6626 22:11:57.475530 [CA 3] Center 36 (8~64) winsize 57
6627 22:11:57.478676 [CA 4] Center 36 (8~64) winsize 57
6628 22:11:57.482462 [CA 5] Center 36 (8~64) winsize 57
6629 22:11:57.482538
6630 22:11:57.485491 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6631 22:11:57.488862
6632 22:11:57.492062 [CATrainingPosCal] consider 2 rank data
6633 22:11:57.492150 u2DelayCellTimex100 = 270/100 ps
6634 22:11:57.499035 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 22:11:57.502381 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 22:11:57.505667 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 22:11:57.508833 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 22:11:57.511899 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 22:11:57.515264 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 22:11:57.515347
6641 22:11:57.519144 CA PerBit enable=1, Macro0, CA PI delay=36
6642 22:11:57.519227
6643 22:11:57.521781 [CBTSetCACLKResult] CA Dly = 36
6644 22:11:57.525196 CS Dly: 1 (0~32)
6645 22:11:57.525327
6646 22:11:57.529177 ----->DramcWriteLeveling(PI) begin...
6647 22:11:57.529308 ==
6648 22:11:57.531779 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 22:11:57.535177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 22:11:57.535303 ==
6651 22:11:57.538419 Write leveling (Byte 0): 40 => 8
6652 22:11:57.542248 Write leveling (Byte 1): 40 => 8
6653 22:11:57.545384 DramcWriteLeveling(PI) end<-----
6654 22:11:57.545510
6655 22:11:57.545626 ==
6656 22:11:57.548822 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 22:11:57.552026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 22:11:57.552152 ==
6659 22:11:57.555390 [Gating] SW mode calibration
6660 22:11:57.561590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6661 22:11:57.568269 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6662 22:11:57.571832 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 22:11:57.574972 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 22:11:57.581686 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 22:11:57.585343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 22:11:57.588719 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 22:11:57.595095 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 22:11:57.598560 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 22:11:57.601766 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 22:11:57.608527 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 22:11:57.608612 Total UI for P1: 0, mck2ui 16
6672 22:11:57.615222 best dqsien dly found for B0: ( 0, 14, 24)
6673 22:11:57.615306 Total UI for P1: 0, mck2ui 16
6674 22:11:57.618363 best dqsien dly found for B1: ( 0, 14, 24)
6675 22:11:57.624895 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6676 22:11:57.628442 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6677 22:11:57.628527
6678 22:11:57.631925 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 22:11:57.634859 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 22:11:57.638284 [Gating] SW calibration Done
6681 22:11:57.638399 ==
6682 22:11:57.641810 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 22:11:57.645080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 22:11:57.645194 ==
6685 22:11:57.648081 RX Vref Scan: 0
6686 22:11:57.648193
6687 22:11:57.648286 RX Vref 0 -> 0, step: 1
6688 22:11:57.648376
6689 22:11:57.651687 RX Delay -410 -> 252, step: 16
6690 22:11:57.658669 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6691 22:11:57.661844 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6692 22:11:57.665081 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6693 22:11:57.668299 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6694 22:11:57.674598 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6695 22:11:57.678282 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6696 22:11:57.681777 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6697 22:11:57.684730 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6698 22:11:57.688269 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6699 22:11:57.694762 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6700 22:11:57.697992 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6701 22:11:57.701669 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6702 22:11:57.708074 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6703 22:11:57.711705 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6704 22:11:57.714690 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6705 22:11:57.718147 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6706 22:11:57.718226 ==
6707 22:11:57.721414 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 22:11:57.728054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 22:11:57.728142 ==
6710 22:11:57.728209 DQS Delay:
6711 22:11:57.731491 DQS0 = 35, DQS1 = 35
6712 22:11:57.731598 DQM Delay:
6713 22:11:57.731665 DQM0 = 17, DQM1 = 13
6714 22:11:57.735143 DQ Delay:
6715 22:11:57.738054 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6716 22:11:57.741217 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6717 22:11:57.741289 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6718 22:11:57.748110 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6719 22:11:57.748188
6720 22:11:57.748250
6721 22:11:57.748309 ==
6722 22:11:57.751661 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 22:11:57.754484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 22:11:57.754588 ==
6725 22:11:57.754680
6726 22:11:57.754768
6727 22:11:57.758398 TX Vref Scan disable
6728 22:11:57.758476 == TX Byte 0 ==
6729 22:11:57.761558 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 22:11:57.768121 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 22:11:57.768202 == TX Byte 1 ==
6732 22:11:57.771525 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 22:11:57.777947 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 22:11:57.778028 ==
6735 22:11:57.781159 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 22:11:57.784621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 22:11:57.784712 ==
6738 22:11:57.784776
6739 22:11:57.784834
6740 22:11:57.787992 TX Vref Scan disable
6741 22:11:57.788065 == TX Byte 0 ==
6742 22:11:57.791771 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 22:11:57.798097 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 22:11:57.798179 == TX Byte 1 ==
6745 22:11:57.801686 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 22:11:57.808157 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 22:11:57.808240
6748 22:11:57.808305 [DATLAT]
6749 22:11:57.808364 Freq=400, CH1 RK0
6750 22:11:57.811419
6751 22:11:57.811500 DATLAT Default: 0xf
6752 22:11:57.814515 0, 0xFFFF, sum = 0
6753 22:11:57.814595 1, 0xFFFF, sum = 0
6754 22:11:57.818168 2, 0xFFFF, sum = 0
6755 22:11:57.818249 3, 0xFFFF, sum = 0
6756 22:11:57.821721 4, 0xFFFF, sum = 0
6757 22:11:57.821796 5, 0xFFFF, sum = 0
6758 22:11:57.824589 6, 0xFFFF, sum = 0
6759 22:11:57.824669 7, 0xFFFF, sum = 0
6760 22:11:57.828325 8, 0xFFFF, sum = 0
6761 22:11:57.828407 9, 0xFFFF, sum = 0
6762 22:11:57.831092 10, 0xFFFF, sum = 0
6763 22:11:57.831169 11, 0xFFFF, sum = 0
6764 22:11:57.834917 12, 0xFFFF, sum = 0
6765 22:11:57.834997 13, 0x0, sum = 1
6766 22:11:57.838169 14, 0x0, sum = 2
6767 22:11:57.838249 15, 0x0, sum = 3
6768 22:11:57.841421 16, 0x0, sum = 4
6769 22:11:57.841500 best_step = 14
6770 22:11:57.841564
6771 22:11:57.841623 ==
6772 22:11:57.844760 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 22:11:57.851319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 22:11:57.851425 ==
6775 22:11:57.851522 RX Vref Scan: 1
6776 22:11:57.851622
6777 22:11:57.854426 RX Vref 0 -> 0, step: 1
6778 22:11:57.854509
6779 22:11:57.857840 RX Delay -311 -> 252, step: 8
6780 22:11:57.857910
6781 22:11:57.860779 Set Vref, RX VrefLevel [Byte0]: 50
6782 22:11:57.864161 [Byte1]: 52
6783 22:11:57.864239
6784 22:11:57.867503 Final RX Vref Byte 0 = 50 to rank0
6785 22:11:57.871426 Final RX Vref Byte 1 = 52 to rank0
6786 22:11:57.874592 Final RX Vref Byte 0 = 50 to rank1
6787 22:11:57.877898 Final RX Vref Byte 1 = 52 to rank1==
6788 22:11:57.881013 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 22:11:57.884401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 22:11:57.887894 ==
6791 22:11:57.887976 DQS Delay:
6792 22:11:57.888040 DQS0 = 28, DQS1 = 32
6793 22:11:57.890876 DQM Delay:
6794 22:11:57.891029 DQM0 = 11, DQM1 = 12
6795 22:11:57.894122 DQ Delay:
6796 22:11:57.894231 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6797 22:11:57.897455 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6798 22:11:57.900751 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6799 22:11:57.904079 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6800 22:11:57.904160
6801 22:11:57.904224
6802 22:11:57.914213 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6803 22:11:57.917340 CH1 RK0: MR19=C0C, MR18=8EC6
6804 22:11:57.923862 CH1_RK0: MR19=0xC0C, MR18=0x8EC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6805 22:11:57.923944 ==
6806 22:11:57.927282 Dram Type= 6, Freq= 0, CH_1, rank 1
6807 22:11:57.930668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 22:11:57.930745 ==
6809 22:11:57.933897 [Gating] SW mode calibration
6810 22:11:57.940755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6811 22:11:57.943826 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6812 22:11:57.950796 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 22:11:57.954029 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 22:11:57.956926 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 22:11:57.963953 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 22:11:57.967057 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 22:11:57.970624 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 22:11:57.977213 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 22:11:57.980450 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 22:11:57.983751 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 22:11:57.986888 Total UI for P1: 0, mck2ui 16
6822 22:11:57.990538 best dqsien dly found for B0: ( 0, 14, 24)
6823 22:11:57.993520 Total UI for P1: 0, mck2ui 16
6824 22:11:57.997245 best dqsien dly found for B1: ( 0, 14, 24)
6825 22:11:58.000567 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6826 22:11:58.003841 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6827 22:11:58.003923
6828 22:11:58.010468 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 22:11:58.013840 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 22:11:58.013922 [Gating] SW calibration Done
6831 22:11:58.017137 ==
6832 22:11:58.020568 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 22:11:58.023471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 22:11:58.023583 ==
6835 22:11:58.023694 RX Vref Scan: 0
6836 22:11:58.023756
6837 22:11:58.027001 RX Vref 0 -> 0, step: 1
6838 22:11:58.027115
6839 22:11:58.030462 RX Delay -410 -> 252, step: 16
6840 22:11:58.033774 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6841 22:11:58.040279 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6842 22:11:58.044049 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6843 22:11:58.047022 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6844 22:11:58.050749 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6845 22:11:58.053889 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6846 22:11:58.060164 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6847 22:11:58.063720 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6848 22:11:58.067255 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6849 22:11:58.070247 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6850 22:11:58.076768 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6851 22:11:58.080215 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6852 22:11:58.083442 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6853 22:11:58.087042 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6854 22:11:58.093804 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6855 22:11:58.097126 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6856 22:11:58.097209 ==
6857 22:11:58.100537 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 22:11:58.103515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 22:11:58.103624 ==
6860 22:11:58.107133 DQS Delay:
6861 22:11:58.107240 DQS0 = 35, DQS1 = 35
6862 22:11:58.110526 DQM Delay:
6863 22:11:58.110625 DQM0 = 19, DQM1 = 14
6864 22:11:58.110747 DQ Delay:
6865 22:11:58.113657 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6866 22:11:58.117023 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6867 22:11:58.120096 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6868 22:11:58.123408 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6869 22:11:58.123491
6870 22:11:58.123596
6871 22:11:58.123678 ==
6872 22:11:58.126870 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 22:11:58.133476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 22:11:58.133561 ==
6875 22:11:58.133626
6876 22:11:58.133686
6877 22:11:58.133744 TX Vref Scan disable
6878 22:11:58.136613 == TX Byte 0 ==
6879 22:11:58.140254 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6880 22:11:58.143416 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6881 22:11:58.146610 == TX Byte 1 ==
6882 22:11:58.150224 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6883 22:11:58.153390 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6884 22:11:58.156569 ==
6885 22:11:58.156653 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 22:11:58.163339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 22:11:58.163423 ==
6888 22:11:58.163488
6889 22:11:58.163548
6890 22:11:58.166584 TX Vref Scan disable
6891 22:11:58.166682 == TX Byte 0 ==
6892 22:11:58.169832 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6893 22:11:58.173510 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6894 22:11:58.176760 == TX Byte 1 ==
6895 22:11:58.180170 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6896 22:11:58.183577 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6897 22:11:58.183681
6898 22:11:58.186971 [DATLAT]
6899 22:11:58.187054 Freq=400, CH1 RK1
6900 22:11:58.187118
6901 22:11:58.189961 DATLAT Default: 0xe
6902 22:11:58.190077 0, 0xFFFF, sum = 0
6903 22:11:58.193777 1, 0xFFFF, sum = 0
6904 22:11:58.193861 2, 0xFFFF, sum = 0
6905 22:11:58.196599 3, 0xFFFF, sum = 0
6906 22:11:58.196683 4, 0xFFFF, sum = 0
6907 22:11:58.200115 5, 0xFFFF, sum = 0
6908 22:11:58.200200 6, 0xFFFF, sum = 0
6909 22:11:58.203339 7, 0xFFFF, sum = 0
6910 22:11:58.203423 8, 0xFFFF, sum = 0
6911 22:11:58.206965 9, 0xFFFF, sum = 0
6912 22:11:58.210163 10, 0xFFFF, sum = 0
6913 22:11:58.210247 11, 0xFFFF, sum = 0
6914 22:11:58.213383 12, 0xFFFF, sum = 0
6915 22:11:58.213467 13, 0x0, sum = 1
6916 22:11:58.213532 14, 0x0, sum = 2
6917 22:11:58.217114 15, 0x0, sum = 3
6918 22:11:58.217197 16, 0x0, sum = 4
6919 22:11:58.220410 best_step = 14
6920 22:11:58.220492
6921 22:11:58.220557 ==
6922 22:11:58.223484 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 22:11:58.227148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 22:11:58.227258 ==
6925 22:11:58.230042 RX Vref Scan: 0
6926 22:11:58.230144
6927 22:11:58.230247 RX Vref 0 -> 0, step: 1
6928 22:11:58.230310
6929 22:11:58.233371 RX Delay -311 -> 252, step: 8
6930 22:11:58.241681 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6931 22:11:58.244782 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6932 22:11:58.248081 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6933 22:11:58.251793 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6934 22:11:58.258539 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6935 22:11:58.261479 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6936 22:11:58.264798 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6937 22:11:58.268088 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6938 22:11:58.275104 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6939 22:11:58.278303 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6940 22:11:58.281795 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6941 22:11:58.284752 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6942 22:11:58.291890 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6943 22:11:58.294798 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6944 22:11:58.298114 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6945 22:11:58.301424 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6946 22:11:58.305014 ==
6947 22:11:58.308366 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 22:11:58.311537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 22:11:58.311654 ==
6950 22:11:58.311719 DQS Delay:
6951 22:11:58.314712 DQS0 = 28, DQS1 = 32
6952 22:11:58.314794 DQM Delay:
6953 22:11:58.318206 DQM0 = 11, DQM1 = 11
6954 22:11:58.318288 DQ Delay:
6955 22:11:58.321519 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6956 22:11:58.324708 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6957 22:11:58.328000 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6958 22:11:58.331257 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6959 22:11:58.331358
6960 22:11:58.331448
6961 22:11:58.337915 [DQSOSCAuto] RK1, (LSB)MR18= 0xc455, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6962 22:11:58.341170 CH1 RK1: MR19=C0C, MR18=C455
6963 22:11:58.348063 CH1_RK1: MR19=0xC0C, MR18=0xC455, DQSOSC=385, MR23=63, INC=398, DEC=265
6964 22:11:58.351502 [RxdqsGatingPostProcess] freq 400
6965 22:11:58.354753 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6966 22:11:58.357925 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 22:11:58.361093 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 22:11:58.364743 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 22:11:58.367871 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 22:11:58.371018 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 22:11:58.374326 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 22:11:58.377692 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 22:11:58.381391 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 22:11:58.384591 Pre-setting of DQS Precalculation
6975 22:11:58.387714 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6976 22:11:58.397574 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6977 22:11:58.404349 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6978 22:11:58.404470
6979 22:11:58.404585
6980 22:11:58.407734 [Calibration Summary] 800 Mbps
6981 22:11:58.407858 CH 0, Rank 0
6982 22:11:58.411356 SW Impedance : PASS
6983 22:11:58.411485 DUTY Scan : NO K
6984 22:11:58.414248 ZQ Calibration : PASS
6985 22:11:58.417703 Jitter Meter : NO K
6986 22:11:58.417826 CBT Training : PASS
6987 22:11:58.420915 Write leveling : PASS
6988 22:11:58.424288 RX DQS gating : PASS
6989 22:11:58.424407 RX DQ/DQS(RDDQC) : PASS
6990 22:11:58.427746 TX DQ/DQS : PASS
6991 22:11:58.430810 RX DATLAT : PASS
6992 22:11:58.430929 RX DQ/DQS(Engine): PASS
6993 22:11:58.434112 TX OE : NO K
6994 22:11:58.434232 All Pass.
6995 22:11:58.434344
6996 22:11:58.437367 CH 0, Rank 1
6997 22:11:58.437490 SW Impedance : PASS
6998 22:11:58.441045 DUTY Scan : NO K
6999 22:11:58.444126 ZQ Calibration : PASS
7000 22:11:58.444247 Jitter Meter : NO K
7001 22:11:58.447523 CBT Training : PASS
7002 22:11:58.447662 Write leveling : NO K
7003 22:11:58.451004 RX DQS gating : PASS
7004 22:11:58.454188 RX DQ/DQS(RDDQC) : PASS
7005 22:11:58.454286 TX DQ/DQS : PASS
7006 22:11:58.457623 RX DATLAT : PASS
7007 22:11:58.460778 RX DQ/DQS(Engine): PASS
7008 22:11:58.460904 TX OE : NO K
7009 22:11:58.464471 All Pass.
7010 22:11:58.464594
7011 22:11:58.464699 CH 1, Rank 0
7012 22:11:58.467523 SW Impedance : PASS
7013 22:11:58.467684 DUTY Scan : NO K
7014 22:11:58.470651 ZQ Calibration : PASS
7015 22:11:58.474330 Jitter Meter : NO K
7016 22:11:58.474413 CBT Training : PASS
7017 22:11:58.477591 Write leveling : PASS
7018 22:11:58.480869 RX DQS gating : PASS
7019 22:11:58.480952 RX DQ/DQS(RDDQC) : PASS
7020 22:11:58.484094 TX DQ/DQS : PASS
7021 22:11:58.484177 RX DATLAT : PASS
7022 22:11:58.487881 RX DQ/DQS(Engine): PASS
7023 22:11:58.490956 TX OE : NO K
7024 22:11:58.491038 All Pass.
7025 22:11:58.491103
7026 22:11:58.491162 CH 1, Rank 1
7027 22:11:58.494436 SW Impedance : PASS
7028 22:11:58.497436 DUTY Scan : NO K
7029 22:11:58.497519 ZQ Calibration : PASS
7030 22:11:58.501082 Jitter Meter : NO K
7031 22:11:58.504287 CBT Training : PASS
7032 22:11:58.504370 Write leveling : NO K
7033 22:11:58.507431 RX DQS gating : PASS
7034 22:11:58.511013 RX DQ/DQS(RDDQC) : PASS
7035 22:11:58.511114 TX DQ/DQS : PASS
7036 22:11:58.514193 RX DATLAT : PASS
7037 22:11:58.517473 RX DQ/DQS(Engine): PASS
7038 22:11:58.517556 TX OE : NO K
7039 22:11:58.517622 All Pass.
7040 22:11:58.520773
7041 22:11:58.520855 DramC Write-DBI off
7042 22:11:58.524482 PER_BANK_REFRESH: Hybrid Mode
7043 22:11:58.524566 TX_TRACKING: ON
7044 22:11:58.534317 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7045 22:11:58.537854 [FAST_K] Save calibration result to emmc
7046 22:11:58.541080 dramc_set_vcore_voltage set vcore to 725000
7047 22:11:58.544414 Read voltage for 1600, 0
7048 22:11:58.544497 Vio18 = 0
7049 22:11:58.547503 Vcore = 725000
7050 22:11:58.547632 Vdram = 0
7051 22:11:58.547700 Vddq = 0
7052 22:11:58.547760 Vmddr = 0
7053 22:11:58.554239 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7054 22:11:58.560897 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7055 22:11:58.560981 MEM_TYPE=3, freq_sel=13
7056 22:11:58.564403 sv_algorithm_assistance_LP4_3733
7057 22:11:58.567265 ============ PULL DRAM RESETB DOWN ============
7058 22:11:58.574191 ========== PULL DRAM RESETB DOWN end =========
7059 22:11:58.577458 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7060 22:11:58.580816 ===================================
7061 22:11:58.584166 LPDDR4 DRAM CONFIGURATION
7062 22:11:58.587210 ===================================
7063 22:11:58.587293 EX_ROW_EN[0] = 0x0
7064 22:11:58.590662 EX_ROW_EN[1] = 0x0
7065 22:11:58.590784 LP4Y_EN = 0x0
7066 22:11:58.593806 WORK_FSP = 0x1
7067 22:11:58.593888 WL = 0x5
7068 22:11:58.597540 RL = 0x5
7069 22:11:58.601050 BL = 0x2
7070 22:11:58.601132 RPST = 0x0
7071 22:11:58.603978 RD_PRE = 0x0
7072 22:11:58.604107 WR_PRE = 0x1
7073 22:11:58.607124 WR_PST = 0x1
7074 22:11:58.607222 DBI_WR = 0x0
7075 22:11:58.610802 DBI_RD = 0x0
7076 22:11:58.610931 OTF = 0x1
7077 22:11:58.614003 ===================================
7078 22:11:58.617611 ===================================
7079 22:11:58.620715 ANA top config
7080 22:11:58.623751 ===================================
7081 22:11:58.623867 DLL_ASYNC_EN = 0
7082 22:11:58.627559 ALL_SLAVE_EN = 0
7083 22:11:58.630688 NEW_RANK_MODE = 1
7084 22:11:58.633741 DLL_IDLE_MODE = 1
7085 22:11:58.633877 LP45_APHY_COMB_EN = 1
7086 22:11:58.637441 TX_ODT_DIS = 0
7087 22:11:58.641330 NEW_8X_MODE = 1
7088 22:11:58.643743 ===================================
7089 22:11:58.647315 ===================================
7090 22:11:58.650465 data_rate = 3200
7091 22:11:58.654274 CKR = 1
7092 22:11:58.654396 DQ_P2S_RATIO = 8
7093 22:11:58.657457 ===================================
7094 22:11:58.660451 CA_P2S_RATIO = 8
7095 22:11:58.664138 DQ_CA_OPEN = 0
7096 22:11:58.667413 DQ_SEMI_OPEN = 0
7097 22:11:58.670583 CA_SEMI_OPEN = 0
7098 22:11:58.674143 CA_FULL_RATE = 0
7099 22:11:58.674262 DQ_CKDIV4_EN = 0
7100 22:11:58.677328 CA_CKDIV4_EN = 0
7101 22:11:58.680368 CA_PREDIV_EN = 0
7102 22:11:58.684007 PH8_DLY = 12
7103 22:11:58.687428 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7104 22:11:58.690515 DQ_AAMCK_DIV = 4
7105 22:11:58.690637 CA_AAMCK_DIV = 4
7106 22:11:58.693861 CA_ADMCK_DIV = 4
7107 22:11:58.697018 DQ_TRACK_CA_EN = 0
7108 22:11:58.700384 CA_PICK = 1600
7109 22:11:58.703606 CA_MCKIO = 1600
7110 22:11:58.707100 MCKIO_SEMI = 0
7111 22:11:58.710462 PLL_FREQ = 3068
7112 22:11:58.713697 DQ_UI_PI_RATIO = 32
7113 22:11:58.713780 CA_UI_PI_RATIO = 0
7114 22:11:58.717047 ===================================
7115 22:11:58.720544 ===================================
7116 22:11:58.723770 memory_type:LPDDR4
7117 22:11:58.727154 GP_NUM : 10
7118 22:11:58.727270 SRAM_EN : 1
7119 22:11:58.730361 MD32_EN : 0
7120 22:11:58.733543 ===================================
7121 22:11:58.737219 [ANA_INIT] >>>>>>>>>>>>>>
7122 22:11:58.740329 <<<<<< [CONFIGURE PHASE]: ANA_TX
7123 22:11:58.743578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7124 22:11:58.747102 ===================================
7125 22:11:58.747186 data_rate = 3200,PCW = 0X7600
7126 22:11:58.750561 ===================================
7127 22:11:58.753718 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7128 22:11:58.760201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 22:11:58.766835 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 22:11:58.770417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7131 22:11:58.773603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7132 22:11:58.777365 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7133 22:11:58.780470 [ANA_INIT] flow start
7134 22:11:58.780579 [ANA_INIT] PLL >>>>>>>>
7135 22:11:58.783455 [ANA_INIT] PLL <<<<<<<<
7136 22:11:58.786757 [ANA_INIT] MIDPI >>>>>>>>
7137 22:11:58.790143 [ANA_INIT] MIDPI <<<<<<<<
7138 22:11:58.790225 [ANA_INIT] DLL >>>>>>>>
7139 22:11:58.793474 [ANA_INIT] DLL <<<<<<<<
7140 22:11:58.793556 [ANA_INIT] flow end
7141 22:11:58.800555 ============ LP4 DIFF to SE enter ============
7142 22:11:58.803658 ============ LP4 DIFF to SE exit ============
7143 22:11:58.806871 [ANA_INIT] <<<<<<<<<<<<<
7144 22:11:58.810304 [Flow] Enable top DCM control >>>>>
7145 22:11:58.813557 [Flow] Enable top DCM control <<<<<
7146 22:11:58.816491 Enable DLL master slave shuffle
7147 22:11:58.819773 ==============================================================
7148 22:11:58.823015 Gating Mode config
7149 22:11:58.826384 ==============================================================
7150 22:11:58.829756 Config description:
7151 22:11:58.840009 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7152 22:11:58.846396 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7153 22:11:58.849602 SELPH_MODE 0: By rank 1: By Phase
7154 22:11:58.856224 ==============================================================
7155 22:11:58.859499 GAT_TRACK_EN = 1
7156 22:11:58.863097 RX_GATING_MODE = 2
7157 22:11:58.866176 RX_GATING_TRACK_MODE = 2
7158 22:11:58.869706 SELPH_MODE = 1
7159 22:11:58.872905 PICG_EARLY_EN = 1
7160 22:11:58.872988 VALID_LAT_VALUE = 1
7161 22:11:58.879915 ==============================================================
7162 22:11:58.883208 Enter into Gating configuration >>>>
7163 22:11:58.886305 Exit from Gating configuration <<<<
7164 22:11:58.889457 Enter into DVFS_PRE_config >>>>>
7165 22:11:58.899421 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7166 22:11:58.902994 Exit from DVFS_PRE_config <<<<<
7167 22:11:58.905827 Enter into PICG configuration >>>>
7168 22:11:58.908997 Exit from PICG configuration <<<<
7169 22:11:58.912739 [RX_INPUT] configuration >>>>>
7170 22:11:58.915863 [RX_INPUT] configuration <<<<<
7171 22:11:58.922359 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7172 22:11:58.925922 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7173 22:11:58.932494 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 22:11:58.939015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 22:11:58.945941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 22:11:58.952848 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 22:11:58.956078 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7178 22:11:58.959289 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7179 22:11:58.962661 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7180 22:11:58.969278 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7181 22:11:58.972785 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7182 22:11:58.975887 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7183 22:11:58.979294 ===================================
7184 22:11:58.982219 LPDDR4 DRAM CONFIGURATION
7185 22:11:58.985623 ===================================
7186 22:11:58.985706 EX_ROW_EN[0] = 0x0
7187 22:11:58.989321 EX_ROW_EN[1] = 0x0
7188 22:11:58.989403 LP4Y_EN = 0x0
7189 22:11:58.992196 WORK_FSP = 0x1
7190 22:11:58.995767 WL = 0x5
7191 22:11:58.995850 RL = 0x5
7192 22:11:58.999071 BL = 0x2
7193 22:11:58.999153 RPST = 0x0
7194 22:11:59.002593 RD_PRE = 0x0
7195 22:11:59.002693 WR_PRE = 0x1
7196 22:11:59.005986 WR_PST = 0x1
7197 22:11:59.006069 DBI_WR = 0x0
7198 22:11:59.009307 DBI_RD = 0x0
7199 22:11:59.009415 OTF = 0x1
7200 22:11:59.012558 ===================================
7201 22:11:59.015836 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7202 22:11:59.022295 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7203 22:11:59.026100 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 22:11:59.029273 ===================================
7205 22:11:59.032736 LPDDR4 DRAM CONFIGURATION
7206 22:11:59.035810 ===================================
7207 22:11:59.035893 EX_ROW_EN[0] = 0x10
7208 22:11:59.039166 EX_ROW_EN[1] = 0x0
7209 22:11:59.039248 LP4Y_EN = 0x0
7210 22:11:59.042283 WORK_FSP = 0x1
7211 22:11:59.042366 WL = 0x5
7212 22:11:59.045633 RL = 0x5
7213 22:11:59.045716 BL = 0x2
7214 22:11:59.048788 RPST = 0x0
7215 22:11:59.048871 RD_PRE = 0x0
7216 22:11:59.052487 WR_PRE = 0x1
7217 22:11:59.052571 WR_PST = 0x1
7218 22:11:59.055612 DBI_WR = 0x0
7219 22:11:59.055710 DBI_RD = 0x0
7220 22:11:59.059496 OTF = 0x1
7221 22:11:59.062603 ===================================
7222 22:11:59.069190 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7223 22:11:59.069274 ==
7224 22:11:59.072563 Dram Type= 6, Freq= 0, CH_0, rank 0
7225 22:11:59.075824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7226 22:11:59.075907 ==
7227 22:11:59.079049 [Duty_Offset_Calibration]
7228 22:11:59.079131 B0:2 B1:1 CA:1
7229 22:11:59.079196
7230 22:11:59.082184 [DutyScan_Calibration_Flow] k_type=0
7231 22:11:59.093762
7232 22:11:59.093844 ==CLK 0==
7233 22:11:59.097340 Final CLK duty delay cell = 0
7234 22:11:59.100353 [0] MAX Duty = 5156%(X100), DQS PI = 22
7235 22:11:59.103333 [0] MIN Duty = 4876%(X100), DQS PI = 48
7236 22:11:59.103416 [0] AVG Duty = 5016%(X100)
7237 22:11:59.106940
7238 22:11:59.110219 CH0 CLK Duty spec in!! Max-Min= 280%
7239 22:11:59.113615 [DutyScan_Calibration_Flow] ====Done====
7240 22:11:59.113697
7241 22:11:59.116770 [DutyScan_Calibration_Flow] k_type=1
7242 22:11:59.132869
7243 22:11:59.132954 ==DQS 0 ==
7244 22:11:59.136470 Final DQS duty delay cell = -4
7245 22:11:59.139715 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7246 22:11:59.142922 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7247 22:11:59.146172 [-4] AVG Duty = 4891%(X100)
7248 22:11:59.146254
7249 22:11:59.146318 ==DQS 1 ==
7250 22:11:59.149426 Final DQS duty delay cell = 0
7251 22:11:59.153071 [0] MAX Duty = 5218%(X100), DQS PI = 22
7252 22:11:59.156415 [0] MIN Duty = 5031%(X100), DQS PI = 52
7253 22:11:59.159614 [0] AVG Duty = 5124%(X100)
7254 22:11:59.159711
7255 22:11:59.162891 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7256 22:11:59.162973
7257 22:11:59.166197 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7258 22:11:59.169382 [DutyScan_Calibration_Flow] ====Done====
7259 22:11:59.169465
7260 22:11:59.172655 [DutyScan_Calibration_Flow] k_type=3
7261 22:11:59.189607
7262 22:11:59.189691 ==DQM 0 ==
7263 22:11:59.192830 Final DQM duty delay cell = 0
7264 22:11:59.195955 [0] MAX Duty = 5218%(X100), DQS PI = 34
7265 22:11:59.199294 [0] MIN Duty = 4907%(X100), DQS PI = 54
7266 22:11:59.202528 [0] AVG Duty = 5062%(X100)
7267 22:11:59.202611
7268 22:11:59.202674 ==DQM 1 ==
7269 22:11:59.206007 Final DQM duty delay cell = -4
7270 22:11:59.209261 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7271 22:11:59.212847 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7272 22:11:59.215906 [-4] AVG Duty = 4922%(X100)
7273 22:11:59.215989
7274 22:11:59.219270 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7275 22:11:59.219353
7276 22:11:59.222829 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7277 22:11:59.225826 [DutyScan_Calibration_Flow] ====Done====
7278 22:11:59.225908
7279 22:11:59.228880 [DutyScan_Calibration_Flow] k_type=2
7280 22:11:59.247202
7281 22:11:59.247291 ==DQ 0 ==
7282 22:11:59.250452 Final DQ duty delay cell = 0
7283 22:11:59.253667 [0] MAX Duty = 5062%(X100), DQS PI = 24
7284 22:11:59.256833 [0] MIN Duty = 4907%(X100), DQS PI = 0
7285 22:11:59.256917 [0] AVG Duty = 4984%(X100)
7286 22:11:59.260046
7287 22:11:59.260143 ==DQ 1 ==
7288 22:11:59.263577 Final DQ duty delay cell = 0
7289 22:11:59.266966 [0] MAX Duty = 5125%(X100), DQS PI = 6
7290 22:11:59.270263 [0] MIN Duty = 4907%(X100), DQS PI = 34
7291 22:11:59.270346 [0] AVG Duty = 5016%(X100)
7292 22:11:59.270410
7293 22:11:59.273573 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7294 22:11:59.276807
7295 22:11:59.276890 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7296 22:11:59.283227 [DutyScan_Calibration_Flow] ====Done====
7297 22:11:59.283310 ==
7298 22:11:59.287116 Dram Type= 6, Freq= 0, CH_1, rank 0
7299 22:11:59.289887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 22:11:59.289975 ==
7301 22:11:59.293472 [Duty_Offset_Calibration]
7302 22:11:59.293602 B0:1 B1:0 CA:0
7303 22:11:59.293721
7304 22:11:59.296712 [DutyScan_Calibration_Flow] k_type=0
7305 22:11:59.306460
7306 22:11:59.306557 ==CLK 0==
7307 22:11:59.309421 Final CLK duty delay cell = -4
7308 22:11:59.312799 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7309 22:11:59.315989 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7310 22:11:59.319509 [-4] AVG Duty = 4922%(X100)
7311 22:11:59.319599
7312 22:11:59.322780 CH1 CLK Duty spec in!! Max-Min= 156%
7313 22:11:59.325996 [DutyScan_Calibration_Flow] ====Done====
7314 22:11:59.326078
7315 22:11:59.329277 [DutyScan_Calibration_Flow] k_type=1
7316 22:11:59.346297
7317 22:11:59.346381 ==DQS 0 ==
7318 22:11:59.349481 Final DQS duty delay cell = 0
7319 22:11:59.352805 [0] MAX Duty = 5094%(X100), DQS PI = 30
7320 22:11:59.356358 [0] MIN Duty = 4875%(X100), DQS PI = 0
7321 22:11:59.356440 [0] AVG Duty = 4984%(X100)
7322 22:11:59.359742
7323 22:11:59.359826 ==DQS 1 ==
7324 22:11:59.363087 Final DQS duty delay cell = 0
7325 22:11:59.366183 [0] MAX Duty = 5249%(X100), DQS PI = 16
7326 22:11:59.369618 [0] MIN Duty = 4969%(X100), DQS PI = 8
7327 22:11:59.369688 [0] AVG Duty = 5109%(X100)
7328 22:11:59.369748
7329 22:11:59.376466 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7330 22:11:59.376566
7331 22:11:59.379618 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7332 22:11:59.383317 [DutyScan_Calibration_Flow] ====Done====
7333 22:11:59.383401
7334 22:11:59.386398 [DutyScan_Calibration_Flow] k_type=3
7335 22:11:59.402916
7336 22:11:59.403025 ==DQM 0 ==
7337 22:11:59.406750 Final DQM duty delay cell = 0
7338 22:11:59.409804 [0] MAX Duty = 5218%(X100), DQS PI = 18
7339 22:11:59.412910 [0] MIN Duty = 4969%(X100), DQS PI = 48
7340 22:11:59.416436 [0] AVG Duty = 5093%(X100)
7341 22:11:59.416519
7342 22:11:59.416586 ==DQM 1 ==
7343 22:11:59.419713 Final DQM duty delay cell = 0
7344 22:11:59.422901 [0] MAX Duty = 5093%(X100), DQS PI = 16
7345 22:11:59.426229 [0] MIN Duty = 4938%(X100), DQS PI = 6
7346 22:11:59.426313 [0] AVG Duty = 5015%(X100)
7347 22:11:59.429875
7348 22:11:59.433259 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7349 22:11:59.433342
7350 22:11:59.436415 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7351 22:11:59.439612 [DutyScan_Calibration_Flow] ====Done====
7352 22:11:59.439721
7353 22:11:59.443172 [DutyScan_Calibration_Flow] k_type=2
7354 22:11:59.459247
7355 22:11:59.459333 ==DQ 0 ==
7356 22:11:59.462411 Final DQ duty delay cell = -4
7357 22:11:59.466003 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7358 22:11:59.468829 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7359 22:11:59.472318 [-4] AVG Duty = 4968%(X100)
7360 22:11:59.472402
7361 22:11:59.472466 ==DQ 1 ==
7362 22:11:59.475381 Final DQ duty delay cell = 0
7363 22:11:59.479159 [0] MAX Duty = 5093%(X100), DQS PI = 16
7364 22:11:59.482342 [0] MIN Duty = 4938%(X100), DQS PI = 8
7365 22:11:59.485440 [0] AVG Duty = 5015%(X100)
7366 22:11:59.485523
7367 22:11:59.489191 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7368 22:11:59.489274
7369 22:11:59.492048 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7370 22:11:59.495791 [DutyScan_Calibration_Flow] ====Done====
7371 22:11:59.498982 nWR fixed to 30
7372 22:11:59.499065 [ModeRegInit_LP4] CH0 RK0
7373 22:11:59.502215 [ModeRegInit_LP4] CH0 RK1
7374 22:11:59.505612 [ModeRegInit_LP4] CH1 RK0
7375 22:11:59.509234 [ModeRegInit_LP4] CH1 RK1
7376 22:11:59.509318 match AC timing 5
7377 22:11:59.515565 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7378 22:11:59.518734 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7379 22:11:59.521979 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7380 22:11:59.529052 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7381 22:11:59.532174 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7382 22:11:59.532263 [MiockJmeterHQA]
7383 22:11:59.532330
7384 22:11:59.535792 [DramcMiockJmeter] u1RxGatingPI = 0
7385 22:11:59.538567 0 : 4362, 4137
7386 22:11:59.538653 4 : 4252, 4027
7387 22:11:59.541880 8 : 4363, 4138
7388 22:11:59.541966 12 : 4253, 4027
7389 22:11:59.542033 16 : 4252, 4027
7390 22:11:59.545531 20 : 4363, 4137
7391 22:11:59.545617 24 : 4252, 4027
7392 22:11:59.548635 28 : 4253, 4027
7393 22:11:59.548722 32 : 4252, 4027
7394 22:11:59.552227 36 : 4255, 4029
7395 22:11:59.552313 40 : 4363, 4138
7396 22:11:59.555330 44 : 4253, 4026
7397 22:11:59.555415 48 : 4363, 4137
7398 22:11:59.555482 52 : 4252, 4027
7399 22:11:59.558693 56 : 4252, 4027
7400 22:11:59.558777 60 : 4252, 4027
7401 22:11:59.561811 64 : 4361, 4137
7402 22:11:59.561895 68 : 4252, 4027
7403 22:11:59.565275 72 : 4361, 4138
7404 22:11:59.565360 76 : 4250, 4027
7405 22:11:59.568457 80 : 4250, 4027
7406 22:11:59.568541 84 : 4250, 4024
7407 22:11:59.568608 88 : 4253, 52
7408 22:11:59.571671 92 : 4360, 0
7409 22:11:59.571757 96 : 4252, 0
7410 22:11:59.571824 100 : 4250, 0
7411 22:11:59.575096 104 : 4252, 0
7412 22:11:59.575179 108 : 4250, 0
7413 22:11:59.578472 112 : 4361, 0
7414 22:11:59.578555 116 : 4250, 0
7415 22:11:59.578620 120 : 4252, 0
7416 22:11:59.581602 124 : 4250, 0
7417 22:11:59.581712 128 : 4250, 0
7418 22:11:59.585156 132 : 4363, 0
7419 22:11:59.585240 136 : 4250, 0
7420 22:11:59.585306 140 : 4250, 0
7421 22:11:59.588590 144 : 4252, 0
7422 22:11:59.588673 148 : 4361, 0
7423 22:11:59.591840 152 : 4250, 0
7424 22:11:59.591959 156 : 4250, 0
7425 22:11:59.592055 160 : 4250, 0
7426 22:11:59.595031 164 : 4250, 0
7427 22:11:59.595114 168 : 4363, 0
7428 22:11:59.595180 172 : 4250, 0
7429 22:11:59.598348 176 : 4361, 0
7430 22:11:59.598431 180 : 4250, 0
7431 22:11:59.601979 184 : 4250, 0
7432 22:11:59.602062 188 : 4250, 0
7433 22:11:59.602128 192 : 4253, 0
7434 22:11:59.605145 196 : 4250, 0
7435 22:11:59.605229 200 : 4361, 0
7436 22:11:59.608440 204 : 4250, 1466
7437 22:11:59.608524 208 : 4250, 4002
7438 22:11:59.611799 212 : 4249, 4027
7439 22:11:59.611883 216 : 4250, 4027
7440 22:11:59.615197 220 : 4250, 4026
7441 22:11:59.615280 224 : 4250, 4026
7442 22:11:59.615346 228 : 4252, 4030
7443 22:11:59.618433 232 : 4252, 4029
7444 22:11:59.618516 236 : 4250, 4027
7445 22:11:59.621833 240 : 4361, 4137
7446 22:11:59.621916 244 : 4361, 4137
7447 22:11:59.624892 248 : 4250, 4027
7448 22:11:59.624976 252 : 4363, 4140
7449 22:11:59.628612 256 : 4250, 4027
7450 22:11:59.628746 260 : 4250, 4027
7451 22:11:59.631776 264 : 4250, 4027
7452 22:11:59.631875 268 : 4252, 4029
7453 22:11:59.634975 272 : 4250, 4027
7454 22:11:59.635058 276 : 4250, 4026
7455 22:11:59.638277 280 : 4250, 4027
7456 22:11:59.638360 284 : 4252, 4029
7457 22:11:59.638426 288 : 4249, 4027
7458 22:11:59.641666 292 : 4361, 4137
7459 22:11:59.641749 296 : 4361, 4138
7460 22:11:59.645436 300 : 4250, 4027
7461 22:11:59.645520 304 : 4363, 4140
7462 22:11:59.648165 308 : 4361, 3993
7463 22:11:59.648249 312 : 4250, 1809
7464 22:11:59.648314
7465 22:11:59.651884 MIOCK jitter meter ch=0
7466 22:11:59.651966
7467 22:11:59.655280 1T = (312-88) = 224 dly cells
7468 22:11:59.661855 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7469 22:11:59.661938 ==
7470 22:11:59.664958 Dram Type= 6, Freq= 0, CH_0, rank 0
7471 22:11:59.668378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7472 22:11:59.668465 ==
7473 22:11:59.674946 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7474 22:11:59.678122 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7475 22:11:59.681536 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7476 22:11:59.688216 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7477 22:11:59.696675 [CA 0] Center 42 (12~73) winsize 62
7478 22:11:59.700171 [CA 1] Center 42 (12~73) winsize 62
7479 22:11:59.703376 [CA 2] Center 37 (8~67) winsize 60
7480 22:11:59.706660 [CA 3] Center 37 (7~67) winsize 61
7481 22:11:59.710171 [CA 4] Center 36 (6~66) winsize 61
7482 22:11:59.713210 [CA 5] Center 35 (6~64) winsize 59
7483 22:11:59.713318
7484 22:11:59.716292 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7485 22:11:59.716405
7486 22:11:59.719555 [CATrainingPosCal] consider 1 rank data
7487 22:11:59.723315 u2DelayCellTimex100 = 290/100 ps
7488 22:11:59.726844 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7489 22:11:59.733184 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7490 22:11:59.736549 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7491 22:11:59.739716 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7492 22:11:59.743513 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7493 22:11:59.746242 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7494 22:11:59.746325
7495 22:11:59.750076 CA PerBit enable=1, Macro0, CA PI delay=35
7496 22:11:59.750158
7497 22:11:59.752826 [CBTSetCACLKResult] CA Dly = 35
7498 22:11:59.756579 CS Dly: 9 (0~40)
7499 22:11:59.759808 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7500 22:11:59.763638 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7501 22:11:59.763721 ==
7502 22:11:59.766317 Dram Type= 6, Freq= 0, CH_0, rank 1
7503 22:11:59.769428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 22:11:59.772913 ==
7505 22:11:59.776437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 22:11:59.779447 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 22:11:59.786059 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 22:11:59.789276 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 22:11:59.799949 [CA 0] Center 42 (12~73) winsize 62
7510 22:11:59.802931 [CA 1] Center 42 (12~73) winsize 62
7511 22:11:59.806266 [CA 2] Center 38 (8~68) winsize 61
7512 22:11:59.810150 [CA 3] Center 37 (8~67) winsize 60
7513 22:11:59.813367 [CA 4] Center 35 (6~65) winsize 60
7514 22:11:59.816247 [CA 5] Center 35 (5~65) winsize 61
7515 22:11:59.816350
7516 22:11:59.820241 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7517 22:11:59.820323
7518 22:11:59.823412 [CATrainingPosCal] consider 2 rank data
7519 22:11:59.826700 u2DelayCellTimex100 = 290/100 ps
7520 22:11:59.829902 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7521 22:11:59.836616 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7522 22:11:59.839610 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7523 22:11:59.843150 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7524 22:11:59.846650 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7525 22:11:59.849736 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7526 22:11:59.849818
7527 22:11:59.852963 CA PerBit enable=1, Macro0, CA PI delay=35
7528 22:11:59.853046
7529 22:11:59.856663 [CBTSetCACLKResult] CA Dly = 35
7530 22:11:59.859966 CS Dly: 10 (0~42)
7531 22:11:59.863289 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 22:11:59.866403 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 22:11:59.866486
7534 22:11:59.869700 ----->DramcWriteLeveling(PI) begin...
7535 22:11:59.869784 ==
7536 22:11:59.873641 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 22:11:59.876541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 22:11:59.879838 ==
7539 22:11:59.879946 Write leveling (Byte 0): 36 => 36
7540 22:11:59.882874 Write leveling (Byte 1): 28 => 28
7541 22:11:59.886557 DramcWriteLeveling(PI) end<-----
7542 22:11:59.886639
7543 22:11:59.886704 ==
7544 22:11:59.889580 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 22:11:59.896458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 22:11:59.896542 ==
7547 22:11:59.896639 [Gating] SW mode calibration
7548 22:11:59.906112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7549 22:11:59.909418 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7550 22:11:59.916261 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 22:11:59.919260 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 22:11:59.922623 1 4 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7553 22:11:59.929342 1 4 12 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
7554 22:11:59.932512 1 4 16 | B1->B0 | 2424 3636 | 1 0 | (1 1) (1 1)
7555 22:11:59.935740 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7556 22:11:59.939334 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7557 22:11:59.945966 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7558 22:11:59.949621 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 22:11:59.952370 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7560 22:11:59.959173 1 5 8 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7561 22:11:59.962607 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
7562 22:11:59.965814 1 5 16 | B1->B0 | 3333 2726 | 1 1 | (1 0) (0 0)
7563 22:11:59.972900 1 5 20 | B1->B0 | 2424 2525 | 0 0 | (1 0) (0 0)
7564 22:11:59.976197 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 22:11:59.979427 1 5 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7566 22:11:59.985814 1 6 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7567 22:11:59.989730 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7568 22:11:59.992426 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7569 22:11:59.999413 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7570 22:12:00.002622 1 6 16 | B1->B0 | 2a2a 4645 | 0 1 | (0 0) (0 0)
7571 22:12:00.005847 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7572 22:12:00.012666 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 22:12:00.016005 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 22:12:00.019465 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 22:12:00.025770 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 22:12:00.029416 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 22:12:00.032695 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 22:12:00.039174 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7579 22:12:00.042208 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7580 22:12:00.045574 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 22:12:00.052599 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 22:12:00.055769 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 22:12:00.058905 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 22:12:00.066018 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 22:12:00.069008 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 22:12:00.072291 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 22:12:00.075604 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 22:12:00.082123 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 22:12:00.085920 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 22:12:00.088765 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 22:12:00.095733 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 22:12:00.099180 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7593 22:12:00.101995 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 22:12:00.108735 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7595 22:12:00.112362 Total UI for P1: 0, mck2ui 16
7596 22:12:00.115627 best dqsien dly found for B0: ( 1, 9, 10)
7597 22:12:00.118604 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7598 22:12:00.122183 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 22:12:00.125405 Total UI for P1: 0, mck2ui 16
7600 22:12:00.128879 best dqsien dly found for B1: ( 1, 9, 18)
7601 22:12:00.132233 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7602 22:12:00.135761 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7603 22:12:00.135844
7604 22:12:00.142377 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7605 22:12:00.145566 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7606 22:12:00.148780 [Gating] SW calibration Done
7607 22:12:00.148859 ==
7608 22:12:00.151984 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 22:12:00.155274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 22:12:00.155350 ==
7611 22:12:00.155414 RX Vref Scan: 0
7612 22:12:00.155473
7613 22:12:00.159042 RX Vref 0 -> 0, step: 1
7614 22:12:00.159115
7615 22:12:00.162263 RX Delay 0 -> 252, step: 8
7616 22:12:00.165150 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7617 22:12:00.168719 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7618 22:12:00.171765 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7619 22:12:00.178539 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7620 22:12:00.182332 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7621 22:12:00.185527 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7622 22:12:00.188801 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7623 22:12:00.191982 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7624 22:12:00.198422 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7625 22:12:00.201874 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7626 22:12:00.205433 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7627 22:12:00.208549 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7628 22:12:00.212056 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7629 22:12:00.218470 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7630 22:12:00.221736 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7631 22:12:00.225126 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7632 22:12:00.225204 ==
7633 22:12:00.228520 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 22:12:00.231882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 22:12:00.231963 ==
7636 22:12:00.235246 DQS Delay:
7637 22:12:00.235317 DQS0 = 0, DQS1 = 0
7638 22:12:00.238614 DQM Delay:
7639 22:12:00.238719 DQM0 = 137, DQM1 = 130
7640 22:12:00.241757 DQ Delay:
7641 22:12:00.245309 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7642 22:12:00.248427 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7643 22:12:00.251918 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7644 22:12:00.255152 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7645 22:12:00.255228
7646 22:12:00.255289
7647 22:12:00.255347 ==
7648 22:12:00.258315 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 22:12:00.261670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 22:12:00.261752 ==
7651 22:12:00.261814
7652 22:12:00.261872
7653 22:12:00.265230 TX Vref Scan disable
7654 22:12:00.268271 == TX Byte 0 ==
7655 22:12:00.271589 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7656 22:12:00.275480 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7657 22:12:00.278321 == TX Byte 1 ==
7658 22:12:00.281883 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7659 22:12:00.285217 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7660 22:12:00.285294 ==
7661 22:12:00.288434 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 22:12:00.294872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 22:12:00.294951 ==
7664 22:12:00.305737
7665 22:12:00.309114 TX Vref early break, caculate TX vref
7666 22:12:00.312531 TX Vref=16, minBit 0, minWin=22, winSum=376
7667 22:12:00.316069 TX Vref=18, minBit 4, minWin=23, winSum=386
7668 22:12:00.319146 TX Vref=20, minBit 7, minWin=23, winSum=399
7669 22:12:00.322367 TX Vref=22, minBit 0, minWin=25, winSum=408
7670 22:12:00.325736 TX Vref=24, minBit 7, minWin=24, winSum=415
7671 22:12:00.332553 TX Vref=26, minBit 7, minWin=25, winSum=425
7672 22:12:00.336033 TX Vref=28, minBit 0, minWin=24, winSum=421
7673 22:12:00.338955 TX Vref=30, minBit 1, minWin=24, winSum=414
7674 22:12:00.342360 TX Vref=32, minBit 6, minWin=23, winSum=399
7675 22:12:00.349137 [TxChooseVref] Worse bit 7, Min win 25, Win sum 425, Final Vref 26
7676 22:12:00.349222
7677 22:12:00.352922 Final TX Range 0 Vref 26
7678 22:12:00.353005
7679 22:12:00.353069 ==
7680 22:12:00.356161 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 22:12:00.359176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 22:12:00.359259 ==
7683 22:12:00.359324
7684 22:12:00.359384
7685 22:12:00.362467 TX Vref Scan disable
7686 22:12:00.365870 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7687 22:12:00.369085 == TX Byte 0 ==
7688 22:12:00.372085 u2DelayCellOfst[0]=13 cells (4 PI)
7689 22:12:00.375571 u2DelayCellOfst[1]=16 cells (5 PI)
7690 22:12:00.378915 u2DelayCellOfst[2]=13 cells (4 PI)
7691 22:12:00.382029 u2DelayCellOfst[3]=10 cells (3 PI)
7692 22:12:00.385895 u2DelayCellOfst[4]=10 cells (3 PI)
7693 22:12:00.388866 u2DelayCellOfst[5]=0 cells (0 PI)
7694 22:12:00.388949 u2DelayCellOfst[6]=20 cells (6 PI)
7695 22:12:00.392158 u2DelayCellOfst[7]=16 cells (5 PI)
7696 22:12:00.398921 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7697 22:12:00.402082 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7698 22:12:00.402165 == TX Byte 1 ==
7699 22:12:00.405379 u2DelayCellOfst[8]=0 cells (0 PI)
7700 22:12:00.408804 u2DelayCellOfst[9]=0 cells (0 PI)
7701 22:12:00.411888 u2DelayCellOfst[10]=10 cells (3 PI)
7702 22:12:00.415415 u2DelayCellOfst[11]=6 cells (2 PI)
7703 22:12:00.418540 u2DelayCellOfst[12]=10 cells (3 PI)
7704 22:12:00.422014 u2DelayCellOfst[13]=10 cells (3 PI)
7705 22:12:00.425263 u2DelayCellOfst[14]=13 cells (4 PI)
7706 22:12:00.429211 u2DelayCellOfst[15]=10 cells (3 PI)
7707 22:12:00.432351 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7708 22:12:00.435581 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7709 22:12:00.438809 DramC Write-DBI on
7710 22:12:00.438908 ==
7711 22:12:00.442243 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 22:12:00.445249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 22:12:00.445322 ==
7714 22:12:00.445384
7715 22:12:00.448594
7716 22:12:00.448670 TX Vref Scan disable
7717 22:12:00.452248 == TX Byte 0 ==
7718 22:12:00.455477 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7719 22:12:00.458858 == TX Byte 1 ==
7720 22:12:00.461749 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7721 22:12:00.461827 DramC Write-DBI off
7722 22:12:00.461889
7723 22:12:00.465321 [DATLAT]
7724 22:12:00.465421 Freq=1600, CH0 RK0
7725 22:12:00.465514
7726 22:12:00.468556 DATLAT Default: 0xf
7727 22:12:00.468657 0, 0xFFFF, sum = 0
7728 22:12:00.471935 1, 0xFFFF, sum = 0
7729 22:12:00.472033 2, 0xFFFF, sum = 0
7730 22:12:00.475030 3, 0xFFFF, sum = 0
7731 22:12:00.475136 4, 0xFFFF, sum = 0
7732 22:12:00.478766 5, 0xFFFF, sum = 0
7733 22:12:00.481841 6, 0xFFFF, sum = 0
7734 22:12:00.481931 7, 0xFFFF, sum = 0
7735 22:12:00.485164 8, 0xFFFF, sum = 0
7736 22:12:00.485242 9, 0xFFFF, sum = 0
7737 22:12:00.488439 10, 0xFFFF, sum = 0
7738 22:12:00.488519 11, 0xFFFF, sum = 0
7739 22:12:00.491561 12, 0xFFFF, sum = 0
7740 22:12:00.491676 13, 0xFFFF, sum = 0
7741 22:12:00.495368 14, 0x0, sum = 1
7742 22:12:00.495461 15, 0x0, sum = 2
7743 22:12:00.498424 16, 0x0, sum = 3
7744 22:12:00.498499 17, 0x0, sum = 4
7745 22:12:00.501668 best_step = 15
7746 22:12:00.501740
7747 22:12:00.501804 ==
7748 22:12:00.505276 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 22:12:00.508532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 22:12:00.508607 ==
7751 22:12:00.508672 RX Vref Scan: 1
7752 22:12:00.508729
7753 22:12:00.511874 Set Vref Range= 24 -> 127
7754 22:12:00.511971
7755 22:12:00.515103 RX Vref 24 -> 127, step: 1
7756 22:12:00.515177
7757 22:12:00.518238 RX Delay 27 -> 252, step: 4
7758 22:12:00.518354
7759 22:12:00.521629 Set Vref, RX VrefLevel [Byte0]: 24
7760 22:12:00.525268 [Byte1]: 24
7761 22:12:00.525344
7762 22:12:00.528596 Set Vref, RX VrefLevel [Byte0]: 25
7763 22:12:00.532004 [Byte1]: 25
7764 22:12:00.532087
7765 22:12:00.535528 Set Vref, RX VrefLevel [Byte0]: 26
7766 22:12:00.538337 [Byte1]: 26
7767 22:12:00.542051
7768 22:12:00.542129 Set Vref, RX VrefLevel [Byte0]: 27
7769 22:12:00.545139 [Byte1]: 27
7770 22:12:00.549592
7771 22:12:00.549695 Set Vref, RX VrefLevel [Byte0]: 28
7772 22:12:00.552765 [Byte1]: 28
7773 22:12:00.557216
7774 22:12:00.557294 Set Vref, RX VrefLevel [Byte0]: 29
7775 22:12:00.560322 [Byte1]: 29
7776 22:12:00.564583
7777 22:12:00.564689 Set Vref, RX VrefLevel [Byte0]: 30
7778 22:12:00.568082 [Byte1]: 30
7779 22:12:00.572377
7780 22:12:00.572452 Set Vref, RX VrefLevel [Byte0]: 31
7781 22:12:00.575274 [Byte1]: 31
7782 22:12:00.579689
7783 22:12:00.579795 Set Vref, RX VrefLevel [Byte0]: 32
7784 22:12:00.582598 [Byte1]: 32
7785 22:12:00.587100
7786 22:12:00.587175 Set Vref, RX VrefLevel [Byte0]: 33
7787 22:12:00.590406 [Byte1]: 33
7788 22:12:00.594658
7789 22:12:00.594753 Set Vref, RX VrefLevel [Byte0]: 34
7790 22:12:00.597983 [Byte1]: 34
7791 22:12:00.602176
7792 22:12:00.602248 Set Vref, RX VrefLevel [Byte0]: 35
7793 22:12:00.605328 [Byte1]: 35
7794 22:12:00.609600
7795 22:12:00.609677 Set Vref, RX VrefLevel [Byte0]: 36
7796 22:12:00.613129 [Byte1]: 36
7797 22:12:00.617368
7798 22:12:00.617476 Set Vref, RX VrefLevel [Byte0]: 37
7799 22:12:00.620694 [Byte1]: 37
7800 22:12:00.624593
7801 22:12:00.624675 Set Vref, RX VrefLevel [Byte0]: 38
7802 22:12:00.627990 [Byte1]: 38
7803 22:12:00.632311
7804 22:12:00.632397 Set Vref, RX VrefLevel [Byte0]: 39
7805 22:12:00.635721 [Byte1]: 39
7806 22:12:00.639740
7807 22:12:00.639885 Set Vref, RX VrefLevel [Byte0]: 40
7808 22:12:00.643015 [Byte1]: 40
7809 22:12:00.647267
7810 22:12:00.647390 Set Vref, RX VrefLevel [Byte0]: 41
7811 22:12:00.650744 [Byte1]: 41
7812 22:12:00.655157
7813 22:12:00.655278 Set Vref, RX VrefLevel [Byte0]: 42
7814 22:12:00.658229 [Byte1]: 42
7815 22:12:00.662530
7816 22:12:00.662613 Set Vref, RX VrefLevel [Byte0]: 43
7817 22:12:00.666070 [Byte1]: 43
7818 22:12:00.669766
7819 22:12:00.669865 Set Vref, RX VrefLevel [Byte0]: 44
7820 22:12:00.673083 [Byte1]: 44
7821 22:12:00.677531
7822 22:12:00.677630 Set Vref, RX VrefLevel [Byte0]: 45
7823 22:12:00.681009 [Byte1]: 45
7824 22:12:00.685282
7825 22:12:00.685380 Set Vref, RX VrefLevel [Byte0]: 46
7826 22:12:00.688278 [Byte1]: 46
7827 22:12:00.692515
7828 22:12:00.692641 Set Vref, RX VrefLevel [Byte0]: 47
7829 22:12:00.695660 [Byte1]: 47
7830 22:12:00.699985
7831 22:12:00.700082 Set Vref, RX VrefLevel [Byte0]: 48
7832 22:12:00.703321 [Byte1]: 48
7833 22:12:00.707793
7834 22:12:00.707877 Set Vref, RX VrefLevel [Byte0]: 49
7835 22:12:00.710675 [Byte1]: 49
7836 22:12:00.715259
7837 22:12:00.715332 Set Vref, RX VrefLevel [Byte0]: 50
7838 22:12:00.718588 [Byte1]: 50
7839 22:12:00.722638
7840 22:12:00.722713 Set Vref, RX VrefLevel [Byte0]: 51
7841 22:12:00.725826 [Byte1]: 51
7842 22:12:00.730143
7843 22:12:00.730265 Set Vref, RX VrefLevel [Byte0]: 52
7844 22:12:00.733349 [Byte1]: 52
7845 22:12:00.737755
7846 22:12:00.737843 Set Vref, RX VrefLevel [Byte0]: 53
7847 22:12:00.741183 [Byte1]: 53
7848 22:12:00.745297
7849 22:12:00.745386 Set Vref, RX VrefLevel [Byte0]: 54
7850 22:12:00.748613 [Byte1]: 54
7851 22:12:00.752630
7852 22:12:00.752765 Set Vref, RX VrefLevel [Byte0]: 55
7853 22:12:00.756223 [Byte1]: 55
7854 22:12:00.760576
7855 22:12:00.760680 Set Vref, RX VrefLevel [Byte0]: 56
7856 22:12:00.763876 [Byte1]: 56
7857 22:12:00.768010
7858 22:12:00.768092 Set Vref, RX VrefLevel [Byte0]: 57
7859 22:12:00.771232 [Byte1]: 57
7860 22:12:00.775275
7861 22:12:00.775358 Set Vref, RX VrefLevel [Byte0]: 58
7862 22:12:00.778757 [Byte1]: 58
7863 22:12:00.782635
7864 22:12:00.782710 Set Vref, RX VrefLevel [Byte0]: 59
7865 22:12:00.786300 [Byte1]: 59
7866 22:12:00.790161
7867 22:12:00.790262 Set Vref, RX VrefLevel [Byte0]: 60
7868 22:12:00.793797 [Byte1]: 60
7869 22:12:00.798438
7870 22:12:00.798547 Set Vref, RX VrefLevel [Byte0]: 61
7871 22:12:00.801028 [Byte1]: 61
7872 22:12:00.805317
7873 22:12:00.805406 Set Vref, RX VrefLevel [Byte0]: 62
7874 22:12:00.808915 [Byte1]: 62
7875 22:12:00.813062
7876 22:12:00.813134 Set Vref, RX VrefLevel [Byte0]: 63
7877 22:12:00.816575 [Byte1]: 63
7878 22:12:00.820604
7879 22:12:00.820677 Set Vref, RX VrefLevel [Byte0]: 64
7880 22:12:00.824058 [Byte1]: 64
7881 22:12:00.827932
7882 22:12:00.828040 Set Vref, RX VrefLevel [Byte0]: 65
7883 22:12:00.831789 [Byte1]: 65
7884 22:12:00.835539
7885 22:12:00.835675 Set Vref, RX VrefLevel [Byte0]: 66
7886 22:12:00.838930 [Byte1]: 66
7887 22:12:00.843372
7888 22:12:00.843471 Set Vref, RX VrefLevel [Byte0]: 67
7889 22:12:00.846426 [Byte1]: 67
7890 22:12:00.850854
7891 22:12:00.850927 Set Vref, RX VrefLevel [Byte0]: 68
7892 22:12:00.854012 [Byte1]: 68
7893 22:12:00.858011
7894 22:12:00.858084 Set Vref, RX VrefLevel [Byte0]: 69
7895 22:12:00.861802 [Byte1]: 69
7896 22:12:00.866145
7897 22:12:00.866224 Set Vref, RX VrefLevel [Byte0]: 70
7898 22:12:00.868917 [Byte1]: 70
7899 22:12:00.873022
7900 22:12:00.873093 Set Vref, RX VrefLevel [Byte0]: 71
7901 22:12:00.876737 [Byte1]: 71
7902 22:12:00.880685
7903 22:12:00.880763 Set Vref, RX VrefLevel [Byte0]: 72
7904 22:12:00.884100 [Byte1]: 72
7905 22:12:00.888771
7906 22:12:00.888887 Set Vref, RX VrefLevel [Byte0]: 73
7907 22:12:00.891567 [Byte1]: 73
7908 22:12:00.895884
7909 22:12:00.895969 Final RX Vref Byte 0 = 56 to rank0
7910 22:12:00.899153 Final RX Vref Byte 1 = 60 to rank0
7911 22:12:00.902387 Final RX Vref Byte 0 = 56 to rank1
7912 22:12:00.905850 Final RX Vref Byte 1 = 60 to rank1==
7913 22:12:00.909091 Dram Type= 6, Freq= 0, CH_0, rank 0
7914 22:12:00.915824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7915 22:12:00.915914 ==
7916 22:12:00.915999 DQS Delay:
7917 22:12:00.916081 DQS0 = 0, DQS1 = 0
7918 22:12:00.919243 DQM Delay:
7919 22:12:00.919328 DQM0 = 134, DQM1 = 127
7920 22:12:00.922455 DQ Delay:
7921 22:12:00.925670 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7922 22:12:00.928985 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7923 22:12:00.932284 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7924 22:12:00.935753 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7925 22:12:00.935838
7926 22:12:00.935923
7927 22:12:00.936004
7928 22:12:00.938961 [DramC_TX_OE_Calibration] TA2
7929 22:12:00.942322 Original DQ_B0 (3 6) =30, OEN = 27
7930 22:12:00.946110 Original DQ_B1 (3 6) =30, OEN = 27
7931 22:12:00.949114 24, 0x0, End_B0=24 End_B1=24
7932 22:12:00.949200 25, 0x0, End_B0=25 End_B1=25
7933 22:12:00.952565 26, 0x0, End_B0=26 End_B1=26
7934 22:12:00.955475 27, 0x0, End_B0=27 End_B1=27
7935 22:12:00.959036 28, 0x0, End_B0=28 End_B1=28
7936 22:12:00.962207 29, 0x0, End_B0=29 End_B1=29
7937 22:12:00.962294 30, 0x0, End_B0=30 End_B1=30
7938 22:12:00.965891 31, 0x4141, End_B0=30 End_B1=30
7939 22:12:00.969187 Byte0 end_step=30 best_step=27
7940 22:12:00.972360 Byte1 end_step=30 best_step=27
7941 22:12:00.975626 Byte0 TX OE(2T, 0.5T) = (3, 3)
7942 22:12:00.978818 Byte1 TX OE(2T, 0.5T) = (3, 3)
7943 22:12:00.978921
7944 22:12:00.979004
7945 22:12:00.985374 [DQSOSCAuto] RK0, (LSB)MR18= 0x2520, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7946 22:12:00.988959 CH0 RK0: MR19=303, MR18=2520
7947 22:12:00.995458 CH0_RK0: MR19=0x303, MR18=0x2520, DQSOSC=391, MR23=63, INC=24, DEC=16
7948 22:12:00.995544
7949 22:12:00.999331 ----->DramcWriteLeveling(PI) begin...
7950 22:12:00.999418 ==
7951 22:12:01.002260 Dram Type= 6, Freq= 0, CH_0, rank 1
7952 22:12:01.005586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 22:12:01.005741 ==
7954 22:12:01.008871 Write leveling (Byte 0): 37 => 37
7955 22:12:01.012390 Write leveling (Byte 1): 30 => 30
7956 22:12:01.015548 DramcWriteLeveling(PI) end<-----
7957 22:12:01.015688
7958 22:12:01.015809 ==
7959 22:12:01.018681 Dram Type= 6, Freq= 0, CH_0, rank 1
7960 22:12:01.022289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 22:12:01.022378 ==
7962 22:12:01.025689 [Gating] SW mode calibration
7963 22:12:01.032138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7964 22:12:01.039019 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7965 22:12:01.042294 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7966 22:12:01.045224 1 4 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7967 22:12:01.052189 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7968 22:12:01.055627 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7969 22:12:01.058781 1 4 16 | B1->B0 | 2d2d 3837 | 0 1 | (0 0) (0 0)
7970 22:12:01.065443 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7971 22:12:01.068826 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7972 22:12:01.072182 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7973 22:12:01.078824 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7974 22:12:01.082023 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7975 22:12:01.085517 1 5 8 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7976 22:12:01.092201 1 5 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
7977 22:12:01.095489 1 5 16 | B1->B0 | 2d2d 2928 | 1 1 | (1 0) (1 0)
7978 22:12:01.098544 1 5 20 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
7979 22:12:01.105252 1 5 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7980 22:12:01.108452 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7981 22:12:01.111911 1 6 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7982 22:12:01.118732 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7983 22:12:01.121829 1 6 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7984 22:12:01.125171 1 6 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7985 22:12:01.132108 1 6 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7986 22:12:01.135470 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 22:12:01.138597 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7988 22:12:01.142397 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 22:12:01.148812 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 22:12:01.152147 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 22:12:01.155486 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 22:12:01.161948 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7993 22:12:01.165469 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7994 22:12:01.168588 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 22:12:01.175326 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 22:12:01.178423 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 22:12:01.181752 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 22:12:01.188177 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 22:12:01.191982 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 22:12:01.195322 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 22:12:01.201945 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 22:12:01.205168 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 22:12:01.208596 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 22:12:01.215105 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 22:12:01.218537 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 22:12:01.221515 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 22:12:01.228470 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 22:12:01.231460 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8009 22:12:01.235198 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8010 22:12:01.241633 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 22:12:01.241732 Total UI for P1: 0, mck2ui 16
8012 22:12:01.248187 best dqsien dly found for B0: ( 1, 9, 14)
8013 22:12:01.248271 Total UI for P1: 0, mck2ui 16
8014 22:12:01.251331 best dqsien dly found for B1: ( 1, 9, 16)
8015 22:12:01.258290 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8016 22:12:01.261834 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8017 22:12:01.261934
8018 22:12:01.264609 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8019 22:12:01.268263 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8020 22:12:01.271542 [Gating] SW calibration Done
8021 22:12:01.271665 ==
8022 22:12:01.274678 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 22:12:01.278305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 22:12:01.278453 ==
8025 22:12:01.281594 RX Vref Scan: 0
8026 22:12:01.281715
8027 22:12:01.281825 RX Vref 0 -> 0, step: 1
8028 22:12:01.281937
8029 22:12:01.285024 RX Delay 0 -> 252, step: 8
8030 22:12:01.288006 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8031 22:12:01.291512 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8032 22:12:01.297985 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8033 22:12:01.301614 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8034 22:12:01.304892 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8035 22:12:01.307940 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8036 22:12:01.311314 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8037 22:12:01.318248 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8038 22:12:01.321592 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8039 22:12:01.324867 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8040 22:12:01.328025 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8041 22:12:01.331445 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8042 22:12:01.338264 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8043 22:12:01.341791 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8044 22:12:01.344840 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8045 22:12:01.348224 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8046 22:12:01.348307 ==
8047 22:12:01.351810 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 22:12:01.358307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 22:12:01.358390 ==
8050 22:12:01.358454 DQS Delay:
8051 22:12:01.358514 DQS0 = 0, DQS1 = 0
8052 22:12:01.361985 DQM Delay:
8053 22:12:01.362067 DQM0 = 137, DQM1 = 129
8054 22:12:01.364837 DQ Delay:
8055 22:12:01.368193 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8056 22:12:01.371377 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8057 22:12:01.375136 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8058 22:12:01.378091 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =139
8059 22:12:01.378174
8060 22:12:01.378238
8061 22:12:01.378297 ==
8062 22:12:01.381533 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 22:12:01.384689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 22:12:01.388358 ==
8065 22:12:01.388441
8066 22:12:01.388505
8067 22:12:01.388564 TX Vref Scan disable
8068 22:12:01.391513 == TX Byte 0 ==
8069 22:12:01.395041 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8070 22:12:01.398361 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8071 22:12:01.401642 == TX Byte 1 ==
8072 22:12:01.404827 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8073 22:12:01.408211 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8074 22:12:01.408294 ==
8075 22:12:01.411915 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 22:12:01.418276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 22:12:01.418359 ==
8078 22:12:01.431073
8079 22:12:01.434767 TX Vref early break, caculate TX vref
8080 22:12:01.437584 TX Vref=16, minBit 1, minWin=22, winSum=384
8081 22:12:01.440662 TX Vref=18, minBit 1, minWin=23, winSum=391
8082 22:12:01.444215 TX Vref=20, minBit 1, minWin=24, winSum=405
8083 22:12:01.447845 TX Vref=22, minBit 0, minWin=25, winSum=414
8084 22:12:01.450893 TX Vref=24, minBit 1, minWin=25, winSum=418
8085 22:12:01.457705 TX Vref=26, minBit 1, minWin=25, winSum=427
8086 22:12:01.460828 TX Vref=28, minBit 7, minWin=24, winSum=425
8087 22:12:01.464150 TX Vref=30, minBit 0, minWin=25, winSum=417
8088 22:12:01.467440 TX Vref=32, minBit 4, minWin=24, winSum=410
8089 22:12:01.470536 TX Vref=34, minBit 0, minWin=24, winSum=402
8090 22:12:01.477360 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 26
8091 22:12:01.477447
8092 22:12:01.480546 Final TX Range 0 Vref 26
8093 22:12:01.480630
8094 22:12:01.480694 ==
8095 22:12:01.484211 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 22:12:01.487470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 22:12:01.487553 ==
8098 22:12:01.487646
8099 22:12:01.487722
8100 22:12:01.490505 TX Vref Scan disable
8101 22:12:01.497492 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8102 22:12:01.497575 == TX Byte 0 ==
8103 22:12:01.500466 u2DelayCellOfst[0]=13 cells (4 PI)
8104 22:12:01.504231 u2DelayCellOfst[1]=16 cells (5 PI)
8105 22:12:01.507420 u2DelayCellOfst[2]=13 cells (4 PI)
8106 22:12:01.510639 u2DelayCellOfst[3]=13 cells (4 PI)
8107 22:12:01.513850 u2DelayCellOfst[4]=10 cells (3 PI)
8108 22:12:01.517216 u2DelayCellOfst[5]=0 cells (0 PI)
8109 22:12:01.520453 u2DelayCellOfst[6]=16 cells (5 PI)
8110 22:12:01.523999 u2DelayCellOfst[7]=16 cells (5 PI)
8111 22:12:01.527123 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8112 22:12:01.530600 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8113 22:12:01.533689 == TX Byte 1 ==
8114 22:12:01.533773 u2DelayCellOfst[8]=0 cells (0 PI)
8115 22:12:01.537166 u2DelayCellOfst[9]=0 cells (0 PI)
8116 22:12:01.540523 u2DelayCellOfst[10]=6 cells (2 PI)
8117 22:12:01.543625 u2DelayCellOfst[11]=6 cells (2 PI)
8118 22:12:01.546851 u2DelayCellOfst[12]=10 cells (3 PI)
8119 22:12:01.550546 u2DelayCellOfst[13]=10 cells (3 PI)
8120 22:12:01.553569 u2DelayCellOfst[14]=13 cells (4 PI)
8121 22:12:01.557356 u2DelayCellOfst[15]=10 cells (3 PI)
8122 22:12:01.560718 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8123 22:12:01.567224 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8124 22:12:01.567308 DramC Write-DBI on
8125 22:12:01.567374 ==
8126 22:12:01.570312 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 22:12:01.573620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 22:12:01.576694 ==
8129 22:12:01.576777
8130 22:12:01.576841
8131 22:12:01.576900 TX Vref Scan disable
8132 22:12:01.580396 == TX Byte 0 ==
8133 22:12:01.583475 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8134 22:12:01.587191 == TX Byte 1 ==
8135 22:12:01.590366 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8136 22:12:01.593766 DramC Write-DBI off
8137 22:12:01.593848
8138 22:12:01.593912 [DATLAT]
8139 22:12:01.593972 Freq=1600, CH0 RK1
8140 22:12:01.594054
8141 22:12:01.596691 DATLAT Default: 0xf
8142 22:12:01.596774 0, 0xFFFF, sum = 0
8143 22:12:01.600240 1, 0xFFFF, sum = 0
8144 22:12:01.603568 2, 0xFFFF, sum = 0
8145 22:12:01.603689 3, 0xFFFF, sum = 0
8146 22:12:01.607245 4, 0xFFFF, sum = 0
8147 22:12:01.607329 5, 0xFFFF, sum = 0
8148 22:12:01.610477 6, 0xFFFF, sum = 0
8149 22:12:01.610561 7, 0xFFFF, sum = 0
8150 22:12:01.613496 8, 0xFFFF, sum = 0
8151 22:12:01.613595 9, 0xFFFF, sum = 0
8152 22:12:01.616839 10, 0xFFFF, sum = 0
8153 22:12:01.616923 11, 0xFFFF, sum = 0
8154 22:12:01.620156 12, 0xFFFF, sum = 0
8155 22:12:01.620242 13, 0xFFFF, sum = 0
8156 22:12:01.623851 14, 0x0, sum = 1
8157 22:12:01.623935 15, 0x0, sum = 2
8158 22:12:01.627146 16, 0x0, sum = 3
8159 22:12:01.627230 17, 0x0, sum = 4
8160 22:12:01.630339 best_step = 15
8161 22:12:01.630422
8162 22:12:01.630486 ==
8163 22:12:01.633386 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 22:12:01.637162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 22:12:01.637246 ==
8166 22:12:01.637311 RX Vref Scan: 0
8167 22:12:01.640078
8168 22:12:01.640160 RX Vref 0 -> 0, step: 1
8169 22:12:01.640242
8170 22:12:01.643820 RX Delay 19 -> 252, step: 4
8171 22:12:01.646575 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8172 22:12:01.653305 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8173 22:12:01.656940 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8174 22:12:01.660710 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8175 22:12:01.663928 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8176 22:12:01.666591 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8177 22:12:01.673230 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8178 22:12:01.676902 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8179 22:12:01.680261 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8180 22:12:01.683477 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8181 22:12:01.686767 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8182 22:12:01.693434 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8183 22:12:01.696764 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8184 22:12:01.699897 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8185 22:12:01.703223 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8186 22:12:01.706608 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8187 22:12:01.710095 ==
8188 22:12:01.710192 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 22:12:01.716503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 22:12:01.716586 ==
8191 22:12:01.716650 DQS Delay:
8192 22:12:01.719790 DQS0 = 0, DQS1 = 0
8193 22:12:01.719873 DQM Delay:
8194 22:12:01.723454 DQM0 = 134, DQM1 = 127
8195 22:12:01.723537 DQ Delay:
8196 22:12:01.726784 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8197 22:12:01.729918 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8198 22:12:01.733123 DQ8 =118, DQ9 =116, DQ10 =130, DQ11 =118
8199 22:12:01.736491 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8200 22:12:01.736573
8201 22:12:01.736638
8202 22:12:01.736698
8203 22:12:01.740065 [DramC_TX_OE_Calibration] TA2
8204 22:12:01.742954 Original DQ_B0 (3 6) =30, OEN = 27
8205 22:12:01.746227 Original DQ_B1 (3 6) =30, OEN = 27
8206 22:12:01.749680 24, 0x0, End_B0=24 End_B1=24
8207 22:12:01.753087 25, 0x0, End_B0=25 End_B1=25
8208 22:12:01.753216 26, 0x0, End_B0=26 End_B1=26
8209 22:12:01.756355 27, 0x0, End_B0=27 End_B1=27
8210 22:12:01.759522 28, 0x0, End_B0=28 End_B1=28
8211 22:12:01.763345 29, 0x0, End_B0=29 End_B1=29
8212 22:12:01.763469 30, 0x0, End_B0=30 End_B1=30
8213 22:12:01.766529 31, 0x4141, End_B0=30 End_B1=30
8214 22:12:01.770025 Byte0 end_step=30 best_step=27
8215 22:12:01.773248 Byte1 end_step=30 best_step=27
8216 22:12:01.776418 Byte0 TX OE(2T, 0.5T) = (3, 3)
8217 22:12:01.780215 Byte1 TX OE(2T, 0.5T) = (3, 3)
8218 22:12:01.780336
8219 22:12:01.780448
8220 22:12:01.786590 [DQSOSCAuto] RK1, (LSB)MR18= 0x210a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
8221 22:12:01.789798 CH0 RK1: MR19=303, MR18=210A
8222 22:12:01.796447 CH0_RK1: MR19=0x303, MR18=0x210A, DQSOSC=393, MR23=63, INC=23, DEC=15
8223 22:12:01.799658 [RxdqsGatingPostProcess] freq 1600
8224 22:12:01.802796 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8225 22:12:01.806613 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 22:12:01.809640 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 22:12:01.813213 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 22:12:01.816071 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 22:12:01.819553 best DQS0 dly(2T, 0.5T) = (1, 1)
8230 22:12:01.822911 best DQS1 dly(2T, 0.5T) = (1, 1)
8231 22:12:01.826267 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8232 22:12:01.829486 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8233 22:12:01.833153 Pre-setting of DQS Precalculation
8234 22:12:01.836333 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8235 22:12:01.836435 ==
8236 22:12:01.839569 Dram Type= 6, Freq= 0, CH_1, rank 0
8237 22:12:01.842712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 22:12:01.846348 ==
8239 22:12:01.849556 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8240 22:12:01.853130 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8241 22:12:01.859764 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8242 22:12:01.866205 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8243 22:12:01.873206 [CA 0] Center 41 (12~71) winsize 60
8244 22:12:01.876670 [CA 1] Center 41 (12~71) winsize 60
8245 22:12:01.879811 [CA 2] Center 39 (10~68) winsize 59
8246 22:12:01.883456 [CA 3] Center 37 (9~66) winsize 58
8247 22:12:01.886639 [CA 4] Center 38 (9~68) winsize 60
8248 22:12:01.889934 [CA 5] Center 37 (8~66) winsize 59
8249 22:12:01.890016
8250 22:12:01.893142 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8251 22:12:01.893224
8252 22:12:01.896524 [CATrainingPosCal] consider 1 rank data
8253 22:12:01.899805 u2DelayCellTimex100 = 290/100 ps
8254 22:12:01.903256 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8255 22:12:01.909673 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8256 22:12:01.913401 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8257 22:12:01.916867 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8258 22:12:01.919945 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8259 22:12:01.923378 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8260 22:12:01.923460
8261 22:12:01.926637 CA PerBit enable=1, Macro0, CA PI delay=37
8262 22:12:01.926720
8263 22:12:01.929798 [CBTSetCACLKResult] CA Dly = 37
8264 22:12:01.933449 CS Dly: 10 (0~41)
8265 22:12:01.936996 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8266 22:12:01.940038 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8267 22:12:01.940121 ==
8268 22:12:01.943174 Dram Type= 6, Freq= 0, CH_1, rank 1
8269 22:12:01.946176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 22:12:01.950048 ==
8271 22:12:01.953044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8272 22:12:01.956289 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8273 22:12:01.962963 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8274 22:12:01.966354 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8275 22:12:01.976607 [CA 0] Center 42 (12~72) winsize 61
8276 22:12:01.979842 [CA 1] Center 42 (13~72) winsize 60
8277 22:12:01.983560 [CA 2] Center 39 (10~68) winsize 59
8278 22:12:01.986717 [CA 3] Center 38 (8~68) winsize 61
8279 22:12:01.990019 [CA 4] Center 38 (9~68) winsize 60
8280 22:12:01.993130 [CA 5] Center 37 (8~67) winsize 60
8281 22:12:01.993213
8282 22:12:01.996806 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8283 22:12:01.996888
8284 22:12:02.000202 [CATrainingPosCal] consider 2 rank data
8285 22:12:02.003424 u2DelayCellTimex100 = 290/100 ps
8286 22:12:02.006657 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8287 22:12:02.013196 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8288 22:12:02.016636 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8289 22:12:02.020145 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8290 22:12:02.023444 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8291 22:12:02.026680 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8292 22:12:02.026763
8293 22:12:02.030032 CA PerBit enable=1, Macro0, CA PI delay=37
8294 22:12:02.030116
8295 22:12:02.033309 [CBTSetCACLKResult] CA Dly = 37
8296 22:12:02.036481 CS Dly: 12 (0~45)
8297 22:12:02.040153 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8298 22:12:02.043406 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8299 22:12:02.043488
8300 22:12:02.046616 ----->DramcWriteLeveling(PI) begin...
8301 22:12:02.046700 ==
8302 22:12:02.049808 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 22:12:02.056481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 22:12:02.056564 ==
8305 22:12:02.059715 Write leveling (Byte 0): 25 => 25
8306 22:12:02.059798 Write leveling (Byte 1): 29 => 29
8307 22:12:02.062816 DramcWriteLeveling(PI) end<-----
8308 22:12:02.062924
8309 22:12:02.063015 ==
8310 22:12:02.066796 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 22:12:02.073266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 22:12:02.073349 ==
8313 22:12:02.076150 [Gating] SW mode calibration
8314 22:12:02.083328 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8315 22:12:02.086575 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8316 22:12:02.092909 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 22:12:02.096241 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 22:12:02.099371 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8319 22:12:02.105994 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8320 22:12:02.109699 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 22:12:02.112751 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 22:12:02.119448 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 22:12:02.122813 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 22:12:02.126106 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 22:12:02.132860 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8326 22:12:02.136066 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
8327 22:12:02.139867 1 5 12 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
8328 22:12:02.142654 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 22:12:02.149701 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 22:12:02.152632 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 22:12:02.156199 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 22:12:02.162890 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 22:12:02.166361 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 22:12:02.169583 1 6 8 | B1->B0 | 2525 3737 | 0 0 | (0 0) (1 1)
8335 22:12:02.175893 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 22:12:02.179501 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 22:12:02.182882 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 22:12:02.189546 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 22:12:02.192769 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 22:12:02.195975 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 22:12:02.202719 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 22:12:02.206103 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8343 22:12:02.209234 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8344 22:12:02.216476 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 22:12:02.219342 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 22:12:02.222882 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 22:12:02.229665 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 22:12:02.232523 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 22:12:02.236263 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 22:12:02.239769 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 22:12:02.246163 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 22:12:02.249305 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 22:12:02.252516 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 22:12:02.259526 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 22:12:02.262431 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 22:12:02.266108 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 22:12:02.272832 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 22:12:02.276022 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8359 22:12:02.279148 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8360 22:12:02.285871 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 22:12:02.289120 Total UI for P1: 0, mck2ui 16
8362 22:12:02.292450 best dqsien dly found for B0: ( 1, 9, 10)
8363 22:12:02.292580 Total UI for P1: 0, mck2ui 16
8364 22:12:02.299023 best dqsien dly found for B1: ( 1, 9, 10)
8365 22:12:02.302333 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8366 22:12:02.305614 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8367 22:12:02.305699
8368 22:12:02.308969 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8369 22:12:02.312270 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8370 22:12:02.315980 [Gating] SW calibration Done
8371 22:12:02.316064 ==
8372 22:12:02.319292 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 22:12:02.322437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 22:12:02.322525 ==
8375 22:12:02.325585 RX Vref Scan: 0
8376 22:12:02.325716
8377 22:12:02.325835 RX Vref 0 -> 0, step: 1
8378 22:12:02.328907
8379 22:12:02.329030 RX Delay 0 -> 252, step: 8
8380 22:12:02.332336 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8381 22:12:02.338772 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8382 22:12:02.342245 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8383 22:12:02.345447 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8384 22:12:02.348891 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8385 22:12:02.352115 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8386 22:12:02.358671 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8387 22:12:02.362385 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8388 22:12:02.365695 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8389 22:12:02.368944 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8390 22:12:02.372444 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8391 22:12:02.378871 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8392 22:12:02.382526 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8393 22:12:02.385685 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8394 22:12:02.388909 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8395 22:12:02.392198 iDelay=200, Bit 15, Center 147 (96 ~ 199) 104
8396 22:12:02.395439 ==
8397 22:12:02.395524 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 22:12:02.402327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 22:12:02.402413 ==
8400 22:12:02.402479 DQS Delay:
8401 22:12:02.405635 DQS0 = 0, DQS1 = 0
8402 22:12:02.405719 DQM Delay:
8403 22:12:02.408642 DQM0 = 136, DQM1 = 134
8404 22:12:02.408726 DQ Delay:
8405 22:12:02.412386 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8406 22:12:02.415636 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8407 22:12:02.418876 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8408 22:12:02.422094 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =147
8409 22:12:02.422178
8410 22:12:02.422244
8411 22:12:02.422305 ==
8412 22:12:02.425270 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 22:12:02.431796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 22:12:02.431882 ==
8415 22:12:02.431948
8416 22:12:02.432010
8417 22:12:02.432068 TX Vref Scan disable
8418 22:12:02.435824 == TX Byte 0 ==
8419 22:12:02.439334 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8420 22:12:02.445532 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8421 22:12:02.445621 == TX Byte 1 ==
8422 22:12:02.448789 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8423 22:12:02.455699 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8424 22:12:02.455783 ==
8425 22:12:02.459194 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 22:12:02.462450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 22:12:02.462536 ==
8428 22:12:02.474492
8429 22:12:02.478003 TX Vref early break, caculate TX vref
8430 22:12:02.481229 TX Vref=16, minBit 1, minWin=23, winSum=376
8431 22:12:02.484567 TX Vref=18, minBit 0, minWin=23, winSum=385
8432 22:12:02.487722 TX Vref=20, minBit 6, minWin=23, winSum=397
8433 22:12:02.491092 TX Vref=22, minBit 0, minWin=24, winSum=406
8434 22:12:02.494412 TX Vref=24, minBit 1, minWin=25, winSum=414
8435 22:12:02.500832 TX Vref=26, minBit 0, minWin=25, winSum=425
8436 22:12:02.504632 TX Vref=28, minBit 6, minWin=24, winSum=421
8437 22:12:02.507905 TX Vref=30, minBit 0, minWin=25, winSum=418
8438 22:12:02.510993 TX Vref=32, minBit 0, minWin=25, winSum=413
8439 22:12:02.514434 TX Vref=34, minBit 0, minWin=24, winSum=400
8440 22:12:02.520719 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8441 22:12:02.520804
8442 22:12:02.524718 Final TX Range 0 Vref 26
8443 22:12:02.524801
8444 22:12:02.524865 ==
8445 22:12:02.527952 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 22:12:02.531169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 22:12:02.531266 ==
8448 22:12:02.531353
8449 22:12:02.531415
8450 22:12:02.534269 TX Vref Scan disable
8451 22:12:02.540790 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8452 22:12:02.540874 == TX Byte 0 ==
8453 22:12:02.544254 u2DelayCellOfst[0]=16 cells (5 PI)
8454 22:12:02.547898 u2DelayCellOfst[1]=10 cells (3 PI)
8455 22:12:02.550940 u2DelayCellOfst[2]=0 cells (0 PI)
8456 22:12:02.554710 u2DelayCellOfst[3]=6 cells (2 PI)
8457 22:12:02.557459 u2DelayCellOfst[4]=6 cells (2 PI)
8458 22:12:02.561143 u2DelayCellOfst[5]=13 cells (4 PI)
8459 22:12:02.564264 u2DelayCellOfst[6]=16 cells (5 PI)
8460 22:12:02.564347 u2DelayCellOfst[7]=6 cells (2 PI)
8461 22:12:02.571055 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8462 22:12:02.574088 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8463 22:12:02.574175 == TX Byte 1 ==
8464 22:12:02.577649 u2DelayCellOfst[8]=0 cells (0 PI)
8465 22:12:02.580914 u2DelayCellOfst[9]=3 cells (1 PI)
8466 22:12:02.584155 u2DelayCellOfst[10]=13 cells (4 PI)
8467 22:12:02.587322 u2DelayCellOfst[11]=3 cells (1 PI)
8468 22:12:02.590991 u2DelayCellOfst[12]=16 cells (5 PI)
8469 22:12:02.594156 u2DelayCellOfst[13]=16 cells (5 PI)
8470 22:12:02.597431 u2DelayCellOfst[14]=16 cells (5 PI)
8471 22:12:02.600832 u2DelayCellOfst[15]=16 cells (5 PI)
8472 22:12:02.604199 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8473 22:12:02.610581 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8474 22:12:02.610682 DramC Write-DBI on
8475 22:12:02.610773 ==
8476 22:12:02.613920 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 22:12:02.617403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 22:12:02.620375 ==
8479 22:12:02.620449
8480 22:12:02.620511
8481 22:12:02.620575 TX Vref Scan disable
8482 22:12:02.623538 == TX Byte 0 ==
8483 22:12:02.626978 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8484 22:12:02.630840 == TX Byte 1 ==
8485 22:12:02.634046 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8486 22:12:02.637302 DramC Write-DBI off
8487 22:12:02.637429
8488 22:12:02.637547 [DATLAT]
8489 22:12:02.637652 Freq=1600, CH1 RK0
8490 22:12:02.637765
8491 22:12:02.640616 DATLAT Default: 0xf
8492 22:12:02.640742 0, 0xFFFF, sum = 0
8493 22:12:02.643781 1, 0xFFFF, sum = 0
8494 22:12:02.643910 2, 0xFFFF, sum = 0
8495 22:12:02.647700 3, 0xFFFF, sum = 0
8496 22:12:02.650463 4, 0xFFFF, sum = 0
8497 22:12:02.650582 5, 0xFFFF, sum = 0
8498 22:12:02.653841 6, 0xFFFF, sum = 0
8499 22:12:02.653966 7, 0xFFFF, sum = 0
8500 22:12:02.657171 8, 0xFFFF, sum = 0
8501 22:12:02.657299 9, 0xFFFF, sum = 0
8502 22:12:02.660360 10, 0xFFFF, sum = 0
8503 22:12:02.660489 11, 0xFFFF, sum = 0
8504 22:12:02.663918 12, 0xFFFF, sum = 0
8505 22:12:02.664046 13, 0xFFFF, sum = 0
8506 22:12:02.667169 14, 0x0, sum = 1
8507 22:12:02.667296 15, 0x0, sum = 2
8508 22:12:02.670192 16, 0x0, sum = 3
8509 22:12:02.670319 17, 0x0, sum = 4
8510 22:12:02.673400 best_step = 15
8511 22:12:02.673505
8512 22:12:02.673597 ==
8513 22:12:02.676690 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 22:12:02.680188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 22:12:02.680315 ==
8516 22:12:02.683426 RX Vref Scan: 1
8517 22:12:02.683553
8518 22:12:02.683673 Set Vref Range= 24 -> 127
8519 22:12:02.683787
8520 22:12:02.687159 RX Vref 24 -> 127, step: 1
8521 22:12:02.687285
8522 22:12:02.690365 RX Delay 27 -> 252, step: 4
8523 22:12:02.690489
8524 22:12:02.693418 Set Vref, RX VrefLevel [Byte0]: 24
8525 22:12:02.696864 [Byte1]: 24
8526 22:12:02.696995
8527 22:12:02.700139 Set Vref, RX VrefLevel [Byte0]: 25
8528 22:12:02.703227 [Byte1]: 25
8529 22:12:02.703353
8530 22:12:02.706624 Set Vref, RX VrefLevel [Byte0]: 26
8531 22:12:02.710130 [Byte1]: 26
8532 22:12:02.713840
8533 22:12:02.713966 Set Vref, RX VrefLevel [Byte0]: 27
8534 22:12:02.717120 [Byte1]: 27
8535 22:12:02.721672
8536 22:12:02.721794 Set Vref, RX VrefLevel [Byte0]: 28
8537 22:12:02.724739 [Byte1]: 28
8538 22:12:02.729357
8539 22:12:02.729484 Set Vref, RX VrefLevel [Byte0]: 29
8540 22:12:02.732552 [Byte1]: 29
8541 22:12:02.736386
8542 22:12:02.736510 Set Vref, RX VrefLevel [Byte0]: 30
8543 22:12:02.739884 [Byte1]: 30
8544 22:12:02.744248
8545 22:12:02.744376 Set Vref, RX VrefLevel [Byte0]: 31
8546 22:12:02.747574 [Byte1]: 31
8547 22:12:02.751472
8548 22:12:02.751603 Set Vref, RX VrefLevel [Byte0]: 32
8549 22:12:02.755218 [Byte1]: 32
8550 22:12:02.759366
8551 22:12:02.759493 Set Vref, RX VrefLevel [Byte0]: 33
8552 22:12:02.762945 [Byte1]: 33
8553 22:12:02.766917
8554 22:12:02.767039 Set Vref, RX VrefLevel [Byte0]: 34
8555 22:12:02.769850 [Byte1]: 34
8556 22:12:02.774126
8557 22:12:02.774252 Set Vref, RX VrefLevel [Byte0]: 35
8558 22:12:02.777810 [Byte1]: 35
8559 22:12:02.781863
8560 22:12:02.781992 Set Vref, RX VrefLevel [Byte0]: 36
8561 22:12:02.784920 [Byte1]: 36
8562 22:12:02.789060
8563 22:12:02.789186 Set Vref, RX VrefLevel [Byte0]: 37
8564 22:12:02.792753 [Byte1]: 37
8565 22:12:02.796551
8566 22:12:02.796677 Set Vref, RX VrefLevel [Byte0]: 38
8567 22:12:02.799812 [Byte1]: 38
8568 22:12:02.804553
8569 22:12:02.804637 Set Vref, RX VrefLevel [Byte0]: 39
8570 22:12:02.807382 [Byte1]: 39
8571 22:12:02.811916
8572 22:12:02.812000 Set Vref, RX VrefLevel [Byte0]: 40
8573 22:12:02.815200 [Byte1]: 40
8574 22:12:02.819713
8575 22:12:02.819797 Set Vref, RX VrefLevel [Byte0]: 41
8576 22:12:02.822899 [Byte1]: 41
8577 22:12:02.827244
8578 22:12:02.827368 Set Vref, RX VrefLevel [Byte0]: 42
8579 22:12:02.830612 [Byte1]: 42
8580 22:12:02.834630
8581 22:12:02.834756 Set Vref, RX VrefLevel [Byte0]: 43
8582 22:12:02.837881 [Byte1]: 43
8583 22:12:02.842260
8584 22:12:02.842388 Set Vref, RX VrefLevel [Byte0]: 44
8585 22:12:02.845470 [Byte1]: 44
8586 22:12:02.849409
8587 22:12:02.849534 Set Vref, RX VrefLevel [Byte0]: 45
8588 22:12:02.852679 [Byte1]: 45
8589 22:12:02.857276
8590 22:12:02.857401 Set Vref, RX VrefLevel [Byte0]: 46
8591 22:12:02.860487 [Byte1]: 46
8592 22:12:02.864872
8593 22:12:02.864995 Set Vref, RX VrefLevel [Byte0]: 47
8594 22:12:02.868158 [Byte1]: 47
8595 22:12:02.871916
8596 22:12:02.872040 Set Vref, RX VrefLevel [Byte0]: 48
8597 22:12:02.875508 [Byte1]: 48
8598 22:12:02.880082
8599 22:12:02.880207 Set Vref, RX VrefLevel [Byte0]: 49
8600 22:12:02.883035 [Byte1]: 49
8601 22:12:02.887045
8602 22:12:02.887168 Set Vref, RX VrefLevel [Byte0]: 50
8603 22:12:02.890355 [Byte1]: 50
8604 22:12:02.894757
8605 22:12:02.894881 Set Vref, RX VrefLevel [Byte0]: 51
8606 22:12:02.897950 [Byte1]: 51
8607 22:12:02.902195
8608 22:12:02.902316 Set Vref, RX VrefLevel [Byte0]: 52
8609 22:12:02.905711 [Byte1]: 52
8610 22:12:02.909748
8611 22:12:02.909879 Set Vref, RX VrefLevel [Byte0]: 53
8612 22:12:02.913351 [Byte1]: 53
8613 22:12:02.917246
8614 22:12:02.917369 Set Vref, RX VrefLevel [Byte0]: 54
8615 22:12:02.920586 [Byte1]: 54
8616 22:12:02.924736
8617 22:12:02.924861 Set Vref, RX VrefLevel [Byte0]: 55
8618 22:12:02.928097 [Byte1]: 55
8619 22:12:02.932588
8620 22:12:02.932715 Set Vref, RX VrefLevel [Byte0]: 56
8621 22:12:02.935486 [Byte1]: 56
8622 22:12:02.940029
8623 22:12:02.940155 Set Vref, RX VrefLevel [Byte0]: 57
8624 22:12:02.943132 [Byte1]: 57
8625 22:12:02.947472
8626 22:12:02.947604 Set Vref, RX VrefLevel [Byte0]: 58
8627 22:12:02.950697 [Byte1]: 58
8628 22:12:02.955109
8629 22:12:02.955234 Set Vref, RX VrefLevel [Byte0]: 59
8630 22:12:02.958387 [Byte1]: 59
8631 22:12:02.962551
8632 22:12:02.962675 Set Vref, RX VrefLevel [Byte0]: 60
8633 22:12:02.965545 [Byte1]: 60
8634 22:12:02.969940
8635 22:12:02.970064 Set Vref, RX VrefLevel [Byte0]: 61
8636 22:12:02.973193 [Byte1]: 61
8637 22:12:02.977548
8638 22:12:02.977669 Set Vref, RX VrefLevel [Byte0]: 62
8639 22:12:02.980853 [Byte1]: 62
8640 22:12:02.985293
8641 22:12:02.985417 Set Vref, RX VrefLevel [Byte0]: 63
8642 22:12:02.988789 [Byte1]: 63
8643 22:12:02.992424
8644 22:12:02.992547 Set Vref, RX VrefLevel [Byte0]: 64
8645 22:12:02.995946 [Byte1]: 64
8646 22:12:03.000409
8647 22:12:03.000536 Set Vref, RX VrefLevel [Byte0]: 65
8648 22:12:03.003721 [Byte1]: 65
8649 22:12:03.007875
8650 22:12:03.007997 Set Vref, RX VrefLevel [Byte0]: 66
8651 22:12:03.011399 [Byte1]: 66
8652 22:12:03.015385
8653 22:12:03.015506 Set Vref, RX VrefLevel [Byte0]: 67
8654 22:12:03.018325 [Byte1]: 67
8655 22:12:03.022680
8656 22:12:03.022801 Set Vref, RX VrefLevel [Byte0]: 68
8657 22:12:03.026207 [Byte1]: 68
8658 22:12:03.030322
8659 22:12:03.030447 Set Vref, RX VrefLevel [Byte0]: 69
8660 22:12:03.033577 [Byte1]: 69
8661 22:12:03.037719
8662 22:12:03.037828 Set Vref, RX VrefLevel [Byte0]: 70
8663 22:12:03.040928 [Byte1]: 70
8664 22:12:03.045142
8665 22:12:03.045227 Set Vref, RX VrefLevel [Byte0]: 71
8666 22:12:03.048749 [Byte1]: 71
8667 22:12:03.053024
8668 22:12:03.053108 Set Vref, RX VrefLevel [Byte0]: 72
8669 22:12:03.056247 [Byte1]: 72
8670 22:12:03.060215
8671 22:12:03.060342 Set Vref, RX VrefLevel [Byte0]: 73
8672 22:12:03.064001 [Byte1]: 73
8673 22:12:03.067885
8674 22:12:03.068014 Set Vref, RX VrefLevel [Byte0]: 74
8675 22:12:03.071521 [Byte1]: 74
8676 22:12:03.075409
8677 22:12:03.075534 Set Vref, RX VrefLevel [Byte0]: 75
8678 22:12:03.079084 [Byte1]: 75
8679 22:12:03.082946
8680 22:12:03.083066 Set Vref, RX VrefLevel [Byte0]: 76
8681 22:12:03.086484 [Byte1]: 76
8682 22:12:03.090879
8683 22:12:03.091005 Final RX Vref Byte 0 = 58 to rank0
8684 22:12:03.094051 Final RX Vref Byte 1 = 56 to rank0
8685 22:12:03.097554 Final RX Vref Byte 0 = 58 to rank1
8686 22:12:03.100694 Final RX Vref Byte 1 = 56 to rank1==
8687 22:12:03.104555 Dram Type= 6, Freq= 0, CH_1, rank 0
8688 22:12:03.107490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8689 22:12:03.110517 ==
8690 22:12:03.110641 DQS Delay:
8691 22:12:03.110755 DQS0 = 0, DQS1 = 0
8692 22:12:03.114269 DQM Delay:
8693 22:12:03.114394 DQM0 = 134, DQM1 = 131
8694 22:12:03.117101 DQ Delay:
8695 22:12:03.120528 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8696 22:12:03.124098 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8697 22:12:03.127454 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8698 22:12:03.130821 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8699 22:12:03.130948
8700 22:12:03.131063
8701 22:12:03.131174
8702 22:12:03.134011 [DramC_TX_OE_Calibration] TA2
8703 22:12:03.137546 Original DQ_B0 (3 6) =30, OEN = 27
8704 22:12:03.140672 Original DQ_B1 (3 6) =30, OEN = 27
8705 22:12:03.144259 24, 0x0, End_B0=24 End_B1=24
8706 22:12:03.144389 25, 0x0, End_B0=25 End_B1=25
8707 22:12:03.147399 26, 0x0, End_B0=26 End_B1=26
8708 22:12:03.150709 27, 0x0, End_B0=27 End_B1=27
8709 22:12:03.153698 28, 0x0, End_B0=28 End_B1=28
8710 22:12:03.153824 29, 0x0, End_B0=29 End_B1=29
8711 22:12:03.157312 30, 0x0, End_B0=30 End_B1=30
8712 22:12:03.160571 31, 0x4141, End_B0=30 End_B1=30
8713 22:12:03.163654 Byte0 end_step=30 best_step=27
8714 22:12:03.167526 Byte1 end_step=30 best_step=27
8715 22:12:03.170793 Byte0 TX OE(2T, 0.5T) = (3, 3)
8716 22:12:03.170890 Byte1 TX OE(2T, 0.5T) = (3, 3)
8717 22:12:03.170980
8718 22:12:03.173899
8719 22:12:03.180943 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8720 22:12:03.183706 CH1 RK0: MR19=303, MR18=1623
8721 22:12:03.190595 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8722 22:12:03.190695
8723 22:12:03.193700 ----->DramcWriteLeveling(PI) begin...
8724 22:12:03.193799 ==
8725 22:12:03.196943 Dram Type= 6, Freq= 0, CH_1, rank 1
8726 22:12:03.200317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8727 22:12:03.200389 ==
8728 22:12:03.204101 Write leveling (Byte 0): 25 => 25
8729 22:12:03.207374 Write leveling (Byte 1): 29 => 29
8730 22:12:03.210698 DramcWriteLeveling(PI) end<-----
8731 22:12:03.210796
8732 22:12:03.210885 ==
8733 22:12:03.213938 Dram Type= 6, Freq= 0, CH_1, rank 1
8734 22:12:03.216875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8735 22:12:03.216950 ==
8736 22:12:03.220462 [Gating] SW mode calibration
8737 22:12:03.226876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8738 22:12:03.233349 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8739 22:12:03.236903 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 22:12:03.240032 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 22:12:03.246888 1 4 8 | B1->B0 | 2424 2323 | 1 0 | (1 1) (0 0)
8742 22:12:03.250098 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8743 22:12:03.253390 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 22:12:03.260212 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 22:12:03.263678 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 22:12:03.266816 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 22:12:03.273192 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 22:12:03.276768 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8749 22:12:03.280503 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8750 22:12:03.286859 1 5 12 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 1)
8751 22:12:03.290245 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8752 22:12:03.293353 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 22:12:03.299853 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 22:12:03.303708 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 22:12:03.306791 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 22:12:03.313393 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 22:12:03.316625 1 6 8 | B1->B0 | 3f3f 2323 | 0 0 | (1 1) (0 0)
8758 22:12:03.319967 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8759 22:12:03.323250 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 22:12:03.329845 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 22:12:03.332943 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 22:12:03.336636 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 22:12:03.343097 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 22:12:03.346290 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 22:12:03.349833 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8766 22:12:03.356177 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8767 22:12:03.359532 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 22:12:03.363124 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 22:12:03.369772 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 22:12:03.373139 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 22:12:03.376169 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 22:12:03.382977 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 22:12:03.386320 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 22:12:03.389490 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 22:12:03.396144 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 22:12:03.399547 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 22:12:03.402703 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 22:12:03.409925 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 22:12:03.413173 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 22:12:03.416473 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8781 22:12:03.422904 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8782 22:12:03.426104 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8783 22:12:03.429408 Total UI for P1: 0, mck2ui 16
8784 22:12:03.432525 best dqsien dly found for B1: ( 1, 9, 6)
8785 22:12:03.436033 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8786 22:12:03.442661 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 22:12:03.442751 Total UI for P1: 0, mck2ui 16
8788 22:12:03.449558 best dqsien dly found for B0: ( 1, 9, 14)
8789 22:12:03.452834 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8790 22:12:03.455991 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8791 22:12:03.456098
8792 22:12:03.459123 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8793 22:12:03.462619 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8794 22:12:03.465947 [Gating] SW calibration Done
8795 22:12:03.466082 ==
8796 22:12:03.470247 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 22:12:03.472622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 22:12:03.472751 ==
8799 22:12:03.475974 RX Vref Scan: 0
8800 22:12:03.476097
8801 22:12:03.476247 RX Vref 0 -> 0, step: 1
8802 22:12:03.476399
8803 22:12:03.479165 RX Delay 0 -> 252, step: 8
8804 22:12:03.482477 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8805 22:12:03.488700 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8806 22:12:03.492239 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8807 22:12:03.495510 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8808 22:12:03.498848 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8809 22:12:03.502159 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8810 22:12:03.508898 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8811 22:12:03.512322 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8812 22:12:03.515568 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8813 22:12:03.518760 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8814 22:12:03.521905 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8815 22:12:03.528546 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8816 22:12:03.532238 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8817 22:12:03.535584 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8818 22:12:03.538808 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8819 22:12:03.541916 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8820 22:12:03.545603 ==
8821 22:12:03.548809 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 22:12:03.552033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 22:12:03.552159 ==
8824 22:12:03.552273 DQS Delay:
8825 22:12:03.555349 DQS0 = 0, DQS1 = 0
8826 22:12:03.555471 DQM Delay:
8827 22:12:03.558632 DQM0 = 136, DQM1 = 133
8828 22:12:03.558752 DQ Delay:
8829 22:12:03.562240 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8830 22:12:03.565348 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8831 22:12:03.568576 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8832 22:12:03.571824 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8833 22:12:03.571948
8834 22:12:03.572061
8835 22:12:03.572169 ==
8836 22:12:03.575075 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 22:12:03.582034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 22:12:03.582161 ==
8839 22:12:03.582275
8840 22:12:03.582385
8841 22:12:03.582497 TX Vref Scan disable
8842 22:12:03.585282 == TX Byte 0 ==
8843 22:12:03.588612 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8844 22:12:03.595281 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8845 22:12:03.595404 == TX Byte 1 ==
8846 22:12:03.598979 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8847 22:12:03.605679 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8848 22:12:03.605806 ==
8849 22:12:03.609006 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 22:12:03.611879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 22:12:03.612006 ==
8852 22:12:03.625384
8853 22:12:03.628768 TX Vref early break, caculate TX vref
8854 22:12:03.631969 TX Vref=16, minBit 0, minWin=23, winSum=382
8855 22:12:03.635294 TX Vref=18, minBit 0, minWin=24, winSum=395
8856 22:12:03.638909 TX Vref=20, minBit 0, minWin=23, winSum=399
8857 22:12:03.642145 TX Vref=22, minBit 0, minWin=23, winSum=406
8858 22:12:03.645280 TX Vref=24, minBit 0, minWin=25, winSum=417
8859 22:12:03.651985 TX Vref=26, minBit 0, minWin=25, winSum=426
8860 22:12:03.655389 TX Vref=28, minBit 0, minWin=24, winSum=426
8861 22:12:03.658593 TX Vref=30, minBit 6, minWin=25, winSum=420
8862 22:12:03.661907 TX Vref=32, minBit 1, minWin=25, winSum=416
8863 22:12:03.665478 TX Vref=34, minBit 0, minWin=24, winSum=407
8864 22:12:03.668570 TX Vref=36, minBit 6, minWin=23, winSum=394
8865 22:12:03.675201 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26
8866 22:12:03.675288
8867 22:12:03.678405 Final TX Range 0 Vref 26
8868 22:12:03.678488
8869 22:12:03.678552 ==
8870 22:12:03.681770 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 22:12:03.685539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 22:12:03.685639 ==
8873 22:12:03.685716
8874 22:12:03.688886
8875 22:12:03.688967 TX Vref Scan disable
8876 22:12:03.695223 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8877 22:12:03.695305 == TX Byte 0 ==
8878 22:12:03.698385 u2DelayCellOfst[0]=16 cells (5 PI)
8879 22:12:03.701760 u2DelayCellOfst[1]=13 cells (4 PI)
8880 22:12:03.705321 u2DelayCellOfst[2]=0 cells (0 PI)
8881 22:12:03.708611 u2DelayCellOfst[3]=6 cells (2 PI)
8882 22:12:03.711849 u2DelayCellOfst[4]=6 cells (2 PI)
8883 22:12:03.714849 u2DelayCellOfst[5]=16 cells (5 PI)
8884 22:12:03.718177 u2DelayCellOfst[6]=16 cells (5 PI)
8885 22:12:03.721726 u2DelayCellOfst[7]=6 cells (2 PI)
8886 22:12:03.725018 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8887 22:12:03.728273 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8888 22:12:03.731501 == TX Byte 1 ==
8889 22:12:03.734729 u2DelayCellOfst[8]=0 cells (0 PI)
8890 22:12:03.734810 u2DelayCellOfst[9]=3 cells (1 PI)
8891 22:12:03.738165 u2DelayCellOfst[10]=10 cells (3 PI)
8892 22:12:03.742003 u2DelayCellOfst[11]=6 cells (2 PI)
8893 22:12:03.744971 u2DelayCellOfst[12]=13 cells (4 PI)
8894 22:12:03.748458 u2DelayCellOfst[13]=13 cells (4 PI)
8895 22:12:03.751754 u2DelayCellOfst[14]=16 cells (5 PI)
8896 22:12:03.755180 u2DelayCellOfst[15]=16 cells (5 PI)
8897 22:12:03.758344 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8898 22:12:03.765048 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8899 22:12:03.765146 DramC Write-DBI on
8900 22:12:03.765224 ==
8901 22:12:03.768257 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 22:12:03.775214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 22:12:03.775297 ==
8904 22:12:03.775361
8905 22:12:03.775421
8906 22:12:03.775477 TX Vref Scan disable
8907 22:12:03.778892 == TX Byte 0 ==
8908 22:12:03.782152 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8909 22:12:03.785248 == TX Byte 1 ==
8910 22:12:03.788594 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8911 22:12:03.791808 DramC Write-DBI off
8912 22:12:03.791890
8913 22:12:03.791953 [DATLAT]
8914 22:12:03.792012 Freq=1600, CH1 RK1
8915 22:12:03.792070
8916 22:12:03.795521 DATLAT Default: 0xf
8917 22:12:03.795627 0, 0xFFFF, sum = 0
8918 22:12:03.798716 1, 0xFFFF, sum = 0
8919 22:12:03.801796 2, 0xFFFF, sum = 0
8920 22:12:03.801879 3, 0xFFFF, sum = 0
8921 22:12:03.805412 4, 0xFFFF, sum = 0
8922 22:12:03.805511 5, 0xFFFF, sum = 0
8923 22:12:03.808808 6, 0xFFFF, sum = 0
8924 22:12:03.808907 7, 0xFFFF, sum = 0
8925 22:12:03.812176 8, 0xFFFF, sum = 0
8926 22:12:03.812260 9, 0xFFFF, sum = 0
8927 22:12:03.815587 10, 0xFFFF, sum = 0
8928 22:12:03.815711 11, 0xFFFF, sum = 0
8929 22:12:03.818323 12, 0xFFFF, sum = 0
8930 22:12:03.818410 13, 0xFFFF, sum = 0
8931 22:12:03.821856 14, 0x0, sum = 1
8932 22:12:03.821987 15, 0x0, sum = 2
8933 22:12:03.824860 16, 0x0, sum = 3
8934 22:12:03.824959 17, 0x0, sum = 4
8935 22:12:03.828522 best_step = 15
8936 22:12:03.828606
8937 22:12:03.828672 ==
8938 22:12:03.831813 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 22:12:03.835120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 22:12:03.835220 ==
8941 22:12:03.835314 RX Vref Scan: 0
8942 22:12:03.838852
8943 22:12:03.838966 RX Vref 0 -> 0, step: 1
8944 22:12:03.839061
8945 22:12:03.842120 RX Delay 19 -> 252, step: 4
8946 22:12:03.845351 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8947 22:12:03.851740 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8948 22:12:03.855096 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8949 22:12:03.858277 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8950 22:12:03.861812 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8951 22:12:03.865339 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8952 22:12:03.868549 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8953 22:12:03.875217 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8954 22:12:03.878821 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8955 22:12:03.881813 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8956 22:12:03.884933 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8957 22:12:03.888240 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8958 22:12:03.895257 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8959 22:12:03.898616 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8960 22:12:03.901762 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8961 22:12:03.904924 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8962 22:12:03.905041 ==
8963 22:12:03.908550 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 22:12:03.915153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 22:12:03.915259 ==
8966 22:12:03.915351 DQS Delay:
8967 22:12:03.918106 DQS0 = 0, DQS1 = 0
8968 22:12:03.918228 DQM Delay:
8969 22:12:03.918318 DQM0 = 134, DQM1 = 130
8970 22:12:03.921527 DQ Delay:
8971 22:12:03.925293 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8972 22:12:03.928176 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8973 22:12:03.931932 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8974 22:12:03.934916 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
8975 22:12:03.935010
8976 22:12:03.935096
8977 22:12:03.935181
8978 22:12:03.938335 [DramC_TX_OE_Calibration] TA2
8979 22:12:03.941671 Original DQ_B0 (3 6) =30, OEN = 27
8980 22:12:03.944819 Original DQ_B1 (3 6) =30, OEN = 27
8981 22:12:03.948045 24, 0x0, End_B0=24 End_B1=24
8982 22:12:03.948128 25, 0x0, End_B0=25 End_B1=25
8983 22:12:03.951905 26, 0x0, End_B0=26 End_B1=26
8984 22:12:03.955111 27, 0x0, End_B0=27 End_B1=27
8985 22:12:03.958339 28, 0x0, End_B0=28 End_B1=28
8986 22:12:03.961508 29, 0x0, End_B0=29 End_B1=29
8987 22:12:03.961592 30, 0x0, End_B0=30 End_B1=30
8988 22:12:03.965214 31, 0x4141, End_B0=30 End_B1=30
8989 22:12:03.968379 Byte0 end_step=30 best_step=27
8990 22:12:03.971391 Byte1 end_step=30 best_step=27
8991 22:12:03.974894 Byte0 TX OE(2T, 0.5T) = (3, 3)
8992 22:12:03.978157 Byte1 TX OE(2T, 0.5T) = (3, 3)
8993 22:12:03.978240
8994 22:12:03.978335
8995 22:12:03.984876 [DQSOSCAuto] RK1, (LSB)MR18= 0x250a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
8996 22:12:03.988117 CH1 RK1: MR19=303, MR18=250A
8997 22:12:03.994809 CH1_RK1: MR19=0x303, MR18=0x250A, DQSOSC=391, MR23=63, INC=24, DEC=16
8998 22:12:03.998082 [RxdqsGatingPostProcess] freq 1600
8999 22:12:04.001330 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9000 22:12:04.004717 best DQS0 dly(2T, 0.5T) = (1, 1)
9001 22:12:04.008344 best DQS1 dly(2T, 0.5T) = (1, 1)
9002 22:12:04.011329 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9003 22:12:04.014536 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9004 22:12:04.017990 best DQS0 dly(2T, 0.5T) = (1, 1)
9005 22:12:04.021194 best DQS1 dly(2T, 0.5T) = (1, 1)
9006 22:12:04.024972 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9007 22:12:04.028001 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9008 22:12:04.031411 Pre-setting of DQS Precalculation
9009 22:12:04.034447 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9010 22:12:04.041081 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9011 22:12:04.047764 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9012 22:12:04.051067
9013 22:12:04.051149
9014 22:12:04.051212 [Calibration Summary] 3200 Mbps
9015 22:12:04.054341 CH 0, Rank 0
9016 22:12:04.054429 SW Impedance : PASS
9017 22:12:04.057655 DUTY Scan : NO K
9018 22:12:04.061450 ZQ Calibration : PASS
9019 22:12:04.061532 Jitter Meter : NO K
9020 22:12:04.064649 CBT Training : PASS
9021 22:12:04.067903 Write leveling : PASS
9022 22:12:04.067984 RX DQS gating : PASS
9023 22:12:04.071466 RX DQ/DQS(RDDQC) : PASS
9024 22:12:04.074872 TX DQ/DQS : PASS
9025 22:12:04.074956 RX DATLAT : PASS
9026 22:12:04.077887 RX DQ/DQS(Engine): PASS
9027 22:12:04.081108 TX OE : PASS
9028 22:12:04.081191 All Pass.
9029 22:12:04.081255
9030 22:12:04.081314 CH 0, Rank 1
9031 22:12:04.084622 SW Impedance : PASS
9032 22:12:04.088066 DUTY Scan : NO K
9033 22:12:04.088148 ZQ Calibration : PASS
9034 22:12:04.091487 Jitter Meter : NO K
9035 22:12:04.091584 CBT Training : PASS
9036 22:12:04.094743 Write leveling : PASS
9037 22:12:04.098119 RX DQS gating : PASS
9038 22:12:04.098202 RX DQ/DQS(RDDQC) : PASS
9039 22:12:04.101277 TX DQ/DQS : PASS
9040 22:12:04.104640 RX DATLAT : PASS
9041 22:12:04.104722 RX DQ/DQS(Engine): PASS
9042 22:12:04.107714 TX OE : PASS
9043 22:12:04.107797 All Pass.
9044 22:12:04.107875
9045 22:12:04.110952 CH 1, Rank 0
9046 22:12:04.111034 SW Impedance : PASS
9047 22:12:04.114628 DUTY Scan : NO K
9048 22:12:04.117739 ZQ Calibration : PASS
9049 22:12:04.117837 Jitter Meter : NO K
9050 22:12:04.121123 CBT Training : PASS
9051 22:12:04.124311 Write leveling : PASS
9052 22:12:04.124392 RX DQS gating : PASS
9053 22:12:04.127492 RX DQ/DQS(RDDQC) : PASS
9054 22:12:04.131325 TX DQ/DQS : PASS
9055 22:12:04.131407 RX DATLAT : PASS
9056 22:12:04.134451 RX DQ/DQS(Engine): PASS
9057 22:12:04.137653 TX OE : PASS
9058 22:12:04.137736 All Pass.
9059 22:12:04.137799
9060 22:12:04.137858 CH 1, Rank 1
9061 22:12:04.140874 SW Impedance : PASS
9062 22:12:04.144363 DUTY Scan : NO K
9063 22:12:04.144446 ZQ Calibration : PASS
9064 22:12:04.147706 Jitter Meter : NO K
9065 22:12:04.147788 CBT Training : PASS
9066 22:12:04.151315 Write leveling : PASS
9067 22:12:04.154509 RX DQS gating : PASS
9068 22:12:04.154591 RX DQ/DQS(RDDQC) : PASS
9069 22:12:04.157597 TX DQ/DQS : PASS
9070 22:12:04.161352 RX DATLAT : PASS
9071 22:12:04.161434 RX DQ/DQS(Engine): PASS
9072 22:12:04.164563 TX OE : PASS
9073 22:12:04.164645 All Pass.
9074 22:12:04.164709
9075 22:12:04.167763 DramC Write-DBI on
9076 22:12:04.170723 PER_BANK_REFRESH: Hybrid Mode
9077 22:12:04.170815 TX_TRACKING: ON
9078 22:12:04.180610 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9079 22:12:04.187447 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9080 22:12:04.194185 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9081 22:12:04.197856 [FAST_K] Save calibration result to emmc
9082 22:12:04.200784 sync common calibartion params.
9083 22:12:04.204187 sync cbt_mode0:1, 1:1
9084 22:12:04.207730 dram_init: ddr_geometry: 2
9085 22:12:04.207813 dram_init: ddr_geometry: 2
9086 22:12:04.211105 dram_init: ddr_geometry: 2
9087 22:12:04.214082 0:dram_rank_size:100000000
9088 22:12:04.217532 1:dram_rank_size:100000000
9089 22:12:04.220723 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9090 22:12:04.223901 DFS_SHUFFLE_HW_MODE: ON
9091 22:12:04.227572 dramc_set_vcore_voltage set vcore to 725000
9092 22:12:04.230827 Read voltage for 1600, 0
9093 22:12:04.230909 Vio18 = 0
9094 22:12:04.230973 Vcore = 725000
9095 22:12:04.234016 Vdram = 0
9096 22:12:04.234096 Vddq = 0
9097 22:12:04.234160 Vmddr = 0
9098 22:12:04.237171 switch to 3200 Mbps bootup
9099 22:12:04.240812 [DramcRunTimeConfig]
9100 22:12:04.240894 PHYPLL
9101 22:12:04.240957 DPM_CONTROL_AFTERK: ON
9102 22:12:04.244027 PER_BANK_REFRESH: ON
9103 22:12:04.247359 REFRESH_OVERHEAD_REDUCTION: ON
9104 22:12:04.247440 CMD_PICG_NEW_MODE: OFF
9105 22:12:04.250532 XRTWTW_NEW_MODE: ON
9106 22:12:04.253775 XRTRTR_NEW_MODE: ON
9107 22:12:04.253856 TX_TRACKING: ON
9108 22:12:04.257155 RDSEL_TRACKING: OFF
9109 22:12:04.257251 DQS Precalculation for DVFS: ON
9110 22:12:04.260501 RX_TRACKING: OFF
9111 22:12:04.260582 HW_GATING DBG: ON
9112 22:12:04.263746 ZQCS_ENABLE_LP4: ON
9113 22:12:04.263831 RX_PICG_NEW_MODE: ON
9114 22:12:04.267241 TX_PICG_NEW_MODE: ON
9115 22:12:04.270451 ENABLE_RX_DCM_DPHY: ON
9116 22:12:04.273813 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9117 22:12:04.273895 DUMMY_READ_FOR_TRACKING: OFF
9118 22:12:04.277169 !!! SPM_CONTROL_AFTERK: OFF
9119 22:12:04.280566 !!! SPM could not control APHY
9120 22:12:04.280647 IMPEDANCE_TRACKING: ON
9121 22:12:04.284146 TEMP_SENSOR: ON
9122 22:12:04.284228 HW_SAVE_FOR_SR: OFF
9123 22:12:04.287468 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9124 22:12:04.290648 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9125 22:12:04.293837 Read ODT Tracking: ON
9126 22:12:04.297203 Refresh Rate DeBounce: ON
9127 22:12:04.297285 DFS_NO_QUEUE_FLUSH: ON
9128 22:12:04.300895 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9129 22:12:04.304183 ENABLE_DFS_RUNTIME_MRW: OFF
9130 22:12:04.307096 DDR_RESERVE_NEW_MODE: ON
9131 22:12:04.307182 MR_CBT_SWITCH_FREQ: ON
9132 22:12:04.310560 =========================
9133 22:12:04.329804 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9134 22:12:04.333094 dram_init: ddr_geometry: 2
9135 22:12:04.351145 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9136 22:12:04.354732 dram_init: dram init end (result: 0)
9137 22:12:04.361632 DRAM-K: Full calibration passed in 24442 msecs
9138 22:12:04.364775 MRC: failed to locate region type 0.
9139 22:12:04.364858 DRAM rank0 size:0x100000000,
9140 22:12:04.368039 DRAM rank1 size=0x100000000
9141 22:12:04.378208 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9142 22:12:04.384855 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9143 22:12:04.391245 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9144 22:12:04.398015 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9145 22:12:04.401222 DRAM rank0 size:0x100000000,
9146 22:12:04.404892 DRAM rank1 size=0x100000000
9147 22:12:04.404974 CBMEM:
9148 22:12:04.407939 IMD: root @ 0xfffff000 254 entries.
9149 22:12:04.411105 IMD: root @ 0xffffec00 62 entries.
9150 22:12:04.414491 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9151 22:12:04.417769 WARNING: RO_VPD is uninitialized or empty.
9152 22:12:04.424586 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9153 22:12:04.431632 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9154 22:12:04.444078 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9155 22:12:04.455277 BS: romstage times (exec / console): total (unknown) / 23976 ms
9156 22:12:04.455381
9157 22:12:04.455482
9158 22:12:04.465306 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9159 22:12:04.468590 ARM64: Exception handlers installed.
9160 22:12:04.472203 ARM64: Testing exception
9161 22:12:04.475013 ARM64: Done test exception
9162 22:12:04.475095 Enumerating buses...
9163 22:12:04.478761 Show all devs... Before device enumeration.
9164 22:12:04.481920 Root Device: enabled 1
9165 22:12:04.485043 CPU_CLUSTER: 0: enabled 1
9166 22:12:04.485125 CPU: 00: enabled 1
9167 22:12:04.488375 Compare with tree...
9168 22:12:04.488459 Root Device: enabled 1
9169 22:12:04.491902 CPU_CLUSTER: 0: enabled 1
9170 22:12:04.495130 CPU: 00: enabled 1
9171 22:12:04.495212 Root Device scanning...
9172 22:12:04.498462 scan_static_bus for Root Device
9173 22:12:04.501994 CPU_CLUSTER: 0 enabled
9174 22:12:04.505188 scan_static_bus for Root Device done
9175 22:12:04.508836 scan_bus: bus Root Device finished in 8 msecs
9176 22:12:04.508918 done
9177 22:12:04.515421 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9178 22:12:04.518527 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9179 22:12:04.525513 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9180 22:12:04.528583 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9181 22:12:04.531825 Allocating resources...
9182 22:12:04.534952 Reading resources...
9183 22:12:04.538735 Root Device read_resources bus 0 link: 0
9184 22:12:04.538818 DRAM rank0 size:0x100000000,
9185 22:12:04.541835 DRAM rank1 size=0x100000000
9186 22:12:04.545173 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9187 22:12:04.548306 CPU: 00 missing read_resources
9188 22:12:04.552105 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9189 22:12:04.558494 Root Device read_resources bus 0 link: 0 done
9190 22:12:04.558576 Done reading resources.
9191 22:12:04.565108 Show resources in subtree (Root Device)...After reading.
9192 22:12:04.568466 Root Device child on link 0 CPU_CLUSTER: 0
9193 22:12:04.572128 CPU_CLUSTER: 0 child on link 0 CPU: 00
9194 22:12:04.581832 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9195 22:12:04.581915 CPU: 00
9196 22:12:04.585096 Root Device assign_resources, bus 0 link: 0
9197 22:12:04.588402 CPU_CLUSTER: 0 missing set_resources
9198 22:12:04.594807 Root Device assign_resources, bus 0 link: 0 done
9199 22:12:04.594889 Done setting resources.
9200 22:12:04.601438 Show resources in subtree (Root Device)...After assigning values.
9201 22:12:04.605139 Root Device child on link 0 CPU_CLUSTER: 0
9202 22:12:04.608198 CPU_CLUSTER: 0 child on link 0 CPU: 00
9203 22:12:04.618198 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9204 22:12:04.618281 CPU: 00
9205 22:12:04.621388 Done allocating resources.
9206 22:12:04.624917 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9207 22:12:04.628062 Enabling resources...
9208 22:12:04.628170 done.
9209 22:12:04.635063 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9210 22:12:04.635145 Initializing devices...
9211 22:12:04.638316 Root Device init
9212 22:12:04.638397 init hardware done!
9213 22:12:04.641364 0x00000018: ctrlr->caps
9214 22:12:04.644956 52.000 MHz: ctrlr->f_max
9215 22:12:04.645077 0.400 MHz: ctrlr->f_min
9216 22:12:04.648175 0x40ff8080: ctrlr->voltages
9217 22:12:04.648259 sclk: 390625
9218 22:12:04.651356 Bus Width = 1
9219 22:12:04.651438 sclk: 390625
9220 22:12:04.654457 Bus Width = 1
9221 22:12:04.654539 Early init status = 3
9222 22:12:04.661286 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9223 22:12:04.664774 in-header: 03 fc 00 00 01 00 00 00
9224 22:12:04.664889 in-data: 00
9225 22:12:04.671073 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9226 22:12:04.674785 in-header: 03 fd 00 00 00 00 00 00
9227 22:12:04.677951 in-data:
9228 22:12:04.681143 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9229 22:12:04.684920 in-header: 03 fc 00 00 01 00 00 00
9230 22:12:04.687632 in-data: 00
9231 22:12:04.690888 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9232 22:12:04.695589 in-header: 03 fd 00 00 00 00 00 00
9233 22:12:04.698953 in-data:
9234 22:12:04.702354 [SSUSB] Setting up USB HOST controller...
9235 22:12:04.705958 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9236 22:12:04.709074 [SSUSB] phy power-on done.
9237 22:12:04.712334 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9238 22:12:04.718663 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9239 22:12:04.722401 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9240 22:12:04.728750 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9241 22:12:04.735549 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9242 22:12:04.742227 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9243 22:12:04.748917 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9244 22:12:04.755363 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9245 22:12:04.758631 SPM: binary array size = 0x9dc
9246 22:12:04.762220 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9247 22:12:04.768528 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9248 22:12:04.775189 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9249 22:12:04.778371 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9250 22:12:04.785297 configure_display: Starting display init
9251 22:12:04.818733 anx7625_power_on_init: Init interface.
9252 22:12:04.822072 anx7625_disable_pd_protocol: Disabled PD feature.
9253 22:12:04.825271 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9254 22:12:04.853145 anx7625_start_dp_work: Secure OCM version=00
9255 22:12:04.856729 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9256 22:12:04.871422 sp_tx_get_edid_block: EDID Block = 1
9257 22:12:04.974103 Extracted contents:
9258 22:12:04.977351 header: 00 ff ff ff ff ff ff 00
9259 22:12:04.980781 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9260 22:12:04.984008 version: 01 04
9261 22:12:04.987140 basic params: 95 1f 11 78 0a
9262 22:12:04.990697 chroma info: 76 90 94 55 54 90 27 21 50 54
9263 22:12:04.993879 established: 00 00 00
9264 22:12:05.000815 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9265 22:12:05.003881 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9266 22:12:05.010639 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9267 22:12:05.017135 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9268 22:12:05.024014 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9269 22:12:05.027288 extensions: 00
9270 22:12:05.027413 checksum: fb
9271 22:12:05.027524
9272 22:12:05.030520 Manufacturer: IVO Model 57d Serial Number 0
9273 22:12:05.033772 Made week 0 of 2020
9274 22:12:05.033897 EDID version: 1.4
9275 22:12:05.037151 Digital display
9276 22:12:05.040298 6 bits per primary color channel
9277 22:12:05.040434 DisplayPort interface
9278 22:12:05.044136 Maximum image size: 31 cm x 17 cm
9279 22:12:05.047222 Gamma: 220%
9280 22:12:05.047345 Check DPMS levels
9281 22:12:05.050296 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9282 22:12:05.053659 First detailed timing is preferred timing
9283 22:12:05.056797 Established timings supported:
9284 22:12:05.060628 Standard timings supported:
9285 22:12:05.060751 Detailed timings
9286 22:12:05.066739 Hex of detail: 383680a07038204018303c0035ae10000019
9287 22:12:05.070436 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9288 22:12:05.077005 0780 0798 07c8 0820 hborder 0
9289 22:12:05.080022 0438 043b 0447 0458 vborder 0
9290 22:12:05.083656 -hsync -vsync
9291 22:12:05.083752 Did detailed timing
9292 22:12:05.086941 Hex of detail: 000000000000000000000000000000000000
9293 22:12:05.089933 Manufacturer-specified data, tag 0
9294 22:12:05.096675 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9295 22:12:05.096758 ASCII string: InfoVision
9296 22:12:05.103495 Hex of detail: 000000fe00523134304e574635205248200a
9297 22:12:05.106651 ASCII string: R140NWF5 RH
9298 22:12:05.106733 Checksum
9299 22:12:05.106797 Checksum: 0xfb (valid)
9300 22:12:05.113408 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9301 22:12:05.116756 DSI data_rate: 832800000 bps
9302 22:12:05.120423 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9303 22:12:05.126695 anx7625_parse_edid: pixelclock(138800).
9304 22:12:05.130137 hactive(1920), hsync(48), hfp(24), hbp(88)
9305 22:12:05.133455 vactive(1080), vsync(12), vfp(3), vbp(17)
9306 22:12:05.137211 anx7625_dsi_config: config dsi.
9307 22:12:05.143624 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9308 22:12:05.156296 anx7625_dsi_config: success to config DSI
9309 22:12:05.159076 anx7625_dp_start: MIPI phy setup OK.
9310 22:12:05.162895 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9311 22:12:05.166190 mtk_ddp_mode_set invalid vrefresh 60
9312 22:12:05.169558 main_disp_path_setup
9313 22:12:05.169639 ovl_layer_smi_id_en
9314 22:12:05.172961 ovl_layer_smi_id_en
9315 22:12:05.173043 ccorr_config
9316 22:12:05.173105 aal_config
9317 22:12:05.176145 gamma_config
9318 22:12:05.176226 postmask_config
9319 22:12:05.179426 dither_config
9320 22:12:05.182524 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9321 22:12:05.189340 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9322 22:12:05.192495 Root Device init finished in 551 msecs
9323 22:12:05.192576 CPU_CLUSTER: 0 init
9324 22:12:05.202655 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9325 22:12:05.206254 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9326 22:12:05.209478 APU_MBOX 0x190000b0 = 0x10001
9327 22:12:05.212998 APU_MBOX 0x190001b0 = 0x10001
9328 22:12:05.216148 APU_MBOX 0x190005b0 = 0x10001
9329 22:12:05.219145 APU_MBOX 0x190006b0 = 0x10001
9330 22:12:05.222551 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9331 22:12:05.234890 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9332 22:12:05.247487 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9333 22:12:05.253903 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9334 22:12:05.265807 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9335 22:12:05.275159 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9336 22:12:05.278193 CPU_CLUSTER: 0 init finished in 81 msecs
9337 22:12:05.281466 Devices initialized
9338 22:12:05.285041 Show all devs... After init.
9339 22:12:05.285122 Root Device: enabled 1
9340 22:12:05.288286 CPU_CLUSTER: 0: enabled 1
9341 22:12:05.291218 CPU: 00: enabled 1
9342 22:12:05.294856 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9343 22:12:05.298183 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9344 22:12:05.301177 ELOG: NV offset 0x57f000 size 0x1000
9345 22:12:05.308220 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9346 22:12:05.314489 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9347 22:12:05.318038 ELOG: Event(17) added with size 13 at 2023-09-05 22:10:58 UTC
9348 22:12:05.321310 out: cmd=0x121: 03 db 21 01 00 00 00 00
9349 22:12:05.324923 in-header: 03 ed 00 00 2c 00 00 00
9350 22:12:05.338657 in-data: 72 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9351 22:12:05.344953 ELOG: Event(A1) added with size 10 at 2023-09-05 22:10:58 UTC
9352 22:12:05.351917 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9353 22:12:05.358012 ELOG: Event(A0) added with size 9 at 2023-09-05 22:10:58 UTC
9354 22:12:05.361602 elog_add_boot_reason: Logged dev mode boot
9355 22:12:05.364734 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9356 22:12:05.368078 Finalize devices...
9357 22:12:05.368162 Devices finalized
9358 22:12:05.374726 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9359 22:12:05.378033 Writing coreboot table at 0xffe64000
9360 22:12:05.381187 0. 000000000010a000-0000000000113fff: RAMSTAGE
9361 22:12:05.384523 1. 0000000040000000-00000000400fffff: RAM
9362 22:12:05.388075 2. 0000000040100000-000000004032afff: RAMSTAGE
9363 22:12:05.394642 3. 000000004032b000-00000000545fffff: RAM
9364 22:12:05.398079 4. 0000000054600000-000000005465ffff: BL31
9365 22:12:05.401361 5. 0000000054660000-00000000ffe63fff: RAM
9366 22:12:05.407763 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9367 22:12:05.411461 7. 0000000100000000-000000023fffffff: RAM
9368 22:12:05.411554 Passing 5 GPIOs to payload:
9369 22:12:05.417644 NAME | PORT | POLARITY | VALUE
9370 22:12:05.421489 EC in RW | 0x000000aa | low | undefined
9371 22:12:05.427862 EC interrupt | 0x00000005 | low | undefined
9372 22:12:05.430808 TPM interrupt | 0x000000ab | high | undefined
9373 22:12:05.438140 SD card detect | 0x00000011 | high | undefined
9374 22:12:05.441269 speaker enable | 0x00000093 | high | undefined
9375 22:12:05.444462 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9376 22:12:05.447561 in-header: 03 f9 00 00 02 00 00 00
9377 22:12:05.451191 in-data: 02 00
9378 22:12:05.451272 ADC[4]: Raw value=904726 ID=7
9379 22:12:05.454517 ADC[3]: Raw value=213441 ID=1
9380 22:12:05.457840 RAM Code: 0x71
9381 22:12:05.457922 ADC[6]: Raw value=75701 ID=0
9382 22:12:05.460980 ADC[5]: Raw value=213072 ID=1
9383 22:12:05.464268 SKU Code: 0x1
9384 22:12:05.467803 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b7d7
9385 22:12:05.471147 coreboot table: 964 bytes.
9386 22:12:05.474466 IMD ROOT 0. 0xfffff000 0x00001000
9387 22:12:05.477793 IMD SMALL 1. 0xffffe000 0x00001000
9388 22:12:05.481444 RO MCACHE 2. 0xffffc000 0x00001104
9389 22:12:05.484605 CONSOLE 3. 0xfff7c000 0x00080000
9390 22:12:05.487834 FMAP 4. 0xfff7b000 0x00000452
9391 22:12:05.491109 TIME STAMP 5. 0xfff7a000 0x00000910
9392 22:12:05.494529 VBOOT WORK 6. 0xfff66000 0x00014000
9393 22:12:05.497792 RAMOOPS 7. 0xffe66000 0x00100000
9394 22:12:05.500793 COREBOOT 8. 0xffe64000 0x00002000
9395 22:12:05.500875 IMD small region:
9396 22:12:05.504056 IMD ROOT 0. 0xffffec00 0x00000400
9397 22:12:05.507527 VPD 1. 0xffffeb80 0x0000006c
9398 22:12:05.510775 MMC STATUS 2. 0xffffeb60 0x00000004
9399 22:12:05.517686 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9400 22:12:05.520823 Probing TPM: done!
9401 22:12:05.523945 Connected to device vid:did:rid of 1ae0:0028:00
9402 22:12:05.534186 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9403 22:12:05.537678 Initialized TPM device CR50 revision 0
9404 22:12:05.541740 Checking cr50 for pending updates
9405 22:12:05.544659 Reading cr50 TPM mode
9406 22:12:05.553577 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9407 22:12:05.559896 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9408 22:12:05.600025 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9409 22:12:05.603736 Checking segment from ROM address 0x40100000
9410 22:12:05.606843 Checking segment from ROM address 0x4010001c
9411 22:12:05.613426 Loading segment from ROM address 0x40100000
9412 22:12:05.613568 code (compression=0)
9413 22:12:05.619995 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9414 22:12:05.630343 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9415 22:12:05.630427 it's not compressed!
9416 22:12:05.636772 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9417 22:12:05.640412 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9418 22:12:05.660904 Loading segment from ROM address 0x4010001c
9419 22:12:05.660988 Entry Point 0x80000000
9420 22:12:05.664079 Loaded segments
9421 22:12:05.667372 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9422 22:12:05.673873 Jumping to boot code at 0x80000000(0xffe64000)
9423 22:12:05.680787 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9424 22:12:05.687094 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9425 22:12:05.695018 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9426 22:12:05.698297 Checking segment from ROM address 0x40100000
9427 22:12:05.701440 Checking segment from ROM address 0x4010001c
9428 22:12:05.708298 Loading segment from ROM address 0x40100000
9429 22:12:05.708380 code (compression=1)
9430 22:12:05.715170 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9431 22:12:05.724713 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9432 22:12:05.724797 using LZMA
9433 22:12:05.733078 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9434 22:12:05.740028 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9435 22:12:05.743061 Loading segment from ROM address 0x4010001c
9436 22:12:05.743171 Entry Point 0x54601000
9437 22:12:05.746268 Loaded segments
9438 22:12:05.749604 NOTICE: MT8192 bl31_setup
9439 22:12:05.757004 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9440 22:12:05.760254 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9441 22:12:05.763362 WARNING: region 0:
9442 22:12:05.766869 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9443 22:12:05.766952 WARNING: region 1:
9444 22:12:05.773401 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9445 22:12:05.777169 WARNING: region 2:
9446 22:12:05.780402 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9447 22:12:05.783602 WARNING: region 3:
9448 22:12:05.786783 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9449 22:12:05.790110 WARNING: region 4:
9450 22:12:05.796914 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9451 22:12:05.796997 WARNING: region 5:
9452 22:12:05.800006 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 22:12:05.803585 WARNING: region 6:
9454 22:12:05.806896 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 22:12:05.810102 WARNING: region 7:
9456 22:12:05.813679 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 22:12:05.819980 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9458 22:12:05.823469 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9459 22:12:05.826731 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9460 22:12:05.833648 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9461 22:12:05.837142 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9462 22:12:05.840397 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9463 22:12:05.846751 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9464 22:12:05.850502 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9465 22:12:05.853650 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9466 22:12:05.860501 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9467 22:12:05.863880 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9468 22:12:05.870289 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9469 22:12:05.873933 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9470 22:12:05.877148 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9471 22:12:05.883759 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9472 22:12:05.886905 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9473 22:12:05.890158 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9474 22:12:05.896992 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9475 22:12:05.900567 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9476 22:12:05.903804 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9477 22:12:05.910434 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9478 22:12:05.914148 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9479 22:12:05.920651 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9480 22:12:05.923822 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9481 22:12:05.927017 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9482 22:12:05.934199 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9483 22:12:05.937013 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9484 22:12:05.943936 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9485 22:12:05.947405 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9486 22:12:05.950448 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9487 22:12:05.957324 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9488 22:12:05.960719 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9489 22:12:05.963816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9490 22:12:05.970907 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9491 22:12:05.974172 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9492 22:12:05.977238 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9493 22:12:05.980567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9494 22:12:05.987566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9495 22:12:05.990627 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9496 22:12:05.994317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9497 22:12:05.997509 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9498 22:12:06.000735 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9499 22:12:06.007534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9500 22:12:06.011523 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9501 22:12:06.014336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9502 22:12:06.018005 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9503 22:12:06.024319 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9504 22:12:06.027768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9505 22:12:06.031023 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9506 22:12:06.037717 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9507 22:12:06.041238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9508 22:12:06.047837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9509 22:12:06.051212 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9510 22:12:06.057829 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9511 22:12:06.061371 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9512 22:12:06.064783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9513 22:12:06.070912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9514 22:12:06.074751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9515 22:12:06.081394 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9516 22:12:06.084415 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9517 22:12:06.091023 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9518 22:12:06.094610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9519 22:12:06.098101 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9520 22:12:06.104542 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9521 22:12:06.108221 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9522 22:12:06.114426 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9523 22:12:06.118180 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9524 22:12:06.124680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9525 22:12:06.127807 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9526 22:12:06.131163 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9527 22:12:06.138184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9528 22:12:06.141533 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9529 22:12:06.148023 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9530 22:12:06.151406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9531 22:12:06.158051 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9532 22:12:06.161103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9533 22:12:06.164641 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9534 22:12:06.171166 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9535 22:12:06.174562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9536 22:12:06.181362 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9537 22:12:06.184242 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9538 22:12:06.191356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9539 22:12:06.194509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9540 22:12:06.198111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9541 22:12:06.204724 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9542 22:12:06.208058 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9543 22:12:06.214386 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9544 22:12:06.217698 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9545 22:12:06.224185 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9546 22:12:06.227762 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9547 22:12:06.230990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9548 22:12:06.237848 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9549 22:12:06.241173 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9550 22:12:06.247570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9551 22:12:06.250865 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9552 22:12:06.257858 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9553 22:12:06.261220 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9554 22:12:06.264457 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9555 22:12:06.267965 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9556 22:12:06.274405 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9557 22:12:06.277650 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9558 22:12:06.281011 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9559 22:12:06.287529 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9560 22:12:06.291151 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9561 22:12:06.297516 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9562 22:12:06.300859 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9563 22:12:06.304498 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9564 22:12:06.310873 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9565 22:12:06.314189 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9566 22:12:06.320874 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9567 22:12:06.324262 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9568 22:12:06.327507 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9569 22:12:06.334114 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9570 22:12:06.337442 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9571 22:12:06.344426 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9572 22:12:06.347403 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9573 22:12:06.351123 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9574 22:12:06.354330 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9575 22:12:06.360994 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9576 22:12:06.364617 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9577 22:12:06.367792 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9578 22:12:06.371144 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9579 22:12:06.377525 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9580 22:12:06.380860 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9581 22:12:06.384372 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9582 22:12:06.391178 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9583 22:12:06.394337 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9584 22:12:06.401050 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9585 22:12:06.404188 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9586 22:12:06.408063 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9587 22:12:06.414464 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9588 22:12:06.417988 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9589 22:12:06.421115 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9590 22:12:06.427513 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9591 22:12:06.431405 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9592 22:12:06.437682 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9593 22:12:06.440951 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9594 22:12:06.444406 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9595 22:12:06.450839 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9596 22:12:06.454513 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9597 22:12:06.461083 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9598 22:12:06.464130 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9599 22:12:06.467947 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9600 22:12:06.474600 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9601 22:12:06.477664 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9602 22:12:06.480904 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9603 22:12:06.487904 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9604 22:12:06.490866 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9605 22:12:06.497933 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9606 22:12:06.501134 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9607 22:12:06.504590 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9608 22:12:06.511305 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9609 22:12:06.514393 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9610 22:12:06.518242 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9611 22:12:06.524471 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9612 22:12:06.528206 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9613 22:12:06.534653 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9614 22:12:06.537759 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9615 22:12:06.541460 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9616 22:12:06.547845 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9617 22:12:06.551033 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9618 22:12:06.557893 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9619 22:12:06.561057 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9620 22:12:06.564633 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9621 22:12:06.571364 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9622 22:12:06.574247 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9623 22:12:06.581138 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9624 22:12:06.584034 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9625 22:12:06.587546 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9626 22:12:06.594237 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9627 22:12:06.597711 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9628 22:12:06.604249 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9629 22:12:06.607393 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9630 22:12:06.610956 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9631 22:12:06.617455 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9632 22:12:06.621187 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9633 22:12:06.624600 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9634 22:12:06.631065 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9635 22:12:06.634570 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9636 22:12:06.641008 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9637 22:12:06.644329 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9638 22:12:06.647837 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9639 22:12:06.654257 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9640 22:12:06.657505 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9641 22:12:06.664076 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9642 22:12:06.668068 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9643 22:12:06.671188 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9644 22:12:06.677443 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9645 22:12:06.681017 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9646 22:12:06.687348 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9647 22:12:06.691030 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9648 22:12:06.694253 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9649 22:12:06.701490 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9650 22:12:06.703946 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9651 22:12:06.710727 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9652 22:12:06.713985 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9653 22:12:06.717319 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9654 22:12:06.723859 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9655 22:12:06.727485 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9656 22:12:06.734043 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9657 22:12:06.737561 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9658 22:12:06.741011 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9659 22:12:06.747603 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9660 22:12:06.750766 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9661 22:12:06.757505 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9662 22:12:06.760891 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9663 22:12:06.767115 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9664 22:12:06.770901 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9665 22:12:06.774040 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9666 22:12:06.780670 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9667 22:12:06.783993 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9668 22:12:06.790671 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9669 22:12:06.793995 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9670 22:12:06.800537 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9671 22:12:06.803573 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9672 22:12:06.807339 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9673 22:12:06.814082 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9674 22:12:06.817120 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9675 22:12:06.823804 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9676 22:12:06.827089 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9677 22:12:06.830286 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9678 22:12:06.836899 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9679 22:12:06.840138 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9680 22:12:06.846851 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9681 22:12:06.850585 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9682 22:12:06.853830 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9683 22:12:06.860204 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9684 22:12:06.863375 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9685 22:12:06.870356 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9686 22:12:06.873643 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9687 22:12:06.876942 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9688 22:12:06.880286 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9689 22:12:06.886748 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9690 22:12:06.889927 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9691 22:12:06.893294 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9692 22:12:06.900052 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9693 22:12:06.903298 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9694 22:12:06.906842 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9695 22:12:06.913426 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9696 22:12:06.916732 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9697 22:12:06.919877 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9698 22:12:06.926751 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9699 22:12:06.929987 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9700 22:12:06.933407 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9701 22:12:06.940157 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9702 22:12:06.943193 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9703 22:12:06.950147 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9704 22:12:06.953416 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9705 22:12:06.956512 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9706 22:12:06.963299 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9707 22:12:06.966598 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9708 22:12:06.970194 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9709 22:12:06.976548 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9710 22:12:06.979779 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9711 22:12:06.986147 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9712 22:12:06.989539 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9713 22:12:06.993312 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9714 22:12:06.999831 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9715 22:12:07.003228 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9716 22:12:07.006536 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9717 22:12:07.013170 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9718 22:12:07.016192 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9719 22:12:07.022796 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9720 22:12:07.026076 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9721 22:12:07.029678 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9722 22:12:07.036281 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9723 22:12:07.039464 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9724 22:12:07.042938 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9725 22:12:07.049457 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9726 22:12:07.052985 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9727 22:12:07.056208 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9728 22:12:07.059265 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9729 22:12:07.062883 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9730 22:12:07.069723 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9731 22:12:07.072962 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9732 22:12:07.075991 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9733 22:12:07.079303 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9734 22:12:07.085968 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9735 22:12:07.089665 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9736 22:12:07.092635 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9737 22:12:07.099448 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9738 22:12:07.102886 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9739 22:12:07.105970 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9740 22:12:07.112472 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9741 22:12:07.116091 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9742 22:12:07.119079 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9743 22:12:07.125942 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9744 22:12:07.129063 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9745 22:12:07.136133 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9746 22:12:07.139309 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9747 22:12:07.142735 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9748 22:12:07.148998 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9749 22:12:07.152621 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9750 22:12:07.158941 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9751 22:12:07.162206 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9752 22:12:07.169274 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9753 22:12:07.172512 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9754 22:12:07.175862 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9755 22:12:07.182258 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9756 22:12:07.185936 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9757 22:12:07.192324 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9758 22:12:07.196171 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9759 22:12:07.198884 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9760 22:12:07.205641 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9761 22:12:07.208909 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9762 22:12:07.215514 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9763 22:12:07.218853 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9764 22:12:07.222373 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9765 22:12:07.228958 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9766 22:12:07.232348 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9767 22:12:07.239002 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9768 22:12:07.242261 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9769 22:12:07.245954 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9770 22:12:07.252125 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9771 22:12:07.256043 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9772 22:12:07.262393 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9773 22:12:07.265553 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9774 22:12:07.268820 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9775 22:12:07.275866 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9776 22:12:07.279150 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9777 22:12:07.285630 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9778 22:12:07.289202 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9779 22:12:07.292297 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9780 22:12:07.298855 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9781 22:12:07.302081 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9782 22:12:07.308681 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9783 22:12:07.312398 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9784 22:12:07.319079 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9785 22:12:07.321923 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9786 22:12:07.325483 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9787 22:12:07.331904 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9788 22:12:07.335261 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9789 22:12:07.342007 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9790 22:12:07.345090 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9791 22:12:07.348524 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9792 22:12:07.355448 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9793 22:12:07.358681 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9794 22:12:07.365486 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9795 22:12:07.368673 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9796 22:12:07.371875 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9797 22:12:07.378446 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9798 22:12:07.382134 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9799 22:12:07.388678 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9800 22:12:07.391847 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9801 22:12:07.398682 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9802 22:12:07.401966 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9803 22:12:07.405256 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9804 22:12:07.411729 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9805 22:12:07.415039 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9806 22:12:07.421422 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9807 22:12:07.424762 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9808 22:12:07.427927 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9809 22:12:07.434994 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9810 22:12:07.438084 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9811 22:12:07.444784 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9812 22:12:07.448002 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9813 22:12:07.451202 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9814 22:12:07.458039 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9815 22:12:07.461137 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9816 22:12:07.467813 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9817 22:12:07.470901 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9818 22:12:07.477517 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9819 22:12:07.481174 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9820 22:12:07.487603 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9821 22:12:07.490868 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9822 22:12:07.494170 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9823 22:12:07.500591 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9824 22:12:07.503942 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9825 22:12:07.511094 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9826 22:12:07.514211 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9827 22:12:07.520853 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9828 22:12:07.524008 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9829 22:12:07.527773 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9830 22:12:07.534278 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9831 22:12:07.537344 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9832 22:12:07.544406 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9833 22:12:07.547025 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9834 22:12:07.553665 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9835 22:12:07.556827 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9836 22:12:07.563748 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9837 22:12:07.567184 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9838 22:12:07.573354 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9839 22:12:07.576959 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9840 22:12:07.580278 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9841 22:12:07.586703 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9842 22:12:07.589970 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9843 22:12:07.596761 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9844 22:12:07.600047 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9845 22:12:07.606860 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9846 22:12:07.610079 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9847 22:12:07.613370 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9848 22:12:07.619687 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9849 22:12:07.623030 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9850 22:12:07.630099 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9851 22:12:07.633313 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9852 22:12:07.640120 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9853 22:12:07.643267 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9854 22:12:07.649898 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9855 22:12:07.653051 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9856 22:12:07.656354 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9857 22:12:07.662874 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9858 22:12:07.666174 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9859 22:12:07.669863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9860 22:12:07.676478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9861 22:12:07.679764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9862 22:12:07.686557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9863 22:12:07.689944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9864 22:12:07.696463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9865 22:12:07.699884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9866 22:12:07.706308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9867 22:12:07.709787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9868 22:12:07.716308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9869 22:12:07.719350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9870 22:12:07.726172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9871 22:12:07.729491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9872 22:12:07.736176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9873 22:12:07.739359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9874 22:12:07.746228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9875 22:12:07.749422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9876 22:12:07.756140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9877 22:12:07.759270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9878 22:12:07.762804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9879 22:12:07.769548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9880 22:12:07.772641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9881 22:12:07.779568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9882 22:12:07.782832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9883 22:12:07.789654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9884 22:12:07.796191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9885 22:12:07.799255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9886 22:12:07.806377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9887 22:12:07.809532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9888 22:12:07.816071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9889 22:12:07.819300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9890 22:12:07.826260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9891 22:12:07.829298 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9892 22:12:07.829420 INFO: [APUAPC] vio 0
9893 22:12:07.836817 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9894 22:12:07.839808 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9895 22:12:07.843454 INFO: [APUAPC] D0_APC_0: 0x400510
9896 22:12:07.846527 INFO: [APUAPC] D0_APC_1: 0x0
9897 22:12:07.850089 INFO: [APUAPC] D0_APC_2: 0x1540
9898 22:12:07.853525 INFO: [APUAPC] D0_APC_3: 0x0
9899 22:12:07.856586 INFO: [APUAPC] D1_APC_0: 0xffffffff
9900 22:12:07.859794 INFO: [APUAPC] D1_APC_1: 0xffffffff
9901 22:12:07.863175 INFO: [APUAPC] D1_APC_2: 0x3fffff
9902 22:12:07.866519 INFO: [APUAPC] D1_APC_3: 0x0
9903 22:12:07.869928 INFO: [APUAPC] D2_APC_0: 0xffffffff
9904 22:12:07.872978 INFO: [APUAPC] D2_APC_1: 0xffffffff
9905 22:12:07.876618 INFO: [APUAPC] D2_APC_2: 0x3fffff
9906 22:12:07.879761 INFO: [APUAPC] D2_APC_3: 0x0
9907 22:12:07.883134 INFO: [APUAPC] D3_APC_0: 0xffffffff
9908 22:12:07.886413 INFO: [APUAPC] D3_APC_1: 0xffffffff
9909 22:12:07.889608 INFO: [APUAPC] D3_APC_2: 0x3fffff
9910 22:12:07.892919 INFO: [APUAPC] D3_APC_3: 0x0
9911 22:12:07.896378 INFO: [APUAPC] D4_APC_0: 0xffffffff
9912 22:12:07.899700 INFO: [APUAPC] D4_APC_1: 0xffffffff
9913 22:12:07.902898 INFO: [APUAPC] D4_APC_2: 0x3fffff
9914 22:12:07.903010 INFO: [APUAPC] D4_APC_3: 0x0
9915 22:12:07.906262 INFO: [APUAPC] D5_APC_0: 0xffffffff
9916 22:12:07.912910 INFO: [APUAPC] D5_APC_1: 0xffffffff
9917 22:12:07.916131 INFO: [APUAPC] D5_APC_2: 0x3fffff
9918 22:12:07.916214 INFO: [APUAPC] D5_APC_3: 0x0
9919 22:12:07.919787 INFO: [APUAPC] D6_APC_0: 0xffffffff
9920 22:12:07.923025 INFO: [APUAPC] D6_APC_1: 0xffffffff
9921 22:12:07.926193 INFO: [APUAPC] D6_APC_2: 0x3fffff
9922 22:12:07.929839 INFO: [APUAPC] D6_APC_3: 0x0
9923 22:12:07.932684 INFO: [APUAPC] D7_APC_0: 0xffffffff
9924 22:12:07.936406 INFO: [APUAPC] D7_APC_1: 0xffffffff
9925 22:12:07.939518 INFO: [APUAPC] D7_APC_2: 0x3fffff
9926 22:12:07.943086 INFO: [APUAPC] D7_APC_3: 0x0
9927 22:12:07.946405 INFO: [APUAPC] D8_APC_0: 0xffffffff
9928 22:12:07.949564 INFO: [APUAPC] D8_APC_1: 0xffffffff
9929 22:12:07.952855 INFO: [APUAPC] D8_APC_2: 0x3fffff
9930 22:12:07.956213 INFO: [APUAPC] D8_APC_3: 0x0
9931 22:12:07.959725 INFO: [APUAPC] D9_APC_0: 0xffffffff
9932 22:12:07.963131 INFO: [APUAPC] D9_APC_1: 0xffffffff
9933 22:12:07.966160 INFO: [APUAPC] D9_APC_2: 0x3fffff
9934 22:12:07.969641 INFO: [APUAPC] D9_APC_3: 0x0
9935 22:12:07.973224 INFO: [APUAPC] D10_APC_0: 0xffffffff
9936 22:12:07.976205 INFO: [APUAPC] D10_APC_1: 0xffffffff
9937 22:12:07.979801 INFO: [APUAPC] D10_APC_2: 0x3fffff
9938 22:12:07.983043 INFO: [APUAPC] D10_APC_3: 0x0
9939 22:12:07.986511 INFO: [APUAPC] D11_APC_0: 0xffffffff
9940 22:12:07.989702 INFO: [APUAPC] D11_APC_1: 0xffffffff
9941 22:12:07.992817 INFO: [APUAPC] D11_APC_2: 0x3fffff
9942 22:12:07.996579 INFO: [APUAPC] D11_APC_3: 0x0
9943 22:12:07.999540 INFO: [APUAPC] D12_APC_0: 0xffffffff
9944 22:12:08.002869 INFO: [APUAPC] D12_APC_1: 0xffffffff
9945 22:12:08.006229 INFO: [APUAPC] D12_APC_2: 0x3fffff
9946 22:12:08.009457 INFO: [APUAPC] D12_APC_3: 0x0
9947 22:12:08.012796 INFO: [APUAPC] D13_APC_0: 0xffffffff
9948 22:12:08.016144 INFO: [APUAPC] D13_APC_1: 0xffffffff
9949 22:12:08.019771 INFO: [APUAPC] D13_APC_2: 0x3fffff
9950 22:12:08.022917 INFO: [APUAPC] D13_APC_3: 0x0
9951 22:12:08.026328 INFO: [APUAPC] D14_APC_0: 0xffffffff
9952 22:12:08.029679 INFO: [APUAPC] D14_APC_1: 0xffffffff
9953 22:12:08.032841 INFO: [APUAPC] D14_APC_2: 0x3fffff
9954 22:12:08.036061 INFO: [APUAPC] D14_APC_3: 0x0
9955 22:12:08.039173 INFO: [APUAPC] D15_APC_0: 0xffffffff
9956 22:12:08.042890 INFO: [APUAPC] D15_APC_1: 0xffffffff
9957 22:12:08.045973 INFO: [APUAPC] D15_APC_2: 0x3fffff
9958 22:12:08.049313 INFO: [APUAPC] D15_APC_3: 0x0
9959 22:12:08.052582 INFO: [APUAPC] APC_CON: 0x4
9960 22:12:08.056222 INFO: [NOCDAPC] D0_APC_0: 0x0
9961 22:12:08.059425 INFO: [NOCDAPC] D0_APC_1: 0x0
9962 22:12:08.062479 INFO: [NOCDAPC] D1_APC_0: 0x0
9963 22:12:08.062604 INFO: [NOCDAPC] D1_APC_1: 0xfff
9964 22:12:08.065782 INFO: [NOCDAPC] D2_APC_0: 0x0
9965 22:12:08.069129 INFO: [NOCDAPC] D2_APC_1: 0xfff
9966 22:12:08.072391 INFO: [NOCDAPC] D3_APC_0: 0x0
9967 22:12:08.076065 INFO: [NOCDAPC] D3_APC_1: 0xfff
9968 22:12:08.079221 INFO: [NOCDAPC] D4_APC_0: 0x0
9969 22:12:08.082502 INFO: [NOCDAPC] D4_APC_1: 0xfff
9970 22:12:08.085611 INFO: [NOCDAPC] D5_APC_0: 0x0
9971 22:12:08.089251 INFO: [NOCDAPC] D5_APC_1: 0xfff
9972 22:12:08.092503 INFO: [NOCDAPC] D6_APC_0: 0x0
9973 22:12:08.095783 INFO: [NOCDAPC] D6_APC_1: 0xfff
9974 22:12:08.095905 INFO: [NOCDAPC] D7_APC_0: 0x0
9975 22:12:08.099090 INFO: [NOCDAPC] D7_APC_1: 0xfff
9976 22:12:08.102417 INFO: [NOCDAPC] D8_APC_0: 0x0
9977 22:12:08.105685 INFO: [NOCDAPC] D8_APC_1: 0xfff
9978 22:12:08.109048 INFO: [NOCDAPC] D9_APC_0: 0x0
9979 22:12:08.112665 INFO: [NOCDAPC] D9_APC_1: 0xfff
9980 22:12:08.115575 INFO: [NOCDAPC] D10_APC_0: 0x0
9981 22:12:08.118805 INFO: [NOCDAPC] D10_APC_1: 0xfff
9982 22:12:08.122601 INFO: [NOCDAPC] D11_APC_0: 0x0
9983 22:12:08.125742 INFO: [NOCDAPC] D11_APC_1: 0xfff
9984 22:12:08.128881 INFO: [NOCDAPC] D12_APC_0: 0x0
9985 22:12:08.132033 INFO: [NOCDAPC] D12_APC_1: 0xfff
9986 22:12:08.135490 INFO: [NOCDAPC] D13_APC_0: 0x0
9987 22:12:08.139257 INFO: [NOCDAPC] D13_APC_1: 0xfff
9988 22:12:08.139380 INFO: [NOCDAPC] D14_APC_0: 0x0
9989 22:12:08.142393 INFO: [NOCDAPC] D14_APC_1: 0xfff
9990 22:12:08.145761 INFO: [NOCDAPC] D15_APC_0: 0x0
9991 22:12:08.148804 INFO: [NOCDAPC] D15_APC_1: 0xfff
9992 22:12:08.152578 INFO: [NOCDAPC] APC_CON: 0x4
9993 22:12:08.155904 INFO: [APUAPC] set_apusys_apc done
9994 22:12:08.159053 INFO: [DEVAPC] devapc_init done
9995 22:12:08.162188 INFO: GICv3 without legacy support detected.
9996 22:12:08.168981 INFO: ARM GICv3 driver initialized in EL3
9997 22:12:08.172246 INFO: Maximum SPI INTID supported: 639
9998 22:12:08.175733 INFO: BL31: Initializing runtime services
9999 22:12:08.181945 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10000 22:12:08.182068 INFO: SPM: enable CPC mode
10001 22:12:08.188717 INFO: mcdi ready for mcusys-off-idle and system suspend
10002 22:12:08.191911 INFO: BL31: Preparing for EL3 exit to normal world
10003 22:12:08.195692 INFO: Entry point address = 0x80000000
10004 22:12:08.198764 INFO: SPSR = 0x8
10005 22:12:08.204506
10006 22:12:08.204630
10007 22:12:08.204739
10008 22:12:08.207826 Starting depthcharge on Spherion...
10009 22:12:08.207949
10010 22:12:08.208061 Wipe memory regions:
10011 22:12:08.208168
10012 22:12:08.209024 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10013 22:12:08.209184 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10014 22:12:08.209322 Setting prompt string to ['asurada:']
10015 22:12:08.209459 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10016 22:12:08.211002 [0x00000040000000, 0x00000054600000)
10017 22:12:08.333478
10018 22:12:08.333645 [0x00000054660000, 0x00000080000000)
10019 22:12:08.593793
10020 22:12:08.597155 [0x000000821a7280, 0x000000ffe64000)
10021 22:12:09.338832
10022 22:12:09.338972 [0x00000100000000, 0x00000240000000)
10023 22:12:11.228089
10024 22:12:11.231710 Initializing XHCI USB controller at 0x11200000.
10025 22:12:12.269388
10026 22:12:12.273197 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10027 22:12:12.273282
10028 22:12:12.273347
10029 22:12:12.273408
10030 22:12:12.273690 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 22:12:12.374036 asurada: tftpboot 192.168.201.1 11440293/tftp-deploy-480emkml/kernel/image.itb 11440293/tftp-deploy-480emkml/kernel/cmdline
10033 22:12:12.374168 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10034 22:12:12.374267 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10035 22:12:12.378886 tftpboot 192.168.201.1 11440293/tftp-deploy-480emkml/kernel/image.ittp-deploy-480emkml/kernel/cmdline
10036 22:12:12.378970
10037 22:12:12.379034 Waiting for link
10038 22:12:12.539428
10039 22:12:12.539570 R8152: Initializing
10040 22:12:12.539679
10041 22:12:12.542633 Version 9 (ocp_data = 6010)
10042 22:12:12.542716
10043 22:12:12.545955 R8152: Done initializing
10044 22:12:12.546038
10045 22:12:12.546103 Adding net device
10046 22:12:14.417469
10047 22:12:14.417605 done.
10048 22:12:14.417672
10049 22:12:14.417734 MAC: 00:e0:4c:78:7a:aa
10050 22:12:14.417793
10051 22:12:14.420851 Sending DHCP discover... done.
10052 22:12:14.420935
10053 22:12:14.424459 Waiting for reply... done.
10054 22:12:14.424542
10055 22:12:14.427359 Sending DHCP request... done.
10056 22:12:14.427461
10057 22:12:14.427552 Waiting for reply... done.
10058 22:12:14.427700
10059 22:12:14.430808 My ip is 192.168.201.12
10060 22:12:14.430886
10061 22:12:14.434151 The DHCP server ip is 192.168.201.1
10062 22:12:14.434271
10063 22:12:14.437152 TFTP server IP predefined by user: 192.168.201.1
10064 22:12:14.437252
10065 22:12:14.444132 Bootfile predefined by user: 11440293/tftp-deploy-480emkml/kernel/image.itb
10066 22:12:14.444264
10067 22:12:14.447532 Sending tftp read request... done.
10068 22:12:14.447692
10069 22:12:14.450686 Waiting for the transfer...
10070 22:12:14.450852
10071 22:12:14.711738 00000000 ################################################################
10072 22:12:14.711878
10073 22:12:14.967314 00080000 ################################################################
10074 22:12:14.967453
10075 22:12:15.225262 00100000 ################################################################
10076 22:12:15.225397
10077 22:12:15.486729 00180000 ################################################################
10078 22:12:15.486924
10079 22:12:15.745105 00200000 ################################################################
10080 22:12:15.745237
10081 22:12:16.007660 00280000 ################################################################
10082 22:12:16.007858
10083 22:12:16.281588 00300000 ################################################################
10084 22:12:16.281752
10085 22:12:16.538435 00380000 ################################################################
10086 22:12:16.538639
10087 22:12:16.793106 00400000 ################################################################
10088 22:12:16.793234
10089 22:12:17.059869 00480000 ################################################################
10090 22:12:17.059997
10091 22:12:17.325337 00500000 ################################################################
10092 22:12:17.325470
10093 22:12:17.586447 00580000 ################################################################
10094 22:12:17.586579
10095 22:12:17.855673 00600000 ################################################################
10096 22:12:17.855814
10097 22:12:18.123791 00680000 ################################################################
10098 22:12:18.123954
10099 22:12:18.386698 00700000 ################################################################
10100 22:12:18.386837
10101 22:12:18.653680 00780000 ################################################################
10102 22:12:18.653819
10103 22:12:18.942889 00800000 ################################################################
10104 22:12:18.943091
10105 22:12:19.237719 00880000 ################################################################
10106 22:12:19.237857
10107 22:12:19.499566 00900000 ################################################################
10108 22:12:19.499743
10109 22:12:19.777172 00980000 ################################################################
10110 22:12:19.777313
10111 22:12:20.075163 00a00000 ################################################################
10112 22:12:20.075353
10113 22:12:20.375453 00a80000 ################################################################
10114 22:12:20.375598
10115 22:12:20.673277 00b00000 ################################################################
10116 22:12:20.673422
10117 22:12:20.947643 00b80000 ################################################################
10118 22:12:20.947784
10119 22:12:21.219391 00c00000 ################################################################
10120 22:12:21.219531
10121 22:12:21.514573 00c80000 ################################################################
10122 22:12:21.514716
10123 22:12:21.804309 00d00000 ################################################################
10124 22:12:21.804455
10125 22:12:22.087749 00d80000 ################################################################
10126 22:12:22.087891
10127 22:12:22.374440 00e00000 ################################################################
10128 22:12:22.374587
10129 22:12:22.669227 00e80000 ################################################################
10130 22:12:22.669366
10131 22:12:22.951043 00f00000 ################################################################
10132 22:12:22.951182
10133 22:12:23.233851 00f80000 ################################################################
10134 22:12:23.234020
10135 22:12:23.521061 01000000 ################################################################
10136 22:12:23.521202
10137 22:12:23.797092 01080000 ################################################################
10138 22:12:23.797265
10139 22:12:24.056095 01100000 ################################################################
10140 22:12:24.056242
10141 22:12:24.312259 01180000 ################################################################
10142 22:12:24.312460
10143 22:12:24.584375 01200000 ################################################################
10144 22:12:24.584516
10145 22:12:24.860528 01280000 ################################################################
10146 22:12:24.860733
10147 22:12:25.148206 01300000 ################################################################
10148 22:12:25.148414
10149 22:12:25.424641 01380000 ################################################################
10150 22:12:25.424786
10151 22:12:25.707564 01400000 ################################################################
10152 22:12:25.707746
10153 22:12:25.970134 01480000 ################################################################
10154 22:12:25.970282
10155 22:12:26.234103 01500000 ################################################################
10156 22:12:26.234246
10157 22:12:26.509264 01580000 ################################################################
10158 22:12:26.509408
10159 22:12:26.808671 01600000 ################################################################
10160 22:12:26.808817
10161 22:12:27.108372 01680000 ################################################################
10162 22:12:27.108518
10163 22:12:27.402890 01700000 ################################################################
10164 22:12:27.403031
10165 22:12:27.683358 01780000 ################################################################
10166 22:12:27.683506
10167 22:12:27.956600 01800000 ################################################################
10168 22:12:27.956743
10169 22:12:28.256238 01880000 ################################################################
10170 22:12:28.256382
10171 22:12:28.553024 01900000 ################################################################
10172 22:12:28.553169
10173 22:12:28.836365 01980000 ################################################################
10174 22:12:28.836581
10175 22:12:29.123846 01a00000 ################################################################
10176 22:12:29.124018
10177 22:12:29.399511 01a80000 ################################################################
10178 22:12:29.399714
10179 22:12:29.663374 01b00000 ################################################################
10180 22:12:29.663514
10181 22:12:29.945395 01b80000 ################################################################
10182 22:12:29.945563
10183 22:12:30.229441 01c00000 ################################################################
10184 22:12:30.229595
10185 22:12:30.513514 01c80000 ################################################################
10186 22:12:30.513711
10187 22:12:30.803011 01d00000 ################################################################
10188 22:12:30.803163
10189 22:12:31.082451 01d80000 ################################################################
10190 22:12:31.082588
10191 22:12:31.363225 01e00000 ################################################################
10192 22:12:31.363430
10193 22:12:31.657046 01e80000 ################################################################
10194 22:12:31.657188
10195 22:12:31.932307 01f00000 ################################################################
10196 22:12:31.932455
10197 22:12:32.202277 01f80000 ################################################################
10198 22:12:32.202479
10199 22:12:32.471416 02000000 ################################################################
10200 22:12:32.471620
10201 22:12:32.738597 02080000 ################################################################
10202 22:12:32.738738
10203 22:12:33.016860 02100000 ################################################################
10204 22:12:33.017068
10205 22:12:33.285221 02180000 ################################################################
10206 22:12:33.285395
10207 22:12:33.563878 02200000 ################################################################
10208 22:12:33.564023
10209 22:12:33.821475 02280000 ################################################################
10210 22:12:33.821624
10211 22:12:34.096152 02300000 ################################################################
10212 22:12:34.096301
10213 22:12:34.372381 02380000 ################################################################
10214 22:12:34.372533
10215 22:12:34.639336 02400000 ################################################################
10216 22:12:34.639485
10217 22:12:34.902559 02480000 ################################################################
10218 22:12:34.902701
10219 22:12:35.176673 02500000 ################################################################
10220 22:12:35.176814
10221 22:12:35.446455 02580000 ################################################################
10222 22:12:35.446627
10223 22:12:35.735181 02600000 ################################################################
10224 22:12:35.735327
10225 22:12:36.026955 02680000 ################################################################
10226 22:12:36.027099
10227 22:12:36.322375 02700000 ################################################################
10228 22:12:36.322526
10229 22:12:36.620560 02780000 ################################################################
10230 22:12:36.620707
10231 22:12:36.891537 02800000 ################################################################
10232 22:12:36.891724
10233 22:12:37.187032 02880000 ################################################################
10234 22:12:37.187225
10235 22:12:37.461548 02900000 ################################################################
10236 22:12:37.461698
10237 22:12:37.723207 02980000 ################################################################
10238 22:12:37.723349
10239 22:12:38.005266 02a00000 ################################################################
10240 22:12:38.005411
10241 22:12:38.299936 02a80000 ################################################################
10242 22:12:38.300107
10243 22:12:38.588075 02b00000 ################################################################
10244 22:12:38.588222
10245 22:12:38.876183 02b80000 ################################################################
10246 22:12:38.876325
10247 22:12:39.164875 02c00000 ################################################################
10248 22:12:39.165042
10249 22:12:39.461975 02c80000 ################################################################
10250 22:12:39.462111
10251 22:12:39.753936 02d00000 ################################################################
10252 22:12:39.754078
10253 22:12:40.049953 02d80000 ################################################################
10254 22:12:40.050123
10255 22:12:40.342417 02e00000 ################################################################
10256 22:12:40.342560
10257 22:12:40.642319 02e80000 ################################################################
10258 22:12:40.642466
10259 22:12:40.942298 02f00000 ################################################################
10260 22:12:40.942439
10261 22:12:41.238922 02f80000 ################################################################
10262 22:12:41.239071
10263 22:12:41.520903 03000000 ################################################################
10264 22:12:41.521045
10265 22:12:41.818133 03080000 ################################################################
10266 22:12:41.818284
10267 22:12:42.094212 03100000 ################################################################
10268 22:12:42.094345
10269 22:12:42.346436 03180000 ################################################################
10270 22:12:42.346596
10271 22:12:42.607464 03200000 ################################################################
10272 22:12:42.607667
10273 22:12:42.866130 03280000 ################################################################
10274 22:12:42.866269
10275 22:12:43.146138 03300000 ################################################################
10276 22:12:43.146340
10277 22:12:43.409421 03380000 ################################################################
10278 22:12:43.409561
10279 22:12:43.675816 03400000 ################################################################
10280 22:12:43.675948
10281 22:12:43.937560 03480000 ################################################################
10282 22:12:43.937694
10283 22:12:44.193381 03500000 ################################################################
10284 22:12:44.193530
10285 22:12:44.453757 03580000 ################################################################
10286 22:12:44.453905
10287 22:12:44.735133 03600000 ################################################################
10288 22:12:44.735299
10289 22:12:44.989743 03680000 ################################################################
10290 22:12:44.989904
10291 22:12:45.239978 03700000 ################################################################
10292 22:12:45.240144
10293 22:12:45.499193 03780000 ################################################################
10294 22:12:45.499384
10295 22:12:45.760708 03800000 ################################################################
10296 22:12:45.760847
10297 22:12:46.049914 03880000 ################################################################
10298 22:12:46.050051
10299 22:12:46.336747 03900000 ################################################################
10300 22:12:46.336889
10301 22:12:46.635361 03980000 ################################################################
10302 22:12:46.635510
10303 22:12:46.919153 03a00000 ################################################################
10304 22:12:46.919296
10305 22:12:47.173356 03a80000 ################################################################
10306 22:12:47.173506
10307 22:12:47.439316 03b00000 ################################################################
10308 22:12:47.439456
10309 22:12:47.719961 03b80000 ################################################################
10310 22:12:47.720109
10311 22:12:48.009708 03c00000 ################################################################
10312 22:12:48.009860
10313 22:12:48.309110 03c80000 ################################################################
10314 22:12:48.309285
10315 22:12:48.600013 03d00000 ################################################################
10316 22:12:48.600239
10317 22:12:48.864814 03d80000 ################################################################
10318 22:12:48.864960
10319 22:12:49.138709 03e00000 ################################################################
10320 22:12:49.138863
10321 22:12:49.426493 03e80000 ################################################################
10322 22:12:49.426638
10323 22:12:49.705850 03f00000 ################################################################
10324 22:12:49.705993
10325 22:12:49.969877 03f80000 ################################################################
10326 22:12:49.970022
10327 22:12:50.237698 04000000 ################################################################
10328 22:12:50.237846
10329 22:12:50.530379 04080000 ################################################################
10330 22:12:50.530523
10331 22:12:50.807651 04100000 ################################################################
10332 22:12:50.807797
10333 22:12:51.077192 04180000 ################################################################
10334 22:12:51.077338
10335 22:12:51.348712 04200000 ################################################################
10336 22:12:51.348882
10337 22:12:51.639464 04280000 ################################################################
10338 22:12:51.639628
10339 22:12:51.911948 04300000 ################################################################
10340 22:12:51.912116
10341 22:12:52.193716 04380000 ################################################################
10342 22:12:52.193864
10343 22:12:52.471082 04400000 ################################################################
10344 22:12:52.471226
10345 22:12:52.738372 04480000 ################################################################
10346 22:12:52.738558
10347 22:12:53.031940 04500000 ################################################################
10348 22:12:53.032098
10349 22:12:53.297267 04580000 ################################################################
10350 22:12:53.297408
10351 22:12:53.584091 04600000 ################################################################
10352 22:12:53.584231
10353 22:12:53.878791 04680000 ################################################################
10354 22:12:53.878937
10355 22:12:54.155854 04700000 ################################################################
10356 22:12:54.155997
10357 22:12:54.414355 04780000 ################################################################
10358 22:12:54.414548
10359 22:12:54.694201 04800000 ################################################################
10360 22:12:54.694356
10361 22:12:54.956429 04880000 ################################################################
10362 22:12:54.956575
10363 22:12:55.209382 04900000 ################################################################
10364 22:12:55.209529
10365 22:12:55.459870 04980000 ################################################################
10366 22:12:55.460019
10367 22:12:55.729869 04a00000 ################################################################
10368 22:12:55.730010
10369 22:12:56.010728 04a80000 ################################################################
10370 22:12:56.010870
10371 22:12:56.285271 04b00000 ################################################################
10372 22:12:56.285415
10373 22:12:56.581750 04b80000 ################################################################
10374 22:12:56.581899
10375 22:12:56.856983 04c00000 ################################################################
10376 22:12:56.857122
10377 22:12:57.146871 04c80000 ################################################################
10378 22:12:57.147040
10379 22:12:57.418867 04d00000 ################################################################
10380 22:12:57.419014
10381 22:12:57.688772 04d80000 ################################################################
10382 22:12:57.688917
10383 22:12:57.962184 04e00000 ################################################################
10384 22:12:57.962342
10385 22:12:58.219750 04e80000 ################################################################
10386 22:12:58.219937
10387 22:12:58.481685 04f00000 ################################################################
10388 22:12:58.481828
10389 22:12:58.780751 04f80000 ################################################################
10390 22:12:58.780896
10391 22:12:59.079027 05000000 ################################################################
10392 22:12:59.079171
10393 22:12:59.371240 05080000 ################################################################
10394 22:12:59.371379
10395 22:12:59.635023 05100000 ################################################################
10396 22:12:59.635174
10397 22:12:59.918122 05180000 ################################################################
10398 22:12:59.918264
10399 22:13:00.213954 05200000 ################################################################
10400 22:13:00.214100
10401 22:13:00.514926 05280000 ################################################################
10402 22:13:00.515070
10403 22:13:00.814317 05300000 ################################################################
10404 22:13:00.814463
10405 22:13:01.115138 05380000 ################################################################
10406 22:13:01.115282
10407 22:13:01.416093 05400000 ################################################################
10408 22:13:01.416236
10409 22:13:01.685676 05480000 ################################################################
10410 22:13:01.685826
10411 22:13:01.971937 05500000 ################################################################
10412 22:13:01.972080
10413 22:13:02.252503 05580000 ################################################################
10414 22:13:02.252653
10415 22:13:02.521640 05600000 ################################################################
10416 22:13:02.521786
10417 22:13:02.791484 05680000 ################################################################
10418 22:13:02.791662
10419 22:13:03.086026 05700000 ################################################################
10420 22:13:03.086245
10421 22:13:03.381424 05780000 ################################################################
10422 22:13:03.381567
10423 22:13:03.651859 05800000 ################################################################
10424 22:13:03.652008
10425 22:13:03.945340 05880000 ################################################################
10426 22:13:03.945486
10427 22:13:04.208870 05900000 ################################################################
10428 22:13:04.209081
10429 22:13:04.472890 05980000 ################################################################
10430 22:13:04.473100
10431 22:13:04.761637 05a00000 ################################################################
10432 22:13:04.761851
10433 22:13:05.042589 05a80000 ################################################################
10434 22:13:05.042735
10435 22:13:05.333237 05b00000 ################################################################
10436 22:13:05.333438
10437 22:13:05.628606 05b80000 ################################################################
10438 22:13:05.628757
10439 22:13:05.911536 05c00000 ################################################################
10440 22:13:05.911731
10441 22:13:06.204097 05c80000 ################################################################
10442 22:13:06.204298
10443 22:13:06.484627 05d00000 ################################################################
10444 22:13:06.484779
10445 22:13:06.783573 05d80000 ################################################################
10446 22:13:06.783744
10447 22:13:07.075473 05e00000 ################################################################
10448 22:13:07.075752
10449 22:13:07.370977 05e80000 ################################################################
10450 22:13:07.371124
10451 22:13:07.669235 05f00000 ################################################################
10452 22:13:07.669404
10453 22:13:07.963369 05f80000 ################################################################
10454 22:13:07.963511
10455 22:13:08.259118 06000000 ################################################################
10456 22:13:08.259272
10457 22:13:08.525110 06080000 ################################################################
10458 22:13:08.525258
10459 22:13:08.782150 06100000 ################################################################
10460 22:13:08.782300
10461 22:13:09.052141 06180000 ################################################################
10462 22:13:09.052352
10463 22:13:09.345473 06200000 ################################################################
10464 22:13:09.345622
10465 22:13:09.624767 06280000 ################################################################
10466 22:13:09.624972
10467 22:13:09.920992 06300000 ################################################################
10468 22:13:09.921141
10469 22:13:10.181875 06380000 ################################################################
10470 22:13:10.182095
10471 22:13:10.450425 06400000 ################################################################
10472 22:13:10.450620
10473 22:13:10.737724 06480000 ################################################################
10474 22:13:10.737868
10475 22:13:10.992849 06500000 ################################################################
10476 22:13:10.993063
10477 22:13:11.246541 06580000 ################################################################
10478 22:13:11.246732
10479 22:13:11.527461 06600000 ################################################################
10480 22:13:11.527610
10481 22:13:11.796361 06680000 ################################################################
10482 22:13:11.796505
10483 22:13:12.060202 06700000 ################################################################
10484 22:13:12.060348
10485 22:13:12.345546 06780000 ################################################################
10486 22:13:12.345696
10487 22:13:12.515787 06800000 ########################################### done.
10488 22:13:12.515924
10489 22:13:12.519798 The bootfile was 109398546 bytes long.
10490 22:13:12.519884
10491 22:13:12.522587 Sending tftp read request... done.
10492 22:13:12.522673
10493 22:13:12.525993 Waiting for the transfer...
10494 22:13:12.526077
10495 22:13:12.526143 00000000 # done.
10496 22:13:12.526206
10497 22:13:12.535831 Command line loaded dynamically from TFTP file: 11440293/tftp-deploy-480emkml/kernel/cmdline
10498 22:13:12.535915
10499 22:13:12.549826 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10500 22:13:12.549915
10501 22:13:12.549980 Loading FIT.
10502 22:13:12.550041
10503 22:13:12.552940 Image ramdisk-1 has 98311238 bytes.
10504 22:13:12.553024
10505 22:13:12.556178 Image fdt-1 has 47278 bytes.
10506 22:13:12.556261
10507 22:13:12.559255 Image kernel-1 has 11037994 bytes.
10508 22:13:12.559337
10509 22:13:12.566069 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10510 22:13:12.569167
10511 22:13:12.585727 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10512 22:13:12.585816
10513 22:13:12.588980 Choosing best match conf-1 for compat google,spherion-rev2.
10514 22:13:12.594755
10515 22:13:12.599388 Connected to device vid:did:rid of 1ae0:0028:00
10516 22:13:12.607734
10517 22:13:12.610850 tpm_get_response: command 0x17b, return code 0x0
10518 22:13:12.610934
10519 22:13:12.614022 ec_init: CrosEC protocol v3 supported (256, 248)
10520 22:13:12.619520
10521 22:13:12.622560 tpm_cleanup: add release locality here.
10522 22:13:12.622643
10523 22:13:12.622709 Shutting down all USB controllers.
10524 22:13:12.622771
10525 22:13:12.625904 Removing current net device
10526 22:13:12.625988
10527 22:13:12.632567 Exiting depthcharge with code 4 at timestamp: 93689544
10528 22:13:12.632652
10529 22:13:12.635729 LZMA decompressing kernel-1 to 0x821a6718
10530 22:13:12.635812
10531 22:13:12.639371 LZMA decompressing kernel-1 to 0x40000000
10532 22:13:14.026858
10533 22:13:14.027009 jumping to kernel
10534 22:13:14.027483 end: 2.2.4 bootloader-commands (duration 00:01:06) [common]
10535 22:13:14.027586 start: 2.2.5 auto-login-action (timeout 00:03:19) [common]
10536 22:13:14.027675 Setting prompt string to ['Linux version [0-9]']
10537 22:13:14.027745 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10538 22:13:14.027813 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10539 22:13:14.108915
10540 22:13:14.111754 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10541 22:13:14.115627 start: 2.2.5.1 login-action (timeout 00:03:19) [common]
10542 22:13:14.115718 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10543 22:13:14.115791 Setting prompt string to []
10544 22:13:14.115873 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10545 22:13:14.115949 Using line separator: #'\n'#
10546 22:13:14.116009 No login prompt set.
10547 22:13:14.116070 Parsing kernel messages
10548 22:13:14.116125 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10549 22:13:14.116228 [login-action] Waiting for messages, (timeout 00:03:19)
10550 22:13:14.135314 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j35911-arm64-gcc-10-defconfig-arm64-chromebook-zzzh4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Sep 5 21:54:53 UTC 2023
10551 22:13:14.138774 [ 0.000000] random: crng init done
10552 22:13:14.145067 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10553 22:13:14.145151 [ 0.000000] efi: UEFI not found.
10554 22:13:14.155066 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10555 22:13:14.161843 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10556 22:13:14.171896 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10557 22:13:14.181734 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10558 22:13:14.188369 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10559 22:13:14.191651 [ 0.000000] printk: bootconsole [mtk8250] enabled
10560 22:13:14.200624 [ 0.000000] NUMA: No NUMA configuration found
10561 22:13:14.207136 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10562 22:13:14.213949 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10563 22:13:14.214033 [ 0.000000] Zone ranges:
10564 22:13:14.220589 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10565 22:13:14.223927 [ 0.000000] DMA32 empty
10566 22:13:14.230241 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10567 22:13:14.233613 [ 0.000000] Movable zone start for each node
10568 22:13:14.236811 [ 0.000000] Early memory node ranges
10569 22:13:14.243754 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10570 22:13:14.250154 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10571 22:13:14.256706 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10572 22:13:14.263552 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10573 22:13:14.270436 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10574 22:13:14.277327 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10575 22:13:14.333238 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10576 22:13:14.339694 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10577 22:13:14.346199 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10578 22:13:14.350006 [ 0.000000] psci: probing for conduit method from DT.
10579 22:13:14.356174 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10580 22:13:14.359539 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10581 22:13:14.366546 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10582 22:13:14.369972 [ 0.000000] psci: SMC Calling Convention v1.2
10583 22:13:14.376414 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10584 22:13:14.379766 [ 0.000000] Detected VIPT I-cache on CPU0
10585 22:13:14.386097 [ 0.000000] CPU features: detected: GIC system register CPU interface
10586 22:13:14.392961 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10587 22:13:14.399170 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10588 22:13:14.406133 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10589 22:13:14.412692 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10590 22:13:14.422899 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10591 22:13:14.426027 [ 0.000000] alternatives: applying boot alternatives
10592 22:13:14.432683 [ 0.000000] Fallback order for Node 0: 0
10593 22:13:14.439935 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10594 22:13:14.440019 [ 0.000000] Policy zone: Normal
10595 22:13:14.455842 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10596 22:13:14.465854 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10597 22:13:14.477431 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10598 22:13:14.487535 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10599 22:13:14.494434 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10600 22:13:14.497325 <6>[ 0.000000] software IO TLB: area num 8.
10601 22:13:14.554065 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10602 22:13:14.702943 <6>[ 0.000000] Memory: 7873548K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 479220K reserved, 32768K cma-reserved)
10603 22:13:14.709655 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10604 22:13:14.716212 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10605 22:13:14.719571 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10606 22:13:14.725819 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10607 22:13:14.732895 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10608 22:13:14.736077 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10609 22:13:14.745906 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10610 22:13:14.752739 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10611 22:13:14.755998 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10612 22:13:14.763715 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10613 22:13:14.766947 <6>[ 0.000000] GICv3: 608 SPIs implemented
10614 22:13:14.773639 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10615 22:13:14.777409 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10616 22:13:14.780432 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10617 22:13:14.790458 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10618 22:13:14.800188 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10619 22:13:14.813285 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10620 22:13:14.820124 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10621 22:13:14.829776 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10622 22:13:14.842700 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10623 22:13:14.849043 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10624 22:13:14.855909 <6>[ 0.009233] Console: colour dummy device 80x25
10625 22:13:14.866082 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10626 22:13:14.872763 <6>[ 0.024401] pid_max: default: 32768 minimum: 301
10627 22:13:14.875604 <6>[ 0.029273] LSM: Security Framework initializing
10628 22:13:14.882681 <6>[ 0.034212] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10629 22:13:14.892390 <6>[ 0.042027] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10630 22:13:14.899124 <6>[ 0.051319] cblist_init_generic: Setting adjustable number of callback queues.
10631 22:13:14.905890 <6>[ 0.058767] cblist_init_generic: Setting shift to 3 and lim to 1.
10632 22:13:14.916000 <6>[ 0.065106] cblist_init_generic: Setting adjustable number of callback queues.
10633 22:13:14.919209 <6>[ 0.072577] cblist_init_generic: Setting shift to 3 and lim to 1.
10634 22:13:14.925642 <6>[ 0.078976] rcu: Hierarchical SRCU implementation.
10635 22:13:14.932409 <6>[ 0.083990] rcu: Max phase no-delay instances is 1000.
10636 22:13:14.938998 <6>[ 0.091024] EFI services will not be available.
10637 22:13:14.942314 <6>[ 0.095995] smp: Bringing up secondary CPUs ...
10638 22:13:14.950172 <6>[ 0.101039] Detected VIPT I-cache on CPU1
10639 22:13:14.956816 <6>[ 0.101107] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10640 22:13:14.963206 <6>[ 0.101139] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10641 22:13:14.967339 <6>[ 0.101474] Detected VIPT I-cache on CPU2
10642 22:13:14.973615 <6>[ 0.101523] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10643 22:13:14.980124 <6>[ 0.101538] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10644 22:13:14.986232 <6>[ 0.101795] Detected VIPT I-cache on CPU3
10645 22:13:14.993342 <6>[ 0.101842] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10646 22:13:14.999891 <6>[ 0.101855] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10647 22:13:15.003268 <6>[ 0.102162] CPU features: detected: Spectre-v4
10648 22:13:15.009714 <6>[ 0.102169] CPU features: detected: Spectre-BHB
10649 22:13:15.013405 <6>[ 0.102174] Detected PIPT I-cache on CPU4
10650 22:13:15.020079 <6>[ 0.102229] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10651 22:13:15.026418 <6>[ 0.102247] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10652 22:13:15.033072 <6>[ 0.102544] Detected PIPT I-cache on CPU5
10653 22:13:15.039489 <6>[ 0.102606] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10654 22:13:15.046453 <6>[ 0.102623] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10655 22:13:15.049592 <6>[ 0.102908] Detected PIPT I-cache on CPU6
10656 22:13:15.056207 <6>[ 0.102972] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10657 22:13:15.062857 <6>[ 0.102989] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10658 22:13:15.069724 <6>[ 0.103288] Detected PIPT I-cache on CPU7
10659 22:13:15.075773 <6>[ 0.103353] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10660 22:13:15.082910 <6>[ 0.103369] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10661 22:13:15.086038 <6>[ 0.103416] smp: Brought up 1 node, 8 CPUs
10662 22:13:15.092425 <6>[ 0.244688] SMP: Total of 8 processors activated.
10663 22:13:15.096183 <6>[ 0.249609] CPU features: detected: 32-bit EL0 Support
10664 22:13:15.105864 <6>[ 0.254972] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10665 22:13:15.112579 <6>[ 0.263772] CPU features: detected: Common not Private translations
10666 22:13:15.115907 <6>[ 0.270287] CPU features: detected: CRC32 instructions
10667 22:13:15.122747 <6>[ 0.275639] CPU features: detected: RCpc load-acquire (LDAPR)
10668 22:13:15.129136 <6>[ 0.281598] CPU features: detected: LSE atomic instructions
10669 22:13:15.135526 <6>[ 0.287379] CPU features: detected: Privileged Access Never
10670 22:13:15.139232 <6>[ 0.293159] CPU features: detected: RAS Extension Support
10671 22:13:15.149018 <6>[ 0.298771] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10672 22:13:15.152281 <6>[ 0.305989] CPU: All CPU(s) started at EL2
10673 22:13:15.158831 <6>[ 0.310306] alternatives: applying system-wide alternatives
10674 22:13:15.168039 <6>[ 0.320975] devtmpfs: initialized
10675 22:13:15.179953 <6>[ 0.329842] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10676 22:13:15.189811 <6>[ 0.339806] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10677 22:13:15.196227 <6>[ 0.347823] pinctrl core: initialized pinctrl subsystem
10678 22:13:15.200092 <6>[ 0.354461] DMI not present or invalid.
10679 22:13:15.206359 <6>[ 0.358867] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10680 22:13:15.216098 <6>[ 0.365724] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10681 22:13:15.222746 <6>[ 0.373303] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10682 22:13:15.233063 <6>[ 0.381523] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10683 22:13:15.236352 <6>[ 0.389765] audit: initializing netlink subsys (disabled)
10684 22:13:15.246073 <5>[ 0.395461] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10685 22:13:15.252735 <6>[ 0.396161] thermal_sys: Registered thermal governor 'step_wise'
10686 22:13:15.259752 <6>[ 0.403429] thermal_sys: Registered thermal governor 'power_allocator'
10687 22:13:15.262634 <6>[ 0.409685] cpuidle: using governor menu
10688 22:13:15.266119 <6>[ 0.420644] NET: Registered PF_QIPCRTR protocol family
10689 22:13:15.276026 <6>[ 0.426125] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10690 22:13:15.279618 <6>[ 0.433229] ASID allocator initialised with 32768 entries
10691 22:13:15.286410 <6>[ 0.439777] Serial: AMBA PL011 UART driver
10692 22:13:15.295442 <4>[ 0.448475] Trying to register duplicate clock ID: 134
10693 22:13:15.348954 <6>[ 0.505787] KASLR enabled
10694 22:13:15.363452 <6>[ 0.513511] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10695 22:13:15.369904 <6>[ 0.520524] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10696 22:13:15.376861 <6>[ 0.527013] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10697 22:13:15.383494 <6>[ 0.534020] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10698 22:13:15.390363 <6>[ 0.540508] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10699 22:13:15.396801 <6>[ 0.547511] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10700 22:13:15.403476 <6>[ 0.553998] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10701 22:13:15.410114 <6>[ 0.561002] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10702 22:13:15.413389 <6>[ 0.568499] ACPI: Interpreter disabled.
10703 22:13:15.421674 <6>[ 0.574909] iommu: Default domain type: Translated
10704 22:13:15.428301 <6>[ 0.580023] iommu: DMA domain TLB invalidation policy: strict mode
10705 22:13:15.431903 <5>[ 0.586646] SCSI subsystem initialized
10706 22:13:15.438354 <6>[ 0.590814] usbcore: registered new interface driver usbfs
10707 22:13:15.444684 <6>[ 0.596545] usbcore: registered new interface driver hub
10708 22:13:15.447906 <6>[ 0.602095] usbcore: registered new device driver usb
10709 22:13:15.454976 <6>[ 0.608184] pps_core: LinuxPPS API ver. 1 registered
10710 22:13:15.465050 <6>[ 0.613379] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10711 22:13:15.468200 <6>[ 0.622728] PTP clock support registered
10712 22:13:15.471475 <6>[ 0.626971] EDAC MC: Ver: 3.0.0
10713 22:13:15.479056 <6>[ 0.632130] FPGA manager framework
10714 22:13:15.482234 <6>[ 0.635807] Advanced Linux Sound Architecture Driver Initialized.
10715 22:13:15.486636 <6>[ 0.642580] vgaarb: loaded
10716 22:13:15.492757 <6>[ 0.645749] clocksource: Switched to clocksource arch_sys_counter
10717 22:13:15.499178 <5>[ 0.652189] VFS: Disk quotas dquot_6.6.0
10718 22:13:15.506150 <6>[ 0.656373] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10719 22:13:15.509352 <6>[ 0.663563] pnp: PnP ACPI: disabled
10720 22:13:15.516947 <6>[ 0.670219] NET: Registered PF_INET protocol family
10721 22:13:15.523806 <6>[ 0.675815] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10722 22:13:15.538202 <6>[ 0.688146] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10723 22:13:15.547821 <6>[ 0.696963] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10724 22:13:15.554562 <6>[ 0.704933] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10725 22:13:15.561556 <6>[ 0.713634] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10726 22:13:15.573349 <6>[ 0.723383] TCP: Hash tables configured (established 65536 bind 65536)
10727 22:13:15.580125 <6>[ 0.730243] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10728 22:13:15.586971 <6>[ 0.737438] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10729 22:13:15.593786 <6>[ 0.745140] NET: Registered PF_UNIX/PF_LOCAL protocol family
10730 22:13:15.600110 <6>[ 0.751319] RPC: Registered named UNIX socket transport module.
10731 22:13:15.603813 <6>[ 0.757472] RPC: Registered udp transport module.
10732 22:13:15.609915 <6>[ 0.762404] RPC: Registered tcp transport module.
10733 22:13:15.616782 <6>[ 0.767336] RPC: Registered tcp NFSv4.1 backchannel transport module.
10734 22:13:15.620320 <6>[ 0.774004] PCI: CLS 0 bytes, default 64
10735 22:13:15.623468 <6>[ 0.778390] Unpacking initramfs...
10736 22:13:15.633469 <6>[ 0.782161] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10737 22:13:15.640180 <6>[ 0.790805] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10738 22:13:15.646610 <6>[ 0.799642] kvm [1]: IPA Size Limit: 40 bits
10739 22:13:15.649837 <6>[ 0.804168] kvm [1]: GICv3: no GICV resource entry
10740 22:13:15.656321 <6>[ 0.809188] kvm [1]: disabling GICv2 emulation
10741 22:13:15.663264 <6>[ 0.813875] kvm [1]: GIC system register CPU interface enabled
10742 22:13:15.666301 <6>[ 0.820043] kvm [1]: vgic interrupt IRQ18
10743 22:13:15.672968 <6>[ 0.825828] kvm [1]: VHE mode initialized successfully
10744 22:13:15.679509 <5>[ 0.832188] Initialise system trusted keyrings
10745 22:13:15.686285 <6>[ 0.836999] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10746 22:13:15.693852 <6>[ 0.846976] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10747 22:13:15.700219 <5>[ 0.853359] NFS: Registering the id_resolver key type
10748 22:13:15.703250 <5>[ 0.858661] Key type id_resolver registered
10749 22:13:15.710057 <5>[ 0.863077] Key type id_legacy registered
10750 22:13:15.716564 <6>[ 0.867355] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10751 22:13:15.723275 <6>[ 0.874274] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10752 22:13:15.729730 <6>[ 0.881971] 9p: Installing v9fs 9p2000 file system support
10753 22:13:15.766740 <5>[ 0.920301] Key type asymmetric registered
10754 22:13:15.770336 <5>[ 0.924629] Asymmetric key parser 'x509' registered
10755 22:13:15.780165 <6>[ 0.929772] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10756 22:13:15.783628 <6>[ 0.937384] io scheduler mq-deadline registered
10757 22:13:15.787053 <6>[ 0.942143] io scheduler kyber registered
10758 22:13:15.805747 <6>[ 0.959107] EINJ: ACPI disabled.
10759 22:13:15.837940 <4>[ 0.984638] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10760 22:13:15.847425 <4>[ 0.995257] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10761 22:13:15.862340 <6>[ 1.015920] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10762 22:13:15.870599 <6>[ 1.023764] printk: console [ttyS0] disabled
10763 22:13:15.898410 <6>[ 1.048410] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10764 22:13:15.904893 <6>[ 1.057884] printk: console [ttyS0] enabled
10765 22:13:15.908052 <6>[ 1.057884] printk: console [ttyS0] enabled
10766 22:13:15.915026 <6>[ 1.066778] printk: bootconsole [mtk8250] disabled
10767 22:13:15.918227 <6>[ 1.066778] printk: bootconsole [mtk8250] disabled
10768 22:13:15.925005 <6>[ 1.078014] SuperH (H)SCI(F) driver initialized
10769 22:13:15.928468 <6>[ 1.083273] msm_serial: driver initialized
10770 22:13:15.942073 <6>[ 1.092232] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10771 22:13:15.951980 <6>[ 1.100779] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10772 22:13:15.959008 <6>[ 1.109320] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10773 22:13:15.968782 <6>[ 1.117949] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10774 22:13:15.978501 <6>[ 1.126656] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10775 22:13:15.985293 <6>[ 1.135376] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10776 22:13:15.995055 <6>[ 1.143915] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10777 22:13:16.002032 <6>[ 1.152718] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10778 22:13:16.011844 <6>[ 1.161261] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10779 22:13:16.023392 <6>[ 1.176589] loop: module loaded
10780 22:13:16.030051 <6>[ 1.182579] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10781 22:13:16.052518 <4>[ 1.205879] mtk-pmic-keys: Failed to locate of_node [id: -1]
10782 22:13:16.059177 <6>[ 1.212821] megasas: 07.719.03.00-rc1
10783 22:13:16.069233 <6>[ 1.222438] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10784 22:13:16.076129 <6>[ 1.229144] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10785 22:13:16.091646 <6>[ 1.245217] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10786 22:13:16.146515 <6>[ 1.293657] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10787 22:13:19.633687 <6>[ 4.787472] Freeing initrd memory: 96004K
10788 22:13:19.643842 <6>[ 4.797674] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10789 22:13:19.654770 <6>[ 4.808566] tun: Universal TUN/TAP device driver, 1.6
10790 22:13:19.657936 <6>[ 4.814642] thunder_xcv, ver 1.0
10791 22:13:19.661562 <6>[ 4.818149] thunder_bgx, ver 1.0
10792 22:13:19.664678 <6>[ 4.821641] nicpf, ver 1.0
10793 22:13:19.675303 <6>[ 4.825652] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10794 22:13:19.678286 <6>[ 4.833128] hns3: Copyright (c) 2017 Huawei Corporation.
10795 22:13:19.685071 <6>[ 4.838718] hclge is initializing
10796 22:13:19.688246 <6>[ 4.842294] e1000: Intel(R) PRO/1000 Network Driver
10797 22:13:19.695153 <6>[ 4.847423] e1000: Copyright (c) 1999-2006 Intel Corporation.
10798 22:13:19.698893 <6>[ 4.853436] e1000e: Intel(R) PRO/1000 Network Driver
10799 22:13:19.705063 <6>[ 4.858652] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10800 22:13:19.711556 <6>[ 4.864836] igb: Intel(R) Gigabit Ethernet Network Driver
10801 22:13:19.718393 <6>[ 4.870485] igb: Copyright (c) 2007-2014 Intel Corporation.
10802 22:13:19.725241 <6>[ 4.876321] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10803 22:13:19.731537 <6>[ 4.882839] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10804 22:13:19.734804 <6>[ 4.889298] sky2: driver version 1.30
10805 22:13:19.741674 <6>[ 4.894298] VFIO - User Level meta-driver version: 0.3
10806 22:13:19.748916 <6>[ 4.902519] usbcore: registered new interface driver usb-storage
10807 22:13:19.755353 <6>[ 4.908962] usbcore: registered new device driver onboard-usb-hub
10808 22:13:19.764142 <6>[ 4.918029] mt6397-rtc mt6359-rtc: registered as rtc0
10809 22:13:19.774098 <6>[ 4.923492] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-05T22:12:13 UTC (1693951933)
10810 22:13:19.777549 <6>[ 4.933059] i2c_dev: i2c /dev entries driver
10811 22:13:19.794405 <6>[ 4.944745] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10812 22:13:19.814168 <6>[ 4.967737] cpu cpu0: EM: created perf domain
10813 22:13:19.817570 <6>[ 4.972730] cpu cpu4: EM: created perf domain
10814 22:13:19.824347 <6>[ 4.978117] sdhci: Secure Digital Host Controller Interface driver
10815 22:13:19.831001 <6>[ 4.984546] sdhci: Copyright(c) Pierre Ossman
10816 22:13:19.837563 <6>[ 4.989499] Synopsys Designware Multimedia Card Interface Driver
10817 22:13:19.844244 <6>[ 4.996136] sdhci-pltfm: SDHCI platform and OF driver helper
10818 22:13:19.847719 <6>[ 4.996207] mmc0: CQHCI version 5.10
10819 22:13:19.854027 <6>[ 5.006371] ledtrig-cpu: registered to indicate activity on CPUs
10820 22:13:19.860574 <6>[ 5.013415] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10821 22:13:19.867285 <6>[ 5.020477] usbcore: registered new interface driver usbhid
10822 22:13:19.870978 <6>[ 5.026299] usbhid: USB HID core driver
10823 22:13:19.877029 <6>[ 5.030506] spi_master spi0: will run message pump with realtime priority
10824 22:13:19.922836 <6>[ 5.069923] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10825 22:13:19.941947 <6>[ 5.085637] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10826 22:13:19.949003 <6>[ 5.100543] cros-ec-spi spi0.0: Chrome EC device registered
10827 22:13:19.952590 <6>[ 5.106610] mmc0: Command Queue Engine enabled
10828 22:13:19.958841 <6>[ 5.111350] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10829 22:13:19.965992 <6>[ 5.118624] mmcblk0: mmc0:0001 DA4128 116 GiB
10830 22:13:19.972304 <6>[ 5.121203] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10831 22:13:19.978891 <6>[ 5.127750] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10832 22:13:19.986072 <6>[ 5.133670] NET: Registered PF_PACKET protocol family
10833 22:13:19.989050 <6>[ 5.139409] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10834 22:13:19.995531 <6>[ 5.143986] 9pnet: Installing 9P2000 support
10835 22:13:19.998669 <6>[ 5.149667] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10836 22:13:20.005230 <5>[ 5.153657] Key type dns_resolver registered
10837 22:13:20.012169 <6>[ 5.159345] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10838 22:13:20.015706 <6>[ 5.164054] registered taskstats version 1
10839 22:13:20.021728 <5>[ 5.174248] Loading compiled-in X.509 certificates
10840 22:13:20.047990 <4>[ 5.195429] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10841 22:13:20.058312 <4>[ 5.206098] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10842 22:13:20.064936 <3>[ 5.216626] debugfs: File 'uA_load' in directory '/' already present!
10843 22:13:20.071260 <3>[ 5.223325] debugfs: File 'min_uV' in directory '/' already present!
10844 22:13:20.078078 <3>[ 5.230005] debugfs: File 'max_uV' in directory '/' already present!
10845 22:13:20.084709 <3>[ 5.236618] debugfs: File 'constraint_flags' in directory '/' already present!
10846 22:13:20.095541 <3>[ 5.245944] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10847 22:13:20.104671 <6>[ 5.258508] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10848 22:13:20.111690 <6>[ 5.265232] xhci-mtk 11200000.usb: xHCI Host Controller
10849 22:13:20.117970 <6>[ 5.270749] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10850 22:13:20.128561 <6>[ 5.278613] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10851 22:13:20.134414 <6>[ 5.288037] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10852 22:13:20.141347 <6>[ 5.294110] xhci-mtk 11200000.usb: xHCI Host Controller
10853 22:13:20.147975 <6>[ 5.299586] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10854 22:13:20.154965 <6>[ 5.307241] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10855 22:13:20.160962 <6>[ 5.315014] hub 1-0:1.0: USB hub found
10856 22:13:20.164465 <6>[ 5.319029] hub 1-0:1.0: 1 port detected
10857 22:13:20.174365 <6>[ 5.323298] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10858 22:13:20.177623 <6>[ 5.331897] hub 2-0:1.0: USB hub found
10859 22:13:20.180774 <6>[ 5.335902] hub 2-0:1.0: 1 port detected
10860 22:13:20.190281 <6>[ 5.344087] mtk-msdc 11f70000.mmc: Got CD GPIO
10861 22:13:20.200461 <6>[ 5.350323] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10862 22:13:20.207076 <6>[ 5.358342] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10863 22:13:20.216905 <4>[ 5.366263] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10864 22:13:20.223355 <6>[ 5.375785] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10865 22:13:20.233414 <6>[ 5.383861] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10866 22:13:20.240006 <6>[ 5.391947] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10867 22:13:20.250025 <6>[ 5.399876] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10868 22:13:20.256552 <6>[ 5.407695] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10869 22:13:20.266891 <6>[ 5.415512] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10870 22:13:20.276715 <6>[ 5.426162] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10871 22:13:20.283237 <6>[ 5.434546] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10872 22:13:20.293200 <6>[ 5.442884] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10873 22:13:20.299842 <6>[ 5.451228] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10874 22:13:20.309763 <6>[ 5.459566] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10875 22:13:20.316683 <6>[ 5.467905] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10876 22:13:20.326450 <6>[ 5.476252] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10877 22:13:20.333207 <6>[ 5.484590] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10878 22:13:20.342781 <6>[ 5.492928] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10879 22:13:20.349608 <6>[ 5.501265] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10880 22:13:20.359576 <6>[ 5.509602] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10881 22:13:20.366365 <6>[ 5.517940] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10882 22:13:20.376051 <6>[ 5.526278] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10883 22:13:20.382563 <6>[ 5.534615] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10884 22:13:20.392773 <6>[ 5.542952] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10885 22:13:20.399403 <6>[ 5.551720] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10886 22:13:20.405876 <6>[ 5.558869] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10887 22:13:20.412713 <6>[ 5.565623] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10888 22:13:20.419435 <6>[ 5.572386] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10889 22:13:20.425791 <6>[ 5.579324] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10890 22:13:20.435840 <6>[ 5.586191] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10891 22:13:20.445700 <6>[ 5.595323] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10892 22:13:20.455695 <6>[ 5.604442] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10893 22:13:20.465682 <6>[ 5.613737] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10894 22:13:20.472214 <6>[ 5.623206] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10895 22:13:20.482132 <6>[ 5.632673] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10896 22:13:20.492147 <6>[ 5.641793] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10897 22:13:20.501996 <6>[ 5.651261] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10898 22:13:20.512064 <6>[ 5.660380] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10899 22:13:20.522123 <6>[ 5.669676] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10900 22:13:20.531773 <6>[ 5.679836] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10901 22:13:20.541711 <6>[ 5.691646] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10902 22:13:20.571792 <6>[ 5.722336] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10903 22:13:20.599883 <6>[ 5.753817] hub 2-1:1.0: USB hub found
10904 22:13:20.603290 <6>[ 5.758318] hub 2-1:1.0: 3 ports detected
10905 22:13:20.723726 <6>[ 5.874018] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10906 22:13:20.878347 <6>[ 6.032169] hub 1-1:1.0: USB hub found
10907 22:13:20.881385 <6>[ 6.036671] hub 1-1:1.0: 4 ports detected
10908 22:13:20.955648 <6>[ 6.106289] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10909 22:13:21.203808 <6>[ 6.354075] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10910 22:13:21.336271 <6>[ 6.490180] hub 1-1.4:1.0: USB hub found
10911 22:13:21.339395 <6>[ 6.494874] hub 1-1.4:1.0: 2 ports detected
10912 22:13:21.639425 <6>[ 6.790049] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10913 22:13:21.831100 <6>[ 6.982125] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10914 22:13:32.840565 <6>[ 17.999145] ALSA device list:
10915 22:13:32.847150 <6>[ 18.002444] No soundcards found.
10916 22:13:32.855125 <6>[ 18.010553] Freeing unused kernel memory: 8384K
10917 22:13:32.858553 <6>[ 18.015593] Run /init as init process
10918 22:13:32.911573 <6>[ 18.067063] NET: Registered PF_INET6 protocol family
10919 22:13:32.918706 <6>[ 18.073408] Segment Routing with IPv6
10920 22:13:32.921378 <6>[ 18.077360] In-situ OAM (IOAM) with IPv6
10921 22:13:32.954054 <30>[ 18.092641] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10922 22:13:32.961147 <30>[ 18.116343] systemd[1]: Detected architecture arm64.
10923 22:13:32.961295
10924 22:13:32.967553 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10925 22:13:32.967701
10926 22:13:32.982554 <30>[ 18.137950] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10927 22:13:33.095455 <30>[ 18.247448] systemd[1]: Queued start job for default target Graphical Interface.
10928 22:13:33.143496 <30>[ 18.298870] systemd[1]: Created slice system-getty.slice.
10929 22:13:33.149931 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10930 22:13:33.167100 <30>[ 18.322699] systemd[1]: Created slice system-modprobe.slice.
10931 22:13:33.174048 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10932 22:13:33.191511 <30>[ 18.346860] systemd[1]: Created slice system-serial\x2dgetty.slice.
10933 22:13:33.201750 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10934 22:13:33.215745 <30>[ 18.371044] systemd[1]: Created slice User and Session Slice.
10935 22:13:33.222308 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10936 22:13:33.242397 <30>[ 18.394565] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10937 22:13:33.252239 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10938 22:13:33.270337 <30>[ 18.422590] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10939 22:13:33.277295 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10940 22:13:33.301263 <30>[ 18.450145] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10941 22:13:33.308046 <30>[ 18.462301] systemd[1]: Reached target Local Encrypted Volumes.
10942 22:13:33.314775 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10943 22:13:33.331276 <30>[ 18.486514] systemd[1]: Reached target Paths.
10944 22:13:33.334288 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10945 22:13:33.350534 <30>[ 18.506068] systemd[1]: Reached target Remote File Systems.
10946 22:13:33.357378 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10947 22:13:33.375435 <30>[ 18.530432] systemd[1]: Reached target Slices.
10948 22:13:33.381729 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10949 22:13:33.394667 <30>[ 18.550076] systemd[1]: Reached target Swap.
10950 22:13:33.397882 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10951 22:13:33.418393 <30>[ 18.570583] systemd[1]: Listening on initctl Compatibility Named Pipe.
10952 22:13:33.425377 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10953 22:13:33.431857 <30>[ 18.585959] systemd[1]: Listening on Journal Audit Socket.
10954 22:13:33.438386 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10955 22:13:33.451350 <30>[ 18.606604] systemd[1]: Listening on Journal Socket (/dev/log).
10956 22:13:33.457789 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10957 22:13:33.475875 <30>[ 18.631359] systemd[1]: Listening on Journal Socket.
10958 22:13:33.482248 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10959 22:13:33.495345 <30>[ 18.650688] systemd[1]: Listening on udev Control Socket.
10960 22:13:33.501822 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10961 22:13:33.519858 <30>[ 18.675137] systemd[1]: Listening on udev Kernel Socket.
10962 22:13:33.526494 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10963 22:13:33.567047 <30>[ 18.722130] systemd[1]: Mounting Huge Pages File System...
10964 22:13:33.573376 Mounting [0;1;39mHuge Pages File System[0m...
10965 22:13:33.591184 <30>[ 18.746448] systemd[1]: Mounting POSIX Message Queue File System...
10966 22:13:33.597882 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10967 22:13:33.619188 <30>[ 18.774641] systemd[1]: Mounting Kernel Debug File System...
10968 22:13:33.625725 Mounting [0;1;39mKernel Debug File System[0m...
10969 22:13:33.642233 <30>[ 18.794604] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10970 22:13:33.656081 <30>[ 18.808143] systemd[1]: Starting Create list of static device nodes for the current kernel...
10971 22:13:33.662958 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10972 22:13:33.683489 <30>[ 18.838895] systemd[1]: Starting Load Kernel Module configfs...
10973 22:13:33.690180 Starting [0;1;39mLoad Kernel Module configfs[0m...
10974 22:13:33.727149 <30>[ 18.882398] systemd[1]: Starting Load Kernel Module drm...
10975 22:13:33.733586 Starting [0;1;39mLoad Kernel Module drm[0m...
10976 22:13:33.750245 <30>[ 18.902110] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10977 22:13:33.765293 <30>[ 18.920691] systemd[1]: Starting Journal Service...
10978 22:13:33.768565 Starting [0;1;39mJournal Service[0m...
10979 22:13:33.789320 <30>[ 18.944633] systemd[1]: Starting Load Kernel Modules...
10980 22:13:33.795639 Starting [0;1;39mLoad Kernel Modules[0m...
10981 22:13:33.819568 <30>[ 18.971503] systemd[1]: Starting Remount Root and Kernel File Systems...
10982 22:13:33.825773 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10983 22:13:33.842539 <30>[ 18.998046] systemd[1]: Starting Coldplug All udev Devices...
10984 22:13:33.849349 Starting [0;1;39mColdplug All udev Devices[0m...
10985 22:13:33.867211 <30>[ 19.022798] systemd[1]: Started Journal Service.
10986 22:13:33.873668 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10987 22:13:33.891295 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10988 22:13:33.908400 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10989 22:13:33.923412 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10990 22:13:33.943239 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10991 22:13:33.960584 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10992 22:13:33.980478 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10993 22:13:33.997049 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10994 22:13:34.016769 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10995 22:13:34.030594 See 'systemctl status systemd-remount-fs.service' for details.
10996 22:13:34.082343 Mounting [0;1;39mKernel Configuration File System[0m...
10997 22:13:34.101326 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10998 22:13:34.116009 <46>[ 19.268422] systemd-journald[177]: Received client request to flush runtime journal.
10999 22:13:34.125567 Starting [0;1;39mLoad/Save Random Seed[0m...
11000 22:13:34.142669 Starting [0;1;39mApply Kernel Variables[0m...
11001 22:13:34.166750 Starting [0;1;39mCreate System Users[0m...
11002 22:13:34.186801 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11003 22:13:34.205613 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11004 22:13:34.228307 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11005 22:13:34.244689 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11006 22:13:34.261005 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11007 22:13:34.284887 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11008 22:13:34.331186 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11009 22:13:34.351061 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11010 22:13:34.363027 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11011 22:13:34.382589 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11012 22:13:34.427269 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11013 22:13:34.454656 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11014 22:13:34.479350 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11015 22:13:34.500114 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11016 22:13:34.543822 Starting [0;1;39mNetwork Time Synchronization[0m...
11017 22:13:34.564738 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11018 22:13:34.623850 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11019 22:13:34.644188 [[0;32m OK [<6>[ 19.796688] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11020 22:13:34.650282 0m] Started [0;1;39mNetwork Time Synchronization[0m.
11021 22:13:34.670612 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11022 22:13:34.676863 <6>[ 19.830922] remoteproc remoteproc0: scp is available
11023 22:13:34.680474 <6>[ 19.836493] remoteproc remoteproc0: powering up scp
11024 22:13:34.690292 <6>[ 19.841642] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11025 22:13:34.696909 <6>[ 19.847408] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11026 22:13:34.703369 <6>[ 19.850147] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11027 22:13:34.709993 <4>[ 19.854055] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11028 22:13:34.720084 <6>[ 19.857674] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11029 22:13:34.726741 <4>[ 19.861665] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11030 22:13:34.736504 <6>[ 19.886870] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11031 22:13:34.743294 <3>[ 19.890728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11032 22:13:34.753012 [[0;32m OK [<3>[ 19.904015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11033 22:13:34.759879 0m] Created slic<6>[ 19.904541] mc: Linux media interface: v0.10
11034 22:13:34.766649 e [0;1;39msyste<6>[ 19.905947] usbcore: registered new interface driver r8152
11035 22:13:34.776352 m-systemd\x2dbac<3>[ 19.913709] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11036 22:13:34.786247 klight.slice[0m<3>[ 19.936345] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11037 22:13:34.786447 .
11038 22:13:34.793157 <6>[ 19.937564] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11039 22:13:34.799523 <3>[ 19.945388] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11040 22:13:34.809372 <3>[ 19.945393] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11041 22:13:34.816408 <3>[ 19.945399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11042 22:13:34.826345 <3>[ 19.945402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11043 22:13:34.832786 <3>[ 19.945466] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11044 22:13:34.843215 <3>[ 19.945524] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11045 22:13:34.849503 <3>[ 19.945529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11046 22:13:34.859504 <3>[ 19.945537] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11047 22:13:34.866067 <3>[ 19.945591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11048 22:13:34.872491 <3>[ 19.945597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11049 22:13:34.882842 <3>[ 19.945600] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11050 22:13:34.889158 <3>[ 19.945603] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11051 22:13:34.899127 <3>[ 19.945606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11052 22:13:34.906189 <3>[ 19.945623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11053 22:13:34.915937 <6>[ 19.973963] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11054 22:13:34.926003 <6>[ 19.986539] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11055 22:13:34.932185 <6>[ 20.015150] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11056 22:13:34.938909 <6>[ 20.018419] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11057 22:13:34.949141 <6>[ 20.018487] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11058 22:13:34.955552 <6>[ 20.018497] remoteproc remoteproc0: remote processor scp is now up
11059 22:13:34.965298 <6>[ 20.022580] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11060 22:13:34.969067 <6>[ 20.026874] pci_bus 0000:00: root bus resource [bus 00-ff]
11061 22:13:34.978908 <6>[ 20.037010] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11062 22:13:34.982039 <6>[ 20.039637] videodev: Linux video capture interface: v2.00
11063 22:13:34.988805 <6>[ 20.043425] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11064 22:13:34.995289 <6>[ 20.046156] usbcore: registered new interface driver cdc_ether
11065 22:13:35.005264 <6>[ 20.056249] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11066 22:13:35.012288 <6>[ 20.060122] usbcore: registered new interface driver r8153_ecm
11067 22:13:35.019042 <6>[ 20.060213] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11068 22:13:35.026342 <6>[ 20.060277] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11069 22:13:35.033523 <6>[ 20.060296] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11070 22:13:35.040467 <6>[ 20.060397] pci 0000:00:00.0: supports D1 D2
11071 22:13:35.047250 <6>[ 20.060402] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11072 22:13:35.053240 <6>[ 20.061473] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11073 22:13:35.060065 <6>[ 20.061574] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11074 22:13:35.067580 <6>[ 20.061600] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11075 22:13:35.074858 <6>[ 20.061616] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11076 22:13:35.081154 <6>[ 20.061631] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11077 22:13:35.087930 <6>[ 20.062280] pci 0000:01:00.0: supports D1 D2
11078 22:13:35.094977 <6>[ 20.062284] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11079 22:13:35.098107 <6>[ 20.068375] Bluetooth: Core ver 2.22
11080 22:13:35.105413 <6>[ 20.071111] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11081 22:13:35.115292 <4>[ 20.073142] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11082 22:13:35.122051 <4>[ 20.073154] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11083 22:13:35.131848 <6>[ 20.077989] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11084 22:13:35.135048 <6>[ 20.087163] NET: Registered PF_BLUETOOTH protocol family
11085 22:13:35.145297 <6>[ 20.093996] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11086 22:13:35.151579 <6>[ 20.101001] Bluetooth: HCI device and connection manager initialized
11087 22:13:35.158979 <6>[ 20.102233] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11088 22:13:35.169525 <6>[ 20.103524] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11089 22:13:35.175613 <6>[ 20.103726] usbcore: registered new interface driver uvcvideo
11090 22:13:35.182585 <6>[ 20.110236] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11091 22:13:35.189130 <6>[ 20.115968] Bluetooth: HCI socket layer initialized
11092 22:13:35.195467 <6>[ 20.125008] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11093 22:13:35.202487 <6>[ 20.129921] r8152 2-1.3:1.0 eth0: v1.12.13
11094 22:13:35.206246 <6>[ 20.130723] Bluetooth: L2CAP socket layer initialized
11095 22:13:35.216108 <6>[ 20.137854] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11096 22:13:35.219543 <6>[ 20.141470] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11097 22:13:35.226173 <6>[ 20.143591] Bluetooth: SCO socket layer initialized
11098 22:13:35.232751 <6>[ 20.144256] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11099 22:13:35.242753 <4>[ 20.144423] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11100 22:13:35.246078 <4>[ 20.144423] Fallback method does not support PEC.
11101 22:13:35.252897 <6>[ 20.150708] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11102 22:13:35.262883 <3>[ 20.187776] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11103 22:13:35.273829 <3>[ 20.190241] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11104 22:13:35.280321 <3>[ 20.192912] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11105 22:13:35.286717 <6>[ 20.194833] pci 0000:00:00.0: PCI bridge to [bus 01]
11106 22:13:35.293741 <6>[ 20.194840] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11107 22:13:35.300742 <6>[ 20.195094] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11108 22:13:35.307746 <6>[ 20.199889] usbcore: registered new interface driver btusb
11109 22:13:35.317608 <4>[ 20.200629] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11110 22:13:35.323942 <3>[ 20.200643] Bluetooth: hci0: Failed to load firmware file (-2)
11111 22:13:35.327200 <3>[ 20.200650] Bluetooth: hci0: Failed to set up firmware (-2)
11112 22:13:35.340469 <4>[ 20.200656] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11113 22:13:35.343839 <6>[ 20.206701] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11114 22:13:35.354798 <3>[ 20.232269] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11115 22:13:35.361329 <3>[ 20.232977] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11116 22:13:35.368511 <6>[ 20.236015] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11117 22:13:35.378814 <3>[ 20.264835] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11118 22:13:35.385530 <5>[ 20.295051] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11119 22:13:35.392426 <3>[ 20.319420] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11120 22:13:35.399195 <5>[ 20.342667] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11121 22:13:35.409275 <3>[ 20.368448] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11122 22:13:35.420035 <4>[ 20.375577] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11123 22:13:35.426790 <3>[ 20.432821] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11124 22:13:35.433511 <6>[ 20.441311] cfg80211: failed to load regulatory.db
11125 22:13:35.440135 <3>[ 20.467315] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11126 22:13:35.450007 <6>[ 20.487803] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11127 22:13:35.453146 <6>[ 20.609170] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11128 22:13:35.459788 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11129 22:13:35.482397 [[0;32m OK [0m] Reached targ<6>[ 20.635877] mt7921e 0000:01:00.0: ASIC revision: 79610010
11130 22:13:35.485455 et [0;1;39mSystem Time Synchronized[0m.
11131 22:13:35.555378 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11132 22:13:35.589580 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_ba<4>[ 20.738438] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11133 22:13:35.589791 cklight[0m.
11134 22:13:35.706972 <4>[ 20.855905] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11135 22:13:35.744744 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11136 22:13:35.758934 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11137 22:13:35.778291 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11138 22:13:35.793992 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11139 22:13:35.822668 [[0;32m OK [0m] Reached target [0;1;39mTime<4>[ 20.972443] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11140 22:13:35.822823 rs[0m.
11141 22:13:35.843987 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11142 22:13:35.858753 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11143 22:13:35.878909 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11144 22:13:35.898759 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11145 22:13:35.943269 <4>[ 21.091946] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11146 22:13:35.953558 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11147 22:13:35.997264 Starting [0;1;39mUser Login Management[0m...
11148 22:13:36.016183 Starting [0;1;39mPermit User Sessions[0m...
11149 22:13:36.034990 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11150 22:13:36.055948 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11151 22:13:36.069326 <4>[ 21.217320] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11152 22:13:36.084921 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11153 22:13:36.106602 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11154 22:13:36.131682 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11155 22:13:36.148247 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11156 22:13:36.164133 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11157 22:13:36.188593 [[0;32m OK [0m] Reached target [0;1;39mMult<4>[ 21.337441] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11158 22:13:36.191522 i-User System[0m.
11159 22:13:36.208761 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11160 22:13:36.267908 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11161 22:13:36.308617 <4>[ 21.457617] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11162 22:13:36.315501 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11163 22:13:36.335233
11164 22:13:36.335388
11165 22:13:36.338394 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11166 22:13:36.338482
11167 22:13:36.341464 debian-bullseye-arm64 login: root (automatic login)
11168 22:13:36.341549
11169 22:13:36.341651
11170 22:13:36.370324 Linux debian-bullseye-arm64 6.1.46-cip4 #1 SMP PREEMPT Tue Sep 5 21:54:53 UTC 2023 aarch64
11171 22:13:36.370475
11172 22:13:36.376495 The programs included with the Debian GNU/Linux system are free software;
11173 22:13:36.383499 the exact distribution terms for each program are described in the
11174 22:13:36.386479 individual files in /usr/share/doc/*/copyright.
11175 22:13:36.386574
11176 22:13:36.393603 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11177 22:13:36.396648 permitted by applicable law.
11178 22:13:36.397000 Matched prompt #10: / #
11180 22:13:36.397208 Setting prompt string to ['/ #']
11181 22:13:36.397300 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11183 22:13:36.397491 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11184 22:13:36.397579 start: 2.2.6 expect-shell-connection (timeout 00:02:57) [common]
11185 22:13:36.397652 Setting prompt string to ['/ #']
11186 22:13:36.397773 Forcing a shell prompt, looking for ['/ #']
11188 22:13:36.448056 / #
11189 22:13:36.448245 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11190 22:13:36.448330 Waiting using forced prompt support (timeout 00:02:30)
11191 22:13:36.448437 <4>[ 21.576747] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11192 22:13:36.453437
11193 22:13:36.453732 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11194 22:13:36.453828 start: 2.2.7 export-device-env (timeout 00:02:57) [common]
11195 22:13:36.453929 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11196 22:13:36.454022 end: 2.2 depthcharge-retry (duration 00:02:03) [common]
11197 22:13:36.454113 end: 2 depthcharge-action (duration 00:02:03) [common]
11198 22:13:36.454200 start: 3 lava-test-retry (timeout 00:05:00) [common]
11199 22:13:36.454286 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11200 22:13:36.454361 Using namespace: common
11202 22:13:36.554740 / # #
11203 22:13:36.554929 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11204 22:13:36.555053 #<4>[ 21.700589] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11205 22:13:36.560439
11206 22:13:36.604018 Using /lava-11440293
11208 22:13:36.704480 / # export SHELL=/bin/sh
11209 22:13:36.704707 export SHELL=/bin/sh<4>[ 21.820562] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11210 22:13:36.709452
11212 22:13:36.810044 / # . /lava-11440293/environment
11213 22:13:36.810278 . /lava-11440293/environment<3>[ 21.937892] mt7921e 0000:01:00.0: hardware init failed
11214 22:13:36.815562
11216 22:13:36.916201 / # /lava-11440293/bin/lava-test-runner /lava-11440293/0
11217 22:13:36.916388 Test shell timeout: 10s (minimum of the action and connection timeout)
11218 22:13:36.921776 /lava-11440293/bin/lava-test-runner /lava-11440293/0
11219 22:13:36.941888 + export TESTRUN_ID=0_sleep
11220 22:13:36.945474 + cd /lava-11440293/0/tests/0_sleep
11221 22:13:36.948585 + cat uuid
11222 22:13:36.948678 + UUID=11440293_1.5.2.3.1
11223 22:13:36.951759 + set +x
11224 22:13:36.955232 <LAVA_SIGNAL_STARTRUN 0_sleep 11440293_1.5.2.3.1>
11225 22:13:36.955504 Received signal: <STARTRUN> 0_sleep 11440293_1.5.2.3.1
11226 22:13:36.955583 Starting test lava.0_sleep (11440293_1.5.2.3.1)
11227 22:13:36.955710 Skipping test definition patterns.
11228 22:13:36.958539 + ./config/lava/sleep/sleep.sh mem freeze
11229 22:13:36.962211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11230 22:13:36.962474 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11232 22:13:36.968729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11233 22:13:36.968999 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11235 22:13:36.972523 rtcwake: assuming RTC uses UTC ...
11236 22:13:36.982048 rtcwake: wakeup from "mem" using rtc0 at Tue Sep 5 22:12:36 2<6>[ 22.137580] PM: suspend entry (deep)
11237 22:13:36.982174 023
11238 22:13:36.985312 <6>[ 22.142733] Filesystems sync: 0.000 seconds
11239 22:13:36.993057 <6>[ 22.148957] Freezing user space processes
11240 22:13:37.002887 <6>[ 22.155114] Freezing user space processes completed (elapsed 0.001 seconds)
11241 22:13:37.006608 <6>[ 22.162366] OOM killer disabled.
11242 22:13:37.009580 <6>[ 22.165852] Freezing remaining freezable tasks
11243 22:13:37.019712 <6>[ 22.171859] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11244 22:13:37.026304 <6>[ 22.179551] printk: Suspending console(s) (use no_console_suspend to debug)
11245 22:13:40.492323 <3>[ 25.422058] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11246 22:13:40.501582 <3>[ 25.422090] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11247 22:13:40.512209 <3>[ 25.422139] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11248 22:13:40.518536 <3>[ 25.422184] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11249 22:13:40.528198 <3>[ 25.422542] PM: Some devices failed to suspend, or early wake event detected
11250 22:13:40.534968 <4>[ 25.438867] typec port0-partner: PM: parent port0 should not be sleeping
11251 22:13:40.538522 <6>[ 25.695049] OOM killer enabled.
11252 22:13:40.541696 <6>[ 25.698462] Restarting tasks ... done.
11253 22:13:40.548356 <5>[ 25.704732] random: crng reseeded on system resumption
11254 22:13:40.552042 <6>[ 25.711613] PM: suspend exit
11255 22:13:40.555181 rtcwake: write error
11256 22:13:40.562585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11257 22:13:40.562898 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11259 22:13:40.565975 rtcwake: assuming RTC uses UTC ...
11260 22:13:40.572687 rtcwake: wakeup from "mem" using rtc0 at Tue Sep 5 22:12:40 2023
11261 22:13:40.585154 <6>[ 25.741270] PM: suspend entry (deep)
11262 22:13:40.588590 <6>[ 25.745154] Filesystems sync: 0.000 seconds
11263 22:13:40.591498 <6>[ 25.750240] Freezing user space processes
11264 22:13:40.603192 <6>[ 25.756193] Freezing user space processes completed (elapsed 0.001 seconds)
11265 22:13:40.606504 <6>[ 25.763428] OOM killer disabled.
11266 22:13:40.609869 <6>[ 25.766907] Freezing remaining freezable tasks
11267 22:13:40.620246 <6>[ 25.772929] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11268 22:13:40.626539 <6>[ 25.780601] printk: Suspending console(s) (use no_console_suspend to debug)
11269 22:13:44.075877 <3>[ 29.006102] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11270 22:13:44.085585 <3>[ 29.006135] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11271 22:13:44.096156 <3>[ 29.006184] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11272 22:13:44.102839 <3>[ 29.006232] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11273 22:13:44.109158 <3>[ 29.006579] PM: Some devices failed to suspend, or early wake event detected
11274 22:13:44.112268 <6>[ 29.272081] OOM killer enabled.
11275 22:13:44.121061 <6>[ 29.275495] Restarting tasks ... done.
11276 22:13:44.124297 <5>[ 29.281795] random: crng reseeded on system resumption
11277 22:13:44.128968 <6>[ 29.288992] PM: suspend exit
11278 22:13:44.132339 rtcwake: write error
11279 22:13:44.139777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11280 22:13:44.140094 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11282 22:13:44.143053 rtcwake: assuming RTC uses UTC ...
11283 22:13:44.149618 rtcwake: wakeup from "mem" using rtc0 at Tue Sep 5 22:12:43 2023
11284 22:13:44.164089 <6>[ 29.320836] PM: suspend entry (deep)
11285 22:13:44.167515 <6>[ 29.324780] Filesystems sync: 0.000 seconds
11286 22:13:44.174319 <6>[ 29.330116] Freezing user space processes
11287 22:13:44.181017 <6>[ 29.336221] Freezing user space processes completed (elapsed 0.001 seconds)
11288 22:13:44.184119 <6>[ 29.343527] OOM killer disabled.
11289 22:13:44.190972 <6>[ 29.347026] Freezing remaining freezable tasks
11290 22:13:44.197458 <6>[ 29.352956] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11291 22:13:44.207792 <6>[ 29.360615] printk: Suspending console(s) (use no_console_suspend to debug)
11292 22:13:47.658154 <3>[ 32.589931] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11293 22:13:47.668188 <3>[ 32.589961] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11294 22:13:47.678510 <3>[ 32.589992] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11295 22:13:47.685050 <3>[ 32.590019] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11296 22:13:47.691868 <3>[ 32.590216] PM: Some devices failed to suspend, or early wake event detected
11297 22:13:47.694872 <6>[ 32.855182] OOM killer enabled.
11298 22:13:47.708208 <6>[ 32.858597] Restarting tasks ... done.
11299 22:13:47.711521 <5>[ 32.869443] random: crng reseeded on system resumption
11300 22:13:47.715700 <6>[ 32.876191] PM: suspend exit
11301 22:13:47.719306 rtcwake: write error
11302 22:13:47.726079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11303 22:13:47.726369 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11305 22:13:47.729874 rtcwake: assuming RTC uses UTC ...
11306 22:13:47.736403 rtcwake: wakeup from "mem" using rtc0 at Tue Sep 5 22:12:47 2023
11307 22:13:47.749906 <6>[ 32.906737] PM: suspend entry (deep)
11308 22:13:47.753193 <6>[ 32.910651] Filesystems sync: 0.000 seconds
11309 22:13:47.756686 <6>[ 32.915764] Freezing user space processes
11310 22:13:47.768299 <6>[ 32.921888] Freezing user space processes completed (elapsed 0.001 seconds)
11311 22:13:47.771492 <6>[ 32.929118] OOM killer disabled.
11312 22:13:47.775065 <6>[ 32.932606] Freezing remaining freezable tasks
11313 22:13:47.784894 <6>[ 32.938546] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11314 22:13:47.791406 <6>[ 32.946215] printk: Suspending console(s) (use no_console_suspend to debug)
11315 22:13:51.250153 <3>[ 36.174022] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11316 22:13:51.260409 <3>[ 36.174046] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11317 22:13:51.270385 <3>[ 36.174075] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11318 22:13:51.277471 <3>[ 36.174103] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11319 22:13:51.283917 <3>[ 36.174322] PM: Some devices failed to suspend, or early wake event detected
11320 22:13:51.287149 <6>[ 36.447653] OOM killer enabled.
11321 22:13:51.296020 <6>[ 36.451067] Restarting tasks ... done.
11322 22:13:51.299030 <5>[ 36.457307] random: crng reseeded on system resumption
11323 22:13:51.303356 <6>[ 36.464189] PM: suspend exit
11324 22:13:51.306510 rtcwake: write error
11325 22:13:51.313790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11326 22:13:51.314085 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11328 22:13:51.317079 rtcwake: assuming RTC uses UTC ...
11329 22:13:51.323797 rtcwake: wakeup from "mem" using rtc0 at Tue Sep 5 22:12:50 2023
11330 22:13:51.336202 <6>[ 36.493819] PM: suspend entry (deep)
11331 22:13:51.339987 <6>[ 36.497691] Filesystems sync: 0.000 seconds
11332 22:13:51.343204 <6>[ 36.502705] Freezing user space processes
11333 22:13:51.354619 <6>[ 36.508695] Freezing user space processes completed (elapsed 0.001 seconds)
11334 22:13:51.358225 <6>[ 36.515966] OOM killer disabled.
11335 22:13:51.360988 <6>[ 36.519450] Freezing remaining freezable tasks
11336 22:13:51.371270 <6>[ 36.525488] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11337 22:13:51.377871 <6>[ 36.533164] printk: Suspending console(s) (use no_console_suspend to debug)
11338 22:13:54.834541 <3>[ 39.758169] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11339 22:13:54.844752 <3>[ 39.758203] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11340 22:13:54.854475 <3>[ 39.758250] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11341 22:13:54.861366 <3>[ 39.758295] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11342 22:13:54.871086 <3>[ 39.758537] PM: Some devices failed to suspend, or early wake event detected
11343 22:13:54.874311 <6>[ 40.032344] OOM killer enabled.
11344 22:13:54.883166 <6>[ 40.035757] Restarting tasks ... done.
11345 22:13:54.886456 <5>[ 40.044864] random: crng reseeded on system resumption
11346 22:13:54.890728 <6>[ 40.051711] PM: suspend exit
11347 22:13:54.894047 rtcwake: write error
11348 22:13:54.900829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11349 22:13:54.901094 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11351 22:13:54.904175 rtcwake: assuming RTC uses UTC ...
11352 22:13:54.910736 rtcwake: wakeup from "mem" using rtc0 at Tue Sep 5 22:12:54 2023
11353 22:13:54.923249 <6>[ 40.081206] PM: suspend entry (deep)
11354 22:13:54.926853 <6>[ 40.085098] Filesystems sync: 0.000 seconds
11355 22:13:54.930361 <6>[ 40.090193] Freezing user space processes
11356 22:13:54.941669 <6>[ 40.096280] Freezing user space processes completed (elapsed 0.001 seconds)
11357 22:13:54.945032 <6>[ 40.103515] OOM killer disabled.
11358 22:13:54.948376 <6>[ 40.106999] Freezing remaining freezable tasks
11359 22:13:54.958482 <6>[ 40.113063] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11360 22:13:54.965360 <6>[ 40.120740] printk: Suspending console(s) (use no_console_suspend to debug)
11361 22:13:58.417685 <3>[ 43.342090] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11362 22:13:58.427853 <3>[ 43.342122] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11363 22:13:58.437563 <3>[ 43.342171] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11364 22:13:58.444413 <3>[ 43.342215] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11365 22:13:58.454607 <3>[ 43.342521] PM: Some devices failed to suspend, or early wake event detected
11366 22:13:58.457906 <6>[ 43.615971] OOM killer enabled.
11367 22:13:58.461149 <6>[ 43.619384] Restarting tasks ... done.
11368 22:13:58.467474 <5>[ 43.625754] random: crng reseeded on system resumption
11369 22:13:58.471058 <6>[ 43.632528] PM: suspend exit
11370 22:13:58.474229 rtcwake: write error
11371 22:13:58.481701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11372 22:13:58.481965 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11374 22:13:58.484982 rtcwake: assuming RTC uses UTC ...
11375 22:13:58.491332 rtcwake: wakeup from "mem" using rtc0 at Tue Sep 5 22:12:58 2023
11376 22:13:58.503858 <6>[ 43.661956] PM: suspend entry (deep)
11377 22:13:58.506991 <6>[ 43.665910] Filesystems sync: 0.000 seconds
11378 22:13:58.510780 <6>[ 43.670927] Freezing user space processes
11379 22:13:58.522038 <6>[ 43.676908] Freezing user space processes completed (elapsed 0.001 seconds)
11380 22:13:58.525776 <6>[ 43.684135] OOM killer disabled.
11381 22:13:58.528770 <6>[ 43.687615] Freezing remaining freezable tasks
11382 22:13:58.538609 <6>[ 43.693633] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11383 22:13:58.545563 <6>[ 43.701306] printk: Suspending console(s) (use no_console_suspend to debug)
11384 22:14:02.001186 <3>[ 46.926099] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11385 22:14:02.011119 <3>[ 46.926138] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11386 22:14:02.021485 <3>[ 46.926191] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11387 22:14:02.027798 <3>[ 46.926236] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11388 22:14:02.034885 <3>[ 46.926480] PM: Some devices failed to suspend, or early wake event detected
11389 22:14:02.041364 <6>[ 47.200073] OOM killer enabled.
11390 22:14:02.051817 <6>[ 47.203485] Restarting tasks ... done.
11391 22:14:02.055265 <5>[ 47.214400] random: crng reseeded on system resumption
11392 22:14:02.058944 <6>[ 47.221065] PM: suspend exit
11393 22:14:02.062193 rtcwake: write error
11394 22:14:02.069484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11395 22:14:02.069772 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11397 22:14:02.073288 rtcwake: assuming RTC uses UTC ...
11398 22:14:02.079556 rtcwake: wakeup from "mem" using rtc0 at Tue Sep 5 22:13:01 2023
11399 22:14:02.092499 <6>[ 47.250804] PM: suspend entry (deep)
11400 22:14:02.095442 <6>[ 47.254692] Filesystems sync: 0.000 seconds
11401 22:14:02.098622 <6>[ 47.259678] Freezing user space processes
11402 22:14:02.110099 <6>[ 47.265680] Freezing user space processes completed (elapsed 0.001 seconds)
11403 22:14:02.113904 <6>[ 47.272914] OOM killer disabled.
11404 22:14:02.117036 <6>[ 47.276395] Freezing remaining freezable tasks
11405 22:14:02.127110 <6>[ 47.282377] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11406 22:14:02.133657 <6>[ 47.290035] printk: Suspending console(s) (use no_console_suspend to debug)
11407 22:14:05.582076 <6>[ 48.206225] vpu: disabling
11408 22:14:05.585195 <6>[ 48.206402] vproc2: disabling
11409 22:14:05.588634 <6>[ 48.206461] vproc1: disabling
11410 22:14:05.591809 <6>[ 48.206519] vaud18: disabling
11411 22:14:05.595413 <6>[ 48.206782] vsram_others: disabling
11412 22:14:05.598712 <6>[ 48.206991] va09: disabling
11413 22:14:05.601947 <6>[ 48.207074] vsram_md: disabling
11414 22:14:05.605184 <6>[ 48.207209] Vgpu: disabling
11415 22:14:05.611866 <3>[ 50.510103] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11416 22:14:05.621873 <3>[ 50.510146] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11417 22:14:05.631812 <3>[ 50.510205] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11418 22:14:05.638413 <3>[ 50.510252] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11419 22:14:05.645332 <3>[ 50.510599] PM: Some devices failed to suspend, or early wake event detected
11420 22:14:05.648535 <6>[ 50.810218] OOM killer enabled.
11421 22:14:05.659416 <6>[ 50.813619] Restarting tasks ... done.
11422 22:14:05.665981 <5>[ 50.823128] random: crng reseeded on system resumption
11423 22:14:05.669271 <6>[ 50.830307] PM: suspend exit
11424 22:14:05.672613 rtcwake: write error
11425 22:14:05.679314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11426 22:14:05.679634 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11428 22:14:05.682605 rtcwake: assuming RTC uses UTC ...
11429 22:14:05.685833 rtcwake: wakeup from "mem" using rtc0 at Tue Sep 5 22:13:05 2023
11430 22:14:05.700534 <6>[ 50.859561] PM: suspend entry (deep)
11431 22:14:05.704036 <6>[ 50.863472] Filesystems sync: 0.000 seconds
11432 22:14:05.707466 <6>[ 50.868498] Freezing user space processes
11433 22:14:05.718977 <6>[ 50.874358] Freezing user space processes completed (elapsed 0.001 seconds)
11434 22:14:05.721988 <6>[ 50.881579] OOM killer disabled.
11435 22:14:05.725076 <6>[ 50.885061] Freezing remaining freezable tasks
11436 22:14:05.735603 <6>[ 50.891165] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11437 22:14:05.741927 <6>[ 50.898836] printk: Suspending console(s) (use no_console_suspend to debug)
11438 22:14:09.169012 <3>[ 54.094115] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11439 22:14:09.178831 <3>[ 54.094147] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11440 22:14:09.189282 <3>[ 54.094195] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11441 22:14:09.195778 <3>[ 54.094239] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11442 22:14:09.202212 <3>[ 54.094546] PM: Some devices failed to suspend, or early wake event detected
11443 22:14:09.205503 <6>[ 54.368347] OOM killer enabled.
11444 22:14:09.217842 <6>[ 54.371767] Restarting tasks ... done.
11445 22:14:09.220918 <5>[ 54.381005] random: crng reseeded on system resumption
11446 22:14:09.224880 <6>[ 54.387754] PM: suspend exit
11447 22:14:09.228074 rtcwake: write error
11448 22:14:09.235103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11449 22:14:09.235382 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11451 22:14:09.238343 rtcwake: assuming RTC uses UTC ...
11452 22:14:09.245348 rtcwake: wakeup from "mem" using rtc0 at Tue Sep 5 22:13:08 2023
11453 22:14:09.257386 <6>[ 54.417145] PM: suspend entry (deep)
11454 22:14:09.260871 <6>[ 54.421060] Filesystems sync: 0.000 seconds
11455 22:14:09.264791 <6>[ 54.426219] Freezing user space processes
11456 22:14:09.276111 <6>[ 54.432249] Freezing user space processes completed (elapsed 0.001 seconds)
11457 22:14:09.279270 <6>[ 54.439485] OOM killer disabled.
11458 22:14:09.282552 <6>[ 54.442966] Freezing remaining freezable tasks
11459 22:14:09.292599 <6>[ 54.449047] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11460 22:14:09.299269 <6>[ 54.456722] printk: Suspending console(s) (use no_console_suspend to debug)
11461 22:14:12.752450 <3>[ 57.678061] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11462 22:14:12.762487 <3>[ 57.678095] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11463 22:14:12.772951 <3>[ 57.678143] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11464 22:14:12.779246 <3>[ 57.678187] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11465 22:14:12.786132 <3>[ 57.678444] PM: Some devices failed to suspend, or early wake event detected
11466 22:14:12.789396 <6>[ 57.952350] OOM killer enabled.
11467 22:14:12.801146 <6>[ 57.955764] Restarting tasks ... done.
11468 22:14:12.804477 <5>[ 57.964846] random: crng reseeded on system resumption
11469 22:14:12.808753 <6>[ 57.972102] PM: suspend exit
11470 22:14:12.812113 rtcwake: write error
11471 22:14:12.819116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11472 22:14:12.819377 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11474 22:14:12.823237 rtcwake: assuming RTC uses UTC ...
11475 22:14:12.829172 rtcwake: wakeup from "freeze" using rtc0 at Tue Sep 5 22:13:12 2023
11476 22:14:12.842906 <6>[ 58.002698] PM: suspend entry (s2idle)
11477 22:14:12.846462 <6>[ 58.006764] Filesystems sync: 0.000 seconds
11478 22:14:12.849862 <6>[ 58.011815] Freezing user space processes
11479 22:14:12.861216 <6>[ 58.017711] Freezing user space processes completed (elapsed 0.001 seconds)
11480 22:14:12.864522 <6>[ 58.024929] OOM killer disabled.
11481 22:14:12.867962 <6>[ 58.028408] Freezing remaining freezable tasks
11482 22:14:12.877892 <6>[ 58.034395] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11483 22:14:12.884788 <6>[ 58.042045] printk: Suspending console(s) (use no_console_suspend to debug)
11484 22:14:16.336021 <3>[ 61.262106] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11485 22:14:16.346314 <3>[ 61.262138] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11486 22:14:16.356177 <3>[ 61.262187] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11487 22:14:16.362412 <3>[ 61.262231] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11488 22:14:16.369296 <3>[ 61.262541] PM: Some devices failed to suspend, or early wake event detected
11489 22:14:16.375576 <6>[ 61.536241] OOM killer enabled.
11490 22:14:16.384356 <6>[ 61.539661] Restarting tasks ... done.
11491 22:14:16.387739 <5>[ 61.548719] random: crng reseeded on system resumption
11492 22:14:16.391541 <6>[ 61.555464] PM: suspend exit
11493 22:14:16.395295 rtcwake: write error
11494 22:14:16.402070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11495 22:14:16.402398 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11497 22:14:16.405298 rtcwake: assuming RTC uses UTC ...
11498 22:14:16.412091 rtcwake: wakeup from "freeze" using rtc0 at Tue Sep 5 22:13:15 2023
11499 22:14:16.424895 <6>[ 61.585042] PM: suspend entry (s2idle)
11500 22:14:16.427922 <6>[ 61.589116] Filesystems sync: 0.000 seconds
11501 22:14:16.431750 <6>[ 61.594218] Freezing user space processes
11502 22:14:16.443064 <6>[ 61.600239] Freezing user space processes completed (elapsed 0.001 seconds)
11503 22:14:16.446455 <6>[ 61.607471] OOM killer disabled.
11504 22:14:16.449607 <6>[ 61.610952] Freezing remaining freezable tasks
11505 22:14:16.460057 <6>[ 61.617004] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11506 22:14:16.466555 <6>[ 61.624673] printk: Suspending console(s) (use no_console_suspend to debug)
11507 22:14:19.919647 <3>[ 64.846057] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11508 22:14:19.929522 <3>[ 64.846090] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11509 22:14:19.939499 <3>[ 64.846139] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11510 22:14:19.946015 <3>[ 64.846187] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11511 22:14:19.952976 <3>[ 64.846452] PM: Some devices failed to suspend, or early wake event detected
11512 22:14:19.956319 <6>[ 65.120245] OOM killer enabled.
11513 22:14:19.968416 <6>[ 65.123658] Restarting tasks ... done.
11514 22:14:19.971953 <5>[ 65.133190] random: crng reseeded on system resumption
11515 22:14:19.976718 <6>[ 65.140557] PM: suspend exit
11516 22:14:19.980083 rtcwake: write error
11517 22:14:19.986816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11518 22:14:19.987080 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11520 22:14:19.990470 rtcwake: assuming RTC uses UTC ...
11521 22:14:19.997209 rtcwake: wakeup from "freeze" using rtc0 at Tue Sep 5 22:13:19 2023
11522 22:14:20.009229 <6>[ 65.170122] PM: suspend entry (s2idle)
11523 22:14:20.013156 <6>[ 65.174177] Filesystems sync: 0.000 seconds
11524 22:14:20.016521 <6>[ 65.179166] Freezing user space processes
11525 22:14:20.027479 <6>[ 65.185175] Freezing user space processes completed (elapsed 0.001 seconds)
11526 22:14:20.030877 <6>[ 65.192410] OOM killer disabled.
11527 22:14:20.034327 <6>[ 65.195893] Freezing remaining freezable tasks
11528 22:14:20.044597 <6>[ 65.201981] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11529 22:14:20.050953 <6>[ 65.209647] printk: Suspending console(s) (use no_console_suspend to debug)
11530 22:14:23.503214 <3>[ 68.430064] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11531 22:14:23.513348 <3>[ 68.430097] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11532 22:14:23.523736 <3>[ 68.430145] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11533 22:14:23.530011 <3>[ 68.430191] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11534 22:14:23.536943 <3>[ 68.430506] PM: Some devices failed to suspend, or early wake event detected
11535 22:14:23.539828 <6>[ 68.704258] OOM killer enabled.
11536 22:14:23.551822 <6>[ 68.707678] Restarting tasks ... done.
11537 22:14:23.554663 <5>[ 68.716780] random: crng reseeded on system resumption
11538 22:14:23.559030 <6>[ 68.723514] PM: suspend exit
11539 22:14:23.562355 rtcwake: write error
11540 22:14:23.569736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11541 22:14:23.569998 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11543 22:14:23.573192 rtcwake: assuming RTC uses UTC ...
11544 22:14:23.579581 rtcwake: wakeup from "freeze" using rtc0 at Tue Sep 5 22:13:23 2023
11545 22:14:23.592046 <6>[ 68.753465] PM: suspend entry (s2idle)
11546 22:14:23.595547 <6>[ 68.757530] Filesystems sync: 0.000 seconds
11547 22:14:23.602489 <6>[ 68.762531] Freezing user space processes
11548 22:14:23.608827 <6>[ 68.768519] Freezing user space processes completed (elapsed 0.001 seconds)
11549 22:14:23.612346 <6>[ 68.775750] OOM killer disabled.
11550 22:14:23.618885 <6>[ 68.779232] Freezing remaining freezable tasks
11551 22:14:23.625432 <6>[ 68.785279] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11552 22:14:23.635510 <6>[ 68.792950] printk: Suspending console(s) (use no_console_suspend to debug)
11553 22:14:27.087247 <3>[ 72.014099] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11554 22:14:27.096658 <3>[ 72.014137] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11555 22:14:27.106587 <3>[ 72.014196] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11556 22:14:27.113570 <3>[ 72.014248] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11557 22:14:27.120381 <3>[ 72.014548] PM: Some devices failed to suspend, or early wake event detected
11558 22:14:27.123333 <6>[ 72.288244] OOM killer enabled.
11559 22:14:27.134809 <6>[ 72.291657] Restarting tasks ... done.
11560 22:14:27.138238 <5>[ 72.300471] random: crng reseeded on system resumption
11561 22:14:27.142478 <6>[ 72.307563] PM: suspend exit
11562 22:14:27.145666 rtcwake: write error
11563 22:14:27.153474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11564 22:14:27.153731 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11566 22:14:27.156594 rtcwake: assuming RTC uses UTC ...
11567 22:14:27.163211 rtcwake: wakeup from "freeze" using rtc0 at Tue Sep 5 22:13:26 2023
11568 22:14:27.175984 <6>[ 72.337352] PM: suspend entry (s2idle)
11569 22:14:27.179258 <6>[ 72.341419] Filesystems sync: 0.000 seconds
11570 22:14:27.182944 <6>[ 72.346449] Freezing user space processes
11571 22:14:27.194102 <6>[ 72.352349] Freezing user space processes completed (elapsed 0.001 seconds)
11572 22:14:27.197581 <6>[ 72.359577] OOM killer disabled.
11573 22:14:27.200869 <6>[ 72.363060] Freezing remaining freezable tasks
11574 22:14:27.210820 <6>[ 72.369173] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11575 22:14:27.217433 <6>[ 72.376854] printk: Suspending console(s) (use no_console_suspend to debug)
11576 22:14:30.670343 <3>[ 75.598031] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11577 22:14:30.680360 <3>[ 75.598062] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11578 22:14:30.690646 <3>[ 75.598110] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11579 22:14:30.697230 <3>[ 75.598158] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11580 22:14:30.703993 <3>[ 75.598428] PM: Some devices failed to suspend, or early wake event detected
11581 22:14:30.707278 <6>[ 75.872241] OOM killer enabled.
11582 22:14:30.716092 <6>[ 75.875655] Restarting tasks ... done.
11583 22:14:30.722538 <5>[ 75.883585] random: crng reseeded on system resumption
11584 22:14:30.725676 <6>[ 75.890329] PM: suspend exit
11585 22:14:30.729200 rtcwake: write error
11586 22:14:30.735718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11587 22:14:30.735982 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11589 22:14:30.739083 rtcwake: assuming RTC uses UTC ...
11590 22:14:30.746071 rtcwake: wakeup from "freeze" using rtc0 at Tue Sep 5 22:13:30 2023
11591 22:14:30.757637 <6>[ 75.919830] PM: suspend entry (s2idle)
11592 22:14:30.761432 <6>[ 75.923916] Filesystems sync: 0.000 seconds
11593 22:14:30.767629 <6>[ 75.928916] Freezing user space processes
11594 22:14:30.774562 <6>[ 75.934717] Freezing user space processes completed (elapsed 0.001 seconds)
11595 22:14:30.777894 <6>[ 75.941935] OOM killer disabled.
11596 22:14:30.784641 <6>[ 75.945412] Freezing remaining freezable tasks
11597 22:14:30.791343 <6>[ 75.951431] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11598 22:14:30.797749 <6>[ 75.959111] printk: Suspending console(s) (use no_console_suspend to debug)
11599 22:14:34.253631 <3>[ 79.182072] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11600 22:14:34.264319 <3>[ 79.182104] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11601 22:14:34.273723 <3>[ 79.182153] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11602 22:14:34.280731 <3>[ 79.182197] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11603 22:14:34.287563 <3>[ 79.182498] PM: Some devices failed to suspend, or early wake event detected
11604 22:14:34.290695 <6>[ 79.456031] OOM killer enabled.
11605 22:14:34.298762 <6>[ 79.459452] Restarting tasks ... done.
11606 22:14:34.305820 <5>[ 79.467033] random: crng reseeded on system resumption
11607 22:14:34.308836 <6>[ 79.473689] PM: suspend exit
11608 22:14:34.312417 rtcwake: write error
11609 22:14:34.319196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11610 22:14:34.319460 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11612 22:14:34.322487 rtcwake: assuming RTC uses UTC ...
11613 22:14:34.328780 rtcwake: wakeup from "freeze" using rtc0 at Tue Sep 5 22:13:33 2023
11614 22:14:34.341401 <6>[ 79.503259] PM: suspend entry (s2idle)
11615 22:14:34.344310 <6>[ 79.507329] Filesystems sync: 0.000 seconds
11616 22:14:34.350857 <6>[ 79.512344] Freezing user space processes
11617 22:14:34.357476 <6>[ 79.517910] Freezing user space processes completed (elapsed 0.001 seconds)
11618 22:14:34.360953 <6>[ 79.525131] OOM killer disabled.
11619 22:14:34.367371 <6>[ 79.528611] Freezing remaining freezable tasks
11620 22:14:34.374334 <6>[ 79.534578] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11621 22:14:34.380911 <6>[ 79.542235] printk: Suspending console(s) (use no_console_suspend to debug)
11622 22:14:37.837833 <3>[ 82.766099] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11623 22:14:37.847563 <3>[ 82.766131] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11624 22:14:37.857811 <3>[ 82.766180] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11625 22:14:37.864392 <3>[ 82.766228] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11626 22:14:37.870814 <3>[ 82.766420] PM: Some devices failed to suspend, or early wake event detected
11627 22:14:37.874294 <6>[ 83.040264] OOM killer enabled.
11628 22:14:37.883798 <6>[ 83.043678] Restarting tasks ... done.
11629 22:14:37.890347 <5>[ 83.053126] random: crng reseeded on system resumption
11630 22:14:37.893924 <6>[ 83.060159] PM: suspend exit
11631 22:14:37.897566 rtcwake: write error
11632 22:14:37.904632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11633 22:14:37.904897 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11635 22:14:37.908013 rtcwake: assuming RTC uses UTC ...
11636 22:14:37.914525 rtcwake: wakeup from "freeze" using rtc0 at Tue Sep 5 22:13:37 2023
11637 22:14:37.927415 <6>[ 83.089852] PM: suspend entry (s2idle)
11638 22:14:37.930461 <6>[ 83.093929] Filesystems sync: 0.000 seconds
11639 22:14:37.937384 <6>[ 83.098952] Freezing user space processes
11640 22:14:37.943949 <6>[ 83.104883] Freezing user space processes completed (elapsed 0.001 seconds)
11641 22:14:37.946992 <6>[ 83.112138] OOM killer disabled.
11642 22:14:37.953891 <6>[ 83.115621] Freezing remaining freezable tasks
11643 22:14:37.960435 <6>[ 83.121661] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11644 22:14:37.970581 <6>[ 83.129336] printk: Suspending console(s) (use no_console_suspend to debug)
11645 22:14:41.421405 <3>[ 86.350080] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11646 22:14:41.431313 <3>[ 86.350112] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11647 22:14:41.441126 <3>[ 86.350160] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11648 22:14:41.447908 <3>[ 86.350204] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11649 22:14:41.454714 <3>[ 86.350589] PM: Some devices failed to suspend, or early wake event detected
11650 22:14:41.457935 <6>[ 86.624248] OOM killer enabled.
11651 22:14:41.466249 <6>[ 86.627661] Restarting tasks ... done.
11652 22:14:41.473296 <5>[ 86.635381] random: crng reseeded on system resumption
11653 22:14:41.476445 <6>[ 86.642104] PM: suspend exit
11654 22:14:41.479753 rtcwake: write error
11655 22:14:41.486587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11656 22:14:41.486848 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11658 22:14:41.489716 rtcwake: assuming RTC uses UTC ...
11659 22:14:41.496158 rtcwake: wakeup from "freeze" using rtc0 at Tue Sep 5 22:13:41 2023
11660 22:14:41.508253 <6>[ 86.671567] PM: suspend entry (s2idle)
11661 22:14:41.512010 <6>[ 86.675632] Filesystems sync: 0.000 seconds
11662 22:14:41.515171 <6>[ 86.680639] Freezing user space processes
11663 22:14:41.526939 <6>[ 86.686532] Freezing user space processes completed (elapsed 0.001 seconds)
11664 22:14:41.530273 <6>[ 86.693755] OOM killer disabled.
11665 22:14:41.533560 <6>[ 86.697233] Freezing remaining freezable tasks
11666 22:14:41.543780 <6>[ 86.703366] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11667 22:14:41.550674 <6>[ 86.711044] printk: Suspending console(s) (use no_console_suspend to debug)
11668 22:14:45.004771 <3>[ 89.934110] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11669 22:14:45.014974 <3>[ 89.934142] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11670 22:14:45.024939 <3>[ 89.934190] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11671 22:14:45.031478 <3>[ 89.934235] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11672 22:14:45.038216 <3>[ 89.934554] PM: Some devices failed to suspend, or early wake event detected
11673 22:14:45.041639 <6>[ 90.208261] OOM killer enabled.
11674 22:14:45.049725 <6>[ 90.211676] Restarting tasks ... done.
11675 22:14:45.056754 <5>[ 90.219248] random: crng reseeded on system resumption
11676 22:14:45.060046 <6>[ 90.226437] PM: suspend exit
11677 22:14:45.063082 rtcwake: write error
11678 22:14:45.069963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11679 22:14:45.070224 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11681 22:14:45.073257 rtcwake: assuming RTC uses UTC ...
11682 22:14:45.080107 rtcwake: wakeup from "freeze" using rtc0 at Tue Sep 5 22:13:44 2023
11683 22:14:45.092642 <6>[ 90.255849] PM: suspend entry (s2idle)
11684 22:14:45.095633 <6>[ 90.259934] Filesystems sync: 0.000 seconds
11685 22:14:45.098818 <6>[ 90.264917] Freezing user space processes
11686 22:14:45.110683 <6>[ 90.270837] Freezing user space processes completed (elapsed 0.001 seconds)
11687 22:14:45.114543 <6>[ 90.278068] OOM killer disabled.
11688 22:14:45.117429 <6>[ 90.281544] Freezing remaining freezable tasks
11689 22:14:45.127474 <6>[ 90.287570] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11690 22:14:45.134237 <6>[ 90.295256] printk: Suspending console(s) (use no_console_suspend to debug)
11691 22:14:48.588474 <3>[ 93.518062] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11692 22:14:48.598793 <3>[ 93.518095] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11693 22:14:48.608568 <3>[ 93.518143] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11694 22:14:48.615262 <3>[ 93.518188] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11695 22:14:48.621782 <3>[ 93.518501] PM: Some devices failed to suspend, or early wake event detected
11696 22:14:48.628207 <6>[ 93.792344] OOM killer enabled.
11697 22:14:48.631497 <6>[ 93.795765] Restarting tasks ... done.
11698 22:14:48.639337 <5>[ 93.803337] random: crng reseeded on system resumption
11699 22:14:48.642522 <6>[ 93.809943] PM: suspend exit
11700 22:14:48.646390 rtcwake: write error
11701 22:14:48.653381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11702 22:14:48.653664 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11704 22:14:48.656684 + set +x
11705 22:14:48.659858 <LAVA_SIGNAL_ENDRUN 0_sleep 11440293_1.5.2.3.1>
11706 22:14:48.659941 <LAVA_TEST_RUNNER EXIT>
11707 22:14:48.660175 Received signal: <ENDRUN> 0_sleep 11440293_1.5.2.3.1
11708 22:14:48.660256 Ending use of test pattern.
11709 22:14:48.660317 Ending test lava.0_sleep (11440293_1.5.2.3.1), duration 71.70
11711 22:14:48.660537 ok: lava_test_shell seems to have completed
11712 22:14:48.660719 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11713 22:14:48.660817 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11714 22:14:48.660900 end: 3 lava-test-retry (duration 00:01:12) [common]
11715 22:14:48.660985 start: 4 finalize (timeout 00:06:10) [common]
11716 22:14:48.661071 start: 4.1 power-off (timeout 00:00:30) [common]
11717 22:14:48.661229 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11718 22:14:48.737753 >> Command sent successfully.
11719 22:14:48.740131 Returned 0 in 0 seconds
11720 22:14:48.840550 end: 4.1 power-off (duration 00:00:00) [common]
11722 22:14:48.840889 start: 4.2 read-feedback (timeout 00:06:10) [common]
11723 22:14:48.841156 Listened to connection for namespace 'common' for up to 1s
11724 22:14:48.841443 Listened to connection for namespace 'common' for up to 1s
11725 22:14:49.842105 Finalising connection for namespace 'common'
11726 22:14:49.842281 Disconnecting from shell: Finalise
11727 22:14:49.842362 / #
11728 22:14:49.942685 end: 4.2 read-feedback (duration 00:00:01) [common]
11729 22:14:49.942839 end: 4 finalize (duration 00:00:01) [common]
11730 22:14:49.942954 Cleaning after the job
11731 22:14:49.943058 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/ramdisk
11732 22:14:49.956642 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/kernel
11733 22:14:49.980191 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/dtb
11734 22:14:49.980401 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440293/tftp-deploy-480emkml/modules
11735 22:14:49.987757 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11440293
11736 22:14:50.158915 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11440293
11737 22:14:50.159092 Job finished correctly