Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 68
1 22:09:39.654217 lava-dispatcher, installed at version: 2023.06
2 22:09:39.654426 start: 0 validate
3 22:09:39.654567 Start time: 2023-09-05 22:09:39.654559+00:00 (UTC)
4 22:09:39.654704 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:09:39.654849 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 22:09:39.924507 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:09:39.925340 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:10:03.441429 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:10:03.442118 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:10:03.712024 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:10:03.712718 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-14-gb994de8f45440%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:10:06.536892 validate duration: 26.88
14 22:10:06.537182 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:10:06.537285 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:10:06.537376 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:10:06.537520 Not decompressing ramdisk as can be used compressed.
18 22:10:06.537624 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 22:10:06.537695 saving as /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/ramdisk/rootfs.cpio.gz
20 22:10:06.537760 total size: 26246609 (25 MB)
21 22:10:06.853901 progress 0 % (0 MB)
22 22:10:06.861370 progress 5 % (1 MB)
23 22:10:06.868112 progress 10 % (2 MB)
24 22:10:06.874860 progress 15 % (3 MB)
25 22:10:06.881672 progress 20 % (5 MB)
26 22:10:06.888460 progress 25 % (6 MB)
27 22:10:06.895479 progress 30 % (7 MB)
28 22:10:06.902643 progress 35 % (8 MB)
29 22:10:06.909677 progress 40 % (10 MB)
30 22:10:06.916503 progress 45 % (11 MB)
31 22:10:06.923333 progress 50 % (12 MB)
32 22:10:06.930079 progress 55 % (13 MB)
33 22:10:06.936907 progress 60 % (15 MB)
34 22:10:06.943794 progress 65 % (16 MB)
35 22:10:06.950687 progress 70 % (17 MB)
36 22:10:06.957492 progress 75 % (18 MB)
37 22:10:06.964249 progress 80 % (20 MB)
38 22:10:06.971038 progress 85 % (21 MB)
39 22:10:06.977735 progress 90 % (22 MB)
40 22:10:06.984446 progress 95 % (23 MB)
41 22:10:06.991272 progress 100 % (25 MB)
42 22:10:06.991539 25 MB downloaded in 0.45 s (55.16 MB/s)
43 22:10:06.991699 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:10:06.991940 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:10:06.992029 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:10:06.992157 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:10:06.992292 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:10:06.992362 saving as /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/kernel/Image
50 22:10:06.992423 total size: 49220096 (46 MB)
51 22:10:06.992484 No compression specified
52 22:10:07.004242 progress 0 % (0 MB)
53 22:10:07.017595 progress 5 % (2 MB)
54 22:10:07.030825 progress 10 % (4 MB)
55 22:10:07.043811 progress 15 % (7 MB)
56 22:10:07.056838 progress 20 % (9 MB)
57 22:10:07.070253 progress 25 % (11 MB)
58 22:10:07.083936 progress 30 % (14 MB)
59 22:10:07.097780 progress 35 % (16 MB)
60 22:10:07.111920 progress 40 % (18 MB)
61 22:10:07.125750 progress 45 % (21 MB)
62 22:10:07.139192 progress 50 % (23 MB)
63 22:10:07.152596 progress 55 % (25 MB)
64 22:10:07.165675 progress 60 % (28 MB)
65 22:10:07.178965 progress 65 % (30 MB)
66 22:10:07.192058 progress 70 % (32 MB)
67 22:10:07.205146 progress 75 % (35 MB)
68 22:10:07.218089 progress 80 % (37 MB)
69 22:10:07.231695 progress 85 % (39 MB)
70 22:10:07.245266 progress 90 % (42 MB)
71 22:10:07.258403 progress 95 % (44 MB)
72 22:10:07.272411 progress 100 % (46 MB)
73 22:10:07.272579 46 MB downloaded in 0.28 s (167.55 MB/s)
74 22:10:07.272778 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:10:07.273013 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:10:07.273103 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:10:07.273193 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:10:07.273379 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:10:07.273449 saving as /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/dtb/mt8192-asurada-spherion-r0.dtb
81 22:10:07.273510 total size: 47278 (0 MB)
82 22:10:07.273572 No compression specified
83 22:10:07.274745 progress 69 % (0 MB)
84 22:10:07.275023 progress 100 % (0 MB)
85 22:10:07.275179 0 MB downloaded in 0.00 s (27.05 MB/s)
86 22:10:07.275301 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:10:07.275522 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:10:07.275607 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:10:07.275689 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:10:07.275803 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-14-gb994de8f45440/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:10:07.275871 saving as /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/modules/modules.tar
93 22:10:07.275931 total size: 8619808 (8 MB)
94 22:10:07.275992 Using unxz to decompress xz
95 22:10:07.280329 progress 0 % (0 MB)
96 22:10:07.302061 progress 5 % (0 MB)
97 22:10:07.324898 progress 10 % (0 MB)
98 22:10:07.351230 progress 15 % (1 MB)
99 22:10:07.377719 progress 20 % (1 MB)
100 22:10:07.405304 progress 25 % (2 MB)
101 22:10:07.432771 progress 30 % (2 MB)
102 22:10:07.460017 progress 35 % (2 MB)
103 22:10:07.485542 progress 40 % (3 MB)
104 22:10:07.511017 progress 45 % (3 MB)
105 22:10:07.541077 progress 50 % (4 MB)
106 22:10:07.572340 progress 55 % (4 MB)
107 22:10:07.598134 progress 60 % (4 MB)
108 22:10:07.621126 progress 65 % (5 MB)
109 22:10:07.648813 progress 70 % (5 MB)
110 22:10:07.673423 progress 75 % (6 MB)
111 22:10:07.699980 progress 80 % (6 MB)
112 22:10:07.731251 progress 85 % (7 MB)
113 22:10:07.758758 progress 90 % (7 MB)
114 22:10:07.783146 progress 95 % (7 MB)
115 22:10:07.809342 progress 100 % (8 MB)
116 22:10:07.813923 8 MB downloaded in 0.54 s (15.28 MB/s)
117 22:10:07.814200 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:10:07.814481 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:10:07.814577 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:10:07.814684 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:10:07.814768 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:10:07.814866 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:10:07.815109 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz
125 22:10:07.815259 makedir: /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin
126 22:10:07.815373 makedir: /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/tests
127 22:10:07.815484 makedir: /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/results
128 22:10:07.815616 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-add-keys
129 22:10:07.815770 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-add-sources
130 22:10:07.815919 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-background-process-start
131 22:10:07.816061 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-background-process-stop
132 22:10:07.816199 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-common-functions
133 22:10:07.816329 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-echo-ipv4
134 22:10:07.816468 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-install-packages
135 22:10:07.816606 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-installed-packages
136 22:10:07.816757 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-os-build
137 22:10:07.816890 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-probe-channel
138 22:10:07.817043 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-probe-ip
139 22:10:07.817190 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-target-ip
140 22:10:07.817331 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-target-mac
141 22:10:07.817463 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-target-storage
142 22:10:07.817606 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-test-case
143 22:10:07.817743 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-test-event
144 22:10:07.817873 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-test-feedback
145 22:10:07.818012 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-test-raise
146 22:10:07.818156 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-test-reference
147 22:10:07.818284 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-test-runner
148 22:10:07.818422 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-test-set
149 22:10:07.818555 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-test-shell
150 22:10:07.818695 Updating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-install-packages (oe)
151 22:10:07.818855 Updating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/bin/lava-installed-packages (oe)
152 22:10:07.818998 Creating /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/environment
153 22:10:07.819116 LAVA metadata
154 22:10:07.819192 - LAVA_JOB_ID=11440302
155 22:10:07.819259 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:10:07.819376 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:10:07.819446 skipped lava-vland-overlay
158 22:10:07.819522 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:10:07.819601 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:10:07.819667 skipped lava-multinode-overlay
161 22:10:07.819754 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:10:07.819841 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:10:07.819919 Loading test definitions
164 22:10:07.820011 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:10:07.820083 Using /lava-11440302 at stage 0
166 22:10:07.820405 uuid=11440302_1.5.2.3.1 testdef=None
167 22:10:07.820495 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:10:07.820582 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:10:07.821132 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:10:07.821368 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:10:07.822042 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:10:07.822276 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:10:07.822916 runner path: /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11440302_1.5.2.3.1
176 22:10:07.823077 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:10:07.823283 Creating lava-test-runner.conf files
179 22:10:07.823358 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11440302/lava-overlay-_axnohlz/lava-11440302/0 for stage 0
180 22:10:07.823450 - 0_v4l2-compliance-mtk-vcodec-enc
181 22:10:07.823550 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:10:07.823638 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:10:07.830994 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:10:07.831114 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:10:07.831214 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:10:07.831318 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:10:07.831409 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:10:08.587171 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:10:08.587586 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:10:08.587713 extracting modules file /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11440302/extract-overlay-ramdisk-czid7p0j/ramdisk
191 22:10:08.839743 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:10:08.839912 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 22:10:08.840030 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11440302/compress-overlay-fz1phieo/overlay-1.5.2.4.tar.gz to ramdisk
194 22:10:08.840113 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11440302/compress-overlay-fz1phieo/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11440302/extract-overlay-ramdisk-czid7p0j/ramdisk
195 22:10:08.847304 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:10:08.847427 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 22:10:08.847522 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:10:08.847614 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 22:10:08.847694 Building ramdisk /var/lib/lava/dispatcher/tmp/11440302/extract-overlay-ramdisk-czid7p0j/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11440302/extract-overlay-ramdisk-czid7p0j/ramdisk
200 22:10:09.544661 >> 228284 blocks
201 22:10:13.562279 rename /var/lib/lava/dispatcher/tmp/11440302/extract-overlay-ramdisk-czid7p0j/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/ramdisk/ramdisk.cpio.gz
202 22:10:13.562732 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 22:10:13.562858 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 22:10:13.562958 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 22:10:13.563072 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/kernel/Image'
206 22:10:26.851868 Returned 0 in 13 seconds
207 22:10:26.952622 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/kernel/image.itb
208 22:10:27.596053 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:10:27.596521 output: Created: Tue Sep 5 23:10:27 2023
210 22:10:27.596661 output: Image 0 (kernel-1)
211 22:10:27.596784 output: Description:
212 22:10:27.596877 output: Created: Tue Sep 5 23:10:27 2023
213 22:10:27.597005 output: Type: Kernel Image
214 22:10:27.597098 output: Compression: lzma compressed
215 22:10:27.597193 output: Data Size: 11037994 Bytes = 10779.29 KiB = 10.53 MiB
216 22:10:27.597287 output: Architecture: AArch64
217 22:10:27.597407 output: OS: Linux
218 22:10:27.597498 output: Load Address: 0x00000000
219 22:10:27.597585 output: Entry Point: 0x00000000
220 22:10:27.597670 output: Hash algo: crc32
221 22:10:27.597785 output: Hash value: 9d08b3de
222 22:10:27.597871 output: Image 1 (fdt-1)
223 22:10:27.597956 output: Description: mt8192-asurada-spherion-r0
224 22:10:27.598041 output: Created: Tue Sep 5 23:10:27 2023
225 22:10:27.598127 output: Type: Flat Device Tree
226 22:10:27.598212 output: Compression: uncompressed
227 22:10:27.598295 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 22:10:27.598380 output: Architecture: AArch64
229 22:10:27.598464 output: Hash algo: crc32
230 22:10:27.598548 output: Hash value: cc4352de
231 22:10:27.598634 output: Image 2 (ramdisk-1)
232 22:10:27.598720 output: Description: unavailable
233 22:10:27.598805 output: Created: Tue Sep 5 23:10:27 2023
234 22:10:27.598889 output: Type: RAMDisk Image
235 22:10:27.598974 output: Compression: Unknown Compression
236 22:10:27.599058 output: Data Size: 39354499 Bytes = 38432.13 KiB = 37.53 MiB
237 22:10:27.599142 output: Architecture: AArch64
238 22:10:27.599244 output: OS: Linux
239 22:10:27.599341 output: Load Address: unavailable
240 22:10:27.599426 output: Entry Point: unavailable
241 22:10:27.599513 output: Hash algo: crc32
242 22:10:27.599613 output: Hash value: c9999bd7
243 22:10:27.599710 output: Default Configuration: 'conf-1'
244 22:10:27.599796 output: Configuration 0 (conf-1)
245 22:10:27.599882 output: Description: mt8192-asurada-spherion-r0
246 22:10:27.599968 output: Kernel: kernel-1
247 22:10:27.600052 output: Init Ramdisk: ramdisk-1
248 22:10:27.600137 output: FDT: fdt-1
249 22:10:27.600221 output: Loadables: kernel-1
250 22:10:27.600307 output:
251 22:10:27.600580 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 22:10:27.600792 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 22:10:27.600943 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 22:10:27.601078 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 22:10:27.601195 No LXC device requested
256 22:10:27.601317 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:10:27.601446 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 22:10:27.601562 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:10:27.601670 Checking files for TFTP limit of 4294967296 bytes.
260 22:10:27.602394 end: 1 tftp-deploy (duration 00:00:21) [common]
261 22:10:27.602533 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:10:27.602663 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:10:27.602836 substitutions:
264 22:10:27.602935 - {DTB}: 11440302/tftp-deploy-3bltm57_/dtb/mt8192-asurada-spherion-r0.dtb
265 22:10:27.603032 - {INITRD}: 11440302/tftp-deploy-3bltm57_/ramdisk/ramdisk.cpio.gz
266 22:10:27.603122 - {KERNEL}: 11440302/tftp-deploy-3bltm57_/kernel/Image
267 22:10:27.603211 - {LAVA_MAC}: None
268 22:10:27.603299 - {PRESEED_CONFIG}: None
269 22:10:27.603386 - {PRESEED_LOCAL}: None
270 22:10:27.603472 - {RAMDISK}: 11440302/tftp-deploy-3bltm57_/ramdisk/ramdisk.cpio.gz
271 22:10:27.603596 - {ROOT_PART}: None
272 22:10:27.603684 - {ROOT}: None
273 22:10:27.603771 - {SERVER_IP}: 192.168.201.1
274 22:10:27.603857 - {TEE}: None
275 22:10:27.603942 Parsed boot commands:
276 22:10:27.604025 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:10:27.604272 Parsed boot commands: tftpboot 192.168.201.1 11440302/tftp-deploy-3bltm57_/kernel/image.itb 11440302/tftp-deploy-3bltm57_/kernel/cmdline
278 22:10:27.604401 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:10:27.604529 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:10:27.604669 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:10:27.604837 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:10:27.604943 Not connected, no need to disconnect.
283 22:10:27.605054 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:10:27.605178 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:10:27.605285 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 22:10:27.610563 Setting prompt string to ['lava-test: # ']
287 22:10:27.611155 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:10:27.611315 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:10:27.611489 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:10:27.611622 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:10:27.611932 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 22:10:32.764466 >> Command sent successfully.
293 22:10:32.777023 Returned 0 in 5 seconds
294 22:10:32.878174 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:10:32.879543 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:10:32.880015 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:10:32.880448 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:10:32.880852 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:10:32.881214 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:10:32.882423 [Enter `^Ec?' for help]
302 22:10:33.043323
303 22:10:33.043828
304 22:10:33.044169 F0: 102B 0000
305 22:10:33.044484
306 22:10:33.044832 F3: 1001 0000 [0200]
307 22:10:33.046257
308 22:10:33.046688 F3: 1001 0000
309 22:10:33.047246
310 22:10:33.047624 F7: 102D 0000
311 22:10:33.047931
312 22:10:33.050250 F1: 0000 0000
313 22:10:33.050692
314 22:10:33.051030 V0: 0000 0000 [0001]
315 22:10:33.051368
316 22:10:33.053251 00: 0007 8000
317 22:10:33.053687
318 22:10:33.054040 01: 0000 0000
319 22:10:33.054367
320 22:10:33.057068 BP: 0C00 0209 [0000]
321 22:10:33.057513
322 22:10:33.057974 G0: 1182 0000
323 22:10:33.058295
324 22:10:33.060535 EC: 0000 0021 [4000]
325 22:10:33.061166
326 22:10:33.061714 S7: 0000 0000 [0000]
327 22:10:33.062209
328 22:10:33.063587 CC: 0000 0000 [0001]
329 22:10:33.064130
330 22:10:33.064502 T0: 0000 0040 [010F]
331 22:10:33.064972
332 22:10:33.065344 Jump to BL
333 22:10:33.065640
334 22:10:33.090377
335 22:10:33.090879
336 22:10:33.091352
337 22:10:33.097734 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:10:33.101876 ARM64: Exception handlers installed.
339 22:10:33.105491 ARM64: Testing exception
340 22:10:33.108442 ARM64: Done test exception
341 22:10:33.114905 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:10:33.125297 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:10:33.132404 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:10:33.142567 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:10:33.148980 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:10:33.155646 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:10:33.167225 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:10:33.174046 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:10:33.193220 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:10:33.196455 WDT: Last reset was cold boot
351 22:10:33.199760 SPI1(PAD0) initialized at 2873684 Hz
352 22:10:33.203425 SPI5(PAD0) initialized at 992727 Hz
353 22:10:33.206485 VBOOT: Loading verstage.
354 22:10:33.213259 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:10:33.216374 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:10:33.220244 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:10:33.223502 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:10:33.230522 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:10:33.237430 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:10:33.248091 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 22:10:33.248512
362 22:10:33.248912
363 22:10:33.258238 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:10:33.261638 ARM64: Exception handlers installed.
365 22:10:33.264788 ARM64: Testing exception
366 22:10:33.265216 ARM64: Done test exception
367 22:10:33.271718 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:10:33.275308 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:10:33.289606 Probing TPM: . done!
370 22:10:33.290026 TPM ready after 0 ms
371 22:10:33.296442 Connected to device vid:did:rid of 1ae0:0028:00
372 22:10:33.303998 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 22:10:33.361028 Initialized TPM device CR50 revision 0
374 22:10:33.372857 tlcl_send_startup: Startup return code is 0
375 22:10:33.373296 TPM: setup succeeded
376 22:10:33.384447 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:10:33.393400 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:10:33.405576 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:10:33.415212 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:10:33.418670 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:10:33.422499 in-header: 03 07 00 00 08 00 00 00
382 22:10:33.426388 in-data: aa e4 47 04 13 02 00 00
383 22:10:33.429823 Chrome EC: UHEPI supported
384 22:10:33.437200 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:10:33.440922 in-header: 03 ad 00 00 08 00 00 00
386 22:10:33.444217 in-data: 00 20 20 08 00 00 00 00
387 22:10:33.444750 Phase 1
388 22:10:33.448471 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:10:33.455748 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:10:33.459430 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:10:33.463171 Recovery requested (1009000e)
392 22:10:33.471331 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:10:33.476764 tlcl_extend: response is 0
394 22:10:33.486543 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:10:33.491481 tlcl_extend: response is 0
396 22:10:33.498153 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:10:33.518770 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 22:10:33.525561 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:10:33.526088
400 22:10:33.526417
401 22:10:33.536408 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:10:33.539644 ARM64: Exception handlers installed.
403 22:10:33.540151 ARM64: Testing exception
404 22:10:33.543337 ARM64: Done test exception
405 22:10:33.564080 pmic_efuse_setting: Set efuses in 11 msecs
406 22:10:33.567658 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:10:33.575040 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:10:33.578319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:10:33.581546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:10:33.588318 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:10:33.591859 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:10:33.599203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:10:33.602882 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:10:33.606655 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:10:33.610329 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:10:33.617552 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:10:33.621200 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:10:33.624987 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:10:33.628649 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:10:33.636361 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:10:33.644023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:10:33.647297 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:10:33.654990 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:10:33.658797 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:10:33.665649 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:10:33.669359 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:10:33.676638 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:10:33.680846 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:10:33.688068 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:10:33.691627 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:10:33.699154 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:10:33.703574 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:10:33.706638 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:10:33.714233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:10:33.717913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:10:33.721967 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:10:33.729284 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:10:33.732756 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:10:33.736471 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:10:33.743552 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:10:33.747689 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:10:33.751476 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:10:33.758796 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:10:33.763024 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:10:33.766549 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:10:33.770256 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:10:33.777219 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:10:33.781354 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:10:33.785278 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:10:33.788348 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:10:33.792035 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:10:33.799451 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:10:33.802812 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:10:33.807066 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:10:33.810544 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:10:33.814208 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:10:33.817663 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:10:33.825111 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:10:33.836411 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:10:33.839998 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:10:33.847807 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:10:33.855282 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:10:33.862667 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:10:33.866670 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:10:33.870340 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:10:33.877068 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x1c
467 22:10:33.880640 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:10:33.889421 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 22:10:33.892852 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:10:33.901389 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 22:10:33.911438 [RTC]rtc_get_frequency_meter,154: input=23, output=979
472 22:10:33.920517 [RTC]rtc_get_frequency_meter,154: input=19, output=885
473 22:10:33.930561 [RTC]rtc_get_frequency_meter,154: input=17, output=837
474 22:10:33.940141 [RTC]rtc_get_frequency_meter,154: input=16, output=814
475 22:10:33.949297 [RTC]rtc_get_frequency_meter,154: input=15, output=789
476 22:10:33.959681 [RTC]rtc_get_frequency_meter,154: input=16, output=813
477 22:10:33.963284 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 22:10:33.966775 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 22:10:33.970373 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:10:33.977347 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:10:33.981388 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:10:33.985199 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:10:33.988540 ADC[4]: Raw value=902066 ID=7
484 22:10:33.992463 ADC[3]: Raw value=213336 ID=1
485 22:10:33.993029 RAM Code: 0x71
486 22:10:33.996277 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:10:34.003338 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:10:34.010939 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 22:10:34.018522 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 22:10:34.019050 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:10:34.023786 in-header: 03 07 00 00 08 00 00 00
492 22:10:34.027400 in-data: aa e4 47 04 13 02 00 00
493 22:10:34.031548 Chrome EC: UHEPI supported
494 22:10:34.038750 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:10:34.042698 in-header: 03 ed 00 00 08 00 00 00
496 22:10:34.043278 in-data: 80 20 60 08 00 00 00 00
497 22:10:34.046099 MRC: failed to locate region type 0.
498 22:10:34.054237 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:10:34.057901 DRAM-K: Running full calibration
500 22:10:34.061196 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 22:10:34.065318 header.status = 0x0
502 22:10:34.068621 header.version = 0x6 (expected: 0x6)
503 22:10:34.072871 header.size = 0xd00 (expected: 0xd00)
504 22:10:34.073308 header.flags = 0x0
505 22:10:34.080108 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:10:34.097818 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 22:10:34.105221 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:10:34.105645 dram_init: ddr_geometry: 2
509 22:10:34.108561 [EMI] MDL number = 2
510 22:10:34.112078 [EMI] Get MDL freq = 0
511 22:10:34.112493 dram_init: ddr_type: 0
512 22:10:34.115615 is_discrete_lpddr4: 1
513 22:10:34.119781 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:10:34.120198
515 22:10:34.120526
516 22:10:34.120958 [Bian_co] ETT version 0.0.0.1
517 22:10:34.126839 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 22:10:34.127257
519 22:10:34.130363 dramc_set_vcore_voltage set vcore to 650000
520 22:10:34.130834 Read voltage for 800, 4
521 22:10:34.133958 Vio18 = 0
522 22:10:34.134372 Vcore = 650000
523 22:10:34.134709 Vdram = 0
524 22:10:34.137671 Vddq = 0
525 22:10:34.138086 Vmddr = 0
526 22:10:34.138417 dram_init: config_dvfs: 1
527 22:10:34.145160 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:10:34.148604 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:10:34.152493 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 22:10:34.158763 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 22:10:34.162525 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 22:10:34.165736 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 22:10:34.166221 MEM_TYPE=3, freq_sel=18
534 22:10:34.168758 sv_algorithm_assistance_LP4_1600
535 22:10:34.175838 ============ PULL DRAM RESETB DOWN ============
536 22:10:34.178827 ========== PULL DRAM RESETB DOWN end =========
537 22:10:34.182475 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:10:34.185949 ===================================
539 22:10:34.188927 LPDDR4 DRAM CONFIGURATION
540 22:10:34.192309 ===================================
541 22:10:34.192808 EX_ROW_EN[0] = 0x0
542 22:10:34.195231 EX_ROW_EN[1] = 0x0
543 22:10:34.198670 LP4Y_EN = 0x0
544 22:10:34.199088 WORK_FSP = 0x0
545 22:10:34.201879 WL = 0x2
546 22:10:34.202440 RL = 0x2
547 22:10:34.205272 BL = 0x2
548 22:10:34.205692 RPST = 0x0
549 22:10:34.208656 RD_PRE = 0x0
550 22:10:34.209116 WR_PRE = 0x1
551 22:10:34.212278 WR_PST = 0x0
552 22:10:34.212743 DBI_WR = 0x0
553 22:10:34.215631 DBI_RD = 0x0
554 22:10:34.216046 OTF = 0x1
555 22:10:34.219003 ===================================
556 22:10:34.222049 ===================================
557 22:10:34.225707 ANA top config
558 22:10:34.229116 ===================================
559 22:10:34.229537 DLL_ASYNC_EN = 0
560 22:10:34.232193 ALL_SLAVE_EN = 1
561 22:10:34.235698 NEW_RANK_MODE = 1
562 22:10:34.238667 DLL_IDLE_MODE = 1
563 22:10:34.242310 LP45_APHY_COMB_EN = 1
564 22:10:34.242729 TX_ODT_DIS = 1
565 22:10:34.246208 NEW_8X_MODE = 1
566 22:10:34.248996 ===================================
567 22:10:34.252809 ===================================
568 22:10:34.256176 data_rate = 1600
569 22:10:34.259087 CKR = 1
570 22:10:34.259507 DQ_P2S_RATIO = 8
571 22:10:34.262855 ===================================
572 22:10:34.266213 CA_P2S_RATIO = 8
573 22:10:34.269245 DQ_CA_OPEN = 0
574 22:10:34.272700 DQ_SEMI_OPEN = 0
575 22:10:34.276204 CA_SEMI_OPEN = 0
576 22:10:34.279645 CA_FULL_RATE = 0
577 22:10:34.280165 DQ_CKDIV4_EN = 1
578 22:10:34.283273 CA_CKDIV4_EN = 1
579 22:10:34.286454 CA_PREDIV_EN = 0
580 22:10:34.289291 PH8_DLY = 0
581 22:10:34.292981 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:10:34.293503 DQ_AAMCK_DIV = 4
583 22:10:34.296280 CA_AAMCK_DIV = 4
584 22:10:34.299447 CA_ADMCK_DIV = 4
585 22:10:34.302697 DQ_TRACK_CA_EN = 0
586 22:10:34.306304 CA_PICK = 800
587 22:10:34.309634 CA_MCKIO = 800
588 22:10:34.313062 MCKIO_SEMI = 0
589 22:10:34.313553 PLL_FREQ = 3068
590 22:10:34.316750 DQ_UI_PI_RATIO = 32
591 22:10:34.320767 CA_UI_PI_RATIO = 0
592 22:10:34.323969 ===================================
593 22:10:34.327657 ===================================
594 22:10:34.328209 memory_type:LPDDR4
595 22:10:34.331584 GP_NUM : 10
596 22:10:34.332150 SRAM_EN : 1
597 22:10:34.335411 MD32_EN : 0
598 22:10:34.338687 ===================================
599 22:10:34.339226 [ANA_INIT] >>>>>>>>>>>>>>
600 22:10:34.342473 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:10:34.346264 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:10:34.350381 ===================================
603 22:10:34.353493 data_rate = 1600,PCW = 0X7600
604 22:10:34.357079 ===================================
605 22:10:34.360503 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:10:34.363500 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:10:34.370120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:10:34.373572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:10:34.380201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:10:34.383732 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:10:34.384165 [ANA_INIT] flow start
612 22:10:34.387100 [ANA_INIT] PLL >>>>>>>>
613 22:10:34.387517 [ANA_INIT] PLL <<<<<<<<
614 22:10:34.390743 [ANA_INIT] MIDPI >>>>>>>>
615 22:10:34.394187 [ANA_INIT] MIDPI <<<<<<<<
616 22:10:34.397128 [ANA_INIT] DLL >>>>>>>>
617 22:10:34.397540 [ANA_INIT] flow end
618 22:10:34.400771 ============ LP4 DIFF to SE enter ============
619 22:10:34.407246 ============ LP4 DIFF to SE exit ============
620 22:10:34.407751 [ANA_INIT] <<<<<<<<<<<<<
621 22:10:34.410755 [Flow] Enable top DCM control >>>>>
622 22:10:34.414304 [Flow] Enable top DCM control <<<<<
623 22:10:34.417187 Enable DLL master slave shuffle
624 22:10:34.424013 ==============================================================
625 22:10:34.424531 Gating Mode config
626 22:10:34.430711 ==============================================================
627 22:10:34.434359 Config description:
628 22:10:34.440785 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:10:34.447478 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:10:34.454143 SELPH_MODE 0: By rank 1: By Phase
631 22:10:34.457732 ==============================================================
632 22:10:34.460785 GAT_TRACK_EN = 1
633 22:10:34.464361 RX_GATING_MODE = 2
634 22:10:34.467767 RX_GATING_TRACK_MODE = 2
635 22:10:34.470781 SELPH_MODE = 1
636 22:10:34.474494 PICG_EARLY_EN = 1
637 22:10:34.478051 VALID_LAT_VALUE = 1
638 22:10:34.481214 ==============================================================
639 22:10:34.484937 Enter into Gating configuration >>>>
640 22:10:34.487962 Exit from Gating configuration <<<<
641 22:10:34.491413 Enter into DVFS_PRE_config >>>>>
642 22:10:34.504931 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:10:34.507879 Exit from DVFS_PRE_config <<<<<
644 22:10:34.511462 Enter into PICG configuration >>>>
645 22:10:34.511982 Exit from PICG configuration <<<<
646 22:10:34.514701 [RX_INPUT] configuration >>>>>
647 22:10:34.518320 [RX_INPUT] configuration <<<<<
648 22:10:34.525051 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:10:34.527929 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:10:34.534920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:10:34.541928 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:10:34.548517 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:10:34.551920 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:10:34.559050 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:10:34.562199 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:10:34.565547 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:10:34.568436 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:10:34.575675 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:10:34.578825 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:10:34.582440 ===================================
661 22:10:34.585477 LPDDR4 DRAM CONFIGURATION
662 22:10:34.589144 ===================================
663 22:10:34.589221 EX_ROW_EN[0] = 0x0
664 22:10:34.592241 EX_ROW_EN[1] = 0x0
665 22:10:34.592315 LP4Y_EN = 0x0
666 22:10:34.595889 WORK_FSP = 0x0
667 22:10:34.595964 WL = 0x2
668 22:10:34.598905 RL = 0x2
669 22:10:34.598981 BL = 0x2
670 22:10:34.602555 RPST = 0x0
671 22:10:34.602659 RD_PRE = 0x0
672 22:10:34.605964 WR_PRE = 0x1
673 22:10:34.606080 WR_PST = 0x0
674 22:10:34.609271 DBI_WR = 0x0
675 22:10:34.609393 DBI_RD = 0x0
676 22:10:34.612845 OTF = 0x1
677 22:10:34.615784 ===================================
678 22:10:34.619479 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:10:34.622417 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:10:34.629564 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:10:34.632519 ===================================
682 22:10:34.632760 LPDDR4 DRAM CONFIGURATION
683 22:10:34.636058 ===================================
684 22:10:34.639401 EX_ROW_EN[0] = 0x10
685 22:10:34.639601 EX_ROW_EN[1] = 0x0
686 22:10:34.642655 LP4Y_EN = 0x0
687 22:10:34.642923 WORK_FSP = 0x0
688 22:10:34.646138 WL = 0x2
689 22:10:34.649780 RL = 0x2
690 22:10:34.650077 BL = 0x2
691 22:10:34.652761 RPST = 0x0
692 22:10:34.653146 RD_PRE = 0x0
693 22:10:34.656484 WR_PRE = 0x1
694 22:10:34.657097 WR_PST = 0x0
695 22:10:34.659976 DBI_WR = 0x0
696 22:10:34.660536 DBI_RD = 0x0
697 22:10:34.663183 OTF = 0x1
698 22:10:34.666412 ===================================
699 22:10:34.670237 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:10:34.675381 nWR fixed to 40
701 22:10:34.678556 [ModeRegInit_LP4] CH0 RK0
702 22:10:34.679125 [ModeRegInit_LP4] CH0 RK1
703 22:10:34.682047 [ModeRegInit_LP4] CH1 RK0
704 22:10:34.685257 [ModeRegInit_LP4] CH1 RK1
705 22:10:34.685673 match AC timing 13
706 22:10:34.691721 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 22:10:34.695374 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:10:34.698488 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:10:34.705766 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:10:34.708733 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:10:34.709176 [EMI DOE] emi_dcm 0
712 22:10:34.715567 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:10:34.715986 ==
714 22:10:34.718764 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:10:34.722257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 22:10:34.722677 ==
717 22:10:34.729202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:10:34.732257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:10:34.742926 [CA 0] Center 37 (7~68) winsize 62
720 22:10:34.746822 [CA 1] Center 37 (6~68) winsize 63
721 22:10:34.749725 [CA 2] Center 35 (5~66) winsize 62
722 22:10:34.753162 [CA 3] Center 34 (4~65) winsize 62
723 22:10:34.756238 [CA 4] Center 34 (4~65) winsize 62
724 22:10:34.759426 [CA 5] Center 33 (3~64) winsize 62
725 22:10:34.759858
726 22:10:34.763011 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 22:10:34.763513
728 22:10:34.766061 [CATrainingPosCal] consider 1 rank data
729 22:10:34.769437 u2DelayCellTimex100 = 270/100 ps
730 22:10:34.772778 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 22:10:34.776468 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 22:10:34.782831 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 22:10:34.786233 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 22:10:34.789785 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
735 22:10:34.793388 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 22:10:34.793812
737 22:10:34.796255 CA PerBit enable=1, Macro0, CA PI delay=33
738 22:10:34.796700
739 22:10:34.800048 [CBTSetCACLKResult] CA Dly = 33
740 22:10:34.800558 CS Dly: 5 (0~36)
741 22:10:34.800956 ==
742 22:10:34.803155 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:10:34.810423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 22:10:34.810946 ==
745 22:10:34.813393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:10:34.819771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:10:34.828827 [CA 0] Center 37 (6~68) winsize 63
748 22:10:34.832382 [CA 1] Center 37 (6~68) winsize 63
749 22:10:34.835738 [CA 2] Center 35 (4~66) winsize 63
750 22:10:34.839329 [CA 3] Center 35 (4~66) winsize 63
751 22:10:34.842511 [CA 4] Center 34 (3~65) winsize 63
752 22:10:34.846007 [CA 5] Center 33 (3~64) winsize 62
753 22:10:34.846535
754 22:10:34.849138 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 22:10:34.849676
756 22:10:34.852607 [CATrainingPosCal] consider 2 rank data
757 22:10:34.855707 u2DelayCellTimex100 = 270/100 ps
758 22:10:34.858810 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 22:10:34.862404 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
760 22:10:34.869397 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 22:10:34.872345 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 22:10:34.875968 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
763 22:10:34.879337 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 22:10:34.879834
765 22:10:34.882743 CA PerBit enable=1, Macro0, CA PI delay=33
766 22:10:34.883244
767 22:10:34.886226 [CBTSetCACLKResult] CA Dly = 33
768 22:10:34.886648 CS Dly: 5 (0~37)
769 22:10:34.887037
770 22:10:34.889256 ----->DramcWriteLeveling(PI) begin...
771 22:10:34.889774 ==
772 22:10:34.892626 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:10:34.900176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:10:34.900610 ==
775 22:10:34.901044 Write leveling (Byte 0): 29 => 29
776 22:10:34.903624 Write leveling (Byte 1): 29 => 29
777 22:10:34.907269 DramcWriteLeveling(PI) end<-----
778 22:10:34.907688
779 22:10:34.908016 ==
780 22:10:34.911373 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:10:34.914367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:10:34.914873 ==
783 22:10:34.918025 [Gating] SW mode calibration
784 22:10:34.924646 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:10:34.932152 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:10:34.935599 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:10:34.938949 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 22:10:34.942290 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 22:10:34.948657 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:10:34.952148 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:10:34.955346 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:10:34.962279 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:10:34.965378 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:10:34.968857 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:10:34.975538 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:10:34.979045 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:10:34.982521 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:10:34.988743 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:10:34.992160 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:10:34.995816 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:10:35.002907 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:10:35.005817 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:10:35.009237 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 22:10:35.012951 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 22:10:35.019212 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 22:10:35.022766 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:10:35.025840 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:10:35.033179 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:10:35.036186 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:10:35.039667 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:10:35.046399 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:10:35.049754 0 9 8 | B1->B0 | 2323 2424 | 1 1 | (1 1) (1 1)
813 22:10:35.053386 0 9 12 | B1->B0 | 2c2c 3333 | 1 0 | (1 1) (0 0)
814 22:10:35.056274 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:10:35.063676 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:10:35.066756 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:10:35.070137 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:10:35.076262 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:10:35.079808 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 22:10:35.083258 0 10 8 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
821 22:10:35.090348 0 10 12 | B1->B0 | 2d2d 2424 | 0 0 | (1 1) (0 0)
822 22:10:35.093108 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:10:35.096577 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:10:35.103251 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:10:35.106858 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:10:35.109846 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:10:35.113226 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 22:10:35.119995 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
829 22:10:35.123836 0 11 12 | B1->B0 | 3838 3e3e | 0 1 | (0 0) (0 0)
830 22:10:35.126697 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:10:35.133376 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:10:35.136917 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:10:35.140423 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:10:35.147074 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 22:10:35.150306 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 22:10:35.153742 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 22:10:35.160823 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:10:35.164250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:10:35.167162 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:10:35.170519 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:10:35.177107 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:10:35.180751 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:10:35.184243 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:10:35.190955 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:10:35.194184 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:10:35.197327 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:10:35.203958 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:10:35.207666 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:10:35.210418 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:10:35.217567 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:10:35.221048 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 22:10:35.224422 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 22:10:35.228098 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 22:10:35.231008 Total UI for P1: 0, mck2ui 16
855 22:10:35.234508 best dqsien dly found for B0: ( 0, 14, 8)
856 22:10:35.237548 Total UI for P1: 0, mck2ui 16
857 22:10:35.241006 best dqsien dly found for B1: ( 0, 14, 10)
858 22:10:35.244442 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 22:10:35.248070 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 22:10:35.248515
861 22:10:35.254799 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 22:10:35.258710 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 22:10:35.259264 [Gating] SW calibration Done
864 22:10:35.261377 ==
865 22:10:35.261796 Dram Type= 6, Freq= 0, CH_0, rank 0
866 22:10:35.267980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 22:10:35.268610 ==
868 22:10:35.269045 RX Vref Scan: 0
869 22:10:35.269494
870 22:10:35.271606 RX Vref 0 -> 0, step: 1
871 22:10:35.272200
872 22:10:35.274863 RX Delay -130 -> 252, step: 16
873 22:10:35.278352 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 22:10:35.281778 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 22:10:35.284947 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 22:10:35.291689 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 22:10:35.295369 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 22:10:35.298451 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 22:10:35.301508 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
880 22:10:35.304799 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
881 22:10:35.308335 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 22:10:35.315188 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 22:10:35.318212 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 22:10:35.321711 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 22:10:35.325259 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 22:10:35.328267 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 22:10:35.335335 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 22:10:35.338652 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 22:10:35.339131 ==
890 22:10:35.342252 Dram Type= 6, Freq= 0, CH_0, rank 0
891 22:10:35.345111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 22:10:35.345770 ==
893 22:10:35.348710 DQS Delay:
894 22:10:35.349208 DQS0 = 0, DQS1 = 0
895 22:10:35.349684 DQM Delay:
896 22:10:35.352202 DQM0 = 84, DQM1 = 78
897 22:10:35.352854 DQ Delay:
898 22:10:35.355263 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 22:10:35.358868 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
900 22:10:35.361931 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 22:10:35.365646 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 22:10:35.366225
903 22:10:35.366801
904 22:10:35.367313 ==
905 22:10:35.368555 Dram Type= 6, Freq= 0, CH_0, rank 0
906 22:10:35.372190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 22:10:35.375349 ==
908 22:10:35.375769
909 22:10:35.376097
910 22:10:35.376404 TX Vref Scan disable
911 22:10:35.379168 == TX Byte 0 ==
912 22:10:35.382245 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 22:10:35.385710 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 22:10:35.389717 == TX Byte 1 ==
915 22:10:35.392575 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 22:10:35.396035 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 22:10:35.396587 ==
918 22:10:35.399093 Dram Type= 6, Freq= 0, CH_0, rank 0
919 22:10:35.405869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 22:10:35.406540 ==
921 22:10:35.418068 TX Vref=22, minBit 7, minWin=26, winSum=440
922 22:10:35.421257 TX Vref=24, minBit 0, minWin=27, winSum=444
923 22:10:35.424599 TX Vref=26, minBit 3, minWin=27, winSum=444
924 22:10:35.428165 TX Vref=28, minBit 0, minWin=27, winSum=445
925 22:10:35.431651 TX Vref=30, minBit 12, minWin=27, winSum=452
926 22:10:35.435047 TX Vref=32, minBit 12, minWin=27, winSum=451
927 22:10:35.441351 [TxChooseVref] Worse bit 12, Min win 27, Win sum 452, Final Vref 30
928 22:10:35.441890
929 22:10:35.445124 Final TX Range 1 Vref 30
930 22:10:35.445690
931 22:10:35.446176 ==
932 22:10:35.448036 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:10:35.451698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:10:35.452165 ==
935 22:10:35.452735
936 22:10:35.453192
937 22:10:35.454994 TX Vref Scan disable
938 22:10:35.458067 == TX Byte 0 ==
939 22:10:35.461709 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 22:10:35.464842 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 22:10:35.468362 == TX Byte 1 ==
942 22:10:35.471287 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 22:10:35.475056 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 22:10:35.475689
945 22:10:35.478536 [DATLAT]
946 22:10:35.479126 Freq=800, CH0 RK0
947 22:10:35.479637
948 22:10:35.481920 DATLAT Default: 0xa
949 22:10:35.482543 0, 0xFFFF, sum = 0
950 22:10:35.485040 1, 0xFFFF, sum = 0
951 22:10:35.485443 2, 0xFFFF, sum = 0
952 22:10:35.488398 3, 0xFFFF, sum = 0
953 22:10:35.489022 4, 0xFFFF, sum = 0
954 22:10:35.491940 5, 0xFFFF, sum = 0
955 22:10:35.492570 6, 0xFFFF, sum = 0
956 22:10:35.494926 7, 0xFFFF, sum = 0
957 22:10:35.495352 8, 0xFFFF, sum = 0
958 22:10:35.498636 9, 0x0, sum = 1
959 22:10:35.499101 10, 0x0, sum = 2
960 22:10:35.502110 11, 0x0, sum = 3
961 22:10:35.502542 12, 0x0, sum = 4
962 22:10:35.505410 best_step = 10
963 22:10:35.505931
964 22:10:35.506305 ==
965 22:10:35.508791 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:10:35.512297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 22:10:35.512814 ==
968 22:10:35.513237 RX Vref Scan: 1
969 22:10:35.513646
970 22:10:35.515439 Set Vref Range= 32 -> 127
971 22:10:35.515944
972 22:10:35.519085 RX Vref 32 -> 127, step: 1
973 22:10:35.519697
974 22:10:35.522108 RX Delay -95 -> 252, step: 8
975 22:10:35.522734
976 22:10:35.525099 Set Vref, RX VrefLevel [Byte0]: 32
977 22:10:35.528484 [Byte1]: 32
978 22:10:35.529115
979 22:10:35.532235 Set Vref, RX VrefLevel [Byte0]: 33
980 22:10:35.535392 [Byte1]: 33
981 22:10:35.535943
982 22:10:35.539607 Set Vref, RX VrefLevel [Byte0]: 34
983 22:10:35.543064 [Byte1]: 34
984 22:10:35.543562
985 22:10:35.546255 Set Vref, RX VrefLevel [Byte0]: 35
986 22:10:35.549330 [Byte1]: 35
987 22:10:35.553538
988 22:10:35.553996 Set Vref, RX VrefLevel [Byte0]: 36
989 22:10:35.556763 [Byte1]: 36
990 22:10:35.560942
991 22:10:35.561375 Set Vref, RX VrefLevel [Byte0]: 37
992 22:10:35.564381 [Byte1]: 37
993 22:10:35.569351
994 22:10:35.569779 Set Vref, RX VrefLevel [Byte0]: 38
995 22:10:35.572373 [Byte1]: 38
996 22:10:35.576662
997 22:10:35.577352 Set Vref, RX VrefLevel [Byte0]: 39
998 22:10:35.580332 [Byte1]: 39
999 22:10:35.584736
1000 22:10:35.585238 Set Vref, RX VrefLevel [Byte0]: 40
1001 22:10:35.587811 [Byte1]: 40
1002 22:10:35.591760
1003 22:10:35.592171 Set Vref, RX VrefLevel [Byte0]: 41
1004 22:10:35.595248 [Byte1]: 41
1005 22:10:35.599123
1006 22:10:35.599587 Set Vref, RX VrefLevel [Byte0]: 42
1007 22:10:35.602275 [Byte1]: 42
1008 22:10:35.606603
1009 22:10:35.607069 Set Vref, RX VrefLevel [Byte0]: 43
1010 22:10:35.609926 [Byte1]: 43
1011 22:10:35.614120
1012 22:10:35.614594 Set Vref, RX VrefLevel [Byte0]: 44
1013 22:10:35.617292 [Byte1]: 44
1014 22:10:35.621927
1015 22:10:35.622381 Set Vref, RX VrefLevel [Byte0]: 45
1016 22:10:35.624902 [Byte1]: 45
1017 22:10:35.629232
1018 22:10:35.629653 Set Vref, RX VrefLevel [Byte0]: 46
1019 22:10:35.632754 [Byte1]: 46
1020 22:10:35.637544
1021 22:10:35.637983 Set Vref, RX VrefLevel [Byte0]: 47
1022 22:10:35.640495 [Byte1]: 47
1023 22:10:35.644555
1024 22:10:35.645064 Set Vref, RX VrefLevel [Byte0]: 48
1025 22:10:35.647821 [Byte1]: 48
1026 22:10:35.652045
1027 22:10:35.652487 Set Vref, RX VrefLevel [Byte0]: 49
1028 22:10:35.655770 [Byte1]: 49
1029 22:10:35.659896
1030 22:10:35.660282 Set Vref, RX VrefLevel [Byte0]: 50
1031 22:10:35.663224 [Byte1]: 50
1032 22:10:35.667313
1033 22:10:35.667725 Set Vref, RX VrefLevel [Byte0]: 51
1034 22:10:35.670669 [Byte1]: 51
1035 22:10:35.674857
1036 22:10:35.675334 Set Vref, RX VrefLevel [Byte0]: 52
1037 22:10:35.678430 [Byte1]: 52
1038 22:10:35.682830
1039 22:10:35.683335 Set Vref, RX VrefLevel [Byte0]: 53
1040 22:10:35.685730 [Byte1]: 53
1041 22:10:35.690715
1042 22:10:35.691216 Set Vref, RX VrefLevel [Byte0]: 54
1043 22:10:35.693486 [Byte1]: 54
1044 22:10:35.697713
1045 22:10:35.698119 Set Vref, RX VrefLevel [Byte0]: 55
1046 22:10:35.701053 [Byte1]: 55
1047 22:10:35.705454
1048 22:10:35.705859 Set Vref, RX VrefLevel [Byte0]: 56
1049 22:10:35.708487 [Byte1]: 56
1050 22:10:35.713409
1051 22:10:35.713938 Set Vref, RX VrefLevel [Byte0]: 57
1052 22:10:35.716167 [Byte1]: 57
1053 22:10:35.720274
1054 22:10:35.720727 Set Vref, RX VrefLevel [Byte0]: 58
1055 22:10:35.723740 [Byte1]: 58
1056 22:10:35.728238
1057 22:10:35.728746 Set Vref, RX VrefLevel [Byte0]: 59
1058 22:10:35.731771 [Byte1]: 59
1059 22:10:35.735916
1060 22:10:35.736331 Set Vref, RX VrefLevel [Byte0]: 60
1061 22:10:35.738828 [Byte1]: 60
1062 22:10:35.743593
1063 22:10:35.744179 Set Vref, RX VrefLevel [Byte0]: 61
1064 22:10:35.746390 [Byte1]: 61
1065 22:10:35.751376
1066 22:10:35.751846 Set Vref, RX VrefLevel [Byte0]: 62
1067 22:10:35.754177 [Byte1]: 62
1068 22:10:35.758631
1069 22:10:35.759096 Set Vref, RX VrefLevel [Byte0]: 63
1070 22:10:35.761874 [Byte1]: 63
1071 22:10:35.766134
1072 22:10:35.766540 Set Vref, RX VrefLevel [Byte0]: 64
1073 22:10:35.769174 [Byte1]: 64
1074 22:10:35.773883
1075 22:10:35.774296 Set Vref, RX VrefLevel [Byte0]: 65
1076 22:10:35.776802 [Byte1]: 65
1077 22:10:35.781524
1078 22:10:35.781934 Set Vref, RX VrefLevel [Byte0]: 66
1079 22:10:35.785266 [Byte1]: 66
1080 22:10:35.788603
1081 22:10:35.789076 Set Vref, RX VrefLevel [Byte0]: 67
1082 22:10:35.792266 [Byte1]: 67
1083 22:10:35.796559
1084 22:10:35.797023 Set Vref, RX VrefLevel [Byte0]: 68
1085 22:10:35.799501 [Byte1]: 68
1086 22:10:35.804272
1087 22:10:35.804735 Set Vref, RX VrefLevel [Byte0]: 69
1088 22:10:35.807721 [Byte1]: 69
1089 22:10:35.812106
1090 22:10:35.812520 Set Vref, RX VrefLevel [Byte0]: 70
1091 22:10:35.815176 [Byte1]: 70
1092 22:10:35.819313
1093 22:10:35.819727 Set Vref, RX VrefLevel [Byte0]: 71
1094 22:10:35.822860 [Byte1]: 71
1095 22:10:35.826905
1096 22:10:35.827320 Set Vref, RX VrefLevel [Byte0]: 72
1097 22:10:35.829968 [Byte1]: 72
1098 22:10:35.834417
1099 22:10:35.834875 Set Vref, RX VrefLevel [Byte0]: 73
1100 22:10:35.837638 [Byte1]: 73
1101 22:10:35.842125
1102 22:10:35.842542 Set Vref, RX VrefLevel [Byte0]: 74
1103 22:10:35.844863 [Byte1]: 74
1104 22:10:35.849311
1105 22:10:35.849397 Set Vref, RX VrefLevel [Byte0]: 75
1106 22:10:35.852321 [Byte1]: 75
1107 22:10:35.856618
1108 22:10:35.856737 Set Vref, RX VrefLevel [Byte0]: 76
1109 22:10:35.860312 [Byte1]: 76
1110 22:10:35.864594
1111 22:10:35.864689 Final RX Vref Byte 0 = 59 to rank0
1112 22:10:35.868254 Final RX Vref Byte 1 = 57 to rank0
1113 22:10:35.870985 Final RX Vref Byte 0 = 59 to rank1
1114 22:10:35.874364 Final RX Vref Byte 1 = 57 to rank1==
1115 22:10:35.878174 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 22:10:35.881493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 22:10:35.884982 ==
1118 22:10:35.885395 DQS Delay:
1119 22:10:35.885719 DQS0 = 0, DQS1 = 0
1120 22:10:35.888364 DQM Delay:
1121 22:10:35.888939 DQM0 = 87, DQM1 = 78
1122 22:10:35.891972 DQ Delay:
1123 22:10:35.892419 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1124 22:10:35.895022 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =92
1125 22:10:35.898202 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1126 22:10:35.901695 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1127 22:10:35.902242
1128 22:10:35.905224
1129 22:10:35.911660 [DQSOSCAuto] RK0, (LSB)MR18= 0x2911, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1130 22:10:35.915060 CH0 RK0: MR19=606, MR18=2911
1131 22:10:35.922955 CH0_RK0: MR19=0x606, MR18=0x2911, DQSOSC=399, MR23=63, INC=92, DEC=61
1132 22:10:35.923369
1133 22:10:35.924838 ----->DramcWriteLeveling(PI) begin...
1134 22:10:35.925328 ==
1135 22:10:35.928417 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 22:10:35.931686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 22:10:35.932096 ==
1138 22:10:35.935325 Write leveling (Byte 0): 31 => 31
1139 22:10:35.938342 Write leveling (Byte 1): 30 => 30
1140 22:10:35.941776 DramcWriteLeveling(PI) end<-----
1141 22:10:35.942245
1142 22:10:35.942588 ==
1143 22:10:35.945229 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 22:10:35.948360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 22:10:35.948939 ==
1146 22:10:35.951698 [Gating] SW mode calibration
1147 22:10:35.958360 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 22:10:35.964950 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 22:10:35.968495 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 22:10:35.971715 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1151 22:10:35.975199 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 22:10:36.022425 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 22:10:36.022542 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 22:10:36.022927 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 22:10:36.023187 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:10:36.023274 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:10:36.023355 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:10:36.023419 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:10:36.023492 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:10:36.023738 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:10:36.023828 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:10:36.041285 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:10:36.041723 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:10:36.042531 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:10:36.042873 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:10:36.045037 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 22:10:36.048689 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1168 22:10:36.052208 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:10:36.055234 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:10:36.062141 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:10:36.065293 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:10:36.068637 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:10:36.075247 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:10:36.078300 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:10:36.081990 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
1176 22:10:36.085112 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
1177 22:10:36.092231 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 22:10:36.095230 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 22:10:36.099088 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 22:10:36.105750 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 22:10:36.108549 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 22:10:36.112306 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1183 22:10:36.118731 0 10 8 | B1->B0 | 3131 2727 | 1 0 | (1 1) (0 0)
1184 22:10:36.122166 0 10 12 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
1185 22:10:36.125370 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 22:10:36.132275 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 22:10:36.135260 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:10:36.138453 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:10:36.141848 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 22:10:36.149350 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1191 22:10:36.152907 0 11 8 | B1->B0 | 2d2d 4242 | 0 0 | (0 0) (0 0)
1192 22:10:36.157083 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1193 22:10:36.160788 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 22:10:36.163899 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 22:10:36.170982 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 22:10:36.174269 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 22:10:36.177967 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 22:10:36.184591 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1199 22:10:36.188070 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1200 22:10:36.191639 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 22:10:36.194682 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 22:10:36.201600 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 22:10:36.205019 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 22:10:36.208532 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:10:36.215020 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:10:36.218780 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:10:36.221710 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:10:36.228396 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:10:36.231788 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:10:36.235333 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:10:36.241673 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:10:36.245169 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:10:36.248897 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:10:36.255419 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:10:36.258460 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1216 22:10:36.261797 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 22:10:36.265674 Total UI for P1: 0, mck2ui 16
1218 22:10:36.269159 best dqsien dly found for B0: ( 0, 14, 8)
1219 22:10:36.272345 Total UI for P1: 0, mck2ui 16
1220 22:10:36.275485 best dqsien dly found for B1: ( 0, 14, 8)
1221 22:10:36.278745 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1222 22:10:36.282357 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 22:10:36.282778
1224 22:10:36.285524 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 22:10:36.289038 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 22:10:36.291962 [Gating] SW calibration Done
1227 22:10:36.292586 ==
1228 22:10:36.295401 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 22:10:36.299030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 22:10:36.302564 ==
1231 22:10:36.302990 RX Vref Scan: 0
1232 22:10:36.303424
1233 22:10:36.306152 RX Vref 0 -> 0, step: 1
1234 22:10:36.306584
1235 22:10:36.307020 RX Delay -130 -> 252, step: 16
1236 22:10:36.312657 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1237 22:10:36.316087 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1238 22:10:36.319354 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1239 22:10:36.322970 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1240 22:10:36.325995 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1241 22:10:36.332777 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1242 22:10:36.336147 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1243 22:10:36.339611 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1244 22:10:36.342725 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 22:10:36.346610 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1246 22:10:36.349504 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1247 22:10:36.356277 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1248 22:10:36.359616 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1249 22:10:36.363472 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1250 22:10:36.366361 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1251 22:10:36.373089 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1252 22:10:36.373516 ==
1253 22:10:36.376599 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 22:10:36.380114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 22:10:36.380586 ==
1256 22:10:36.381061 DQS Delay:
1257 22:10:36.383215 DQS0 = 0, DQS1 = 0
1258 22:10:36.383640 DQM Delay:
1259 22:10:36.386947 DQM0 = 87, DQM1 = 76
1260 22:10:36.387375 DQ Delay:
1261 22:10:36.389909 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1262 22:10:36.393355 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1263 22:10:36.396922 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1264 22:10:36.400210 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1265 22:10:36.400656
1266 22:10:36.401174
1267 22:10:36.401703 ==
1268 22:10:36.403390 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 22:10:36.406741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 22:10:36.407159 ==
1271 22:10:36.407483
1272 22:10:36.407786
1273 22:10:36.410517 TX Vref Scan disable
1274 22:10:36.413882 == TX Byte 0 ==
1275 22:10:36.417342 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1276 22:10:36.420390 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1277 22:10:36.423620 == TX Byte 1 ==
1278 22:10:36.426876 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1279 22:10:36.431045 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1280 22:10:36.431564 ==
1281 22:10:36.433995 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 22:10:36.437224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 22:10:36.437644 ==
1284 22:10:36.451271 TX Vref=22, minBit 3, minWin=27, winSum=445
1285 22:10:36.454690 TX Vref=24, minBit 9, minWin=27, winSum=451
1286 22:10:36.458375 TX Vref=26, minBit 3, minWin=27, winSum=451
1287 22:10:36.461945 TX Vref=28, minBit 8, minWin=27, winSum=450
1288 22:10:36.465022 TX Vref=30, minBit 5, minWin=28, winSum=459
1289 22:10:36.468308 TX Vref=32, minBit 5, minWin=28, winSum=458
1290 22:10:36.475113 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
1291 22:10:36.475627
1292 22:10:36.478364 Final TX Range 1 Vref 30
1293 22:10:36.478828
1294 22:10:36.479170 ==
1295 22:10:36.481816 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 22:10:36.484907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 22:10:36.485320 ==
1298 22:10:36.485642
1299 22:10:36.485939
1300 22:10:36.488503 TX Vref Scan disable
1301 22:10:36.491615 == TX Byte 0 ==
1302 22:10:36.495136 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1303 22:10:36.498233 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1304 22:10:36.501753 == TX Byte 1 ==
1305 22:10:36.505404 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1306 22:10:36.508750 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1307 22:10:36.509169
1308 22:10:36.511940 [DATLAT]
1309 22:10:36.512479 Freq=800, CH0 RK1
1310 22:10:36.512874
1311 22:10:36.515456 DATLAT Default: 0xa
1312 22:10:36.515864 0, 0xFFFF, sum = 0
1313 22:10:36.518842 1, 0xFFFF, sum = 0
1314 22:10:36.519377 2, 0xFFFF, sum = 0
1315 22:10:36.522480 3, 0xFFFF, sum = 0
1316 22:10:36.522998 4, 0xFFFF, sum = 0
1317 22:10:36.525100 5, 0xFFFF, sum = 0
1318 22:10:36.525610 6, 0xFFFF, sum = 0
1319 22:10:36.528483 7, 0xFFFF, sum = 0
1320 22:10:36.528954 8, 0xFFFF, sum = 0
1321 22:10:36.532115 9, 0x0, sum = 1
1322 22:10:36.532529 10, 0x0, sum = 2
1323 22:10:36.535302 11, 0x0, sum = 3
1324 22:10:36.535716 12, 0x0, sum = 4
1325 22:10:36.538790 best_step = 10
1326 22:10:36.539194
1327 22:10:36.539515 ==
1328 22:10:36.541896 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 22:10:36.545536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 22:10:36.545947 ==
1331 22:10:36.546389 RX Vref Scan: 0
1332 22:10:36.548877
1333 22:10:36.549285 RX Vref 0 -> 0, step: 1
1334 22:10:36.549606
1335 22:10:36.552317 RX Delay -95 -> 252, step: 8
1336 22:10:36.555576 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1337 22:10:36.562184 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 22:10:36.565640 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1339 22:10:36.568756 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1340 22:10:36.572327 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 22:10:36.575392 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 22:10:36.582475 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 22:10:36.585599 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 22:10:36.589287 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 22:10:36.592202 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 22:10:36.595731 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 22:10:36.599402 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 22:10:36.605976 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1349 22:10:36.609558 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1350 22:10:36.612896 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 22:10:36.616209 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1352 22:10:36.616622 ==
1353 22:10:36.619402 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 22:10:36.626348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 22:10:36.626766 ==
1356 22:10:36.627090 DQS Delay:
1357 22:10:36.629324 DQS0 = 0, DQS1 = 0
1358 22:10:36.629730 DQM Delay:
1359 22:10:36.630057 DQM0 = 87, DQM1 = 77
1360 22:10:36.632737 DQ Delay:
1361 22:10:36.635695 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1362 22:10:36.639371 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1363 22:10:36.639783 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1364 22:10:36.646088 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1365 22:10:36.646570
1366 22:10:36.646906
1367 22:10:36.652783 [DQSOSCAuto] RK1, (LSB)MR18= 0x361f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1368 22:10:36.656175 CH0 RK1: MR19=606, MR18=361F
1369 22:10:36.662940 CH0_RK1: MR19=0x606, MR18=0x361F, DQSOSC=396, MR23=63, INC=94, DEC=62
1370 22:10:36.665994 [RxdqsGatingPostProcess] freq 800
1371 22:10:36.669851 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 22:10:36.672707 Pre-setting of DQS Precalculation
1373 22:10:36.676365 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 22:10:36.679488 ==
1375 22:10:36.683228 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 22:10:36.686260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 22:10:36.686677 ==
1378 22:10:36.690142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 22:10:36.696359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 22:10:36.706401 [CA 0] Center 36 (6~67) winsize 62
1381 22:10:36.709405 [CA 1] Center 36 (6~67) winsize 62
1382 22:10:36.712782 [CA 2] Center 34 (4~64) winsize 61
1383 22:10:36.716595 [CA 3] Center 33 (3~64) winsize 62
1384 22:10:36.719713 [CA 4] Center 34 (3~65) winsize 63
1385 22:10:36.723286 [CA 5] Center 33 (3~64) winsize 62
1386 22:10:36.723707
1387 22:10:36.726223 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 22:10:36.726688
1389 22:10:36.729672 [CATrainingPosCal] consider 1 rank data
1390 22:10:36.733194 u2DelayCellTimex100 = 270/100 ps
1391 22:10:36.736471 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 22:10:36.739901 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1393 22:10:36.743210 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1394 22:10:36.749741 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 22:10:36.753354 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1396 22:10:36.757036 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 22:10:36.757522
1398 22:10:36.760253 CA PerBit enable=1, Macro0, CA PI delay=33
1399 22:10:36.760866
1400 22:10:36.763445 [CBTSetCACLKResult] CA Dly = 33
1401 22:10:36.763905 CS Dly: 5 (0~36)
1402 22:10:36.764263 ==
1403 22:10:36.766569 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 22:10:36.773357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 22:10:36.773842 ==
1406 22:10:36.776557 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 22:10:36.782948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 22:10:36.792421 [CA 0] Center 36 (6~67) winsize 62
1409 22:10:36.795755 [CA 1] Center 36 (6~67) winsize 62
1410 22:10:36.799508 [CA 2] Center 34 (4~64) winsize 61
1411 22:10:36.802716 [CA 3] Center 33 (3~64) winsize 62
1412 22:10:36.806267 [CA 4] Center 34 (3~65) winsize 63
1413 22:10:36.809067 [CA 5] Center 33 (3~64) winsize 62
1414 22:10:36.809480
1415 22:10:36.812660 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 22:10:36.813066
1417 22:10:36.817069 [CATrainingPosCal] consider 2 rank data
1418 22:10:36.820269 u2DelayCellTimex100 = 270/100 ps
1419 22:10:36.823695 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1420 22:10:36.827191 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1421 22:10:36.830997 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1422 22:10:36.834691 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 22:10:36.838777 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1424 22:10:36.841797 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 22:10:36.842212
1426 22:10:36.845697 CA PerBit enable=1, Macro0, CA PI delay=33
1427 22:10:36.846110
1428 22:10:36.849428 [CBTSetCACLKResult] CA Dly = 33
1429 22:10:36.849965 CS Dly: 5 (0~37)
1430 22:10:36.850314
1431 22:10:36.852319 ----->DramcWriteLeveling(PI) begin...
1432 22:10:36.852823 ==
1433 22:10:36.856101 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 22:10:36.862761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 22:10:36.863278 ==
1436 22:10:36.865903 Write leveling (Byte 0): 29 => 29
1437 22:10:36.869733 Write leveling (Byte 1): 31 => 31
1438 22:10:36.870246 DramcWriteLeveling(PI) end<-----
1439 22:10:36.870572
1440 22:10:36.872934 ==
1441 22:10:36.876241 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 22:10:36.879329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 22:10:36.879864 ==
1444 22:10:36.882740 [Gating] SW mode calibration
1445 22:10:36.890062 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 22:10:36.892647 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 22:10:36.899835 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 22:10:36.903555 0 6 4 | B1->B0 | 2423 2323 | 1 0 | (1 1) (1 1)
1449 22:10:36.906779 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1450 22:10:36.909370 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 22:10:36.916386 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 22:10:36.920064 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1453 22:10:36.923000 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:10:36.930136 0 6 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1455 22:10:36.933291 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:10:36.936778 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:10:36.943172 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:10:36.946990 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:10:36.949945 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:10:36.956601 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1461 22:10:36.959684 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1462 22:10:36.962989 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1463 22:10:36.969960 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1464 22:10:36.973210 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1465 22:10:36.976584 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
1466 22:10:36.980265 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1467 22:10:36.986804 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:10:36.990487 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:10:36.993418 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:10:37.000320 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:10:37.003680 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1472 22:10:37.006766 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:10:37.013372 0 9 8 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
1474 22:10:37.017167 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 22:10:37.020570 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1476 22:10:37.027253 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 22:10:37.030738 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1478 22:10:37.033849 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 22:10:37.037531 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 22:10:37.044027 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 0)
1481 22:10:37.047044 0 10 8 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
1482 22:10:37.050436 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:10:37.057282 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 22:10:37.060789 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 22:10:37.063847 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:10:37.070831 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:10:37.074407 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:10:37.077086 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:10:37.083977 0 11 8 | B1->B0 | 3232 3232 | 0 0 | (0 0) (0 0)
1490 22:10:37.087436 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 22:10:37.090695 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 22:10:37.097439 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 22:10:37.100359 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 22:10:37.103871 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 22:10:37.107410 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 22:10:37.113811 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 22:10:37.117515 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1498 22:10:37.120478 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 22:10:37.127861 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 22:10:37.130905 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 22:10:37.134105 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:10:37.141245 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:10:37.144541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:10:37.147601 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:10:37.154230 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:10:37.157976 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:10:37.161473 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:10:37.164374 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:10:37.171094 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:10:37.174303 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:10:37.178077 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:10:37.184780 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:10:37.187995 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1514 22:10:37.191402 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 22:10:37.194873 Total UI for P1: 0, mck2ui 16
1516 22:10:37.198007 best dqsien dly found for B0: ( 0, 14, 8)
1517 22:10:37.201553 Total UI for P1: 0, mck2ui 16
1518 22:10:37.204782 best dqsien dly found for B1: ( 0, 14, 8)
1519 22:10:37.208080 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1520 22:10:37.211515 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1521 22:10:37.211932
1522 22:10:37.214726 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1523 22:10:37.221726 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1524 22:10:37.222143 [Gating] SW calibration Done
1525 22:10:37.222472 ==
1526 22:10:37.225371 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 22:10:37.231492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 22:10:37.231904 ==
1529 22:10:37.232277 RX Vref Scan: 0
1530 22:10:37.232720
1531 22:10:37.235043 RX Vref 0 -> 0, step: 1
1532 22:10:37.235488
1533 22:10:37.238358 RX Delay -130 -> 252, step: 16
1534 22:10:37.241547 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1535 22:10:37.244759 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1536 22:10:37.248537 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1537 22:10:37.251726 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1538 22:10:37.258537 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1539 22:10:37.262003 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1540 22:10:37.265595 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1541 22:10:37.268825 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1542 22:10:37.271704 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1543 22:10:37.278822 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1544 22:10:37.282167 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1545 22:10:37.285323 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1546 22:10:37.289003 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1547 22:10:37.292137 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1548 22:10:37.298768 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1549 22:10:37.302328 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1550 22:10:37.302780 ==
1551 22:10:37.305184 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 22:10:37.308858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 22:10:37.309277 ==
1554 22:10:37.312281 DQS Delay:
1555 22:10:37.312733 DQS0 = 0, DQS1 = 0
1556 22:10:37.313073 DQM Delay:
1557 22:10:37.315393 DQM0 = 85, DQM1 = 75
1558 22:10:37.315805 DQ Delay:
1559 22:10:37.318834 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1560 22:10:37.322507 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =77
1561 22:10:37.325462 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
1562 22:10:37.329344 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1563 22:10:37.329928
1564 22:10:37.330271
1565 22:10:37.330698 ==
1566 22:10:37.332402 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 22:10:37.335918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 22:10:37.339177 ==
1569 22:10:37.339589
1570 22:10:37.339942
1571 22:10:37.340431 TX Vref Scan disable
1572 22:10:37.342593 == TX Byte 0 ==
1573 22:10:37.345828 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1574 22:10:37.349025 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1575 22:10:37.352441 == TX Byte 1 ==
1576 22:10:37.355591 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1577 22:10:37.359034 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1578 22:10:37.359449 ==
1579 22:10:37.362649 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 22:10:37.369115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 22:10:37.369559 ==
1582 22:10:37.381295 TX Vref=22, minBit 8, minWin=26, winSum=434
1583 22:10:37.384565 TX Vref=24, minBit 8, minWin=26, winSum=441
1584 22:10:37.387557 TX Vref=26, minBit 8, minWin=27, winSum=448
1585 22:10:37.391279 TX Vref=28, minBit 3, minWin=27, winSum=452
1586 22:10:37.394910 TX Vref=30, minBit 5, minWin=28, winSum=456
1587 22:10:37.398444 TX Vref=32, minBit 13, minWin=27, winSum=453
1588 22:10:37.405534 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 30
1589 22:10:37.406124
1590 22:10:37.408504 Final TX Range 1 Vref 30
1591 22:10:37.409089
1592 22:10:37.409493 ==
1593 22:10:37.412215 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 22:10:37.415223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 22:10:37.415850 ==
1596 22:10:37.416279
1597 22:10:37.416799
1598 22:10:37.418573 TX Vref Scan disable
1599 22:10:37.421945 == TX Byte 0 ==
1600 22:10:37.425617 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1601 22:10:37.428649 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1602 22:10:37.432131 == TX Byte 1 ==
1603 22:10:37.435634 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1604 22:10:37.438959 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1605 22:10:37.439375
1606 22:10:37.439702 [DATLAT]
1607 22:10:37.442306 Freq=800, CH1 RK0
1608 22:10:37.442816
1609 22:10:37.445448 DATLAT Default: 0xa
1610 22:10:37.445864 0, 0xFFFF, sum = 0
1611 22:10:37.449040 1, 0xFFFF, sum = 0
1612 22:10:37.449464 2, 0xFFFF, sum = 0
1613 22:10:37.452278 3, 0xFFFF, sum = 0
1614 22:10:37.452758 4, 0xFFFF, sum = 0
1615 22:10:37.455540 5, 0xFFFF, sum = 0
1616 22:10:37.455963 6, 0xFFFF, sum = 0
1617 22:10:37.459331 7, 0xFFFF, sum = 0
1618 22:10:37.459748 8, 0xFFFF, sum = 0
1619 22:10:37.463141 9, 0x0, sum = 1
1620 22:10:37.463654 10, 0x0, sum = 2
1621 22:10:37.463991 11, 0x0, sum = 3
1622 22:10:37.466605 12, 0x0, sum = 4
1623 22:10:37.467117 best_step = 10
1624 22:10:37.467619
1625 22:10:37.468094 ==
1626 22:10:37.469576 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 22:10:37.476329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 22:10:37.476834 ==
1629 22:10:37.477181 RX Vref Scan: 1
1630 22:10:37.477503
1631 22:10:37.479633 Set Vref Range= 32 -> 127
1632 22:10:37.480117
1633 22:10:37.482670 RX Vref 32 -> 127, step: 1
1634 22:10:37.483098
1635 22:10:37.486341 RX Delay -111 -> 252, step: 8
1636 22:10:37.487030
1637 22:10:37.489803 Set Vref, RX VrefLevel [Byte0]: 32
1638 22:10:37.490248 [Byte1]: 32
1639 22:10:37.494227
1640 22:10:37.494664 Set Vref, RX VrefLevel [Byte0]: 33
1641 22:10:37.497338 [Byte1]: 33
1642 22:10:37.501533
1643 22:10:37.501978 Set Vref, RX VrefLevel [Byte0]: 34
1644 22:10:37.505155 [Byte1]: 34
1645 22:10:37.509453
1646 22:10:37.509895 Set Vref, RX VrefLevel [Byte0]: 35
1647 22:10:37.512491 [Byte1]: 35
1648 22:10:37.516794
1649 22:10:37.517209 Set Vref, RX VrefLevel [Byte0]: 36
1650 22:10:37.520384 [Byte1]: 36
1651 22:10:37.524509
1652 22:10:37.525032 Set Vref, RX VrefLevel [Byte0]: 37
1653 22:10:37.527991 [Byte1]: 37
1654 22:10:37.532438
1655 22:10:37.533028 Set Vref, RX VrefLevel [Byte0]: 38
1656 22:10:37.535907 [Byte1]: 38
1657 22:10:37.540002
1658 22:10:37.540445 Set Vref, RX VrefLevel [Byte0]: 39
1659 22:10:37.543244 [Byte1]: 39
1660 22:10:37.547400
1661 22:10:37.547481 Set Vref, RX VrefLevel [Byte0]: 40
1662 22:10:37.550549 [Byte1]: 40
1663 22:10:37.554966
1664 22:10:37.555122 Set Vref, RX VrefLevel [Byte0]: 41
1665 22:10:37.558240 [Byte1]: 41
1666 22:10:37.562671
1667 22:10:37.562827 Set Vref, RX VrefLevel [Byte0]: 42
1668 22:10:37.565998 [Byte1]: 42
1669 22:10:37.570606
1670 22:10:37.570744 Set Vref, RX VrefLevel [Byte0]: 43
1671 22:10:37.573626 [Byte1]: 43
1672 22:10:37.578006
1673 22:10:37.578121 Set Vref, RX VrefLevel [Byte0]: 44
1674 22:10:37.581364 [Byte1]: 44
1675 22:10:37.585574
1676 22:10:37.586003 Set Vref, RX VrefLevel [Byte0]: 45
1677 22:10:37.589241 [Byte1]: 45
1678 22:10:37.593303
1679 22:10:37.593717 Set Vref, RX VrefLevel [Byte0]: 46
1680 22:10:37.596848 [Byte1]: 46
1681 22:10:37.601245
1682 22:10:37.601718 Set Vref, RX VrefLevel [Byte0]: 47
1683 22:10:37.604179 [Byte1]: 47
1684 22:10:37.608991
1685 22:10:37.609400 Set Vref, RX VrefLevel [Byte0]: 48
1686 22:10:37.611987 [Byte1]: 48
1687 22:10:37.616391
1688 22:10:37.616905 Set Vref, RX VrefLevel [Byte0]: 49
1689 22:10:37.619558 [Byte1]: 49
1690 22:10:37.624371
1691 22:10:37.624821 Set Vref, RX VrefLevel [Byte0]: 50
1692 22:10:37.627434 [Byte1]: 50
1693 22:10:37.632032
1694 22:10:37.632442 Set Vref, RX VrefLevel [Byte0]: 51
1695 22:10:37.635081 [Byte1]: 51
1696 22:10:37.639304
1697 22:10:37.639715 Set Vref, RX VrefLevel [Byte0]: 52
1698 22:10:37.642895 [Byte1]: 52
1699 22:10:37.646723
1700 22:10:37.647137 Set Vref, RX VrefLevel [Byte0]: 53
1701 22:10:37.650083 [Byte1]: 53
1702 22:10:37.654431
1703 22:10:37.654860 Set Vref, RX VrefLevel [Byte0]: 54
1704 22:10:37.657931 [Byte1]: 54
1705 22:10:37.662056
1706 22:10:37.662469 Set Vref, RX VrefLevel [Byte0]: 55
1707 22:10:37.665781 [Byte1]: 55
1708 22:10:37.669978
1709 22:10:37.670392 Set Vref, RX VrefLevel [Byte0]: 56
1710 22:10:37.673074 [Byte1]: 56
1711 22:10:37.677268
1712 22:10:37.677816 Set Vref, RX VrefLevel [Byte0]: 57
1713 22:10:37.680787 [Byte1]: 57
1714 22:10:37.685477
1715 22:10:37.686097 Set Vref, RX VrefLevel [Byte0]: 58
1716 22:10:37.688152 [Byte1]: 58
1717 22:10:37.692864
1718 22:10:37.693275 Set Vref, RX VrefLevel [Byte0]: 59
1719 22:10:37.696074 [Byte1]: 59
1720 22:10:37.700293
1721 22:10:37.700748 Set Vref, RX VrefLevel [Byte0]: 60
1722 22:10:37.703567 [Byte1]: 60
1723 22:10:37.708338
1724 22:10:37.708781 Set Vref, RX VrefLevel [Byte0]: 61
1725 22:10:37.711494 [Byte1]: 61
1726 22:10:37.715738
1727 22:10:37.716287 Set Vref, RX VrefLevel [Byte0]: 62
1728 22:10:37.719059 [Byte1]: 62
1729 22:10:37.723398
1730 22:10:37.723912 Set Vref, RX VrefLevel [Byte0]: 63
1731 22:10:37.726372 [Byte1]: 63
1732 22:10:37.731214
1733 22:10:37.731633 Set Vref, RX VrefLevel [Byte0]: 64
1734 22:10:37.734158 [Byte1]: 64
1735 22:10:37.739009
1736 22:10:37.739561 Set Vref, RX VrefLevel [Byte0]: 65
1737 22:10:37.741943 [Byte1]: 65
1738 22:10:37.746156
1739 22:10:37.746661 Set Vref, RX VrefLevel [Byte0]: 66
1740 22:10:37.749296 [Byte1]: 66
1741 22:10:37.754094
1742 22:10:37.754502 Set Vref, RX VrefLevel [Byte0]: 67
1743 22:10:37.757009 [Byte1]: 67
1744 22:10:37.761905
1745 22:10:37.762374 Set Vref, RX VrefLevel [Byte0]: 68
1746 22:10:37.765056 [Byte1]: 68
1747 22:10:37.769080
1748 22:10:37.769561 Set Vref, RX VrefLevel [Byte0]: 69
1749 22:10:37.772739 [Byte1]: 69
1750 22:10:37.777062
1751 22:10:37.777587 Set Vref, RX VrefLevel [Byte0]: 70
1752 22:10:37.780364 [Byte1]: 70
1753 22:10:37.784414
1754 22:10:37.785071 Set Vref, RX VrefLevel [Byte0]: 71
1755 22:10:37.788111 [Byte1]: 71
1756 22:10:37.792202
1757 22:10:37.792885 Set Vref, RX VrefLevel [Byte0]: 72
1758 22:10:37.795613 [Byte1]: 72
1759 22:10:37.799536
1760 22:10:37.800194 Set Vref, RX VrefLevel [Byte0]: 73
1761 22:10:37.802961 [Byte1]: 73
1762 22:10:37.807303
1763 22:10:37.807792 Set Vref, RX VrefLevel [Byte0]: 74
1764 22:10:37.810629 [Byte1]: 74
1765 22:10:37.815230
1766 22:10:37.815645 Set Vref, RX VrefLevel [Byte0]: 75
1767 22:10:37.818290 [Byte1]: 75
1768 22:10:37.822769
1769 22:10:37.823348 Set Vref, RX VrefLevel [Byte0]: 76
1770 22:10:37.826359 [Byte1]: 76
1771 22:10:37.830686
1772 22:10:37.831097 Set Vref, RX VrefLevel [Byte0]: 77
1773 22:10:37.833920 [Byte1]: 77
1774 22:10:37.838123
1775 22:10:37.838534 Final RX Vref Byte 0 = 66 to rank0
1776 22:10:37.841725 Final RX Vref Byte 1 = 58 to rank0
1777 22:10:37.844632 Final RX Vref Byte 0 = 66 to rank1
1778 22:10:37.848120 Final RX Vref Byte 1 = 58 to rank1==
1779 22:10:37.851839 Dram Type= 6, Freq= 0, CH_1, rank 0
1780 22:10:37.854815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 22:10:37.858400 ==
1782 22:10:37.858916 DQS Delay:
1783 22:10:37.859337 DQS0 = 0, DQS1 = 0
1784 22:10:37.861738 DQM Delay:
1785 22:10:37.862269 DQM0 = 83, DQM1 = 74
1786 22:10:37.864776 DQ Delay:
1787 22:10:37.865285 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1788 22:10:37.868488 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1789 22:10:37.871556 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1790 22:10:37.875221 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1791 22:10:37.875631
1792 22:10:37.878306
1793 22:10:37.884968 [DQSOSCAuto] RK0, (LSB)MR18= 0x28fc, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
1794 22:10:37.888404 CH1 RK0: MR19=605, MR18=28FC
1795 22:10:37.895227 CH1_RK0: MR19=0x605, MR18=0x28FC, DQSOSC=399, MR23=63, INC=92, DEC=61
1796 22:10:37.895637
1797 22:10:37.898316 ----->DramcWriteLeveling(PI) begin...
1798 22:10:37.898847 ==
1799 22:10:37.901647 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 22:10:37.905199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 22:10:37.905614 ==
1802 22:10:37.908296 Write leveling (Byte 0): 28 => 28
1803 22:10:37.911719 Write leveling (Byte 1): 28 => 28
1804 22:10:37.914859 DramcWriteLeveling(PI) end<-----
1805 22:10:37.915264
1806 22:10:37.915584 ==
1807 22:10:37.918335 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 22:10:37.921776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 22:10:37.922185 ==
1810 22:10:37.925302 [Gating] SW mode calibration
1811 22:10:37.931572 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1812 22:10:37.938739 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1813 22:10:37.942253 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1814 22:10:37.945132 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
1815 22:10:37.952094 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 22:10:37.955368 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 22:10:37.958882 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:10:37.962050 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1819 22:10:37.968698 0 6 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1820 22:10:37.972394 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:10:37.975574 0 7 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1822 22:10:37.982010 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:10:37.985579 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:10:37.989211 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1825 22:10:37.995817 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1826 22:10:37.999508 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1827 22:10:38.002629 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1828 22:10:38.006060 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1829 22:10:38.012266 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1830 22:10:38.016029 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (1 0)
1831 22:10:38.019076 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1832 22:10:38.025639 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1833 22:10:38.029275 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:10:38.032641 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1835 22:10:38.039618 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:10:38.042511 0 8 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1837 22:10:38.045839 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1838 22:10:38.052577 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1839 22:10:38.056294 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1840 22:10:38.058931 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 22:10:38.062203 0 9 16 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
1842 22:10:38.069494 0 9 20 | B1->B0 | 3534 3434 | 1 1 | (1 1) (1 1)
1843 22:10:38.072432 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1844 22:10:38.076195 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 22:10:38.082924 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
1846 22:10:38.086479 0 10 4 | B1->B0 | 3030 2929 | 1 0 | (1 1) (0 0)
1847 22:10:38.089527 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1848 22:10:38.096260 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 22:10:38.099765 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:10:38.102978 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:10:38.109614 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 22:10:38.113177 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 22:10:38.116589 0 11 0 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1854 22:10:38.120247 0 11 4 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (1 1)
1855 22:10:38.127076 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1856 22:10:38.130027 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 22:10:38.133583 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 22:10:38.140116 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 22:10:38.143867 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 22:10:38.147323 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 22:10:38.153889 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 22:10:38.157561 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1863 22:10:38.160428 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:10:38.167145 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 22:10:38.170960 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 22:10:38.174110 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 22:10:38.177451 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 22:10:38.184130 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 22:10:38.187051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:10:38.190577 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:10:38.197282 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:10:38.200957 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:10:38.203891 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:10:38.210919 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:10:38.214006 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:10:38.217621 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:10:38.224412 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:10:38.227565 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1879 22:10:38.230980 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 22:10:38.234370 Total UI for P1: 0, mck2ui 16
1881 22:10:38.238026 best dqsien dly found for B0: ( 0, 14, 4)
1882 22:10:38.241003 Total UI for P1: 0, mck2ui 16
1883 22:10:38.244721 best dqsien dly found for B1: ( 0, 14, 6)
1884 22:10:38.247729 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1885 22:10:38.251357 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1886 22:10:38.251869
1887 22:10:38.254361 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1888 22:10:38.258143 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1889 22:10:38.261455 [Gating] SW calibration Done
1890 22:10:38.261940 ==
1891 22:10:38.264642 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 22:10:38.268209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 22:10:38.268620 ==
1894 22:10:38.271214 RX Vref Scan: 0
1895 22:10:38.271622
1896 22:10:38.274697 RX Vref 0 -> 0, step: 1
1897 22:10:38.275106
1898 22:10:38.275431 RX Delay -130 -> 252, step: 16
1899 22:10:38.281303 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1900 22:10:38.284625 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1901 22:10:38.288441 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1902 22:10:38.291759 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1903 22:10:38.294631 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1904 22:10:38.301821 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1905 22:10:38.305352 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1906 22:10:38.308240 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1907 22:10:38.311877 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1908 22:10:38.314875 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1909 22:10:38.318437 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1910 22:10:38.325309 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1911 22:10:38.328648 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1912 22:10:38.331773 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1913 22:10:38.335329 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1914 22:10:38.341753 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1915 22:10:38.342242 ==
1916 22:10:38.345403 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 22:10:38.348719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 22:10:38.349141 ==
1919 22:10:38.349470 DQS Delay:
1920 22:10:38.351955 DQS0 = 0, DQS1 = 0
1921 22:10:38.352585 DQM Delay:
1922 22:10:38.355387 DQM0 = 78, DQM1 = 77
1923 22:10:38.355992 DQ Delay:
1924 22:10:38.358601 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1925 22:10:38.362156 DQ4 =69, DQ5 =93, DQ6 =93, DQ7 =69
1926 22:10:38.365615 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1927 22:10:38.368736 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1928 22:10:38.369180
1929 22:10:38.369616
1930 22:10:38.369941 ==
1931 22:10:38.372150 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 22:10:38.375038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 22:10:38.375627 ==
1934 22:10:38.375974
1935 22:10:38.376382
1936 22:10:38.378682 TX Vref Scan disable
1937 22:10:38.381903 == TX Byte 0 ==
1938 22:10:38.385434 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1939 22:10:38.389143 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1940 22:10:38.392116 == TX Byte 1 ==
1941 22:10:38.395467 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1942 22:10:38.398779 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1943 22:10:38.399484 ==
1944 22:10:38.402456 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 22:10:38.405583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 22:10:38.406207 ==
1947 22:10:38.419764 TX Vref=22, minBit 12, minWin=26, winSum=438
1948 22:10:38.422988 TX Vref=24, minBit 0, minWin=27, winSum=445
1949 22:10:38.426633 TX Vref=26, minBit 10, minWin=27, winSum=447
1950 22:10:38.430196 TX Vref=28, minBit 10, minWin=27, winSum=450
1951 22:10:38.433196 TX Vref=30, minBit 13, minWin=27, winSum=452
1952 22:10:38.440271 TX Vref=32, minBit 13, minWin=27, winSum=451
1953 22:10:38.443241 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 30
1954 22:10:38.443907
1955 22:10:38.446729 Final TX Range 1 Vref 30
1956 22:10:38.447242
1957 22:10:38.447702 ==
1958 22:10:38.449764 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 22:10:38.453391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 22:10:38.453846 ==
1961 22:10:38.456433
1962 22:10:38.457107
1963 22:10:38.457637 TX Vref Scan disable
1964 22:10:38.460074 == TX Byte 0 ==
1965 22:10:38.463529 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1966 22:10:38.466860 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1967 22:10:38.470349 == TX Byte 1 ==
1968 22:10:38.473395 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1969 22:10:38.477044 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1970 22:10:38.477467
1971 22:10:38.480479 [DATLAT]
1972 22:10:38.480993 Freq=800, CH1 RK1
1973 22:10:38.481326
1974 22:10:38.483510 DATLAT Default: 0xa
1975 22:10:38.483920 0, 0xFFFF, sum = 0
1976 22:10:38.487222 1, 0xFFFF, sum = 0
1977 22:10:38.487686 2, 0xFFFF, sum = 0
1978 22:10:38.490865 3, 0xFFFF, sum = 0
1979 22:10:38.491639 4, 0xFFFF, sum = 0
1980 22:10:38.493900 5, 0xFFFF, sum = 0
1981 22:10:38.494328 6, 0xFFFF, sum = 0
1982 22:10:38.497562 7, 0xFFFF, sum = 0
1983 22:10:38.497982 8, 0xFFFF, sum = 0
1984 22:10:38.500481 9, 0x0, sum = 1
1985 22:10:38.501113 10, 0x0, sum = 2
1986 22:10:38.504143 11, 0x0, sum = 3
1987 22:10:38.504757 12, 0x0, sum = 4
1988 22:10:38.507001 best_step = 10
1989 22:10:38.507598
1990 22:10:38.508106 ==
1991 22:10:38.510792 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 22:10:38.514053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 22:10:38.514470 ==
1994 22:10:38.514796 RX Vref Scan: 0
1995 22:10:38.517323
1996 22:10:38.517763 RX Vref 0 -> 0, step: 1
1997 22:10:38.518146
1998 22:10:38.520480 RX Delay -95 -> 252, step: 8
1999 22:10:38.524098 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2000 22:10:38.530687 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2001 22:10:38.534225 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2002 22:10:38.537277 iDelay=201, Bit 3, Center 80 (-31 ~ 192) 224
2003 22:10:38.540579 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2004 22:10:38.544057 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2005 22:10:38.550656 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2006 22:10:38.554124 iDelay=201, Bit 7, Center 76 (-31 ~ 184) 216
2007 22:10:38.557095 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2008 22:10:38.560850 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2009 22:10:38.564529 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2010 22:10:38.567361 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2011 22:10:38.574260 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2012 22:10:38.577349 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2013 22:10:38.580912 iDelay=201, Bit 14, Center 80 (-39 ~ 200) 240
2014 22:10:38.584401 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2015 22:10:38.584478 ==
2016 22:10:38.587295 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 22:10:38.594001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 22:10:38.594083 ==
2019 22:10:38.594148 DQS Delay:
2020 22:10:38.597585 DQS0 = 0, DQS1 = 0
2021 22:10:38.597691 DQM Delay:
2022 22:10:38.597755 DQM0 = 80, DQM1 = 75
2023 22:10:38.601187 DQ Delay:
2024 22:10:38.604315 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =80
2025 22:10:38.607961 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
2026 22:10:38.611058 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2027 22:10:38.614013 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
2028 22:10:38.614113
2029 22:10:38.614185
2030 22:10:38.621118 [DQSOSCAuto] RK1, (LSB)MR18= 0x232f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
2031 22:10:38.624562 CH1 RK1: MR19=606, MR18=232F
2032 22:10:38.631256 CH1_RK1: MR19=0x606, MR18=0x232F, DQSOSC=397, MR23=63, INC=93, DEC=62
2033 22:10:38.634460 [RxdqsGatingPostProcess] freq 800
2034 22:10:38.638150 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 22:10:38.641312 Pre-setting of DQS Precalculation
2036 22:10:38.647647 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 22:10:38.654570 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 22:10:38.661349 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 22:10:38.661425
2040 22:10:38.661488
2041 22:10:38.664453 [Calibration Summary] 1600 Mbps
2042 22:10:38.664523 CH 0, Rank 0
2043 22:10:38.668136 SW Impedance : PASS
2044 22:10:38.668207 DUTY Scan : NO K
2045 22:10:38.671590 ZQ Calibration : PASS
2046 22:10:38.674658 Jitter Meter : NO K
2047 22:10:38.674738 CBT Training : PASS
2048 22:10:38.678150 Write leveling : PASS
2049 22:10:38.681155 RX DQS gating : PASS
2050 22:10:38.681240 RX DQ/DQS(RDDQC) : PASS
2051 22:10:38.684987 TX DQ/DQS : PASS
2052 22:10:38.688254 RX DATLAT : PASS
2053 22:10:38.688345 RX DQ/DQS(Engine): PASS
2054 22:10:38.691624 TX OE : NO K
2055 22:10:38.691725 All Pass.
2056 22:10:38.691803
2057 22:10:38.695009 CH 0, Rank 1
2058 22:10:38.695116 SW Impedance : PASS
2059 22:10:38.698480 DUTY Scan : NO K
2060 22:10:38.698588 ZQ Calibration : PASS
2061 22:10:38.701630 Jitter Meter : NO K
2062 22:10:38.704761 CBT Training : PASS
2063 22:10:38.704892 Write leveling : PASS
2064 22:10:38.708246 RX DQS gating : PASS
2065 22:10:38.711391 RX DQ/DQS(RDDQC) : PASS
2066 22:10:38.711587 TX DQ/DQS : PASS
2067 22:10:38.715174 RX DATLAT : PASS
2068 22:10:38.718767 RX DQ/DQS(Engine): PASS
2069 22:10:38.718984 TX OE : NO K
2070 22:10:38.721477 All Pass.
2071 22:10:38.721574
2072 22:10:38.721661 CH 1, Rank 0
2073 22:10:38.725200 SW Impedance : PASS
2074 22:10:38.725297 DUTY Scan : NO K
2075 22:10:38.728137 ZQ Calibration : PASS
2076 22:10:38.731328 Jitter Meter : NO K
2077 22:10:38.731425 CBT Training : PASS
2078 22:10:38.734672 Write leveling : PASS
2079 22:10:38.734742 RX DQS gating : PASS
2080 22:10:38.738090 RX DQ/DQS(RDDQC) : PASS
2081 22:10:38.741611 TX DQ/DQS : PASS
2082 22:10:38.741692 RX DATLAT : PASS
2083 22:10:38.745212 RX DQ/DQS(Engine): PASS
2084 22:10:38.748616 TX OE : NO K
2085 22:10:38.748746 All Pass.
2086 22:10:38.748820
2087 22:10:38.748878 CH 1, Rank 1
2088 22:10:38.751691 SW Impedance : PASS
2089 22:10:38.755552 DUTY Scan : NO K
2090 22:10:38.755655 ZQ Calibration : PASS
2091 22:10:38.758445 Jitter Meter : NO K
2092 22:10:38.761891 CBT Training : PASS
2093 22:10:38.761965 Write leveling : PASS
2094 22:10:38.765084 RX DQS gating : PASS
2095 22:10:38.768652 RX DQ/DQS(RDDQC) : PASS
2096 22:10:38.768742 TX DQ/DQS : PASS
2097 22:10:38.772393 RX DATLAT : PASS
2098 22:10:38.772477 RX DQ/DQS(Engine): PASS
2099 22:10:38.775319 TX OE : NO K
2100 22:10:38.775411 All Pass.
2101 22:10:38.775484
2102 22:10:38.778839 DramC Write-DBI off
2103 22:10:38.782232 PER_BANK_REFRESH: Hybrid Mode
2104 22:10:38.782331 TX_TRACKING: ON
2105 22:10:38.785306 [GetDramInforAfterCalByMRR] Vendor 6.
2106 22:10:38.788770 [GetDramInforAfterCalByMRR] Revision 606.
2107 22:10:38.792160 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 22:10:38.795298 MR0 0x3b3b
2109 22:10:38.795369 MR8 0x5151
2110 22:10:38.799767 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 22:10:38.799935
2112 22:10:38.800010 MR0 0x3b3b
2113 22:10:38.802773 MR8 0x5151
2114 22:10:38.805731 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 22:10:38.805911
2116 22:10:38.815513 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 22:10:38.819166 [FAST_K] Save calibration result to emmc
2118 22:10:38.822197 [FAST_K] Save calibration result to emmc
2119 22:10:38.822363 dram_init: config_dvfs: 1
2120 22:10:38.829726 dramc_set_vcore_voltage set vcore to 662500
2121 22:10:38.829961 Read voltage for 1200, 2
2122 22:10:38.832338 Vio18 = 0
2123 22:10:38.832506 Vcore = 662500
2124 22:10:38.832624 Vdram = 0
2125 22:10:38.832761 Vddq = 0
2126 22:10:38.836277 Vmddr = 0
2127 22:10:38.839919 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 22:10:38.846361 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 22:10:38.849824 MEM_TYPE=3, freq_sel=15
2130 22:10:38.850566 sv_algorithm_assistance_LP4_1600
2131 22:10:38.856279 ============ PULL DRAM RESETB DOWN ============
2132 22:10:38.860030 ========== PULL DRAM RESETB DOWN end =========
2133 22:10:38.863225 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 22:10:38.866550 ===================================
2135 22:10:38.869701 LPDDR4 DRAM CONFIGURATION
2136 22:10:38.873328 ===================================
2137 22:10:38.876532 EX_ROW_EN[0] = 0x0
2138 22:10:38.876989 EX_ROW_EN[1] = 0x0
2139 22:10:38.879851 LP4Y_EN = 0x0
2140 22:10:38.880404 WORK_FSP = 0x0
2141 22:10:38.883062 WL = 0x4
2142 22:10:38.883472 RL = 0x4
2143 22:10:38.886563 BL = 0x2
2144 22:10:38.886969 RPST = 0x0
2145 22:10:38.890072 RD_PRE = 0x0
2146 22:10:38.890684 WR_PRE = 0x1
2147 22:10:38.893095 WR_PST = 0x0
2148 22:10:38.893504 DBI_WR = 0x0
2149 22:10:38.896559 DBI_RD = 0x0
2150 22:10:38.897015 OTF = 0x1
2151 22:10:38.900076 ===================================
2152 22:10:38.903184 ===================================
2153 22:10:38.906861 ANA top config
2154 22:10:38.910394 ===================================
2155 22:10:38.910806 DLL_ASYNC_EN = 0
2156 22:10:38.913177 ALL_SLAVE_EN = 0
2157 22:10:38.916838 NEW_RANK_MODE = 1
2158 22:10:38.920107 DLL_IDLE_MODE = 1
2159 22:10:38.920783 LP45_APHY_COMB_EN = 1
2160 22:10:38.923731 TX_ODT_DIS = 1
2161 22:10:38.926678 NEW_8X_MODE = 1
2162 22:10:38.930397 ===================================
2163 22:10:38.933402 ===================================
2164 22:10:38.936850 data_rate = 2400
2165 22:10:38.940434 CKR = 1
2166 22:10:38.943404 DQ_P2S_RATIO = 8
2167 22:10:38.943951 ===================================
2168 22:10:38.946911 CA_P2S_RATIO = 8
2169 22:10:38.950131 DQ_CA_OPEN = 0
2170 22:10:38.953784 DQ_SEMI_OPEN = 0
2171 22:10:38.957134 CA_SEMI_OPEN = 0
2172 22:10:38.960162 CA_FULL_RATE = 0
2173 22:10:38.960575 DQ_CKDIV4_EN = 0
2174 22:10:38.963624 CA_CKDIV4_EN = 0
2175 22:10:38.967354 CA_PREDIV_EN = 0
2176 22:10:38.970521 PH8_DLY = 17
2177 22:10:38.973471 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 22:10:38.977013 DQ_AAMCK_DIV = 4
2179 22:10:38.977424 CA_AAMCK_DIV = 4
2180 22:10:38.980626 CA_ADMCK_DIV = 4
2181 22:10:38.984237 DQ_TRACK_CA_EN = 0
2182 22:10:38.987158 CA_PICK = 1200
2183 22:10:38.990609 CA_MCKIO = 1200
2184 22:10:38.994059 MCKIO_SEMI = 0
2185 22:10:38.997172 PLL_FREQ = 2366
2186 22:10:38.997583 DQ_UI_PI_RATIO = 32
2187 22:10:39.000619 CA_UI_PI_RATIO = 0
2188 22:10:39.003926 ===================================
2189 22:10:39.007154 ===================================
2190 22:10:39.010331 memory_type:LPDDR4
2191 22:10:39.014239 GP_NUM : 10
2192 22:10:39.014821 SRAM_EN : 1
2193 22:10:39.017565 MD32_EN : 0
2194 22:10:39.020375 ===================================
2195 22:10:39.020872 [ANA_INIT] >>>>>>>>>>>>>>
2196 22:10:39.023834 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 22:10:39.027407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 22:10:39.030267 ===================================
2199 22:10:39.034134 data_rate = 2400,PCW = 0X5b00
2200 22:10:39.037615 ===================================
2201 22:10:39.040595 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 22:10:39.047116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 22:10:39.050435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 22:10:39.057362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 22:10:39.060763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 22:10:39.064187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 22:10:39.064479 [ANA_INIT] flow start
2208 22:10:39.067393 [ANA_INIT] PLL >>>>>>>>
2209 22:10:39.070522 [ANA_INIT] PLL <<<<<<<<
2210 22:10:39.070940 [ANA_INIT] MIDPI >>>>>>>>
2211 22:10:39.074119 [ANA_INIT] MIDPI <<<<<<<<
2212 22:10:39.077226 [ANA_INIT] DLL >>>>>>>>
2213 22:10:39.080837 [ANA_INIT] DLL <<<<<<<<
2214 22:10:39.081145 [ANA_INIT] flow end
2215 22:10:39.084527 ============ LP4 DIFF to SE enter ============
2216 22:10:39.091081 ============ LP4 DIFF to SE exit ============
2217 22:10:39.091388 [ANA_INIT] <<<<<<<<<<<<<
2218 22:10:39.094207 [Flow] Enable top DCM control >>>>>
2219 22:10:39.097839 [Flow] Enable top DCM control <<<<<
2220 22:10:39.101405 Enable DLL master slave shuffle
2221 22:10:39.107665 ==============================================================
2222 22:10:39.107975 Gating Mode config
2223 22:10:39.114299 ==============================================================
2224 22:10:39.114625 Config description:
2225 22:10:39.124242 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 22:10:39.131151 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 22:10:39.138059 SELPH_MODE 0: By rank 1: By Phase
2228 22:10:39.141272 ==============================================================
2229 22:10:39.144952 GAT_TRACK_EN = 1
2230 22:10:39.148003 RX_GATING_MODE = 2
2231 22:10:39.151505 RX_GATING_TRACK_MODE = 2
2232 22:10:39.155077 SELPH_MODE = 1
2233 22:10:39.158024 PICG_EARLY_EN = 1
2234 22:10:39.161988 VALID_LAT_VALUE = 1
2235 22:10:39.165015 ==============================================================
2236 22:10:39.168367 Enter into Gating configuration >>>>
2237 22:10:39.171327 Exit from Gating configuration <<<<
2238 22:10:39.174989 Enter into DVFS_PRE_config >>>>>
2239 22:10:39.188056 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 22:10:39.188150 Exit from DVFS_PRE_config <<<<<
2241 22:10:39.191140 Enter into PICG configuration >>>>
2242 22:10:39.194797 Exit from PICG configuration <<<<
2243 22:10:39.197999 [RX_INPUT] configuration >>>>>
2244 22:10:39.201688 [RX_INPUT] configuration <<<<<
2245 22:10:39.208155 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 22:10:39.211879 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 22:10:39.218513 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 22:10:39.225328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 22:10:39.231687 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 22:10:39.238292 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 22:10:39.241809 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 22:10:39.245370 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 22:10:39.248818 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 22:10:39.251855 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 22:10:39.258731 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 22:10:39.261721 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 22:10:39.265257 ===================================
2258 22:10:39.268245 LPDDR4 DRAM CONFIGURATION
2259 22:10:39.271994 ===================================
2260 22:10:39.272084 EX_ROW_EN[0] = 0x0
2261 22:10:39.275336 EX_ROW_EN[1] = 0x0
2262 22:10:39.275433 LP4Y_EN = 0x0
2263 22:10:39.278304 WORK_FSP = 0x0
2264 22:10:39.278410 WL = 0x4
2265 22:10:39.281623 RL = 0x4
2266 22:10:39.281727 BL = 0x2
2267 22:10:39.285171 RPST = 0x0
2268 22:10:39.285250 RD_PRE = 0x0
2269 22:10:39.288967 WR_PRE = 0x1
2270 22:10:39.289045 WR_PST = 0x0
2271 22:10:39.292338 DBI_WR = 0x0
2272 22:10:39.295410 DBI_RD = 0x0
2273 22:10:39.295516 OTF = 0x1
2274 22:10:39.298490 ===================================
2275 22:10:39.302155 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 22:10:39.305202 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 22:10:39.312139 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 22:10:39.315608 ===================================
2279 22:10:39.315701 LPDDR4 DRAM CONFIGURATION
2280 22:10:39.318957 ===================================
2281 22:10:39.322342 EX_ROW_EN[0] = 0x10
2282 22:10:39.325531 EX_ROW_EN[1] = 0x0
2283 22:10:39.325635 LP4Y_EN = 0x0
2284 22:10:39.329040 WORK_FSP = 0x0
2285 22:10:39.329146 WL = 0x4
2286 22:10:39.332483 RL = 0x4
2287 22:10:39.332585 BL = 0x2
2288 22:10:39.335498 RPST = 0x0
2289 22:10:39.335609 RD_PRE = 0x0
2290 22:10:39.339235 WR_PRE = 0x1
2291 22:10:39.339352 WR_PST = 0x0
2292 22:10:39.342398 DBI_WR = 0x0
2293 22:10:39.342503 DBI_RD = 0x0
2294 22:10:39.345686 OTF = 0x1
2295 22:10:39.348962 ===================================
2296 22:10:39.356131 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 22:10:39.356214 ==
2298 22:10:39.359108 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 22:10:39.362689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 22:10:39.362856 ==
2301 22:10:39.366639 [Duty_Offset_Calibration]
2302 22:10:39.366806 B0:2 B1:-1 CA:1
2303 22:10:39.366884
2304 22:10:39.369574 [DutyScan_Calibration_Flow] k_type=0
2305 22:10:39.378544
2306 22:10:39.378634 ==CLK 0==
2307 22:10:39.381415 Final CLK duty delay cell = -4
2308 22:10:39.384961 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2309 22:10:39.388615 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2310 22:10:39.391485 [-4] AVG Duty = 4953%(X100)
2311 22:10:39.391563
2312 22:10:39.394851 CH0 CLK Duty spec in!! Max-Min= 156%
2313 22:10:39.398428 [DutyScan_Calibration_Flow] ====Done====
2314 22:10:39.398507
2315 22:10:39.401550 [DutyScan_Calibration_Flow] k_type=1
2316 22:10:39.416493
2317 22:10:39.416599 ==DQS 0 ==
2318 22:10:39.419995 Final DQS duty delay cell = -4
2319 22:10:39.422903 [-4] MAX Duty = 5000%(X100), DQS PI = 44
2320 22:10:39.426392 [-4] MIN Duty = 4876%(X100), DQS PI = 10
2321 22:10:39.429940 [-4] AVG Duty = 4938%(X100)
2322 22:10:39.430019
2323 22:10:39.430080 ==DQS 1 ==
2324 22:10:39.433845 Final DQS duty delay cell = -4
2325 22:10:39.436379 [-4] MAX Duty = 5093%(X100), DQS PI = 4
2326 22:10:39.440005 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2327 22:10:39.443364 [-4] AVG Duty = 5046%(X100)
2328 22:10:39.443442
2329 22:10:39.446892 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2330 22:10:39.446969
2331 22:10:39.449830 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2332 22:10:39.453999 [DutyScan_Calibration_Flow] ====Done====
2333 22:10:39.454106
2334 22:10:39.456615 [DutyScan_Calibration_Flow] k_type=3
2335 22:10:39.473808
2336 22:10:39.473889 ==DQM 0 ==
2337 22:10:39.476859 Final DQM duty delay cell = 0
2338 22:10:39.479931 [0] MAX Duty = 5000%(X100), DQS PI = 54
2339 22:10:39.483577 [0] MIN Duty = 4907%(X100), DQS PI = 2
2340 22:10:39.483655 [0] AVG Duty = 4953%(X100)
2341 22:10:39.487160
2342 22:10:39.487238 ==DQM 1 ==
2343 22:10:39.490229 Final DQM duty delay cell = 0
2344 22:10:39.493819 [0] MAX Duty = 5124%(X100), DQS PI = 32
2345 22:10:39.496911 [0] MIN Duty = 4969%(X100), DQS PI = 10
2346 22:10:39.497022 [0] AVG Duty = 5046%(X100)
2347 22:10:39.497112
2348 22:10:39.500224 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2349 22:10:39.504129
2350 22:10:39.507120 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2351 22:10:39.510813 [DutyScan_Calibration_Flow] ====Done====
2352 22:10:39.510896
2353 22:10:39.513690 [DutyScan_Calibration_Flow] k_type=2
2354 22:10:39.529067
2355 22:10:39.529174 ==DQ 0 ==
2356 22:10:39.532897 Final DQ duty delay cell = -4
2357 22:10:39.535959 [-4] MAX Duty = 5031%(X100), DQS PI = 44
2358 22:10:39.539642 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2359 22:10:39.542572 [-4] AVG Duty = 4953%(X100)
2360 22:10:39.542716
2361 22:10:39.542830 ==DQ 1 ==
2362 22:10:39.546089 Final DQ duty delay cell = 0
2363 22:10:39.549214 [0] MAX Duty = 5031%(X100), DQS PI = 18
2364 22:10:39.552569 [0] MIN Duty = 4907%(X100), DQS PI = 46
2365 22:10:39.552811 [0] AVG Duty = 4969%(X100)
2366 22:10:39.556188
2367 22:10:39.559444 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2368 22:10:39.559713
2369 22:10:39.563182 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2370 22:10:39.566273 [DutyScan_Calibration_Flow] ====Done====
2371 22:10:39.566677 ==
2372 22:10:39.569853 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 22:10:39.572864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 22:10:39.573268 ==
2375 22:10:39.576462 [Duty_Offset_Calibration]
2376 22:10:39.576966 B0:1 B1:1 CA:2
2377 22:10:39.577294
2378 22:10:39.579717 [DutyScan_Calibration_Flow] k_type=0
2379 22:10:39.589732
2380 22:10:39.589822 ==CLK 0==
2381 22:10:39.593226 Final CLK duty delay cell = 0
2382 22:10:39.596345 [0] MAX Duty = 5125%(X100), DQS PI = 24
2383 22:10:39.599910 [0] MIN Duty = 4969%(X100), DQS PI = 40
2384 22:10:39.600091 [0] AVG Duty = 5047%(X100)
2385 22:10:39.600179
2386 22:10:39.602786 CH1 CLK Duty spec in!! Max-Min= 156%
2387 22:10:39.609728 [DutyScan_Calibration_Flow] ====Done====
2388 22:10:39.609863
2389 22:10:39.612704 [DutyScan_Calibration_Flow] k_type=1
2390 22:10:39.628886
2391 22:10:39.629080 ==DQS 0 ==
2392 22:10:39.632508 Final DQS duty delay cell = 0
2393 22:10:39.636252 [0] MAX Duty = 5031%(X100), DQS PI = 18
2394 22:10:39.639205 [0] MIN Duty = 4844%(X100), DQS PI = 48
2395 22:10:39.639493 [0] AVG Duty = 4937%(X100)
2396 22:10:39.643181
2397 22:10:39.643551 ==DQS 1 ==
2398 22:10:39.646322 Final DQS duty delay cell = 0
2399 22:10:39.649685 [0] MAX Duty = 5062%(X100), DQS PI = 36
2400 22:10:39.653062 [0] MIN Duty = 4907%(X100), DQS PI = 16
2401 22:10:39.653498 [0] AVG Duty = 4984%(X100)
2402 22:10:39.653832
2403 22:10:39.659216 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2404 22:10:39.659634
2405 22:10:39.662559 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2406 22:10:39.666468 [DutyScan_Calibration_Flow] ====Done====
2407 22:10:39.667028
2408 22:10:39.669926 [DutyScan_Calibration_Flow] k_type=3
2409 22:10:39.686122
2410 22:10:39.686639 ==DQM 0 ==
2411 22:10:39.689511 Final DQM duty delay cell = 0
2412 22:10:39.692482 [0] MAX Duty = 5093%(X100), DQS PI = 18
2413 22:10:39.696084 [0] MIN Duty = 4907%(X100), DQS PI = 48
2414 22:10:39.696497 [0] AVG Duty = 5000%(X100)
2415 22:10:39.699472
2416 22:10:39.699987 ==DQM 1 ==
2417 22:10:39.703044 Final DQM duty delay cell = 0
2418 22:10:39.706125 [0] MAX Duty = 5156%(X100), DQS PI = 62
2419 22:10:39.709277 [0] MIN Duty = 4938%(X100), DQS PI = 22
2420 22:10:39.709738 [0] AVG Duty = 5047%(X100)
2421 22:10:39.713438
2422 22:10:39.716575 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2423 22:10:39.717354
2424 22:10:39.719794 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2425 22:10:39.722906 [DutyScan_Calibration_Flow] ====Done====
2426 22:10:39.723460
2427 22:10:39.726494 [DutyScan_Calibration_Flow] k_type=2
2428 22:10:39.742221
2429 22:10:39.742681 ==DQ 0 ==
2430 22:10:39.746386 Final DQ duty delay cell = 0
2431 22:10:39.749021 [0] MAX Duty = 5156%(X100), DQS PI = 18
2432 22:10:39.752375 [0] MIN Duty = 4907%(X100), DQS PI = 50
2433 22:10:39.752891 [0] AVG Duty = 5031%(X100)
2434 22:10:39.755944
2435 22:10:39.756550 ==DQ 1 ==
2436 22:10:39.758954 Final DQ duty delay cell = 0
2437 22:10:39.762264 [0] MAX Duty = 5093%(X100), DQS PI = 10
2438 22:10:39.765558 [0] MIN Duty = 5031%(X100), DQS PI = 2
2439 22:10:39.765969 [0] AVG Duty = 5062%(X100)
2440 22:10:39.766287
2441 22:10:39.769335 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2442 22:10:39.769758
2443 22:10:39.772566 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2444 22:10:39.778983 [DutyScan_Calibration_Flow] ====Done====
2445 22:10:39.783011 nWR fixed to 30
2446 22:10:39.783518 [ModeRegInit_LP4] CH0 RK0
2447 22:10:39.786411 [ModeRegInit_LP4] CH0 RK1
2448 22:10:39.789635 [ModeRegInit_LP4] CH1 RK0
2449 22:10:39.790038 [ModeRegInit_LP4] CH1 RK1
2450 22:10:39.792360 match AC timing 7
2451 22:10:39.795754 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 22:10:39.799341 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 22:10:39.806019 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 22:10:39.809458 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 22:10:39.815931 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 22:10:39.816338 ==
2457 22:10:39.819252 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 22:10:39.823193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 22:10:39.823602 ==
2460 22:10:39.826182 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 22:10:39.832931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2462 22:10:39.842367 [CA 0] Center 40 (10~71) winsize 62
2463 22:10:39.845972 [CA 1] Center 39 (9~70) winsize 62
2464 22:10:39.848987 [CA 2] Center 36 (6~67) winsize 62
2465 22:10:39.852322 [CA 3] Center 35 (5~66) winsize 62
2466 22:10:39.855707 [CA 4] Center 35 (5~65) winsize 61
2467 22:10:39.859143 [CA 5] Center 34 (4~65) winsize 62
2468 22:10:39.859549
2469 22:10:39.862381 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2470 22:10:39.862787
2471 22:10:39.865738 [CATrainingPosCal] consider 1 rank data
2472 22:10:39.869372 u2DelayCellTimex100 = 270/100 ps
2473 22:10:39.872901 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2474 22:10:39.875856 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2475 22:10:39.879299 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2476 22:10:39.886349 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2477 22:10:39.889569 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2478 22:10:39.892841 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2479 22:10:39.893252
2480 22:10:39.895813 CA PerBit enable=1, Macro0, CA PI delay=34
2481 22:10:39.896275
2482 22:10:39.899327 [CBTSetCACLKResult] CA Dly = 34
2483 22:10:39.899736 CS Dly: 7 (0~38)
2484 22:10:39.900058 ==
2485 22:10:39.902665 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 22:10:39.909681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 22:10:39.910179 ==
2488 22:10:39.913167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 22:10:39.919299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2490 22:10:39.928141 [CA 0] Center 39 (9~70) winsize 62
2491 22:10:39.931498 [CA 1] Center 39 (9~70) winsize 62
2492 22:10:39.934700 [CA 2] Center 36 (6~67) winsize 62
2493 22:10:39.938264 [CA 3] Center 36 (5~67) winsize 63
2494 22:10:39.941584 [CA 4] Center 34 (4~65) winsize 62
2495 22:10:39.945167 [CA 5] Center 34 (4~64) winsize 61
2496 22:10:39.945576
2497 22:10:39.948183 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2498 22:10:39.948592
2499 22:10:39.951794 [CATrainingPosCal] consider 2 rank data
2500 22:10:39.955355 u2DelayCellTimex100 = 270/100 ps
2501 22:10:39.958616 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2502 22:10:39.961849 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2503 22:10:39.965332 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2504 22:10:39.971465 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2505 22:10:39.975005 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2506 22:10:39.978563 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2507 22:10:39.978972
2508 22:10:39.981879 CA PerBit enable=1, Macro0, CA PI delay=34
2509 22:10:39.982289
2510 22:10:39.985330 [CBTSetCACLKResult] CA Dly = 34
2511 22:10:39.985741 CS Dly: 8 (0~41)
2512 22:10:39.986063
2513 22:10:39.988832 ----->DramcWriteLeveling(PI) begin...
2514 22:10:39.989254 ==
2515 22:10:39.992206 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 22:10:39.998780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 22:10:39.999336 ==
2518 22:10:40.002399 Write leveling (Byte 0): 34 => 34
2519 22:10:40.005487 Write leveling (Byte 1): 28 => 28
2520 22:10:40.005946 DramcWriteLeveling(PI) end<-----
2521 22:10:40.006347
2522 22:10:40.008792 ==
2523 22:10:40.009317 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 22:10:40.015702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 22:10:40.016130 ==
2526 22:10:40.018727 [Gating] SW mode calibration
2527 22:10:40.025400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 22:10:40.028783 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 22:10:40.035365 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 22:10:40.039022 0 15 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
2531 22:10:40.042235 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2532 22:10:40.045930 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 22:10:40.052218 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 22:10:40.055770 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 22:10:40.058897 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 22:10:40.066115 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 22:10:40.068906 1 0 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2538 22:10:40.072350 1 0 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2539 22:10:40.079336 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 22:10:40.082412 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 22:10:40.085898 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 22:10:40.092507 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 22:10:40.096120 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 22:10:40.099569 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 22:10:40.106437 1 1 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2546 22:10:40.109403 1 1 4 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
2547 22:10:40.113011 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 22:10:40.116432 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 22:10:40.122952 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 22:10:40.126653 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 22:10:40.129664 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 22:10:40.136621 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 22:10:40.139765 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2554 22:10:40.143196 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 22:10:40.149640 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 22:10:40.153294 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 22:10:40.156380 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 22:10:40.159679 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 22:10:40.166931 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 22:10:40.170119 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:10:40.173470 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:10:40.179958 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:10:40.183248 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:10:40.186715 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:10:40.193816 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:10:40.196774 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:10:40.200501 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:10:40.206871 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:10:40.210422 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2570 22:10:40.213847 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 22:10:40.216802 Total UI for P1: 0, mck2ui 16
2572 22:10:40.220164 best dqsien dly found for B0: ( 1, 4, 0)
2573 22:10:40.223371 Total UI for P1: 0, mck2ui 16
2574 22:10:40.227183 best dqsien dly found for B1: ( 1, 4, 0)
2575 22:10:40.230193 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2576 22:10:40.233816 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2577 22:10:40.234453
2578 22:10:40.236980 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2579 22:10:40.240453 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2580 22:10:40.243434 [Gating] SW calibration Done
2581 22:10:40.244067 ==
2582 22:10:40.247212 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 22:10:40.250780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 22:10:40.253809 ==
2585 22:10:40.254261 RX Vref Scan: 0
2586 22:10:40.254676
2587 22:10:40.257543 RX Vref 0 -> 0, step: 1
2588 22:10:40.258133
2589 22:10:40.260210 RX Delay -40 -> 252, step: 8
2590 22:10:40.263676 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2591 22:10:40.267401 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2592 22:10:40.270310 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2593 22:10:40.273476 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2594 22:10:40.276775 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2595 22:10:40.284009 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2596 22:10:40.287492 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2597 22:10:40.290515 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2598 22:10:40.293890 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2599 22:10:40.297052 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2600 22:10:40.304414 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2601 22:10:40.307196 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2602 22:10:40.310771 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2603 22:10:40.314251 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2604 22:10:40.317202 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2605 22:10:40.324273 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2606 22:10:40.324539 ==
2607 22:10:40.327199 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 22:10:40.330634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 22:10:40.330807 ==
2610 22:10:40.330973 DQS Delay:
2611 22:10:40.334137 DQS0 = 0, DQS1 = 0
2612 22:10:40.334329 DQM Delay:
2613 22:10:40.337593 DQM0 = 115, DQM1 = 107
2614 22:10:40.337747 DQ Delay:
2615 22:10:40.340933 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2616 22:10:40.344263 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2617 22:10:40.347456 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2618 22:10:40.350976 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2619 22:10:40.351099
2620 22:10:40.351194
2621 22:10:40.351284 ==
2622 22:10:40.353888 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 22:10:40.360711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 22:10:40.360807 ==
2625 22:10:40.360901
2626 22:10:40.360990
2627 22:10:40.361076 TX Vref Scan disable
2628 22:10:40.364174 == TX Byte 0 ==
2629 22:10:40.367293 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2630 22:10:40.370749 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2631 22:10:40.374396 == TX Byte 1 ==
2632 22:10:40.377748 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2633 22:10:40.381398 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2634 22:10:40.384429 ==
2635 22:10:40.384576 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 22:10:40.391010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 22:10:40.391132 ==
2638 22:10:40.402698 TX Vref=22, minBit 1, minWin=24, winSum=413
2639 22:10:40.405877 TX Vref=24, minBit 1, minWin=25, winSum=421
2640 22:10:40.409817 TX Vref=26, minBit 1, minWin=25, winSum=423
2641 22:10:40.412885 TX Vref=28, minBit 0, minWin=26, winSum=429
2642 22:10:40.416426 TX Vref=30, minBit 0, minWin=26, winSum=433
2643 22:10:40.419676 TX Vref=32, minBit 1, minWin=26, winSum=432
2644 22:10:40.426260 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 30
2645 22:10:40.426343
2646 22:10:40.429218 Final TX Range 1 Vref 30
2647 22:10:40.429301
2648 22:10:40.429366 ==
2649 22:10:40.432735 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 22:10:40.436126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 22:10:40.436210 ==
2652 22:10:40.436275
2653 22:10:40.436335
2654 22:10:40.439693 TX Vref Scan disable
2655 22:10:40.442828 == TX Byte 0 ==
2656 22:10:40.446354 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2657 22:10:40.449858 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2658 22:10:40.453195 == TX Byte 1 ==
2659 22:10:40.456089 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2660 22:10:40.459840 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2661 22:10:40.459922
2662 22:10:40.462943 [DATLAT]
2663 22:10:40.463025 Freq=1200, CH0 RK0
2664 22:10:40.463092
2665 22:10:40.466452 DATLAT Default: 0xd
2666 22:10:40.466533 0, 0xFFFF, sum = 0
2667 22:10:40.469489 1, 0xFFFF, sum = 0
2668 22:10:40.469571 2, 0xFFFF, sum = 0
2669 22:10:40.473095 3, 0xFFFF, sum = 0
2670 22:10:40.473175 4, 0xFFFF, sum = 0
2671 22:10:40.476624 5, 0xFFFF, sum = 0
2672 22:10:40.476746 6, 0xFFFF, sum = 0
2673 22:10:40.479937 7, 0xFFFF, sum = 0
2674 22:10:40.480017 8, 0xFFFF, sum = 0
2675 22:10:40.483325 9, 0xFFFF, sum = 0
2676 22:10:40.483406 10, 0xFFFF, sum = 0
2677 22:10:40.486820 11, 0xFFFF, sum = 0
2678 22:10:40.486900 12, 0x0, sum = 1
2679 22:10:40.490156 13, 0x0, sum = 2
2680 22:10:40.490237 14, 0x0, sum = 3
2681 22:10:40.493216 15, 0x0, sum = 4
2682 22:10:40.493296 best_step = 13
2683 22:10:40.493359
2684 22:10:40.493418 ==
2685 22:10:40.496367 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 22:10:40.500076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 22:10:40.503653 ==
2688 22:10:40.503734 RX Vref Scan: 1
2689 22:10:40.503796
2690 22:10:40.507033 Set Vref Range= 32 -> 127
2691 22:10:40.507113
2692 22:10:40.510361 RX Vref 32 -> 127, step: 1
2693 22:10:40.510441
2694 22:10:40.510504 RX Delay -21 -> 252, step: 4
2695 22:10:40.510562
2696 22:10:40.513582 Set Vref, RX VrefLevel [Byte0]: 32
2697 22:10:40.516661 [Byte1]: 32
2698 22:10:40.520880
2699 22:10:40.520972 Set Vref, RX VrefLevel [Byte0]: 33
2700 22:10:40.524226 [Byte1]: 33
2701 22:10:40.529081
2702 22:10:40.529186 Set Vref, RX VrefLevel [Byte0]: 34
2703 22:10:40.531971 [Byte1]: 34
2704 22:10:40.536759
2705 22:10:40.536829 Set Vref, RX VrefLevel [Byte0]: 35
2706 22:10:40.540095 [Byte1]: 35
2707 22:10:40.544344
2708 22:10:40.544412 Set Vref, RX VrefLevel [Byte0]: 36
2709 22:10:40.547942 [Byte1]: 36
2710 22:10:40.552724
2711 22:10:40.552789 Set Vref, RX VrefLevel [Byte0]: 37
2712 22:10:40.555974 [Byte1]: 37
2713 22:10:40.560225
2714 22:10:40.560290 Set Vref, RX VrefLevel [Byte0]: 38
2715 22:10:40.563871 [Byte1]: 38
2716 22:10:40.568396
2717 22:10:40.568462 Set Vref, RX VrefLevel [Byte0]: 39
2718 22:10:40.571509 [Byte1]: 39
2719 22:10:40.576292
2720 22:10:40.576391 Set Vref, RX VrefLevel [Byte0]: 40
2721 22:10:40.579680 [Byte1]: 40
2722 22:10:40.584508
2723 22:10:40.584601 Set Vref, RX VrefLevel [Byte0]: 41
2724 22:10:40.587530 [Byte1]: 41
2725 22:10:40.592432
2726 22:10:40.592507 Set Vref, RX VrefLevel [Byte0]: 42
2727 22:10:40.595708 [Byte1]: 42
2728 22:10:40.599983
2729 22:10:40.600077 Set Vref, RX VrefLevel [Byte0]: 43
2730 22:10:40.603329 [Byte1]: 43
2731 22:10:40.607687
2732 22:10:40.607766 Set Vref, RX VrefLevel [Byte0]: 44
2733 22:10:40.611266 [Byte1]: 44
2734 22:10:40.616152
2735 22:10:40.616256 Set Vref, RX VrefLevel [Byte0]: 45
2736 22:10:40.619500 [Byte1]: 45
2737 22:10:40.623601
2738 22:10:40.623702 Set Vref, RX VrefLevel [Byte0]: 46
2739 22:10:40.626922 [Byte1]: 46
2740 22:10:40.631601
2741 22:10:40.631697 Set Vref, RX VrefLevel [Byte0]: 47
2742 22:10:40.635280 [Byte1]: 47
2743 22:10:40.640169
2744 22:10:40.640263 Set Vref, RX VrefLevel [Byte0]: 48
2745 22:10:40.642991 [Byte1]: 48
2746 22:10:40.647739
2747 22:10:40.647830 Set Vref, RX VrefLevel [Byte0]: 49
2748 22:10:40.651206 [Byte1]: 49
2749 22:10:40.655471
2750 22:10:40.655569 Set Vref, RX VrefLevel [Byte0]: 50
2751 22:10:40.659081 [Byte1]: 50
2752 22:10:40.663603
2753 22:10:40.663695 Set Vref, RX VrefLevel [Byte0]: 51
2754 22:10:40.667079 [Byte1]: 51
2755 22:10:40.671155
2756 22:10:40.671248 Set Vref, RX VrefLevel [Byte0]: 52
2757 22:10:40.674649 [Byte1]: 52
2758 22:10:40.679309
2759 22:10:40.679402 Set Vref, RX VrefLevel [Byte0]: 53
2760 22:10:40.682480 [Byte1]: 53
2761 22:10:40.687282
2762 22:10:40.687368 Set Vref, RX VrefLevel [Byte0]: 54
2763 22:10:40.690497 [Byte1]: 54
2764 22:10:40.695292
2765 22:10:40.695380 Set Vref, RX VrefLevel [Byte0]: 55
2766 22:10:40.698730 [Byte1]: 55
2767 22:10:40.703130
2768 22:10:40.703225 Set Vref, RX VrefLevel [Byte0]: 56
2769 22:10:40.706709 [Byte1]: 56
2770 22:10:40.710944
2771 22:10:40.711033 Set Vref, RX VrefLevel [Byte0]: 57
2772 22:10:40.714818 [Byte1]: 57
2773 22:10:40.718849
2774 22:10:40.718940 Set Vref, RX VrefLevel [Byte0]: 58
2775 22:10:40.722139 [Byte1]: 58
2776 22:10:40.727154
2777 22:10:40.727235 Set Vref, RX VrefLevel [Byte0]: 59
2778 22:10:40.730301 [Byte1]: 59
2779 22:10:40.734863
2780 22:10:40.734944 Set Vref, RX VrefLevel [Byte0]: 60
2781 22:10:40.738184 [Byte1]: 60
2782 22:10:40.742888
2783 22:10:40.742977 Set Vref, RX VrefLevel [Byte0]: 61
2784 22:10:40.749373 [Byte1]: 61
2785 22:10:40.749454
2786 22:10:40.752371 Set Vref, RX VrefLevel [Byte0]: 62
2787 22:10:40.756108 [Byte1]: 62
2788 22:10:40.756205
2789 22:10:40.759137 Set Vref, RX VrefLevel [Byte0]: 63
2790 22:10:40.762597 [Byte1]: 63
2791 22:10:40.766276
2792 22:10:40.766372 Set Vref, RX VrefLevel [Byte0]: 64
2793 22:10:40.770098 [Byte1]: 64
2794 22:10:40.774745
2795 22:10:40.774825 Set Vref, RX VrefLevel [Byte0]: 65
2796 22:10:40.777683 [Byte1]: 65
2797 22:10:40.782661
2798 22:10:40.782750 Set Vref, RX VrefLevel [Byte0]: 66
2799 22:10:40.785642 [Byte1]: 66
2800 22:10:40.790342
2801 22:10:40.790432 Set Vref, RX VrefLevel [Byte0]: 67
2802 22:10:40.793682 [Byte1]: 67
2803 22:10:40.798321
2804 22:10:40.798453 Final RX Vref Byte 0 = 53 to rank0
2805 22:10:40.801409 Final RX Vref Byte 1 = 50 to rank0
2806 22:10:40.804943 Final RX Vref Byte 0 = 53 to rank1
2807 22:10:40.808412 Final RX Vref Byte 1 = 50 to rank1==
2808 22:10:40.811396 Dram Type= 6, Freq= 0, CH_0, rank 0
2809 22:10:40.815125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2810 22:10:40.818195 ==
2811 22:10:40.818305 DQS Delay:
2812 22:10:40.818415 DQS0 = 0, DQS1 = 0
2813 22:10:40.821594 DQM Delay:
2814 22:10:40.821699 DQM0 = 114, DQM1 = 105
2815 22:10:40.825156 DQ Delay:
2816 22:10:40.828732 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2817 22:10:40.831688 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2818 22:10:40.835252 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
2819 22:10:40.838394 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2820 22:10:40.838474
2821 22:10:40.838538
2822 22:10:40.845505 [DQSOSCAuto] RK0, (LSB)MR18= 0xfded, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 411 ps
2823 22:10:40.848409 CH0 RK0: MR19=303, MR18=FDED
2824 22:10:40.855119 CH0_RK0: MR19=0x303, MR18=0xFDED, DQSOSC=411, MR23=63, INC=38, DEC=25
2825 22:10:40.855254
2826 22:10:40.858787 ----->DramcWriteLeveling(PI) begin...
2827 22:10:40.858883 ==
2828 22:10:40.861819 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 22:10:40.865371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 22:10:40.865467 ==
2831 22:10:40.868316 Write leveling (Byte 0): 34 => 34
2832 22:10:40.871994 Write leveling (Byte 1): 30 => 30
2833 22:10:40.875101 DramcWriteLeveling(PI) end<-----
2834 22:10:40.875200
2835 22:10:40.875287 ==
2836 22:10:40.878469 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 22:10:40.881968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 22:10:40.885026 ==
2839 22:10:40.885102 [Gating] SW mode calibration
2840 22:10:40.892200 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2841 22:10:40.899085 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2842 22:10:40.901936 0 15 0 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
2843 22:10:40.908965 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
2844 22:10:40.911869 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 22:10:40.915288 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 22:10:40.918854 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 22:10:40.925702 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 22:10:40.928974 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 22:10:40.932452 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
2850 22:10:40.938876 1 0 0 | B1->B0 | 2d2d 2727 | 1 0 | (1 0) (0 0)
2851 22:10:40.942256 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 22:10:40.945639 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 22:10:40.952557 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 22:10:40.955839 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 22:10:40.959004 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 22:10:40.965661 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2857 22:10:40.969049 1 0 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2858 22:10:40.972532 1 1 0 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
2859 22:10:40.979220 1 1 4 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
2860 22:10:40.982772 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 22:10:40.985910 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 22:10:40.989406 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 22:10:40.996313 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 22:10:40.999263 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 22:10:41.002943 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2866 22:10:41.009690 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2867 22:10:41.012575 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2868 22:10:41.016107 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 22:10:41.022722 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 22:10:41.026340 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 22:10:41.029870 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 22:10:41.036431 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 22:10:41.039309 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 22:10:41.042995 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 22:10:41.046111 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 22:10:41.053109 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 22:10:41.056287 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 22:10:41.059612 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 22:10:41.066378 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 22:10:41.069776 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 22:10:41.073029 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2882 22:10:41.079565 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2883 22:10:41.079664 Total UI for P1: 0, mck2ui 16
2884 22:10:41.086306 best dqsien dly found for B0: ( 1, 3, 28)
2885 22:10:41.089917 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2886 22:10:41.093596 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 22:10:41.096532 Total UI for P1: 0, mck2ui 16
2888 22:10:41.100017 best dqsien dly found for B1: ( 1, 4, 2)
2889 22:10:41.103551 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2890 22:10:41.106599 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2891 22:10:41.106671
2892 22:10:41.110119 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2893 22:10:41.116805 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2894 22:10:41.116890 [Gating] SW calibration Done
2895 22:10:41.116960 ==
2896 22:10:41.120263 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 22:10:41.126764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 22:10:41.126838 ==
2899 22:10:41.126899 RX Vref Scan: 0
2900 22:10:41.126963
2901 22:10:41.130218 RX Vref 0 -> 0, step: 1
2902 22:10:41.130293
2903 22:10:41.133257 RX Delay -40 -> 252, step: 8
2904 22:10:41.136706 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2905 22:10:41.139916 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2906 22:10:41.142966 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2907 22:10:41.146576 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2908 22:10:41.153128 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2909 22:10:41.156682 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2910 22:10:41.160068 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2911 22:10:41.163451 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2912 22:10:41.166671 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2913 22:10:41.169996 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2914 22:10:41.176807 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2915 22:10:41.180036 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2916 22:10:41.183456 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2917 22:10:41.187257 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2918 22:10:41.193624 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2919 22:10:41.196778 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2920 22:10:41.196863 ==
2921 22:10:41.200286 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 22:10:41.203415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 22:10:41.203496 ==
2924 22:10:41.203559 DQS Delay:
2925 22:10:41.206901 DQS0 = 0, DQS1 = 0
2926 22:10:41.206980 DQM Delay:
2927 22:10:41.210208 DQM0 = 115, DQM1 = 105
2928 22:10:41.210332 DQ Delay:
2929 22:10:41.213713 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2930 22:10:41.216795 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2931 22:10:41.220353 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2932 22:10:41.223687 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2933 22:10:41.223775
2934 22:10:41.223835
2935 22:10:41.227046 ==
2936 22:10:41.227146 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 22:10:41.233602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 22:10:41.233702 ==
2939 22:10:41.233795
2940 22:10:41.233887
2941 22:10:41.237034 TX Vref Scan disable
2942 22:10:41.237151 == TX Byte 0 ==
2943 22:10:41.240831 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2944 22:10:41.247384 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2945 22:10:41.247484 == TX Byte 1 ==
2946 22:10:41.250971 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2947 22:10:41.257576 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2948 22:10:41.257653 ==
2949 22:10:41.260683 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 22:10:41.263789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 22:10:41.263861 ==
2952 22:10:41.275775 TX Vref=22, minBit 1, minWin=25, winSum=423
2953 22:10:41.279246 TX Vref=24, minBit 1, minWin=25, winSum=423
2954 22:10:41.282764 TX Vref=26, minBit 3, minWin=25, winSum=432
2955 22:10:41.286062 TX Vref=28, minBit 13, minWin=26, winSum=438
2956 22:10:41.289730 TX Vref=30, minBit 3, minWin=26, winSum=436
2957 22:10:41.292599 TX Vref=32, minBit 1, minWin=26, winSum=436
2958 22:10:41.299368 [TxChooseVref] Worse bit 13, Min win 26, Win sum 438, Final Vref 28
2959 22:10:41.299497
2960 22:10:41.302971 Final TX Range 1 Vref 28
2961 22:10:41.303055
2962 22:10:41.303118 ==
2963 22:10:41.306059 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 22:10:41.309539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 22:10:41.309627 ==
2966 22:10:41.309690
2967 22:10:41.309749
2968 22:10:41.312693 TX Vref Scan disable
2969 22:10:41.316057 == TX Byte 0 ==
2970 22:10:41.319841 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2971 22:10:41.322948 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2972 22:10:41.326152 == TX Byte 1 ==
2973 22:10:41.329574 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2974 22:10:41.333330 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2975 22:10:41.333428
2976 22:10:41.336271 [DATLAT]
2977 22:10:41.336368 Freq=1200, CH0 RK1
2978 22:10:41.336463
2979 22:10:41.339842 DATLAT Default: 0xd
2980 22:10:41.339936 0, 0xFFFF, sum = 0
2981 22:10:41.342923 1, 0xFFFF, sum = 0
2982 22:10:41.343003 2, 0xFFFF, sum = 0
2983 22:10:41.346549 3, 0xFFFF, sum = 0
2984 22:10:41.346629 4, 0xFFFF, sum = 0
2985 22:10:41.350266 5, 0xFFFF, sum = 0
2986 22:10:41.350390 6, 0xFFFF, sum = 0
2987 22:10:41.353214 7, 0xFFFF, sum = 0
2988 22:10:41.353305 8, 0xFFFF, sum = 0
2989 22:10:41.356378 9, 0xFFFF, sum = 0
2990 22:10:41.356458 10, 0xFFFF, sum = 0
2991 22:10:41.359854 11, 0xFFFF, sum = 0
2992 22:10:41.359934 12, 0x0, sum = 1
2993 22:10:41.363438 13, 0x0, sum = 2
2994 22:10:41.363544 14, 0x0, sum = 3
2995 22:10:41.366852 15, 0x0, sum = 4
2996 22:10:41.366949 best_step = 13
2997 22:10:41.367034
2998 22:10:41.367125 ==
2999 22:10:41.369736 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 22:10:41.376799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 22:10:41.376874 ==
3002 22:10:41.376935 RX Vref Scan: 0
3003 22:10:41.376992
3004 22:10:41.379811 RX Vref 0 -> 0, step: 1
3005 22:10:41.379904
3006 22:10:41.383034 RX Delay -21 -> 252, step: 4
3007 22:10:41.386500 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3008 22:10:41.390256 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3009 22:10:41.393514 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3010 22:10:41.400148 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3011 22:10:41.403355 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3012 22:10:41.406876 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3013 22:10:41.409915 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3014 22:10:41.413438 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3015 22:10:41.420154 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3016 22:10:41.423587 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3017 22:10:41.427170 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3018 22:10:41.430496 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3019 22:10:41.433481 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3020 22:10:41.440219 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3021 22:10:41.443676 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3022 22:10:41.447319 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3023 22:10:41.447415 ==
3024 22:10:41.450243 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 22:10:41.453836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 22:10:41.453931 ==
3027 22:10:41.457604 DQS Delay:
3028 22:10:41.457675 DQS0 = 0, DQS1 = 0
3029 22:10:41.457734 DQM Delay:
3030 22:10:41.460506 DQM0 = 114, DQM1 = 104
3031 22:10:41.460608 DQ Delay:
3032 22:10:41.463966 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3033 22:10:41.467749 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =122
3034 22:10:41.470933 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =94
3035 22:10:41.477381 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3036 22:10:41.477485
3037 22:10:41.477574
3038 22:10:41.484245 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3039 22:10:41.487737 CH0 RK1: MR19=403, MR18=2F3
3040 22:10:41.494422 CH0_RK1: MR19=0x403, MR18=0x2F3, DQSOSC=409, MR23=63, INC=39, DEC=26
3041 22:10:41.494497 [RxdqsGatingPostProcess] freq 1200
3042 22:10:41.500594 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3043 22:10:41.504185 best DQS0 dly(2T, 0.5T) = (0, 12)
3044 22:10:41.508229 best DQS1 dly(2T, 0.5T) = (0, 12)
3045 22:10:41.511009 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3046 22:10:41.514729 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3047 22:10:41.517766 best DQS0 dly(2T, 0.5T) = (0, 11)
3048 22:10:41.521346 best DQS1 dly(2T, 0.5T) = (0, 12)
3049 22:10:41.524451 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3050 22:10:41.524554 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3051 22:10:41.528062 Pre-setting of DQS Precalculation
3052 22:10:41.534590 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3053 22:10:41.534688 ==
3054 22:10:41.538614 Dram Type= 6, Freq= 0, CH_1, rank 0
3055 22:10:41.541256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 22:10:41.541352 ==
3057 22:10:41.548117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3058 22:10:41.554798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3059 22:10:41.561638 [CA 0] Center 38 (8~68) winsize 61
3060 22:10:41.565233 [CA 1] Center 38 (8~68) winsize 61
3061 22:10:41.568206 [CA 2] Center 35 (5~65) winsize 61
3062 22:10:41.571921 [CA 3] Center 34 (4~65) winsize 62
3063 22:10:41.574935 [CA 4] Center 34 (4~65) winsize 62
3064 22:10:41.578474 [CA 5] Center 34 (4~64) winsize 61
3065 22:10:41.578552
3066 22:10:41.581937 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3067 22:10:41.582017
3068 22:10:41.585036 [CATrainingPosCal] consider 1 rank data
3069 22:10:41.588479 u2DelayCellTimex100 = 270/100 ps
3070 22:10:41.591796 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3071 22:10:41.595245 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3072 22:10:41.598485 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3073 22:10:41.605212 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3074 22:10:41.608864 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3075 22:10:41.611901 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3076 22:10:41.612001
3077 22:10:41.615522 CA PerBit enable=1, Macro0, CA PI delay=34
3078 22:10:41.615621
3079 22:10:41.618783 [CBTSetCACLKResult] CA Dly = 34
3080 22:10:41.618886 CS Dly: 6 (0~37)
3081 22:10:41.618976 ==
3082 22:10:41.622475 Dram Type= 6, Freq= 0, CH_1, rank 1
3083 22:10:41.625351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 22:10:41.629143 ==
3085 22:10:41.632314 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3086 22:10:41.638912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3087 22:10:41.646924 [CA 0] Center 38 (8~68) winsize 61
3088 22:10:41.650728 [CA 1] Center 38 (9~68) winsize 60
3089 22:10:41.653836 [CA 2] Center 34 (4~65) winsize 62
3090 22:10:41.657418 [CA 3] Center 34 (4~65) winsize 62
3091 22:10:41.660284 [CA 4] Center 34 (4~65) winsize 62
3092 22:10:41.663828 [CA 5] Center 33 (3~64) winsize 62
3093 22:10:41.663927
3094 22:10:41.667626 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3095 22:10:41.667723
3096 22:10:41.670669 [CATrainingPosCal] consider 2 rank data
3097 22:10:41.674217 u2DelayCellTimex100 = 270/100 ps
3098 22:10:41.677206 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3099 22:10:41.680862 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3100 22:10:41.684233 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3101 22:10:41.691012 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3102 22:10:41.694186 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3103 22:10:41.697570 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3104 22:10:41.697668
3105 22:10:41.701112 CA PerBit enable=1, Macro0, CA PI delay=34
3106 22:10:41.701198
3107 22:10:41.704019 [CBTSetCACLKResult] CA Dly = 34
3108 22:10:41.704097 CS Dly: 7 (0~40)
3109 22:10:41.704159
3110 22:10:41.707341 ----->DramcWriteLeveling(PI) begin...
3111 22:10:41.707455 ==
3112 22:10:41.710701 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 22:10:41.717750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 22:10:41.717860 ==
3115 22:10:41.720912 Write leveling (Byte 0): 25 => 25
3116 22:10:41.721012 Write leveling (Byte 1): 31 => 31
3117 22:10:41.724213 DramcWriteLeveling(PI) end<-----
3118 22:10:41.724318
3119 22:10:41.727632 ==
3120 22:10:41.727734 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 22:10:41.734717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 22:10:41.734829 ==
3123 22:10:41.738092 [Gating] SW mode calibration
3124 22:10:41.744436 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3125 22:10:41.748155 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3126 22:10:41.751458 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3127 22:10:41.758597 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 22:10:41.761820 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 22:10:41.764640 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3130 22:10:41.771782 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3131 22:10:41.774754 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 22:10:41.778383 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
3133 22:10:41.784990 0 15 28 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 0)
3134 22:10:41.788464 1 0 0 | B1->B0 | 2525 2c2c | 0 0 | (1 1) (0 0)
3135 22:10:41.792158 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 22:10:41.798242 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3137 22:10:41.801777 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 22:10:41.805306 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3139 22:10:41.811678 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 22:10:41.815268 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 22:10:41.818232 1 0 28 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
3142 22:10:41.821770 1 1 0 | B1->B0 | 4646 3a3a | 0 0 | (0 0) (0 0)
3143 22:10:41.828218 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 22:10:41.832083 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 22:10:41.835277 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 22:10:41.842079 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 22:10:41.845221 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 22:10:41.848346 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 22:10:41.855380 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 22:10:41.858857 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 22:10:41.861996 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3152 22:10:41.868852 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 22:10:41.871871 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 22:10:41.875351 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 22:10:41.879081 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 22:10:41.885721 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 22:10:41.888794 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 22:10:41.892238 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 22:10:41.899412 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 22:10:41.902327 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 22:10:41.906037 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 22:10:41.912638 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 22:10:41.915578 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 22:10:41.919153 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 22:10:41.926089 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3166 22:10:41.929584 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3167 22:10:41.932786 Total UI for P1: 0, mck2ui 16
3168 22:10:41.935818 best dqsien dly found for B1: ( 1, 3, 30)
3169 22:10:41.939219 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 22:10:41.942736 Total UI for P1: 0, mck2ui 16
3171 22:10:41.946158 best dqsien dly found for B0: ( 1, 3, 30)
3172 22:10:41.949713 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3173 22:10:41.952710 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3174 22:10:41.952801
3175 22:10:41.956358 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3176 22:10:41.959602 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3177 22:10:41.962940 [Gating] SW calibration Done
3178 22:10:41.963019 ==
3179 22:10:41.966674 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 22:10:41.969420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 22:10:41.973227 ==
3182 22:10:41.973306 RX Vref Scan: 0
3183 22:10:41.973407
3184 22:10:41.976267 RX Vref 0 -> 0, step: 1
3185 22:10:41.976346
3186 22:10:41.980182 RX Delay -40 -> 252, step: 8
3187 22:10:41.982749 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3188 22:10:41.986525 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3189 22:10:41.989970 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3190 22:10:41.992931 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3191 22:10:42.000123 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3192 22:10:42.002981 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3193 22:10:42.006642 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3194 22:10:42.009604 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3195 22:10:42.013312 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3196 22:10:42.016279 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3197 22:10:42.023502 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3198 22:10:42.026535 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3199 22:10:42.030011 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3200 22:10:42.033417 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3201 22:10:42.037010 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3202 22:10:42.043385 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3203 22:10:42.043465 ==
3204 22:10:42.046799 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 22:10:42.050134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 22:10:42.050214 ==
3207 22:10:42.050276 DQS Delay:
3208 22:10:42.053626 DQS0 = 0, DQS1 = 0
3209 22:10:42.053704 DQM Delay:
3210 22:10:42.056735 DQM0 = 116, DQM1 = 109
3211 22:10:42.056848 DQ Delay:
3212 22:10:42.060176 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3213 22:10:42.063903 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3214 22:10:42.066933 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3215 22:10:42.070010 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3216 22:10:42.070105
3217 22:10:42.070196
3218 22:10:42.070283 ==
3219 22:10:42.073406 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 22:10:42.080063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 22:10:42.080168 ==
3222 22:10:42.080260
3223 22:10:42.080347
3224 22:10:42.080435 TX Vref Scan disable
3225 22:10:42.083805 == TX Byte 0 ==
3226 22:10:42.087087 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3227 22:10:42.091061 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3228 22:10:42.093889 == TX Byte 1 ==
3229 22:10:42.097412 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3230 22:10:42.100434 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3231 22:10:42.104123 ==
3232 22:10:42.104202 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 22:10:42.110711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 22:10:42.110791 ==
3235 22:10:42.121920 TX Vref=22, minBit 1, minWin=24, winSum=411
3236 22:10:42.125477 TX Vref=24, minBit 15, minWin=24, winSum=413
3237 22:10:42.129008 TX Vref=26, minBit 5, minWin=25, winSum=420
3238 22:10:42.131982 TX Vref=28, minBit 15, minWin=25, winSum=426
3239 22:10:42.135685 TX Vref=30, minBit 1, minWin=26, winSum=425
3240 22:10:42.139080 TX Vref=32, minBit 1, minWin=26, winSum=428
3241 22:10:42.145447 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 32
3242 22:10:42.145543
3243 22:10:42.149187 Final TX Range 1 Vref 32
3244 22:10:42.149309
3245 22:10:42.149400 ==
3246 22:10:42.152783 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 22:10:42.155950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 22:10:42.156059 ==
3249 22:10:42.156160
3250 22:10:42.156249
3251 22:10:42.158800 TX Vref Scan disable
3252 22:10:42.162245 == TX Byte 0 ==
3253 22:10:42.165878 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3254 22:10:42.168931 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3255 22:10:42.172583 == TX Byte 1 ==
3256 22:10:42.175691 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3257 22:10:42.179186 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3258 22:10:42.179288
3259 22:10:42.182824 [DATLAT]
3260 22:10:42.182927 Freq=1200, CH1 RK0
3261 22:10:42.183023
3262 22:10:42.185640 DATLAT Default: 0xd
3263 22:10:42.185742 0, 0xFFFF, sum = 0
3264 22:10:42.188879 1, 0xFFFF, sum = 0
3265 22:10:42.188983 2, 0xFFFF, sum = 0
3266 22:10:42.192370 3, 0xFFFF, sum = 0
3267 22:10:42.192477 4, 0xFFFF, sum = 0
3268 22:10:42.195811 5, 0xFFFF, sum = 0
3269 22:10:42.195884 6, 0xFFFF, sum = 0
3270 22:10:42.199573 7, 0xFFFF, sum = 0
3271 22:10:42.199685 8, 0xFFFF, sum = 0
3272 22:10:42.202704 9, 0xFFFF, sum = 0
3273 22:10:42.202812 10, 0xFFFF, sum = 0
3274 22:10:42.205825 11, 0xFFFF, sum = 0
3275 22:10:42.205932 12, 0x0, sum = 1
3276 22:10:42.209306 13, 0x0, sum = 2
3277 22:10:42.209387 14, 0x0, sum = 3
3278 22:10:42.212850 15, 0x0, sum = 4
3279 22:10:42.212931 best_step = 13
3280 22:10:42.212993
3281 22:10:42.213051 ==
3282 22:10:42.215758 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 22:10:42.222777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 22:10:42.222878 ==
3285 22:10:42.222978 RX Vref Scan: 1
3286 22:10:42.223074
3287 22:10:42.226161 Set Vref Range= 32 -> 127
3288 22:10:42.226267
3289 22:10:42.229166 RX Vref 32 -> 127, step: 1
3290 22:10:42.229276
3291 22:10:42.229368 RX Delay -21 -> 252, step: 4
3292 22:10:42.229466
3293 22:10:42.232811 Set Vref, RX VrefLevel [Byte0]: 32
3294 22:10:42.235945 [Byte1]: 32
3295 22:10:42.240822
3296 22:10:42.240925 Set Vref, RX VrefLevel [Byte0]: 33
3297 22:10:42.243893 [Byte1]: 33
3298 22:10:42.248514
3299 22:10:42.248619 Set Vref, RX VrefLevel [Byte0]: 34
3300 22:10:42.251961 [Byte1]: 34
3301 22:10:42.256345
3302 22:10:42.256459 Set Vref, RX VrefLevel [Byte0]: 35
3303 22:10:42.259464 [Byte1]: 35
3304 22:10:42.264394
3305 22:10:42.264475 Set Vref, RX VrefLevel [Byte0]: 36
3306 22:10:42.267766 [Byte1]: 36
3307 22:10:42.272297
3308 22:10:42.272377 Set Vref, RX VrefLevel [Byte0]: 37
3309 22:10:42.275312 [Byte1]: 37
3310 22:10:42.280089
3311 22:10:42.280168 Set Vref, RX VrefLevel [Byte0]: 38
3312 22:10:42.283201 [Byte1]: 38
3313 22:10:42.288024
3314 22:10:42.288128 Set Vref, RX VrefLevel [Byte0]: 39
3315 22:10:42.291343 [Byte1]: 39
3316 22:10:42.295802
3317 22:10:42.295905 Set Vref, RX VrefLevel [Byte0]: 40
3318 22:10:42.299353 [Byte1]: 40
3319 22:10:42.304119
3320 22:10:42.304224 Set Vref, RX VrefLevel [Byte0]: 41
3321 22:10:42.306878 [Byte1]: 41
3322 22:10:42.311545
3323 22:10:42.311651 Set Vref, RX VrefLevel [Byte0]: 42
3324 22:10:42.314930 [Byte1]: 42
3325 22:10:42.319685
3326 22:10:42.319786 Set Vref, RX VrefLevel [Byte0]: 43
3327 22:10:42.323027 [Byte1]: 43
3328 22:10:42.327337
3329 22:10:42.327453 Set Vref, RX VrefLevel [Byte0]: 44
3330 22:10:42.330669 [Byte1]: 44
3331 22:10:42.335597
3332 22:10:42.335704 Set Vref, RX VrefLevel [Byte0]: 45
3333 22:10:42.338630 [Byte1]: 45
3334 22:10:42.343419
3335 22:10:42.343524 Set Vref, RX VrefLevel [Byte0]: 46
3336 22:10:42.346524 [Byte1]: 46
3337 22:10:42.351345
3338 22:10:42.351456 Set Vref, RX VrefLevel [Byte0]: 47
3339 22:10:42.354797 [Byte1]: 47
3340 22:10:42.359517
3341 22:10:42.359630 Set Vref, RX VrefLevel [Byte0]: 48
3342 22:10:42.362901 [Byte1]: 48
3343 22:10:42.367047
3344 22:10:42.367157 Set Vref, RX VrefLevel [Byte0]: 49
3345 22:10:42.370367 [Byte1]: 49
3346 22:10:42.375392
3347 22:10:42.375496 Set Vref, RX VrefLevel [Byte0]: 50
3348 22:10:42.378649 [Byte1]: 50
3349 22:10:42.382858
3350 22:10:42.382960 Set Vref, RX VrefLevel [Byte0]: 51
3351 22:10:42.386763 [Byte1]: 51
3352 22:10:42.390844
3353 22:10:42.390948 Set Vref, RX VrefLevel [Byte0]: 52
3354 22:10:42.394597 [Byte1]: 52
3355 22:10:42.399126
3356 22:10:42.399229 Set Vref, RX VrefLevel [Byte0]: 53
3357 22:10:42.402335 [Byte1]: 53
3358 22:10:42.406585
3359 22:10:42.406686 Set Vref, RX VrefLevel [Byte0]: 54
3360 22:10:42.410232 [Byte1]: 54
3361 22:10:42.415001
3362 22:10:42.415109 Set Vref, RX VrefLevel [Byte0]: 55
3363 22:10:42.418231 [Byte1]: 55
3364 22:10:42.422678
3365 22:10:42.422789 Set Vref, RX VrefLevel [Byte0]: 56
3366 22:10:42.426138 [Byte1]: 56
3367 22:10:42.430414
3368 22:10:42.430519 Set Vref, RX VrefLevel [Byte0]: 57
3369 22:10:42.433672 [Byte1]: 57
3370 22:10:42.438609
3371 22:10:42.438716 Set Vref, RX VrefLevel [Byte0]: 58
3372 22:10:42.441647 [Byte1]: 58
3373 22:10:42.446420
3374 22:10:42.446527 Set Vref, RX VrefLevel [Byte0]: 59
3375 22:10:42.449496 [Byte1]: 59
3376 22:10:42.454507
3377 22:10:42.454619 Set Vref, RX VrefLevel [Byte0]: 60
3378 22:10:42.457452 [Byte1]: 60
3379 22:10:42.462322
3380 22:10:42.462427 Set Vref, RX VrefLevel [Byte0]: 61
3381 22:10:42.465646 [Byte1]: 61
3382 22:10:42.470341
3383 22:10:42.470441 Set Vref, RX VrefLevel [Byte0]: 62
3384 22:10:42.473485 [Byte1]: 62
3385 22:10:42.477928
3386 22:10:42.478031 Set Vref, RX VrefLevel [Byte0]: 63
3387 22:10:42.481457 [Byte1]: 63
3388 22:10:42.486206
3389 22:10:42.486308 Set Vref, RX VrefLevel [Byte0]: 64
3390 22:10:42.489417 [Byte1]: 64
3391 22:10:42.494092
3392 22:10:42.494207 Set Vref, RX VrefLevel [Byte0]: 65
3393 22:10:42.497091 [Byte1]: 65
3394 22:10:42.501758
3395 22:10:42.501862 Set Vref, RX VrefLevel [Byte0]: 66
3396 22:10:42.505054 [Byte1]: 66
3397 22:10:42.509657
3398 22:10:42.509762 Set Vref, RX VrefLevel [Byte0]: 67
3399 22:10:42.512920 [Byte1]: 67
3400 22:10:42.517585
3401 22:10:42.517689 Set Vref, RX VrefLevel [Byte0]: 68
3402 22:10:42.521254 [Byte1]: 68
3403 22:10:42.525672
3404 22:10:42.525777 Set Vref, RX VrefLevel [Byte0]: 69
3405 22:10:42.528848 [Byte1]: 69
3406 22:10:42.533350
3407 22:10:42.533451 Set Vref, RX VrefLevel [Byte0]: 70
3408 22:10:42.536814 [Byte1]: 70
3409 22:10:42.541247
3410 22:10:42.541352 Final RX Vref Byte 0 = 57 to rank0
3411 22:10:42.544563 Final RX Vref Byte 1 = 50 to rank0
3412 22:10:42.547977 Final RX Vref Byte 0 = 57 to rank1
3413 22:10:42.551651 Final RX Vref Byte 1 = 50 to rank1==
3414 22:10:42.555186 Dram Type= 6, Freq= 0, CH_1, rank 0
3415 22:10:42.558189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3416 22:10:42.561858 ==
3417 22:10:42.561940 DQS Delay:
3418 22:10:42.562051 DQS0 = 0, DQS1 = 0
3419 22:10:42.565068 DQM Delay:
3420 22:10:42.565149 DQM0 = 115, DQM1 = 108
3421 22:10:42.568323 DQ Delay:
3422 22:10:42.571471 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3423 22:10:42.575029 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =112
3424 22:10:42.578479 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3425 22:10:42.581919 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3426 22:10:42.582027
3427 22:10:42.582121
3428 22:10:42.588459 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
3429 22:10:42.591737 CH1 RK0: MR19=403, MR18=1E6
3430 22:10:42.598275 CH1_RK0: MR19=0x403, MR18=0x1E6, DQSOSC=409, MR23=63, INC=39, DEC=26
3431 22:10:42.598379
3432 22:10:42.601858 ----->DramcWriteLeveling(PI) begin...
3433 22:10:42.601960 ==
3434 22:10:42.605060 Dram Type= 6, Freq= 0, CH_1, rank 1
3435 22:10:42.608491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3436 22:10:42.608596 ==
3437 22:10:42.611603 Write leveling (Byte 0): 26 => 26
3438 22:10:42.615187 Write leveling (Byte 1): 29 => 29
3439 22:10:42.618796 DramcWriteLeveling(PI) end<-----
3440 22:10:42.618876
3441 22:10:42.618940 ==
3442 22:10:42.621719 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 22:10:42.625411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3444 22:10:42.625490 ==
3445 22:10:42.628288 [Gating] SW mode calibration
3446 22:10:42.635187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3447 22:10:42.641879 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3448 22:10:42.645245 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3449 22:10:42.648620 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 22:10:42.655528 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 22:10:42.658826 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 22:10:42.662624 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 22:10:42.669076 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3454 22:10:42.672623 0 15 24 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 1)
3455 22:10:42.675784 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3456 22:10:42.682359 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 22:10:42.685771 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3458 22:10:42.689326 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 22:10:42.695784 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 22:10:42.699099 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 22:10:42.702555 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 22:10:42.709047 1 0 24 | B1->B0 | 2a2a 4343 | 0 0 | (0 0) (0 0)
3463 22:10:42.712701 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
3464 22:10:42.715760 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 22:10:42.718818 1 1 4 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
3466 22:10:42.726033 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 22:10:42.728933 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 22:10:42.732620 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 22:10:42.738955 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 22:10:42.742406 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3471 22:10:42.745934 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3472 22:10:42.752311 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 22:10:42.755828 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 22:10:42.759257 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 22:10:42.765627 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 22:10:42.769162 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 22:10:42.772504 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 22:10:42.779291 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 22:10:42.782812 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 22:10:42.785860 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 22:10:42.792370 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 22:10:42.795927 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 22:10:42.799172 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 22:10:42.802402 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 22:10:42.809025 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3486 22:10:42.812580 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3487 22:10:42.816303 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
3488 22:10:42.819260 Total UI for P1: 0, mck2ui 16
3489 22:10:42.822290 best dqsien dly found for B0: ( 1, 3, 22)
3490 22:10:42.829345 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 22:10:42.829427 Total UI for P1: 0, mck2ui 16
3492 22:10:42.836062 best dqsien dly found for B1: ( 1, 3, 30)
3493 22:10:42.839577 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3494 22:10:42.843095 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3495 22:10:42.843203
3496 22:10:42.846433 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3497 22:10:42.849442 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3498 22:10:42.852587 [Gating] SW calibration Done
3499 22:10:42.852694 ==
3500 22:10:42.855977 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 22:10:42.859430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 22:10:42.859546 ==
3503 22:10:42.862765 RX Vref Scan: 0
3504 22:10:42.862875
3505 22:10:42.862979 RX Vref 0 -> 0, step: 1
3506 22:10:42.863075
3507 22:10:42.866131 RX Delay -40 -> 252, step: 8
3508 22:10:42.869407 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3509 22:10:42.875895 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3510 22:10:42.879371 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3511 22:10:42.883010 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3512 22:10:42.886005 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3513 22:10:42.889762 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3514 22:10:42.895871 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3515 22:10:42.899684 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3516 22:10:42.902969 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3517 22:10:42.905943 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3518 22:10:42.909446 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3519 22:10:42.912868 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3520 22:10:42.919686 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3521 22:10:42.922595 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3522 22:10:42.926129 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3523 22:10:42.929299 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3524 22:10:42.929398 ==
3525 22:10:42.932608 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 22:10:42.939919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 22:10:42.940002 ==
3528 22:10:42.940066 DQS Delay:
3529 22:10:42.942998 DQS0 = 0, DQS1 = 0
3530 22:10:42.943078 DQM Delay:
3531 22:10:42.943142 DQM0 = 113, DQM1 = 109
3532 22:10:42.946463 DQ Delay:
3533 22:10:42.949378 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3534 22:10:42.952997 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =107
3535 22:10:42.956118 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3536 22:10:42.959622 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3537 22:10:42.959734
3538 22:10:42.959845
3539 22:10:42.959938 ==
3540 22:10:42.963060 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 22:10:42.966344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 22:10:42.966418 ==
3543 22:10:42.966479
3544 22:10:42.969630
3545 22:10:42.969703 TX Vref Scan disable
3546 22:10:42.973026 == TX Byte 0 ==
3547 22:10:42.977045 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3548 22:10:42.979419 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3549 22:10:42.982852 == TX Byte 1 ==
3550 22:10:42.986392 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3551 22:10:42.989451 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3552 22:10:42.989531 ==
3553 22:10:42.993002 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 22:10:42.999602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 22:10:42.999683 ==
3556 22:10:43.010297 TX Vref=22, minBit 3, minWin=25, winSum=413
3557 22:10:43.013303 TX Vref=24, minBit 0, minWin=25, winSum=424
3558 22:10:43.016812 TX Vref=26, minBit 0, minWin=26, winSum=427
3559 22:10:43.020352 TX Vref=28, minBit 1, minWin=26, winSum=430
3560 22:10:43.023627 TX Vref=30, minBit 8, minWin=26, winSum=431
3561 22:10:43.026808 TX Vref=32, minBit 5, minWin=26, winSum=433
3562 22:10:43.033458 [TxChooseVref] Worse bit 5, Min win 26, Win sum 433, Final Vref 32
3563 22:10:43.033540
3564 22:10:43.037144 Final TX Range 1 Vref 32
3565 22:10:43.037226
3566 22:10:43.037291 ==
3567 22:10:43.040138 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 22:10:43.043814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 22:10:43.043895 ==
3570 22:10:43.043959
3571 22:10:43.044019
3572 22:10:43.047371 TX Vref Scan disable
3573 22:10:43.050076 == TX Byte 0 ==
3574 22:10:43.053668 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3575 22:10:43.057098 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3576 22:10:43.060207 == TX Byte 1 ==
3577 22:10:43.063851 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3578 22:10:43.067008 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3579 22:10:43.067108
3580 22:10:43.070370 [DATLAT]
3581 22:10:43.070472 Freq=1200, CH1 RK1
3582 22:10:43.070564
3583 22:10:43.073818 DATLAT Default: 0xd
3584 22:10:43.073918 0, 0xFFFF, sum = 0
3585 22:10:43.076945 1, 0xFFFF, sum = 0
3586 22:10:43.077049 2, 0xFFFF, sum = 0
3587 22:10:43.080135 3, 0xFFFF, sum = 0
3588 22:10:43.080245 4, 0xFFFF, sum = 0
3589 22:10:43.083698 5, 0xFFFF, sum = 0
3590 22:10:43.083803 6, 0xFFFF, sum = 0
3591 22:10:43.086931 7, 0xFFFF, sum = 0
3592 22:10:43.087049 8, 0xFFFF, sum = 0
3593 22:10:43.090199 9, 0xFFFF, sum = 0
3594 22:10:43.090286 10, 0xFFFF, sum = 0
3595 22:10:43.093660 11, 0xFFFF, sum = 0
3596 22:10:43.093736 12, 0x0, sum = 1
3597 22:10:43.096803 13, 0x0, sum = 2
3598 22:10:43.096909 14, 0x0, sum = 3
3599 22:10:43.100379 15, 0x0, sum = 4
3600 22:10:43.100482 best_step = 13
3601 22:10:43.100573
3602 22:10:43.100662 ==
3603 22:10:43.104070 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 22:10:43.110611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 22:10:43.110739 ==
3606 22:10:43.110862 RX Vref Scan: 0
3607 22:10:43.110993
3608 22:10:43.113440 RX Vref 0 -> 0, step: 1
3609 22:10:43.113545
3610 22:10:43.116931 RX Delay -13 -> 252, step: 4
3611 22:10:43.120450 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3612 22:10:43.123543 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3613 22:10:43.130613 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3614 22:10:43.133720 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3615 22:10:43.137295 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3616 22:10:43.140281 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3617 22:10:43.143894 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3618 22:10:43.146846 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3619 22:10:43.153878 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3620 22:10:43.157134 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3621 22:10:43.160544 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3622 22:10:43.164116 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3623 22:10:43.167128 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3624 22:10:43.173900 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3625 22:10:43.176879 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3626 22:10:43.180435 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3627 22:10:43.180542 ==
3628 22:10:43.183523 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 22:10:43.187306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 22:10:43.187405 ==
3631 22:10:43.190362 DQS Delay:
3632 22:10:43.190463 DQS0 = 0, DQS1 = 0
3633 22:10:43.193890 DQM Delay:
3634 22:10:43.193988 DQM0 = 113, DQM1 = 109
3635 22:10:43.197376 DQ Delay:
3636 22:10:43.200474 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3637 22:10:43.203705 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3638 22:10:43.207445 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =100
3639 22:10:43.210276 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3640 22:10:43.210376
3641 22:10:43.210477
3642 22:10:43.217396 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3643 22:10:43.220805 CH1 RK1: MR19=303, MR18=F6FC
3644 22:10:43.227387 CH1_RK1: MR19=0x303, MR18=0xF6FC, DQSOSC=411, MR23=63, INC=38, DEC=25
3645 22:10:43.230371 [RxdqsGatingPostProcess] freq 1200
3646 22:10:43.236944 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3647 22:10:43.237055 best DQS0 dly(2T, 0.5T) = (0, 11)
3648 22:10:43.240672 best DQS1 dly(2T, 0.5T) = (0, 11)
3649 22:10:43.243944 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3650 22:10:43.247159 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3651 22:10:43.250754 best DQS0 dly(2T, 0.5T) = (0, 11)
3652 22:10:43.254293 best DQS1 dly(2T, 0.5T) = (0, 11)
3653 22:10:43.257110 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3654 22:10:43.260883 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3655 22:10:43.264155 Pre-setting of DQS Precalculation
3656 22:10:43.267457 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3657 22:10:43.277499 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3658 22:10:43.284375 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3659 22:10:43.284456
3660 22:10:43.284518
3661 22:10:43.287226 [Calibration Summary] 2400 Mbps
3662 22:10:43.287305 CH 0, Rank 0
3663 22:10:43.290345 SW Impedance : PASS
3664 22:10:43.290424 DUTY Scan : NO K
3665 22:10:43.293976 ZQ Calibration : PASS
3666 22:10:43.297746 Jitter Meter : NO K
3667 22:10:43.297825 CBT Training : PASS
3668 22:10:43.300483 Write leveling : PASS
3669 22:10:43.304083 RX DQS gating : PASS
3670 22:10:43.304164 RX DQ/DQS(RDDQC) : PASS
3671 22:10:43.307266 TX DQ/DQS : PASS
3672 22:10:43.310521 RX DATLAT : PASS
3673 22:10:43.310602 RX DQ/DQS(Engine): PASS
3674 22:10:43.313985 TX OE : NO K
3675 22:10:43.314065 All Pass.
3676 22:10:43.314129
3677 22:10:43.317265 CH 0, Rank 1
3678 22:10:43.317345 SW Impedance : PASS
3679 22:10:43.320607 DUTY Scan : NO K
3680 22:10:43.324146 ZQ Calibration : PASS
3681 22:10:43.324253 Jitter Meter : NO K
3682 22:10:43.327053 CBT Training : PASS
3683 22:10:43.327154 Write leveling : PASS
3684 22:10:43.330592 RX DQS gating : PASS
3685 22:10:43.333562 RX DQ/DQS(RDDQC) : PASS
3686 22:10:43.333664 TX DQ/DQS : PASS
3687 22:10:43.337382 RX DATLAT : PASS
3688 22:10:43.340332 RX DQ/DQS(Engine): PASS
3689 22:10:43.340447 TX OE : NO K
3690 22:10:43.343787 All Pass.
3691 22:10:43.343887
3692 22:10:43.343980 CH 1, Rank 0
3693 22:10:43.347313 SW Impedance : PASS
3694 22:10:43.347414 DUTY Scan : NO K
3695 22:10:43.350633 ZQ Calibration : PASS
3696 22:10:43.353569 Jitter Meter : NO K
3697 22:10:43.353673 CBT Training : PASS
3698 22:10:43.357225 Write leveling : PASS
3699 22:10:43.360278 RX DQS gating : PASS
3700 22:10:43.360388 RX DQ/DQS(RDDQC) : PASS
3701 22:10:43.363612 TX DQ/DQS : PASS
3702 22:10:43.363714 RX DATLAT : PASS
3703 22:10:43.367463 RX DQ/DQS(Engine): PASS
3704 22:10:43.370306 TX OE : NO K
3705 22:10:43.370416 All Pass.
3706 22:10:43.370506
3707 22:10:43.370594 CH 1, Rank 1
3708 22:10:43.373716 SW Impedance : PASS
3709 22:10:43.377613 DUTY Scan : NO K
3710 22:10:43.377717 ZQ Calibration : PASS
3711 22:10:43.380702 Jitter Meter : NO K
3712 22:10:43.384328 CBT Training : PASS
3713 22:10:43.384427 Write leveling : PASS
3714 22:10:43.387306 RX DQS gating : PASS
3715 22:10:43.390334 RX DQ/DQS(RDDQC) : PASS
3716 22:10:43.390433 TX DQ/DQS : PASS
3717 22:10:43.393968 RX DATLAT : PASS
3718 22:10:43.396949 RX DQ/DQS(Engine): PASS
3719 22:10:43.397047 TX OE : NO K
3720 22:10:43.397137 All Pass.
3721 22:10:43.400724
3722 22:10:43.400883 DramC Write-DBI off
3723 22:10:43.404163 PER_BANK_REFRESH: Hybrid Mode
3724 22:10:43.404294 TX_TRACKING: ON
3725 22:10:43.414082 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3726 22:10:43.417387 [FAST_K] Save calibration result to emmc
3727 22:10:43.421003 dramc_set_vcore_voltage set vcore to 650000
3728 22:10:43.423799 Read voltage for 600, 5
3729 22:10:43.423901 Vio18 = 0
3730 22:10:43.427293 Vcore = 650000
3731 22:10:43.427391 Vdram = 0
3732 22:10:43.427482 Vddq = 0
3733 22:10:43.427570 Vmddr = 0
3734 22:10:43.433796 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3735 22:10:43.437353 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3736 22:10:43.440962 MEM_TYPE=3, freq_sel=19
3737 22:10:43.443926 sv_algorithm_assistance_LP4_1600
3738 22:10:43.447491 ============ PULL DRAM RESETB DOWN ============
3739 22:10:43.453981 ========== PULL DRAM RESETB DOWN end =========
3740 22:10:43.457694 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3741 22:10:43.460553 ===================================
3742 22:10:43.464234 LPDDR4 DRAM CONFIGURATION
3743 22:10:43.467241 ===================================
3744 22:10:43.467342 EX_ROW_EN[0] = 0x0
3745 22:10:43.470699 EX_ROW_EN[1] = 0x0
3746 22:10:43.470801 LP4Y_EN = 0x0
3747 22:10:43.473975 WORK_FSP = 0x0
3748 22:10:43.474078 WL = 0x2
3749 22:10:43.477607 RL = 0x2
3750 22:10:43.477710 BL = 0x2
3751 22:10:43.480976 RPST = 0x0
3752 22:10:43.481080 RD_PRE = 0x0
3753 22:10:43.484377 WR_PRE = 0x1
3754 22:10:43.484480 WR_PST = 0x0
3755 22:10:43.487795 DBI_WR = 0x0
3756 22:10:43.487899 DBI_RD = 0x0
3757 22:10:43.490822 OTF = 0x1
3758 22:10:43.494411 ===================================
3759 22:10:43.497628 ===================================
3760 22:10:43.497733 ANA top config
3761 22:10:43.501107 ===================================
3762 22:10:43.504185 DLL_ASYNC_EN = 0
3763 22:10:43.507748 ALL_SLAVE_EN = 1
3764 22:10:43.511151 NEW_RANK_MODE = 1
3765 22:10:43.511257 DLL_IDLE_MODE = 1
3766 22:10:43.514735 LP45_APHY_COMB_EN = 1
3767 22:10:43.517811 TX_ODT_DIS = 1
3768 22:10:43.520747 NEW_8X_MODE = 1
3769 22:10:43.524391 ===================================
3770 22:10:43.527660 ===================================
3771 22:10:43.531437 data_rate = 1200
3772 22:10:43.531550 CKR = 1
3773 22:10:43.534125 DQ_P2S_RATIO = 8
3774 22:10:43.537371 ===================================
3775 22:10:43.541003 CA_P2S_RATIO = 8
3776 22:10:43.544135 DQ_CA_OPEN = 0
3777 22:10:43.547651 DQ_SEMI_OPEN = 0
3778 22:10:43.551192 CA_SEMI_OPEN = 0
3779 22:10:43.551303 CA_FULL_RATE = 0
3780 22:10:43.554324 DQ_CKDIV4_EN = 1
3781 22:10:43.557857 CA_CKDIV4_EN = 1
3782 22:10:43.560799 CA_PREDIV_EN = 0
3783 22:10:43.564143 PH8_DLY = 0
3784 22:10:43.564256 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3785 22:10:43.567430 DQ_AAMCK_DIV = 4
3786 22:10:43.571169 CA_AAMCK_DIV = 4
3787 22:10:43.574510 CA_ADMCK_DIV = 4
3788 22:10:43.577891 DQ_TRACK_CA_EN = 0
3789 22:10:43.581254 CA_PICK = 600
3790 22:10:43.584186 CA_MCKIO = 600
3791 22:10:43.584290 MCKIO_SEMI = 0
3792 22:10:43.587868 PLL_FREQ = 2288
3793 22:10:43.591154 DQ_UI_PI_RATIO = 32
3794 22:10:43.594468 CA_UI_PI_RATIO = 0
3795 22:10:43.598107 ===================================
3796 22:10:43.601238 ===================================
3797 22:10:43.604768 memory_type:LPDDR4
3798 22:10:43.604880 GP_NUM : 10
3799 22:10:43.607691 SRAM_EN : 1
3800 22:10:43.607794 MD32_EN : 0
3801 22:10:43.611389 ===================================
3802 22:10:43.614778 [ANA_INIT] >>>>>>>>>>>>>>
3803 22:10:43.617770 <<<<<< [CONFIGURE PHASE]: ANA_TX
3804 22:10:43.621360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3805 22:10:43.624983 ===================================
3806 22:10:43.627939 data_rate = 1200,PCW = 0X5800
3807 22:10:43.631606 ===================================
3808 22:10:43.634609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3809 22:10:43.637835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3810 22:10:43.644598 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3811 22:10:43.647947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3812 22:10:43.651669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3813 22:10:43.655057 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3814 22:10:43.657943 [ANA_INIT] flow start
3815 22:10:43.661683 [ANA_INIT] PLL >>>>>>>>
3816 22:10:43.661787 [ANA_INIT] PLL <<<<<<<<
3817 22:10:43.664651 [ANA_INIT] MIDPI >>>>>>>>
3818 22:10:43.668206 [ANA_INIT] MIDPI <<<<<<<<
3819 22:10:43.671519 [ANA_INIT] DLL >>>>>>>>
3820 22:10:43.671618 [ANA_INIT] flow end
3821 22:10:43.674665 ============ LP4 DIFF to SE enter ============
3822 22:10:43.681427 ============ LP4 DIFF to SE exit ============
3823 22:10:43.681541 [ANA_INIT] <<<<<<<<<<<<<
3824 22:10:43.685335 [Flow] Enable top DCM control >>>>>
3825 22:10:43.688115 [Flow] Enable top DCM control <<<<<
3826 22:10:43.691895 Enable DLL master slave shuffle
3827 22:10:43.698062 ==============================================================
3828 22:10:43.698170 Gating Mode config
3829 22:10:43.705494 ==============================================================
3830 22:10:43.708557 Config description:
3831 22:10:43.715142 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3832 22:10:43.721538 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3833 22:10:43.728616 SELPH_MODE 0: By rank 1: By Phase
3834 22:10:43.735028 ==============================================================
3835 22:10:43.735139 GAT_TRACK_EN = 1
3836 22:10:43.738054 RX_GATING_MODE = 2
3837 22:10:43.741635 RX_GATING_TRACK_MODE = 2
3838 22:10:43.744763 SELPH_MODE = 1
3839 22:10:43.748346 PICG_EARLY_EN = 1
3840 22:10:43.751950 VALID_LAT_VALUE = 1
3841 22:10:43.758002 ==============================================================
3842 22:10:43.761651 Enter into Gating configuration >>>>
3843 22:10:43.765311 Exit from Gating configuration <<<<
3844 22:10:43.768245 Enter into DVFS_PRE_config >>>>>
3845 22:10:43.778456 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3846 22:10:43.781766 Exit from DVFS_PRE_config <<<<<
3847 22:10:43.785227 Enter into PICG configuration >>>>
3848 22:10:43.788856 Exit from PICG configuration <<<<
3849 22:10:43.788941 [RX_INPUT] configuration >>>>>
3850 22:10:43.792026 [RX_INPUT] configuration <<<<<
3851 22:10:43.798570 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3852 22:10:43.801686 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3853 22:10:43.808704 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3854 22:10:43.815133 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3855 22:10:43.821721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3856 22:10:43.828778 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3857 22:10:43.832133 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3858 22:10:43.835212 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3859 22:10:43.839047 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3860 22:10:43.845593 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3861 22:10:43.848482 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3862 22:10:43.851938 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3863 22:10:43.855409 ===================================
3864 22:10:43.859265 LPDDR4 DRAM CONFIGURATION
3865 22:10:43.861877 ===================================
3866 22:10:43.865314 EX_ROW_EN[0] = 0x0
3867 22:10:43.865395 EX_ROW_EN[1] = 0x0
3868 22:10:43.868646 LP4Y_EN = 0x0
3869 22:10:43.868735 WORK_FSP = 0x0
3870 22:10:43.872160 WL = 0x2
3871 22:10:43.872240 RL = 0x2
3872 22:10:43.875808 BL = 0x2
3873 22:10:43.875888 RPST = 0x0
3874 22:10:43.878926 RD_PRE = 0x0
3875 22:10:43.879006 WR_PRE = 0x1
3876 22:10:43.881933 WR_PST = 0x0
3877 22:10:43.882013 DBI_WR = 0x0
3878 22:10:43.885429 DBI_RD = 0x0
3879 22:10:43.885508 OTF = 0x1
3880 22:10:43.888840 ===================================
3881 22:10:43.891976 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3882 22:10:43.898698 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3883 22:10:43.902274 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3884 22:10:43.905464 ===================================
3885 22:10:43.909009 LPDDR4 DRAM CONFIGURATION
3886 22:10:43.912742 ===================================
3887 22:10:43.912823 EX_ROW_EN[0] = 0x10
3888 22:10:43.915436 EX_ROW_EN[1] = 0x0
3889 22:10:43.915515 LP4Y_EN = 0x0
3890 22:10:43.918770 WORK_FSP = 0x0
3891 22:10:43.918850 WL = 0x2
3892 22:10:43.922297 RL = 0x2
3893 22:10:43.925849 BL = 0x2
3894 22:10:43.925930 RPST = 0x0
3895 22:10:43.928869 RD_PRE = 0x0
3896 22:10:43.928949 WR_PRE = 0x1
3897 22:10:43.932221 WR_PST = 0x0
3898 22:10:43.932331 DBI_WR = 0x0
3899 22:10:43.935597 DBI_RD = 0x0
3900 22:10:43.935676 OTF = 0x1
3901 22:10:43.939158 ===================================
3902 22:10:43.945453 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3903 22:10:43.949774 nWR fixed to 30
3904 22:10:43.952628 [ModeRegInit_LP4] CH0 RK0
3905 22:10:43.952720 [ModeRegInit_LP4] CH0 RK1
3906 22:10:43.956089 [ModeRegInit_LP4] CH1 RK0
3907 22:10:43.959401 [ModeRegInit_LP4] CH1 RK1
3908 22:10:43.959481 match AC timing 17
3909 22:10:43.966178 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3910 22:10:43.969089 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3911 22:10:43.972353 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3912 22:10:43.979177 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3913 22:10:43.982819 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3914 22:10:43.982923 ==
3915 22:10:43.986052 Dram Type= 6, Freq= 0, CH_0, rank 0
3916 22:10:43.989488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3917 22:10:43.989568 ==
3918 22:10:43.995903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3919 22:10:44.002480 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3920 22:10:44.005741 [CA 0] Center 36 (6~66) winsize 61
3921 22:10:44.008970 [CA 1] Center 36 (6~66) winsize 61
3922 22:10:44.012521 [CA 2] Center 34 (4~65) winsize 62
3923 22:10:44.016088 [CA 3] Center 34 (4~65) winsize 62
3924 22:10:44.019247 [CA 4] Center 34 (4~64) winsize 61
3925 22:10:44.022606 [CA 5] Center 33 (3~64) winsize 62
3926 22:10:44.022709
3927 22:10:44.025612 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3928 22:10:44.025710
3929 22:10:44.029472 [CATrainingPosCal] consider 1 rank data
3930 22:10:44.032354 u2DelayCellTimex100 = 270/100 ps
3931 22:10:44.035719 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3932 22:10:44.039348 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3933 22:10:44.042888 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3934 22:10:44.045902 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3935 22:10:44.048957 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3936 22:10:44.052595 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3937 22:10:44.055780
3938 22:10:44.059175 CA PerBit enable=1, Macro0, CA PI delay=33
3939 22:10:44.059282
3940 22:10:44.062807 [CBTSetCACLKResult] CA Dly = 33
3941 22:10:44.062907 CS Dly: 5 (0~36)
3942 22:10:44.063007 ==
3943 22:10:44.065713 Dram Type= 6, Freq= 0, CH_0, rank 1
3944 22:10:44.069270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3945 22:10:44.069397 ==
3946 22:10:44.075675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3947 22:10:44.082713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3948 22:10:44.085630 [CA 0] Center 36 (6~66) winsize 61
3949 22:10:44.089361 [CA 1] Center 36 (6~66) winsize 61
3950 22:10:44.092347 [CA 2] Center 34 (4~65) winsize 62
3951 22:10:44.095972 [CA 3] Center 34 (4~65) winsize 62
3952 22:10:44.099384 [CA 4] Center 33 (3~64) winsize 62
3953 22:10:44.102846 [CA 5] Center 33 (3~64) winsize 62
3954 22:10:44.102977
3955 22:10:44.106118 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3956 22:10:44.106221
3957 22:10:44.109724 [CATrainingPosCal] consider 2 rank data
3958 22:10:44.112530 u2DelayCellTimex100 = 270/100 ps
3959 22:10:44.115861 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3960 22:10:44.119594 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3961 22:10:44.122688 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3962 22:10:44.126201 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3963 22:10:44.129231 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3964 22:10:44.133174 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3965 22:10:44.133284
3966 22:10:44.139746 CA PerBit enable=1, Macro0, CA PI delay=33
3967 22:10:44.139851
3968 22:10:44.139955 [CBTSetCACLKResult] CA Dly = 33
3969 22:10:44.143049 CS Dly: 4 (0~35)
3970 22:10:44.143152
3971 22:10:44.145874 ----->DramcWriteLeveling(PI) begin...
3972 22:10:44.145978 ==
3973 22:10:44.149648 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 22:10:44.153117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 22:10:44.153220 ==
3976 22:10:44.156198 Write leveling (Byte 0): 34 => 34
3977 22:10:44.159392 Write leveling (Byte 1): 29 => 29
3978 22:10:44.163057 DramcWriteLeveling(PI) end<-----
3979 22:10:44.163155
3980 22:10:44.163256 ==
3981 22:10:44.166124 Dram Type= 6, Freq= 0, CH_0, rank 0
3982 22:10:44.169593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 22:10:44.172634 ==
3984 22:10:44.172780 [Gating] SW mode calibration
3985 22:10:44.182772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3986 22:10:44.186213 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3987 22:10:44.189635 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 22:10:44.196347 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 22:10:44.199951 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 22:10:44.202875 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 22:10:44.209394 0 9 16 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (0 0)
3992 22:10:44.213130 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 22:10:44.216176 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 22:10:44.222747 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 22:10:44.225983 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 22:10:44.229378 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 22:10:44.233137 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 22:10:44.239631 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3999 22:10:44.242648 0 10 16 | B1->B0 | 3030 3b3b | 0 0 | (0 0) (0 0)
4000 22:10:44.246369 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 22:10:44.252826 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 22:10:44.256302 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 22:10:44.259389 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 22:10:44.266035 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 22:10:44.269721 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 22:10:44.272704 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 22:10:44.279916 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4008 22:10:44.282797 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 22:10:44.286676 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 22:10:44.292810 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 22:10:44.296167 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 22:10:44.299745 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 22:10:44.306698 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 22:10:44.309807 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:10:44.313293 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 22:10:44.316184 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 22:10:44.323550 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 22:10:44.326520 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 22:10:44.330031 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 22:10:44.336326 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 22:10:44.339540 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 22:10:44.343144 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4023 22:10:44.349580 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4024 22:10:44.349682 Total UI for P1: 0, mck2ui 16
4025 22:10:44.356312 best dqsien dly found for B0: ( 0, 13, 12)
4026 22:10:44.360206 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 22:10:44.363322 Total UI for P1: 0, mck2ui 16
4028 22:10:44.366430 best dqsien dly found for B1: ( 0, 13, 16)
4029 22:10:44.370020 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4030 22:10:44.372907 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4031 22:10:44.373007
4032 22:10:44.376543 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4033 22:10:44.379621 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4034 22:10:44.383257 [Gating] SW calibration Done
4035 22:10:44.383362 ==
4036 22:10:44.386323 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 22:10:44.390090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 22:10:44.393088 ==
4039 22:10:44.393187 RX Vref Scan: 0
4040 22:10:44.393276
4041 22:10:44.396370 RX Vref 0 -> 0, step: 1
4042 22:10:44.396484
4043 22:10:44.399919 RX Delay -230 -> 252, step: 16
4044 22:10:44.403233 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4045 22:10:44.406738 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4046 22:10:44.409737 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4047 22:10:44.413484 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4048 22:10:44.419615 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4049 22:10:44.422844 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4050 22:10:44.426407 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4051 22:10:44.429806 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4052 22:10:44.436362 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4053 22:10:44.439711 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4054 22:10:44.443140 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4055 22:10:44.446284 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4056 22:10:44.452934 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4057 22:10:44.456582 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4058 22:10:44.459477 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4059 22:10:44.462968 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4060 22:10:44.463072 ==
4061 22:10:44.466228 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 22:10:44.473034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 22:10:44.473141 ==
4064 22:10:44.473241 DQS Delay:
4065 22:10:44.473337 DQS0 = 0, DQS1 = 0
4066 22:10:44.476484 DQM Delay:
4067 22:10:44.476582 DQM0 = 40, DQM1 = 32
4068 22:10:44.479600 DQ Delay:
4069 22:10:44.483254 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4070 22:10:44.483363 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4071 22:10:44.486902 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4072 22:10:44.489848 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4073 22:10:44.493343
4074 22:10:44.493423
4075 22:10:44.493487 ==
4076 22:10:44.496882 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 22:10:44.499788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 22:10:44.499898 ==
4079 22:10:44.499991
4080 22:10:44.500080
4081 22:10:44.503255 TX Vref Scan disable
4082 22:10:44.503362 == TX Byte 0 ==
4083 22:10:44.510162 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4084 22:10:44.512874 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4085 22:10:44.512954 == TX Byte 1 ==
4086 22:10:44.519903 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4087 22:10:44.522932 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4088 22:10:44.523033 ==
4089 22:10:44.526599 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 22:10:44.529668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 22:10:44.529790 ==
4092 22:10:44.529889
4093 22:10:44.529983
4094 22:10:44.533025 TX Vref Scan disable
4095 22:10:44.536366 == TX Byte 0 ==
4096 22:10:44.539822 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4097 22:10:44.543373 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4098 22:10:44.546842 == TX Byte 1 ==
4099 22:10:44.549818 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4100 22:10:44.553513 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4101 22:10:44.553623
4102 22:10:44.556855 [DATLAT]
4103 22:10:44.556935 Freq=600, CH0 RK0
4104 22:10:44.556999
4105 22:10:44.559878 DATLAT Default: 0x9
4106 22:10:44.559962 0, 0xFFFF, sum = 0
4107 22:10:44.563591 1, 0xFFFF, sum = 0
4108 22:10:44.563673 2, 0xFFFF, sum = 0
4109 22:10:44.566499 3, 0xFFFF, sum = 0
4110 22:10:44.566580 4, 0xFFFF, sum = 0
4111 22:10:44.569790 5, 0xFFFF, sum = 0
4112 22:10:44.569872 6, 0xFFFF, sum = 0
4113 22:10:44.573535 7, 0xFFFF, sum = 0
4114 22:10:44.573627 8, 0x0, sum = 1
4115 22:10:44.576856 9, 0x0, sum = 2
4116 22:10:44.576938 10, 0x0, sum = 3
4117 22:10:44.579657 11, 0x0, sum = 4
4118 22:10:44.579738 best_step = 9
4119 22:10:44.579801
4120 22:10:44.579860 ==
4121 22:10:44.583085 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 22:10:44.589663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 22:10:44.589745 ==
4124 22:10:44.589809 RX Vref Scan: 1
4125 22:10:44.589869
4126 22:10:44.593290 RX Vref 0 -> 0, step: 1
4127 22:10:44.593371
4128 22:10:44.596343 RX Delay -195 -> 252, step: 8
4129 22:10:44.596467
4130 22:10:44.599853 Set Vref, RX VrefLevel [Byte0]: 53
4131 22:10:44.603185 [Byte1]: 50
4132 22:10:44.603301
4133 22:10:44.606585 Final RX Vref Byte 0 = 53 to rank0
4134 22:10:44.609985 Final RX Vref Byte 1 = 50 to rank0
4135 22:10:44.613006 Final RX Vref Byte 0 = 53 to rank1
4136 22:10:44.616356 Final RX Vref Byte 1 = 50 to rank1==
4137 22:10:44.619816 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 22:10:44.622870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 22:10:44.622951 ==
4140 22:10:44.626416 DQS Delay:
4141 22:10:44.626513 DQS0 = 0, DQS1 = 0
4142 22:10:44.626577 DQM Delay:
4143 22:10:44.630126 DQM0 = 43, DQM1 = 34
4144 22:10:44.630205 DQ Delay:
4145 22:10:44.633121 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4146 22:10:44.636821 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4147 22:10:44.639785 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4148 22:10:44.643109 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4149 22:10:44.643191
4150 22:10:44.643255
4151 22:10:44.652806 [DQSOSCAuto] RK0, (LSB)MR18= 0x4422, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4152 22:10:44.652921 CH0 RK0: MR19=808, MR18=4422
4153 22:10:44.659688 CH0_RK0: MR19=0x808, MR18=0x4422, DQSOSC=396, MR23=63, INC=167, DEC=111
4154 22:10:44.659794
4155 22:10:44.662953 ----->DramcWriteLeveling(PI) begin...
4156 22:10:44.663058 ==
4157 22:10:44.666393 Dram Type= 6, Freq= 0, CH_0, rank 1
4158 22:10:44.673014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 22:10:44.673118 ==
4160 22:10:44.676519 Write leveling (Byte 0): 32 => 32
4161 22:10:44.680004 Write leveling (Byte 1): 29 => 29
4162 22:10:44.680111 DramcWriteLeveling(PI) end<-----
4163 22:10:44.680215
4164 22:10:44.683090 ==
4165 22:10:44.686626 Dram Type= 6, Freq= 0, CH_0, rank 1
4166 22:10:44.689625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 22:10:44.689714 ==
4168 22:10:44.693289 [Gating] SW mode calibration
4169 22:10:44.699945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4170 22:10:44.703338 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4171 22:10:44.709766 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 22:10:44.713178 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 22:10:44.716620 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 22:10:44.722951 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)
4175 22:10:44.726440 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4176 22:10:44.729944 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 22:10:44.736660 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 22:10:44.740058 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 22:10:44.743160 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 22:10:44.746715 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 22:10:44.753308 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 22:10:44.756600 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
4183 22:10:44.760354 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4184 22:10:44.766635 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 22:10:44.769801 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 22:10:44.773297 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 22:10:44.780188 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 22:10:44.783676 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 22:10:44.786607 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 22:10:44.793171 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 22:10:44.796578 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4192 22:10:44.800109 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 22:10:44.806728 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 22:10:44.809712 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 22:10:44.813197 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 22:10:44.820229 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 22:10:44.823615 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 22:10:44.826584 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 22:10:44.830439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 22:10:44.836584 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 22:10:44.840054 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 22:10:44.843109 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 22:10:44.849935 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 22:10:44.853466 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 22:10:44.856937 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 22:10:44.863258 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4207 22:10:44.866762 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 22:10:44.870385 Total UI for P1: 0, mck2ui 16
4209 22:10:44.873790 best dqsien dly found for B0: ( 0, 13, 12)
4210 22:10:44.877076 Total UI for P1: 0, mck2ui 16
4211 22:10:44.880100 best dqsien dly found for B1: ( 0, 13, 14)
4212 22:10:44.883407 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4213 22:10:44.886910 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4214 22:10:44.886989
4215 22:10:44.889981 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4216 22:10:44.893480 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4217 22:10:44.897143 [Gating] SW calibration Done
4218 22:10:44.897247 ==
4219 22:10:44.900074 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 22:10:44.903512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 22:10:44.906789 ==
4222 22:10:44.906893 RX Vref Scan: 0
4223 22:10:44.906994
4224 22:10:44.910197 RX Vref 0 -> 0, step: 1
4225 22:10:44.910299
4226 22:10:44.913318 RX Delay -230 -> 252, step: 16
4227 22:10:44.916891 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4228 22:10:44.919932 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4229 22:10:44.923280 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4230 22:10:44.930087 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4231 22:10:44.933407 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4232 22:10:44.936772 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4233 22:10:44.940195 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4234 22:10:44.943180 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4235 22:10:44.950266 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4236 22:10:44.953417 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4237 22:10:44.957126 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4238 22:10:44.960087 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4239 22:10:44.963658 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4240 22:10:44.969901 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4241 22:10:44.973830 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4242 22:10:44.977011 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4243 22:10:44.977115 ==
4244 22:10:44.979897 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 22:10:44.983343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 22:10:44.986850 ==
4247 22:10:44.986955 DQS Delay:
4248 22:10:44.987039 DQS0 = 0, DQS1 = 0
4249 22:10:44.990452 DQM Delay:
4250 22:10:44.990554 DQM0 = 40, DQM1 = 32
4251 22:10:44.993477 DQ Delay:
4252 22:10:44.993577 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4253 22:10:44.996748 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4254 22:10:45.000357 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4255 22:10:45.003359 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4256 22:10:45.003468
4257 22:10:45.006877
4258 22:10:45.006977 ==
4259 22:10:45.010443 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 22:10:45.013663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 22:10:45.013764 ==
4262 22:10:45.013856
4263 22:10:45.013946
4264 22:10:45.016938 TX Vref Scan disable
4265 22:10:45.017038 == TX Byte 0 ==
4266 22:10:45.023488 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4267 22:10:45.027235 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4268 22:10:45.027333 == TX Byte 1 ==
4269 22:10:45.033712 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4270 22:10:45.036546 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4271 22:10:45.036670 ==
4272 22:10:45.040301 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 22:10:45.043670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 22:10:45.043788 ==
4275 22:10:45.043942
4276 22:10:45.044033
4277 22:10:45.047265 TX Vref Scan disable
4278 22:10:45.050002 == TX Byte 0 ==
4279 22:10:45.053658 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4280 22:10:45.056620 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4281 22:10:45.060452 == TX Byte 1 ==
4282 22:10:45.063551 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4283 22:10:45.066999 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4284 22:10:45.067108
4285 22:10:45.070174 [DATLAT]
4286 22:10:45.070276 Freq=600, CH0 RK1
4287 22:10:45.070403
4288 22:10:45.073714 DATLAT Default: 0x9
4289 22:10:45.073816 0, 0xFFFF, sum = 0
4290 22:10:45.076986 1, 0xFFFF, sum = 0
4291 22:10:45.077090 2, 0xFFFF, sum = 0
4292 22:10:45.080243 3, 0xFFFF, sum = 0
4293 22:10:45.080346 4, 0xFFFF, sum = 0
4294 22:10:45.083880 5, 0xFFFF, sum = 0
4295 22:10:45.083982 6, 0xFFFF, sum = 0
4296 22:10:45.086776 7, 0xFFFF, sum = 0
4297 22:10:45.086883 8, 0x0, sum = 1
4298 22:10:45.090556 9, 0x0, sum = 2
4299 22:10:45.090660 10, 0x0, sum = 3
4300 22:10:45.093563 11, 0x0, sum = 4
4301 22:10:45.093644 best_step = 9
4302 22:10:45.093712
4303 22:10:45.093773 ==
4304 22:10:45.097333 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 22:10:45.100174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 22:10:45.100280 ==
4307 22:10:45.103759 RX Vref Scan: 0
4308 22:10:45.103864
4309 22:10:45.107327 RX Vref 0 -> 0, step: 1
4310 22:10:45.107426
4311 22:10:45.107526 RX Delay -195 -> 252, step: 8
4312 22:10:45.115506 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4313 22:10:45.118404 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4314 22:10:45.122310 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4315 22:10:45.125319 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4316 22:10:45.132084 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4317 22:10:45.135190 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4318 22:10:45.138790 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4319 22:10:45.141852 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4320 22:10:45.145049 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4321 22:10:45.151974 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4322 22:10:45.154758 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4323 22:10:45.158181 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4324 22:10:45.161703 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4325 22:10:45.168269 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4326 22:10:45.171884 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4327 22:10:45.174851 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4328 22:10:45.174931 ==
4329 22:10:45.178500 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 22:10:45.182107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 22:10:45.184847 ==
4332 22:10:45.184938 DQS Delay:
4333 22:10:45.185002 DQS0 = 0, DQS1 = 0
4334 22:10:45.188188 DQM Delay:
4335 22:10:45.188293 DQM0 = 39, DQM1 = 33
4336 22:10:45.191615 DQ Delay:
4337 22:10:45.194575 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4338 22:10:45.194649 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4339 22:10:45.198189 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4340 22:10:45.202047 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4341 22:10:45.204982
4342 22:10:45.205059
4343 22:10:45.211637 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4344 22:10:45.214837 CH0 RK1: MR19=808, MR18=4E2F
4345 22:10:45.221793 CH0_RK1: MR19=0x808, MR18=0x4E2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4346 22:10:45.224900 [RxdqsGatingPostProcess] freq 600
4347 22:10:45.228161 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4348 22:10:45.231551 Pre-setting of DQS Precalculation
4349 22:10:45.238360 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4350 22:10:45.238440 ==
4351 22:10:45.242187 Dram Type= 6, Freq= 0, CH_1, rank 0
4352 22:10:45.245004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 22:10:45.245085 ==
4354 22:10:45.248658 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4355 22:10:45.254893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4356 22:10:45.258602 [CA 0] Center 35 (5~66) winsize 62
4357 22:10:45.262350 [CA 1] Center 35 (5~65) winsize 61
4358 22:10:45.265739 [CA 2] Center 34 (4~65) winsize 62
4359 22:10:45.269042 [CA 3] Center 33 (3~64) winsize 62
4360 22:10:45.272488 [CA 4] Center 34 (3~65) winsize 63
4361 22:10:45.275608 [CA 5] Center 33 (2~64) winsize 63
4362 22:10:45.275713
4363 22:10:45.279294 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4364 22:10:45.279391
4365 22:10:45.282379 [CATrainingPosCal] consider 1 rank data
4366 22:10:45.286139 u2DelayCellTimex100 = 270/100 ps
4367 22:10:45.289204 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4368 22:10:45.292564 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4369 22:10:45.295806 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4370 22:10:45.302299 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4371 22:10:45.306058 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4372 22:10:45.309136 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4373 22:10:45.309215
4374 22:10:45.312398 CA PerBit enable=1, Macro0, CA PI delay=33
4375 22:10:45.312476
4376 22:10:45.315869 [CBTSetCACLKResult] CA Dly = 33
4377 22:10:45.315950 CS Dly: 5 (0~36)
4378 22:10:45.316017 ==
4379 22:10:45.318940 Dram Type= 6, Freq= 0, CH_1, rank 1
4380 22:10:45.325969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 22:10:45.326046 ==
4382 22:10:45.329096 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4383 22:10:45.335749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4384 22:10:45.339090 [CA 0] Center 35 (5~66) winsize 62
4385 22:10:45.342306 [CA 1] Center 36 (6~66) winsize 61
4386 22:10:45.345784 [CA 2] Center 34 (4~65) winsize 62
4387 22:10:45.349461 [CA 3] Center 33 (3~64) winsize 62
4388 22:10:45.352461 [CA 4] Center 34 (4~65) winsize 62
4389 22:10:45.356141 [CA 5] Center 33 (3~64) winsize 62
4390 22:10:45.356224
4391 22:10:45.359288 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4392 22:10:45.359371
4393 22:10:45.362781 [CATrainingPosCal] consider 2 rank data
4394 22:10:45.366245 u2DelayCellTimex100 = 270/100 ps
4395 22:10:45.369646 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4396 22:10:45.372353 CA1 delay=35 (6~65),Diff = 2 PI (19 cell)
4397 22:10:45.376336 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 22:10:45.382503 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 22:10:45.386163 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 22:10:45.389197 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4401 22:10:45.389282
4402 22:10:45.392805 CA PerBit enable=1, Macro0, CA PI delay=33
4403 22:10:45.392889
4404 22:10:45.395842 [CBTSetCACLKResult] CA Dly = 33
4405 22:10:45.395925 CS Dly: 5 (0~36)
4406 22:10:45.396010
4407 22:10:45.399443 ----->DramcWriteLeveling(PI) begin...
4408 22:10:45.399529 ==
4409 22:10:45.402731 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 22:10:45.409839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 22:10:45.409929 ==
4412 22:10:45.412618 Write leveling (Byte 0): 32 => 32
4413 22:10:45.415721 Write leveling (Byte 1): 32 => 32
4414 22:10:45.415804 DramcWriteLeveling(PI) end<-----
4415 22:10:45.415919
4416 22:10:45.419053 ==
4417 22:10:45.422455 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 22:10:45.426140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 22:10:45.426224 ==
4420 22:10:45.429178 [Gating] SW mode calibration
4421 22:10:45.436094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4422 22:10:45.439479 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4423 22:10:45.446131 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 22:10:45.449347 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4425 22:10:45.452524 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4426 22:10:45.459285 0 9 12 | B1->B0 | 3434 3232 | 0 1 | (0 1) (1 0)
4427 22:10:45.462899 0 9 16 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (1 1)
4428 22:10:45.466207 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 22:10:45.472578 0 9 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
4430 22:10:45.475893 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 22:10:45.479167 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 22:10:45.482777 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 22:10:45.489578 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 22:10:45.492610 0 10 12 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
4435 22:10:45.496288 0 10 16 | B1->B0 | 4343 4444 | 1 0 | (0 0) (0 0)
4436 22:10:45.502988 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 22:10:45.506097 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 22:10:45.509515 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 22:10:45.516091 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 22:10:45.519937 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 22:10:45.522942 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 22:10:45.529755 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 22:10:45.533368 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4444 22:10:45.536464 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 22:10:45.543147 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 22:10:45.546542 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 22:10:45.549470 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 22:10:45.556243 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 22:10:45.559670 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 22:10:45.563274 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:10:45.566178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 22:10:45.572995 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 22:10:45.576433 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 22:10:45.579869 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 22:10:45.586432 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 22:10:45.589596 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 22:10:45.592856 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 22:10:45.599720 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4459 22:10:45.603239 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4460 22:10:45.606285 Total UI for P1: 0, mck2ui 16
4461 22:10:45.609843 best dqsien dly found for B1: ( 0, 13, 14)
4462 22:10:45.612931 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 22:10:45.616254 Total UI for P1: 0, mck2ui 16
4464 22:10:45.619610 best dqsien dly found for B0: ( 0, 13, 14)
4465 22:10:45.623348 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4466 22:10:45.626452 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4467 22:10:45.626537
4468 22:10:45.633284 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4469 22:10:45.636634 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4470 22:10:45.636746 [Gating] SW calibration Done
4471 22:10:45.639689 ==
4472 22:10:45.642769 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 22:10:45.646319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 22:10:45.646404 ==
4475 22:10:45.646489 RX Vref Scan: 0
4476 22:10:45.646570
4477 22:10:45.649784 RX Vref 0 -> 0, step: 1
4478 22:10:45.649881
4479 22:10:45.652826 RX Delay -230 -> 252, step: 16
4480 22:10:45.656392 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4481 22:10:45.659844 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4482 22:10:45.666107 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4483 22:10:45.669971 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4484 22:10:45.672888 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4485 22:10:45.676812 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4486 22:10:45.680036 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4487 22:10:45.686366 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4488 22:10:45.689663 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4489 22:10:45.693185 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4490 22:10:45.696529 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4491 22:10:45.702825 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4492 22:10:45.706573 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4493 22:10:45.709688 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4494 22:10:45.713202 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4495 22:10:45.716247 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4496 22:10:45.719937 ==
4497 22:10:45.722965 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 22:10:45.726261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 22:10:45.726366 ==
4500 22:10:45.726470 DQS Delay:
4501 22:10:45.729587 DQS0 = 0, DQS1 = 0
4502 22:10:45.729667 DQM Delay:
4503 22:10:45.733386 DQM0 = 44, DQM1 = 35
4504 22:10:45.733490 DQ Delay:
4505 22:10:45.736843 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4506 22:10:45.740048 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4507 22:10:45.742987 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4508 22:10:45.746652 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4509 22:10:45.746736
4510 22:10:45.746821
4511 22:10:45.746917 ==
4512 22:10:45.749636 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 22:10:45.753111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 22:10:45.753201 ==
4515 22:10:45.753265
4516 22:10:45.753324
4517 22:10:45.756189 TX Vref Scan disable
4518 22:10:45.759646 == TX Byte 0 ==
4519 22:10:45.763093 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4520 22:10:45.766713 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4521 22:10:45.769704 == TX Byte 1 ==
4522 22:10:45.773361 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4523 22:10:45.776530 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4524 22:10:45.776611 ==
4525 22:10:45.779994 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 22:10:45.783377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 22:10:45.786243 ==
4528 22:10:45.786323
4529 22:10:45.786386
4530 22:10:45.786444 TX Vref Scan disable
4531 22:10:45.790510 == TX Byte 0 ==
4532 22:10:45.793906 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4533 22:10:45.796878 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4534 22:10:45.800225 == TX Byte 1 ==
4535 22:10:45.803616 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4536 22:10:45.807065 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4537 22:10:45.810309
4538 22:10:45.810404 [DATLAT]
4539 22:10:45.810484 Freq=600, CH1 RK0
4540 22:10:45.810559
4541 22:10:45.813756 DATLAT Default: 0x9
4542 22:10:45.813836 0, 0xFFFF, sum = 0
4543 22:10:45.816829 1, 0xFFFF, sum = 0
4544 22:10:45.816912 2, 0xFFFF, sum = 0
4545 22:10:45.820603 3, 0xFFFF, sum = 0
4546 22:10:45.820741 4, 0xFFFF, sum = 0
4547 22:10:45.823606 5, 0xFFFF, sum = 0
4548 22:10:45.823688 6, 0xFFFF, sum = 0
4549 22:10:45.827162 7, 0xFFFF, sum = 0
4550 22:10:45.827244 8, 0x0, sum = 1
4551 22:10:45.830795 9, 0x0, sum = 2
4552 22:10:45.830876 10, 0x0, sum = 3
4553 22:10:45.833744 11, 0x0, sum = 4
4554 22:10:45.833826 best_step = 9
4555 22:10:45.833889
4556 22:10:45.833947 ==
4557 22:10:45.837053 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 22:10:45.840840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 22:10:45.844021 ==
4560 22:10:45.844101 RX Vref Scan: 1
4561 22:10:45.844165
4562 22:10:45.847222 RX Vref 0 -> 0, step: 1
4563 22:10:45.847304
4564 22:10:45.851035 RX Delay -195 -> 252, step: 8
4565 22:10:45.851115
4566 22:10:45.851179 Set Vref, RX VrefLevel [Byte0]: 57
4567 22:10:45.853927 [Byte1]: 50
4568 22:10:45.859313
4569 22:10:45.859393 Final RX Vref Byte 0 = 57 to rank0
4570 22:10:45.862285 Final RX Vref Byte 1 = 50 to rank0
4571 22:10:45.865774 Final RX Vref Byte 0 = 57 to rank1
4572 22:10:45.869387 Final RX Vref Byte 1 = 50 to rank1==
4573 22:10:45.872462 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 22:10:45.879015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 22:10:45.879097 ==
4576 22:10:45.879161 DQS Delay:
4577 22:10:45.879220 DQS0 = 0, DQS1 = 0
4578 22:10:45.882569 DQM Delay:
4579 22:10:45.882648 DQM0 = 41, DQM1 = 33
4580 22:10:45.885797 DQ Delay:
4581 22:10:45.889056 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4582 22:10:45.889164 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4583 22:10:45.892435 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4584 22:10:45.896154 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4585 22:10:45.899064
4586 22:10:45.899144
4587 22:10:45.906093 [DQSOSCAuto] RK0, (LSB)MR18= 0x490e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4588 22:10:45.909473 CH1 RK0: MR19=808, MR18=490E
4589 22:10:45.915635 CH1_RK0: MR19=0x808, MR18=0x490E, DQSOSC=396, MR23=63, INC=167, DEC=111
4590 22:10:45.915716
4591 22:10:45.919241 ----->DramcWriteLeveling(PI) begin...
4592 22:10:45.919323 ==
4593 22:10:45.922822 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 22:10:45.925893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 22:10:45.925975 ==
4596 22:10:45.928900 Write leveling (Byte 0): 32 => 32
4597 22:10:45.932556 Write leveling (Byte 1): 29 => 29
4598 22:10:45.935528 DramcWriteLeveling(PI) end<-----
4599 22:10:45.935629
4600 22:10:45.935750 ==
4601 22:10:45.939114 Dram Type= 6, Freq= 0, CH_1, rank 1
4602 22:10:45.942682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 22:10:45.942758 ==
4604 22:10:45.945614 [Gating] SW mode calibration
4605 22:10:45.952659 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4606 22:10:45.959220 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4607 22:10:45.962783 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4608 22:10:45.965893 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4609 22:10:45.972325 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 22:10:45.975747 0 9 12 | B1->B0 | 3030 2929 | 1 0 | (0 0) (1 1)
4611 22:10:45.979447 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4612 22:10:45.986104 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4613 22:10:45.989036 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 22:10:45.992486 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4615 22:10:45.999330 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 22:10:46.002575 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 22:10:46.006017 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 22:10:46.012451 0 10 12 | B1->B0 | 3030 3939 | 1 0 | (0 0) (1 1)
4619 22:10:46.015864 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
4620 22:10:46.019380 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 22:10:46.022415 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 22:10:46.029009 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 22:10:46.032584 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 22:10:46.035926 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 22:10:46.042447 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 22:10:46.045963 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4627 22:10:46.049093 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 22:10:46.055707 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 22:10:46.059077 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 22:10:46.062958 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 22:10:46.069046 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 22:10:46.073160 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 22:10:46.075952 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 22:10:46.082731 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 22:10:46.085730 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 22:10:46.089412 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 22:10:46.096054 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 22:10:46.099147 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 22:10:46.102760 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 22:10:46.106165 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 22:10:46.112919 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 22:10:46.115964 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4643 22:10:46.119374 Total UI for P1: 0, mck2ui 16
4644 22:10:46.122756 best dqsien dly found for B0: ( 0, 13, 10)
4645 22:10:46.126123 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4646 22:10:46.132733 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 22:10:46.132810 Total UI for P1: 0, mck2ui 16
4648 22:10:46.139668 best dqsien dly found for B1: ( 0, 13, 14)
4649 22:10:46.142639 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4650 22:10:46.145836 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4651 22:10:46.145911
4652 22:10:46.149741 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4653 22:10:46.152720 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4654 22:10:46.155621 [Gating] SW calibration Done
4655 22:10:46.155696 ==
4656 22:10:46.159286 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 22:10:46.162501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 22:10:46.162591 ==
4659 22:10:46.165871 RX Vref Scan: 0
4660 22:10:46.165944
4661 22:10:46.166006 RX Vref 0 -> 0, step: 1
4662 22:10:46.169574
4663 22:10:46.169647 RX Delay -230 -> 252, step: 16
4664 22:10:46.175734 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4665 22:10:46.179182 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4666 22:10:46.182337 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4667 22:10:46.185471 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4668 22:10:46.192658 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4669 22:10:46.195786 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4670 22:10:46.199540 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4671 22:10:46.202372 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4672 22:10:46.205842 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4673 22:10:46.212388 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4674 22:10:46.216015 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4675 22:10:46.219145 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4676 22:10:46.222205 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4677 22:10:46.229117 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4678 22:10:46.232489 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4679 22:10:46.235629 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4680 22:10:46.235711 ==
4681 22:10:46.239165 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 22:10:46.242861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 22:10:46.242944 ==
4684 22:10:46.245616 DQS Delay:
4685 22:10:46.245698 DQS0 = 0, DQS1 = 0
4686 22:10:46.249586 DQM Delay:
4687 22:10:46.249668 DQM0 = 40, DQM1 = 34
4688 22:10:46.249751 DQ Delay:
4689 22:10:46.252584 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4690 22:10:46.255843 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4691 22:10:46.259737 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4692 22:10:46.262701 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4693 22:10:46.262784
4694 22:10:46.262867
4695 22:10:46.262946 ==
4696 22:10:46.265905 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 22:10:46.272273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 22:10:46.272355 ==
4699 22:10:46.272438
4700 22:10:46.272535
4701 22:10:46.272630 TX Vref Scan disable
4702 22:10:46.276597 == TX Byte 0 ==
4703 22:10:46.280045 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4704 22:10:46.283121 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4705 22:10:46.286420 == TX Byte 1 ==
4706 22:10:46.289635 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4707 22:10:46.293085 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4708 22:10:46.297024 ==
4709 22:10:46.299968 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 22:10:46.303046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 22:10:46.303122 ==
4712 22:10:46.303184
4713 22:10:46.303251
4714 22:10:46.306563 TX Vref Scan disable
4715 22:10:46.306648 == TX Byte 0 ==
4716 22:10:46.312965 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4717 22:10:46.316563 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4718 22:10:46.316637 == TX Byte 1 ==
4719 22:10:46.323414 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4720 22:10:46.326355 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4721 22:10:46.326430
4722 22:10:46.326501 [DATLAT]
4723 22:10:46.330093 Freq=600, CH1 RK1
4724 22:10:46.330174
4725 22:10:46.330236 DATLAT Default: 0x9
4726 22:10:46.333286 0, 0xFFFF, sum = 0
4727 22:10:46.333359 1, 0xFFFF, sum = 0
4728 22:10:46.336810 2, 0xFFFF, sum = 0
4729 22:10:46.336885 3, 0xFFFF, sum = 0
4730 22:10:46.339866 4, 0xFFFF, sum = 0
4731 22:10:46.339940 5, 0xFFFF, sum = 0
4732 22:10:46.343403 6, 0xFFFF, sum = 0
4733 22:10:46.343479 7, 0xFFFF, sum = 0
4734 22:10:46.346960 8, 0x0, sum = 1
4735 22:10:46.347029 9, 0x0, sum = 2
4736 22:10:46.350023 10, 0x0, sum = 3
4737 22:10:46.350098 11, 0x0, sum = 4
4738 22:10:46.353693 best_step = 9
4739 22:10:46.353774
4740 22:10:46.353835 ==
4741 22:10:46.356551 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 22:10:46.360147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 22:10:46.360222 ==
4744 22:10:46.363400 RX Vref Scan: 0
4745 22:10:46.363476
4746 22:10:46.363539 RX Vref 0 -> 0, step: 1
4747 22:10:46.363605
4748 22:10:46.366494 RX Delay -195 -> 252, step: 8
4749 22:10:46.373854 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4750 22:10:46.377174 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4751 22:10:46.380142 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4752 22:10:46.383589 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4753 22:10:46.390311 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4754 22:10:46.393839 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4755 22:10:46.397142 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4756 22:10:46.400579 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4757 22:10:46.403691 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4758 22:10:46.410244 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4759 22:10:46.413849 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4760 22:10:46.417180 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4761 22:10:46.420663 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4762 22:10:46.427315 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4763 22:10:46.430550 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4764 22:10:46.434034 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4765 22:10:46.434133 ==
4766 22:10:46.437066 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 22:10:46.440872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 22:10:46.440962 ==
4769 22:10:46.443708 DQS Delay:
4770 22:10:46.443837 DQS0 = 0, DQS1 = 0
4771 22:10:46.447146 DQM Delay:
4772 22:10:46.447240 DQM0 = 38, DQM1 = 33
4773 22:10:46.447304 DQ Delay:
4774 22:10:46.450506 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4775 22:10:46.453596 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4776 22:10:46.457311 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4777 22:10:46.460869 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4778 22:10:46.460975
4779 22:10:46.461067
4780 22:10:46.470354 [DQSOSCAuto] RK1, (LSB)MR18= 0x3948, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4781 22:10:46.473694 CH1 RK1: MR19=808, MR18=3948
4782 22:10:46.480442 CH1_RK1: MR19=0x808, MR18=0x3948, DQSOSC=396, MR23=63, INC=167, DEC=111
4783 22:10:46.480573 [RxdqsGatingPostProcess] freq 600
4784 22:10:46.486920 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4785 22:10:46.490298 Pre-setting of DQS Precalculation
4786 22:10:46.493701 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4787 22:10:46.503832 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4788 22:10:46.510113 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4789 22:10:46.510278
4790 22:10:46.510378
4791 22:10:46.513491 [Calibration Summary] 1200 Mbps
4792 22:10:46.513581 CH 0, Rank 0
4793 22:10:46.517341 SW Impedance : PASS
4794 22:10:46.517433 DUTY Scan : NO K
4795 22:10:46.520197 ZQ Calibration : PASS
4796 22:10:46.523749 Jitter Meter : NO K
4797 22:10:46.523840 CBT Training : PASS
4798 22:10:46.527300 Write leveling : PASS
4799 22:10:46.530262 RX DQS gating : PASS
4800 22:10:46.530379 RX DQ/DQS(RDDQC) : PASS
4801 22:10:46.533744 TX DQ/DQS : PASS
4802 22:10:46.536852 RX DATLAT : PASS
4803 22:10:46.536931 RX DQ/DQS(Engine): PASS
4804 22:10:46.540566 TX OE : NO K
4805 22:10:46.540641 All Pass.
4806 22:10:46.540732
4807 22:10:46.540810 CH 0, Rank 1
4808 22:10:46.543396 SW Impedance : PASS
4809 22:10:46.547172 DUTY Scan : NO K
4810 22:10:46.547260 ZQ Calibration : PASS
4811 22:10:46.550117 Jitter Meter : NO K
4812 22:10:46.553623 CBT Training : PASS
4813 22:10:46.553762 Write leveling : PASS
4814 22:10:46.556755 RX DQS gating : PASS
4815 22:10:46.560510 RX DQ/DQS(RDDQC) : PASS
4816 22:10:46.560625 TX DQ/DQS : PASS
4817 22:10:46.563573 RX DATLAT : PASS
4818 22:10:46.567284 RX DQ/DQS(Engine): PASS
4819 22:10:46.567397 TX OE : NO K
4820 22:10:46.570304 All Pass.
4821 22:10:46.570379
4822 22:10:46.570442 CH 1, Rank 0
4823 22:10:46.573951 SW Impedance : PASS
4824 22:10:46.574033 DUTY Scan : NO K
4825 22:10:46.576955 ZQ Calibration : PASS
4826 22:10:46.580558 Jitter Meter : NO K
4827 22:10:46.580677 CBT Training : PASS
4828 22:10:46.583452 Write leveling : PASS
4829 22:10:46.583535 RX DQS gating : PASS
4830 22:10:46.586947 RX DQ/DQS(RDDQC) : PASS
4831 22:10:46.590467 TX DQ/DQS : PASS
4832 22:10:46.590551 RX DATLAT : PASS
4833 22:10:46.594155 RX DQ/DQS(Engine): PASS
4834 22:10:46.597470 TX OE : NO K
4835 22:10:46.597553 All Pass.
4836 22:10:46.597619
4837 22:10:46.597681 CH 1, Rank 1
4838 22:10:46.600659 SW Impedance : PASS
4839 22:10:46.603572 DUTY Scan : NO K
4840 22:10:46.603655 ZQ Calibration : PASS
4841 22:10:46.607136 Jitter Meter : NO K
4842 22:10:46.610585 CBT Training : PASS
4843 22:10:46.610671 Write leveling : PASS
4844 22:10:46.613784 RX DQS gating : PASS
4845 22:10:46.617630 RX DQ/DQS(RDDQC) : PASS
4846 22:10:46.617712 TX DQ/DQS : PASS
4847 22:10:46.620544 RX DATLAT : PASS
4848 22:10:46.620657 RX DQ/DQS(Engine): PASS
4849 22:10:46.624057 TX OE : NO K
4850 22:10:46.624169 All Pass.
4851 22:10:46.624263
4852 22:10:46.627140 DramC Write-DBI off
4853 22:10:46.630596 PER_BANK_REFRESH: Hybrid Mode
4854 22:10:46.630679 TX_TRACKING: ON
4855 22:10:46.640619 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4856 22:10:46.644178 [FAST_K] Save calibration result to emmc
4857 22:10:46.647225 dramc_set_vcore_voltage set vcore to 662500
4858 22:10:46.650927 Read voltage for 933, 3
4859 22:10:46.651009 Vio18 = 0
4860 22:10:46.651074 Vcore = 662500
4861 22:10:46.653920 Vdram = 0
4862 22:10:46.654002 Vddq = 0
4863 22:10:46.654066 Vmddr = 0
4864 22:10:46.660560 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4865 22:10:46.664298 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4866 22:10:46.667385 MEM_TYPE=3, freq_sel=17
4867 22:10:46.670998 sv_algorithm_assistance_LP4_1600
4868 22:10:46.674180 ============ PULL DRAM RESETB DOWN ============
4869 22:10:46.677659 ========== PULL DRAM RESETB DOWN end =========
4870 22:10:46.684189 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4871 22:10:46.687754 ===================================
4872 22:10:46.687839 LPDDR4 DRAM CONFIGURATION
4873 22:10:46.690687 ===================================
4874 22:10:46.694280 EX_ROW_EN[0] = 0x0
4875 22:10:46.697885 EX_ROW_EN[1] = 0x0
4876 22:10:46.697970 LP4Y_EN = 0x0
4877 22:10:46.700811 WORK_FSP = 0x0
4878 22:10:46.700894 WL = 0x3
4879 22:10:46.704224 RL = 0x3
4880 22:10:46.704309 BL = 0x2
4881 22:10:46.707772 RPST = 0x0
4882 22:10:46.707855 RD_PRE = 0x0
4883 22:10:46.711086 WR_PRE = 0x1
4884 22:10:46.711169 WR_PST = 0x0
4885 22:10:46.714085 DBI_WR = 0x0
4886 22:10:46.714166 DBI_RD = 0x0
4887 22:10:46.717526 OTF = 0x1
4888 22:10:46.721061 ===================================
4889 22:10:46.724739 ===================================
4890 22:10:46.724820 ANA top config
4891 22:10:46.727792 ===================================
4892 22:10:46.731239 DLL_ASYNC_EN = 0
4893 22:10:46.734739 ALL_SLAVE_EN = 1
4894 22:10:46.734821 NEW_RANK_MODE = 1
4895 22:10:46.737945 DLL_IDLE_MODE = 1
4896 22:10:46.741076 LP45_APHY_COMB_EN = 1
4897 22:10:46.744434 TX_ODT_DIS = 1
4898 22:10:46.747985 NEW_8X_MODE = 1
4899 22:10:46.751126 ===================================
4900 22:10:46.754771 ===================================
4901 22:10:46.754853 data_rate = 1866
4902 22:10:46.758131 CKR = 1
4903 22:10:46.761257 DQ_P2S_RATIO = 8
4904 22:10:46.764263 ===================================
4905 22:10:46.768026 CA_P2S_RATIO = 8
4906 22:10:46.771410 DQ_CA_OPEN = 0
4907 22:10:46.774742 DQ_SEMI_OPEN = 0
4908 22:10:46.774829 CA_SEMI_OPEN = 0
4909 22:10:46.777796 CA_FULL_RATE = 0
4910 22:10:46.781498 DQ_CKDIV4_EN = 1
4911 22:10:46.784357 CA_CKDIV4_EN = 1
4912 22:10:46.787943 CA_PREDIV_EN = 0
4913 22:10:46.788072 PH8_DLY = 0
4914 22:10:46.790991 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4915 22:10:46.794499 DQ_AAMCK_DIV = 4
4916 22:10:46.798058 CA_AAMCK_DIV = 4
4917 22:10:46.801096 CA_ADMCK_DIV = 4
4918 22:10:46.804618 DQ_TRACK_CA_EN = 0
4919 22:10:46.808126 CA_PICK = 933
4920 22:10:46.808207 CA_MCKIO = 933
4921 22:10:46.810964 MCKIO_SEMI = 0
4922 22:10:46.814856 PLL_FREQ = 3732
4923 22:10:46.817880 DQ_UI_PI_RATIO = 32
4924 22:10:46.821248 CA_UI_PI_RATIO = 0
4925 22:10:46.824405 ===================================
4926 22:10:46.827811 ===================================
4927 22:10:46.831426 memory_type:LPDDR4
4928 22:10:46.831521 GP_NUM : 10
4929 22:10:46.834486 SRAM_EN : 1
4930 22:10:46.834567 MD32_EN : 0
4931 22:10:46.837481 ===================================
4932 22:10:46.841133 [ANA_INIT] >>>>>>>>>>>>>>
4933 22:10:46.844819 <<<<<< [CONFIGURE PHASE]: ANA_TX
4934 22:10:46.847743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4935 22:10:46.851116 ===================================
4936 22:10:46.854559 data_rate = 1866,PCW = 0X8f00
4937 22:10:46.858129 ===================================
4938 22:10:46.861095 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4939 22:10:46.864852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 22:10:46.871653 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 22:10:46.874424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4942 22:10:46.877792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4943 22:10:46.881099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4944 22:10:46.884140 [ANA_INIT] flow start
4945 22:10:46.887733 [ANA_INIT] PLL >>>>>>>>
4946 22:10:46.887825 [ANA_INIT] PLL <<<<<<<<
4947 22:10:46.891178 [ANA_INIT] MIDPI >>>>>>>>
4948 22:10:46.894676 [ANA_INIT] MIDPI <<<<<<<<
4949 22:10:46.897645 [ANA_INIT] DLL >>>>>>>>
4950 22:10:46.897722 [ANA_INIT] flow end
4951 22:10:46.901074 ============ LP4 DIFF to SE enter ============
4952 22:10:46.907713 ============ LP4 DIFF to SE exit ============
4953 22:10:46.907810 [ANA_INIT] <<<<<<<<<<<<<
4954 22:10:46.910895 [Flow] Enable top DCM control >>>>>
4955 22:10:46.914492 [Flow] Enable top DCM control <<<<<
4956 22:10:46.917924 Enable DLL master slave shuffle
4957 22:10:46.924516 ==============================================================
4958 22:10:46.924613 Gating Mode config
4959 22:10:46.931138 ==============================================================
4960 22:10:46.934563 Config description:
4961 22:10:46.941221 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4962 22:10:46.948171 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4963 22:10:46.954776 SELPH_MODE 0: By rank 1: By Phase
4964 22:10:46.957849 ==============================================================
4965 22:10:46.961572 GAT_TRACK_EN = 1
4966 22:10:46.964575 RX_GATING_MODE = 2
4967 22:10:46.968291 RX_GATING_TRACK_MODE = 2
4968 22:10:46.971381 SELPH_MODE = 1
4969 22:10:46.974953 PICG_EARLY_EN = 1
4970 22:10:46.977974 VALID_LAT_VALUE = 1
4971 22:10:46.985028 ==============================================================
4972 22:10:46.988696 Enter into Gating configuration >>>>
4973 22:10:46.991720 Exit from Gating configuration <<<<
4974 22:10:46.991825 Enter into DVFS_PRE_config >>>>>
4975 22:10:47.005214 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4976 22:10:47.008305 Exit from DVFS_PRE_config <<<<<
4977 22:10:47.011386 Enter into PICG configuration >>>>
4978 22:10:47.015020 Exit from PICG configuration <<<<
4979 22:10:47.015098 [RX_INPUT] configuration >>>>>
4980 22:10:47.018330 [RX_INPUT] configuration <<<<<
4981 22:10:47.025031 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4982 22:10:47.028584 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4983 22:10:47.035014 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4984 22:10:47.041725 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4985 22:10:47.048460 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 22:10:47.055094 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 22:10:47.058657 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4988 22:10:47.061590 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4989 22:10:47.065103 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4990 22:10:47.072074 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4991 22:10:47.074962 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4992 22:10:47.078510 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4993 22:10:47.081735 ===================================
4994 22:10:47.085359 LPDDR4 DRAM CONFIGURATION
4995 22:10:47.088453 ===================================
4996 22:10:47.088585 EX_ROW_EN[0] = 0x0
4997 22:10:47.091973 EX_ROW_EN[1] = 0x0
4998 22:10:47.095298 LP4Y_EN = 0x0
4999 22:10:47.095399 WORK_FSP = 0x0
5000 22:10:47.098407 WL = 0x3
5001 22:10:47.098557 RL = 0x3
5002 22:10:47.102106 BL = 0x2
5003 22:10:47.102209 RPST = 0x0
5004 22:10:47.105194 RD_PRE = 0x0
5005 22:10:47.105280 WR_PRE = 0x1
5006 22:10:47.108556 WR_PST = 0x0
5007 22:10:47.108679 DBI_WR = 0x0
5008 22:10:47.111658 DBI_RD = 0x0
5009 22:10:47.111755 OTF = 0x1
5010 22:10:47.115316 ===================================
5011 22:10:47.118710 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5012 22:10:47.125305 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5013 22:10:47.128291 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5014 22:10:47.132109 ===================================
5015 22:10:47.135329 LPDDR4 DRAM CONFIGURATION
5016 22:10:47.138349 ===================================
5017 22:10:47.138424 EX_ROW_EN[0] = 0x10
5018 22:10:47.142045 EX_ROW_EN[1] = 0x0
5019 22:10:47.142123 LP4Y_EN = 0x0
5020 22:10:47.145107 WORK_FSP = 0x0
5021 22:10:47.145180 WL = 0x3
5022 22:10:47.148662 RL = 0x3
5023 22:10:47.151694 BL = 0x2
5024 22:10:47.151792 RPST = 0x0
5025 22:10:47.155001 RD_PRE = 0x0
5026 22:10:47.155106 WR_PRE = 0x1
5027 22:10:47.158572 WR_PST = 0x0
5028 22:10:47.158652 DBI_WR = 0x0
5029 22:10:47.161914 DBI_RD = 0x0
5030 22:10:47.162008 OTF = 0x1
5031 22:10:47.165469 ===================================
5032 22:10:47.171938 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5033 22:10:47.175543 nWR fixed to 30
5034 22:10:47.179233 [ModeRegInit_LP4] CH0 RK0
5035 22:10:47.179312 [ModeRegInit_LP4] CH0 RK1
5036 22:10:47.182691 [ModeRegInit_LP4] CH1 RK0
5037 22:10:47.186019 [ModeRegInit_LP4] CH1 RK1
5038 22:10:47.186100 match AC timing 9
5039 22:10:47.192220 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5040 22:10:47.195932 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5041 22:10:47.199374 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5042 22:10:47.205559 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5043 22:10:47.209145 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5044 22:10:47.209226 ==
5045 22:10:47.212255 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 22:10:47.216196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5047 22:10:47.216311 ==
5048 22:10:47.222476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5049 22:10:47.228999 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5050 22:10:47.232625 [CA 0] Center 38 (8~69) winsize 62
5051 22:10:47.235711 [CA 1] Center 38 (7~69) winsize 63
5052 22:10:47.239249 [CA 2] Center 35 (5~66) winsize 62
5053 22:10:47.242842 [CA 3] Center 35 (4~66) winsize 63
5054 22:10:47.245749 [CA 4] Center 34 (4~64) winsize 61
5055 22:10:47.249537 [CA 5] Center 34 (4~64) winsize 61
5056 22:10:47.249656
5057 22:10:47.252920 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5058 22:10:47.252996
5059 22:10:47.256055 [CATrainingPosCal] consider 1 rank data
5060 22:10:47.259446 u2DelayCellTimex100 = 270/100 ps
5061 22:10:47.262778 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5062 22:10:47.266184 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5063 22:10:47.269817 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5064 22:10:47.272640 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5065 22:10:47.276481 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5066 22:10:47.279661 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5067 22:10:47.279781
5068 22:10:47.282773 CA PerBit enable=1, Macro0, CA PI delay=34
5069 22:10:47.282873
5070 22:10:47.286434 [CBTSetCACLKResult] CA Dly = 34
5071 22:10:47.289510 CS Dly: 6 (0~37)
5072 22:10:47.289612 ==
5073 22:10:47.293191 Dram Type= 6, Freq= 0, CH_0, rank 1
5074 22:10:47.295987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5075 22:10:47.296076 ==
5076 22:10:47.302824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5077 22:10:47.309983 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5078 22:10:47.312886 [CA 0] Center 38 (8~69) winsize 62
5079 22:10:47.316436 [CA 1] Center 38 (7~69) winsize 63
5080 22:10:47.319919 [CA 2] Center 35 (5~66) winsize 62
5081 22:10:47.322916 [CA 3] Center 35 (4~66) winsize 63
5082 22:10:47.322995 [CA 4] Center 34 (3~65) winsize 63
5083 22:10:47.326292 [CA 5] Center 33 (3~64) winsize 62
5084 22:10:47.326371
5085 22:10:47.332869 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5086 22:10:47.332961
5087 22:10:47.336478 [CATrainingPosCal] consider 2 rank data
5088 22:10:47.339406 u2DelayCellTimex100 = 270/100 ps
5089 22:10:47.342904 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5090 22:10:47.346369 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5091 22:10:47.350018 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5092 22:10:47.353016 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5093 22:10:47.356616 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5094 22:10:47.359694 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5095 22:10:47.359770
5096 22:10:47.362941 CA PerBit enable=1, Macro0, CA PI delay=34
5097 22:10:47.363060
5098 22:10:47.366244 [CBTSetCACLKResult] CA Dly = 34
5099 22:10:47.369614 CS Dly: 7 (0~39)
5100 22:10:47.369700
5101 22:10:47.372990 ----->DramcWriteLeveling(PI) begin...
5102 22:10:47.373070 ==
5103 22:10:47.376496 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 22:10:47.379575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 22:10:47.379680 ==
5106 22:10:47.382919 Write leveling (Byte 0): 31 => 31
5107 22:10:47.386218 Write leveling (Byte 1): 30 => 30
5108 22:10:47.389579 DramcWriteLeveling(PI) end<-----
5109 22:10:47.389655
5110 22:10:47.389724 ==
5111 22:10:47.393161 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 22:10:47.396821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 22:10:47.396899 ==
5114 22:10:47.399866 [Gating] SW mode calibration
5115 22:10:47.406401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5116 22:10:47.413436 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5117 22:10:47.416458 0 14 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5118 22:10:47.420418 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5119 22:10:47.426779 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 22:10:47.430328 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 22:10:47.433188 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 22:10:47.440135 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 22:10:47.443313 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 22:10:47.446507 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5125 22:10:47.449984 0 15 0 | B1->B0 | 3232 2929 | 0 0 | (0 1) (0 1)
5126 22:10:47.456611 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5127 22:10:47.460234 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 22:10:47.463728 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 22:10:47.470215 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 22:10:47.473213 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 22:10:47.476903 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 22:10:47.483411 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
5133 22:10:47.487060 1 0 0 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (0 0)
5134 22:10:47.489831 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 22:10:47.496764 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 22:10:47.500569 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 22:10:47.503427 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 22:10:47.509977 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 22:10:47.513829 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 22:10:47.516677 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5141 22:10:47.523340 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5142 22:10:47.526723 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5143 22:10:47.530258 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 22:10:47.536522 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 22:10:47.540131 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 22:10:47.543832 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 22:10:47.546767 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 22:10:47.554264 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 22:10:47.557148 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 22:10:47.559892 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 22:10:47.566536 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 22:10:47.570249 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 22:10:47.573400 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 22:10:47.580327 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 22:10:47.583239 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 22:10:47.586615 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5157 22:10:47.593422 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5158 22:10:47.596901 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5159 22:10:47.600270 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 22:10:47.603374 Total UI for P1: 0, mck2ui 16
5161 22:10:47.606946 best dqsien dly found for B0: ( 1, 3, 0)
5162 22:10:47.610116 Total UI for P1: 0, mck2ui 16
5163 22:10:47.613441 best dqsien dly found for B1: ( 1, 3, 2)
5164 22:10:47.617240 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5165 22:10:47.620026 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5166 22:10:47.620107
5167 22:10:47.623679 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5168 22:10:47.626621 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5169 22:10:47.630068 [Gating] SW calibration Done
5170 22:10:47.630150 ==
5171 22:10:47.633418 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 22:10:47.640105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 22:10:47.640186 ==
5174 22:10:47.640249 RX Vref Scan: 0
5175 22:10:47.640309
5176 22:10:47.643493 RX Vref 0 -> 0, step: 1
5177 22:10:47.643604
5178 22:10:47.646827 RX Delay -80 -> 252, step: 8
5179 22:10:47.650327 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5180 22:10:47.653872 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5181 22:10:47.656847 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5182 22:10:47.660351 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5183 22:10:47.664245 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5184 22:10:47.670278 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5185 22:10:47.673824 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5186 22:10:47.676892 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5187 22:10:47.680492 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5188 22:10:47.684121 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5189 22:10:47.686894 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5190 22:10:47.693634 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5191 22:10:47.697271 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5192 22:10:47.700397 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5193 22:10:47.704024 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5194 22:10:47.707005 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5195 22:10:47.707086 ==
5196 22:10:47.710218 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 22:10:47.717328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 22:10:47.717411 ==
5199 22:10:47.717476 DQS Delay:
5200 22:10:47.720375 DQS0 = 0, DQS1 = 0
5201 22:10:47.720448 DQM Delay:
5202 22:10:47.720509 DQM0 = 96, DQM1 = 87
5203 22:10:47.723857 DQ Delay:
5204 22:10:47.727642 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5205 22:10:47.730433 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5206 22:10:47.734080 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5207 22:10:47.737684 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5208 22:10:47.737766
5209 22:10:47.737830
5210 22:10:47.737888 ==
5211 22:10:47.740366 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 22:10:47.743904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 22:10:47.743984 ==
5214 22:10:47.744052
5215 22:10:47.744112
5216 22:10:47.747244 TX Vref Scan disable
5217 22:10:47.747325 == TX Byte 0 ==
5218 22:10:47.754051 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5219 22:10:47.757236 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5220 22:10:47.757316 == TX Byte 1 ==
5221 22:10:47.764175 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5222 22:10:47.767193 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5223 22:10:47.767273 ==
5224 22:10:47.770931 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 22:10:47.774066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 22:10:47.774194 ==
5227 22:10:47.774258
5228 22:10:47.774317
5229 22:10:47.777328 TX Vref Scan disable
5230 22:10:47.780595 == TX Byte 0 ==
5231 22:10:47.784398 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5232 22:10:47.787272 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5233 22:10:47.790844 == TX Byte 1 ==
5234 22:10:47.793732 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5235 22:10:47.797404 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5236 22:10:47.797484
5237 22:10:47.800567 [DATLAT]
5238 22:10:47.800646 Freq=933, CH0 RK0
5239 22:10:47.800751
5240 22:10:47.804000 DATLAT Default: 0xd
5241 22:10:47.804081 0, 0xFFFF, sum = 0
5242 22:10:47.807759 1, 0xFFFF, sum = 0
5243 22:10:47.807841 2, 0xFFFF, sum = 0
5244 22:10:47.810961 3, 0xFFFF, sum = 0
5245 22:10:47.811057 4, 0xFFFF, sum = 0
5246 22:10:47.813879 5, 0xFFFF, sum = 0
5247 22:10:47.814034 6, 0xFFFF, sum = 0
5248 22:10:47.817302 7, 0xFFFF, sum = 0
5249 22:10:47.817409 8, 0xFFFF, sum = 0
5250 22:10:47.820478 9, 0xFFFF, sum = 0
5251 22:10:47.820591 10, 0x0, sum = 1
5252 22:10:47.824095 11, 0x0, sum = 2
5253 22:10:47.824208 12, 0x0, sum = 3
5254 22:10:47.827144 13, 0x0, sum = 4
5255 22:10:47.827230 best_step = 11
5256 22:10:47.827315
5257 22:10:47.827396 ==
5258 22:10:47.830829 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 22:10:47.837342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 22:10:47.837426 ==
5261 22:10:47.837510 RX Vref Scan: 1
5262 22:10:47.837589
5263 22:10:47.840985 RX Vref 0 -> 0, step: 1
5264 22:10:47.841067
5265 22:10:47.843869 RX Delay -61 -> 252, step: 4
5266 22:10:47.843951
5267 22:10:47.847469 Set Vref, RX VrefLevel [Byte0]: 53
5268 22:10:47.850428 [Byte1]: 50
5269 22:10:47.850510
5270 22:10:47.854049 Final RX Vref Byte 0 = 53 to rank0
5271 22:10:47.857631 Final RX Vref Byte 1 = 50 to rank0
5272 22:10:47.860444 Final RX Vref Byte 0 = 53 to rank1
5273 22:10:47.864110 Final RX Vref Byte 1 = 50 to rank1==
5274 22:10:47.867673 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 22:10:47.870565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 22:10:47.870646 ==
5277 22:10:47.874135 DQS Delay:
5278 22:10:47.874246 DQS0 = 0, DQS1 = 0
5279 22:10:47.874344 DQM Delay:
5280 22:10:47.877588 DQM0 = 96, DQM1 = 88
5281 22:10:47.877662 DQ Delay:
5282 22:10:47.880525 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5283 22:10:47.884390 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =104
5284 22:10:47.887353 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =82
5285 22:10:47.890481 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =96
5286 22:10:47.890561
5287 22:10:47.890631
5288 22:10:47.900683 [DQSOSCAuto] RK0, (LSB)MR18= 0x1804, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5289 22:10:47.900766 CH0 RK0: MR19=505, MR18=1804
5290 22:10:47.907590 CH0_RK0: MR19=0x505, MR18=0x1804, DQSOSC=414, MR23=63, INC=63, DEC=42
5291 22:10:47.907676
5292 22:10:47.910726 ----->DramcWriteLeveling(PI) begin...
5293 22:10:47.910838 ==
5294 22:10:47.913961 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 22:10:47.920610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 22:10:47.920714 ==
5297 22:10:47.923978 Write leveling (Byte 0): 29 => 29
5298 22:10:47.927207 Write leveling (Byte 1): 29 => 29
5299 22:10:47.927308 DramcWriteLeveling(PI) end<-----
5300 22:10:47.930659
5301 22:10:47.930736 ==
5302 22:10:47.934287 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 22:10:47.937470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 22:10:47.937549 ==
5305 22:10:47.941027 [Gating] SW mode calibration
5306 22:10:47.947665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5307 22:10:47.951066 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5308 22:10:47.957687 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
5309 22:10:47.961318 0 14 4 | B1->B0 | 3332 3434 | 1 1 | (1 1) (1 1)
5310 22:10:47.964187 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 22:10:47.971187 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 22:10:47.974526 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 22:10:47.977662 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 22:10:47.984023 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 22:10:47.987809 0 14 28 | B1->B0 | 3131 2b2b | 0 0 | (0 1) (1 1)
5316 22:10:47.990765 0 15 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
5317 22:10:47.994166 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 22:10:48.000901 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 22:10:48.004427 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 22:10:48.008209 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 22:10:48.014501 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 22:10:48.017940 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 22:10:48.021187 0 15 28 | B1->B0 | 2c2c 3d3d | 0 0 | (1 1) (1 1)
5324 22:10:48.027718 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5325 22:10:48.031156 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 22:10:48.034575 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 22:10:48.041364 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 22:10:48.044376 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 22:10:48.047613 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 22:10:48.054448 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5331 22:10:48.058024 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5332 22:10:48.061438 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5333 22:10:48.064531 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5334 22:10:48.071242 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 22:10:48.075060 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 22:10:48.077968 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 22:10:48.085086 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 22:10:48.087858 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 22:10:48.091991 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 22:10:48.098029 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 22:10:48.101655 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 22:10:48.104737 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 22:10:48.111552 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 22:10:48.114608 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 22:10:48.118023 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 22:10:48.124696 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5347 22:10:48.128109 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5348 22:10:48.131463 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5349 22:10:48.134597 Total UI for P1: 0, mck2ui 16
5350 22:10:48.137927 best dqsien dly found for B0: ( 1, 2, 26)
5351 22:10:48.141289 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 22:10:48.145004 Total UI for P1: 0, mck2ui 16
5353 22:10:48.148135 best dqsien dly found for B1: ( 1, 3, 0)
5354 22:10:48.151779 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5355 22:10:48.154758 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5356 22:10:48.158041
5357 22:10:48.161611 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5358 22:10:48.165143 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5359 22:10:48.168194 [Gating] SW calibration Done
5360 22:10:48.168287 ==
5361 22:10:48.171878 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 22:10:48.174867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 22:10:48.174940 ==
5364 22:10:48.175007 RX Vref Scan: 0
5365 22:10:48.175070
5366 22:10:48.178577 RX Vref 0 -> 0, step: 1
5367 22:10:48.178653
5368 22:10:48.181478 RX Delay -80 -> 252, step: 8
5369 22:10:48.185013 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5370 22:10:48.188163 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5371 22:10:48.191665 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5372 22:10:48.195161 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5373 22:10:48.201580 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5374 22:10:48.205187 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5375 22:10:48.208652 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5376 22:10:48.211812 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5377 22:10:48.215043 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5378 22:10:48.218539 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5379 22:10:48.225035 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5380 22:10:48.228588 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5381 22:10:48.231674 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5382 22:10:48.235407 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5383 22:10:48.238248 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5384 22:10:48.241799 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5385 22:10:48.245340 ==
5386 22:10:48.248336 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 22:10:48.251988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 22:10:48.252070 ==
5389 22:10:48.252135 DQS Delay:
5390 22:10:48.255170 DQS0 = 0, DQS1 = 0
5391 22:10:48.255251 DQM Delay:
5392 22:10:48.258885 DQM0 = 97, DQM1 = 87
5393 22:10:48.258966 DQ Delay:
5394 22:10:48.262000 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5395 22:10:48.265564 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5396 22:10:48.268561 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =75
5397 22:10:48.272255 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5398 22:10:48.272372
5399 22:10:48.272468
5400 22:10:48.272558 ==
5401 22:10:48.275768 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 22:10:48.278780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 22:10:48.278886 ==
5404 22:10:48.278979
5405 22:10:48.279075
5406 22:10:48.282285 TX Vref Scan disable
5407 22:10:48.285315 == TX Byte 0 ==
5408 22:10:48.288787 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5409 22:10:48.292333 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5410 22:10:48.295501 == TX Byte 1 ==
5411 22:10:48.298644 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5412 22:10:48.302130 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5413 22:10:48.302212 ==
5414 22:10:48.305721 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 22:10:48.309223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 22:10:48.309342 ==
5417 22:10:48.309444
5418 22:10:48.312213
5419 22:10:48.312324 TX Vref Scan disable
5420 22:10:48.315289 == TX Byte 0 ==
5421 22:10:48.319112 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5422 22:10:48.322688 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5423 22:10:48.325578 == TX Byte 1 ==
5424 22:10:48.329045 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5425 22:10:48.332080 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5426 22:10:48.332167
5427 22:10:48.335677 [DATLAT]
5428 22:10:48.335786 Freq=933, CH0 RK1
5429 22:10:48.335879
5430 22:10:48.338683 DATLAT Default: 0xb
5431 22:10:48.338770 0, 0xFFFF, sum = 0
5432 22:10:48.342279 1, 0xFFFF, sum = 0
5433 22:10:48.342361 2, 0xFFFF, sum = 0
5434 22:10:48.345447 3, 0xFFFF, sum = 0
5435 22:10:48.345530 4, 0xFFFF, sum = 0
5436 22:10:48.348969 5, 0xFFFF, sum = 0
5437 22:10:48.349045 6, 0xFFFF, sum = 0
5438 22:10:48.351959 7, 0xFFFF, sum = 0
5439 22:10:48.355447 8, 0xFFFF, sum = 0
5440 22:10:48.355558 9, 0xFFFF, sum = 0
5441 22:10:48.355652 10, 0x0, sum = 1
5442 22:10:48.358645 11, 0x0, sum = 2
5443 22:10:48.358724 12, 0x0, sum = 3
5444 22:10:48.362407 13, 0x0, sum = 4
5445 22:10:48.362490 best_step = 11
5446 22:10:48.362554
5447 22:10:48.362613 ==
5448 22:10:48.365665 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 22:10:48.372397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 22:10:48.372555 ==
5451 22:10:48.372679 RX Vref Scan: 0
5452 22:10:48.372790
5453 22:10:48.375505 RX Vref 0 -> 0, step: 1
5454 22:10:48.375634
5455 22:10:48.378521 RX Delay -69 -> 252, step: 4
5456 22:10:48.382220 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5457 22:10:48.385861 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5458 22:10:48.392167 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5459 22:10:48.395929 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5460 22:10:48.398935 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5461 22:10:48.402454 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5462 22:10:48.405383 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5463 22:10:48.408944 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5464 22:10:48.415852 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5465 22:10:48.419153 iDelay=199, Bit 9, Center 76 (-13 ~ 166) 180
5466 22:10:48.422748 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5467 22:10:48.425697 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5468 22:10:48.429705 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5469 22:10:48.432328 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5470 22:10:48.438976 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5471 22:10:48.442402 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5472 22:10:48.442503 ==
5473 22:10:48.445802 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 22:10:48.449434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 22:10:48.449541 ==
5476 22:10:48.452372 DQS Delay:
5477 22:10:48.452477 DQS0 = 0, DQS1 = 0
5478 22:10:48.452567 DQM Delay:
5479 22:10:48.456237 DQM0 = 95, DQM1 = 87
5480 22:10:48.456312 DQ Delay:
5481 22:10:48.459114 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5482 22:10:48.462592 DQ4 =94, DQ5 =84, DQ6 =106, DQ7 =102
5483 22:10:48.466013 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =78
5484 22:10:48.469059 DQ12 =90, DQ13 =92, DQ14 =98, DQ15 =96
5485 22:10:48.469137
5486 22:10:48.469200
5487 22:10:48.479172 [DQSOSCAuto] RK1, (LSB)MR18= 0x1905, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5488 22:10:48.479284 CH0 RK1: MR19=505, MR18=1905
5489 22:10:48.485906 CH0_RK1: MR19=0x505, MR18=0x1905, DQSOSC=413, MR23=63, INC=63, DEC=42
5490 22:10:48.489212 [RxdqsGatingPostProcess] freq 933
5491 22:10:48.496115 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5492 22:10:48.499332 best DQS0 dly(2T, 0.5T) = (0, 11)
5493 22:10:48.503043 best DQS1 dly(2T, 0.5T) = (0, 11)
5494 22:10:48.505829 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5495 22:10:48.509309 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5496 22:10:48.509402 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 22:10:48.512436 best DQS1 dly(2T, 0.5T) = (0, 11)
5498 22:10:48.516000 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 22:10:48.519314 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5500 22:10:48.522498 Pre-setting of DQS Precalculation
5501 22:10:48.529621 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5502 22:10:48.529710 ==
5503 22:10:48.532614 Dram Type= 6, Freq= 0, CH_1, rank 0
5504 22:10:48.536101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 22:10:48.536182 ==
5506 22:10:48.542852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5507 22:10:48.549200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5508 22:10:48.552533 [CA 0] Center 36 (6~67) winsize 62
5509 22:10:48.555886 [CA 1] Center 36 (6~67) winsize 62
5510 22:10:48.559542 [CA 2] Center 34 (4~64) winsize 61
5511 22:10:48.562621 [CA 3] Center 33 (3~64) winsize 62
5512 22:10:48.562742 [CA 4] Center 34 (4~64) winsize 61
5513 22:10:48.566129 [CA 5] Center 33 (3~63) winsize 61
5514 22:10:48.566239
5515 22:10:48.572845 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5516 22:10:48.572926
5517 22:10:48.575940 [CATrainingPosCal] consider 1 rank data
5518 22:10:48.579059 u2DelayCellTimex100 = 270/100 ps
5519 22:10:48.582556 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5520 22:10:48.585777 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5521 22:10:48.589368 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5522 22:10:48.592734 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5523 22:10:48.595969 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5524 22:10:48.599066 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5525 22:10:48.599191
5526 22:10:48.602808 CA PerBit enable=1, Macro0, CA PI delay=33
5527 22:10:48.602910
5528 22:10:48.605656 [CBTSetCACLKResult] CA Dly = 33
5529 22:10:48.609314 CS Dly: 4 (0~35)
5530 22:10:48.609392 ==
5531 22:10:48.612851 Dram Type= 6, Freq= 0, CH_1, rank 1
5532 22:10:48.615781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 22:10:48.615881 ==
5534 22:10:48.622848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 22:10:48.629289 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5536 22:10:48.632313 [CA 0] Center 36 (6~67) winsize 62
5537 22:10:48.636007 [CA 1] Center 37 (7~67) winsize 61
5538 22:10:48.639305 [CA 2] Center 33 (3~64) winsize 62
5539 22:10:48.642966 [CA 3] Center 33 (3~64) winsize 62
5540 22:10:48.643083 [CA 4] Center 34 (3~65) winsize 63
5541 22:10:48.645937 [CA 5] Center 32 (2~63) winsize 62
5542 22:10:48.646010
5543 22:10:48.652622 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5544 22:10:48.652758
5545 22:10:48.656352 [CATrainingPosCal] consider 2 rank data
5546 22:10:48.659490 u2DelayCellTimex100 = 270/100 ps
5547 22:10:48.662631 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5548 22:10:48.665939 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5549 22:10:48.669599 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5550 22:10:48.672891 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5551 22:10:48.676086 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5552 22:10:48.679307 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5553 22:10:48.679416
5554 22:10:48.683188 CA PerBit enable=1, Macro0, CA PI delay=33
5555 22:10:48.683294
5556 22:10:48.686224 [CBTSetCACLKResult] CA Dly = 33
5557 22:10:48.689651 CS Dly: 5 (0~37)
5558 22:10:48.689738
5559 22:10:48.693256 ----->DramcWriteLeveling(PI) begin...
5560 22:10:48.693360 ==
5561 22:10:48.696026 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 22:10:48.699463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 22:10:48.699540 ==
5564 22:10:48.703134 Write leveling (Byte 0): 26 => 26
5565 22:10:48.706315 Write leveling (Byte 1): 29 => 29
5566 22:10:48.709270 DramcWriteLeveling(PI) end<-----
5567 22:10:48.709372
5568 22:10:48.709473 ==
5569 22:10:48.712482 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 22:10:48.716178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 22:10:48.716260 ==
5572 22:10:48.719679 [Gating] SW mode calibration
5573 22:10:48.726020 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5574 22:10:48.732416 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5575 22:10:48.736085 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5576 22:10:48.739085 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5577 22:10:48.746223 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 22:10:48.749340 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5579 22:10:48.753001 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5580 22:10:48.758972 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 22:10:48.762591 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 22:10:48.766276 0 14 28 | B1->B0 | 2e2e 3030 | 0 0 | (0 1) (0 1)
5583 22:10:48.772469 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5584 22:10:48.775739 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 22:10:48.779266 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 22:10:48.786079 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5587 22:10:48.789456 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 22:10:48.792461 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 22:10:48.799632 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5590 22:10:48.802543 0 15 28 | B1->B0 | 2c2c 2e2e | 0 0 | (1 1) (1 1)
5591 22:10:48.806045 1 0 0 | B1->B0 | 4444 4444 | 0 0 | (0 0) (0 0)
5592 22:10:48.809271 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 22:10:48.815917 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 22:10:48.819280 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 22:10:48.823098 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 22:10:48.829633 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 22:10:48.832727 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 22:10:48.836136 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5599 22:10:48.842692 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 22:10:48.846055 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 22:10:48.849707 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 22:10:48.856285 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 22:10:48.860059 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 22:10:48.863015 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 22:10:48.866816 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 22:10:48.873499 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 22:10:48.876394 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 22:10:48.880074 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 22:10:48.886571 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 22:10:48.889671 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 22:10:48.893443 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 22:10:48.899657 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 22:10:48.903289 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5614 22:10:48.906604 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5615 22:10:48.913056 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 22:10:48.913144 Total UI for P1: 0, mck2ui 16
5617 22:10:48.920127 best dqsien dly found for B0: ( 1, 2, 26)
5618 22:10:48.920213 Total UI for P1: 0, mck2ui 16
5619 22:10:48.923197 best dqsien dly found for B1: ( 1, 2, 26)
5620 22:10:48.930062 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5621 22:10:48.933197 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5622 22:10:48.933312
5623 22:10:48.936564 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5624 22:10:48.940321 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5625 22:10:48.943400 [Gating] SW calibration Done
5626 22:10:48.943499 ==
5627 22:10:48.946735 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 22:10:48.950660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 22:10:48.950746 ==
5630 22:10:48.953223 RX Vref Scan: 0
5631 22:10:48.953306
5632 22:10:48.953390 RX Vref 0 -> 0, step: 1
5633 22:10:48.953468
5634 22:10:48.956853 RX Delay -80 -> 252, step: 8
5635 22:10:48.959961 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5636 22:10:48.963509 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5637 22:10:48.970106 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5638 22:10:48.973284 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5639 22:10:48.976747 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5640 22:10:48.980266 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5641 22:10:48.983878 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5642 22:10:48.986996 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5643 22:10:48.993578 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5644 22:10:48.996904 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5645 22:10:49.000393 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5646 22:10:49.003397 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5647 22:10:49.007275 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5648 22:10:49.010524 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5649 22:10:49.016801 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5650 22:10:49.020119 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5651 22:10:49.020200 ==
5652 22:10:49.023803 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 22:10:49.026841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 22:10:49.026922 ==
5655 22:10:49.030611 DQS Delay:
5656 22:10:49.030737 DQS0 = 0, DQS1 = 0
5657 22:10:49.030830 DQM Delay:
5658 22:10:49.033540 DQM0 = 95, DQM1 = 89
5659 22:10:49.033619 DQ Delay:
5660 22:10:49.036933 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =95
5661 22:10:49.040536 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5662 22:10:49.043619 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5663 22:10:49.046931 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5664 22:10:49.047011
5665 22:10:49.047074
5666 22:10:49.047133 ==
5667 22:10:49.050309 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 22:10:49.057061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 22:10:49.057143 ==
5670 22:10:49.057226
5671 22:10:49.057305
5672 22:10:49.057397 TX Vref Scan disable
5673 22:10:49.060104 == TX Byte 0 ==
5674 22:10:49.063476 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5675 22:10:49.066961 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5676 22:10:49.070309 == TX Byte 1 ==
5677 22:10:49.073326 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5678 22:10:49.076999 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5679 22:10:49.080212 ==
5680 22:10:49.083965 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 22:10:49.086788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 22:10:49.086867 ==
5683 22:10:49.086961
5684 22:10:49.087018
5685 22:10:49.090522 TX Vref Scan disable
5686 22:10:49.090606 == TX Byte 0 ==
5687 22:10:49.097147 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5688 22:10:49.100586 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5689 22:10:49.100727 == TX Byte 1 ==
5690 22:10:49.106805 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5691 22:10:49.110394 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5692 22:10:49.110473
5693 22:10:49.110537 [DATLAT]
5694 22:10:49.113340 Freq=933, CH1 RK0
5695 22:10:49.113439
5696 22:10:49.113581 DATLAT Default: 0xd
5697 22:10:49.117066 0, 0xFFFF, sum = 0
5698 22:10:49.117147 1, 0xFFFF, sum = 0
5699 22:10:49.120225 2, 0xFFFF, sum = 0
5700 22:10:49.120306 3, 0xFFFF, sum = 0
5701 22:10:49.123615 4, 0xFFFF, sum = 0
5702 22:10:49.123733 5, 0xFFFF, sum = 0
5703 22:10:49.126775 6, 0xFFFF, sum = 0
5704 22:10:49.126857 7, 0xFFFF, sum = 0
5705 22:10:49.130358 8, 0xFFFF, sum = 0
5706 22:10:49.130439 9, 0xFFFF, sum = 0
5707 22:10:49.133783 10, 0x0, sum = 1
5708 22:10:49.133864 11, 0x0, sum = 2
5709 22:10:49.136881 12, 0x0, sum = 3
5710 22:10:49.136962 13, 0x0, sum = 4
5711 22:10:49.140423 best_step = 11
5712 22:10:49.140528
5713 22:10:49.140619 ==
5714 22:10:49.143813 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 22:10:49.146634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 22:10:49.146730 ==
5717 22:10:49.150112 RX Vref Scan: 1
5718 22:10:49.150194
5719 22:10:49.150277 RX Vref 0 -> 0, step: 1
5720 22:10:49.150355
5721 22:10:49.153764 RX Delay -61 -> 252, step: 4
5722 22:10:49.153846
5723 22:10:49.157283 Set Vref, RX VrefLevel [Byte0]: 57
5724 22:10:49.160395 [Byte1]: 50
5725 22:10:49.164366
5726 22:10:49.164447 Final RX Vref Byte 0 = 57 to rank0
5727 22:10:49.167623 Final RX Vref Byte 1 = 50 to rank0
5728 22:10:49.171112 Final RX Vref Byte 0 = 57 to rank1
5729 22:10:49.174409 Final RX Vref Byte 1 = 50 to rank1==
5730 22:10:49.177609 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 22:10:49.184160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 22:10:49.184242 ==
5733 22:10:49.184326 DQS Delay:
5734 22:10:49.184423 DQS0 = 0, DQS1 = 0
5735 22:10:49.187314 DQM Delay:
5736 22:10:49.187411 DQM0 = 97, DQM1 = 90
5737 22:10:49.190889 DQ Delay:
5738 22:10:49.194009 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =98
5739 22:10:49.197643 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5740 22:10:49.200707 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5741 22:10:49.204268 DQ12 =100, DQ13 =98, DQ14 =96, DQ15 =94
5742 22:10:49.204350
5743 22:10:49.204433
5744 22:10:49.211122 [DQSOSCAuto] RK0, (LSB)MR18= 0x13f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5745 22:10:49.214081 CH1 RK0: MR19=504, MR18=13F0
5746 22:10:49.220532 CH1_RK0: MR19=0x504, MR18=0x13F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5747 22:10:49.220616
5748 22:10:49.224045 ----->DramcWriteLeveling(PI) begin...
5749 22:10:49.224126 ==
5750 22:10:49.227602 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 22:10:49.230590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 22:10:49.230670 ==
5753 22:10:49.234052 Write leveling (Byte 0): 27 => 27
5754 22:10:49.237363 Write leveling (Byte 1): 29 => 29
5755 22:10:49.240544 DramcWriteLeveling(PI) end<-----
5756 22:10:49.240641
5757 22:10:49.240731 ==
5758 22:10:49.243946 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 22:10:49.247603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 22:10:49.247725 ==
5761 22:10:49.250704 [Gating] SW mode calibration
5762 22:10:49.257667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5763 22:10:49.264212 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5764 22:10:49.267271 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 22:10:49.270764 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5766 22:10:49.277735 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 22:10:49.280969 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 22:10:49.283944 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5769 22:10:49.291244 0 14 20 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
5770 22:10:49.294126 0 14 24 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
5771 22:10:49.297959 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5772 22:10:49.304549 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 22:10:49.307631 0 15 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5774 22:10:49.311261 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 22:10:49.317714 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5776 22:10:49.321124 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 22:10:49.324662 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5778 22:10:49.330966 0 15 24 | B1->B0 | 2828 2f2f | 0 1 | (0 0) (0 0)
5779 22:10:49.334562 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5780 22:10:49.337627 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 22:10:49.341378 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 22:10:49.347777 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 22:10:49.350994 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 22:10:49.354325 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 22:10:49.360999 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 22:10:49.364206 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5787 22:10:49.367944 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5788 22:10:49.374370 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 22:10:49.377880 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 22:10:49.380886 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 22:10:49.387902 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 22:10:49.391357 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 22:10:49.394628 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 22:10:49.401159 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 22:10:49.404123 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 22:10:49.407840 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 22:10:49.414239 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 22:10:49.417936 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 22:10:49.421252 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 22:10:49.427585 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 22:10:49.431102 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 22:10:49.434516 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5803 22:10:49.437608 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 22:10:49.441139 Total UI for P1: 0, mck2ui 16
5805 22:10:49.444902 best dqsien dly found for B0: ( 1, 2, 24)
5806 22:10:49.447756 Total UI for P1: 0, mck2ui 16
5807 22:10:49.451239 best dqsien dly found for B1: ( 1, 2, 26)
5808 22:10:49.454759 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5809 22:10:49.457830 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5810 22:10:49.457911
5811 22:10:49.464560 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5812 22:10:49.467895 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5813 22:10:49.471213 [Gating] SW calibration Done
5814 22:10:49.471296 ==
5815 22:10:49.474463 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 22:10:49.477828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 22:10:49.477912 ==
5818 22:10:49.477997 RX Vref Scan: 0
5819 22:10:49.478100
5820 22:10:49.481097 RX Vref 0 -> 0, step: 1
5821 22:10:49.481184
5822 22:10:49.484323 RX Delay -80 -> 252, step: 8
5823 22:10:49.487788 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5824 22:10:49.491236 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5825 22:10:49.494366 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5826 22:10:49.501206 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5827 22:10:49.504276 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5828 22:10:49.507997 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5829 22:10:49.511366 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5830 22:10:49.514567 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5831 22:10:49.517595 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5832 22:10:49.524575 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5833 22:10:49.527796 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5834 22:10:49.531291 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5835 22:10:49.534152 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5836 22:10:49.537659 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5837 22:10:49.544135 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5838 22:10:49.547981 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5839 22:10:49.548064 ==
5840 22:10:49.550918 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 22:10:49.554558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 22:10:49.554642 ==
5843 22:10:49.554727 DQS Delay:
5844 22:10:49.557350 DQS0 = 0, DQS1 = 0
5845 22:10:49.557432 DQM Delay:
5846 22:10:49.560940 DQM0 = 94, DQM1 = 88
5847 22:10:49.561024 DQ Delay:
5848 22:10:49.564157 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5849 22:10:49.567642 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5850 22:10:49.570896 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5851 22:10:49.574209 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5852 22:10:49.574292
5853 22:10:49.574376
5854 22:10:49.574455 ==
5855 22:10:49.577576 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 22:10:49.580926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 22:10:49.584247 ==
5858 22:10:49.584352
5859 22:10:49.584443
5860 22:10:49.584529 TX Vref Scan disable
5861 22:10:49.587812 == TX Byte 0 ==
5862 22:10:49.590918 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5863 22:10:49.594293 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5864 22:10:49.597420 == TX Byte 1 ==
5865 22:10:49.600644 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5866 22:10:49.604213 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5867 22:10:49.604398 ==
5868 22:10:49.607459 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 22:10:49.614141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 22:10:49.614231 ==
5871 22:10:49.614298
5872 22:10:49.614359
5873 22:10:49.614432 TX Vref Scan disable
5874 22:10:49.618436 == TX Byte 0 ==
5875 22:10:49.621622 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5876 22:10:49.625106 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5877 22:10:49.628621 == TX Byte 1 ==
5878 22:10:49.631752 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5879 22:10:49.635086 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5880 22:10:49.638619
5881 22:10:49.638707 [DATLAT]
5882 22:10:49.638817 Freq=933, CH1 RK1
5883 22:10:49.638897
5884 22:10:49.641700 DATLAT Default: 0xb
5885 22:10:49.641790 0, 0xFFFF, sum = 0
5886 22:10:49.645447 1, 0xFFFF, sum = 0
5887 22:10:49.645529 2, 0xFFFF, sum = 0
5888 22:10:49.648513 3, 0xFFFF, sum = 0
5889 22:10:49.648594 4, 0xFFFF, sum = 0
5890 22:10:49.651638 5, 0xFFFF, sum = 0
5891 22:10:49.651721 6, 0xFFFF, sum = 0
5892 22:10:49.655278 7, 0xFFFF, sum = 0
5893 22:10:49.658926 8, 0xFFFF, sum = 0
5894 22:10:49.659008 9, 0xFFFF, sum = 0
5895 22:10:49.659131 10, 0x0, sum = 1
5896 22:10:49.662042 11, 0x0, sum = 2
5897 22:10:49.662125 12, 0x0, sum = 3
5898 22:10:49.665284 13, 0x0, sum = 4
5899 22:10:49.665366 best_step = 11
5900 22:10:49.665430
5901 22:10:49.665490 ==
5902 22:10:49.668946 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 22:10:49.675350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 22:10:49.675447 ==
5905 22:10:49.675542 RX Vref Scan: 0
5906 22:10:49.675632
5907 22:10:49.678742 RX Vref 0 -> 0, step: 1
5908 22:10:49.678822
5909 22:10:49.682433 RX Delay -61 -> 252, step: 4
5910 22:10:49.685155 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5911 22:10:49.688701 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5912 22:10:49.695787 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5913 22:10:49.699071 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5914 22:10:49.702310 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5915 22:10:49.705823 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5916 22:10:49.709063 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5917 22:10:49.712038 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5918 22:10:49.718824 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5919 22:10:49.722392 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5920 22:10:49.725492 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5921 22:10:49.729188 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5922 22:10:49.732081 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5923 22:10:49.735787 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5924 22:10:49.742253 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5925 22:10:49.745470 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5926 22:10:49.745551 ==
5927 22:10:49.749111 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 22:10:49.752237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 22:10:49.752320 ==
5930 22:10:49.755428 DQS Delay:
5931 22:10:49.755510 DQS0 = 0, DQS1 = 0
5932 22:10:49.755575 DQM Delay:
5933 22:10:49.759118 DQM0 = 95, DQM1 = 90
5934 22:10:49.759202 DQ Delay:
5935 22:10:49.762243 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5936 22:10:49.765701 DQ4 =98, DQ5 =106, DQ6 =102, DQ7 =90
5937 22:10:49.769187 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =82
5938 22:10:49.772305 DQ12 =98, DQ13 =98, DQ14 =100, DQ15 =98
5939 22:10:49.772385
5940 22:10:49.772479
5941 22:10:49.782233 [DQSOSCAuto] RK1, (LSB)MR18= 0xd16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5942 22:10:49.782315 CH1 RK1: MR19=505, MR18=D16
5943 22:10:49.789324 CH1_RK1: MR19=0x505, MR18=0xD16, DQSOSC=414, MR23=63, INC=63, DEC=42
5944 22:10:49.792358 [RxdqsGatingPostProcess] freq 933
5945 22:10:49.799577 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5946 22:10:49.802660 best DQS0 dly(2T, 0.5T) = (0, 10)
5947 22:10:49.805876 best DQS1 dly(2T, 0.5T) = (0, 10)
5948 22:10:49.809402 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5949 22:10:49.812844 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5950 22:10:49.812925 best DQS0 dly(2T, 0.5T) = (0, 10)
5951 22:10:49.816074 best DQS1 dly(2T, 0.5T) = (0, 10)
5952 22:10:49.819473 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5953 22:10:49.822693 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5954 22:10:49.826406 Pre-setting of DQS Precalculation
5955 22:10:49.832610 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5956 22:10:49.839154 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5957 22:10:49.845865 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5958 22:10:49.845946
5959 22:10:49.846010
5960 22:10:49.849378 [Calibration Summary] 1866 Mbps
5961 22:10:49.849460 CH 0, Rank 0
5962 22:10:49.853007 SW Impedance : PASS
5963 22:10:49.856147 DUTY Scan : NO K
5964 22:10:49.856228 ZQ Calibration : PASS
5965 22:10:49.859242 Jitter Meter : NO K
5966 22:10:49.862759 CBT Training : PASS
5967 22:10:49.862854 Write leveling : PASS
5968 22:10:49.865926 RX DQS gating : PASS
5969 22:10:49.866007 RX DQ/DQS(RDDQC) : PASS
5970 22:10:49.869553 TX DQ/DQS : PASS
5971 22:10:49.873305 RX DATLAT : PASS
5972 22:10:49.873386 RX DQ/DQS(Engine): PASS
5973 22:10:49.876313 TX OE : NO K
5974 22:10:49.876393 All Pass.
5975 22:10:49.876457
5976 22:10:49.879233 CH 0, Rank 1
5977 22:10:49.879314 SW Impedance : PASS
5978 22:10:49.882974 DUTY Scan : NO K
5979 22:10:49.886226 ZQ Calibration : PASS
5980 22:10:49.886307 Jitter Meter : NO K
5981 22:10:49.889578 CBT Training : PASS
5982 22:10:49.892907 Write leveling : PASS
5983 22:10:49.892988 RX DQS gating : PASS
5984 22:10:49.896046 RX DQ/DQS(RDDQC) : PASS
5985 22:10:49.899559 TX DQ/DQS : PASS
5986 22:10:49.899640 RX DATLAT : PASS
5987 22:10:49.903022 RX DQ/DQS(Engine): PASS
5988 22:10:49.903106 TX OE : NO K
5989 22:10:49.906169 All Pass.
5990 22:10:49.906249
5991 22:10:49.906313 CH 1, Rank 0
5992 22:10:49.909789 SW Impedance : PASS
5993 22:10:49.909871 DUTY Scan : NO K
5994 22:10:49.912986 ZQ Calibration : PASS
5995 22:10:49.916305 Jitter Meter : NO K
5996 22:10:49.916387 CBT Training : PASS
5997 22:10:49.919774 Write leveling : PASS
5998 22:10:49.922754 RX DQS gating : PASS
5999 22:10:49.922835 RX DQ/DQS(RDDQC) : PASS
6000 22:10:49.926060 TX DQ/DQS : PASS
6001 22:10:49.929543 RX DATLAT : PASS
6002 22:10:49.929624 RX DQ/DQS(Engine): PASS
6003 22:10:49.932641 TX OE : NO K
6004 22:10:49.932748 All Pass.
6005 22:10:49.932813
6006 22:10:49.936350 CH 1, Rank 1
6007 22:10:49.936448 SW Impedance : PASS
6008 22:10:49.939891 DUTY Scan : NO K
6009 22:10:49.942935 ZQ Calibration : PASS
6010 22:10:49.943015 Jitter Meter : NO K
6011 22:10:49.946491 CBT Training : PASS
6012 22:10:49.946572 Write leveling : PASS
6013 22:10:49.949656 RX DQS gating : PASS
6014 22:10:49.953218 RX DQ/DQS(RDDQC) : PASS
6015 22:10:49.953300 TX DQ/DQS : PASS
6016 22:10:49.956290 RX DATLAT : PASS
6017 22:10:49.959928 RX DQ/DQS(Engine): PASS
6018 22:10:49.960008 TX OE : NO K
6019 22:10:49.962901 All Pass.
6020 22:10:49.962982
6021 22:10:49.963046 DramC Write-DBI off
6022 22:10:49.966381 PER_BANK_REFRESH: Hybrid Mode
6023 22:10:49.966462 TX_TRACKING: ON
6024 22:10:49.976370 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6025 22:10:49.979589 [FAST_K] Save calibration result to emmc
6026 22:10:49.983056 dramc_set_vcore_voltage set vcore to 650000
6027 22:10:49.986444 Read voltage for 400, 6
6028 22:10:49.986525 Vio18 = 0
6029 22:10:49.990052 Vcore = 650000
6030 22:10:49.990132 Vdram = 0
6031 22:10:49.990197 Vddq = 0
6032 22:10:49.992975 Vmddr = 0
6033 22:10:49.996159 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6034 22:10:50.003006 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6035 22:10:50.003088 MEM_TYPE=3, freq_sel=20
6036 22:10:50.006703 sv_algorithm_assistance_LP4_800
6037 22:10:50.009692 ============ PULL DRAM RESETB DOWN ============
6038 22:10:50.016386 ========== PULL DRAM RESETB DOWN end =========
6039 22:10:50.019837 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6040 22:10:50.023080 ===================================
6041 22:10:50.026731 LPDDR4 DRAM CONFIGURATION
6042 22:10:50.030060 ===================================
6043 22:10:50.030141 EX_ROW_EN[0] = 0x0
6044 22:10:50.033357 EX_ROW_EN[1] = 0x0
6045 22:10:50.033454 LP4Y_EN = 0x0
6046 22:10:50.036644 WORK_FSP = 0x0
6047 22:10:50.036768 WL = 0x2
6048 22:10:50.040121 RL = 0x2
6049 22:10:50.040208 BL = 0x2
6050 22:10:50.043199 RPST = 0x0
6051 22:10:50.043296 RD_PRE = 0x0
6052 22:10:50.046950 WR_PRE = 0x1
6053 22:10:50.049996 WR_PST = 0x0
6054 22:10:50.050076 DBI_WR = 0x0
6055 22:10:50.053712 DBI_RD = 0x0
6056 22:10:50.053792 OTF = 0x1
6057 22:10:50.056675 ===================================
6058 22:10:50.060303 ===================================
6059 22:10:50.060384 ANA top config
6060 22:10:50.063352 ===================================
6061 22:10:50.067059 DLL_ASYNC_EN = 0
6062 22:10:50.070195 ALL_SLAVE_EN = 1
6063 22:10:50.073410 NEW_RANK_MODE = 1
6064 22:10:50.073491 DLL_IDLE_MODE = 1
6065 22:10:50.076675 LP45_APHY_COMB_EN = 1
6066 22:10:50.080573 TX_ODT_DIS = 1
6067 22:10:50.083380 NEW_8X_MODE = 1
6068 22:10:50.087008 ===================================
6069 22:10:50.090216 ===================================
6070 22:10:50.093962 data_rate = 800
6071 22:10:50.094043 CKR = 1
6072 22:10:50.097015 DQ_P2S_RATIO = 4
6073 22:10:50.100122 ===================================
6074 22:10:50.103819 CA_P2S_RATIO = 4
6075 22:10:50.106847 DQ_CA_OPEN = 0
6076 22:10:50.110238 DQ_SEMI_OPEN = 1
6077 22:10:50.113359 CA_SEMI_OPEN = 1
6078 22:10:50.113441 CA_FULL_RATE = 0
6079 22:10:50.117114 DQ_CKDIV4_EN = 0
6080 22:10:50.120173 CA_CKDIV4_EN = 1
6081 22:10:50.123274 CA_PREDIV_EN = 0
6082 22:10:50.126932 PH8_DLY = 0
6083 22:10:50.130386 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6084 22:10:50.130467 DQ_AAMCK_DIV = 0
6085 22:10:50.133657 CA_AAMCK_DIV = 0
6086 22:10:50.137099 CA_ADMCK_DIV = 4
6087 22:10:50.140153 DQ_TRACK_CA_EN = 0
6088 22:10:50.143329 CA_PICK = 800
6089 22:10:50.147168 CA_MCKIO = 400
6090 22:10:50.150386 MCKIO_SEMI = 400
6091 22:10:50.150499 PLL_FREQ = 3016
6092 22:10:50.153384 DQ_UI_PI_RATIO = 32
6093 22:10:50.157077 CA_UI_PI_RATIO = 32
6094 22:10:50.160139 ===================================
6095 22:10:50.163665 ===================================
6096 22:10:50.167455 memory_type:LPDDR4
6097 22:10:50.167551 GP_NUM : 10
6098 22:10:50.170318 SRAM_EN : 1
6099 22:10:50.174194 MD32_EN : 0
6100 22:10:50.176882 ===================================
6101 22:10:50.176968 [ANA_INIT] >>>>>>>>>>>>>>
6102 22:10:50.180801 <<<<<< [CONFIGURE PHASE]: ANA_TX
6103 22:10:50.184010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6104 22:10:50.187084 ===================================
6105 22:10:50.190101 data_rate = 800,PCW = 0X7400
6106 22:10:50.193704 ===================================
6107 22:10:50.196656 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6108 22:10:50.203880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 22:10:50.213477 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 22:10:50.216802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6111 22:10:50.223823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6112 22:10:50.226728 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6113 22:10:50.226810 [ANA_INIT] flow start
6114 22:10:50.230140 [ANA_INIT] PLL >>>>>>>>
6115 22:10:50.233419 [ANA_INIT] PLL <<<<<<<<
6116 22:10:50.233499 [ANA_INIT] MIDPI >>>>>>>>
6117 22:10:50.236813 [ANA_INIT] MIDPI <<<<<<<<
6118 22:10:50.240606 [ANA_INIT] DLL >>>>>>>>
6119 22:10:50.240713 [ANA_INIT] flow end
6120 22:10:50.243874 ============ LP4 DIFF to SE enter ============
6121 22:10:50.250007 ============ LP4 DIFF to SE exit ============
6122 22:10:50.250092 [ANA_INIT] <<<<<<<<<<<<<
6123 22:10:50.253611 [Flow] Enable top DCM control >>>>>
6124 22:10:50.256994 [Flow] Enable top DCM control <<<<<
6125 22:10:50.260225 Enable DLL master slave shuffle
6126 22:10:50.266978 ==============================================================
6127 22:10:50.267063 Gating Mode config
6128 22:10:50.273715 ==============================================================
6129 22:10:50.276812 Config description:
6130 22:10:50.286852 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6131 22:10:50.293603 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6132 22:10:50.296633 SELPH_MODE 0: By rank 1: By Phase
6133 22:10:50.303253 ==============================================================
6134 22:10:50.306772 GAT_TRACK_EN = 0
6135 22:10:50.306849 RX_GATING_MODE = 2
6136 22:10:50.309902 RX_GATING_TRACK_MODE = 2
6137 22:10:50.313328 SELPH_MODE = 1
6138 22:10:50.316597 PICG_EARLY_EN = 1
6139 22:10:50.319933 VALID_LAT_VALUE = 1
6140 22:10:50.327107 ==============================================================
6141 22:10:50.330208 Enter into Gating configuration >>>>
6142 22:10:50.333600 Exit from Gating configuration <<<<
6143 22:10:50.336993 Enter into DVFS_PRE_config >>>>>
6144 22:10:50.346900 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6145 22:10:50.350013 Exit from DVFS_PRE_config <<<<<
6146 22:10:50.353518 Enter into PICG configuration >>>>
6147 22:10:50.356861 Exit from PICG configuration <<<<
6148 22:10:50.360259 [RX_INPUT] configuration >>>>>
6149 22:10:50.360340 [RX_INPUT] configuration <<<<<
6150 22:10:50.366843 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6151 22:10:50.373435 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6152 22:10:50.377257 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 22:10:50.383561 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 22:10:50.390178 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6155 22:10:50.396767 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6156 22:10:50.400372 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6157 22:10:50.403354 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6158 22:10:50.410325 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6159 22:10:50.413434 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6160 22:10:50.416540 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6161 22:10:50.423510 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6162 22:10:50.426536 ===================================
6163 22:10:50.426616 LPDDR4 DRAM CONFIGURATION
6164 22:10:50.430069 ===================================
6165 22:10:50.433740 EX_ROW_EN[0] = 0x0
6166 22:10:50.433825 EX_ROW_EN[1] = 0x0
6167 22:10:50.436717 LP4Y_EN = 0x0
6168 22:10:50.436799 WORK_FSP = 0x0
6169 22:10:50.440084 WL = 0x2
6170 22:10:50.440169 RL = 0x2
6171 22:10:50.443336 BL = 0x2
6172 22:10:50.443441 RPST = 0x0
6173 22:10:50.446807 RD_PRE = 0x0
6174 22:10:50.450133 WR_PRE = 0x1
6175 22:10:50.450217 WR_PST = 0x0
6176 22:10:50.453681 DBI_WR = 0x0
6177 22:10:50.453766 DBI_RD = 0x0
6178 22:10:50.457069 OTF = 0x1
6179 22:10:50.460190 ===================================
6180 22:10:50.463292 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6181 22:10:50.466842 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6182 22:10:50.470364 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 22:10:50.473866 ===================================
6184 22:10:50.476875 LPDDR4 DRAM CONFIGURATION
6185 22:10:50.480321 ===================================
6186 22:10:50.483649 EX_ROW_EN[0] = 0x10
6187 22:10:50.483756 EX_ROW_EN[1] = 0x0
6188 22:10:50.487035 LP4Y_EN = 0x0
6189 22:10:50.487139 WORK_FSP = 0x0
6190 22:10:50.490158 WL = 0x2
6191 22:10:50.490264 RL = 0x2
6192 22:10:50.493519 BL = 0x2
6193 22:10:50.493624 RPST = 0x0
6194 22:10:50.496659 RD_PRE = 0x0
6195 22:10:50.496772 WR_PRE = 0x1
6196 22:10:50.500085 WR_PST = 0x0
6197 22:10:50.500192 DBI_WR = 0x0
6198 22:10:50.503387 DBI_RD = 0x0
6199 22:10:50.503497 OTF = 0x1
6200 22:10:50.506993 ===================================
6201 22:10:50.513991 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6202 22:10:50.518241 nWR fixed to 30
6203 22:10:50.521856 [ModeRegInit_LP4] CH0 RK0
6204 22:10:50.521940 [ModeRegInit_LP4] CH0 RK1
6205 22:10:50.524739 [ModeRegInit_LP4] CH1 RK0
6206 22:10:50.528250 [ModeRegInit_LP4] CH1 RK1
6207 22:10:50.528335 match AC timing 19
6208 22:10:50.534912 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6209 22:10:50.538003 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6210 22:10:50.541463 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6211 22:10:50.548145 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6212 22:10:50.551332 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6213 22:10:50.551418 ==
6214 22:10:50.555109 Dram Type= 6, Freq= 0, CH_0, rank 0
6215 22:10:50.558422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 22:10:50.558508 ==
6217 22:10:50.564673 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 22:10:50.571455 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6219 22:10:50.574764 [CA 0] Center 36 (8~64) winsize 57
6220 22:10:50.578369 [CA 1] Center 36 (8~64) winsize 57
6221 22:10:50.581584 [CA 2] Center 36 (8~64) winsize 57
6222 22:10:50.581668 [CA 3] Center 36 (8~64) winsize 57
6223 22:10:50.584812 [CA 4] Center 36 (8~64) winsize 57
6224 22:10:50.587987 [CA 5] Center 36 (8~64) winsize 57
6225 22:10:50.588072
6226 22:10:50.591547 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6227 22:10:50.594632
6228 22:10:50.598079 [CATrainingPosCal] consider 1 rank data
6229 22:10:50.598164 u2DelayCellTimex100 = 270/100 ps
6230 22:10:50.604776 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 22:10:50.608412 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 22:10:50.611414 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 22:10:50.615186 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 22:10:50.618666 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 22:10:50.621577 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 22:10:50.621689
6237 22:10:50.624679 CA PerBit enable=1, Macro0, CA PI delay=36
6238 22:10:50.624789
6239 22:10:50.628167 [CBTSetCACLKResult] CA Dly = 36
6240 22:10:50.631845 CS Dly: 1 (0~32)
6241 22:10:50.631929 ==
6242 22:10:50.635331 Dram Type= 6, Freq= 0, CH_0, rank 1
6243 22:10:50.638441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 22:10:50.638526 ==
6245 22:10:50.641931 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 22:10:50.648651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6247 22:10:50.651631 [CA 0] Center 36 (8~64) winsize 57
6248 22:10:50.655592 [CA 1] Center 36 (8~64) winsize 57
6249 22:10:50.659055 [CA 2] Center 36 (8~64) winsize 57
6250 22:10:50.661655 [CA 3] Center 36 (8~64) winsize 57
6251 22:10:50.664911 [CA 4] Center 36 (8~64) winsize 57
6252 22:10:50.668541 [CA 5] Center 36 (8~64) winsize 57
6253 22:10:50.668626
6254 22:10:50.671837 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6255 22:10:50.671920
6256 22:10:50.675105 [CATrainingPosCal] consider 2 rank data
6257 22:10:50.678692 u2DelayCellTimex100 = 270/100 ps
6258 22:10:50.681874 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 22:10:50.685583 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 22:10:50.688553 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 22:10:50.691975 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 22:10:50.695320 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 22:10:50.698963 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 22:10:50.699067
6265 22:10:50.705503 CA PerBit enable=1, Macro0, CA PI delay=36
6266 22:10:50.705605
6267 22:10:50.708528 [CBTSetCACLKResult] CA Dly = 36
6268 22:10:50.708611 CS Dly: 1 (0~32)
6269 22:10:50.708741
6270 22:10:50.711746 ----->DramcWriteLeveling(PI) begin...
6271 22:10:50.711830 ==
6272 22:10:50.715263 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 22:10:50.718922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 22:10:50.719007 ==
6275 22:10:50.722427 Write leveling (Byte 0): 40 => 8
6276 22:10:50.725391 Write leveling (Byte 1): 32 => 0
6277 22:10:50.728928 DramcWriteLeveling(PI) end<-----
6278 22:10:50.729013
6279 22:10:50.729097 ==
6280 22:10:50.731918 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 22:10:50.735590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 22:10:50.738617 ==
6283 22:10:50.738731 [Gating] SW mode calibration
6284 22:10:50.745480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6285 22:10:50.751911 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6286 22:10:50.755500 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 22:10:50.761971 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 22:10:50.765135 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 22:10:50.768592 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 22:10:50.775745 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 22:10:50.778845 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 22:10:50.782114 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 22:10:50.789035 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 22:10:50.792569 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 22:10:50.795312 Total UI for P1: 0, mck2ui 16
6296 22:10:50.798952 best dqsien dly found for B0: ( 0, 14, 24)
6297 22:10:50.802047 Total UI for P1: 0, mck2ui 16
6298 22:10:50.805778 best dqsien dly found for B1: ( 0, 14, 24)
6299 22:10:50.808887 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6300 22:10:50.812090 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6301 22:10:50.812173
6302 22:10:50.815697 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 22:10:50.818649 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 22:10:50.822356 [Gating] SW calibration Done
6305 22:10:50.822463 ==
6306 22:10:50.826047 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 22:10:50.828982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 22:10:50.829055 ==
6309 22:10:50.832567 RX Vref Scan: 0
6310 22:10:50.832663
6311 22:10:50.832764 RX Vref 0 -> 0, step: 1
6312 22:10:50.835643
6313 22:10:50.835721 RX Delay -410 -> 252, step: 16
6314 22:10:50.842413 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6315 22:10:50.845920 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6316 22:10:50.848971 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6317 22:10:50.852511 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6318 22:10:50.859277 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6319 22:10:50.862222 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6320 22:10:50.865783 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6321 22:10:50.869183 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6322 22:10:50.875844 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6323 22:10:50.879086 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6324 22:10:50.882318 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6325 22:10:50.885807 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6326 22:10:50.892502 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6327 22:10:50.895897 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6328 22:10:50.898978 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6329 22:10:50.902491 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6330 22:10:50.905930 ==
6331 22:10:50.906005 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 22:10:50.912497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 22:10:50.912576 ==
6334 22:10:50.912639 DQS Delay:
6335 22:10:50.915518 DQS0 = 35, DQS1 = 51
6336 22:10:50.915595 DQM Delay:
6337 22:10:50.919033 DQM0 = 8, DQM1 = 11
6338 22:10:50.919116 DQ Delay:
6339 22:10:50.922488 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6340 22:10:50.925775 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6341 22:10:50.925862 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6342 22:10:50.932280 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6343 22:10:50.932358
6344 22:10:50.932422
6345 22:10:50.932480 ==
6346 22:10:50.935941 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 22:10:50.939577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 22:10:50.939651 ==
6349 22:10:50.939720
6350 22:10:50.939779
6351 22:10:50.942315 TX Vref Scan disable
6352 22:10:50.942385 == TX Byte 0 ==
6353 22:10:50.945616 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 22:10:50.952872 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 22:10:50.952949 == TX Byte 1 ==
6356 22:10:50.955972 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6357 22:10:50.962601 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6358 22:10:50.962684 ==
6359 22:10:50.966157 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 22:10:50.969319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 22:10:50.969398 ==
6362 22:10:50.969461
6363 22:10:50.969518
6364 22:10:50.972185 TX Vref Scan disable
6365 22:10:50.972269 == TX Byte 0 ==
6366 22:10:50.979157 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 22:10:50.982105 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 22:10:50.982185 == TX Byte 1 ==
6369 22:10:50.989127 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6370 22:10:50.992792 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6371 22:10:50.992914
6372 22:10:50.992978 [DATLAT]
6373 22:10:50.995619 Freq=400, CH0 RK0
6374 22:10:50.995719
6375 22:10:50.995807 DATLAT Default: 0xf
6376 22:10:50.999215 0, 0xFFFF, sum = 0
6377 22:10:50.999312 1, 0xFFFF, sum = 0
6378 22:10:51.002941 2, 0xFFFF, sum = 0
6379 22:10:51.003043 3, 0xFFFF, sum = 0
6380 22:10:51.005892 4, 0xFFFF, sum = 0
6381 22:10:51.005963 5, 0xFFFF, sum = 0
6382 22:10:51.009539 6, 0xFFFF, sum = 0
6383 22:10:51.009608 7, 0xFFFF, sum = 0
6384 22:10:51.012408 8, 0xFFFF, sum = 0
6385 22:10:51.012478 9, 0xFFFF, sum = 0
6386 22:10:51.015714 10, 0xFFFF, sum = 0
6387 22:10:51.015790 11, 0xFFFF, sum = 0
6388 22:10:51.019205 12, 0xFFFF, sum = 0
6389 22:10:51.019305 13, 0x0, sum = 1
6390 22:10:51.022315 14, 0x0, sum = 2
6391 22:10:51.022416 15, 0x0, sum = 3
6392 22:10:51.025811 16, 0x0, sum = 4
6393 22:10:51.025906 best_step = 14
6394 22:10:51.025992
6395 22:10:51.026075 ==
6396 22:10:51.029017 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 22:10:51.036262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 22:10:51.036380 ==
6399 22:10:51.036523 RX Vref Scan: 1
6400 22:10:51.036624
6401 22:10:51.038979 RX Vref 0 -> 0, step: 1
6402 22:10:51.039080
6403 22:10:51.042235 RX Delay -343 -> 252, step: 8
6404 22:10:51.042334
6405 22:10:51.045769 Set Vref, RX VrefLevel [Byte0]: 53
6406 22:10:51.048774 [Byte1]: 50
6407 22:10:51.048849
6408 22:10:51.052402 Final RX Vref Byte 0 = 53 to rank0
6409 22:10:51.055580 Final RX Vref Byte 1 = 50 to rank0
6410 22:10:51.059196 Final RX Vref Byte 0 = 53 to rank1
6411 22:10:51.062221 Final RX Vref Byte 1 = 50 to rank1==
6412 22:10:51.065665 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 22:10:51.069429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 22:10:51.072349 ==
6415 22:10:51.072432 DQS Delay:
6416 22:10:51.072517 DQS0 = 44, DQS1 = 60
6417 22:10:51.075417 DQM Delay:
6418 22:10:51.075499 DQM0 = 12, DQM1 = 15
6419 22:10:51.079032 DQ Delay:
6420 22:10:51.082570 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6421 22:10:51.082688 DQ4 =16, DQ5 =0, DQ6 =20, DQ7 =20
6422 22:10:51.085351 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6423 22:10:51.089177 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6424 22:10:51.089260
6425 22:10:51.089344
6426 22:10:51.098999 [DQSOSCAuto] RK0, (LSB)MR18= 0x8958, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6427 22:10:51.102554 CH0 RK0: MR19=C0C, MR18=8958
6428 22:10:51.108807 CH0_RK0: MR19=0xC0C, MR18=0x8958, DQSOSC=392, MR23=63, INC=384, DEC=256
6429 22:10:51.108887 ==
6430 22:10:51.112860 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 22:10:51.115865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 22:10:51.115944 ==
6433 22:10:51.118948 [Gating] SW mode calibration
6434 22:10:51.125639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6435 22:10:51.129264 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6436 22:10:51.135727 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 22:10:51.139143 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 22:10:51.142265 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 22:10:51.149078 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 22:10:51.152593 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 22:10:51.156058 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 22:10:51.162553 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 22:10:51.166249 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 22:10:51.169367 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 22:10:51.172985 Total UI for P1: 0, mck2ui 16
6446 22:10:51.176165 best dqsien dly found for B0: ( 0, 14, 24)
6447 22:10:51.179756 Total UI for P1: 0, mck2ui 16
6448 22:10:51.182730 best dqsien dly found for B1: ( 0, 14, 24)
6449 22:10:51.186328 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6450 22:10:51.189194 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6451 22:10:51.189276
6452 22:10:51.192577 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 22:10:51.199331 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 22:10:51.199414 [Gating] SW calibration Done
6455 22:10:51.199499 ==
6456 22:10:51.202749 Dram Type= 6, Freq= 0, CH_0, rank 1
6457 22:10:51.209327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 22:10:51.209413 ==
6459 22:10:51.209477 RX Vref Scan: 0
6460 22:10:51.209535
6461 22:10:51.213002 RX Vref 0 -> 0, step: 1
6462 22:10:51.213129
6463 22:10:51.215884 RX Delay -410 -> 252, step: 16
6464 22:10:51.219636 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6465 22:10:51.222905 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6466 22:10:51.229634 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6467 22:10:51.232870 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6468 22:10:51.236091 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6469 22:10:51.239579 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6470 22:10:51.242646 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6471 22:10:51.249697 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6472 22:10:51.252910 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6473 22:10:51.256268 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6474 22:10:51.259822 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6475 22:10:51.266140 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6476 22:10:51.269865 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6477 22:10:51.272883 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6478 22:10:51.276503 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6479 22:10:51.283190 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6480 22:10:51.283269 ==
6481 22:10:51.286843 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 22:10:51.289913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 22:10:51.289997 ==
6484 22:10:51.290074 DQS Delay:
6485 22:10:51.292970 DQS0 = 43, DQS1 = 51
6486 22:10:51.293050 DQM Delay:
6487 22:10:51.296590 DQM0 = 11, DQM1 = 10
6488 22:10:51.296713 DQ Delay:
6489 22:10:51.300118 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6490 22:10:51.303214 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6491 22:10:51.306206 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6492 22:10:51.309820 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6493 22:10:51.309903
6494 22:10:51.309970
6495 22:10:51.310035 ==
6496 22:10:51.312847 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 22:10:51.316475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 22:10:51.316566 ==
6499 22:10:51.316631
6500 22:10:51.316714
6501 22:10:51.319544 TX Vref Scan disable
6502 22:10:51.319630 == TX Byte 0 ==
6503 22:10:51.326442 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6504 22:10:51.329801 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6505 22:10:51.329882 == TX Byte 1 ==
6506 22:10:51.336258 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6507 22:10:51.339477 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6508 22:10:51.339559 ==
6509 22:10:51.343118 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 22:10:51.346629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 22:10:51.346707 ==
6512 22:10:51.346778
6513 22:10:51.346841
6514 22:10:51.349805 TX Vref Scan disable
6515 22:10:51.353216 == TX Byte 0 ==
6516 22:10:51.356208 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6517 22:10:51.359660 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6518 22:10:51.359743 == TX Byte 1 ==
6519 22:10:51.366330 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6520 22:10:51.369839 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6521 22:10:51.369958
6522 22:10:51.370056 [DATLAT]
6523 22:10:51.372834 Freq=400, CH0 RK1
6524 22:10:51.372936
6525 22:10:51.373042 DATLAT Default: 0xe
6526 22:10:51.376757 0, 0xFFFF, sum = 0
6527 22:10:51.376858 1, 0xFFFF, sum = 0
6528 22:10:51.379827 2, 0xFFFF, sum = 0
6529 22:10:51.379939 3, 0xFFFF, sum = 0
6530 22:10:51.383475 4, 0xFFFF, sum = 0
6531 22:10:51.383588 5, 0xFFFF, sum = 0
6532 22:10:51.386347 6, 0xFFFF, sum = 0
6533 22:10:51.386418 7, 0xFFFF, sum = 0
6534 22:10:51.390167 8, 0xFFFF, sum = 0
6535 22:10:51.390281 9, 0xFFFF, sum = 0
6536 22:10:51.392928 10, 0xFFFF, sum = 0
6537 22:10:51.396189 11, 0xFFFF, sum = 0
6538 22:10:51.396300 12, 0xFFFF, sum = 0
6539 22:10:51.399713 13, 0x0, sum = 1
6540 22:10:51.399811 14, 0x0, sum = 2
6541 22:10:51.399918 15, 0x0, sum = 3
6542 22:10:51.403411 16, 0x0, sum = 4
6543 22:10:51.403502 best_step = 14
6544 22:10:51.403565
6545 22:10:51.406313 ==
6546 22:10:51.406409 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 22:10:51.412797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 22:10:51.412874 ==
6549 22:10:51.412942 RX Vref Scan: 0
6550 22:10:51.413003
6551 22:10:51.416367 RX Vref 0 -> 0, step: 1
6552 22:10:51.416481
6553 22:10:51.419572 RX Delay -343 -> 252, step: 8
6554 22:10:51.426645 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6555 22:10:51.429571 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6556 22:10:51.433069 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6557 22:10:51.436294 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6558 22:10:51.443063 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6559 22:10:51.446363 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6560 22:10:51.449726 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6561 22:10:51.453249 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6562 22:10:51.460204 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6563 22:10:51.463163 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6564 22:10:51.466352 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6565 22:10:51.470119 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6566 22:10:51.476383 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6567 22:10:51.479896 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6568 22:10:51.482965 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6569 22:10:51.486706 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6570 22:10:51.489688 ==
6571 22:10:51.493463 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 22:10:51.496542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 22:10:51.496621 ==
6574 22:10:51.496748 DQS Delay:
6575 22:10:51.499982 DQS0 = 48, DQS1 = 60
6576 22:10:51.500056 DQM Delay:
6577 22:10:51.503284 DQM0 = 12, DQM1 = 13
6578 22:10:51.503360 DQ Delay:
6579 22:10:51.506804 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6580 22:10:51.509794 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =16
6581 22:10:51.513446 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6582 22:10:51.516869 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6583 22:10:51.516976
6584 22:10:51.517042
6585 22:10:51.522985 [DQSOSCAuto] RK1, (LSB)MR18= 0x9363, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6586 22:10:51.526723 CH0 RK1: MR19=C0C, MR18=9363
6587 22:10:51.532971 CH0_RK1: MR19=0xC0C, MR18=0x9363, DQSOSC=391, MR23=63, INC=386, DEC=257
6588 22:10:51.536761 [RxdqsGatingPostProcess] freq 400
6589 22:10:51.539949 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6590 22:10:51.543346 best DQS0 dly(2T, 0.5T) = (0, 10)
6591 22:10:51.546406 best DQS1 dly(2T, 0.5T) = (0, 10)
6592 22:10:51.550053 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6593 22:10:51.553544 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6594 22:10:51.556726 best DQS0 dly(2T, 0.5T) = (0, 10)
6595 22:10:51.559868 best DQS1 dly(2T, 0.5T) = (0, 10)
6596 22:10:51.563087 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6597 22:10:51.566775 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6598 22:10:51.569703 Pre-setting of DQS Precalculation
6599 22:10:51.573342 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6600 22:10:51.573441 ==
6601 22:10:51.576286 Dram Type= 6, Freq= 0, CH_1, rank 0
6602 22:10:51.583356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 22:10:51.583440 ==
6604 22:10:51.586622 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 22:10:51.593390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6606 22:10:51.596353 [CA 0] Center 36 (8~64) winsize 57
6607 22:10:51.599964 [CA 1] Center 36 (8~64) winsize 57
6608 22:10:51.603031 [CA 2] Center 36 (8~64) winsize 57
6609 22:10:51.606656 [CA 3] Center 36 (8~64) winsize 57
6610 22:10:51.609726 [CA 4] Center 36 (8~64) winsize 57
6611 22:10:51.613154 [CA 5] Center 36 (8~64) winsize 57
6612 22:10:51.613237
6613 22:10:51.616380 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6614 22:10:51.616463
6615 22:10:51.619755 [CATrainingPosCal] consider 1 rank data
6616 22:10:51.623489 u2DelayCellTimex100 = 270/100 ps
6617 22:10:51.626761 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 22:10:51.629943 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 22:10:51.632951 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 22:10:51.636542 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 22:10:51.640314 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 22:10:51.643092 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 22:10:51.643193
6624 22:10:51.649846 CA PerBit enable=1, Macro0, CA PI delay=36
6625 22:10:51.649929
6626 22:10:51.650014 [CBTSetCACLKResult] CA Dly = 36
6627 22:10:51.653200 CS Dly: 1 (0~32)
6628 22:10:51.653314 ==
6629 22:10:51.656736 Dram Type= 6, Freq= 0, CH_1, rank 1
6630 22:10:51.660085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 22:10:51.660177 ==
6632 22:10:51.666651 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 22:10:51.673409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6634 22:10:51.676816 [CA 0] Center 36 (8~64) winsize 57
6635 22:10:51.680188 [CA 1] Center 36 (8~64) winsize 57
6636 22:10:51.683011 [CA 2] Center 36 (8~64) winsize 57
6637 22:10:51.683151 [CA 3] Center 36 (8~64) winsize 57
6638 22:10:51.686553 [CA 4] Center 36 (8~64) winsize 57
6639 22:10:51.689738 [CA 5] Center 36 (8~64) winsize 57
6640 22:10:51.689835
6641 22:10:51.693143 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6642 22:10:51.696949
6643 22:10:51.700092 [CATrainingPosCal] consider 2 rank data
6644 22:10:51.700165 u2DelayCellTimex100 = 270/100 ps
6645 22:10:51.706753 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 22:10:51.709715 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 22:10:51.713280 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 22:10:51.717018 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 22:10:51.719918 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 22:10:51.723616 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 22:10:51.723735
6652 22:10:51.726505 CA PerBit enable=1, Macro0, CA PI delay=36
6653 22:10:51.726587
6654 22:10:51.730201 [CBTSetCACLKResult] CA Dly = 36
6655 22:10:51.733570 CS Dly: 1 (0~32)
6656 22:10:51.733669
6657 22:10:51.736734 ----->DramcWriteLeveling(PI) begin...
6658 22:10:51.736833 ==
6659 22:10:51.739868 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 22:10:51.743562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 22:10:51.743646 ==
6662 22:10:51.746586 Write leveling (Byte 0): 40 => 8
6663 22:10:51.750127 Write leveling (Byte 1): 40 => 8
6664 22:10:51.753416 DramcWriteLeveling(PI) end<-----
6665 22:10:51.753490
6666 22:10:51.753552 ==
6667 22:10:51.756773 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 22:10:51.760262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 22:10:51.760341 ==
6670 22:10:51.763720 [Gating] SW mode calibration
6671 22:10:51.770451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6672 22:10:51.776733 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6673 22:10:51.780210 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6674 22:10:51.783381 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6675 22:10:51.786729 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 22:10:51.793402 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 22:10:51.796522 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 22:10:51.800066 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 22:10:51.807056 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 22:10:51.810070 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 22:10:51.813697 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 22:10:51.816897 Total UI for P1: 0, mck2ui 16
6683 22:10:51.820455 best dqsien dly found for B0: ( 0, 14, 24)
6684 22:10:51.824229 Total UI for P1: 0, mck2ui 16
6685 22:10:51.827015 best dqsien dly found for B1: ( 0, 14, 24)
6686 22:10:51.830649 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6687 22:10:51.833810 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6688 22:10:51.833891
6689 22:10:51.840760 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 22:10:51.843806 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 22:10:51.843915 [Gating] SW calibration Done
6692 22:10:51.847409 ==
6693 22:10:51.850494 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 22:10:51.854159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 22:10:51.854241 ==
6696 22:10:51.854306 RX Vref Scan: 0
6697 22:10:51.854366
6698 22:10:51.857189 RX Vref 0 -> 0, step: 1
6699 22:10:51.857273
6700 22:10:51.860369 RX Delay -410 -> 252, step: 16
6701 22:10:51.863677 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6702 22:10:51.867236 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6703 22:10:51.873857 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6704 22:10:51.877135 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6705 22:10:51.880781 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6706 22:10:51.884105 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6707 22:10:51.890759 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6708 22:10:51.894122 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6709 22:10:51.897375 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6710 22:10:51.900444 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6711 22:10:51.907144 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6712 22:10:51.910703 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6713 22:10:51.914125 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6714 22:10:51.917102 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6715 22:10:51.924376 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6716 22:10:51.927242 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6717 22:10:51.927322 ==
6718 22:10:51.930870 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 22:10:51.933996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 22:10:51.934076 ==
6721 22:10:51.937208 DQS Delay:
6722 22:10:51.937288 DQS0 = 43, DQS1 = 59
6723 22:10:51.937350 DQM Delay:
6724 22:10:51.940760 DQM0 = 12, DQM1 = 17
6725 22:10:51.940839 DQ Delay:
6726 22:10:51.944574 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6727 22:10:51.947414 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6728 22:10:51.950714 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6729 22:10:51.953844 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6730 22:10:51.953923
6731 22:10:51.953986
6732 22:10:51.954044 ==
6733 22:10:51.957518 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 22:10:51.961136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 22:10:51.961216 ==
6736 22:10:51.964051
6737 22:10:51.964129
6738 22:10:51.964191 TX Vref Scan disable
6739 22:10:51.967577 == TX Byte 0 ==
6740 22:10:51.970681 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 22:10:51.974220 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 22:10:51.977643 == TX Byte 1 ==
6743 22:10:51.980560 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 22:10:51.984119 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 22:10:51.984197 ==
6746 22:10:51.987251 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 22:10:51.991034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 22:10:51.994454 ==
6749 22:10:51.994530
6750 22:10:51.994592
6751 22:10:51.994650 TX Vref Scan disable
6752 22:10:51.997473 == TX Byte 0 ==
6753 22:10:52.001123 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 22:10:52.003880 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 22:10:52.007254 == TX Byte 1 ==
6756 22:10:52.010928 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 22:10:52.014241 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 22:10:52.014321
6759 22:10:52.014384 [DATLAT]
6760 22:10:52.017351 Freq=400, CH1 RK0
6761 22:10:52.017425
6762 22:10:52.020521 DATLAT Default: 0xf
6763 22:10:52.020602 0, 0xFFFF, sum = 0
6764 22:10:52.024160 1, 0xFFFF, sum = 0
6765 22:10:52.024240 2, 0xFFFF, sum = 0
6766 22:10:52.027695 3, 0xFFFF, sum = 0
6767 22:10:52.027792 4, 0xFFFF, sum = 0
6768 22:10:52.030738 5, 0xFFFF, sum = 0
6769 22:10:52.030821 6, 0xFFFF, sum = 0
6770 22:10:52.033872 7, 0xFFFF, sum = 0
6771 22:10:52.033957 8, 0xFFFF, sum = 0
6772 22:10:52.037393 9, 0xFFFF, sum = 0
6773 22:10:52.037469 10, 0xFFFF, sum = 0
6774 22:10:52.040583 11, 0xFFFF, sum = 0
6775 22:10:52.040698 12, 0xFFFF, sum = 0
6776 22:10:52.044092 13, 0x0, sum = 1
6777 22:10:52.044172 14, 0x0, sum = 2
6778 22:10:52.047227 15, 0x0, sum = 3
6779 22:10:52.047306 16, 0x0, sum = 4
6780 22:10:52.050838 best_step = 14
6781 22:10:52.050918
6782 22:10:52.050979 ==
6783 22:10:52.053879 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 22:10:52.057637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 22:10:52.057716 ==
6786 22:10:52.057780 RX Vref Scan: 1
6787 22:10:52.060775
6788 22:10:52.060856 RX Vref 0 -> 0, step: 1
6789 22:10:52.060924
6790 22:10:52.064307 RX Delay -359 -> 252, step: 8
6791 22:10:52.064378
6792 22:10:52.067921 Set Vref, RX VrefLevel [Byte0]: 57
6793 22:10:52.070793 [Byte1]: 50
6794 22:10:52.075093
6795 22:10:52.078436 Final RX Vref Byte 0 = 57 to rank0
6796 22:10:52.078515 Final RX Vref Byte 1 = 50 to rank0
6797 22:10:52.081615 Final RX Vref Byte 0 = 57 to rank1
6798 22:10:52.084970 Final RX Vref Byte 1 = 50 to rank1==
6799 22:10:52.088381 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 22:10:52.094825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 22:10:52.094908 ==
6802 22:10:52.094971 DQS Delay:
6803 22:10:52.095031 DQS0 = 48, DQS1 = 60
6804 22:10:52.098537 DQM Delay:
6805 22:10:52.098615 DQM0 = 12, DQM1 = 12
6806 22:10:52.101738 DQ Delay:
6807 22:10:52.105222 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6808 22:10:52.105301 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6809 22:10:52.108912 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6810 22:10:52.111695 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6811 22:10:52.111800
6812 22:10:52.111889
6813 22:10:52.121972 [DQSOSCAuto] RK0, (LSB)MR18= 0x9138, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
6814 22:10:52.125224 CH1 RK0: MR19=C0C, MR18=9138
6815 22:10:52.131710 CH1_RK0: MR19=0xC0C, MR18=0x9138, DQSOSC=391, MR23=63, INC=386, DEC=257
6816 22:10:52.131809 ==
6817 22:10:52.135070 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 22:10:52.138299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 22:10:52.138378 ==
6820 22:10:52.141889 [Gating] SW mode calibration
6821 22:10:52.148632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6822 22:10:52.151539 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6823 22:10:52.158284 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 22:10:52.161707 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6825 22:10:52.165159 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 22:10:52.171837 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 22:10:52.174872 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 22:10:52.178553 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 22:10:52.185194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 22:10:52.188612 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 22:10:52.191635 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 22:10:52.195514 Total UI for P1: 0, mck2ui 16
6833 22:10:52.198389 best dqsien dly found for B0: ( 0, 14, 24)
6834 22:10:52.201973 Total UI for P1: 0, mck2ui 16
6835 22:10:52.205286 best dqsien dly found for B1: ( 0, 14, 24)
6836 22:10:52.208835 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6837 22:10:52.212143 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6838 22:10:52.212252
6839 22:10:52.215279 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 22:10:52.222022 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 22:10:52.222116 [Gating] SW calibration Done
6842 22:10:52.222181 ==
6843 22:10:52.225567 Dram Type= 6, Freq= 0, CH_1, rank 1
6844 22:10:52.231836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 22:10:52.231952 ==
6846 22:10:52.232051 RX Vref Scan: 0
6847 22:10:52.232116
6848 22:10:52.235377 RX Vref 0 -> 0, step: 1
6849 22:10:52.235446
6850 22:10:52.238752 RX Delay -410 -> 252, step: 16
6851 22:10:52.242173 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6852 22:10:52.245280 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6853 22:10:52.252230 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6854 22:10:52.255120 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6855 22:10:52.258808 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6856 22:10:52.261763 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6857 22:10:52.268650 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6858 22:10:52.272187 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6859 22:10:52.275435 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6860 22:10:52.278809 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6861 22:10:52.285251 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6862 22:10:52.288899 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6863 22:10:52.291814 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6864 22:10:52.295214 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6865 22:10:52.301677 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6866 22:10:52.305531 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6867 22:10:52.305621 ==
6868 22:10:52.308573 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 22:10:52.311996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 22:10:52.312077 ==
6871 22:10:52.315229 DQS Delay:
6872 22:10:52.315307 DQS0 = 43, DQS1 = 59
6873 22:10:52.315379 DQM Delay:
6874 22:10:52.318841 DQM0 = 10, DQM1 = 18
6875 22:10:52.318935 DQ Delay:
6876 22:10:52.322379 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6877 22:10:52.325348 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6878 22:10:52.328768 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6879 22:10:52.332139 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6880 22:10:52.332219
6881 22:10:52.332287
6882 22:10:52.332381 ==
6883 22:10:52.335647 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 22:10:52.338750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 22:10:52.338838 ==
6886 22:10:52.338928
6887 22:10:52.342090
6888 22:10:52.342162 TX Vref Scan disable
6889 22:10:52.345624 == TX Byte 0 ==
6890 22:10:52.348430 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6891 22:10:52.351880 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6892 22:10:52.355399 == TX Byte 1 ==
6893 22:10:52.358476 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6894 22:10:52.362187 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6895 22:10:52.362285 ==
6896 22:10:52.365631 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 22:10:52.368615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 22:10:52.368728 ==
6899 22:10:52.368818
6900 22:10:52.372370
6901 22:10:52.372468 TX Vref Scan disable
6902 22:10:52.375393 == TX Byte 0 ==
6903 22:10:52.379122 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6904 22:10:52.382260 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6905 22:10:52.385520 == TX Byte 1 ==
6906 22:10:52.389092 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6907 22:10:52.392255 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6908 22:10:52.392351
6909 22:10:52.392448 [DATLAT]
6910 22:10:52.395771 Freq=400, CH1 RK1
6911 22:10:52.395857
6912 22:10:52.395916 DATLAT Default: 0xe
6913 22:10:52.398842 0, 0xFFFF, sum = 0
6914 22:10:52.398944 1, 0xFFFF, sum = 0
6915 22:10:52.402358 2, 0xFFFF, sum = 0
6916 22:10:52.402429 3, 0xFFFF, sum = 0
6917 22:10:52.405761 4, 0xFFFF, sum = 0
6918 22:10:52.405833 5, 0xFFFF, sum = 0
6919 22:10:52.409191 6, 0xFFFF, sum = 0
6920 22:10:52.412198 7, 0xFFFF, sum = 0
6921 22:10:52.412287 8, 0xFFFF, sum = 0
6922 22:10:52.415484 9, 0xFFFF, sum = 0
6923 22:10:52.415599 10, 0xFFFF, sum = 0
6924 22:10:52.419105 11, 0xFFFF, sum = 0
6925 22:10:52.419227 12, 0xFFFF, sum = 0
6926 22:10:52.421999 13, 0x0, sum = 1
6927 22:10:52.422071 14, 0x0, sum = 2
6928 22:10:52.425873 15, 0x0, sum = 3
6929 22:10:52.425953 16, 0x0, sum = 4
6930 22:10:52.426016 best_step = 14
6931 22:10:52.428607
6932 22:10:52.428726 ==
6933 22:10:52.432201 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 22:10:52.435646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 22:10:52.435732 ==
6936 22:10:52.435796 RX Vref Scan: 0
6937 22:10:52.435855
6938 22:10:52.439414 RX Vref 0 -> 0, step: 1
6939 22:10:52.439517
6940 22:10:52.442396 RX Delay -359 -> 252, step: 8
6941 22:10:52.449163 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6942 22:10:52.452616 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6943 22:10:52.455991 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6944 22:10:52.459036 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6945 22:10:52.465698 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6946 22:10:52.469375 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6947 22:10:52.472300 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6948 22:10:52.476049 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6949 22:10:52.482656 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6950 22:10:52.485745 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6951 22:10:52.489249 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6952 22:10:52.492534 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6953 22:10:52.499610 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6954 22:10:52.502756 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6955 22:10:52.506377 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6956 22:10:52.509346 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6957 22:10:52.512761 ==
6958 22:10:52.512832 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 22:10:52.519501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 22:10:52.519581 ==
6961 22:10:52.519644 DQS Delay:
6962 22:10:52.523031 DQS0 = 52, DQS1 = 56
6963 22:10:52.523098 DQM Delay:
6964 22:10:52.526293 DQM0 = 12, DQM1 = 9
6965 22:10:52.526383 DQ Delay:
6966 22:10:52.529432 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6967 22:10:52.533672 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6968 22:10:52.533742 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6969 22:10:52.536324 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6970 22:10:52.539563
6971 22:10:52.539642
6972 22:10:52.546415 [DQSOSCAuto] RK1, (LSB)MR18= 0x7890, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
6973 22:10:52.549903 CH1 RK1: MR19=C0C, MR18=7890
6974 22:10:52.556510 CH1_RK1: MR19=0xC0C, MR18=0x7890, DQSOSC=391, MR23=63, INC=386, DEC=257
6975 22:10:52.559791 [RxdqsGatingPostProcess] freq 400
6976 22:10:52.563134 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6977 22:10:52.566901 best DQS0 dly(2T, 0.5T) = (0, 10)
6978 22:10:52.569696 best DQS1 dly(2T, 0.5T) = (0, 10)
6979 22:10:52.573430 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6980 22:10:52.576414 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6981 22:10:52.580131 best DQS0 dly(2T, 0.5T) = (0, 10)
6982 22:10:52.583014 best DQS1 dly(2T, 0.5T) = (0, 10)
6983 22:10:52.586629 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6984 22:10:52.589673 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6985 22:10:52.593389 Pre-setting of DQS Precalculation
6986 22:10:52.596181 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6987 22:10:52.603414 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6988 22:10:52.610052 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6989 22:10:52.613184
6990 22:10:52.613267
6991 22:10:52.613331 [Calibration Summary] 800 Mbps
6992 22:10:52.616208 CH 0, Rank 0
6993 22:10:52.616286 SW Impedance : PASS
6994 22:10:52.619511 DUTY Scan : NO K
6995 22:10:52.623046 ZQ Calibration : PASS
6996 22:10:52.623147 Jitter Meter : NO K
6997 22:10:52.626642 CBT Training : PASS
6998 22:10:52.629901 Write leveling : PASS
6999 22:10:52.629985 RX DQS gating : PASS
7000 22:10:52.633187 RX DQ/DQS(RDDQC) : PASS
7001 22:10:52.636710 TX DQ/DQS : PASS
7002 22:10:52.636811 RX DATLAT : PASS
7003 22:10:52.640320 RX DQ/DQS(Engine): PASS
7004 22:10:52.640400 TX OE : NO K
7005 22:10:52.643014 All Pass.
7006 22:10:52.643115
7007 22:10:52.643178 CH 0, Rank 1
7008 22:10:52.646843 SW Impedance : PASS
7009 22:10:52.646916 DUTY Scan : NO K
7010 22:10:52.650126 ZQ Calibration : PASS
7011 22:10:52.653134 Jitter Meter : NO K
7012 22:10:52.653215 CBT Training : PASS
7013 22:10:52.656775 Write leveling : NO K
7014 22:10:52.659739 RX DQS gating : PASS
7015 22:10:52.659819 RX DQ/DQS(RDDQC) : PASS
7016 22:10:52.663410 TX DQ/DQS : PASS
7017 22:10:52.666727 RX DATLAT : PASS
7018 22:10:52.666830 RX DQ/DQS(Engine): PASS
7019 22:10:52.670463 TX OE : NO K
7020 22:10:52.670570 All Pass.
7021 22:10:52.670670
7022 22:10:52.673145 CH 1, Rank 0
7023 22:10:52.673216 SW Impedance : PASS
7024 22:10:52.676633 DUTY Scan : NO K
7025 22:10:52.679677 ZQ Calibration : PASS
7026 22:10:52.679747 Jitter Meter : NO K
7027 22:10:52.683408 CBT Training : PASS
7028 22:10:52.683489 Write leveling : PASS
7029 22:10:52.686959 RX DQS gating : PASS
7030 22:10:52.689962 RX DQ/DQS(RDDQC) : PASS
7031 22:10:52.690043 TX DQ/DQS : PASS
7032 22:10:52.693559 RX DATLAT : PASS
7033 22:10:52.696555 RX DQ/DQS(Engine): PASS
7034 22:10:52.696674 TX OE : NO K
7035 22:10:52.700148 All Pass.
7036 22:10:52.700221
7037 22:10:52.700317 CH 1, Rank 1
7038 22:10:52.703170 SW Impedance : PASS
7039 22:10:52.703265 DUTY Scan : NO K
7040 22:10:52.707113 ZQ Calibration : PASS
7041 22:10:52.710213 Jitter Meter : NO K
7042 22:10:52.710288 CBT Training : PASS
7043 22:10:52.713713 Write leveling : NO K
7044 22:10:52.716696 RX DQS gating : PASS
7045 22:10:52.716803 RX DQ/DQS(RDDQC) : PASS
7046 22:10:52.720251 TX DQ/DQS : PASS
7047 22:10:52.723269 RX DATLAT : PASS
7048 22:10:52.723350 RX DQ/DQS(Engine): PASS
7049 22:10:52.726890 TX OE : NO K
7050 22:10:52.726971 All Pass.
7051 22:10:52.727051
7052 22:10:52.729825 DramC Write-DBI off
7053 22:10:52.733403 PER_BANK_REFRESH: Hybrid Mode
7054 22:10:52.733484 TX_TRACKING: ON
7055 22:10:52.743516 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7056 22:10:52.746741 [FAST_K] Save calibration result to emmc
7057 22:10:52.750274 dramc_set_vcore_voltage set vcore to 725000
7058 22:10:52.750355 Read voltage for 1600, 0
7059 22:10:52.753825 Vio18 = 0
7060 22:10:52.753911 Vcore = 725000
7061 22:10:52.754006 Vdram = 0
7062 22:10:52.756893 Vddq = 0
7063 22:10:52.757000 Vmddr = 0
7064 22:10:52.760313 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7065 22:10:52.766941 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7066 22:10:52.770118 MEM_TYPE=3, freq_sel=13
7067 22:10:52.773561 sv_algorithm_assistance_LP4_3733
7068 22:10:52.776776 ============ PULL DRAM RESETB DOWN ============
7069 22:10:52.780127 ========== PULL DRAM RESETB DOWN end =========
7070 22:10:52.787067 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7071 22:10:52.790054 ===================================
7072 22:10:52.790134 LPDDR4 DRAM CONFIGURATION
7073 22:10:52.793711 ===================================
7074 22:10:52.796797 EX_ROW_EN[0] = 0x0
7075 22:10:52.796877 EX_ROW_EN[1] = 0x0
7076 22:10:52.800542 LP4Y_EN = 0x0
7077 22:10:52.800639 WORK_FSP = 0x1
7078 22:10:52.803601 WL = 0x5
7079 22:10:52.803680 RL = 0x5
7080 22:10:52.807105 BL = 0x2
7081 22:10:52.807188 RPST = 0x0
7082 22:10:52.810151 RD_PRE = 0x0
7083 22:10:52.813570 WR_PRE = 0x1
7084 22:10:52.813649 WR_PST = 0x1
7085 22:10:52.816893 DBI_WR = 0x0
7086 22:10:52.816972 DBI_RD = 0x0
7087 22:10:52.820267 OTF = 0x1
7088 22:10:52.824063 ===================================
7089 22:10:52.827002 ===================================
7090 22:10:52.827082 ANA top config
7091 22:10:52.830593 ===================================
7092 22:10:52.833587 DLL_ASYNC_EN = 0
7093 22:10:52.833667 ALL_SLAVE_EN = 0
7094 22:10:52.837232 NEW_RANK_MODE = 1
7095 22:10:52.840336 DLL_IDLE_MODE = 1
7096 22:10:52.843815 LP45_APHY_COMB_EN = 1
7097 22:10:52.847194 TX_ODT_DIS = 0
7098 22:10:52.847273 NEW_8X_MODE = 1
7099 22:10:52.850553 ===================================
7100 22:10:52.853744 ===================================
7101 22:10:52.857140 data_rate = 3200
7102 22:10:52.860677 CKR = 1
7103 22:10:52.863870 DQ_P2S_RATIO = 8
7104 22:10:52.867281 ===================================
7105 22:10:52.870805 CA_P2S_RATIO = 8
7106 22:10:52.870884 DQ_CA_OPEN = 0
7107 22:10:52.873704 DQ_SEMI_OPEN = 0
7108 22:10:52.877587 CA_SEMI_OPEN = 0
7109 22:10:52.880399 CA_FULL_RATE = 0
7110 22:10:52.883912 DQ_CKDIV4_EN = 0
7111 22:10:52.887396 CA_CKDIV4_EN = 0
7112 22:10:52.887475 CA_PREDIV_EN = 0
7113 22:10:52.890768 PH8_DLY = 12
7114 22:10:52.894012 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7115 22:10:52.897413 DQ_AAMCK_DIV = 4
7116 22:10:52.900460 CA_AAMCK_DIV = 4
7117 22:10:52.904111 CA_ADMCK_DIV = 4
7118 22:10:52.904189 DQ_TRACK_CA_EN = 0
7119 22:10:52.907659 CA_PICK = 1600
7120 22:10:52.910826 CA_MCKIO = 1600
7121 22:10:52.913733 MCKIO_SEMI = 0
7122 22:10:52.917345 PLL_FREQ = 3068
7123 22:10:52.920507 DQ_UI_PI_RATIO = 32
7124 22:10:52.923753 CA_UI_PI_RATIO = 0
7125 22:10:52.927116 ===================================
7126 22:10:52.930769 ===================================
7127 22:10:52.930849 memory_type:LPDDR4
7128 22:10:52.934023 GP_NUM : 10
7129 22:10:52.937705 SRAM_EN : 1
7130 22:10:52.937783 MD32_EN : 0
7131 22:10:52.940844 ===================================
7132 22:10:52.943715 [ANA_INIT] >>>>>>>>>>>>>>
7133 22:10:52.947553 <<<<<< [CONFIGURE PHASE]: ANA_TX
7134 22:10:52.951070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7135 22:10:52.953983 ===================================
7136 22:10:52.957464 data_rate = 3200,PCW = 0X7600
7137 22:10:52.957544 ===================================
7138 22:10:52.963934 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7139 22:10:52.967784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 22:10:52.973892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 22:10:52.977075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7142 22:10:52.980726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7143 22:10:52.984146 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7144 22:10:52.987420 [ANA_INIT] flow start
7145 22:10:52.990405 [ANA_INIT] PLL >>>>>>>>
7146 22:10:52.990476 [ANA_INIT] PLL <<<<<<<<
7147 22:10:52.994249 [ANA_INIT] MIDPI >>>>>>>>
7148 22:10:52.997177 [ANA_INIT] MIDPI <<<<<<<<
7149 22:10:52.997282 [ANA_INIT] DLL >>>>>>>>
7150 22:10:53.000619 [ANA_INIT] DLL <<<<<<<<
7151 22:10:53.003926 [ANA_INIT] flow end
7152 22:10:53.007478 ============ LP4 DIFF to SE enter ============
7153 22:10:53.010728 ============ LP4 DIFF to SE exit ============
7154 22:10:53.013848 [ANA_INIT] <<<<<<<<<<<<<
7155 22:10:53.017556 [Flow] Enable top DCM control >>>>>
7156 22:10:53.020474 [Flow] Enable top DCM control <<<<<
7157 22:10:53.023994 Enable DLL master slave shuffle
7158 22:10:53.027597 ==============================================================
7159 22:10:53.030776 Gating Mode config
7160 22:10:53.037230 ==============================================================
7161 22:10:53.037307 Config description:
7162 22:10:53.047676 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7163 22:10:53.054154 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7164 22:10:53.057074 SELPH_MODE 0: By rank 1: By Phase
7165 22:10:53.064159 ==============================================================
7166 22:10:53.067486 GAT_TRACK_EN = 1
7167 22:10:53.070661 RX_GATING_MODE = 2
7168 22:10:53.074118 RX_GATING_TRACK_MODE = 2
7169 22:10:53.077791 SELPH_MODE = 1
7170 22:10:53.080779 PICG_EARLY_EN = 1
7171 22:10:53.080860 VALID_LAT_VALUE = 1
7172 22:10:53.087374 ==============================================================
7173 22:10:53.090843 Enter into Gating configuration >>>>
7174 22:10:53.094214 Exit from Gating configuration <<<<
7175 22:10:53.097600 Enter into DVFS_PRE_config >>>>>
7176 22:10:53.107233 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7177 22:10:53.110912 Exit from DVFS_PRE_config <<<<<
7178 22:10:53.113848 Enter into PICG configuration >>>>
7179 22:10:53.117360 Exit from PICG configuration <<<<
7180 22:10:53.120504 [RX_INPUT] configuration >>>>>
7181 22:10:53.124206 [RX_INPUT] configuration <<<<<
7182 22:10:53.127313 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7183 22:10:53.134382 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7184 22:10:53.140938 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 22:10:53.147396 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 22:10:53.153876 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7187 22:10:53.157590 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7188 22:10:53.163834 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7189 22:10:53.167443 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7190 22:10:53.170505 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7191 22:10:53.174069 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7192 22:10:53.181171 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7193 22:10:53.184179 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7194 22:10:53.187742 ===================================
7195 22:10:53.191105 LPDDR4 DRAM CONFIGURATION
7196 22:10:53.194268 ===================================
7197 22:10:53.194375 EX_ROW_EN[0] = 0x0
7198 22:10:53.197503 EX_ROW_EN[1] = 0x0
7199 22:10:53.197576 LP4Y_EN = 0x0
7200 22:10:53.200412 WORK_FSP = 0x1
7201 22:10:53.200510 WL = 0x5
7202 22:10:53.204006 RL = 0x5
7203 22:10:53.204099 BL = 0x2
7204 22:10:53.207355 RPST = 0x0
7205 22:10:53.207452 RD_PRE = 0x0
7206 22:10:53.210601 WR_PRE = 0x1
7207 22:10:53.210709 WR_PST = 0x1
7208 22:10:53.214128 DBI_WR = 0x0
7209 22:10:53.214220 DBI_RD = 0x0
7210 22:10:53.217238 OTF = 0x1
7211 22:10:53.220878 ===================================
7212 22:10:53.224284 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7213 22:10:53.227460 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7214 22:10:53.234180 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 22:10:53.237207 ===================================
7216 22:10:53.237278 LPDDR4 DRAM CONFIGURATION
7217 22:10:53.240599 ===================================
7218 22:10:53.244029 EX_ROW_EN[0] = 0x10
7219 22:10:53.247300 EX_ROW_EN[1] = 0x0
7220 22:10:53.247410 LP4Y_EN = 0x0
7221 22:10:53.250979 WORK_FSP = 0x1
7222 22:10:53.251072 WL = 0x5
7223 22:10:53.254505 RL = 0x5
7224 22:10:53.254599 BL = 0x2
7225 22:10:53.257628 RPST = 0x0
7226 22:10:53.257767 RD_PRE = 0x0
7227 22:10:53.260617 WR_PRE = 0x1
7228 22:10:53.260736 WR_PST = 0x1
7229 22:10:53.264226 DBI_WR = 0x0
7230 22:10:53.264316 DBI_RD = 0x0
7231 22:10:53.267659 OTF = 0x1
7232 22:10:53.270851 ===================================
7233 22:10:53.278074 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7234 22:10:53.278171 ==
7235 22:10:53.280790 Dram Type= 6, Freq= 0, CH_0, rank 0
7236 22:10:53.284237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7237 22:10:53.284331 ==
7238 22:10:53.287920 [Duty_Offset_Calibration]
7239 22:10:53.287994 B0:2 B1:-1 CA:1
7240 22:10:53.288055
7241 22:10:53.290927 [DutyScan_Calibration_Flow] k_type=0
7242 22:10:53.300247
7243 22:10:53.300347 ==CLK 0==
7244 22:10:53.303616 Final CLK duty delay cell = -4
7245 22:10:53.307266 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7246 22:10:53.310403 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7247 22:10:53.313741 [-4] AVG Duty = 4937%(X100)
7248 22:10:53.313848
7249 22:10:53.317298 CH0 CLK Duty spec in!! Max-Min= 187%
7250 22:10:53.320378 [DutyScan_Calibration_Flow] ====Done====
7251 22:10:53.320478
7252 22:10:53.323971 [DutyScan_Calibration_Flow] k_type=1
7253 22:10:53.339959
7254 22:10:53.340075 ==DQS 0 ==
7255 22:10:53.343373 Final DQS duty delay cell = 0
7256 22:10:53.346946 [0] MAX Duty = 5125%(X100), DQS PI = 20
7257 22:10:53.349788 [0] MIN Duty = 5000%(X100), DQS PI = 14
7258 22:10:53.353118 [0] AVG Duty = 5062%(X100)
7259 22:10:53.353197
7260 22:10:53.353259 ==DQS 1 ==
7261 22:10:53.357141 Final DQS duty delay cell = -4
7262 22:10:53.360007 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7263 22:10:53.363488 [-4] MIN Duty = 5031%(X100), DQS PI = 8
7264 22:10:53.366572 [-4] AVG Duty = 5062%(X100)
7265 22:10:53.366651
7266 22:10:53.370041 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7267 22:10:53.370120
7268 22:10:53.373081 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7269 22:10:53.376701 [DutyScan_Calibration_Flow] ====Done====
7270 22:10:53.376793
7271 22:10:53.379732 [DutyScan_Calibration_Flow] k_type=3
7272 22:10:53.397235
7273 22:10:53.397314 ==DQM 0 ==
7274 22:10:53.400594 Final DQM duty delay cell = 0
7275 22:10:53.404295 [0] MAX Duty = 5000%(X100), DQS PI = 20
7276 22:10:53.407748 [0] MIN Duty = 4844%(X100), DQS PI = 8
7277 22:10:53.407847 [0] AVG Duty = 4922%(X100)
7278 22:10:53.410571
7279 22:10:53.410663 ==DQM 1 ==
7280 22:10:53.413973 Final DQM duty delay cell = 0
7281 22:10:53.417345 [0] MAX Duty = 5218%(X100), DQS PI = 58
7282 22:10:53.420565 [0] MIN Duty = 4969%(X100), DQS PI = 18
7283 22:10:53.420697 [0] AVG Duty = 5093%(X100)
7284 22:10:53.424072
7285 22:10:53.427816 CH0 DQM 0 Duty spec in!! Max-Min= 156%
7286 22:10:53.427895
7287 22:10:53.430588 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7288 22:10:53.434143 [DutyScan_Calibration_Flow] ====Done====
7289 22:10:53.434251
7290 22:10:53.437316 [DutyScan_Calibration_Flow] k_type=2
7291 22:10:53.454586
7292 22:10:53.454666 ==DQ 0 ==
7293 22:10:53.457656 Final DQ duty delay cell = 0
7294 22:10:53.460923 [0] MAX Duty = 5156%(X100), DQS PI = 40
7295 22:10:53.464574 [0] MIN Duty = 5031%(X100), DQS PI = 10
7296 22:10:53.464710 [0] AVG Duty = 5093%(X100)
7297 22:10:53.464788
7298 22:10:53.468077 ==DQ 1 ==
7299 22:10:53.471549 Final DQ duty delay cell = 0
7300 22:10:53.474954 [0] MAX Duty = 5000%(X100), DQS PI = 0
7301 22:10:53.477907 [0] MIN Duty = 4907%(X100), DQS PI = 42
7302 22:10:53.477987 [0] AVG Duty = 4953%(X100)
7303 22:10:53.478050
7304 22:10:53.481565 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7305 22:10:53.481635
7306 22:10:53.484528 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7307 22:10:53.488322 [DutyScan_Calibration_Flow] ====Done====
7308 22:10:53.491187 ==
7309 22:10:53.494738 Dram Type= 6, Freq= 0, CH_1, rank 0
7310 22:10:53.497810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7311 22:10:53.497885 ==
7312 22:10:53.501215 [Duty_Offset_Calibration]
7313 22:10:53.501291 B0:1 B1:1 CA:2
7314 22:10:53.501353
7315 22:10:53.504789 [DutyScan_Calibration_Flow] k_type=0
7316 22:10:53.514836
7317 22:10:53.514913 ==CLK 0==
7318 22:10:53.518317 Final CLK duty delay cell = 0
7319 22:10:53.521377 [0] MAX Duty = 5187%(X100), DQS PI = 24
7320 22:10:53.524322 [0] MIN Duty = 4938%(X100), DQS PI = 50
7321 22:10:53.524417 [0] AVG Duty = 5062%(X100)
7322 22:10:53.527749
7323 22:10:53.531064 CH1 CLK Duty spec in!! Max-Min= 249%
7324 22:10:53.534249 [DutyScan_Calibration_Flow] ====Done====
7325 22:10:53.534328
7326 22:10:53.537806 [DutyScan_Calibration_Flow] k_type=1
7327 22:10:53.554113
7328 22:10:53.554190 ==DQS 0 ==
7329 22:10:53.557708 Final DQS duty delay cell = 0
7330 22:10:53.561118 [0] MAX Duty = 5062%(X100), DQS PI = 20
7331 22:10:53.564581 [0] MIN Duty = 4813%(X100), DQS PI = 50
7332 22:10:53.564659 [0] AVG Duty = 4937%(X100)
7333 22:10:53.567924
7334 22:10:53.568020 ==DQS 1 ==
7335 22:10:53.571036 Final DQS duty delay cell = 0
7336 22:10:53.574140 [0] MAX Duty = 5031%(X100), DQS PI = 36
7337 22:10:53.577921 [0] MIN Duty = 4938%(X100), DQS PI = 14
7338 22:10:53.578032 [0] AVG Duty = 4984%(X100)
7339 22:10:53.581439
7340 22:10:53.584541 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7341 22:10:53.584638
7342 22:10:53.587936 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7343 22:10:53.590992 [DutyScan_Calibration_Flow] ====Done====
7344 22:10:53.591061
7345 22:10:53.594593 [DutyScan_Calibration_Flow] k_type=3
7346 22:10:53.611468
7347 22:10:53.611552 ==DQM 0 ==
7348 22:10:53.614729 Final DQM duty delay cell = 0
7349 22:10:53.617812 [0] MAX Duty = 5156%(X100), DQS PI = 20
7350 22:10:53.621218 [0] MIN Duty = 4844%(X100), DQS PI = 48
7351 22:10:53.624251 [0] AVG Duty = 5000%(X100)
7352 22:10:53.624331
7353 22:10:53.624393 ==DQM 1 ==
7354 22:10:53.627601 Final DQM duty delay cell = 0
7355 22:10:53.631276 [0] MAX Duty = 5156%(X100), DQS PI = 60
7356 22:10:53.634680 [0] MIN Duty = 4875%(X100), DQS PI = 20
7357 22:10:53.638012 [0] AVG Duty = 5015%(X100)
7358 22:10:53.638125
7359 22:10:53.640894 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7360 22:10:53.640972
7361 22:10:53.644548 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7362 22:10:53.647656 [DutyScan_Calibration_Flow] ====Done====
7363 22:10:53.647755
7364 22:10:53.650811 [DutyScan_Calibration_Flow] k_type=2
7365 22:10:53.668284
7366 22:10:53.668379 ==DQ 0 ==
7367 22:10:53.671663 Final DQ duty delay cell = 0
7368 22:10:53.675216 [0] MAX Duty = 5156%(X100), DQS PI = 20
7369 22:10:53.677879 [0] MIN Duty = 4907%(X100), DQS PI = 50
7370 22:10:53.678018 [0] AVG Duty = 5031%(X100)
7371 22:10:53.681519
7372 22:10:53.681586 ==DQ 1 ==
7373 22:10:53.685119 Final DQ duty delay cell = 0
7374 22:10:53.688237 [0] MAX Duty = 5093%(X100), DQS PI = 8
7375 22:10:53.691495 [0] MIN Duty = 5031%(X100), DQS PI = 0
7376 22:10:53.691610 [0] AVG Duty = 5062%(X100)
7377 22:10:53.691715
7378 22:10:53.695116 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7379 22:10:53.695181
7380 22:10:53.698186 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7381 22:10:53.701438 [DutyScan_Calibration_Flow] ====Done====
7382 22:10:53.707440 nWR fixed to 30
7383 22:10:53.710378 [ModeRegInit_LP4] CH0 RK0
7384 22:10:53.710457 [ModeRegInit_LP4] CH0 RK1
7385 22:10:53.713394 [ModeRegInit_LP4] CH1 RK0
7386 22:10:53.717150 [ModeRegInit_LP4] CH1 RK1
7387 22:10:53.717230 match AC timing 5
7388 22:10:53.723562 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7389 22:10:53.726753 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7390 22:10:53.730281 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7391 22:10:53.736678 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7392 22:10:53.740339 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7393 22:10:53.740448 [MiockJmeterHQA]
7394 22:10:53.743640
7395 22:10:53.743715 [DramcMiockJmeter] u1RxGatingPI = 0
7396 22:10:53.746979 0 : 4258, 4031
7397 22:10:53.747049 4 : 4365, 4140
7398 22:10:53.750428 8 : 4253, 4027
7399 22:10:53.750508 12 : 4252, 4027
7400 22:10:53.753452 16 : 4363, 4140
7401 22:10:53.753576 20 : 4252, 4027
7402 22:10:53.753654 24 : 4255, 4029
7403 22:10:53.756932 28 : 4253, 4026
7404 22:10:53.757013 32 : 4363, 4138
7405 22:10:53.760402 36 : 4363, 4137
7406 22:10:53.760482 40 : 4252, 4027
7407 22:10:53.763408 44 : 4253, 4026
7408 22:10:53.763488 48 : 4252, 4027
7409 22:10:53.766579 52 : 4252, 4027
7410 22:10:53.766659 56 : 4254, 4029
7411 22:10:53.766723 60 : 4363, 4137
7412 22:10:53.770150 64 : 4253, 4027
7413 22:10:53.770230 68 : 4252, 4027
7414 22:10:53.773251 72 : 4250, 4027
7415 22:10:53.773333 76 : 4252, 4029
7416 22:10:53.776680 80 : 4250, 4027
7417 22:10:53.776795 84 : 4360, 4138
7418 22:10:53.780139 88 : 4361, 4137
7419 22:10:53.780221 92 : 4250, 4027
7420 22:10:53.780286 96 : 4250, 3241
7421 22:10:53.783474 100 : 4250, 0
7422 22:10:53.783567 104 : 4250, 0
7423 22:10:53.787125 108 : 4252, 0
7424 22:10:53.787205 112 : 4250, 0
7425 22:10:53.787268 116 : 4250, 0
7426 22:10:53.790017 120 : 4360, 0
7427 22:10:53.790134 124 : 4250, 0
7428 22:10:53.790244 128 : 4250, 0
7429 22:10:53.793636 132 : 4361, 0
7430 22:10:53.793736 136 : 4360, 0
7431 22:10:53.796612 140 : 4363, 0
7432 22:10:53.796744 144 : 4250, 0
7433 22:10:53.796841 148 : 4250, 0
7434 22:10:53.799874 152 : 4250, 0
7435 22:10:53.799975 156 : 4250, 0
7436 22:10:53.803417 160 : 4250, 0
7437 22:10:53.803507 164 : 4250, 0
7438 22:10:53.803569 168 : 4252, 0
7439 22:10:53.806549 172 : 4250, 0
7440 22:10:53.806619 176 : 4250, 0
7441 22:10:53.810089 180 : 4253, 0
7442 22:10:53.810160 184 : 4361, 0
7443 22:10:53.810221 188 : 4360, 0
7444 22:10:53.813962 192 : 4363, 0
7445 22:10:53.814032 196 : 4250, 0
7446 22:10:53.814092 200 : 4250, 0
7447 22:10:53.816853 204 : 4250, 0
7448 22:10:53.816923 208 : 4250, 0
7449 22:10:53.819961 212 : 4250, 97
7450 22:10:53.820034 216 : 4250, 3680
7451 22:10:53.823625 220 : 4361, 4138
7452 22:10:53.823699 224 : 4250, 4027
7453 22:10:53.826602 228 : 4250, 4026
7454 22:10:53.826679 232 : 4363, 4140
7455 22:10:53.826741 236 : 4250, 4026
7456 22:10:53.830183 240 : 4250, 4027
7457 22:10:53.830253 244 : 4250, 4027
7458 22:10:53.833091 248 : 4250, 4027
7459 22:10:53.833162 252 : 4250, 4026
7460 22:10:53.836604 256 : 4250, 4027
7461 22:10:53.836737 260 : 4360, 4138
7462 22:10:53.840005 264 : 4250, 4027
7463 22:10:53.840077 268 : 4250, 4026
7464 22:10:53.843338 272 : 4361, 4137
7465 22:10:53.843444 276 : 4250, 4027
7466 22:10:53.846602 280 : 4250, 4027
7467 22:10:53.846701 284 : 4364, 4140
7468 22:10:53.850481 288 : 4250, 4026
7469 22:10:53.850579 292 : 4250, 4027
7470 22:10:53.850677 296 : 4250, 4027
7471 22:10:53.853414 300 : 4253, 4029
7472 22:10:53.853491 304 : 4250, 4026
7473 22:10:53.856628 308 : 4250, 4027
7474 22:10:53.856732 312 : 4360, 4138
7475 22:10:53.860255 316 : 4250, 4027
7476 22:10:53.860335 320 : 4250, 4026
7477 22:10:53.863788 324 : 4361, 4137
7478 22:10:53.863870 328 : 4250, 4027
7479 22:10:53.866695 332 : 4250, 3079
7480 22:10:53.866813 336 : 4364, 146
7481 22:10:53.866908
7482 22:10:53.870412 MIOCK jitter meter ch=0
7483 22:10:53.870517
7484 22:10:53.873345 1T = (336-100) = 236 dly cells
7485 22:10:53.876989 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7486 22:10:53.877094 ==
7487 22:10:53.880044 Dram Type= 6, Freq= 0, CH_0, rank 0
7488 22:10:53.887399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7489 22:10:53.887479 ==
7490 22:10:53.890169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7491 22:10:53.896786 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7492 22:10:53.900157 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7493 22:10:53.906739 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7494 22:10:53.914776 [CA 0] Center 44 (14~75) winsize 62
7495 22:10:53.917794 [CA 1] Center 44 (14~74) winsize 61
7496 22:10:53.921266 [CA 2] Center 39 (10~68) winsize 59
7497 22:10:53.924730 [CA 3] Center 38 (9~68) winsize 60
7498 22:10:53.927744 [CA 4] Center 37 (7~67) winsize 61
7499 22:10:53.931318 [CA 5] Center 37 (7~67) winsize 61
7500 22:10:53.931414
7501 22:10:53.934763 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7502 22:10:53.934869
7503 22:10:53.937893 [CATrainingPosCal] consider 1 rank data
7504 22:10:53.941148 u2DelayCellTimex100 = 275/100 ps
7505 22:10:53.944427 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7506 22:10:53.951076 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7507 22:10:53.954621 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7508 22:10:53.957830 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
7509 22:10:53.961553 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7510 22:10:53.964766 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7511 22:10:53.964850
7512 22:10:53.968049 CA PerBit enable=1, Macro0, CA PI delay=37
7513 22:10:53.968143
7514 22:10:53.971164 [CBTSetCACLKResult] CA Dly = 37
7515 22:10:53.974488 CS Dly: 11 (0~42)
7516 22:10:53.977865 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7517 22:10:53.981659 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7518 22:10:53.981761 ==
7519 22:10:53.984545 Dram Type= 6, Freq= 0, CH_0, rank 1
7520 22:10:53.988044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 22:10:53.988121 ==
7522 22:10:53.994673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7523 22:10:53.998456 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7524 22:10:54.004587 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7525 22:10:54.008214 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7526 22:10:54.017931 [CA 0] Center 44 (14~75) winsize 62
7527 22:10:54.021574 [CA 1] Center 44 (14~75) winsize 62
7528 22:10:54.025120 [CA 2] Center 40 (11~69) winsize 59
7529 22:10:54.028203 [CA 3] Center 39 (10~69) winsize 60
7530 22:10:54.031792 [CA 4] Center 38 (8~68) winsize 61
7531 22:10:54.034818 [CA 5] Center 37 (7~67) winsize 61
7532 22:10:54.034899
7533 22:10:54.038657 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7534 22:10:54.038734
7535 22:10:54.041555 [CATrainingPosCal] consider 2 rank data
7536 22:10:54.045184 u2DelayCellTimex100 = 275/100 ps
7537 22:10:54.048522 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7538 22:10:54.055264 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7539 22:10:54.058772 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7540 22:10:54.061561 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7541 22:10:54.065168 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7542 22:10:54.068123 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7543 22:10:54.068204
7544 22:10:54.071720 CA PerBit enable=1, Macro0, CA PI delay=37
7545 22:10:54.071825
7546 22:10:54.075261 [CBTSetCACLKResult] CA Dly = 37
7547 22:10:54.078563 CS Dly: 12 (0~44)
7548 22:10:54.081745 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7549 22:10:54.085051 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7550 22:10:54.085141
7551 22:10:54.088505 ----->DramcWriteLeveling(PI) begin...
7552 22:10:54.088616 ==
7553 22:10:54.091513 Dram Type= 6, Freq= 0, CH_0, rank 0
7554 22:10:54.094690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 22:10:54.098170 ==
7556 22:10:54.098246 Write leveling (Byte 0): 32 => 32
7557 22:10:54.101962 Write leveling (Byte 1): 28 => 28
7558 22:10:54.105248 DramcWriteLeveling(PI) end<-----
7559 22:10:54.105329
7560 22:10:54.105414 ==
7561 22:10:54.108343 Dram Type= 6, Freq= 0, CH_0, rank 0
7562 22:10:54.114802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7563 22:10:54.114886 ==
7564 22:10:54.114974 [Gating] SW mode calibration
7565 22:10:54.124989 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7566 22:10:54.128417 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7567 22:10:54.131456 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 22:10:54.138595 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 22:10:54.141702 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 22:10:54.144684 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 22:10:54.151833 1 4 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7572 22:10:54.155320 1 4 20 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7573 22:10:54.158161 1 4 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7574 22:10:54.165292 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 22:10:54.168113 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7576 22:10:54.171618 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7577 22:10:54.178210 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7578 22:10:54.181737 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7579 22:10:54.185278 1 5 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 0)
7580 22:10:54.191820 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7581 22:10:54.194961 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
7582 22:10:54.198363 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 22:10:54.205066 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 22:10:54.208215 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 22:10:54.211729 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 22:10:54.218724 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7587 22:10:54.221613 1 6 16 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
7588 22:10:54.225364 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7589 22:10:54.228572 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7590 22:10:54.235426 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 22:10:54.238808 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 22:10:54.241759 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7593 22:10:54.248503 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 22:10:54.252165 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 22:10:54.255246 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7596 22:10:54.262134 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7597 22:10:54.265213 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 22:10:54.268673 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 22:10:54.275439 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 22:10:54.278364 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 22:10:54.281937 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 22:10:54.288626 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 22:10:54.292179 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 22:10:54.295386 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 22:10:54.298945 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 22:10:54.305429 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 22:10:54.309222 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 22:10:54.312033 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 22:10:54.318859 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 22:10:54.322242 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 22:10:54.325456 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7612 22:10:54.332195 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7613 22:10:54.335633 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7614 22:10:54.338921 Total UI for P1: 0, mck2ui 16
7615 22:10:54.342070 best dqsien dly found for B0: ( 1, 9, 18)
7616 22:10:54.345373 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 22:10:54.348989 Total UI for P1: 0, mck2ui 16
7618 22:10:54.352023 best dqsien dly found for B1: ( 1, 9, 22)
7619 22:10:54.355705 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7620 22:10:54.358797 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7621 22:10:54.358876
7622 22:10:54.365876 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7623 22:10:54.368564 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7624 22:10:54.368693 [Gating] SW calibration Done
7625 22:10:54.372280 ==
7626 22:10:54.375246 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 22:10:54.378656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 22:10:54.378736 ==
7629 22:10:54.378799 RX Vref Scan: 0
7630 22:10:54.378857
7631 22:10:54.382224 RX Vref 0 -> 0, step: 1
7632 22:10:54.382346
7633 22:10:54.385228 RX Delay 0 -> 252, step: 8
7634 22:10:54.388870 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7635 22:10:54.392365 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7636 22:10:54.395421 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7637 22:10:54.401916 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7638 22:10:54.405554 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7639 22:10:54.408674 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7640 22:10:54.412255 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7641 22:10:54.415730 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7642 22:10:54.422401 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7643 22:10:54.425818 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7644 22:10:54.428762 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7645 22:10:54.432376 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7646 22:10:54.435786 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7647 22:10:54.442622 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7648 22:10:54.445996 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7649 22:10:54.449142 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7650 22:10:54.449221 ==
7651 22:10:54.452327 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 22:10:54.455894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 22:10:54.455999 ==
7654 22:10:54.458874 DQS Delay:
7655 22:10:54.458978 DQS0 = 0, DQS1 = 0
7656 22:10:54.459119 DQM Delay:
7657 22:10:54.462496 DQM0 = 132, DQM1 = 124
7658 22:10:54.462575 DQ Delay:
7659 22:10:54.466106 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7660 22:10:54.468959 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7661 22:10:54.475584 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =115
7662 22:10:54.479162 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7663 22:10:54.479241
7664 22:10:54.479303
7665 22:10:54.479361 ==
7666 22:10:54.482313 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 22:10:54.486091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 22:10:54.486170 ==
7669 22:10:54.486282
7670 22:10:54.486378
7671 22:10:54.488997 TX Vref Scan disable
7672 22:10:54.489102 == TX Byte 0 ==
7673 22:10:54.495417 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7674 22:10:54.499237 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7675 22:10:54.499316 == TX Byte 1 ==
7676 22:10:54.505664 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7677 22:10:54.508821 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7678 22:10:54.508926 ==
7679 22:10:54.512530 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 22:10:54.515567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 22:10:54.515648 ==
7682 22:10:54.531236
7683 22:10:54.534492 TX Vref early break, caculate TX vref
7684 22:10:54.537984 TX Vref=16, minBit 0, minWin=21, winSum=360
7685 22:10:54.541467 TX Vref=18, minBit 0, minWin=22, winSum=373
7686 22:10:54.544954 TX Vref=20, minBit 4, minWin=23, winSum=386
7687 22:10:54.548082 TX Vref=22, minBit 0, minWin=23, winSum=393
7688 22:10:54.551099 TX Vref=24, minBit 0, minWin=24, winSum=404
7689 22:10:54.558181 TX Vref=26, minBit 4, minWin=24, winSum=414
7690 22:10:54.561215 TX Vref=28, minBit 0, minWin=25, winSum=421
7691 22:10:54.564844 TX Vref=30, minBit 0, minWin=26, winSum=420
7692 22:10:54.568401 TX Vref=32, minBit 0, minWin=25, winSum=417
7693 22:10:54.571554 TX Vref=34, minBit 0, minWin=24, winSum=406
7694 22:10:54.574553 TX Vref=36, minBit 0, minWin=23, winSum=393
7695 22:10:54.581420 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 30
7696 22:10:54.581502
7697 22:10:54.584601 Final TX Range 0 Vref 30
7698 22:10:54.584736
7699 22:10:54.584799 ==
7700 22:10:54.587907 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 22:10:54.591555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 22:10:54.591651 ==
7703 22:10:54.591773
7704 22:10:54.591857
7705 22:10:54.594939 TX Vref Scan disable
7706 22:10:54.601763 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7707 22:10:54.601844 == TX Byte 0 ==
7708 22:10:54.604577 u2DelayCellOfst[0]=14 cells (4 PI)
7709 22:10:54.608264 u2DelayCellOfst[1]=21 cells (6 PI)
7710 22:10:54.611399 u2DelayCellOfst[2]=10 cells (3 PI)
7711 22:10:54.614957 u2DelayCellOfst[3]=14 cells (4 PI)
7712 22:10:54.618005 u2DelayCellOfst[4]=10 cells (3 PI)
7713 22:10:54.621552 u2DelayCellOfst[5]=0 cells (0 PI)
7714 22:10:54.624573 u2DelayCellOfst[6]=17 cells (5 PI)
7715 22:10:54.628309 u2DelayCellOfst[7]=17 cells (5 PI)
7716 22:10:54.631304 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7717 22:10:54.634486 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7718 22:10:54.638211 == TX Byte 1 ==
7719 22:10:54.638291 u2DelayCellOfst[8]=3 cells (1 PI)
7720 22:10:54.641663 u2DelayCellOfst[9]=0 cells (0 PI)
7721 22:10:54.644515 u2DelayCellOfst[10]=7 cells (2 PI)
7722 22:10:54.647992 u2DelayCellOfst[11]=3 cells (1 PI)
7723 22:10:54.651504 u2DelayCellOfst[12]=14 cells (4 PI)
7724 22:10:54.654419 u2DelayCellOfst[13]=14 cells (4 PI)
7725 22:10:54.657860 u2DelayCellOfst[14]=17 cells (5 PI)
7726 22:10:54.661025 u2DelayCellOfst[15]=10 cells (3 PI)
7727 22:10:54.664929 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7728 22:10:54.671461 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7729 22:10:54.671557 DramC Write-DBI on
7730 22:10:54.671619 ==
7731 22:10:54.674760 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 22:10:54.677924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 22:10:54.681548 ==
7734 22:10:54.681627
7735 22:10:54.681689
7736 22:10:54.681747 TX Vref Scan disable
7737 22:10:54.685088 == TX Byte 0 ==
7738 22:10:54.687884 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7739 22:10:54.691567 == TX Byte 1 ==
7740 22:10:54.694669 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7741 22:10:54.694749 DramC Write-DBI off
7742 22:10:54.698156
7743 22:10:54.698235 [DATLAT]
7744 22:10:54.698297 Freq=1600, CH0 RK0
7745 22:10:54.698355
7746 22:10:54.701361 DATLAT Default: 0xf
7747 22:10:54.701441 0, 0xFFFF, sum = 0
7748 22:10:54.704731 1, 0xFFFF, sum = 0
7749 22:10:54.704812 2, 0xFFFF, sum = 0
7750 22:10:54.708405 3, 0xFFFF, sum = 0
7751 22:10:54.708486 4, 0xFFFF, sum = 0
7752 22:10:54.711513 5, 0xFFFF, sum = 0
7753 22:10:54.715089 6, 0xFFFF, sum = 0
7754 22:10:54.715169 7, 0xFFFF, sum = 0
7755 22:10:54.718086 8, 0xFFFF, sum = 0
7756 22:10:54.718166 9, 0xFFFF, sum = 0
7757 22:10:54.721816 10, 0xFFFF, sum = 0
7758 22:10:54.721896 11, 0xFFFF, sum = 0
7759 22:10:54.724803 12, 0xFFFF, sum = 0
7760 22:10:54.724884 13, 0xFFFF, sum = 0
7761 22:10:54.728305 14, 0x0, sum = 1
7762 22:10:54.728385 15, 0x0, sum = 2
7763 22:10:54.731458 16, 0x0, sum = 3
7764 22:10:54.731537 17, 0x0, sum = 4
7765 22:10:54.735005 best_step = 15
7766 22:10:54.735083
7767 22:10:54.735145 ==
7768 22:10:54.737974 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 22:10:54.741639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 22:10:54.741718 ==
7771 22:10:54.741809 RX Vref Scan: 1
7772 22:10:54.741868
7773 22:10:54.745263 Set Vref Range= 24 -> 127
7774 22:10:54.745342
7775 22:10:54.748242 RX Vref 24 -> 127, step: 1
7776 22:10:54.748320
7777 22:10:54.751748 RX Delay 11 -> 252, step: 4
7778 22:10:54.751826
7779 22:10:54.754581 Set Vref, RX VrefLevel [Byte0]: 24
7780 22:10:54.757945 [Byte1]: 24
7781 22:10:54.758024
7782 22:10:54.761271 Set Vref, RX VrefLevel [Byte0]: 25
7783 22:10:54.764898 [Byte1]: 25
7784 22:10:54.765005
7785 22:10:54.768205 Set Vref, RX VrefLevel [Byte0]: 26
7786 22:10:54.771371 [Byte1]: 26
7787 22:10:54.775039
7788 22:10:54.775148 Set Vref, RX VrefLevel [Byte0]: 27
7789 22:10:54.778251 [Byte1]: 27
7790 22:10:54.782936
7791 22:10:54.783046 Set Vref, RX VrefLevel [Byte0]: 28
7792 22:10:54.786045 [Byte1]: 28
7793 22:10:54.790208
7794 22:10:54.793750 Set Vref, RX VrefLevel [Byte0]: 29
7795 22:10:54.793831 [Byte1]: 29
7796 22:10:54.798163
7797 22:10:54.798249 Set Vref, RX VrefLevel [Byte0]: 30
7798 22:10:54.801533 [Byte1]: 30
7799 22:10:54.805669
7800 22:10:54.805752 Set Vref, RX VrefLevel [Byte0]: 31
7801 22:10:54.809025 [Byte1]: 31
7802 22:10:54.813178
7803 22:10:54.813261 Set Vref, RX VrefLevel [Byte0]: 32
7804 22:10:54.816400 [Byte1]: 32
7805 22:10:54.820525
7806 22:10:54.820630 Set Vref, RX VrefLevel [Byte0]: 33
7807 22:10:54.824526 [Byte1]: 33
7808 22:10:54.828345
7809 22:10:54.828428 Set Vref, RX VrefLevel [Byte0]: 34
7810 22:10:54.831427 [Byte1]: 34
7811 22:10:54.836202
7812 22:10:54.836286 Set Vref, RX VrefLevel [Byte0]: 35
7813 22:10:54.839166 [Byte1]: 35
7814 22:10:54.844188
7815 22:10:54.844265 Set Vref, RX VrefLevel [Byte0]: 36
7816 22:10:54.846936 [Byte1]: 36
7817 22:10:54.851211
7818 22:10:54.851287 Set Vref, RX VrefLevel [Byte0]: 37
7819 22:10:54.854814 [Byte1]: 37
7820 22:10:54.858848
7821 22:10:54.858932 Set Vref, RX VrefLevel [Byte0]: 38
7822 22:10:54.862331 [Byte1]: 38
7823 22:10:54.866383
7824 22:10:54.866468 Set Vref, RX VrefLevel [Byte0]: 39
7825 22:10:54.869614 [Byte1]: 39
7826 22:10:54.873844
7827 22:10:54.873920 Set Vref, RX VrefLevel [Byte0]: 40
7828 22:10:54.877438 [Byte1]: 40
7829 22:10:54.881998
7830 22:10:54.882077 Set Vref, RX VrefLevel [Byte0]: 41
7831 22:10:54.884837 [Byte1]: 41
7832 22:10:54.889335
7833 22:10:54.889409 Set Vref, RX VrefLevel [Byte0]: 42
7834 22:10:54.892501 [Byte1]: 42
7835 22:10:54.896991
7836 22:10:54.897072 Set Vref, RX VrefLevel [Byte0]: 43
7837 22:10:54.900432 [Byte1]: 43
7838 22:10:54.904396
7839 22:10:54.904470 Set Vref, RX VrefLevel [Byte0]: 44
7840 22:10:54.908056 [Byte1]: 44
7841 22:10:54.912350
7842 22:10:54.912426 Set Vref, RX VrefLevel [Byte0]: 45
7843 22:10:54.915393 [Byte1]: 45
7844 22:10:54.919607
7845 22:10:54.919686 Set Vref, RX VrefLevel [Byte0]: 46
7846 22:10:54.926325 [Byte1]: 46
7847 22:10:54.926410
7848 22:10:54.929370 Set Vref, RX VrefLevel [Byte0]: 47
7849 22:10:54.932985 [Byte1]: 47
7850 22:10:54.933064
7851 22:10:54.936591 Set Vref, RX VrefLevel [Byte0]: 48
7852 22:10:54.939647 [Byte1]: 48
7853 22:10:54.939726
7854 22:10:54.943114 Set Vref, RX VrefLevel [Byte0]: 49
7855 22:10:54.946096 [Byte1]: 49
7856 22:10:54.950171
7857 22:10:54.953302 Set Vref, RX VrefLevel [Byte0]: 50
7858 22:10:54.956824 [Byte1]: 50
7859 22:10:54.956906
7860 22:10:54.959819 Set Vref, RX VrefLevel [Byte0]: 51
7861 22:10:54.963250 [Byte1]: 51
7862 22:10:54.963321
7863 22:10:54.966771 Set Vref, RX VrefLevel [Byte0]: 52
7864 22:10:54.970331 [Byte1]: 52
7865 22:10:54.970400
7866 22:10:54.973133 Set Vref, RX VrefLevel [Byte0]: 53
7867 22:10:54.976436 [Byte1]: 53
7868 22:10:54.980674
7869 22:10:54.980751 Set Vref, RX VrefLevel [Byte0]: 54
7870 22:10:54.984119 [Byte1]: 54
7871 22:10:54.988045
7872 22:10:54.988127 Set Vref, RX VrefLevel [Byte0]: 55
7873 22:10:54.991690 [Byte1]: 55
7874 22:10:54.996023
7875 22:10:54.996099 Set Vref, RX VrefLevel [Byte0]: 56
7876 22:10:54.998966 [Byte1]: 56
7877 22:10:55.003301
7878 22:10:55.003376 Set Vref, RX VrefLevel [Byte0]: 57
7879 22:10:55.006987 [Byte1]: 57
7880 22:10:55.011246
7881 22:10:55.011325 Set Vref, RX VrefLevel [Byte0]: 58
7882 22:10:55.014524 [Byte1]: 58
7883 22:10:55.018841
7884 22:10:55.018920 Set Vref, RX VrefLevel [Byte0]: 59
7885 22:10:55.021768 [Byte1]: 59
7886 22:10:55.026391
7887 22:10:55.026478 Set Vref, RX VrefLevel [Byte0]: 60
7888 22:10:55.029767 [Byte1]: 60
7889 22:10:55.034092
7890 22:10:55.034197 Set Vref, RX VrefLevel [Byte0]: 61
7891 22:10:55.037146 [Byte1]: 61
7892 22:10:55.041376
7893 22:10:55.041450 Set Vref, RX VrefLevel [Byte0]: 62
7894 22:10:55.044595 [Byte1]: 62
7895 22:10:55.049449
7896 22:10:55.049524 Set Vref, RX VrefLevel [Byte0]: 63
7897 22:10:55.052202 [Byte1]: 63
7898 22:10:55.056477
7899 22:10:55.056552 Set Vref, RX VrefLevel [Byte0]: 64
7900 22:10:55.060075 [Byte1]: 64
7901 22:10:55.064366
7902 22:10:55.064447 Set Vref, RX VrefLevel [Byte0]: 65
7903 22:10:55.067887 [Byte1]: 65
7904 22:10:55.072125
7905 22:10:55.072207 Set Vref, RX VrefLevel [Byte0]: 66
7906 22:10:55.075158 [Byte1]: 66
7907 22:10:55.079546
7908 22:10:55.079624 Set Vref, RX VrefLevel [Byte0]: 67
7909 22:10:55.082802 [Byte1]: 67
7910 22:10:55.087595
7911 22:10:55.087701 Set Vref, RX VrefLevel [Byte0]: 68
7912 22:10:55.090627 [Byte1]: 68
7913 22:10:55.094599
7914 22:10:55.094677 Set Vref, RX VrefLevel [Byte0]: 69
7915 22:10:55.097907 [Byte1]: 69
7916 22:10:55.102206
7917 22:10:55.102285 Set Vref, RX VrefLevel [Byte0]: 70
7918 22:10:55.105877 [Byte1]: 70
7919 22:10:55.110140
7920 22:10:55.110236 Set Vref, RX VrefLevel [Byte0]: 71
7921 22:10:55.113586 [Byte1]: 71
7922 22:10:55.117687
7923 22:10:55.117769 Set Vref, RX VrefLevel [Byte0]: 72
7924 22:10:55.121150 [Byte1]: 72
7925 22:10:55.124996
7926 22:10:55.125178 Set Vref, RX VrefLevel [Byte0]: 73
7927 22:10:55.128848 [Byte1]: 73
7928 22:10:55.132764
7929 22:10:55.132841 Set Vref, RX VrefLevel [Byte0]: 74
7930 22:10:55.136226 [Byte1]: 74
7931 22:10:55.140413
7932 22:10:55.140511 Set Vref, RX VrefLevel [Byte0]: 75
7933 22:10:55.143842 [Byte1]: 75
7934 22:10:55.148071
7935 22:10:55.148160 Set Vref, RX VrefLevel [Byte0]: 76
7936 22:10:55.151743 [Byte1]: 76
7937 22:10:55.156040
7938 22:10:55.156184 Final RX Vref Byte 0 = 58 to rank0
7939 22:10:55.159017 Final RX Vref Byte 1 = 61 to rank0
7940 22:10:55.162589 Final RX Vref Byte 0 = 58 to rank1
7941 22:10:55.165469 Final RX Vref Byte 1 = 61 to rank1==
7942 22:10:55.169046 Dram Type= 6, Freq= 0, CH_0, rank 0
7943 22:10:55.172339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7944 22:10:55.175904 ==
7945 22:10:55.175984 DQS Delay:
7946 22:10:55.176047 DQS0 = 0, DQS1 = 0
7947 22:10:55.179039 DQM Delay:
7948 22:10:55.179118 DQM0 = 130, DQM1 = 122
7949 22:10:55.182559 DQ Delay:
7950 22:10:55.185626 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7951 22:10:55.188968 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7952 22:10:55.192388 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =118
7953 22:10:55.196042 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
7954 22:10:55.196121
7955 22:10:55.196185
7956 22:10:55.196243
7957 22:10:55.199497 [DramC_TX_OE_Calibration] TA2
7958 22:10:55.202742 Original DQ_B0 (3 6) =30, OEN = 27
7959 22:10:55.205727 Original DQ_B1 (3 6) =30, OEN = 27
7960 22:10:55.209291 24, 0x0, End_B0=24 End_B1=24
7961 22:10:55.209372 25, 0x0, End_B0=25 End_B1=25
7962 22:10:55.212428 26, 0x0, End_B0=26 End_B1=26
7963 22:10:55.215991 27, 0x0, End_B0=27 End_B1=27
7964 22:10:55.219074 28, 0x0, End_B0=28 End_B1=28
7965 22:10:55.219155 29, 0x0, End_B0=29 End_B1=29
7966 22:10:55.222640 30, 0x0, End_B0=30 End_B1=30
7967 22:10:55.225682 31, 0x4141, End_B0=30 End_B1=30
7968 22:10:55.229322 Byte0 end_step=30 best_step=27
7969 22:10:55.232465 Byte1 end_step=30 best_step=27
7970 22:10:55.235948 Byte0 TX OE(2T, 0.5T) = (3, 3)
7971 22:10:55.236056 Byte1 TX OE(2T, 0.5T) = (3, 3)
7972 22:10:55.236117
7973 22:10:55.236174
7974 22:10:55.246179 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7975 22:10:55.249261 CH0 RK0: MR19=303, MR18=1509
7976 22:10:55.252571 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7977 22:10:55.256162
7978 22:10:55.259364 ----->DramcWriteLeveling(PI) begin...
7979 22:10:55.259506 ==
7980 22:10:55.262626 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 22:10:55.266114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7982 22:10:55.266194 ==
7983 22:10:55.269149 Write leveling (Byte 0): 33 => 33
7984 22:10:55.272820 Write leveling (Byte 1): 26 => 26
7985 22:10:55.276178 DramcWriteLeveling(PI) end<-----
7986 22:10:55.276258
7987 22:10:55.276321 ==
7988 22:10:55.279351 Dram Type= 6, Freq= 0, CH_0, rank 1
7989 22:10:55.282984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 22:10:55.283067 ==
7991 22:10:55.286077 [Gating] SW mode calibration
7992 22:10:55.292562 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7993 22:10:55.299410 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7994 22:10:55.302975 1 4 0 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
7995 22:10:55.305996 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 22:10:55.309279 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7997 22:10:55.316336 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7998 22:10:55.319329 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7999 22:10:55.322959 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8000 22:10:55.329099 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 22:10:55.332559 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 22:10:55.336064 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 22:10:55.342391 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 22:10:55.346115 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8005 22:10:55.349289 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8006 22:10:55.355976 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8007 22:10:55.359561 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (0 1) (0 0)
8008 22:10:55.362703 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 22:10:55.370031 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 22:10:55.373085 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 22:10:55.376007 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 22:10:55.383204 1 6 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8013 22:10:55.386163 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8014 22:10:55.389751 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8015 22:10:55.392903 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
8016 22:10:55.399966 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 22:10:55.403017 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 22:10:55.406305 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 22:10:55.413184 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 22:10:55.416177 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8021 22:10:55.419351 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8022 22:10:55.426228 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8023 22:10:55.429610 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8024 22:10:55.433304 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8025 22:10:55.440038 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 22:10:55.442901 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 22:10:55.446402 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 22:10:55.452987 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 22:10:55.456254 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 22:10:55.459893 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 22:10:55.463173 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 22:10:55.469784 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 22:10:55.472989 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 22:10:55.476217 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 22:10:55.483678 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 22:10:55.486342 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8037 22:10:55.489963 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8038 22:10:55.492901 Total UI for P1: 0, mck2ui 16
8039 22:10:55.496537 best dqsien dly found for B0: ( 1, 9, 8)
8040 22:10:55.503286 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8041 22:10:55.506422 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8042 22:10:55.509889 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 22:10:55.513579 Total UI for P1: 0, mck2ui 16
8044 22:10:55.517119 best dqsien dly found for B1: ( 1, 9, 20)
8045 22:10:55.520101 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8046 22:10:55.523385 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8047 22:10:55.523466
8048 22:10:55.526809 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8049 22:10:55.533212 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8050 22:10:55.533294 [Gating] SW calibration Done
8051 22:10:55.533358 ==
8052 22:10:55.536738 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 22:10:55.543423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 22:10:55.543504 ==
8055 22:10:55.543568 RX Vref Scan: 0
8056 22:10:55.543627
8057 22:10:55.546884 RX Vref 0 -> 0, step: 1
8058 22:10:55.546964
8059 22:10:55.550318 RX Delay 0 -> 252, step: 8
8060 22:10:55.553196 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8061 22:10:55.556490 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8062 22:10:55.559823 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8063 22:10:55.563176 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8064 22:10:55.570087 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8065 22:10:55.573562 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8066 22:10:55.576624 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8067 22:10:55.580217 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8068 22:10:55.583631 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8069 22:10:55.590632 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8070 22:10:55.593369 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8071 22:10:55.597131 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8072 22:10:55.600086 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8073 22:10:55.603328 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8074 22:10:55.610434 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8075 22:10:55.613535 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8076 22:10:55.613614 ==
8077 22:10:55.617145 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 22:10:55.620066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 22:10:55.620146 ==
8080 22:10:55.623944 DQS Delay:
8081 22:10:55.624024 DQS0 = 0, DQS1 = 0
8082 22:10:55.624087 DQM Delay:
8083 22:10:55.626845 DQM0 = 130, DQM1 = 124
8084 22:10:55.626923 DQ Delay:
8085 22:10:55.630451 DQ0 =131, DQ1 =131, DQ2 =123, DQ3 =131
8086 22:10:55.633790 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8087 22:10:55.637071 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8088 22:10:55.643769 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8089 22:10:55.643848
8090 22:10:55.643909
8091 22:10:55.643967 ==
8092 22:10:55.647623 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 22:10:55.650467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 22:10:55.650583 ==
8095 22:10:55.650645
8096 22:10:55.650702
8097 22:10:55.654013 TX Vref Scan disable
8098 22:10:55.654122 == TX Byte 0 ==
8099 22:10:55.660441 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8100 22:10:55.663861 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8101 22:10:55.663967 == TX Byte 1 ==
8102 22:10:55.670072 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8103 22:10:55.673596 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8104 22:10:55.673701 ==
8105 22:10:55.677075 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 22:10:55.680337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 22:10:55.680444 ==
8108 22:10:55.695828
8109 22:10:55.699428 TX Vref early break, caculate TX vref
8110 22:10:55.702978 TX Vref=16, minBit 2, minWin=22, winSum=371
8111 22:10:55.706292 TX Vref=18, minBit 9, minWin=22, winSum=378
8112 22:10:55.709339 TX Vref=20, minBit 8, minWin=23, winSum=388
8113 22:10:55.712852 TX Vref=22, minBit 2, minWin=24, winSum=402
8114 22:10:55.716060 TX Vref=24, minBit 3, minWin=24, winSum=405
8115 22:10:55.722597 TX Vref=26, minBit 3, minWin=25, winSum=415
8116 22:10:55.725967 TX Vref=28, minBit 1, minWin=25, winSum=416
8117 22:10:55.729176 TX Vref=30, minBit 2, minWin=25, winSum=417
8118 22:10:55.732584 TX Vref=32, minBit 0, minWin=25, winSum=414
8119 22:10:55.736271 TX Vref=34, minBit 4, minWin=24, winSum=403
8120 22:10:55.739159 TX Vref=36, minBit 0, minWin=24, winSum=392
8121 22:10:55.746162 [TxChooseVref] Worse bit 2, Min win 25, Win sum 417, Final Vref 30
8122 22:10:55.746301
8123 22:10:55.749128 Final TX Range 0 Vref 30
8124 22:10:55.749245
8125 22:10:55.749367 ==
8126 22:10:55.752302 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 22:10:55.755866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 22:10:55.755997 ==
8129 22:10:55.756088
8130 22:10:55.756177
8131 22:10:55.759288 TX Vref Scan disable
8132 22:10:55.766004 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8133 22:10:55.766109 == TX Byte 0 ==
8134 22:10:55.769674 u2DelayCellOfst[0]=10 cells (3 PI)
8135 22:10:55.772618 u2DelayCellOfst[1]=17 cells (5 PI)
8136 22:10:55.776255 u2DelayCellOfst[2]=7 cells (2 PI)
8137 22:10:55.779579 u2DelayCellOfst[3]=10 cells (3 PI)
8138 22:10:55.782847 u2DelayCellOfst[4]=7 cells (2 PI)
8139 22:10:55.785870 u2DelayCellOfst[5]=0 cells (0 PI)
8140 22:10:55.789265 u2DelayCellOfst[6]=17 cells (5 PI)
8141 22:10:55.792812 u2DelayCellOfst[7]=17 cells (5 PI)
8142 22:10:55.796091 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8143 22:10:55.799266 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8144 22:10:55.802545 == TX Byte 1 ==
8145 22:10:55.802645 u2DelayCellOfst[8]=0 cells (0 PI)
8146 22:10:55.805925 u2DelayCellOfst[9]=0 cells (0 PI)
8147 22:10:55.809784 u2DelayCellOfst[10]=3 cells (1 PI)
8148 22:10:55.812548 u2DelayCellOfst[11]=0 cells (0 PI)
8149 22:10:55.816343 u2DelayCellOfst[12]=10 cells (3 PI)
8150 22:10:55.819281 u2DelayCellOfst[13]=10 cells (3 PI)
8151 22:10:55.822886 u2DelayCellOfst[14]=14 cells (4 PI)
8152 22:10:55.826083 u2DelayCellOfst[15]=10 cells (3 PI)
8153 22:10:55.829368 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8154 22:10:55.836267 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8155 22:10:55.836388 DramC Write-DBI on
8156 22:10:55.836488 ==
8157 22:10:55.839650 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 22:10:55.842681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 22:10:55.842794 ==
8160 22:10:55.842888
8161 22:10:55.846100
8162 22:10:55.846207 TX Vref Scan disable
8163 22:10:55.849570 == TX Byte 0 ==
8164 22:10:55.853055 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8165 22:10:55.856055 == TX Byte 1 ==
8166 22:10:55.859560 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8167 22:10:55.859662 DramC Write-DBI off
8168 22:10:55.859754
8169 22:10:55.862934 [DATLAT]
8170 22:10:55.863035 Freq=1600, CH0 RK1
8171 22:10:55.863138
8172 22:10:55.865989 DATLAT Default: 0xf
8173 22:10:55.866098 0, 0xFFFF, sum = 0
8174 22:10:55.869332 1, 0xFFFF, sum = 0
8175 22:10:55.869441 2, 0xFFFF, sum = 0
8176 22:10:55.872892 3, 0xFFFF, sum = 0
8177 22:10:55.872971 4, 0xFFFF, sum = 0
8178 22:10:55.876586 5, 0xFFFF, sum = 0
8179 22:10:55.876700 6, 0xFFFF, sum = 0
8180 22:10:55.879769 7, 0xFFFF, sum = 0
8181 22:10:55.882555 8, 0xFFFF, sum = 0
8182 22:10:55.882657 9, 0xFFFF, sum = 0
8183 22:10:55.886125 10, 0xFFFF, sum = 0
8184 22:10:55.886227 11, 0xFFFF, sum = 0
8185 22:10:55.889558 12, 0xFFFF, sum = 0
8186 22:10:55.889666 13, 0xFFFF, sum = 0
8187 22:10:55.892789 14, 0x0, sum = 1
8188 22:10:55.892890 15, 0x0, sum = 2
8189 22:10:55.896036 16, 0x0, sum = 3
8190 22:10:55.896150 17, 0x0, sum = 4
8191 22:10:55.896250 best_step = 15
8192 22:10:55.899390
8193 22:10:55.899507 ==
8194 22:10:55.903255 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 22:10:55.905943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 22:10:55.906047 ==
8197 22:10:55.906140 RX Vref Scan: 0
8198 22:10:55.906231
8199 22:10:55.909612 RX Vref 0 -> 0, step: 1
8200 22:10:55.909715
8201 22:10:55.913227 RX Delay 11 -> 252, step: 4
8202 22:10:55.915996 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8203 22:10:55.919607 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8204 22:10:55.926401 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8205 22:10:55.929580 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8206 22:10:55.933254 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8207 22:10:55.936089 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8208 22:10:55.939757 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8209 22:10:55.946175 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8210 22:10:55.949815 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8211 22:10:55.952804 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8212 22:10:55.956171 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8213 22:10:55.959439 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8214 22:10:55.966118 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8215 22:10:55.969681 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8216 22:10:55.972623 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8217 22:10:55.976574 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8218 22:10:55.976697 ==
8219 22:10:55.979691 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 22:10:55.986271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 22:10:55.986372 ==
8222 22:10:55.986463 DQS Delay:
8223 22:10:55.986552 DQS0 = 0, DQS1 = 0
8224 22:10:55.989897 DQM Delay:
8225 22:10:55.989994 DQM0 = 127, DQM1 = 122
8226 22:10:55.992941 DQ Delay:
8227 22:10:55.996332 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8228 22:10:55.999910 DQ4 =124, DQ5 =116, DQ6 =136, DQ7 =134
8229 22:10:56.003410 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8230 22:10:56.006825 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8231 22:10:56.006936
8232 22:10:56.007028
8233 22:10:56.007125
8234 22:10:56.009916 [DramC_TX_OE_Calibration] TA2
8235 22:10:56.013166 Original DQ_B0 (3 6) =30, OEN = 27
8236 22:10:56.016206 Original DQ_B1 (3 6) =30, OEN = 27
8237 22:10:56.019825 24, 0x0, End_B0=24 End_B1=24
8238 22:10:56.019929 25, 0x0, End_B0=25 End_B1=25
8239 22:10:56.023409 26, 0x0, End_B0=26 End_B1=26
8240 22:10:56.026319 27, 0x0, End_B0=27 End_B1=27
8241 22:10:56.029838 28, 0x0, End_B0=28 End_B1=28
8242 22:10:56.029946 29, 0x0, End_B0=29 End_B1=29
8243 22:10:56.033057 30, 0x0, End_B0=30 End_B1=30
8244 22:10:56.036787 31, 0x4141, End_B0=30 End_B1=30
8245 22:10:56.039699 Byte0 end_step=30 best_step=27
8246 22:10:56.043271 Byte1 end_step=30 best_step=27
8247 22:10:56.046922 Byte0 TX OE(2T, 0.5T) = (3, 3)
8248 22:10:56.047017 Byte1 TX OE(2T, 0.5T) = (3, 3)
8249 22:10:56.047104
8250 22:10:56.047192
8251 22:10:56.056404 [DQSOSCAuto] RK1, (LSB)MR18= 0x180c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8252 22:10:56.059893 CH0 RK1: MR19=303, MR18=180C
8253 22:10:56.066748 CH0_RK1: MR19=0x303, MR18=0x180C, DQSOSC=397, MR23=63, INC=23, DEC=15
8254 22:10:56.066860 [RxdqsGatingPostProcess] freq 1600
8255 22:10:56.073473 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8256 22:10:56.076447 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 22:10:56.080098 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 22:10:56.083154 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 22:10:56.086847 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 22:10:56.090313 best DQS0 dly(2T, 0.5T) = (1, 1)
8261 22:10:56.093521 best DQS1 dly(2T, 0.5T) = (1, 1)
8262 22:10:56.093591 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8263 22:10:56.096515 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8264 22:10:56.100083 Pre-setting of DQS Precalculation
8265 22:10:56.106690 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8266 22:10:56.106766 ==
8267 22:10:56.109870 Dram Type= 6, Freq= 0, CH_1, rank 0
8268 22:10:56.113683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 22:10:56.113764 ==
8270 22:10:56.120227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8271 22:10:56.123757 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8272 22:10:56.126784 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8273 22:10:56.133290 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8274 22:10:56.142334 [CA 0] Center 42 (14~71) winsize 58
8275 22:10:56.145876 [CA 1] Center 42 (13~71) winsize 59
8276 22:10:56.149539 [CA 2] Center 37 (8~66) winsize 59
8277 22:10:56.152333 [CA 3] Center 35 (6~65) winsize 60
8278 22:10:56.155936 [CA 4] Center 37 (8~67) winsize 60
8279 22:10:56.158925 [CA 5] Center 36 (7~66) winsize 60
8280 22:10:56.159025
8281 22:10:56.162557 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8282 22:10:56.162655
8283 22:10:56.165563 [CATrainingPosCal] consider 1 rank data
8284 22:10:56.169051 u2DelayCellTimex100 = 275/100 ps
8285 22:10:56.172592 CA0 delay=42 (14~71),Diff = 7 PI (24 cell)
8286 22:10:56.179199 CA1 delay=42 (13~71),Diff = 7 PI (24 cell)
8287 22:10:56.182640 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8288 22:10:56.185809 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8289 22:10:56.189593 CA4 delay=37 (8~67),Diff = 2 PI (7 cell)
8290 22:10:56.192591 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8291 22:10:56.192698
8292 22:10:56.195656 CA PerBit enable=1, Macro0, CA PI delay=35
8293 22:10:56.195733
8294 22:10:56.199293 [CBTSetCACLKResult] CA Dly = 35
8295 22:10:56.199391 CS Dly: 9 (0~40)
8296 22:10:56.206001 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8297 22:10:56.209183 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8298 22:10:56.209282 ==
8299 22:10:56.212838 Dram Type= 6, Freq= 0, CH_1, rank 1
8300 22:10:56.216166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 22:10:56.216264 ==
8302 22:10:56.222734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8303 22:10:56.225897 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8304 22:10:56.229180 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8305 22:10:56.236282 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8306 22:10:56.245591 [CA 0] Center 43 (14~72) winsize 59
8307 22:10:56.249010 [CA 1] Center 43 (14~72) winsize 59
8308 22:10:56.252171 [CA 2] Center 38 (9~67) winsize 59
8309 22:10:56.255462 [CA 3] Center 37 (8~66) winsize 59
8310 22:10:56.259078 [CA 4] Center 38 (9~67) winsize 59
8311 22:10:56.262192 [CA 5] Center 36 (7~66) winsize 60
8312 22:10:56.262262
8313 22:10:56.265871 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8314 22:10:56.265938
8315 22:10:56.269367 [CATrainingPosCal] consider 2 rank data
8316 22:10:56.272631 u2DelayCellTimex100 = 275/100 ps
8317 22:10:56.275602 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8318 22:10:56.279295 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8319 22:10:56.286000 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8320 22:10:56.289223 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8321 22:10:56.292416 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8322 22:10:56.295867 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8323 22:10:56.295967
8324 22:10:56.299039 CA PerBit enable=1, Macro0, CA PI delay=36
8325 22:10:56.299111
8326 22:10:56.302747 [CBTSetCACLKResult] CA Dly = 36
8327 22:10:56.302817 CS Dly: 11 (0~44)
8328 22:10:56.309396 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8329 22:10:56.312531 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8330 22:10:56.312649
8331 22:10:56.316132 ----->DramcWriteLeveling(PI) begin...
8332 22:10:56.316242 ==
8333 22:10:56.318930 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 22:10:56.322468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 22:10:56.322571 ==
8336 22:10:56.326003 Write leveling (Byte 0): 26 => 26
8337 22:10:56.329130 Write leveling (Byte 1): 27 => 27
8338 22:10:56.332968 DramcWriteLeveling(PI) end<-----
8339 22:10:56.333067
8340 22:10:56.333155 ==
8341 22:10:56.336075 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 22:10:56.339370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 22:10:56.342654 ==
8344 22:10:56.342750 [Gating] SW mode calibration
8345 22:10:56.349596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8346 22:10:56.356230 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8347 22:10:56.359391 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 22:10:56.366215 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 22:10:56.369187 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 22:10:56.373067 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 22:10:56.379345 1 4 16 | B1->B0 | 3232 2a2a | 0 1 | (0 0) (1 1)
8352 22:10:56.382930 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 22:10:56.385885 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 22:10:56.389363 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 22:10:56.396346 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 22:10:56.399600 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 22:10:56.402518 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 22:10:56.409505 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8359 22:10:56.413034 1 5 16 | B1->B0 | 2b2b 3333 | 1 0 | (1 0) (0 1)
8360 22:10:56.416070 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8361 22:10:56.422772 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 22:10:56.426353 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 22:10:56.429390 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 22:10:56.436178 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 22:10:56.439631 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 22:10:56.443015 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 22:10:56.449438 1 6 16 | B1->B0 | 4646 3434 | 0 0 | (0 0) (0 0)
8368 22:10:56.453020 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 22:10:56.456031 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 22:10:56.463357 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 22:10:56.466127 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 22:10:56.469530 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 22:10:56.473130 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 22:10:56.479915 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8375 22:10:56.483201 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8376 22:10:56.486206 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 22:10:56.493202 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 22:10:56.496229 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 22:10:56.499820 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 22:10:56.506462 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 22:10:56.509791 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 22:10:56.513061 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 22:10:56.519688 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 22:10:56.522675 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 22:10:56.526326 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 22:10:56.532967 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 22:10:56.536532 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 22:10:56.540129 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 22:10:56.546613 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 22:10:56.549565 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8391 22:10:56.553177 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8392 22:10:56.556264 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 22:10:56.559669 Total UI for P1: 0, mck2ui 16
8394 22:10:56.563358 best dqsien dly found for B0: ( 1, 9, 14)
8395 22:10:56.566342 Total UI for P1: 0, mck2ui 16
8396 22:10:56.570045 best dqsien dly found for B1: ( 1, 9, 16)
8397 22:10:56.572823 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8398 22:10:56.576423 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8399 22:10:56.579692
8400 22:10:56.583165 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8401 22:10:56.586811 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8402 22:10:56.589776 [Gating] SW calibration Done
8403 22:10:56.589863 ==
8404 22:10:56.593188 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 22:10:56.596843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 22:10:56.596949 ==
8407 22:10:56.597039 RX Vref Scan: 0
8408 22:10:56.597124
8409 22:10:56.600314 RX Vref 0 -> 0, step: 1
8410 22:10:56.600410
8411 22:10:56.603369 RX Delay 0 -> 252, step: 8
8412 22:10:56.606824 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8413 22:10:56.609718 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8414 22:10:56.613480 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8415 22:10:56.619926 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8416 22:10:56.623330 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8417 22:10:56.626429 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8418 22:10:56.630179 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8419 22:10:56.633158 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8420 22:10:56.639946 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8421 22:10:56.643595 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8422 22:10:56.646874 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8423 22:10:56.650475 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8424 22:10:56.653654 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8425 22:10:56.660077 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8426 22:10:56.663400 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8427 22:10:56.666914 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8428 22:10:56.666993 ==
8429 22:10:56.669761 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 22:10:56.673570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 22:10:56.673653 ==
8432 22:10:56.676587 DQS Delay:
8433 22:10:56.676704 DQS0 = 0, DQS1 = 0
8434 22:10:56.680130 DQM Delay:
8435 22:10:56.680234 DQM0 = 134, DQM1 = 126
8436 22:10:56.680324 DQ Delay:
8437 22:10:56.686689 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8438 22:10:56.690133 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8439 22:10:56.693351 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8440 22:10:56.696589 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
8441 22:10:56.696720
8442 22:10:56.696816
8443 22:10:56.696878 ==
8444 22:10:56.700169 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 22:10:56.703758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 22:10:56.703856 ==
8447 22:10:56.703954
8448 22:10:56.704040
8449 22:10:56.707011 TX Vref Scan disable
8450 22:10:56.710332 == TX Byte 0 ==
8451 22:10:56.713368 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8452 22:10:56.716987 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8453 22:10:56.719870 == TX Byte 1 ==
8454 22:10:56.723488 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8455 22:10:56.727093 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8456 22:10:56.727196 ==
8457 22:10:56.730172 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 22:10:56.733477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 22:10:56.733558 ==
8460 22:10:56.747923
8461 22:10:56.750720 TX Vref early break, caculate TX vref
8462 22:10:56.754153 TX Vref=16, minBit 8, minWin=21, winSum=366
8463 22:10:56.757772 TX Vref=18, minBit 8, minWin=21, winSum=373
8464 22:10:56.760996 TX Vref=20, minBit 5, minWin=23, winSum=388
8465 22:10:56.764206 TX Vref=22, minBit 5, minWin=23, winSum=390
8466 22:10:56.767643 TX Vref=24, minBit 5, minWin=24, winSum=407
8467 22:10:56.774150 TX Vref=26, minBit 1, minWin=25, winSum=411
8468 22:10:56.777651 TX Vref=28, minBit 5, minWin=25, winSum=417
8469 22:10:56.780816 TX Vref=30, minBit 5, minWin=25, winSum=418
8470 22:10:56.783940 TX Vref=32, minBit 0, minWin=25, winSum=411
8471 22:10:56.787590 TX Vref=34, minBit 0, minWin=24, winSum=394
8472 22:10:56.794456 [TxChooseVref] Worse bit 5, Min win 25, Win sum 418, Final Vref 30
8473 22:10:56.794562
8474 22:10:56.797475 Final TX Range 0 Vref 30
8475 22:10:56.797548
8476 22:10:56.797608 ==
8477 22:10:56.800567 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 22:10:56.803962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 22:10:56.804031 ==
8480 22:10:56.804089
8481 22:10:56.804144
8482 22:10:56.807362 TX Vref Scan disable
8483 22:10:56.814045 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8484 22:10:56.814124 == TX Byte 0 ==
8485 22:10:56.817514 u2DelayCellOfst[0]=17 cells (5 PI)
8486 22:10:56.820576 u2DelayCellOfst[1]=10 cells (3 PI)
8487 22:10:56.824099 u2DelayCellOfst[2]=0 cells (0 PI)
8488 22:10:56.827893 u2DelayCellOfst[3]=7 cells (2 PI)
8489 22:10:56.830843 u2DelayCellOfst[4]=7 cells (2 PI)
8490 22:10:56.830956 u2DelayCellOfst[5]=21 cells (6 PI)
8491 22:10:56.834411 u2DelayCellOfst[6]=17 cells (5 PI)
8492 22:10:56.837576 u2DelayCellOfst[7]=7 cells (2 PI)
8493 22:10:56.844554 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8494 22:10:56.847906 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8495 22:10:56.847978 == TX Byte 1 ==
8496 22:10:56.850845 u2DelayCellOfst[8]=0 cells (0 PI)
8497 22:10:56.854518 u2DelayCellOfst[9]=7 cells (2 PI)
8498 22:10:56.857483 u2DelayCellOfst[10]=14 cells (4 PI)
8499 22:10:56.861114 u2DelayCellOfst[11]=10 cells (3 PI)
8500 22:10:56.864113 u2DelayCellOfst[12]=17 cells (5 PI)
8501 22:10:56.867373 u2DelayCellOfst[13]=21 cells (6 PI)
8502 22:10:56.870835 u2DelayCellOfst[14]=21 cells (6 PI)
8503 22:10:56.874380 u2DelayCellOfst[15]=21 cells (6 PI)
8504 22:10:56.877800 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8505 22:10:56.881251 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8506 22:10:56.884043 DramC Write-DBI on
8507 22:10:56.884114 ==
8508 22:10:56.887843 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 22:10:56.890756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 22:10:56.890852 ==
8511 22:10:56.890939
8512 22:10:56.891032
8513 22:10:56.894362 TX Vref Scan disable
8514 22:10:56.897553 == TX Byte 0 ==
8515 22:10:56.901171 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8516 22:10:56.901242 == TX Byte 1 ==
8517 22:10:56.907783 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8518 22:10:56.907854 DramC Write-DBI off
8519 22:10:56.907913
8520 22:10:56.911352 [DATLAT]
8521 22:10:56.911435 Freq=1600, CH1 RK0
8522 22:10:56.911493
8523 22:10:56.914782 DATLAT Default: 0xf
8524 22:10:56.914875 0, 0xFFFF, sum = 0
8525 22:10:56.917844 1, 0xFFFF, sum = 0
8526 22:10:56.917953 2, 0xFFFF, sum = 0
8527 22:10:56.921329 3, 0xFFFF, sum = 0
8528 22:10:56.921471 4, 0xFFFF, sum = 0
8529 22:10:56.924367 5, 0xFFFF, sum = 0
8530 22:10:56.924447 6, 0xFFFF, sum = 0
8531 22:10:56.927818 7, 0xFFFF, sum = 0
8532 22:10:56.927898 8, 0xFFFF, sum = 0
8533 22:10:56.931329 9, 0xFFFF, sum = 0
8534 22:10:56.931410 10, 0xFFFF, sum = 0
8535 22:10:56.934570 11, 0xFFFF, sum = 0
8536 22:10:56.934650 12, 0xFFFF, sum = 0
8537 22:10:56.937692 13, 0xFFFF, sum = 0
8538 22:10:56.937771 14, 0x0, sum = 1
8539 22:10:56.941293 15, 0x0, sum = 2
8540 22:10:56.941373 16, 0x0, sum = 3
8541 22:10:56.944333 17, 0x0, sum = 4
8542 22:10:56.944413 best_step = 15
8543 22:10:56.944475
8544 22:10:56.944532 ==
8545 22:10:56.947543 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 22:10:56.954734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 22:10:56.954814 ==
8548 22:10:56.954875 RX Vref Scan: 1
8549 22:10:56.954933
8550 22:10:56.957884 Set Vref Range= 24 -> 127
8551 22:10:56.957990
8552 22:10:56.961079 RX Vref 24 -> 127, step: 1
8553 22:10:56.961158
8554 22:10:56.964627 RX Delay 19 -> 252, step: 4
8555 22:10:56.964734
8556 22:10:56.964798 Set Vref, RX VrefLevel [Byte0]: 24
8557 22:10:56.967639 [Byte1]: 24
8558 22:10:56.972141
8559 22:10:56.972225 Set Vref, RX VrefLevel [Byte0]: 25
8560 22:10:56.975572 [Byte1]: 25
8561 22:10:56.979338
8562 22:10:56.979417 Set Vref, RX VrefLevel [Byte0]: 26
8563 22:10:56.982896 [Byte1]: 26
8564 22:10:56.986895
8565 22:10:56.986975 Set Vref, RX VrefLevel [Byte0]: 27
8566 22:10:56.990651 [Byte1]: 27
8567 22:10:56.994922
8568 22:10:56.995002 Set Vref, RX VrefLevel [Byte0]: 28
8569 22:10:56.997925 [Byte1]: 28
8570 22:10:57.002403
8571 22:10:57.002483 Set Vref, RX VrefLevel [Byte0]: 29
8572 22:10:57.005923 [Byte1]: 29
8573 22:10:57.010130
8574 22:10:57.010209 Set Vref, RX VrefLevel [Byte0]: 30
8575 22:10:57.013132 [Byte1]: 30
8576 22:10:57.017396
8577 22:10:57.017475 Set Vref, RX VrefLevel [Byte0]: 31
8578 22:10:57.020508 [Byte1]: 31
8579 22:10:57.024966
8580 22:10:57.025046 Set Vref, RX VrefLevel [Byte0]: 32
8581 22:10:57.028448 [Byte1]: 32
8582 22:10:57.032651
8583 22:10:57.032768 Set Vref, RX VrefLevel [Byte0]: 33
8584 22:10:57.035567 [Byte1]: 33
8585 22:10:57.040108
8586 22:10:57.040187 Set Vref, RX VrefLevel [Byte0]: 34
8587 22:10:57.043506 [Byte1]: 34
8588 22:10:57.047718
8589 22:10:57.047822 Set Vref, RX VrefLevel [Byte0]: 35
8590 22:10:57.051035 [Byte1]: 35
8591 22:10:57.055469
8592 22:10:57.055548 Set Vref, RX VrefLevel [Byte0]: 36
8593 22:10:57.058431 [Byte1]: 36
8594 22:10:57.063295
8595 22:10:57.063375 Set Vref, RX VrefLevel [Byte0]: 37
8596 22:10:57.066104 [Byte1]: 37
8597 22:10:57.070444
8598 22:10:57.070523 Set Vref, RX VrefLevel [Byte0]: 38
8599 22:10:57.073720 [Byte1]: 38
8600 22:10:57.078118
8601 22:10:57.078202 Set Vref, RX VrefLevel [Byte0]: 39
8602 22:10:57.081129 [Byte1]: 39
8603 22:10:57.085670
8604 22:10:57.085746 Set Vref, RX VrefLevel [Byte0]: 40
8605 22:10:57.088969 [Byte1]: 40
8606 22:10:57.092819
8607 22:10:57.092897 Set Vref, RX VrefLevel [Byte0]: 41
8608 22:10:57.096130 [Byte1]: 41
8609 22:10:57.100613
8610 22:10:57.100747 Set Vref, RX VrefLevel [Byte0]: 42
8611 22:10:57.104352 [Byte1]: 42
8612 22:10:57.108502
8613 22:10:57.108604 Set Vref, RX VrefLevel [Byte0]: 43
8614 22:10:57.111472 [Byte1]: 43
8615 22:10:57.115912
8616 22:10:57.116010 Set Vref, RX VrefLevel [Byte0]: 44
8617 22:10:57.119453 [Byte1]: 44
8618 22:10:57.123623
8619 22:10:57.123725 Set Vref, RX VrefLevel [Byte0]: 45
8620 22:10:57.127012 [Byte1]: 45
8621 22:10:57.131114
8622 22:10:57.131189 Set Vref, RX VrefLevel [Byte0]: 46
8623 22:10:57.134168 [Byte1]: 46
8624 22:10:57.138809
8625 22:10:57.138889 Set Vref, RX VrefLevel [Byte0]: 47
8626 22:10:57.141950 [Byte1]: 47
8627 22:10:57.146208
8628 22:10:57.146279 Set Vref, RX VrefLevel [Byte0]: 48
8629 22:10:57.149895 [Byte1]: 48
8630 22:10:57.153615
8631 22:10:57.153686 Set Vref, RX VrefLevel [Byte0]: 49
8632 22:10:57.156883 [Byte1]: 49
8633 22:10:57.161337
8634 22:10:57.161414 Set Vref, RX VrefLevel [Byte0]: 50
8635 22:10:57.164402 [Byte1]: 50
8636 22:10:57.168567
8637 22:10:57.168691 Set Vref, RX VrefLevel [Byte0]: 51
8638 22:10:57.172431 [Byte1]: 51
8639 22:10:57.176637
8640 22:10:57.176741 Set Vref, RX VrefLevel [Byte0]: 52
8641 22:10:57.179977 [Byte1]: 52
8642 22:10:57.184125
8643 22:10:57.184206 Set Vref, RX VrefLevel [Byte0]: 53
8644 22:10:57.187560 [Byte1]: 53
8645 22:10:57.191365
8646 22:10:57.191445 Set Vref, RX VrefLevel [Byte0]: 54
8647 22:10:57.194613 [Byte1]: 54
8648 22:10:57.199238
8649 22:10:57.199319 Set Vref, RX VrefLevel [Byte0]: 55
8650 22:10:57.202390 [Byte1]: 55
8651 22:10:57.206913
8652 22:10:57.207038 Set Vref, RX VrefLevel [Byte0]: 56
8653 22:10:57.209982 [Byte1]: 56
8654 22:10:57.214275
8655 22:10:57.214356 Set Vref, RX VrefLevel [Byte0]: 57
8656 22:10:57.217900 [Byte1]: 57
8657 22:10:57.221573
8658 22:10:57.221653 Set Vref, RX VrefLevel [Byte0]: 58
8659 22:10:57.225100 [Byte1]: 58
8660 22:10:57.229340
8661 22:10:57.229430 Set Vref, RX VrefLevel [Byte0]: 59
8662 22:10:57.232819 [Byte1]: 59
8663 22:10:57.236833
8664 22:10:57.236916 Set Vref, RX VrefLevel [Byte0]: 60
8665 22:10:57.240365 [Byte1]: 60
8666 22:10:57.244415
8667 22:10:57.244531 Set Vref, RX VrefLevel [Byte0]: 61
8668 22:10:57.248168 [Byte1]: 61
8669 22:10:57.252452
8670 22:10:57.252565 Set Vref, RX VrefLevel [Byte0]: 62
8671 22:10:57.255633 [Byte1]: 62
8672 22:10:57.259715
8673 22:10:57.259783 Set Vref, RX VrefLevel [Byte0]: 63
8674 22:10:57.263265 [Byte1]: 63
8675 22:10:57.267200
8676 22:10:57.267279 Set Vref, RX VrefLevel [Byte0]: 64
8677 22:10:57.270670 [Byte1]: 64
8678 22:10:57.274661
8679 22:10:57.274741 Set Vref, RX VrefLevel [Byte0]: 65
8680 22:10:57.278339 [Byte1]: 65
8681 22:10:57.282441
8682 22:10:57.282521 Set Vref, RX VrefLevel [Byte0]: 66
8683 22:10:57.285491 [Byte1]: 66
8684 22:10:57.289926
8685 22:10:57.290008 Set Vref, RX VrefLevel [Byte0]: 67
8686 22:10:57.293358 [Byte1]: 67
8687 22:10:57.297776
8688 22:10:57.297856 Set Vref, RX VrefLevel [Byte0]: 68
8689 22:10:57.301320 [Byte1]: 68
8690 22:10:57.304979
8691 22:10:57.305060 Set Vref, RX VrefLevel [Byte0]: 69
8692 22:10:57.308697 [Byte1]: 69
8693 22:10:57.312591
8694 22:10:57.312698 Set Vref, RX VrefLevel [Byte0]: 70
8695 22:10:57.315966 [Byte1]: 70
8696 22:10:57.320558
8697 22:10:57.320638 Set Vref, RX VrefLevel [Byte0]: 71
8698 22:10:57.323925 [Byte1]: 71
8699 22:10:57.328287
8700 22:10:57.328367 Set Vref, RX VrefLevel [Byte0]: 72
8701 22:10:57.331099 [Byte1]: 72
8702 22:10:57.335550
8703 22:10:57.335630 Set Vref, RX VrefLevel [Byte0]: 73
8704 22:10:57.339040 [Byte1]: 73
8705 22:10:57.342988
8706 22:10:57.343068 Set Vref, RX VrefLevel [Byte0]: 74
8707 22:10:57.346412 [Byte1]: 74
8708 22:10:57.350386
8709 22:10:57.350466 Set Vref, RX VrefLevel [Byte0]: 75
8710 22:10:57.354073 [Byte1]: 75
8711 22:10:57.358298
8712 22:10:57.358378 Final RX Vref Byte 0 = 64 to rank0
8713 22:10:57.361342 Final RX Vref Byte 1 = 55 to rank0
8714 22:10:57.364801 Final RX Vref Byte 0 = 64 to rank1
8715 22:10:57.367841 Final RX Vref Byte 1 = 55 to rank1==
8716 22:10:57.371327 Dram Type= 6, Freq= 0, CH_1, rank 0
8717 22:10:57.378138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 22:10:57.378248 ==
8719 22:10:57.378314 DQS Delay:
8720 22:10:57.378373 DQS0 = 0, DQS1 = 0
8721 22:10:57.381359 DQM Delay:
8722 22:10:57.381439 DQM0 = 132, DQM1 = 124
8723 22:10:57.385132 DQ Delay:
8724 22:10:57.387886 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =132
8725 22:10:57.391198 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8726 22:10:57.394728 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8727 22:10:57.398097 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8728 22:10:57.398177
8729 22:10:57.398240
8730 22:10:57.398298
8731 22:10:57.401684 [DramC_TX_OE_Calibration] TA2
8732 22:10:57.404567 Original DQ_B0 (3 6) =30, OEN = 27
8733 22:10:57.408074 Original DQ_B1 (3 6) =30, OEN = 27
8734 22:10:57.411135 24, 0x0, End_B0=24 End_B1=24
8735 22:10:57.411216 25, 0x0, End_B0=25 End_B1=25
8736 22:10:57.414683 26, 0x0, End_B0=26 End_B1=26
8737 22:10:57.418318 27, 0x0, End_B0=27 End_B1=27
8738 22:10:57.421314 28, 0x0, End_B0=28 End_B1=28
8739 22:10:57.421396 29, 0x0, End_B0=29 End_B1=29
8740 22:10:57.424595 30, 0x0, End_B0=30 End_B1=30
8741 22:10:57.428077 31, 0x4141, End_B0=30 End_B1=30
8742 22:10:57.431086 Byte0 end_step=30 best_step=27
8743 22:10:57.434980 Byte1 end_step=30 best_step=27
8744 22:10:57.437925 Byte0 TX OE(2T, 0.5T) = (3, 3)
8745 22:10:57.438006 Byte1 TX OE(2T, 0.5T) = (3, 3)
8746 22:10:57.441090
8747 22:10:57.441170
8748 22:10:57.448279 [DQSOSCAuto] RK0, (LSB)MR18= 0x1400, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8749 22:10:57.451636 CH1 RK0: MR19=303, MR18=1400
8750 22:10:57.457990 CH1_RK0: MR19=0x303, MR18=0x1400, DQSOSC=399, MR23=63, INC=23, DEC=15
8751 22:10:57.458072
8752 22:10:57.461718 ----->DramcWriteLeveling(PI) begin...
8753 22:10:57.461800 ==
8754 22:10:57.464856 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 22:10:57.468265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 22:10:57.468345 ==
8757 22:10:57.471361 Write leveling (Byte 0): 26 => 26
8758 22:10:57.474845 Write leveling (Byte 1): 27 => 27
8759 22:10:57.477916 DramcWriteLeveling(PI) end<-----
8760 22:10:57.477996
8761 22:10:57.478060 ==
8762 22:10:57.481274 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 22:10:57.484543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 22:10:57.484653 ==
8765 22:10:57.488022 [Gating] SW mode calibration
8766 22:10:57.494905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8767 22:10:57.501708 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8768 22:10:57.505020 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 22:10:57.508023 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 22:10:57.515080 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
8771 22:10:57.518333 1 4 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
8772 22:10:57.521887 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 22:10:57.528525 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 22:10:57.531627 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 22:10:57.535008 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 22:10:57.538177 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 22:10:57.545148 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8778 22:10:57.547931 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8779 22:10:57.551330 1 5 12 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
8780 22:10:57.558509 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8781 22:10:57.562070 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 22:10:57.565120 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 22:10:57.571746 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 22:10:57.574750 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 22:10:57.578423 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
8786 22:10:57.584984 1 6 8 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (0 0)
8787 22:10:57.588367 1 6 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8788 22:10:57.591941 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 22:10:57.598454 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 22:10:57.601343 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 22:10:57.605041 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 22:10:57.611686 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 22:10:57.614827 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8794 22:10:57.618316 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8795 22:10:57.621928 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8796 22:10:57.628565 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8797 22:10:57.631502 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 22:10:57.635241 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 22:10:57.641643 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 22:10:57.645108 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 22:10:57.648300 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 22:10:57.655135 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 22:10:57.658652 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 22:10:57.661872 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 22:10:57.668414 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 22:10:57.671797 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 22:10:57.675324 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 22:10:57.681914 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 22:10:57.685670 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8810 22:10:57.688585 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8811 22:10:57.692327 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8812 22:10:57.695319 Total UI for P1: 0, mck2ui 16
8813 22:10:57.698880 best dqsien dly found for B0: ( 1, 9, 6)
8814 22:10:57.705269 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8815 22:10:57.708658 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 22:10:57.711869 Total UI for P1: 0, mck2ui 16
8817 22:10:57.715278 best dqsien dly found for B1: ( 1, 9, 14)
8818 22:10:57.718617 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8819 22:10:57.721864 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8820 22:10:57.721944
8821 22:10:57.725586 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8822 22:10:57.728892 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8823 22:10:57.731816 [Gating] SW calibration Done
8824 22:10:57.731896 ==
8825 22:10:57.735509 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 22:10:57.742120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 22:10:57.742201 ==
8828 22:10:57.742265 RX Vref Scan: 0
8829 22:10:57.742324
8830 22:10:57.745230 RX Vref 0 -> 0, step: 1
8831 22:10:57.745311
8832 22:10:57.748776 RX Delay 0 -> 252, step: 8
8833 22:10:57.752537 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8834 22:10:57.755860 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8835 22:10:57.758634 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8836 22:10:57.762601 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8837 22:10:57.765950 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8838 22:10:57.772133 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8839 22:10:57.775586 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8840 22:10:57.778822 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8841 22:10:57.782177 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8842 22:10:57.785881 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8843 22:10:57.792074 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8844 22:10:57.795637 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8845 22:10:57.799229 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8846 22:10:57.802263 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8847 22:10:57.805948 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8848 22:10:57.812272 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8849 22:10:57.812354 ==
8850 22:10:57.815638 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 22:10:57.819198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 22:10:57.819294 ==
8853 22:10:57.819358 DQS Delay:
8854 22:10:57.822220 DQS0 = 0, DQS1 = 0
8855 22:10:57.822302 DQM Delay:
8856 22:10:57.825741 DQM0 = 132, DQM1 = 127
8857 22:10:57.825893 DQ Delay:
8858 22:10:57.829238 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8859 22:10:57.832363 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8860 22:10:57.835637 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8861 22:10:57.839225 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8862 22:10:57.839330
8863 22:10:57.839428
8864 22:10:57.842263 ==
8865 22:10:57.845958 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 22:10:57.848939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 22:10:57.849027 ==
8868 22:10:57.849128
8869 22:10:57.849222
8870 22:10:57.852507 TX Vref Scan disable
8871 22:10:57.852618 == TX Byte 0 ==
8872 22:10:57.855511 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8873 22:10:57.862107 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8874 22:10:57.862205 == TX Byte 1 ==
8875 22:10:57.865693 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8876 22:10:57.872487 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8877 22:10:57.872569 ==
8878 22:10:57.875665 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 22:10:57.879329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 22:10:57.879442 ==
8881 22:10:57.892563
8882 22:10:57.896263 TX Vref early break, caculate TX vref
8883 22:10:57.899774 TX Vref=16, minBit 8, minWin=22, winSum=376
8884 22:10:57.902814 TX Vref=18, minBit 8, minWin=22, winSum=389
8885 22:10:57.905970 TX Vref=20, minBit 8, minWin=23, winSum=389
8886 22:10:57.909214 TX Vref=22, minBit 8, minWin=24, winSum=405
8887 22:10:57.912947 TX Vref=24, minBit 0, minWin=25, winSum=413
8888 22:10:57.919261 TX Vref=26, minBit 6, minWin=25, winSum=417
8889 22:10:57.922658 TX Vref=28, minBit 1, minWin=26, winSum=425
8890 22:10:57.926379 TX Vref=30, minBit 0, minWin=25, winSum=421
8891 22:10:57.929134 TX Vref=32, minBit 0, minWin=25, winSum=416
8892 22:10:57.932829 TX Vref=34, minBit 0, minWin=25, winSum=408
8893 22:10:57.936424 TX Vref=36, minBit 8, minWin=23, winSum=394
8894 22:10:57.942774 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 28
8895 22:10:57.942856
8896 22:10:57.946256 Final TX Range 0 Vref 28
8897 22:10:57.946361
8898 22:10:57.946463 ==
8899 22:10:57.949287 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 22:10:57.952963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 22:10:57.953074 ==
8902 22:10:57.953181
8903 22:10:57.953247
8904 22:10:57.955907 TX Vref Scan disable
8905 22:10:57.962568 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8906 22:10:57.962680 == TX Byte 0 ==
8907 22:10:57.966141 u2DelayCellOfst[0]=17 cells (5 PI)
8908 22:10:57.969732 u2DelayCellOfst[1]=10 cells (3 PI)
8909 22:10:57.973227 u2DelayCellOfst[2]=0 cells (0 PI)
8910 22:10:57.976157 u2DelayCellOfst[3]=7 cells (2 PI)
8911 22:10:57.979687 u2DelayCellOfst[4]=10 cells (3 PI)
8912 22:10:57.982741 u2DelayCellOfst[5]=17 cells (5 PI)
8913 22:10:57.986406 u2DelayCellOfst[6]=17 cells (5 PI)
8914 22:10:57.989402 u2DelayCellOfst[7]=7 cells (2 PI)
8915 22:10:57.992969 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8916 22:10:57.996207 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8917 22:10:57.996305 == TX Byte 1 ==
8918 22:10:57.999490 u2DelayCellOfst[8]=0 cells (0 PI)
8919 22:10:58.002920 u2DelayCellOfst[9]=3 cells (1 PI)
8920 22:10:58.006374 u2DelayCellOfst[10]=10 cells (3 PI)
8921 22:10:58.009756 u2DelayCellOfst[11]=7 cells (2 PI)
8922 22:10:58.013013 u2DelayCellOfst[12]=14 cells (4 PI)
8923 22:10:58.016058 u2DelayCellOfst[13]=14 cells (4 PI)
8924 22:10:58.019436 u2DelayCellOfst[14]=17 cells (5 PI)
8925 22:10:58.022908 u2DelayCellOfst[15]=14 cells (4 PI)
8926 22:10:58.026416 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8927 22:10:58.033088 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8928 22:10:58.033171 DramC Write-DBI on
8929 22:10:58.033274 ==
8930 22:10:58.036156 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 22:10:58.039922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 22:10:58.040004 ==
8933 22:10:58.043057
8934 22:10:58.043139
8935 22:10:58.043205 TX Vref Scan disable
8936 22:10:58.045994 == TX Byte 0 ==
8937 22:10:58.049389 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8938 22:10:58.052818 == TX Byte 1 ==
8939 22:10:58.056014 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8940 22:10:58.056133 DramC Write-DBI off
8941 22:10:58.059719
8942 22:10:58.059808 [DATLAT]
8943 22:10:58.059886 Freq=1600, CH1 RK1
8944 22:10:58.059976
8945 22:10:58.062760 DATLAT Default: 0xf
8946 22:10:58.062852 0, 0xFFFF, sum = 0
8947 22:10:58.066312 1, 0xFFFF, sum = 0
8948 22:10:58.066393 2, 0xFFFF, sum = 0
8949 22:10:58.069412 3, 0xFFFF, sum = 0
8950 22:10:58.069493 4, 0xFFFF, sum = 0
8951 22:10:58.073026 5, 0xFFFF, sum = 0
8952 22:10:58.073118 6, 0xFFFF, sum = 0
8953 22:10:58.076386 7, 0xFFFF, sum = 0
8954 22:10:58.079799 8, 0xFFFF, sum = 0
8955 22:10:58.079893 9, 0xFFFF, sum = 0
8956 22:10:58.082858 10, 0xFFFF, sum = 0
8957 22:10:58.082986 11, 0xFFFF, sum = 0
8958 22:10:58.086005 12, 0xFFFF, sum = 0
8959 22:10:58.086114 13, 0xFFFF, sum = 0
8960 22:10:58.089590 14, 0x0, sum = 1
8961 22:10:58.089672 15, 0x0, sum = 2
8962 22:10:58.092655 16, 0x0, sum = 3
8963 22:10:58.092746 17, 0x0, sum = 4
8964 22:10:58.092821 best_step = 15
8965 22:10:58.096353
8966 22:10:58.096434 ==
8967 22:10:58.099557 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 22:10:58.103086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 22:10:58.103174 ==
8970 22:10:58.103242 RX Vref Scan: 0
8971 22:10:58.103310
8972 22:10:58.106469 RX Vref 0 -> 0, step: 1
8973 22:10:58.106559
8974 22:10:58.109808 RX Delay 11 -> 252, step: 4
8975 22:10:58.113299 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8976 22:10:58.116119 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8977 22:10:58.122958 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8978 22:10:58.126251 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8979 22:10:58.129445 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8980 22:10:58.133032 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8981 22:10:58.136475 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8982 22:10:58.143290 iDelay=191, Bit 7, Center 124 (75 ~ 174) 100
8983 22:10:58.146522 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8984 22:10:58.149406 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8985 22:10:58.153095 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8986 22:10:58.156153 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8987 22:10:58.162812 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8988 22:10:58.166501 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
8989 22:10:58.169499 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8990 22:10:58.173178 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
8991 22:10:58.173299 ==
8992 22:10:58.176148 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 22:10:58.179549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 22:10:58.183150 ==
8995 22:10:58.183271 DQS Delay:
8996 22:10:58.183352 DQS0 = 0, DQS1 = 0
8997 22:10:58.186729 DQM Delay:
8998 22:10:58.186830 DQM0 = 129, DQM1 = 126
8999 22:10:58.189813 DQ Delay:
9000 22:10:58.193517 DQ0 =134, DQ1 =126, DQ2 =118, DQ3 =126
9001 22:10:58.196572 DQ4 =130, DQ5 =142, DQ6 =136, DQ7 =124
9002 22:10:58.200212 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9003 22:10:58.203241 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =136
9004 22:10:58.203350
9005 22:10:58.203445
9006 22:10:58.203542
9007 22:10:58.206840 [DramC_TX_OE_Calibration] TA2
9008 22:10:58.209841 Original DQ_B0 (3 6) =30, OEN = 27
9009 22:10:58.213205 Original DQ_B1 (3 6) =30, OEN = 27
9010 22:10:58.213288 24, 0x0, End_B0=24 End_B1=24
9011 22:10:58.216963 25, 0x0, End_B0=25 End_B1=25
9012 22:10:58.220430 26, 0x0, End_B0=26 End_B1=26
9013 22:10:58.223386 27, 0x0, End_B0=27 End_B1=27
9014 22:10:58.226708 28, 0x0, End_B0=28 End_B1=28
9015 22:10:58.226792 29, 0x0, End_B0=29 End_B1=29
9016 22:10:58.230275 30, 0x0, End_B0=30 End_B1=30
9017 22:10:58.233816 31, 0x4141, End_B0=30 End_B1=30
9018 22:10:58.236747 Byte0 end_step=30 best_step=27
9019 22:10:58.240329 Byte1 end_step=30 best_step=27
9020 22:10:58.240414 Byte0 TX OE(2T, 0.5T) = (3, 3)
9021 22:10:58.243400 Byte1 TX OE(2T, 0.5T) = (3, 3)
9022 22:10:58.243475
9023 22:10:58.243537
9024 22:10:58.253686 [DQSOSCAuto] RK1, (LSB)MR18= 0xe14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9025 22:10:58.253768 CH1 RK1: MR19=303, MR18=E14
9026 22:10:58.260175 CH1_RK1: MR19=0x303, MR18=0xE14, DQSOSC=399, MR23=63, INC=23, DEC=15
9027 22:10:58.263220 [RxdqsGatingPostProcess] freq 1600
9028 22:10:58.269991 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9029 22:10:58.273169 best DQS0 dly(2T, 0.5T) = (1, 1)
9030 22:10:58.276939 best DQS1 dly(2T, 0.5T) = (1, 1)
9031 22:10:58.279914 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9032 22:10:58.283465 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9033 22:10:58.283548 best DQS0 dly(2T, 0.5T) = (1, 1)
9034 22:10:58.286913 best DQS1 dly(2T, 0.5T) = (1, 1)
9035 22:10:58.290178 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9036 22:10:58.293580 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9037 22:10:58.296696 Pre-setting of DQS Precalculation
9038 22:10:58.303511 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9039 22:10:58.310072 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9040 22:10:58.317183 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9041 22:10:58.317268
9042 22:10:58.317333
9043 22:10:58.320256 [Calibration Summary] 3200 Mbps
9044 22:10:58.320338 CH 0, Rank 0
9045 22:10:58.323790 SW Impedance : PASS
9046 22:10:58.326853 DUTY Scan : NO K
9047 22:10:58.326964 ZQ Calibration : PASS
9048 22:10:58.330575 Jitter Meter : NO K
9049 22:10:58.333658 CBT Training : PASS
9050 22:10:58.333759 Write leveling : PASS
9051 22:10:58.336740 RX DQS gating : PASS
9052 22:10:58.339995 RX DQ/DQS(RDDQC) : PASS
9053 22:10:58.340069 TX DQ/DQS : PASS
9054 22:10:58.343298 RX DATLAT : PASS
9055 22:10:58.343371 RX DQ/DQS(Engine): PASS
9056 22:10:58.346959 TX OE : PASS
9057 22:10:58.347035 All Pass.
9058 22:10:58.347098
9059 22:10:58.349961 CH 0, Rank 1
9060 22:10:58.350057 SW Impedance : PASS
9061 22:10:58.353765 DUTY Scan : NO K
9062 22:10:58.356586 ZQ Calibration : PASS
9063 22:10:58.356675 Jitter Meter : NO K
9064 22:10:58.359962 CBT Training : PASS
9065 22:10:58.363635 Write leveling : PASS
9066 22:10:58.363718 RX DQS gating : PASS
9067 22:10:58.366676 RX DQ/DQS(RDDQC) : PASS
9068 22:10:58.369873 TX DQ/DQS : PASS
9069 22:10:58.369950 RX DATLAT : PASS
9070 22:10:58.373430 RX DQ/DQS(Engine): PASS
9071 22:10:58.376467 TX OE : PASS
9072 22:10:58.376577 All Pass.
9073 22:10:58.376688
9074 22:10:58.376783 CH 1, Rank 0
9075 22:10:58.379574 SW Impedance : PASS
9076 22:10:58.383091 DUTY Scan : NO K
9077 22:10:58.383168 ZQ Calibration : PASS
9078 22:10:58.386436 Jitter Meter : NO K
9079 22:10:58.389629 CBT Training : PASS
9080 22:10:58.389713 Write leveling : PASS
9081 22:10:58.392961 RX DQS gating : PASS
9082 22:10:58.396379 RX DQ/DQS(RDDQC) : PASS
9083 22:10:58.396464 TX DQ/DQS : PASS
9084 22:10:58.399806 RX DATLAT : PASS
9085 22:10:58.399884 RX DQ/DQS(Engine): PASS
9086 22:10:58.403186 TX OE : PASS
9087 22:10:58.403275 All Pass.
9088 22:10:58.403371
9089 22:10:58.406462 CH 1, Rank 1
9090 22:10:58.406557 SW Impedance : PASS
9091 22:10:58.410183 DUTY Scan : NO K
9092 22:10:58.413122 ZQ Calibration : PASS
9093 22:10:58.413206 Jitter Meter : NO K
9094 22:10:58.416844 CBT Training : PASS
9095 22:10:58.419716 Write leveling : PASS
9096 22:10:58.419799 RX DQS gating : PASS
9097 22:10:58.423219 RX DQ/DQS(RDDQC) : PASS
9098 22:10:58.426725 TX DQ/DQS : PASS
9099 22:10:58.426805 RX DATLAT : PASS
9100 22:10:58.429756 RX DQ/DQS(Engine): PASS
9101 22:10:58.429839 TX OE : PASS
9102 22:10:58.433473 All Pass.
9103 22:10:58.433551
9104 22:10:58.433613 DramC Write-DBI on
9105 22:10:58.436511 PER_BANK_REFRESH: Hybrid Mode
9106 22:10:58.440113 TX_TRACKING: ON
9107 22:10:58.446817 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9108 22:10:58.457033 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9109 22:10:58.463640 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9110 22:10:58.467151 [FAST_K] Save calibration result to emmc
9111 22:10:58.469928 sync common calibartion params.
9112 22:10:58.470044 sync cbt_mode0:1, 1:1
9113 22:10:58.473353 dram_init: ddr_geometry: 2
9114 22:10:58.476673 dram_init: ddr_geometry: 2
9115 22:10:58.480296 dram_init: ddr_geometry: 2
9116 22:10:58.480375 0:dram_rank_size:100000000
9117 22:10:58.483530 1:dram_rank_size:100000000
9118 22:10:58.490097 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9119 22:10:58.490183 DFS_SHUFFLE_HW_MODE: ON
9120 22:10:58.493217 dramc_set_vcore_voltage set vcore to 725000
9121 22:10:58.496877 Read voltage for 1600, 0
9122 22:10:58.496955 Vio18 = 0
9123 22:10:58.500439 Vcore = 725000
9124 22:10:58.500539 Vdram = 0
9125 22:10:58.500632 Vddq = 0
9126 22:10:58.503817 Vmddr = 0
9127 22:10:58.503913 switch to 3200 Mbps bootup
9128 22:10:58.506937 [DramcRunTimeConfig]
9129 22:10:58.507027 PHYPLL
9130 22:10:58.510137 DPM_CONTROL_AFTERK: ON
9131 22:10:58.510224 PER_BANK_REFRESH: ON
9132 22:10:58.513745 REFRESH_OVERHEAD_REDUCTION: ON
9133 22:10:58.517008 CMD_PICG_NEW_MODE: OFF
9134 22:10:58.517102 XRTWTW_NEW_MODE: ON
9135 22:10:58.520215 XRTRTR_NEW_MODE: ON
9136 22:10:58.520288 TX_TRACKING: ON
9137 22:10:58.523616 RDSEL_TRACKING: OFF
9138 22:10:58.526862 DQS Precalculation for DVFS: ON
9139 22:10:58.526940 RX_TRACKING: OFF
9140 22:10:58.530241 HW_GATING DBG: ON
9141 22:10:58.530312 ZQCS_ENABLE_LP4: ON
9142 22:10:58.533848 RX_PICG_NEW_MODE: ON
9143 22:10:58.533938 TX_PICG_NEW_MODE: ON
9144 22:10:58.537022 ENABLE_RX_DCM_DPHY: ON
9145 22:10:58.539987 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9146 22:10:58.543609 DUMMY_READ_FOR_TRACKING: OFF
9147 22:10:58.543731 !!! SPM_CONTROL_AFTERK: OFF
9148 22:10:58.546798 !!! SPM could not control APHY
9149 22:10:58.550364 IMPEDANCE_TRACKING: ON
9150 22:10:58.550450 TEMP_SENSOR: ON
9151 22:10:58.553520 HW_SAVE_FOR_SR: OFF
9152 22:10:58.556894 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9153 22:10:58.559998 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9154 22:10:58.560080 Read ODT Tracking: ON
9155 22:10:58.563636 Refresh Rate DeBounce: ON
9156 22:10:58.566505 DFS_NO_QUEUE_FLUSH: ON
9157 22:10:58.570044 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9158 22:10:58.570153 ENABLE_DFS_RUNTIME_MRW: OFF
9159 22:10:58.573381 DDR_RESERVE_NEW_MODE: ON
9160 22:10:58.576523 MR_CBT_SWITCH_FREQ: ON
9161 22:10:58.576638 =========================
9162 22:10:58.597091 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9163 22:10:58.600218 dram_init: ddr_geometry: 2
9164 22:10:58.618664 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9165 22:10:58.622191 dram_init: dram init end (result: 0)
9166 22:10:58.628872 DRAM-K: Full calibration passed in 24560 msecs
9167 22:10:58.632022 MRC: failed to locate region type 0.
9168 22:10:58.632105 DRAM rank0 size:0x100000000,
9169 22:10:58.635479 DRAM rank1 size=0x100000000
9170 22:10:58.645252 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9171 22:10:58.651916 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9172 22:10:58.659163 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9173 22:10:58.665783 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9174 22:10:58.669105 DRAM rank0 size:0x100000000,
9175 22:10:58.672141 DRAM rank1 size=0x100000000
9176 22:10:58.672245 CBMEM:
9177 22:10:58.675716 IMD: root @ 0xfffff000 254 entries.
9178 22:10:58.678802 IMD: root @ 0xffffec00 62 entries.
9179 22:10:58.682461 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9180 22:10:58.685600 WARNING: RO_VPD is uninitialized or empty.
9181 22:10:58.692037 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9182 22:10:58.698988 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9183 22:10:58.711802 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9184 22:10:58.722940 BS: romstage times (exec / console): total (unknown) / 24068 ms
9185 22:10:58.723053
9186 22:10:58.723145
9187 22:10:58.733166 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9188 22:10:58.736575 ARM64: Exception handlers installed.
9189 22:10:58.739583 ARM64: Testing exception
9190 22:10:58.742713 ARM64: Done test exception
9191 22:10:58.742815 Enumerating buses...
9192 22:10:58.746193 Show all devs... Before device enumeration.
9193 22:10:58.749315 Root Device: enabled 1
9194 22:10:58.752814 CPU_CLUSTER: 0: enabled 1
9195 22:10:58.752902 CPU: 00: enabled 1
9196 22:10:58.756116 Compare with tree...
9197 22:10:58.756222 Root Device: enabled 1
9198 22:10:58.759877 CPU_CLUSTER: 0: enabled 1
9199 22:10:58.762854 CPU: 00: enabled 1
9200 22:10:58.762930 Root Device scanning...
9201 22:10:58.766292 scan_static_bus for Root Device
9202 22:10:58.769525 CPU_CLUSTER: 0 enabled
9203 22:10:58.773035 scan_static_bus for Root Device done
9204 22:10:58.776358 scan_bus: bus Root Device finished in 8 msecs
9205 22:10:58.776432 done
9206 22:10:58.783164 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9207 22:10:58.786279 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9208 22:10:58.793040 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9209 22:10:58.796304 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9210 22:10:58.800167 Allocating resources...
9211 22:10:58.800241 Reading resources...
9212 22:10:58.803398 Root Device read_resources bus 0 link: 0
9213 22:10:58.806654 DRAM rank0 size:0x100000000,
9214 22:10:58.809955 DRAM rank1 size=0x100000000
9215 22:10:58.813016 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9216 22:10:58.816624 CPU: 00 missing read_resources
9217 22:10:58.819514 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9218 22:10:58.826827 Root Device read_resources bus 0 link: 0 done
9219 22:10:58.826933 Done reading resources.
9220 22:10:58.833282 Show resources in subtree (Root Device)...After reading.
9221 22:10:58.836300 Root Device child on link 0 CPU_CLUSTER: 0
9222 22:10:58.839860 CPU_CLUSTER: 0 child on link 0 CPU: 00
9223 22:10:58.849581 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9224 22:10:58.849673 CPU: 00
9225 22:10:58.853150 Root Device assign_resources, bus 0 link: 0
9226 22:10:58.856266 CPU_CLUSTER: 0 missing set_resources
9227 22:10:58.859947 Root Device assign_resources, bus 0 link: 0 done
9228 22:10:58.863427 Done setting resources.
9229 22:10:58.869453 Show resources in subtree (Root Device)...After assigning values.
9230 22:10:58.872934 Root Device child on link 0 CPU_CLUSTER: 0
9231 22:10:58.876492 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 22:10:58.886156 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 22:10:58.886266 CPU: 00
9234 22:10:58.889772 Done allocating resources.
9235 22:10:58.893492 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9236 22:10:58.896435 Enabling resources...
9237 22:10:58.896535 done.
9238 22:10:58.899422 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9239 22:10:58.903108 Initializing devices...
9240 22:10:58.906700 Root Device init
9241 22:10:58.906796 init hardware done!
9242 22:10:58.909944 0x00000018: ctrlr->caps
9243 22:10:58.910027 52.000 MHz: ctrlr->f_max
9244 22:10:58.912947 0.400 MHz: ctrlr->f_min
9245 22:10:58.916263 0x40ff8080: ctrlr->voltages
9246 22:10:58.916370 sclk: 390625
9247 22:10:58.919732 Bus Width = 1
9248 22:10:58.919810 sclk: 390625
9249 22:10:58.919878 Bus Width = 1
9250 22:10:58.923044 Early init status = 3
9251 22:10:58.926728 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9252 22:10:58.930363 in-header: 03 fc 00 00 01 00 00 00
9253 22:10:58.933984 in-data: 00
9254 22:10:58.937056 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9255 22:10:58.941706 in-header: 03 fd 00 00 00 00 00 00
9256 22:10:58.945255 in-data:
9257 22:10:58.948414 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9258 22:10:58.952502 in-header: 03 fc 00 00 01 00 00 00
9259 22:10:58.955581 in-data: 00
9260 22:10:58.958582 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9261 22:10:58.964579 in-header: 03 fd 00 00 00 00 00 00
9262 22:10:58.967707 in-data:
9263 22:10:58.971401 [SSUSB] Setting up USB HOST controller...
9264 22:10:58.974461 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9265 22:10:58.977729 [SSUSB] phy power-on done.
9266 22:10:58.981038 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9267 22:10:58.987800 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9268 22:10:58.990988 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9269 22:10:58.997874 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9270 22:10:59.004992 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9271 22:10:59.011681 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9272 22:10:59.018201 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9273 22:10:59.024887 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9274 22:10:59.025004 SPM: binary array size = 0x9dc
9275 22:10:59.031377 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9276 22:10:59.038111 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9277 22:10:59.044872 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9278 22:10:59.048371 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9279 22:10:59.051358 configure_display: Starting display init
9280 22:10:59.087523 anx7625_power_on_init: Init interface.
9281 22:10:59.091062 anx7625_disable_pd_protocol: Disabled PD feature.
9282 22:10:59.094886 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9283 22:10:59.122195 anx7625_start_dp_work: Secure OCM version=00
9284 22:10:59.125784 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9285 22:10:59.140443 sp_tx_get_edid_block: EDID Block = 1
9286 22:10:59.242648 Extracted contents:
9287 22:10:59.245901 header: 00 ff ff ff ff ff ff 00
9288 22:10:59.249248 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9289 22:10:59.252871 version: 01 04
9290 22:10:59.256178 basic params: 95 1f 11 78 0a
9291 22:10:59.259719 chroma info: 76 90 94 55 54 90 27 21 50 54
9292 22:10:59.262449 established: 00 00 00
9293 22:10:59.269651 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9294 22:10:59.272592 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9295 22:10:59.279227 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9296 22:10:59.285961 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9297 22:10:59.292588 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9298 22:10:59.296045 extensions: 00
9299 22:10:59.296162 checksum: fb
9300 22:10:59.296253
9301 22:10:59.299651 Manufacturer: IVO Model 57d Serial Number 0
9302 22:10:59.302828 Made week 0 of 2020
9303 22:10:59.303007 EDID version: 1.4
9304 22:10:59.306044 Digital display
9305 22:10:59.309646 6 bits per primary color channel
9306 22:10:59.309718 DisplayPort interface
9307 22:10:59.312572 Maximum image size: 31 cm x 17 cm
9308 22:10:59.312677 Gamma: 220%
9309 22:10:59.316302 Check DPMS levels
9310 22:10:59.319806 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9311 22:10:59.322825 First detailed timing is preferred timing
9312 22:10:59.326024 Established timings supported:
9313 22:10:59.329330 Standard timings supported:
9314 22:10:59.329496 Detailed timings
9315 22:10:59.335860 Hex of detail: 383680a07038204018303c0035ae10000019
9316 22:10:59.339138 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9317 22:10:59.342679 0780 0798 07c8 0820 hborder 0
9318 22:10:59.349207 0438 043b 0447 0458 vborder 0
9319 22:10:59.349294 -hsync -vsync
9320 22:10:59.352769 Did detailed timing
9321 22:10:59.356301 Hex of detail: 000000000000000000000000000000000000
9322 22:10:59.359340 Manufacturer-specified data, tag 0
9323 22:10:59.365964 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9324 22:10:59.366065 ASCII string: InfoVision
9325 22:10:59.372637 Hex of detail: 000000fe00523134304e574635205248200a
9326 22:10:59.372758 ASCII string: R140NWF5 RH
9327 22:10:59.375749 Checksum
9328 22:10:59.375815 Checksum: 0xfb (valid)
9329 22:10:59.383030 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9330 22:10:59.385996 DSI data_rate: 832800000 bps
9331 22:10:59.389066 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9332 22:10:59.392613 anx7625_parse_edid: pixelclock(138800).
9333 22:10:59.399100 hactive(1920), hsync(48), hfp(24), hbp(88)
9334 22:10:59.402510 vactive(1080), vsync(12), vfp(3), vbp(17)
9335 22:10:59.405762 anx7625_dsi_config: config dsi.
9336 22:10:59.412035 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9337 22:10:59.425211 anx7625_dsi_config: success to config DSI
9338 22:10:59.428223 anx7625_dp_start: MIPI phy setup OK.
9339 22:10:59.431444 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9340 22:10:59.435001 mtk_ddp_mode_set invalid vrefresh 60
9341 22:10:59.438772 main_disp_path_setup
9342 22:10:59.438851 ovl_layer_smi_id_en
9343 22:10:59.441649 ovl_layer_smi_id_en
9344 22:10:59.441745 ccorr_config
9345 22:10:59.441836 aal_config
9346 22:10:59.445180 gamma_config
9347 22:10:59.445251 postmask_config
9348 22:10:59.448377 dither_config
9349 22:10:59.451316 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9350 22:10:59.458494 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9351 22:10:59.461777 Root Device init finished in 553 msecs
9352 22:10:59.461872 CPU_CLUSTER: 0 init
9353 22:10:59.471649 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9354 22:10:59.475089 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9355 22:10:59.478607 APU_MBOX 0x190000b0 = 0x10001
9356 22:10:59.482295 APU_MBOX 0x190001b0 = 0x10001
9357 22:10:59.485194 APU_MBOX 0x190005b0 = 0x10001
9358 22:10:59.485332 APU_MBOX 0x190006b0 = 0x10001
9359 22:10:59.491806 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9360 22:10:59.503671 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9361 22:10:59.516450 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9362 22:10:59.523067 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9363 22:10:59.534486 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9364 22:10:59.543523 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9365 22:10:59.547291 CPU_CLUSTER: 0 init finished in 81 msecs
9366 22:10:59.550764 Devices initialized
9367 22:10:59.553613 Show all devs... After init.
9368 22:10:59.553708 Root Device: enabled 1
9369 22:10:59.556920 CPU_CLUSTER: 0: enabled 1
9370 22:10:59.560115 CPU: 00: enabled 1
9371 22:10:59.563766 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9372 22:10:59.566791 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9373 22:10:59.570091 ELOG: NV offset 0x57f000 size 0x1000
9374 22:10:59.576839 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9375 22:10:59.583598 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9376 22:10:59.586791 ELOG: Event(17) added with size 13 at 2023-09-05 22:11:02 UTC
9377 22:10:59.590448 out: cmd=0x121: 03 db 21 01 00 00 00 00
9378 22:10:59.595109 in-header: 03 e7 00 00 2c 00 00 00
9379 22:10:59.608239 in-data: 78 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9380 22:10:59.614709 ELOG: Event(A1) added with size 10 at 2023-09-05 22:11:02 UTC
9381 22:10:59.621479 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9382 22:10:59.628108 ELOG: Event(A0) added with size 9 at 2023-09-05 22:11:02 UTC
9383 22:10:59.631881 elog_add_boot_reason: Logged dev mode boot
9384 22:10:59.635165 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9385 22:10:59.638240 Finalize devices...
9386 22:10:59.638420 Devices finalized
9387 22:10:59.645026 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9388 22:10:59.648687 Writing coreboot table at 0xffe64000
9389 22:10:59.651856 0. 000000000010a000-0000000000113fff: RAMSTAGE
9390 22:10:59.655543 1. 0000000040000000-00000000400fffff: RAM
9391 22:10:59.658344 2. 0000000040100000-000000004032afff: RAMSTAGE
9392 22:10:59.665306 3. 000000004032b000-00000000545fffff: RAM
9393 22:10:59.668688 4. 0000000054600000-000000005465ffff: BL31
9394 22:10:59.671703 5. 0000000054660000-00000000ffe63fff: RAM
9395 22:10:59.675379 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9396 22:10:59.681761 7. 0000000100000000-000000023fffffff: RAM
9397 22:10:59.681880 Passing 5 GPIOs to payload:
9398 22:10:59.688880 NAME | PORT | POLARITY | VALUE
9399 22:10:59.691835 EC in RW | 0x000000aa | low | undefined
9400 22:10:59.695175 EC interrupt | 0x00000005 | low | undefined
9401 22:10:59.702172 TPM interrupt | 0x000000ab | high | undefined
9402 22:10:59.705079 SD card detect | 0x00000011 | high | undefined
9403 22:10:59.711722 speaker enable | 0x00000093 | high | undefined
9404 22:10:59.715227 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9405 22:10:59.718457 in-header: 03 f9 00 00 02 00 00 00
9406 22:10:59.718574 in-data: 02 00
9407 22:10:59.721805 ADC[4]: Raw value=900221 ID=7
9408 22:10:59.725336 ADC[3]: Raw value=213336 ID=1
9409 22:10:59.725417 RAM Code: 0x71
9410 22:10:59.728597 ADC[6]: Raw value=74557 ID=0
9411 22:10:59.732041 ADC[5]: Raw value=211860 ID=1
9412 22:10:59.732131 SKU Code: 0x1
9413 22:10:59.738606 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ae81
9414 22:10:59.742150 coreboot table: 964 bytes.
9415 22:10:59.745255 IMD ROOT 0. 0xfffff000 0x00001000
9416 22:10:59.748899 IMD SMALL 1. 0xffffe000 0x00001000
9417 22:10:59.751886 RO MCACHE 2. 0xffffc000 0x00001104
9418 22:10:59.755568 CONSOLE 3. 0xfff7c000 0x00080000
9419 22:10:59.755648 FMAP 4. 0xfff7b000 0x00000452
9420 22:10:59.758488 TIME STAMP 5. 0xfff7a000 0x00000910
9421 22:10:59.762145 VBOOT WORK 6. 0xfff66000 0x00014000
9422 22:10:59.765479 RAMOOPS 7. 0xffe66000 0x00100000
9423 22:10:59.769003 COREBOOT 8. 0xffe64000 0x00002000
9424 22:10:59.771833 IMD small region:
9425 22:10:59.775344 IMD ROOT 0. 0xffffec00 0x00000400
9426 22:10:59.778843 VPD 1. 0xffffeb80 0x0000006c
9427 22:10:59.782364 MMC STATUS 2. 0xffffeb60 0x00000004
9428 22:10:59.788584 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9429 22:10:59.788695 Probing TPM: done!
9430 22:10:59.795860 Connected to device vid:did:rid of 1ae0:0028:00
9431 22:10:59.802543 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9432 22:10:59.805806 Initialized TPM device CR50 revision 0
9433 22:10:59.808964 Checking cr50 for pending updates
9434 22:10:59.814506 Reading cr50 TPM mode
9435 22:10:59.822953 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9436 22:10:59.829501 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9437 22:10:59.869641 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9438 22:10:59.873297 Checking segment from ROM address 0x40100000
9439 22:10:59.876892 Checking segment from ROM address 0x4010001c
9440 22:10:59.883175 Loading segment from ROM address 0x40100000
9441 22:10:59.883253 code (compression=0)
9442 22:10:59.889997 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9443 22:10:59.899920 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9444 22:10:59.900004 it's not compressed!
9445 22:10:59.906599 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9446 22:10:59.910063 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9447 22:10:59.930268 Loading segment from ROM address 0x4010001c
9448 22:10:59.930385 Entry Point 0x80000000
9449 22:10:59.934032 Loaded segments
9450 22:10:59.937041 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9451 22:10:59.943729 Jumping to boot code at 0x80000000(0xffe64000)
9452 22:10:59.950725 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9453 22:10:59.956851 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9454 22:10:59.964847 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9455 22:10:59.968006 Checking segment from ROM address 0x40100000
9456 22:10:59.971464 Checking segment from ROM address 0x4010001c
9457 22:10:59.975072 Loading segment from ROM address 0x40100000
9458 22:10:59.978004 code (compression=1)
9459 22:10:59.985043 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9460 22:10:59.994622 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9461 22:10:59.994735 using LZMA
9462 22:11:00.003307 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9463 22:11:00.010085 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9464 22:11:00.013145 Loading segment from ROM address 0x4010001c
9465 22:11:00.013224 Entry Point 0x54601000
9466 22:11:00.016430 Loaded segments
9467 22:11:00.019940 NOTICE: MT8192 bl31_setup
9468 22:11:00.026928 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9469 22:11:00.029853 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9470 22:11:00.033527 WARNING: region 0:
9471 22:11:00.036603 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 22:11:00.036739 WARNING: region 1:
9473 22:11:00.043404 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9474 22:11:00.043483 WARNING: region 2:
9475 22:11:00.050329 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9476 22:11:00.053566 WARNING: region 3:
9477 22:11:00.057005 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9478 22:11:00.060604 WARNING: region 4:
9479 22:11:00.063639 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 22:11:00.067228 WARNING: region 5:
9481 22:11:00.070229 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 22:11:00.073679 WARNING: region 6:
9483 22:11:00.076852 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 22:11:00.076933 WARNING: region 7:
9485 22:11:00.083498 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 22:11:00.090476 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9487 22:11:00.093936 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9488 22:11:00.097113 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9489 22:11:00.100582 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9490 22:11:00.107363 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9491 22:11:00.110614 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9492 22:11:00.117044 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9493 22:11:00.120658 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9494 22:11:00.123878 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9495 22:11:00.130624 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9496 22:11:00.134206 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9497 22:11:00.137364 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9498 22:11:00.144576 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9499 22:11:00.147564 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9500 22:11:00.150923 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9501 22:11:00.157366 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9502 22:11:00.160871 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9503 22:11:00.167627 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9504 22:11:00.171199 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9505 22:11:00.174298 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9506 22:11:00.180762 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9507 22:11:00.184369 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9508 22:11:00.187890 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9509 22:11:00.194505 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9510 22:11:00.197665 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9511 22:11:00.204641 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9512 22:11:00.208098 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9513 22:11:00.211301 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9514 22:11:00.218244 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9515 22:11:00.221276 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9516 22:11:00.224566 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9517 22:11:00.231269 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9518 22:11:00.235210 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9519 22:11:00.238311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9520 22:11:00.241768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9521 22:11:00.248581 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9522 22:11:00.252070 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9523 22:11:00.254876 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9524 22:11:00.258460 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9525 22:11:00.265048 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9526 22:11:00.268522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9527 22:11:00.271896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9528 22:11:00.275162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9529 22:11:00.281927 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9530 22:11:00.285283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9531 22:11:00.288861 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9532 22:11:00.292355 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9533 22:11:00.298682 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9534 22:11:00.302536 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9535 22:11:00.305784 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9536 22:11:00.312315 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9537 22:11:00.315798 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9538 22:11:00.322536 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9539 22:11:00.326139 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9540 22:11:00.332485 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9541 22:11:00.335874 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9542 22:11:00.338876 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9543 22:11:00.345565 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9544 22:11:00.349263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9545 22:11:00.355706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9546 22:11:00.359192 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9547 22:11:00.365780 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9548 22:11:00.369160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9549 22:11:00.372881 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9550 22:11:00.379772 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9551 22:11:00.383162 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9552 22:11:00.389538 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9553 22:11:00.392390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9554 22:11:00.399627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9555 22:11:00.402610 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9556 22:11:00.406061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9557 22:11:00.412974 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9558 22:11:00.416341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9559 22:11:00.422797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9560 22:11:00.426262 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9561 22:11:00.429511 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9562 22:11:00.436318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9563 22:11:00.440021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9564 22:11:00.446469 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9565 22:11:00.450045 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9566 22:11:00.457180 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9567 22:11:00.460192 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9568 22:11:00.463677 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9569 22:11:00.470100 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9570 22:11:00.473967 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9571 22:11:00.480136 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9572 22:11:00.483832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9573 22:11:00.487107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9574 22:11:00.493677 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9575 22:11:00.497219 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9576 22:11:00.503950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9577 22:11:00.507007 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9578 22:11:00.510775 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9579 22:11:00.517351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9580 22:11:00.520767 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9581 22:11:00.526985 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9582 22:11:00.530606 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9583 22:11:00.534225 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9584 22:11:00.537606 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9585 22:11:00.544111 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9586 22:11:00.547721 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9587 22:11:00.550997 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9588 22:11:00.557493 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9589 22:11:00.561074 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9590 22:11:00.567745 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9591 22:11:00.570722 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9592 22:11:00.574465 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9593 22:11:00.581360 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9594 22:11:00.584500 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9595 22:11:00.591548 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9596 22:11:00.594891 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9597 22:11:00.597938 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9598 22:11:00.604525 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9599 22:11:00.608024 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9600 22:11:00.611751 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9601 22:11:00.617836 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9602 22:11:00.621576 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9603 22:11:00.624758 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9604 22:11:00.631663 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9605 22:11:00.635046 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9606 22:11:00.638053 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9607 22:11:00.641836 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9608 22:11:00.644771 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9609 22:11:00.651820 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9610 22:11:00.655018 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9611 22:11:00.658558 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9612 22:11:00.665324 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9613 22:11:00.668838 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9614 22:11:00.675480 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9615 22:11:00.678990 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9616 22:11:00.681927 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9617 22:11:00.688899 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9618 22:11:00.692337 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9619 22:11:00.695256 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9620 22:11:00.702408 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9621 22:11:00.705389 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9622 22:11:00.712358 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9623 22:11:00.715672 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9624 22:11:00.718861 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9625 22:11:00.726191 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9626 22:11:00.729108 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9627 22:11:00.732766 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9628 22:11:00.739465 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9629 22:11:00.742595 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9630 22:11:00.749280 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9631 22:11:00.752959 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9632 22:11:00.756025 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9633 22:11:00.762647 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9634 22:11:00.766162 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9635 22:11:00.769390 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9636 22:11:00.776282 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9637 22:11:00.779905 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9638 22:11:00.782948 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9639 22:11:00.789553 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9640 22:11:00.792992 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9641 22:11:00.799686 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9642 22:11:00.803024 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9643 22:11:00.806794 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9644 22:11:00.812972 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9645 22:11:00.816388 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9646 22:11:00.823121 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9647 22:11:00.826737 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9648 22:11:00.829760 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9649 22:11:00.836964 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9650 22:11:00.839962 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9651 22:11:00.843564 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9652 22:11:00.850260 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9653 22:11:00.853081 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9654 22:11:00.859983 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9655 22:11:00.863464 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9656 22:11:00.866507 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9657 22:11:00.873212 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9658 22:11:00.876601 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9659 22:11:00.880140 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9660 22:11:00.886754 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9661 22:11:00.890103 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9662 22:11:00.896855 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9663 22:11:00.900329 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9664 22:11:00.903309 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9665 22:11:00.909954 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9666 22:11:00.913211 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9667 22:11:00.920375 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9668 22:11:00.923381 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9669 22:11:00.926505 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9670 22:11:00.933355 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9671 22:11:00.936811 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9672 22:11:00.940266 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9673 22:11:00.946506 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9674 22:11:00.950134 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9675 22:11:00.956741 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9676 22:11:00.959888 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9677 22:11:00.967050 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9678 22:11:00.970219 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9679 22:11:00.973243 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9680 22:11:00.979905 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9681 22:11:00.983649 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9682 22:11:00.990059 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9683 22:11:00.993686 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9684 22:11:00.996860 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9685 22:11:01.003590 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9686 22:11:01.006639 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9687 22:11:01.013596 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9688 22:11:01.016791 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9689 22:11:01.020380 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9690 22:11:01.026997 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9691 22:11:01.030300 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9692 22:11:01.036662 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9693 22:11:01.040225 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9694 22:11:01.043596 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9695 22:11:01.050266 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9696 22:11:01.053886 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9697 22:11:01.060399 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9698 22:11:01.063667 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9699 22:11:01.069989 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9700 22:11:01.073726 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9701 22:11:01.076956 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9702 22:11:01.083686 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9703 22:11:01.087284 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9704 22:11:01.093858 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9705 22:11:01.097253 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9706 22:11:01.100184 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9707 22:11:01.106791 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9708 22:11:01.110160 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9709 22:11:01.117013 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9710 22:11:01.120317 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9711 22:11:01.123704 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9712 22:11:01.130359 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9713 22:11:01.133788 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9714 22:11:01.140388 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9715 22:11:01.143590 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9716 22:11:01.146770 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9717 22:11:01.150301 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9718 22:11:01.153734 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9719 22:11:01.160371 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9720 22:11:01.164094 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9721 22:11:01.166850 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9722 22:11:01.174113 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9723 22:11:01.177121 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9724 22:11:01.180258 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9725 22:11:01.186982 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9726 22:11:01.190677 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9727 22:11:01.197223 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9728 22:11:01.200488 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9729 22:11:01.203927 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9730 22:11:01.210473 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9731 22:11:01.213912 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9732 22:11:01.217391 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9733 22:11:01.223877 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9734 22:11:01.227464 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9735 22:11:01.231154 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9736 22:11:01.237638 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9737 22:11:01.240641 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9738 22:11:01.247443 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9739 22:11:01.250632 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9740 22:11:01.254208 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9741 22:11:01.260901 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9742 22:11:01.264374 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9743 22:11:01.267734 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9744 22:11:01.274006 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9745 22:11:01.277597 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9746 22:11:01.280856 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9747 22:11:01.287412 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9748 22:11:01.291135 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9749 22:11:01.294176 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9750 22:11:01.300857 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9751 22:11:01.304507 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9752 22:11:01.307825 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9753 22:11:01.314708 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9754 22:11:01.317466 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9755 22:11:01.321008 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9756 22:11:01.327655 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9757 22:11:01.330786 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9758 22:11:01.334516 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9759 22:11:01.337783 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9760 22:11:01.341021 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9761 22:11:01.347646 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9762 22:11:01.351037 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9763 22:11:01.354381 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9764 22:11:01.357750 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9765 22:11:01.364255 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9766 22:11:01.367794 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9767 22:11:01.370892 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9768 22:11:01.377948 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9769 22:11:01.380889 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9770 22:11:01.384605 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9771 22:11:01.390883 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9772 22:11:01.394452 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9773 22:11:01.400893 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9774 22:11:01.404336 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9775 22:11:01.407940 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9776 22:11:01.414542 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9777 22:11:01.417936 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9778 22:11:01.424278 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9779 22:11:01.427918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9780 22:11:01.434571 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9781 22:11:01.437832 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9782 22:11:01.441297 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9783 22:11:01.447567 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9784 22:11:01.451040 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9785 22:11:01.454534 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9786 22:11:01.461095 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9787 22:11:01.464589 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9788 22:11:01.471034 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9789 22:11:01.474309 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9790 22:11:01.481452 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9791 22:11:01.484574 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9792 22:11:01.488100 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9793 22:11:01.494647 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9794 22:11:01.497996 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9795 22:11:01.501347 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9796 22:11:01.508084 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9797 22:11:01.511612 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9798 22:11:01.518335 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9799 22:11:01.521551 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9800 22:11:01.525003 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9801 22:11:01.531507 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9802 22:11:01.534536 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9803 22:11:01.541245 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9804 22:11:01.544813 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9805 22:11:01.551465 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9806 22:11:01.554788 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9807 22:11:01.558051 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9808 22:11:01.564587 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9809 22:11:01.568326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9810 22:11:01.571219 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9811 22:11:01.578150 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9812 22:11:01.581363 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9813 22:11:01.588142 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9814 22:11:01.591677 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9815 22:11:01.594644 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9816 22:11:01.601764 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9817 22:11:01.604892 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9818 22:11:01.611600 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9819 22:11:01.614862 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9820 22:11:01.621205 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9821 22:11:01.625003 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9822 22:11:01.627992 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9823 22:11:01.634712 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9824 22:11:01.637881 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9825 22:11:01.641603 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9826 22:11:01.648175 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9827 22:11:01.651171 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9828 22:11:01.658542 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9829 22:11:01.661364 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9830 22:11:01.668052 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9831 22:11:01.671755 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9832 22:11:01.674742 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9833 22:11:01.681308 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9834 22:11:01.685093 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9835 22:11:01.687986 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9836 22:11:01.694980 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9837 22:11:01.698618 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9838 22:11:01.704821 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9839 22:11:01.708466 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9840 22:11:01.714965 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9841 22:11:01.717944 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9842 22:11:01.721443 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9843 22:11:01.728087 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9844 22:11:01.731768 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9845 22:11:01.738461 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9846 22:11:01.741320 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9847 22:11:01.744650 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9848 22:11:01.751774 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9849 22:11:01.754667 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9850 22:11:01.761216 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9851 22:11:01.764605 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9852 22:11:01.771256 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9853 22:11:01.774699 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9854 22:11:01.781301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9855 22:11:01.784849 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9856 22:11:01.787965 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9857 22:11:01.795114 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9858 22:11:01.798230 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9859 22:11:01.804597 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9860 22:11:01.807905 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9861 22:11:01.815091 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9862 22:11:01.817937 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9863 22:11:01.821615 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9864 22:11:01.828211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9865 22:11:01.831252 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9866 22:11:01.838018 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9867 22:11:01.841505 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9868 22:11:01.848273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9869 22:11:01.851322 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9870 22:11:01.854620 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9871 22:11:01.861486 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9872 22:11:01.865204 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9873 22:11:01.871605 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9874 22:11:01.875186 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9875 22:11:01.878600 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9876 22:11:01.884726 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9877 22:11:01.888536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9878 22:11:01.895071 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9879 22:11:01.898064 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9880 22:11:01.904793 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9881 22:11:01.908479 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9882 22:11:01.911739 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9883 22:11:01.918247 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9884 22:11:01.921522 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9885 22:11:01.928618 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9886 22:11:01.931497 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9887 22:11:01.938193 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9888 22:11:01.941892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9889 22:11:01.945352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9890 22:11:01.951927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9891 22:11:01.954958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9892 22:11:01.962317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9893 22:11:01.965229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9894 22:11:01.971606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9895 22:11:01.975259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9896 22:11:01.981937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9897 22:11:01.985286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9898 22:11:01.991886 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9899 22:11:01.995529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9900 22:11:01.998620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9901 22:11:02.005337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9902 22:11:02.008896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9903 22:11:02.015461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9904 22:11:02.018460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9905 22:11:02.025265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9906 22:11:02.028598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9907 22:11:02.035439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9908 22:11:02.038751 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9909 22:11:02.045548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9910 22:11:02.048473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9911 22:11:02.055832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9912 22:11:02.058660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9913 22:11:02.065684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9914 22:11:02.068794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9915 22:11:02.075265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9916 22:11:02.078493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9917 22:11:02.085466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9918 22:11:02.088350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9919 22:11:02.095470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9920 22:11:02.098717 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9921 22:11:02.102101 INFO: [APUAPC] vio 0
9922 22:11:02.105674 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9923 22:11:02.108765 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9924 22:11:02.111818 INFO: [APUAPC] D0_APC_0: 0x400510
9925 22:11:02.115780 INFO: [APUAPC] D0_APC_1: 0x0
9926 22:11:02.118859 INFO: [APUAPC] D0_APC_2: 0x1540
9927 22:11:02.122352 INFO: [APUAPC] D0_APC_3: 0x0
9928 22:11:02.125353 INFO: [APUAPC] D1_APC_0: 0xffffffff
9929 22:11:02.128797 INFO: [APUAPC] D1_APC_1: 0xffffffff
9930 22:11:02.132040 INFO: [APUAPC] D1_APC_2: 0x3fffff
9931 22:11:02.135454 INFO: [APUAPC] D1_APC_3: 0x0
9932 22:11:02.138995 INFO: [APUAPC] D2_APC_0: 0xffffffff
9933 22:11:02.142071 INFO: [APUAPC] D2_APC_1: 0xffffffff
9934 22:11:02.145473 INFO: [APUAPC] D2_APC_2: 0x3fffff
9935 22:11:02.149111 INFO: [APUAPC] D2_APC_3: 0x0
9936 22:11:02.151941 INFO: [APUAPC] D3_APC_0: 0xffffffff
9937 22:11:02.155678 INFO: [APUAPC] D3_APC_1: 0xffffffff
9938 22:11:02.158686 INFO: [APUAPC] D3_APC_2: 0x3fffff
9939 22:11:02.162500 INFO: [APUAPC] D3_APC_3: 0x0
9940 22:11:02.165342 INFO: [APUAPC] D4_APC_0: 0xffffffff
9941 22:11:02.168956 INFO: [APUAPC] D4_APC_1: 0xffffffff
9942 22:11:02.172418 INFO: [APUAPC] D4_APC_2: 0x3fffff
9943 22:11:02.175685 INFO: [APUAPC] D4_APC_3: 0x0
9944 22:11:02.178807 INFO: [APUAPC] D5_APC_0: 0xffffffff
9945 22:11:02.182010 INFO: [APUAPC] D5_APC_1: 0xffffffff
9946 22:11:02.185750 INFO: [APUAPC] D5_APC_2: 0x3fffff
9947 22:11:02.188863 INFO: [APUAPC] D5_APC_3: 0x0
9948 22:11:02.192522 INFO: [APUAPC] D6_APC_0: 0xffffffff
9949 22:11:02.195696 INFO: [APUAPC] D6_APC_1: 0xffffffff
9950 22:11:02.199254 INFO: [APUAPC] D6_APC_2: 0x3fffff
9951 22:11:02.199335 INFO: [APUAPC] D6_APC_3: 0x0
9952 22:11:02.202142 INFO: [APUAPC] D7_APC_0: 0xffffffff
9953 22:11:02.205933 INFO: [APUAPC] D7_APC_1: 0xffffffff
9954 22:11:02.209302 INFO: [APUAPC] D7_APC_2: 0x3fffff
9955 22:11:02.212367 INFO: [APUAPC] D7_APC_3: 0x0
9956 22:11:02.215814 INFO: [APUAPC] D8_APC_0: 0xffffffff
9957 22:11:02.218699 INFO: [APUAPC] D8_APC_1: 0xffffffff
9958 22:11:02.222381 INFO: [APUAPC] D8_APC_2: 0x3fffff
9959 22:11:02.225516 INFO: [APUAPC] D8_APC_3: 0x0
9960 22:11:02.229093 INFO: [APUAPC] D9_APC_0: 0xffffffff
9961 22:11:02.232580 INFO: [APUAPC] D9_APC_1: 0xffffffff
9962 22:11:02.235499 INFO: [APUAPC] D9_APC_2: 0x3fffff
9963 22:11:02.238734 INFO: [APUAPC] D9_APC_3: 0x0
9964 22:11:02.242104 INFO: [APUAPC] D10_APC_0: 0xffffffff
9965 22:11:02.245780 INFO: [APUAPC] D10_APC_1: 0xffffffff
9966 22:11:02.249264 INFO: [APUAPC] D10_APC_2: 0x3fffff
9967 22:11:02.252179 INFO: [APUAPC] D10_APC_3: 0x0
9968 22:11:02.255500 INFO: [APUAPC] D11_APC_0: 0xffffffff
9969 22:11:02.259174 INFO: [APUAPC] D11_APC_1: 0xffffffff
9970 22:11:02.262186 INFO: [APUAPC] D11_APC_2: 0x3fffff
9971 22:11:02.265639 INFO: [APUAPC] D11_APC_3: 0x0
9972 22:11:02.269306 INFO: [APUAPC] D12_APC_0: 0xffffffff
9973 22:11:02.272790 INFO: [APUAPC] D12_APC_1: 0xffffffff
9974 22:11:02.275909 INFO: [APUAPC] D12_APC_2: 0x3fffff
9975 22:11:02.279031 INFO: [APUAPC] D12_APC_3: 0x0
9976 22:11:02.282973 INFO: [APUAPC] D13_APC_0: 0xffffffff
9977 22:11:02.285943 INFO: [APUAPC] D13_APC_1: 0xffffffff
9978 22:11:02.289108 INFO: [APUAPC] D13_APC_2: 0x3fffff
9979 22:11:02.292605 INFO: [APUAPC] D13_APC_3: 0x0
9980 22:11:02.296091 INFO: [APUAPC] D14_APC_0: 0xffffffff
9981 22:11:02.299483 INFO: [APUAPC] D14_APC_1: 0xffffffff
9982 22:11:02.302804 INFO: [APUAPC] D14_APC_2: 0x3fffff
9983 22:11:02.306448 INFO: [APUAPC] D14_APC_3: 0x0
9984 22:11:02.309379 INFO: [APUAPC] D15_APC_0: 0xffffffff
9985 22:11:02.313368 INFO: [APUAPC] D15_APC_1: 0xffffffff
9986 22:11:02.316130 INFO: [APUAPC] D15_APC_2: 0x3fffff
9987 22:11:02.319326 INFO: [APUAPC] D15_APC_3: 0x0
9988 22:11:02.322826 INFO: [APUAPC] APC_CON: 0x4
9989 22:11:02.326338 INFO: [NOCDAPC] D0_APC_0: 0x0
9990 22:11:02.329423 INFO: [NOCDAPC] D0_APC_1: 0x0
9991 22:11:02.329496 INFO: [NOCDAPC] D1_APC_0: 0x0
9992 22:11:02.333223 INFO: [NOCDAPC] D1_APC_1: 0xfff
9993 22:11:02.336074 INFO: [NOCDAPC] D2_APC_0: 0x0
9994 22:11:02.339480 INFO: [NOCDAPC] D2_APC_1: 0xfff
9995 22:11:02.342908 INFO: [NOCDAPC] D3_APC_0: 0x0
9996 22:11:02.346245 INFO: [NOCDAPC] D3_APC_1: 0xfff
9997 22:11:02.349655 INFO: [NOCDAPC] D4_APC_0: 0x0
9998 22:11:02.352957 INFO: [NOCDAPC] D4_APC_1: 0xfff
9999 22:11:02.356760 INFO: [NOCDAPC] D5_APC_0: 0x0
10000 22:11:02.359531 INFO: [NOCDAPC] D5_APC_1: 0xfff
10001 22:11:02.359614 INFO: [NOCDAPC] D6_APC_0: 0x0
10002 22:11:02.362725 INFO: [NOCDAPC] D6_APC_1: 0xfff
10003 22:11:02.366138 INFO: [NOCDAPC] D7_APC_0: 0x0
10004 22:11:02.369892 INFO: [NOCDAPC] D7_APC_1: 0xfff
10005 22:11:02.372879 INFO: [NOCDAPC] D8_APC_0: 0x0
10006 22:11:02.376621 INFO: [NOCDAPC] D8_APC_1: 0xfff
10007 22:11:02.379462 INFO: [NOCDAPC] D9_APC_0: 0x0
10008 22:11:02.383206 INFO: [NOCDAPC] D9_APC_1: 0xfff
10009 22:11:02.386558 INFO: [NOCDAPC] D10_APC_0: 0x0
10010 22:11:02.389537 INFO: [NOCDAPC] D10_APC_1: 0xfff
10011 22:11:02.393088 INFO: [NOCDAPC] D11_APC_0: 0x0
10012 22:11:02.396362 INFO: [NOCDAPC] D11_APC_1: 0xfff
10013 22:11:02.396444 INFO: [NOCDAPC] D12_APC_0: 0x0
10014 22:11:02.399649 INFO: [NOCDAPC] D12_APC_1: 0xfff
10015 22:11:02.402764 INFO: [NOCDAPC] D13_APC_0: 0x0
10016 22:11:02.406310 INFO: [NOCDAPC] D13_APC_1: 0xfff
10017 22:11:02.409853 INFO: [NOCDAPC] D14_APC_0: 0x0
10018 22:11:02.413082 INFO: [NOCDAPC] D14_APC_1: 0xfff
10019 22:11:02.416561 INFO: [NOCDAPC] D15_APC_0: 0x0
10020 22:11:02.419809 INFO: [NOCDAPC] D15_APC_1: 0xfff
10021 22:11:02.422953 INFO: [NOCDAPC] APC_CON: 0x4
10022 22:11:02.426257 INFO: [APUAPC] set_apusys_apc done
10023 22:11:02.429369 INFO: [DEVAPC] devapc_init done
10024 22:11:02.432966 INFO: GICv3 without legacy support detected.
10025 22:11:02.436370 INFO: ARM GICv3 driver initialized in EL3
10026 22:11:02.439905 INFO: Maximum SPI INTID supported: 639
10027 22:11:02.443671 INFO: BL31: Initializing runtime services
10028 22:11:02.449566 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10029 22:11:02.452870 INFO: SPM: enable CPC mode
10030 22:11:02.459949 INFO: mcdi ready for mcusys-off-idle and system suspend
10031 22:11:02.463480 INFO: BL31: Preparing for EL3 exit to normal world
10032 22:11:02.466723 INFO: Entry point address = 0x80000000
10033 22:11:02.469686 INFO: SPSR = 0x8
10034 22:11:02.474528
10035 22:11:02.474601
10036 22:11:02.474667
10037 22:11:02.477648 Starting depthcharge on Spherion...
10038 22:11:02.477716
10039 22:11:02.477773 Wipe memory regions:
10040 22:11:02.477832
10041 22:11:02.478490 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10042 22:11:02.478585 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10043 22:11:02.478664 Setting prompt string to ['asurada:']
10044 22:11:02.478740 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10045 22:11:02.481442 [0x00000040000000, 0x00000054600000)
10046 22:11:02.603240
10047 22:11:02.603375 [0x00000054660000, 0x00000080000000)
10048 22:11:02.864284
10049 22:11:02.864430 [0x000000821a7280, 0x000000ffe64000)
10050 22:11:03.608053
10051 22:11:03.608186 [0x00000100000000, 0x00000240000000)
10052 22:11:05.496738
10053 22:11:05.499891 Initializing XHCI USB controller at 0x11200000.
10054 22:11:06.538430
10055 22:11:06.541600 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10056 22:11:06.541699
10057 22:11:06.541773
10058 22:11:06.541836
10059 22:11:06.542123 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 22:11:06.642438 asurada: tftpboot 192.168.201.1 11440302/tftp-deploy-3bltm57_/kernel/image.itb 11440302/tftp-deploy-3bltm57_/kernel/cmdline
10062 22:11:06.642565 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 22:11:06.642648 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10064 22:11:06.646671 tftpboot 192.168.201.1 11440302/tftp-deploy-3bltm57_/kernel/image.ittp-deploy-3bltm57_/kernel/cmdline
10065 22:11:06.646753
10066 22:11:06.646817 Waiting for link
10067 22:11:06.807373
10068 22:11:06.807516 R8152: Initializing
10069 22:11:06.807584
10070 22:11:06.810611 Version 6 (ocp_data = 5c30)
10071 22:11:06.810706
10072 22:11:06.813897 R8152: Done initializing
10073 22:11:06.813978
10074 22:11:06.814042 Adding net device
10075 22:11:08.905417
10076 22:11:08.905563 done.
10077 22:11:08.905630
10078 22:11:08.905691 MAC: 00:24:32:30:78:52
10079 22:11:08.905748
10080 22:11:08.908887 Sending DHCP discover... done.
10081 22:11:08.908968
10082 22:11:17.265399 Waiting for reply... done.
10083 22:11:17.265554
10084 22:11:17.265655 Sending DHCP request... done.
10085 22:11:17.269062
10086 22:11:17.269146 Waiting for reply... done.
10087 22:11:17.269212
10088 22:11:17.272015 My ip is 192.168.201.14
10089 22:11:17.272097
10090 22:11:17.275397 The DHCP server ip is 192.168.201.1
10091 22:11:17.275479
10092 22:11:17.278878 TFTP server IP predefined by user: 192.168.201.1
10093 22:11:17.278960
10094 22:11:17.285851 Bootfile predefined by user: 11440302/tftp-deploy-3bltm57_/kernel/image.itb
10095 22:11:17.285949
10096 22:11:17.288690 Sending tftp read request... done.
10097 22:11:17.288796
10098 22:11:17.292063 Waiting for the transfer...
10099 22:11:17.292207
10100 22:11:17.894137 00000000 ################################################################
10101 22:11:17.894335
10102 22:11:18.495361 00080000 ################################################################
10103 22:11:18.495516
10104 22:11:19.061263 00100000 ################################################################
10105 22:11:19.061396
10106 22:11:19.673049 00180000 ################################################################
10107 22:11:19.673539
10108 22:11:20.295853 00200000 ################################################################
10109 22:11:20.295983
10110 22:11:20.886752 00280000 ################################################################
10111 22:11:20.886912
10112 22:11:21.508943 00300000 ################################################################
10113 22:11:21.509079
10114 22:11:22.029793 00380000 ################################################################
10115 22:11:22.029945
10116 22:11:22.552918 00400000 ################################################################
10117 22:11:22.553064
10118 22:11:23.085207 00480000 ################################################################
10119 22:11:23.085354
10120 22:11:23.731415 00500000 ################################################################
10121 22:11:23.731920
10122 22:11:24.290856 00580000 ################################################################
10123 22:11:24.290992
10124 22:11:24.920040 00600000 ################################################################
10125 22:11:24.920852
10126 22:11:25.575790 00680000 ################################################################
10127 22:11:25.576293
10128 22:11:26.143239 00700000 ################################################################
10129 22:11:26.143388
10130 22:11:26.751704 00780000 ################################################################
10131 22:11:26.752358
10132 22:11:27.324093 00800000 ################################################################
10133 22:11:27.324240
10134 22:11:27.875724 00880000 ################################################################
10135 22:11:27.875880
10136 22:11:28.493825 00900000 ################################################################
10137 22:11:28.493954
10138 22:11:29.098665 00980000 ################################################################
10139 22:11:29.099171
10140 22:11:29.673078 00a00000 ################################################################
10141 22:11:29.673646
10142 22:11:30.253159 00a80000 ################################################################
10143 22:11:30.253315
10144 22:11:30.868480 00b00000 ################################################################
10145 22:11:30.868627
10146 22:11:31.472051 00b80000 ################################################################
10147 22:11:31.472192
10148 22:11:32.123249 00c00000 ################################################################
10149 22:11:32.123765
10150 22:11:32.784720 00c80000 ################################################################
10151 22:11:32.785221
10152 22:11:33.455873 00d00000 ################################################################
10153 22:11:33.456359
10154 22:11:34.121734 00d80000 ################################################################
10155 22:11:34.122294
10156 22:11:34.758951 00e00000 ################################################################
10157 22:11:34.759448
10158 22:11:35.358986 00e80000 ################################################################
10159 22:11:35.359487
10160 22:11:36.010568 00f00000 ################################################################
10161 22:11:36.011056
10162 22:11:36.672991 00f80000 ################################################################
10163 22:11:36.673492
10164 22:11:37.285602 01000000 ################################################################
10165 22:11:37.285738
10166 22:11:37.926378 01080000 ################################################################
10167 22:11:37.926971
10168 22:11:38.582405 01100000 ################################################################
10169 22:11:38.582900
10170 22:11:39.253792 01180000 ################################################################
10171 22:11:39.254069
10172 22:11:39.875873 01200000 ################################################################
10173 22:11:39.876040
10174 22:11:40.492360 01280000 ################################################################
10175 22:11:40.492913
10176 22:11:41.122826 01300000 ################################################################
10177 22:11:41.122963
10178 22:11:41.749736 01380000 ################################################################
10179 22:11:41.750240
10180 22:11:42.366916 01400000 ################################################################
10181 22:11:42.367250
10182 22:11:43.029238 01480000 ################################################################
10183 22:11:43.029743
10184 22:11:43.674575 01500000 ################################################################
10185 22:11:43.675148
10186 22:11:44.308464 01580000 ################################################################
10187 22:11:44.308619
10188 22:11:44.983572 01600000 ################################################################
10189 22:11:44.984268
10190 22:11:45.599993 01680000 ################################################################
10191 22:11:45.600496
10192 22:11:46.253666 01700000 ################################################################
10193 22:11:46.253851
10194 22:11:46.890998 01780000 ################################################################
10195 22:11:46.891150
10196 22:11:47.506329 01800000 ################################################################
10197 22:11:47.506848
10198 22:11:48.138397 01880000 ################################################################
10199 22:11:48.138909
10200 22:11:48.781135 01900000 ################################################################
10201 22:11:48.781684
10202 22:11:49.419264 01980000 ################################################################
10203 22:11:49.419782
10204 22:11:50.073202 01a00000 ################################################################
10205 22:11:50.073735
10206 22:11:50.667644 01a80000 ################################################################
10207 22:11:50.667865
10208 22:11:51.327517 01b00000 ################################################################
10209 22:11:51.328052
10210 22:11:51.950003 01b80000 ################################################################
10211 22:11:51.950153
10212 22:11:52.546275 01c00000 ################################################################
10213 22:11:52.546430
10214 22:11:53.210422 01c80000 ################################################################
10215 22:11:53.211097
10216 22:11:53.874976 01d00000 ################################################################
10217 22:11:53.875491
10218 22:11:54.545016 01d80000 ################################################################
10219 22:11:54.545529
10220 22:11:55.188574 01e00000 ################################################################
10221 22:11:55.189194
10222 22:11:55.821631 01e80000 ################################################################
10223 22:11:55.822125
10224 22:11:56.475169 01f00000 ################################################################
10225 22:11:56.475677
10226 22:11:57.149027 01f80000 ################################################################
10227 22:11:57.149565
10228 22:11:57.765236 02000000 ################################################################
10229 22:11:57.765375
10230 22:11:58.337524 02080000 ################################################################
10231 22:11:58.338007
10232 22:11:58.926224 02100000 ################################################################
10233 22:11:58.926761
10234 22:11:59.527805 02180000 ################################################################
10235 22:11:59.528355
10236 22:12:00.196230 02200000 ################################################################
10237 22:12:00.196815
10238 22:12:00.857328 02280000 ################################################################
10239 22:12:00.857847
10240 22:12:01.513562 02300000 ################################################################
10241 22:12:01.514089
10242 22:12:02.143103 02380000 ################################################################
10243 22:12:02.143414
10244 22:12:02.770197 02400000 ################################################################
10245 22:12:02.770743
10246 22:12:03.399612 02480000 ################################################################
10247 22:12:03.400113
10248 22:12:04.049786 02500000 ################################################################
10249 22:12:04.050270
10250 22:12:04.708238 02580000 ################################################################
10251 22:12:04.708820
10252 22:12:05.349614 02600000 ################################################################
10253 22:12:05.350136
10254 22:12:06.016972 02680000 ################################################################
10255 22:12:06.017201
10256 22:12:06.643313 02700000 ################################################################
10257 22:12:06.643809
10258 22:12:07.271570 02780000 ################################################################
10259 22:12:07.272083
10260 22:12:07.941830 02800000 ################################################################
10261 22:12:07.942343
10262 22:12:08.594424 02880000 ################################################################
10263 22:12:08.594969
10264 22:12:09.272634 02900000 ################################################################
10265 22:12:09.273168
10266 22:12:09.944549 02980000 ################################################################
10267 22:12:09.944721
10268 22:12:10.591484 02a00000 ################################################################
10269 22:12:10.592122
10270 22:12:11.249839 02a80000 ################################################################
10271 22:12:11.250513
10272 22:12:11.932540 02b00000 ################################################################
10273 22:12:11.933155
10274 22:12:12.571880 02b80000 ################################################################
10275 22:12:12.572590
10276 22:12:13.239166 02c00000 ################################################################
10277 22:12:13.239683
10278 22:12:13.879863 02c80000 ################################################################
10279 22:12:13.880468
10280 22:12:14.555431 02d00000 ################################################################
10281 22:12:14.555936
10282 22:12:15.153926 02d80000 ################################################################
10283 22:12:15.154086
10284 22:12:15.802343 02e00000 ################################################################
10285 22:12:15.802485
10286 22:12:16.462675 02e80000 ################################################################
10287 22:12:16.463195
10288 22:12:17.127053 02f00000 ################################################################
10289 22:12:17.127582
10290 22:12:17.767114 02f80000 ################################################################
10291 22:12:17.767697
10292 22:12:17.910267 03000000 ############## done.
10293 22:12:17.910787
10294 22:12:17.913905 The bootfile was 50441806 bytes long.
10295 22:12:17.914405
10296 22:12:17.917249 Sending tftp read request... done.
10297 22:12:17.917712
10298 22:12:17.920783 Waiting for the transfer...
10299 22:12:17.921254
10300 22:12:17.921620 00000000 # done.
10301 22:12:17.921942
10302 22:12:17.927789 Command line loaded dynamically from TFTP file: 11440302/tftp-deploy-3bltm57_/kernel/cmdline
10303 22:12:17.928258
10304 22:12:17.940823 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10305 22:12:17.941253
10306 22:12:17.944444 Loading FIT.
10307 22:12:17.944899
10308 22:12:17.948342 Image ramdisk-1 has 39354499 bytes.
10309 22:12:17.948922
10310 22:12:17.949266 Image fdt-1 has 47278 bytes.
10311 22:12:17.951011
10312 22:12:17.951426 Image kernel-1 has 11037994 bytes.
10313 22:12:17.951755
10314 22:12:17.961298 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10315 22:12:17.961839
10316 22:12:17.978225 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10317 22:12:17.978776
10318 22:12:17.984146 Choosing best match conf-1 for compat google,spherion-rev2.
10319 22:12:17.988523
10320 22:12:17.993310 Connected to device vid:did:rid of 1ae0:0028:00
10321 22:12:18.001197
10322 22:12:18.004484 tpm_get_response: command 0x17b, return code 0x0
10323 22:12:18.005036
10324 22:12:18.007917 ec_init: CrosEC protocol v3 supported (256, 248)
10325 22:12:18.013263
10326 22:12:18.016421 tpm_cleanup: add release locality here.
10327 22:12:18.016970
10328 22:12:18.017312 Shutting down all USB controllers.
10329 22:12:18.017622
10330 22:12:18.019739 Removing current net device
10331 22:12:18.020154
10332 22:12:18.026475 Exiting depthcharge with code 4 at timestamp: 104932649
10333 22:12:18.026895
10334 22:12:18.030436 LZMA decompressing kernel-1 to 0x821a6718
10335 22:12:18.031032
10336 22:12:18.033261 LZMA decompressing kernel-1 to 0x40000000
10337 22:12:19.420634
10338 22:12:19.421169 jumping to kernel
10339 22:12:19.422583 end: 2.2.4 bootloader-commands (duration 00:01:17) [common]
10340 22:12:19.423061 start: 2.2.5 auto-login-action (timeout 00:03:08) [common]
10341 22:12:19.423430 Setting prompt string to ['Linux version [0-9]']
10342 22:12:19.423779 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10343 22:12:19.424122 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10344 22:12:19.502886
10345 22:12:19.506448 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10346 22:12:19.509561 start: 2.2.5.1 login-action (timeout 00:03:08) [common]
10347 22:12:19.510139 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10348 22:12:19.510545 Setting prompt string to []
10349 22:12:19.510983 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10350 22:12:19.511385 Using line separator: #'\n'#
10351 22:12:19.511715 No login prompt set.
10352 22:12:19.512220 Parsing kernel messages
10353 22:12:19.512869 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10354 22:12:19.513534 [login-action] Waiting for messages, (timeout 00:03:08)
10355 22:12:19.528983 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j35911-arm64-gcc-10-defconfig-arm64-chromebook-zzzh4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Sep 5 21:54:53 UTC 2023
10356 22:12:19.532450 [ 0.000000] random: crng init done
10357 22:12:19.536076 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10358 22:12:19.539263 [ 0.000000] efi: UEFI not found.
10359 22:12:19.549555 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10360 22:12:19.556100 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10361 22:12:19.565908 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10362 22:12:19.576216 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10363 22:12:19.582409 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10364 22:12:19.585546 [ 0.000000] printk: bootconsole [mtk8250] enabled
10365 22:12:19.594240 [ 0.000000] NUMA: No NUMA configuration found
10366 22:12:19.601158 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10367 22:12:19.607494 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10368 22:12:19.607936 [ 0.000000] Zone ranges:
10369 22:12:19.614388 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10370 22:12:19.617542 [ 0.000000] DMA32 empty
10371 22:12:19.624478 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10372 22:12:19.627685 [ 0.000000] Movable zone start for each node
10373 22:12:19.631345 [ 0.000000] Early memory node ranges
10374 22:12:19.637768 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10375 22:12:19.644918 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10376 22:12:19.651317 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10377 22:12:19.657704 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10378 22:12:19.661331 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10379 22:12:19.671170 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10380 22:12:19.726606 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10381 22:12:19.734148 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10382 22:12:19.740075 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10383 22:12:19.743201 [ 0.000000] psci: probing for conduit method from DT.
10384 22:12:19.750273 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10385 22:12:19.753014 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10386 22:12:19.760224 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10387 22:12:19.763508 [ 0.000000] psci: SMC Calling Convention v1.2
10388 22:12:19.770579 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10389 22:12:19.773986 [ 0.000000] Detected VIPT I-cache on CPU0
10390 22:12:19.780071 [ 0.000000] CPU features: detected: GIC system register CPU interface
10391 22:12:19.787192 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10392 22:12:19.793576 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10393 22:12:19.800609 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10394 22:12:19.807294 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10395 22:12:19.813565 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10396 22:12:19.820248 [ 0.000000] alternatives: applying boot alternatives
10397 22:12:19.823901 [ 0.000000] Fallback order for Node 0: 0
10398 22:12:19.829998 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10399 22:12:19.833403 [ 0.000000] Policy zone: Normal
10400 22:12:19.850882 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10401 22:12:19.859955 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10402 22:12:19.871269 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10403 22:12:19.881521 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10404 22:12:19.888075 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10405 22:12:19.890964 <6>[ 0.000000] software IO TLB: area num 8.
10406 22:12:19.947485 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10407 22:12:20.096785 <6>[ 0.000000] Memory: 7931124K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 421644K reserved, 32768K cma-reserved)
10408 22:12:20.102987 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10409 22:12:20.110151 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10410 22:12:20.113097 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10411 22:12:20.120276 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10412 22:12:20.126834 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10413 22:12:20.130187 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10414 22:12:20.140447 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10415 22:12:20.146781 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10416 22:12:20.150309 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10417 22:12:20.157814 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10418 22:12:20.160717 <6>[ 0.000000] GICv3: 608 SPIs implemented
10419 22:12:20.167423 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10420 22:12:20.171038 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10421 22:12:20.174358 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10422 22:12:20.184383 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10423 22:12:20.194364 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10424 22:12:20.207762 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10425 22:12:20.214192 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10426 22:12:20.222870 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10427 22:12:20.236124 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10428 22:12:20.243646 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10429 22:12:20.250140 <6>[ 0.009179] Console: colour dummy device 80x25
10430 22:12:20.259760 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10431 22:12:20.262858 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10432 22:12:20.269938 <6>[ 0.029219] LSM: Security Framework initializing
10433 22:12:20.276211 <6>[ 0.034157] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10434 22:12:20.286225 <6>[ 0.041970] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10435 22:12:20.292864 <6>[ 0.051398] cblist_init_generic: Setting adjustable number of callback queues.
10436 22:12:20.299434 <6>[ 0.058844] cblist_init_generic: Setting shift to 3 and lim to 1.
10437 22:12:20.309266 <6>[ 0.065183] cblist_init_generic: Setting adjustable number of callback queues.
10438 22:12:20.312568 <6>[ 0.072655] cblist_init_generic: Setting shift to 3 and lim to 1.
10439 22:12:20.319226 <6>[ 0.079092] rcu: Hierarchical SRCU implementation.
10440 22:12:20.325654 <6>[ 0.084105] rcu: Max phase no-delay instances is 1000.
10441 22:12:20.332740 <6>[ 0.091173] EFI services will not be available.
10442 22:12:20.335695 <6>[ 0.096141] smp: Bringing up secondary CPUs ...
10443 22:12:20.344187 <6>[ 0.101194] Detected VIPT I-cache on CPU1
10444 22:12:20.350561 <6>[ 0.101264] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10445 22:12:20.357343 <6>[ 0.101295] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10446 22:12:20.360301 <6>[ 0.101625] Detected VIPT I-cache on CPU2
10447 22:12:20.367175 <6>[ 0.101675] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10448 22:12:20.374442 <6>[ 0.101689] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10449 22:12:20.380732 <6>[ 0.101948] Detected VIPT I-cache on CPU3
10450 22:12:20.387115 <6>[ 0.101994] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10451 22:12:20.393977 <6>[ 0.102008] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10452 22:12:20.397487 <6>[ 0.102310] CPU features: detected: Spectre-v4
10453 22:12:20.404311 <6>[ 0.102317] CPU features: detected: Spectre-BHB
10454 22:12:20.407126 <6>[ 0.102321] Detected PIPT I-cache on CPU4
10455 22:12:20.414191 <6>[ 0.102372] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10456 22:12:20.420561 <6>[ 0.102387] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10457 22:12:20.424086 <6>[ 0.102665] Detected PIPT I-cache on CPU5
10458 22:12:20.434088 <6>[ 0.102720] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10459 22:12:20.440852 <6>[ 0.102736] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10460 22:12:20.444467 <6>[ 0.103013] Detected PIPT I-cache on CPU6
10461 22:12:20.451030 <6>[ 0.103076] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10462 22:12:20.457582 <6>[ 0.103092] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10463 22:12:20.460429 <6>[ 0.103391] Detected PIPT I-cache on CPU7
10464 22:12:20.467920 <6>[ 0.103455] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10465 22:12:20.474518 <6>[ 0.103472] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10466 22:12:20.480960 <6>[ 0.103518] smp: Brought up 1 node, 8 CPUs
10467 22:12:20.484366 <6>[ 0.244669] SMP: Total of 8 processors activated.
10468 22:12:20.490478 <6>[ 0.249590] CPU features: detected: 32-bit EL0 Support
10469 22:12:20.500782 <6>[ 0.254952] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10470 22:12:20.504020 <6>[ 0.263752] CPU features: detected: Common not Private translations
10471 22:12:20.510526 <6>[ 0.270228] CPU features: detected: CRC32 instructions
10472 22:12:20.517368 <6>[ 0.275579] CPU features: detected: RCpc load-acquire (LDAPR)
10473 22:12:20.523907 <6>[ 0.281576] CPU features: detected: LSE atomic instructions
10474 22:12:20.527208 <6>[ 0.287357] CPU features: detected: Privileged Access Never
10475 22:12:20.533697 <6>[ 0.293172] CPU features: detected: RAS Extension Support
10476 22:12:20.540384 <6>[ 0.298781] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10477 22:12:20.546996 <6>[ 0.306002] CPU: All CPU(s) started at EL2
10478 22:12:20.550311 <6>[ 0.310318] alternatives: applying system-wide alternatives
10479 22:12:20.561115 <6>[ 0.321037] devtmpfs: initialized
10480 22:12:20.573536 <6>[ 0.329896] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10481 22:12:20.583644 <6>[ 0.339856] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10482 22:12:20.590126 <6>[ 0.347875] pinctrl core: initialized pinctrl subsystem
10483 22:12:20.593685 <6>[ 0.354508] DMI not present or invalid.
10484 22:12:20.600181 <6>[ 0.358916] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10485 22:12:20.606815 <6>[ 0.365762] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10486 22:12:20.616707 <6>[ 0.373345] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10487 22:12:20.623667 <6>[ 0.381562] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10488 22:12:20.630282 <6>[ 0.389805] audit: initializing netlink subsys (disabled)
10489 22:12:20.640231 <5>[ 0.395499] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10490 22:12:20.643592 <6>[ 0.396202] thermal_sys: Registered thermal governor 'step_wise'
10491 22:12:20.650325 <6>[ 0.403464] thermal_sys: Registered thermal governor 'power_allocator'
10492 22:12:20.656897 <6>[ 0.409720] cpuidle: using governor menu
10493 22:12:20.660101 <6>[ 0.420680] NET: Registered PF_QIPCRTR protocol family
10494 22:12:20.670095 <6>[ 0.426162] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10495 22:12:20.673532 <6>[ 0.433267] ASID allocator initialised with 32768 entries
10496 22:12:20.680229 <6>[ 0.439829] Serial: AMBA PL011 UART driver
10497 22:12:20.688523 <4>[ 0.448549] Trying to register duplicate clock ID: 134
10498 22:12:20.742762 <6>[ 0.505845] KASLR enabled
10499 22:12:20.757017 <6>[ 0.513559] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10500 22:12:20.763784 <6>[ 0.520572] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10501 22:12:20.770482 <6>[ 0.527060] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10502 22:12:20.777240 <6>[ 0.534066] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10503 22:12:20.783836 <6>[ 0.540553] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10504 22:12:20.790628 <6>[ 0.547557] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10505 22:12:20.796828 <6>[ 0.554046] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10506 22:12:20.803598 <6>[ 0.561050] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10507 22:12:20.807065 <6>[ 0.568547] ACPI: Interpreter disabled.
10508 22:12:20.814951 <6>[ 0.574934] iommu: Default domain type: Translated
10509 22:12:20.822002 <6>[ 0.580044] iommu: DMA domain TLB invalidation policy: strict mode
10510 22:12:20.824930 <5>[ 0.586696] SCSI subsystem initialized
10511 22:12:20.831654 <6>[ 0.590863] usbcore: registered new interface driver usbfs
10512 22:12:20.838626 <6>[ 0.596596] usbcore: registered new interface driver hub
10513 22:12:20.841574 <6>[ 0.602147] usbcore: registered new device driver usb
10514 22:12:20.848216 <6>[ 0.608232] pps_core: LinuxPPS API ver. 1 registered
10515 22:12:20.858120 <6>[ 0.613426] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10516 22:12:20.861851 <6>[ 0.622774] PTP clock support registered
10517 22:12:20.864771 <6>[ 0.627015] EDAC MC: Ver: 3.0.0
10518 22:12:20.872810 <6>[ 0.632162] FPGA manager framework
10519 22:12:20.876130 <6>[ 0.635841] Advanced Linux Sound Architecture Driver Initialized.
10520 22:12:20.879926 <6>[ 0.642613] vgaarb: loaded
10521 22:12:20.886351 <6>[ 0.645796] clocksource: Switched to clocksource arch_sys_counter
10522 22:12:20.893093 <5>[ 0.652229] VFS: Disk quotas dquot_6.6.0
10523 22:12:20.899689 <6>[ 0.656414] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10524 22:12:20.902792 <6>[ 0.663599] pnp: PnP ACPI: disabled
10525 22:12:20.910889 <6>[ 0.670257] NET: Registered PF_INET protocol family
10526 22:12:20.920305 <6>[ 0.675840] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10527 22:12:20.931919 <6>[ 0.688134] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10528 22:12:20.941427 <6>[ 0.696947] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10529 22:12:20.948450 <6>[ 0.704917] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10530 22:12:20.955255 <6>[ 0.713616] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10531 22:12:20.966905 <6>[ 0.723333] TCP: Hash tables configured (established 65536 bind 65536)
10532 22:12:20.973599 <6>[ 0.730191] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10533 22:12:20.980504 <6>[ 0.737393] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10534 22:12:20.987023 <6>[ 0.745090] NET: Registered PF_UNIX/PF_LOCAL protocol family
10535 22:12:20.993477 <6>[ 0.751267] RPC: Registered named UNIX socket transport module.
10536 22:12:20.997165 <6>[ 0.757421] RPC: Registered udp transport module.
10537 22:12:21.003734 <6>[ 0.762352] RPC: Registered tcp transport module.
10538 22:12:21.010008 <6>[ 0.767284] RPC: Registered tcp NFSv4.1 backchannel transport module.
10539 22:12:21.013532 <6>[ 0.773952] PCI: CLS 0 bytes, default 64
10540 22:12:21.016866 <6>[ 0.778364] Unpacking initramfs...
10541 22:12:21.041070 <6>[ 0.797905] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10542 22:12:21.050999 <6>[ 0.806529] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10543 22:12:21.054493 <6>[ 0.815380] kvm [1]: IPA Size Limit: 40 bits
10544 22:12:21.061004 <6>[ 0.819907] kvm [1]: GICv3: no GICV resource entry
10545 22:12:21.064530 <6>[ 0.824928] kvm [1]: disabling GICv2 emulation
10546 22:12:21.071324 <6>[ 0.829617] kvm [1]: GIC system register CPU interface enabled
10547 22:12:21.074838 <6>[ 0.835778] kvm [1]: vgic interrupt IRQ18
10548 22:12:21.081344 <6>[ 0.840128] kvm [1]: VHE mode initialized successfully
10549 22:12:21.088024 <5>[ 0.846575] Initialise system trusted keyrings
10550 22:12:21.094587 <6>[ 0.851415] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10551 22:12:21.101852 <6>[ 0.861388] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10552 22:12:21.108292 <5>[ 0.867774] NFS: Registering the id_resolver key type
10553 22:12:21.111808 <5>[ 0.873073] Key type id_resolver registered
10554 22:12:21.118147 <5>[ 0.877488] Key type id_legacy registered
10555 22:12:21.124820 <6>[ 0.881767] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10556 22:12:21.131720 <6>[ 0.888688] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10557 22:12:21.138180 <6>[ 0.896396] 9p: Installing v9fs 9p2000 file system support
10558 22:12:21.174022 <5>[ 0.933838] Key type asymmetric registered
10559 22:12:21.177329 <5>[ 0.938170] Asymmetric key parser 'x509' registered
10560 22:12:21.187410 <6>[ 0.943309] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10561 22:12:21.190878 <6>[ 0.950932] io scheduler mq-deadline registered
10562 22:12:21.193970 <6>[ 0.955709] io scheduler kyber registered
10563 22:12:21.212650 <6>[ 0.972642] EINJ: ACPI disabled.
10564 22:12:21.245586 <4>[ 0.998244] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 22:12:21.254966 <4>[ 1.008858] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10566 22:12:21.270331 <6>[ 1.029621] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10567 22:12:21.277865 <6>[ 1.037593] printk: console [ttyS0] disabled
10568 22:12:21.305909 <6>[ 1.062236] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10569 22:12:21.312772 <6>[ 1.071712] printk: console [ttyS0] enabled
10570 22:12:21.315772 <6>[ 1.071712] printk: console [ttyS0] enabled
10571 22:12:21.322497 <6>[ 1.080605] printk: bootconsole [mtk8250] disabled
10572 22:12:21.325557 <6>[ 1.080605] printk: bootconsole [mtk8250] disabled
10573 22:12:21.332344 <6>[ 1.091787] SuperH (H)SCI(F) driver initialized
10574 22:12:21.335450 <6>[ 1.097071] msm_serial: driver initialized
10575 22:12:21.349805 <6>[ 1.106089] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10576 22:12:21.359331 <6>[ 1.114637] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10577 22:12:21.366385 <6>[ 1.123179] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10578 22:12:21.376458 <6>[ 1.131808] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10579 22:12:21.382517 <6>[ 1.140514] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10580 22:12:21.392991 <6>[ 1.149233] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10581 22:12:21.402957 <6>[ 1.157774] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10582 22:12:21.409260 <6>[ 1.166579] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10583 22:12:21.419182 <6>[ 1.175122] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10584 22:12:21.430613 <6>[ 1.190749] loop: module loaded
10585 22:12:21.437286 <6>[ 1.196791] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10586 22:12:21.460417 <4>[ 1.220320] mtk-pmic-keys: Failed to locate of_node [id: -1]
10587 22:12:21.466955 <6>[ 1.227282] megasas: 07.719.03.00-rc1
10588 22:12:21.476931 <6>[ 1.236861] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10589 22:12:21.485489 <6>[ 1.245197] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10590 22:12:21.502290 <6>[ 1.261926] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10591 22:12:21.559143 <6>[ 1.312180] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10592 22:12:22.619066 <6>[ 2.379310] Freeing initrd memory: 38428K
10593 22:12:22.629356 <6>[ 2.389673] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10594 22:12:22.640302 <6>[ 2.400558] tun: Universal TUN/TAP device driver, 1.6
10595 22:12:22.643933 <6>[ 2.406625] thunder_xcv, ver 1.0
10596 22:12:22.647068 <6>[ 2.410131] thunder_bgx, ver 1.0
10597 22:12:22.650860 <6>[ 2.413623] nicpf, ver 1.0
10598 22:12:22.661185 <6>[ 2.417632] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10599 22:12:22.664114 <6>[ 2.425109] hns3: Copyright (c) 2017 Huawei Corporation.
10600 22:12:22.667608 <6>[ 2.430695] hclge is initializing
10601 22:12:22.674036 <6>[ 2.434274] e1000: Intel(R) PRO/1000 Network Driver
10602 22:12:22.680891 <6>[ 2.439403] e1000: Copyright (c) 1999-2006 Intel Corporation.
10603 22:12:22.684003 <6>[ 2.445417] e1000e: Intel(R) PRO/1000 Network Driver
10604 22:12:22.690913 <6>[ 2.450632] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10605 22:12:22.697652 <6>[ 2.456816] igb: Intel(R) Gigabit Ethernet Network Driver
10606 22:12:22.703956 <6>[ 2.462466] igb: Copyright (c) 2007-2014 Intel Corporation.
10607 22:12:22.710519 <6>[ 2.468301] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10608 22:12:22.717199 <6>[ 2.474819] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10609 22:12:22.720901 <6>[ 2.481279] sky2: driver version 1.30
10610 22:12:22.727304 <6>[ 2.486268] VFIO - User Level meta-driver version: 0.3
10611 22:12:22.734739 <6>[ 2.494511] usbcore: registered new interface driver usb-storage
10612 22:12:22.741393 <6>[ 2.500951] usbcore: registered new device driver onboard-usb-hub
10613 22:12:22.750101 <6>[ 2.510028] mt6397-rtc mt6359-rtc: registered as rtc0
10614 22:12:22.759821 <6>[ 2.515494] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-05T22:12:25 UTC (1693951945)
10615 22:12:22.763381 <6>[ 2.525066] i2c_dev: i2c /dev entries driver
10616 22:12:22.780061 <6>[ 2.536808] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10617 22:12:22.799463 <6>[ 2.559804] cpu cpu0: EM: created perf domain
10618 22:12:22.803149 <6>[ 2.564793] cpu cpu4: EM: created perf domain
10619 22:12:22.810298 <6>[ 2.570397] sdhci: Secure Digital Host Controller Interface driver
10620 22:12:22.817278 <6>[ 2.576826] sdhci: Copyright(c) Pierre Ossman
10621 22:12:22.823641 <6>[ 2.581765] Synopsys Designware Multimedia Card Interface Driver
10622 22:12:22.830200 <6>[ 2.588400] sdhci-pltfm: SDHCI platform and OF driver helper
10623 22:12:22.833533 <6>[ 2.588464] mmc0: CQHCI version 5.10
10624 22:12:22.840330 <6>[ 2.598785] ledtrig-cpu: registered to indicate activity on CPUs
10625 22:12:22.847019 <6>[ 2.605842] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10626 22:12:22.853726 <6>[ 2.612893] usbcore: registered new interface driver usbhid
10627 22:12:22.856702 <6>[ 2.618715] usbhid: USB HID core driver
10628 22:12:22.863831 <6>[ 2.622916] spi_master spi0: will run message pump with realtime priority
10629 22:12:22.907542 <6>[ 2.660706] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10630 22:12:22.926041 <6>[ 2.675778] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10631 22:12:22.929018 <6>[ 2.689313] mmc0: Command Queue Engine enabled
10632 22:12:22.936319 <6>[ 2.694071] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10633 22:12:22.942188 <6>[ 2.701668] mmcblk0: mmc0:0001 DA4128 116 GiB
10634 22:12:22.948664 <6>[ 2.706666] cros-ec-spi spi0.0: Chrome EC device registered
10635 22:12:22.952209 <6>[ 2.710610] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10636 22:12:22.959869 <6>[ 2.719366] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10637 22:12:22.965998 <6>[ 2.725409] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10638 22:12:22.972533 <6>[ 2.731272] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10639 22:12:22.991715 <6>[ 2.748086] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10640 22:12:22.998650 <6>[ 2.758662] NET: Registered PF_PACKET protocol family
10641 22:12:23.002178 <6>[ 2.764065] 9pnet: Installing 9P2000 support
10642 22:12:23.008777 <5>[ 2.768634] Key type dns_resolver registered
10643 22:12:23.011815 <6>[ 2.773621] registered taskstats version 1
10644 22:12:23.018917 <5>[ 2.778010] Loading compiled-in X.509 certificates
10645 22:12:23.049065 <4>[ 2.802344] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10646 22:12:23.059398 <4>[ 2.813064] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10647 22:12:23.065569 <3>[ 2.823599] debugfs: File 'uA_load' in directory '/' already present!
10648 22:12:23.072386 <3>[ 2.830299] debugfs: File 'min_uV' in directory '/' already present!
10649 22:12:23.079449 <3>[ 2.836906] debugfs: File 'max_uV' in directory '/' already present!
10650 22:12:23.085533 <3>[ 2.843513] debugfs: File 'constraint_flags' in directory '/' already present!
10651 22:12:23.096409 <3>[ 2.853123] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10652 22:12:23.106694 <6>[ 2.866544] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10653 22:12:23.113083 <6>[ 2.873248] xhci-mtk 11200000.usb: xHCI Host Controller
10654 22:12:23.119722 <6>[ 2.878760] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10655 22:12:23.130143 <6>[ 2.886598] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10656 22:12:23.136598 <6>[ 2.896015] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10657 22:12:23.143521 <6>[ 2.902079] xhci-mtk 11200000.usb: xHCI Host Controller
10658 22:12:23.149969 <6>[ 2.907554] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10659 22:12:23.156521 <6>[ 2.915197] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10660 22:12:23.163013 <6>[ 2.922834] hub 1-0:1.0: USB hub found
10661 22:12:23.166459 <6>[ 2.926841] hub 1-0:1.0: 1 port detected
10662 22:12:23.173345 <6>[ 2.931110] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10663 22:12:23.180118 <6>[ 2.939665] hub 2-0:1.0: USB hub found
10664 22:12:23.183204 <6>[ 2.943669] hub 2-0:1.0: 1 port detected
10665 22:12:23.192043 <6>[ 2.951799] mtk-msdc 11f70000.mmc: Got CD GPIO
10666 22:12:23.203211 <6>[ 2.959801] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10667 22:12:23.209904 <6>[ 2.967842] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10668 22:12:23.219954 <4>[ 2.975811] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10669 22:12:23.229890 <6>[ 2.985336] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10670 22:12:23.236738 <6>[ 2.993416] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10671 22:12:23.242785 <6>[ 3.001501] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10672 22:12:23.253377 <6>[ 3.009423] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10673 22:12:23.259802 <6>[ 3.017244] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10674 22:12:23.269836 <6>[ 3.025061] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10675 22:12:23.279891 <6>[ 3.035377] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10676 22:12:23.286498 <6>[ 3.043730] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10677 22:12:23.296625 <6>[ 3.052068] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10678 22:12:23.302360 <6>[ 3.060405] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10679 22:12:23.312580 <6>[ 3.068742] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10680 22:12:23.319309 <6>[ 3.077080] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10681 22:12:23.329201 <6>[ 3.085418] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10682 22:12:23.335899 <6>[ 3.093755] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10683 22:12:23.346060 <6>[ 3.102093] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10684 22:12:23.352502 <6>[ 3.110431] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10685 22:12:23.362688 <6>[ 3.118770] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10686 22:12:23.368991 <6>[ 3.127107] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10687 22:12:23.379227 <6>[ 3.135444] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10688 22:12:23.385723 <6>[ 3.143782] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10689 22:12:23.395890 <6>[ 3.152123] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10690 22:12:23.402795 <6>[ 3.160911] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10691 22:12:23.409063 <6>[ 3.168105] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10692 22:12:23.415200 <6>[ 3.174867] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10693 22:12:23.422044 <6>[ 3.181630] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10694 22:12:23.428949 <6>[ 3.188570] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10695 22:12:23.438589 <6>[ 3.195415] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10696 22:12:23.448758 <6>[ 3.204549] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10697 22:12:23.458514 <6>[ 3.213669] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10698 22:12:23.468314 <6>[ 3.222963] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10699 22:12:23.475494 <6>[ 3.232448] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10700 22:12:23.485197 <6>[ 3.241929] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10701 22:12:23.495395 <6>[ 3.251051] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10702 22:12:23.505141 <6>[ 3.260519] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10703 22:12:23.514792 <6>[ 3.269638] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10704 22:12:23.525170 <6>[ 3.278934] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10705 22:12:23.534785 <6>[ 3.289094] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10706 22:12:23.544661 <6>[ 3.300789] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10707 22:12:23.573430 <6>[ 3.330358] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10708 22:12:23.601781 <6>[ 3.361606] hub 2-1:1.0: USB hub found
10709 22:12:23.605062 <6>[ 3.366106] hub 2-1:1.0: 3 ports detected
10710 22:12:23.721937 <6>[ 3.482063] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10711 22:12:23.879893 <6>[ 3.640010] hub 1-1:1.0: USB hub found
10712 22:12:23.882980 <6>[ 3.644527] hub 1-1:1.0: 4 ports detected
10713 22:12:23.961299 <6>[ 3.718392] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10714 22:12:24.205220 <6>[ 3.962201] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10715 22:12:24.337509 <6>[ 4.097444] hub 1-1.4:1.0: USB hub found
10716 22:12:24.340401 <6>[ 4.102069] hub 1-1.4:1.0: 2 ports detected
10717 22:12:24.637133 <6>[ 4.394054] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10718 22:12:24.829040 <6>[ 4.586119] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10719 22:12:35.834956 <6>[ 15.599169] ALSA device list:
10720 22:12:35.841446 <6>[ 15.602470] No soundcards found.
10721 22:12:35.849388 <6>[ 15.610613] Freeing unused kernel memory: 8384K
10722 22:12:35.852845 <6>[ 15.615717] Run /init as init process
10723 22:12:35.906790 <6>[ 15.668338] NET: Registered PF_INET6 protocol family
10724 22:12:35.913109 <6>[ 15.674630] Segment Routing with IPv6
10725 22:12:35.916441 <6>[ 15.678575] In-situ OAM (IOAM) with IPv6
10726 22:12:35.947533 <30>[ 15.692498] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10727 22:12:35.954649 <30>[ 15.716315] systemd[1]: Detected architecture arm64.
10728 22:12:35.955058
10729 22:12:35.961409 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10730 22:12:35.961815
10731 22:12:35.976889 <30>[ 15.738178] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10732 22:12:36.131420 <30>[ 15.889918] systemd[1]: Queued start job for default target Graphical Interface.
10733 22:12:36.164797 <30>[ 15.926698] systemd[1]: Created slice system-getty.slice.
10734 22:12:36.171664 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10735 22:12:36.188975 <30>[ 15.950324] systemd[1]: Created slice system-modprobe.slice.
10736 22:12:36.195562 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10737 22:12:36.213457 <30>[ 15.974661] systemd[1]: Created slice system-serial\x2dgetty.slice.
10738 22:12:36.223094 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10739 22:12:36.237755 <30>[ 15.999069] systemd[1]: Created slice User and Session Slice.
10740 22:12:36.244564 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10741 22:12:36.264093 <30>[ 16.022648] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10742 22:12:36.273952 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10743 22:12:36.292338 <30>[ 16.050617] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10744 22:12:36.298700 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10745 22:12:36.319224 <30>[ 16.074053] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10746 22:12:36.325520 <30>[ 16.086173] systemd[1]: Reached target Local Encrypted Volumes.
10747 22:12:36.331926 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10748 22:12:36.348871 <30>[ 16.110504] systemd[1]: Reached target Paths.
10749 22:12:36.352246 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10750 22:12:36.368728 <30>[ 16.130104] systemd[1]: Reached target Remote File Systems.
10751 22:12:36.375541 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10752 22:12:36.393572 <30>[ 16.154465] systemd[1]: Reached target Slices.
10753 22:12:36.399309 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10754 22:12:36.412567 <30>[ 16.174120] systemd[1]: Reached target Swap.
10755 22:12:36.415723 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10756 22:12:36.436548 <30>[ 16.194643] systemd[1]: Listening on initctl Compatibility Named Pipe.
10757 22:12:36.443576 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10758 22:12:36.449987 <30>[ 16.210062] systemd[1]: Listening on Journal Audit Socket.
10759 22:12:36.456374 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10760 22:12:36.469554 <30>[ 16.230637] systemd[1]: Listening on Journal Socket (/dev/log).
10761 22:12:36.475785 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10762 22:12:36.494450 <30>[ 16.255431] systemd[1]: Listening on Journal Socket.
10763 22:12:36.500565 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10764 22:12:36.516838 <30>[ 16.274893] systemd[1]: Listening on Network Service Netlink Socket.
10765 22:12:36.523085 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10766 22:12:36.538374 <30>[ 16.299416] systemd[1]: Listening on udev Control Socket.
10767 22:12:36.544599 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10768 22:12:36.561625 <30>[ 16.323251] systemd[1]: Listening on udev Kernel Socket.
10769 22:12:36.568081 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10770 22:12:36.624774 <30>[ 16.386463] systemd[1]: Mounting Huge Pages File System...
10771 22:12:36.631293 Mounting [0;1;39mHuge Pages File System[0m...
10772 22:12:36.648426 <30>[ 16.410379] systemd[1]: Mounting POSIX Message Queue File System...
10773 22:12:36.655129 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10774 22:12:36.705013 <30>[ 16.466540] systemd[1]: Mounting Kernel Debug File System...
10775 22:12:36.711263 Mounting [0;1;39mKernel Debug File System[0m...
10776 22:12:36.731669 <30>[ 16.490232] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10777 22:12:36.742966 <30>[ 16.501221] systemd[1]: Starting Create list of static device nodes for the current kernel...
10778 22:12:36.749369 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10779 22:12:36.788821 <30>[ 16.550710] systemd[1]: Starting Load Kernel Module configfs...
10780 22:12:36.795974 Starting [0;1;39mLoad Kernel Module configfs[0m...
10781 22:12:36.813957 <30>[ 16.575248] systemd[1]: Starting Load Kernel Module drm...
10782 22:12:36.820114 Starting [0;1;39mLoad Kernel Module drm[0m...
10783 22:12:36.836083 <30>[ 16.594499] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10784 22:12:36.889242 <30>[ 16.650761] systemd[1]: Starting Journal Service...
10785 22:12:36.893099 Starting [0;1;39mJournal Service[0m...
10786 22:12:36.912744 <30>[ 16.673915] systemd[1]: Starting Load Kernel Modules...
10787 22:12:36.919592 Starting [0;1;39mLoad Kernel Modules[0m...
10788 22:12:36.938960 <30>[ 16.696875] systemd[1]: Starting Remount Root and Kernel File Systems...
10789 22:12:36.945221 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10790 22:12:36.963017 <30>[ 16.725306] systemd[1]: Starting Coldplug All udev Devices...
10791 22:12:36.970196 Starting [0;1;39mColdplug All udev Devices[0m...
10792 22:12:36.987577 <30>[ 16.749390] systemd[1]: Started Journal Service.
10793 22:12:36.994022 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10794 22:12:37.010630 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10795 22:12:37.025395 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10796 22:12:37.041368 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10797 22:12:37.061445 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10798 22:12:37.080242 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10799 22:12:37.098892 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10800 22:12:37.118953 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10801 22:12:37.139466 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10802 22:12:37.152483 See 'systemctl status systemd-remount-fs.service' for details.
10803 22:12:37.207787 Mounting [0;1;39mKernel Configuration File System[0m...
10804 22:12:37.229292 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10805 22:12:37.243035 <46>[ 17.001062] systemd-journald[185]: Received client request to flush runtime journal.
10806 22:12:37.255527 Starting [0;1;39mLoad/Save Random Seed[0m...
10807 22:12:37.277033 Starting [0;1;39mApply Kernel Variables[0m...
10808 22:12:37.302747 Starting [0;1;39mCreate System Users[0m...
10809 22:12:37.327047 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10810 22:12:37.349361 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10811 22:12:37.373362 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10812 22:12:37.394318 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10813 22:12:37.401461 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10814 22:12:37.416476 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10815 22:12:37.477589 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10816 22:12:37.502343 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10817 22:12:37.521111 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10818 22:12:37.540500 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10819 22:12:37.581690 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10820 22:12:37.609213 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10821 22:12:37.630863 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10822 22:12:37.652459 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10823 22:12:37.720356 Starting [0;1;39mNetwork Service[0m...
10824 22:12:37.750860 Starting [0;1;39mNetwork Time Synchronization[0m...
10825 22:12:37.775183 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10826 22:12:37.827328 [[0;32m OK [0m] Started [0;1;39mNetwork Ser<6>[ 17.585580] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10827 22:12:37.827845 vice[0m.
10828 22:12:37.841803 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10829 22:12:37.847822 <6>[ 17.609527] remoteproc remoteproc0: scp is available
10830 22:12:37.854538 <6>[ 17.616800] remoteproc remoteproc0: powering up scp
10831 22:12:37.861090 <6>[ 17.621501] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10832 22:12:37.871089 <6>[ 17.622056] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10833 22:12:37.877807 <6>[ 17.629617] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10834 22:12:37.884574 <6>[ 17.638017] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10835 22:12:37.894688 <6>[ 17.646703] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10836 22:12:37.898180 <6>[ 17.647248] mc: Linux media interface: v0.10
10837 22:12:37.904647 [[0;32m OK [<6>[ 17.667076] videodev: Linux video capture interface: v2.00
10838 22:12:37.911247 0m] Found device [0;1;39m/dev/ttyS0[0m.
10839 22:12:37.941640 [[0;32m OK [0m] Finished [0<4>[ 17.699314] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10840 22:12:37.947890 ;1;39mUpdate UTM<6>[ 17.700955] usbcore: registered new interface driver r8152
10841 22:12:37.951166 P about System B<6>[ 17.701028] Bluetooth: Core ver 2.22
10842 22:12:37.958083 <6>[ 17.701080] NET: Registered PF_BLUETOOTH protocol family
10843 22:12:37.964753 <6>[ 17.701082] Bluetooth: HCI device and connection manager initialized
10844 22:12:37.967708 <6>[ 17.701097] Bluetooth: HCI socket layer initialized
10845 22:12:37.974460 <6>[ 17.701100] Bluetooth: L2CAP socket layer initialized
10846 22:12:37.981655 <6>[ 17.701108] Bluetooth: SCO socket layer initialized
10847 22:12:37.987780 <4>[ 17.706951] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10848 22:12:37.988219 oot/Shutdown[0m.
10849 22:12:38.004839 <3>[ 17.763331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10850 22:12:38.011610 <3>[ 17.771589] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10851 22:12:38.021107 <6>[ 17.774180] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10852 22:12:38.027901 <6>[ 17.774180] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10853 22:12:38.038232 <3>[ 17.780523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 22:12:38.044764 <6>[ 17.788881] remoteproc remoteproc0: remote processor scp is now up
10855 22:12:38.051165 <3>[ 17.802114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 22:12:38.057943 <6>[ 17.809709] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10857 22:12:38.067751 <3>[ 17.810010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 22:12:38.074539 <3>[ 17.810020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 22:12:38.084569 <3>[ 17.810025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 22:12:38.091215 <3>[ 17.810029] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 22:12:38.097376 <3>[ 17.813706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 22:12:38.107520 <6>[ 17.815354] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10863 22:12:38.117249 <6>[ 17.816928] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10864 22:12:38.124322 <6>[ 17.818366] pci_bus 0000:00: root bus resource [bus 00-ff]
10865 22:12:38.130728 <3>[ 17.830858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10866 22:12:38.140469 <6>[ 17.833190] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10867 22:12:38.147133 <6>[ 17.833425] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10868 22:12:38.153807 <3>[ 17.841465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 22:12:38.163941 <6>[ 17.849666] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10870 22:12:38.174677 <3>[ 17.857632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 22:12:38.181589 <3>[ 17.858310] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 22:12:38.191063 <4>[ 17.860305] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10873 22:12:38.194705 <4>[ 17.860305] Fallback method does not support PEC.
10874 22:12:38.204341 <6>[ 17.865364] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10875 22:12:38.210785 <6>[ 17.866369] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10876 22:12:38.217867 <6>[ 17.866395] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10877 22:12:38.224628 <3>[ 17.876041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 22:12:38.234890 <6>[ 17.885591] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10879 22:12:38.241593 <3>[ 17.890689] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10880 22:12:38.247881 <3>[ 17.890695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 22:12:38.258259 <3>[ 17.890698] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 22:12:38.264874 <3>[ 17.890774] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 22:12:38.271995 <6>[ 17.891106] usbcore: registered new interface driver cdc_ether
10884 22:12:38.279184 <4>[ 17.897098] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10885 22:12:38.288851 <4>[ 17.897108] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10886 22:12:38.296412 <6>[ 17.899132] usbcore: registered new interface driver r8153_ecm
10887 22:12:38.299817 <6>[ 17.899632] pci 0000:00:00.0: supports D1 D2
10888 22:12:38.306798 <6>[ 17.899685] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10889 22:12:38.313547 <6>[ 17.901599] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10890 22:12:38.319959 <6>[ 17.901726] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10891 22:12:38.327081 <6>[ 17.901760] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10892 22:12:38.333832 <6>[ 17.901814] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10893 22:12:38.344170 <6>[ 17.901835] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10894 22:12:38.347763 <6>[ 17.901963] pci 0000:01:00.0: supports D1 D2
10895 22:12:38.354054 <6>[ 17.901967] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10896 22:12:38.360710 <6>[ 17.921974] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10897 22:12:38.368218 <6>[ 17.925480] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10898 22:12:38.378389 <6>[ 17.928756] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10899 22:12:38.384996 <6>[ 17.933521] usbcore: registered new interface driver btusb
10900 22:12:38.394667 <4>[ 17.933922] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10901 22:12:38.401067 <3>[ 17.933935] Bluetooth: hci0: Failed to load firmware file (-2)
10902 22:12:38.405153 <3>[ 17.933940] Bluetooth: hci0: Failed to set up firmware (-2)
10903 22:12:38.418048 <4>[ 17.933946] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10904 22:12:38.425439 <6>[ 17.940646] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10905 22:12:38.428983 <6>[ 17.941937] r8152 2-1.3:1.0 eth0: v1.12.13
10906 22:12:38.435780 <6>[ 17.953198] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10907 22:12:38.442273 <6>[ 17.961614] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10908 22:12:38.448751 <6>[ 17.961624] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10909 22:12:38.459177 <6>[ 17.961640] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10910 22:12:38.472091 <6>[ 17.963460] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10911 22:12:38.475081 <6>[ 17.963605] usbcore: registered new interface driver uvcvideo
10912 22:12:38.482297 <6>[ 17.985303] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10913 22:12:38.492576 <6>[ 17.992418] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10914 22:12:38.498665 <6>[ 17.992432] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10915 22:12:38.508928 <3>[ 18.003419] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 22:12:38.515212 <6>[ 18.007982] pci 0000:00:00.0: PCI bridge to [bus 01]
10917 22:12:38.521610 <6>[ 18.007988] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10918 22:12:38.531452 <3>[ 18.038488] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 22:12:38.538231 <3>[ 18.039180] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10920 22:12:38.545007 <6>[ 18.047549] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10921 22:12:38.551467 <3>[ 18.066249] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 22:12:38.561456 <3>[ 18.068796] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10923 22:12:38.568062 <6>[ 18.073398] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10924 22:12:38.574336 <3>[ 18.104970] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 22:12:38.581044 <6>[ 18.110279] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10926 22:12:38.591260 <3>[ 18.135395] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 22:12:38.597485 <5>[ 18.164533] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10928 22:12:38.608126 <3>[ 18.192877] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 22:12:38.614415 <5>[ 18.205961] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10930 22:12:38.621208 <4>[ 18.380956] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10931 22:12:38.628004 <6>[ 18.389859] cfg80211: failed to load regulatory.db
10932 22:12:38.638166 [[0;32m OK [<3>[ 18.394235] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 22:12:38.645212 0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10934 22:12:38.661209 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10935 22:12:38.671171 <3>[ 18.429729] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 22:12:38.687084 [[0;32m OK [0m] Reached targ<6>[ 18.444415] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10937 22:12:38.694854 et [0;1;39mSyst<6>[ 18.452808] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10938 22:12:38.695457 em Time Synchronized[0m.
10939 22:12:38.718862 <6>[ 18.480740] mt7921e 0000:01:00.0: ASIC revision: 79610010
10940 22:12:38.736361 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10941 22:12:38.752216 Starting [0;1;39mNetwork Name Resolution[0m...
10942 22:12:38.774093 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10943 22:12:38.812973 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10944 22:12:38.827058 <4>[ 18.582704] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10945 22:12:38.882814 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10946 22:12:38.896323 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10947 22:12:38.915261 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10948 22:12:38.929010 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10949 22:12:38.945261 <4>[ 18.700669] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10950 22:12:38.956232 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10951 22:12:38.972245 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10952 22:12:38.983999 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10953 22:12:39.004405 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10954 22:12:39.016514 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10955 22:12:39.032261 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10956 22:12:39.053662 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10957 22:12:39.063605 <4>[ 18.820559] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10958 22:12:39.108567 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10959 22:12:39.137685 Starting [0;1;39mUser Login Management[0m...
10960 22:12:39.157362 Starting [0;1;39mPermit User Sessions[0m...
10961 22:12:39.189092 [[0;32m OK [<4>[ 18.944204] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10962 22:12:39.195461 0m] Finished [0;1;39mPermit User Sessions[0m.
10963 22:12:39.249884 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10964 22:12:39.269925 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10965 22:12:39.285163 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10966 22:12:39.313408 <4>[ 19.068530] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10967 22:12:39.319988 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10968 22:12:39.338437 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10969 22:12:39.358627 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10970 22:12:39.378876 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10971 22:12:39.397213 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10972 22:12:39.433735 <4>[ 19.188979] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10973 22:12:39.462311 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10974 22:12:39.498395 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10975 22:12:39.543427
10976 22:12:39.543949
10977 22:12:39.557323 Debian GNU/Linux 11 debian-bu<4>[ 19.310913] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10978 22:12:39.557888 llseye-arm64 ttyS0
10979 22:12:39.558307
10980 22:12:39.563863 debian-bullseye-arm64 login: root (automatic login)
10981 22:12:39.564272
10982 22:12:39.564595
10983 22:12:39.570090 Linux debian-bullseye-arm64 6.1.46-cip4 #1 SMP PREEMPT Tue Sep 5 21:54:53 UTC 2023 aarch64
10984 22:12:39.570186
10985 22:12:39.576428 The programs included with the Debian GNU/Linux system are free software;
10986 22:12:39.582971 the exact distribution terms for each program are described in the
10987 22:12:39.586716 individual files in /usr/share/doc/*/copyright.
10988 22:12:39.586801
10989 22:12:39.593080 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10990 22:12:39.596189 permitted by applicable law.
10991 22:12:39.596525 Matched prompt #10: / #
10993 22:12:39.596764 Setting prompt string to ['/ #']
10994 22:12:39.596854 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10996 22:12:39.597040 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10997 22:12:39.597126 start: 2.2.6 expect-shell-connection (timeout 00:02:48) [common]
10998 22:12:39.597195 Setting prompt string to ['/ #']
10999 22:12:39.597255 Forcing a shell prompt, looking for ['/ #']
11001 22:12:39.647478 / #
11002 22:12:39.647861 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11003 22:12:39.648105 Waiting using forced prompt support (timeout 00:02:30)
11004 22:12:39.653172
11005 22:12:39.653743 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11006 22:12:39.654094 start: 2.2.7 export-device-env (timeout 00:02:48) [common]
11007 22:12:39.654426 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11008 22:12:39.654772 end: 2.2 depthcharge-retry (duration 00:02:12) [common]
11009 22:12:39.655077 end: 2 depthcharge-action (duration 00:02:12) [common]
11010 22:12:39.655379 start: 3 lava-test-retry (timeout 00:07:27) [common]
11011 22:12:39.655673 start: 3.1 lava-test-shell (timeout 00:07:27) [common]
11012 22:12:39.655925 Using namespace: common
11014 22:12:39.756816 / # #
11015 22:12:39.757401 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11016 22:12:39.757896 <4>[ 19.433384] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11017 22:12:39.763321 #
11018 22:12:39.764079 Using /lava-11440302
11020 22:12:39.865061 / # export SHELL=/bin/sh
11021 22:12:39.865416 <4>[ 19.552426] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11022 22:12:39.870633 export SHELL=/bin/sh
11024 22:12:39.971568 / # . /lava-11440302/environment
11025 22:12:39.971969 <6>[ 19.645589] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
11026 22:12:39.972141 <6>[ 19.653612] r8152 2-1.3:1.0 enx002432307852: carrier on
11027 22:12:39.972292 <4>[ 19.673156] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11028 22:12:39.976705 . /lava-11440302/environment
11030 22:12:40.077859 / # /lava-11440302/bin/lava-test-runner /lava-11440302/0
11031 22:12:40.078477 Test shell timeout: 10s (minimum of the action and connection timeout)
11032 22:12:40.080091 <3>[ 19.790163] mt7921e 0000:01:00.0: hardware init failed
11033 22:12:40.083991 /lava-11440302/bin/lava-test-runner /lava-11440302/0
11034 22:12:40.125054 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11035 22:12:40.125508 + cd /lava-11440302/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11036 22:12:40.125845 + cat uuid
11037 22:12:40.126273 + UUID=11440302_1.5.2.3.1
11038 22:12:40.126589 + set +x
11039 22:12:40.126932 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11440302_1.5.2.3.1>
11040 22:12:40.127543 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11440302_1.5.2.3.1
11041 22:12:40.127895 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11440302_1.5.2.3.1)
11042 22:12:40.128328 Skipping test definition patterns.
11043 22:12:40.128873 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11044 22:12:40.134240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11045 22:12:40.134651 device: /dev/video2
11046 22:12:40.135233 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11048 22:12:40.143830 <4>[ 19.902050] use of bytesused == 0 is deprecated and will be removed in the future,
11049 22:12:40.147106 <4>[ 19.909922] use the actual size instead.
11050 22:12:40.153575 <4>[ 19.916074] ------------[ cut here ]------------
11051 22:12:40.160281 <4>[ 19.920986] get_vaddr_frames() cannot follow VM_IO mapping
11052 22:12:40.170484 <4>[ 19.921154] WARNING: CPU: 0 PID: 312 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11053 22:12:40.220460 <4>[ 19.939278] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 mtk_vcodec_enc mtk_vcodec_common mtk_vpu uvcvideo btusb v4l2_mem2mem videobuf2_vmalloc videobuf2_dma_contig cros_ec_rpmsg r8153_ecm btintel cdc_ether btmtk videobuf2_memops btrtl hid_google_hammer usbnet btbcm videobuf2_v4l2 sbs_battery cros_ec_chardev hid_vivaldi_common cros_ec_typec elants_i2c elan_i2c videobuf2_common bluetooth r8152 crct10dif_ce videodev ecdh_generic ecc mc rfkill pcie_mediatek_gen3 mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11054 22:12:40.229860 <4>[ 19.988666] CPU: 0 PID: 312 Comm: v4l2-compliance Not tainted 6.1.46-cip4 #1
11055 22:12:40.233679 <4>[ 19.995964] Hardware name: Google Spherion (rev0 - 3) (DT)
11056 22:12:40.243260 <4>[ 20.001699] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11057 22:12:40.246643 <4>[ 20.008911] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11058 22:12:40.253582 <4>[ 20.015003] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11059 22:12:40.256817 <4>[ 20.021094] sp : ffff8000091c3850
11060 22:12:40.263381 <4>[ 20.024658] x29: ffff8000091c3850 x28: ffffcb581c57c000 x27: ffffcb581c578238
11061 22:12:40.273220 <4>[ 20.032046] x26: 0000000000000000 x25: ffffcb586ce2c0e0 x24: ffff6db98e8c9298
11062 22:12:40.279916 <4>[ 20.039433] x23: ffff6db98a297800 x22: ffff6db980d48410 x21: 0000000000000000
11063 22:12:40.287055 <4>[ 20.046820] x20: 00000000fffffff2 x19: ffff6db989b58a00 x18: fffffffffffe9758
11064 22:12:40.293144 <4>[ 20.054207] x17: 0000000000000000 x16: ffffcb586ac8bb90 x15: 0000000000000038
11065 22:12:40.303274 <4>[ 20.061594] x14: ffffcb586d7134a8 x13: 000000000000064e x12: 000000000000021a
11066 22:12:40.309822 <4>[ 20.068980] x11: fffffffffffe9758 x10: fffffffffffe9720 x9 : 00000000fffff21a
11067 22:12:40.316345 <4>[ 20.076368] x8 : ffffcb586d7134a8 x7 : ffffcb586d76b4a8 x6 : 0000000000001938
11068 22:12:40.323399 <4>[ 20.083754] x5 : ffff6dbabef15a18 x4 : 00000000fffff21a x3 : ffffa26251ec2000
11069 22:12:40.332890 <4>[ 20.091141] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff6db98c059d80
11070 22:12:40.333443 <4>[ 20.098529] Call trace:
11071 22:12:40.339714 <4>[ 20.101225] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11072 22:12:40.346040 <4>[ 20.106969] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11073 22:12:40.352893 <4>[ 20.112972] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11074 22:12:40.359885 <4>[ 20.119325] __prepare_userptr+0x280/0x410 [videobuf2_common]
11075 22:12:40.362642 <4>[ 20.125329] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11076 22:12:40.369379 <4>[ 20.130987] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11077 22:12:40.376185 <4>[ 20.137165] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11078 22:12:40.382892 <4>[ 20.142668] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11079 22:12:40.385925 <4>[ 20.148443] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11080 22:12:40.392957 <4>[ 20.154709] v4l_prepare_buf+0x48/0x60 [videodev]
11081 22:12:40.399074 <4>[ 20.159738] __video_do_ioctl+0x184/0x3d0 [videodev]
11082 22:12:40.402653 <4>[ 20.164985] video_usercopy+0x358/0x680 [videodev]
11083 22:12:40.406181 <4>[ 20.170059] video_ioctl2+0x18/0x30 [videodev]
11084 22:12:40.413097 <4>[ 20.174785] v4l2_ioctl+0x40/0x60 [videodev]
11085 22:12:40.416104 <4>[ 20.179337] __arm64_sys_ioctl+0xa8/0xf0
11086 22:12:40.419413 <4>[ 20.183518] invoke_syscall+0x48/0x114
11087 22:12:40.426118 <4>[ 20.187523] el0_svc_common.constprop.0+0x44/0xec
11088 22:12:40.429116 <4>[ 20.192479] do_el0_svc+0x2c/0xd0
11089 22:12:40.432567 <4>[ 20.196046] el0_svc+0x2c/0x84
11090 22:12:40.436048 <4>[ 20.199354] el0t_64_sync_handler+0xb8/0xc0
11091 22:12:40.438971 <4>[ 20.203788] el0t_64_sync+0x18c/0x190
11092 22:12:40.445627 <4>[ 20.207703] ---[ end trace 0000000000000000 ]---
11093 22:12:40.459178 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11094 22:12:40.467784 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11095 22:12:40.475219
11096 22:12:40.489743 Compliance test for mtk-vcodec-enc device /dev/video2:
11097 22:12:40.498755
11098 22:12:40.510326 Driver Info:
11099 22:12:40.523889 Driver name : mtk-vcodec-enc
11100 22:12:40.541625 Card type : MT8192 video encoder
11101 22:12:40.551203 Bus info : platform:17020000.vcodec
11102 22:12:40.561889 Driver version : 6.1.46
11103 22:12:40.578473 Capabilities : 0x84204000
11104 22:12:40.588030 Video Memory-to-Memory Multiplanar
11105 22:12:40.597611 Streaming
11106 22:12:40.613938 Extended Pix Format
11107 22:12:40.624201 Device Capabilities
11108 22:12:40.634574 Device Caps : 0x04204000
11109 22:12:40.649069 Video Memory-to-Memory Multiplanar
11110 22:12:40.659475 Streaming
11111 22:12:40.676261 Extended Pix Format
11112 22:12:40.687439 Detected Stateful Encoder
11113 22:12:40.702668
11114 22:12:40.719776 Required ioctls:
11115 22:12:40.735341 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11116 22:12:40.735880 test VIDIOC_QUERYCAP: OK
11117 22:12:40.736563 Received signal: <TESTSET> START Required-ioctls
11118 22:12:40.737020 Starting test_set Required-ioctls
11119 22:12:40.759985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11120 22:12:40.760807 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11122 22:12:40.762947 test invalid ioctls: OK
11123 22:12:40.789747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11124 22:12:40.790156
11125 22:12:40.790731 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11127 22:12:40.798903 Allow for multiple opens:
11128 22:12:40.805641 <LAVA_SIGNAL_TESTSET STOP>
11129 22:12:40.806302 Received signal: <TESTSET> STOP
11130 22:12:40.806654 Closing test_set Required-ioctls
11131 22:12:40.815231 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11132 22:12:40.815891 Received signal: <TESTSET> START Allow-for-multiple-opens
11133 22:12:40.816237 Starting test_set Allow-for-multiple-opens
11134 22:12:40.818136 test second /dev/video2 open: OK
11135 22:12:40.840096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11136 22:12:40.840785 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11138 22:12:40.843148 test VIDIOC_QUERYCAP: OK
11139 22:12:40.864551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11140 22:12:40.865295 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11142 22:12:40.867951 test VIDIOC_G/S_PRIORITY: OK
11143 22:12:40.890216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11144 22:12:40.891006 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11146 22:12:40.893706 test for unlimited opens: OK
11147 22:12:40.915838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11148 22:12:40.916335
11149 22:12:40.916923 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11151 22:12:40.927417 Debug ioctls:
11152 22:12:40.935132 <LAVA_SIGNAL_TESTSET STOP>
11153 22:12:40.935905 Received signal: <TESTSET> STOP
11154 22:12:40.936262 Closing test_set Allow-for-multiple-opens
11155 22:12:40.944991 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11156 22:12:40.945819 Received signal: <TESTSET> START Debug-ioctls
11157 22:12:40.946207 Starting test_set Debug-ioctls
11158 22:12:40.947796 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11159 22:12:40.973065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11160 22:12:40.973878 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11162 22:12:40.979510 test VIDIOC_LOG_STATUS: OK (Not Supported)
11163 22:12:40.997987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11164 22:12:40.998541
11165 22:12:40.999181 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11167 22:12:41.009574 Input ioctls:
11168 22:12:41.016020 <LAVA_SIGNAL_TESTSET STOP>
11169 22:12:41.016853 Received signal: <TESTSET> STOP
11170 22:12:41.017243 Closing test_set Debug-ioctls
11171 22:12:41.028649 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11172 22:12:41.029541 Received signal: <TESTSET> START Input-ioctls
11173 22:12:41.029931 Starting test_set Input-ioctls
11174 22:12:41.031985 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11175 22:12:41.054193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11176 22:12:41.055015 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11178 22:12:41.057533 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11179 22:12:41.075179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11180 22:12:41.076001 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11182 22:12:41.081779 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11183 22:12:41.101747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11184 22:12:41.102570 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11186 22:12:41.105257 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11187 22:12:41.130660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11188 22:12:41.131367 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11190 22:12:41.134335 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11191 22:12:41.155593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11192 22:12:41.156315 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11194 22:12:41.158679 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11195 22:12:41.184354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11196 22:12:41.185073 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11198 22:12:41.187987 Inputs: 0 Audio Inputs: 0 Tuners: 0
11199 22:12:41.195223
11200 22:12:41.212174 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11201 22:12:41.232461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11202 22:12:41.233202 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11204 22:12:41.238817 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11205 22:12:41.256773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11206 22:12:41.257562 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11208 22:12:41.260463 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11209 22:12:41.285821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11210 22:12:41.286520 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11212 22:12:41.292164 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11213 22:12:41.310100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11214 22:12:41.310891 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11216 22:12:41.316730 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11217 22:12:41.339961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11218 22:12:41.340389
11219 22:12:41.341038 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11221 22:12:41.361410 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11222 22:12:41.387096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11223 22:12:41.387782 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11225 22:12:41.393551 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11226 22:12:41.415152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11227 22:12:41.415944 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11229 22:12:41.418860 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11230 22:12:41.435863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11231 22:12:41.436788 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11233 22:12:41.439339 test VIDIOC_G/S_EDID: OK (Not Supported)
11234 22:12:41.465725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11235 22:12:41.466215
11236 22:12:41.466810 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11238 22:12:41.478500 Control ioctls:
11239 22:12:41.487984 <LAVA_SIGNAL_TESTSET STOP>
11240 22:12:41.488659 Received signal: <TESTSET> STOP
11241 22:12:41.489041 Closing test_set Input-ioctls
11242 22:12:41.502008 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11243 22:12:41.502678 Received signal: <TESTSET> START Control-ioctls
11244 22:12:41.503032 Starting test_set Control-ioctls
11245 22:12:41.505361 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11246 22:12:41.528279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11247 22:12:41.528966 test VIDIOC_QUERYCTRL: OK
11248 22:12:41.529753 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11250 22:12:41.547391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11251 22:12:41.548209 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11253 22:12:41.550627 test VIDIOC_G/S_CTRL: OK
11254 22:12:41.576959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11255 22:12:41.577743 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11257 22:12:41.580004 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11258 22:12:41.601921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11259 22:12:41.602721 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11261 22:12:41.611797 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11262 22:12:41.615000 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11263 22:12:41.640635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11264 22:12:41.641527 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11266 22:12:41.643538 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11267 22:12:41.666589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11268 22:12:41.667417 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11270 22:12:41.669837 Standard Controls: 16 Private Controls: 0
11271 22:12:41.677065
11272 22:12:41.687639 Format ioctls:
11273 22:12:41.695399 <LAVA_SIGNAL_TESTSET STOP>
11274 22:12:41.696243 Received signal: <TESTSET> STOP
11275 22:12:41.696643 Closing test_set Control-ioctls
11276 22:12:41.704480 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11277 22:12:41.705373 Received signal: <TESTSET> START Format-ioctls
11278 22:12:41.705768 Starting test_set Format-ioctls
11279 22:12:41.707484 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11280 22:12:41.732391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11281 22:12:41.733284 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11283 22:12:41.735143 test VIDIOC_G/S_PARM: OK
11284 22:12:41.753663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11285 22:12:41.754518 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11287 22:12:41.756449 test VIDIOC_G_FBUF: OK (Not Supported)
11288 22:12:41.778114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11289 22:12:41.778956 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11291 22:12:41.781153 test VIDIOC_G_FMT: OK
11292 22:12:41.807063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11293 22:12:41.807893 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11295 22:12:41.809630 test VIDIOC_TRY_FMT: OK
11296 22:12:41.839343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11297 22:12:41.840165 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11299 22:12:41.849490 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11300 22:12:41.852612 test VIDIOC_S_FMT: FAIL
11301 22:12:41.875240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11302 22:12:41.876025 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11304 22:12:41.878366 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11305 22:12:41.900322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11306 22:12:41.901042 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11308 22:12:41.903506 test Cropping: OK
11309 22:12:41.924732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11310 22:12:41.925638 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11312 22:12:41.927678 test Composing: OK (Not Supported)
11313 22:12:41.946981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11314 22:12:41.947697 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11316 22:12:41.950316 test Scaling: OK (Not Supported)
11317 22:12:41.971395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11318 22:12:41.971972
11319 22:12:41.972754 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11321 22:12:41.986265 Codec ioctls:
11322 22:12:41.993816 <LAVA_SIGNAL_TESTSET STOP>
11323 22:12:41.994497 Received signal: <TESTSET> STOP
11324 22:12:41.994846 Closing test_set Format-ioctls
11325 22:12:42.004189 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11326 22:12:42.005029 Received signal: <TESTSET> START Codec-ioctls
11327 22:12:42.005397 Starting test_set Codec-ioctls
11328 22:12:42.007478 test VIDIOC_(TRY_)ENCODER_CMD: OK
11329 22:12:42.033196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11330 22:12:42.033968 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11332 22:12:42.039692 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11333 22:12:42.062834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11334 22:12:42.063604 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11336 22:12:42.069534 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11337 22:12:42.087676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11338 22:12:42.088198
11339 22:12:42.088802 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11341 22:12:42.098371 Buffer ioctls:
11342 22:12:42.107729 <LAVA_SIGNAL_TESTSET STOP>
11343 22:12:42.108405 Received signal: <TESTSET> STOP
11344 22:12:42.108799 Closing test_set Codec-ioctls
11345 22:12:42.117348 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11346 22:12:42.118025 Received signal: <TESTSET> START Buffer-ioctls
11347 22:12:42.118383 Starting test_set Buffer-ioctls
11348 22:12:42.120555 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11349 22:12:42.145105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11350 22:12:42.145192 test VIDIOC_EXPBUF: OK
11351 22:12:42.145427 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11353 22:12:42.165419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11354 22:12:42.165686 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11356 22:12:42.168546 test Requests: OK (Not Supported)
11357 22:12:42.194418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11358 22:12:42.194569
11359 22:12:42.194877 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11361 22:12:42.205727 Test input 0:
11362 22:12:42.214464
11363 22:12:42.225453 Streaming ioctls:
11364 22:12:42.232824 <LAVA_SIGNAL_TESTSET STOP>
11365 22:12:42.233507 Received signal: <TESTSET> STOP
11366 22:12:42.233858 Closing test_set Buffer-ioctls
11367 22:12:42.242454 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11368 22:12:42.243251 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11369 22:12:42.243603 Starting test_set Streaming-ioctls_Test-input-0
11370 22:12:42.245745 test read/write: OK (Not Supported)
11371 22:12:42.267607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11372 22:12:42.268367 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11374 22:12:42.274218 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11375 22:12:42.285955 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11376 22:12:42.295641 test blocking wait: FAIL
11377 22:12:42.319587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11378 22:12:42.320471 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11380 22:12:42.325952 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11381 22:12:42.331338 test MMAP (select): FAIL
11382 22:12:42.355609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11383 22:12:42.356502 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11385 22:12:42.362000 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11386 22:12:42.366095 test MMAP (epoll): FAIL
11387 22:12:42.390975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11388 22:12:42.391762 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11390 22:12:42.397806 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11391 22:12:42.414822 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11392 22:12:42.417988 test USERPTR (select): FAIL
11393 22:12:42.447765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11394 22:12:42.448456 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11396 22:12:42.454424 test DMABUF: Cannot test, specify --expbuf-device
11397 22:12:42.457965
11398 22:12:42.480287 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11399 22:12:42.484332 <LAVA_TEST_RUNNER EXIT>
11400 22:12:42.485131 ok: lava_test_shell seems to have completed
11401 22:12:42.485581 Marking unfinished test run as failed
11403 22:12:42.491587 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11404 22:12:42.492611 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11405 22:12:42.493303 end: 3 lava-test-retry (duration 00:00:03) [common]
11406 22:12:42.493916 start: 4 finalize (timeout 00:07:24) [common]
11407 22:12:42.494375 start: 4.1 power-off (timeout 00:00:30) [common]
11408 22:12:42.495705 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11409 22:12:42.617545 >> Command sent successfully.
11410 22:12:42.622199 Returned 0 in 0 seconds
11411 22:12:42.723186 end: 4.1 power-off (duration 00:00:00) [common]
11413 22:12:42.724739 start: 4.2 read-feedback (timeout 00:07:24) [common]
11414 22:12:42.725965 Listened to connection for namespace 'common' for up to 1s
11415 22:12:43.726490 Finalising connection for namespace 'common'
11416 22:12:43.726806 Disconnecting from shell: Finalise
11417 22:12:43.726966 / #
11418 22:12:43.827642 end: 4.2 read-feedback (duration 00:00:01) [common]
11419 22:12:43.828426 end: 4 finalize (duration 00:00:01) [common]
11420 22:12:43.829289 Cleaning after the job
11421 22:12:43.830085 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/ramdisk
11422 22:12:43.852121 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/kernel
11423 22:12:43.867929 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/dtb
11424 22:12:43.868200 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11440302/tftp-deploy-3bltm57_/modules
11425 22:12:43.877654 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11440302
11426 22:12:43.947373 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11440302
11427 22:12:43.947550 Job finished correctly