Boot log: mt8192-asurada-spherion-r0

    1 13:57:23.089045  lava-dispatcher, installed at version: 2023.06
    2 13:57:23.089274  start: 0 validate
    3 13:57:23.089416  Start time: 2023-08-28 13:57:23.089408+00:00 (UTC)
    4 13:57:23.089563  Using caching service: 'http://localhost/cache/?uri=%s'
    5 13:57:23.089714  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
    6 13:57:23.353892  Using caching service: 'http://localhost/cache/?uri=%s'
    7 13:57:23.354075  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 13:57:43.126740  Using caching service: 'http://localhost/cache/?uri=%s'
    9 13:57:43.127528  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 13:57:43.397757  Using caching service: 'http://localhost/cache/?uri=%s'
   11 13:57:43.398480  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   12 13:57:46.667453  validate duration: 23.58
   14 13:57:46.667818  start: 1 tftp-deploy (timeout 00:10:00) [common]
   15 13:57:46.667948  start: 1.1 download-retry (timeout 00:10:00) [common]
   16 13:57:46.668060  start: 1.1.1 http-download (timeout 00:10:00) [common]
   17 13:57:46.668222  Not decompressing ramdisk as can be used compressed.
   18 13:57:46.668335  downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
   19 13:57:46.668423  saving as /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/ramdisk/rootfs.cpio.gz
   20 13:57:46.668506  total size: 8181372 (7 MB)
   21 13:57:46.669816  progress   0 % (0 MB)
   22 13:57:46.672326  progress   5 % (0 MB)
   23 13:57:46.674428  progress  10 % (0 MB)
   24 13:57:46.676733  progress  15 % (1 MB)
   25 13:57:46.678815  progress  20 % (1 MB)
   26 13:57:46.681070  progress  25 % (1 MB)
   27 13:57:46.683138  progress  30 % (2 MB)
   28 13:57:46.685610  progress  35 % (2 MB)
   29 13:57:46.687928  progress  40 % (3 MB)
   30 13:57:46.690192  progress  45 % (3 MB)
   31 13:57:46.692555  progress  50 % (3 MB)
   32 13:57:46.694848  progress  55 % (4 MB)
   33 13:57:46.696952  progress  60 % (4 MB)
   34 13:57:46.699176  progress  65 % (5 MB)
   35 13:57:46.701218  progress  70 % (5 MB)
   36 13:57:46.703436  progress  75 % (5 MB)
   37 13:57:46.705485  progress  80 % (6 MB)
   38 13:57:46.707697  progress  85 % (6 MB)
   39 13:57:46.709744  progress  90 % (7 MB)
   40 13:57:46.711988  progress  95 % (7 MB)
   41 13:57:46.714046  progress 100 % (7 MB)
   42 13:57:46.714245  7 MB downloaded in 0.05 s (170.58 MB/s)
   43 13:57:46.714398  end: 1.1.1 http-download (duration 00:00:00) [common]
   45 13:57:46.714637  end: 1.1 download-retry (duration 00:00:00) [common]
   46 13:57:46.714723  start: 1.2 download-retry (timeout 00:10:00) [common]
   47 13:57:46.714808  start: 1.2.1 http-download (timeout 00:10:00) [common]
   48 13:57:46.714947  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   49 13:57:46.715018  saving as /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/kernel/Image
   50 13:57:46.715079  total size: 49222144 (46 MB)
   51 13:57:46.715139  No compression specified
   52 13:57:46.716309  progress   0 % (0 MB)
   53 13:57:46.729048  progress   5 % (2 MB)
   54 13:57:46.741829  progress  10 % (4 MB)
   55 13:57:46.754775  progress  15 % (7 MB)
   56 13:57:46.767490  progress  20 % (9 MB)
   57 13:57:46.780202  progress  25 % (11 MB)
   58 13:57:46.793029  progress  30 % (14 MB)
   59 13:57:46.805758  progress  35 % (16 MB)
   60 13:57:46.818512  progress  40 % (18 MB)
   61 13:57:46.831304  progress  45 % (21 MB)
   62 13:57:46.844247  progress  50 % (23 MB)
   63 13:57:46.857105  progress  55 % (25 MB)
   64 13:57:46.870040  progress  60 % (28 MB)
   65 13:57:46.882712  progress  65 % (30 MB)
   66 13:57:46.895515  progress  70 % (32 MB)
   67 13:57:46.908283  progress  75 % (35 MB)
   68 13:57:46.921010  progress  80 % (37 MB)
   69 13:57:46.933886  progress  85 % (39 MB)
   70 13:57:46.946586  progress  90 % (42 MB)
   71 13:57:46.959306  progress  95 % (44 MB)
   72 13:57:46.971947  progress 100 % (46 MB)
   73 13:57:46.972118  46 MB downloaded in 0.26 s (182.63 MB/s)
   74 13:57:46.972275  end: 1.2.1 http-download (duration 00:00:00) [common]
   76 13:57:46.972516  end: 1.2 download-retry (duration 00:00:00) [common]
   77 13:57:46.972609  start: 1.3 download-retry (timeout 00:10:00) [common]
   78 13:57:46.972696  start: 1.3.1 http-download (timeout 00:10:00) [common]
   79 13:57:46.972835  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   80 13:57:46.972905  saving as /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/dtb/mt8192-asurada-spherion-r0.dtb
   81 13:57:46.972966  total size: 47278 (0 MB)
   82 13:57:46.973029  No compression specified
   83 13:57:46.974137  progress  69 % (0 MB)
   84 13:57:46.974414  progress 100 % (0 MB)
   85 13:57:46.974571  0 MB downloaded in 0.00 s (28.15 MB/s)
   86 13:57:46.974694  end: 1.3.1 http-download (duration 00:00:00) [common]
   88 13:57:46.974918  end: 1.3 download-retry (duration 00:00:00) [common]
   89 13:57:46.975005  start: 1.4 download-retry (timeout 00:10:00) [common]
   90 13:57:46.975089  start: 1.4.1 http-download (timeout 00:10:00) [common]
   91 13:57:46.975208  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
   92 13:57:46.975276  saving as /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/modules/modules.tar
   93 13:57:46.975336  total size: 8615960 (8 MB)
   94 13:57:46.975407  Using unxz to decompress xz
   95 13:57:46.979542  progress   0 % (0 MB)
   96 13:57:47.001069  progress   5 % (0 MB)
   97 13:57:47.023545  progress  10 % (0 MB)
   98 13:57:47.049875  progress  15 % (1 MB)
   99 13:57:47.075198  progress  20 % (1 MB)
  100 13:57:47.101894  progress  25 % (2 MB)
  101 13:57:47.129226  progress  30 % (2 MB)
  102 13:57:47.157062  progress  35 % (2 MB)
  103 13:57:47.183024  progress  40 % (3 MB)
  104 13:57:47.208500  progress  45 % (3 MB)
  105 13:57:47.235443  progress  50 % (4 MB)
  106 13:57:47.260984  progress  55 % (4 MB)
  107 13:57:47.285935  progress  60 % (4 MB)
  108 13:57:47.308945  progress  65 % (5 MB)
  109 13:57:47.336880  progress  70 % (5 MB)
  110 13:57:47.361420  progress  75 % (6 MB)
  111 13:57:47.388035  progress  80 % (6 MB)
  112 13:57:47.418325  progress  85 % (7 MB)
  113 13:57:47.445075  progress  90 % (7 MB)
  114 13:57:47.469763  progress  95 % (7 MB)
  115 13:57:47.493257  progress 100 % (8 MB)
  116 13:57:47.499683  8 MB downloaded in 0.52 s (15.67 MB/s)
  117 13:57:47.500049  end: 1.4.1 http-download (duration 00:00:01) [common]
  119 13:57:47.500489  end: 1.4 download-retry (duration 00:00:01) [common]
  120 13:57:47.500631  start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
  121 13:57:47.500783  start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
  122 13:57:47.500917  end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
  123 13:57:47.501053  start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
  124 13:57:47.501376  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n
  125 13:57:47.501586  makedir: /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin
  126 13:57:47.501745  makedir: /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/tests
  127 13:57:47.501900  makedir: /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/results
  128 13:57:47.502074  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-add-keys
  129 13:57:47.502291  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-add-sources
  130 13:57:47.502496  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-background-process-start
  131 13:57:47.502690  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-background-process-stop
  132 13:57:47.502880  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-common-functions
  133 13:57:47.503069  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-echo-ipv4
  134 13:57:47.503268  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-install-packages
  135 13:57:47.503475  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-installed-packages
  136 13:57:47.503666  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-os-build
  137 13:57:47.503861  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-probe-channel
  138 13:57:47.504051  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-probe-ip
  139 13:57:47.504241  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-target-ip
  140 13:57:47.504430  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-target-mac
  141 13:57:47.504629  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-target-storage
  142 13:57:47.504828  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-test-case
  143 13:57:47.505020  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-test-event
  144 13:57:47.505214  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-test-feedback
  145 13:57:47.505411  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-test-raise
  146 13:57:47.505607  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-test-reference
  147 13:57:47.505806  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-test-runner
  148 13:57:47.506004  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-test-set
  149 13:57:47.506202  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-test-shell
  150 13:57:47.506406  Updating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-install-packages (oe)
  151 13:57:47.506635  Updating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/bin/lava-installed-packages (oe)
  152 13:57:47.506819  Creating /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/environment
  153 13:57:47.506975  LAVA metadata
  154 13:57:47.507093  - LAVA_JOB_ID=11372182
  155 13:57:47.507204  - LAVA_DISPATCHER_IP=192.168.201.1
  156 13:57:47.507361  start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
  157 13:57:47.507475  skipped lava-vland-overlay
  158 13:57:47.507597  end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
  159 13:57:47.507728  start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
  160 13:57:47.507841  skipped lava-multinode-overlay
  161 13:57:47.507976  end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  162 13:57:47.508112  start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
  163 13:57:47.508235  Loading test definitions
  164 13:57:47.508383  start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
  165 13:57:47.508504  Using /lava-11372182 at stage 0
  166 13:57:47.508992  uuid=11372182_1.5.2.3.1 testdef=None
  167 13:57:47.509125  end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
  168 13:57:47.509255  start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
  169 13:57:47.510077  end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
  171 13:57:47.510435  start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
  172 13:57:47.511443  end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
  174 13:57:47.511818  start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
  175 13:57:47.512800  runner path: /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/0/tests/0_dmesg test_uuid 11372182_1.5.2.3.1
  176 13:57:47.513019  end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  178 13:57:47.513389  start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
  179 13:57:47.513499  Using /lava-11372182 at stage 1
  180 13:57:47.513962  uuid=11372182_1.5.2.3.5 testdef=None
  181 13:57:47.514096  end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
  182 13:57:47.514225  start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
  183 13:57:47.514980  end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
  185 13:57:47.515329  start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
  186 13:57:47.516958  end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
  188 13:57:47.517324  start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
  189 13:57:47.518305  runner path: /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/1/tests/1_bootrr test_uuid 11372182_1.5.2.3.5
  190 13:57:47.518525  end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
  192 13:57:47.518867  Creating lava-test-runner.conf files
  193 13:57:47.518968  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/0 for stage 0
  194 13:57:47.519110  - 0_dmesg
  195 13:57:47.519232  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11372182/lava-overlay-tdyl0v5n/lava-11372182/1 for stage 1
  196 13:57:47.519378  - 1_bootrr
  197 13:57:47.519529  end: 1.5.2.3 test-definition (duration 00:00:00) [common]
  198 13:57:47.519662  start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
  199 13:57:47.531672  end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
  200 13:57:47.531846  start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
  201 13:57:47.531979  end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  202 13:57:47.532115  end: 1.5.2 lava-overlay (duration 00:00:00) [common]
  203 13:57:47.532251  start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
  204 13:57:47.793898  end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  205 13:57:47.794386  start: 1.5.4 extract-modules (timeout 00:09:59) [common]
  206 13:57:47.794544  extracting modules file /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11372182/extract-overlay-ramdisk-3r3d6qxk/ramdisk
  207 13:57:48.034885  end: 1.5.4 extract-modules (duration 00:00:00) [common]
  208 13:57:48.035052  start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
  209 13:57:48.035150  [common] Applying overlay /var/lib/lava/dispatcher/tmp/11372182/compress-overlay-1xdh1ty3/overlay-1.5.2.4.tar.gz to ramdisk
  210 13:57:48.035223  [common] Applying overlay /var/lib/lava/dispatcher/tmp/11372182/compress-overlay-1xdh1ty3/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11372182/extract-overlay-ramdisk-3r3d6qxk/ramdisk
  211 13:57:48.043653  end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
  212 13:57:48.043796  start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
  213 13:57:48.043888  end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
  214 13:57:48.043978  start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
  215 13:57:48.044058  Building ramdisk /var/lib/lava/dispatcher/tmp/11372182/extract-overlay-ramdisk-3r3d6qxk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11372182/extract-overlay-ramdisk-3r3d6qxk/ramdisk
  216 13:57:48.440202  >> 145138 blocks

  217 13:57:50.715227  rename /var/lib/lava/dispatcher/tmp/11372182/extract-overlay-ramdisk-3r3d6qxk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/ramdisk/ramdisk.cpio.gz
  218 13:57:50.715773  end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
  219 13:57:50.715919  start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
  220 13:57:50.716053  start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
  221 13:57:50.716176  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/kernel/Image'
  222 13:58:03.820525  Returned 0 in 13 seconds
  223 13:58:03.921140  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/kernel/image.itb
  224 13:58:04.326883  output: FIT description: Kernel Image image with one or more FDT blobs
  225 13:58:04.327263  output: Created:         Mon Aug 28 14:58:04 2023
  226 13:58:04.327343  output:  Image 0 (kernel-1)
  227 13:58:04.327525  output:   Description:  
  228 13:58:04.327594  output:   Created:      Mon Aug 28 14:58:04 2023
  229 13:58:04.327659  output:   Type:         Kernel Image
  230 13:58:04.327760  output:   Compression:  lzma compressed
  231 13:58:04.327825  output:   Data Size:    11039834 Bytes = 10781.09 KiB = 10.53 MiB
  232 13:58:04.327888  output:   Architecture: AArch64
  233 13:58:04.327950  output:   OS:           Linux
  234 13:58:04.328028  output:   Load Address: 0x00000000
  235 13:58:04.328087  output:   Entry Point:  0x00000000
  236 13:58:04.328149  output:   Hash algo:    crc32
  237 13:58:04.328207  output:   Hash value:   946c5cd4
  238 13:58:04.328280  output:  Image 1 (fdt-1)
  239 13:58:04.328393  output:   Description:  mt8192-asurada-spherion-r0
  240 13:58:04.328485  output:   Created:      Mon Aug 28 14:58:04 2023
  241 13:58:04.328555  output:   Type:         Flat Device Tree
  242 13:58:04.328610  output:   Compression:  uncompressed
  243 13:58:04.328665  output:   Data Size:    47278 Bytes = 46.17 KiB = 0.05 MiB
  244 13:58:04.328720  output:   Architecture: AArch64
  245 13:58:04.328774  output:   Hash algo:    crc32
  246 13:58:04.328828  output:   Hash value:   cc4352de
  247 13:58:04.328883  output:  Image 2 (ramdisk-1)
  248 13:58:04.328937  output:   Description:  unavailable
  249 13:58:04.328992  output:   Created:      Mon Aug 28 14:58:04 2023
  250 13:58:04.329046  output:   Type:         RAMDisk Image
  251 13:58:04.329100  output:   Compression:  Unknown Compression
  252 13:58:04.329154  output:   Data Size:    21368684 Bytes = 20867.86 KiB = 20.38 MiB
  253 13:58:04.329208  output:   Architecture: AArch64
  254 13:58:04.329282  output:   OS:           Linux
  255 13:58:04.329338  output:   Load Address: unavailable
  256 13:58:04.329400  output:   Entry Point:  unavailable
  257 13:58:04.329455  output:   Hash algo:    crc32
  258 13:58:04.329510  output:   Hash value:   f4829b1c
  259 13:58:04.329564  output:  Default Configuration: 'conf-1'
  260 13:58:04.329619  output:  Configuration 0 (conf-1)
  261 13:58:04.329673  output:   Description:  mt8192-asurada-spherion-r0
  262 13:58:04.329727  output:   Kernel:       kernel-1
  263 13:58:04.329809  output:   Init Ramdisk: ramdisk-1
  264 13:58:04.329868  output:   FDT:          fdt-1
  265 13:58:04.329922  output:   Loadables:    kernel-1
  266 13:58:04.329977  output: 
  267 13:58:04.330198  end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
  268 13:58:04.330325  end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
  269 13:58:04.330440  end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
  270 13:58:04.330540  start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
  271 13:58:04.330628  No LXC device requested
  272 13:58:04.330712  end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
  273 13:58:04.330799  start: 1.7 deploy-device-env (timeout 00:09:42) [common]
  274 13:58:04.330878  end: 1.7 deploy-device-env (duration 00:00:00) [common]
  275 13:58:04.330950  Checking files for TFTP limit of 4294967296 bytes.
  276 13:58:04.331540  end: 1 tftp-deploy (duration 00:00:18) [common]
  277 13:58:04.331647  start: 2 depthcharge-action (timeout 00:05:00) [common]
  278 13:58:04.331742  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  279 13:58:04.331873  substitutions:
  280 13:58:04.331943  - {DTB}: 11372182/tftp-deploy-cl_h_2zg/dtb/mt8192-asurada-spherion-r0.dtb
  281 13:58:04.332009  - {INITRD}: 11372182/tftp-deploy-cl_h_2zg/ramdisk/ramdisk.cpio.gz
  282 13:58:04.332073  - {KERNEL}: 11372182/tftp-deploy-cl_h_2zg/kernel/Image
  283 13:58:04.332132  - {LAVA_MAC}: None
  284 13:58:04.332206  - {PRESEED_CONFIG}: None
  285 13:58:04.332310  - {PRESEED_LOCAL}: None
  286 13:58:04.332407  - {RAMDISK}: 11372182/tftp-deploy-cl_h_2zg/ramdisk/ramdisk.cpio.gz
  287 13:58:04.332506  - {ROOT_PART}: None
  288 13:58:04.332590  - {ROOT}: None
  289 13:58:04.332649  - {SERVER_IP}: 192.168.201.1
  290 13:58:04.332706  - {TEE}: None
  291 13:58:04.332765  Parsed boot commands:
  292 13:58:04.332820  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  293 13:58:04.333020  Parsed boot commands: tftpboot 192.168.201.1 11372182/tftp-deploy-cl_h_2zg/kernel/image.itb 11372182/tftp-deploy-cl_h_2zg/kernel/cmdline 
  294 13:58:04.333112  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  295 13:58:04.333202  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  296 13:58:04.333315  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  297 13:58:04.333408  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  298 13:58:04.333486  Not connected, no need to disconnect.
  299 13:58:04.333565  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  300 13:58:04.333657  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  301 13:58:04.333728  [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
  302 13:58:04.337759  Setting prompt string to ['lava-test: # ']
  303 13:58:04.338225  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  304 13:58:04.338353  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  305 13:58:04.338492  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  306 13:58:04.338796  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  307 13:58:04.339042  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
  308 13:58:09.475174  >> Command sent successfully.

  309 13:58:09.477826  Returned 0 in 5 seconds
  310 13:58:09.578399  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  312 13:58:09.579132  end: 2.2.2 reset-device (duration 00:00:05) [common]
  313 13:58:09.579349  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  314 13:58:09.579556  Setting prompt string to 'Starting depthcharge on Spherion...'
  315 13:58:09.579720  Changing prompt to 'Starting depthcharge on Spherion...'
  316 13:58:09.579888  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  317 13:58:09.580466  [Enter `^Ec?' for help]

  318 13:58:09.751737  

  319 13:58:09.752024  

  320 13:58:09.752188  F0: 102B 0000

  321 13:58:09.752340  

  322 13:58:09.752488  F3: 1001 0000 [0200]

  323 13:58:09.755328  

  324 13:58:09.755534  F3: 1001 0000

  325 13:58:09.755684  

  326 13:58:09.755830  F7: 102D 0000

  327 13:58:09.755974  

  328 13:58:09.758516  F1: 0000 0000

  329 13:58:09.758679  

  330 13:58:09.758825  V0: 0000 0000 [0001]

  331 13:58:09.758975  

  332 13:58:09.761995  00: 0007 8000

  333 13:58:09.762164  

  334 13:58:09.762311  01: 0000 0000

  335 13:58:09.762458  

  336 13:58:09.765505  BP: 0C00 0209 [0000]

  337 13:58:09.765665  

  338 13:58:09.765810  G0: 1182 0000

  339 13:58:09.765954  

  340 13:58:09.768580  EC: 0000 0021 [4000]

  341 13:58:09.768721  

  342 13:58:09.768846  S7: 0000 0000 [0000]

  343 13:58:09.768970  

  344 13:58:09.772373  CC: 0000 0000 [0001]

  345 13:58:09.772518  

  346 13:58:09.772646  T0: 0000 0040 [010F]

  347 13:58:09.772771  

  348 13:58:09.772897  Jump to BL

  349 13:58:09.773020  

  350 13:58:09.798735  

  351 13:58:09.798868  

  352 13:58:09.798954  

  353 13:58:09.805859  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  354 13:58:09.808921  ARM64: Exception handlers installed.

  355 13:58:09.813445  ARM64: Testing exception

  356 13:58:09.816284  ARM64: Done test exception

  357 13:58:09.822820  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  358 13:58:09.832811  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  359 13:58:09.839622  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  360 13:58:09.849435  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  361 13:58:09.856578  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  362 13:58:09.866576  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  363 13:58:09.877917  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  364 13:58:09.883600  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  365 13:58:09.901576  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  366 13:58:09.905300  WDT: Last reset was cold boot

  367 13:58:09.908348  SPI1(PAD0) initialized at 2873684 Hz

  368 13:58:09.911684  SPI5(PAD0) initialized at 992727 Hz

  369 13:58:09.915176  VBOOT: Loading verstage.

  370 13:58:09.921433  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  371 13:58:09.924954  FMAP: Found "FLASH" version 1.1 at 0x20000.

  372 13:58:09.928483  FMAP: base = 0x0 size = 0x800000 #areas = 25

  373 13:58:09.931655  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  374 13:58:09.939092  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  375 13:58:09.945893  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  376 13:58:09.956760  read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps

  377 13:58:09.956893  

  378 13:58:09.957015  

  379 13:58:09.966370  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  380 13:58:09.970034  ARM64: Exception handlers installed.

  381 13:58:09.973066  ARM64: Testing exception

  382 13:58:09.973152  ARM64: Done test exception

  383 13:58:09.979875  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  384 13:58:09.983564  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  385 13:58:09.997706  Probing TPM: . done!

  386 13:58:09.997798  TPM ready after 0 ms

  387 13:58:10.004153  Connected to device vid:did:rid of 1ae0:0028:00

  388 13:58:10.011087  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

  389 13:58:10.052529  Initialized TPM device CR50 revision 0

  390 13:58:10.064820  tlcl_send_startup: Startup return code is 0

  391 13:58:10.065353  TPM: setup succeeded

  392 13:58:10.076293  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  393 13:58:10.084882  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  394 13:58:10.096672  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  395 13:58:10.107619  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  396 13:58:10.111025  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  397 13:58:10.114663  in-header: 03 07 00 00 08 00 00 00 

  398 13:58:10.117913  in-data: aa e4 47 04 13 02 00 00 

  399 13:58:10.118498  Chrome EC: UHEPI supported

  400 13:58:10.124869  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  401 13:58:10.129685  in-header: 03 9d 00 00 08 00 00 00 

  402 13:58:10.133288  in-data: 10 20 20 08 00 00 00 00 

  403 13:58:10.133724  Phase 1

  404 13:58:10.140225  FMAP: area GBB found @ 3f5000 (12032 bytes)

  405 13:58:10.143561  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  406 13:58:10.151039  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  407 13:58:10.154476  Recovery requested (1009000e)

  408 13:58:10.160440  TPM: Extending digest for VBOOT: boot mode into PCR 0

  409 13:58:10.166266  tlcl_extend: response is 0

  410 13:58:10.173792  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  411 13:58:10.179311  tlcl_extend: response is 0

  412 13:58:10.186212  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  413 13:58:10.207295  read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps

  414 13:58:10.214706  BS: bootblock times (exec / console): total (unknown) / 148 ms

  415 13:58:10.215237  

  416 13:58:10.215623  

  417 13:58:10.221780  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  418 13:58:10.225648  ARM64: Exception handlers installed.

  419 13:58:10.229167  ARM64: Testing exception

  420 13:58:10.232388  ARM64: Done test exception

  421 13:58:10.252344  pmic_efuse_setting: Set efuses in 11 msecs

  422 13:58:10.256015  pmwrap_interface_init: Select PMIF_VLD_RDY

  423 13:58:10.259741  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  424 13:58:10.267027  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  425 13:58:10.270652  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  426 13:58:10.274173  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  427 13:58:10.281558  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  428 13:58:10.285475  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  429 13:58:10.289060  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  430 13:58:10.296124  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  431 13:58:10.298997  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  432 13:58:10.306174  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  433 13:58:10.309062  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  434 13:58:10.312363  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  435 13:58:10.319814  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  436 13:58:10.322810  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  437 13:58:10.329745  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  438 13:58:10.336150  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  439 13:58:10.342503  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  440 13:58:10.346163  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  441 13:58:10.352753  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  442 13:58:10.360661  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  443 13:58:10.364395  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  444 13:58:10.367913  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  445 13:58:10.374955  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  446 13:58:10.381897  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  447 13:58:10.385209  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  448 13:58:10.391744  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  449 13:58:10.395274  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  450 13:58:10.402497  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  451 13:58:10.405697  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  452 13:58:10.409199  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  453 13:58:10.416181  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  454 13:58:10.420200  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  455 13:58:10.427677  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  456 13:58:10.431302  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  457 13:58:10.435260  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  458 13:58:10.442913  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  459 13:58:10.446844  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  460 13:58:10.449571  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  461 13:58:10.456631  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  462 13:58:10.459366  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  463 13:58:10.462941  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  464 13:58:10.469510  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  465 13:58:10.473048  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  466 13:58:10.476203  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  467 13:58:10.482607  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  468 13:58:10.486269  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  469 13:58:10.489738  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  470 13:58:10.493031  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  471 13:58:10.499715  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  472 13:58:10.502742  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  473 13:58:10.506449  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  474 13:58:10.516177  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  475 13:58:10.523161  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  476 13:58:10.529653  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  477 13:58:10.536106  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  478 13:58:10.546233  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  479 13:58:10.549690  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  480 13:58:10.552735  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  481 13:58:10.559312  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  482 13:58:10.566334  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x1e

  483 13:58:10.569291  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  484 13:58:10.576646  [RTC]rtc_osc_init,62: osc32con val = 0xde6f

  485 13:58:10.579945  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  486 13:58:10.589627  [RTC]rtc_get_frequency_meter,154: input=15, output=793

  487 13:58:10.592861  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f

  488 13:58:10.599954  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  489 13:58:10.603181  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  490 13:58:10.605945  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  491 13:58:10.609507  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  492 13:58:10.612809  ADC[4]: Raw value=895561 ID=7

  493 13:58:10.616203  ADC[3]: Raw value=213070 ID=1

  494 13:58:10.616627  RAM Code: 0x71

  495 13:58:10.622904  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  496 13:58:10.626538  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  497 13:58:10.636583  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  498 13:58:10.643227  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  499 13:58:10.646860  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  500 13:58:10.649819  in-header: 03 07 00 00 08 00 00 00 

  501 13:58:10.653619  in-data: aa e4 47 04 13 02 00 00 

  502 13:58:10.654214  Chrome EC: UHEPI supported

  503 13:58:10.660501  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  504 13:58:10.664516  in-header: 03 d5 00 00 08 00 00 00 

  505 13:58:10.668244  in-data: 98 20 60 08 00 00 00 00 

  506 13:58:10.671868  MRC: failed to locate region type 0.

  507 13:58:10.679113  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  508 13:58:10.682725  DRAM-K: Running full calibration

  509 13:58:10.686487  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  510 13:58:10.690120  header.status = 0x0

  511 13:58:10.693738  header.version = 0x6 (expected: 0x6)

  512 13:58:10.696845  header.size = 0xd00 (expected: 0xd00)

  513 13:58:10.697455  header.flags = 0x0

  514 13:58:10.703457  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  515 13:58:10.722288  read SPI 0x72590 0x1c583: 12504 us, 9284 KB/s, 74.272 Mbps

  516 13:58:10.729159  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  517 13:58:10.733420  dram_init: ddr_geometry: 2

  518 13:58:10.733612  [EMI] MDL number = 2

  519 13:58:10.736939  [EMI] Get MDL freq = 0

  520 13:58:10.737125  dram_init: ddr_type: 0

  521 13:58:10.740607  is_discrete_lpddr4: 1

  522 13:58:10.744258  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  523 13:58:10.744542  

  524 13:58:10.744778  

  525 13:58:10.744983  [Bian_co] ETT version 0.0.0.1

  526 13:58:10.751470   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  527 13:58:10.751660  

  528 13:58:10.755104  dramc_set_vcore_voltage set vcore to 650000

  529 13:58:10.755288  Read voltage for 800, 4

  530 13:58:10.759152  Vio18 = 0

  531 13:58:10.759336  Vcore = 650000

  532 13:58:10.759516  Vdram = 0

  533 13:58:10.759656  Vddq = 0

  534 13:58:10.763295  Vmddr = 0

  535 13:58:10.763500  dram_init: config_dvfs: 1

  536 13:58:10.770758  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  537 13:58:10.774324  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  538 13:58:10.777918  [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9

  539 13:58:10.781607  freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9

  540 13:58:10.785242  [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9

  541 13:58:10.789132  freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9

  542 13:58:10.793242  MEM_TYPE=3, freq_sel=18

  543 13:58:10.793521  sv_algorithm_assistance_LP4_1600 

  544 13:58:10.800260  ============ PULL DRAM RESETB DOWN ============

  545 13:58:10.803179  ========== PULL DRAM RESETB DOWN end =========

  546 13:58:10.806629  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  547 13:58:10.810055  =================================== 

  548 13:58:10.813419  LPDDR4 DRAM CONFIGURATION

  549 13:58:10.816307  =================================== 

  550 13:58:10.820061  EX_ROW_EN[0]    = 0x0

  551 13:58:10.820488  EX_ROW_EN[1]    = 0x0

  552 13:58:10.823479  LP4Y_EN      = 0x0

  553 13:58:10.824111  WORK_FSP     = 0x0

  554 13:58:10.826954  WL           = 0x2

  555 13:58:10.827420  RL           = 0x2

  556 13:58:10.830208  BL           = 0x2

  557 13:58:10.830646  RPST         = 0x0

  558 13:58:10.833670  RD_PRE       = 0x0

  559 13:58:10.834137  WR_PRE       = 0x1

  560 13:58:10.836667  WR_PST       = 0x0

  561 13:58:10.837186  DBI_WR       = 0x0

  562 13:58:10.839828  DBI_RD       = 0x0

  563 13:58:10.840276  OTF          = 0x1

  564 13:58:10.843470  =================================== 

  565 13:58:10.846626  =================================== 

  566 13:58:10.850345  ANA top config

  567 13:58:10.853765  =================================== 

  568 13:58:10.854283  DLL_ASYNC_EN            =  0

  569 13:58:10.856573  ALL_SLAVE_EN            =  1

  570 13:58:10.860091  NEW_RANK_MODE           =  1

  571 13:58:10.863690  DLL_IDLE_MODE           =  1

  572 13:58:10.866599  LP45_APHY_COMB_EN       =  1

  573 13:58:10.867022  TX_ODT_DIS              =  1

  574 13:58:10.870017  NEW_8X_MODE             =  1

  575 13:58:10.873789  =================================== 

  576 13:58:10.876840  =================================== 

  577 13:58:10.880279  data_rate                  = 1600

  578 13:58:10.883435  CKR                        = 1

  579 13:58:10.886486  DQ_P2S_RATIO               = 8

  580 13:58:10.889888  =================================== 

  581 13:58:10.890436  CA_P2S_RATIO               = 8

  582 13:58:10.893565  DQ_CA_OPEN                 = 0

  583 13:58:10.896891  DQ_SEMI_OPEN               = 0

  584 13:58:10.899868  CA_SEMI_OPEN               = 0

  585 13:58:10.903497  CA_FULL_RATE               = 0

  586 13:58:10.906768  DQ_CKDIV4_EN               = 1

  587 13:58:10.907216  CA_CKDIV4_EN               = 1

  588 13:58:10.910676  CA_PREDIV_EN               = 0

  589 13:58:10.913725  PH8_DLY                    = 0

  590 13:58:10.917179  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  591 13:58:10.919847  DQ_AAMCK_DIV               = 4

  592 13:58:10.923162  CA_AAMCK_DIV               = 4

  593 13:58:10.923840  CA_ADMCK_DIV               = 4

  594 13:58:10.927275  DQ_TRACK_CA_EN             = 0

  595 13:58:10.929889  CA_PICK                    = 800

  596 13:58:10.933301  CA_MCKIO                   = 800

  597 13:58:10.936878  MCKIO_SEMI                 = 0

  598 13:58:10.940423  PLL_FREQ                   = 3068

  599 13:58:10.943344  DQ_UI_PI_RATIO             = 32

  600 13:58:10.943820  CA_UI_PI_RATIO             = 0

  601 13:58:10.947060  =================================== 

  602 13:58:10.949877  =================================== 

  603 13:58:10.953674  memory_type:LPDDR4         

  604 13:58:10.956790  GP_NUM     : 10       

  605 13:58:10.957396  SRAM_EN    : 1       

  606 13:58:10.960369  MD32_EN    : 0       

  607 13:58:10.963624  =================================== 

  608 13:58:10.966974  [ANA_INIT] >>>>>>>>>>>>>> 

  609 13:58:10.967461  <<<<<< [CONFIGURE PHASE]: ANA_TX

  610 13:58:10.970316  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  611 13:58:10.973316  =================================== 

  612 13:58:10.976928  data_rate = 1600,PCW = 0X7600

  613 13:58:10.980285  =================================== 

  614 13:58:10.983267  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  615 13:58:10.989799  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  616 13:58:10.996860  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  617 13:58:10.999682  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  618 13:58:11.003334  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  619 13:58:11.007303  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  620 13:58:11.007447  [ANA_INIT] flow start 

  621 13:58:11.010808  [ANA_INIT] PLL >>>>>>>> 

  622 13:58:11.014453  [ANA_INIT] PLL <<<<<<<< 

  623 13:58:11.014571  [ANA_INIT] MIDPI >>>>>>>> 

  624 13:58:11.018117  [ANA_INIT] MIDPI <<<<<<<< 

  625 13:58:11.021925  [ANA_INIT] DLL >>>>>>>> 

  626 13:58:11.022010  [ANA_INIT] flow end 

  627 13:58:11.025421  ============ LP4 DIFF to SE enter ============

  628 13:58:11.029065  ============ LP4 DIFF to SE exit  ============

  629 13:58:11.032680  [ANA_INIT] <<<<<<<<<<<<< 

  630 13:58:11.036658  [Flow] Enable top DCM control >>>>> 

  631 13:58:11.039998  [Flow] Enable top DCM control <<<<< 

  632 13:58:11.043791  Enable DLL master slave shuffle 

  633 13:58:11.046690  ============================================================== 

  634 13:58:11.050186  Gating Mode config

  635 13:58:11.053956  ============================================================== 

  636 13:58:11.057129  Config description: 

  637 13:58:11.066607  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  638 13:58:11.073900  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  639 13:58:11.076649  SELPH_MODE            0: By rank         1: By Phase 

  640 13:58:11.083500  ============================================================== 

  641 13:58:11.086822  GAT_TRACK_EN                 =  1

  642 13:58:11.090470  RX_GATING_MODE               =  2

  643 13:58:11.093280  RX_GATING_TRACK_MODE         =  2

  644 13:58:11.096946  SELPH_MODE                   =  1

  645 13:58:11.099908  PICG_EARLY_EN                =  1

  646 13:58:11.100011  VALID_LAT_VALUE              =  1

  647 13:58:11.107152  ============================================================== 

  648 13:58:11.110237  Enter into Gating configuration >>>> 

  649 13:58:11.113187  Exit from Gating configuration <<<< 

  650 13:58:11.116605  Enter into  DVFS_PRE_config >>>>> 

  651 13:58:11.126644  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  652 13:58:11.130441  Exit from  DVFS_PRE_config <<<<< 

  653 13:58:11.133854  Enter into PICG configuration >>>> 

  654 13:58:11.137112  Exit from PICG configuration <<<< 

  655 13:58:11.140318  [RX_INPUT] configuration >>>>> 

  656 13:58:11.143294  [RX_INPUT] configuration <<<<< 

  657 13:58:11.147051  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  658 13:58:11.153938  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  659 13:58:11.160871  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  660 13:58:11.164921  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  661 13:58:11.171983  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  662 13:58:11.179101  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  663 13:58:11.182927  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  664 13:58:11.186310  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  665 13:58:11.189987  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  666 13:58:11.193099  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  667 13:58:11.200804  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  668 13:58:11.203924  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  669 13:58:11.207704  =================================== 

  670 13:58:11.207787  LPDDR4 DRAM CONFIGURATION

  671 13:58:11.211230  =================================== 

  672 13:58:11.214899  EX_ROW_EN[0]    = 0x0

  673 13:58:11.214983  EX_ROW_EN[1]    = 0x0

  674 13:58:11.218571  LP4Y_EN      = 0x0

  675 13:58:11.218654  WORK_FSP     = 0x0

  676 13:58:11.222054  WL           = 0x2

  677 13:58:11.222137  RL           = 0x2

  678 13:58:11.226001  BL           = 0x2

  679 13:58:11.226085  RPST         = 0x0

  680 13:58:11.229673  RD_PRE       = 0x0

  681 13:58:11.229757  WR_PRE       = 0x1

  682 13:58:11.233463  WR_PST       = 0x0

  683 13:58:11.233547  DBI_WR       = 0x0

  684 13:58:11.233612  DBI_RD       = 0x0

  685 13:58:11.237031  OTF          = 0x1

  686 13:58:11.241256  =================================== 

  687 13:58:11.244491  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  688 13:58:11.248653  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  689 13:58:11.252316  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  690 13:58:11.255248  =================================== 

  691 13:58:11.258887  LPDDR4 DRAM CONFIGURATION

  692 13:58:11.262992  =================================== 

  693 13:58:11.263077  EX_ROW_EN[0]    = 0x10

  694 13:58:11.266591  EX_ROW_EN[1]    = 0x0

  695 13:58:11.266692  LP4Y_EN      = 0x0

  696 13:58:11.270228  WORK_FSP     = 0x0

  697 13:58:11.270312  WL           = 0x2

  698 13:58:11.273873  RL           = 0x2

  699 13:58:11.273958  BL           = 0x2

  700 13:58:11.277260  RPST         = 0x0

  701 13:58:11.277344  RD_PRE       = 0x0

  702 13:58:11.280752  WR_PRE       = 0x1

  703 13:58:11.280925  WR_PST       = 0x0

  704 13:58:11.284501  DBI_WR       = 0x0

  705 13:58:11.284585  DBI_RD       = 0x0

  706 13:58:11.288380  OTF          = 0x1

  707 13:58:11.288463  =================================== 

  708 13:58:11.295009  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  709 13:58:11.300219  nWR fixed to 40

  710 13:58:11.303546  [ModeRegInit_LP4] CH0 RK0

  711 13:58:11.303630  [ModeRegInit_LP4] CH0 RK1

  712 13:58:11.307310  [ModeRegInit_LP4] CH1 RK0

  713 13:58:11.307400  [ModeRegInit_LP4] CH1 RK1

  714 13:58:11.311255  match AC timing 13

  715 13:58:11.314984  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  716 13:58:11.318228  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  717 13:58:11.325373  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  718 13:58:11.329250  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  719 13:58:11.332499  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  720 13:58:11.336456  [EMI DOE] emi_dcm 0

  721 13:58:11.340556  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  722 13:58:11.340665  ==

  723 13:58:11.344064  Dram Type= 6, Freq= 0, CH_0, rank 0

  724 13:58:11.347431  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  725 13:58:11.347530  ==

  726 13:58:11.351513  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  727 13:58:11.358814  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  728 13:58:11.367826  [CA 0] Center 38 (7~69) winsize 63

  729 13:58:11.371517  [CA 1] Center 37 (7~68) winsize 62

  730 13:58:11.375159  [CA 2] Center 35 (5~66) winsize 62

  731 13:58:11.379131  [CA 3] Center 35 (5~66) winsize 62

  732 13:58:11.382651  [CA 4] Center 34 (4~65) winsize 62

  733 13:58:11.382735  [CA 5] Center 34 (4~65) winsize 62

  734 13:58:11.382802  

  735 13:58:11.386362  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  736 13:58:11.390042  

  737 13:58:11.390228  [CATrainingPosCal] consider 1 rank data

  738 13:58:11.393672  u2DelayCellTimex100 = 270/100 ps

  739 13:58:11.397595  CA0 delay=38 (7~69),Diff = 4 PI (28 cell)

  740 13:58:11.401438  CA1 delay=37 (7~68),Diff = 3 PI (21 cell)

  741 13:58:11.405282  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

  742 13:58:11.408399  CA3 delay=35 (5~66),Diff = 1 PI (7 cell)

  743 13:58:11.412256  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

  744 13:58:11.416361  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

  745 13:58:11.416445  

  746 13:58:11.419598  CA PerBit enable=1, Macro0, CA PI delay=34

  747 13:58:11.419681  

  748 13:58:11.423174  [CBTSetCACLKResult] CA Dly = 34

  749 13:58:11.423273  CS Dly: 6 (0~37)

  750 13:58:11.426911  ==

  751 13:58:11.427034  Dram Type= 6, Freq= 0, CH_0, rank 1

  752 13:58:11.434733  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  753 13:58:11.434819  ==

  754 13:58:11.438247  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  755 13:58:11.444838  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  756 13:58:11.453512  [CA 0] Center 38 (7~69) winsize 63

  757 13:58:11.457129  [CA 1] Center 37 (7~68) winsize 62

  758 13:58:11.460790  [CA 2] Center 35 (5~66) winsize 62

  759 13:58:11.464090  [CA 3] Center 35 (5~66) winsize 62

  760 13:58:11.467638  [CA 4] Center 34 (4~65) winsize 62

  761 13:58:11.470157  [CA 5] Center 34 (4~65) winsize 62

  762 13:58:11.470269  

  763 13:58:11.473886  [CmdBusTrainingLP45] Vref(ca) range 1: 30

  764 13:58:11.474010  

  765 13:58:11.477420  [CATrainingPosCal] consider 2 rank data

  766 13:58:11.480581  u2DelayCellTimex100 = 270/100 ps

  767 13:58:11.483576  CA0 delay=38 (7~69),Diff = 4 PI (28 cell)

  768 13:58:11.487129  CA1 delay=37 (7~68),Diff = 3 PI (21 cell)

  769 13:58:11.490513  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

  770 13:58:11.496972  CA3 delay=35 (5~66),Diff = 1 PI (7 cell)

  771 13:58:11.500580  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

  772 13:58:11.503964  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

  773 13:58:11.504265  

  774 13:58:11.506943  CA PerBit enable=1, Macro0, CA PI delay=34

  775 13:58:11.507247  

  776 13:58:11.510337  [CBTSetCACLKResult] CA Dly = 34

  777 13:58:11.510641  CS Dly: 6 (0~37)

  778 13:58:11.510884  

  779 13:58:11.514089  ----->DramcWriteLeveling(PI) begin...

  780 13:58:11.514416  ==

  781 13:58:11.517180  Dram Type= 6, Freq= 0, CH_0, rank 0

  782 13:58:11.523807  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  783 13:58:11.524121  ==

  784 13:58:11.526952  Write leveling (Byte 0): 33 => 33

  785 13:58:11.530641  Write leveling (Byte 1): 29 => 29

  786 13:58:11.531063  DramcWriteLeveling(PI) end<-----

  787 13:58:11.531334  

  788 13:58:11.533780  ==

  789 13:58:11.537204  Dram Type= 6, Freq= 0, CH_0, rank 0

  790 13:58:11.540536  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  791 13:58:11.540844  ==

  792 13:58:11.544087  [Gating] SW mode calibration

  793 13:58:11.550466  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  794 13:58:11.553762  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  795 13:58:11.560154   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  796 13:58:11.563630   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  797 13:58:11.566943   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

  798 13:58:11.574073   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  799 13:58:11.577100   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  800 13:58:11.580248   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  801 13:58:11.586969   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  802 13:58:11.591193   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  803 13:58:11.593892   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  804 13:58:11.597958   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  805 13:58:11.601331   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  806 13:58:11.608770   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  807 13:58:11.611554   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  808 13:58:11.615016   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  809 13:58:11.622548   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  810 13:58:11.626048   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  811 13:58:11.629537   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  812 13:58:11.632544   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  813 13:58:11.639149   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  814 13:58:11.643006   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  815 13:58:11.645926   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  816 13:58:11.652576   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  817 13:58:11.656096   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  818 13:58:11.659176   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  819 13:58:11.666511   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  820 13:58:11.669360   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  821 13:58:11.672743   0  9  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  822 13:58:11.676573   0  9 12 | B1->B0 | 2828 3131 | 0 1 | (0 0) (1 1)

  823 13:58:11.682745   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  824 13:58:11.686538   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  825 13:58:11.689684   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  826 13:58:11.696265   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  827 13:58:11.699459   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  828 13:58:11.702859   0 10  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

  829 13:58:11.709470   0 10  8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)

  830 13:58:11.713051   0 10 12 | B1->B0 | 2f2f 2929 | 0 0 | (1 1) (1 1)

  831 13:58:11.716154   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  832 13:58:11.723087   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  833 13:58:11.726633   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  834 13:58:11.729764   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  835 13:58:11.736322   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  836 13:58:11.739783   0 11  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  837 13:58:11.743088   0 11  8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)

  838 13:58:11.749521   0 11 12 | B1->B0 | 3636 4141 | 1 0 | (0 0) (0 0)

  839 13:58:11.753100   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  840 13:58:11.756788   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  841 13:58:11.759905   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  842 13:58:11.766881   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  843 13:58:11.770383   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  844 13:58:11.773345   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  845 13:58:11.780336   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

  846 13:58:11.783326   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  847 13:58:11.787015   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  848 13:58:11.793223   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  849 13:58:11.796632   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  850 13:58:11.799940   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  851 13:58:11.806940   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  852 13:58:11.810170   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  853 13:58:11.813149   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  854 13:58:11.820243   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  855 13:58:11.823177   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  856 13:58:11.826640   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  857 13:58:11.833405   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  858 13:58:11.836885   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  859 13:58:11.839850   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  860 13:58:11.846880   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  861 13:58:11.850245   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  862 13:58:11.853592   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  863 13:58:11.857053  Total UI for P1: 0, mck2ui 16

  864 13:58:11.860105  best dqsien dly found for B0: ( 0, 14,  8)

  865 13:58:11.863438   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  866 13:58:11.870421   0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  867 13:58:11.873559  Total UI for P1: 0, mck2ui 16

  868 13:58:11.877030  best dqsien dly found for B1: ( 0, 14, 14)

  869 13:58:11.880072  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

  870 13:58:11.883102  best DQS1 dly(MCK, UI, PI) = (0, 14, 14)

  871 13:58:11.883572  

  872 13:58:11.886580  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

  873 13:58:11.890232  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 14)

  874 13:58:11.893781  [Gating] SW calibration Done

  875 13:58:11.894207  ==

  876 13:58:11.896704  Dram Type= 6, Freq= 0, CH_0, rank 0

  877 13:58:11.899847  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  878 13:58:11.900326  ==

  879 13:58:11.903072  RX Vref Scan: 0

  880 13:58:11.903545  

  881 13:58:11.903892  RX Vref 0 -> 0, step: 1

  882 13:58:11.906843  

  883 13:58:11.907270  RX Delay -130 -> 252, step: 16

  884 13:58:11.913556  iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256

  885 13:58:11.917279  iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256

  886 13:58:11.920137  iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256

  887 13:58:11.923784  iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256

  888 13:58:11.926651  iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256

  889 13:58:11.933235  iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256

  890 13:58:11.936570  iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240

  891 13:58:11.940326  iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256

  892 13:58:11.943541  iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256

  893 13:58:11.946563  iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256

  894 13:58:11.949719  iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240

  895 13:58:11.956543  iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256

  896 13:58:11.959850  iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256

  897 13:58:11.963548  iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256

  898 13:58:11.966407  iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256

  899 13:58:11.973559  iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256

  900 13:58:11.974102  ==

  901 13:58:11.977249  Dram Type= 6, Freq= 0, CH_0, rank 0

  902 13:58:11.980057  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  903 13:58:11.980498  ==

  904 13:58:11.980843  DQS Delay:

  905 13:58:11.983334  DQS0 = 0, DQS1 = 0

  906 13:58:11.983805  DQM Delay:

  907 13:58:11.986917  DQM0 = 78, DQM1 = 70

  908 13:58:11.987351  DQ Delay:

  909 13:58:11.990311  DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77

  910 13:58:11.993061  DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93

  911 13:58:11.996891  DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61

  912 13:58:12.000603  DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77

  913 13:58:12.001153  

  914 13:58:12.001498  

  915 13:58:12.001963  ==

  916 13:58:12.003681  Dram Type= 6, Freq= 0, CH_0, rank 0

  917 13:58:12.007226  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  918 13:58:12.007742  ==

  919 13:58:12.008090  

  920 13:58:12.008405  

  921 13:58:12.010324  	TX Vref Scan disable

  922 13:58:12.013733   == TX Byte 0 ==

  923 13:58:12.017617  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

  924 13:58:12.021058  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

  925 13:58:12.023831   == TX Byte 1 ==

  926 13:58:12.027122  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

  927 13:58:12.030426  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

  928 13:58:12.030853  ==

  929 13:58:12.033972  Dram Type= 6, Freq= 0, CH_0, rank 0

  930 13:58:12.037197  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  931 13:58:12.037627  ==

  932 13:58:12.051854  TX Vref=22, minBit 5, minWin=26, winSum=429

  933 13:58:12.055522  TX Vref=24, minBit 5, minWin=27, winSum=440

  934 13:58:12.058222  TX Vref=26, minBit 5, minWin=27, winSum=443

  935 13:58:12.062254  TX Vref=28, minBit 4, minWin=27, winSum=443

  936 13:58:12.065234  TX Vref=30, minBit 1, minWin=27, winSum=442

  937 13:58:12.068545  TX Vref=32, minBit 1, minWin=27, winSum=441

  938 13:58:12.075668  [TxChooseVref] Worse bit 5, Min win 27, Win sum 443, Final Vref 26

  939 13:58:12.076250  

  940 13:58:12.078970  Final TX Range 1 Vref 26

  941 13:58:12.079598  

  942 13:58:12.079979  ==

  943 13:58:12.082660  Dram Type= 6, Freq= 0, CH_0, rank 0

  944 13:58:12.085344  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  945 13:58:12.085827  ==

  946 13:58:12.086211  

  947 13:58:12.086566  

  948 13:58:12.088783  	TX Vref Scan disable

  949 13:58:12.092297   == TX Byte 0 ==

  950 13:58:12.095133  Update DQ  dly =583 (2 ,1, 39)  DQ  OEN =(1 ,6)

  951 13:58:12.098530  Update DQM dly =583 (2 ,1, 39)  DQM OEN =(1 ,6)

  952 13:58:12.101845   == TX Byte 1 ==

  953 13:58:12.105189  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

  954 13:58:12.108628  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

  955 13:58:12.109057  

  956 13:58:12.112104  [DATLAT]

  957 13:58:12.112712  Freq=800, CH0 RK0

  958 13:58:12.113071  

  959 13:58:12.115231  DATLAT Default: 0xa

  960 13:58:12.115704  0, 0xFFFF, sum = 0

  961 13:58:12.118394  1, 0xFFFF, sum = 0

  962 13:58:12.118848  2, 0xFFFF, sum = 0

  963 13:58:12.122051  3, 0xFFFF, sum = 0

  964 13:58:12.122587  4, 0xFFFF, sum = 0

  965 13:58:12.125835  5, 0xFFFF, sum = 0

  966 13:58:12.126371  6, 0xFFFF, sum = 0

  967 13:58:12.128625  7, 0xFFFF, sum = 0

  968 13:58:12.129158  8, 0xFFFF, sum = 0

  969 13:58:12.132124  9, 0x0, sum = 1

  970 13:58:12.132561  10, 0x0, sum = 2

  971 13:58:12.135201  11, 0x0, sum = 3

  972 13:58:12.135829  12, 0x0, sum = 4

  973 13:58:12.138578  best_step = 10

  974 13:58:12.139049  

  975 13:58:12.139434  ==

  976 13:58:12.141926  Dram Type= 6, Freq= 0, CH_0, rank 0

  977 13:58:12.145492  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  978 13:58:12.146021  ==

  979 13:58:12.148457  RX Vref Scan: 1

  980 13:58:12.148919  

  981 13:58:12.149309  Set Vref Range= 32 -> 127

  982 13:58:12.149634  

  983 13:58:12.151573  RX Vref 32 -> 127, step: 1

  984 13:58:12.152002  

  985 13:58:12.155354  RX Delay -111 -> 252, step: 8

  986 13:58:12.155821  

  987 13:58:12.158351  Set Vref, RX VrefLevel [Byte0]: 32

  988 13:58:12.161874                           [Byte1]: 32

  989 13:58:12.162401  

  990 13:58:12.165407  Set Vref, RX VrefLevel [Byte0]: 33

  991 13:58:12.168726                           [Byte1]: 33

  992 13:58:12.171825  

  993 13:58:12.175522  Set Vref, RX VrefLevel [Byte0]: 34

  994 13:58:12.178490                           [Byte1]: 34

  995 13:58:12.178926  

  996 13:58:12.182631  Set Vref, RX VrefLevel [Byte0]: 35

  997 13:58:12.185458                           [Byte1]: 35

  998 13:58:12.185885  

  999 13:58:12.189165  Set Vref, RX VrefLevel [Byte0]: 36

 1000 13:58:12.192089                           [Byte1]: 36

 1001 13:58:12.192516  

 1002 13:58:12.195575  Set Vref, RX VrefLevel [Byte0]: 37

 1003 13:58:12.199126                           [Byte1]: 37

 1004 13:58:12.203055  

 1005 13:58:12.203659  Set Vref, RX VrefLevel [Byte0]: 38

 1006 13:58:12.206405                           [Byte1]: 38

 1007 13:58:12.210567  

 1008 13:58:12.211096  Set Vref, RX VrefLevel [Byte0]: 39

 1009 13:58:12.214287                           [Byte1]: 39

 1010 13:58:12.218476  

 1011 13:58:12.218999  Set Vref, RX VrefLevel [Byte0]: 40

 1012 13:58:12.221548                           [Byte1]: 40

 1013 13:58:12.225588  

 1014 13:58:12.226011  Set Vref, RX VrefLevel [Byte0]: 41

 1015 13:58:12.229090                           [Byte1]: 41

 1016 13:58:12.233812  

 1017 13:58:12.234339  Set Vref, RX VrefLevel [Byte0]: 42

 1018 13:58:12.236725                           [Byte1]: 42

 1019 13:58:12.241252  

 1020 13:58:12.241779  Set Vref, RX VrefLevel [Byte0]: 43

 1021 13:58:12.243986                           [Byte1]: 43

 1022 13:58:12.248870  

 1023 13:58:12.249447  Set Vref, RX VrefLevel [Byte0]: 44

 1024 13:58:12.252045                           [Byte1]: 44

 1025 13:58:12.256852  

 1026 13:58:12.257380  Set Vref, RX VrefLevel [Byte0]: 45

 1027 13:58:12.259637                           [Byte1]: 45

 1028 13:58:12.264641  

 1029 13:58:12.265163  Set Vref, RX VrefLevel [Byte0]: 46

 1030 13:58:12.267941                           [Byte1]: 46

 1031 13:58:12.271989  

 1032 13:58:12.272512  Set Vref, RX VrefLevel [Byte0]: 47

 1033 13:58:12.275074                           [Byte1]: 47

 1034 13:58:12.279707  

 1035 13:58:12.280185  Set Vref, RX VrefLevel [Byte0]: 48

 1036 13:58:12.283022                           [Byte1]: 48

 1037 13:58:12.286986  

 1038 13:58:12.287506  Set Vref, RX VrefLevel [Byte0]: 49

 1039 13:58:12.290310                           [Byte1]: 49

 1040 13:58:12.294942  

 1041 13:58:12.295368  Set Vref, RX VrefLevel [Byte0]: 50

 1042 13:58:12.297921                           [Byte1]: 50

 1043 13:58:12.302322  

 1044 13:58:12.302853  Set Vref, RX VrefLevel [Byte0]: 51

 1045 13:58:12.305280                           [Byte1]: 51

 1046 13:58:12.309855  

 1047 13:58:12.310424  Set Vref, RX VrefLevel [Byte0]: 52

 1048 13:58:12.313224                           [Byte1]: 52

 1049 13:58:12.317256  

 1050 13:58:12.317723  Set Vref, RX VrefLevel [Byte0]: 53

 1051 13:58:12.321248                           [Byte1]: 53

 1052 13:58:12.325222  

 1053 13:58:12.325803  Set Vref, RX VrefLevel [Byte0]: 54

 1054 13:58:12.328442                           [Byte1]: 54

 1055 13:58:12.332774  

 1056 13:58:12.333343  Set Vref, RX VrefLevel [Byte0]: 55

 1057 13:58:12.336217                           [Byte1]: 55

 1058 13:58:12.340360  

 1059 13:58:12.341068  Set Vref, RX VrefLevel [Byte0]: 56

 1060 13:58:12.343713                           [Byte1]: 56

 1061 13:58:12.348086  

 1062 13:58:12.348831  Set Vref, RX VrefLevel [Byte0]: 57

 1063 13:58:12.351253                           [Byte1]: 57

 1064 13:58:12.355939  

 1065 13:58:12.356404  Set Vref, RX VrefLevel [Byte0]: 58

 1066 13:58:12.358777                           [Byte1]: 58

 1067 13:58:12.363444  

 1068 13:58:12.363870  Set Vref, RX VrefLevel [Byte0]: 59

 1069 13:58:12.366716                           [Byte1]: 59

 1070 13:58:12.371302  

 1071 13:58:12.371891  Set Vref, RX VrefLevel [Byte0]: 60

 1072 13:58:12.374317                           [Byte1]: 60

 1073 13:58:12.378945  

 1074 13:58:12.379523  Set Vref, RX VrefLevel [Byte0]: 61

 1075 13:58:12.382052                           [Byte1]: 61

 1076 13:58:12.385980  

 1077 13:58:12.386406  Set Vref, RX VrefLevel [Byte0]: 62

 1078 13:58:12.390211                           [Byte1]: 62

 1079 13:58:12.393654  

 1080 13:58:12.394080  Set Vref, RX VrefLevel [Byte0]: 63

 1081 13:58:12.397661                           [Byte1]: 63

 1082 13:58:12.401987  

 1083 13:58:12.402513  Set Vref, RX VrefLevel [Byte0]: 64

 1084 13:58:12.404605                           [Byte1]: 64

 1085 13:58:12.408884  

 1086 13:58:12.409277  Set Vref, RX VrefLevel [Byte0]: 65

 1087 13:58:12.412828                           [Byte1]: 65

 1088 13:58:12.416832  

 1089 13:58:12.417375  Set Vref, RX VrefLevel [Byte0]: 66

 1090 13:58:12.420497                           [Byte1]: 66

 1091 13:58:12.424418  

 1092 13:58:12.424987  Set Vref, RX VrefLevel [Byte0]: 67

 1093 13:58:12.428015                           [Byte1]: 67

 1094 13:58:12.432556  

 1095 13:58:12.433126  Set Vref, RX VrefLevel [Byte0]: 68

 1096 13:58:12.435567                           [Byte1]: 68

 1097 13:58:12.440161  

 1098 13:58:12.440720  Set Vref, RX VrefLevel [Byte0]: 69

 1099 13:58:12.443170                           [Byte1]: 69

 1100 13:58:12.447757  

 1101 13:58:12.448321  Set Vref, RX VrefLevel [Byte0]: 70

 1102 13:58:12.450745                           [Byte1]: 70

 1103 13:58:12.455556  

 1104 13:58:12.456105  Set Vref, RX VrefLevel [Byte0]: 71

 1105 13:58:12.458328                           [Byte1]: 71

 1106 13:58:12.462446  

 1107 13:58:12.462919  Set Vref, RX VrefLevel [Byte0]: 72

 1108 13:58:12.466387                           [Byte1]: 72

 1109 13:58:12.470753  

 1110 13:58:12.471324  Set Vref, RX VrefLevel [Byte0]: 73

 1111 13:58:12.473873                           [Byte1]: 73

 1112 13:58:12.477946  

 1113 13:58:12.478515  Set Vref, RX VrefLevel [Byte0]: 74

 1114 13:58:12.481431                           [Byte1]: 74

 1115 13:58:12.486117  

 1116 13:58:12.486691  Set Vref, RX VrefLevel [Byte0]: 75

 1117 13:58:12.488894                           [Byte1]: 75

 1118 13:58:12.493342  

 1119 13:58:12.493803  Set Vref, RX VrefLevel [Byte0]: 76

 1120 13:58:12.496735                           [Byte1]: 76

 1121 13:58:12.500917  

 1122 13:58:12.501595  Set Vref, RX VrefLevel [Byte0]: 77

 1123 13:58:12.503925                           [Byte1]: 77

 1124 13:58:12.509011  

 1125 13:58:12.509796  Set Vref, RX VrefLevel [Byte0]: 78

 1126 13:58:12.511852                           [Byte1]: 78

 1127 13:58:12.516622  

 1128 13:58:12.517195  Set Vref, RX VrefLevel [Byte0]: 79

 1129 13:58:12.519718                           [Byte1]: 79

 1130 13:58:12.524351  

 1131 13:58:12.524909  Final RX Vref Byte 0 = 61 to rank0

 1132 13:58:12.527316  Final RX Vref Byte 1 = 55 to rank0

 1133 13:58:12.530852  Final RX Vref Byte 0 = 61 to rank1

 1134 13:58:12.533751  Final RX Vref Byte 1 = 55 to rank1==

 1135 13:58:12.537412  Dram Type= 6, Freq= 0, CH_0, rank 0

 1136 13:58:12.544323  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1137 13:58:12.544905  ==

 1138 13:58:12.545280  DQS Delay:

 1139 13:58:12.545628  DQS0 = 0, DQS1 = 0

 1140 13:58:12.547342  DQM Delay:

 1141 13:58:12.547938  DQM0 = 81, DQM1 = 67

 1142 13:58:12.550575  DQ Delay:

 1143 13:58:12.554096  DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80

 1144 13:58:12.554671  DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92

 1145 13:58:12.557233  DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60

 1146 13:58:12.560790  DQ12 =72, DQ13 =68, DQ14 =80, DQ15 =76

 1147 13:58:12.563977  

 1148 13:58:12.564548  

 1149 13:58:12.570842  [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps

 1150 13:58:12.574481  CH0 RK0: MR19=606, MR18=2424

 1151 13:58:12.580626  CH0_RK0: MR19=0x606, MR18=0x2424, DQSOSC=400, MR23=63, INC=92, DEC=61

 1152 13:58:12.581176  

 1153 13:58:12.584228  ----->DramcWriteLeveling(PI) begin...

 1154 13:58:12.584720  ==

 1155 13:58:12.587043  Dram Type= 6, Freq= 0, CH_0, rank 1

 1156 13:58:12.591105  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1157 13:58:12.591741  ==

 1158 13:58:12.593979  Write leveling (Byte 0): 33 => 33

 1159 13:58:12.597253  Write leveling (Byte 1): 33 => 33

 1160 13:58:12.600646  DramcWriteLeveling(PI) end<-----

 1161 13:58:12.601205  

 1162 13:58:12.601571  ==

 1163 13:58:12.604037  Dram Type= 6, Freq= 0, CH_0, rank 1

 1164 13:58:12.607608  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1165 13:58:12.608166  ==

 1166 13:58:12.610930  [Gating] SW mode calibration

 1167 13:58:12.617467  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1168 13:58:12.624123  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1169 13:58:12.627653   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1170 13:58:12.630456   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1171 13:58:12.637089   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1172 13:58:12.640547   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1173 13:58:12.643954   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1174 13:58:12.650587   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1175 13:58:12.653715   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1176 13:58:12.657573   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1177 13:58:12.663950   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1178 13:58:12.667516   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1179 13:58:12.670757   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1180 13:58:12.674009   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1181 13:58:12.721299   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1182 13:58:12.721874   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1183 13:58:12.722245   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1184 13:58:12.722944   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1185 13:58:12.723309   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1186 13:58:12.723697   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1187 13:58:12.724026   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1188 13:58:12.724342   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1189 13:58:12.724654   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1190 13:58:12.725030   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1191 13:58:12.765237   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1192 13:58:12.765981   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1193 13:58:12.766407   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1194 13:58:12.766855   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1195 13:58:12.767575   0  9  8 | B1->B0 | 2323 2e2e | 0 0 | (1 1) (0 0)

 1196 13:58:12.767952   0  9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 1197 13:58:12.768291   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1198 13:58:12.768621   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1199 13:58:12.768941   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1200 13:58:12.769431   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1201 13:58:12.769836   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1202 13:58:12.772692   0 10  4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)

 1203 13:58:12.776632   0 10  8 | B1->B0 | 3030 2525 | 0 0 | (0 1) (1 0)

 1204 13:58:12.779419   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1205 13:58:12.786493   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1206 13:58:12.789537   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1207 13:58:12.793163   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1208 13:58:12.799863   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1209 13:58:12.803155   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1210 13:58:12.806348   0 11  4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)

 1211 13:58:12.813226   0 11  8 | B1->B0 | 3333 3a3a | 0 0 | (1 1) (1 1)

 1212 13:58:12.816630   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1213 13:58:12.819989   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1214 13:58:12.826358   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1215 13:58:12.829285   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1216 13:58:12.833073   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1217 13:58:12.836802   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1218 13:58:12.844267   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1219 13:58:12.848196   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1220 13:58:12.851546   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1221 13:58:12.854857   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1222 13:58:12.862229   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1223 13:58:12.865574   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1224 13:58:12.868553   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1225 13:58:12.872261   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1226 13:58:12.878692   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1227 13:58:12.881991   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1228 13:58:12.885260   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1229 13:58:12.891909   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1230 13:58:12.895207   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1231 13:58:12.898765   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1232 13:58:12.905491   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1233 13:58:12.908697   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1234 13:58:12.912452   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1235 13:58:12.918633   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1236 13:58:12.919198  Total UI for P1: 0, mck2ui 16

 1237 13:58:12.922509  best dqsien dly found for B0: ( 0, 14,  6)

 1238 13:58:12.928763   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1239 13:58:12.932389  Total UI for P1: 0, mck2ui 16

 1240 13:58:12.935251  best dqsien dly found for B1: ( 0, 14,  8)

 1241 13:58:12.939042  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

 1242 13:58:12.942437  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1243 13:58:12.943001  

 1244 13:58:12.945198  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1245 13:58:12.948932  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1246 13:58:12.952160  [Gating] SW calibration Done

 1247 13:58:12.952626  ==

 1248 13:58:12.955341  Dram Type= 6, Freq= 0, CH_0, rank 1

 1249 13:58:12.959119  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1250 13:58:12.959739  ==

 1251 13:58:12.961800  RX Vref Scan: 0

 1252 13:58:12.962260  

 1253 13:58:12.962628  RX Vref 0 -> 0, step: 1

 1254 13:58:12.965271  

 1255 13:58:12.965732  RX Delay -130 -> 252, step: 16

 1256 13:58:12.972062  iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256

 1257 13:58:12.975329  iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256

 1258 13:58:12.979026  iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240

 1259 13:58:12.982184  iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256

 1260 13:58:12.985283  iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256

 1261 13:58:12.992291  iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240

 1262 13:58:12.995528  iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256

 1263 13:58:12.998716  iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256

 1264 13:58:13.001937  iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256

 1265 13:58:13.005426  iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240

 1266 13:58:13.012349  iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240

 1267 13:58:13.015136  iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256

 1268 13:58:13.018775  iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256

 1269 13:58:13.022378  iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256

 1270 13:58:13.025738  iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256

 1271 13:58:13.031941  iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256

 1272 13:58:13.032406  ==

 1273 13:58:13.035306  Dram Type= 6, Freq= 0, CH_0, rank 1

 1274 13:58:13.038935  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1275 13:58:13.039552  ==

 1276 13:58:13.039928  DQS Delay:

 1277 13:58:13.042317  DQS0 = 0, DQS1 = 0

 1278 13:58:13.042882  DQM Delay:

 1279 13:58:13.045284  DQM0 = 79, DQM1 = 69

 1280 13:58:13.045749  DQ Delay:

 1281 13:58:13.049270  DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77

 1282 13:58:13.051872  DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93

 1283 13:58:13.055511  DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61

 1284 13:58:13.059118  DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77

 1285 13:58:13.059809  

 1286 13:58:13.060183  

 1287 13:58:13.060528  ==

 1288 13:58:13.062051  Dram Type= 6, Freq= 0, CH_0, rank 1

 1289 13:58:13.065559  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1290 13:58:13.066131  ==

 1291 13:58:13.066504  

 1292 13:58:13.066840  

 1293 13:58:13.068530  	TX Vref Scan disable

 1294 13:58:13.072171   == TX Byte 0 ==

 1295 13:58:13.076073  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

 1296 13:58:13.078753  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

 1297 13:58:13.082466   == TX Byte 1 ==

 1298 13:58:13.086030  Update DQ  dly =583 (2 ,1, 39)  DQ  OEN =(1 ,6)

 1299 13:58:13.089059  Update DQM dly =583 (2 ,1, 39)  DQM OEN =(1 ,6)

 1300 13:58:13.089524  ==

 1301 13:58:13.092438  Dram Type= 6, Freq= 0, CH_0, rank 1

 1302 13:58:13.095260  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1303 13:58:13.098772  ==

 1304 13:58:13.110397  TX Vref=22, minBit 1, minWin=27, winSum=440

 1305 13:58:13.113776  TX Vref=24, minBit 1, minWin=27, winSum=443

 1306 13:58:13.116704  TX Vref=26, minBit 1, minWin=27, winSum=444

 1307 13:58:13.119611  TX Vref=28, minBit 1, minWin=27, winSum=442

 1308 13:58:13.123050  TX Vref=30, minBit 1, minWin=27, winSum=442

 1309 13:58:13.126252  TX Vref=32, minBit 4, minWin=27, winSum=446

 1310 13:58:13.133082  [TxChooseVref] Worse bit 4, Min win 27, Win sum 446, Final Vref 32

 1311 13:58:13.133547  

 1312 13:58:13.136724  Final TX Range 1 Vref 32

 1313 13:58:13.137188  

 1314 13:58:13.137549  ==

 1315 13:58:13.139757  Dram Type= 6, Freq= 0, CH_0, rank 1

 1316 13:58:13.143329  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1317 13:58:13.143836  ==

 1318 13:58:13.144202  

 1319 13:58:13.146246  

 1320 13:58:13.146695  	TX Vref Scan disable

 1321 13:58:13.149909   == TX Byte 0 ==

 1322 13:58:13.153229  Update DQ  dly =583 (2 ,1, 39)  DQ  OEN =(1 ,6)

 1323 13:58:13.159617  Update DQM dly =583 (2 ,1, 39)  DQM OEN =(1 ,6)

 1324 13:58:13.160042   == TX Byte 1 ==

 1325 13:58:13.163115  Update DQ  dly =583 (2 ,1, 39)  DQ  OEN =(1 ,6)

 1326 13:58:13.166838  Update DQM dly =583 (2 ,1, 39)  DQM OEN =(1 ,6)

 1327 13:58:13.170086  

 1328 13:58:13.170418  [DATLAT]

 1329 13:58:13.170673  Freq=800, CH0 RK1

 1330 13:58:13.170911  

 1331 13:58:13.173528  DATLAT Default: 0xa

 1332 13:58:13.173949  0, 0xFFFF, sum = 0

 1333 13:58:13.176270  1, 0xFFFF, sum = 0

 1334 13:58:13.176597  2, 0xFFFF, sum = 0

 1335 13:58:13.180045  3, 0xFFFF, sum = 0

 1336 13:58:13.180488  4, 0xFFFF, sum = 0

 1337 13:58:13.182840  5, 0xFFFF, sum = 0

 1338 13:58:13.183167  6, 0xFFFF, sum = 0

 1339 13:58:13.186050  7, 0xFFFF, sum = 0

 1340 13:58:13.190199  8, 0xFFFF, sum = 0

 1341 13:58:13.190631  9, 0x0, sum = 1

 1342 13:58:13.190900  10, 0x0, sum = 2

 1343 13:58:13.193145  11, 0x0, sum = 3

 1344 13:58:13.193473  12, 0x0, sum = 4

 1345 13:58:13.196256  best_step = 10

 1346 13:58:13.196686  

 1347 13:58:13.196950  ==

 1348 13:58:13.199649  Dram Type= 6, Freq= 0, CH_0, rank 1

 1349 13:58:13.203333  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1350 13:58:13.203796  ==

 1351 13:58:13.207044  RX Vref Scan: 0

 1352 13:58:13.207503  

 1353 13:58:13.207777  RX Vref 0 -> 0, step: 1

 1354 13:58:13.208019  

 1355 13:58:13.209702  RX Delay -111 -> 252, step: 8

 1356 13:58:13.216917  iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232

 1357 13:58:13.219838  iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232

 1358 13:58:13.223453  iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232

 1359 13:58:13.226541  iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240

 1360 13:58:13.229874  iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232

 1361 13:58:13.236610  iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240

 1362 13:58:13.240388  iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240

 1363 13:58:13.243147  iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232

 1364 13:58:13.246416  iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232

 1365 13:58:13.249794  iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232

 1366 13:58:13.256304  iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240

 1367 13:58:13.259961  iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232

 1368 13:58:13.263263  iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240

 1369 13:58:13.266778  iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232

 1370 13:58:13.269743  iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240

 1371 13:58:13.276942  iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232

 1372 13:58:13.277485  ==

 1373 13:58:13.280067  Dram Type= 6, Freq= 0, CH_0, rank 1

 1374 13:58:13.283026  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1375 13:58:13.283557  ==

 1376 13:58:13.283931  DQS Delay:

 1377 13:58:13.286444  DQS0 = 0, DQS1 = 0

 1378 13:58:13.286900  DQM Delay:

 1379 13:58:13.290018  DQM0 = 78, DQM1 = 69

 1380 13:58:13.290571  DQ Delay:

 1381 13:58:13.293088  DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72

 1382 13:58:13.296657  DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92

 1383 13:58:13.300203  DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60

 1384 13:58:13.303067  DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76

 1385 13:58:13.303663  

 1386 13:58:13.304025  

 1387 13:58:13.309576  [DQSOSCAuto] RK1, (LSB)MR18= 0x4924, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps

 1388 13:58:13.313400  CH0 RK1: MR19=606, MR18=4924

 1389 13:58:13.320163  CH0_RK1: MR19=0x606, MR18=0x4924, DQSOSC=391, MR23=63, INC=96, DEC=64

 1390 13:58:13.323349  [RxdqsGatingPostProcess] freq 800

 1391 13:58:13.330059  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1392 13:58:13.333217  Pre-setting of DQS Precalculation

 1393 13:58:13.337069  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1394 13:58:13.337629  ==

 1395 13:58:13.340219  Dram Type= 6, Freq= 0, CH_1, rank 0

 1396 13:58:13.343707  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1397 13:58:13.344175  ==

 1398 13:58:13.350233  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1399 13:58:13.356373  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1400 13:58:13.364860  [CA 0] Center 36 (6~66) winsize 61

 1401 13:58:13.368080  [CA 1] Center 36 (6~67) winsize 62

 1402 13:58:13.371342  [CA 2] Center 34 (5~64) winsize 60

 1403 13:58:13.374821  [CA 3] Center 34 (4~64) winsize 61

 1404 13:58:13.377957  [CA 4] Center 34 (4~64) winsize 61

 1405 13:58:13.381462  [CA 5] Center 33 (3~64) winsize 62

 1406 13:58:13.381928  

 1407 13:58:13.384476  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1408 13:58:13.384940  

 1409 13:58:13.388035  [CATrainingPosCal] consider 1 rank data

 1410 13:58:13.391515  u2DelayCellTimex100 = 270/100 ps

 1411 13:58:13.395097  CA0 delay=36 (6~66),Diff = 3 PI (21 cell)

 1412 13:58:13.397852  CA1 delay=36 (6~67),Diff = 3 PI (21 cell)

 1413 13:58:13.405238  CA2 delay=34 (5~64),Diff = 1 PI (7 cell)

 1414 13:58:13.408523  CA3 delay=34 (4~64),Diff = 1 PI (7 cell)

 1415 13:58:13.411644  CA4 delay=34 (4~64),Diff = 1 PI (7 cell)

 1416 13:58:13.415237  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1417 13:58:13.415860  

 1418 13:58:13.418163  CA PerBit enable=1, Macro0, CA PI delay=33

 1419 13:58:13.418635  

 1420 13:58:13.422064  [CBTSetCACLKResult] CA Dly = 33

 1421 13:58:13.422640  CS Dly: 5 (0~36)

 1422 13:58:13.423013  ==

 1423 13:58:13.424536  Dram Type= 6, Freq= 0, CH_1, rank 1

 1424 13:58:13.431471  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1425 13:58:13.432048  ==

 1426 13:58:13.434601  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1427 13:58:13.441827  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1428 13:58:13.451623  [CA 0] Center 36 (6~66) winsize 61

 1429 13:58:13.454573  [CA 1] Center 36 (6~67) winsize 62

 1430 13:58:13.458138  [CA 2] Center 34 (4~65) winsize 62

 1431 13:58:13.461147  [CA 3] Center 33 (3~64) winsize 62

 1432 13:58:13.464018  [CA 4] Center 34 (4~64) winsize 61

 1433 13:58:13.467758  [CA 5] Center 33 (3~64) winsize 62

 1434 13:58:13.468328  

 1435 13:58:13.470973  [CmdBusTrainingLP45] Vref(ca) range 1: 30

 1436 13:58:13.471466  

 1437 13:58:13.474927  [CATrainingPosCal] consider 2 rank data

 1438 13:58:13.477779  u2DelayCellTimex100 = 270/100 ps

 1439 13:58:13.480658  CA0 delay=36 (6~66),Diff = 3 PI (21 cell)

 1440 13:58:13.484302  CA1 delay=36 (6~67),Diff = 3 PI (21 cell)

 1441 13:58:13.491562  CA2 delay=34 (5~64),Diff = 1 PI (7 cell)

 1442 13:58:13.494541  CA3 delay=34 (4~64),Diff = 1 PI (7 cell)

 1443 13:58:13.498837  CA4 delay=34 (4~64),Diff = 1 PI (7 cell)

 1444 13:58:13.502098  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1445 13:58:13.502566  

 1446 13:58:13.506405  CA PerBit enable=1, Macro0, CA PI delay=33

 1447 13:58:13.507002  

 1448 13:58:13.507416  [CBTSetCACLKResult] CA Dly = 33

 1449 13:58:13.509519  CS Dly: 6 (0~38)

 1450 13:58:13.509978  

 1451 13:58:13.513676  ----->DramcWriteLeveling(PI) begin...

 1452 13:58:13.514142  ==

 1453 13:58:13.517289  Dram Type= 6, Freq= 0, CH_1, rank 0

 1454 13:58:13.520649  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1455 13:58:13.521113  ==

 1456 13:58:13.524482  Write leveling (Byte 0): 25 => 25

 1457 13:58:13.528748  Write leveling (Byte 1): 29 => 29

 1458 13:58:13.529213  DramcWriteLeveling(PI) end<-----

 1459 13:58:13.529578  

 1460 13:58:13.529912  ==

 1461 13:58:13.532003  Dram Type= 6, Freq= 0, CH_1, rank 0

 1462 13:58:13.538532  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1463 13:58:13.539011  ==

 1464 13:58:13.541704  [Gating] SW mode calibration

 1465 13:58:13.548163  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1466 13:58:13.551494  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1467 13:58:13.558423   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1468 13:58:13.561851   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1469 13:58:13.564807   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1470 13:58:13.568397   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1471 13:58:13.574950   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1472 13:58:13.578446   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1473 13:58:13.581784   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1474 13:58:13.587951   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1475 13:58:13.591652   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1476 13:58:13.594788   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1477 13:58:13.601142   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1478 13:58:13.604754   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1479 13:58:13.608015   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1480 13:58:13.614923   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1481 13:58:13.618001   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1482 13:58:13.621855   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1483 13:58:13.628298   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1484 13:58:13.631445   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1485 13:58:13.635080   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1486 13:58:13.641686   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1487 13:58:13.645134   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1488 13:58:13.648142   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1489 13:58:13.655006   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1490 13:58:13.658476   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1491 13:58:13.661607   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1492 13:58:13.664951   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1493 13:58:13.671772   0  9  8 | B1->B0 | 2e2e 2a2a | 1 1 | (1 1) (1 1)

 1494 13:58:13.675091   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1495 13:58:13.678640   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1496 13:58:13.685293   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1497 13:58:13.688767   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1498 13:58:13.692116   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1499 13:58:13.698095   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1500 13:58:13.702024   0 10  4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)

 1501 13:58:13.704981   0 10  8 | B1->B0 | 2828 2d2d | 0 0 | (0 1) (0 1)

 1502 13:58:13.712186   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1503 13:58:13.714975   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1504 13:58:13.718134   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1505 13:58:13.724686   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1506 13:58:13.727800   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1507 13:58:13.731560   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1508 13:58:13.737927   0 11  4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)

 1509 13:58:13.741294   0 11  8 | B1->B0 | 4141 3a3a | 0 0 | (0 0) (0 0)

 1510 13:58:13.745077   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1511 13:58:13.751269   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1512 13:58:13.754429   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1513 13:58:13.758574   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1514 13:58:13.761328   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1515 13:58:13.768004   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1516 13:58:13.771332   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1517 13:58:13.774304   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1518 13:58:13.781633   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1519 13:58:13.784601   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1520 13:58:13.787687   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1521 13:58:13.794732   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1522 13:58:13.797684   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1523 13:58:13.801152   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1524 13:58:13.807675   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1525 13:58:13.811588   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1526 13:58:13.814561   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1527 13:58:13.820962   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1528 13:58:13.824611   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1529 13:58:13.827968   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1530 13:58:13.834292   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1531 13:58:13.837650   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1532 13:58:13.841361   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1533 13:58:13.847600   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1534 13:58:13.851226   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1535 13:58:13.854738  Total UI for P1: 0, mck2ui 16

 1536 13:58:13.857781  best dqsien dly found for B0: ( 0, 14,  8)

 1537 13:58:13.861000  Total UI for P1: 0, mck2ui 16

 1538 13:58:13.864672  best dqsien dly found for B1: ( 0, 14,  8)

 1539 13:58:13.867890  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

 1540 13:58:13.871348  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1541 13:58:13.871475  

 1542 13:58:13.874376  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1543 13:58:13.877826  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1544 13:58:13.881656  [Gating] SW calibration Done

 1545 13:58:13.881737  ==

 1546 13:58:13.884812  Dram Type= 6, Freq= 0, CH_1, rank 0

 1547 13:58:13.888285  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1548 13:58:13.888366  ==

 1549 13:58:13.891213  RX Vref Scan: 0

 1550 13:58:13.891293  

 1551 13:58:13.891356  RX Vref 0 -> 0, step: 1

 1552 13:58:13.891459  

 1553 13:58:13.894442  RX Delay -130 -> 252, step: 16

 1554 13:58:13.897864  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1555 13:58:13.904846  iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256

 1556 13:58:13.907849  iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240

 1557 13:58:13.911414  iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256

 1558 13:58:13.914690  iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256

 1559 13:58:13.918058  iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256

 1560 13:58:13.924802  iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256

 1561 13:58:13.927988  iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256

 1562 13:58:13.931091  iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256

 1563 13:58:13.934735  iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256

 1564 13:58:13.937851  iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240

 1565 13:58:13.944735  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1566 13:58:13.948282  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1567 13:58:13.951351  iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256

 1568 13:58:13.954792  iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256

 1569 13:58:13.958557  iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256

 1570 13:58:13.961143  ==

 1571 13:58:13.964778  Dram Type= 6, Freq= 0, CH_1, rank 0

 1572 13:58:13.967721  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1573 13:58:13.967802  ==

 1574 13:58:13.967867  DQS Delay:

 1575 13:58:13.971301  DQS0 = 0, DQS1 = 0

 1576 13:58:13.971390  DQM Delay:

 1577 13:58:13.974690  DQM0 = 81, DQM1 = 72

 1578 13:58:13.974771  DQ Delay:

 1579 13:58:13.978330  DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77

 1580 13:58:13.981158  DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77

 1581 13:58:13.984510  DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69

 1582 13:58:13.988326  DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77

 1583 13:58:13.988408  

 1584 13:58:13.988472  

 1585 13:58:13.988532  ==

 1586 13:58:13.991679  Dram Type= 6, Freq= 0, CH_1, rank 0

 1587 13:58:13.994746  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1588 13:58:13.994828  ==

 1589 13:58:13.994892  

 1590 13:58:13.994952  

 1591 13:58:13.998087  	TX Vref Scan disable

 1592 13:58:14.001505   == TX Byte 0 ==

 1593 13:58:14.005143  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1594 13:58:14.008013  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1595 13:58:14.011256   == TX Byte 1 ==

 1596 13:58:14.014809  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1597 13:58:14.018191  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1598 13:58:14.018321  ==

 1599 13:58:14.021240  Dram Type= 6, Freq= 0, CH_1, rank 0

 1600 13:58:14.024727  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1601 13:58:14.024809  ==

 1602 13:58:14.039314  TX Vref=22, minBit 8, minWin=27, winSum=448

 1603 13:58:14.042706  TX Vref=24, minBit 8, minWin=27, winSum=450

 1604 13:58:14.046027  TX Vref=26, minBit 11, minWin=27, winSum=451

 1605 13:58:14.049256  TX Vref=28, minBit 11, minWin=27, winSum=455

 1606 13:58:14.052570  TX Vref=30, minBit 0, minWin=28, winSum=457

 1607 13:58:14.059514  TX Vref=32, minBit 8, minWin=27, winSum=451

 1608 13:58:14.063077  [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30

 1609 13:58:14.063158  

 1610 13:58:14.065893  Final TX Range 1 Vref 30

 1611 13:58:14.065973  

 1612 13:58:14.066037  ==

 1613 13:58:14.069932  Dram Type= 6, Freq= 0, CH_1, rank 0

 1614 13:58:14.073205  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1615 13:58:14.073286  ==

 1616 13:58:14.073350  

 1617 13:58:14.073409  

 1618 13:58:14.076644  	TX Vref Scan disable

 1619 13:58:14.079962   == TX Byte 0 ==

 1620 13:58:14.083557  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1621 13:58:14.086791  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1622 13:58:14.090161   == TX Byte 1 ==

 1623 13:58:14.093211  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1624 13:58:14.096475  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1625 13:58:14.096568  

 1626 13:58:14.099844  [DATLAT]

 1627 13:58:14.099926  Freq=800, CH1 RK0

 1628 13:58:14.099991  

 1629 13:58:14.103343  DATLAT Default: 0xa

 1630 13:58:14.103465  0, 0xFFFF, sum = 0

 1631 13:58:14.106451  1, 0xFFFF, sum = 0

 1632 13:58:14.106571  2, 0xFFFF, sum = 0

 1633 13:58:14.109795  3, 0xFFFF, sum = 0

 1634 13:58:14.109878  4, 0xFFFF, sum = 0

 1635 13:58:14.113181  5, 0xFFFF, sum = 0

 1636 13:58:14.113264  6, 0xFFFF, sum = 0

 1637 13:58:14.116539  7, 0xFFFF, sum = 0

 1638 13:58:14.116629  8, 0xFFFF, sum = 0

 1639 13:58:14.120000  9, 0x0, sum = 1

 1640 13:58:14.120082  10, 0x0, sum = 2

 1641 13:58:14.123497  11, 0x0, sum = 3

 1642 13:58:14.123610  12, 0x0, sum = 4

 1643 13:58:14.126417  best_step = 10

 1644 13:58:14.126515  

 1645 13:58:14.126615  ==

 1646 13:58:14.130035  Dram Type= 6, Freq= 0, CH_1, rank 0

 1647 13:58:14.133649  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1648 13:58:14.133731  ==

 1649 13:58:14.136950  RX Vref Scan: 1

 1650 13:58:14.137031  

 1651 13:58:14.137095  Set Vref Range= 32 -> 127

 1652 13:58:14.137154  

 1653 13:58:14.140147  RX Vref 32 -> 127, step: 1

 1654 13:58:14.140228  

 1655 13:58:14.143326  RX Delay -111 -> 252, step: 8

 1656 13:58:14.143446  

 1657 13:58:14.146838  Set Vref, RX VrefLevel [Byte0]: 32

 1658 13:58:14.150276                           [Byte1]: 32

 1659 13:58:14.150359  

 1660 13:58:14.153272  Set Vref, RX VrefLevel [Byte0]: 33

 1661 13:58:14.156649                           [Byte1]: 33

 1662 13:58:14.160230  

 1663 13:58:14.160348  Set Vref, RX VrefLevel [Byte0]: 34

 1664 13:58:14.163293                           [Byte1]: 34

 1665 13:58:14.167727  

 1666 13:58:14.167808  Set Vref, RX VrefLevel [Byte0]: 35

 1667 13:58:14.171141                           [Byte1]: 35

 1668 13:58:14.175201  

 1669 13:58:14.175281  Set Vref, RX VrefLevel [Byte0]: 36

 1670 13:58:14.178644                           [Byte1]: 36

 1671 13:58:14.183395  

 1672 13:58:14.183476  Set Vref, RX VrefLevel [Byte0]: 37

 1673 13:58:14.186408                           [Byte1]: 37

 1674 13:58:14.190536  

 1675 13:58:14.190616  Set Vref, RX VrefLevel [Byte0]: 38

 1676 13:58:14.193883                           [Byte1]: 38

 1677 13:58:14.198584  

 1678 13:58:14.198664  Set Vref, RX VrefLevel [Byte0]: 39

 1679 13:58:14.201492                           [Byte1]: 39

 1680 13:58:14.205892  

 1681 13:58:14.205973  Set Vref, RX VrefLevel [Byte0]: 40

 1682 13:58:14.209515                           [Byte1]: 40

 1683 13:58:14.213822  

 1684 13:58:14.213902  Set Vref, RX VrefLevel [Byte0]: 41

 1685 13:58:14.216608                           [Byte1]: 41

 1686 13:58:14.221209  

 1687 13:58:14.221289  Set Vref, RX VrefLevel [Byte0]: 42

 1688 13:58:14.224712                           [Byte1]: 42

 1689 13:58:14.228658  

 1690 13:58:14.228739  Set Vref, RX VrefLevel [Byte0]: 43

 1691 13:58:14.232174                           [Byte1]: 43

 1692 13:58:14.236474  

 1693 13:58:14.236554  Set Vref, RX VrefLevel [Byte0]: 44

 1694 13:58:14.239844                           [Byte1]: 44

 1695 13:58:14.243874  

 1696 13:58:14.243955  Set Vref, RX VrefLevel [Byte0]: 45

 1697 13:58:14.247354                           [Byte1]: 45

 1698 13:58:14.251482  

 1699 13:58:14.251562  Set Vref, RX VrefLevel [Byte0]: 46

 1700 13:58:14.255182                           [Byte1]: 46

 1701 13:58:14.259577  

 1702 13:58:14.259658  Set Vref, RX VrefLevel [Byte0]: 47

 1703 13:58:14.262673                           [Byte1]: 47

 1704 13:58:14.266852  

 1705 13:58:14.266932  Set Vref, RX VrefLevel [Byte0]: 48

 1706 13:58:14.270384                           [Byte1]: 48

 1707 13:58:14.274675  

 1708 13:58:14.274756  Set Vref, RX VrefLevel [Byte0]: 49

 1709 13:58:14.278173                           [Byte1]: 49

 1710 13:58:14.282219  

 1711 13:58:14.282299  Set Vref, RX VrefLevel [Byte0]: 50

 1712 13:58:14.288876                           [Byte1]: 50

 1713 13:58:14.288957  

 1714 13:58:14.292258  Set Vref, RX VrefLevel [Byte0]: 51

 1715 13:58:14.295735                           [Byte1]: 51

 1716 13:58:14.295816  

 1717 13:58:14.299272  Set Vref, RX VrefLevel [Byte0]: 52

 1718 13:58:14.302228                           [Byte1]: 52

 1719 13:58:14.302309  

 1720 13:58:14.305411  Set Vref, RX VrefLevel [Byte0]: 53

 1721 13:58:14.308786                           [Byte1]: 53

 1722 13:58:14.313235  

 1723 13:58:14.313315  Set Vref, RX VrefLevel [Byte0]: 54

 1724 13:58:14.316241                           [Byte1]: 54

 1725 13:58:14.320541  

 1726 13:58:14.320651  Set Vref, RX VrefLevel [Byte0]: 55

 1727 13:58:14.324174                           [Byte1]: 55

 1728 13:58:14.328379  

 1729 13:58:14.328459  Set Vref, RX VrefLevel [Byte0]: 56

 1730 13:58:14.331395                           [Byte1]: 56

 1731 13:58:14.336208  

 1732 13:58:14.336288  Set Vref, RX VrefLevel [Byte0]: 57

 1733 13:58:14.339253                           [Byte1]: 57

 1734 13:58:14.343684  

 1735 13:58:14.343757  Set Vref, RX VrefLevel [Byte0]: 58

 1736 13:58:14.346736                           [Byte1]: 58

 1737 13:58:14.351447  

 1738 13:58:14.351529  Set Vref, RX VrefLevel [Byte0]: 59

 1739 13:58:14.354485                           [Byte1]: 59

 1740 13:58:14.358903  

 1741 13:58:14.358983  Set Vref, RX VrefLevel [Byte0]: 60

 1742 13:58:14.362196                           [Byte1]: 60

 1743 13:58:14.366545  

 1744 13:58:14.366685  Set Vref, RX VrefLevel [Byte0]: 61

 1745 13:58:14.369578                           [Byte1]: 61

 1746 13:58:14.374040  

 1747 13:58:14.374121  Set Vref, RX VrefLevel [Byte0]: 62

 1748 13:58:14.377363                           [Byte1]: 62

 1749 13:58:14.381915  

 1750 13:58:14.381995  Set Vref, RX VrefLevel [Byte0]: 63

 1751 13:58:14.384836                           [Byte1]: 63

 1752 13:58:14.389612  

 1753 13:58:14.389692  Set Vref, RX VrefLevel [Byte0]: 64

 1754 13:58:14.392734                           [Byte1]: 64

 1755 13:58:14.396974  

 1756 13:58:14.397054  Set Vref, RX VrefLevel [Byte0]: 65

 1757 13:58:14.400271                           [Byte1]: 65

 1758 13:58:14.405030  

 1759 13:58:14.405110  Set Vref, RX VrefLevel [Byte0]: 66

 1760 13:58:14.408300                           [Byte1]: 66

 1761 13:58:14.412515  

 1762 13:58:14.412595  Set Vref, RX VrefLevel [Byte0]: 67

 1763 13:58:14.415684                           [Byte1]: 67

 1764 13:58:14.419710  

 1765 13:58:14.419791  Set Vref, RX VrefLevel [Byte0]: 68

 1766 13:58:14.423100                           [Byte1]: 68

 1767 13:58:14.427638  

 1768 13:58:14.427724  Set Vref, RX VrefLevel [Byte0]: 69

 1769 13:58:14.430856                           [Byte1]: 69

 1770 13:58:14.434966  

 1771 13:58:14.435074  Set Vref, RX VrefLevel [Byte0]: 70

 1772 13:58:14.438647                           [Byte1]: 70

 1773 13:58:14.442685  

 1774 13:58:14.442762  Set Vref, RX VrefLevel [Byte0]: 71

 1775 13:58:14.446112                           [Byte1]: 71

 1776 13:58:14.450499  

 1777 13:58:14.450587  Set Vref, RX VrefLevel [Byte0]: 72

 1778 13:58:14.453775                           [Byte1]: 72

 1779 13:58:14.458445  

 1780 13:58:14.458520  Set Vref, RX VrefLevel [Byte0]: 73

 1781 13:58:14.461373                           [Byte1]: 73

 1782 13:58:14.465584  

 1783 13:58:14.465659  Set Vref, RX VrefLevel [Byte0]: 74

 1784 13:58:14.469161                           [Byte1]: 74

 1785 13:58:14.473231  

 1786 13:58:14.473311  Set Vref, RX VrefLevel [Byte0]: 75

 1787 13:58:14.477014                           [Byte1]: 75

 1788 13:58:14.480867  

 1789 13:58:14.480950  Set Vref, RX VrefLevel [Byte0]: 76

 1790 13:58:14.484544                           [Byte1]: 76

 1791 13:58:14.488811  

 1792 13:58:14.488901  Set Vref, RX VrefLevel [Byte0]: 77

 1793 13:58:14.492448                           [Byte1]: 77

 1794 13:58:14.496550  

 1795 13:58:14.496637  Final RX Vref Byte 0 = 54 to rank0

 1796 13:58:14.499451  Final RX Vref Byte 1 = 55 to rank0

 1797 13:58:14.502906  Final RX Vref Byte 0 = 54 to rank1

 1798 13:58:14.506404  Final RX Vref Byte 1 = 55 to rank1==

 1799 13:58:14.509757  Dram Type= 6, Freq= 0, CH_1, rank 0

 1800 13:58:14.516606  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1801 13:58:14.516689  ==

 1802 13:58:14.516755  DQS Delay:

 1803 13:58:14.516839  DQS0 = 0, DQS1 = 0

 1804 13:58:14.519728  DQM Delay:

 1805 13:58:14.519804  DQM0 = 80, DQM1 = 70

 1806 13:58:14.522981  DQ Delay:

 1807 13:58:14.526358  DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76

 1808 13:58:14.526442  DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76

 1809 13:58:14.529756  DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64

 1810 13:58:14.533286  DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76

 1811 13:58:14.536564  

 1812 13:58:14.536644  

 1813 13:58:14.543554  [DQSOSCAuto] RK0, (LSB)MR18= 0x101a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps

 1814 13:58:14.546734  CH1 RK0: MR19=606, MR18=101A

 1815 13:58:14.552862  CH1_RK0: MR19=0x606, MR18=0x101A, DQSOSC=403, MR23=63, INC=90, DEC=60

 1816 13:58:14.552944  

 1817 13:58:14.556315  ----->DramcWriteLeveling(PI) begin...

 1818 13:58:14.556398  ==

 1819 13:58:14.559880  Dram Type= 6, Freq= 0, CH_1, rank 1

 1820 13:58:14.563348  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1821 13:58:14.563442  ==

 1822 13:58:14.566300  Write leveling (Byte 0): 28 => 28

 1823 13:58:14.569840  Write leveling (Byte 1): 30 => 30

 1824 13:58:14.573176  DramcWriteLeveling(PI) end<-----

 1825 13:58:14.573256  

 1826 13:58:14.573320  ==

 1827 13:58:14.576458  Dram Type= 6, Freq= 0, CH_1, rank 1

 1828 13:58:14.579856  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1829 13:58:14.579938  ==

 1830 13:58:14.582812  [Gating] SW mode calibration

 1831 13:58:14.589966  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1832 13:58:14.596714  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1833 13:58:14.599880   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1834 13:58:14.603298   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1835 13:58:14.609786   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1836 13:58:14.613130   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1837 13:58:14.616553   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1838 13:58:14.622881   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1839 13:58:14.626496   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1840 13:58:14.629651   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1841 13:58:14.636510   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1842 13:58:14.639478   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1843 13:58:14.643402   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1844 13:58:14.650102   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1845 13:58:14.652862   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1846 13:58:14.656388   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1847 13:58:14.659485   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1848 13:58:14.666498   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1849 13:58:14.669367   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1850 13:58:14.672977   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1851 13:58:14.679426   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1852 13:58:14.683017   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1853 13:58:14.686269   0  8 16 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)

 1854 13:58:14.692823   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1855 13:58:14.696334   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1856 13:58:14.699319   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1857 13:58:14.706468   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1858 13:58:14.709567   0  9  4 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)

 1859 13:58:14.712874   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1860 13:58:14.719631   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1861 13:58:14.722570   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1862 13:58:14.726512   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1863 13:58:14.733016   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1864 13:58:14.736490   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1865 13:58:14.739699   0 10  0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)

 1866 13:58:14.746157   0 10  4 | B1->B0 | 3030 2e2e | 0 1 | (0 0) (1 0)

 1867 13:58:14.749471   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1868 13:58:14.752907   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1869 13:58:14.759481   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1870 13:58:14.763067   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1871 13:58:14.766054   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1872 13:58:14.769616   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1873 13:58:14.776002   0 11  0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)

 1874 13:58:14.779557   0 11  4 | B1->B0 | 3030 3939 | 0 0 | (0 0) (1 1)

 1875 13:58:14.783055   0 11  8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)

 1876 13:58:14.789305   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1877 13:58:14.792793   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1878 13:58:14.795930   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1879 13:58:14.802793   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1880 13:58:14.806494   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1881 13:58:14.809359   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1882 13:58:14.816156   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1883 13:58:14.819657   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1884 13:58:14.823036   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1885 13:58:14.829344   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1886 13:58:14.832776   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1887 13:58:14.836219   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1888 13:58:14.843067   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1889 13:58:14.846812   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1890 13:58:14.849618   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1891 13:58:14.856179   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1892 13:58:14.859356   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1893 13:58:14.863094   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1894 13:58:14.869449   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1895 13:58:14.872799   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1896 13:58:14.876298   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1897 13:58:14.879210   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1898 13:58:14.886235   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1899 13:58:14.889333   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1900 13:58:14.892800  Total UI for P1: 0, mck2ui 16

 1901 13:58:14.896138  best dqsien dly found for B0: ( 0, 14,  4)

 1902 13:58:14.899815   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1903 13:58:14.902725  Total UI for P1: 0, mck2ui 16

 1904 13:58:14.906223  best dqsien dly found for B1: ( 0, 14,  8)

 1905 13:58:14.909417  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1906 13:58:14.913121  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1907 13:58:14.913202  

 1908 13:58:14.919658  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1909 13:58:14.923010  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1910 13:58:14.923091  [Gating] SW calibration Done

 1911 13:58:14.926071  ==

 1912 13:58:14.926152  Dram Type= 6, Freq= 0, CH_1, rank 1

 1913 13:58:14.933306  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1914 13:58:14.933387  ==

 1915 13:58:14.933451  RX Vref Scan: 0

 1916 13:58:14.933510  

 1917 13:58:14.936189  RX Vref 0 -> 0, step: 1

 1918 13:58:14.936269  

 1919 13:58:14.939354  RX Delay -130 -> 252, step: 16

 1920 13:58:14.942603  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1921 13:58:14.946506  iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240

 1922 13:58:14.949561  iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240

 1923 13:58:14.956642  iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256

 1924 13:58:14.959560  iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256

 1925 13:58:14.962999  iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256

 1926 13:58:14.966262  iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240

 1927 13:58:14.969461  iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256

 1928 13:58:14.976593  iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256

 1929 13:58:14.979846  iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256

 1930 13:58:14.983054  iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256

 1931 13:58:14.986253  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1932 13:58:14.989738  iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256

 1933 13:58:14.996232  iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256

 1934 13:58:14.999839  iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256

 1935 13:58:15.003314  iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256

 1936 13:58:15.003433  ==

 1937 13:58:15.006826  Dram Type= 6, Freq= 0, CH_1, rank 1

 1938 13:58:15.009723  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1939 13:58:15.009805  ==

 1940 13:58:15.013205  DQS Delay:

 1941 13:58:15.013286  DQS0 = 0, DQS1 = 0

 1942 13:58:15.016784  DQM Delay:

 1943 13:58:15.016864  DQM0 = 79, DQM1 = 72

 1944 13:58:15.016928  DQ Delay:

 1945 13:58:15.019627  DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77

 1946 13:58:15.023195  DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77

 1947 13:58:15.026687  DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69

 1948 13:58:15.029845  DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77

 1949 13:58:15.029926  

 1950 13:58:15.029989  

 1951 13:58:15.030048  ==

 1952 13:58:15.033201  Dram Type= 6, Freq= 0, CH_1, rank 1

 1953 13:58:15.039651  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1954 13:58:15.039733  ==

 1955 13:58:15.039797  

 1956 13:58:15.039872  

 1957 13:58:15.039944  	TX Vref Scan disable

 1958 13:58:15.043676   == TX Byte 0 ==

 1959 13:58:15.046946  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1960 13:58:15.053178  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1961 13:58:15.053324   == TX Byte 1 ==

 1962 13:58:15.056825  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1963 13:58:15.063703  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1964 13:58:15.063787  ==

 1965 13:58:15.066944  Dram Type= 6, Freq= 0, CH_1, rank 1

 1966 13:58:15.070075  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1967 13:58:15.070158  ==

 1968 13:58:15.082396  TX Vref=22, minBit 11, minWin=27, winSum=449

 1969 13:58:15.085759  TX Vref=24, minBit 0, minWin=28, winSum=453

 1970 13:58:15.089185  TX Vref=26, minBit 6, minWin=28, winSum=459

 1971 13:58:15.092523  TX Vref=28, minBit 4, minWin=28, winSum=459

 1972 13:58:15.095955  TX Vref=30, minBit 9, minWin=28, winSum=461

 1973 13:58:15.099479  TX Vref=32, minBit 2, minWin=28, winSum=456

 1974 13:58:15.105887  [TxChooseVref] Worse bit 9, Min win 28, Win sum 461, Final Vref 30

 1975 13:58:15.105970  

 1976 13:58:15.109388  Final TX Range 1 Vref 30

 1977 13:58:15.109472  

 1978 13:58:15.109538  ==

 1979 13:58:15.112796  Dram Type= 6, Freq= 0, CH_1, rank 1

 1980 13:58:15.116086  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1981 13:58:15.116204  ==

 1982 13:58:15.116312  

 1983 13:58:15.119051  

 1984 13:58:15.119156  	TX Vref Scan disable

 1985 13:58:15.122644   == TX Byte 0 ==

 1986 13:58:15.125722  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1987 13:58:15.129088  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1988 13:58:15.132994   == TX Byte 1 ==

 1989 13:58:15.135802  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1990 13:58:15.139231  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1991 13:58:15.142525  

 1992 13:58:15.142601  [DATLAT]

 1993 13:58:15.142666  Freq=800, CH1 RK1

 1994 13:58:15.142727  

 1995 13:58:15.146264  DATLAT Default: 0xa

 1996 13:58:15.146347  0, 0xFFFF, sum = 0

 1997 13:58:15.149156  1, 0xFFFF, sum = 0

 1998 13:58:15.149240  2, 0xFFFF, sum = 0

 1999 13:58:15.152493  3, 0xFFFF, sum = 0

 2000 13:58:15.152577  4, 0xFFFF, sum = 0

 2001 13:58:15.155858  5, 0xFFFF, sum = 0

 2002 13:58:15.155942  6, 0xFFFF, sum = 0

 2003 13:58:15.159128  7, 0xFFFF, sum = 0

 2004 13:58:15.162505  8, 0xFFFF, sum = 0

 2005 13:58:15.162590  9, 0x0, sum = 1

 2006 13:58:15.162657  10, 0x0, sum = 2

 2007 13:58:15.165819  11, 0x0, sum = 3

 2008 13:58:15.165903  12, 0x0, sum = 4

 2009 13:58:15.169127  best_step = 10

 2010 13:58:15.169208  

 2011 13:58:15.169274  ==

 2012 13:58:15.172766  Dram Type= 6, Freq= 0, CH_1, rank 1

 2013 13:58:15.176093  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2014 13:58:15.176176  ==

 2015 13:58:15.179157  RX Vref Scan: 0

 2016 13:58:15.179267  

 2017 13:58:15.179364  RX Vref 0 -> 0, step: 1

 2018 13:58:15.179451  

 2019 13:58:15.182940  RX Delay -111 -> 252, step: 8

 2020 13:58:15.189531  iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240

 2021 13:58:15.193116  iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240

 2022 13:58:15.196018  iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240

 2023 13:58:15.199541  iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240

 2024 13:58:15.202714  iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248

 2025 13:58:15.209473  iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240

 2026 13:58:15.212697  iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240

 2027 13:58:15.216251  iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248

 2028 13:58:15.219139  iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248

 2029 13:58:15.222692  iDelay=209, Bit 9, Center 60 (-63 ~ 184) 248

 2030 13:58:15.229618  iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248

 2031 13:58:15.232518  iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240

 2032 13:58:15.235919  iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240

 2033 13:58:15.239332  iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240

 2034 13:58:15.242939  iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240

 2035 13:58:15.249169  iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248

 2036 13:58:15.249266  ==

 2037 13:58:15.252609  Dram Type= 6, Freq= 0, CH_1, rank 1

 2038 13:58:15.256092  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2039 13:58:15.256179  ==

 2040 13:58:15.256251  DQS Delay:

 2041 13:58:15.259645  DQS0 = 0, DQS1 = 0

 2042 13:58:15.259730  DQM Delay:

 2043 13:58:15.262686  DQM0 = 77, DQM1 = 72

 2044 13:58:15.262767  DQ Delay:

 2045 13:58:15.265849  DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72

 2046 13:58:15.269522  DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76

 2047 13:58:15.273048  DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64

 2048 13:58:15.276565  DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76

 2049 13:58:15.276649  

 2050 13:58:15.276714  

 2051 13:58:15.282771  [DQSOSCAuto] RK1, (LSB)MR18= 0x233a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps

 2052 13:58:15.286291  CH1 RK1: MR19=606, MR18=233A

 2053 13:58:15.292722  CH1_RK1: MR19=0x606, MR18=0x233A, DQSOSC=395, MR23=63, INC=94, DEC=63

 2054 13:58:15.295805  [RxdqsGatingPostProcess] freq 800

 2055 13:58:15.302363  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2056 13:58:15.305925  Pre-setting of DQS Precalculation

 2057 13:58:15.309549  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2058 13:58:15.316044  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2059 13:58:15.322572  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2060 13:58:15.322672  

 2061 13:58:15.326236  

 2062 13:58:15.326317  [Calibration Summary] 1600 Mbps

 2063 13:58:15.329284  CH 0, Rank 0

 2064 13:58:15.329418  SW Impedance     : PASS

 2065 13:58:15.332366  DUTY Scan        : NO K

 2066 13:58:15.335809  ZQ Calibration   : PASS

 2067 13:58:15.335897  Jitter Meter     : NO K

 2068 13:58:15.339172  CBT Training     : PASS

 2069 13:58:15.342336  Write leveling   : PASS

 2070 13:58:15.342417  RX DQS gating    : PASS

 2071 13:58:15.345663  RX DQ/DQS(RDDQC) : PASS

 2072 13:58:15.349178  TX DQ/DQS        : PASS

 2073 13:58:15.349259  RX DATLAT        : PASS

 2074 13:58:15.352552  RX DQ/DQS(Engine): PASS

 2075 13:58:15.355727  TX OE            : NO K

 2076 13:58:15.355808  All Pass.

 2077 13:58:15.355872  

 2078 13:58:15.355932  CH 0, Rank 1

 2079 13:58:15.359540  SW Impedance     : PASS

 2080 13:58:15.359621  DUTY Scan        : NO K

 2081 13:58:15.362540  ZQ Calibration   : PASS

 2082 13:58:15.365723  Jitter Meter     : NO K

 2083 13:58:15.365830  CBT Training     : PASS

 2084 13:58:15.368974  Write leveling   : PASS

 2085 13:58:15.372771  RX DQS gating    : PASS

 2086 13:58:15.372851  RX DQ/DQS(RDDQC) : PASS

 2087 13:58:15.375582  TX DQ/DQS        : PASS

 2088 13:58:15.378953  RX DATLAT        : PASS

 2089 13:58:15.379065  RX DQ/DQS(Engine): PASS

 2090 13:58:15.382745  TX OE            : NO K

 2091 13:58:15.382827  All Pass.

 2092 13:58:15.382908  

 2093 13:58:15.385521  CH 1, Rank 0

 2094 13:58:15.385601  SW Impedance     : PASS

 2095 13:58:15.388899  DUTY Scan        : NO K

 2096 13:58:15.392433  ZQ Calibration   : PASS

 2097 13:58:15.392514  Jitter Meter     : NO K

 2098 13:58:15.395730  CBT Training     : PASS

 2099 13:58:15.399187  Write leveling   : PASS

 2100 13:58:15.399267  RX DQS gating    : PASS

 2101 13:58:15.402112  RX DQ/DQS(RDDQC) : PASS

 2102 13:58:15.405587  TX DQ/DQS        : PASS

 2103 13:58:15.405669  RX DATLAT        : PASS

 2104 13:58:15.408737  RX DQ/DQS(Engine): PASS

 2105 13:58:15.408818  TX OE            : NO K

 2106 13:58:15.411977  All Pass.

 2107 13:58:15.412083  

 2108 13:58:15.412180  CH 1, Rank 1

 2109 13:58:15.415588  SW Impedance     : PASS

 2110 13:58:15.415669  DUTY Scan        : NO K

 2111 13:58:15.419026  ZQ Calibration   : PASS

 2112 13:58:15.422807  Jitter Meter     : NO K

 2113 13:58:15.422888  CBT Training     : PASS

 2114 13:58:15.425448  Write leveling   : PASS

 2115 13:58:15.428788  RX DQS gating    : PASS

 2116 13:58:15.428896  RX DQ/DQS(RDDQC) : PASS

 2117 13:58:15.432150  TX DQ/DQS        : PASS

 2118 13:58:15.435786  RX DATLAT        : PASS

 2119 13:58:15.435866  RX DQ/DQS(Engine): PASS

 2120 13:58:15.439004  TX OE            : NO K

 2121 13:58:15.439111  All Pass.

 2122 13:58:15.439203  

 2123 13:58:15.442436  DramC Write-DBI off

 2124 13:58:15.445473  	PER_BANK_REFRESH: Hybrid Mode

 2125 13:58:15.445580  TX_TRACKING: ON

 2126 13:58:15.449181  [GetDramInforAfterCalByMRR] Vendor 6.

 2127 13:58:15.451866  [GetDramInforAfterCalByMRR] Revision 606.

 2128 13:58:15.455825  [GetDramInforAfterCalByMRR] Revision 2 0.

 2129 13:58:15.458698  MR0 0x3b3b

 2130 13:58:15.458781  MR8 0x5151

 2131 13:58:15.462102  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2132 13:58:15.462183  

 2133 13:58:15.462247  MR0 0x3b3b

 2134 13:58:15.465340  MR8 0x5151

 2135 13:58:15.469030  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2136 13:58:15.469139  

 2137 13:58:15.478822  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2138 13:58:15.482337  [FAST_K] Save calibration result to emmc

 2139 13:58:15.485693  [FAST_K] Save calibration result to emmc

 2140 13:58:15.485777  dram_init: config_dvfs: 1

 2141 13:58:15.491979  dramc_set_vcore_voltage set vcore to 662500

 2142 13:58:15.492064  Read voltage for 1200, 2

 2143 13:58:15.495570  Vio18 = 0

 2144 13:58:15.495645  Vcore = 662500

 2145 13:58:15.495715  Vdram = 0

 2146 13:58:15.495780  Vddq = 0

 2147 13:58:15.498844  Vmddr = 0

 2148 13:58:15.501846  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2149 13:58:15.508661  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2150 13:58:15.512166  MEM_TYPE=3, freq_sel=15

 2151 13:58:15.512248  sv_algorithm_assistance_LP4_1600 

 2152 13:58:15.518438  ============ PULL DRAM RESETB DOWN ============

 2153 13:58:15.522106  ========== PULL DRAM RESETB DOWN end =========

 2154 13:58:15.525644  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2155 13:58:15.528610  =================================== 

 2156 13:58:15.532163  LPDDR4 DRAM CONFIGURATION

 2157 13:58:15.535835  =================================== 

 2158 13:58:15.538806  EX_ROW_EN[0]    = 0x0

 2159 13:58:15.538889  EX_ROW_EN[1]    = 0x0

 2160 13:58:15.542432  LP4Y_EN      = 0x0

 2161 13:58:15.542548  WORK_FSP     = 0x0

 2162 13:58:15.545291  WL           = 0x4

 2163 13:58:15.545390  RL           = 0x4

 2164 13:58:15.548674  BL           = 0x2

 2165 13:58:15.548790  RPST         = 0x0

 2166 13:58:15.552038  RD_PRE       = 0x0

 2167 13:58:15.552126  WR_PRE       = 0x1

 2168 13:58:15.555480  WR_PST       = 0x0

 2169 13:58:15.555567  DBI_WR       = 0x0

 2170 13:58:15.558539  DBI_RD       = 0x0

 2171 13:58:15.558655  OTF          = 0x1

 2172 13:58:15.562351  =================================== 

 2173 13:58:15.565384  =================================== 

 2174 13:58:15.568865  ANA top config

 2175 13:58:15.571856  =================================== 

 2176 13:58:15.575718  DLL_ASYNC_EN            =  0

 2177 13:58:15.575799  ALL_SLAVE_EN            =  0

 2178 13:58:15.578791  NEW_RANK_MODE           =  1

 2179 13:58:15.582042  DLL_IDLE_MODE           =  1

 2180 13:58:15.585466  LP45_APHY_COMB_EN       =  1

 2181 13:58:15.585548  TX_ODT_DIS              =  1

 2182 13:58:15.588591  NEW_8X_MODE             =  1

 2183 13:58:15.591847  =================================== 

 2184 13:58:15.595581  =================================== 

 2185 13:58:15.598481  data_rate                  = 2400

 2186 13:58:15.601937  CKR                        = 1

 2187 13:58:15.605509  DQ_P2S_RATIO               = 8

 2188 13:58:15.608574  =================================== 

 2189 13:58:15.612278  CA_P2S_RATIO               = 8

 2190 13:58:15.612360  DQ_CA_OPEN                 = 0

 2191 13:58:15.615290  DQ_SEMI_OPEN               = 0

 2192 13:58:15.618764  CA_SEMI_OPEN               = 0

 2193 13:58:15.621812  CA_FULL_RATE               = 0

 2194 13:58:15.625200  DQ_CKDIV4_EN               = 0

 2195 13:58:15.628839  CA_CKDIV4_EN               = 0

 2196 13:58:15.628923  CA_PREDIV_EN               = 0

 2197 13:58:15.632296  PH8_DLY                    = 17

 2198 13:58:15.635155  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2199 13:58:15.638866  DQ_AAMCK_DIV               = 4

 2200 13:58:15.642474  CA_AAMCK_DIV               = 4

 2201 13:58:15.642576  CA_ADMCK_DIV               = 4

 2202 13:58:15.645259  DQ_TRACK_CA_EN             = 0

 2203 13:58:15.648722  CA_PICK                    = 1200

 2204 13:58:15.652229  CA_MCKIO                   = 1200

 2205 13:58:15.655258  MCKIO_SEMI                 = 0

 2206 13:58:15.658919  PLL_FREQ                   = 2366

 2207 13:58:15.662361  DQ_UI_PI_RATIO             = 32

 2208 13:58:15.665599  CA_UI_PI_RATIO             = 0

 2209 13:58:15.668764  =================================== 

 2210 13:58:15.668865  =================================== 

 2211 13:58:15.672226  memory_type:LPDDR4         

 2212 13:58:15.675213  GP_NUM     : 10       

 2213 13:58:15.675317  SRAM_EN    : 1       

 2214 13:58:15.678541  MD32_EN    : 0       

 2215 13:58:15.682176  =================================== 

 2216 13:58:15.685140  [ANA_INIT] >>>>>>>>>>>>>> 

 2217 13:58:15.688773  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2218 13:58:15.692169  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2219 13:58:15.695379  =================================== 

 2220 13:58:15.695490  data_rate = 2400,PCW = 0X5b00

 2221 13:58:15.698889  =================================== 

 2222 13:58:15.701928  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2223 13:58:15.708766  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2224 13:58:15.715320  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2225 13:58:15.718768  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2226 13:58:15.722455  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2227 13:58:15.725423  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2228 13:58:15.728859  [ANA_INIT] flow start 

 2229 13:58:15.728938  [ANA_INIT] PLL >>>>>>>> 

 2230 13:58:15.732501  [ANA_INIT] PLL <<<<<<<< 

 2231 13:58:15.735600  [ANA_INIT] MIDPI >>>>>>>> 

 2232 13:58:15.739030  [ANA_INIT] MIDPI <<<<<<<< 

 2233 13:58:15.739113  [ANA_INIT] DLL >>>>>>>> 

 2234 13:58:15.742251  [ANA_INIT] DLL <<<<<<<< 

 2235 13:58:15.745833  [ANA_INIT] flow end 

 2236 13:58:15.748741  ============ LP4 DIFF to SE enter ============

 2237 13:58:15.752347  ============ LP4 DIFF to SE exit  ============

 2238 13:58:15.755655  [ANA_INIT] <<<<<<<<<<<<< 

 2239 13:58:15.758810  [Flow] Enable top DCM control >>>>> 

 2240 13:58:15.762136  [Flow] Enable top DCM control <<<<< 

 2241 13:58:15.765660  Enable DLL master slave shuffle 

 2242 13:58:15.769006  ============================================================== 

 2243 13:58:15.772621  Gating Mode config

 2244 13:58:15.775651  ============================================================== 

 2245 13:58:15.779128  Config description: 

 2246 13:58:15.789117  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2247 13:58:15.795270  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2248 13:58:15.799158  SELPH_MODE            0: By rank         1: By Phase 

 2249 13:58:15.805826  ============================================================== 

 2250 13:58:15.808877  GAT_TRACK_EN                 =  1

 2251 13:58:15.812350  RX_GATING_MODE               =  2

 2252 13:58:15.815328  RX_GATING_TRACK_MODE         =  2

 2253 13:58:15.818897  SELPH_MODE                   =  1

 2254 13:58:15.818977  PICG_EARLY_EN                =  1

 2255 13:58:15.822621  VALID_LAT_VALUE              =  1

 2256 13:58:15.828919  ============================================================== 

 2257 13:58:15.832211  Enter into Gating configuration >>>> 

 2258 13:58:15.835994  Exit from Gating configuration <<<< 

 2259 13:58:15.838749  Enter into  DVFS_PRE_config >>>>> 

 2260 13:58:15.848945  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2261 13:58:15.852124  Exit from  DVFS_PRE_config <<<<< 

 2262 13:58:15.855772  Enter into PICG configuration >>>> 

 2263 13:58:15.858977  Exit from PICG configuration <<<< 

 2264 13:58:15.862304  [RX_INPUT] configuration >>>>> 

 2265 13:58:15.865921  [RX_INPUT] configuration <<<<< 

 2266 13:58:15.869307  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2267 13:58:15.875950  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2268 13:58:15.882584  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2269 13:58:15.889246  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2270 13:58:15.892211  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2271 13:58:15.898975  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2272 13:58:15.902568  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2273 13:58:15.909060  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2274 13:58:15.912456  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2275 13:58:15.916279  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2276 13:58:15.919119  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2277 13:58:15.925699  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2278 13:58:15.928982  =================================== 

 2279 13:58:15.929068  LPDDR4 DRAM CONFIGURATION

 2280 13:58:15.932515  =================================== 

 2281 13:58:15.935584  EX_ROW_EN[0]    = 0x0

 2282 13:58:15.939182  EX_ROW_EN[1]    = 0x0

 2283 13:58:15.939296  LP4Y_EN      = 0x0

 2284 13:58:15.942789  WORK_FSP     = 0x0

 2285 13:58:15.942866  WL           = 0x4

 2286 13:58:15.945835  RL           = 0x4

 2287 13:58:15.945911  BL           = 0x2

 2288 13:58:15.948845  RPST         = 0x0

 2289 13:58:15.948926  RD_PRE       = 0x0

 2290 13:58:15.952492  WR_PRE       = 0x1

 2291 13:58:15.952611  WR_PST       = 0x0

 2292 13:58:15.956062  DBI_WR       = 0x0

 2293 13:58:15.956149  DBI_RD       = 0x0

 2294 13:58:15.958859  OTF          = 0x1

 2295 13:58:15.962720  =================================== 

 2296 13:58:15.965860  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2297 13:58:15.969399  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2298 13:58:15.976024  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2299 13:58:15.979315  =================================== 

 2300 13:58:15.979463  LPDDR4 DRAM CONFIGURATION

 2301 13:58:15.982673  =================================== 

 2302 13:58:15.986220  EX_ROW_EN[0]    = 0x10

 2303 13:58:15.986300  EX_ROW_EN[1]    = 0x0

 2304 13:58:15.989103  LP4Y_EN      = 0x0

 2305 13:58:15.992726  WORK_FSP     = 0x0

 2306 13:58:15.992804  WL           = 0x4

 2307 13:58:15.995707  RL           = 0x4

 2308 13:58:15.995790  BL           = 0x2

 2309 13:58:15.999147  RPST         = 0x0

 2310 13:58:15.999260  RD_PRE       = 0x0

 2311 13:58:16.002329  WR_PRE       = 0x1

 2312 13:58:16.002418  WR_PST       = 0x0

 2313 13:58:16.005964  DBI_WR       = 0x0

 2314 13:58:16.006055  DBI_RD       = 0x0

 2315 13:58:16.009465  OTF          = 0x1

 2316 13:58:16.012807  =================================== 

 2317 13:58:16.016105  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2318 13:58:16.019217  ==

 2319 13:58:16.022779  Dram Type= 6, Freq= 0, CH_0, rank 0

 2320 13:58:16.025735  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2321 13:58:16.025820  ==

 2322 13:58:16.029335  [Duty_Offset_Calibration]

 2323 13:58:16.029434  	B0:2	B1:0	CA:3

 2324 13:58:16.029528  

 2325 13:58:16.032819  [DutyScan_Calibration_Flow] k_type=0

 2326 13:58:16.041947  

 2327 13:58:16.042030  ==CLK 0==

 2328 13:58:16.045230  Final CLK duty delay cell = 0

 2329 13:58:16.048856  [0] MAX Duty = 5031%(X100), DQS PI = 12

 2330 13:58:16.052284  [0] MIN Duty = 4906%(X100), DQS PI = 54

 2331 13:58:16.052361  [0] AVG Duty = 4968%(X100)

 2332 13:58:16.055282  

 2333 13:58:16.058382  CH0 CLK Duty spec in!! Max-Min= 125%

 2334 13:58:16.061684  [DutyScan_Calibration_Flow] ====Done====

 2335 13:58:16.061760  

 2336 13:58:16.065264  [DutyScan_Calibration_Flow] k_type=1

 2337 13:58:16.080518  

 2338 13:58:16.080607  ==DQS 0 ==

 2339 13:58:16.083701  Final DQS duty delay cell = 0

 2340 13:58:16.087139  [0] MAX Duty = 5062%(X100), DQS PI = 12

 2341 13:58:16.090378  [0] MIN Duty = 4907%(X100), DQS PI = 46

 2342 13:58:16.093925  [0] AVG Duty = 4984%(X100)

 2343 13:58:16.094004  

 2344 13:58:16.094080  ==DQS 1 ==

 2345 13:58:16.097396  Final DQS duty delay cell = -4

 2346 13:58:16.100379  [-4] MAX Duty = 5000%(X100), DQS PI = 36

 2347 13:58:16.103839  [-4] MIN Duty = 4907%(X100), DQS PI = 0

 2348 13:58:16.107184  [-4] AVG Duty = 4953%(X100)

 2349 13:58:16.107263  

 2350 13:58:16.110668  CH0 DQS 0 Duty spec in!! Max-Min= 155%

 2351 13:58:16.110748  

 2352 13:58:16.113623  CH0 DQS 1 Duty spec in!! Max-Min= 93%

 2353 13:58:16.117313  [DutyScan_Calibration_Flow] ====Done====

 2354 13:58:16.117389  

 2355 13:58:16.120314  [DutyScan_Calibration_Flow] k_type=3

 2356 13:58:16.138005  

 2357 13:58:16.138099  ==DQM 0 ==

 2358 13:58:16.141157  Final DQM duty delay cell = 0

 2359 13:58:16.144708  [0] MAX Duty = 5124%(X100), DQS PI = 10

 2360 13:58:16.148278  [0] MIN Duty = 4876%(X100), DQS PI = 48

 2361 13:58:16.151219  [0] AVG Duty = 5000%(X100)

 2362 13:58:16.151323  

 2363 13:58:16.151453  ==DQM 1 ==

 2364 13:58:16.154895  Final DQM duty delay cell = 4

 2365 13:58:16.158604  [4] MAX Duty = 5124%(X100), DQS PI = 2

 2366 13:58:16.161343  [4] MIN Duty = 5031%(X100), DQS PI = 12

 2367 13:58:16.161464  [4] AVG Duty = 5077%(X100)

 2368 13:58:16.164617  

 2369 13:58:16.168027  CH0 DQM 0 Duty spec in!! Max-Min= 248%

 2370 13:58:16.168111  

 2371 13:58:16.171522  CH0 DQM 1 Duty spec in!! Max-Min= 93%

 2372 13:58:16.174550  [DutyScan_Calibration_Flow] ====Done====

 2373 13:58:16.174644  

 2374 13:58:16.177658  [DutyScan_Calibration_Flow] k_type=2

 2375 13:58:16.192859  

 2376 13:58:16.192944  ==DQ 0 ==

 2377 13:58:16.196400  Final DQ duty delay cell = -4

 2378 13:58:16.199683  [-4] MAX Duty = 5031%(X100), DQS PI = 20

 2379 13:58:16.202577  [-4] MIN Duty = 4907%(X100), DQS PI = 42

 2380 13:58:16.206648  [-4] AVG Duty = 4969%(X100)

 2381 13:58:16.206739  

 2382 13:58:16.206813  ==DQ 1 ==

 2383 13:58:16.209745  Final DQ duty delay cell = -4

 2384 13:58:16.212702  [-4] MAX Duty = 5000%(X100), DQS PI = 0

 2385 13:58:16.216251  [-4] MIN Duty = 4876%(X100), DQS PI = 20

 2386 13:58:16.219691  [-4] AVG Duty = 4938%(X100)

 2387 13:58:16.219767  

 2388 13:58:16.222587  CH0 DQ 0 Duty spec in!! Max-Min= 124%

 2389 13:58:16.222667  

 2390 13:58:16.226245  CH0 DQ 1 Duty spec in!! Max-Min= 124%

 2391 13:58:16.229933  [DutyScan_Calibration_Flow] ====Done====

 2392 13:58:16.230051  ==

 2393 13:58:16.232707  Dram Type= 6, Freq= 0, CH_1, rank 0

 2394 13:58:16.236211  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2395 13:58:16.236315  ==

 2396 13:58:16.239327  [Duty_Offset_Calibration]

 2397 13:58:16.239468  	B0:1	B1:-2	CA:0

 2398 13:58:16.239536  

 2399 13:58:16.242651  [DutyScan_Calibration_Flow] k_type=0

 2400 13:58:16.253242  

 2401 13:58:16.253343  ==CLK 0==

 2402 13:58:16.256859  Final CLK duty delay cell = 0

 2403 13:58:16.260308  [0] MAX Duty = 5062%(X100), DQS PI = 30

 2404 13:58:16.263347  [0] MIN Duty = 4876%(X100), DQS PI = 2

 2405 13:58:16.263470  [0] AVG Duty = 4969%(X100)

 2406 13:58:16.263543  

 2407 13:58:16.266898  CH1 CLK Duty spec in!! Max-Min= 186%

 2408 13:58:16.273577  [DutyScan_Calibration_Flow] ====Done====

 2409 13:58:16.273663  

 2410 13:58:16.276860  [DutyScan_Calibration_Flow] k_type=1

 2411 13:58:16.292009  

 2412 13:58:16.292099  ==DQS 0 ==

 2413 13:58:16.295181  Final DQS duty delay cell = -4

 2414 13:58:16.298612  [-4] MAX Duty = 5031%(X100), DQS PI = 24

 2415 13:58:16.301992  [-4] MIN Duty = 4907%(X100), DQS PI = 4

 2416 13:58:16.305488  [-4] AVG Duty = 4969%(X100)

 2417 13:58:16.305581  

 2418 13:58:16.305647  ==DQS 1 ==

 2419 13:58:16.308823  Final DQS duty delay cell = 0

 2420 13:58:16.312102  [0] MAX Duty = 5093%(X100), DQS PI = 0

 2421 13:58:16.315050  [0] MIN Duty = 4876%(X100), DQS PI = 26

 2422 13:58:16.318902  [0] AVG Duty = 4984%(X100)

 2423 13:58:16.318979  

 2424 13:58:16.322092  CH1 DQS 0 Duty spec in!! Max-Min= 124%

 2425 13:58:16.322172  

 2426 13:58:16.325163  CH1 DQS 1 Duty spec in!! Max-Min= 217%

 2427 13:58:16.328827  [DutyScan_Calibration_Flow] ====Done====

 2428 13:58:16.328914  

 2429 13:58:16.331855  [DutyScan_Calibration_Flow] k_type=3

 2430 13:58:16.348392  

 2431 13:58:16.348483  ==DQM 0 ==

 2432 13:58:16.352056  Final DQM duty delay cell = 0

 2433 13:58:16.355503  [0] MAX Duty = 5031%(X100), DQS PI = 24

 2434 13:58:16.358307  [0] MIN Duty = 4876%(X100), DQS PI = 4

 2435 13:58:16.358385  [0] AVG Duty = 4953%(X100)

 2436 13:58:16.361961  

 2437 13:58:16.362044  ==DQM 1 ==

 2438 13:58:16.365076  Final DQM duty delay cell = 0

 2439 13:58:16.368883  [0] MAX Duty = 5031%(X100), DQS PI = 36

 2440 13:58:16.371794  [0] MIN Duty = 4907%(X100), DQS PI = 0

 2441 13:58:16.371875  [0] AVG Duty = 4969%(X100)

 2442 13:58:16.375148  

 2443 13:58:16.378288  CH1 DQM 0 Duty spec in!! Max-Min= 155%

 2444 13:58:16.378369  

 2445 13:58:16.381969  CH1 DQM 1 Duty spec in!! Max-Min= 124%

 2446 13:58:16.385024  [DutyScan_Calibration_Flow] ====Done====

 2447 13:58:16.385116  

 2448 13:58:16.388437  [DutyScan_Calibration_Flow] k_type=2

 2449 13:58:16.404696  

 2450 13:58:16.404782  ==DQ 0 ==

 2451 13:58:16.408543  Final DQ duty delay cell = 0

 2452 13:58:16.411748  [0] MAX Duty = 5093%(X100), DQS PI = 20

 2453 13:58:16.414929  [0] MIN Duty = 4907%(X100), DQS PI = 56

 2454 13:58:16.415027  [0] AVG Duty = 5000%(X100)

 2455 13:58:16.415111  

 2456 13:58:16.417979  ==DQ 1 ==

 2457 13:58:16.421794  Final DQ duty delay cell = 0

 2458 13:58:16.425061  [0] MAX Duty = 5125%(X100), DQS PI = 46

 2459 13:58:16.427948  [0] MIN Duty = 4969%(X100), DQS PI = 26

 2460 13:58:16.428056  [0] AVG Duty = 5047%(X100)

 2461 13:58:16.428149  

 2462 13:58:16.431928  CH1 DQ 0 Duty spec in!! Max-Min= 186%

 2463 13:58:16.432053  

 2464 13:58:16.434809  CH1 DQ 1 Duty spec in!! Max-Min= 156%

 2465 13:58:16.441937  [DutyScan_Calibration_Flow] ====Done====

 2466 13:58:16.445068  nWR fixed to 30

 2467 13:58:16.445152  [ModeRegInit_LP4] CH0 RK0

 2468 13:58:16.448831  [ModeRegInit_LP4] CH0 RK1

 2469 13:58:16.451680  [ModeRegInit_LP4] CH1 RK0

 2470 13:58:16.451788  [ModeRegInit_LP4] CH1 RK1

 2471 13:58:16.455499  match AC timing 7

 2472 13:58:16.458753  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2473 13:58:16.461611  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2474 13:58:16.468566  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2475 13:58:16.472245  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2476 13:58:16.478408  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2477 13:58:16.478517  ==

 2478 13:58:16.482255  Dram Type= 6, Freq= 0, CH_0, rank 0

 2479 13:58:16.485057  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2480 13:58:16.485143  ==

 2481 13:58:16.492187  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2482 13:58:16.495303  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2483 13:58:16.505256  [CA 0] Center 40 (10~71) winsize 62

 2484 13:58:16.508420  [CA 1] Center 39 (9~70) winsize 62

 2485 13:58:16.511445  [CA 2] Center 36 (6~66) winsize 61

 2486 13:58:16.514811  [CA 3] Center 35 (5~66) winsize 62

 2487 13:58:16.518245  [CA 4] Center 34 (4~65) winsize 62

 2488 13:58:16.521513  [CA 5] Center 33 (3~63) winsize 61

 2489 13:58:16.521595  

 2490 13:58:16.524902  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 2491 13:58:16.525010  

 2492 13:58:16.528491  [CATrainingPosCal] consider 1 rank data

 2493 13:58:16.531556  u2DelayCellTimex100 = 270/100 ps

 2494 13:58:16.535244  CA0 delay=40 (10~71),Diff = 7 PI (33 cell)

 2495 13:58:16.538499  CA1 delay=39 (9~70),Diff = 6 PI (28 cell)

 2496 13:58:16.545330  CA2 delay=36 (6~66),Diff = 3 PI (14 cell)

 2497 13:58:16.548426  CA3 delay=35 (5~66),Diff = 2 PI (9 cell)

 2498 13:58:16.551715  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 2499 13:58:16.555146  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 2500 13:58:16.555227  

 2501 13:58:16.558429  CA PerBit enable=1, Macro0, CA PI delay=33

 2502 13:58:16.558536  

 2503 13:58:16.561419  [CBTSetCACLKResult] CA Dly = 33

 2504 13:58:16.561517  CS Dly: 7 (0~38)

 2505 13:58:16.564854  ==

 2506 13:58:16.564935  Dram Type= 6, Freq= 0, CH_0, rank 1

 2507 13:58:16.571632  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2508 13:58:16.571714  ==

 2509 13:58:16.575323  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2510 13:58:16.581682  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35

 2511 13:58:16.591198  [CA 0] Center 40 (10~70) winsize 61

 2512 13:58:16.594220  [CA 1] Center 39 (9~70) winsize 62

 2513 13:58:16.597730  [CA 2] Center 35 (5~66) winsize 62

 2514 13:58:16.601182  [CA 3] Center 35 (5~66) winsize 62

 2515 13:58:16.604711  [CA 4] Center 34 (3~65) winsize 63

 2516 13:58:16.607696  [CA 5] Center 33 (3~64) winsize 62

 2517 13:58:16.607777  

 2518 13:58:16.611146  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2519 13:58:16.611227  

 2520 13:58:16.614776  [CATrainingPosCal] consider 2 rank data

 2521 13:58:16.617615  u2DelayCellTimex100 = 270/100 ps

 2522 13:58:16.621078  CA0 delay=40 (10~70),Diff = 7 PI (33 cell)

 2523 13:58:16.624758  CA1 delay=39 (9~70),Diff = 6 PI (28 cell)

 2524 13:58:16.631384  CA2 delay=36 (6~66),Diff = 3 PI (14 cell)

 2525 13:58:16.634892  CA3 delay=35 (5~66),Diff = 2 PI (9 cell)

 2526 13:58:16.637625  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 2527 13:58:16.641236  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 2528 13:58:16.641317  

 2529 13:58:16.644550  CA PerBit enable=1, Macro0, CA PI delay=33

 2530 13:58:16.644631  

 2531 13:58:16.647565  [CBTSetCACLKResult] CA Dly = 33

 2532 13:58:16.647646  CS Dly: 8 (0~40)

 2533 13:58:16.647711  

 2534 13:58:16.651197  ----->DramcWriteLeveling(PI) begin...

 2535 13:58:16.654629  ==

 2536 13:58:16.657558  Dram Type= 6, Freq= 0, CH_0, rank 0

 2537 13:58:16.660996  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2538 13:58:16.661078  ==

 2539 13:58:16.664548  Write leveling (Byte 0): 31 => 31

 2540 13:58:16.667541  Write leveling (Byte 1): 28 => 28

 2541 13:58:16.670872  DramcWriteLeveling(PI) end<-----

 2542 13:58:16.670953  

 2543 13:58:16.671016  ==

 2544 13:58:16.674197  Dram Type= 6, Freq= 0, CH_0, rank 0

 2545 13:58:16.677807  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2546 13:58:16.677888  ==

 2547 13:58:16.680959  [Gating] SW mode calibration

 2548 13:58:16.687855  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2549 13:58:16.694824  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2550 13:58:16.697926   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2551 13:58:16.700827   0 15  4 | B1->B0 | 2727 3333 | 1 0 | (0 0) (0 0)

 2552 13:58:16.704496   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2553 13:58:16.711308   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2554 13:58:16.714189   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2555 13:58:16.717681   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2556 13:58:16.724997   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2557 13:58:16.727728   0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2558 13:58:16.731033   1  0  0 | B1->B0 | 3030 2a2a | 1 0 | (0 1) (1 0)

 2559 13:58:16.738276   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 2560 13:58:16.741365   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2561 13:58:16.744317   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2562 13:58:16.750827   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2563 13:58:16.754288   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2564 13:58:16.757461   1  0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2565 13:58:16.764611   1  0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)

 2566 13:58:16.767635   1  1  0 | B1->B0 | 2c2c 3838 | 0 0 | (1 1) (1 1)

 2567 13:58:16.770866   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2568 13:58:16.777697   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2569 13:58:16.781145   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2570 13:58:16.784596   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2571 13:58:16.791055   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2572 13:58:16.794280   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2573 13:58:16.797710   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2574 13:58:16.801270   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2575 13:58:16.807886   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2576 13:58:16.811092   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2577 13:58:16.814524   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2578 13:58:16.820975   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2579 13:58:16.824736   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2580 13:58:16.827572   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2581 13:58:16.834585   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2582 13:58:16.837617   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2583 13:58:16.841165   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2584 13:58:16.847737   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2585 13:58:16.851191   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2586 13:58:16.854175   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2587 13:58:16.861207   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2588 13:58:16.864719   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2589 13:58:16.867808   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2590 13:58:16.874342   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2591 13:58:16.877918   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2592 13:58:16.881634  Total UI for P1: 0, mck2ui 16

 2593 13:58:16.884481  best dqsien dly found for B0: ( 1,  3, 30)

 2594 13:58:16.888011   1  4  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2595 13:58:16.890928  Total UI for P1: 0, mck2ui 16

 2596 13:58:16.894647  best dqsien dly found for B1: ( 1,  4,  2)

 2597 13:58:16.897660  best DQS0 dly(MCK, UI, PI) = (1, 3, 30)

 2598 13:58:16.901186  best DQS1 dly(MCK, UI, PI) = (1, 4, 2)

 2599 13:58:16.901269  

 2600 13:58:16.904692  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2601 13:58:16.908056  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)

 2602 13:58:16.911168  [Gating] SW calibration Done

 2603 13:58:16.911266  ==

 2604 13:58:16.914764  Dram Type= 6, Freq= 0, CH_0, rank 0

 2605 13:58:16.921095  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2606 13:58:16.921178  ==

 2607 13:58:16.921243  RX Vref Scan: 0

 2608 13:58:16.921304  

 2609 13:58:16.924767  RX Vref 0 -> 0, step: 1

 2610 13:58:16.924849  

 2611 13:58:16.927943  RX Delay -40 -> 252, step: 8

 2612 13:58:16.931133  iDelay=200, Bit 0, Center 111 (32 ~ 191) 160

 2613 13:58:16.934720  iDelay=200, Bit 1, Center 111 (40 ~ 183) 144

 2614 13:58:16.937568  iDelay=200, Bit 2, Center 115 (40 ~ 191) 152

 2615 13:58:16.941188  iDelay=200, Bit 3, Center 107 (32 ~ 183) 152

 2616 13:58:16.948018  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 2617 13:58:16.951173  iDelay=200, Bit 5, Center 99 (24 ~ 175) 152

 2618 13:58:16.954726  iDelay=200, Bit 6, Center 119 (48 ~ 191) 144

 2619 13:58:16.957654  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 2620 13:58:16.961364  iDelay=200, Bit 8, Center 91 (16 ~ 167) 152

 2621 13:58:16.964319  iDelay=200, Bit 9, Center 87 (8 ~ 167) 160

 2622 13:58:16.970856  iDelay=200, Bit 10, Center 103 (32 ~ 175) 144

 2623 13:58:16.974222  iDelay=200, Bit 11, Center 99 (24 ~ 175) 152

 2624 13:58:16.978047  iDelay=200, Bit 12, Center 107 (32 ~ 183) 152

 2625 13:58:16.980795  iDelay=200, Bit 13, Center 107 (32 ~ 183) 152

 2626 13:58:16.987549  iDelay=200, Bit 14, Center 115 (40 ~ 191) 152

 2627 13:58:16.990952  iDelay=200, Bit 15, Center 111 (40 ~ 183) 144

 2628 13:58:16.991028  ==

 2629 13:58:16.994563  Dram Type= 6, Freq= 0, CH_0, rank 0

 2630 13:58:16.997679  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2631 13:58:16.997761  ==

 2632 13:58:16.997827  DQS Delay:

 2633 13:58:17.001348  DQS0 = 0, DQS1 = 0

 2634 13:58:17.001429  DQM Delay:

 2635 13:58:17.004223  DQM0 = 112, DQM1 = 102

 2636 13:58:17.004333  DQ Delay:

 2637 13:58:17.007504  DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107

 2638 13:58:17.010739  DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123

 2639 13:58:17.014163  DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99

 2640 13:58:17.017641  DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111

 2641 13:58:17.017723  

 2642 13:58:17.017789  

 2643 13:58:17.021112  ==

 2644 13:58:17.024551  Dram Type= 6, Freq= 0, CH_0, rank 0

 2645 13:58:17.027600  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2646 13:58:17.027682  ==

 2647 13:58:17.027747  

 2648 13:58:17.027807  

 2649 13:58:17.030894  	TX Vref Scan disable

 2650 13:58:17.030979   == TX Byte 0 ==

 2651 13:58:17.034152  Update DQ  dly =849 (3 ,2, 17)  DQ  OEN =(2 ,7)

 2652 13:58:17.041010  Update DQM dly =849 (3 ,2, 17)  DQM OEN =(2 ,7)

 2653 13:58:17.041107   == TX Byte 1 ==

 2654 13:58:17.044336  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 2655 13:58:17.051006  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 2656 13:58:17.051087  ==

 2657 13:58:17.054543  Dram Type= 6, Freq= 0, CH_0, rank 0

 2658 13:58:17.057421  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2659 13:58:17.057505  ==

 2660 13:58:17.070155  TX Vref=22, minBit 8, minWin=25, winSum=420

 2661 13:58:17.072926  TX Vref=24, minBit 5, minWin=25, winSum=424

 2662 13:58:17.076526  TX Vref=26, minBit 4, minWin=26, winSum=430

 2663 13:58:17.079577  TX Vref=28, minBit 10, minWin=25, winSum=436

 2664 13:58:17.082989  TX Vref=30, minBit 8, minWin=26, winSum=437

 2665 13:58:17.089845  TX Vref=32, minBit 8, minWin=24, winSum=430

 2666 13:58:17.093294  [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 30

 2667 13:58:17.093375  

 2668 13:58:17.096250  Final TX Range 1 Vref 30

 2669 13:58:17.096359  

 2670 13:58:17.096471  ==

 2671 13:58:17.099518  Dram Type= 6, Freq= 0, CH_0, rank 0

 2672 13:58:17.103018  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2673 13:58:17.103097  ==

 2674 13:58:17.106119  

 2675 13:58:17.106210  

 2676 13:58:17.106286  	TX Vref Scan disable

 2677 13:58:17.109788   == TX Byte 0 ==

 2678 13:58:17.113332  Update DQ  dly =850 (3 ,2, 18)  DQ  OEN =(2 ,7)

 2679 13:58:17.116655  Update DQM dly =850 (3 ,2, 18)  DQM OEN =(2 ,7)

 2680 13:58:17.120028   == TX Byte 1 ==

 2681 13:58:17.122830  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2682 13:58:17.126160  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2683 13:58:17.129518  

 2684 13:58:17.129601  [DATLAT]

 2685 13:58:17.129726  Freq=1200, CH0 RK0

 2686 13:58:17.129856  

 2687 13:58:17.133442  DATLAT Default: 0xd

 2688 13:58:17.133524  0, 0xFFFF, sum = 0

 2689 13:58:17.136214  1, 0xFFFF, sum = 0

 2690 13:58:17.136297  2, 0xFFFF, sum = 0

 2691 13:58:17.139548  3, 0xFFFF, sum = 0

 2692 13:58:17.139631  4, 0xFFFF, sum = 0

 2693 13:58:17.143321  5, 0xFFFF, sum = 0

 2694 13:58:17.146302  6, 0xFFFF, sum = 0

 2695 13:58:17.146385  7, 0xFFFF, sum = 0

 2696 13:58:17.150013  8, 0xFFFF, sum = 0

 2697 13:58:17.150096  9, 0xFFFF, sum = 0

 2698 13:58:17.152963  10, 0xFFFF, sum = 0

 2699 13:58:17.153076  11, 0xFFFF, sum = 0

 2700 13:58:17.156240  12, 0x0, sum = 1

 2701 13:58:17.156324  13, 0x0, sum = 2

 2702 13:58:17.159493  14, 0x0, sum = 3

 2703 13:58:17.159576  15, 0x0, sum = 4

 2704 13:58:17.159692  best_step = 13

 2705 13:58:17.159768  

 2706 13:58:17.162975  ==

 2707 13:58:17.166146  Dram Type= 6, Freq= 0, CH_0, rank 0

 2708 13:58:17.169750  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2709 13:58:17.169833  ==

 2710 13:58:17.169922  RX Vref Scan: 1

 2711 13:58:17.170070  

 2712 13:58:17.172683  Set Vref Range= 32 -> 127

 2713 13:58:17.172764  

 2714 13:58:17.176687  RX Vref 32 -> 127, step: 1

 2715 13:58:17.176769  

 2716 13:58:17.179584  RX Delay -37 -> 252, step: 4

 2717 13:58:17.179683  

 2718 13:58:17.182898  Set Vref, RX VrefLevel [Byte0]: 32

 2719 13:58:17.186662                           [Byte1]: 32

 2720 13:58:17.186743  

 2721 13:58:17.189336  Set Vref, RX VrefLevel [Byte0]: 33

 2722 13:58:17.192831                           [Byte1]: 33

 2723 13:58:17.196338  

 2724 13:58:17.196440  Set Vref, RX VrefLevel [Byte0]: 34

 2725 13:58:17.199332                           [Byte1]: 34

 2726 13:58:17.204232  

 2727 13:58:17.204322  Set Vref, RX VrefLevel [Byte0]: 35

 2728 13:58:17.207645                           [Byte1]: 35

 2729 13:58:17.212252  

 2730 13:58:17.212328  Set Vref, RX VrefLevel [Byte0]: 36

 2731 13:58:17.215773                           [Byte1]: 36

 2732 13:58:17.220019  

 2733 13:58:17.220102  Set Vref, RX VrefLevel [Byte0]: 37

 2734 13:58:17.223496                           [Byte1]: 37

 2735 13:58:17.228082  

 2736 13:58:17.228165  Set Vref, RX VrefLevel [Byte0]: 38

 2737 13:58:17.231488                           [Byte1]: 38

 2738 13:58:17.236770  

 2739 13:58:17.236871  Set Vref, RX VrefLevel [Byte0]: 39

 2740 13:58:17.239713                           [Byte1]: 39

 2741 13:58:17.244162  

 2742 13:58:17.244242  Set Vref, RX VrefLevel [Byte0]: 40

 2743 13:58:17.247362                           [Byte1]: 40

 2744 13:58:17.252526  

 2745 13:58:17.252614  Set Vref, RX VrefLevel [Byte0]: 41

 2746 13:58:17.255286                           [Byte1]: 41

 2747 13:58:17.260195  

 2748 13:58:17.260322  Set Vref, RX VrefLevel [Byte0]: 42

 2749 13:58:17.263481                           [Byte1]: 42

 2750 13:58:17.267956  

 2751 13:58:17.268043  Set Vref, RX VrefLevel [Byte0]: 43

 2752 13:58:17.271558                           [Byte1]: 43

 2753 13:58:17.276651  

 2754 13:58:17.276734  Set Vref, RX VrefLevel [Byte0]: 44

 2755 13:58:17.279251                           [Byte1]: 44

 2756 13:58:17.284267  

 2757 13:58:17.284346  Set Vref, RX VrefLevel [Byte0]: 45

 2758 13:58:17.287667                           [Byte1]: 45

 2759 13:58:17.292289  

 2760 13:58:17.292368  Set Vref, RX VrefLevel [Byte0]: 46

 2761 13:58:17.295422                           [Byte1]: 46

 2762 13:58:17.300130  

 2763 13:58:17.300217  Set Vref, RX VrefLevel [Byte0]: 47

 2764 13:58:17.303612                           [Byte1]: 47

 2765 13:58:17.308446  

 2766 13:58:17.308529  Set Vref, RX VrefLevel [Byte0]: 48

 2767 13:58:17.311611                           [Byte1]: 48

 2768 13:58:17.316219  

 2769 13:58:17.316301  Set Vref, RX VrefLevel [Byte0]: 49

 2770 13:58:17.319932                           [Byte1]: 49

 2771 13:58:17.324010  

 2772 13:58:17.324091  Set Vref, RX VrefLevel [Byte0]: 50

 2773 13:58:17.327817                           [Byte1]: 50

 2774 13:58:17.332211  

 2775 13:58:17.332292  Set Vref, RX VrefLevel [Byte0]: 51

 2776 13:58:17.335465                           [Byte1]: 51

 2777 13:58:17.340458  

 2778 13:58:17.340540  Set Vref, RX VrefLevel [Byte0]: 52

 2779 13:58:17.343798                           [Byte1]: 52

 2780 13:58:17.348127  

 2781 13:58:17.348209  Set Vref, RX VrefLevel [Byte0]: 53

 2782 13:58:17.351554                           [Byte1]: 53

 2783 13:58:17.356735  

 2784 13:58:17.356816  Set Vref, RX VrefLevel [Byte0]: 54

 2785 13:58:17.359573                           [Byte1]: 54

 2786 13:58:17.364266  

 2787 13:58:17.364347  Set Vref, RX VrefLevel [Byte0]: 55

 2788 13:58:17.367844                           [Byte1]: 55

 2789 13:58:17.372149  

 2790 13:58:17.372250  Set Vref, RX VrefLevel [Byte0]: 56

 2791 13:58:17.375338                           [Byte1]: 56

 2792 13:58:17.380255  

 2793 13:58:17.380367  Set Vref, RX VrefLevel [Byte0]: 57

 2794 13:58:17.383642                           [Byte1]: 57

 2795 13:58:17.388595  

 2796 13:58:17.388675  Set Vref, RX VrefLevel [Byte0]: 58

 2797 13:58:17.391334                           [Byte1]: 58

 2798 13:58:17.396039  

 2799 13:58:17.396121  Set Vref, RX VrefLevel [Byte0]: 59

 2800 13:58:17.399554                           [Byte1]: 59

 2801 13:58:17.404274  

 2802 13:58:17.404355  Set Vref, RX VrefLevel [Byte0]: 60

 2803 13:58:17.407720                           [Byte1]: 60

 2804 13:58:17.412061  

 2805 13:58:17.412140  Set Vref, RX VrefLevel [Byte0]: 61

 2806 13:58:17.415652                           [Byte1]: 61

 2807 13:58:17.420350  

 2808 13:58:17.420432  Set Vref, RX VrefLevel [Byte0]: 62

 2809 13:58:17.423799                           [Byte1]: 62

 2810 13:58:17.428567  

 2811 13:58:17.428646  Set Vref, RX VrefLevel [Byte0]: 63

 2812 13:58:17.431673                           [Byte1]: 63

 2813 13:58:17.436015  

 2814 13:58:17.436097  Set Vref, RX VrefLevel [Byte0]: 64

 2815 13:58:17.439454                           [Byte1]: 64

 2816 13:58:17.444376  

 2817 13:58:17.444454  Set Vref, RX VrefLevel [Byte0]: 65

 2818 13:58:17.447754                           [Byte1]: 65

 2819 13:58:17.452301  

 2820 13:58:17.452396  Set Vref, RX VrefLevel [Byte0]: 66

 2821 13:58:17.458495                           [Byte1]: 66

 2822 13:58:17.458576  

 2823 13:58:17.462240  Set Vref, RX VrefLevel [Byte0]: 67

 2824 13:58:17.465170                           [Byte1]: 67

 2825 13:58:17.465244  

 2826 13:58:17.468804  Set Vref, RX VrefLevel [Byte0]: 68

 2827 13:58:17.471658                           [Byte1]: 68

 2828 13:58:17.476056  

 2829 13:58:17.476132  Set Vref, RX VrefLevel [Byte0]: 69

 2830 13:58:17.479658                           [Byte1]: 69

 2831 13:58:17.484130  

 2832 13:58:17.484210  Set Vref, RX VrefLevel [Byte0]: 70

 2833 13:58:17.487849                           [Byte1]: 70

 2834 13:58:17.492058  

 2835 13:58:17.492141  Set Vref, RX VrefLevel [Byte0]: 71

 2836 13:58:17.495662                           [Byte1]: 71

 2837 13:58:17.500070  

 2838 13:58:17.500188  Set Vref, RX VrefLevel [Byte0]: 72

 2839 13:58:17.503552                           [Byte1]: 72

 2840 13:58:17.508462  

 2841 13:58:17.508550  Set Vref, RX VrefLevel [Byte0]: 73

 2842 13:58:17.511461                           [Byte1]: 73

 2843 13:58:17.516066  

 2844 13:58:17.516148  Set Vref, RX VrefLevel [Byte0]: 74

 2845 13:58:17.519585                           [Byte1]: 74

 2846 13:58:17.524092  

 2847 13:58:17.524176  Final RX Vref Byte 0 = 61 to rank0

 2848 13:58:17.527656  Final RX Vref Byte 1 = 49 to rank0

 2849 13:58:17.531181  Final RX Vref Byte 0 = 61 to rank1

 2850 13:58:17.534355  Final RX Vref Byte 1 = 49 to rank1==

 2851 13:58:17.537678  Dram Type= 6, Freq= 0, CH_0, rank 0

 2852 13:58:17.544010  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2853 13:58:17.544090  ==

 2854 13:58:17.544167  DQS Delay:

 2855 13:58:17.544230  DQS0 = 0, DQS1 = 0

 2856 13:58:17.547553  DQM Delay:

 2857 13:58:17.547625  DQM0 = 111, DQM1 = 100

 2858 13:58:17.550971  DQ Delay:

 2859 13:58:17.554534  DQ0 =108, DQ1 =110, DQ2 =112, DQ3 =108

 2860 13:58:17.557929  DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120

 2861 13:58:17.560725  DQ8 =92, DQ9 =84, DQ10 =100, DQ11 =94

 2862 13:58:17.564321  DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110

 2863 13:58:17.564394  

 2864 13:58:17.564463  

 2865 13:58:17.570766  [DQSOSCAuto] RK0, (LSB)MR18= 0xff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps

 2866 13:58:17.574200  CH0 RK0: MR19=403, MR18=FF

 2867 13:58:17.580747  CH0_RK0: MR19=0x403, MR18=0xFF, DQSOSC=410, MR23=63, INC=39, DEC=26

 2868 13:58:17.580830  

 2869 13:58:17.584165  ----->DramcWriteLeveling(PI) begin...

 2870 13:58:17.584248  ==

 2871 13:58:17.587645  Dram Type= 6, Freq= 0, CH_0, rank 1

 2872 13:58:17.590531  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2873 13:58:17.590613  ==

 2874 13:58:17.593875  Write leveling (Byte 0): 32 => 32

 2875 13:58:17.597266  Write leveling (Byte 1): 30 => 30

 2876 13:58:17.600700  DramcWriteLeveling(PI) end<-----

 2877 13:58:17.600781  

 2878 13:58:17.600845  ==

 2879 13:58:17.604182  Dram Type= 6, Freq= 0, CH_0, rank 1

 2880 13:58:17.607316  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2881 13:58:17.610675  ==

 2882 13:58:17.610757  [Gating] SW mode calibration

 2883 13:58:17.617149  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2884 13:58:17.623741  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2885 13:58:17.627305   0 15  0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)

 2886 13:58:17.634004   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2887 13:58:17.637802   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2888 13:58:17.640712   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2889 13:58:17.647013   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2890 13:58:17.650450   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 2891 13:58:17.653949   0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)

 2892 13:58:17.660440   0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)

 2893 13:58:17.663786   1  0  0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)

 2894 13:58:17.667004   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2895 13:58:17.674110   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2896 13:58:17.677462   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2897 13:58:17.680303   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2898 13:58:17.683890   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2899 13:58:17.690468   1  0 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)

 2900 13:58:17.693961   1  0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)

 2901 13:58:17.697035   1  1  0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)

 2902 13:58:17.703880   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2903 13:58:17.706998   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2904 13:58:17.710469   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2905 13:58:17.717037   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2906 13:58:17.720361   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2907 13:58:17.723654   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2908 13:58:17.730793   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2909 13:58:17.734034   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2910 13:58:17.737473   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2911 13:58:17.744333   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2912 13:58:17.747541   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2913 13:58:17.750526   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2914 13:58:17.757054   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2915 13:58:17.760526   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2916 13:58:17.764224   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2917 13:58:17.770473   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2918 13:58:17.774032   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2919 13:58:17.777342   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2920 13:58:17.780414   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2921 13:58:17.787573   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2922 13:58:17.790723   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2923 13:58:17.794351   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2924 13:58:17.800687   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 2925 13:58:17.800799  Total UI for P1: 0, mck2ui 16

 2926 13:58:17.807480  best dqsien dly found for B0: ( 1,  3, 24)

 2927 13:58:17.810719   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2928 13:58:17.814314  Total UI for P1: 0, mck2ui 16

 2929 13:58:17.817716  best dqsien dly found for B1: ( 1,  3, 30)

 2930 13:58:17.820635  best DQS0 dly(MCK, UI, PI) = (1, 3, 24)

 2931 13:58:17.824331  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 2932 13:58:17.824412  

 2933 13:58:17.827731  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)

 2934 13:58:17.831089  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2935 13:58:17.834499  [Gating] SW calibration Done

 2936 13:58:17.834581  ==

 2937 13:58:17.837519  Dram Type= 6, Freq= 0, CH_0, rank 1

 2938 13:58:17.840866  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2939 13:58:17.840948  ==

 2940 13:58:17.844326  RX Vref Scan: 0

 2941 13:58:17.844407  

 2942 13:58:17.847295  RX Vref 0 -> 0, step: 1

 2943 13:58:17.847403  

 2944 13:58:17.847483  RX Delay -40 -> 252, step: 8

 2945 13:58:17.854571  iDelay=200, Bit 0, Center 111 (40 ~ 183) 144

 2946 13:58:17.857550  iDelay=200, Bit 1, Center 111 (32 ~ 191) 160

 2947 13:58:17.861034  iDelay=200, Bit 2, Center 111 (40 ~ 183) 144

 2948 13:58:17.864561  iDelay=200, Bit 3, Center 107 (32 ~ 183) 152

 2949 13:58:17.867411  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 2950 13:58:17.874296  iDelay=200, Bit 5, Center 99 (32 ~ 167) 136

 2951 13:58:17.877605  iDelay=200, Bit 6, Center 119 (40 ~ 199) 160

 2952 13:58:17.880871  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 2953 13:58:17.884166  iDelay=200, Bit 8, Center 91 (16 ~ 167) 152

 2954 13:58:17.887891  iDelay=200, Bit 9, Center 83 (8 ~ 159) 152

 2955 13:58:17.891209  iDelay=200, Bit 10, Center 103 (32 ~ 175) 144

 2956 13:58:17.897519  iDelay=200, Bit 11, Center 95 (24 ~ 167) 144

 2957 13:58:17.901294  iDelay=200, Bit 12, Center 107 (32 ~ 183) 152

 2958 13:58:17.904138  iDelay=200, Bit 13, Center 107 (32 ~ 183) 152

 2959 13:58:17.907647  iDelay=200, Bit 14, Center 111 (40 ~ 183) 144

 2960 13:58:17.914499  iDelay=200, Bit 15, Center 107 (32 ~ 183) 152

 2961 13:58:17.914582  ==

 2962 13:58:17.917558  Dram Type= 6, Freq= 0, CH_0, rank 1

 2963 13:58:17.921112  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2964 13:58:17.921194  ==

 2965 13:58:17.921259  DQS Delay:

 2966 13:58:17.923879  DQS0 = 0, DQS1 = 0

 2967 13:58:17.923961  DQM Delay:

 2968 13:58:17.927527  DQM0 = 112, DQM1 = 100

 2969 13:58:17.927609  DQ Delay:

 2970 13:58:17.930980  DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107

 2971 13:58:17.934365  DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123

 2972 13:58:17.937531  DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95

 2973 13:58:17.940846  DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =107

 2974 13:58:17.940958  

 2975 13:58:17.941049  

 2976 13:58:17.941112  ==

 2977 13:58:17.943934  Dram Type= 6, Freq= 0, CH_0, rank 1

 2978 13:58:17.950947  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2979 13:58:17.951029  ==

 2980 13:58:17.951093  

 2981 13:58:17.951154  

 2982 13:58:17.951212  	TX Vref Scan disable

 2983 13:58:17.954462   == TX Byte 0 ==

 2984 13:58:17.957644  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2985 13:58:17.964116  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2986 13:58:17.964199   == TX Byte 1 ==

 2987 13:58:17.967677  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2988 13:58:17.974164  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2989 13:58:17.974245  ==

 2990 13:58:17.977364  Dram Type= 6, Freq= 0, CH_0, rank 1

 2991 13:58:17.980748  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2992 13:58:17.980858  ==

 2993 13:58:17.992346  TX Vref=22, minBit 1, minWin=26, winSum=425

 2994 13:58:17.995742  TX Vref=24, minBit 1, minWin=26, winSum=430

 2995 13:58:17.999053  TX Vref=26, minBit 11, minWin=26, winSum=433

 2996 13:58:18.002309  TX Vref=28, minBit 1, minWin=27, winSum=441

 2997 13:58:18.005696  TX Vref=30, minBit 10, minWin=26, winSum=443

 2998 13:58:18.012230  TX Vref=32, minBit 8, minWin=26, winSum=441

 2999 13:58:18.015828  [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 28

 3000 13:58:18.015910  

 3001 13:58:18.019251  Final TX Range 1 Vref 28

 3002 13:58:18.019362  

 3003 13:58:18.019504  ==

 3004 13:58:18.022149  Dram Type= 6, Freq= 0, CH_0, rank 1

 3005 13:58:18.025522  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3006 13:58:18.025635  ==

 3007 13:58:18.029143  

 3008 13:58:18.029223  

 3009 13:58:18.029288  	TX Vref Scan disable

 3010 13:58:18.032510   == TX Byte 0 ==

 3011 13:58:18.035420  Update DQ  dly =850 (3 ,2, 18)  DQ  OEN =(2 ,7)

 3012 13:58:18.038924  Update DQM dly =850 (3 ,2, 18)  DQM OEN =(2 ,7)

 3013 13:58:18.042405   == TX Byte 1 ==

 3014 13:58:18.045268  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3015 13:58:18.052391  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3016 13:58:18.052473  

 3017 13:58:18.052538  [DATLAT]

 3018 13:58:18.052598  Freq=1200, CH0 RK1

 3019 13:58:18.052656  

 3020 13:58:18.055309  DATLAT Default: 0xd

 3021 13:58:18.055427  0, 0xFFFF, sum = 0

 3022 13:58:18.058801  1, 0xFFFF, sum = 0

 3023 13:58:18.058884  2, 0xFFFF, sum = 0

 3024 13:58:18.062187  3, 0xFFFF, sum = 0

 3025 13:58:18.065843  4, 0xFFFF, sum = 0

 3026 13:58:18.065926  5, 0xFFFF, sum = 0

 3027 13:58:18.068675  6, 0xFFFF, sum = 0

 3028 13:58:18.068758  7, 0xFFFF, sum = 0

 3029 13:58:18.072221  8, 0xFFFF, sum = 0

 3030 13:58:18.072304  9, 0xFFFF, sum = 0

 3031 13:58:18.075543  10, 0xFFFF, sum = 0

 3032 13:58:18.075627  11, 0xFFFF, sum = 0

 3033 13:58:18.079078  12, 0x0, sum = 1

 3034 13:58:18.079161  13, 0x0, sum = 2

 3035 13:58:18.082172  14, 0x0, sum = 3

 3036 13:58:18.082255  15, 0x0, sum = 4

 3037 13:58:18.082322  best_step = 13

 3038 13:58:18.082382  

 3039 13:58:18.085690  ==

 3040 13:58:18.088906  Dram Type= 6, Freq= 0, CH_0, rank 1

 3041 13:58:18.092334  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3042 13:58:18.092411  ==

 3043 13:58:18.092490  RX Vref Scan: 0

 3044 13:58:18.092552  

 3045 13:58:18.095311  RX Vref 0 -> 0, step: 1

 3046 13:58:18.095414  

 3047 13:58:18.098805  RX Delay -37 -> 252, step: 4

 3048 13:58:18.101996  iDelay=195, Bit 0, Center 108 (39 ~ 178) 140

 3049 13:58:18.108648  iDelay=195, Bit 1, Center 110 (39 ~ 182) 144

 3050 13:58:18.112124  iDelay=195, Bit 2, Center 108 (39 ~ 178) 140

 3051 13:58:18.115387  iDelay=195, Bit 3, Center 108 (39 ~ 178) 140

 3052 13:58:18.118609  iDelay=195, Bit 4, Center 112 (43 ~ 182) 140

 3053 13:58:18.122209  iDelay=195, Bit 5, Center 100 (35 ~ 166) 132

 3054 13:58:18.128637  iDelay=195, Bit 6, Center 120 (47 ~ 194) 148

 3055 13:58:18.131970  iDelay=195, Bit 7, Center 120 (47 ~ 194) 148

 3056 13:58:18.135388  iDelay=195, Bit 8, Center 90 (19 ~ 162) 144

 3057 13:58:18.138725  iDelay=195, Bit 9, Center 82 (11 ~ 154) 144

 3058 13:58:18.142054  iDelay=195, Bit 10, Center 102 (31 ~ 174) 144

 3059 13:58:18.145212  iDelay=195, Bit 11, Center 92 (23 ~ 162) 140

 3060 13:58:18.152168  iDelay=195, Bit 12, Center 108 (39 ~ 178) 140

 3061 13:58:18.155816  iDelay=195, Bit 13, Center 106 (35 ~ 178) 144

 3062 13:58:18.158742  iDelay=195, Bit 14, Center 114 (47 ~ 182) 136

 3063 13:58:18.162133  iDelay=195, Bit 15, Center 108 (39 ~ 178) 140

 3064 13:58:18.162209  ==

 3065 13:58:18.165529  Dram Type= 6, Freq= 0, CH_0, rank 1

 3066 13:58:18.171966  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3067 13:58:18.172047  ==

 3068 13:58:18.172115  DQS Delay:

 3069 13:58:18.175573  DQS0 = 0, DQS1 = 0

 3070 13:58:18.175647  DQM Delay:

 3071 13:58:18.175710  DQM0 = 110, DQM1 = 100

 3072 13:58:18.178614  DQ Delay:

 3073 13:58:18.182162  DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108

 3074 13:58:18.185131  DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120

 3075 13:58:18.188865  DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =92

 3076 13:58:18.192114  DQ12 =108, DQ13 =106, DQ14 =114, DQ15 =108

 3077 13:58:18.192217  

 3078 13:58:18.192312  

 3079 13:58:18.201877  [DQSOSCAuto] RK1, (LSB)MR18= 0x17fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps

 3080 13:58:18.201956  CH0 RK1: MR19=403, MR18=17FE

 3081 13:58:18.208684  CH0_RK1: MR19=0x403, MR18=0x17FE, DQSOSC=401, MR23=63, INC=40, DEC=27

 3082 13:58:18.212213  [RxdqsGatingPostProcess] freq 1200

 3083 13:58:18.218784  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3084 13:58:18.222118  best DQS0 dly(2T, 0.5T) = (0, 11)

 3085 13:58:18.225439  best DQS1 dly(2T, 0.5T) = (0, 12)

 3086 13:58:18.228801  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3087 13:58:18.231922  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3088 13:58:18.232021  best DQS0 dly(2T, 0.5T) = (0, 11)

 3089 13:58:18.235480  best DQS1 dly(2T, 0.5T) = (0, 11)

 3090 13:58:18.239042  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3091 13:58:18.241821  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3092 13:58:18.245048  Pre-setting of DQS Precalculation

 3093 13:58:18.252091  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3094 13:58:18.252194  ==

 3095 13:58:18.255250  Dram Type= 6, Freq= 0, CH_1, rank 0

 3096 13:58:18.258583  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3097 13:58:18.258664  ==

 3098 13:58:18.265577  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3099 13:58:18.268869  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3100 13:58:18.278652  [CA 0] Center 37 (7~67) winsize 61

 3101 13:58:18.282046  [CA 1] Center 37 (7~68) winsize 62

 3102 13:58:18.285737  [CA 2] Center 34 (4~64) winsize 61

 3103 13:58:18.288705  [CA 3] Center 34 (4~64) winsize 61

 3104 13:58:18.292024  [CA 4] Center 34 (4~64) winsize 61

 3105 13:58:18.295148  [CA 5] Center 33 (3~63) winsize 61

 3106 13:58:18.295250  

 3107 13:58:18.298416  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3108 13:58:18.298492  

 3109 13:58:18.301939  [CATrainingPosCal] consider 1 rank data

 3110 13:58:18.305531  u2DelayCellTimex100 = 270/100 ps

 3111 13:58:18.308465  CA0 delay=37 (7~67),Diff = 4 PI (19 cell)

 3112 13:58:18.312024  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3113 13:58:18.318868  CA2 delay=34 (4~64),Diff = 1 PI (4 cell)

 3114 13:58:18.321902  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3115 13:58:18.325290  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3116 13:58:18.328264  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 3117 13:58:18.328338  

 3118 13:58:18.332041  CA PerBit enable=1, Macro0, CA PI delay=33

 3119 13:58:18.332118  

 3120 13:58:18.335017  [CBTSetCACLKResult] CA Dly = 33

 3121 13:58:18.335088  CS Dly: 6 (0~37)

 3122 13:58:18.335150  ==

 3123 13:58:18.338678  Dram Type= 6, Freq= 0, CH_1, rank 1

 3124 13:58:18.345330  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3125 13:58:18.345411  ==

 3126 13:58:18.348783  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3127 13:58:18.355212  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35

 3128 13:58:18.363964  [CA 0] Center 38 (8~68) winsize 61

 3129 13:58:18.367187  [CA 1] Center 37 (7~68) winsize 62

 3130 13:58:18.370972  [CA 2] Center 34 (4~65) winsize 62

 3131 13:58:18.374215  [CA 3] Center 33 (3~64) winsize 62

 3132 13:58:18.377641  [CA 4] Center 34 (4~65) winsize 62

 3133 13:58:18.380602  [CA 5] Center 32 (2~63) winsize 62

 3134 13:58:18.380678  

 3135 13:58:18.384057  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3136 13:58:18.384134  

 3137 13:58:18.387584  [CATrainingPosCal] consider 2 rank data

 3138 13:58:18.390665  u2DelayCellTimex100 = 270/100 ps

 3139 13:58:18.394224  CA0 delay=37 (8~67),Diff = 4 PI (19 cell)

 3140 13:58:18.397281  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3141 13:58:18.403968  CA2 delay=34 (4~64),Diff = 1 PI (4 cell)

 3142 13:58:18.407237  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3143 13:58:18.410656  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3144 13:58:18.414041  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 3145 13:58:18.414116  

 3146 13:58:18.417730  CA PerBit enable=1, Macro0, CA PI delay=33

 3147 13:58:18.417803  

 3148 13:58:18.420496  [CBTSetCACLKResult] CA Dly = 33

 3149 13:58:18.420568  CS Dly: 7 (0~40)

 3150 13:58:18.420629  

 3151 13:58:18.424120  ----->DramcWriteLeveling(PI) begin...

 3152 13:58:18.427787  ==

 3153 13:58:18.427880  Dram Type= 6, Freq= 0, CH_1, rank 0

 3154 13:58:18.434116  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3155 13:58:18.434200  ==

 3156 13:58:18.437350  Write leveling (Byte 0): 26 => 26

 3157 13:58:18.440673  Write leveling (Byte 1): 28 => 28

 3158 13:58:18.440752  DramcWriteLeveling(PI) end<-----

 3159 13:58:18.444254  

 3160 13:58:18.444341  ==

 3161 13:58:18.447326  Dram Type= 6, Freq= 0, CH_1, rank 0

 3162 13:58:18.451223  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3163 13:58:18.451305  ==

 3164 13:58:18.454328  [Gating] SW mode calibration

 3165 13:58:18.460635  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3166 13:58:18.464459  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3167 13:58:18.470841   0 15  0 | B1->B0 | 2c2c 2626 | 0 1 | (0 0) (1 1)

 3168 13:58:18.474372   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3169 13:58:18.477710   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3170 13:58:18.483967   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3171 13:58:18.487629   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3172 13:58:18.491076   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3173 13:58:18.497428   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3174 13:58:18.501071   0 15 28 | B1->B0 | 2c2c 2b2b | 0 0 | (0 0) (1 0)

 3175 13:58:18.503947   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3176 13:58:18.510948   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3177 13:58:18.513864   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3178 13:58:18.517615   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3179 13:58:18.524122   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3180 13:58:18.527382   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3181 13:58:18.531017   1  0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 3182 13:58:18.537280   1  0 28 | B1->B0 | 3f3f 3b3b | 0 0 | (0 0) (0 0)

 3183 13:58:18.540880   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3184 13:58:18.544130   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3185 13:58:18.547317   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3186 13:58:18.554099   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3187 13:58:18.557623   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3188 13:58:18.560675   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3189 13:58:18.567243   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3190 13:58:18.570620   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3191 13:58:18.574126   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3192 13:58:18.580545   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3193 13:58:18.584145   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3194 13:58:18.587206   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3195 13:58:18.593837   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3196 13:58:18.597509   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3197 13:58:18.600850   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3198 13:58:18.607450   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3199 13:58:18.610995   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3200 13:58:18.613888   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3201 13:58:18.620843   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3202 13:58:18.624259   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3203 13:58:18.627622   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3204 13:58:18.634168   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3205 13:58:18.637841   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3206 13:58:18.640827   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3207 13:58:18.647243   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 3208 13:58:18.647323  Total UI for P1: 0, mck2ui 16

 3209 13:58:18.650436  best dqsien dly found for B0: ( 1,  3, 28)

 3210 13:58:18.657587   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3211 13:58:18.660433  Total UI for P1: 0, mck2ui 16

 3212 13:58:18.664116  best dqsien dly found for B1: ( 1,  3, 30)

 3213 13:58:18.667099  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 3214 13:58:18.670603  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 3215 13:58:18.670680  

 3216 13:58:18.673910  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 3217 13:58:18.677110  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 3218 13:58:18.680512  [Gating] SW calibration Done

 3219 13:58:18.680595  ==

 3220 13:58:18.683962  Dram Type= 6, Freq= 0, CH_1, rank 0

 3221 13:58:18.687311  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3222 13:58:18.687430  ==

 3223 13:58:18.690872  RX Vref Scan: 0

 3224 13:58:18.690947  

 3225 13:58:18.691009  RX Vref 0 -> 0, step: 1

 3226 13:58:18.693782  

 3227 13:58:18.693866  RX Delay -40 -> 252, step: 8

 3228 13:58:18.700962  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 3229 13:58:18.703699  iDelay=200, Bit 1, Center 107 (32 ~ 183) 152

 3230 13:58:18.707306  iDelay=200, Bit 2, Center 103 (32 ~ 175) 144

 3231 13:58:18.710442  iDelay=200, Bit 3, Center 115 (40 ~ 191) 152

 3232 13:58:18.713926  iDelay=200, Bit 4, Center 111 (40 ~ 183) 144

 3233 13:58:18.717666  iDelay=200, Bit 5, Center 123 (48 ~ 199) 152

 3234 13:58:18.724088  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 3235 13:58:18.727496  iDelay=200, Bit 7, Center 111 (40 ~ 183) 144

 3236 13:58:18.731313  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 3237 13:58:18.733863  iDelay=200, Bit 9, Center 99 (32 ~ 167) 136

 3238 13:58:18.737540  iDelay=200, Bit 10, Center 103 (32 ~ 175) 144

 3239 13:58:18.744261  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 3240 13:58:18.747865  iDelay=200, Bit 12, Center 115 (40 ~ 191) 152

 3241 13:58:18.750945  iDelay=200, Bit 13, Center 115 (40 ~ 191) 152

 3242 13:58:18.754322  iDelay=200, Bit 14, Center 111 (40 ~ 183) 144

 3243 13:58:18.757732  iDelay=200, Bit 15, Center 111 (40 ~ 183) 144

 3244 13:58:18.760870  ==

 3245 13:58:18.760958  Dram Type= 6, Freq= 0, CH_1, rank 0

 3246 13:58:18.767646  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3247 13:58:18.767725  ==

 3248 13:58:18.767800  DQS Delay:

 3249 13:58:18.771261  DQS0 = 0, DQS1 = 0

 3250 13:58:18.771335  DQM Delay:

 3251 13:58:18.774082  DQM0 = 114, DQM1 = 106

 3252 13:58:18.774165  DQ Delay:

 3253 13:58:18.777728  DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =115

 3254 13:58:18.780647  DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111

 3255 13:58:18.784488  DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103

 3256 13:58:18.787316  DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111

 3257 13:58:18.787448  

 3258 13:58:18.787513  

 3259 13:58:18.787573  ==

 3260 13:58:18.790730  Dram Type= 6, Freq= 0, CH_1, rank 0

 3261 13:58:18.797810  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3262 13:58:18.797891  ==

 3263 13:58:18.797960  

 3264 13:58:18.798021  

 3265 13:58:18.798080  	TX Vref Scan disable

 3266 13:58:18.800728   == TX Byte 0 ==

 3267 13:58:18.804238  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3268 13:58:18.807226  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3269 13:58:18.810899   == TX Byte 1 ==

 3270 13:58:18.813890  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3271 13:58:18.817734  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3272 13:58:18.820691  ==

 3273 13:58:18.823940  Dram Type= 6, Freq= 0, CH_1, rank 0

 3274 13:58:18.827256  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3275 13:58:18.827363  ==

 3276 13:58:18.839046  TX Vref=22, minBit 10, minWin=24, winSum=407

 3277 13:58:18.842276  TX Vref=24, minBit 10, minWin=24, winSum=412

 3278 13:58:18.845480  TX Vref=26, minBit 9, minWin=25, winSum=420

 3279 13:58:18.848641  TX Vref=28, minBit 9, minWin=25, winSum=423

 3280 13:58:18.852406  TX Vref=30, minBit 9, minWin=24, winSum=423

 3281 13:58:18.858766  TX Vref=32, minBit 9, minWin=25, winSum=423

 3282 13:58:18.862196  [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 28

 3283 13:58:18.862270  

 3284 13:58:18.865482  Final TX Range 1 Vref 28

 3285 13:58:18.865556  

 3286 13:58:18.865618  ==

 3287 13:58:18.868728  Dram Type= 6, Freq= 0, CH_1, rank 0

 3288 13:58:18.872007  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3289 13:58:18.872084  ==

 3290 13:58:18.874817  

 3291 13:58:18.874890  

 3292 13:58:18.874952  	TX Vref Scan disable

 3293 13:58:18.878395   == TX Byte 0 ==

 3294 13:58:18.881766  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3295 13:58:18.885487  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3296 13:58:18.888227   == TX Byte 1 ==

 3297 13:58:18.892073  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3298 13:58:18.895081  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3299 13:58:18.898420  

 3300 13:58:18.898496  [DATLAT]

 3301 13:58:18.898588  Freq=1200, CH1 RK0

 3302 13:58:18.898679  

 3303 13:58:18.901623  DATLAT Default: 0xd

 3304 13:58:18.901694  0, 0xFFFF, sum = 0

 3305 13:58:18.905115  1, 0xFFFF, sum = 0

 3306 13:58:18.905191  2, 0xFFFF, sum = 0

 3307 13:58:18.908813  3, 0xFFFF, sum = 0

 3308 13:58:18.908886  4, 0xFFFF, sum = 0

 3309 13:58:18.911939  5, 0xFFFF, sum = 0

 3310 13:58:18.912013  6, 0xFFFF, sum = 0

 3311 13:58:18.915442  7, 0xFFFF, sum = 0

 3312 13:58:18.918435  8, 0xFFFF, sum = 0

 3313 13:58:18.918506  9, 0xFFFF, sum = 0

 3314 13:58:18.922025  10, 0xFFFF, sum = 0

 3315 13:58:18.922096  11, 0xFFFF, sum = 0

 3316 13:58:18.925334  12, 0x0, sum = 1

 3317 13:58:18.925414  13, 0x0, sum = 2

 3318 13:58:18.928431  14, 0x0, sum = 3

 3319 13:58:18.928505  15, 0x0, sum = 4

 3320 13:58:18.928566  best_step = 13

 3321 13:58:18.928626  

 3322 13:58:18.932130  ==

 3323 13:58:18.935538  Dram Type= 6, Freq= 0, CH_1, rank 0

 3324 13:58:18.938610  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3325 13:58:18.938697  ==

 3326 13:58:18.938793  RX Vref Scan: 1

 3327 13:58:18.938896  

 3328 13:58:18.942051  Set Vref Range= 32 -> 127

 3329 13:58:18.942121  

 3330 13:58:18.945053  RX Vref 32 -> 127, step: 1

 3331 13:58:18.945123  

 3332 13:58:18.948594  RX Delay -21 -> 252, step: 4

 3333 13:58:18.948666  

 3334 13:58:18.951736  Set Vref, RX VrefLevel [Byte0]: 32

 3335 13:58:18.954898                           [Byte1]: 32

 3336 13:58:18.954995  

 3337 13:58:18.958528  Set Vref, RX VrefLevel [Byte0]: 33

 3338 13:58:18.962001                           [Byte1]: 33

 3339 13:58:18.962074  

 3340 13:58:18.965431  Set Vref, RX VrefLevel [Byte0]: 34

 3341 13:58:18.968354                           [Byte1]: 34

 3342 13:58:18.972670  

 3343 13:58:18.972745  Set Vref, RX VrefLevel [Byte0]: 35

 3344 13:58:18.976081                           [Byte1]: 35

 3345 13:58:18.980535  

 3346 13:58:18.980610  Set Vref, RX VrefLevel [Byte0]: 36

 3347 13:58:18.984210                           [Byte1]: 36

 3348 13:58:18.988455  

 3349 13:58:18.988533  Set Vref, RX VrefLevel [Byte0]: 37

 3350 13:58:18.991899                           [Byte1]: 37

 3351 13:58:18.996597  

 3352 13:58:18.996671  Set Vref, RX VrefLevel [Byte0]: 38

 3353 13:58:18.999811                           [Byte1]: 38

 3354 13:58:19.004330  

 3355 13:58:19.004406  Set Vref, RX VrefLevel [Byte0]: 39

 3356 13:58:19.007586                           [Byte1]: 39

 3357 13:58:19.012136  

 3358 13:58:19.012214  Set Vref, RX VrefLevel [Byte0]: 40

 3359 13:58:19.016032                           [Byte1]: 40

 3360 13:58:19.020073  

 3361 13:58:19.020145  Set Vref, RX VrefLevel [Byte0]: 41

 3362 13:58:19.023536                           [Byte1]: 41

 3363 13:58:19.028024  

 3364 13:58:19.028098  Set Vref, RX VrefLevel [Byte0]: 42

 3365 13:58:19.031266                           [Byte1]: 42

 3366 13:58:19.036030  

 3367 13:58:19.036103  Set Vref, RX VrefLevel [Byte0]: 43

 3368 13:58:19.039190                           [Byte1]: 43

 3369 13:58:19.044117  

 3370 13:58:19.044194  Set Vref, RX VrefLevel [Byte0]: 44

 3371 13:58:19.047112                           [Byte1]: 44

 3372 13:58:19.052029  

 3373 13:58:19.052130  Set Vref, RX VrefLevel [Byte0]: 45

 3374 13:58:19.055601                           [Byte1]: 45

 3375 13:58:19.059885  

 3376 13:58:19.059961  Set Vref, RX VrefLevel [Byte0]: 46

 3377 13:58:19.062976                           [Byte1]: 46

 3378 13:58:19.067529  

 3379 13:58:19.067603  Set Vref, RX VrefLevel [Byte0]: 47

 3380 13:58:19.071290                           [Byte1]: 47

 3381 13:58:19.075865  

 3382 13:58:19.075967  Set Vref, RX VrefLevel [Byte0]: 48

 3383 13:58:19.079219                           [Byte1]: 48

 3384 13:58:19.083781  

 3385 13:58:19.083854  Set Vref, RX VrefLevel [Byte0]: 49

 3386 13:58:19.087145                           [Byte1]: 49

 3387 13:58:19.091408  

 3388 13:58:19.091482  Set Vref, RX VrefLevel [Byte0]: 50

 3389 13:58:19.094790                           [Byte1]: 50

 3390 13:58:19.099496  

 3391 13:58:19.099573  Set Vref, RX VrefLevel [Byte0]: 51

 3392 13:58:19.103030                           [Byte1]: 51

 3393 13:58:19.107292  

 3394 13:58:19.107435  Set Vref, RX VrefLevel [Byte0]: 52

 3395 13:58:19.110594                           [Byte1]: 52

 3396 13:58:19.115534  

 3397 13:58:19.115610  Set Vref, RX VrefLevel [Byte0]: 53

 3398 13:58:19.118389                           [Byte1]: 53

 3399 13:58:19.123182  

 3400 13:58:19.123282  Set Vref, RX VrefLevel [Byte0]: 54

 3401 13:58:19.126716                           [Byte1]: 54

 3402 13:58:19.131082  

 3403 13:58:19.131155  Set Vref, RX VrefLevel [Byte0]: 55

 3404 13:58:19.134397                           [Byte1]: 55

 3405 13:58:19.139010  

 3406 13:58:19.139112  Set Vref, RX VrefLevel [Byte0]: 56

 3407 13:58:19.142614                           [Byte1]: 56

 3408 13:58:19.146887  

 3409 13:58:19.146992  Set Vref, RX VrefLevel [Byte0]: 57

 3410 13:58:19.149991                           [Byte1]: 57

 3411 13:58:19.155174  

 3412 13:58:19.155276  Set Vref, RX VrefLevel [Byte0]: 58

 3413 13:58:19.158147                           [Byte1]: 58

 3414 13:58:19.162811  

 3415 13:58:19.162924  Set Vref, RX VrefLevel [Byte0]: 59

 3416 13:58:19.165870                           [Byte1]: 59

 3417 13:58:19.170648  

 3418 13:58:19.170726  Set Vref, RX VrefLevel [Byte0]: 60

 3419 13:58:19.174048                           [Byte1]: 60

 3420 13:58:19.178801  

 3421 13:58:19.178921  Set Vref, RX VrefLevel [Byte0]: 61

 3422 13:58:19.181660                           [Byte1]: 61

 3423 13:58:19.186536  

 3424 13:58:19.186616  Set Vref, RX VrefLevel [Byte0]: 62

 3425 13:58:19.189906                           [Byte1]: 62

 3426 13:58:19.194773  

 3427 13:58:19.194864  Set Vref, RX VrefLevel [Byte0]: 63

 3428 13:58:19.197722                           [Byte1]: 63

 3429 13:58:19.202458  

 3430 13:58:19.202541  Set Vref, RX VrefLevel [Byte0]: 64

 3431 13:58:19.205847                           [Byte1]: 64

 3432 13:58:19.210498  

 3433 13:58:19.210580  Set Vref, RX VrefLevel [Byte0]: 65

 3434 13:58:19.213774                           [Byte1]: 65

 3435 13:58:19.218149  

 3436 13:58:19.218241  Set Vref, RX VrefLevel [Byte0]: 66

 3437 13:58:19.221373                           [Byte1]: 66

 3438 13:58:19.226038  

 3439 13:58:19.226122  Set Vref, RX VrefLevel [Byte0]: 67

 3440 13:58:19.229369                           [Byte1]: 67

 3441 13:58:19.234025  

 3442 13:58:19.234121  Final RX Vref Byte 0 = 59 to rank0

 3443 13:58:19.237515  Final RX Vref Byte 1 = 57 to rank0

 3444 13:58:19.241044  Final RX Vref Byte 0 = 59 to rank1

 3445 13:58:19.244030  Final RX Vref Byte 1 = 57 to rank1==

 3446 13:58:19.247668  Dram Type= 6, Freq= 0, CH_1, rank 0

 3447 13:58:19.250648  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3448 13:58:19.254183  ==

 3449 13:58:19.254272  DQS Delay:

 3450 13:58:19.254356  DQS0 = 0, DQS1 = 0

 3451 13:58:19.257599  DQM Delay:

 3452 13:58:19.257679  DQM0 = 114, DQM1 = 107

 3453 13:58:19.260630  DQ Delay:

 3454 13:58:19.264108  DQ0 =116, DQ1 =108, DQ2 =108, DQ3 =112

 3455 13:58:19.267441  DQ4 =112, DQ5 =124, DQ6 =124, DQ7 =112

 3456 13:58:19.270520  DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =102

 3457 13:58:19.274053  DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =114

 3458 13:58:19.274133  

 3459 13:58:19.274200  

 3460 13:58:19.280891  [DQSOSCAuto] RK0, (LSB)MR18= 0xeef5, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps

 3461 13:58:19.284365  CH1 RK0: MR19=303, MR18=EEF5

 3462 13:58:19.291022  CH1_RK0: MR19=0x303, MR18=0xEEF5, DQSOSC=414, MR23=63, INC=38, DEC=25

 3463 13:58:19.291110  

 3464 13:58:19.294092  ----->DramcWriteLeveling(PI) begin...

 3465 13:58:19.294171  ==

 3466 13:58:19.297641  Dram Type= 6, Freq= 0, CH_1, rank 1

 3467 13:58:19.300467  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3468 13:58:19.304054  ==

 3469 13:58:19.304147  Write leveling (Byte 0): 23 => 23

 3470 13:58:19.307620  Write leveling (Byte 1): 28 => 28

 3471 13:58:19.310852  DramcWriteLeveling(PI) end<-----

 3472 13:58:19.310931  

 3473 13:58:19.310999  ==

 3474 13:58:19.314663  Dram Type= 6, Freq= 0, CH_1, rank 1

 3475 13:58:19.320907  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3476 13:58:19.320989  ==

 3477 13:58:19.321057  [Gating] SW mode calibration

 3478 13:58:19.330551  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3479 13:58:19.334668  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3480 13:58:19.337701   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3481 13:58:19.344113   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3482 13:58:19.347159   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3483 13:58:19.350689   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3484 13:58:19.357116   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3485 13:58:19.360561   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 3486 13:58:19.364152   0 15 24 | B1->B0 | 3232 2323 | 1 0 | (1 1) (1 0)

 3487 13:58:19.370993   0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)

 3488 13:58:19.374572   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3489 13:58:19.377647   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3490 13:58:19.384013   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3491 13:58:19.387332   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3492 13:58:19.390962   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3493 13:58:19.397252   1  0 20 | B1->B0 | 2424 2929 | 0 1 | (0 0) (1 1)

 3494 13:58:19.400917   1  0 24 | B1->B0 | 3030 4646 | 0 0 | (1 1) (0 0)

 3495 13:58:19.404054   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3496 13:58:19.410441   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3497 13:58:19.413960   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3498 13:58:19.417556   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3499 13:58:19.420725   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3500 13:58:19.427126   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3501 13:58:19.430730   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3502 13:58:19.433825   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3503 13:58:19.440653   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 3504 13:58:19.443950   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3505 13:58:19.447139   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3506 13:58:19.453743   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3507 13:58:19.457236   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3508 13:58:19.460665   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3509 13:58:19.467654   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3510 13:58:19.470691   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3511 13:58:19.473844   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3512 13:58:19.480779   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3513 13:58:19.483744   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3514 13:58:19.487111   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3515 13:58:19.494110   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3516 13:58:19.497344   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3517 13:58:19.500679   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3518 13:58:19.507147   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3519 13:58:19.510110   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3520 13:58:19.513436   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3521 13:58:19.517154  Total UI for P1: 0, mck2ui 16

 3522 13:58:19.520402  best dqsien dly found for B0: ( 1,  3, 26)

 3523 13:58:19.523500  Total UI for P1: 0, mck2ui 16

 3524 13:58:19.526808  best dqsien dly found for B1: ( 1,  3, 26)

 3525 13:58:19.530335  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3526 13:58:19.533461  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3527 13:58:19.533533  

 3528 13:58:19.537108  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3529 13:58:19.543459  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3530 13:58:19.543542  [Gating] SW calibration Done

 3531 13:58:19.546883  ==

 3532 13:58:19.546964  Dram Type= 6, Freq= 0, CH_1, rank 1

 3533 13:58:19.553646  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3534 13:58:19.553728  ==

 3535 13:58:19.553793  RX Vref Scan: 0

 3536 13:58:19.553853  

 3537 13:58:19.556640  RX Vref 0 -> 0, step: 1

 3538 13:58:19.556721  

 3539 13:58:19.560075  RX Delay -40 -> 252, step: 8

 3540 13:58:19.563148  iDelay=200, Bit 0, Center 115 (40 ~ 191) 152

 3541 13:58:19.566813  iDelay=200, Bit 1, Center 103 (32 ~ 175) 144

 3542 13:58:19.570275  iDelay=200, Bit 2, Center 99 (24 ~ 175) 152

 3543 13:58:19.576834  iDelay=200, Bit 3, Center 107 (32 ~ 183) 152

 3544 13:58:19.579967  iDelay=200, Bit 4, Center 107 (32 ~ 183) 152

 3545 13:58:19.583524  iDelay=200, Bit 5, Center 119 (40 ~ 199) 160

 3546 13:58:19.586534  iDelay=200, Bit 6, Center 119 (40 ~ 199) 160

 3547 13:58:19.589877  iDelay=200, Bit 7, Center 111 (40 ~ 183) 144

 3548 13:58:19.596360  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 3549 13:58:19.599964  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 3550 13:58:19.603541  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 3551 13:58:19.606567  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 3552 13:58:19.609621  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 3553 13:58:19.616995  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3554 13:58:19.620206  iDelay=200, Bit 14, Center 115 (40 ~ 191) 152

 3555 13:58:19.623347  iDelay=200, Bit 15, Center 115 (40 ~ 191) 152

 3556 13:58:19.623471  ==

 3557 13:58:19.626776  Dram Type= 6, Freq= 0, CH_1, rank 1

 3558 13:58:19.630115  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3559 13:58:19.630197  ==

 3560 13:58:19.632957  DQS Delay:

 3561 13:58:19.633038  DQS0 = 0, DQS1 = 0

 3562 13:58:19.636245  DQM Delay:

 3563 13:58:19.636326  DQM0 = 110, DQM1 = 109

 3564 13:58:19.639891  DQ Delay:

 3565 13:58:19.642848  DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107

 3566 13:58:19.646562  DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111

 3567 13:58:19.649651  DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103

 3568 13:58:19.653099  DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115

 3569 13:58:19.653180  

 3570 13:58:19.653243  

 3571 13:58:19.653303  ==

 3572 13:58:19.656383  Dram Type= 6, Freq= 0, CH_1, rank 1

 3573 13:58:19.659540  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3574 13:58:19.659622  ==

 3575 13:58:19.659686  

 3576 13:58:19.659745  

 3577 13:58:19.663261  	TX Vref Scan disable

 3578 13:58:19.666654   == TX Byte 0 ==

 3579 13:58:19.669652  Update DQ  dly =842 (3 ,2, 10)  DQ  OEN =(2 ,7)

 3580 13:58:19.672810  Update DQM dly =842 (3 ,2, 10)  DQM OEN =(2 ,7)

 3581 13:58:19.676324   == TX Byte 1 ==

 3582 13:58:19.679870  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3583 13:58:19.683239  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3584 13:58:19.683345  ==

 3585 13:58:19.686137  Dram Type= 6, Freq= 0, CH_1, rank 1

 3586 13:58:19.689551  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3587 13:58:19.693168  ==

 3588 13:58:19.703234  TX Vref=22, minBit 1, minWin=25, winSum=422

 3589 13:58:19.706806  TX Vref=24, minBit 9, minWin=25, winSum=426

 3590 13:58:19.709747  TX Vref=26, minBit 0, minWin=26, winSum=432

 3591 13:58:19.713288  TX Vref=28, minBit 0, minWin=26, winSum=433

 3592 13:58:19.716719  TX Vref=30, minBit 9, minWin=26, winSum=437

 3593 13:58:19.723073  TX Vref=32, minBit 1, minWin=26, winSum=434

 3594 13:58:19.726529  [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30

 3595 13:58:19.726634  

 3596 13:58:19.730275  Final TX Range 1 Vref 30

 3597 13:58:19.730416  

 3598 13:58:19.730509  ==

 3599 13:58:19.733340  Dram Type= 6, Freq= 0, CH_1, rank 1

 3600 13:58:19.736719  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3601 13:58:19.736801  ==

 3602 13:58:19.736865  

 3603 13:58:19.740006  

 3604 13:58:19.740089  	TX Vref Scan disable

 3605 13:58:19.743107   == TX Byte 0 ==

 3606 13:58:19.746631  Update DQ  dly =841 (3 ,1, 41)  DQ  OEN =(2 ,6)

 3607 13:58:19.749721  Update DQM dly =841 (3 ,1, 41)  DQM OEN =(2 ,6)

 3608 13:58:19.753582   == TX Byte 1 ==

 3609 13:58:19.756660  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3610 13:58:19.760049  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3611 13:58:19.760131  

 3612 13:58:19.762893  [DATLAT]

 3613 13:58:19.762974  Freq=1200, CH1 RK1

 3614 13:58:19.763039  

 3615 13:58:19.766785  DATLAT Default: 0xd

 3616 13:58:19.766866  0, 0xFFFF, sum = 0

 3617 13:58:19.769390  1, 0xFFFF, sum = 0

 3618 13:58:19.769474  2, 0xFFFF, sum = 0

 3619 13:58:19.773059  3, 0xFFFF, sum = 0

 3620 13:58:19.773142  4, 0xFFFF, sum = 0

 3621 13:58:19.776404  5, 0xFFFF, sum = 0

 3622 13:58:19.779987  6, 0xFFFF, sum = 0

 3623 13:58:19.780071  7, 0xFFFF, sum = 0

 3624 13:58:19.783183  8, 0xFFFF, sum = 0

 3625 13:58:19.783283  9, 0xFFFF, sum = 0

 3626 13:58:19.786059  10, 0xFFFF, sum = 0

 3627 13:58:19.786142  11, 0xFFFF, sum = 0

 3628 13:58:19.789621  12, 0x0, sum = 1

 3629 13:58:19.789703  13, 0x0, sum = 2

 3630 13:58:19.792704  14, 0x0, sum = 3

 3631 13:58:19.792787  15, 0x0, sum = 4

 3632 13:58:19.792854  best_step = 13

 3633 13:58:19.792913  

 3634 13:58:19.796400  ==

 3635 13:58:19.799343  Dram Type= 6, Freq= 0, CH_1, rank 1

 3636 13:58:19.802805  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3637 13:58:19.802887  ==

 3638 13:58:19.802952  RX Vref Scan: 0

 3639 13:58:19.803012  

 3640 13:58:19.805985  RX Vref 0 -> 0, step: 1

 3641 13:58:19.806066  

 3642 13:58:19.809384  RX Delay -21 -> 252, step: 4

 3643 13:58:19.812692  iDelay=195, Bit 0, Center 114 (43 ~ 186) 144

 3644 13:58:19.819282  iDelay=195, Bit 1, Center 108 (43 ~ 174) 132

 3645 13:58:19.822905  iDelay=195, Bit 2, Center 104 (35 ~ 174) 140

 3646 13:58:19.825804  iDelay=195, Bit 3, Center 110 (43 ~ 178) 136

 3647 13:58:19.829385  iDelay=195, Bit 4, Center 108 (39 ~ 178) 140

 3648 13:58:19.832351  iDelay=195, Bit 5, Center 122 (51 ~ 194) 144

 3649 13:58:19.839103  iDelay=195, Bit 6, Center 122 (51 ~ 194) 144

 3650 13:58:19.842348  iDelay=195, Bit 7, Center 110 (43 ~ 178) 136

 3651 13:58:19.845595  iDelay=195, Bit 8, Center 98 (35 ~ 162) 128

 3652 13:58:19.848709  iDelay=195, Bit 9, Center 100 (35 ~ 166) 132

 3653 13:58:19.851972  iDelay=195, Bit 10, Center 112 (43 ~ 182) 140

 3654 13:58:19.858991  iDelay=195, Bit 11, Center 104 (39 ~ 170) 132

 3655 13:58:19.862455  iDelay=195, Bit 12, Center 122 (59 ~ 186) 128

 3656 13:58:19.865431  iDelay=195, Bit 13, Center 116 (51 ~ 182) 132

 3657 13:58:19.868741  iDelay=195, Bit 14, Center 120 (59 ~ 182) 124

 3658 13:58:19.875123  iDelay=195, Bit 15, Center 120 (59 ~ 182) 124

 3659 13:58:19.875206  ==

 3660 13:58:19.878912  Dram Type= 6, Freq= 0, CH_1, rank 1

 3661 13:58:19.882223  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3662 13:58:19.882306  ==

 3663 13:58:19.882371  DQS Delay:

 3664 13:58:19.885294  DQS0 = 0, DQS1 = 0

 3665 13:58:19.885375  DQM Delay:

 3666 13:58:19.888810  DQM0 = 112, DQM1 = 111

 3667 13:58:19.888892  DQ Delay:

 3668 13:58:19.891869  DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =110

 3669 13:58:19.895075  DQ4 =108, DQ5 =122, DQ6 =122, DQ7 =110

 3670 13:58:19.898593  DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =104

 3671 13:58:19.901567  DQ12 =122, DQ13 =116, DQ14 =120, DQ15 =120

 3672 13:58:19.901648  

 3673 13:58:19.905147  

 3674 13:58:19.911589  [DQSOSCAuto] RK1, (LSB)MR18= 0xfa09, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps

 3675 13:58:19.915388  CH1 RK1: MR19=304, MR18=FA09

 3676 13:58:19.921664  CH1_RK1: MR19=0x304, MR18=0xFA09, DQSOSC=406, MR23=63, INC=39, DEC=26

 3677 13:58:19.921746  [RxdqsGatingPostProcess] freq 1200

 3678 13:58:19.928474  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3679 13:58:19.932068  best DQS0 dly(2T, 0.5T) = (0, 11)

 3680 13:58:19.935121  best DQS1 dly(2T, 0.5T) = (0, 11)

 3681 13:58:19.938450  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3682 13:58:19.941520  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3683 13:58:19.945279  best DQS0 dly(2T, 0.5T) = (0, 11)

 3684 13:58:19.948637  best DQS1 dly(2T, 0.5T) = (0, 11)

 3685 13:58:19.951821  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3686 13:58:19.955225  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3687 13:58:19.958499  Pre-setting of DQS Precalculation

 3688 13:58:19.961682  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3689 13:58:19.968484  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3690 13:58:19.978181  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3691 13:58:19.978264  

 3692 13:58:19.978328  

 3693 13:58:19.978388  [Calibration Summary] 2400 Mbps

 3694 13:58:19.981337  CH 0, Rank 0

 3695 13:58:19.981418  SW Impedance     : PASS

 3696 13:58:19.984758  DUTY Scan        : NO K

 3697 13:58:19.988384  ZQ Calibration   : PASS

 3698 13:58:19.988465  Jitter Meter     : NO K

 3699 13:58:19.991318  CBT Training     : PASS

 3700 13:58:19.994646  Write leveling   : PASS

 3701 13:58:19.994727  RX DQS gating    : PASS

 3702 13:58:19.998495  RX DQ/DQS(RDDQC) : PASS

 3703 13:58:20.001405  TX DQ/DQS        : PASS

 3704 13:58:20.001487  RX DATLAT        : PASS

 3705 13:58:20.004713  RX DQ/DQS(Engine): PASS

 3706 13:58:20.008634  TX OE            : NO K

 3707 13:58:20.008709  All Pass.

 3708 13:58:20.008773  

 3709 13:58:20.008833  CH 0, Rank 1

 3710 13:58:20.011590  SW Impedance     : PASS

 3711 13:58:20.015260  DUTY Scan        : NO K

 3712 13:58:20.015368  ZQ Calibration   : PASS

 3713 13:58:20.018296  Jitter Meter     : NO K

 3714 13:58:20.021288  CBT Training     : PASS

 3715 13:58:20.021373  Write leveling   : PASS

 3716 13:58:20.025012  RX DQS gating    : PASS

 3717 13:58:20.027971  RX DQ/DQS(RDDQC) : PASS

 3718 13:58:20.028052  TX DQ/DQS        : PASS

 3719 13:58:20.031770  RX DATLAT        : PASS

 3720 13:58:20.031873  RX DQ/DQS(Engine): PASS

 3721 13:58:20.034664  TX OE            : NO K

 3722 13:58:20.034746  All Pass.

 3723 13:58:20.034811  

 3724 13:58:20.038497  CH 1, Rank 0

 3725 13:58:20.038579  SW Impedance     : PASS

 3726 13:58:20.041215  DUTY Scan        : NO K

 3727 13:58:20.044607  ZQ Calibration   : PASS

 3728 13:58:20.044692  Jitter Meter     : NO K

 3729 13:58:20.048115  CBT Training     : PASS

 3730 13:58:20.051193  Write leveling   : PASS

 3731 13:58:20.051274  RX DQS gating    : PASS

 3732 13:58:20.054701  RX DQ/DQS(RDDQC) : PASS

 3733 13:58:20.058029  TX DQ/DQS        : PASS

 3734 13:58:20.058111  RX DATLAT        : PASS

 3735 13:58:20.061034  RX DQ/DQS(Engine): PASS

 3736 13:58:20.064487  TX OE            : NO K

 3737 13:58:20.064570  All Pass.

 3738 13:58:20.064635  

 3739 13:58:20.064695  CH 1, Rank 1

 3740 13:58:20.067570  SW Impedance     : PASS

 3741 13:58:20.071144  DUTY Scan        : NO K

 3742 13:58:20.071243  ZQ Calibration   : PASS

 3743 13:58:20.074235  Jitter Meter     : NO K

 3744 13:58:20.077688  CBT Training     : PASS

 3745 13:58:20.077770  Write leveling   : PASS

 3746 13:58:20.081142  RX DQS gating    : PASS

 3747 13:58:20.084576  RX DQ/DQS(RDDQC) : PASS

 3748 13:58:20.084658  TX DQ/DQS        : PASS

 3749 13:58:20.087848  RX DATLAT        : PASS

 3750 13:58:20.087930  RX DQ/DQS(Engine): PASS

 3751 13:58:20.091318  TX OE            : NO K

 3752 13:58:20.091441  All Pass.

 3753 13:58:20.091509  

 3754 13:58:20.094628  DramC Write-DBI off

 3755 13:58:20.097466  	PER_BANK_REFRESH: Hybrid Mode

 3756 13:58:20.097547  TX_TRACKING: ON

 3757 13:58:20.107834  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3758 13:58:20.110949  [FAST_K] Save calibration result to emmc

 3759 13:58:20.114442  dramc_set_vcore_voltage set vcore to 650000

 3760 13:58:20.117533  Read voltage for 600, 5

 3761 13:58:20.117615  Vio18 = 0

 3762 13:58:20.120750  Vcore = 650000

 3763 13:58:20.120832  Vdram = 0

 3764 13:58:20.120897  Vddq = 0

 3765 13:58:20.120957  Vmddr = 0

 3766 13:58:20.127473  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3767 13:58:20.134285  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3768 13:58:20.134368  MEM_TYPE=3, freq_sel=19

 3769 13:58:20.137528  sv_algorithm_assistance_LP4_1600 

 3770 13:58:20.140444  ============ PULL DRAM RESETB DOWN ============

 3771 13:58:20.147349  ========== PULL DRAM RESETB DOWN end =========

 3772 13:58:20.151005  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3773 13:58:20.153860  =================================== 

 3774 13:58:20.157144  LPDDR4 DRAM CONFIGURATION

 3775 13:58:20.160437  =================================== 

 3776 13:58:20.160519  EX_ROW_EN[0]    = 0x0

 3777 13:58:20.163829  EX_ROW_EN[1]    = 0x0

 3778 13:58:20.163911  LP4Y_EN      = 0x0

 3779 13:58:20.167290  WORK_FSP     = 0x0

 3780 13:58:20.167380  WL           = 0x2

 3781 13:58:20.170502  RL           = 0x2

 3782 13:58:20.173727  BL           = 0x2

 3783 13:58:20.173808  RPST         = 0x0

 3784 13:58:20.177110  RD_PRE       = 0x0

 3785 13:58:20.177191  WR_PRE       = 0x1

 3786 13:58:20.180689  WR_PST       = 0x0

 3787 13:58:20.180771  DBI_WR       = 0x0

 3788 13:58:20.183784  DBI_RD       = 0x0

 3789 13:58:20.183866  OTF          = 0x1

 3790 13:58:20.186804  =================================== 

 3791 13:58:20.190135  =================================== 

 3792 13:58:20.193740  ANA top config

 3793 13:58:20.193822  =================================== 

 3794 13:58:20.196761  DLL_ASYNC_EN            =  0

 3795 13:58:20.200274  ALL_SLAVE_EN            =  1

 3796 13:58:20.203439  NEW_RANK_MODE           =  1

 3797 13:58:20.207162  DLL_IDLE_MODE           =  1

 3798 13:58:20.207244  LP45_APHY_COMB_EN       =  1

 3799 13:58:20.210658  TX_ODT_DIS              =  1

 3800 13:58:20.213600  NEW_8X_MODE             =  1

 3801 13:58:20.216911  =================================== 

 3802 13:58:20.220565  =================================== 

 3803 13:58:20.223550  data_rate                  = 1200

 3804 13:58:20.226842  CKR                        = 1

 3805 13:58:20.226924  DQ_P2S_RATIO               = 8

 3806 13:58:20.229992  =================================== 

 3807 13:58:20.233885  CA_P2S_RATIO               = 8

 3808 13:58:20.236881  DQ_CA_OPEN                 = 0

 3809 13:58:20.240007  DQ_SEMI_OPEN               = 0

 3810 13:58:20.243444  CA_SEMI_OPEN               = 0

 3811 13:58:20.246633  CA_FULL_RATE               = 0

 3812 13:58:20.246716  DQ_CKDIV4_EN               = 1

 3813 13:58:20.250049  CA_CKDIV4_EN               = 1

 3814 13:58:20.253666  CA_PREDIV_EN               = 0

 3815 13:58:20.256536  PH8_DLY                    = 0

 3816 13:58:20.260034  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3817 13:58:20.263219  DQ_AAMCK_DIV               = 4

 3818 13:58:20.263301  CA_AAMCK_DIV               = 4

 3819 13:58:20.266424  CA_ADMCK_DIV               = 4

 3820 13:58:20.269817  DQ_TRACK_CA_EN             = 0

 3821 13:58:20.273300  CA_PICK                    = 600

 3822 13:58:20.276910  CA_MCKIO                   = 600

 3823 13:58:20.279755  MCKIO_SEMI                 = 0

 3824 13:58:20.283185  PLL_FREQ                   = 2288

 3825 13:58:20.283267  DQ_UI_PI_RATIO             = 32

 3826 13:58:20.286964  CA_UI_PI_RATIO             = 0

 3827 13:58:20.290458  =================================== 

 3828 13:58:20.293097  =================================== 

 3829 13:58:20.296759  memory_type:LPDDR4         

 3830 13:58:20.300266  GP_NUM     : 10       

 3831 13:58:20.300349  SRAM_EN    : 1       

 3832 13:58:20.303097  MD32_EN    : 0       

 3833 13:58:20.306694  =================================== 

 3834 13:58:20.309994  [ANA_INIT] >>>>>>>>>>>>>> 

 3835 13:58:20.310077  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3836 13:58:20.313191  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3837 13:58:20.316442  =================================== 

 3838 13:58:20.319977  data_rate = 1200,PCW = 0X5800

 3839 13:58:20.323276  =================================== 

 3840 13:58:20.326641  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3841 13:58:20.333123  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3842 13:58:20.339502  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3843 13:58:20.342956  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3844 13:58:20.346454  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3845 13:58:20.349826  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3846 13:58:20.352852  [ANA_INIT] flow start 

 3847 13:58:20.352935  [ANA_INIT] PLL >>>>>>>> 

 3848 13:58:20.356094  [ANA_INIT] PLL <<<<<<<< 

 3849 13:58:20.359751  [ANA_INIT] MIDPI >>>>>>>> 

 3850 13:58:20.362977  [ANA_INIT] MIDPI <<<<<<<< 

 3851 13:58:20.363059  [ANA_INIT] DLL >>>>>>>> 

 3852 13:58:20.366369  [ANA_INIT] flow end 

 3853 13:58:20.369700  ============ LP4 DIFF to SE enter ============

 3854 13:58:20.372956  ============ LP4 DIFF to SE exit  ============

 3855 13:58:20.376241  [ANA_INIT] <<<<<<<<<<<<< 

 3856 13:58:20.379198  [Flow] Enable top DCM control >>>>> 

 3857 13:58:20.382839  [Flow] Enable top DCM control <<<<< 

 3858 13:58:20.386271  Enable DLL master slave shuffle 

 3859 13:58:20.389732  ============================================================== 

 3860 13:58:20.392453  Gating Mode config

 3861 13:58:20.399804  ============================================================== 

 3862 13:58:20.399887  Config description: 

 3863 13:58:20.409219  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3864 13:58:20.416186  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3865 13:58:20.422761  SELPH_MODE            0: By rank         1: By Phase 

 3866 13:58:20.426098  ============================================================== 

 3867 13:58:20.429585  GAT_TRACK_EN                 =  1

 3868 13:58:20.432876  RX_GATING_MODE               =  2

 3869 13:58:20.435953  RX_GATING_TRACK_MODE         =  2

 3870 13:58:20.439557  SELPH_MODE                   =  1

 3871 13:58:20.443119  PICG_EARLY_EN                =  1

 3872 13:58:20.446010  VALID_LAT_VALUE              =  1

 3873 13:58:20.449420  ============================================================== 

 3874 13:58:20.452863  Enter into Gating configuration >>>> 

 3875 13:58:20.456004  Exit from Gating configuration <<<< 

 3876 13:58:20.459466  Enter into  DVFS_PRE_config >>>>> 

 3877 13:58:20.472832  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3878 13:58:20.472916  Exit from  DVFS_PRE_config <<<<< 

 3879 13:58:20.476043  Enter into PICG configuration >>>> 

 3880 13:58:20.479763  Exit from PICG configuration <<<< 

 3881 13:58:20.482676  [RX_INPUT] configuration >>>>> 

 3882 13:58:20.485982  [RX_INPUT] configuration <<<<< 

 3883 13:58:20.492230  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3884 13:58:20.495959  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3885 13:58:20.502159  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3886 13:58:20.509054  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3887 13:58:20.515570  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3888 13:58:20.522243  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3889 13:58:20.525599  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3890 13:58:20.528779  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3891 13:58:20.532742  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3892 13:58:20.538744  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3893 13:58:20.542376  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3894 13:58:20.545838  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3895 13:58:20.548635  =================================== 

 3896 13:58:20.552334  LPDDR4 DRAM CONFIGURATION

 3897 13:58:20.555609  =================================== 

 3898 13:58:20.558817  EX_ROW_EN[0]    = 0x0

 3899 13:58:20.558899  EX_ROW_EN[1]    = 0x0

 3900 13:58:20.562084  LP4Y_EN      = 0x0

 3901 13:58:20.562166  WORK_FSP     = 0x0

 3902 13:58:20.565156  WL           = 0x2

 3903 13:58:20.565237  RL           = 0x2

 3904 13:58:20.568887  BL           = 0x2

 3905 13:58:20.568968  RPST         = 0x0

 3906 13:58:20.572143  RD_PRE       = 0x0

 3907 13:58:20.572224  WR_PRE       = 0x1

 3908 13:58:20.575571  WR_PST       = 0x0

 3909 13:58:20.575652  DBI_WR       = 0x0

 3910 13:58:20.578914  DBI_RD       = 0x0

 3911 13:58:20.578995  OTF          = 0x1

 3912 13:58:20.582249  =================================== 

 3913 13:58:20.588619  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3914 13:58:20.591991  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3915 13:58:20.594982  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3916 13:58:20.598476  =================================== 

 3917 13:58:20.602194  LPDDR4 DRAM CONFIGURATION

 3918 13:58:20.605110  =================================== 

 3919 13:58:20.608313  EX_ROW_EN[0]    = 0x10

 3920 13:58:20.608422  EX_ROW_EN[1]    = 0x0

 3921 13:58:20.612165  LP4Y_EN      = 0x0

 3922 13:58:20.612253  WORK_FSP     = 0x0

 3923 13:58:20.615143  WL           = 0x2

 3924 13:58:20.615230  RL           = 0x2

 3925 13:58:20.618808  BL           = 0x2

 3926 13:58:20.618893  RPST         = 0x0

 3927 13:58:20.621546  RD_PRE       = 0x0

 3928 13:58:20.621631  WR_PRE       = 0x1

 3929 13:58:20.625009  WR_PST       = 0x0

 3930 13:58:20.625095  DBI_WR       = 0x0

 3931 13:58:20.628594  DBI_RD       = 0x0

 3932 13:58:20.628680  OTF          = 0x1

 3933 13:58:20.632015  =================================== 

 3934 13:58:20.638496  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3935 13:58:20.642969  nWR fixed to 30

 3936 13:58:20.646201  [ModeRegInit_LP4] CH0 RK0

 3937 13:58:20.646283  [ModeRegInit_LP4] CH0 RK1

 3938 13:58:20.649842  [ModeRegInit_LP4] CH1 RK0

 3939 13:58:20.652684  [ModeRegInit_LP4] CH1 RK1

 3940 13:58:20.652765  match AC timing 17

 3941 13:58:20.659624  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3942 13:58:20.662547  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3943 13:58:20.666062  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3944 13:58:20.672778  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3945 13:58:20.676156  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3946 13:58:20.676238  ==

 3947 13:58:20.679145  Dram Type= 6, Freq= 0, CH_0, rank 0

 3948 13:58:20.683083  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3949 13:58:20.683166  ==

 3950 13:58:20.689510  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3951 13:58:20.695865  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 3952 13:58:20.699240  [CA 0] Center 37 (7~67) winsize 61

 3953 13:58:20.702457  [CA 1] Center 37 (7~67) winsize 61

 3954 13:58:20.705783  [CA 2] Center 35 (5~65) winsize 61

 3955 13:58:20.709423  [CA 3] Center 35 (5~65) winsize 61

 3956 13:58:20.712914  [CA 4] Center 34 (4~65) winsize 62

 3957 13:58:20.715808  [CA 5] Center 34 (4~64) winsize 61

 3958 13:58:20.715889  

 3959 13:58:20.718950  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 3960 13:58:20.719031  

 3961 13:58:20.722625  [CATrainingPosCal] consider 1 rank data

 3962 13:58:20.725660  u2DelayCellTimex100 = 270/100 ps

 3963 13:58:20.729080  CA0 delay=37 (7~67),Diff = 3 PI (28 cell)

 3964 13:58:20.732525  CA1 delay=37 (7~67),Diff = 3 PI (28 cell)

 3965 13:58:20.735949  CA2 delay=35 (5~65),Diff = 1 PI (9 cell)

 3966 13:58:20.739104  CA3 delay=35 (5~65),Diff = 1 PI (9 cell)

 3967 13:58:20.742280  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 3968 13:58:20.749368  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 3969 13:58:20.749451  

 3970 13:58:20.752643  CA PerBit enable=1, Macro0, CA PI delay=34

 3971 13:58:20.752724  

 3972 13:58:20.755430  [CBTSetCACLKResult] CA Dly = 34

 3973 13:58:20.755511  CS Dly: 5 (0~36)

 3974 13:58:20.755576  ==

 3975 13:58:20.759013  Dram Type= 6, Freq= 0, CH_0, rank 1

 3976 13:58:20.762440  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3977 13:58:20.765485  ==

 3978 13:58:20.769087  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3979 13:58:20.775781  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3980 13:58:20.779026  [CA 0] Center 37 (7~67) winsize 61

 3981 13:58:20.782063  [CA 1] Center 37 (7~67) winsize 61

 3982 13:58:20.785425  [CA 2] Center 35 (5~65) winsize 61

 3983 13:58:20.788774  [CA 3] Center 34 (4~65) winsize 62

 3984 13:58:20.792319  [CA 4] Center 33 (3~64) winsize 62

 3985 13:58:20.795342  [CA 5] Center 33 (3~64) winsize 62

 3986 13:58:20.795446  

 3987 13:58:20.798916  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3988 13:58:20.799013  

 3989 13:58:20.802569  [CATrainingPosCal] consider 2 rank data

 3990 13:58:20.805569  u2DelayCellTimex100 = 270/100 ps

 3991 13:58:20.808706  CA0 delay=37 (7~67),Diff = 3 PI (28 cell)

 3992 13:58:20.812258  CA1 delay=37 (7~67),Diff = 3 PI (28 cell)

 3993 13:58:20.815626  CA2 delay=35 (5~65),Diff = 1 PI (9 cell)

 3994 13:58:20.821786  CA3 delay=35 (5~65),Diff = 1 PI (9 cell)

 3995 13:58:20.824977  CA4 delay=34 (4~64),Diff = 0 PI (0 cell)

 3996 13:58:20.828535  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 3997 13:58:20.828644  

 3998 13:58:20.831697  CA PerBit enable=1, Macro0, CA PI delay=34

 3999 13:58:20.831789  

 4000 13:58:20.835204  [CBTSetCACLKResult] CA Dly = 34

 4001 13:58:20.835311  CS Dly: 6 (0~38)

 4002 13:58:20.835438  

 4003 13:58:20.838409  ----->DramcWriteLeveling(PI) begin...

 4004 13:58:20.838516  ==

 4005 13:58:20.841940  Dram Type= 6, Freq= 0, CH_0, rank 0

 4006 13:58:20.848123  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4007 13:58:20.848200  ==

 4008 13:58:20.851738  Write leveling (Byte 0): 33 => 33

 4009 13:58:20.855461  Write leveling (Byte 1): 33 => 33

 4010 13:58:20.855543  DramcWriteLeveling(PI) end<-----

 4011 13:58:20.858515  

 4012 13:58:20.858625  ==

 4013 13:58:20.861412  Dram Type= 6, Freq= 0, CH_0, rank 0

 4014 13:58:20.864910  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4015 13:58:20.865018  ==

 4016 13:58:20.868491  [Gating] SW mode calibration

 4017 13:58:20.874663  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4018 13:58:20.878261  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4019 13:58:20.884651   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4020 13:58:20.888085   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4021 13:58:20.891670   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4022 13:58:20.898073   0  9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)

 4023 13:58:20.901411   0  9 16 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)

 4024 13:58:20.904579   0  9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 4025 13:58:20.911618   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4026 13:58:20.914634   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4027 13:58:20.917611   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4028 13:58:20.924492   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4029 13:58:20.928097   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4030 13:58:20.931334   0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)

 4031 13:58:20.938025   0 10 16 | B1->B0 | 2f2f 3939 | 0 0 | (0 0) (1 1)

 4032 13:58:20.941155   0 10 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)

 4033 13:58:20.944741   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4034 13:58:20.951173   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4035 13:58:20.954441   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4036 13:58:20.957453   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4037 13:58:20.964519   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4038 13:58:20.967874   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4039 13:58:20.970776   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 4040 13:58:20.977567   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4041 13:58:20.981178   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4042 13:58:20.984100   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4043 13:58:20.990593   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4044 13:58:20.993995   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4045 13:58:20.997620   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4046 13:58:21.003979   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4047 13:58:21.007724   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4048 13:58:21.010694   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4049 13:58:21.017495   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4050 13:58:21.020516   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4051 13:58:21.023795   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4052 13:58:21.030671   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4053 13:58:21.033854   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4054 13:58:21.037614   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4055 13:58:21.041096   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 4056 13:58:21.043948  Total UI for P1: 0, mck2ui 16

 4057 13:58:21.047543  best dqsien dly found for B0: ( 0, 13, 14)

 4058 13:58:21.054252   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4059 13:58:21.057382  Total UI for P1: 0, mck2ui 16

 4060 13:58:21.060750  best dqsien dly found for B1: ( 0, 13, 18)

 4061 13:58:21.063784  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4062 13:58:21.067714  best DQS1 dly(MCK, UI, PI) = (0, 13, 18)

 4063 13:58:21.067823  

 4064 13:58:21.070336  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4065 13:58:21.074242  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)

 4066 13:58:21.077133  [Gating] SW calibration Done

 4067 13:58:21.077215  ==

 4068 13:58:21.080523  Dram Type= 6, Freq= 0, CH_0, rank 0

 4069 13:58:21.083688  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4070 13:58:21.083770  ==

 4071 13:58:21.087023  RX Vref Scan: 0

 4072 13:58:21.087104  

 4073 13:58:21.090712  RX Vref 0 -> 0, step: 1

 4074 13:58:21.090794  

 4075 13:58:21.090858  RX Delay -230 -> 252, step: 16

 4076 13:58:21.097078  iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336

 4077 13:58:21.100605  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4078 13:58:21.103400  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4079 13:58:21.107065  iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336

 4080 13:58:21.113424  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4081 13:58:21.117055  iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320

 4082 13:58:21.120481  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4083 13:58:21.123330  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4084 13:58:21.126894  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4085 13:58:21.133580  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4086 13:58:21.136748  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4087 13:58:21.140248  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4088 13:58:21.143742  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4089 13:58:21.150341  iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336

 4090 13:58:21.153513  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4091 13:58:21.156993  iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336

 4092 13:58:21.157076  ==

 4093 13:58:21.159675  Dram Type= 6, Freq= 0, CH_0, rank 0

 4094 13:58:21.167007  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4095 13:58:21.167089  ==

 4096 13:58:21.167155  DQS Delay:

 4097 13:58:21.167215  DQS0 = 0, DQS1 = 0

 4098 13:58:21.169763  DQM Delay:

 4099 13:58:21.169844  DQM0 = 38, DQM1 = 30

 4100 13:58:21.173316  DQ Delay:

 4101 13:58:21.176680  DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33

 4102 13:58:21.179638  DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49

 4103 13:58:21.183172  DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25

 4104 13:58:21.186718  DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33

 4105 13:58:21.186800  

 4106 13:58:21.186864  

 4107 13:58:21.186923  ==

 4108 13:58:21.189760  Dram Type= 6, Freq= 0, CH_0, rank 0

 4109 13:58:21.193185  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4110 13:58:21.193266  ==

 4111 13:58:21.193332  

 4112 13:58:21.193391  

 4113 13:58:21.196630  	TX Vref Scan disable

 4114 13:58:21.196712   == TX Byte 0 ==

 4115 13:58:21.202960  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4116 13:58:21.206495  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4117 13:58:21.206576   == TX Byte 1 ==

 4118 13:58:21.212877  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4119 13:58:21.216455  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4120 13:58:21.216536  ==

 4121 13:58:21.219300  Dram Type= 6, Freq= 0, CH_0, rank 0

 4122 13:58:21.222847  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4123 13:58:21.222928  ==

 4124 13:58:21.222993  

 4125 13:58:21.225949  

 4126 13:58:21.226029  	TX Vref Scan disable

 4127 13:58:21.229705   == TX Byte 0 ==

 4128 13:58:21.233279  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4129 13:58:21.239629  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4130 13:58:21.239710   == TX Byte 1 ==

 4131 13:58:21.242531  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4132 13:58:21.249189  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4133 13:58:21.249270  

 4134 13:58:21.249335  [DATLAT]

 4135 13:58:21.249395  Freq=600, CH0 RK0

 4136 13:58:21.249455  

 4137 13:58:21.252686  DATLAT Default: 0x9

 4138 13:58:21.252767  0, 0xFFFF, sum = 0

 4139 13:58:21.256102  1, 0xFFFF, sum = 0

 4140 13:58:21.259534  2, 0xFFFF, sum = 0

 4141 13:58:21.259616  3, 0xFFFF, sum = 0

 4142 13:58:21.262789  4, 0xFFFF, sum = 0

 4143 13:58:21.262871  5, 0xFFFF, sum = 0

 4144 13:58:21.266098  6, 0xFFFF, sum = 0

 4145 13:58:21.266181  7, 0xFFFF, sum = 0

 4146 13:58:21.269354  8, 0x0, sum = 1

 4147 13:58:21.269471  9, 0x0, sum = 2

 4148 13:58:21.269568  10, 0x0, sum = 3

 4149 13:58:21.272712  11, 0x0, sum = 4

 4150 13:58:21.272795  best_step = 9

 4151 13:58:21.272861  

 4152 13:58:21.272921  ==

 4153 13:58:21.276507  Dram Type= 6, Freq= 0, CH_0, rank 0

 4154 13:58:21.282740  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4155 13:58:21.282842  ==

 4156 13:58:21.282933  RX Vref Scan: 1

 4157 13:58:21.283031  

 4158 13:58:21.285872  RX Vref 0 -> 0, step: 1

 4159 13:58:21.285953  

 4160 13:58:21.289129  RX Delay -195 -> 252, step: 8

 4161 13:58:21.289207  

 4162 13:58:21.292387  Set Vref, RX VrefLevel [Byte0]: 61

 4163 13:58:21.295947                           [Byte1]: 49

 4164 13:58:21.296030  

 4165 13:58:21.298858  Final RX Vref Byte 0 = 61 to rank0

 4166 13:58:21.302245  Final RX Vref Byte 1 = 49 to rank0

 4167 13:58:21.305903  Final RX Vref Byte 0 = 61 to rank1

 4168 13:58:21.309382  Final RX Vref Byte 1 = 49 to rank1==

 4169 13:58:21.312531  Dram Type= 6, Freq= 0, CH_0, rank 0

 4170 13:58:21.315817  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4171 13:58:21.315899  ==

 4172 13:58:21.318862  DQS Delay:

 4173 13:58:21.318943  DQS0 = 0, DQS1 = 0

 4174 13:58:21.322324  DQM Delay:

 4175 13:58:21.322405  DQM0 = 34, DQM1 = 28

 4176 13:58:21.322469  DQ Delay:

 4177 13:58:21.325824  DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32

 4178 13:58:21.329475  DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44

 4179 13:58:21.332408  DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20

 4180 13:58:21.335385  DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36

 4181 13:58:21.335481  

 4182 13:58:21.335546  

 4183 13:58:21.345438  [DQSOSCAuto] RK0, (LSB)MR18= 0x4746, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps

 4184 13:58:21.348841  CH0 RK0: MR19=808, MR18=4746

 4185 13:58:21.355921  CH0_RK0: MR19=0x808, MR18=0x4746, DQSOSC=396, MR23=63, INC=167, DEC=111

 4186 13:58:21.356003  

 4187 13:58:21.358733  ----->DramcWriteLeveling(PI) begin...

 4188 13:58:21.358832  ==

 4189 13:58:21.361917  Dram Type= 6, Freq= 0, CH_0, rank 1

 4190 13:58:21.365771  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4191 13:58:21.365853  ==

 4192 13:58:21.368814  Write leveling (Byte 0): 33 => 33

 4193 13:58:21.371873  Write leveling (Byte 1): 31 => 31

 4194 13:58:21.375280  DramcWriteLeveling(PI) end<-----

 4195 13:58:21.375363  

 4196 13:58:21.375449  ==

 4197 13:58:21.378499  Dram Type= 6, Freq= 0, CH_0, rank 1

 4198 13:58:21.381969  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4199 13:58:21.382051  ==

 4200 13:58:21.385667  [Gating] SW mode calibration

 4201 13:58:21.391700  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4202 13:58:21.398791  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4203 13:58:21.402142   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4204 13:58:21.405106   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4205 13:58:21.412056   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4206 13:58:21.415113   0  9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)

 4207 13:58:21.418575   0  9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)

 4208 13:58:21.424972   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4209 13:58:21.428599   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4210 13:58:21.432152   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4211 13:58:21.438454   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4212 13:58:21.441838   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4213 13:58:21.444805   0 10  8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 4214 13:58:21.451745   0 10 12 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)

 4215 13:58:21.454715   0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)

 4216 13:58:21.458287   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4217 13:58:21.465035   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4218 13:58:21.468217   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4219 13:58:21.471846   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4220 13:58:21.478168   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4221 13:58:21.481427   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4222 13:58:21.484819   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4223 13:58:21.491514   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 4224 13:58:21.494933   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4225 13:58:21.498162   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4226 13:58:21.504696   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4227 13:58:21.507675   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4228 13:58:21.511115   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4229 13:58:21.514318   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4230 13:58:21.521325   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4231 13:58:21.524515   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4232 13:58:21.527969   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4233 13:58:21.534380   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4234 13:58:21.537406   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4235 13:58:21.540874   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4236 13:58:21.547889   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4237 13:58:21.550996   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4238 13:58:21.554344   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4239 13:58:21.557474  Total UI for P1: 0, mck2ui 16

 4240 13:58:21.561074  best dqsien dly found for B0: ( 0, 13, 10)

 4241 13:58:21.567913   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4242 13:58:21.571314   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4243 13:58:21.573932  Total UI for P1: 0, mck2ui 16

 4244 13:58:21.577233  best dqsien dly found for B1: ( 0, 13, 14)

 4245 13:58:21.580735  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4246 13:58:21.584408  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4247 13:58:21.584490  

 4248 13:58:21.587337  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4249 13:58:21.590791  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4250 13:58:21.593851  [Gating] SW calibration Done

 4251 13:58:21.593960  ==

 4252 13:58:21.597755  Dram Type= 6, Freq= 0, CH_0, rank 1

 4253 13:58:21.604022  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4254 13:58:21.604110  ==

 4255 13:58:21.604178  RX Vref Scan: 0

 4256 13:58:21.604239  

 4257 13:58:21.607519  RX Vref 0 -> 0, step: 1

 4258 13:58:21.607591  

 4259 13:58:21.610633  RX Delay -230 -> 252, step: 16

 4260 13:58:21.614104  iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336

 4261 13:58:21.617368  iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336

 4262 13:58:21.620380  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4263 13:58:21.626934  iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336

 4264 13:58:21.630360  iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336

 4265 13:58:21.634020  iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336

 4266 13:58:21.637411  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4267 13:58:21.643610  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4268 13:58:21.647521  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4269 13:58:21.650042  iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320

 4270 13:58:21.653431  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4271 13:58:21.657013  iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336

 4272 13:58:21.663514  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4273 13:58:21.667027  iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336

 4274 13:58:21.670444  iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320

 4275 13:58:21.673782  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4276 13:58:21.676675  ==

 4277 13:58:21.680011  Dram Type= 6, Freq= 0, CH_0, rank 1

 4278 13:58:21.683353  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4279 13:58:21.683473  ==

 4280 13:58:21.683537  DQS Delay:

 4281 13:58:21.687119  DQS0 = 0, DQS1 = 0

 4282 13:58:21.687200  DQM Delay:

 4283 13:58:21.689867  DQM0 = 35, DQM1 = 28

 4284 13:58:21.689949  DQ Delay:

 4285 13:58:21.693570  DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33

 4286 13:58:21.696922  DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49

 4287 13:58:21.699893  DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =17

 4288 13:58:21.703420  DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41

 4289 13:58:21.703502  

 4290 13:58:21.703567  

 4291 13:58:21.703627  ==

 4292 13:58:21.706644  Dram Type= 6, Freq= 0, CH_0, rank 1

 4293 13:58:21.710224  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4294 13:58:21.710305  ==

 4295 13:58:21.710370  

 4296 13:58:21.710429  

 4297 13:58:21.713134  	TX Vref Scan disable

 4298 13:58:21.716815   == TX Byte 0 ==

 4299 13:58:21.719806  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4300 13:58:21.723135  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4301 13:58:21.726624   == TX Byte 1 ==

 4302 13:58:21.729655  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4303 13:58:21.733045  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4304 13:58:21.733125  ==

 4305 13:58:21.736283  Dram Type= 6, Freq= 0, CH_0, rank 1

 4306 13:58:21.742786  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4307 13:58:21.742868  ==

 4308 13:58:21.742933  

 4309 13:58:21.742991  

 4310 13:58:21.743048  	TX Vref Scan disable

 4311 13:58:21.747212   == TX Byte 0 ==

 4312 13:58:21.750663  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4313 13:58:21.754228  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4314 13:58:21.757249   == TX Byte 1 ==

 4315 13:58:21.760486  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4316 13:58:21.764282  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4317 13:58:21.767104  

 4318 13:58:21.767183  [DATLAT]

 4319 13:58:21.767249  Freq=600, CH0 RK1

 4320 13:58:21.767310  

 4321 13:58:21.770612  DATLAT Default: 0x9

 4322 13:58:21.770684  0, 0xFFFF, sum = 0

 4323 13:58:21.773959  1, 0xFFFF, sum = 0

 4324 13:58:21.774041  2, 0xFFFF, sum = 0

 4325 13:58:21.777336  3, 0xFFFF, sum = 0

 4326 13:58:21.777418  4, 0xFFFF, sum = 0

 4327 13:58:21.780888  5, 0xFFFF, sum = 0

 4328 13:58:21.783904  6, 0xFFFF, sum = 0

 4329 13:58:21.783986  7, 0xFFFF, sum = 0

 4330 13:58:21.784051  8, 0x0, sum = 1

 4331 13:58:21.787176  9, 0x0, sum = 2

 4332 13:58:21.787258  10, 0x0, sum = 3

 4333 13:58:21.790997  11, 0x0, sum = 4

 4334 13:58:21.791079  best_step = 9

 4335 13:58:21.791143  

 4336 13:58:21.791202  ==

 4337 13:58:21.793954  Dram Type= 6, Freq= 0, CH_0, rank 1

 4338 13:58:21.800255  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4339 13:58:21.800337  ==

 4340 13:58:21.800400  RX Vref Scan: 0

 4341 13:58:21.800460  

 4342 13:58:21.803899  RX Vref 0 -> 0, step: 1

 4343 13:58:21.803980  

 4344 13:58:21.807218  RX Delay -195 -> 252, step: 8

 4345 13:58:21.810438  iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320

 4346 13:58:21.817121  iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320

 4347 13:58:21.820561  iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312

 4348 13:58:21.823561  iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320

 4349 13:58:21.827295  iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312

 4350 13:58:21.833862  iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320

 4351 13:58:21.836880  iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320

 4352 13:58:21.840154  iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320

 4353 13:58:21.843563  iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320

 4354 13:58:21.846926  iDelay=205, Bit 9, Center 8 (-147 ~ 164) 312

 4355 13:58:21.853744  iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320

 4356 13:58:21.856578  iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320

 4357 13:58:21.860121  iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320

 4358 13:58:21.863181  iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320

 4359 13:58:21.869958  iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320

 4360 13:58:21.873106  iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320

 4361 13:58:21.873189  ==

 4362 13:58:21.876633  Dram Type= 6, Freq= 0, CH_0, rank 1

 4363 13:58:21.880041  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4364 13:58:21.880135  ==

 4365 13:58:21.883528  DQS Delay:

 4366 13:58:21.883635  DQS0 = 0, DQS1 = 0

 4367 13:58:21.883725  DQM Delay:

 4368 13:58:21.886331  DQM0 = 33, DQM1 = 27

 4369 13:58:21.886428  DQ Delay:

 4370 13:58:21.889871  DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28

 4371 13:58:21.893271  DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44

 4372 13:58:21.896963  DQ8 =20, DQ9 =8, DQ10 =28, DQ11 =20

 4373 13:58:21.899926  DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36

 4374 13:58:21.900007  

 4375 13:58:21.900072  

 4376 13:58:21.909736  [DQSOSCAuto] RK1, (LSB)MR18= 0x6e3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps

 4377 13:58:21.913083  CH0 RK1: MR19=808, MR18=6E3D

 4378 13:58:21.916037  CH0_RK1: MR19=0x808, MR18=0x6E3D, DQSOSC=389, MR23=63, INC=173, DEC=115

 4379 13:58:21.919490  [RxdqsGatingPostProcess] freq 600

 4380 13:58:21.925970  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4381 13:58:21.929329  Pre-setting of DQS Precalculation

 4382 13:58:21.932932  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4383 13:58:21.933013  ==

 4384 13:58:21.936398  Dram Type= 6, Freq= 0, CH_1, rank 0

 4385 13:58:21.943166  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4386 13:58:21.943278  ==

 4387 13:58:21.945910  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4388 13:58:21.952778  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4389 13:58:21.956270  [CA 0] Center 35 (5~66) winsize 62

 4390 13:58:21.959283  [CA 1] Center 35 (5~66) winsize 62

 4391 13:58:21.962674  [CA 2] Center 34 (4~65) winsize 62

 4392 13:58:21.966037  [CA 3] Center 34 (3~65) winsize 63

 4393 13:58:21.969596  [CA 4] Center 34 (4~65) winsize 62

 4394 13:58:21.972811  [CA 5] Center 33 (3~64) winsize 62

 4395 13:58:21.972893  

 4396 13:58:21.976060  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4397 13:58:21.976142  

 4398 13:58:21.979281  [CATrainingPosCal] consider 1 rank data

 4399 13:58:21.982773  u2DelayCellTimex100 = 270/100 ps

 4400 13:58:21.985997  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4401 13:58:21.992738  CA1 delay=35 (5~66),Diff = 2 PI (19 cell)

 4402 13:58:21.995843  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4403 13:58:21.999302  CA3 delay=34 (3~65),Diff = 1 PI (9 cell)

 4404 13:58:22.002889  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4405 13:58:22.005749  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4406 13:58:22.005831  

 4407 13:58:22.009442  CA PerBit enable=1, Macro0, CA PI delay=33

 4408 13:58:22.009524  

 4409 13:58:22.012497  [CBTSetCACLKResult] CA Dly = 33

 4410 13:58:22.012579  CS Dly: 5 (0~36)

 4411 13:58:22.016011  ==

 4412 13:58:22.019509  Dram Type= 6, Freq= 0, CH_1, rank 1

 4413 13:58:22.022565  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4414 13:58:22.022648  ==

 4415 13:58:22.025865  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4416 13:58:22.032504  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4417 13:58:22.036577  [CA 0] Center 36 (6~66) winsize 61

 4418 13:58:22.039527  [CA 1] Center 36 (6~66) winsize 61

 4419 13:58:22.043098  [CA 2] Center 34 (4~65) winsize 62

 4420 13:58:22.046041  [CA 3] Center 33 (3~64) winsize 62

 4421 13:58:22.049517  [CA 4] Center 34 (4~65) winsize 62

 4422 13:58:22.052830  [CA 5] Center 33 (3~64) winsize 62

 4423 13:58:22.052911  

 4424 13:58:22.056233  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4425 13:58:22.056315  

 4426 13:58:22.059282  [CATrainingPosCal] consider 2 rank data

 4427 13:58:22.062697  u2DelayCellTimex100 = 270/100 ps

 4428 13:58:22.065807  CA0 delay=36 (6~66),Diff = 3 PI (28 cell)

 4429 13:58:22.072642  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 4430 13:58:22.076068  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4431 13:58:22.079406  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 4432 13:58:22.082520  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4433 13:58:22.085942  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4434 13:58:22.086085  

 4435 13:58:22.089512  CA PerBit enable=1, Macro0, CA PI delay=33

 4436 13:58:22.089594  

 4437 13:58:22.092514  [CBTSetCACLKResult] CA Dly = 33

 4438 13:58:22.092595  CS Dly: 5 (0~37)

 4439 13:58:22.095916  

 4440 13:58:22.099603  ----->DramcWriteLeveling(PI) begin...

 4441 13:58:22.099685  ==

 4442 13:58:22.102412  Dram Type= 6, Freq= 0, CH_1, rank 0

 4443 13:58:22.106134  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4444 13:58:22.106216  ==

 4445 13:58:22.109013  Write leveling (Byte 0): 30 => 30

 4446 13:58:22.112626  Write leveling (Byte 1): 29 => 29

 4447 13:58:22.115514  DramcWriteLeveling(PI) end<-----

 4448 13:58:22.115595  

 4449 13:58:22.115659  ==

 4450 13:58:22.119009  Dram Type= 6, Freq= 0, CH_1, rank 0

 4451 13:58:22.122365  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4452 13:58:22.122447  ==

 4453 13:58:22.125770  [Gating] SW mode calibration

 4454 13:58:22.132440  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4455 13:58:22.139153  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4456 13:58:22.142109   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4457 13:58:22.145611   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4458 13:58:22.152148   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4459 13:58:22.155638   0  9 12 | B1->B0 | 3232 3131 | 0 0 | (0 0) (0 0)

 4460 13:58:22.159071   0  9 16 | B1->B0 | 2929 2323 | 0 1 | (0 0) (1 0)

 4461 13:58:22.162293   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4462 13:58:22.169259   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4463 13:58:22.172568   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4464 13:58:22.175515   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4465 13:58:22.182497   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4466 13:58:22.185879   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4467 13:58:22.189126   0 10 12 | B1->B0 | 2f2e 3030 | 1 0 | (0 0) (1 1)

 4468 13:58:22.195740   0 10 16 | B1->B0 | 4141 4242 | 0 0 | (0 0) (0 0)

 4469 13:58:22.198734   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4470 13:58:22.202805   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4471 13:58:22.209265   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4472 13:58:22.212205   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4473 13:58:22.215695   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4474 13:58:22.222289   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4475 13:58:22.225505   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 4476 13:58:22.228532   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4477 13:58:22.235011   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4478 13:58:22.238423   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4479 13:58:22.241846   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4480 13:58:22.248706   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4481 13:58:22.251557   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4482 13:58:22.255159   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4483 13:58:22.261726   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4484 13:58:22.264844   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4485 13:58:22.268358   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4486 13:58:22.275415   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4487 13:58:22.278499   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4488 13:58:22.281665   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4489 13:58:22.288300   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4490 13:58:22.291643   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4491 13:58:22.294593   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4492 13:58:22.301619   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4493 13:58:22.301716  Total UI for P1: 0, mck2ui 16

 4494 13:58:22.308080  best dqsien dly found for B0: ( 0, 13, 12)

 4495 13:58:22.308162  Total UI for P1: 0, mck2ui 16

 4496 13:58:22.311644  best dqsien dly found for B1: ( 0, 13, 12)

 4497 13:58:22.318257  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4498 13:58:22.321272  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4499 13:58:22.321353  

 4500 13:58:22.324912  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4501 13:58:22.328185  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4502 13:58:22.331283  [Gating] SW calibration Done

 4503 13:58:22.331364  ==

 4504 13:58:22.334853  Dram Type= 6, Freq= 0, CH_1, rank 0

 4505 13:58:22.337880  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4506 13:58:22.337961  ==

 4507 13:58:22.341408  RX Vref Scan: 0

 4508 13:58:22.341489  

 4509 13:58:22.341553  RX Vref 0 -> 0, step: 1

 4510 13:58:22.341614  

 4511 13:58:22.344641  RX Delay -230 -> 252, step: 16

 4512 13:58:22.351350  iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336

 4513 13:58:22.354641  iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336

 4514 13:58:22.358123  iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352

 4515 13:58:22.361107  iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336

 4516 13:58:22.364618  iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336

 4517 13:58:22.371434  iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336

 4518 13:58:22.374324  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4519 13:58:22.377844  iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336

 4520 13:58:22.381245  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4521 13:58:22.384476  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4522 13:58:22.390751  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4523 13:58:22.394205  iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352

 4524 13:58:22.397424  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4525 13:58:22.404301  iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336

 4526 13:58:22.407647  iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336

 4527 13:58:22.410911  iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336

 4528 13:58:22.410992  ==

 4529 13:58:22.414273  Dram Type= 6, Freq= 0, CH_1, rank 0

 4530 13:58:22.417514  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4531 13:58:22.417595  ==

 4532 13:58:22.421109  DQS Delay:

 4533 13:58:22.421190  DQS0 = 0, DQS1 = 0

 4534 13:58:22.424538  DQM Delay:

 4535 13:58:22.424635  DQM0 = 38, DQM1 = 28

 4536 13:58:22.424701  DQ Delay:

 4537 13:58:22.427717  DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33

 4538 13:58:22.430989  DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33

 4539 13:58:22.434355  DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25

 4540 13:58:22.437492  DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33

 4541 13:58:22.437573  

 4542 13:58:22.437637  

 4543 13:58:22.440774  ==

 4544 13:58:22.440857  Dram Type= 6, Freq= 0, CH_1, rank 0

 4545 13:58:22.447158  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4546 13:58:22.447264  ==

 4547 13:58:22.447357  

 4548 13:58:22.447470  

 4549 13:58:22.450491  	TX Vref Scan disable

 4550 13:58:22.450566   == TX Byte 0 ==

 4551 13:58:22.453963  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4552 13:58:22.460466  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4553 13:58:22.460540   == TX Byte 1 ==

 4554 13:58:22.466988  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4555 13:58:22.470677  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4556 13:58:22.470774  ==

 4557 13:58:22.473910  Dram Type= 6, Freq= 0, CH_1, rank 0

 4558 13:58:22.476722  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4559 13:58:22.476825  ==

 4560 13:58:22.476915  

 4561 13:58:22.477001  

 4562 13:58:22.480408  	TX Vref Scan disable

 4563 13:58:22.483590   == TX Byte 0 ==

 4564 13:58:22.486929  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4565 13:58:22.490510  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4566 13:58:22.493409   == TX Byte 1 ==

 4567 13:58:22.496905  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4568 13:58:22.500029  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4569 13:58:22.500127  

 4570 13:58:22.503555  [DATLAT]

 4571 13:58:22.503628  Freq=600, CH1 RK0

 4572 13:58:22.503690  

 4573 13:58:22.506772  DATLAT Default: 0x9

 4574 13:58:22.506875  0, 0xFFFF, sum = 0

 4575 13:58:22.509955  1, 0xFFFF, sum = 0

 4576 13:58:22.510028  2, 0xFFFF, sum = 0

 4577 13:58:22.513129  3, 0xFFFF, sum = 0

 4578 13:58:22.513205  4, 0xFFFF, sum = 0

 4579 13:58:22.516306  5, 0xFFFF, sum = 0

 4580 13:58:22.516375  6, 0xFFFF, sum = 0

 4581 13:58:22.520023  7, 0xFFFF, sum = 0

 4582 13:58:22.520099  8, 0x0, sum = 1

 4583 13:58:22.522968  9, 0x0, sum = 2

 4584 13:58:22.523051  10, 0x0, sum = 3

 4585 13:58:22.526556  11, 0x0, sum = 4

 4586 13:58:22.526652  best_step = 9

 4587 13:58:22.526718  

 4588 13:58:22.526778  ==

 4589 13:58:22.529726  Dram Type= 6, Freq= 0, CH_1, rank 0

 4590 13:58:22.536189  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4591 13:58:22.536271  ==

 4592 13:58:22.536352  RX Vref Scan: 1

 4593 13:58:22.536414  

 4594 13:58:22.539594  RX Vref 0 -> 0, step: 1

 4595 13:58:22.539676  

 4596 13:58:22.543364  RX Delay -195 -> 252, step: 8

 4597 13:58:22.543479  

 4598 13:58:22.546502  Set Vref, RX VrefLevel [Byte0]: 59

 4599 13:58:22.549633                           [Byte1]: 57

 4600 13:58:22.549715  

 4601 13:58:22.552727  Final RX Vref Byte 0 = 59 to rank0

 4602 13:58:22.556839  Final RX Vref Byte 1 = 57 to rank0

 4603 13:58:22.559798  Final RX Vref Byte 0 = 59 to rank1

 4604 13:58:22.563224  Final RX Vref Byte 1 = 57 to rank1==

 4605 13:58:22.566247  Dram Type= 6, Freq= 0, CH_1, rank 0

 4606 13:58:22.569662  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4607 13:58:22.569744  ==

 4608 13:58:22.572727  DQS Delay:

 4609 13:58:22.572808  DQS0 = 0, DQS1 = 0

 4610 13:58:22.576236  DQM Delay:

 4611 13:58:22.576317  DQM0 = 39, DQM1 = 28

 4612 13:58:22.576381  DQ Delay:

 4613 13:58:22.579612  DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36

 4614 13:58:22.582306  DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36

 4615 13:58:22.586297  DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20

 4616 13:58:22.589062  DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36

 4617 13:58:22.589144  

 4618 13:58:22.589208  

 4619 13:58:22.599071  [DQSOSCAuto] RK0, (LSB)MR18= 0x202d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps

 4620 13:58:22.602577  CH1 RK0: MR19=808, MR18=202D

 4621 13:58:22.609364  CH1_RK0: MR19=0x808, MR18=0x202D, DQSOSC=401, MR23=63, INC=163, DEC=108

 4622 13:58:22.609446  

 4623 13:58:22.612675  ----->DramcWriteLeveling(PI) begin...

 4624 13:58:22.612754  ==

 4625 13:58:22.616013  Dram Type= 6, Freq= 0, CH_1, rank 1

 4626 13:58:22.618994  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4627 13:58:22.619066  ==

 4628 13:58:22.622179  Write leveling (Byte 0): 29 => 29

 4629 13:58:22.626097  Write leveling (Byte 1): 30 => 30

 4630 13:58:22.628990  DramcWriteLeveling(PI) end<-----

 4631 13:58:22.629071  

 4632 13:58:22.629134  ==

 4633 13:58:22.632431  Dram Type= 6, Freq= 0, CH_1, rank 1

 4634 13:58:22.635605  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4635 13:58:22.635677  ==

 4636 13:58:22.639182  [Gating] SW mode calibration

 4637 13:58:22.645185  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4638 13:58:22.652033  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4639 13:58:22.655376   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4640 13:58:22.658570   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4641 13:58:22.665598   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4642 13:58:22.668438   0  9 12 | B1->B0 | 3232 2e2e | 1 1 | (1 0) (1 0)

 4643 13:58:22.671682   0  9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)

 4644 13:58:22.678377   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4645 13:58:22.682007   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4646 13:58:22.684952   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4647 13:58:22.691905   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4648 13:58:22.695519   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4649 13:58:22.698467   0 10  8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)

 4650 13:58:22.704877   0 10 12 | B1->B0 | 2c2c 3b3b | 1 0 | (0 0) (0 0)

 4651 13:58:22.708675   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4652 13:58:22.712083   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4653 13:58:22.718693   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4654 13:58:22.721903   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4655 13:58:22.725378   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4656 13:58:22.731411   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4657 13:58:22.734715   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4658 13:58:22.738233   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4659 13:58:22.744978   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4660 13:58:22.748054   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4661 13:58:22.751519   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4662 13:58:22.758254   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4663 13:58:22.761328   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4664 13:58:22.764536   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4665 13:58:22.768416   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4666 13:58:22.775256   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4667 13:58:22.778126   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4668 13:58:22.781382   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4669 13:58:22.788561   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4670 13:58:22.791535   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4671 13:58:22.794732   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4672 13:58:22.801355   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4673 13:58:22.804728   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4674 13:58:22.807681   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4675 13:58:22.811506  Total UI for P1: 0, mck2ui 16

 4676 13:58:22.814337  best dqsien dly found for B0: ( 0, 13, 10)

 4677 13:58:22.821355   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4678 13:58:22.821467  Total UI for P1: 0, mck2ui 16

 4679 13:58:22.827628  best dqsien dly found for B1: ( 0, 13, 12)

 4680 13:58:22.831506  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4681 13:58:22.834279  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4682 13:58:22.834361  

 4683 13:58:22.837820  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4684 13:58:22.841453  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4685 13:58:22.844435  [Gating] SW calibration Done

 4686 13:58:22.844516  ==

 4687 13:58:22.848016  Dram Type= 6, Freq= 0, CH_1, rank 1

 4688 13:58:22.851203  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4689 13:58:22.851312  ==

 4690 13:58:22.854667  RX Vref Scan: 0

 4691 13:58:22.854749  

 4692 13:58:22.854814  RX Vref 0 -> 0, step: 1

 4693 13:58:22.854875  

 4694 13:58:22.858079  RX Delay -230 -> 252, step: 16

 4695 13:58:22.864272  iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352

 4696 13:58:22.867994  iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336

 4697 13:58:22.871548  iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336

 4698 13:58:22.874223  iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336

 4699 13:58:22.877799  iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336

 4700 13:58:22.884404  iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336

 4701 13:58:22.887576  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4702 13:58:22.891120  iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336

 4703 13:58:22.894121  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4704 13:58:22.900776  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4705 13:58:22.904581  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4706 13:58:22.907796  iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352

 4707 13:58:22.910693  iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352

 4708 13:58:22.917756  iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352

 4709 13:58:22.920928  iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352

 4710 13:58:22.924206  iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352

 4711 13:58:22.924288  ==

 4712 13:58:22.927269  Dram Type= 6, Freq= 0, CH_1, rank 1

 4713 13:58:22.930712  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4714 13:58:22.934172  ==

 4715 13:58:22.934253  DQS Delay:

 4716 13:58:22.934317  DQS0 = 0, DQS1 = 0

 4717 13:58:22.937498  DQM Delay:

 4718 13:58:22.937578  DQM0 = 36, DQM1 = 32

 4719 13:58:22.940867  DQ Delay:

 4720 13:58:22.940947  DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33

 4721 13:58:22.944370  DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33

 4722 13:58:22.947223  DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25

 4723 13:58:22.950767  DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41

 4724 13:58:22.950848  

 4725 13:58:22.953738  

 4726 13:58:22.953818  ==

 4727 13:58:22.957377  Dram Type= 6, Freq= 0, CH_1, rank 1

 4728 13:58:22.960773  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4729 13:58:22.960855  ==

 4730 13:58:22.960920  

 4731 13:58:22.960979  

 4732 13:58:22.964080  	TX Vref Scan disable

 4733 13:58:22.964161   == TX Byte 0 ==

 4734 13:58:22.970406  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4735 13:58:22.973820  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4736 13:58:22.973901   == TX Byte 1 ==

 4737 13:58:22.980230  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4738 13:58:22.983664  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4739 13:58:22.983746  ==

 4740 13:58:22.987126  Dram Type= 6, Freq= 0, CH_1, rank 1

 4741 13:58:22.990578  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4742 13:58:22.990660  ==

 4743 13:58:22.990755  

 4744 13:58:22.990857  

 4745 13:58:22.993797  	TX Vref Scan disable

 4746 13:58:22.996798   == TX Byte 0 ==

 4747 13:58:23.000235  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4748 13:58:23.003584  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4749 13:58:23.006708   == TX Byte 1 ==

 4750 13:58:23.010016  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4751 13:58:23.013105  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4752 13:58:23.016841  

 4753 13:58:23.016943  [DATLAT]

 4754 13:58:23.017034  Freq=600, CH1 RK1

 4755 13:58:23.017132  

 4756 13:58:23.020283  DATLAT Default: 0x9

 4757 13:58:23.020372  0, 0xFFFF, sum = 0

 4758 13:58:23.023162  1, 0xFFFF, sum = 0

 4759 13:58:23.023270  2, 0xFFFF, sum = 0

 4760 13:58:23.026612  3, 0xFFFF, sum = 0

 4761 13:58:23.026716  4, 0xFFFF, sum = 0

 4762 13:58:23.030224  5, 0xFFFF, sum = 0

 4763 13:58:23.033013  6, 0xFFFF, sum = 0

 4764 13:58:23.033120  7, 0xFFFF, sum = 0

 4765 13:58:23.033212  8, 0x0, sum = 1

 4766 13:58:23.036517  9, 0x0, sum = 2

 4767 13:58:23.036591  10, 0x0, sum = 3

 4768 13:58:23.040068  11, 0x0, sum = 4

 4769 13:58:23.040171  best_step = 9

 4770 13:58:23.040264  

 4771 13:58:23.040350  ==

 4772 13:58:23.043192  Dram Type= 6, Freq= 0, CH_1, rank 1

 4773 13:58:23.050017  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4774 13:58:23.050127  ==

 4775 13:58:23.050221  RX Vref Scan: 0

 4776 13:58:23.050310  

 4777 13:58:23.052951  RX Vref 0 -> 0, step: 1

 4778 13:58:23.053048  

 4779 13:58:23.056413  RX Delay -195 -> 252, step: 8

 4780 13:58:23.060085  iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312

 4781 13:58:23.066231  iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312

 4782 13:58:23.069711  iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312

 4783 13:58:23.073189  iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312

 4784 13:58:23.076047  iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312

 4785 13:58:23.082681  iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320

 4786 13:58:23.086243  iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320

 4787 13:58:23.089599  iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320

 4788 13:58:23.092779  iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328

 4789 13:58:23.096178  iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328

 4790 13:58:23.103080  iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328

 4791 13:58:23.105986  iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328

 4792 13:58:23.109415  iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320

 4793 13:58:23.112478  iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320

 4794 13:58:23.119132  iDelay=205, Bit 14, Center 32 (-131 ~ 196) 328

 4795 13:58:23.122513  iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320

 4796 13:58:23.122604  ==

 4797 13:58:23.125674  Dram Type= 6, Freq= 0, CH_1, rank 1

 4798 13:58:23.129020  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4799 13:58:23.129107  ==

 4800 13:58:23.132493  DQS Delay:

 4801 13:58:23.132575  DQS0 = 0, DQS1 = 0

 4802 13:58:23.132641  DQM Delay:

 4803 13:58:23.135918  DQM0 = 35, DQM1 = 28

 4804 13:58:23.136000  DQ Delay:

 4805 13:58:23.139638  DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32

 4806 13:58:23.142518  DQ4 =32, DQ5 =44, DQ6 =44, DQ7 =36

 4807 13:58:23.146051  DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =24

 4808 13:58:23.149354  DQ12 =36, DQ13 =36, DQ14 =32, DQ15 =36

 4809 13:58:23.149436  

 4810 13:58:23.149500  

 4811 13:58:23.158918  [DQSOSCAuto] RK1, (LSB)MR18= 0x3958, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps

 4812 13:58:23.162658  CH1 RK1: MR19=808, MR18=3958

 4813 13:58:23.166022  CH1_RK1: MR19=0x808, MR18=0x3958, DQSOSC=393, MR23=63, INC=169, DEC=113

 4814 13:58:23.169053  [RxdqsGatingPostProcess] freq 600

 4815 13:58:23.175530  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4816 13:58:23.179108  Pre-setting of DQS Precalculation

 4817 13:58:23.182050  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4818 13:58:23.192121  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4819 13:58:23.198698  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4820 13:58:23.198780  

 4821 13:58:23.198844  

 4822 13:58:23.202266  [Calibration Summary] 1200 Mbps

 4823 13:58:23.202347  CH 0, Rank 0

 4824 13:58:23.205631  SW Impedance     : PASS

 4825 13:58:23.205712  DUTY Scan        : NO K

 4826 13:58:23.208792  ZQ Calibration   : PASS

 4827 13:58:23.212181  Jitter Meter     : NO K

 4828 13:58:23.212263  CBT Training     : PASS

 4829 13:58:23.215111  Write leveling   : PASS

 4830 13:58:23.218846  RX DQS gating    : PASS

 4831 13:58:23.218929  RX DQ/DQS(RDDQC) : PASS

 4832 13:58:23.222319  TX DQ/DQS        : PASS

 4833 13:58:23.225908  RX DATLAT        : PASS

 4834 13:58:23.225990  RX DQ/DQS(Engine): PASS

 4835 13:58:23.228370  TX OE            : NO K

 4836 13:58:23.228453  All Pass.

 4837 13:58:23.228518  

 4838 13:58:23.231951  CH 0, Rank 1

 4839 13:58:23.232058  SW Impedance     : PASS

 4840 13:58:23.235156  DUTY Scan        : NO K

 4841 13:58:23.235238  ZQ Calibration   : PASS

 4842 13:58:23.238455  Jitter Meter     : NO K

 4843 13:58:23.241790  CBT Training     : PASS

 4844 13:58:23.241872  Write leveling   : PASS

 4845 13:58:23.245385  RX DQS gating    : PASS

 4846 13:58:23.248828  RX DQ/DQS(RDDQC) : PASS

 4847 13:58:23.248910  TX DQ/DQS        : PASS

 4848 13:58:23.252448  RX DATLAT        : PASS

 4849 13:58:23.255249  RX DQ/DQS(Engine): PASS

 4850 13:58:23.255330  TX OE            : NO K

 4851 13:58:23.258952  All Pass.

 4852 13:58:23.259033  

 4853 13:58:23.259097  CH 1, Rank 0

 4854 13:58:23.262045  SW Impedance     : PASS

 4855 13:58:23.262155  DUTY Scan        : NO K

 4856 13:58:23.264889  ZQ Calibration   : PASS

 4857 13:58:23.268518  Jitter Meter     : NO K

 4858 13:58:23.268619  CBT Training     : PASS

 4859 13:58:23.271974  Write leveling   : PASS

 4860 13:58:23.275017  RX DQS gating    : PASS

 4861 13:58:23.275114  RX DQ/DQS(RDDQC) : PASS

 4862 13:58:23.278275  TX DQ/DQS        : PASS

 4863 13:58:23.281756  RX DATLAT        : PASS

 4864 13:58:23.281867  RX DQ/DQS(Engine): PASS

 4865 13:58:23.285316  TX OE            : NO K

 4866 13:58:23.285391  All Pass.

 4867 13:58:23.285466  

 4868 13:58:23.285556  CH 1, Rank 1

 4869 13:58:23.289077  SW Impedance     : PASS

 4870 13:58:23.291674  DUTY Scan        : NO K

 4871 13:58:23.291747  ZQ Calibration   : PASS

 4872 13:58:23.295323  Jitter Meter     : NO K

 4873 13:58:23.298468  CBT Training     : PASS

 4874 13:58:23.298551  Write leveling   : PASS

 4875 13:58:23.301715  RX DQS gating    : PASS

 4876 13:58:23.305138  RX DQ/DQS(RDDQC) : PASS

 4877 13:58:23.305235  TX DQ/DQS        : PASS

 4878 13:58:23.308473  RX DATLAT        : PASS

 4879 13:58:23.311839  RX DQ/DQS(Engine): PASS

 4880 13:58:23.311922  TX OE            : NO K

 4881 13:58:23.314937  All Pass.

 4882 13:58:23.315019  

 4883 13:58:23.315084  DramC Write-DBI off

 4884 13:58:23.318453  	PER_BANK_REFRESH: Hybrid Mode

 4885 13:58:23.318535  TX_TRACKING: ON

 4886 13:58:23.328481  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4887 13:58:23.331751  [FAST_K] Save calibration result to emmc

 4888 13:58:23.335065  dramc_set_vcore_voltage set vcore to 662500

 4889 13:58:23.338465  Read voltage for 933, 3

 4890 13:58:23.338541  Vio18 = 0

 4891 13:58:23.341371  Vcore = 662500

 4892 13:58:23.341449  Vdram = 0

 4893 13:58:23.341513  Vddq = 0

 4894 13:58:23.345114  Vmddr = 0

 4895 13:58:23.348601  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4896 13:58:23.354927  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4897 13:58:23.355003  MEM_TYPE=3, freq_sel=17

 4898 13:58:23.358274  sv_algorithm_assistance_LP4_1600 

 4899 13:58:23.364429  ============ PULL DRAM RESETB DOWN ============

 4900 13:58:23.368276  ========== PULL DRAM RESETB DOWN end =========

 4901 13:58:23.371340  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4902 13:58:23.374693  =================================== 

 4903 13:58:23.377795  LPDDR4 DRAM CONFIGURATION

 4904 13:58:23.381243  =================================== 

 4905 13:58:23.381332  EX_ROW_EN[0]    = 0x0

 4906 13:58:23.384636  EX_ROW_EN[1]    = 0x0

 4907 13:58:23.388127  LP4Y_EN      = 0x0

 4908 13:58:23.388200  WORK_FSP     = 0x0

 4909 13:58:23.391142  WL           = 0x3

 4910 13:58:23.391225  RL           = 0x3

 4911 13:58:23.394572  BL           = 0x2

 4912 13:58:23.394644  RPST         = 0x0

 4913 13:58:23.397693  RD_PRE       = 0x0

 4914 13:58:23.397765  WR_PRE       = 0x1

 4915 13:58:23.401151  WR_PST       = 0x0

 4916 13:58:23.401232  DBI_WR       = 0x0

 4917 13:58:23.404704  DBI_RD       = 0x0

 4918 13:58:23.404801  OTF          = 0x1

 4919 13:58:23.407586  =================================== 

 4920 13:58:23.410911  =================================== 

 4921 13:58:23.414177  ANA top config

 4922 13:58:23.417583  =================================== 

 4923 13:58:23.417656  DLL_ASYNC_EN            =  0

 4924 13:58:23.420911  ALL_SLAVE_EN            =  1

 4925 13:58:23.424306  NEW_RANK_MODE           =  1

 4926 13:58:23.427835  DLL_IDLE_MODE           =  1

 4927 13:58:23.431172  LP45_APHY_COMB_EN       =  1

 4928 13:58:23.431274  TX_ODT_DIS              =  1

 4929 13:58:23.434021  NEW_8X_MODE             =  1

 4930 13:58:23.437761  =================================== 

 4931 13:58:23.441145  =================================== 

 4932 13:58:23.443871  data_rate                  = 1866

 4933 13:58:23.447298  CKR                        = 1

 4934 13:58:23.450743  DQ_P2S_RATIO               = 8

 4935 13:58:23.453864  =================================== 

 4936 13:58:23.457267  CA_P2S_RATIO               = 8

 4937 13:58:23.457340  DQ_CA_OPEN                 = 0

 4938 13:58:23.460921  DQ_SEMI_OPEN               = 0

 4939 13:58:23.464382  CA_SEMI_OPEN               = 0

 4940 13:58:23.467433  CA_FULL_RATE               = 0

 4941 13:58:23.470668  DQ_CKDIV4_EN               = 1

 4942 13:58:23.470740  CA_CKDIV4_EN               = 1

 4943 13:58:23.473810  CA_PREDIV_EN               = 0

 4944 13:58:23.477369  PH8_DLY                    = 0

 4945 13:58:23.480724  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4946 13:58:23.483741  DQ_AAMCK_DIV               = 4

 4947 13:58:23.487318  CA_AAMCK_DIV               = 4

 4948 13:58:23.487448  CA_ADMCK_DIV               = 4

 4949 13:58:23.490628  DQ_TRACK_CA_EN             = 0

 4950 13:58:23.494535  CA_PICK                    = 933

 4951 13:58:23.497238  CA_MCKIO                   = 933

 4952 13:58:23.500891  MCKIO_SEMI                 = 0

 4953 13:58:23.504037  PLL_FREQ                   = 3732

 4954 13:58:23.507537  DQ_UI_PI_RATIO             = 32

 4955 13:58:23.507620  CA_UI_PI_RATIO             = 0

 4956 13:58:23.510265  =================================== 

 4957 13:58:23.513775  =================================== 

 4958 13:58:23.517179  memory_type:LPDDR4         

 4959 13:58:23.520422  GP_NUM     : 10       

 4960 13:58:23.520505  SRAM_EN    : 1       

 4961 13:58:23.524292  MD32_EN    : 0       

 4962 13:58:23.527414  =================================== 

 4963 13:58:23.530928  [ANA_INIT] >>>>>>>>>>>>>> 

 4964 13:58:23.533494  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4965 13:58:23.536923  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4966 13:58:23.540140  =================================== 

 4967 13:58:23.540223  data_rate = 1866,PCW = 0X8f00

 4968 13:58:23.543684  =================================== 

 4969 13:58:23.550477  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4970 13:58:23.553445  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4971 13:58:23.560548  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4972 13:58:23.563508  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4973 13:58:23.567069  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4974 13:58:23.569797  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4975 13:58:23.573471  [ANA_INIT] flow start 

 4976 13:58:23.577036  [ANA_INIT] PLL >>>>>>>> 

 4977 13:58:23.577119  [ANA_INIT] PLL <<<<<<<< 

 4978 13:58:23.580087  [ANA_INIT] MIDPI >>>>>>>> 

 4979 13:58:23.583870  [ANA_INIT] MIDPI <<<<<<<< 

 4980 13:58:23.583953  [ANA_INIT] DLL >>>>>>>> 

 4981 13:58:23.586905  [ANA_INIT] flow end 

 4982 13:58:23.589978  ============ LP4 DIFF to SE enter ============

 4983 13:58:23.596404  ============ LP4 DIFF to SE exit  ============

 4984 13:58:23.596487  [ANA_INIT] <<<<<<<<<<<<< 

 4985 13:58:23.599689  [Flow] Enable top DCM control >>>>> 

 4986 13:58:23.602840  [Flow] Enable top DCM control <<<<< 

 4987 13:58:23.606281  Enable DLL master slave shuffle 

 4988 13:58:23.612798  ============================================================== 

 4989 13:58:23.612881  Gating Mode config

 4990 13:58:23.619714  ============================================================== 

 4991 13:58:23.622664  Config description: 

 4992 13:58:23.629353  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4993 13:58:23.635800  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4994 13:58:23.642911  SELPH_MODE            0: By rank         1: By Phase 

 4995 13:58:23.649353  ============================================================== 

 4996 13:58:23.652689  GAT_TRACK_EN                 =  1

 4997 13:58:23.652772  RX_GATING_MODE               =  2

 4998 13:58:23.655997  RX_GATING_TRACK_MODE         =  2

 4999 13:58:23.659934  SELPH_MODE                   =  1

 5000 13:58:23.662608  PICG_EARLY_EN                =  1

 5001 13:58:23.666052  VALID_LAT_VALUE              =  1

 5002 13:58:23.672538  ============================================================== 

 5003 13:58:23.675671  Enter into Gating configuration >>>> 

 5004 13:58:23.679190  Exit from Gating configuration <<<< 

 5005 13:58:23.682554  Enter into  DVFS_PRE_config >>>>> 

 5006 13:58:23.692241  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 5007 13:58:23.695496  Exit from  DVFS_PRE_config <<<<< 

 5008 13:58:23.699141  Enter into PICG configuration >>>> 

 5009 13:58:23.702671  Exit from PICG configuration <<<< 

 5010 13:58:23.705690  [RX_INPUT] configuration >>>>> 

 5011 13:58:23.708832  [RX_INPUT] configuration <<<<< 

 5012 13:58:23.712280  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 5013 13:58:23.718929  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 5014 13:58:23.725667  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 5015 13:58:23.729140  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 5016 13:58:23.735620  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 5017 13:58:23.741998  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 5018 13:58:23.745419  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 5019 13:58:23.748921  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 5020 13:58:23.755526  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 5021 13:58:23.759183  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 5022 13:58:23.762304  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 5023 13:58:23.769181  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5024 13:58:23.772236  =================================== 

 5025 13:58:23.772320  LPDDR4 DRAM CONFIGURATION

 5026 13:58:23.775805  =================================== 

 5027 13:58:23.779288  EX_ROW_EN[0]    = 0x0

 5028 13:58:23.779376  EX_ROW_EN[1]    = 0x0

 5029 13:58:23.782096  LP4Y_EN      = 0x0

 5030 13:58:23.785449  WORK_FSP     = 0x0

 5031 13:58:23.785531  WL           = 0x3

 5032 13:58:23.789039  RL           = 0x3

 5033 13:58:23.789122  BL           = 0x2

 5034 13:58:23.792039  RPST         = 0x0

 5035 13:58:23.792123  RD_PRE       = 0x0

 5036 13:58:23.795644  WR_PRE       = 0x1

 5037 13:58:23.795727  WR_PST       = 0x0

 5038 13:58:23.798796  DBI_WR       = 0x0

 5039 13:58:23.798879  DBI_RD       = 0x0

 5040 13:58:23.802150  OTF          = 0x1

 5041 13:58:23.805888  =================================== 

 5042 13:58:23.808780  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5043 13:58:23.812322  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5044 13:58:23.818952  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5045 13:58:23.821715  =================================== 

 5046 13:58:23.821797  LPDDR4 DRAM CONFIGURATION

 5047 13:58:23.825269  =================================== 

 5048 13:58:23.828349  EX_ROW_EN[0]    = 0x10

 5049 13:58:23.828432  EX_ROW_EN[1]    = 0x0

 5050 13:58:23.831896  LP4Y_EN      = 0x0

 5051 13:58:23.835252  WORK_FSP     = 0x0

 5052 13:58:23.835349  WL           = 0x3

 5053 13:58:23.838478  RL           = 0x3

 5054 13:58:23.838560  BL           = 0x2

 5055 13:58:23.841838  RPST         = 0x0

 5056 13:58:23.841946  RD_PRE       = 0x0

 5057 13:58:23.845527  WR_PRE       = 0x1

 5058 13:58:23.845609  WR_PST       = 0x0

 5059 13:58:23.848372  DBI_WR       = 0x0

 5060 13:58:23.848454  DBI_RD       = 0x0

 5061 13:58:23.851809  OTF          = 0x1

 5062 13:58:23.854956  =================================== 

 5063 13:58:23.861601  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5064 13:58:23.864859  nWR fixed to 30

 5065 13:58:23.864943  [ModeRegInit_LP4] CH0 RK0

 5066 13:58:23.868191  [ModeRegInit_LP4] CH0 RK1

 5067 13:58:23.871479  [ModeRegInit_LP4] CH1 RK0

 5068 13:58:23.871561  [ModeRegInit_LP4] CH1 RK1

 5069 13:58:23.874926  match AC timing 9

 5070 13:58:23.878489  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5071 13:58:23.881527  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5072 13:58:23.887898  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5073 13:58:23.891244  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5074 13:58:23.897853  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5075 13:58:23.897946  ==

 5076 13:58:23.901471  Dram Type= 6, Freq= 0, CH_0, rank 0

 5077 13:58:23.904380  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5078 13:58:23.904465  ==

 5079 13:58:23.911362  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5080 13:58:23.917868  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 5081 13:58:23.921383  [CA 0] Center 38 (7~69) winsize 63

 5082 13:58:23.924305  [CA 1] Center 38 (7~69) winsize 63

 5083 13:58:23.927853  [CA 2] Center 35 (5~66) winsize 62

 5084 13:58:23.930985  [CA 3] Center 35 (4~66) winsize 63

 5085 13:58:23.934186  [CA 4] Center 34 (4~65) winsize 62

 5086 13:58:23.937801  [CA 5] Center 33 (3~64) winsize 62

 5087 13:58:23.937885  

 5088 13:58:23.940989  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 5089 13:58:23.941101  

 5090 13:58:23.944070  [CATrainingPosCal] consider 1 rank data

 5091 13:58:23.947983  u2DelayCellTimex100 = 270/100 ps

 5092 13:58:23.950982  CA0 delay=38 (7~69),Diff = 5 PI (31 cell)

 5093 13:58:23.954566  CA1 delay=38 (7~69),Diff = 5 PI (31 cell)

 5094 13:58:23.957497  CA2 delay=35 (5~66),Diff = 2 PI (12 cell)

 5095 13:58:23.960937  CA3 delay=35 (4~66),Diff = 2 PI (12 cell)

 5096 13:58:23.964539  CA4 delay=34 (4~65),Diff = 1 PI (6 cell)

 5097 13:58:23.967609  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5098 13:58:23.967692  

 5099 13:58:23.971463  CA PerBit enable=1, Macro0, CA PI delay=33

 5100 13:58:23.974872  

 5101 13:58:23.974953  [CBTSetCACLKResult] CA Dly = 33

 5102 13:58:23.977833  CS Dly: 7 (0~38)

 5103 13:58:23.977915  ==

 5104 13:58:23.981123  Dram Type= 6, Freq= 0, CH_0, rank 1

 5105 13:58:23.984128  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5106 13:58:23.984236  ==

 5107 13:58:23.991199  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5108 13:58:23.997487  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5109 13:58:24.001000  [CA 0] Center 38 (8~69) winsize 62

 5110 13:58:24.004840  [CA 1] Center 38 (8~69) winsize 62

 5111 13:58:24.007379  [CA 2] Center 35 (5~66) winsize 62

 5112 13:58:24.010737  [CA 3] Center 35 (5~65) winsize 61

 5113 13:58:24.014069  [CA 4] Center 34 (4~64) winsize 61

 5114 13:58:24.017635  [CA 5] Center 33 (3~64) winsize 62

 5115 13:58:24.017738  

 5116 13:58:24.020768  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5117 13:58:24.020880  

 5118 13:58:24.024098  [CATrainingPosCal] consider 2 rank data

 5119 13:58:24.027837  u2DelayCellTimex100 = 270/100 ps

 5120 13:58:24.030670  CA0 delay=38 (8~69),Diff = 5 PI (31 cell)

 5121 13:58:24.034043  CA1 delay=38 (8~69),Diff = 5 PI (31 cell)

 5122 13:58:24.037498  CA2 delay=35 (5~66),Diff = 2 PI (12 cell)

 5123 13:58:24.040995  CA3 delay=35 (5~65),Diff = 2 PI (12 cell)

 5124 13:58:24.044208  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5125 13:58:24.047424  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5126 13:58:24.047506  

 5127 13:58:24.053840  CA PerBit enable=1, Macro0, CA PI delay=33

 5128 13:58:24.053922  

 5129 13:58:24.057106  [CBTSetCACLKResult] CA Dly = 33

 5130 13:58:24.057188  CS Dly: 7 (0~39)

 5131 13:58:24.057254  

 5132 13:58:24.060601  ----->DramcWriteLeveling(PI) begin...

 5133 13:58:24.060684  ==

 5134 13:58:24.064106  Dram Type= 6, Freq= 0, CH_0, rank 0

 5135 13:58:24.067324  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5136 13:58:24.070550  ==

 5137 13:58:24.070632  Write leveling (Byte 0): 31 => 31

 5138 13:58:24.073627  Write leveling (Byte 1): 30 => 30

 5139 13:58:24.076962  DramcWriteLeveling(PI) end<-----

 5140 13:58:24.077043  

 5141 13:58:24.077109  ==

 5142 13:58:24.080183  Dram Type= 6, Freq= 0, CH_0, rank 0

 5143 13:58:24.087055  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5144 13:58:24.087140  ==

 5145 13:58:24.087206  [Gating] SW mode calibration

 5146 13:58:24.096829  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5147 13:58:24.100453  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5148 13:58:24.103397   0 14  0 | B1->B0 | 2323 2b2b | 0 1 | (1 1) (1 1)

 5149 13:58:24.110754   0 14  4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)

 5150 13:58:24.113403   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5151 13:58:24.117268   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5152 13:58:24.123779   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5153 13:58:24.126864   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5154 13:58:24.130229   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5155 13:58:24.136841   0 14 28 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)

 5156 13:58:24.140036   0 15  0 | B1->B0 | 3232 2424 | 0 0 | (0 0) (1 0)

 5157 13:58:24.143701   0 15  4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)

 5158 13:58:24.152574   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5159 13:58:24.153477   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5160 13:58:24.156421   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5161 13:58:24.163478   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5162 13:58:24.166449   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5163 13:58:24.169671   0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 5164 13:58:24.176696   1  0  0 | B1->B0 | 2e2e 3f3f | 0 0 | (0 0) (0 0)

 5165 13:58:24.179763   1  0  4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

 5166 13:58:24.183040   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5167 13:58:24.189830   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5168 13:58:24.193665   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5169 13:58:24.196266   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5170 13:58:24.203024   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5171 13:58:24.206254   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5172 13:58:24.209668   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5173 13:58:24.216181   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5174 13:58:24.219755   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5175 13:58:24.222583   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5176 13:58:24.229267   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5177 13:58:24.232466   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5178 13:58:24.235886   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5179 13:58:24.242387   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5180 13:58:24.245852   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5181 13:58:24.249423   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5182 13:58:24.255653   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5183 13:58:24.259162   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5184 13:58:24.262818   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5185 13:58:24.269205   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5186 13:58:24.272614   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5187 13:58:24.275617   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5188 13:58:24.282295   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 5189 13:58:24.282377  Total UI for P1: 0, mck2ui 16

 5190 13:58:24.288849  best dqsien dly found for B0: ( 1,  2, 28)

 5191 13:58:24.292261   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5192 13:58:24.295495  Total UI for P1: 0, mck2ui 16

 5193 13:58:24.298975  best dqsien dly found for B1: ( 1,  3,  2)

 5194 13:58:24.302881  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5195 13:58:24.305781  best DQS1 dly(MCK, UI, PI) = (1, 3, 2)

 5196 13:58:24.305862  

 5197 13:58:24.308856  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5198 13:58:24.312117  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)

 5199 13:58:24.315568  [Gating] SW calibration Done

 5200 13:58:24.315649  ==

 5201 13:58:24.318898  Dram Type= 6, Freq= 0, CH_0, rank 0

 5202 13:58:24.322092  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5203 13:58:24.322174  ==

 5204 13:58:24.325590  RX Vref Scan: 0

 5205 13:58:24.325671  

 5206 13:58:24.328996  RX Vref 0 -> 0, step: 1

 5207 13:58:24.329078  

 5208 13:58:24.329157  RX Delay -80 -> 252, step: 8

 5209 13:58:24.335539  iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200

 5210 13:58:24.338586  iDelay=208, Bit 1, Center 95 (0 ~ 191) 192

 5211 13:58:24.341828  iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200

 5212 13:58:24.345438  iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192

 5213 13:58:24.348856  iDelay=208, Bit 4, Center 95 (0 ~ 191) 192

 5214 13:58:24.351820  iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192

 5215 13:58:24.358776  iDelay=208, Bit 6, Center 103 (8 ~ 199) 192

 5216 13:58:24.361732  iDelay=208, Bit 7, Center 107 (8 ~ 207) 200

 5217 13:58:24.365567  iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200

 5218 13:58:24.368857  iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200

 5219 13:58:24.371800  iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200

 5220 13:58:24.378776  iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192

 5221 13:58:24.381659  iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208

 5222 13:58:24.385135  iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200

 5223 13:58:24.388391  iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200

 5224 13:58:24.392012  iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200

 5225 13:58:24.395511  ==

 5226 13:58:24.395605  Dram Type= 6, Freq= 0, CH_0, rank 0

 5227 13:58:24.401711  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5228 13:58:24.401806  ==

 5229 13:58:24.401897  DQS Delay:

 5230 13:58:24.405003  DQS0 = 0, DQS1 = 0

 5231 13:58:24.405090  DQM Delay:

 5232 13:58:24.408363  DQM0 = 93, DQM1 = 83

 5233 13:58:24.408460  DQ Delay:

 5234 13:58:24.411707  DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87

 5235 13:58:24.414894  DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107

 5236 13:58:24.418194  DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79

 5237 13:58:24.421517  DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91

 5238 13:58:24.421597  

 5239 13:58:24.421692  

 5240 13:58:24.421780  ==

 5241 13:58:24.424803  Dram Type= 6, Freq= 0, CH_0, rank 0

 5242 13:58:24.427988  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5243 13:58:24.428077  ==

 5244 13:58:24.428159  

 5245 13:58:24.428243  

 5246 13:58:24.431183  	TX Vref Scan disable

 5247 13:58:24.434879   == TX Byte 0 ==

 5248 13:58:24.438500  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5249 13:58:24.441283  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5250 13:58:24.444831   == TX Byte 1 ==

 5251 13:58:24.448416  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5252 13:58:24.451096  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5253 13:58:24.451187  ==

 5254 13:58:24.454777  Dram Type= 6, Freq= 0, CH_0, rank 0

 5255 13:58:24.461621  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5256 13:58:24.461708  ==

 5257 13:58:24.461808  

 5258 13:58:24.461890  

 5259 13:58:24.461971  	TX Vref Scan disable

 5260 13:58:24.465285   == TX Byte 0 ==

 5261 13:58:24.468743  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5262 13:58:24.475108  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5263 13:58:24.475199   == TX Byte 1 ==

 5264 13:58:24.478718  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5265 13:58:24.485257  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5266 13:58:24.485344  

 5267 13:58:24.485446  [DATLAT]

 5268 13:58:24.485544  Freq=933, CH0 RK0

 5269 13:58:24.485612  

 5270 13:58:24.488650  DATLAT Default: 0xd

 5271 13:58:24.488726  0, 0xFFFF, sum = 0

 5272 13:58:24.491615  1, 0xFFFF, sum = 0

 5273 13:58:24.491703  2, 0xFFFF, sum = 0

 5274 13:58:24.495029  3, 0xFFFF, sum = 0

 5275 13:58:24.498405  4, 0xFFFF, sum = 0

 5276 13:58:24.498485  5, 0xFFFF, sum = 0

 5277 13:58:24.501536  6, 0xFFFF, sum = 0

 5278 13:58:24.501621  7, 0xFFFF, sum = 0

 5279 13:58:24.505505  8, 0xFFFF, sum = 0

 5280 13:58:24.505589  9, 0xFFFF, sum = 0

 5281 13:58:24.508350  10, 0x0, sum = 1

 5282 13:58:24.508433  11, 0x0, sum = 2

 5283 13:58:24.512081  12, 0x0, sum = 3

 5284 13:58:24.512164  13, 0x0, sum = 4

 5285 13:58:24.512229  best_step = 11

 5286 13:58:24.512289  

 5287 13:58:24.514818  ==

 5288 13:58:24.518310  Dram Type= 6, Freq= 0, CH_0, rank 0

 5289 13:58:24.521465  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5290 13:58:24.521547  ==

 5291 13:58:24.521612  RX Vref Scan: 1

 5292 13:58:24.521673  

 5293 13:58:24.524806  RX Vref 0 -> 0, step: 1

 5294 13:58:24.524886  

 5295 13:58:24.528229  RX Delay -77 -> 252, step: 4

 5296 13:58:24.528311  

 5297 13:58:24.531538  Set Vref, RX VrefLevel [Byte0]: 61

 5298 13:58:24.534806                           [Byte1]: 49

 5299 13:58:24.534887  

 5300 13:58:24.538130  Final RX Vref Byte 0 = 61 to rank0

 5301 13:58:24.541623  Final RX Vref Byte 1 = 49 to rank0

 5302 13:58:24.545143  Final RX Vref Byte 0 = 61 to rank1

 5303 13:58:24.548101  Final RX Vref Byte 1 = 49 to rank1==

 5304 13:58:24.551238  Dram Type= 6, Freq= 0, CH_0, rank 0

 5305 13:58:24.558301  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5306 13:58:24.558393  ==

 5307 13:58:24.558466  DQS Delay:

 5308 13:58:24.558541  DQS0 = 0, DQS1 = 0

 5309 13:58:24.561199  DQM Delay:

 5310 13:58:24.561280  DQM0 = 95, DQM1 = 82

 5311 13:58:24.564734  DQ Delay:

 5312 13:58:24.568480  DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92

 5313 13:58:24.571264  DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106

 5314 13:58:24.574947  DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76

 5315 13:58:24.577794  DQ12 =86, DQ13 =86, DQ14 =96, DQ15 =90

 5316 13:58:24.577875  

 5317 13:58:24.577940  

 5318 13:58:24.584495  [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps

 5319 13:58:24.587894  CH0 RK0: MR19=505, MR18=1515

 5320 13:58:24.594354  CH0_RK0: MR19=0x505, MR18=0x1515, DQSOSC=415, MR23=63, INC=62, DEC=41

 5321 13:58:24.594435  

 5322 13:58:24.597853  ----->DramcWriteLeveling(PI) begin...

 5323 13:58:24.597935  ==

 5324 13:58:24.601352  Dram Type= 6, Freq= 0, CH_0, rank 1

 5325 13:58:24.604713  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5326 13:58:24.604794  ==

 5327 13:58:24.607991  Write leveling (Byte 0): 29 => 29

 5328 13:58:24.611186  Write leveling (Byte 1): 29 => 29

 5329 13:58:24.614664  DramcWriteLeveling(PI) end<-----

 5330 13:58:24.614745  

 5331 13:58:24.614840  ==

 5332 13:58:24.618317  Dram Type= 6, Freq= 0, CH_0, rank 1

 5333 13:58:24.621036  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5334 13:58:24.621117  ==

 5335 13:58:24.624743  [Gating] SW mode calibration

 5336 13:58:24.630960  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5337 13:58:24.637516  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5338 13:58:24.641249   0 14  0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)

 5339 13:58:24.644454   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5340 13:58:24.650912   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5341 13:58:24.654273   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5342 13:58:24.657444   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5343 13:58:24.664472   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5344 13:58:24.667649   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5345 13:58:24.671071   0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)

 5346 13:58:24.677704   0 15  0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)

 5347 13:58:24.680736   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5348 13:58:24.684369   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5349 13:58:24.690784   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5350 13:58:24.693979   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5351 13:58:24.697536   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5352 13:58:24.704066   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5353 13:58:24.707655   0 15 28 | B1->B0 | 2929 3e3e | 0 0 | (1 1) (0 0)

 5354 13:58:24.710475   1  0  0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)

 5355 13:58:24.717222   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5356 13:58:24.720650   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5357 13:58:24.724020   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5358 13:58:24.730566   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5359 13:58:24.733948   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5360 13:58:24.737463   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5361 13:58:24.743727   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5362 13:58:24.746909   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5363 13:58:24.750251   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5364 13:58:24.756811   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5365 13:58:24.760552   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5366 13:58:24.763454   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5367 13:58:24.770494   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5368 13:58:24.773588   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5369 13:58:24.776763   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5370 13:58:24.783203   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5371 13:58:24.786600   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5372 13:58:24.790154   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5373 13:58:24.796892   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5374 13:58:24.799980   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5375 13:58:24.803508   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5376 13:58:24.810012   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5377 13:58:24.813384   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5378 13:58:24.816958   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5379 13:58:24.819731  Total UI for P1: 0, mck2ui 16

 5380 13:58:24.823275  best dqsien dly found for B0: ( 1,  2, 28)

 5381 13:58:24.826697  Total UI for P1: 0, mck2ui 16

 5382 13:58:24.830126  best dqsien dly found for B1: ( 1,  2, 30)

 5383 13:58:24.833175  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5384 13:58:24.836786  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5385 13:58:24.836867  

 5386 13:58:24.839676  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5387 13:58:24.846554  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5388 13:58:24.846635  [Gating] SW calibration Done

 5389 13:58:24.846700  ==

 5390 13:58:24.849672  Dram Type= 6, Freq= 0, CH_0, rank 1

 5391 13:58:24.856452  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5392 13:58:24.856534  ==

 5393 13:58:24.856599  RX Vref Scan: 0

 5394 13:58:24.856658  

 5395 13:58:24.859654  RX Vref 0 -> 0, step: 1

 5396 13:58:24.859735  

 5397 13:58:24.862952  RX Delay -80 -> 252, step: 8

 5398 13:58:24.866341  iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200

 5399 13:58:24.869630  iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208

 5400 13:58:24.872768  iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200

 5401 13:58:24.879513  iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208

 5402 13:58:24.882808  iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200

 5403 13:58:24.885955  iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192

 5404 13:58:24.889820  iDelay=208, Bit 6, Center 103 (0 ~ 207) 208

 5405 13:58:24.892848  iDelay=208, Bit 7, Center 103 (0 ~ 207) 208

 5406 13:58:24.896493  iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200

 5407 13:58:24.902859  iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200

 5408 13:58:24.906207  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5409 13:58:24.909352  iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184

 5410 13:58:24.912950  iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200

 5411 13:58:24.916293  iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200

 5412 13:58:24.922781  iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200

 5413 13:58:24.926173  iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192

 5414 13:58:24.926252  ==

 5415 13:58:24.929103  Dram Type= 6, Freq= 0, CH_0, rank 1

 5416 13:58:24.932342  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5417 13:58:24.932430  ==

 5418 13:58:24.935661  DQS Delay:

 5419 13:58:24.935741  DQS0 = 0, DQS1 = 0

 5420 13:58:24.935815  DQM Delay:

 5421 13:58:24.939234  DQM0 = 92, DQM1 = 83

 5422 13:58:24.939328  DQ Delay:

 5423 13:58:24.942731  DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87

 5424 13:58:24.945834  DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103

 5425 13:58:24.949272  DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75

 5426 13:58:24.952832  DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87

 5427 13:58:24.952927  

 5428 13:58:24.952998  

 5429 13:58:24.953063  ==

 5430 13:58:24.955899  Dram Type= 6, Freq= 0, CH_0, rank 1

 5431 13:58:24.962462  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5432 13:58:24.962542  ==

 5433 13:58:24.962610  

 5434 13:58:24.962677  

 5435 13:58:24.962745  	TX Vref Scan disable

 5436 13:58:24.965998   == TX Byte 0 ==

 5437 13:58:24.969127  Update DQ  dly =713 (2 ,5, 41)  DQ  OEN =(2 ,2)

 5438 13:58:24.976208  Update DQM dly =713 (2 ,5, 41)  DQM OEN =(2 ,2)

 5439 13:58:24.976298   == TX Byte 1 ==

 5440 13:58:24.979522  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5441 13:58:24.985707  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5442 13:58:24.985790  ==

 5443 13:58:24.989295  Dram Type= 6, Freq= 0, CH_0, rank 1

 5444 13:58:24.992576  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5445 13:58:24.992663  ==

 5446 13:58:24.992741  

 5447 13:58:24.992806  

 5448 13:58:24.996183  	TX Vref Scan disable

 5449 13:58:24.996264   == TX Byte 0 ==

 5450 13:58:25.002418  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5451 13:58:25.005659  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5452 13:58:25.005748   == TX Byte 1 ==

 5453 13:58:25.012538  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5454 13:58:25.015752  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5455 13:58:25.015834  

 5456 13:58:25.015909  [DATLAT]

 5457 13:58:25.019171  Freq=933, CH0 RK1

 5458 13:58:25.019254  

 5459 13:58:25.019319  DATLAT Default: 0xb

 5460 13:58:25.022690  0, 0xFFFF, sum = 0

 5461 13:58:25.022763  1, 0xFFFF, sum = 0

 5462 13:58:25.025469  2, 0xFFFF, sum = 0

 5463 13:58:25.025552  3, 0xFFFF, sum = 0

 5464 13:58:25.029005  4, 0xFFFF, sum = 0

 5465 13:58:25.032548  5, 0xFFFF, sum = 0

 5466 13:58:25.032631  6, 0xFFFF, sum = 0

 5467 13:58:25.035514  7, 0xFFFF, sum = 0

 5468 13:58:25.035597  8, 0xFFFF, sum = 0

 5469 13:58:25.038798  9, 0xFFFF, sum = 0

 5470 13:58:25.038880  10, 0x0, sum = 1

 5471 13:58:25.042231  11, 0x0, sum = 2

 5472 13:58:25.042314  12, 0x0, sum = 3

 5473 13:58:25.042380  13, 0x0, sum = 4

 5474 13:58:25.045610  best_step = 11

 5475 13:58:25.045691  

 5476 13:58:25.045756  ==

 5477 13:58:25.049471  Dram Type= 6, Freq= 0, CH_0, rank 1

 5478 13:58:25.052183  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5479 13:58:25.052265  ==

 5480 13:58:25.055850  RX Vref Scan: 0

 5481 13:58:25.055931  

 5482 13:58:25.055996  RX Vref 0 -> 0, step: 1

 5483 13:58:25.056055  

 5484 13:58:25.058838  RX Delay -77 -> 252, step: 4

 5485 13:58:25.066463  iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192

 5486 13:58:25.069811  iDelay=199, Bit 1, Center 94 (3 ~ 186) 184

 5487 13:58:25.073185  iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188

 5488 13:58:25.076823  iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196

 5489 13:58:25.079611  iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192

 5490 13:58:25.086552  iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188

 5491 13:58:25.089468  iDelay=199, Bit 6, Center 104 (11 ~ 198) 188

 5492 13:58:25.093086  iDelay=199, Bit 7, Center 100 (7 ~ 194) 188

 5493 13:58:25.096272  iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180

 5494 13:58:25.099502  iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180

 5495 13:58:25.102716  iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184

 5496 13:58:25.109577  iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180

 5497 13:58:25.112672  iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188

 5498 13:58:25.116019  iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184

 5499 13:58:25.119298  iDelay=199, Bit 14, Center 96 (7 ~ 186) 180

 5500 13:58:25.122585  iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184

 5501 13:58:25.126042  ==

 5502 13:58:25.129275  Dram Type= 6, Freq= 0, CH_0, rank 1

 5503 13:58:25.132617  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5504 13:58:25.132712  ==

 5505 13:58:25.132813  DQS Delay:

 5506 13:58:25.136106  DQS0 = 0, DQS1 = 0

 5507 13:58:25.136202  DQM Delay:

 5508 13:58:25.139080  DQM0 = 91, DQM1 = 83

 5509 13:58:25.139167  DQ Delay:

 5510 13:58:25.142504  DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88

 5511 13:58:25.145863  DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =100

 5512 13:58:25.149290  DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76

 5513 13:58:25.152389  DQ12 =88, DQ13 =90, DQ14 =96, DQ15 =90

 5514 13:58:25.152494  

 5515 13:58:25.152605  

 5516 13:58:25.158834  [DQSOSCAuto] RK1, (LSB)MR18= 0x2e10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps

 5517 13:58:25.162599  CH0 RK1: MR19=505, MR18=2E10

 5518 13:58:25.168840  CH0_RK1: MR19=0x505, MR18=0x2E10, DQSOSC=407, MR23=63, INC=65, DEC=43

 5519 13:58:25.172382  [RxdqsGatingPostProcess] freq 933

 5520 13:58:25.178876  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5521 13:58:25.182247  best DQS0 dly(2T, 0.5T) = (0, 10)

 5522 13:58:25.182331  best DQS1 dly(2T, 0.5T) = (0, 11)

 5523 13:58:25.185797  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5524 13:58:25.189106  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5525 13:58:25.192115  best DQS0 dly(2T, 0.5T) = (0, 10)

 5526 13:58:25.195448  best DQS1 dly(2T, 0.5T) = (0, 10)

 5527 13:58:25.198420  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5528 13:58:25.201929  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5529 13:58:25.205371  Pre-setting of DQS Precalculation

 5530 13:58:25.211893  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5531 13:58:25.211988  ==

 5532 13:58:25.215511  Dram Type= 6, Freq= 0, CH_1, rank 0

 5533 13:58:25.218751  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5534 13:58:25.218866  ==

 5535 13:58:25.225181  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5536 13:58:25.228319  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5537 13:58:25.232940  [CA 0] Center 37 (7~68) winsize 62

 5538 13:58:25.235990  [CA 1] Center 37 (7~68) winsize 62

 5539 13:58:25.239596  [CA 2] Center 34 (5~64) winsize 60

 5540 13:58:25.242959  [CA 3] Center 34 (5~64) winsize 60

 5541 13:58:25.246422  [CA 4] Center 35 (5~65) winsize 61

 5542 13:58:25.249689  [CA 5] Center 33 (4~63) winsize 60

 5543 13:58:25.249764  

 5544 13:58:25.252525  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5545 13:58:25.252597  

 5546 13:58:25.255958  [CATrainingPosCal] consider 1 rank data

 5547 13:58:25.259693  u2DelayCellTimex100 = 270/100 ps

 5548 13:58:25.263005  CA0 delay=37 (7~68),Diff = 4 PI (24 cell)

 5549 13:58:25.266535  CA1 delay=37 (7~68),Diff = 4 PI (24 cell)

 5550 13:58:25.272643  CA2 delay=34 (5~64),Diff = 1 PI (6 cell)

 5551 13:58:25.275944  CA3 delay=34 (5~64),Diff = 1 PI (6 cell)

 5552 13:58:25.279271  CA4 delay=35 (5~65),Diff = 2 PI (12 cell)

 5553 13:58:25.282421  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 5554 13:58:25.282503  

 5555 13:58:25.285752  CA PerBit enable=1, Macro0, CA PI delay=33

 5556 13:58:25.285833  

 5557 13:58:25.289159  [CBTSetCACLKResult] CA Dly = 33

 5558 13:58:25.289258  CS Dly: 6 (0~37)

 5559 13:58:25.292727  ==

 5560 13:58:25.295761  Dram Type= 6, Freq= 0, CH_1, rank 1

 5561 13:58:25.299300  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5562 13:58:25.299441  ==

 5563 13:58:25.302687  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5564 13:58:25.309000  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5565 13:58:25.312893  [CA 0] Center 37 (7~68) winsize 62

 5566 13:58:25.316296  [CA 1] Center 37 (7~68) winsize 62

 5567 13:58:25.319673  [CA 2] Center 35 (5~65) winsize 61

 5568 13:58:25.323282  [CA 3] Center 34 (4~64) winsize 61

 5569 13:58:25.326336  [CA 4] Center 34 (4~65) winsize 62

 5570 13:58:25.329359  [CA 5] Center 34 (4~64) winsize 61

 5571 13:58:25.329447  

 5572 13:58:25.332761  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5573 13:58:25.332850  

 5574 13:58:25.336444  [CATrainingPosCal] consider 2 rank data

 5575 13:58:25.339520  u2DelayCellTimex100 = 270/100 ps

 5576 13:58:25.342724  CA0 delay=37 (7~68),Diff = 4 PI (24 cell)

 5577 13:58:25.349576  CA1 delay=37 (7~68),Diff = 4 PI (24 cell)

 5578 13:58:25.352679  CA2 delay=34 (5~64),Diff = 1 PI (6 cell)

 5579 13:58:25.355878  CA3 delay=34 (5~64),Diff = 1 PI (6 cell)

 5580 13:58:25.359537  CA4 delay=35 (5~65),Diff = 2 PI (12 cell)

 5581 13:58:25.362964  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 5582 13:58:25.363064  

 5583 13:58:25.365886  CA PerBit enable=1, Macro0, CA PI delay=33

 5584 13:58:25.365982  

 5585 13:58:25.369367  [CBTSetCACLKResult] CA Dly = 33

 5586 13:58:25.369457  CS Dly: 7 (0~39)

 5587 13:58:25.373019  

 5588 13:58:25.375991  ----->DramcWriteLeveling(PI) begin...

 5589 13:58:25.376087  ==

 5590 13:58:25.379566  Dram Type= 6, Freq= 0, CH_1, rank 0

 5591 13:58:25.382276  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5592 13:58:25.382357  ==

 5593 13:58:25.385808  Write leveling (Byte 0): 27 => 27

 5594 13:58:25.389341  Write leveling (Byte 1): 29 => 29

 5595 13:58:25.392695  DramcWriteLeveling(PI) end<-----

 5596 13:58:25.392794  

 5597 13:58:25.392884  ==

 5598 13:58:25.396385  Dram Type= 6, Freq= 0, CH_1, rank 0

 5599 13:58:25.399039  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5600 13:58:25.399120  ==

 5601 13:58:25.402638  [Gating] SW mode calibration

 5602 13:58:25.408950  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5603 13:58:25.415474  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5604 13:58:25.419428   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5605 13:58:25.422476   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5606 13:58:25.429207   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5607 13:58:25.432262   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5608 13:58:25.435758   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5609 13:58:25.442535   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5610 13:58:25.445719   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 5611 13:58:25.448763   0 14 28 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (0 1)

 5612 13:58:25.455351   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5613 13:58:25.458533   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5614 13:58:25.462247   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5615 13:58:25.468748   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5616 13:58:25.471954   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5617 13:58:25.475506   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5618 13:58:25.481834   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5619 13:58:25.485284   0 15 28 | B1->B0 | 3131 3030 | 0 0 | (0 0) (1 1)

 5620 13:58:25.488833   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5621 13:58:25.495386   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5622 13:58:25.498706   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5623 13:58:25.501676   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5624 13:58:25.505392   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5625 13:58:25.511764   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5626 13:58:25.515533   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5627 13:58:25.518636   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5628 13:58:25.525038   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5629 13:58:25.528709   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5630 13:58:25.531881   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5631 13:58:25.538494   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5632 13:58:25.541658   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5633 13:58:25.545198   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5634 13:58:25.551439   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5635 13:58:25.554847   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5636 13:58:25.558495   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5637 13:58:25.564916   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5638 13:58:25.568192   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5639 13:58:25.571650   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5640 13:58:25.578369   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5641 13:58:25.581651   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5642 13:58:25.585241   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5643 13:58:25.591428   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 5644 13:58:25.595226   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 5645 13:58:25.597930  Total UI for P1: 0, mck2ui 16

 5646 13:58:25.601856  best dqsien dly found for B1: ( 1,  2, 28)

 5647 13:58:25.604992   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5648 13:58:25.608588  Total UI for P1: 0, mck2ui 16

 5649 13:58:25.611321  best dqsien dly found for B0: ( 1,  3,  0)

 5650 13:58:25.614802  best DQS0 dly(MCK, UI, PI) = (1, 3, 0)

 5651 13:58:25.617813  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5652 13:58:25.617904  

 5653 13:58:25.621487  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)

 5654 13:58:25.628117  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5655 13:58:25.628206  [Gating] SW calibration Done

 5656 13:58:25.628297  ==

 5657 13:58:25.631225  Dram Type= 6, Freq= 0, CH_1, rank 0

 5658 13:58:25.637990  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5659 13:58:25.638074  ==

 5660 13:58:25.638190  RX Vref Scan: 0

 5661 13:58:25.638275  

 5662 13:58:25.641634  RX Vref 0 -> 0, step: 1

 5663 13:58:25.641712  

 5664 13:58:25.644691  RX Delay -80 -> 252, step: 8

 5665 13:58:25.647834  iDelay=208, Bit 0, Center 99 (0 ~ 199) 200

 5666 13:58:25.651055  iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200

 5667 13:58:25.654789  iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200

 5668 13:58:25.657862  iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200

 5669 13:58:25.664617  iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200

 5670 13:58:25.667624  iDelay=208, Bit 5, Center 103 (0 ~ 207) 208

 5671 13:58:25.670879  iDelay=208, Bit 6, Center 103 (0 ~ 207) 208

 5672 13:58:25.674474  iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200

 5673 13:58:25.677993  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5674 13:58:25.684609  iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192

 5675 13:58:25.687777  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5676 13:58:25.691057  iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200

 5677 13:58:25.694628  iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200

 5678 13:58:25.697609  iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200

 5679 13:58:25.704435  iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200

 5680 13:58:25.708169  iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200

 5681 13:58:25.708267  ==

 5682 13:58:25.710882  Dram Type= 6, Freq= 0, CH_1, rank 0

 5683 13:58:25.714379  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5684 13:58:25.714496  ==

 5685 13:58:25.714605  DQS Delay:

 5686 13:58:25.717399  DQS0 = 0, DQS1 = 0

 5687 13:58:25.717475  DQM Delay:

 5688 13:58:25.720798  DQM0 = 94, DQM1 = 86

 5689 13:58:25.720872  DQ Delay:

 5690 13:58:25.724366  DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91

 5691 13:58:25.727400  DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91

 5692 13:58:25.730944  DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83

 5693 13:58:25.734258  DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91

 5694 13:58:25.734335  

 5695 13:58:25.734398  

 5696 13:58:25.734458  ==

 5697 13:58:25.737640  Dram Type= 6, Freq= 0, CH_1, rank 0

 5698 13:58:25.743838  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5699 13:58:25.743929  ==

 5700 13:58:25.743995  

 5701 13:58:25.744055  

 5702 13:58:25.744114  	TX Vref Scan disable

 5703 13:58:25.747512   == TX Byte 0 ==

 5704 13:58:25.750949  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5705 13:58:25.757080  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5706 13:58:25.757174   == TX Byte 1 ==

 5707 13:58:25.760851  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5708 13:58:25.767494  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5709 13:58:25.767582  ==

 5710 13:58:25.770721  Dram Type= 6, Freq= 0, CH_1, rank 0

 5711 13:58:25.773937  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5712 13:58:25.774052  ==

 5713 13:58:25.774146  

 5714 13:58:25.774241  

 5715 13:58:25.777020  	TX Vref Scan disable

 5716 13:58:25.777095   == TX Byte 0 ==

 5717 13:58:25.784108  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5718 13:58:25.787030  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5719 13:58:25.787106   == TX Byte 1 ==

 5720 13:58:25.793955  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5721 13:58:25.797032  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5722 13:58:25.797114  

 5723 13:58:25.797180  [DATLAT]

 5724 13:58:25.800273  Freq=933, CH1 RK0

 5725 13:58:25.800367  

 5726 13:58:25.800453  DATLAT Default: 0xd

 5727 13:58:25.803647  0, 0xFFFF, sum = 0

 5728 13:58:25.803730  1, 0xFFFF, sum = 0

 5729 13:58:25.807178  2, 0xFFFF, sum = 0

 5730 13:58:25.807267  3, 0xFFFF, sum = 0

 5731 13:58:25.810762  4, 0xFFFF, sum = 0

 5732 13:58:25.813619  5, 0xFFFF, sum = 0

 5733 13:58:25.813703  6, 0xFFFF, sum = 0

 5734 13:58:25.817169  7, 0xFFFF, sum = 0

 5735 13:58:25.817266  8, 0xFFFF, sum = 0

 5736 13:58:25.820672  9, 0xFFFF, sum = 0

 5737 13:58:25.820757  10, 0x0, sum = 1

 5738 13:58:25.823734  11, 0x0, sum = 2

 5739 13:58:25.823821  12, 0x0, sum = 3

 5740 13:58:25.823910  13, 0x0, sum = 4

 5741 13:58:25.827155  best_step = 11

 5742 13:58:25.827237  

 5743 13:58:25.827352  ==

 5744 13:58:25.830334  Dram Type= 6, Freq= 0, CH_1, rank 0

 5745 13:58:25.833935  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5746 13:58:25.834021  ==

 5747 13:58:25.837173  RX Vref Scan: 1

 5748 13:58:25.837254  

 5749 13:58:25.837341  RX Vref 0 -> 0, step: 1

 5750 13:58:25.840116  

 5751 13:58:25.840198  RX Delay -61 -> 252, step: 4

 5752 13:58:25.840293  

 5753 13:58:25.843551  Set Vref, RX VrefLevel [Byte0]: 59

 5754 13:58:25.846654                           [Byte1]: 57

 5755 13:58:25.851493  

 5756 13:58:25.851575  Final RX Vref Byte 0 = 59 to rank0

 5757 13:58:25.854764  Final RX Vref Byte 1 = 57 to rank0

 5758 13:58:25.858282  Final RX Vref Byte 0 = 59 to rank1

 5759 13:58:25.861510  Final RX Vref Byte 1 = 57 to rank1==

 5760 13:58:25.864608  Dram Type= 6, Freq= 0, CH_1, rank 0

 5761 13:58:25.871471  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5762 13:58:25.871600  ==

 5763 13:58:25.871689  DQS Delay:

 5764 13:58:25.874830  DQS0 = 0, DQS1 = 0

 5765 13:58:25.874920  DQM Delay:

 5766 13:58:25.875006  DQM0 = 96, DQM1 = 88

 5767 13:58:25.878090  DQ Delay:

 5768 13:58:25.881006  DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =92

 5769 13:58:25.884866  DQ4 =94, DQ5 =108, DQ6 =108, DQ7 =94

 5770 13:58:25.887687  DQ8 =76, DQ9 =80, DQ10 =86, DQ11 =80

 5771 13:58:25.891270  DQ12 =98, DQ13 =94, DQ14 =96, DQ15 =94

 5772 13:58:25.891356  

 5773 13:58:25.891499  

 5774 13:58:25.897706  [DQSOSCAuto] RK0, (LSB)MR18= 0xfe07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps

 5775 13:58:25.900925  CH1 RK0: MR19=405, MR18=FE07

 5776 13:58:25.907882  CH1_RK0: MR19=0x405, MR18=0xFE07, DQSOSC=419, MR23=63, INC=61, DEC=41

 5777 13:58:25.907966  

 5778 13:58:25.910769  ----->DramcWriteLeveling(PI) begin...

 5779 13:58:25.910850  ==

 5780 13:58:25.914379  Dram Type= 6, Freq= 0, CH_1, rank 1

 5781 13:58:25.917725  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5782 13:58:25.917809  ==

 5783 13:58:25.920654  Write leveling (Byte 0): 27 => 27

 5784 13:58:25.924264  Write leveling (Byte 1): 28 => 28

 5785 13:58:25.927217  DramcWriteLeveling(PI) end<-----

 5786 13:58:25.927296  

 5787 13:58:25.927451  ==

 5788 13:58:25.930818  Dram Type= 6, Freq= 0, CH_1, rank 1

 5789 13:58:25.933762  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5790 13:58:25.937399  ==

 5791 13:58:25.937484  [Gating] SW mode calibration

 5792 13:58:25.944112  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5793 13:58:25.950684  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5794 13:58:25.953571   0 14  0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)

 5795 13:58:25.960383   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5796 13:58:25.963569   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5797 13:58:25.967306   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5798 13:58:25.973411   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5799 13:58:25.977255   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5800 13:58:25.980377   0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)

 5801 13:58:25.986733   0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)

 5802 13:58:25.990041   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5803 13:58:25.993591   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5804 13:58:26.000163   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5805 13:58:26.003523   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5806 13:58:26.006790   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5807 13:58:26.013060   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5808 13:58:26.016385   0 15 24 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)

 5809 13:58:26.019804   0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)

 5810 13:58:26.026899   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5811 13:58:26.030035   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5812 13:58:26.033071   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5813 13:58:26.040158   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5814 13:58:26.043074   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5815 13:58:26.046580   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5816 13:58:26.053271   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5817 13:58:26.056314   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5818 13:58:26.059768   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5819 13:58:26.066160   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5820 13:58:26.069401   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5821 13:58:26.073162   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5822 13:58:26.079740   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5823 13:58:26.082868   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5824 13:58:26.086399   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5825 13:58:26.092641   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5826 13:58:26.096435   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5827 13:58:26.099528   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5828 13:58:26.105884   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5829 13:58:26.109388   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5830 13:58:26.112644   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5831 13:58:26.119239   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5832 13:58:26.122823   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5833 13:58:26.125717   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5834 13:58:26.129158  Total UI for P1: 0, mck2ui 16

 5835 13:58:26.132503  best dqsien dly found for B0: ( 1,  2, 24)

 5836 13:58:26.136078   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5837 13:58:26.139063  Total UI for P1: 0, mck2ui 16

 5838 13:58:26.142550  best dqsien dly found for B1: ( 1,  2, 26)

 5839 13:58:26.148654  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5840 13:58:26.152090  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5841 13:58:26.152184  

 5842 13:58:26.155162  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5843 13:58:26.158671  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5844 13:58:26.161823  [Gating] SW calibration Done

 5845 13:58:26.161911  ==

 5846 13:58:26.165146  Dram Type= 6, Freq= 0, CH_1, rank 1

 5847 13:58:26.168762  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5848 13:58:26.168863  ==

 5849 13:58:26.171656  RX Vref Scan: 0

 5850 13:58:26.171742  

 5851 13:58:26.171862  RX Vref 0 -> 0, step: 1

 5852 13:58:26.171968  

 5853 13:58:26.175131  RX Delay -80 -> 252, step: 8

 5854 13:58:26.178422  iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208

 5855 13:58:26.185070  iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192

 5856 13:58:26.188032  iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200

 5857 13:58:26.191574  iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200

 5858 13:58:26.195220  iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200

 5859 13:58:26.198091  iDelay=208, Bit 5, Center 103 (0 ~ 207) 208

 5860 13:58:26.204950  iDelay=208, Bit 6, Center 103 (0 ~ 207) 208

 5861 13:58:26.208035  iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200

 5862 13:58:26.211471  iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200

 5863 13:58:26.215019  iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200

 5864 13:58:26.217903  iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200

 5865 13:58:26.224458  iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200

 5866 13:58:26.227850  iDelay=208, Bit 12, Center 99 (0 ~ 199) 200

 5867 13:58:26.230948  iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208

 5868 13:58:26.234833  iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208

 5869 13:58:26.237619  iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208

 5870 13:58:26.237722  ==

 5871 13:58:26.241002  Dram Type= 6, Freq= 0, CH_1, rank 1

 5872 13:58:26.247730  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5873 13:58:26.247822  ==

 5874 13:58:26.247892  DQS Delay:

 5875 13:58:26.251293  DQS0 = 0, DQS1 = 0

 5876 13:58:26.251377  DQM Delay:

 5877 13:58:26.251443  DQM0 = 93, DQM1 = 88

 5878 13:58:26.254230  DQ Delay:

 5879 13:58:26.257943  DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91

 5880 13:58:26.261059  DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91

 5881 13:58:26.264353  DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83

 5882 13:58:26.267292  DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95

 5883 13:58:26.267431  

 5884 13:58:26.267500  

 5885 13:58:26.267562  ==

 5886 13:58:26.270631  Dram Type= 6, Freq= 0, CH_1, rank 1

 5887 13:58:26.274334  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5888 13:58:26.274426  ==

 5889 13:58:26.274522  

 5890 13:58:26.274612  

 5891 13:58:26.277833  	TX Vref Scan disable

 5892 13:58:26.280752   == TX Byte 0 ==

 5893 13:58:26.283979  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5894 13:58:26.287846  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5895 13:58:26.290476   == TX Byte 1 ==

 5896 13:58:26.294332  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5897 13:58:26.297639  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5898 13:58:26.297723  ==

 5899 13:58:26.300623  Dram Type= 6, Freq= 0, CH_1, rank 1

 5900 13:58:26.303596  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5901 13:58:26.306898  ==

 5902 13:58:26.306979  

 5903 13:58:26.307070  

 5904 13:58:26.307158  	TX Vref Scan disable

 5905 13:58:26.310448   == TX Byte 0 ==

 5906 13:58:26.313851  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5907 13:58:26.320363  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5908 13:58:26.320490   == TX Byte 1 ==

 5909 13:58:26.323829  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5910 13:58:26.330683  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5911 13:58:26.330783  

 5912 13:58:26.330873  [DATLAT]

 5913 13:58:26.330962  Freq=933, CH1 RK1

 5914 13:58:26.331042  

 5915 13:58:26.334201  DATLAT Default: 0xb

 5916 13:58:26.334302  0, 0xFFFF, sum = 0

 5917 13:58:26.336883  1, 0xFFFF, sum = 0

 5918 13:58:26.340592  2, 0xFFFF, sum = 0

 5919 13:58:26.340676  3, 0xFFFF, sum = 0

 5920 13:58:26.343522  4, 0xFFFF, sum = 0

 5921 13:58:26.343604  5, 0xFFFF, sum = 0

 5922 13:58:26.346968  6, 0xFFFF, sum = 0

 5923 13:58:26.347050  7, 0xFFFF, sum = 0

 5924 13:58:26.350168  8, 0xFFFF, sum = 0

 5925 13:58:26.350253  9, 0xFFFF, sum = 0

 5926 13:58:26.353859  10, 0x0, sum = 1

 5927 13:58:26.353974  11, 0x0, sum = 2

 5928 13:58:26.357338  12, 0x0, sum = 3

 5929 13:58:26.357429  13, 0x0, sum = 4

 5930 13:58:26.357519  best_step = 11

 5931 13:58:26.360276  

 5932 13:58:26.360356  ==

 5933 13:58:26.363467  Dram Type= 6, Freq= 0, CH_1, rank 1

 5934 13:58:26.366801  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5935 13:58:26.366888  ==

 5936 13:58:26.366982  RX Vref Scan: 0

 5937 13:58:26.367083  

 5938 13:58:26.370005  RX Vref 0 -> 0, step: 1

 5939 13:58:26.370092  

 5940 13:58:26.373331  RX Delay -69 -> 252, step: 4

 5941 13:58:26.379681  iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196

 5942 13:58:26.383344  iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192

 5943 13:58:26.386728  iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192

 5944 13:58:26.389662  iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196

 5945 13:58:26.393330  iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192

 5946 13:58:26.396512  iDelay=203, Bit 5, Center 102 (3 ~ 202) 200

 5947 13:58:26.402877  iDelay=203, Bit 6, Center 102 (3 ~ 202) 200

 5948 13:58:26.406779  iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196

 5949 13:58:26.409474  iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188

 5950 13:58:26.412844  iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188

 5951 13:58:26.416450  iDelay=203, Bit 10, Center 92 (-5 ~ 190) 196

 5952 13:58:26.423166  iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192

 5953 13:58:26.426163  iDelay=203, Bit 12, Center 98 (3 ~ 194) 192

 5954 13:58:26.429951  iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192

 5955 13:58:26.432928  iDelay=203, Bit 14, Center 96 (3 ~ 190) 188

 5956 13:58:26.435920  iDelay=203, Bit 15, Center 96 (-1 ~ 194) 196

 5957 13:58:26.439127  ==

 5958 13:58:26.442420  Dram Type= 6, Freq= 0, CH_1, rank 1

 5959 13:58:26.445927  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5960 13:58:26.446035  ==

 5961 13:58:26.446137  DQS Delay:

 5962 13:58:26.449202  DQS0 = 0, DQS1 = 0

 5963 13:58:26.449305  DQM Delay:

 5964 13:58:26.452702  DQM0 = 91, DQM1 = 89

 5965 13:58:26.452799  DQ Delay:

 5966 13:58:26.455938  DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88

 5967 13:58:26.459120  DQ4 =90, DQ5 =102, DQ6 =102, DQ7 =88

 5968 13:58:26.462591  DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =82

 5969 13:58:26.465981  DQ12 =98, DQ13 =94, DQ14 =96, DQ15 =96

 5970 13:58:26.466087  

 5971 13:58:26.466181  

 5972 13:58:26.472590  [DQSOSCAuto] RK1, (LSB)MR18= 0x1125, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps

 5973 13:58:26.475676  CH1 RK1: MR19=505, MR18=1125

 5974 13:58:26.482353  CH1_RK1: MR19=0x505, MR18=0x1125, DQSOSC=410, MR23=63, INC=64, DEC=42

 5975 13:58:26.485419  [RxdqsGatingPostProcess] freq 933

 5976 13:58:26.492374  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5977 13:58:26.495286  best DQS0 dly(2T, 0.5T) = (0, 11)

 5978 13:58:26.495402  best DQS1 dly(2T, 0.5T) = (0, 10)

 5979 13:58:26.498967  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 5980 13:58:26.502044  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5981 13:58:26.505245  best DQS0 dly(2T, 0.5T) = (0, 10)

 5982 13:58:26.508363  best DQS1 dly(2T, 0.5T) = (0, 10)

 5983 13:58:26.511686  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5984 13:58:26.515106  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5985 13:58:26.518617  Pre-setting of DQS Precalculation

 5986 13:58:26.525004  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5987 13:58:26.531608  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5988 13:58:26.538609  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5989 13:58:26.538718  

 5990 13:58:26.538823  

 5991 13:58:26.542181  [Calibration Summary] 1866 Mbps

 5992 13:58:26.542285  CH 0, Rank 0

 5993 13:58:26.544859  SW Impedance     : PASS

 5994 13:58:26.548056  DUTY Scan        : NO K

 5995 13:58:26.548161  ZQ Calibration   : PASS

 5996 13:58:26.551994  Jitter Meter     : NO K

 5997 13:58:26.554925  CBT Training     : PASS

 5998 13:58:26.555030  Write leveling   : PASS

 5999 13:58:26.558142  RX DQS gating    : PASS

 6000 13:58:26.561674  RX DQ/DQS(RDDQC) : PASS

 6001 13:58:26.561779  TX DQ/DQS        : PASS

 6002 13:58:26.564651  RX DATLAT        : PASS

 6003 13:58:26.568015  RX DQ/DQS(Engine): PASS

 6004 13:58:26.568123  TX OE            : NO K

 6005 13:58:26.571466  All Pass.

 6006 13:58:26.571573  

 6007 13:58:26.571670  CH 0, Rank 1

 6008 13:58:26.574398  SW Impedance     : PASS

 6009 13:58:26.574502  DUTY Scan        : NO K

 6010 13:58:26.577994  ZQ Calibration   : PASS

 6011 13:58:26.581364  Jitter Meter     : NO K

 6012 13:58:26.581471  CBT Training     : PASS

 6013 13:58:26.584337  Write leveling   : PASS

 6014 13:58:26.587853  RX DQS gating    : PASS

 6015 13:58:26.587988  RX DQ/DQS(RDDQC) : PASS

 6016 13:58:26.590957  TX DQ/DQS        : PASS

 6017 13:58:26.591067  RX DATLAT        : PASS

 6018 13:58:26.594407  RX DQ/DQS(Engine): PASS

 6019 13:58:26.597446  TX OE            : NO K

 6020 13:58:26.597551  All Pass.

 6021 13:58:26.597648  

 6022 13:58:26.597740  CH 1, Rank 0

 6023 13:58:26.600850  SW Impedance     : PASS

 6024 13:58:26.604410  DUTY Scan        : NO K

 6025 13:58:26.604517  ZQ Calibration   : PASS

 6026 13:58:26.607384  Jitter Meter     : NO K

 6027 13:58:26.610664  CBT Training     : PASS

 6028 13:58:26.610769  Write leveling   : PASS

 6029 13:58:26.614026  RX DQS gating    : PASS

 6030 13:58:26.617479  RX DQ/DQS(RDDQC) : PASS

 6031 13:58:26.617593  TX DQ/DQS        : PASS

 6032 13:58:26.620628  RX DATLAT        : PASS

 6033 13:58:26.624576  RX DQ/DQS(Engine): PASS

 6034 13:58:26.624684  TX OE            : NO K

 6035 13:58:26.627470  All Pass.

 6036 13:58:26.627574  

 6037 13:58:26.627669  CH 1, Rank 1

 6038 13:58:26.631096  SW Impedance     : PASS

 6039 13:58:26.631207  DUTY Scan        : NO K

 6040 13:58:26.633833  ZQ Calibration   : PASS

 6041 13:58:26.637275  Jitter Meter     : NO K

 6042 13:58:26.637381  CBT Training     : PASS

 6043 13:58:26.640813  Write leveling   : PASS

 6044 13:58:26.643698  RX DQS gating    : PASS

 6045 13:58:26.643802  RX DQ/DQS(RDDQC) : PASS

 6046 13:58:26.647128  TX DQ/DQS        : PASS

 6047 13:58:26.650420  RX DATLAT        : PASS

 6048 13:58:26.650526  RX DQ/DQS(Engine): PASS

 6049 13:58:26.653734  TX OE            : NO K

 6050 13:58:26.653839  All Pass.

 6051 13:58:26.653933  

 6052 13:58:26.657505  DramC Write-DBI off

 6053 13:58:26.660873  	PER_BANK_REFRESH: Hybrid Mode

 6054 13:58:26.660981  TX_TRACKING: ON

 6055 13:58:26.670540  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6056 13:58:26.673540  [FAST_K] Save calibration result to emmc

 6057 13:58:26.677010  dramc_set_vcore_voltage set vcore to 650000

 6058 13:58:26.680468  Read voltage for 400, 6

 6059 13:58:26.680574  Vio18 = 0

 6060 13:58:26.680671  Vcore = 650000

 6061 13:58:26.683814  Vdram = 0

 6062 13:58:26.683918  Vddq = 0

 6063 13:58:26.684015  Vmddr = 0

 6064 13:58:26.690394  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6065 13:58:26.693657  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6066 13:58:26.696952  MEM_TYPE=3, freq_sel=20

 6067 13:58:26.700239  sv_algorithm_assistance_LP4_800 

 6068 13:58:26.703550  ============ PULL DRAM RESETB DOWN ============

 6069 13:58:26.707156  ========== PULL DRAM RESETB DOWN end =========

 6070 13:58:26.713432  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6071 13:58:26.716947  =================================== 

 6072 13:58:26.717055  LPDDR4 DRAM CONFIGURATION

 6073 13:58:26.720520  =================================== 

 6074 13:58:26.723713  EX_ROW_EN[0]    = 0x0

 6075 13:58:26.726818  EX_ROW_EN[1]    = 0x0

 6076 13:58:26.726923  LP4Y_EN      = 0x0

 6077 13:58:26.730410  WORK_FSP     = 0x0

 6078 13:58:26.730518  WL           = 0x2

 6079 13:58:26.733231  RL           = 0x2

 6080 13:58:26.733336  BL           = 0x2

 6081 13:58:26.736890  RPST         = 0x0

 6082 13:58:26.736993  RD_PRE       = 0x0

 6083 13:58:26.740200  WR_PRE       = 0x1

 6084 13:58:26.740300  WR_PST       = 0x0

 6085 13:58:26.743266  DBI_WR       = 0x0

 6086 13:58:26.743385  DBI_RD       = 0x0

 6087 13:58:26.746583  OTF          = 0x1

 6088 13:58:26.749919  =================================== 

 6089 13:58:26.753537  =================================== 

 6090 13:58:26.753650  ANA top config

 6091 13:58:26.756362  =================================== 

 6092 13:58:26.759689  DLL_ASYNC_EN            =  0

 6093 13:58:26.763183  ALL_SLAVE_EN            =  1

 6094 13:58:26.766126  NEW_RANK_MODE           =  1

 6095 13:58:26.766239  DLL_IDLE_MODE           =  1

 6096 13:58:26.769488  LP45_APHY_COMB_EN       =  1

 6097 13:58:26.773373  TX_ODT_DIS              =  1

 6098 13:58:26.776472  NEW_8X_MODE             =  1

 6099 13:58:26.779558  =================================== 

 6100 13:58:26.782925  =================================== 

 6101 13:58:26.786306  data_rate                  =  800

 6102 13:58:26.786417  CKR                        = 1

 6103 13:58:26.789904  DQ_P2S_RATIO               = 4

 6104 13:58:26.792774  =================================== 

 6105 13:58:26.796430  CA_P2S_RATIO               = 4

 6106 13:58:26.799498  DQ_CA_OPEN                 = 0

 6107 13:58:26.802803  DQ_SEMI_OPEN               = 1

 6108 13:58:26.806151  CA_SEMI_OPEN               = 1

 6109 13:58:26.806266  CA_FULL_RATE               = 0

 6110 13:58:26.809352  DQ_CKDIV4_EN               = 0

 6111 13:58:26.813021  CA_CKDIV4_EN               = 1

 6112 13:58:26.816039  CA_PREDIV_EN               = 0

 6113 13:58:26.819261  PH8_DLY                    = 0

 6114 13:58:26.822901  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6115 13:58:26.823009  DQ_AAMCK_DIV               = 0

 6116 13:58:26.825772  CA_AAMCK_DIV               = 0

 6117 13:58:26.829355  CA_ADMCK_DIV               = 4

 6118 13:58:26.832908  DQ_TRACK_CA_EN             = 0

 6119 13:58:26.835538  CA_PICK                    = 800

 6120 13:58:26.839057  CA_MCKIO                   = 400

 6121 13:58:26.842325  MCKIO_SEMI                 = 400

 6122 13:58:26.842430  PLL_FREQ                   = 3016

 6123 13:58:26.846098  DQ_UI_PI_RATIO             = 32

 6124 13:58:26.848963  CA_UI_PI_RATIO             = 32

 6125 13:58:26.852314  =================================== 

 6126 13:58:26.855814  =================================== 

 6127 13:58:26.859180  memory_type:LPDDR4         

 6128 13:58:26.862678  GP_NUM     : 10       

 6129 13:58:26.862784  SRAM_EN    : 1       

 6130 13:58:26.865435  MD32_EN    : 0       

 6131 13:58:26.869079  =================================== 

 6132 13:58:26.872021  [ANA_INIT] >>>>>>>>>>>>>> 

 6133 13:58:26.872128  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6134 13:58:26.875458  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6135 13:58:26.878959  =================================== 

 6136 13:58:26.881885  data_rate = 800,PCW = 0X7400

 6137 13:58:26.885662  =================================== 

 6138 13:58:26.889114  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6139 13:58:26.895521  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6140 13:58:26.905427  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6141 13:58:26.912280  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6142 13:58:26.915196  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6143 13:58:26.918575  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6144 13:58:26.918680  [ANA_INIT] flow start 

 6145 13:58:26.921862  [ANA_INIT] PLL >>>>>>>> 

 6146 13:58:26.925122  [ANA_INIT] PLL <<<<<<<< 

 6147 13:58:26.925237  [ANA_INIT] MIDPI >>>>>>>> 

 6148 13:58:26.928732  [ANA_INIT] MIDPI <<<<<<<< 

 6149 13:58:26.931878  [ANA_INIT] DLL >>>>>>>> 

 6150 13:58:26.931985  [ANA_INIT] flow end 

 6151 13:58:26.938427  ============ LP4 DIFF to SE enter ============

 6152 13:58:26.941982  ============ LP4 DIFF to SE exit  ============

 6153 13:58:26.945433  [ANA_INIT] <<<<<<<<<<<<< 

 6154 13:58:26.948951  [Flow] Enable top DCM control >>>>> 

 6155 13:58:26.951752  [Flow] Enable top DCM control <<<<< 

 6156 13:58:26.951857  Enable DLL master slave shuffle 

 6157 13:58:26.958220  ============================================================== 

 6158 13:58:26.961673  Gating Mode config

 6159 13:58:26.964749  ============================================================== 

 6160 13:58:26.968258  Config description: 

 6161 13:58:26.978240  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6162 13:58:26.985205  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6163 13:58:26.988407  SELPH_MODE            0: By rank         1: By Phase 

 6164 13:58:26.994665  ============================================================== 

 6165 13:58:26.998503  GAT_TRACK_EN                 =  0

 6166 13:58:27.001981  RX_GATING_MODE               =  2

 6167 13:58:27.004745  RX_GATING_TRACK_MODE         =  2

 6168 13:58:27.008372  SELPH_MODE                   =  1

 6169 13:58:27.008477  PICG_EARLY_EN                =  1

 6170 13:58:27.012051  VALID_LAT_VALUE              =  1

 6171 13:58:27.017946  ============================================================== 

 6172 13:58:27.021527  Enter into Gating configuration >>>> 

 6173 13:58:27.024862  Exit from Gating configuration <<<< 

 6174 13:58:27.028576  Enter into  DVFS_PRE_config >>>>> 

 6175 13:58:27.037890  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6176 13:58:27.041389  Exit from  DVFS_PRE_config <<<<< 

 6177 13:58:27.044701  Enter into PICG configuration >>>> 

 6178 13:58:27.048093  Exit from PICG configuration <<<< 

 6179 13:58:27.051546  [RX_INPUT] configuration >>>>> 

 6180 13:58:27.054497  [RX_INPUT] configuration <<<<< 

 6181 13:58:27.057886  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6182 13:58:27.064862  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6183 13:58:27.071081  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6184 13:58:27.077575  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6185 13:58:27.084729  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6186 13:58:27.091580  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6187 13:58:27.094084  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6188 13:58:27.097372  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6189 13:58:27.100923  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6190 13:58:27.107901  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6191 13:58:27.110822  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6192 13:58:27.114188  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6193 13:58:27.117727  =================================== 

 6194 13:58:27.121414  LPDDR4 DRAM CONFIGURATION

 6195 13:58:27.124153  =================================== 

 6196 13:58:27.124255  EX_ROW_EN[0]    = 0x0

 6197 13:58:27.127806  EX_ROW_EN[1]    = 0x0

 6198 13:58:27.127909  LP4Y_EN      = 0x0

 6199 13:58:27.130904  WORK_FSP     = 0x0

 6200 13:58:27.131007  WL           = 0x2

 6201 13:58:27.134442  RL           = 0x2

 6202 13:58:27.138027  BL           = 0x2

 6203 13:58:27.138128  RPST         = 0x0

 6204 13:58:27.140965  RD_PRE       = 0x0

 6205 13:58:27.141067  WR_PRE       = 0x1

 6206 13:58:27.143881  WR_PST       = 0x0

 6207 13:58:27.143985  DBI_WR       = 0x0

 6208 13:58:27.147556  DBI_RD       = 0x0

 6209 13:58:27.147661  OTF          = 0x1

 6210 13:58:27.150557  =================================== 

 6211 13:58:27.154566  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6212 13:58:27.160640  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6213 13:58:27.164375  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6214 13:58:27.167384  =================================== 

 6215 13:58:27.170485  LPDDR4 DRAM CONFIGURATION

 6216 13:58:27.174122  =================================== 

 6217 13:58:27.174230  EX_ROW_EN[0]    = 0x10

 6218 13:58:27.177021  EX_ROW_EN[1]    = 0x0

 6219 13:58:27.177126  LP4Y_EN      = 0x0

 6220 13:58:27.180725  WORK_FSP     = 0x0

 6221 13:58:27.180832  WL           = 0x2

 6222 13:58:27.183534  RL           = 0x2

 6223 13:58:27.187153  BL           = 0x2

 6224 13:58:27.187258  RPST         = 0x0

 6225 13:58:27.190458  RD_PRE       = 0x0

 6226 13:58:27.190564  WR_PRE       = 0x1

 6227 13:58:27.193693  WR_PST       = 0x0

 6228 13:58:27.193802  DBI_WR       = 0x0

 6229 13:58:27.197339  DBI_RD       = 0x0

 6230 13:58:27.197441  OTF          = 0x1

 6231 13:58:27.200665  =================================== 

 6232 13:58:27.207380  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6233 13:58:27.210907  nWR fixed to 30

 6234 13:58:27.213987  [ModeRegInit_LP4] CH0 RK0

 6235 13:58:27.214090  [ModeRegInit_LP4] CH0 RK1

 6236 13:58:27.217645  [ModeRegInit_LP4] CH1 RK0

 6237 13:58:27.220644  [ModeRegInit_LP4] CH1 RK1

 6238 13:58:27.220748  match AC timing 19

 6239 13:58:27.227498  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6240 13:58:27.230403  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6241 13:58:27.233864  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6242 13:58:27.240452  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6243 13:58:27.243898  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6244 13:58:27.244002  ==

 6245 13:58:27.246972  Dram Type= 6, Freq= 0, CH_0, rank 0

 6246 13:58:27.250639  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6247 13:58:27.250744  ==

 6248 13:58:27.257119  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6249 13:58:27.263919  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 6250 13:58:27.267310  [CA 0] Center 36 (8~64) winsize 57

 6251 13:58:27.270765  [CA 1] Center 36 (8~64) winsize 57

 6252 13:58:27.273685  [CA 2] Center 36 (8~64) winsize 57

 6253 13:58:27.277417  [CA 3] Center 36 (8~64) winsize 57

 6254 13:58:27.277501  [CA 4] Center 36 (8~64) winsize 57

 6255 13:58:27.280668  [CA 5] Center 36 (8~64) winsize 57

 6256 13:58:27.280742  

 6257 13:58:27.287326  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 6258 13:58:27.287460  

 6259 13:58:27.290637  [CATrainingPosCal] consider 1 rank data

 6260 13:58:27.293655  u2DelayCellTimex100 = 270/100 ps

 6261 13:58:27.296909  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6262 13:58:27.300536  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6263 13:58:27.303485  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6264 13:58:27.307118  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6265 13:58:27.310040  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6266 13:58:27.313884  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6267 13:58:27.313971  

 6268 13:58:27.316629  CA PerBit enable=1, Macro0, CA PI delay=36

 6269 13:58:27.316737  

 6270 13:58:27.320123  [CBTSetCACLKResult] CA Dly = 36

 6271 13:58:27.323294  CS Dly: 1 (0~32)

 6272 13:58:27.323447  ==

 6273 13:58:27.326774  Dram Type= 6, Freq= 0, CH_0, rank 1

 6274 13:58:27.330383  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6275 13:58:27.330489  ==

 6276 13:58:27.336764  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6277 13:58:27.343152  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6278 13:58:27.343256  [CA 0] Center 36 (8~64) winsize 57

 6279 13:58:27.346728  [CA 1] Center 36 (8~64) winsize 57

 6280 13:58:27.350312  [CA 2] Center 36 (8~64) winsize 57

 6281 13:58:27.353149  [CA 3] Center 36 (8~64) winsize 57

 6282 13:58:27.356666  [CA 4] Center 36 (8~64) winsize 57

 6283 13:58:27.360229  [CA 5] Center 36 (8~64) winsize 57

 6284 13:58:27.360308  

 6285 13:58:27.363098  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6286 13:58:27.363197  

 6287 13:58:27.366380  [CATrainingPosCal] consider 2 rank data

 6288 13:58:27.370048  u2DelayCellTimex100 = 270/100 ps

 6289 13:58:27.373558  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6290 13:58:27.379558  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6291 13:58:27.383135  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6292 13:58:27.386348  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6293 13:58:27.389927  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6294 13:58:27.392822  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6295 13:58:27.392896  

 6296 13:58:27.396988  CA PerBit enable=1, Macro0, CA PI delay=36

 6297 13:58:27.397063  

 6298 13:58:27.399506  [CBTSetCACLKResult] CA Dly = 36

 6299 13:58:27.399585  CS Dly: 1 (0~32)

 6300 13:58:27.403119  

 6301 13:58:27.406464  ----->DramcWriteLeveling(PI) begin...

 6302 13:58:27.406552  ==

 6303 13:58:27.409674  Dram Type= 6, Freq= 0, CH_0, rank 0

 6304 13:58:27.412956  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6305 13:58:27.413062  ==

 6306 13:58:27.416191  Write leveling (Byte 0): 40 => 8

 6307 13:58:27.419210  Write leveling (Byte 1): 40 => 8

 6308 13:58:27.422997  DramcWriteLeveling(PI) end<-----

 6309 13:58:27.423100  

 6310 13:58:27.423200  ==

 6311 13:58:27.425824  Dram Type= 6, Freq= 0, CH_0, rank 0

 6312 13:58:27.429287  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6313 13:58:27.429409  ==

 6314 13:58:27.432729  [Gating] SW mode calibration

 6315 13:58:27.439661  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6316 13:58:27.446386  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6317 13:58:27.449478   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6318 13:58:27.452882   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6319 13:58:27.459642   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6320 13:58:27.463434   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6321 13:58:27.466646   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6322 13:58:27.469423   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6323 13:58:27.476257   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6324 13:58:27.479196   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6325 13:58:27.483081   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6326 13:58:27.485852  Total UI for P1: 0, mck2ui 16

 6327 13:58:27.489214  best dqsien dly found for B0: ( 0, 14, 24)

 6328 13:58:27.492402  Total UI for P1: 0, mck2ui 16

 6329 13:58:27.495940  best dqsien dly found for B1: ( 0, 14, 24)

 6330 13:58:27.499433  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6331 13:58:27.505808  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6332 13:58:27.505889  

 6333 13:58:27.509127  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6334 13:58:27.512480  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6335 13:58:27.515754  [Gating] SW calibration Done

 6336 13:58:27.515877  ==

 6337 13:58:27.519525  Dram Type= 6, Freq= 0, CH_0, rank 0

 6338 13:58:27.522889  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6339 13:58:27.522971  ==

 6340 13:58:27.523036  RX Vref Scan: 0

 6341 13:58:27.525624  

 6342 13:58:27.525705  RX Vref 0 -> 0, step: 1

 6343 13:58:27.525769  

 6344 13:58:27.528986  RX Delay -410 -> 252, step: 16

 6345 13:58:27.532116  iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512

 6346 13:58:27.538847  iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512

 6347 13:58:27.542329  iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512

 6348 13:58:27.545567  iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512

 6349 13:58:27.548737  iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512

 6350 13:58:27.555723  iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512

 6351 13:58:27.559100  iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512

 6352 13:58:27.561933  iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512

 6353 13:58:27.565773  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6354 13:58:27.571880  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6355 13:58:27.575334  iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528

 6356 13:58:27.578434  iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528

 6357 13:58:27.585232  iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512

 6358 13:58:27.588661  iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512

 6359 13:58:27.591769  iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512

 6360 13:58:27.595208  iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512

 6361 13:58:27.595290  ==

 6362 13:58:27.598589  Dram Type= 6, Freq= 0, CH_0, rank 0

 6363 13:58:27.604876  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6364 13:58:27.604990  ==

 6365 13:58:27.605089  DQS Delay:

 6366 13:58:27.608582  DQS0 = 59, DQS1 = 59

 6367 13:58:27.608682  DQM Delay:

 6368 13:58:27.611485  DQM0 = 18, DQM1 = 10

 6369 13:58:27.611581  DQ Delay:

 6370 13:58:27.615078  DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16

 6371 13:58:27.618166  DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32

 6372 13:58:27.621718  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8

 6373 13:58:27.624678  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6374 13:58:27.624783  

 6375 13:58:27.624888  

 6376 13:58:27.624979  ==

 6377 13:58:27.628206  Dram Type= 6, Freq= 0, CH_0, rank 0

 6378 13:58:27.631620  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6379 13:58:27.631701  ==

 6380 13:58:27.631765  

 6381 13:58:27.631825  

 6382 13:58:27.634972  	TX Vref Scan disable

 6383 13:58:27.635073   == TX Byte 0 ==

 6384 13:58:27.641167  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6385 13:58:27.644635  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6386 13:58:27.644740   == TX Byte 1 ==

 6387 13:58:27.651383  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6388 13:58:27.654647  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6389 13:58:27.654757  ==

 6390 13:58:27.657632  Dram Type= 6, Freq= 0, CH_0, rank 0

 6391 13:58:27.661248  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6392 13:58:27.661353  ==

 6393 13:58:27.661447  

 6394 13:58:27.661539  

 6395 13:58:27.664349  	TX Vref Scan disable

 6396 13:58:27.664453   == TX Byte 0 ==

 6397 13:58:27.671009  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6398 13:58:27.674454  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6399 13:58:27.674569   == TX Byte 1 ==

 6400 13:58:27.680835  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6401 13:58:27.684211  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6402 13:58:27.684314  

 6403 13:58:27.684406  [DATLAT]

 6404 13:58:27.687862  Freq=400, CH0 RK0

 6405 13:58:27.687968  

 6406 13:58:27.688063  DATLAT Default: 0xf

 6407 13:58:27.690729  0, 0xFFFF, sum = 0

 6408 13:58:27.690835  1, 0xFFFF, sum = 0

 6409 13:58:27.694249  2, 0xFFFF, sum = 0

 6410 13:58:27.694355  3, 0xFFFF, sum = 0

 6411 13:58:27.697332  4, 0xFFFF, sum = 0

 6412 13:58:27.697441  5, 0xFFFF, sum = 0

 6413 13:58:27.700852  6, 0xFFFF, sum = 0

 6414 13:58:27.704231  7, 0xFFFF, sum = 0

 6415 13:58:27.704339  8, 0xFFFF, sum = 0

 6416 13:58:27.707752  9, 0xFFFF, sum = 0

 6417 13:58:27.707858  10, 0xFFFF, sum = 0

 6418 13:58:27.710853  11, 0xFFFF, sum = 0

 6419 13:58:27.710956  12, 0xFFFF, sum = 0

 6420 13:58:27.714197  13, 0x0, sum = 1

 6421 13:58:27.714303  14, 0x0, sum = 2

 6422 13:58:27.717766  15, 0x0, sum = 3

 6423 13:58:27.717874  16, 0x0, sum = 4

 6424 13:58:27.717970  best_step = 14

 6425 13:58:27.720648  

 6426 13:58:27.720749  ==

 6427 13:58:27.723977  Dram Type= 6, Freq= 0, CH_0, rank 0

 6428 13:58:27.727553  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6429 13:58:27.727655  ==

 6430 13:58:27.727747  RX Vref Scan: 1

 6431 13:58:27.727839  

 6432 13:58:27.730407  RX Vref 0 -> 0, step: 1

 6433 13:58:27.730495  

 6434 13:58:27.733706  RX Delay -359 -> 252, step: 8

 6435 13:58:27.733804  

 6436 13:58:27.737026  Set Vref, RX VrefLevel [Byte0]: 61

 6437 13:58:27.740468                           [Byte1]: 49

 6438 13:58:27.744438  

 6439 13:58:27.744540  Final RX Vref Byte 0 = 61 to rank0

 6440 13:58:27.747644  Final RX Vref Byte 1 = 49 to rank0

 6441 13:58:27.751356  Final RX Vref Byte 0 = 61 to rank1

 6442 13:58:27.754279  Final RX Vref Byte 1 = 49 to rank1==

 6443 13:58:27.757689  Dram Type= 6, Freq= 0, CH_0, rank 0

 6444 13:58:27.764039  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6445 13:58:27.764153  ==

 6446 13:58:27.764249  DQS Delay:

 6447 13:58:27.767724  DQS0 = 60, DQS1 = 68

 6448 13:58:27.767871  DQM Delay:

 6449 13:58:27.767966  DQM0 = 14, DQM1 = 14

 6450 13:58:27.771118  DQ Delay:

 6451 13:58:27.774385  DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12

 6452 13:58:27.777478  DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24

 6453 13:58:27.777584  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8

 6454 13:58:27.784081  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24

 6455 13:58:27.784192  

 6456 13:58:27.784287  

 6457 13:58:27.790642  [DQSOSCAuto] RK0, (LSB)MR18= 0x8382, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps

 6458 13:58:27.793804  CH0 RK0: MR19=C0C, MR18=8382

 6459 13:58:27.800517  CH0_RK0: MR19=0xC0C, MR18=0x8382, DQSOSC=393, MR23=63, INC=382, DEC=254

 6460 13:58:27.800630  ==

 6461 13:58:27.803887  Dram Type= 6, Freq= 0, CH_0, rank 1

 6462 13:58:27.807554  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6463 13:58:27.807656  ==

 6464 13:58:27.810642  [Gating] SW mode calibration

 6465 13:58:27.817500  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6466 13:58:27.824068  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6467 13:58:27.827345   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6468 13:58:27.830446   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6469 13:58:27.837302   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6470 13:58:27.840671   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6471 13:58:27.843641   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6472 13:58:27.850389   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6473 13:58:27.853630   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6474 13:58:27.857038   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6475 13:58:27.863697   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6476 13:58:27.863804  Total UI for P1: 0, mck2ui 16

 6477 13:58:27.870476  best dqsien dly found for B0: ( 0, 14, 24)

 6478 13:58:27.870583  Total UI for P1: 0, mck2ui 16

 6479 13:58:27.876854  best dqsien dly found for B1: ( 0, 14, 24)

 6480 13:58:27.880122  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6481 13:58:27.883420  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6482 13:58:27.883519  

 6483 13:58:27.886960  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6484 13:58:27.890041  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6485 13:58:27.893338  [Gating] SW calibration Done

 6486 13:58:27.893442  ==

 6487 13:58:27.896626  Dram Type= 6, Freq= 0, CH_0, rank 1

 6488 13:58:27.899843  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6489 13:58:27.899947  ==

 6490 13:58:27.903392  RX Vref Scan: 0

 6491 13:58:27.903512  

 6492 13:58:27.903605  RX Vref 0 -> 0, step: 1

 6493 13:58:27.903701  

 6494 13:58:27.906784  RX Delay -410 -> 252, step: 16

 6495 13:58:27.913280  iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512

 6496 13:58:27.916492  iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512

 6497 13:58:27.920139  iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512

 6498 13:58:27.923516  iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528

 6499 13:58:27.929921  iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512

 6500 13:58:27.933086  iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512

 6501 13:58:27.936536  iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528

 6502 13:58:27.940249  iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528

 6503 13:58:27.946395  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6504 13:58:27.949542  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6505 13:58:27.953695  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6506 13:58:27.956178  iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512

 6507 13:58:27.962817  iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512

 6508 13:58:27.966187  iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512

 6509 13:58:27.969923  iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512

 6510 13:58:27.972703  iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512

 6511 13:58:27.976381  ==

 6512 13:58:27.979779  Dram Type= 6, Freq= 0, CH_0, rank 1

 6513 13:58:27.982756  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6514 13:58:27.982862  ==

 6515 13:58:27.982958  DQS Delay:

 6516 13:58:27.986489  DQS0 = 59, DQS1 = 59

 6517 13:58:27.986593  DQM Delay:

 6518 13:58:27.989591  DQM0 = 15, DQM1 = 10

 6519 13:58:27.989692  DQ Delay:

 6520 13:58:27.992681  DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8

 6521 13:58:27.996130  DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24

 6522 13:58:27.999245  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0

 6523 13:58:28.003239  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6524 13:58:28.003348  

 6525 13:58:28.003487  

 6526 13:58:28.003596  ==

 6527 13:58:28.005968  Dram Type= 6, Freq= 0, CH_0, rank 1

 6528 13:58:28.009648  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6529 13:58:28.009753  ==

 6530 13:58:28.009847  

 6531 13:58:28.009939  

 6532 13:58:28.012345  	TX Vref Scan disable

 6533 13:58:28.012449   == TX Byte 0 ==

 6534 13:58:28.019217  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6535 13:58:28.022357  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6536 13:58:28.022462   == TX Byte 1 ==

 6537 13:58:28.029494  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6538 13:58:28.032713  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6539 13:58:28.032821  ==

 6540 13:58:28.035674  Dram Type= 6, Freq= 0, CH_0, rank 1

 6541 13:58:28.039051  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6542 13:58:28.039149  ==

 6543 13:58:28.039243  

 6544 13:58:28.039333  

 6545 13:58:28.042571  	TX Vref Scan disable

 6546 13:58:28.042673   == TX Byte 0 ==

 6547 13:58:28.048972  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6548 13:58:28.052643  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6549 13:58:28.052748   == TX Byte 1 ==

 6550 13:58:28.059668  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6551 13:58:28.062389  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6552 13:58:28.062494  

 6553 13:58:28.062589  [DATLAT]

 6554 13:58:28.065613  Freq=400, CH0 RK1

 6555 13:58:28.065712  

 6556 13:58:28.065803  DATLAT Default: 0xe

 6557 13:58:28.069150  0, 0xFFFF, sum = 0

 6558 13:58:28.069257  1, 0xFFFF, sum = 0

 6559 13:58:28.072575  2, 0xFFFF, sum = 0

 6560 13:58:28.072682  3, 0xFFFF, sum = 0

 6561 13:58:28.075514  4, 0xFFFF, sum = 0

 6562 13:58:28.075621  5, 0xFFFF, sum = 0

 6563 13:58:28.079108  6, 0xFFFF, sum = 0

 6564 13:58:28.082459  7, 0xFFFF, sum = 0

 6565 13:58:28.082565  8, 0xFFFF, sum = 0

 6566 13:58:28.085609  9, 0xFFFF, sum = 0

 6567 13:58:28.085712  10, 0xFFFF, sum = 0

 6568 13:58:28.089062  11, 0xFFFF, sum = 0

 6569 13:58:28.089165  12, 0xFFFF, sum = 0

 6570 13:58:28.092077  13, 0x0, sum = 1

 6571 13:58:28.092179  14, 0x0, sum = 2

 6572 13:58:28.095551  15, 0x0, sum = 3

 6573 13:58:28.095658  16, 0x0, sum = 4

 6574 13:58:28.098553  best_step = 14

 6575 13:58:28.098657  

 6576 13:58:28.098752  ==

 6577 13:58:28.102260  Dram Type= 6, Freq= 0, CH_0, rank 1

 6578 13:58:28.105375  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6579 13:58:28.105481  ==

 6580 13:58:28.105580  RX Vref Scan: 0

 6581 13:58:28.105673  

 6582 13:58:28.108596  RX Vref 0 -> 0, step: 1

 6583 13:58:28.108698  

 6584 13:58:28.112083  RX Delay -359 -> 252, step: 8

 6585 13:58:28.119188  iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504

 6586 13:58:28.122641  iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504

 6587 13:58:28.125935  iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504

 6588 13:58:28.129093  iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504

 6589 13:58:28.135964  iDelay=217, Bit 4, Center -48 (-295 ~ 200) 496

 6590 13:58:28.139117  iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504

 6591 13:58:28.142440  iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512

 6592 13:58:28.145800  iDelay=217, Bit 7, Center -40 (-295 ~ 216) 512

 6593 13:58:28.152594  iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496

 6594 13:58:28.155721  iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496

 6595 13:58:28.158963  iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504

 6596 13:58:28.165458  iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496

 6597 13:58:28.168845  iDelay=217, Bit 12, Center -52 (-303 ~ 200) 504

 6598 13:58:28.172021  iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504

 6599 13:58:28.175454  iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504

 6600 13:58:28.182166  iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496

 6601 13:58:28.182274  ==

 6602 13:58:28.185400  Dram Type= 6, Freq= 0, CH_0, rank 1

 6603 13:58:28.188944  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6604 13:58:28.189053  ==

 6605 13:58:28.189148  DQS Delay:

 6606 13:58:28.192007  DQS0 = 60, DQS1 = 72

 6607 13:58:28.192108  DQM Delay:

 6608 13:58:28.195315  DQM0 = 11, DQM1 = 17

 6609 13:58:28.195460  DQ Delay:

 6610 13:58:28.198716  DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8

 6611 13:58:28.202237  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20

 6612 13:58:28.205206  DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8

 6613 13:58:28.208761  DQ12 =20, DQ13 =28, DQ14 =28, DQ15 =24

 6614 13:58:28.208860  

 6615 13:58:28.208952  

 6616 13:58:28.215353  [DQSOSCAuto] RK1, (LSB)MR18= 0xca7e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps

 6617 13:58:28.218695  CH0 RK1: MR19=C0C, MR18=CA7E

 6618 13:58:28.225647  CH0_RK1: MR19=0xC0C, MR18=0xCA7E, DQSOSC=384, MR23=63, INC=400, DEC=267

 6619 13:58:28.228373  [RxdqsGatingPostProcess] freq 400

 6620 13:58:28.235571  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6621 13:58:28.238455  best DQS0 dly(2T, 0.5T) = (0, 10)

 6622 13:58:28.238538  best DQS1 dly(2T, 0.5T) = (0, 10)

 6623 13:58:28.241830  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6624 13:58:28.245266  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6625 13:58:28.248405  best DQS0 dly(2T, 0.5T) = (0, 10)

 6626 13:58:28.251956  best DQS1 dly(2T, 0.5T) = (0, 10)

 6627 13:58:28.255260  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6628 13:58:28.258500  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6629 13:58:28.261978  Pre-setting of DQS Precalculation

 6630 13:58:28.268384  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6631 13:58:28.268482  ==

 6632 13:58:28.271741  Dram Type= 6, Freq= 0, CH_1, rank 0

 6633 13:58:28.275221  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6634 13:58:28.275304  ==

 6635 13:58:28.281939  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6636 13:58:28.284847  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6637 13:58:28.288430  [CA 0] Center 36 (8~64) winsize 57

 6638 13:58:28.291953  [CA 1] Center 36 (8~64) winsize 57

 6639 13:58:28.294942  [CA 2] Center 36 (8~64) winsize 57

 6640 13:58:28.298567  [CA 3] Center 36 (8~64) winsize 57

 6641 13:58:28.301663  [CA 4] Center 36 (8~64) winsize 57

 6642 13:58:28.304877  [CA 5] Center 36 (8~64) winsize 57

 6643 13:58:28.304960  

 6644 13:58:28.308042  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6645 13:58:28.308125  

 6646 13:58:28.311319  [CATrainingPosCal] consider 1 rank data

 6647 13:58:28.314958  u2DelayCellTimex100 = 270/100 ps

 6648 13:58:28.317785  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6649 13:58:28.321645  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6650 13:58:28.327959  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6651 13:58:28.331526  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6652 13:58:28.334729  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6653 13:58:28.337861  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6654 13:58:28.337945  

 6655 13:58:28.341349  CA PerBit enable=1, Macro0, CA PI delay=36

 6656 13:58:28.341432  

 6657 13:58:28.344571  [CBTSetCACLKResult] CA Dly = 36

 6658 13:58:28.344654  CS Dly: 1 (0~32)

 6659 13:58:28.344721  ==

 6660 13:58:28.348286  Dram Type= 6, Freq= 0, CH_1, rank 1

 6661 13:58:28.354352  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6662 13:58:28.354451  ==

 6663 13:58:28.357914  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6664 13:58:28.364563  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6665 13:58:28.368097  [CA 0] Center 36 (8~64) winsize 57

 6666 13:58:28.370961  [CA 1] Center 36 (8~64) winsize 57

 6667 13:58:28.374226  [CA 2] Center 36 (8~64) winsize 57

 6668 13:58:28.377914  [CA 3] Center 36 (8~64) winsize 57

 6669 13:58:28.380868  [CA 4] Center 36 (8~64) winsize 57

 6670 13:58:28.384323  [CA 5] Center 36 (8~64) winsize 57

 6671 13:58:28.384406  

 6672 13:58:28.387838  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6673 13:58:28.387920  

 6674 13:58:28.390989  [CATrainingPosCal] consider 2 rank data

 6675 13:58:28.394042  u2DelayCellTimex100 = 270/100 ps

 6676 13:58:28.397561  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6677 13:58:28.400946  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6678 13:58:28.404517  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6679 13:58:28.407446  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6680 13:58:28.411128  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6681 13:58:28.417437  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6682 13:58:28.417549  

 6683 13:58:28.420991  CA PerBit enable=1, Macro0, CA PI delay=36

 6684 13:58:28.421074  

 6685 13:58:28.424423  [CBTSetCACLKResult] CA Dly = 36

 6686 13:58:28.424506  CS Dly: 1 (0~32)

 6687 13:58:28.424573  

 6688 13:58:28.427661  ----->DramcWriteLeveling(PI) begin...

 6689 13:58:28.427745  ==

 6690 13:58:28.431085  Dram Type= 6, Freq= 0, CH_1, rank 0

 6691 13:58:28.434112  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6692 13:58:28.437564  ==

 6693 13:58:28.437646  Write leveling (Byte 0): 40 => 8

 6694 13:58:28.440902  Write leveling (Byte 1): 40 => 8

 6695 13:58:28.444497  DramcWriteLeveling(PI) end<-----

 6696 13:58:28.444595  

 6697 13:58:28.444676  ==

 6698 13:58:28.447223  Dram Type= 6, Freq= 0, CH_1, rank 0

 6699 13:58:28.454039  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6700 13:58:28.454148  ==

 6701 13:58:28.457053  [Gating] SW mode calibration

 6702 13:58:28.464243  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6703 13:58:28.467190  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6704 13:58:28.473627   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6705 13:58:28.477118   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6706 13:58:28.480518   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6707 13:58:28.487008   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6708 13:58:28.490532   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6709 13:58:28.493865   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6710 13:58:28.500314   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6711 13:58:28.504121   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6712 13:58:28.506838   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6713 13:58:28.510673  Total UI for P1: 0, mck2ui 16

 6714 13:58:28.513471  best dqsien dly found for B0: ( 0, 14, 24)

 6715 13:58:28.517037  Total UI for P1: 0, mck2ui 16

 6716 13:58:28.520632  best dqsien dly found for B1: ( 0, 14, 24)

 6717 13:58:28.523633  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6718 13:58:28.527027  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6719 13:58:28.527105  

 6720 13:58:28.530044  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6721 13:58:28.537135  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6722 13:58:28.537218  [Gating] SW calibration Done

 6723 13:58:28.537284  ==

 6724 13:58:28.539946  Dram Type= 6, Freq= 0, CH_1, rank 0

 6725 13:58:28.546690  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6726 13:58:28.546773  ==

 6727 13:58:28.546839  RX Vref Scan: 0

 6728 13:58:28.546900  

 6729 13:58:28.550306  RX Vref 0 -> 0, step: 1

 6730 13:58:28.550389  

 6731 13:58:28.553419  RX Delay -410 -> 252, step: 16

 6732 13:58:28.556717  iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512

 6733 13:58:28.559943  iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512

 6734 13:58:28.566626  iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528

 6735 13:58:28.569809  iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512

 6736 13:58:28.573416  iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512

 6737 13:58:28.576384  iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512

 6738 13:58:28.583354  iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512

 6739 13:58:28.586246  iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512

 6740 13:58:28.589513  iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528

 6741 13:58:28.593154  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6742 13:58:28.599539  iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528

 6743 13:58:28.603317  iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528

 6744 13:58:28.606224  iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528

 6745 13:58:28.612791  iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512

 6746 13:58:28.616420  iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512

 6747 13:58:28.619862  iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528

 6748 13:58:28.619936  ==

 6749 13:58:28.622957  Dram Type= 6, Freq= 0, CH_1, rank 0

 6750 13:58:28.626272  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6751 13:58:28.626347  ==

 6752 13:58:28.629744  DQS Delay:

 6753 13:58:28.629843  DQS0 = 51, DQS1 = 67

 6754 13:58:28.632995  DQM Delay:

 6755 13:58:28.633069  DQM0 = 13, DQM1 = 19

 6756 13:58:28.635972  DQ Delay:

 6757 13:58:28.636046  DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8

 6758 13:58:28.639466  DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8

 6759 13:58:28.642605  DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16

 6760 13:58:28.646009  DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32

 6761 13:58:28.646111  

 6762 13:58:28.646207  

 6763 13:58:28.646296  ==

 6764 13:58:28.649559  Dram Type= 6, Freq= 0, CH_1, rank 0

 6765 13:58:28.655879  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6766 13:58:28.655962  ==

 6767 13:58:28.656028  

 6768 13:58:28.656089  

 6769 13:58:28.656148  	TX Vref Scan disable

 6770 13:58:28.659407   == TX Byte 0 ==

 6771 13:58:28.662706  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6772 13:58:28.666009  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6773 13:58:28.669412   == TX Byte 1 ==

 6774 13:58:28.673009  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6775 13:58:28.676150  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6776 13:58:28.679391  ==

 6777 13:58:28.679487  Dram Type= 6, Freq= 0, CH_1, rank 0

 6778 13:58:28.686088  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6779 13:58:28.686171  ==

 6780 13:58:28.686236  

 6781 13:58:28.686296  

 6782 13:58:28.689448  	TX Vref Scan disable

 6783 13:58:28.689530   == TX Byte 0 ==

 6784 13:58:28.692956  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6785 13:58:28.695893  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6786 13:58:28.699416   == TX Byte 1 ==

 6787 13:58:28.702427  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6788 13:58:28.705801  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6789 13:58:28.709405  

 6790 13:58:28.709486  [DATLAT]

 6791 13:58:28.709551  Freq=400, CH1 RK0

 6792 13:58:28.709613  

 6793 13:58:28.712498  DATLAT Default: 0xf

 6794 13:58:28.712581  0, 0xFFFF, sum = 0

 6795 13:58:28.715819  1, 0xFFFF, sum = 0

 6796 13:58:28.715956  2, 0xFFFF, sum = 0

 6797 13:58:28.719047  3, 0xFFFF, sum = 0

 6798 13:58:28.719132  4, 0xFFFF, sum = 0

 6799 13:58:28.722330  5, 0xFFFF, sum = 0

 6800 13:58:28.722414  6, 0xFFFF, sum = 0

 6801 13:58:28.725988  7, 0xFFFF, sum = 0

 6802 13:58:28.728868  8, 0xFFFF, sum = 0

 6803 13:58:28.728969  9, 0xFFFF, sum = 0

 6804 13:58:28.732368  10, 0xFFFF, sum = 0

 6805 13:58:28.732453  11, 0xFFFF, sum = 0

 6806 13:58:28.736001  12, 0xFFFF, sum = 0

 6807 13:58:28.736085  13, 0x0, sum = 1

 6808 13:58:28.738994  14, 0x0, sum = 2

 6809 13:58:28.739078  15, 0x0, sum = 3

 6810 13:58:28.742320  16, 0x0, sum = 4

 6811 13:58:28.742404  best_step = 14

 6812 13:58:28.742470  

 6813 13:58:28.742532  ==

 6814 13:58:28.745838  Dram Type= 6, Freq= 0, CH_1, rank 0

 6815 13:58:28.748853  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6816 13:58:28.748937  ==

 6817 13:58:28.752264  RX Vref Scan: 1

 6818 13:58:28.752376  

 6819 13:58:28.755684  RX Vref 0 -> 0, step: 1

 6820 13:58:28.755796  

 6821 13:58:28.755892  RX Delay -375 -> 252, step: 8

 6822 13:58:28.758852  

 6823 13:58:28.758934  Set Vref, RX VrefLevel [Byte0]: 59

 6824 13:58:28.762521                           [Byte1]: 57

 6825 13:58:28.767999  

 6826 13:58:28.768127  Final RX Vref Byte 0 = 59 to rank0

 6827 13:58:28.771549  Final RX Vref Byte 1 = 57 to rank0

 6828 13:58:28.774493  Final RX Vref Byte 0 = 59 to rank1

 6829 13:58:28.777887  Final RX Vref Byte 1 = 57 to rank1==

 6830 13:58:28.781430  Dram Type= 6, Freq= 0, CH_1, rank 0

 6831 13:58:28.787546  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6832 13:58:28.787659  ==

 6833 13:58:28.787725  DQS Delay:

 6834 13:58:28.791078  DQS0 = 52, DQS1 = 72

 6835 13:58:28.791163  DQM Delay:

 6836 13:58:28.791229  DQM0 = 9, DQM1 = 17

 6837 13:58:28.794536  DQ Delay:

 6838 13:58:28.797788  DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4

 6839 13:58:28.797889  DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4

 6840 13:58:28.801278  DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =12

 6841 13:58:28.804615  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6842 13:58:28.804699  

 6843 13:58:28.807344  

 6844 13:58:28.814257  [DQSOSCAuto] RK0, (LSB)MR18= 0x576a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps

 6845 13:58:28.817864  CH1 RK0: MR19=C0C, MR18=576A

 6846 13:58:28.824188  CH1_RK0: MR19=0xC0C, MR18=0x576A, DQSOSC=396, MR23=63, INC=376, DEC=251

 6847 13:58:28.824272  ==

 6848 13:58:28.827723  Dram Type= 6, Freq= 0, CH_1, rank 1

 6849 13:58:28.830681  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6850 13:58:28.830791  ==

 6851 13:58:28.834243  [Gating] SW mode calibration

 6852 13:58:28.840923  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6853 13:58:28.847256  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6854 13:58:28.850736   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6855 13:58:28.854181   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6856 13:58:28.857454   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6857 13:58:28.864099   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6858 13:58:28.867231   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6859 13:58:28.870687   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6860 13:58:28.877588   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6861 13:58:28.880423   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6862 13:58:28.884061   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6863 13:58:28.887235  Total UI for P1: 0, mck2ui 16

 6864 13:58:28.890497  best dqsien dly found for B0: ( 0, 14, 24)

 6865 13:58:28.893891  Total UI for P1: 0, mck2ui 16

 6866 13:58:28.897412  best dqsien dly found for B1: ( 0, 14, 24)

 6867 13:58:28.900384  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6868 13:58:28.907121  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6869 13:58:28.907203  

 6870 13:58:28.910262  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6871 13:58:28.913816  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6872 13:58:28.917355  [Gating] SW calibration Done

 6873 13:58:28.917437  ==

 6874 13:58:28.920828  Dram Type= 6, Freq= 0, CH_1, rank 1

 6875 13:58:28.923650  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6876 13:58:28.923733  ==

 6877 13:58:28.927192  RX Vref Scan: 0

 6878 13:58:28.927273  

 6879 13:58:28.927338  RX Vref 0 -> 0, step: 1

 6880 13:58:28.927438  

 6881 13:58:28.930387  RX Delay -410 -> 252, step: 16

 6882 13:58:28.933715  iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528

 6883 13:58:28.940227  iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512

 6884 13:58:28.943701  iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512

 6885 13:58:28.946952  iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512

 6886 13:58:28.950075  iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512

 6887 13:58:28.956935  iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512

 6888 13:58:28.960550  iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512

 6889 13:58:28.963491  iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512

 6890 13:58:28.966744  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6891 13:58:28.973476  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6892 13:58:28.976964  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6893 13:58:28.979967  iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528

 6894 13:58:28.983648  iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528

 6895 13:58:28.990149  iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528

 6896 13:58:28.993779  iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528

 6897 13:58:28.996738  iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528

 6898 13:58:28.996822  ==

 6899 13:58:29.000229  Dram Type= 6, Freq= 0, CH_1, rank 1

 6900 13:58:29.006784  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6901 13:58:29.006867  ==

 6902 13:58:29.006933  DQS Delay:

 6903 13:58:29.009718  DQS0 = 59, DQS1 = 59

 6904 13:58:29.009801  DQM Delay:

 6905 13:58:29.009867  DQM0 = 19, DQM1 = 15

 6906 13:58:29.013568  DQ Delay:

 6907 13:58:29.016934  DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16

 6908 13:58:29.019919  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6909 13:58:29.023056  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6910 13:58:29.026413  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6911 13:58:29.026511  

 6912 13:58:29.026585  

 6913 13:58:29.026648  ==

 6914 13:58:29.030061  Dram Type= 6, Freq= 0, CH_1, rank 1

 6915 13:58:29.033279  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6916 13:58:29.033371  ==

 6917 13:58:29.033440  

 6918 13:58:29.033539  

 6919 13:58:29.036775  	TX Vref Scan disable

 6920 13:58:29.036858   == TX Byte 0 ==

 6921 13:58:29.043245  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6922 13:58:29.046765  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6923 13:58:29.046860   == TX Byte 1 ==

 6924 13:58:29.049573  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6925 13:58:29.056471  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6926 13:58:29.056554  ==

 6927 13:58:29.059378  Dram Type= 6, Freq= 0, CH_1, rank 1

 6928 13:58:29.062718  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6929 13:58:29.062806  ==

 6930 13:58:29.062872  

 6931 13:58:29.062931  

 6932 13:58:29.066135  	TX Vref Scan disable

 6933 13:58:29.066216   == TX Byte 0 ==

 6934 13:58:29.073138  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6935 13:58:29.076127  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6936 13:58:29.076212   == TX Byte 1 ==

 6937 13:58:29.080273  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6938 13:58:29.086709  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6939 13:58:29.086788  

 6940 13:58:29.086863  [DATLAT]

 6941 13:58:29.089637  Freq=400, CH1 RK1

 6942 13:58:29.089722  

 6943 13:58:29.089789  DATLAT Default: 0xe

 6944 13:58:29.092905  0, 0xFFFF, sum = 0

 6945 13:58:29.092987  1, 0xFFFF, sum = 0

 6946 13:58:29.096163  2, 0xFFFF, sum = 0

 6947 13:58:29.096248  3, 0xFFFF, sum = 0

 6948 13:58:29.099693  4, 0xFFFF, sum = 0

 6949 13:58:29.099782  5, 0xFFFF, sum = 0

 6950 13:58:29.102876  6, 0xFFFF, sum = 0

 6951 13:58:29.102964  7, 0xFFFF, sum = 0

 6952 13:58:29.106019  8, 0xFFFF, sum = 0

 6953 13:58:29.106101  9, 0xFFFF, sum = 0

 6954 13:58:29.109947  10, 0xFFFF, sum = 0

 6955 13:58:29.110030  11, 0xFFFF, sum = 0

 6956 13:58:29.113044  12, 0xFFFF, sum = 0

 6957 13:58:29.113125  13, 0x0, sum = 1

 6958 13:58:29.116314  14, 0x0, sum = 2

 6959 13:58:29.116401  15, 0x0, sum = 3

 6960 13:58:29.119705  16, 0x0, sum = 4

 6961 13:58:29.119787  best_step = 14

 6962 13:58:29.119865  

 6963 13:58:29.119930  ==

 6964 13:58:29.122927  Dram Type= 6, Freq= 0, CH_1, rank 1

 6965 13:58:29.129677  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6966 13:58:29.129766  ==

 6967 13:58:29.129838  RX Vref Scan: 0

 6968 13:58:29.129903  

 6969 13:58:29.132687  RX Vref 0 -> 0, step: 1

 6970 13:58:29.132777  

 6971 13:58:29.136302  RX Delay -359 -> 252, step: 8

 6972 13:58:29.142656  iDelay=217, Bit 0, Center -40 (-295 ~ 216) 512

 6973 13:58:29.145506  iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504

 6974 13:58:29.150307  iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504

 6975 13:58:29.152695  iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504

 6976 13:58:29.159299  iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512

 6977 13:58:29.162349  iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504

 6978 13:58:29.165396  iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504

 6979 13:58:29.168893  iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512

 6980 13:58:29.175872  iDelay=217, Bit 8, Center -68 (-327 ~ 192) 520

 6981 13:58:29.178887  iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512

 6982 13:58:29.181969  iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512

 6983 13:58:29.189042  iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520

 6984 13:58:29.192554  iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512

 6985 13:58:29.195209  iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512

 6986 13:58:29.198635  iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512

 6987 13:58:29.205828  iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512

 6988 13:58:29.205909  ==

 6989 13:58:29.208577  Dram Type= 6, Freq= 0, CH_1, rank 1

 6990 13:58:29.212181  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6991 13:58:29.212265  ==

 6992 13:58:29.212340  DQS Delay:

 6993 13:58:29.215028  DQS0 = 60, DQS1 = 68

 6994 13:58:29.215107  DQM Delay:

 6995 13:58:29.218523  DQM0 = 13, DQM1 = 14

 6996 13:58:29.218607  DQ Delay:

 6997 13:58:29.222162  DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8

 6998 13:58:29.225291  DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12

 6999 13:58:29.228815  DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8

 7000 13:58:29.232287  DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20

 7001 13:58:29.232370  

 7002 13:58:29.232436  

 7003 13:58:29.238747  [DQSOSCAuto] RK1, (LSB)MR18= 0x82b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps

 7004 13:58:29.242495  CH1 RK1: MR19=C0C, MR18=82B0

 7005 13:58:29.248697  CH1_RK1: MR19=0xC0C, MR18=0x82B0, DQSOSC=387, MR23=63, INC=394, DEC=262

 7006 13:58:29.251782  [RxdqsGatingPostProcess] freq 400

 7007 13:58:29.258719  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 7008 13:58:29.261625  best DQS0 dly(2T, 0.5T) = (0, 10)

 7009 13:58:29.261712  best DQS1 dly(2T, 0.5T) = (0, 10)

 7010 13:58:29.265221  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7011 13:58:29.268226  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7012 13:58:29.271403  best DQS0 dly(2T, 0.5T) = (0, 10)

 7013 13:58:29.275006  best DQS1 dly(2T, 0.5T) = (0, 10)

 7014 13:58:29.278419  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7015 13:58:29.281365  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7016 13:58:29.284808  Pre-setting of DQS Precalculation

 7017 13:58:29.291127  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 7018 13:58:29.298382  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 7019 13:58:29.304670  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 7020 13:58:29.304762  

 7021 13:58:29.304833  

 7022 13:58:29.308174  [Calibration Summary] 800 Mbps

 7023 13:58:29.308252  CH 0, Rank 0

 7024 13:58:29.311530  SW Impedance     : PASS

 7025 13:58:29.314388  DUTY Scan        : NO K

 7026 13:58:29.314475  ZQ Calibration   : PASS

 7027 13:58:29.317985  Jitter Meter     : NO K

 7028 13:58:29.321447  CBT Training     : PASS

 7029 13:58:29.321527  Write leveling   : PASS

 7030 13:58:29.324830  RX DQS gating    : PASS

 7031 13:58:29.327772  RX DQ/DQS(RDDQC) : PASS

 7032 13:58:29.327868  TX DQ/DQS        : PASS

 7033 13:58:29.331193  RX DATLAT        : PASS

 7034 13:58:29.334306  RX DQ/DQS(Engine): PASS

 7035 13:58:29.334385  TX OE            : NO K

 7036 13:58:29.334455  All Pass.

 7037 13:58:29.337799  

 7038 13:58:29.337876  CH 0, Rank 1

 7039 13:58:29.341378  SW Impedance     : PASS

 7040 13:58:29.341459  DUTY Scan        : NO K

 7041 13:58:29.344634  ZQ Calibration   : PASS

 7042 13:58:29.344717  Jitter Meter     : NO K

 7043 13:58:29.347808  CBT Training     : PASS

 7044 13:58:29.351424  Write leveling   : NO K

 7045 13:58:29.351508  RX DQS gating    : PASS

 7046 13:58:29.354244  RX DQ/DQS(RDDQC) : PASS

 7047 13:58:29.357806  TX DQ/DQS        : PASS

 7048 13:58:29.357917  RX DATLAT        : PASS

 7049 13:58:29.361200  RX DQ/DQS(Engine): PASS

 7050 13:58:29.364454  TX OE            : NO K

 7051 13:58:29.364537  All Pass.

 7052 13:58:29.364603  

 7053 13:58:29.364664  CH 1, Rank 0

 7054 13:58:29.368172  SW Impedance     : PASS

 7055 13:58:29.370822  DUTY Scan        : NO K

 7056 13:58:29.370904  ZQ Calibration   : PASS

 7057 13:58:29.374328  Jitter Meter     : NO K

 7058 13:58:29.377778  CBT Training     : PASS

 7059 13:58:29.377861  Write leveling   : PASS

 7060 13:58:29.381323  RX DQS gating    : PASS

 7061 13:58:29.384348  RX DQ/DQS(RDDQC) : PASS

 7062 13:58:29.384431  TX DQ/DQS        : PASS

 7063 13:58:29.387731  RX DATLAT        : PASS

 7064 13:58:29.387814  RX DQ/DQS(Engine): PASS

 7065 13:58:29.390704  TX OE            : NO K

 7066 13:58:29.390787  All Pass.

 7067 13:58:29.390853  

 7068 13:58:29.393961  CH 1, Rank 1

 7069 13:58:29.394044  SW Impedance     : PASS

 7070 13:58:29.397510  DUTY Scan        : NO K

 7071 13:58:29.401312  ZQ Calibration   : PASS

 7072 13:58:29.401394  Jitter Meter     : NO K

 7073 13:58:29.404188  CBT Training     : PASS

 7074 13:58:29.407806  Write leveling   : NO K

 7075 13:58:29.407889  RX DQS gating    : PASS

 7076 13:58:29.410705  RX DQ/DQS(RDDQC) : PASS

 7077 13:58:29.414081  TX DQ/DQS        : PASS

 7078 13:58:29.414164  RX DATLAT        : PASS

 7079 13:58:29.417705  RX DQ/DQS(Engine): PASS

 7080 13:58:29.420871  TX OE            : NO K

 7081 13:58:29.420969  All Pass.

 7082 13:58:29.421049  

 7083 13:58:29.421109  DramC Write-DBI off

 7084 13:58:29.424426  	PER_BANK_REFRESH: Hybrid Mode

 7085 13:58:29.427441  TX_TRACKING: ON

 7086 13:58:29.434063  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7087 13:58:29.437423  [FAST_K] Save calibration result to emmc

 7088 13:58:29.444318  dramc_set_vcore_voltage set vcore to 725000

 7089 13:58:29.444402  Read voltage for 1600, 0

 7090 13:58:29.447584  Vio18 = 0

 7091 13:58:29.447667  Vcore = 725000

 7092 13:58:29.447733  Vdram = 0

 7093 13:58:29.450531  Vddq = 0

 7094 13:58:29.450613  Vmddr = 0

 7095 13:58:29.454044  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7096 13:58:29.460611  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7097 13:58:29.463973  MEM_TYPE=3, freq_sel=13

 7098 13:58:29.467259  sv_algorithm_assistance_LP4_3733 

 7099 13:58:29.470553  ============ PULL DRAM RESETB DOWN ============

 7100 13:58:29.474000  ========== PULL DRAM RESETB DOWN end =========

 7101 13:58:29.477671  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7102 13:58:29.480872  =================================== 

 7103 13:58:29.484385  LPDDR4 DRAM CONFIGURATION

 7104 13:58:29.487270  =================================== 

 7105 13:58:29.490817  EX_ROW_EN[0]    = 0x0

 7106 13:58:29.490919  EX_ROW_EN[1]    = 0x0

 7107 13:58:29.494396  LP4Y_EN      = 0x0

 7108 13:58:29.494511  WORK_FSP     = 0x1

 7109 13:58:29.497531  WL           = 0x5

 7110 13:58:29.497639  RL           = 0x5

 7111 13:58:29.500626  BL           = 0x2

 7112 13:58:29.500703  RPST         = 0x0

 7113 13:58:29.504171  RD_PRE       = 0x0

 7114 13:58:29.504257  WR_PRE       = 0x1

 7115 13:58:29.507582  WR_PST       = 0x1

 7116 13:58:29.507688  DBI_WR       = 0x0

 7117 13:58:29.510520  DBI_RD       = 0x0

 7118 13:58:29.514012  OTF          = 0x1

 7119 13:58:29.517631  =================================== 

 7120 13:58:29.517714  =================================== 

 7121 13:58:29.520539  ANA top config

 7122 13:58:29.523800  =================================== 

 7123 13:58:29.527128  DLL_ASYNC_EN            =  0

 7124 13:58:29.527210  ALL_SLAVE_EN            =  0

 7125 13:58:29.530664  NEW_RANK_MODE           =  1

 7126 13:58:29.533636  DLL_IDLE_MODE           =  1

 7127 13:58:29.537264  LP45_APHY_COMB_EN       =  1

 7128 13:58:29.540298  TX_ODT_DIS              =  0

 7129 13:58:29.540381  NEW_8X_MODE             =  1

 7130 13:58:29.543499  =================================== 

 7131 13:58:29.547096  =================================== 

 7132 13:58:29.550354  data_rate                  = 3200

 7133 13:58:29.553548  CKR                        = 1

 7134 13:58:29.557130  DQ_P2S_RATIO               = 8

 7135 13:58:29.560434  =================================== 

 7136 13:58:29.563384  CA_P2S_RATIO               = 8

 7137 13:58:29.566735  DQ_CA_OPEN                 = 0

 7138 13:58:29.566817  DQ_SEMI_OPEN               = 0

 7139 13:58:29.570267  CA_SEMI_OPEN               = 0

 7140 13:58:29.573460  CA_FULL_RATE               = 0

 7141 13:58:29.577094  DQ_CKDIV4_EN               = 0

 7142 13:58:29.580327  CA_CKDIV4_EN               = 0

 7143 13:58:29.583190  CA_PREDIV_EN               = 0

 7144 13:58:29.583276  PH8_DLY                    = 12

 7145 13:58:29.586858  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7146 13:58:29.590234  DQ_AAMCK_DIV               = 4

 7147 13:58:29.593503  CA_AAMCK_DIV               = 4

 7148 13:58:29.596525  CA_ADMCK_DIV               = 4

 7149 13:58:29.600175  DQ_TRACK_CA_EN             = 0

 7150 13:58:29.603259  CA_PICK                    = 1600

 7151 13:58:29.603341  CA_MCKIO                   = 1600

 7152 13:58:29.606520  MCKIO_SEMI                 = 0

 7153 13:58:29.610094  PLL_FREQ                   = 3068

 7154 13:58:29.613285  DQ_UI_PI_RATIO             = 32

 7155 13:58:29.616688  CA_UI_PI_RATIO             = 0

 7156 13:58:29.619663  =================================== 

 7157 13:58:29.623296  =================================== 

 7158 13:58:29.626767  memory_type:LPDDR4         

 7159 13:58:29.626846  GP_NUM     : 10       

 7160 13:58:29.629747  SRAM_EN    : 1       

 7161 13:58:29.629826  MD32_EN    : 0       

 7162 13:58:29.632948  =================================== 

 7163 13:58:29.636465  [ANA_INIT] >>>>>>>>>>>>>> 

 7164 13:58:29.639499  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7165 13:58:29.642825  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7166 13:58:29.646323  =================================== 

 7167 13:58:29.649327  data_rate = 3200,PCW = 0X7600

 7168 13:58:29.652812  =================================== 

 7169 13:58:29.656091  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7170 13:58:29.663181  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7171 13:58:29.666190  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7172 13:58:29.673003  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7173 13:58:29.676536  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7174 13:58:29.679417  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7175 13:58:29.679514  [ANA_INIT] flow start 

 7176 13:58:29.683017  [ANA_INIT] PLL >>>>>>>> 

 7177 13:58:29.686572  [ANA_INIT] PLL <<<<<<<< 

 7178 13:58:29.686655  [ANA_INIT] MIDPI >>>>>>>> 

 7179 13:58:29.689410  [ANA_INIT] MIDPI <<<<<<<< 

 7180 13:58:29.692790  [ANA_INIT] DLL >>>>>>>> 

 7181 13:58:29.692872  [ANA_INIT] DLL <<<<<<<< 

 7182 13:58:29.696076  [ANA_INIT] flow end 

 7183 13:58:29.699686  ============ LP4 DIFF to SE enter ============

 7184 13:58:29.705915  ============ LP4 DIFF to SE exit  ============

 7185 13:58:29.706016  [ANA_INIT] <<<<<<<<<<<<< 

 7186 13:58:29.709216  [Flow] Enable top DCM control >>>>> 

 7187 13:58:29.712948  [Flow] Enable top DCM control <<<<< 

 7188 13:58:29.715810  Enable DLL master slave shuffle 

 7189 13:58:29.722721  ============================================================== 

 7190 13:58:29.722813  Gating Mode config

 7191 13:58:29.729195  ============================================================== 

 7192 13:58:29.732577  Config description: 

 7193 13:58:29.738999  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7194 13:58:29.745705  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7195 13:58:29.752435  SELPH_MODE            0: By rank         1: By Phase 

 7196 13:58:29.759023  ============================================================== 

 7197 13:58:29.759112  GAT_TRACK_EN                 =  1

 7198 13:58:29.762405  RX_GATING_MODE               =  2

 7199 13:58:29.765875  RX_GATING_TRACK_MODE         =  2

 7200 13:58:29.769061  SELPH_MODE                   =  1

 7201 13:58:29.772233  PICG_EARLY_EN                =  1

 7202 13:58:29.775651  VALID_LAT_VALUE              =  1

 7203 13:58:29.782019  ============================================================== 

 7204 13:58:29.785456  Enter into Gating configuration >>>> 

 7205 13:58:29.788549  Exit from Gating configuration <<<< 

 7206 13:58:29.792351  Enter into  DVFS_PRE_config >>>>> 

 7207 13:58:29.802166  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7208 13:58:29.805499  Exit from  DVFS_PRE_config <<<<< 

 7209 13:58:29.808550  Enter into PICG configuration >>>> 

 7210 13:58:29.811740  Exit from PICG configuration <<<< 

 7211 13:58:29.815399  [RX_INPUT] configuration >>>>> 

 7212 13:58:29.818830  [RX_INPUT] configuration <<<<< 

 7213 13:58:29.821741  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7214 13:58:29.828625  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7215 13:58:29.834917  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7216 13:58:29.838435  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7217 13:58:29.845318  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7218 13:58:29.851903  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7219 13:58:29.855183  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7220 13:58:29.858618  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7221 13:58:29.865268  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7222 13:58:29.868583  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7223 13:58:29.871446  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7224 13:58:29.878330  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7225 13:58:29.881487  =================================== 

 7226 13:58:29.881570  LPDDR4 DRAM CONFIGURATION

 7227 13:58:29.885050  =================================== 

 7228 13:58:29.888426  EX_ROW_EN[0]    = 0x0

 7229 13:58:29.891350  EX_ROW_EN[1]    = 0x0

 7230 13:58:29.891451  LP4Y_EN      = 0x0

 7231 13:58:29.894981  WORK_FSP     = 0x1

 7232 13:58:29.895089  WL           = 0x5

 7233 13:58:29.898092  RL           = 0x5

 7234 13:58:29.898189  BL           = 0x2

 7235 13:58:29.901431  RPST         = 0x0

 7236 13:58:29.901510  RD_PRE       = 0x0

 7237 13:58:29.904623  WR_PRE       = 0x1

 7238 13:58:29.904700  WR_PST       = 0x1

 7239 13:58:29.908435  DBI_WR       = 0x0

 7240 13:58:29.908514  DBI_RD       = 0x0

 7241 13:58:29.911282  OTF          = 0x1

 7242 13:58:29.914682  =================================== 

 7243 13:58:29.917809  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7244 13:58:29.921160  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7245 13:58:29.928213  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7246 13:58:29.931584  =================================== 

 7247 13:58:29.931659  LPDDR4 DRAM CONFIGURATION

 7248 13:58:29.935028  =================================== 

 7249 13:58:29.938113  EX_ROW_EN[0]    = 0x10

 7250 13:58:29.938196  EX_ROW_EN[1]    = 0x0

 7251 13:58:29.941395  LP4Y_EN      = 0x0

 7252 13:58:29.944781  WORK_FSP     = 0x1

 7253 13:58:29.944858  WL           = 0x5

 7254 13:58:29.948150  RL           = 0x5

 7255 13:58:29.948224  BL           = 0x2

 7256 13:58:29.951283  RPST         = 0x0

 7257 13:58:29.951418  RD_PRE       = 0x0

 7258 13:58:29.954835  WR_PRE       = 0x1

 7259 13:58:29.954919  WR_PST       = 0x1

 7260 13:58:29.958251  DBI_WR       = 0x0

 7261 13:58:29.958336  DBI_RD       = 0x0

 7262 13:58:29.961587  OTF          = 0x1

 7263 13:58:29.964705  =================================== 

 7264 13:58:29.971282  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7265 13:58:29.971398  ==

 7266 13:58:29.974734  Dram Type= 6, Freq= 0, CH_0, rank 0

 7267 13:58:29.977865  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7268 13:58:29.977950  ==

 7269 13:58:29.981283  [Duty_Offset_Calibration]

 7270 13:58:29.981367  	B0:2	B1:0	CA:3

 7271 13:58:29.981451  

 7272 13:58:29.984444  [DutyScan_Calibration_Flow] k_type=0

 7273 13:58:29.994848  

 7274 13:58:29.994933  ==CLK 0==

 7275 13:58:29.998324  Final CLK duty delay cell = 0

 7276 13:58:30.001270  [0] MAX Duty = 5031%(X100), DQS PI = 12

 7277 13:58:30.004887  [0] MIN Duty = 4907%(X100), DQS PI = 6

 7278 13:58:30.004972  [0] AVG Duty = 4969%(X100)

 7279 13:58:30.008141  

 7280 13:58:30.011702  CH0 CLK Duty spec in!! Max-Min= 124%

 7281 13:58:30.014602  [DutyScan_Calibration_Flow] ====Done====

 7282 13:58:30.014686  

 7283 13:58:30.017685  [DutyScan_Calibration_Flow] k_type=1

 7284 13:58:30.034466  

 7285 13:58:30.034553  ==DQS 0 ==

 7286 13:58:30.037860  Final DQS duty delay cell = 0

 7287 13:58:30.040919  [0] MAX Duty = 5125%(X100), DQS PI = 30

 7288 13:58:30.044524  [0] MIN Duty = 4907%(X100), DQS PI = 0

 7289 13:58:30.047859  [0] AVG Duty = 5016%(X100)

 7290 13:58:30.047943  

 7291 13:58:30.048029  ==DQS 1 ==

 7292 13:58:30.051096  Final DQS duty delay cell = 0

 7293 13:58:30.054497  [0] MAX Duty = 5156%(X100), DQS PI = 32

 7294 13:58:30.057340  [0] MIN Duty = 5062%(X100), DQS PI = 8

 7295 13:58:30.060695  [0] AVG Duty = 5109%(X100)

 7296 13:58:30.060778  

 7297 13:58:30.064047  CH0 DQS 0 Duty spec in!! Max-Min= 218%

 7298 13:58:30.064130  

 7299 13:58:30.067368  CH0 DQS 1 Duty spec in!! Max-Min= 94%

 7300 13:58:30.070517  [DutyScan_Calibration_Flow] ====Done====

 7301 13:58:30.070595  

 7302 13:58:30.074040  [DutyScan_Calibration_Flow] k_type=3

 7303 13:58:30.091105  

 7304 13:58:30.091191  ==DQM 0 ==

 7305 13:58:30.094515  Final DQM duty delay cell = 0

 7306 13:58:30.098001  [0] MAX Duty = 5156%(X100), DQS PI = 14

 7307 13:58:30.101181  [0] MIN Duty = 4875%(X100), DQS PI = 0

 7308 13:58:30.101265  [0] AVG Duty = 5015%(X100)

 7309 13:58:30.104659  

 7310 13:58:30.104763  ==DQM 1 ==

 7311 13:58:30.108216  Final DQM duty delay cell = 0

 7312 13:58:30.111024  [0] MAX Duty = 4938%(X100), DQS PI = 52

 7313 13:58:30.114327  [0] MIN Duty = 4813%(X100), DQS PI = 12

 7314 13:58:30.117460  [0] AVG Duty = 4875%(X100)

 7315 13:58:30.117541  

 7316 13:58:30.121020  CH0 DQM 0 Duty spec in!! Max-Min= 281%

 7317 13:58:30.121100  

 7318 13:58:30.124691  CH0 DQM 1 Duty spec in!! Max-Min= 125%

 7319 13:58:30.127651  [DutyScan_Calibration_Flow] ====Done====

 7320 13:58:30.127732  

 7321 13:58:30.130748  [DutyScan_Calibration_Flow] k_type=2

 7322 13:58:30.147269  

 7323 13:58:30.147350  ==DQ 0 ==

 7324 13:58:30.150768  Final DQ duty delay cell = -4

 7325 13:58:30.154160  [-4] MAX Duty = 5000%(X100), DQS PI = 18

 7326 13:58:30.157414  [-4] MIN Duty = 4876%(X100), DQS PI = 0

 7327 13:58:30.160936  [-4] AVG Duty = 4938%(X100)

 7328 13:58:30.161016  

 7329 13:58:30.161080  ==DQ 1 ==

 7330 13:58:30.164153  Final DQ duty delay cell = 0

 7331 13:58:30.167051  [0] MAX Duty = 5156%(X100), DQS PI = 60

 7332 13:58:30.170404  [0] MIN Duty = 5000%(X100), DQS PI = 16

 7333 13:58:30.173802  [0] AVG Duty = 5078%(X100)

 7334 13:58:30.173883  

 7335 13:58:30.177165  CH0 DQ 0 Duty spec in!! Max-Min= 124%

 7336 13:58:30.177245  

 7337 13:58:30.180335  CH0 DQ 1 Duty spec in!! Max-Min= 156%

 7338 13:58:30.183664  [DutyScan_Calibration_Flow] ====Done====

 7339 13:58:30.183777  ==

 7340 13:58:30.187172  Dram Type= 6, Freq= 0, CH_1, rank 0

 7341 13:58:30.190663  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7342 13:58:30.190745  ==

 7343 13:58:30.193454  [Duty_Offset_Calibration]

 7344 13:58:30.193534  	B0:1	B1:-2	CA:0

 7345 13:58:30.193598  

 7346 13:58:30.196780  [DutyScan_Calibration_Flow] k_type=0

 7347 13:58:30.208430  

 7348 13:58:30.208510  ==CLK 0==

 7349 13:58:30.211365  Final CLK duty delay cell = 0

 7350 13:58:30.214625  [0] MAX Duty = 5093%(X100), DQS PI = 30

 7351 13:58:30.218039  [0] MIN Duty = 4844%(X100), DQS PI = 60

 7352 13:58:30.218121  [0] AVG Duty = 4968%(X100)

 7353 13:58:30.221074  

 7354 13:58:30.224579  CH1 CLK Duty spec in!! Max-Min= 249%

 7355 13:58:30.228323  [DutyScan_Calibration_Flow] ====Done====

 7356 13:58:30.228407  

 7357 13:58:30.231299  [DutyScan_Calibration_Flow] k_type=1

 7358 13:58:30.246760  

 7359 13:58:30.246844  ==DQS 0 ==

 7360 13:58:30.249972  Final DQS duty delay cell = -4

 7361 13:58:30.253294  [-4] MAX Duty = 4969%(X100), DQS PI = 24

 7362 13:58:30.256446  [-4] MIN Duty = 4844%(X100), DQS PI = 46

 7363 13:58:30.259808  [-4] AVG Duty = 4906%(X100)

 7364 13:58:30.259889  

 7365 13:58:30.259952  ==DQS 1 ==

 7366 13:58:30.263072  Final DQS duty delay cell = 0

 7367 13:58:30.266580  [0] MAX Duty = 5093%(X100), DQS PI = 62

 7368 13:58:30.269814  [0] MIN Duty = 4844%(X100), DQS PI = 24

 7369 13:58:30.273389  [0] AVG Duty = 4968%(X100)

 7370 13:58:30.273471  

 7371 13:58:30.276808  CH1 DQS 0 Duty spec in!! Max-Min= 125%

 7372 13:58:30.276889  

 7373 13:58:30.280069  CH1 DQS 1 Duty spec in!! Max-Min= 249%

 7374 13:58:30.283051  [DutyScan_Calibration_Flow] ====Done====

 7375 13:58:30.283133  

 7376 13:58:30.286513  [DutyScan_Calibration_Flow] k_type=3

 7377 13:58:30.303835  

 7378 13:58:30.303918  ==DQM 0 ==

 7379 13:58:30.307166  Final DQM duty delay cell = 0

 7380 13:58:30.310457  [0] MAX Duty = 5031%(X100), DQS PI = 24

 7381 13:58:30.313671  [0] MIN Duty = 4813%(X100), DQS PI = 54

 7382 13:58:30.317227  [0] AVG Duty = 4922%(X100)

 7383 13:58:30.317309  

 7384 13:58:30.317373  ==DQM 1 ==

 7385 13:58:30.320532  Final DQM duty delay cell = 0

 7386 13:58:30.323584  [0] MAX Duty = 5062%(X100), DQS PI = 34

 7387 13:58:30.327199  [0] MIN Duty = 4875%(X100), DQS PI = 24

 7388 13:58:30.330636  [0] AVG Duty = 4968%(X100)

 7389 13:58:30.330717  

 7390 13:58:30.333650  CH1 DQM 0 Duty spec in!! Max-Min= 218%

 7391 13:58:30.333732  

 7392 13:58:30.336913  CH1 DQM 1 Duty spec in!! Max-Min= 187%

 7393 13:58:30.340425  [DutyScan_Calibration_Flow] ====Done====

 7394 13:58:30.340506  

 7395 13:58:30.344255  [DutyScan_Calibration_Flow] k_type=2

 7396 13:58:30.361035  

 7397 13:58:30.361116  ==DQ 0 ==

 7398 13:58:30.364231  Final DQ duty delay cell = 0

 7399 13:58:30.367523  [0] MAX Duty = 5093%(X100), DQS PI = 22

 7400 13:58:30.370612  [0] MIN Duty = 4938%(X100), DQS PI = 0

 7401 13:58:30.370694  [0] AVG Duty = 5015%(X100)

 7402 13:58:30.370758  

 7403 13:58:30.373922  ==DQ 1 ==

 7404 13:58:30.377559  Final DQ duty delay cell = 0

 7405 13:58:30.380624  [0] MAX Duty = 5156%(X100), DQS PI = 36

 7406 13:58:30.384209  [0] MIN Duty = 4938%(X100), DQS PI = 24

 7407 13:58:30.384292  [0] AVG Duty = 5047%(X100)

 7408 13:58:30.384356  

 7409 13:58:30.387567  CH1 DQ 0 Duty spec in!! Max-Min= 155%

 7410 13:58:30.390467  

 7411 13:58:30.393763  CH1 DQ 1 Duty spec in!! Max-Min= 218%

 7412 13:58:30.397145  [DutyScan_Calibration_Flow] ====Done====

 7413 13:58:30.400363  nWR fixed to 30

 7414 13:58:30.400435  [ModeRegInit_LP4] CH0 RK0

 7415 13:58:30.404081  [ModeRegInit_LP4] CH0 RK1

 7416 13:58:30.406957  [ModeRegInit_LP4] CH1 RK0

 7417 13:58:30.407038  [ModeRegInit_LP4] CH1 RK1

 7418 13:58:30.410411  match AC timing 5

 7419 13:58:30.413883  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7420 13:58:30.420106  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7421 13:58:30.423507  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7422 13:58:30.430298  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7423 13:58:30.433797  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7424 13:58:30.433879  [MiockJmeterHQA]

 7425 13:58:30.433943  

 7426 13:58:30.436738  [DramcMiockJmeter] u1RxGatingPI = 0

 7427 13:58:30.440246  0 : 4263, 4032

 7428 13:58:30.440330  4 : 4255, 4029

 7429 13:58:30.440396  8 : 4366, 4139

 7430 13:58:30.443881  12 : 4366, 4140

 7431 13:58:30.443964  16 : 4257, 4030

 7432 13:58:30.446749  20 : 4258, 4029

 7433 13:58:30.446831  24 : 4252, 4030

 7434 13:58:30.450407  28 : 4255, 4029

 7435 13:58:30.450489  32 : 4258, 4031

 7436 13:58:30.453779  36 : 4252, 4029

 7437 13:58:30.453862  40 : 4366, 4140

 7438 13:58:30.453927  44 : 4365, 4139

 7439 13:58:30.456883  48 : 4255, 4029

 7440 13:58:30.456965  52 : 4253, 4029

 7441 13:58:30.459971  56 : 4363, 4140

 7442 13:58:30.460054  60 : 4363, 4140

 7443 13:58:30.463518  64 : 4250, 4027

 7444 13:58:30.463607  68 : 4252, 4029

 7445 13:58:30.467122  72 : 4363, 4140

 7446 13:58:30.467207  76 : 4255, 4029

 7447 13:58:30.467311  80 : 4253, 4029

 7448 13:58:30.470428  84 : 4250, 4027

 7449 13:58:30.470514  88 : 4363, 4140

 7450 13:58:30.473569  92 : 4255, 4029

 7451 13:58:30.473643  96 : 4365, 4140

 7452 13:58:30.476895  100 : 4253, 4029

 7453 13:58:30.476965  104 : 4253, 3839

 7454 13:58:30.480476  108 : 4255, 13

 7455 13:58:30.480558  112 : 4252, 0

 7456 13:58:30.480623  116 : 4255, 0

 7457 13:58:30.483265  120 : 4255, 0

 7458 13:58:30.483347  124 : 4363, 0

 7459 13:58:30.483427  128 : 4363, 0

 7460 13:58:30.486678  132 : 4253, 0

 7461 13:58:30.486760  136 : 4252, 0

 7462 13:58:30.489920  140 : 4254, 0

 7463 13:58:30.490003  144 : 4252, 0

 7464 13:58:30.490068  148 : 4254, 0

 7465 13:58:30.493582  152 : 4250, 0

 7466 13:58:30.493664  156 : 4252, 0

 7467 13:58:30.496784  160 : 4253, 0

 7468 13:58:30.496866  164 : 4252, 0

 7469 13:58:30.496931  168 : 4252, 0

 7470 13:58:30.500333  172 : 4252, 0

 7471 13:58:30.500415  176 : 4253, 0

 7472 13:58:30.503140  180 : 4252, 0

 7473 13:58:30.503222  184 : 4254, 0

 7474 13:58:30.503287  188 : 4253, 0

 7475 13:58:30.506686  192 : 4363, 0

 7476 13:58:30.506768  196 : 4252, 0

 7477 13:58:30.509924  200 : 4253, 0

 7478 13:58:30.510048  204 : 4253, 0

 7479 13:58:30.510149  208 : 4363, 0

 7480 13:58:30.513581  212 : 4363, 0

 7481 13:58:30.513663  216 : 4252, 0

 7482 13:58:30.513729  220 : 4253, 0

 7483 13:58:30.516408  224 : 4252, 0

 7484 13:58:30.516490  228 : 4253, 0

 7485 13:58:30.520168  232 : 4255, 1

 7486 13:58:30.520251  236 : 4255, 992

 7487 13:58:30.523181  240 : 4363, 4140

 7488 13:58:30.523263  244 : 4364, 4140

 7489 13:58:30.523329  248 : 4253, 4029

 7490 13:58:30.526775  252 : 4363, 4140

 7491 13:58:30.526857  256 : 4250, 4026

 7492 13:58:30.530189  260 : 4253, 4029

 7493 13:58:30.530271  264 : 4252, 4030

 7494 13:58:30.533205  268 : 4258, 4032

 7495 13:58:30.533288  272 : 4255, 4029

 7496 13:58:30.536537  276 : 4366, 4140

 7497 13:58:30.536620  280 : 4363, 4140

 7498 13:58:30.539823  284 : 4250, 4026

 7499 13:58:30.539911  288 : 4368, 4142

 7500 13:58:30.543270  292 : 4255, 4029

 7501 13:58:30.543345  296 : 4364, 4140

 7502 13:58:30.546826  300 : 4363, 4139

 7503 13:58:30.546912  304 : 4255, 4029

 7504 13:58:30.546997  308 : 4252, 4029

 7505 13:58:30.549649  312 : 4363, 4140

 7506 13:58:30.549734  316 : 4363, 4140

 7507 13:58:30.552941  320 : 4255, 4029

 7508 13:58:30.553027  324 : 4253, 4027

 7509 13:58:30.556243  328 : 4366, 4140

 7510 13:58:30.556328  332 : 4363, 4140

 7511 13:58:30.559968  336 : 4255, 4029

 7512 13:58:30.560054  340 : 4258, 4032

 7513 13:58:30.562930  344 : 4252, 4029

 7514 13:58:30.563015  348 : 4254, 4030

 7515 13:58:30.566460  352 : 4252, 4027

 7516 13:58:30.566547  356 : 4257, 3203

 7517 13:58:30.566633  360 : 4252, 22

 7518 13:58:30.569771  

 7519 13:58:30.569854  	MIOCK jitter meter	ch=0

 7520 13:58:30.569940  

 7521 13:58:30.572821  1T = (360-108) = 252 dly cells

 7522 13:58:30.579758  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps

 7523 13:58:30.579843  ==

 7524 13:58:30.582765  Dram Type= 6, Freq= 0, CH_0, rank 0

 7525 13:58:30.586177  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7526 13:58:30.586261  ==

 7527 13:58:30.593166  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7528 13:58:30.596518  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7529 13:58:30.599309  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7530 13:58:30.606202  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7531 13:58:30.615767  [CA 0] Center 43 (13~74) winsize 62

 7532 13:58:30.618846  [CA 1] Center 43 (13~74) winsize 62

 7533 13:58:30.622429  [CA 2] Center 39 (10~68) winsize 59

 7534 13:58:30.625412  [CA 3] Center 39 (10~68) winsize 59

 7535 13:58:30.629033  [CA 4] Center 36 (7~66) winsize 60

 7536 13:58:30.632437  [CA 5] Center 36 (7~66) winsize 60

 7537 13:58:30.632522  

 7538 13:58:30.635737  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7539 13:58:30.635820  

 7540 13:58:30.638866  [CATrainingPosCal] consider 1 rank data

 7541 13:58:30.642209  u2DelayCellTimex100 = 258/100 ps

 7542 13:58:30.648814  CA0 delay=43 (13~74),Diff = 7 PI (26 cell)

 7543 13:58:30.652418  CA1 delay=43 (13~74),Diff = 7 PI (26 cell)

 7544 13:58:30.656175  CA2 delay=39 (10~68),Diff = 3 PI (11 cell)

 7545 13:58:30.658960  CA3 delay=39 (10~68),Diff = 3 PI (11 cell)

 7546 13:58:30.662144  CA4 delay=36 (7~66),Diff = 0 PI (0 cell)

 7547 13:58:30.665328  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 7548 13:58:30.665413  

 7549 13:58:30.668865  CA PerBit enable=1, Macro0, CA PI delay=36

 7550 13:58:30.668949  

 7551 13:58:30.672488  [CBTSetCACLKResult] CA Dly = 36

 7552 13:58:30.675279  CS Dly: 11 (0~42)

 7553 13:58:30.678845  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7554 13:58:30.682080  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7555 13:58:30.682164  ==

 7556 13:58:30.685153  Dram Type= 6, Freq= 0, CH_0, rank 1

 7557 13:58:30.691814  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7558 13:58:30.691899  ==

 7559 13:58:30.695941  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7560 13:58:30.701858  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7561 13:58:30.705532  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7562 13:58:30.711956  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7563 13:58:30.719570  [CA 0] Center 44 (14~75) winsize 62

 7564 13:58:30.722878  [CA 1] Center 43 (13~74) winsize 62

 7565 13:58:30.726555  [CA 2] Center 39 (10~69) winsize 60

 7566 13:58:30.729763  [CA 3] Center 39 (10~69) winsize 60

 7567 13:58:30.733211  [CA 4] Center 37 (8~67) winsize 60

 7568 13:58:30.736060  [CA 5] Center 37 (7~67) winsize 61

 7569 13:58:30.736141  

 7570 13:58:30.739974  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7571 13:58:30.740055  

 7572 13:58:30.742793  [CATrainingPosCal] consider 2 rank data

 7573 13:58:30.746269  u2DelayCellTimex100 = 258/100 ps

 7574 13:58:30.749600  CA0 delay=44 (14~74),Diff = 8 PI (30 cell)

 7575 13:58:30.756242  CA1 delay=43 (13~74),Diff = 7 PI (26 cell)

 7576 13:58:30.759513  CA2 delay=39 (10~68),Diff = 3 PI (11 cell)

 7577 13:58:30.762789  CA3 delay=39 (10~68),Diff = 3 PI (11 cell)

 7578 13:58:30.765794  CA4 delay=37 (8~66),Diff = 1 PI (3 cell)

 7579 13:58:30.769409  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 7580 13:58:30.769489  

 7581 13:58:30.772385  CA PerBit enable=1, Macro0, CA PI delay=36

 7582 13:58:30.772468  

 7583 13:58:30.775820  [CBTSetCACLKResult] CA Dly = 36

 7584 13:58:30.779347  CS Dly: 11 (0~42)

 7585 13:58:30.782366  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7586 13:58:30.786048  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7587 13:58:30.786130  

 7588 13:58:30.789357  ----->DramcWriteLeveling(PI) begin...

 7589 13:58:30.789439  ==

 7590 13:58:30.792595  Dram Type= 6, Freq= 0, CH_0, rank 0

 7591 13:58:30.799037  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7592 13:58:30.799118  ==

 7593 13:58:30.802384  Write leveling (Byte 0): 36 => 36

 7594 13:58:30.805933  Write leveling (Byte 1): 28 => 28

 7595 13:58:30.806015  DramcWriteLeveling(PI) end<-----

 7596 13:58:30.809623  

 7597 13:58:30.809723  ==

 7598 13:58:30.812351  Dram Type= 6, Freq= 0, CH_0, rank 0

 7599 13:58:30.815916  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7600 13:58:30.815998  ==

 7601 13:58:30.819126  [Gating] SW mode calibration

 7602 13:58:30.825585  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7603 13:58:30.828807  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7604 13:58:30.835513   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7605 13:58:30.838689   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7606 13:58:30.842351   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7607 13:58:30.848727   1  4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7608 13:58:30.852191   1  4 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)

 7609 13:58:30.855252   1  4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)

 7610 13:58:30.861939   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7611 13:58:30.865329   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7612 13:58:30.868705   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7613 13:58:30.875086   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7614 13:58:30.878386   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7615 13:58:30.882063   1  5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 7616 13:58:30.888335   1  5 16 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)

 7617 13:58:30.891763   1  5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)

 7618 13:58:30.894988   1  5 24 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)

 7619 13:58:30.901796   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7620 13:58:30.905034   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7621 13:58:30.908893   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7622 13:58:30.915396   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7623 13:58:30.918149   1  6 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)

 7624 13:58:30.921743   1  6 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)

 7625 13:58:30.928075   1  6 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)

 7626 13:58:30.931782   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7627 13:58:30.935037   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7628 13:58:30.941461   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7629 13:58:30.944985   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7630 13:58:30.948365   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7631 13:58:30.954685   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7632 13:58:30.958362   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7633 13:58:30.961701   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7634 13:58:30.968203   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7635 13:58:30.971269   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7636 13:58:30.975030   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7637 13:58:30.978607   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7638 13:58:30.985220   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7639 13:58:30.988076   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7640 13:58:30.991665   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7641 13:58:30.997817   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7642 13:58:31.001271   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7643 13:58:31.004529   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7644 13:58:31.011114   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7645 13:58:31.014394   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7646 13:58:31.017636   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7647 13:58:31.024981   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7648 13:58:31.027807   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7649 13:58:31.031329   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 7650 13:58:31.034585  Total UI for P1: 0, mck2ui 16

 7651 13:58:31.038010  best dqsien dly found for B0: ( 1,  9, 14)

 7652 13:58:31.044197   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7653 13:58:31.047463   1  9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7654 13:58:31.051189  Total UI for P1: 0, mck2ui 16

 7655 13:58:31.054504  best dqsien dly found for B1: ( 1,  9, 24)

 7656 13:58:31.057671  best DQS0 dly(MCK, UI, PI) = (1, 9, 14)

 7657 13:58:31.060713  best DQS1 dly(MCK, UI, PI) = (1, 9, 24)

 7658 13:58:31.060797  

 7659 13:58:31.064386  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)

 7660 13:58:31.070740  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)

 7661 13:58:31.070822  [Gating] SW calibration Done

 7662 13:58:31.070888  ==

 7663 13:58:31.074325  Dram Type= 6, Freq= 0, CH_0, rank 0

 7664 13:58:31.080727  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7665 13:58:31.080810  ==

 7666 13:58:31.080875  RX Vref Scan: 0

 7667 13:58:31.080935  

 7668 13:58:31.084209  RX Vref 0 -> 0, step: 1

 7669 13:58:31.084291  

 7670 13:58:31.087546  RX Delay 0 -> 252, step: 8

 7671 13:58:31.090815  iDelay=192, Bit 0, Center 127 (72 ~ 183) 112

 7672 13:58:31.094533  iDelay=192, Bit 1, Center 131 (80 ~ 183) 104

 7673 13:58:31.097833  iDelay=192, Bit 2, Center 127 (72 ~ 183) 112

 7674 13:58:31.100808  iDelay=192, Bit 3, Center 123 (72 ~ 175) 104

 7675 13:58:31.107759  iDelay=192, Bit 4, Center 127 (72 ~ 183) 112

 7676 13:58:31.110930  iDelay=192, Bit 5, Center 115 (64 ~ 167) 104

 7677 13:58:31.114470  iDelay=192, Bit 6, Center 139 (88 ~ 191) 104

 7678 13:58:31.117132  iDelay=192, Bit 7, Center 139 (88 ~ 191) 104

 7679 13:58:31.120969  iDelay=192, Bit 8, Center 115 (56 ~ 175) 120

 7680 13:58:31.127216  iDelay=192, Bit 9, Center 111 (56 ~ 167) 112

 7681 13:58:31.130887  iDelay=192, Bit 10, Center 123 (64 ~ 183) 120

 7682 13:58:31.134362  iDelay=192, Bit 11, Center 115 (56 ~ 175) 120

 7683 13:58:31.137226  iDelay=192, Bit 12, Center 127 (72 ~ 183) 112

 7684 13:58:31.140400  iDelay=192, Bit 13, Center 131 (72 ~ 191) 120

 7685 13:58:31.147555  iDelay=192, Bit 14, Center 135 (80 ~ 191) 112

 7686 13:58:31.150337  iDelay=192, Bit 15, Center 131 (72 ~ 191) 120

 7687 13:58:31.150437  ==

 7688 13:58:31.153665  Dram Type= 6, Freq= 0, CH_0, rank 0

 7689 13:58:31.156872  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7690 13:58:31.156955  ==

 7691 13:58:31.160526  DQS Delay:

 7692 13:58:31.160600  DQS0 = 0, DQS1 = 0

 7693 13:58:31.163869  DQM Delay:

 7694 13:58:31.163941  DQM0 = 128, DQM1 = 123

 7695 13:58:31.164008  DQ Delay:

 7696 13:58:31.167484  DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123

 7697 13:58:31.173634  DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139

 7698 13:58:31.176838  DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115

 7699 13:58:31.180395  DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131

 7700 13:58:31.180494  

 7701 13:58:31.180583  

 7702 13:58:31.180678  ==

 7703 13:58:31.183366  Dram Type= 6, Freq= 0, CH_0, rank 0

 7704 13:58:31.186746  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7705 13:58:31.186820  ==

 7706 13:58:31.186891  

 7707 13:58:31.186950  

 7708 13:58:31.190059  	TX Vref Scan disable

 7709 13:58:31.193820   == TX Byte 0 ==

 7710 13:58:31.197082  Update DQ  dly =993 (3 ,6, 33)  DQ  OEN =(3 ,3)

 7711 13:58:31.200275  Update DQM dly =993 (3 ,6, 33)  DQM OEN =(3 ,3)

 7712 13:58:31.203730   == TX Byte 1 ==

 7713 13:58:31.207044  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 7714 13:58:31.210521  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7715 13:58:31.210598  ==

 7716 13:58:31.213509  Dram Type= 6, Freq= 0, CH_0, rank 0

 7717 13:58:31.216955  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7718 13:58:31.219952  ==

 7719 13:58:31.232349  

 7720 13:58:31.235082  TX Vref early break, caculate TX vref

 7721 13:58:31.238601  TX Vref=16, minBit 8, minWin=21, winSum=366

 7722 13:58:31.242168  TX Vref=18, minBit 8, minWin=21, winSum=369

 7723 13:58:31.245600  TX Vref=20, minBit 4, minWin=23, winSum=382

 7724 13:58:31.248504  TX Vref=22, minBit 8, minWin=23, winSum=391

 7725 13:58:31.251875  TX Vref=24, minBit 9, minWin=23, winSum=400

 7726 13:58:31.258824  TX Vref=26, minBit 9, minWin=24, winSum=406

 7727 13:58:31.261615  TX Vref=28, minBit 8, minWin=24, winSum=407

 7728 13:58:31.265468  TX Vref=30, minBit 8, minWin=24, winSum=403

 7729 13:58:31.268689  TX Vref=32, minBit 8, minWin=23, winSum=392

 7730 13:58:31.271706  TX Vref=34, minBit 9, minWin=21, winSum=384

 7731 13:58:31.278450  [TxChooseVref] Worse bit 8, Min win 24, Win sum 407, Final Vref 28

 7732 13:58:31.278534  

 7733 13:58:31.281514  Final TX Range 0 Vref 28

 7734 13:58:31.281597  

 7735 13:58:31.281662  ==

 7736 13:58:31.285034  Dram Type= 6, Freq= 0, CH_0, rank 0

 7737 13:58:31.288456  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7738 13:58:31.288539  ==

 7739 13:58:31.288604  

 7740 13:58:31.288664  

 7741 13:58:31.291888  	TX Vref Scan disable

 7742 13:58:31.298306  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps

 7743 13:58:31.298390   == TX Byte 0 ==

 7744 13:58:31.301569  u2DelayCellOfst[0]=15 cells (4 PI)

 7745 13:58:31.304746  u2DelayCellOfst[1]=18 cells (5 PI)

 7746 13:58:31.308810  u2DelayCellOfst[2]=15 cells (4 PI)

 7747 13:58:31.311426  u2DelayCellOfst[3]=15 cells (4 PI)

 7748 13:58:31.314962  u2DelayCellOfst[4]=11 cells (3 PI)

 7749 13:58:31.318471  u2DelayCellOfst[5]=0 cells (0 PI)

 7750 13:58:31.321636  u2DelayCellOfst[6]=22 cells (6 PI)

 7751 13:58:31.325066  u2DelayCellOfst[7]=18 cells (5 PI)

 7752 13:58:31.328028  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 7753 13:58:31.331479  Update DQM dly =993 (3 ,6, 33)  DQM OEN =(3 ,3)

 7754 13:58:31.334902   == TX Byte 1 ==

 7755 13:58:31.338180  u2DelayCellOfst[8]=0 cells (0 PI)

 7756 13:58:31.338262  u2DelayCellOfst[9]=3 cells (1 PI)

 7757 13:58:31.341594  u2DelayCellOfst[10]=7 cells (2 PI)

 7758 13:58:31.345147  u2DelayCellOfst[11]=3 cells (1 PI)

 7759 13:58:31.348034  u2DelayCellOfst[12]=11 cells (3 PI)

 7760 13:58:31.351688  u2DelayCellOfst[13]=11 cells (3 PI)

 7761 13:58:31.354750  u2DelayCellOfst[14]=15 cells (4 PI)

 7762 13:58:31.357903  u2DelayCellOfst[15]=11 cells (3 PI)

 7763 13:58:31.361269  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 7764 13:58:31.367815  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7765 13:58:31.367930  DramC Write-DBI on

 7766 13:58:31.368027  ==

 7767 13:58:31.371250  Dram Type= 6, Freq= 0, CH_0, rank 0

 7768 13:58:31.377981  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7769 13:58:31.378091  ==

 7770 13:58:31.378188  

 7771 13:58:31.378283  

 7772 13:58:31.378377  	TX Vref Scan disable

 7773 13:58:31.381735   == TX Byte 0 ==

 7774 13:58:31.384892  Update DQM dly =736 (2 ,6, 32)  DQM OEN =(3 ,3)

 7775 13:58:31.388630   == TX Byte 1 ==

 7776 13:58:31.391676  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 7777 13:58:31.394876  DramC Write-DBI off

 7778 13:58:31.394992  

 7779 13:58:31.395088  [DATLAT]

 7780 13:58:31.395178  Freq=1600, CH0 RK0

 7781 13:58:31.395278  

 7782 13:58:31.398313  DATLAT Default: 0xf

 7783 13:58:31.398417  0, 0xFFFF, sum = 0

 7784 13:58:31.401786  1, 0xFFFF, sum = 0

 7785 13:58:31.404610  2, 0xFFFF, sum = 0

 7786 13:58:31.404720  3, 0xFFFF, sum = 0

 7787 13:58:31.408052  4, 0xFFFF, sum = 0

 7788 13:58:31.408161  5, 0xFFFF, sum = 0

 7789 13:58:31.411560  6, 0xFFFF, sum = 0

 7790 13:58:31.411682  7, 0xFFFF, sum = 0

 7791 13:58:31.414924  8, 0xFFFF, sum = 0

 7792 13:58:31.415031  9, 0xFFFF, sum = 0

 7793 13:58:31.418234  10, 0xFFFF, sum = 0

 7794 13:58:31.418345  11, 0xFFFF, sum = 0

 7795 13:58:31.421657  12, 0xFFFF, sum = 0

 7796 13:58:31.421767  13, 0xCFFF, sum = 0

 7797 13:58:31.424481  14, 0x0, sum = 1

 7798 13:58:31.424590  15, 0x0, sum = 2

 7799 13:58:31.427900  16, 0x0, sum = 3

 7800 13:58:31.428009  17, 0x0, sum = 4

 7801 13:58:31.431489  best_step = 15

 7802 13:58:31.431593  

 7803 13:58:31.431688  ==

 7804 13:58:31.434829  Dram Type= 6, Freq= 0, CH_0, rank 0

 7805 13:58:31.437940  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7806 13:58:31.438047  ==

 7807 13:58:31.441234  RX Vref Scan: 1

 7808 13:58:31.441338  

 7809 13:58:31.441433  Set Vref Range= 24 -> 127

 7810 13:58:31.441526  

 7811 13:58:31.444552  RX Vref 24 -> 127, step: 1

 7812 13:58:31.444658  

 7813 13:58:31.447779  RX Delay 11 -> 252, step: 4

 7814 13:58:31.447885  

 7815 13:58:31.451039  Set Vref, RX VrefLevel [Byte0]: 24

 7816 13:58:31.454926                           [Byte1]: 24

 7817 13:58:31.455038  

 7818 13:58:31.457828  Set Vref, RX VrefLevel [Byte0]: 25

 7819 13:58:31.461483                           [Byte1]: 25

 7820 13:58:31.461589  

 7821 13:58:31.464929  Set Vref, RX VrefLevel [Byte0]: 26

 7822 13:58:31.467891                           [Byte1]: 26

 7823 13:58:31.472222  

 7824 13:58:31.472336  Set Vref, RX VrefLevel [Byte0]: 27

 7825 13:58:31.475586                           [Byte1]: 27

 7826 13:58:31.479634  

 7827 13:58:31.479742  Set Vref, RX VrefLevel [Byte0]: 28

 7828 13:58:31.483117                           [Byte1]: 28

 7829 13:58:31.487145  

 7830 13:58:31.487266  Set Vref, RX VrefLevel [Byte0]: 29

 7831 13:58:31.490419                           [Byte1]: 29

 7832 13:58:31.494940  

 7833 13:58:31.495047  Set Vref, RX VrefLevel [Byte0]: 30

 7834 13:58:31.498334                           [Byte1]: 30

 7835 13:58:31.502501  

 7836 13:58:31.502605  Set Vref, RX VrefLevel [Byte0]: 31

 7837 13:58:31.505863                           [Byte1]: 31

 7838 13:58:31.510409  

 7839 13:58:31.510515  Set Vref, RX VrefLevel [Byte0]: 32

 7840 13:58:31.513650                           [Byte1]: 32

 7841 13:58:31.517487  

 7842 13:58:31.517601  Set Vref, RX VrefLevel [Byte0]: 33

 7843 13:58:31.524179                           [Byte1]: 33

 7844 13:58:31.524286  

 7845 13:58:31.527632  Set Vref, RX VrefLevel [Byte0]: 34

 7846 13:58:31.530873                           [Byte1]: 34

 7847 13:58:31.530982  

 7848 13:58:31.533789  Set Vref, RX VrefLevel [Byte0]: 35

 7849 13:58:31.537200                           [Byte1]: 35

 7850 13:58:31.540964  

 7851 13:58:31.541068  Set Vref, RX VrefLevel [Byte0]: 36

 7852 13:58:31.543694                           [Byte1]: 36

 7853 13:58:31.548734  

 7854 13:58:31.548845  Set Vref, RX VrefLevel [Byte0]: 37

 7855 13:58:31.551819                           [Byte1]: 37

 7856 13:58:31.555957  

 7857 13:58:31.556071  Set Vref, RX VrefLevel [Byte0]: 38

 7858 13:58:31.559047                           [Byte1]: 38

 7859 13:58:31.563145  

 7860 13:58:31.563252  Set Vref, RX VrefLevel [Byte0]: 39

 7861 13:58:31.566672                           [Byte1]: 39

 7862 13:58:31.570951  

 7863 13:58:31.571058  Set Vref, RX VrefLevel [Byte0]: 40

 7864 13:58:31.574469                           [Byte1]: 40

 7865 13:58:31.578591  

 7866 13:58:31.578704  Set Vref, RX VrefLevel [Byte0]: 41

 7867 13:58:31.581980                           [Byte1]: 41

 7868 13:58:31.586243  

 7869 13:58:31.586354  Set Vref, RX VrefLevel [Byte0]: 42

 7870 13:58:31.589495                           [Byte1]: 42

 7871 13:58:31.594086  

 7872 13:58:31.594195  Set Vref, RX VrefLevel [Byte0]: 43

 7873 13:58:31.597493                           [Byte1]: 43

 7874 13:58:31.601432  

 7875 13:58:31.601540  Set Vref, RX VrefLevel [Byte0]: 44

 7876 13:58:31.604730                           [Byte1]: 44

 7877 13:58:31.608938  

 7878 13:58:31.609045  Set Vref, RX VrefLevel [Byte0]: 45

 7879 13:58:31.612247                           [Byte1]: 45

 7880 13:58:31.616974  

 7881 13:58:31.617081  Set Vref, RX VrefLevel [Byte0]: 46

 7882 13:58:31.620232                           [Byte1]: 46

 7883 13:58:31.624114  

 7884 13:58:31.624220  Set Vref, RX VrefLevel [Byte0]: 47

 7885 13:58:31.627361                           [Byte1]: 47

 7886 13:58:31.632024  

 7887 13:58:31.632130  Set Vref, RX VrefLevel [Byte0]: 48

 7888 13:58:31.635021                           [Byte1]: 48

 7889 13:58:31.639568  

 7890 13:58:31.639674  Set Vref, RX VrefLevel [Byte0]: 49

 7891 13:58:31.642582                           [Byte1]: 49

 7892 13:58:31.647303  

 7893 13:58:31.647450  Set Vref, RX VrefLevel [Byte0]: 50

 7894 13:58:31.650328                           [Byte1]: 50

 7895 13:58:31.654706  

 7896 13:58:31.654813  Set Vref, RX VrefLevel [Byte0]: 51

 7897 13:58:31.658146                           [Byte1]: 51

 7898 13:58:31.662393  

 7899 13:58:31.662497  Set Vref, RX VrefLevel [Byte0]: 52

 7900 13:58:31.665522                           [Byte1]: 52

 7901 13:58:31.670029  

 7902 13:58:31.670133  Set Vref, RX VrefLevel [Byte0]: 53

 7903 13:58:31.673672                           [Byte1]: 53

 7904 13:58:31.677853  

 7905 13:58:31.677958  Set Vref, RX VrefLevel [Byte0]: 54

 7906 13:58:31.680731                           [Byte1]: 54

 7907 13:58:31.685376  

 7908 13:58:31.685483  Set Vref, RX VrefLevel [Byte0]: 55

 7909 13:58:31.688546                           [Byte1]: 55

 7910 13:58:31.692618  

 7911 13:58:31.692724  Set Vref, RX VrefLevel [Byte0]: 56

 7912 13:58:31.696165                           [Byte1]: 56

 7913 13:58:31.700610  

 7914 13:58:31.700714  Set Vref, RX VrefLevel [Byte0]: 57

 7915 13:58:31.703721                           [Byte1]: 57

 7916 13:58:31.707922  

 7917 13:58:31.708030  Set Vref, RX VrefLevel [Byte0]: 58

 7918 13:58:31.711314                           [Byte1]: 58

 7919 13:58:31.715641  

 7920 13:58:31.715719  Set Vref, RX VrefLevel [Byte0]: 59

 7921 13:58:31.718822                           [Byte1]: 59

 7922 13:58:31.723349  

 7923 13:58:31.723487  Set Vref, RX VrefLevel [Byte0]: 60

 7924 13:58:31.726350                           [Byte1]: 60

 7925 13:58:31.730584  

 7926 13:58:31.730691  Set Vref, RX VrefLevel [Byte0]: 61

 7927 13:58:31.734615                           [Byte1]: 61

 7928 13:58:31.738714  

 7929 13:58:31.738825  Set Vref, RX VrefLevel [Byte0]: 62

 7930 13:58:31.741514                           [Byte1]: 62

 7931 13:58:31.746262  

 7932 13:58:31.746369  Set Vref, RX VrefLevel [Byte0]: 63

 7933 13:58:31.749711                           [Byte1]: 63

 7934 13:58:31.753750  

 7935 13:58:31.753856  Set Vref, RX VrefLevel [Byte0]: 64

 7936 13:58:31.756956                           [Byte1]: 64

 7937 13:58:31.761010  

 7938 13:58:31.761114  Set Vref, RX VrefLevel [Byte0]: 65

 7939 13:58:31.764442                           [Byte1]: 65

 7940 13:58:31.769174  

 7941 13:58:31.769281  Set Vref, RX VrefLevel [Byte0]: 66

 7942 13:58:31.772053                           [Byte1]: 66

 7943 13:58:31.776557  

 7944 13:58:31.776666  Set Vref, RX VrefLevel [Byte0]: 67

 7945 13:58:31.779829                           [Byte1]: 67

 7946 13:58:31.783949  

 7947 13:58:31.784054  Set Vref, RX VrefLevel [Byte0]: 68

 7948 13:58:31.787582                           [Byte1]: 68

 7949 13:58:31.791622  

 7950 13:58:31.791731  Set Vref, RX VrefLevel [Byte0]: 69

 7951 13:58:31.794988                           [Byte1]: 69

 7952 13:58:31.799424  

 7953 13:58:31.799545  Set Vref, RX VrefLevel [Byte0]: 70

 7954 13:58:31.802684                           [Byte1]: 70

 7955 13:58:31.807430  

 7956 13:58:31.807539  Set Vref, RX VrefLevel [Byte0]: 71

 7957 13:58:31.810381                           [Byte1]: 71

 7958 13:58:31.814546  

 7959 13:58:31.814664  Set Vref, RX VrefLevel [Byte0]: 72

 7960 13:58:31.818116                           [Byte1]: 72

 7961 13:58:31.822361  

 7962 13:58:31.822480  Set Vref, RX VrefLevel [Byte0]: 73

 7963 13:58:31.825721                           [Byte1]: 73

 7964 13:58:31.829851  

 7965 13:58:31.829957  Set Vref, RX VrefLevel [Byte0]: 74

 7966 13:58:31.833058                           [Byte1]: 74

 7967 13:58:31.837485  

 7968 13:58:31.837593  Set Vref, RX VrefLevel [Byte0]: 75

 7969 13:58:31.840527                           [Byte1]: 75

 7970 13:58:31.844937  

 7971 13:58:31.845044  Set Vref, RX VrefLevel [Byte0]: 76

 7972 13:58:31.848264                           [Byte1]: 76

 7973 13:58:31.852835  

 7974 13:58:31.852942  Final RX Vref Byte 0 = 63 to rank0

 7975 13:58:31.855768  Final RX Vref Byte 1 = 57 to rank0

 7976 13:58:31.859217  Final RX Vref Byte 0 = 63 to rank1

 7977 13:58:31.862349  Final RX Vref Byte 1 = 57 to rank1==

 7978 13:58:31.865809  Dram Type= 6, Freq= 0, CH_0, rank 0

 7979 13:58:31.873076  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7980 13:58:31.873187  ==

 7981 13:58:31.873292  DQS Delay:

 7982 13:58:31.873390  DQS0 = 0, DQS1 = 0

 7983 13:58:31.875652  DQM Delay:

 7984 13:58:31.875760  DQM0 = 126, DQM1 = 119

 7985 13:58:31.879020  DQ Delay:

 7986 13:58:31.882511  DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122

 7987 13:58:31.885928  DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138

 7988 13:58:31.888960  DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114

 7989 13:58:31.892542  DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128

 7990 13:58:31.892646  

 7991 13:58:31.892744  

 7992 13:58:31.892835  

 7993 13:58:31.895494  [DramC_TX_OE_Calibration] TA2

 7994 13:58:31.898880  Original DQ_B0 (3 6) =30, OEN = 27

 7995 13:58:31.902203  Original DQ_B1 (3 6) =30, OEN = 27

 7996 13:58:31.905692  24, 0x0, End_B0=24 End_B1=24

 7997 13:58:31.905799  25, 0x0, End_B0=25 End_B1=25

 7998 13:58:31.909416  26, 0x0, End_B0=26 End_B1=26

 7999 13:58:31.912551  27, 0x0, End_B0=27 End_B1=27

 8000 13:58:31.915998  28, 0x0, End_B0=28 End_B1=28

 8001 13:58:31.918974  29, 0x0, End_B0=29 End_B1=29

 8002 13:58:31.919082  30, 0x0, End_B0=30 End_B1=30

 8003 13:58:31.922527  31, 0x4141, End_B0=30 End_B1=30

 8004 13:58:31.925649  Byte0 end_step=30  best_step=27

 8005 13:58:31.928690  Byte1 end_step=30  best_step=27

 8006 13:58:31.932010  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8007 13:58:31.935570  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8008 13:58:31.935649  

 8009 13:58:31.935737  

 8010 13:58:31.942410  [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps

 8011 13:58:31.946024  CH0 RK0: MR19=303, MR18=1313

 8012 13:58:31.952348  CH0_RK0: MR19=0x303, MR18=0x1313, DQSOSC=400, MR23=63, INC=23, DEC=15

 8013 13:58:31.952457  

 8014 13:58:31.955202  ----->DramcWriteLeveling(PI) begin...

 8015 13:58:31.955312  ==

 8016 13:58:31.958878  Dram Type= 6, Freq= 0, CH_0, rank 1

 8017 13:58:31.962063  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8018 13:58:31.962168  ==

 8019 13:58:31.965599  Write leveling (Byte 0): 31 => 31

 8020 13:58:31.968981  Write leveling (Byte 1): 28 => 28

 8021 13:58:31.972044  DramcWriteLeveling(PI) end<-----

 8022 13:58:31.972148  

 8023 13:58:31.972279  ==

 8024 13:58:31.975517  Dram Type= 6, Freq= 0, CH_0, rank 1

 8025 13:58:31.978439  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8026 13:58:31.978544  ==

 8027 13:58:31.981991  [Gating] SW mode calibration

 8028 13:58:31.988444  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8029 13:58:31.995334  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8030 13:58:31.998717   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8031 13:58:32.005066   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8032 13:58:32.008567   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8033 13:58:32.011661   1  4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)

 8034 13:58:32.018485   1  4 16 | B1->B0 | 2a29 3434 | 1 1 | (0 0) (1 1)

 8035 13:58:32.021809   1  4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)

 8036 13:58:32.025173   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8037 13:58:32.028305   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8038 13:58:32.035073   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8039 13:58:32.037996   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8040 13:58:32.041496   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 8041 13:58:32.048292   1  5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)

 8042 13:58:32.051769   1  5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)

 8043 13:58:32.055089   1  5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)

 8044 13:58:32.061390   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8045 13:58:32.065118   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8046 13:58:32.068256   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8047 13:58:32.074579   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8048 13:58:32.078016   1  6  8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)

 8049 13:58:32.081773   1  6 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)

 8050 13:58:32.087946   1  6 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)

 8051 13:58:32.091456   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8052 13:58:32.094930   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8053 13:58:32.101549   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8054 13:58:32.105165   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8055 13:58:32.107898   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8056 13:58:32.114904   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8057 13:58:32.117821   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8058 13:58:32.121222   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8059 13:58:32.127964   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8060 13:58:32.131335   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8061 13:58:32.134678   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8062 13:58:32.141427   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8063 13:58:32.144308   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8064 13:58:32.148023   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8065 13:58:32.154729   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8066 13:58:32.157821   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8067 13:58:32.160841   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8068 13:58:32.167616   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8069 13:58:32.171043   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8070 13:58:32.174077   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8071 13:58:32.180723   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8072 13:58:32.184174   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8073 13:58:32.187244   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8074 13:58:32.194023   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8075 13:58:32.194131  Total UI for P1: 0, mck2ui 16

 8076 13:58:32.197532  best dqsien dly found for B0: ( 1,  9, 10)

 8077 13:58:32.203973   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8078 13:58:32.207098   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8079 13:58:32.210509  Total UI for P1: 0, mck2ui 16

 8080 13:58:32.213991  best dqsien dly found for B1: ( 1,  9, 18)

 8081 13:58:32.217402  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8082 13:58:32.220721  best DQS1 dly(MCK, UI, PI) = (1, 9, 18)

 8083 13:58:32.220823  

 8084 13:58:32.223820  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8085 13:58:32.231014  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)

 8086 13:58:32.231116  [Gating] SW calibration Done

 8087 13:58:32.231218  ==

 8088 13:58:32.233875  Dram Type= 6, Freq= 0, CH_0, rank 1

 8089 13:58:32.240211  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8090 13:58:32.240314  ==

 8091 13:58:32.240413  RX Vref Scan: 0

 8092 13:58:32.240503  

 8093 13:58:32.243862  RX Vref 0 -> 0, step: 1

 8094 13:58:32.243960  

 8095 13:58:32.246805  RX Delay 0 -> 252, step: 8

 8096 13:58:32.250303  iDelay=200, Bit 0, Center 127 (72 ~ 183) 112

 8097 13:58:32.254034  iDelay=200, Bit 1, Center 131 (72 ~ 191) 120

 8098 13:58:32.256839  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8099 13:58:32.263732  iDelay=200, Bit 3, Center 123 (64 ~ 183) 120

 8100 13:58:32.267011  iDelay=200, Bit 4, Center 127 (72 ~ 183) 112

 8101 13:58:32.270190  iDelay=200, Bit 5, Center 115 (56 ~ 175) 120

 8102 13:58:32.273314  iDelay=200, Bit 6, Center 139 (80 ~ 199) 120

 8103 13:58:32.276624  iDelay=200, Bit 7, Center 139 (80 ~ 199) 120

 8104 13:58:32.283368  iDelay=200, Bit 8, Center 111 (48 ~ 175) 128

 8105 13:58:32.286757  iDelay=200, Bit 9, Center 107 (48 ~ 167) 120

 8106 13:58:32.290078  iDelay=200, Bit 10, Center 123 (64 ~ 183) 120

 8107 13:58:32.293284  iDelay=200, Bit 11, Center 115 (56 ~ 175) 120

 8108 13:58:32.296862  iDelay=200, Bit 12, Center 127 (64 ~ 191) 128

 8109 13:58:32.303573  iDelay=200, Bit 13, Center 131 (72 ~ 191) 120

 8110 13:58:32.307035  iDelay=200, Bit 14, Center 131 (72 ~ 191) 120

 8111 13:58:32.310378  iDelay=200, Bit 15, Center 127 (64 ~ 191) 128

 8112 13:58:32.310478  ==

 8113 13:58:32.313644  Dram Type= 6, Freq= 0, CH_0, rank 1

 8114 13:58:32.316601  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8115 13:58:32.316681  ==

 8116 13:58:32.319849  DQS Delay:

 8117 13:58:32.319925  DQS0 = 0, DQS1 = 0

 8118 13:58:32.323348  DQM Delay:

 8119 13:58:32.323494  DQM0 = 128, DQM1 = 121

 8120 13:58:32.326794  DQ Delay:

 8121 13:58:32.329705  DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123

 8122 13:58:32.333175  DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139

 8123 13:58:32.336835  DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115

 8124 13:58:32.339820  DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127

 8125 13:58:32.339896  

 8126 13:58:32.339960  

 8127 13:58:32.340024  ==

 8128 13:58:32.343353  Dram Type= 6, Freq= 0, CH_0, rank 1

 8129 13:58:32.346358  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8130 13:58:32.346462  ==

 8131 13:58:32.346555  

 8132 13:58:32.346646  

 8133 13:58:32.349758  	TX Vref Scan disable

 8134 13:58:32.352906   == TX Byte 0 ==

 8135 13:58:32.356881  Update DQ  dly =987 (3 ,6, 27)  DQ  OEN =(3 ,3)

 8136 13:58:32.359993  Update DQM dly =987 (3 ,6, 27)  DQM OEN =(3 ,3)

 8137 13:58:32.363479   == TX Byte 1 ==

 8138 13:58:32.366324  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8139 13:58:32.369922  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8140 13:58:32.370025  ==

 8141 13:58:32.372924  Dram Type= 6, Freq= 0, CH_0, rank 1

 8142 13:58:32.379596  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8143 13:58:32.379701  ==

 8144 13:58:32.391096  

 8145 13:58:32.394827  TX Vref early break, caculate TX vref

 8146 13:58:32.397998  TX Vref=16, minBit 1, minWin=22, winSum=364

 8147 13:58:32.402017  TX Vref=18, minBit 1, minWin=22, winSum=376

 8148 13:58:32.404677  TX Vref=20, minBit 8, minWin=22, winSum=380

 8149 13:58:32.407885  TX Vref=22, minBit 1, minWin=23, winSum=390

 8150 13:58:32.411332  TX Vref=24, minBit 8, minWin=24, winSum=400

 8151 13:58:32.418089  TX Vref=26, minBit 8, minWin=24, winSum=409

 8152 13:58:32.420916  TX Vref=28, minBit 8, minWin=24, winSum=412

 8153 13:58:32.424378  TX Vref=30, minBit 8, minWin=24, winSum=409

 8154 13:58:32.427757  TX Vref=32, minBit 8, minWin=22, winSum=397

 8155 13:58:32.430995  TX Vref=34, minBit 8, minWin=22, winSum=386

 8156 13:58:32.437904  [TxChooseVref] Worse bit 8, Min win 24, Win sum 412, Final Vref 28

 8157 13:58:32.438011  

 8158 13:58:32.440947  Final TX Range 0 Vref 28

 8159 13:58:32.441050  

 8160 13:58:32.441145  ==

 8161 13:58:32.444383  Dram Type= 6, Freq= 0, CH_0, rank 1

 8162 13:58:32.447820  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8163 13:58:32.447923  ==

 8164 13:58:32.448021  

 8165 13:58:32.448112  

 8166 13:58:32.451271  	TX Vref Scan disable

 8167 13:58:32.457704  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps

 8168 13:58:32.457810   == TX Byte 0 ==

 8169 13:58:32.460763  u2DelayCellOfst[0]=15 cells (4 PI)

 8170 13:58:32.464499  u2DelayCellOfst[1]=18 cells (5 PI)

 8171 13:58:32.467877  u2DelayCellOfst[2]=11 cells (3 PI)

 8172 13:58:32.470851  u2DelayCellOfst[3]=11 cells (3 PI)

 8173 13:58:32.474486  u2DelayCellOfst[4]=7 cells (2 PI)

 8174 13:58:32.478039  u2DelayCellOfst[5]=0 cells (0 PI)

 8175 13:58:32.481121  u2DelayCellOfst[6]=18 cells (5 PI)

 8176 13:58:32.484428  u2DelayCellOfst[7]=18 cells (5 PI)

 8177 13:58:32.487907  Update DQ  dly =985 (3 ,6, 25)  DQ  OEN =(3 ,3)

 8178 13:58:32.490827  Update DQM dly =987 (3 ,6, 27)  DQM OEN =(3 ,3)

 8179 13:58:32.493953   == TX Byte 1 ==

 8180 13:58:32.494058  u2DelayCellOfst[8]=3 cells (1 PI)

 8181 13:58:32.497846  u2DelayCellOfst[9]=0 cells (0 PI)

 8182 13:58:32.500697  u2DelayCellOfst[10]=7 cells (2 PI)

 8183 13:58:32.503820  u2DelayCellOfst[11]=7 cells (2 PI)

 8184 13:58:32.507609  u2DelayCellOfst[12]=15 cells (4 PI)

 8185 13:58:32.510549  u2DelayCellOfst[13]=11 cells (3 PI)

 8186 13:58:32.514168  u2DelayCellOfst[14]=15 cells (4 PI)

 8187 13:58:32.517471  u2DelayCellOfst[15]=15 cells (4 PI)

 8188 13:58:32.520388  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8189 13:58:32.527474  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8190 13:58:32.527555  DramC Write-DBI on

 8191 13:58:32.527626  ==

 8192 13:58:32.530251  Dram Type= 6, Freq= 0, CH_0, rank 1

 8193 13:58:32.534071  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8194 13:58:32.536890  ==

 8195 13:58:32.536999  

 8196 13:58:32.537091  

 8197 13:58:32.537183  	TX Vref Scan disable

 8198 13:58:32.540727   == TX Byte 0 ==

 8199 13:58:32.544053  Update DQM dly =731 (2 ,6, 27)  DQM OEN =(3 ,3)

 8200 13:58:32.547049   == TX Byte 1 ==

 8201 13:58:32.550707  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8202 13:58:32.554148  DramC Write-DBI off

 8203 13:58:32.554252  

 8204 13:58:32.554343  [DATLAT]

 8205 13:58:32.554432  Freq=1600, CH0 RK1

 8206 13:58:32.554501  

 8207 13:58:32.557217  DATLAT Default: 0xf

 8208 13:58:32.560654  0, 0xFFFF, sum = 0

 8209 13:58:32.560758  1, 0xFFFF, sum = 0

 8210 13:58:32.564221  2, 0xFFFF, sum = 0

 8211 13:58:32.564328  3, 0xFFFF, sum = 0

 8212 13:58:32.567474  4, 0xFFFF, sum = 0

 8213 13:58:32.567550  5, 0xFFFF, sum = 0

 8214 13:58:32.570456  6, 0xFFFF, sum = 0

 8215 13:58:32.570531  7, 0xFFFF, sum = 0

 8216 13:58:32.573744  8, 0xFFFF, sum = 0

 8217 13:58:32.573850  9, 0xFFFF, sum = 0

 8218 13:58:32.577365  10, 0xFFFF, sum = 0

 8219 13:58:32.577472  11, 0xFFFF, sum = 0

 8220 13:58:32.580180  12, 0xFFFF, sum = 0

 8221 13:58:32.580282  13, 0xCFFF, sum = 0

 8222 13:58:32.583698  14, 0x0, sum = 1

 8223 13:58:32.583802  15, 0x0, sum = 2

 8224 13:58:32.587428  16, 0x0, sum = 3

 8225 13:58:32.587533  17, 0x0, sum = 4

 8226 13:58:32.590649  best_step = 15

 8227 13:58:32.590753  

 8228 13:58:32.590848  ==

 8229 13:58:32.593470  Dram Type= 6, Freq= 0, CH_0, rank 1

 8230 13:58:32.597033  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8231 13:58:32.597136  ==

 8232 13:58:32.600351  RX Vref Scan: 0

 8233 13:58:32.600451  

 8234 13:58:32.600548  RX Vref 0 -> 0, step: 1

 8235 13:58:32.600639  

 8236 13:58:32.603409  RX Delay 3 -> 252, step: 4

 8237 13:58:32.606958  iDelay=191, Bit 0, Center 124 (71 ~ 178) 108

 8238 13:58:32.613387  iDelay=191, Bit 1, Center 126 (71 ~ 182) 112

 8239 13:58:32.616585  iDelay=191, Bit 2, Center 120 (67 ~ 174) 108

 8240 13:58:32.620457  iDelay=191, Bit 3, Center 120 (63 ~ 178) 116

 8241 13:58:32.623388  iDelay=191, Bit 4, Center 124 (71 ~ 178) 108

 8242 13:58:32.626724  iDelay=191, Bit 5, Center 112 (59 ~ 166) 108

 8243 13:58:32.633481  iDelay=191, Bit 6, Center 134 (79 ~ 190) 112

 8244 13:58:32.636724  iDelay=191, Bit 7, Center 134 (79 ~ 190) 112

 8245 13:58:32.640009  iDelay=191, Bit 8, Center 112 (55 ~ 170) 116

 8246 13:58:32.643476  iDelay=191, Bit 9, Center 106 (51 ~ 162) 112

 8247 13:58:32.646722  iDelay=191, Bit 10, Center 120 (63 ~ 178) 116

 8248 13:58:32.653371  iDelay=191, Bit 11, Center 112 (55 ~ 170) 116

 8249 13:58:32.656663  iDelay=191, Bit 12, Center 124 (67 ~ 182) 116

 8250 13:58:32.659588  iDelay=191, Bit 13, Center 124 (67 ~ 182) 116

 8251 13:58:32.663389  iDelay=191, Bit 14, Center 128 (71 ~ 186) 116

 8252 13:58:32.669806  iDelay=191, Bit 15, Center 124 (67 ~ 182) 116

 8253 13:58:32.669911  ==

 8254 13:58:32.673122  Dram Type= 6, Freq= 0, CH_0, rank 1

 8255 13:58:32.676331  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8256 13:58:32.676431  ==

 8257 13:58:32.676528  DQS Delay:

 8258 13:58:32.679875  DQS0 = 0, DQS1 = 0

 8259 13:58:32.679973  DQM Delay:

 8260 13:58:32.683233  DQM0 = 124, DQM1 = 118

 8261 13:58:32.683331  DQ Delay:

 8262 13:58:32.686302  DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =120

 8263 13:58:32.689645  DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134

 8264 13:58:32.692982  DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =112

 8265 13:58:32.696440  DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124

 8266 13:58:32.696541  

 8267 13:58:32.696632  

 8268 13:58:32.699548  

 8269 13:58:32.699651  [DramC_TX_OE_Calibration] TA2

 8270 13:58:32.702867  Original DQ_B0 (3 6) =30, OEN = 27

 8271 13:58:32.706441  Original DQ_B1 (3 6) =30, OEN = 27

 8272 13:58:32.709654  24, 0x0, End_B0=24 End_B1=24

 8273 13:58:32.713359  25, 0x0, End_B0=25 End_B1=25

 8274 13:58:32.716378  26, 0x0, End_B0=26 End_B1=26

 8275 13:58:32.716453  27, 0x0, End_B0=27 End_B1=27

 8276 13:58:32.719694  28, 0x0, End_B0=28 End_B1=28

 8277 13:58:32.723026  29, 0x0, End_B0=29 End_B1=29

 8278 13:58:32.726650  30, 0x0, End_B0=30 End_B1=30

 8279 13:58:32.729534  31, 0x4545, End_B0=30 End_B1=30

 8280 13:58:32.729641  Byte0 end_step=30  best_step=27

 8281 13:58:32.732987  Byte1 end_step=30  best_step=27

 8282 13:58:32.735889  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8283 13:58:32.739551  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8284 13:58:32.739628  

 8285 13:58:32.739698  

 8286 13:58:32.745895  [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps

 8287 13:58:32.749494  CH0 RK1: MR19=303, MR18=220F

 8288 13:58:32.755873  CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16

 8289 13:58:32.759752  [RxdqsGatingPostProcess] freq 1600

 8290 13:58:32.766117  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8291 13:58:32.769140  best DQS0 dly(2T, 0.5T) = (1, 1)

 8292 13:58:32.769249  best DQS1 dly(2T, 0.5T) = (1, 1)

 8293 13:58:32.772452  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8294 13:58:32.775860  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8295 13:58:32.779525  best DQS0 dly(2T, 0.5T) = (1, 1)

 8296 13:58:32.782700  best DQS1 dly(2T, 0.5T) = (1, 1)

 8297 13:58:32.786065  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8298 13:58:32.789106  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8299 13:58:32.792522  Pre-setting of DQS Precalculation

 8300 13:58:32.796016  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8301 13:58:32.798894  ==

 8302 13:58:32.802377  Dram Type= 6, Freq= 0, CH_1, rank 0

 8303 13:58:32.806004  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8304 13:58:32.806106  ==

 8305 13:58:32.809084  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8306 13:58:32.815920  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8307 13:58:32.818991  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8308 13:58:32.825686  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8309 13:58:32.834015  [CA 0] Center 41 (13~70) winsize 58

 8310 13:58:32.836891  [CA 1] Center 42 (12~72) winsize 61

 8311 13:58:32.840506  [CA 2] Center 37 (8~66) winsize 59

 8312 13:58:32.843514  [CA 3] Center 37 (8~66) winsize 59

 8313 13:58:32.847030  [CA 4] Center 37 (8~67) winsize 60

 8314 13:58:32.850586  [CA 5] Center 36 (7~66) winsize 60

 8315 13:58:32.850692  

 8316 13:58:32.854062  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8317 13:58:32.854161  

 8318 13:58:32.857420  [CATrainingPosCal] consider 1 rank data

 8319 13:58:32.860237  u2DelayCellTimex100 = 258/100 ps

 8320 13:58:32.863869  CA0 delay=41 (13~70),Diff = 5 PI (18 cell)

 8321 13:58:32.870266  CA1 delay=42 (12~72),Diff = 6 PI (22 cell)

 8322 13:58:32.873585  CA2 delay=37 (8~66),Diff = 1 PI (3 cell)

 8323 13:58:32.877314  CA3 delay=37 (8~66),Diff = 1 PI (3 cell)

 8324 13:58:32.880216  CA4 delay=37 (8~67),Diff = 1 PI (3 cell)

 8325 13:58:32.883573  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8326 13:58:32.883653  

 8327 13:58:32.887056  CA PerBit enable=1, Macro0, CA PI delay=36

 8328 13:58:32.887158  

 8329 13:58:32.890168  [CBTSetCACLKResult] CA Dly = 36

 8330 13:58:32.893638  CS Dly: 10 (0~41)

 8331 13:58:32.897173  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8332 13:58:32.900297  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8333 13:58:32.900398  ==

 8334 13:58:32.903693  Dram Type= 6, Freq= 0, CH_1, rank 1

 8335 13:58:32.907425  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8336 13:58:32.907508  ==

 8337 13:58:32.913370  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8338 13:58:32.917131  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8339 13:58:32.923356  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8340 13:58:32.927101  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8341 13:58:32.936705  [CA 0] Center 42 (13~71) winsize 59

 8342 13:58:32.939944  [CA 1] Center 42 (12~72) winsize 61

 8343 13:58:32.943340  [CA 2] Center 37 (8~67) winsize 60

 8344 13:58:32.946933  [CA 3] Center 36 (7~66) winsize 60

 8345 13:58:32.949855  [CA 4] Center 37 (7~67) winsize 61

 8346 13:58:32.953428  [CA 5] Center 36 (6~66) winsize 61

 8347 13:58:32.953511  

 8348 13:58:32.957178  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8349 13:58:32.957261  

 8350 13:58:32.959801  [CATrainingPosCal] consider 2 rank data

 8351 13:58:32.963855  u2DelayCellTimex100 = 258/100 ps

 8352 13:58:32.967042  CA0 delay=41 (13~70),Diff = 5 PI (18 cell)

 8353 13:58:32.973323  CA1 delay=42 (12~72),Diff = 6 PI (22 cell)

 8354 13:58:32.976755  CA2 delay=37 (8~66),Diff = 1 PI (3 cell)

 8355 13:58:32.980357  CA3 delay=37 (8~66),Diff = 1 PI (3 cell)

 8356 13:58:32.983263  CA4 delay=37 (8~67),Diff = 1 PI (3 cell)

 8357 13:58:32.986543  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8358 13:58:32.986624  

 8359 13:58:32.990438  CA PerBit enable=1, Macro0, CA PI delay=36

 8360 13:58:32.990535  

 8361 13:58:32.993529  [CBTSetCACLKResult] CA Dly = 36

 8362 13:58:32.996737  CS Dly: 11 (0~43)

 8363 13:58:32.999878  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8364 13:58:33.003405  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8365 13:58:33.003501  

 8366 13:58:33.006575  ----->DramcWriteLeveling(PI) begin...

 8367 13:58:33.006659  ==

 8368 13:58:33.009762  Dram Type= 6, Freq= 0, CH_1, rank 0

 8369 13:58:33.016340  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8370 13:58:33.016422  ==

 8371 13:58:33.019722  Write leveling (Byte 0): 25 => 25

 8372 13:58:33.019805  Write leveling (Byte 1): 27 => 27

 8373 13:58:33.023196  DramcWriteLeveling(PI) end<-----

 8374 13:58:33.023278  

 8375 13:58:33.023342  ==

 8376 13:58:33.026728  Dram Type= 6, Freq= 0, CH_1, rank 0

 8377 13:58:33.033063  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8378 13:58:33.033146  ==

 8379 13:58:33.036520  [Gating] SW mode calibration

 8380 13:58:33.042854  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8381 13:58:33.046090  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8382 13:58:33.052939   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8383 13:58:33.056088   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8384 13:58:33.059688   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8385 13:58:33.066093   1  4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8386 13:58:33.069656   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8387 13:58:33.073125   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8388 13:58:33.079453   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8389 13:58:33.082995   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8390 13:58:33.086069   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8391 13:58:33.092924   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8392 13:58:33.096421   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8393 13:58:33.099321   1  5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 8394 13:58:33.106199   1  5 16 | B1->B0 | 2727 2929 | 0 1 | (0 1) (1 0)

 8395 13:58:33.109446   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8396 13:58:33.112801   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8397 13:58:33.116094   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8398 13:58:33.122434   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8399 13:58:33.126051   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8400 13:58:33.129444   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8401 13:58:33.136099   1  6 12 | B1->B0 | 2d2d 2929 | 0 0 | (0 0) (1 1)

 8402 13:58:33.139000   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8403 13:58:33.142698   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8404 13:58:33.149006   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8405 13:58:33.152395   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8406 13:58:33.155720   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8407 13:58:33.162380   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8408 13:58:33.165804   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8409 13:58:33.168786   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8410 13:58:33.175759   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8411 13:58:33.178805   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8412 13:58:33.182272   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8413 13:58:33.188755   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8414 13:58:33.192566   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8415 13:58:33.196021   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8416 13:58:33.202286   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8417 13:58:33.205300   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8418 13:58:33.208589   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8419 13:58:33.215345   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8420 13:58:33.218699   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8421 13:58:33.222245   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8422 13:58:33.228719   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8423 13:58:33.232156   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8424 13:58:33.235360   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8425 13:58:33.241944   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8426 13:58:33.245049   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8427 13:58:33.248517  Total UI for P1: 0, mck2ui 16

 8428 13:58:33.251685  best dqsien dly found for B0: ( 1,  9, 12)

 8429 13:58:33.255652   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8430 13:58:33.258422  Total UI for P1: 0, mck2ui 16

 8431 13:58:33.261849  best dqsien dly found for B1: ( 1,  9, 14)

 8432 13:58:33.265081  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8433 13:58:33.268465  best DQS1 dly(MCK, UI, PI) = (1, 9, 14)

 8434 13:58:33.268571  

 8435 13:58:33.274812  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8436 13:58:33.278565  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8437 13:58:33.278645  [Gating] SW calibration Done

 8438 13:58:33.281736  ==

 8439 13:58:33.285195  Dram Type= 6, Freq= 0, CH_1, rank 0

 8440 13:58:33.288376  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8441 13:58:33.288475  ==

 8442 13:58:33.288575  RX Vref Scan: 0

 8443 13:58:33.288677  

 8444 13:58:33.291585  RX Vref 0 -> 0, step: 1

 8445 13:58:33.291662  

 8446 13:58:33.295200  RX Delay 0 -> 252, step: 8

 8447 13:58:33.298015  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8448 13:58:33.301620  iDelay=200, Bit 1, Center 127 (64 ~ 191) 128

 8449 13:58:33.304932  iDelay=200, Bit 2, Center 119 (64 ~ 175) 112

 8450 13:58:33.311333  iDelay=200, Bit 3, Center 131 (72 ~ 191) 120

 8451 13:58:33.314827  iDelay=200, Bit 4, Center 127 (72 ~ 183) 112

 8452 13:58:33.318234  iDelay=200, Bit 5, Center 143 (88 ~ 199) 112

 8453 13:58:33.321611  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8454 13:58:33.325214  iDelay=200, Bit 7, Center 131 (72 ~ 191) 120

 8455 13:58:33.331356  iDelay=200, Bit 8, Center 111 (56 ~ 167) 112

 8456 13:58:33.334484  iDelay=200, Bit 9, Center 115 (56 ~ 175) 120

 8457 13:58:33.337966  iDelay=200, Bit 10, Center 127 (80 ~ 175) 96

 8458 13:58:33.341167  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 8459 13:58:33.344673  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8460 13:58:33.351039  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8461 13:58:33.354626  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8462 13:58:33.358157  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8463 13:58:33.358263  ==

 8464 13:58:33.361042  Dram Type= 6, Freq= 0, CH_1, rank 0

 8465 13:58:33.364575  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8466 13:58:33.367661  ==

 8467 13:58:33.367765  DQS Delay:

 8468 13:58:33.367861  DQS0 = 0, DQS1 = 0

 8469 13:58:33.371550  DQM Delay:

 8470 13:58:33.371650  DQM0 = 132, DQM1 = 126

 8471 13:58:33.374275  DQ Delay:

 8472 13:58:33.377735  DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131

 8473 13:58:33.381463  DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131

 8474 13:58:33.384576  DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119

 8475 13:58:33.387895  DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135

 8476 13:58:33.387992  

 8477 13:58:33.388083  

 8478 13:58:33.388175  ==

 8479 13:58:33.391083  Dram Type= 6, Freq= 0, CH_1, rank 0

 8480 13:58:33.394029  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8481 13:58:33.394101  ==

 8482 13:58:33.394164  

 8483 13:58:33.397515  

 8484 13:58:33.397617  	TX Vref Scan disable

 8485 13:58:33.400757   == TX Byte 0 ==

 8486 13:58:33.404210  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8487 13:58:33.407761  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8488 13:58:33.410706   == TX Byte 1 ==

 8489 13:58:33.414419  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8490 13:58:33.417605  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8491 13:58:33.417682  ==

 8492 13:58:33.420734  Dram Type= 6, Freq= 0, CH_1, rank 0

 8493 13:58:33.427610  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8494 13:58:33.427715  ==

 8495 13:58:33.440581  

 8496 13:58:33.443697  TX Vref early break, caculate TX vref

 8497 13:58:33.446662  TX Vref=16, minBit 13, minWin=21, winSum=362

 8498 13:58:33.450055  TX Vref=18, minBit 1, minWin=22, winSum=375

 8499 13:58:33.453636  TX Vref=20, minBit 6, minWin=23, winSum=387

 8500 13:58:33.456586  TX Vref=22, minBit 1, minWin=24, winSum=398

 8501 13:58:33.459868  TX Vref=24, minBit 0, minWin=24, winSum=402

 8502 13:58:33.466397  TX Vref=26, minBit 13, minWin=24, winSum=411

 8503 13:58:33.469839  TX Vref=28, minBit 0, minWin=24, winSum=413

 8504 13:58:33.473214  TX Vref=30, minBit 0, minWin=25, winSum=415

 8505 13:58:33.476407  TX Vref=32, minBit 1, minWin=24, winSum=408

 8506 13:58:33.479733  TX Vref=34, minBit 6, minWin=23, winSum=396

 8507 13:58:33.483357  TX Vref=36, minBit 6, minWin=22, winSum=386

 8508 13:58:33.489696  [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 30

 8509 13:58:33.489801  

 8510 13:58:33.493105  Final TX Range 0 Vref 30

 8511 13:58:33.493204  

 8512 13:58:33.493296  ==

 8513 13:58:33.496506  Dram Type= 6, Freq= 0, CH_1, rank 0

 8514 13:58:33.499847  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8515 13:58:33.499929  ==

 8516 13:58:33.500020  

 8517 13:58:33.503247  

 8518 13:58:33.503355  	TX Vref Scan disable

 8519 13:58:33.509704  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps

 8520 13:58:33.509810   == TX Byte 0 ==

 8521 13:58:33.513099  u2DelayCellOfst[0]=22 cells (6 PI)

 8522 13:58:33.516608  u2DelayCellOfst[1]=15 cells (4 PI)

 8523 13:58:33.519547  u2DelayCellOfst[2]=0 cells (0 PI)

 8524 13:58:33.523164  u2DelayCellOfst[3]=7 cells (2 PI)

 8525 13:58:33.526400  u2DelayCellOfst[4]=11 cells (3 PI)

 8526 13:58:33.529707  u2DelayCellOfst[5]=26 cells (7 PI)

 8527 13:58:33.532891  u2DelayCellOfst[6]=22 cells (6 PI)

 8528 13:58:33.536399  u2DelayCellOfst[7]=7 cells (2 PI)

 8529 13:58:33.539555  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8530 13:58:33.542861  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8531 13:58:33.546445   == TX Byte 1 ==

 8532 13:58:33.549587  u2DelayCellOfst[8]=0 cells (0 PI)

 8533 13:58:33.552666  u2DelayCellOfst[9]=7 cells (2 PI)

 8534 13:58:33.556088  u2DelayCellOfst[10]=15 cells (4 PI)

 8535 13:58:33.556191  u2DelayCellOfst[11]=11 cells (3 PI)

 8536 13:58:33.559901  u2DelayCellOfst[12]=18 cells (5 PI)

 8537 13:58:33.562715  u2DelayCellOfst[13]=22 cells (6 PI)

 8538 13:58:33.566121  u2DelayCellOfst[14]=22 cells (6 PI)

 8539 13:58:33.569727  u2DelayCellOfst[15]=22 cells (6 PI)

 8540 13:58:33.576053  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8541 13:58:33.579092  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8542 13:58:33.579198  DramC Write-DBI on

 8543 13:58:33.582490  ==

 8544 13:58:33.582582  Dram Type= 6, Freq= 0, CH_1, rank 0

 8545 13:58:33.589563  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8546 13:58:33.589645  ==

 8547 13:58:33.589717  

 8548 13:58:33.589807  

 8549 13:58:33.592632  	TX Vref Scan disable

 8550 13:58:33.592712   == TX Byte 0 ==

 8551 13:58:33.599653  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8552 13:58:33.599759   == TX Byte 1 ==

 8553 13:58:33.602573  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 8554 13:58:33.605989  DramC Write-DBI off

 8555 13:58:33.606066  

 8556 13:58:33.606150  [DATLAT]

 8557 13:58:33.609021  Freq=1600, CH1 RK0

 8558 13:58:33.609127  

 8559 13:58:33.609225  DATLAT Default: 0xf

 8560 13:58:33.612261  0, 0xFFFF, sum = 0

 8561 13:58:33.612372  1, 0xFFFF, sum = 0

 8562 13:58:33.616238  2, 0xFFFF, sum = 0

 8563 13:58:33.616344  3, 0xFFFF, sum = 0

 8564 13:58:33.619095  4, 0xFFFF, sum = 0

 8565 13:58:33.619198  5, 0xFFFF, sum = 0

 8566 13:58:33.622728  6, 0xFFFF, sum = 0

 8567 13:58:33.622829  7, 0xFFFF, sum = 0

 8568 13:58:33.625495  8, 0xFFFF, sum = 0

 8569 13:58:33.625599  9, 0xFFFF, sum = 0

 8570 13:58:33.629036  10, 0xFFFF, sum = 0

 8571 13:58:33.632640  11, 0xFFFF, sum = 0

 8572 13:58:33.632744  12, 0xFFFF, sum = 0

 8573 13:58:33.635639  13, 0x8FFF, sum = 0

 8574 13:58:33.635744  14, 0x0, sum = 1

 8575 13:58:33.638819  15, 0x0, sum = 2

 8576 13:58:33.638926  16, 0x0, sum = 3

 8577 13:58:33.642366  17, 0x0, sum = 4

 8578 13:58:33.642474  best_step = 15

 8579 13:58:33.642568  

 8580 13:58:33.642656  ==

 8581 13:58:33.645317  Dram Type= 6, Freq= 0, CH_1, rank 0

 8582 13:58:33.648860  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8583 13:58:33.648964  ==

 8584 13:58:33.651947  RX Vref Scan: 1

 8585 13:58:33.652022  

 8586 13:58:33.655367  Set Vref Range= 24 -> 127

 8587 13:58:33.655478  

 8588 13:58:33.655568  RX Vref 24 -> 127, step: 1

 8589 13:58:33.655659  

 8590 13:58:33.658944  RX Delay 11 -> 252, step: 4

 8591 13:58:33.659046  

 8592 13:58:33.661869  Set Vref, RX VrefLevel [Byte0]: 24

 8593 13:58:33.665796                           [Byte1]: 24

 8594 13:58:33.669120  

 8595 13:58:33.669204  Set Vref, RX VrefLevel [Byte0]: 25

 8596 13:58:33.672113                           [Byte1]: 25

 8597 13:58:33.676756  

 8598 13:58:33.676838  Set Vref, RX VrefLevel [Byte0]: 26

 8599 13:58:33.679503                           [Byte1]: 26

 8600 13:58:33.684161  

 8601 13:58:33.684243  Set Vref, RX VrefLevel [Byte0]: 27

 8602 13:58:33.687305                           [Byte1]: 27

 8603 13:58:33.691933  

 8604 13:58:33.692016  Set Vref, RX VrefLevel [Byte0]: 28

 8605 13:58:33.695265                           [Byte1]: 28

 8606 13:58:33.699406  

 8607 13:58:33.699502  Set Vref, RX VrefLevel [Byte0]: 29

 8608 13:58:33.702603                           [Byte1]: 29

 8609 13:58:33.706643  

 8610 13:58:33.706725  Set Vref, RX VrefLevel [Byte0]: 30

 8611 13:58:33.710069                           [Byte1]: 30

 8612 13:58:33.714658  

 8613 13:58:33.714740  Set Vref, RX VrefLevel [Byte0]: 31

 8614 13:58:33.717582                           [Byte1]: 31

 8615 13:58:33.722165  

 8616 13:58:33.722247  Set Vref, RX VrefLevel [Byte0]: 32

 8617 13:58:33.725348                           [Byte1]: 32

 8618 13:58:33.729656  

 8619 13:58:33.729738  Set Vref, RX VrefLevel [Byte0]: 33

 8620 13:58:33.732764                           [Byte1]: 33

 8621 13:58:33.737211  

 8622 13:58:33.737293  Set Vref, RX VrefLevel [Byte0]: 34

 8623 13:58:33.740406                           [Byte1]: 34

 8624 13:58:33.744843  

 8625 13:58:33.744925  Set Vref, RX VrefLevel [Byte0]: 35

 8626 13:58:33.748422                           [Byte1]: 35

 8627 13:58:33.752511  

 8628 13:58:33.752593  Set Vref, RX VrefLevel [Byte0]: 36

 8629 13:58:33.756003                           [Byte1]: 36

 8630 13:58:33.760052  

 8631 13:58:33.760134  Set Vref, RX VrefLevel [Byte0]: 37

 8632 13:58:33.763430                           [Byte1]: 37

 8633 13:58:33.767915  

 8634 13:58:33.767997  Set Vref, RX VrefLevel [Byte0]: 38

 8635 13:58:33.770827                           [Byte1]: 38

 8636 13:58:33.775455  

 8637 13:58:33.775542  Set Vref, RX VrefLevel [Byte0]: 39

 8638 13:58:33.778507                           [Byte1]: 39

 8639 13:58:33.783221  

 8640 13:58:33.783303  Set Vref, RX VrefLevel [Byte0]: 40

 8641 13:58:33.786158                           [Byte1]: 40

 8642 13:58:33.790746  

 8643 13:58:33.790829  Set Vref, RX VrefLevel [Byte0]: 41

 8644 13:58:33.793806                           [Byte1]: 41

 8645 13:58:33.798208  

 8646 13:58:33.798291  Set Vref, RX VrefLevel [Byte0]: 42

 8647 13:58:33.801553                           [Byte1]: 42

 8648 13:58:33.806220  

 8649 13:58:33.806301  Set Vref, RX VrefLevel [Byte0]: 43

 8650 13:58:33.809222                           [Byte1]: 43

 8651 13:58:33.813287  

 8652 13:58:33.813369  Set Vref, RX VrefLevel [Byte0]: 44

 8653 13:58:33.816586                           [Byte1]: 44

 8654 13:58:33.821268  

 8655 13:58:33.821350  Set Vref, RX VrefLevel [Byte0]: 45

 8656 13:58:33.824439                           [Byte1]: 45

 8657 13:58:33.828384  

 8658 13:58:33.828467  Set Vref, RX VrefLevel [Byte0]: 46

 8659 13:58:33.832161                           [Byte1]: 46

 8660 13:58:33.836057  

 8661 13:58:33.836139  Set Vref, RX VrefLevel [Byte0]: 47

 8662 13:58:33.839562                           [Byte1]: 47

 8663 13:58:33.844126  

 8664 13:58:33.844208  Set Vref, RX VrefLevel [Byte0]: 48

 8665 13:58:33.846892                           [Byte1]: 48

 8666 13:58:33.851911  

 8667 13:58:33.851993  Set Vref, RX VrefLevel [Byte0]: 49

 8668 13:58:33.854660                           [Byte1]: 49

 8669 13:58:33.859548  

 8670 13:58:33.859630  Set Vref, RX VrefLevel [Byte0]: 50

 8671 13:58:33.862393                           [Byte1]: 50

 8672 13:58:33.866601  

 8673 13:58:33.866683  Set Vref, RX VrefLevel [Byte0]: 51

 8674 13:58:33.869949                           [Byte1]: 51

 8675 13:58:33.874447  

 8676 13:58:33.874529  Set Vref, RX VrefLevel [Byte0]: 52

 8677 13:58:33.877452                           [Byte1]: 52

 8678 13:58:33.882238  

 8679 13:58:33.882320  Set Vref, RX VrefLevel [Byte0]: 53

 8680 13:58:33.885521                           [Byte1]: 53

 8681 13:58:33.889375  

 8682 13:58:33.889458  Set Vref, RX VrefLevel [Byte0]: 54

 8683 13:58:33.892805                           [Byte1]: 54

 8684 13:58:33.896935  

 8685 13:58:33.897017  Set Vref, RX VrefLevel [Byte0]: 55

 8686 13:58:33.900167                           [Byte1]: 55

 8687 13:58:33.904697  

 8688 13:58:33.904779  Set Vref, RX VrefLevel [Byte0]: 56

 8689 13:58:33.908126                           [Byte1]: 56

 8690 13:58:33.912173  

 8691 13:58:33.912255  Set Vref, RX VrefLevel [Byte0]: 57

 8692 13:58:33.915892                           [Byte1]: 57

 8693 13:58:33.919855  

 8694 13:58:33.919937  Set Vref, RX VrefLevel [Byte0]: 58

 8695 13:58:33.923585                           [Byte1]: 58

 8696 13:58:33.927500  

 8697 13:58:33.927582  Set Vref, RX VrefLevel [Byte0]: 59

 8698 13:58:33.930949                           [Byte1]: 59

 8699 13:58:33.935122  

 8700 13:58:33.935233  Set Vref, RX VrefLevel [Byte0]: 60

 8701 13:58:33.938376                           [Byte1]: 60

 8702 13:58:33.942762  

 8703 13:58:33.942867  Set Vref, RX VrefLevel [Byte0]: 61

 8704 13:58:33.946359                           [Byte1]: 61

 8705 13:58:33.950365  

 8706 13:58:33.950472  Set Vref, RX VrefLevel [Byte0]: 62

 8707 13:58:33.953624                           [Byte1]: 62

 8708 13:58:33.957961  

 8709 13:58:33.958067  Set Vref, RX VrefLevel [Byte0]: 63

 8710 13:58:33.961356                           [Byte1]: 63

 8711 13:58:33.965586  

 8712 13:58:33.965688  Set Vref, RX VrefLevel [Byte0]: 64

 8713 13:58:33.969017                           [Byte1]: 64

 8714 13:58:33.973256  

 8715 13:58:33.973358  Set Vref, RX VrefLevel [Byte0]: 65

 8716 13:58:33.976600                           [Byte1]: 65

 8717 13:58:33.980819  

 8718 13:58:33.980922  Set Vref, RX VrefLevel [Byte0]: 66

 8719 13:58:33.984315                           [Byte1]: 66

 8720 13:58:33.988368  

 8721 13:58:33.988455  Set Vref, RX VrefLevel [Byte0]: 67

 8722 13:58:33.991871                           [Byte1]: 67

 8723 13:58:33.996063  

 8724 13:58:33.996166  Set Vref, RX VrefLevel [Byte0]: 68

 8725 13:58:33.999523                           [Byte1]: 68

 8726 13:58:34.003806  

 8727 13:58:34.003917  Set Vref, RX VrefLevel [Byte0]: 69

 8728 13:58:34.007136                           [Byte1]: 69

 8729 13:58:34.011109  

 8730 13:58:34.011213  Final RX Vref Byte 0 = 56 to rank0

 8731 13:58:34.014651  Final RX Vref Byte 1 = 53 to rank0

 8732 13:58:34.017600  Final RX Vref Byte 0 = 56 to rank1

 8733 13:58:34.021255  Final RX Vref Byte 1 = 53 to rank1==

 8734 13:58:34.024691  Dram Type= 6, Freq= 0, CH_1, rank 0

 8735 13:58:34.030898  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8736 13:58:34.031009  ==

 8737 13:58:34.031103  DQS Delay:

 8738 13:58:34.034295  DQS0 = 0, DQS1 = 0

 8739 13:58:34.034395  DQM Delay:

 8740 13:58:34.034463  DQM0 = 131, DQM1 = 123

 8741 13:58:34.037795  DQ Delay:

 8742 13:58:34.041145  DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130

 8743 13:58:34.044184  DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128

 8744 13:58:34.047726  DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116

 8745 13:58:34.051175  DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132

 8746 13:58:34.051280  

 8747 13:58:34.051381  

 8748 13:58:34.051481  

 8749 13:58:34.054286  [DramC_TX_OE_Calibration] TA2

 8750 13:58:34.057509  Original DQ_B0 (3 6) =30, OEN = 27

 8751 13:58:34.061066  Original DQ_B1 (3 6) =30, OEN = 27

 8752 13:58:34.064311  24, 0x0, End_B0=24 End_B1=24

 8753 13:58:34.064428  25, 0x0, End_B0=25 End_B1=25

 8754 13:58:34.067634  26, 0x0, End_B0=26 End_B1=26

 8755 13:58:34.070580  27, 0x0, End_B0=27 End_B1=27

 8756 13:58:34.074074  28, 0x0, End_B0=28 End_B1=28

 8757 13:58:34.077670  29, 0x0, End_B0=29 End_B1=29

 8758 13:58:34.077776  30, 0x0, End_B0=30 End_B1=30

 8759 13:58:34.081309  31, 0x4141, End_B0=30 End_B1=30

 8760 13:58:34.084184  Byte0 end_step=30  best_step=27

 8761 13:58:34.087261  Byte1 end_step=30  best_step=27

 8762 13:58:34.090512  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8763 13:58:34.093910  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8764 13:58:34.094012  

 8765 13:58:34.094105  

 8766 13:58:34.100372  [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps

 8767 13:58:34.103966  CH1 RK0: MR19=303, MR18=80D

 8768 13:58:34.110508  CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15

 8769 13:58:34.110593  

 8770 13:58:34.114136  ----->DramcWriteLeveling(PI) begin...

 8771 13:58:34.114241  ==

 8772 13:58:34.116949  Dram Type= 6, Freq= 0, CH_1, rank 1

 8773 13:58:34.120224  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8774 13:58:34.120330  ==

 8775 13:58:34.123920  Write leveling (Byte 0): 24 => 24

 8776 13:58:34.127365  Write leveling (Byte 1): 28 => 28

 8777 13:58:34.130538  DramcWriteLeveling(PI) end<-----

 8778 13:58:34.130640  

 8779 13:58:34.130731  ==

 8780 13:58:34.134060  Dram Type= 6, Freq= 0, CH_1, rank 1

 8781 13:58:34.137212  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8782 13:58:34.137315  ==

 8783 13:58:34.140367  [Gating] SW mode calibration

 8784 13:58:34.147080  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8785 13:58:34.153777  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8786 13:58:34.157058   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8787 13:58:34.160452   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8788 13:58:34.167336   1  4  8 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)

 8789 13:58:34.170406   1  4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8790 13:58:34.173729   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8791 13:58:34.180480   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8792 13:58:34.183489   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8793 13:58:34.186739   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8794 13:58:34.193397   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8795 13:58:34.196770   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8796 13:58:34.200290   1  5  8 | B1->B0 | 3232 2b2b | 1 0 | (1 0) (0 1)

 8797 13:58:34.206742   1  5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)

 8798 13:58:34.210236   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8799 13:58:34.213251   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8800 13:58:34.219836   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8801 13:58:34.223404   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8802 13:58:34.226754   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8803 13:58:34.233347   1  6  4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 8804 13:58:34.236584   1  6  8 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)

 8805 13:58:34.239980   1  6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 8806 13:58:34.246806   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8807 13:58:34.249756   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8808 13:58:34.253216   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8809 13:58:34.259725   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8810 13:58:34.263135   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8811 13:58:34.266395   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8812 13:58:34.273333   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8813 13:58:34.276295   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8814 13:58:34.279550   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8815 13:58:34.286261   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8816 13:58:34.289675   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8817 13:58:34.292588   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8818 13:58:34.299685   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8819 13:58:34.302989   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8820 13:58:34.306551   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8821 13:58:34.313213   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8822 13:58:34.316040   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8823 13:58:34.319560   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8824 13:58:34.326037   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8825 13:58:34.329528   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8826 13:58:34.333099   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8827 13:58:34.339409   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8828 13:58:34.342828   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8829 13:58:34.345636   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8830 13:58:34.349395  Total UI for P1: 0, mck2ui 16

 8831 13:58:34.353016  best dqsien dly found for B0: ( 1,  9,  8)

 8832 13:58:34.355941  Total UI for P1: 0, mck2ui 16

 8833 13:58:34.359352  best dqsien dly found for B1: ( 1,  9,  8)

 8834 13:58:34.362188  best DQS0 dly(MCK, UI, PI) = (1, 9, 8)

 8835 13:58:34.365828  best DQS1 dly(MCK, UI, PI) = (1, 9, 8)

 8836 13:58:34.365933  

 8837 13:58:34.369002  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)

 8838 13:58:34.375511  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)

 8839 13:58:34.375620  [Gating] SW calibration Done

 8840 13:58:34.375715  ==

 8841 13:58:34.379156  Dram Type= 6, Freq= 0, CH_1, rank 1

 8842 13:58:34.385685  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8843 13:58:34.385794  ==

 8844 13:58:34.385888  RX Vref Scan: 0

 8845 13:58:34.385983  

 8846 13:58:34.388988  RX Vref 0 -> 0, step: 1

 8847 13:58:34.389089  

 8848 13:58:34.392046  RX Delay 0 -> 252, step: 8

 8849 13:58:34.395557  iDelay=200, Bit 0, Center 131 (72 ~ 191) 120

 8850 13:58:34.399201  iDelay=200, Bit 1, Center 127 (72 ~ 183) 112

 8851 13:58:34.402340  iDelay=200, Bit 2, Center 115 (56 ~ 175) 120

 8852 13:58:34.405911  iDelay=200, Bit 3, Center 127 (64 ~ 191) 128

 8853 13:58:34.411982  iDelay=200, Bit 4, Center 127 (64 ~ 191) 128

 8854 13:58:34.415679  iDelay=200, Bit 5, Center 139 (80 ~ 199) 120

 8855 13:58:34.418310  iDelay=200, Bit 6, Center 139 (80 ~ 199) 120

 8856 13:58:34.421820  iDelay=200, Bit 7, Center 127 (64 ~ 191) 128

 8857 13:58:34.425433  iDelay=200, Bit 8, Center 111 (48 ~ 175) 128

 8858 13:58:34.431932  iDelay=200, Bit 9, Center 115 (56 ~ 175) 120

 8859 13:58:34.434884  iDelay=200, Bit 10, Center 131 (72 ~ 191) 120

 8860 13:58:34.438361  iDelay=200, Bit 11, Center 123 (64 ~ 183) 120

 8861 13:58:34.441637  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8862 13:58:34.448481  iDelay=200, Bit 13, Center 139 (80 ~ 199) 120

 8863 13:58:34.451810  iDelay=200, Bit 14, Center 131 (72 ~ 191) 120

 8864 13:58:34.455118  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8865 13:58:34.455222  ==

 8866 13:58:34.458089  Dram Type= 6, Freq= 0, CH_1, rank 1

 8867 13:58:34.461447  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8868 13:58:34.461551  ==

 8869 13:58:34.464783  DQS Delay:

 8870 13:58:34.464888  DQS0 = 0, DQS1 = 0

 8871 13:58:34.468311  DQM Delay:

 8872 13:58:34.468421  DQM0 = 129, DQM1 = 127

 8873 13:58:34.471619  DQ Delay:

 8874 13:58:34.474579  DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127

 8875 13:58:34.478480  DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127

 8876 13:58:34.481661  DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123

 8877 13:58:34.485119  DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135

 8878 13:58:34.485223  

 8879 13:58:34.485319  

 8880 13:58:34.485409  ==

 8881 13:58:34.488110  Dram Type= 6, Freq= 0, CH_1, rank 1

 8882 13:58:34.491280  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8883 13:58:34.491406  ==

 8884 13:58:34.491496  

 8885 13:58:34.491560  

 8886 13:58:34.494630  	TX Vref Scan disable

 8887 13:58:34.498101   == TX Byte 0 ==

 8888 13:58:34.501334  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8889 13:58:34.504474  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8890 13:58:34.507952   == TX Byte 1 ==

 8891 13:58:34.511347  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8892 13:58:34.514495  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8893 13:58:34.514600  ==

 8894 13:58:34.517685  Dram Type= 6, Freq= 0, CH_1, rank 1

 8895 13:58:34.524505  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8896 13:58:34.524596  ==

 8897 13:58:34.536061  

 8898 13:58:34.539425  TX Vref early break, caculate TX vref

 8899 13:58:34.543037  TX Vref=16, minBit 0, minWin=23, winSum=383

 8900 13:58:34.545972  TX Vref=18, minBit 0, minWin=23, winSum=390

 8901 13:58:34.549790  TX Vref=20, minBit 0, minWin=24, winSum=401

 8902 13:58:34.552665  TX Vref=22, minBit 0, minWin=23, winSum=407

 8903 13:58:34.556095  TX Vref=24, minBit 0, minWin=25, winSum=415

 8904 13:58:34.562910  TX Vref=26, minBit 1, minWin=25, winSum=424

 8905 13:58:34.566228  TX Vref=28, minBit 1, minWin=25, winSum=423

 8906 13:58:34.569474  TX Vref=30, minBit 1, minWin=25, winSum=423

 8907 13:58:34.572622  TX Vref=32, minBit 1, minWin=24, winSum=413

 8908 13:58:34.575796  TX Vref=34, minBit 1, minWin=23, winSum=401

 8909 13:58:34.582650  [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 26

 8910 13:58:34.582736  

 8911 13:58:34.585914  Final TX Range 0 Vref 26

 8912 13:58:34.586018  

 8913 13:58:34.586117  ==

 8914 13:58:34.589241  Dram Type= 6, Freq= 0, CH_1, rank 1

 8915 13:58:34.592417  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8916 13:58:34.592523  ==

 8917 13:58:34.592586  

 8918 13:58:34.592646  

 8919 13:58:34.595555  	TX Vref Scan disable

 8920 13:58:34.602151  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps

 8921 13:58:34.602255   == TX Byte 0 ==

 8922 13:58:34.605887  u2DelayCellOfst[0]=18 cells (5 PI)

 8923 13:58:34.608860  u2DelayCellOfst[1]=15 cells (4 PI)

 8924 13:58:34.612292  u2DelayCellOfst[2]=0 cells (0 PI)

 8925 13:58:34.615562  u2DelayCellOfst[3]=7 cells (2 PI)

 8926 13:58:34.619480  u2DelayCellOfst[4]=11 cells (3 PI)

 8927 13:58:34.622235  u2DelayCellOfst[5]=22 cells (6 PI)

 8928 13:58:34.625742  u2DelayCellOfst[6]=22 cells (6 PI)

 8929 13:58:34.628958  u2DelayCellOfst[7]=7 cells (2 PI)

 8930 13:58:34.632235  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8931 13:58:34.635643  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8932 13:58:34.638866   == TX Byte 1 ==

 8933 13:58:34.638967  u2DelayCellOfst[8]=0 cells (0 PI)

 8934 13:58:34.642159  u2DelayCellOfst[9]=7 cells (2 PI)

 8935 13:58:34.645707  u2DelayCellOfst[10]=15 cells (4 PI)

 8936 13:58:34.649090  u2DelayCellOfst[11]=7 cells (2 PI)

 8937 13:58:34.652405  u2DelayCellOfst[12]=18 cells (5 PI)

 8938 13:58:34.655684  u2DelayCellOfst[13]=15 cells (4 PI)

 8939 13:58:34.659197  u2DelayCellOfst[14]=18 cells (5 PI)

 8940 13:58:34.662155  u2DelayCellOfst[15]=18 cells (5 PI)

 8941 13:58:34.665712  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8942 13:58:34.672209  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8943 13:58:34.672317  DramC Write-DBI on

 8944 13:58:34.672414  ==

 8945 13:58:34.675570  Dram Type= 6, Freq= 0, CH_1, rank 1

 8946 13:58:34.678928  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8947 13:58:34.681968  ==

 8948 13:58:34.682068  

 8949 13:58:34.682164  

 8950 13:58:34.682253  	TX Vref Scan disable

 8951 13:58:34.685336   == TX Byte 0 ==

 8952 13:58:34.688734  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8953 13:58:34.692059   == TX Byte 1 ==

 8954 13:58:34.695323  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8955 13:58:34.698872  DramC Write-DBI off

 8956 13:58:34.698977  

 8957 13:58:34.699069  [DATLAT]

 8958 13:58:34.699158  Freq=1600, CH1 RK1

 8959 13:58:34.699249  

 8960 13:58:34.702206  DATLAT Default: 0xf

 8961 13:58:34.702309  0, 0xFFFF, sum = 0

 8962 13:58:34.705676  1, 0xFFFF, sum = 0

 8963 13:58:34.708578  2, 0xFFFF, sum = 0

 8964 13:58:34.708742  3, 0xFFFF, sum = 0

 8965 13:58:34.712207  4, 0xFFFF, sum = 0

 8966 13:58:34.712313  5, 0xFFFF, sum = 0

 8967 13:58:34.715511  6, 0xFFFF, sum = 0

 8968 13:58:34.715590  7, 0xFFFF, sum = 0

 8969 13:58:34.718784  8, 0xFFFF, sum = 0

 8970 13:58:34.718859  9, 0xFFFF, sum = 0

 8971 13:58:34.722108  10, 0xFFFF, sum = 0

 8972 13:58:34.722215  11, 0xFFFF, sum = 0

 8973 13:58:34.725077  12, 0xFFFF, sum = 0

 8974 13:58:34.725182  13, 0x8FFF, sum = 0

 8975 13:58:34.728570  14, 0x0, sum = 1

 8976 13:58:34.728650  15, 0x0, sum = 2

 8977 13:58:34.732012  16, 0x0, sum = 3

 8978 13:58:34.732089  17, 0x0, sum = 4

 8979 13:58:34.735323  best_step = 15

 8980 13:58:34.735449  

 8981 13:58:34.735539  ==

 8982 13:58:34.738481  Dram Type= 6, Freq= 0, CH_1, rank 1

 8983 13:58:34.742065  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8984 13:58:34.742170  ==

 8985 13:58:34.744994  RX Vref Scan: 0

 8986 13:58:34.745082  

 8987 13:58:34.745146  RX Vref 0 -> 0, step: 1

 8988 13:58:34.745207  

 8989 13:58:34.748714  RX Delay 3 -> 252, step: 4

 8990 13:58:34.751755  iDelay=195, Bit 0, Center 132 (79 ~ 186) 108

 8991 13:58:34.758452  iDelay=195, Bit 1, Center 126 (75 ~ 178) 104

 8992 13:58:34.761930  iDelay=195, Bit 2, Center 116 (63 ~ 170) 108

 8993 13:58:34.764910  iDelay=195, Bit 3, Center 126 (71 ~ 182) 112

 8994 13:58:34.768520  iDelay=195, Bit 4, Center 124 (67 ~ 182) 116

 8995 13:58:34.771496  iDelay=195, Bit 5, Center 138 (83 ~ 194) 112

 8996 13:58:34.778403  iDelay=195, Bit 6, Center 138 (83 ~ 194) 112

 8997 13:58:34.782021  iDelay=195, Bit 7, Center 122 (67 ~ 178) 112

 8998 13:58:34.785181  iDelay=195, Bit 8, Center 112 (55 ~ 170) 116

 8999 13:58:34.788309  iDelay=195, Bit 9, Center 112 (59 ~ 166) 108

 9000 13:58:34.791721  iDelay=195, Bit 10, Center 128 (75 ~ 182) 108

 9001 13:58:34.798365  iDelay=195, Bit 11, Center 120 (67 ~ 174) 108

 9002 13:58:34.801451  iDelay=195, Bit 12, Center 132 (79 ~ 186) 108

 9003 13:58:34.804833  iDelay=195, Bit 13, Center 132 (79 ~ 186) 108

 9004 13:58:34.808435  iDelay=195, Bit 14, Center 130 (75 ~ 186) 112

 9005 13:58:34.814974  iDelay=195, Bit 15, Center 134 (79 ~ 190) 112

 9006 13:58:34.815083  ==

 9007 13:58:34.818426  Dram Type= 6, Freq= 0, CH_1, rank 1

 9008 13:58:34.821448  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9009 13:58:34.821554  ==

 9010 13:58:34.821647  DQS Delay:

 9011 13:58:34.824866  DQS0 = 0, DQS1 = 0

 9012 13:58:34.824971  DQM Delay:

 9013 13:58:34.828097  DQM0 = 127, DQM1 = 125

 9014 13:58:34.828176  DQ Delay:

 9015 13:58:34.831495  DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =126

 9016 13:58:34.834962  DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122

 9017 13:58:34.838143  DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120

 9018 13:58:34.841913  DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134

 9019 13:58:34.842019  

 9020 13:58:34.842093  

 9021 13:58:34.842185  

 9022 13:58:34.844666  [DramC_TX_OE_Calibration] TA2

 9023 13:58:34.848050  Original DQ_B0 (3 6) =30, OEN = 27

 9024 13:58:34.851482  Original DQ_B1 (3 6) =30, OEN = 27

 9025 13:58:34.854976  24, 0x0, End_B0=24 End_B1=24

 9026 13:58:34.857975  25, 0x0, End_B0=25 End_B1=25

 9027 13:58:34.858089  26, 0x0, End_B0=26 End_B1=26

 9028 13:58:34.861754  27, 0x0, End_B0=27 End_B1=27

 9029 13:58:34.864672  28, 0x0, End_B0=28 End_B1=28

 9030 13:58:34.868275  29, 0x0, End_B0=29 End_B1=29

 9031 13:58:34.871131  30, 0x0, End_B0=30 End_B1=30

 9032 13:58:34.871239  31, 0x4141, End_B0=30 End_B1=30

 9033 13:58:34.874862  Byte0 end_step=30  best_step=27

 9034 13:58:34.877935  Byte1 end_step=30  best_step=27

 9035 13:58:34.881450  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9036 13:58:34.884723  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9037 13:58:34.884829  

 9038 13:58:34.884925  

 9039 13:58:34.890816  [DQSOSCAuto] RK1, (LSB)MR18= 0x121d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps

 9040 13:58:34.894753  CH1 RK1: MR19=303, MR18=121D

 9041 13:58:34.901127  CH1_RK1: MR19=0x303, MR18=0x121D, DQSOSC=395, MR23=63, INC=23, DEC=15

 9042 13:58:34.904653  [RxdqsGatingPostProcess] freq 1600

 9043 13:58:34.911341  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9044 13:58:34.914706  best DQS0 dly(2T, 0.5T) = (1, 1)

 9045 13:58:34.914808  best DQS1 dly(2T, 0.5T) = (1, 1)

 9046 13:58:34.917424  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9047 13:58:34.920827  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9048 13:58:34.923916  best DQS0 dly(2T, 0.5T) = (1, 1)

 9049 13:58:34.927734  best DQS1 dly(2T, 0.5T) = (1, 1)

 9050 13:58:34.930973  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9051 13:58:34.934198  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9052 13:58:34.937471  Pre-setting of DQS Precalculation

 9053 13:58:34.940758  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9054 13:58:34.950613  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9055 13:58:34.957471  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9056 13:58:34.957579  

 9057 13:58:34.957672  

 9058 13:58:34.960703  [Calibration Summary] 3200 Mbps

 9059 13:58:34.960813  CH 0, Rank 0

 9060 13:58:34.963953  SW Impedance     : PASS

 9061 13:58:34.964094  DUTY Scan        : NO K

 9062 13:58:34.967060  ZQ Calibration   : PASS

 9063 13:58:34.970539  Jitter Meter     : NO K

 9064 13:58:34.970621  CBT Training     : PASS

 9065 13:58:34.974062  Write leveling   : PASS

 9066 13:58:34.977022  RX DQS gating    : PASS

 9067 13:58:34.977140  RX DQ/DQS(RDDQC) : PASS

 9068 13:58:34.980519  TX DQ/DQS        : PASS

 9069 13:58:34.983754  RX DATLAT        : PASS

 9070 13:58:34.983861  RX DQ/DQS(Engine): PASS

 9071 13:58:34.987339  TX OE            : PASS

 9072 13:58:34.987446  All Pass.

 9073 13:58:34.987515  

 9074 13:58:34.990501  CH 0, Rank 1

 9075 13:58:34.990576  SW Impedance     : PASS

 9076 13:58:34.993882  DUTY Scan        : NO K

 9077 13:58:34.996987  ZQ Calibration   : PASS

 9078 13:58:34.997089  Jitter Meter     : NO K

 9079 13:58:35.000374  CBT Training     : PASS

 9080 13:58:35.003454  Write leveling   : PASS

 9081 13:58:35.003585  RX DQS gating    : PASS

 9082 13:58:35.006852  RX DQ/DQS(RDDQC) : PASS

 9083 13:58:35.010349  TX DQ/DQS        : PASS

 9084 13:58:35.010472  RX DATLAT        : PASS

 9085 13:58:35.013888  RX DQ/DQS(Engine): PASS

 9086 13:58:35.013999  TX OE            : PASS

 9087 13:58:35.016736  All Pass.

 9088 13:58:35.016818  

 9089 13:58:35.016884  CH 1, Rank 0

 9090 13:58:35.020064  SW Impedance     : PASS

 9091 13:58:35.020146  DUTY Scan        : NO K

 9092 13:58:35.023520  ZQ Calibration   : PASS

 9093 13:58:35.026805  Jitter Meter     : NO K

 9094 13:58:35.026887  CBT Training     : PASS

 9095 13:58:35.030426  Write leveling   : PASS

 9096 13:58:35.033758  RX DQS gating    : PASS

 9097 13:58:35.033842  RX DQ/DQS(RDDQC) : PASS

 9098 13:58:35.037055  TX DQ/DQS        : PASS

 9099 13:58:35.040290  RX DATLAT        : PASS

 9100 13:58:35.040372  RX DQ/DQS(Engine): PASS

 9101 13:58:35.043494  TX OE            : PASS

 9102 13:58:35.043577  All Pass.

 9103 13:58:35.043642  

 9104 13:58:35.047124  CH 1, Rank 1

 9105 13:58:35.047206  SW Impedance     : PASS

 9106 13:58:35.050340  DUTY Scan        : NO K

 9107 13:58:35.053538  ZQ Calibration   : PASS

 9108 13:58:35.053621  Jitter Meter     : NO K

 9109 13:58:35.056788  CBT Training     : PASS

 9110 13:58:35.060239  Write leveling   : PASS

 9111 13:58:35.060322  RX DQS gating    : PASS

 9112 13:58:35.063528  RX DQ/DQS(RDDQC) : PASS

 9113 13:58:35.063611  TX DQ/DQS        : PASS

 9114 13:58:35.066635  RX DATLAT        : PASS

 9115 13:58:35.070239  RX DQ/DQS(Engine): PASS

 9116 13:58:35.070321  TX OE            : PASS

 9117 13:58:35.073490  All Pass.

 9118 13:58:35.073600  

 9119 13:58:35.073699  DramC Write-DBI on

 9120 13:58:35.076981  	PER_BANK_REFRESH: Hybrid Mode

 9121 13:58:35.080054  TX_TRACKING: ON

 9122 13:58:35.087217  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9123 13:58:35.097012  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9124 13:58:35.103047  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9125 13:58:35.106443  [FAST_K] Save calibration result to emmc

 9126 13:58:35.110191  sync common calibartion params.

 9127 13:58:35.110306  sync cbt_mode0:1, 1:1

 9128 13:58:35.113237  dram_init: ddr_geometry: 2

 9129 13:58:35.116687  dram_init: ddr_geometry: 2

 9130 13:58:35.119964  dram_init: ddr_geometry: 2

 9131 13:58:35.120047  0:dram_rank_size:100000000

 9132 13:58:35.123520  1:dram_rank_size:100000000

 9133 13:58:35.129863  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9134 13:58:35.129945  DFS_SHUFFLE_HW_MODE: ON

 9135 13:58:35.136259  dramc_set_vcore_voltage set vcore to 725000

 9136 13:58:35.136342  Read voltage for 1600, 0

 9137 13:58:35.139581  Vio18 = 0

 9138 13:58:35.139680  Vcore = 725000

 9139 13:58:35.139759  Vdram = 0

 9140 13:58:35.139820  Vddq = 0

 9141 13:58:35.142825  Vmddr = 0

 9142 13:58:35.142907  switch to 3200 Mbps bootup

 9143 13:58:35.146575  [DramcRunTimeConfig]

 9144 13:58:35.146696  PHYPLL

 9145 13:58:35.149436  DPM_CONTROL_AFTERK: ON

 9146 13:58:35.149549  PER_BANK_REFRESH: ON

 9147 13:58:35.152961  REFRESH_OVERHEAD_REDUCTION: ON

 9148 13:58:35.156421  CMD_PICG_NEW_MODE: OFF

 9149 13:58:35.156518  XRTWTW_NEW_MODE: ON

 9150 13:58:35.160069  XRTRTR_NEW_MODE: ON

 9151 13:58:35.160182  TX_TRACKING: ON

 9152 13:58:35.162988  RDSEL_TRACKING: OFF

 9153 13:58:35.166221  DQS Precalculation for DVFS: ON

 9154 13:58:35.166304  RX_TRACKING: OFF

 9155 13:58:35.169513  HW_GATING DBG: ON

 9156 13:58:35.169625  ZQCS_ENABLE_LP4: ON

 9157 13:58:35.173429  RX_PICG_NEW_MODE: ON

 9158 13:58:35.173511  TX_PICG_NEW_MODE: ON

 9159 13:58:35.176193  ENABLE_RX_DCM_DPHY: ON

 9160 13:58:35.179730  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9161 13:58:35.183614  DUMMY_READ_FOR_TRACKING: OFF

 9162 13:58:35.186310  !!! SPM_CONTROL_AFTERK: OFF

 9163 13:58:35.186431  !!! SPM could not control APHY

 9164 13:58:35.189665  IMPEDANCE_TRACKING: ON

 9165 13:58:35.189747  TEMP_SENSOR: ON

 9166 13:58:35.193071  HW_SAVE_FOR_SR: OFF

 9167 13:58:35.196819  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9168 13:58:35.199344  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9169 13:58:35.202994  Read ODT Tracking: ON

 9170 13:58:35.203109  Refresh Rate DeBounce: ON

 9171 13:58:35.206042  DFS_NO_QUEUE_FLUSH: ON

 9172 13:58:35.209436  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9173 13:58:35.212651  ENABLE_DFS_RUNTIME_MRW: OFF

 9174 13:58:35.212774  DDR_RESERVE_NEW_MODE: ON

 9175 13:58:35.216023  MR_CBT_SWITCH_FREQ: ON

 9176 13:58:35.219472  =========================

 9177 13:58:35.237145  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9178 13:58:35.240215  dram_init: ddr_geometry: 2

 9179 13:58:35.258465  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9180 13:58:35.261901  dram_init: dram init end (result: 0)

 9181 13:58:35.268578  DRAM-K: Full calibration passed in 24575 msecs

 9182 13:58:35.272062  MRC: failed to locate region type 0.

 9183 13:58:35.272145  DRAM rank0 size:0x100000000,

 9184 13:58:35.275190  DRAM rank1 size=0x100000000

 9185 13:58:35.285198  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9186 13:58:35.292248  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9187 13:58:35.298702  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9188 13:58:35.305242  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9189 13:58:35.308527  DRAM rank0 size:0x100000000,

 9190 13:58:35.311855  DRAM rank1 size=0x100000000

 9191 13:58:35.311954  CBMEM:

 9192 13:58:35.315265  IMD: root @ 0xfffff000 254 entries.

 9193 13:58:35.318920  IMD: root @ 0xffffec00 62 entries.

 9194 13:58:35.321923  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9195 13:58:35.325195  WARNING: RO_VPD is uninitialized or empty.

 9196 13:58:35.331651  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9197 13:58:35.338527  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9198 13:58:35.351751  read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps

 9199 13:58:35.362858  BS: romstage times (exec / console): total (unknown) / 24041 ms

 9200 13:58:35.363005  

 9201 13:58:35.363140  

 9202 13:58:35.372656  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9203 13:58:35.376198  ARM64: Exception handlers installed.

 9204 13:58:35.379064  ARM64: Testing exception

 9205 13:58:35.382635  ARM64: Done test exception

 9206 13:58:35.382719  Enumerating buses...

 9207 13:58:35.386430  Show all devs... Before device enumeration.

 9208 13:58:35.389450  Root Device: enabled 1

 9209 13:58:35.392354  CPU_CLUSTER: 0: enabled 1

 9210 13:58:35.392468  CPU: 00: enabled 1

 9211 13:58:35.395980  Compare with tree...

 9212 13:58:35.396089  Root Device: enabled 1

 9213 13:58:35.399524   CPU_CLUSTER: 0: enabled 1

 9214 13:58:35.402827    CPU: 00: enabled 1

 9215 13:58:35.402932  Root Device scanning...

 9216 13:58:35.406081  scan_static_bus for Root Device

 9217 13:58:35.409495  CPU_CLUSTER: 0 enabled

 9218 13:58:35.412391  scan_static_bus for Root Device done

 9219 13:58:35.415618  scan_bus: bus Root Device finished in 8 msecs

 9220 13:58:35.415730  done

 9221 13:58:35.422559  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9222 13:58:35.425757  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9223 13:58:35.432375  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9224 13:58:35.435538  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9225 13:58:35.438883  Allocating resources...

 9226 13:58:35.442371  Reading resources...

 9227 13:58:35.445740  Root Device read_resources bus 0 link: 0

 9228 13:58:35.445822  DRAM rank0 size:0x100000000,

 9229 13:58:35.448531  DRAM rank1 size=0x100000000

 9230 13:58:35.452230  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9231 13:58:35.455330  CPU: 00 missing read_resources

 9232 13:58:35.462175  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9233 13:58:35.465890  Root Device read_resources bus 0 link: 0 done

 9234 13:58:35.466015  Done reading resources.

 9235 13:58:35.471725  Show resources in subtree (Root Device)...After reading.

 9236 13:58:35.475181   Root Device child on link 0 CPU_CLUSTER: 0

 9237 13:58:35.478717    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9238 13:58:35.488861    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9239 13:58:35.488968     CPU: 00

 9240 13:58:35.491668  Root Device assign_resources, bus 0 link: 0

 9241 13:58:35.495216  CPU_CLUSTER: 0 missing set_resources

 9242 13:58:35.502126  Root Device assign_resources, bus 0 link: 0 done

 9243 13:58:35.502246  Done setting resources.

 9244 13:58:35.508386  Show resources in subtree (Root Device)...After assigning values.

 9245 13:58:35.512044   Root Device child on link 0 CPU_CLUSTER: 0

 9246 13:58:35.514781    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9247 13:58:35.524721    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9248 13:58:35.524829     CPU: 00

 9249 13:58:35.527885  Done allocating resources.

 9250 13:58:35.535000  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9251 13:58:35.535086  Enabling resources...

 9252 13:58:35.535152  done.

 9253 13:58:35.541436  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9254 13:58:35.541527  Initializing devices...

 9255 13:58:35.545158  Root Device init

 9256 13:58:35.545240  init hardware done!

 9257 13:58:35.547912  0x00000018: ctrlr->caps

 9258 13:58:35.551126  52.000 MHz: ctrlr->f_max

 9259 13:58:35.551238  0.400 MHz: ctrlr->f_min

 9260 13:58:35.554389  0x40ff8080: ctrlr->voltages

 9261 13:58:35.557848  sclk: 390625

 9262 13:58:35.557962  Bus Width = 1

 9263 13:58:35.558057  sclk: 390625

 9264 13:58:35.560985  Bus Width = 1

 9265 13:58:35.561096  Early init status = 3

 9266 13:58:35.568306  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9267 13:58:35.570881  in-header: 03 fb 00 00 01 00 00 00 

 9268 13:58:35.574355  in-data: 01 

 9269 13:58:35.577705  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9270 13:58:35.581412  in-header: 03 fb 00 00 01 00 00 00 

 9271 13:58:35.584975  in-data: 01 

 9272 13:58:35.588617  [SSUSB] Setting up USB HOST controller...

 9273 13:58:35.591601  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9274 13:58:35.595226  [SSUSB] phy power-on done.

 9275 13:58:35.598321  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9276 13:58:35.604739  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9277 13:58:35.608034  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9278 13:58:35.614977  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9279 13:58:35.621543  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9280 13:58:35.628122  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9281 13:58:35.634624  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9282 13:58:35.641528  read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps

 9283 13:58:35.645196  SPM: binary array size = 0x9dc

 9284 13:58:35.647865  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9285 13:58:35.654526  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9286 13:58:35.661662  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9287 13:58:35.668259  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9288 13:58:35.671038  configure_display: Starting display init

 9289 13:58:35.705052  anx7625_power_on_init: Init interface.

 9290 13:58:35.708688  anx7625_disable_pd_protocol: Disabled PD feature.

 9291 13:58:35.711716  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9292 13:58:35.739392  anx7625_start_dp_work: Secure OCM version=00

 9293 13:58:35.742941  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9294 13:58:35.757407  sp_tx_get_edid_block: EDID Block = 1

 9295 13:58:35.860393  Extracted contents:

 9296 13:58:35.863340  header:          00 ff ff ff ff ff ff 00

 9297 13:58:35.866927  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9298 13:58:35.870103  version:         01 04

 9299 13:58:35.873721  basic params:    95 1f 11 78 0a

 9300 13:58:35.876775  chroma info:     76 90 94 55 54 90 27 21 50 54

 9301 13:58:35.880434  established:     00 00 00

 9302 13:58:35.886878  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9303 13:58:35.890056  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9304 13:58:35.896624  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9305 13:58:35.903557  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9306 13:58:35.909723  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9307 13:58:35.913442  extensions:      00

 9308 13:58:35.913527  checksum:        fb

 9309 13:58:35.913594  

 9310 13:58:35.916453  Manufacturer: IVO Model 57d Serial Number 0

 9311 13:58:35.919970  Made week 0 of 2020

 9312 13:58:35.920052  EDID version: 1.4

 9313 13:58:35.923308  Digital display

 9314 13:58:35.926199  6 bits per primary color channel

 9315 13:58:35.926313  DisplayPort interface

 9316 13:58:35.929791  Maximum image size: 31 cm x 17 cm

 9317 13:58:35.933322  Gamma: 220%

 9318 13:58:35.933428  Check DPMS levels

 9319 13:58:35.936544  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9320 13:58:35.943109  First detailed timing is preferred timing

 9321 13:58:35.943241  Established timings supported:

 9322 13:58:35.946110  Standard timings supported:

 9323 13:58:35.949347  Detailed timings

 9324 13:58:35.953120  Hex of detail: 383680a07038204018303c0035ae10000019

 9325 13:58:35.956398  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9326 13:58:35.962587                 0780 0798 07c8 0820 hborder 0

 9327 13:58:35.966159                 0438 043b 0447 0458 vborder 0

 9328 13:58:35.969870                 -hsync -vsync

 9329 13:58:35.969945  Did detailed timing

 9330 13:58:35.975902  Hex of detail: 000000000000000000000000000000000000

 9331 13:58:35.979387  Manufacturer-specified data, tag 0

 9332 13:58:35.983179  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9333 13:58:35.985905  ASCII string: InfoVision

 9334 13:58:35.989642  Hex of detail: 000000fe00523134304e574635205248200a

 9335 13:58:35.992765  ASCII string: R140NWF5 RH 

 9336 13:58:35.992868  Checksum

 9337 13:58:35.996120  Checksum: 0xfb (valid)

 9338 13:58:35.999231  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9339 13:58:36.002478  DSI data_rate: 832800000 bps

 9340 13:58:36.009174  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9341 13:58:36.012583  anx7625_parse_edid: pixelclock(138800).

 9342 13:58:36.016352   hactive(1920), hsync(48), hfp(24), hbp(88)

 9343 13:58:36.019252   vactive(1080), vsync(12), vfp(3), vbp(17)

 9344 13:58:36.022496  anx7625_dsi_config: config dsi.

 9345 13:58:36.029195  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9346 13:58:36.042033  anx7625_dsi_config: success to config DSI

 9347 13:58:36.045308  anx7625_dp_start: MIPI phy setup OK.

 9348 13:58:36.048705  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9349 13:58:36.051771  mtk_ddp_mode_set invalid vrefresh 60

 9350 13:58:36.055483  main_disp_path_setup

 9351 13:58:36.055560  ovl_layer_smi_id_en

 9352 13:58:36.058599  ovl_layer_smi_id_en

 9353 13:58:36.058677  ccorr_config

 9354 13:58:36.058744  aal_config

 9355 13:58:36.062012  gamma_config

 9356 13:58:36.062106  postmask_config

 9357 13:58:36.065380  dither_config

 9358 13:58:36.068997  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9359 13:58:36.075694                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9360 13:58:36.078969  Root Device init finished in 530 msecs

 9361 13:58:36.081989  CPU_CLUSTER: 0 init

 9362 13:58:36.088882  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9363 13:58:36.092423  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9364 13:58:36.095261  APU_MBOX 0x190000b0 = 0x10001

 9365 13:58:36.098497  APU_MBOX 0x190001b0 = 0x10001

 9366 13:58:36.102391  APU_MBOX 0x190005b0 = 0x10001

 9367 13:58:36.105145  APU_MBOX 0x190006b0 = 0x10001

 9368 13:58:36.108685  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9369 13:58:36.121123  read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps

 9370 13:58:36.133929  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9371 13:58:36.140134  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9372 13:58:36.151897  read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps

 9373 13:58:36.161031  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9374 13:58:36.164347  CPU_CLUSTER: 0 init finished in 81 msecs

 9375 13:58:36.167673  Devices initialized

 9376 13:58:36.171136  Show all devs... After init.

 9377 13:58:36.171251  Root Device: enabled 1

 9378 13:58:36.174374  CPU_CLUSTER: 0: enabled 1

 9379 13:58:36.177441  CPU: 00: enabled 1

 9380 13:58:36.181354  BS: BS_DEV_INIT run times (exec / console): 207 / 428 ms

 9381 13:58:36.184088  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9382 13:58:36.187680  ELOG: NV offset 0x57f000 size 0x1000

 9383 13:58:36.194561  read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps

 9384 13:58:36.201024  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9385 13:58:36.204009  ELOG: Event(17) added with size 13 at 2023-08-28 13:58:40 UTC

 9386 13:58:36.207817  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9387 13:58:36.211278  in-header: 03 71 00 00 2c 00 00 00 

 9388 13:58:36.224726  in-data: ee 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9389 13:58:36.231215  ELOG: Event(A1) added with size 10 at 2023-08-28 13:58:40 UTC

 9390 13:58:36.237870  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9391 13:58:36.244889  ELOG: Event(A0) added with size 9 at 2023-08-28 13:58:40 UTC

 9392 13:58:36.248123  elog_add_boot_reason: Logged dev mode boot

 9393 13:58:36.250954  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9394 13:58:36.254395  Finalize devices...

 9395 13:58:36.254505  Devices finalized

 9396 13:58:36.261119  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9397 13:58:36.264819  Writing coreboot table at 0xffe64000

 9398 13:58:36.267822   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9399 13:58:36.270915   1. 0000000040000000-00000000400fffff: RAM

 9400 13:58:36.277745   2. 0000000040100000-000000004032afff: RAMSTAGE

 9401 13:58:36.281142   3. 000000004032b000-00000000545fffff: RAM

 9402 13:58:36.284295   4. 0000000054600000-000000005465ffff: BL31

 9403 13:58:36.287307   5. 0000000054660000-00000000ffe63fff: RAM

 9404 13:58:36.294544   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9405 13:58:36.297351   7. 0000000100000000-000000023fffffff: RAM

 9406 13:58:36.297451  Passing 5 GPIOs to payload:

 9407 13:58:36.304545              NAME |       PORT | POLARITY |     VALUE

 9408 13:58:36.307670          EC in RW | 0x000000aa |      low | undefined

 9409 13:58:36.314405      EC interrupt | 0x00000005 |      low | undefined

 9410 13:58:36.317642     TPM interrupt | 0x000000ab |     high | undefined

 9411 13:58:36.320620    SD card detect | 0x00000011 |     high | undefined

 9412 13:58:36.327518    speaker enable | 0x00000093 |     high | undefined

 9413 13:58:36.330467  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9414 13:58:36.333754  in-header: 03 f9 00 00 02 00 00 00 

 9415 13:58:36.337300  in-data: 02 00 

 9416 13:58:36.337402  ADC[4]: Raw value=894821 ID=7

 9417 13:58:36.340384  ADC[3]: Raw value=212700 ID=1

 9418 13:58:36.343981  RAM Code: 0x71

 9419 13:58:36.344078  ADC[6]: Raw value=74722 ID=0

 9420 13:58:36.347686  ADC[5]: Raw value=212700 ID=1

 9421 13:58:36.350446  SKU Code: 0x1

 9422 13:58:36.354394  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2dff

 9423 13:58:36.357209  coreboot table: 964 bytes.

 9424 13:58:36.360335  IMD ROOT    0. 0xfffff000 0x00001000

 9425 13:58:36.363859  IMD SMALL   1. 0xffffe000 0x00001000

 9426 13:58:36.367400  RO MCACHE   2. 0xffffc000 0x00001104

 9427 13:58:36.370577  CONSOLE     3. 0xfff7c000 0x00080000

 9428 13:58:36.373795  FMAP        4. 0xfff7b000 0x00000452

 9429 13:58:36.377041  TIME STAMP  5. 0xfff7a000 0x00000910

 9430 13:58:36.380136  VBOOT WORK  6. 0xfff66000 0x00014000

 9431 13:58:36.383620  RAMOOPS     7. 0xffe66000 0x00100000

 9432 13:58:36.387207  COREBOOT    8. 0xffe64000 0x00002000

 9433 13:58:36.387298  IMD small region:

 9434 13:58:36.390388    IMD ROOT    0. 0xffffec00 0x00000400

 9435 13:58:36.393569    VPD         1. 0xffffeb80 0x0000006c

 9436 13:58:36.400404    MMC STATUS  2. 0xffffeb60 0x00000004

 9437 13:58:36.403778  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9438 13:58:36.406882  Probing TPM:  done!

 9439 13:58:36.410360  Connected to device vid:did:rid of 1ae0:0028:00

 9440 13:58:36.420588  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

 9441 13:58:36.424005  Initialized TPM device CR50 revision 0

 9442 13:58:36.427605  Checking cr50 for pending updates

 9443 13:58:36.431052  Reading cr50 TPM mode

 9444 13:58:36.440176  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9445 13:58:36.446782  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9446 13:58:36.486141  read SPI 0x3990ec 0x4f1b0: 34861 us, 9294 KB/s, 74.352 Mbps

 9447 13:58:36.489594  Checking segment from ROM address 0x40100000

 9448 13:58:36.493116  Checking segment from ROM address 0x4010001c

 9449 13:58:36.500239  Loading segment from ROM address 0x40100000

 9450 13:58:36.500356    code (compression=0)

 9451 13:58:36.509709    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9452 13:58:36.516490  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9453 13:58:36.516598  it's not compressed!

 9454 13:58:36.523362  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9455 13:58:36.526412  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9456 13:58:36.547227  Loading segment from ROM address 0x4010001c

 9457 13:58:36.547341    Entry Point 0x80000000

 9458 13:58:36.550642  Loaded segments

 9459 13:58:36.553527  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9460 13:58:36.560139  Jumping to boot code at 0x80000000(0xffe64000)

 9461 13:58:36.566845  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9462 13:58:36.573476  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9463 13:58:36.581238  read SPI 0x8eb68 0x74a8: 3225 us, 9260 KB/s, 74.080 Mbps

 9464 13:58:36.584358  Checking segment from ROM address 0x40100000

 9465 13:58:36.588147  Checking segment from ROM address 0x4010001c

 9466 13:58:36.594433  Loading segment from ROM address 0x40100000

 9467 13:58:36.594513    code (compression=1)

 9468 13:58:36.601037    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9469 13:58:36.611342  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9470 13:58:36.611450  using LZMA

 9471 13:58:36.619851  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9472 13:58:36.626232  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9473 13:58:36.629892  Loading segment from ROM address 0x4010001c

 9474 13:58:36.629993    Entry Point 0x54601000

 9475 13:58:36.633145  Loaded segments

 9476 13:58:36.635984  NOTICE:  MT8192 bl31_setup

 9477 13:58:36.643675  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9478 13:58:36.646499  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9479 13:58:36.649884  WARNING: region 0:

 9480 13:58:36.653508  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9481 13:58:36.653590  WARNING: region 1:

 9482 13:58:36.660001  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9483 13:58:36.663382  WARNING: region 2:

 9484 13:58:36.667041  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9485 13:58:36.669879  WARNING: region 3:

 9486 13:58:36.673469  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9487 13:58:36.676989  WARNING: region 4:

 9488 13:58:36.683780  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9489 13:58:36.683862  WARNING: region 5:

 9490 13:58:36.686774  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9491 13:58:36.690229  WARNING: region 6:

 9492 13:58:36.693217  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9493 13:58:36.693299  WARNING: region 7:

 9494 13:58:36.700450  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9495 13:58:36.706958  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9496 13:58:36.709902  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9497 13:58:36.713264  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9498 13:58:36.719877  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9499 13:58:36.723455  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9500 13:58:36.726782  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9501 13:58:36.733226  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9502 13:58:36.736426  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9503 13:58:36.743687  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9504 13:58:36.746895  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9505 13:58:36.750248  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9506 13:58:36.757141  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9507 13:58:36.760247  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9508 13:58:36.763628  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9509 13:58:36.769977  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9510 13:58:36.773710  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9511 13:58:36.776926  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9512 13:58:36.783323  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9513 13:58:36.787230  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9514 13:58:36.790014  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9515 13:58:36.796734  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9516 13:58:36.800708  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9517 13:58:36.806661  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9518 13:58:36.810038  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9519 13:58:36.817218  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9520 13:58:36.820012  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9521 13:58:36.823207  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9522 13:58:36.830322  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9523 13:58:36.833845  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9524 13:58:36.836815  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9525 13:58:36.843565  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9526 13:58:36.846967  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9527 13:58:36.850425  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9528 13:58:36.857155  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9529 13:58:36.860358  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9530 13:58:36.863800  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9531 13:58:36.867145  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9532 13:58:36.873353  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9533 13:58:36.876812  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9534 13:58:36.880382  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9535 13:58:36.883272  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9536 13:58:36.889956  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9537 13:58:36.893552  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9538 13:58:36.897107  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9539 13:58:36.900257  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9540 13:58:36.906666  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9541 13:58:36.910042  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9542 13:58:36.913668  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9543 13:58:36.920208  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9544 13:58:36.923232  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9545 13:58:36.930512  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9546 13:58:36.933657  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9547 13:58:36.936903  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9548 13:58:36.943476  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9549 13:58:36.946753  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9550 13:58:36.953631  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9551 13:58:36.957324  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9552 13:58:36.960383  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9553 13:58:36.966817  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9554 13:58:36.969984  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9555 13:58:36.977220  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9556 13:58:36.980159  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9557 13:58:36.986551  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9558 13:58:36.990239  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9559 13:58:36.996790  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9560 13:58:36.999744  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9561 13:58:37.003333  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9562 13:58:37.009869  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9563 13:58:37.013382  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9564 13:58:37.019933  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9565 13:58:37.023339  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9566 13:58:37.030237  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9567 13:58:37.033271  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9568 13:58:37.036731  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9569 13:58:37.043186  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9570 13:58:37.046855  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9571 13:58:37.053284  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9572 13:58:37.056464  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9573 13:58:37.063232  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9574 13:58:37.066640  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9575 13:58:37.073165  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9576 13:58:37.076548  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9577 13:58:37.079756  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9578 13:58:37.086690  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9579 13:58:37.090049  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9580 13:58:37.096394  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9581 13:58:37.099953  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9582 13:58:37.103099  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9583 13:58:37.110185  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9584 13:58:37.113155  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9585 13:58:37.119664  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9586 13:58:37.123120  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9587 13:58:37.129609  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9588 13:58:37.133102  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9589 13:58:37.139754  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9590 13:58:37.143409  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9591 13:58:37.146779  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9592 13:58:37.153180  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9593 13:58:37.157012  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9594 13:58:37.159724  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9595 13:58:37.162902  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9596 13:58:37.169892  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9597 13:58:37.173365  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9598 13:58:37.180233  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9599 13:58:37.183453  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9600 13:58:37.186470  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9601 13:58:37.193212  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9602 13:58:37.196425  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9603 13:58:37.203621  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9604 13:58:37.206723  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9605 13:58:37.209581  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9606 13:58:37.216216  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9607 13:58:37.219929  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9608 13:58:37.226266  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9609 13:58:37.229838  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9610 13:58:37.233036  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9611 13:58:37.236308  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9612 13:58:37.243467  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9613 13:58:37.246508  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9614 13:58:37.249784  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9615 13:58:37.256256  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9616 13:58:37.259556  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9617 13:58:37.262873  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9618 13:58:37.266535  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9619 13:58:37.273052  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9620 13:58:37.276369  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9621 13:58:37.279989  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9622 13:58:37.286696  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9623 13:58:37.289592  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9624 13:58:37.296389  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9625 13:58:37.299517  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9626 13:58:37.303138  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9627 13:58:37.309804  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9628 13:58:37.312875  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9629 13:58:37.319801  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9630 13:58:37.322858  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9631 13:58:37.326237  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9632 13:58:37.332820  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9633 13:58:37.336412  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9634 13:58:37.343184  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9635 13:58:37.346677  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9636 13:58:37.349807  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9637 13:58:37.356753  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9638 13:58:37.359631  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9639 13:58:37.363407  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9640 13:58:37.369831  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9641 13:58:37.373118  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9642 13:58:37.380253  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9643 13:58:37.383696  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9644 13:58:37.386585  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9645 13:58:37.392955  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9646 13:58:37.396685  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9647 13:58:37.399872  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9648 13:58:37.406237  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9649 13:58:37.409681  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9650 13:58:37.416618  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9651 13:58:37.419670  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9652 13:58:37.422889  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9653 13:58:37.429531  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9654 13:58:37.433032  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9655 13:58:37.439539  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9656 13:58:37.443124  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9657 13:58:37.446176  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9658 13:58:37.452676  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9659 13:58:37.456213  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9660 13:58:37.462352  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9661 13:58:37.465572  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9662 13:58:37.468974  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9663 13:58:37.475777  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9664 13:58:37.478796  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9665 13:58:37.485680  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9666 13:58:37.489075  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9667 13:58:37.492459  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9668 13:58:37.499020  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9669 13:58:37.502426  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9670 13:58:37.509047  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9671 13:58:37.512979  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9672 13:58:37.515703  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9673 13:58:37.522327  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9674 13:58:37.525525  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9675 13:58:37.528920  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9676 13:58:37.535579  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9677 13:58:37.539165  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9678 13:58:37.545924  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9679 13:58:37.548699  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9680 13:58:37.552284  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9681 13:58:37.559011  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9682 13:58:37.561859  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9683 13:58:37.568994  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9684 13:58:37.571947  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9685 13:58:37.578513  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9686 13:58:37.581852  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9687 13:58:37.585451  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9688 13:58:37.591782  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9689 13:58:37.594953  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9690 13:58:37.602052  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9691 13:58:37.605280  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9692 13:58:37.611639  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9693 13:58:37.615093  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9694 13:58:37.618434  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9695 13:58:37.624795  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9696 13:58:37.627764  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9697 13:58:37.634953  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9698 13:58:37.638130  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9699 13:58:37.644634  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9700 13:58:37.647776  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9701 13:58:37.651441  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9702 13:58:37.658120  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9703 13:58:37.661481  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9704 13:58:37.667976  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9705 13:58:37.671202  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9706 13:58:37.674974  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9707 13:58:37.681171  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9708 13:58:37.684875  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9709 13:58:37.691221  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9710 13:58:37.694527  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9711 13:58:37.697804  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9712 13:58:37.704683  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9713 13:58:37.708230  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9714 13:58:37.714482  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9715 13:58:37.717766  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9716 13:58:37.724557  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9717 13:58:37.728119  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9718 13:58:37.730957  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9719 13:58:37.737371  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9720 13:58:37.740700  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9721 13:58:37.747494  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9722 13:58:37.750950  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9723 13:58:37.753933  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9724 13:58:37.761174  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9725 13:58:37.764149  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9726 13:58:37.767575  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9727 13:58:37.770620  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9728 13:58:37.777565  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9729 13:58:37.780701  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9730 13:58:37.784230  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9731 13:58:37.790471  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9732 13:58:37.793816  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9733 13:58:37.797352  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9734 13:58:37.803818  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9735 13:58:37.807292  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9736 13:58:37.813970  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9737 13:58:37.817288  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9738 13:58:37.820563  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9739 13:58:37.827251  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9740 13:58:37.830755  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9741 13:58:37.833716  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9742 13:58:37.840741  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9743 13:58:37.843626  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9744 13:58:37.847534  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9745 13:58:37.853747  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9746 13:58:37.857137  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9747 13:58:37.863912  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9748 13:58:37.866965  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9749 13:58:37.870592  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9750 13:58:37.876925  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9751 13:58:37.880700  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9752 13:58:37.886678  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9753 13:58:37.890157  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9754 13:58:37.893182  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9755 13:58:37.900066  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9756 13:58:37.903436  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9757 13:58:37.906619  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9758 13:58:37.913365  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9759 13:58:37.916905  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9760 13:58:37.920256  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9761 13:58:37.926582  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9762 13:58:37.929926  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9763 13:58:37.932995  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9764 13:58:37.939657  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9765 13:58:37.943109  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9766 13:58:37.946275  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9767 13:58:37.949464  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9768 13:58:37.952711  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9769 13:58:37.959712  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9770 13:58:37.963302  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9771 13:58:37.966079  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9772 13:58:37.973240  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9773 13:58:37.976105  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9774 13:58:37.979572  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9775 13:58:37.982587  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9776 13:58:37.989374  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9777 13:58:37.992802  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9778 13:58:37.999237  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9779 13:58:38.002642  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9780 13:58:38.006137  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9781 13:58:38.012713  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9782 13:58:38.016186  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9783 13:58:38.022566  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9784 13:58:38.025996  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9785 13:58:38.029265  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9786 13:58:38.035775  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9787 13:58:38.038992  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9788 13:58:38.045932  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9789 13:58:38.048860  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9790 13:58:38.055655  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9791 13:58:38.058691  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9792 13:58:38.062521  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9793 13:58:38.068600  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9794 13:58:38.071938  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9795 13:58:38.078825  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9796 13:58:38.081890  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9797 13:58:38.085445  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9798 13:58:38.091948  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9799 13:58:38.095529  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9800 13:58:38.102206  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9801 13:58:38.105538  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9802 13:58:38.108759  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9803 13:58:38.115160  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9804 13:58:38.118656  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9805 13:58:38.124958  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9806 13:58:38.128285  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9807 13:58:38.134964  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9808 13:58:38.138830  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9809 13:58:38.142118  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9810 13:58:38.148500  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9811 13:58:38.152085  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9812 13:58:38.158745  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9813 13:58:38.161773  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9814 13:58:38.164894  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9815 13:58:38.171846  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9816 13:58:38.175053  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9817 13:58:38.182137  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9818 13:58:38.185057  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9819 13:58:38.188161  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9820 13:58:38.194781  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9821 13:58:38.198513  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9822 13:58:38.205019  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9823 13:58:38.208439  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9824 13:58:38.211349  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9825 13:58:38.218235  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9826 13:58:38.221211  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9827 13:58:38.228183  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9828 13:58:38.231249  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9829 13:58:38.237850  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9830 13:58:38.241054  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9831 13:58:38.244984  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9832 13:58:38.251155  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9833 13:58:38.254839  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9834 13:58:38.261090  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9835 13:58:38.264565  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9836 13:58:38.268126  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9837 13:58:38.274503  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9838 13:58:38.277785  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9839 13:58:38.284294  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9840 13:58:38.287692  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9841 13:58:38.291312  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9842 13:58:38.297734  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9843 13:58:38.301362  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9844 13:58:38.308093  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9845 13:58:38.310943  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9846 13:58:38.314647  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9847 13:58:38.321782  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9848 13:58:38.324332  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9849 13:58:38.331544  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9850 13:58:38.334570  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9851 13:58:38.340911  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9852 13:58:38.345087  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9853 13:58:38.347656  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9854 13:58:38.354441  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9855 13:58:38.358169  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9856 13:58:38.364440  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9857 13:58:38.367539  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9858 13:58:38.374247  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9859 13:58:38.377699  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9860 13:58:38.380797  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9861 13:58:38.387391  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9862 13:58:38.390930  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9863 13:58:38.397523  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9864 13:58:38.400801  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9865 13:58:38.407558  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9866 13:58:38.411059  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9867 13:58:38.417440  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9868 13:58:38.420378  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9869 13:58:38.423987  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9870 13:58:38.430768  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9871 13:58:38.433902  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9872 13:58:38.440287  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9873 13:58:38.443330  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9874 13:58:38.450482  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9875 13:58:38.453345  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9876 13:58:38.460256  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9877 13:58:38.463606  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9878 13:58:38.466613  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9879 13:58:38.473482  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9880 13:58:38.476963  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9881 13:58:38.483026  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9882 13:58:38.486569  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9883 13:58:38.493176  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9884 13:58:38.496725  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9885 13:58:38.499957  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9886 13:58:38.506705  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9887 13:58:38.509791  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9888 13:58:38.516680  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9889 13:58:38.519803  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9890 13:58:38.526827  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9891 13:58:38.530415  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9892 13:58:38.532944  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9893 13:58:38.539573  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9894 13:58:38.543151  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9895 13:58:38.549472  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9896 13:58:38.553013  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9897 13:58:38.559657  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9898 13:58:38.563135  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9899 13:58:38.566483  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9900 13:58:38.573127  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9901 13:58:38.576649  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9902 13:58:38.582796  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9903 13:58:38.586329  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9904 13:58:38.592592  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9905 13:58:38.595790  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9906 13:58:38.602470  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9907 13:58:38.606105  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9908 13:58:38.612889  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9909 13:58:38.616340  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9910 13:58:38.622861  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9911 13:58:38.625790  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9912 13:58:38.632405  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9913 13:58:38.635784  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9914 13:58:38.642408  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9915 13:58:38.645621  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9916 13:58:38.652065  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9917 13:58:38.655669  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9918 13:58:38.662577  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9919 13:58:38.665394  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9920 13:58:38.672079  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9921 13:58:38.675537  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9922 13:58:38.682025  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9923 13:58:38.685450  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9924 13:58:38.692344  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9925 13:58:38.695588  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9926 13:58:38.702090  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9927 13:58:38.705210  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9928 13:58:38.711731  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9929 13:58:38.715160  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9930 13:58:38.718543  INFO:    [APUAPC] vio 0

 9931 13:58:38.722170  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9932 13:58:38.728705  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9933 13:58:38.731647  INFO:    [APUAPC] D0_APC_0: 0x400510

 9934 13:58:38.731730  INFO:    [APUAPC] D0_APC_1: 0x0

 9935 13:58:38.735198  INFO:    [APUAPC] D0_APC_2: 0x1540

 9936 13:58:38.738401  INFO:    [APUAPC] D0_APC_3: 0x0

 9937 13:58:38.741882  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9938 13:58:38.744972  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9939 13:58:38.748593  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9940 13:58:38.751907  INFO:    [APUAPC] D1_APC_3: 0x0

 9941 13:58:38.754732  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9942 13:58:38.758193  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9943 13:58:38.761553  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9944 13:58:38.764887  INFO:    [APUAPC] D2_APC_3: 0x0

 9945 13:58:38.768307  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9946 13:58:38.771886  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9947 13:58:38.774719  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9948 13:58:38.778774  INFO:    [APUAPC] D3_APC_3: 0x0

 9949 13:58:38.781525  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9950 13:58:38.784999  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9951 13:58:38.787955  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9952 13:58:38.791350  INFO:    [APUAPC] D4_APC_3: 0x0

 9953 13:58:38.794783  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9954 13:58:38.798351  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9955 13:58:38.801759  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9956 13:58:38.804640  INFO:    [APUAPC] D5_APC_3: 0x0

 9957 13:58:38.808447  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9958 13:58:38.811519  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9959 13:58:38.814634  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9960 13:58:38.818059  INFO:    [APUAPC] D6_APC_3: 0x0

 9961 13:58:38.821163  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9962 13:58:38.824710  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9963 13:58:38.828290  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9964 13:58:38.831290  INFO:    [APUAPC] D7_APC_3: 0x0

 9965 13:58:38.834731  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9966 13:58:38.837891  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9967 13:58:38.841425  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9968 13:58:38.844830  INFO:    [APUAPC] D8_APC_3: 0x0

 9969 13:58:38.848351  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9970 13:58:38.851462  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9971 13:58:38.854535  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9972 13:58:38.854611  INFO:    [APUAPC] D9_APC_3: 0x0

 9973 13:58:38.861015  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9974 13:58:38.864610  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9975 13:58:38.867755  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9976 13:58:38.867866  INFO:    [APUAPC] D10_APC_3: 0x0

 9977 13:58:38.874730  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9978 13:58:38.877834  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9979 13:58:38.880966  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9980 13:58:38.884672  INFO:    [APUAPC] D11_APC_3: 0x0

 9981 13:58:38.887841  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9982 13:58:38.891535  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9983 13:58:38.894352  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9984 13:58:38.897318  INFO:    [APUAPC] D12_APC_3: 0x0

 9985 13:58:38.900935  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9986 13:58:38.904239  INFO:    [APUAPC] D13_APC_1: 0xffffffff

 9987 13:58:38.907634  INFO:    [APUAPC] D13_APC_2: 0x3fffff

 9988 13:58:38.910556  INFO:    [APUAPC] D13_APC_3: 0x0

 9989 13:58:38.914359  INFO:    [APUAPC] D14_APC_0: 0xffffffff

 9990 13:58:38.917189  INFO:    [APUAPC] D14_APC_1: 0xffffffff

 9991 13:58:38.920981  INFO:    [APUAPC] D14_APC_2: 0x3fffff

 9992 13:58:38.924131  INFO:    [APUAPC] D14_APC_3: 0x0

 9993 13:58:38.927607  INFO:    [APUAPC] D15_APC_0: 0xffffffff

 9994 13:58:38.930583  INFO:    [APUAPC] D15_APC_1: 0xffffffff

 9995 13:58:38.934247  INFO:    [APUAPC] D15_APC_2: 0x3fffff

 9996 13:58:38.937688  INFO:    [APUAPC] D15_APC_3: 0x0

 9997 13:58:38.940525  INFO:    [APUAPC] APC_CON: 0x4

 9998 13:58:38.940608  INFO:    [NOCDAPC] D0_APC_0: 0x0

 9999 13:58:38.944088  INFO:    [NOCDAPC] D0_APC_1: 0x0

10000 13:58:38.947634  INFO:    [NOCDAPC] D1_APC_0: 0x0

10001 13:58:38.950501  INFO:    [NOCDAPC] D1_APC_1: 0xfff

10002 13:58:38.953873  INFO:    [NOCDAPC] D2_APC_0: 0x0

10003 13:58:38.957444  INFO:    [NOCDAPC] D2_APC_1: 0xfff

10004 13:58:38.960763  INFO:    [NOCDAPC] D3_APC_0: 0x0

10005 13:58:38.963710  INFO:    [NOCDAPC] D3_APC_1: 0xfff

10006 13:58:38.967298  INFO:    [NOCDAPC] D4_APC_0: 0x0

10007 13:58:38.970310  INFO:    [NOCDAPC] D4_APC_1: 0xfff

10008 13:58:38.970392  INFO:    [NOCDAPC] D5_APC_0: 0x0

10009 13:58:38.974191  INFO:    [NOCDAPC] D5_APC_1: 0xfff

10010 13:58:38.976915  INFO:    [NOCDAPC] D6_APC_0: 0x0

10011 13:58:38.980600  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10012 13:58:38.983603  INFO:    [NOCDAPC] D7_APC_0: 0x0

10013 13:58:38.986962  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10014 13:58:38.990639  INFO:    [NOCDAPC] D8_APC_0: 0x0

10015 13:58:38.993641  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10016 13:58:38.997207  INFO:    [NOCDAPC] D9_APC_0: 0x0

10017 13:58:39.000199  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10018 13:58:39.003606  INFO:    [NOCDAPC] D10_APC_0: 0x0

10019 13:58:39.007339  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10020 13:58:39.007421  INFO:    [NOCDAPC] D11_APC_0: 0x0

10021 13:58:39.010689  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10022 13:58:39.013430  INFO:    [NOCDAPC] D12_APC_0: 0x0

10023 13:58:39.016906  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10024 13:58:39.019922  INFO:    [NOCDAPC] D13_APC_0: 0x0

10025 13:58:39.023607  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10026 13:58:39.026646  INFO:    [NOCDAPC] D14_APC_0: 0x0

10027 13:58:39.029767  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10028 13:58:39.033531  INFO:    [NOCDAPC] D15_APC_0: 0x0

10029 13:58:39.036947  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10030 13:58:39.039868  INFO:    [NOCDAPC] APC_CON: 0x4

10031 13:58:39.043507  INFO:    [APUAPC] set_apusys_apc done

10032 13:58:39.046327  INFO:    [DEVAPC] devapc_init done

10033 13:58:39.049896  INFO:    GICv3 without legacy support detected.

10034 13:58:39.053067  INFO:    ARM GICv3 driver initialized in EL3

10035 13:58:39.056668  INFO:    Maximum SPI INTID supported: 639

10036 13:58:39.063136  INFO:    BL31: Initializing runtime services

10037 13:58:39.066451  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10038 13:58:39.069568  INFO:    SPM: enable CPC mode

10039 13:58:39.076521  INFO:    mcdi ready for mcusys-off-idle and system suspend

10040 13:58:39.080164  INFO:    BL31: Preparing for EL3 exit to normal world

10041 13:58:39.083364  INFO:    Entry point address = 0x80000000

10042 13:58:39.086224  INFO:    SPSR = 0x8

10043 13:58:39.091316  

10044 13:58:39.091442  

10045 13:58:39.091534  

10046 13:58:39.092242  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10047 13:58:39.092378  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10048 13:58:39.092488  Setting prompt string to ['asurada:']
10049 13:58:39.092633  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10050 13:58:39.094614  Starting depthcharge on Spherion...

10051 13:58:39.094688  

10052 13:58:39.094750  Wipe memory regions:

10053 13:58:39.094809  

10054 13:58:39.098358  	[0x00000040000000, 0x00000054600000)

10055 13:58:39.220090  

10056 13:58:39.220259  	[0x00000054660000, 0x00000080000000)

10057 13:58:39.480712  

10058 13:58:39.480866  	[0x000000821a7280, 0x000000ffe64000)

10059 13:58:40.225979  

10060 13:58:40.226119  	[0x00000100000000, 0x00000240000000)

10061 13:58:42.115944  

10062 13:58:42.119709  Initializing XHCI USB controller at 0x11200000.

10063 13:58:43.157071  

10064 13:58:43.160362  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10065 13:58:43.160453  

10066 13:58:43.160556  

10067 13:58:43.160618  

10068 13:58:43.160896  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 13:58:43.261229  asurada: tftpboot 192.168.201.1 11372182/tftp-deploy-cl_h_2zg/kernel/image.itb 11372182/tftp-deploy-cl_h_2zg/kernel/cmdline 

10071 13:58:43.261383  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 13:58:43.261492  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10073 13:58:43.265866  tftpboot 192.168.201.1 11372182/tftp-deploy-cl_h_2zg/kernel/image.itp-deploy-cl_h_2zg/kernel/cmdline 

10074 13:58:43.265952  

10075 13:58:43.266019  Waiting for link

10076 13:58:43.426231  

10077 13:58:43.426367  R8152: Initializing

10078 13:58:43.426435  

10079 13:58:43.429351  Version 6 (ocp_data = 5c30)

10080 13:58:43.429426  

10081 13:58:43.432956  R8152: Done initializing

10082 13:58:43.433038  

10083 13:58:43.433104  Adding net device

10084 13:58:45.336518  

10085 13:58:45.336658  done.

10086 13:58:45.336726  

10087 13:58:45.336788  MAC: 00:24:32:30:78:ff

10088 13:58:45.336847  

10089 13:58:45.339543  Sending DHCP discover... done.

10090 13:58:45.339627  

10091 13:58:45.343034  Waiting for reply... done.

10092 13:58:45.343117  

10093 13:58:45.346293  Sending DHCP request... done.

10094 13:58:45.346381  

10095 13:58:45.350828  Waiting for reply... done.

10096 13:58:45.350910  

10097 13:58:45.350976  My ip is 192.168.201.21

10098 13:58:45.351038  

10099 13:58:45.353766  The DHCP server ip is 192.168.201.1

10100 13:58:45.353848  

10101 13:58:45.360654  TFTP server IP predefined by user: 192.168.201.1

10102 13:58:45.360737  

10103 13:58:45.367335  Bootfile predefined by user: 11372182/tftp-deploy-cl_h_2zg/kernel/image.itb

10104 13:58:45.367468  

10105 13:58:45.367534  Sending tftp read request... done.

10106 13:58:45.370450  

10107 13:58:45.374730  Waiting for the transfer... 

10108 13:58:45.374820  

10109 13:58:45.962973  00000000 ################################################################

10110 13:58:45.963120  

10111 13:58:46.535611  00080000 ################################################################

10112 13:58:46.535763  

10113 13:58:47.107322  00100000 ################################################################

10114 13:58:47.107497  

10115 13:58:47.690607  00180000 ################################################################

10116 13:58:47.690749  

10117 13:58:48.274790  00200000 ################################################################

10118 13:58:48.274940  

10119 13:58:48.834606  00280000 ################################################################

10120 13:58:48.834749  

10121 13:58:49.418611  00300000 ################################################################

10122 13:58:49.418795  

10123 13:58:49.988809  00380000 ################################################################

10124 13:58:49.988995  

10125 13:58:50.567735  00400000 ################################################################

10126 13:58:50.567889  

10127 13:58:51.138075  00480000 ################################################################

10128 13:58:51.138218  

10129 13:58:51.711012  00500000 ################################################################

10130 13:58:51.711172  

10131 13:58:52.281109  00580000 ################################################################

10132 13:58:52.281261  

10133 13:58:52.856564  00600000 ################################################################

10134 13:58:52.856717  

10135 13:58:53.418292  00680000 ################################################################

10136 13:58:53.418433  

10137 13:58:54.022930  00700000 ################################################################

10138 13:58:54.023556  

10139 13:58:54.721441  00780000 ################################################################

10140 13:58:54.722052  

10141 13:58:55.423896  00800000 ################################################################

10142 13:58:55.424466  

10143 13:58:56.055435  00880000 ################################################################

10144 13:58:56.055572  

10145 13:58:56.614717  00900000 ################################################################

10146 13:58:56.614872  

10147 13:58:57.193812  00980000 ################################################################

10148 13:58:57.194362  

10149 13:58:57.917152  00a00000 ################################################################

10150 13:58:57.917724  

10151 13:58:58.557144  00a80000 ################################################################

10152 13:58:58.557310  

10153 13:58:59.177431  00b00000 ################################################################

10154 13:58:59.177571  

10155 13:58:59.800122  00b80000 ################################################################

10156 13:58:59.800768  

10157 13:59:00.510826  00c00000 ################################################################

10158 13:59:00.511444  

10159 13:59:01.220892  00c80000 ################################################################

10160 13:59:01.221463  

10161 13:59:01.825454  00d00000 ################################################################

10162 13:59:01.825593  

10163 13:59:02.449580  00d80000 ################################################################

10164 13:59:02.449714  

10165 13:59:03.025270  00e00000 ################################################################

10166 13:59:03.025972  

10167 13:59:03.727423  00e80000 ################################################################

10168 13:59:03.728060  

10169 13:59:04.433286  00f00000 ################################################################

10170 13:59:04.433957  

10171 13:59:05.111873  00f80000 ################################################################

10172 13:59:05.112428  

10173 13:59:05.803889  01000000 ################################################################

10174 13:59:05.804484  

10175 13:59:06.524468  01080000 ################################################################

10176 13:59:06.525072  

10177 13:59:07.258428  01100000 ################################################################

10178 13:59:07.258800  

10179 13:59:07.987443  01180000 ################################################################

10180 13:59:07.988014  

10181 13:59:08.718020  01200000 ################################################################

10182 13:59:08.718613  

10183 13:59:09.462857  01280000 ################################################################

10184 13:59:09.463459  

10185 13:59:10.201412  01300000 ################################################################

10186 13:59:10.201937  

10187 13:59:10.914943  01380000 ################################################################

10188 13:59:10.915517  

10189 13:59:11.606691  01400000 ################################################################

10190 13:59:11.607309  

10191 13:59:12.301536  01480000 ################################################################

10192 13:59:12.302194  

10193 13:59:12.965277  01500000 ################################################################

10194 13:59:12.965814  

10195 13:59:13.666551  01580000 ################################################################

10196 13:59:13.667097  

10197 13:59:14.360416  01600000 ################################################################

10198 13:59:14.360952  

10199 13:59:15.060364  01680000 ################################################################

10200 13:59:15.061037  

10201 13:59:15.691881  01700000 ################################################################

10202 13:59:15.692018  

10203 13:59:16.296746  01780000 ################################################################

10204 13:59:16.297249  

10205 13:59:16.899037  01800000 ################################################################

10206 13:59:16.899173  

10207 13:59:17.467121  01880000 ################################################################

10208 13:59:17.467299  

10209 13:59:18.048505  01900000 ################################################################

10210 13:59:18.048640  

10211 13:59:18.698445  01980000 ################################################################

10212 13:59:18.698583  

10213 13:59:19.289074  01a00000 ################################################################

10214 13:59:19.289224  

10215 13:59:19.901932  01a80000 ################################################################

10216 13:59:19.902076  

10217 13:59:20.596196  01b00000 ################################################################

10218 13:59:20.596796  

10219 13:59:21.303132  01b80000 ################################################################

10220 13:59:21.303878  

10221 13:59:21.877196  01c00000 ################################################################

10222 13:59:21.877346  

10223 13:59:22.455587  01c80000 ################################################################

10224 13:59:22.455731  

10225 13:59:23.057304  01d00000 ################################################################

10226 13:59:23.057456  

10227 13:59:23.659625  01d80000 ################################################################

10228 13:59:23.659775  

10229 13:59:24.276513  01e00000 ################################################################

10230 13:59:24.276670  

10231 13:59:24.809370  01e80000 ########################################################### done.

10232 13:59:24.809517  

10233 13:59:24.812656  The bootfile was 32457830 bytes long.

10234 13:59:24.812731  

10235 13:59:24.815761  Sending tftp read request... done.

10236 13:59:24.815844  

10237 13:59:24.818975  Waiting for the transfer... 

10238 13:59:24.819058  

10239 13:59:24.819123  00000000 # done.

10240 13:59:24.819185  

10241 13:59:24.829354  Command line loaded dynamically from TFTP file: 11372182/tftp-deploy-cl_h_2zg/kernel/cmdline

10242 13:59:24.829441  

10243 13:59:24.842494  The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10244 13:59:24.842578  

10245 13:59:24.842643  Loading FIT.

10246 13:59:24.842702  

10247 13:59:24.846104  Image ramdisk-1 has 21368684 bytes.

10248 13:59:24.846186  

10249 13:59:24.849197  Image fdt-1 has 47278 bytes.

10250 13:59:24.849279  

10251 13:59:24.852216  Image kernel-1 has 11039834 bytes.

10252 13:59:24.852297  

10253 13:59:24.858909  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10254 13:59:24.862401  

10255 13:59:24.878846  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10256 13:59:24.878939  

10257 13:59:24.882060  Choosing best match conf-1 for compat google,spherion-rev2.

10258 13:59:24.887626  

10259 13:59:24.891861  Connected to device vid:did:rid of 1ae0:0028:00

10260 13:59:24.898800  

10261 13:59:24.902659  tpm_get_response: command 0x17b, return code 0x0

10262 13:59:24.902741  

10263 13:59:24.905866  ec_init: CrosEC protocol v3 supported (256, 248)

10264 13:59:24.909543  

10265 13:59:24.913069  tpm_cleanup: add release locality here.

10266 13:59:24.913150  

10267 13:59:24.913213  Shutting down all USB controllers.

10268 13:59:24.916287  

10269 13:59:24.916367  Removing current net device

10270 13:59:24.916430  

10271 13:59:24.922788  Exiting depthcharge with code 4 at timestamp: 75120460

10272 13:59:24.922869  

10273 13:59:24.926110  LZMA decompressing kernel-1 to 0x821a6718

10274 13:59:24.926191  

10275 13:59:24.929817  LZMA decompressing kernel-1 to 0x40000000

10276 13:59:26.317367  

10277 13:59:26.317924  jumping to kernel

10278 13:59:26.319422  end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10279 13:59:26.319959  start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10280 13:59:26.320367  Setting prompt string to ['Linux version [0-9]']
10281 13:59:26.320741  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10282 13:59:26.321126  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10283 13:59:26.398991  

10284 13:59:26.402684  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10285 13:59:26.406098  start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10286 13:59:26.406608  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10287 13:59:26.407003  Setting prompt string to []
10288 13:59:26.407486  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10289 13:59:26.407897  Using line separator: #'\n'#
10290 13:59:26.408230  No login prompt set.
10291 13:59:26.408569  Parsing kernel messages
10292 13:59:26.408880  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10293 13:59:26.409432  [login-action] Waiting for messages, (timeout 00:03:38)
10294 13:59:26.425367  [    0.000000] Linux version 6.1.46-cip4-rt2 (KernelCI@build-j25372-arm64-gcc-10-defconfig-arm64-chromebook-2wz78) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 28 13:41:26 UTC 2023

10295 13:59:26.428771  [    0.000000] random: crng init done

10296 13:59:26.435139  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10297 13:59:26.438713  [    0.000000] efi: UEFI not found.

10298 13:59:26.445321  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10299 13:59:26.455015  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10300 13:59:26.461808  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10301 13:59:26.472031  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10302 13:59:26.478281  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10303 13:59:26.484985  [    0.000000] printk: bootconsole [mtk8250] enabled

10304 13:59:26.491298  [    0.000000] NUMA: No NUMA configuration found

10305 13:59:26.498492  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10306 13:59:26.501833  [    0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]

10307 13:59:26.504860  [    0.000000] Zone ranges:

10308 13:59:26.511330  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10309 13:59:26.515205  [    0.000000]   DMA32    empty

10310 13:59:26.521405  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10311 13:59:26.524882  [    0.000000] Movable zone start for each node

10312 13:59:26.528250  [    0.000000] Early memory node ranges

10313 13:59:26.534771  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10314 13:59:26.541504  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10315 13:59:26.548022  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10316 13:59:26.554242  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10317 13:59:26.561103  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10318 13:59:26.567647  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10319 13:59:26.623652  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10320 13:59:26.629872  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10321 13:59:26.636386  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10322 13:59:26.639820  [    0.000000] psci: probing for conduit method from DT.

10323 13:59:26.646534  [    0.000000] psci: PSCIv1.1 detected in firmware.

10324 13:59:26.649919  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10325 13:59:26.656559  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10326 13:59:26.659674  [    0.000000] psci: SMC Calling Convention v1.2

10327 13:59:26.666106  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10328 13:59:26.669507  [    0.000000] Detected VIPT I-cache on CPU0

10329 13:59:26.676164  [    0.000000] CPU features: detected: GIC system register CPU interface

10330 13:59:26.682603  [    0.000000] CPU features: detected: Virtualization Host Extensions

10331 13:59:26.689268  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10332 13:59:26.695958  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10333 13:59:26.705705  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10334 13:59:26.712481  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10335 13:59:26.715905  [    0.000000] alternatives: applying boot alternatives

10336 13:59:26.722755  [    0.000000] Fallback order for Node 0: 0 

10337 13:59:26.729355  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10338 13:59:26.732359  [    0.000000] Policy zone: Normal

10339 13:59:26.745686  [    0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10340 13:59:26.755190  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10341 13:59:26.767836  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10342 13:59:26.777687  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10343 13:59:26.784623  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10344 13:59:26.787828  <6>[    0.000000] software IO TLB: area num 8.

10345 13:59:26.844679  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10346 13:59:26.993490  <6>[    0.000000] Memory: 7948624K/8385536K available (17984K kernel code, 4100K rwdata, 17468K rodata, 8384K init, 615K bss, 404144K reserved, 32768K cma-reserved)

10347 13:59:27.000657  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10348 13:59:27.006768  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10349 13:59:27.010327  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10350 13:59:27.016937  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10351 13:59:27.023732  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10352 13:59:27.027179  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10353 13:59:27.036638  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10354 13:59:27.043343  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10355 13:59:27.046574  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10356 13:59:27.054674  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10357 13:59:27.058147  <6>[    0.000000] GICv3: 608 SPIs implemented

10358 13:59:27.064487  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10359 13:59:27.067924  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10360 13:59:27.071016  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10361 13:59:27.081010  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10362 13:59:27.091099  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10363 13:59:27.103988  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10364 13:59:27.110638  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10365 13:59:27.120009  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10366 13:59:27.133515  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10367 13:59:27.140039  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10368 13:59:27.147012  <6>[    0.009185] Console: colour dummy device 80x25

10369 13:59:27.156467  <6>[    0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10370 13:59:27.162858  <6>[    0.024415] pid_max: default: 32768 minimum: 301

10371 13:59:27.166348  <6>[    0.029286] LSM: Security Framework initializing

10372 13:59:27.173069  <6>[    0.034225] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10373 13:59:27.182832  <6>[    0.042038] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10374 13:59:27.189833  <6>[    0.051466] cblist_init_generic: Setting adjustable number of callback queues.

10375 13:59:27.196152  <6>[    0.058913] cblist_init_generic: Setting shift to 3 and lim to 1.

10376 13:59:27.206553  <6>[    0.065251] cblist_init_generic: Setting adjustable number of callback queues.

10377 13:59:27.213183  <6>[    0.072676] cblist_init_generic: Setting shift to 3 and lim to 1.

10378 13:59:27.216515  <6>[    0.079153] rcu: Hierarchical SRCU implementation.

10379 13:59:27.222758  <6>[    0.079155] rcu: 	Max phase no-delay instances is 1000.

10380 13:59:27.229091  <6>[    0.079179] printk: bootconsole [mtk8250] printing thread started

10381 13:59:27.236511  <6>[    0.097507] EFI services will not be available.

10382 13:59:27.239281  <6>[    0.097703] smp: Bringing up secondary CPUs ...

10383 13:59:27.242628  <6>[    0.098006] Detected VIPT I-cache on CPU1

10384 13:59:27.252748  <6>[    0.098074] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10385 13:59:27.259339  <6>[    0.098105] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10386 13:59:27.268723  <6>[    0.125984] Detected VIPT I-cache on CPU2

10387 13:59:27.274964  <6>[    0.126034] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10388 13:59:27.284718  <6>[    0.126051] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10389 13:59:27.288000  <6>[    0.126311] Detected VIPT I-cache on CPU3

10390 13:59:27.294774  <6>[    0.126357] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10391 13:59:27.301311  <6>[    0.126371] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10392 13:59:27.304600  <6>[    0.126678] CPU features: detected: Spectre-v4

10393 13:59:27.310949  <6>[    0.126684] CPU features: detected: Spectre-BHB

10394 13:59:27.314649  <6>[    0.126690] Detected PIPT I-cache on CPU4

10395 13:59:27.320991  <6>[    0.126749] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10396 13:59:27.327813  <6>[    0.126765] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10397 13:59:27.334043  <6>[    0.127057] Detected PIPT I-cache on CPU5

10398 13:59:27.340696  <6>[    0.127119] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10399 13:59:27.347104  <6>[    0.127135] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10400 13:59:27.350760  <6>[    0.127412] Detected PIPT I-cache on CPU6

10401 13:59:27.360509  <6>[    0.127476] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10402 13:59:27.367134  <6>[    0.127492] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10403 13:59:27.370971  <6>[    0.127784] Detected PIPT I-cache on CPU7

10404 13:59:27.376887  <6>[    0.127848] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10405 13:59:27.384064  <6>[    0.127864] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10406 13:59:27.386788  <6>[    0.127910] smp: Brought up 1 node, 8 CPUs

10407 13:59:27.393499  <6>[    0.127914] SMP: Total of 8 processors activated.

10408 13:59:27.400401  <6>[    0.127917] CPU features: detected: 32-bit EL0 Support

10409 13:59:27.406539  <6>[    0.127919] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10410 13:59:27.413269  <6>[    0.127921] CPU features: detected: Common not Private translations

10411 13:59:27.419946  <6>[    0.127923] CPU features: detected: CRC32 instructions

10412 13:59:27.427118  <6>[    0.127926] CPU features: detected: RCpc load-acquire (LDAPR)

10413 13:59:27.429636  <6>[    0.127927] CPU features: detected: LSE atomic instructions

10414 13:59:27.436665  <6>[    0.127929] CPU features: detected: Privileged Access Never

10415 13:59:27.443277  <6>[    0.127930] CPU features: detected: RAS Extension Support

10416 13:59:27.449951  <6>[    0.127933] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10417 13:59:27.453201  <6>[    0.128001] CPU: All CPU(s) started at EL2

10418 13:59:27.475886  �ߍ�ͽ�ɍ��

10419 13:59:27.482556  ɍ�}���}��չѕ�5R�<6>[    0.34<4429] printk: console [ttyS0] printing thread started

10420 13:59:27.485737  5<6>[    0.344458] printk: console [ttyS0] enabled

10421 13:59:27.492962  >[    0.225448] VFS: Disk quotas dquot_6.6.0

10422 13:59:27.499007  <6>[    0.225476] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10423 13:59:27.502405  <6>[    0.225575] pnp: PnP ACPI: disabled

10424 13:59:27.505882  <6>[    0.228080] NET: Registered PF_INET protocol family

10425 13:59:27.515635  <6>[    0.228559] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10426 13:59:27.522937  <6>[    0.344464] printk: bootconsole [mtk8250] disabled

10427 13:59:27.529273  <6>[    0.382782] printk: bootconsole [mtk8250] printing thread stopped

10428 13:59:27.532809  <6>[    0.383774] SuperH (H)SCI(F) driver initialized

10429 13:59:27.539426  <6>[    0.384246] msm_serial: driver initialized

10430 13:59:27.545678  <6>[    0.388812] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10431 13:59:27.555852  <6>[    0.388841] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10432 13:59:27.562159  <6>[    0.388870] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10433 13:59:27.570866  <6>[    0.388899] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10434 13:59:27.586548  <6>[    0.388920] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10435 13:59:27.594585  <6>[    0.388947] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10436 13:59:27.611139  <6>[    0.388975] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10437 13:59:27.612178  <6>[    0.389084] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10438 13:59:27.619888  <6>[    0.389113] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10439 13:59:27.624006  <6>[    0.400438] loop: module loaded

10440 13:59:27.630297  <6>[    0.402982] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10441 13:59:27.633754  <4>[    0.419718] mtk-pmic-keys: Failed to locate of_node [id: -1]

10442 13:59:27.637447  <6>[    0.420501] megasas: 07.719.03.00-rc1

10443 13:59:27.640565  <6>[    0.432756] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10444 13:59:27.647479  <6>[    0.436708] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10445 13:59:27.653525  <6>[    0.448788] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10446 13:59:27.663468  <6>[    0.500644] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b

10447 13:59:28.266769  <6>[    1.127727] Freeing initrd memory: 20864K

10448 13:59:28.278655  <6>[    1.139211] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10449 13:59:28.285202  <6>[    1.143935] tun: Universal TUN/TAP device driver, 1.6

10450 13:59:28.288927  <6>[    1.144691] thunder_xcv, ver 1.0

10451 13:59:28.291683  <6>[    1.144708] thunder_bgx, ver 1.0

10452 13:59:28.295199  <6>[    1.144738] nicpf, ver 1.0

10453 13:59:28.301825  <6>[    1.145832] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10454 13:59:28.308835  <6>[    1.145835] hns3: Copyright (c) 2017 Huawei Corporation.

10455 13:59:28.311983  <6>[    1.145864] hclge is initializing

10456 13:59:28.315631  <6>[    1.145878] e1000: Intel(R) PRO/1000 Network Driver

10457 13:59:28.322342  <6>[    1.145881] e1000: Copyright (c) 1999-2006 Intel Corporation.

10458 13:59:28.329441  <6>[    1.145897] e1000e: Intel(R) PRO/1000 Network Driver

10459 13:59:28.333112  <6>[    1.145899] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10460 13:59:28.340378  <6>[    1.145915] igb: Intel(R) Gigabit Ethernet Network Driver

10461 13:59:28.346582  <6>[    1.145917] igb: Copyright (c) 2007-2014 Intel Corporation.

10462 13:59:28.353660  <6>[    1.145930] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10463 13:59:28.357806  <6>[    1.145932] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10464 13:59:28.361004  <6>[    1.146226] sky2: driver version 1.30

10465 13:59:28.367685  <6>[    1.147296] VFIO - User Level meta-driver version: 0.3

10466 13:59:28.374426  <6>[    1.150156] usbcore: registered new interface driver usb-storage

10467 13:59:28.381145  <6>[    1.150336] usbcore: registered new device driver onboard-usb-hub

10468 13:59:28.384485  <6>[    1.153061] mt6397-rtc mt6359-rtc: registered as rtc0

10469 13:59:28.394661  <6>[    1.153215] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-28T13:59:32 UTC (1693231172)

10470 13:59:28.397827  <6>[    1.153833] i2c_dev: i2c /dev entries driver

10471 13:59:28.408135  <6>[    1.160978] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10472 13:59:28.411013  <6>[    1.176975] cpu cpu0: EM: created perf domain

10473 13:59:28.417668  <6>[    1.177227] cpu cpu4: EM: created perf domain

10474 13:59:28.420892  <6>[    1.179866] sdhci: Secure Digital Host Controller Interface driver

10475 13:59:28.427742  <6>[    1.179867] sdhci: Copyright(c) Pierre Ossman

10476 13:59:28.434297  <6>[    1.180232] Synopsys Designware Multimedia Card Interface Driver

10477 13:59:28.441275  <6>[    1.180610] sdhci-pltfm: SDHCI platform and OF driver helper

10478 13:59:28.444123  <6>[    1.184535] ledtrig-cpu: registered to indicate activity on CPUs

10479 13:59:28.450754  <6>[    1.185293] mmc0: CQHCI version 5.10

10480 13:59:28.457830  <6>[    1.185297] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10481 13:59:28.460579  <6>[    1.185579] usbcore: registered new interface driver usbhid

10482 13:59:28.467628  <6>[    1.185581] usbhid: USB HID core driver

10483 13:59:28.474181  <6>[    1.185672] spi_master spi0: will run message pump with realtime priority

10484 13:59:28.487643  <6>[    1.217342] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10485 13:59:28.500081  <6>[    1.220518] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10486 13:59:28.503571  <6>[    1.221632] cros-ec-spi spi0.0: Chrome EC device registered

10487 13:59:28.514009  <6>[    1.239897] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10488 13:59:28.520394  <6>[    1.242815] NET: Registered PF_PACKET protocol family

10489 13:59:28.523454  <6>[    1.242928] 9pnet: Installing 9P2000 support

10490 13:59:28.530442  <5>[    1.242971] Key type dns_resolver registered

10491 13:59:28.533754  <6>[    1.243405] registered taskstats version 1

10492 13:59:28.536828  <5>[    1.243423] Loading compiled-in X.509 certificates

10493 13:59:28.549905  <4>[    1.267281] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10494 13:59:28.559920  <4>[    1.267466] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10495 13:59:28.566452  <3>[    1.267478] debugfs: File 'uA_load' in directory '/' already present!

10496 13:59:28.573145  <3>[    1.267487] debugfs: File 'min_uV' in directory '/' already present!

10497 13:59:28.579883  <3>[    1.267490] debugfs: File 'max_uV' in directory '/' already present!

10498 13:59:28.586605  <3>[    1.267494] debugfs: File 'constraint_flags' in directory '/' already present!

10499 13:59:28.596824  <3>[    1.269752] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10500 13:59:28.599834  <6>[    1.277583] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10501 13:59:28.606148  <6>[    1.278190] xhci-mtk 11200000.usb: xHCI Host Controller

10502 13:59:28.612982  <6>[    1.278209] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10503 13:59:28.623209  <6>[    1.278427] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10504 13:59:28.629192  <6>[    1.278483] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10505 13:59:28.635864  <6>[    1.278613] xhci-mtk 11200000.usb: xHCI Host Controller

10506 13:59:28.642722  <6>[    1.278620] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10507 13:59:28.649317  <6>[    1.278628] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10508 13:59:28.653077  <6>[    1.279077] hub 1-0:1.0: USB hub found

10509 13:59:28.659192  <6>[    1.279104] hub 1-0:1.0: 1 port detected

10510 13:59:28.665866  <6>[    1.279335] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10511 13:59:28.668893  <6>[    1.279610] hub 2-0:1.0: USB hub found

10512 13:59:28.675983  <6>[    1.279625] hub 2-0:1.0: 1 port detected

10513 13:59:28.678930  <6>[    1.283141] mtk-msdc 11f70000.mmc: Got CD GPIO

10514 13:59:28.685843  <6>[    1.284436] mmc0: Command Queue Engine enabled

10515 13:59:28.692784  <6>[    1.284445] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10516 13:59:28.695488  <6>[    1.284903] mmcblk0: mmc0:0001 DA4128 116 GiB 

10517 13:59:28.702014  <6>[    1.288432]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10518 13:59:28.705495  <6>[    1.289533] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10519 13:59:28.711849  <6>[    1.290306] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10520 13:59:28.718876  <6>[    1.291345] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10521 13:59:28.725416  <6>[    1.300755] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10522 13:59:28.735027  <6>[    1.300763] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10523 13:59:28.741866  <4>[    1.300915] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10524 13:59:28.751966  <6>[    1.301567] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10525 13:59:28.758460  <6>[    1.301570] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10526 13:59:28.768207  <6>[    1.301739] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10527 13:59:28.775492  <6>[    1.301751] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10528 13:59:28.781720  <6>[    1.301754] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10529 13:59:28.791988  <6>[    1.301759] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10530 13:59:28.801442  <6>[    1.303147] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10531 13:59:28.808064  <6>[    1.303162] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10532 13:59:28.818236  <6>[    1.303168] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10533 13:59:28.824700  <6>[    1.303175] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10534 13:59:28.834211  <6>[    1.303180] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10535 13:59:28.841199  <6>[    1.303186] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10536 13:59:28.851423  <6>[    1.303192] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10537 13:59:28.857661  <6>[    1.303198] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10538 13:59:28.867540  <6>[    1.303204] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10539 13:59:28.873954  <6>[    1.303213] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10540 13:59:28.884295  <6>[    1.303219] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10541 13:59:28.890541  <6>[    1.303225] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10542 13:59:28.900586  <6>[    1.303230] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10543 13:59:28.907251  <6>[    1.303236] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10544 13:59:28.917378  <6>[    1.303242] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10545 13:59:28.923815  <6>[    1.303721] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10546 13:59:28.930304  <6>[    1.304547] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10547 13:59:28.936986  <6>[    1.305089] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10548 13:59:28.943637  <6>[    1.305733] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10549 13:59:28.950072  <6>[    1.306369] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10550 13:59:28.959826  <6>[    1.306573] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10551 13:59:28.966704  <6>[    1.306589] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10552 13:59:28.976447  <6>[    1.306596] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10553 13:59:28.986250  <6>[    1.306603] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10554 13:59:28.996197  <6>[    1.306610] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10555 13:59:29.005914  <6>[    1.306617] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10556 13:59:29.015967  <6>[    1.306624] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10557 13:59:29.022761  <6>[    1.306631] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10558 13:59:29.032526  <6>[    1.306637] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10559 13:59:29.042728  <6>[    1.306645] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10560 13:59:29.052700  <6>[    1.306649] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10561 13:59:29.062360  <6>[    1.307565] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10562 13:59:29.069276  <6>[    1.705378] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10563 13:59:29.072092  <6>[    1.857959] hub 1-1:1.0: USB hub found

10564 13:59:29.075441  <6>[    1.858370] hub 1-1:1.0: 4 ports detected

10565 13:59:29.126089  <6>[    1.981909] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10566 13:59:29.146928  <6>[    2.006924] hub 2-1:1.0: USB hub found

10567 13:59:29.150094  <6>[    2.007370] hub 2-1:1.0: 3 ports detected

10568 13:59:29.313906  <6>[    2.169615] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10569 13:59:29.434517  <6>[    2.297118] hub 1-1.4:1.0: USB hub found

10570 13:59:29.437756  <6>[    2.297546] hub 1-1.4:1.0: 2 ports detected

10571 13:59:29.517900  <6>[    2.373750] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10572 13:59:29.729872  <6>[    2.585620] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10573 13:59:29.914065  <6>[    2.769626] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10574 13:59:40.738145  <6>[   13.602603] ALSA device list:

10575 13:59:40.744880  <6>[   13.602624]   No soundcards found.

10576 13:59:40.748075  <6>[   13.607006] Freeing unused kernel memory: 8384K

10577 13:59:40.751279  <6>[   13.607110] Run /init as init process

10578 13:59:40.766399  Starting syslogd: OK

10579 13:59:40.770721  Starting klogd: OK

10580 13:59:40.780767  Running sysctl: OK

10581 13:59:40.790458  Populating /dev using udev: <30>[   13.653195] udevd[200]: starting version 3.2.9

10582 13:59:40.793619  <27>[   13.657127] udevd[200]: specified user 'tss' unknown

10583 13:59:40.800561  <27>[   13.657176] udevd[200]: specified group 'tss' unknown

10584 13:59:40.803675  <30>[   13.658339] udevd[201]: starting eudev-3.2.9

10585 13:59:40.813703  <27>[   13.676348] udevd[201]: specified user 'tss' unknown

10586 13:59:40.819840  <27>[   13.676378] udevd[201]: specified group 'tss' unknown

10587 13:59:40.920615  <6>[   13.780292] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10588 13:59:40.927495  <6>[   13.780352] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10589 13:59:40.937064  <6>[   13.780360] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10590 13:59:40.948606  <6>[   13.790575] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10591 13:59:40.951841  <6>[   13.798778] remoteproc remoteproc0: scp is available

10592 13:59:40.959019  <6>[   13.798917] remoteproc remoteproc0: powering up scp

10593 13:59:40.965344  <6>[   13.798930] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10594 13:59:40.971833  <6>[   13.798969] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10595 13:59:40.975255  <6>[   13.822441] mc: Linux media interface: v0.10

10596 13:59:40.981647  <6>[   13.836464] videodev: Linux video capture interface: v2.00

10597 13:59:41.001052  <4>[   13.859414] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10598 13:59:41.003952  <6>[   13.860383] Bluetooth: Core ver 2.22

10599 13:59:41.010587  <6>[   13.860444] NET: Registered PF_BLUETOOTH protocol family

10600 13:59:41.017279  <6>[   13.860446] Bluetooth: HCI device and connection manager initialized

10601 13:59:41.020313  <6>[   13.860462] Bluetooth: HCI socket layer initialized

10602 13:59:41.027330  <6>[   13.860465] Bluetooth: L2CAP socket layer initialized

10603 13:59:41.030453  <6>[   13.860491] Bluetooth: SCO socket layer initialized

10604 13:59:41.037323  <4>[   13.860900] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10605 13:59:41.043803  <6>[   13.862389] usbcore: registered new interface driver r8152

10606 13:59:41.053383  <3>[   13.863699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10607 13:59:41.060318  <3>[   13.863716] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10608 13:59:41.066792  <3>[   13.863728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10609 13:59:41.077531  <3>[   13.863919] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10610 13:59:41.083483  <3>[   13.863930] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10611 13:59:41.094035  <3>[   13.863939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10612 13:59:41.100857  <3>[   13.863957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10613 13:59:41.107699  <3>[   13.863967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10614 13:59:41.117393  <3>[   13.864016] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10615 13:59:41.123927  <3>[   13.864089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10616 13:59:41.133650  <3>[   13.864097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10617 13:59:41.140466  <3>[   13.864103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10618 13:59:41.150217  <3>[   13.864199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10619 13:59:41.156803  <3>[   13.864207] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10620 13:59:41.166699  <3>[   13.864216] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10621 13:59:41.173411  <3>[   13.864224] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10622 13:59:41.180217  <3>[   13.864231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10623 13:59:41.189938  <3>[   13.864315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10624 13:59:41.196530  <6>[   13.896683] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10625 13:59:41.203424  <6>[   13.899198] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10626 13:59:41.209785  <6>[   13.899249] pci_bus 0000:00: root bus resource [bus 00-ff]

10627 13:59:41.216780  <6>[   13.899263] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10628 13:59:41.226489  <6>[   13.899272] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10629 13:59:41.232857  <6>[   13.899337] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10630 13:59:41.239652  <6>[   13.899363] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10631 13:59:41.245918  <6>[   13.899476] pci 0000:00:00.0: supports D1 D2

10632 13:59:41.252927  <6>[   13.899480] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10633 13:59:41.259343  <6>[   13.901738] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10634 13:59:41.265969  <6>[   13.901972] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10635 13:59:41.272812  <6>[   13.902008] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10636 13:59:41.282637  <6>[   13.902031] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10637 13:59:41.289050  <6>[   13.902081] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10638 13:59:41.292555  <6>[   13.902373] pci 0000:01:00.0: supports D1 D2

10639 13:59:41.299340  <6>[   13.902397] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10640 13:59:41.305651  <6>[   13.913553] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10641 13:59:41.315282  <6>[   13.913632] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10642 13:59:41.322315  <6>[   13.913639] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10643 13:59:41.332150  <6>[   13.913653] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10644 13:59:41.338881  <6>[   13.913670] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10645 13:59:41.348750  <6>[   13.913686] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10646 13:59:41.351808  <6>[   13.913709] pci 0000:00:00.0: PCI bridge to [bus 01]

10647 13:59:41.361441  <6>[   13.913718] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10648 13:59:41.368292  <6>[   13.913935] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10649 13:59:41.371835  <6>[   13.916702] pcieport 0000:00:00.0: PME: Signaling with IRQ 282

10650 13:59:41.378206  <6>[   13.917158] pcieport 0000:00:00.0: AER: enabled with IRQ 282

10651 13:59:41.388234  <4>[   13.923518] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10652 13:59:41.391743  <4>[   13.923518] Fallback method does not support PEC.

10653 13:59:41.401108  <6>[   13.924294] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10654 13:59:41.408260  <6>[   13.924303] remoteproc remoteproc0: remote processor scp is now up

10655 13:59:41.414367  <6>[   13.924318] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10656 13:59:41.424477  <3>[   13.940576] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10657 13:59:41.430985  <6>[   13.949641] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10658 13:59:41.437778  <3>[   13.965565] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10659 13:59:41.447797  <6>[   13.971900] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2

10660 13:59:41.457638  <4>[   13.976581] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2

10661 13:59:41.464026  <4>[   13.976590] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)

10662 13:59:41.474644  <6>[   13.978543] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003

10663 13:59:41.484122  <6>[   13.978754] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3

10664 13:59:41.490623  <6>[   14.020656] usbcore: registered new interface driver cdc_ether

10665 13:59:41.497078  <6>[   14.033882] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10666 13:59:41.503851  <6>[   14.035334] usbcore: registered new interface driver r8153_ecm

10667 13:59:41.517093  <6>[   14.035443] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10668 13:59:41.523562  <6>[   14.035807] usbcore: registered new interface driver uvcvideo

10669 13:59:41.526919  <6>[   14.045540] r8152 2-1.3:1.0 eth0: v1.12.13

10670 13:59:41.533612  <5>[   14.048185] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10671 13:59:41.543447  <6>[   14.050572] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

10672 13:59:41.550302  <6>[   14.054574] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

10673 13:59:41.556710  <6>[   14.059882] usbcore: registered new interface driver btusb

10674 13:59:41.566615  <4>[   14.060696] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10675 13:59:41.573115  <3>[   14.060714] Bluetooth: hci0: Failed to load firmware file (-2)

10676 13:59:41.579919  <3>[   14.060721] Bluetooth: hci0: Failed to set up firmware (-2)

10677 13:59:41.590005  <4>[   14.060728] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10678 13:59:41.596092  <5>[   14.061458] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10679 13:59:41.606166  <4>[   14.061516] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10680 13:59:41.609585  <6>[   14.061523] cfg80211: failed to load regulatory.db

10681 13:59:41.616308  <6>[   14.074065] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10682 13:59:41.622614  <6>[   14.162455] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10683 13:59:41.629393  <6>[   14.162557] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10684 13:59:41.635966  <6>[   14.181438] mt7921e 0000:01:00.0: ASIC revision: 79610010

10685 13:59:41.645565  <4>[   14.276342] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10686 13:59:41.659012  <4>[   14.382996] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10687 13:59:41.668688  <4>[   14.490731] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10688 13:59:41.710696  done

10689 13:59:41.729982  Saving random seed: OK

10690 13:59:41.744111  <4>[   14.597634] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10691 13:59:41.756263  Starting network: OK

10692 13:59:41.801414  Starting dropbear sshd: <6>[   14.664494] NET: Registered PF_INET6 protocol family

10693 13:59:41.804847  <6>[   14.665666] Segment Routing with IPv6

10694 13:59:41.811080  <6>[   14.665680] In-situ OAM (IOAM) with IPv6

10695 13:59:41.811593  OK

10696 13:59:41.819771  /bin/sh: can't access tty; job control turned off

10697 13:59:41.820822  Matched prompt #10: / #
10699 13:59:41.821917  Setting prompt string to ['/ #']
10700 13:59:41.822382  end: 2.2.5.1 login-action (duration 00:00:15) [common]
10702 13:59:41.823480  end: 2.2.5 auto-login-action (duration 00:00:16) [common]
10703 13:59:41.823981  start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
10704 13:59:41.824373  Setting prompt string to ['/ #']
10705 13:59:41.824708  Forcing a shell prompt, looking for ['/ #']
10707 13:59:41.875515  / # 

10708 13:59:41.876087  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10709 13:59:41.876521  Waiting using forced prompt support (timeout 00:02:30)
10710 13:59:41.877028  <4>[   14.707891] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10711 13:59:41.881822  

10712 13:59:41.882650  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10713 13:59:41.883168  start: 2.2.7 export-device-env (timeout 00:03:22) [common]
10714 13:59:41.883733  end: 2.2.7 export-device-env (duration 00:00:00) [common]
10715 13:59:41.884225  end: 2.2 depthcharge-retry (duration 00:01:38) [common]
10716 13:59:41.884745  end: 2 depthcharge-action (duration 00:01:38) [common]
10717 13:59:41.885228  start: 3 lava-test-retry (timeout 00:01:00) [common]
10718 13:59:41.885703  start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10719 13:59:41.886105  Using namespace: common
10721 13:59:41.987205  / # #

10722 13:59:41.987801  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10723 13:59:41.988351  #<4>[   14.815936] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10724 13:59:41.993519  

10725 13:59:41.994282  Using /lava-11372182
10727 13:59:42.095442  / # export SHELL=/bin/sh

10728 13:59:42.096144  export SHELL=/bin/sh<4>[   14.924089] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10729 13:59:42.101948  

10731 13:59:42.203526  / # . /lava-11372182/environment

10732 13:59:42.204225  . /lava-11372182/environment<4>[   15.032324] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10733 13:59:42.209463  

10735 13:59:42.311017  / # /lava-11372182/bin/lava-test-runner /lava-11372182/0

10736 13:59:42.311600  Test shell timeout: 10s (minimum of the action and connection timeout)
10737 13:59:42.313502  /lava-11372182/bin/lava-test-runner /lava-11372182/0<4>[   15.140379] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10738 13:59:42.317284  

10739 13:59:42.359691  + export 'TESTRUN_ID=0_dmesg'

10740 13:59:42.360164  + cd /lava-11372182/0/tests/0_dmesg

10741 13:59:42.360536  + cat uuid

10742 13:59:42.361185  <8>[   15.205386] <LAVA_SIGNAL_STARTRUN 0_dmesg 11372182_1.5.2.3.1>

10743 13:59:42.361556  + UUID=11372182_1.5.2.3.1

10744 13:59:42.361891  + set +x

10745 13:59:42.362290  + KERNELCI_LAVA=y /bin/sh /<8>[   15.217711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>

10746 13:59:42.362946  Received signal: <STARTRUN> 0_dmesg 11372182_1.5.2.3.1
10747 13:59:42.363331  Starting test lava.0_dmesg (11372182_1.5.2.3.1)
10748 13:59:42.363818  Skipping test definition patterns.
10749 13:59:42.364303  Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10751 13:59:42.371862  opt/kernelci/dme<8>[   15.229275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>

10752 13:59:42.372334  sg.sh

10753 13:59:42.372960  Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10755 13:59:42.391658  <4>[   15.249035] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10756 13:59:42.398448  Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10758 13:59:42.401489  <8>[   15.253674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>

10759 13:59:42.401958  + set +x

10760 13:59:42.402330  <LAVA_TEST_RUNNER EXIT>

10761 13:59:42.403144  ok: lava_test_shell seems to have completed
10762 13:59:42.403641  Marking unfinished test run as failed
10764 13:59:42.404699  alert: pass
crit: pass
emerg: pass

10765 13:59:42.405133  end: 3.1 lava-test-shell (duration 00:00:01) [common]
10766 13:59:42.405579  end: 3 lava-test-retry (duration 00:00:01) [common]
10767 13:59:42.406047  start: 4 lava-test-retry (timeout 00:01:00) [common]
10768 13:59:42.406496  start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10769 13:59:42.406856  Using namespace: common
10771 13:59:42.508016  /#

10772 13:59:42.508640  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10773 13:59:42.509318   # <8>[   15.269548] <LAVA_SIGNAL_ENDRUN 0_dmesg 11372182_1.5.2.3.1>

10774 13:59:42.509714  #<3>[   15.353764] mt7921e 0000:01:00.0: hardware init failed

10775 13:59:42.510370  Using /lava-11372182
10777 13:59:42.611480  export SHELL=/bin/sh

10778 13:59:42.612188  

10780 13:59:42.713739  / # export SHELL=/bin/sh. /lava-11372182/environment

10781 13:59:42.714440  

10783 13:59:42.816221  / # . /lava-11372182/environment/lava-11372182/bin/lava-test-runner /lava-11372182/1

10784 13:59:42.816810  Test shell timeout: 10s (minimum of the action and connection timeout)
10785 13:59:42.817498  

10786 13:59:42.822806  / # /lava-11372182/bin/lava-test-runner /lava-11372182/1

10787 13:59:42.840455  + export 'TESTRUN_ID=1_bootrr'

10788 13:59:42.850654  + cd /lava-11372182/1/tests/1_boot<8>[   15.709990] <LAVA_SIGNAL_STARTRUN 1_bootrr 11372182_1.5.2.3.5>

10789 13:59:42.851127  rr

10790 13:59:42.851797  Received signal: <STARTRUN> 1_bootrr 11372182_1.5.2.3.5
10791 13:59:42.852174  Starting test lava.1_bootrr (11372182_1.5.2.3.5)
10792 13:59:42.852598  Skipping test definition patterns.
10793 13:59:42.853306  + cat uuid

10794 13:59:42.853711  + UUID=11372182_1.5.2.3.5

10795 13:59:42.854057  + set +x

10796 13:59:42.869920  + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11372182/1/../bin:/<8>[   15.726643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>

10797 13:59:42.870662  Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10799 13:59:42.873488  sbin:/usr/sbin:/bin:/usr/bin'

10800 13:59:42.873952  + cd /opt/bootrr/libexec/bootrr

10801 13:59:42.876725  + sh helpers/bootrr-auto

10802 13:59:42.886317  /lava-<8>[   15.743871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>

10803 13:59:42.887049  Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10805 13:59:42.889821  11372182/1/../bin/lava-test-case

10806 13:59:42.893069  /lava-11372182/1/../bin/lava-test-case

10807 13:59:42.893612  /usr/bin/tpm2_getcap

10808 13:59:42.916492  /lava-11372182/1/../bin/lava-test-case

10809 13:59:42.923509  <8>[   15.784186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>

10810 13:59:42.924245  Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10812 13:59:42.934337  /lava-11372182/1/../bin/lava-test-case

10813 13:59:42.944748  <8>[   15.801525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>

10814 13:59:42.945603  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10816 13:59:42.948083  /lava-11372182/1/../bin/lava-test-case

10817 13:59:42.955099  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10819 13:59:42.958174  <8>[   15.816502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>

10820 13:59:42.961263  /lava-11372182/1/../bin/lava-test-case

10821 13:59:42.968303  <8>[   15.828533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>

10822 13:59:42.969048  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10824 13:59:42.971499  /lava-11372182/1/../bin/lava-test-case

10825 13:59:42.981464  <8>[   15.840729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>

10826 13:59:42.982136  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10828 13:59:42.984408  /lava-11372182/1/../bin/lava-test-case

10829 13:59:42.991027  <8>[   15.853181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>

10830 13:59:42.991878  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10832 13:59:42.994297  /lava-11372182/1/../bin/lava-test-case

10833 13:59:43.003979  <8>[   15.864583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>

10834 13:59:43.004754  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10836 13:59:43.007639  /lava-11372182/1/../bin/lava-test-case

10837 13:59:43.020117  /lava-11372182/1<8>[   15.877371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>

10838 13:59:43.020913  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10840 13:59:43.030124  /../bin/lava-tes<8>[   15.883865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>

10841 13:59:43.031034  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10843 13:59:43.033576  t-case

10844 13:59:43.036256  /lava-11372182/1/../bin/lava-test-case

10845 13:59:43.046282  <8>[   15.903441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>

10846 13:59:43.047142  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10848 13:59:43.049511  /lava-11372182/1/../bin/lava-test-case

10849 13:59:43.060785  <8>[   15.917564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>

10850 13:59:43.061608  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10852 13:59:43.064137  /lava-11372182/1/../bin/lava-test-case

10853 13:59:43.076566  <8>[   15.933952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>

10854 13:59:43.077328  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10856 13:59:43.079875  /lava-11372182/1/../bin/lava-test-case

10857 13:59:43.089989  <8>[   15.949035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>

10858 13:59:43.090895  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10860 13:59:43.099634  /lava-11372182/1/../bin/lava-tes<8>[   15.961150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>

10861 13:59:43.100115  t-case

10862 13:59:43.100782  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10864 13:59:43.106415  /lava-11372182/1/../bin/lava-test-case

10865 13:59:43.113119  <8>[   15.972664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>

10866 13:59:43.114101  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10868 13:59:43.116512  /lava-11372182/1/../bin/lava-test-case

10869 13:59:43.123351  <8>[   15.984553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>

10870 13:59:43.124223  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10872 13:59:43.129784  /lava-11372182/1/../bin/lava-test-case

10873 13:59:43.135934  <8>[   15.996441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>

10874 13:59:43.136911  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10876 13:59:43.139340  /lava-11372182/1/../bin/lava-test-case

10877 13:59:43.149358  <8>[   16.008573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>

10878 13:59:43.150112  Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10880 13:59:43.152813  /lava-11372182/1/../bin/lava-test-case

10881 13:59:43.159309  <8>[   16.020321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>

10882 13:59:43.160149  Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10884 13:59:43.162620  /lava-11372182/1/../bin/lava-test-case

10885 13:59:43.172744  <8>[   16.032189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>

10886 13:59:43.173516  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10888 13:59:43.175628  /lava-11372182/1/../bin/lava-test-case

10889 13:59:43.182399  <8>[   16.044670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>

10890 13:59:43.183134  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10892 13:59:43.185798  /lava-11372182/1/../bin/lava-test-case

10893 13:59:43.197059  <8>[   16.056293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>

10894 13:59:43.197788  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10896 13:59:43.199925  /lava-11372182/1/../bin/lava-test-case

10897 13:59:43.209610  <8>[   16.068980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>

10898 13:59:43.210338  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10900 13:59:43.212933  /lava-11372182/1/../bin/lava-test-case

10901 13:59:43.220096  <8>[   16.080786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>

10902 13:59:43.220842  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10904 13:59:43.223229  /lava-11372182/1/../bin/lava-test-case

10905 13:59:43.233406  <8>[   16.092820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>

10906 13:59:43.234343  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10908 13:59:43.236470  /lava-11372182/1/../bin/lava-test-case

10909 13:59:43.243487  <8>[   16.104859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>

10910 13:59:43.244473  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10912 13:59:43.246517  /lava-11372182/1/../bin/lava-test-case

10913 13:59:43.256798  <8>[   16.116136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>

10914 13:59:43.257583  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10916 13:59:43.260192  /lava-11372182/1/../bin/lava-test-case

10917 13:59:43.272350  <8>[   16.130170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>

10918 13:59:43.273084  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10920 13:59:43.276013  /lava-11372182/1/../bin/lava-test-case

10921 13:59:43.283191  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10923 13:59:43.285780  <8>[   16.145018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>

10924 13:59:43.289694  /lava-11372182/1/../bin/lava-test-case

10925 13:59:43.295710  <8>[   16.156406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>

10926 13:59:43.296438  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10928 13:59:43.299029  /lava-11372182/1/../bin/lava-test-case

10929 13:59:43.308872  <8>[   16.168365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>

10930 13:59:43.309601  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10932 13:59:43.312408  /lava-11372182/1/../bin/lava-test-case

10933 13:59:43.318877  <8>[   16.181126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>

10934 13:59:43.319847  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10936 13:59:43.325528  /lava-11372182/1/../bin/lava-test-case

10937 13:59:43.336493  <8>[   16.193473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>

10938 13:59:43.337440  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10940 13:59:43.339962  /lava-11372182/1/../bin/lava-test-case

10941 13:59:43.346466  <8>[   16.208274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>

10942 13:59:43.347270  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10944 13:59:43.353172  /lava-11372182/1/../bin/lava-test-case

10945 13:59:43.359469  <8>[   16.220839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>

10946 13:59:43.360284  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10948 13:59:43.363042  /lava-11372182/1/../bin/lava-test-case

10949 13:59:43.373203  <8>[   16.232580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>

10950 13:59:43.374135  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10952 13:59:43.376035  /lava-11372182/1/../bin/lava-test-case

10953 13:59:43.388512  <8>[   16.245520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>

10954 13:59:43.389313  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10956 13:59:43.391855  /lava-11372182/1/../bin/lava-test-case

10957 13:59:43.403603  /lava-11372182/1<8>[   16.261485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>

10958 13:59:43.404567  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10960 13:59:43.413942  /../bin/lava-tes<8>[   16.269919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>

10961 13:59:43.414595  t-case

10962 13:59:43.415358  Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10964 13:59:43.420477  /lava-11372182/1/../bin/lava-test-case

10965 13:59:43.427304  <8>[   16.286711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>

10966 13:59:43.428246  Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10968 13:59:43.430228  /lava-11372182/1/../bin/lava-test-case

10969 13:59:43.440187  <8>[   16.300960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>

10970 13:59:43.441102  Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10972 13:59:43.443764  /lava-11372182/1/../bin/lava-test-case

10973 13:59:43.456520  <8>[   16.314235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>

10974 13:59:43.457324  Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
10976 13:59:43.459745  /lava-11372182/1/../bin/lava-test-case

10977 13:59:43.472436  <8>[   16.329938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>

10978 13:59:43.473257  Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
10980 13:59:43.476050  /lava-11372182/1/../bin/lava-test-case

10981 13:59:43.487879  /lava-11372182/1<8>[   16.345498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>

10982 13:59:43.488713  Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
10984 13:59:43.498156  /../bin/lava-tes<8>[   16.352829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>

10985 13:59:43.498819  t-case

10986 13:59:43.499728  Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
10988 13:59:43.501593  /lava-11372182/1/../bin/lava-test-case

10989 13:59:43.512906  <8>[   16.370418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>

10990 13:59:43.513758  Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
10992 13:59:43.515653  /lava-11372182/1/../bin/lava-test-case

10993 13:59:43.525789  <8>[   16.383421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>

10994 13:59:43.526722  Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
10996 13:59:43.529198  /lava-11372182/1/../bin/lava-test-case

10997 13:59:43.540691  <8>[   16.397579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>

10998 13:59:43.541643  Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11000 13:59:43.543959  /lava-11372182/1/../bin/lava-test-case

11001 13:59:43.550597  <8>[   16.413132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>

11002 13:59:43.551490  Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11004 13:59:43.557125  /lava-11372182/1/../bin/lava-test-case

11005 13:59:43.563957  <8>[   16.425156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>

11006 13:59:43.564776  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11008 13:59:43.566737  /lava-11372182/1/../bin/lava-test-case

11009 13:59:43.580479  <8>[   16.438472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>

11010 13:59:43.581302  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11012 13:59:43.583635  /lava-11372182/1/../bin/lava-test-case

11013 13:59:43.590871  Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11015 13:59:43.594262  <8>[   16.452000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>

11016 13:59:43.596957  /lava-11372182/1/../bin/lava-test-case

11017 13:59:43.603868  <8>[   16.464446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>

11018 13:59:43.604665  Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11020 13:59:43.607338  /lava-11372182/1/../bin/lava-test-case

11021 13:59:43.614477  Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11023 13:59:43.617334  <8>[   16.475681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>

11024 13:59:43.620582  /lava-11372182/1/../bin/lava-test-case

11025 13:59:43.627175  <8>[   16.488879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>

11026 13:59:43.628133  Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11028 13:59:43.630229  /lava-11372182/1/../bin/lava-test-case

11029 13:59:43.640424  <8>[   16.500356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>

11030 13:59:43.641242  Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11032 13:59:43.643530  /lava-11372182/1/../bin/lava-test-case

11033 13:59:43.650226  <8>[   16.511915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>

11034 13:59:43.651044  Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11036 13:59:43.653785  /lava-11372182/1/../bin/lava-test-case

11037 13:59:43.664898  <8>[   16.524552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>

11038 13:59:43.665879  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11040 13:59:43.667801  /lava-11372182/1/../bin/lava-test-case

11041 13:59:43.674810  <8>[   16.537014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>

11042 13:59:43.675692  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11044 13:59:43.677669  /lava-11372182/1/../bin/lava-test-case

11045 13:59:43.688322  <8>[   16.548555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>

11046 13:59:43.689059  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11048 13:59:43.692291  /lava-11372182/1/../bin/lava-test-case

11049 13:59:43.701893  <8>[   16.559690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>

11050 13:59:43.702706  Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11052 13:59:43.705329  /lava-11372182/1/../bin/lava-test-case

11053 13:59:43.712075  <8>[   16.572731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>

11054 13:59:43.712908  Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11056 13:59:43.715315  /lava-11372182/1/../bin/lava-test-case

11057 13:59:43.725034  <8>[   16.585141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>

11058 13:59:43.725793  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11060 13:59:43.728249  /lava-11372182/1/../bin/lava-test-case

11061 13:59:43.740684  <8>[   16.597581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>

11062 13:59:43.741425  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11064 13:59:43.743999  /lava-11372182/1/../bin/lava-test-case

11065 13:59:43.754177  <8>[   16.612282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>

11066 13:59:43.754903  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11068 13:59:43.757607  /lava-11372182/1/../bin/lava-test-case

11069 13:59:43.763837  <8>[   16.624896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>

11070 13:59:43.764557  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11072 13:59:43.767254  /lava-11372182/1/../bin/lava-test-case

11073 13:59:43.777418  <8>[   16.636921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>

11074 13:59:43.778250  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11076 13:59:43.780342  /lava-11372182/1/../bin/lava-test-case

11077 13:59:43.787064  <8>[   16.648855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>

11078 13:59:43.787831  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11080 13:59:43.790129  /lava-11372182/1/../bin/lava-test-case

11081 13:59:43.800364  <8>[   16.660308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>

11082 13:59:43.801093  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11084 13:59:43.803820  /lava-11372182/1/../bin/lava-test-case

11085 13:59:43.810295  <8>[   16.672134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>

11086 13:59:43.811229  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11088 13:59:43.816888  /lava-11372182/1/../bin/lava-test-case

11089 13:59:43.823673  <8>[   16.685146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>

11090 13:59:43.824373  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11092 13:59:43.827010  /lava-11372182/1/../bin/lava-test-case

11093 13:59:43.837135  <8>[   16.696255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>

11094 13:59:43.837976  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11096 13:59:43.840065  /lava-11372182/1/../bin/lava-test-case

11097 13:59:43.846819  <8>[   16.708135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>

11098 13:59:43.847667  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11100 13:59:43.849997  /lava-11372182/1/../bin/lava-test-case

11101 13:59:43.860634  <8>[   16.720014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>

11102 13:59:43.861381  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11104 13:59:43.864036  /lava-11372182/1/../bin/lava-test-case

11105 13:59:43.870486  <8>[   16.732584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>

11106 13:59:43.871192  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11108 13:59:43.873627  /lava-11372182/1/../bin/lava-test-case

11109 13:59:43.884229  <8>[   16.744626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>

11110 13:59:43.885075  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11112 13:59:43.887540  /lava-11372182/1/../bin/lava-test-case

11113 13:59:43.894520  <8>[   16.755928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>

11114 13:59:43.895207  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11116 13:59:43.897768  /lava-11372182/1/../bin/lava-test-case

11117 13:59:43.908286  <8>[   16.768842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>

11118 13:59:43.909125  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11120 13:59:43.911772  /lava-11372182/1/../bin/lava-test-case

11121 13:59:43.918524  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11123 13:59:43.921708  <8>[   16.780059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>

11124 13:59:43.924422  /lava-11372182/1/../bin/lava-test-case

11125 13:59:43.931578  <8>[   16.792897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>

11126 13:59:43.932458  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11128 13:59:43.934422  /lava-11372182/1/../bin/lava-test-case

11129 13:59:43.944346  <8>[   16.804012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>

11130 13:59:43.945074  Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11132 13:59:43.947992  /lava-11372182/1/../bin/lava-test-case

11133 13:59:43.954580  <8>[   16.816511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>

11134 13:59:43.955480  Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11136 13:59:43.957625  /lava-11372182/1/../bin/lava-test-case

11137 13:59:43.968091  <8>[   16.828245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>

11138 13:59:43.968838  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11140 13:59:43.971329  /lava-11372182/1/../bin/lava-test-case

11141 13:59:43.984272  /lava-11372182/1<8>[   16.841902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>

11142 13:59:43.985123  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11144 13:59:43.994248  <8>[   16.848902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>

11145 13:59:43.994760  /../bin/lava-test-case

11146 13:59:43.995459  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11148 13:59:43.997906  /lava-11372182/1/../bin/lava-test-case

11149 13:59:44.008721  <8>[   16.866044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>

11150 13:59:44.009526  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11152 13:59:44.011944  /lava-11372182/1/../bin/lava-test-case

11153 13:59:44.021528  <8>[   16.880384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>

11154 13:59:44.022219  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11156 13:59:44.024721  /lava-11372182/1/../bin/lava-test-case

11157 13:59:44.031806  <8>[   16.893241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>

11158 13:59:44.032619  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11160 13:59:44.034890  /lava-11372182/1/../bin/lava-test-case

11161 13:59:44.045298  <8>[   16.903972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>

11162 13:59:44.046022  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11164 13:59:44.048278  /lava-11372182/1/../bin/lava-test-case

11165 13:59:44.054681  <8>[   16.916740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>

11166 13:59:44.055468  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11168 13:59:44.058294  /lava-11372182/1/../bin/lava-test-case

11169 13:59:44.068208  <8>[   16.928490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>

11170 13:59:44.068949  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11172 13:59:44.071498  /lava-11372182/1/../bin/lava-test-case

11173 13:59:44.084463  <8>[   16.941951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>

11174 13:59:44.085296  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11176 13:59:44.087499  /lava-11372182/1/../bin/lava-test-case

11177 13:59:44.094888  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11179 13:59:44.097587  <8>[   16.957215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>

11180 13:59:44.100743  /lava-11372182/1/../bin/lava-test-case

11181 13:59:44.107680  <8>[   16.969189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>

11182 13:59:44.108388  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11184 13:59:44.110806  /lava-11372182/1/../bin/lava-test-case

11185 13:59:44.124376  <8>[   16.981539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>

11186 13:59:44.125133  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11188 13:59:44.127495  /lava-11372182/1/../bin/lava-test-case

11189 13:59:44.134444  Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11191 13:59:44.137504  <8>[   16.996065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>

11192 13:59:44.140608  /lava-11372182/1/../bin/lava-test-case

11193 13:59:44.147741  <8>[   17.008186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>

11194 13:59:44.148490  Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11196 13:59:44.151275  /lava-11372182/1/../bin/lava-test-case

11197 13:59:44.160662  <8>[   17.019584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>

11198 13:59:44.161399  Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11200 13:59:45.163888  /lava-11372182/1/../bin/lava-test-case

11201 13:59:45.176480  <8>[   18.033531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>

11202 13:59:45.177268  Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11204 13:59:45.179722  /lava-11372182/1/../bin/lava-test-case

11205 13:59:45.186571  Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11207 13:59:45.189448  <8>[   18.048470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>

11208 13:59:46.191116  /lava-11372182/1/../bin/lava-test-case

11209 13:59:46.197941  <8>[   19.060951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>

11210 13:59:46.198879  Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11212 13:59:46.200996  /lava-11372182/1/../bin/lava-test-case

11213 13:59:46.212080  <8>[   19.072159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>

11214 13:59:46.212925  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11216 13:59:47.217606  /lava-11372182/1/../bin/lava-test-case

11217 13:59:47.230068  <8>[   20.087688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>

11218 13:59:47.230963  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11220 13:59:47.232910  /lava-11372182/1/../bin/lava-test-case

11221 13:59:47.243893  <8>[   20.101907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>

11222 13:59:47.244710  Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11224 13:59:48.244794  /lava-11372182/1/../bin/lava-test-case

11225 13:59:48.260616  <8>[   21.117467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>

11226 13:59:48.261550  Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11228 13:59:48.264464  /lava-11372182/1/../bin/lava-test-case

11229 13:59:48.270711  <8>[   21.133091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>

11230 13:59:48.271525  Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11232 13:59:49.276587  /lava-11372182/1/../bin/lava-test-case

11233 13:59:49.282849  <8>[   22.144740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>

11234 13:59:49.283803  Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11236 13:59:49.285974  /lava-11372182/1/../bin/lava-test-case

11237 13:59:49.295669  <8>[   22.155620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>

11238 13:59:49.296537  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11240 13:59:50.303486  /lava-11372182/1/../bin/lava-test-case

11241 13:59:50.315842  <8>[   23.173647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>

11242 13:59:50.316700  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11244 13:59:50.319174  /lava-11372182/1/../bin/lava-test-case

11245 13:59:50.329150  <8>[   23.188641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>

11246 13:59:50.329887  Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11248 13:59:51.333271  /lava-11372182/1/../bin/lava-test-case

11249 13:59:51.345749  <8>[   24.201855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>

11250 13:59:51.346495  Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11252 13:59:51.349348  /lava-11372182/1/../bin/lava-test-case

11253 13:59:51.359403  <8>[   24.219506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>

11254 13:59:51.360137  Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11256 13:59:51.362912  /lava-11372182/1/../bin/lava-test-case

11257 13:59:51.375445  <8>[   24.234781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>

11258 13:59:51.376171  Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11260 13:59:52.378201  /lava-11372182/1/../bin/lava-test-case

11261 13:59:52.388518  <8>[   25.248442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>

11262 13:59:52.389258  Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11264 13:59:52.391206  /lava-11372182/1/../bin/lava-test-case

11265 13:59:52.398300  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11267 13:59:52.401494  <8>[   25.260527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>

11268 13:59:52.404636  /lava-11372182/1/../bin/lava-test-case

11269 13:59:52.411554  <8>[   25.272753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>

11270 13:59:52.412227  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11272 13:59:52.414312  /lava-11372182/1/../bin/lava-test-case

11273 13:59:52.424415  <8>[   25.285052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>

11274 13:59:52.425086  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11276 13:59:52.427626  /lava-11372182/1/../bin/lava-test-case

11277 13:59:52.439684  <8>[   25.297747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>

11278 13:59:52.440411  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11280 13:59:52.442974  /lava-11372182/1/../bin/lava-test-case

11281 13:59:52.452789  <8>[   25.312448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>

11282 13:59:52.453532  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11284 13:59:52.455902  /lava-11372182/1/../bin/lava-test-case

11285 13:59:52.462496  <8>[   25.324940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>

11286 13:59:52.463226  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11288 13:59:52.465826  /lava-11372182/1/../bin/lava-test-case

11289 13:59:52.475860  <8>[   25.337123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>

11290 13:59:52.476676  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11292 13:59:52.479468  /lava-11372182/1/../bin/lava-test-case

11293 13:59:52.491837  <8>[   25.350079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>

11294 13:59:52.492685  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11296 13:59:52.495266  /lava-11372182/1/../bin/lava-test-case

11297 13:59:52.501549  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11299 13:59:52.504726  <8>[   25.364547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>

11300 13:59:52.507905  /lava-11372182/1/../bin/lava-test-case

11301 13:59:52.514892  <8>[   25.376465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>

11302 13:59:52.515858  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11304 13:59:52.517994  /lava-11372182/1/../bin/lava-test-case

11305 13:59:52.531590  <8>[   25.389404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>

11306 13:59:52.532388  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11308 13:59:52.534689  /lava-11372182/1/../bin/lava-test-case

11309 13:59:52.544588  <8>[   25.404545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>

11310 13:59:52.545434  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11312 13:59:52.547973  /lava-11372182/1/../bin/lava-test-case

11313 13:59:52.559343  /lava-11372182/1<8>[   25.417592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>

11314 13:59:52.560322  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11316 13:59:52.568874  <8>[   25.424070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>

11317 13:59:52.569826  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11319 13:59:52.575752  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11321 13:59:52.578921  <8>[   25.433481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>

11322 13:59:52.585740  <8>[   25.442940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>

11323 13:59:52.586682  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11325 13:59:52.588849  /../bin/lava-test-case

11326 13:59:52.591969  /lava-11372182/1/../bin/lava-test-case

11327 13:59:52.599117  <8>[   25.459445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>

11328 13:59:52.600075  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11330 13:59:52.602086  /lava-11372182/1/../bin/lava-test-case

11331 13:59:52.611988  /lava-11<8>[   25.473226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>

11332 13:59:52.612825  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11334 13:59:52.615561  372182/1/../bin/lava-test-case

11335 13:59:52.619059  /lava-11372182/1/../bin/lava-test-case

11336 13:59:52.625317  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11338 13:59:52.628489  /lava-11<8>[   25.485912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>

11339 13:59:52.629112  372182/1/../bin/lava-test-case

11340 13:59:52.632041  /lava-11372182/1/../bin/lava-test-case

11341 13:59:52.643543  <8>[   25.502766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>

11342 13:59:52.644482  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11344 13:59:53.647498  /lava-11372182/1/../bin/lava-test-case

11345 13:59:53.653876  <8>[   26.517078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>

11346 13:59:53.654799  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11348 13:59:54.658171  /lava-11372182/1/../bin/lava-test-case

11349 13:59:54.664604  <8>[   27.527576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>

11350 13:59:54.664869  Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11352 13:59:54.668100  /lava-11372182/1/../bin/lava-test-case

11353 13:59:54.682701  <8>[   27.541336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>

11354 13:59:54.682955  Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11356 13:59:54.686061  /lava-11372182/1/../bin/lava-test-case

11357 13:59:54.699118  <8>[   27.558286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>

11358 13:59:54.699377  Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11360 13:59:54.702112  /lava-11372182/1/../bin/lava-test-case

11361 13:59:54.712293  <8>[   27.572084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>

11362 13:59:54.712544  Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11364 13:59:54.714998  /lava-11372182/1/../bin/lava-test-case

11365 13:59:54.726397  /lava-11372182/1<8>[   27.585598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>

11366 13:59:54.726651  Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11368 13:59:54.736115  <8>[   27.592540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>

11369 13:59:54.736197  /../bin/lava-test-case

11370 13:59:54.736431  Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11372 13:59:54.739579  /lava-11372182/1/../bin/lava-test-case

11373 13:59:54.750578  /lava-11372182/1<8>[   27.609638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>

11374 13:59:54.750832  Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11376 13:59:54.756979  Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11378 13:59:54.760423  <8>[   27.616365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>

11379 13:59:54.760507  /../bin/lava-test-case

11380 13:59:54.770106  /lava-11372182/1/../bin/<8>[   27.632723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>

11381 13:59:54.770189  lava-test-case

11382 13:59:54.770422  Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11384 13:59:54.776605  /lava-11372182/1/../bin/lava-test-case

11385 13:59:54.783741  <8>[   27.644151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>

11386 13:59:54.783994  Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11388 13:59:54.786332  /lava-11372182/1/../bin/lava-test-case

11389 13:59:54.798654  <8>[   27.658103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>

11390 13:59:54.798933  Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11392 13:59:54.801851  /lava-11372182/1/../bin/lava-test-case

11393 13:59:54.811879  <8>[   27.672127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>

11394 13:59:54.812131  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11396 13:59:54.815294  /lava-11372182/1/../bin/lava-test-case

11397 13:59:54.826590  <8>[   27.686164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>

11398 13:59:54.826842  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11400 13:59:54.829997  /lava-11372182/1/../bin/lava-test-case

11401 13:59:54.836616  <8>[   27.699953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>

11402 13:59:54.836867  Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11404 13:59:54.843256  /lava-11372182/1/../bin/lava-test-case

11405 13:59:54.849689  <8>[   27.712932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>

11406 13:59:54.849940  Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11408 13:59:54.853114  /lava-11372182/1/../bin/lava-test-case

11409 13:59:54.863113  <8>[   27.723463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>

11410 13:59:54.863365  Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11412 13:59:54.866477  /lava-11372182/1/../bin/lava-test-case

11413 13:59:54.873149  <8>[   27.736286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>

11414 13:59:54.873400  Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11416 13:59:54.876479  /lava-11372182/1/../bin/lava-test-case

11417 13:59:54.886932  <8>[   27.748964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>

11418 13:59:54.887213  Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11420 13:59:54.890494  /lava-11372182/1/../bin/lava-test-case

11421 13:59:54.896495  <8>[   27.760184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>

11422 13:59:54.896752  Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11424 13:59:54.900111  /lava-11372182/1/../bin/lava-test-case

11425 13:59:54.910872  <8>[   27.771445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>

11426 13:59:54.911126  Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11428 13:59:54.913873  /lava-11372182/1/../bin/lava-test-case

11429 13:59:54.920817  <8>[   27.784822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>

11430 13:59:54.921069  Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11432 13:59:55.925938  /lava-11372182/1/../bin/lava-test-case

11433 13:59:55.935551  <8>[   28.795311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>

11434 13:59:55.935867  Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11436 13:59:56.935517  /lava-11372182/1/../bin/lava-test-case

11437 13:59:56.946222  <8>[   29.808212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>

11438 13:59:56.946527  Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11439 13:59:56.946614  Bad test result: blocked
11440 13:59:56.949758  /lava-11372182/1/../bin/lava-test-case

11441 13:59:56.956668  <8>[   29.820832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>

11442 13:59:56.956944  Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11444 13:59:57.963736  /lava-11372182/1/../bin/lava-test-case

11445 13:59:57.974394  <8>[   30.834293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>

11446 13:59:57.974680  Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11448 13:59:57.977383  /lava-11372182/1/../bin/lava-test-case

11449 13:59:57.990398  <8>[   30.851476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>

11450 13:59:57.990650  Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11452 13:59:57.993450  /lava-11372182/1/../bin/lava-test-case

11453 13:59:58.000335  <8>[   30.864998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>

11454 13:59:58.000586  Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11456 13:59:58.003304  /lava-11372182/1/../bin/lava-test-case

11457 13:59:58.018452  <8>[   30.877922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>

11458 13:59:58.018736  Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11460 13:59:58.021443  /lava-11372182/1/../bin/lava-test-case

11461 13:59:58.031433  <8>[   30.891736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>

11462 13:59:58.031690  Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11464 13:59:58.034961  /lava-11372182/1/../bin/lava-test-case

11465 13:59:58.041150  <8>[   30.904750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>

11466 13:59:58.041396  Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11468 13:59:58.044624  /lava-11372182/1/../bin/lava-test-case

11469 13:59:58.054737  <8>[   30.917218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>

11470 13:59:58.054985  Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11472 13:59:59.057915  /lava-11372182/1/../bin/lava-test-case

11473 13:59:59.064313  <8>[   31.927839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>

11474 13:59:59.064595  Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11476 13:59:59.067663  /lava-11372182/1/../bin/lava-test-case

11477 13:59:59.078167  <8>[   31.941285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>

11478 13:59:59.078455  Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11480 14:00:00.081960  /lava-11372182/1/../bin/lava-test-case

11481 14:00:00.088758  <8>[   32.952135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>

11482 14:00:00.089052  Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11484 14:00:00.091782  /lava-11372182/1/../bin/lava-test-case

11485 14:00:00.101927  <8>[   32.964971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>

11486 14:00:00.102221  Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11488 14:00:01.106322  /lava-11372182/1/../bin/lava-test-case

11489 14:00:01.113028  <8>[   33.976162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>

11490 14:00:01.113996  Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11492 14:00:01.115859  /lava-11372182/1/../bin/lava-test-case

11493 14:00:01.126319  <8>[   33.989036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>

11494 14:00:01.127273  Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11496 14:00:02.129616  /lava-11372182/1/../bin/lava-test-case

11497 14:00:02.136588  <8>[   35.000423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>

11498 14:00:02.136852  Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11500 14:00:02.139813  /lava-11372182/1/../bin/lava-test-case

11501 14:00:02.154029  <8>[   35.013429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>

11502 14:00:02.154312  Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11504 14:00:02.157273  /lava-11372182/1/../bin/lava-test-case

11505 14:00:02.163520  <8>[   35.028142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>

11506 14:00:02.163881  Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11508 14:00:02.167349  /lava-11372182/1/../bin/lava-test-case

11509 14:00:02.177712  <8>[   35.039980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>

11510 14:00:02.177986  Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11512 14:00:02.181155  /lava-11372182/1/../bin/lava-test-case

11513 14:00:02.187475  <8>[   35.053209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>

11514 14:00:02.187742  Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11516 14:00:02.194451  /lava-11372182/1/../bin/lava-test-case

11517 14:00:02.200860  <8>[   35.065034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>

11518 14:00:02.201148  Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11520 14:00:02.204335  /lava-11372182/1/../bin/lava-test-case

11521 14:00:02.214043  <8>[   35.076405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>

11522 14:00:02.214317  Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11524 14:00:02.217470  /lava-11372182/1/../bin/lava-test-case

11525 14:00:02.223769  <8>[   35.088660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>

11526 14:00:02.224013  Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11528 14:00:02.227041  /lava-11372182/1/../bin/lava-test-case

11529 14:00:02.237624  <8>[   35.100013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>

11530 14:00:02.237902  Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11532 14:00:02.241298  /lava-11372182/1/../bin/lava-test-case

11533 14:00:02.248083  <8>[   35.113270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>

11534 14:00:02.248339  Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11536 14:00:02.250855  + set +x

11537 14:00:02.250954  <LAVA_TEST_RUNNER EXIT>

11538 14:00:02.251219  ok: lava_test_shell seems to have completed
11539 14:00:02.251314  Marking unfinished test run as failed
11541 14:00:02.253247  all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass

11542 14:00:02.253429  end: 4.1 lava-test-shell (duration 00:00:20) [common]
11543 14:00:02.253590  end: 4 lava-test-retry (duration 00:00:20) [common]
11544 14:00:02.253727  start: 5 finalize (timeout 00:07:44) [common]
11545 14:00:02.253859  start: 5.1 power-off (timeout 00:00:30) [common]
11546 14:00:02.254152  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11547 14:00:02.330300  >> Command sent successfully.

11548 14:00:02.332720  Returned 0 in 0 seconds
11549 14:00:02.433356  end: 5.1 power-off (duration 00:00:00) [common]
11551 14:00:02.433701  start: 5.2 read-feedback (timeout 00:07:44) [common]
11552 14:00:02.434010  Listened to connection for namespace 'common' for up to 1s
11554 14:00:02.434445  Listened to connection for namespace 'common' for up to 1s
11555 14:00:03.435053  Finalising connection for namespace 'common'
11556 14:00:03.435809  Disconnecting from shell: Finalise
11557 14:00:03.536883  end: 5.2 read-feedback (duration 00:00:01) [common]
11558 14:00:03.537622  end: 5 finalize (duration 00:00:01) [common]
11559 14:00:03.538225  Cleaning after the job
11560 14:00:03.538760  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/ramdisk
11561 14:00:03.554824  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/kernel
11562 14:00:03.581634  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/dtb
11563 14:00:03.581989  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372182/tftp-deploy-cl_h_2zg/modules
11564 14:00:03.592986  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11372182
11565 14:00:03.640648  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11372182
11566 14:00:03.640803  Job finished correctly