Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 128
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 21
1 13:58:41.967826 lava-dispatcher, installed at version: 2023.06
2 13:58:41.968054 start: 0 validate
3 13:58:41.968198 Start time: 2023-08-28 13:58:41.968188+00:00 (UTC)
4 13:58:41.968339 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:58:41.968493 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:58:42.227976 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:58:42.228216 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:58:42.486939 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:58:42.487771 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:58:59.253883 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:58:59.254594 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:58:59.793869 validate duration: 17.83
14 13:58:59.795135 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:58:59.795753 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:58:59.796477 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:58:59.797157 Not decompressing ramdisk as can be used compressed.
18 13:58:59.797642 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 13:58:59.798014 saving as /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/ramdisk/rootfs.cpio.gz
20 13:58:59.798390 total size: 84918747 (80 MB)
21 13:59:04.708543 progress 0 % (0 MB)
22 13:59:04.771382 progress 5 % (4 MB)
23 13:59:04.794500 progress 10 % (8 MB)
24 13:59:04.816485 progress 15 % (12 MB)
25 13:59:04.838368 progress 20 % (16 MB)
26 13:59:04.860406 progress 25 % (20 MB)
27 13:59:04.882578 progress 30 % (24 MB)
28 13:59:04.904693 progress 35 % (28 MB)
29 13:59:04.926962 progress 40 % (32 MB)
30 13:59:04.949217 progress 45 % (36 MB)
31 13:59:04.971326 progress 50 % (40 MB)
32 13:59:04.993581 progress 55 % (44 MB)
33 13:59:05.016036 progress 60 % (48 MB)
34 13:59:05.038492 progress 65 % (52 MB)
35 13:59:05.060881 progress 70 % (56 MB)
36 13:59:05.082923 progress 75 % (60 MB)
37 13:59:05.105583 progress 80 % (64 MB)
38 13:59:05.127936 progress 85 % (68 MB)
39 13:59:05.150247 progress 90 % (72 MB)
40 13:59:05.172359 progress 95 % (76 MB)
41 13:59:05.194217 progress 100 % (80 MB)
42 13:59:05.194448 80 MB downloaded in 5.40 s (15.01 MB/s)
43 13:59:05.194618 end: 1.1.1 http-download (duration 00:00:05) [common]
45 13:59:05.194862 end: 1.1 download-retry (duration 00:00:05) [common]
46 13:59:05.194950 start: 1.2 download-retry (timeout 00:09:55) [common]
47 13:59:05.195033 start: 1.2.1 http-download (timeout 00:09:55) [common]
48 13:59:05.195178 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:59:05.195251 saving as /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/kernel/Image
50 13:59:05.195313 total size: 49222144 (46 MB)
51 13:59:05.195376 No compression specified
52 13:59:05.196533 progress 0 % (0 MB)
53 13:59:05.209467 progress 5 % (2 MB)
54 13:59:05.222463 progress 10 % (4 MB)
55 13:59:05.235311 progress 15 % (7 MB)
56 13:59:05.248221 progress 20 % (9 MB)
57 13:59:05.261247 progress 25 % (11 MB)
58 13:59:05.273977 progress 30 % (14 MB)
59 13:59:05.286680 progress 35 % (16 MB)
60 13:59:05.299394 progress 40 % (18 MB)
61 13:59:05.312768 progress 45 % (21 MB)
62 13:59:05.326300 progress 50 % (23 MB)
63 13:59:05.339125 progress 55 % (25 MB)
64 13:59:05.352342 progress 60 % (28 MB)
65 13:59:05.365868 progress 65 % (30 MB)
66 13:59:05.378994 progress 70 % (32 MB)
67 13:59:05.391858 progress 75 % (35 MB)
68 13:59:05.404668 progress 80 % (37 MB)
69 13:59:05.417743 progress 85 % (39 MB)
70 13:59:05.430912 progress 90 % (42 MB)
71 13:59:05.443897 progress 95 % (44 MB)
72 13:59:05.456601 progress 100 % (46 MB)
73 13:59:05.456779 46 MB downloaded in 0.26 s (179.54 MB/s)
74 13:59:05.456990 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:59:05.457225 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:59:05.457311 start: 1.3 download-retry (timeout 00:09:54) [common]
78 13:59:05.457403 start: 1.3.1 http-download (timeout 00:09:54) [common]
79 13:59:05.457542 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:59:05.457614 saving as /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/dtb/mt8192-asurada-spherion-r0.dtb
81 13:59:05.457676 total size: 47278 (0 MB)
82 13:59:05.457738 No compression specified
83 13:59:05.458877 progress 69 % (0 MB)
84 13:59:05.459156 progress 100 % (0 MB)
85 13:59:05.459317 0 MB downloaded in 0.00 s (27.52 MB/s)
86 13:59:05.459441 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:59:05.459704 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:59:05.459791 start: 1.4 download-retry (timeout 00:09:54) [common]
90 13:59:05.459875 start: 1.4.1 http-download (timeout 00:09:54) [common]
91 13:59:05.459990 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:59:05.460116 saving as /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/modules/modules.tar
93 13:59:05.460192 total size: 8615960 (8 MB)
94 13:59:05.460254 Using unxz to decompress xz
95 13:59:05.464509 progress 0 % (0 MB)
96 13:59:05.486091 progress 5 % (0 MB)
97 13:59:05.508002 progress 10 % (0 MB)
98 13:59:05.534634 progress 15 % (1 MB)
99 13:59:05.560547 progress 20 % (1 MB)
100 13:59:05.586503 progress 25 % (2 MB)
101 13:59:05.612758 progress 30 % (2 MB)
102 13:59:05.640607 progress 35 % (2 MB)
103 13:59:05.666628 progress 40 % (3 MB)
104 13:59:05.692552 progress 45 % (3 MB)
105 13:59:05.720385 progress 50 % (4 MB)
106 13:59:05.746930 progress 55 % (4 MB)
107 13:59:05.773011 progress 60 % (4 MB)
108 13:59:05.796462 progress 65 % (5 MB)
109 13:59:05.825269 progress 70 % (5 MB)
110 13:59:05.850683 progress 75 % (6 MB)
111 13:59:05.877421 progress 80 % (6 MB)
112 13:59:05.912914 progress 85 % (7 MB)
113 13:59:05.943347 progress 90 % (7 MB)
114 13:59:05.967438 progress 95 % (7 MB)
115 13:59:05.990237 progress 100 % (8 MB)
116 13:59:05.996479 8 MB downloaded in 0.54 s (15.32 MB/s)
117 13:59:05.996737 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:59:05.996998 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:59:05.997093 start: 1.5 prepare-tftp-overlay (timeout 00:09:54) [common]
121 13:59:05.997190 start: 1.5.1 extract-nfsrootfs (timeout 00:09:54) [common]
122 13:59:05.997273 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:59:05.997363 start: 1.5.2 lava-overlay (timeout 00:09:54) [common]
124 13:59:05.997592 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7
125 13:59:05.997729 makedir: /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin
126 13:59:05.997837 makedir: /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/tests
127 13:59:05.997936 makedir: /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/results
128 13:59:05.998058 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-add-keys
129 13:59:05.998207 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-add-sources
130 13:59:05.998343 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-background-process-start
131 13:59:05.998476 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-background-process-stop
132 13:59:05.998605 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-common-functions
133 13:59:05.998732 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-echo-ipv4
134 13:59:05.998862 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-install-packages
135 13:59:05.998990 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-installed-packages
136 13:59:05.999117 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-os-build
137 13:59:05.999244 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-probe-channel
138 13:59:05.999371 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-probe-ip
139 13:59:05.999497 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-target-ip
140 13:59:05.999628 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-target-mac
141 13:59:05.999757 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-target-storage
142 13:59:05.999888 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-test-case
143 13:59:06.000018 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-test-event
144 13:59:06.000144 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-test-feedback
145 13:59:06.000272 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-test-raise
146 13:59:06.000401 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-test-reference
147 13:59:06.000528 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-test-runner
148 13:59:06.000654 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-test-set
149 13:59:06.000782 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-test-shell
150 13:59:06.000913 Updating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-install-packages (oe)
151 13:59:06.001071 Updating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/bin/lava-installed-packages (oe)
152 13:59:06.001202 Creating /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/environment
153 13:59:06.001303 LAVA metadata
154 13:59:06.001378 - LAVA_JOB_ID=11372169
155 13:59:06.001448 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:59:06.001553 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:54) [common]
157 13:59:06.001620 skipped lava-vland-overlay
158 13:59:06.001694 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:59:06.001779 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
160 13:59:06.001841 skipped lava-multinode-overlay
161 13:59:06.001916 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:59:06.002000 start: 1.5.2.3 test-definition (timeout 00:09:54) [common]
163 13:59:06.002073 Loading test definitions
164 13:59:06.002164 start: 1.5.2.3.1 git-repo-action (timeout 00:09:54) [common]
165 13:59:06.002237 Using /lava-11372169 at stage 0
166 13:59:06.002332 Fetching tests from https://github.com/kernelci/kernelci-core
167 13:59:06.002418 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/0/tests/0_sleep'
168 13:59:06.688577 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/0/tests/0_sleep
169 13:59:06.689923 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 13:59:06.690341 uuid=11372169_1.5.2.3.1 testdef=None
171 13:59:06.690500 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 13:59:06.690779 start: 1.5.2.3.2 test-overlay (timeout 00:09:53) [common]
174 13:59:06.691362 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 13:59:06.691733 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:53) [common]
177 13:59:06.692458 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 13:59:06.692720 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
180 13:59:06.693663 runner path: /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/0/tests/0_sleep test_uuid 11372169_1.5.2.3.1
181 13:59:06.693781 sleep_params='mem freeze'
182 13:59:06.693955 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 13:59:06.694315 Creating lava-test-runner.conf files
185 13:59:06.694418 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11372169/lava-overlay-faui49w7/lava-11372169/0 for stage 0
186 13:59:06.694560 - 0_sleep
187 13:59:06.694706 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 13:59:06.694810 start: 1.5.2.4 compress-overlay (timeout 00:09:53) [common]
189 13:59:06.821618 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 13:59:06.821786 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
191 13:59:06.821904 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 13:59:06.822025 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 13:59:06.822138 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
194 13:59:09.269673 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 13:59:09.270085 start: 1.5.4 extract-modules (timeout 00:09:51) [common]
196 13:59:09.270214 extracting modules file /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11372169/extract-overlay-ramdisk-9aek4tve/ramdisk
197 13:59:09.498616 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 13:59:09.498793 start: 1.5.5 apply-overlay-tftp (timeout 00:09:50) [common]
199 13:59:09.498894 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11372169/compress-overlay-r369pb7l/overlay-1.5.2.4.tar.gz to ramdisk
200 13:59:09.498968 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11372169/compress-overlay-r369pb7l/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11372169/extract-overlay-ramdisk-9aek4tve/ramdisk
201 13:59:09.593168 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 13:59:09.593335 start: 1.5.6 configure-preseed-file (timeout 00:09:50) [common]
203 13:59:09.593432 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 13:59:09.593522 start: 1.5.7 compress-ramdisk (timeout 00:09:50) [common]
205 13:59:09.593603 Building ramdisk /var/lib/lava/dispatcher/tmp/11372169/extract-overlay-ramdisk-9aek4tve/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11372169/extract-overlay-ramdisk-9aek4tve/ramdisk
206 13:59:11.095353 >> 563314 blocks
207 13:59:20.736143 rename /var/lib/lava/dispatcher/tmp/11372169/extract-overlay-ramdisk-9aek4tve/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/ramdisk/ramdisk.cpio.gz
208 13:59:20.736605 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 13:59:20.736737 start: 1.5.8 prepare-kernel (timeout 00:09:39) [common]
210 13:59:20.736844 start: 1.5.8.1 prepare-fit (timeout 00:09:39) [common]
211 13:59:20.736966 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/kernel/Image'
212 13:59:33.099881 Returned 0 in 12 seconds
213 13:59:33.200820 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/kernel/image.itb
214 13:59:34.555526 output: FIT description: Kernel Image image with one or more FDT blobs
215 13:59:34.555956 output: Created: Mon Aug 28 14:59:34 2023
216 13:59:34.556031 output: Image 0 (kernel-1)
217 13:59:34.556095 output: Description:
218 13:59:34.556158 output: Created: Mon Aug 28 14:59:34 2023
219 13:59:34.556221 output: Type: Kernel Image
220 13:59:34.556282 output: Compression: lzma compressed
221 13:59:34.556343 output: Data Size: 11039834 Bytes = 10781.09 KiB = 10.53 MiB
222 13:59:34.556403 output: Architecture: AArch64
223 13:59:34.556462 output: OS: Linux
224 13:59:34.556518 output: Load Address: 0x00000000
225 13:59:34.556571 output: Entry Point: 0x00000000
226 13:59:34.556623 output: Hash algo: crc32
227 13:59:34.556675 output: Hash value: 946c5cd4
228 13:59:34.556727 output: Image 1 (fdt-1)
229 13:59:34.556779 output: Description: mt8192-asurada-spherion-r0
230 13:59:34.556831 output: Created: Mon Aug 28 14:59:34 2023
231 13:59:34.556884 output: Type: Flat Device Tree
232 13:59:34.556935 output: Compression: uncompressed
233 13:59:34.556988 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 13:59:34.557039 output: Architecture: AArch64
235 13:59:34.557091 output: Hash algo: crc32
236 13:59:34.557143 output: Hash value: cc4352de
237 13:59:34.557194 output: Image 2 (ramdisk-1)
238 13:59:34.557245 output: Description: unavailable
239 13:59:34.557297 output: Created: Mon Aug 28 14:59:34 2023
240 13:59:34.557349 output: Type: RAMDisk Image
241 13:59:34.557401 output: Compression: Unknown Compression
242 13:59:34.557453 output: Data Size: 98307415 Bytes = 96003.33 KiB = 93.75 MiB
243 13:59:34.557505 output: Architecture: AArch64
244 13:59:34.557557 output: OS: Linux
245 13:59:34.557608 output: Load Address: unavailable
246 13:59:34.557659 output: Entry Point: unavailable
247 13:59:34.557710 output: Hash algo: crc32
248 13:59:34.557761 output: Hash value: bab9916e
249 13:59:34.557811 output: Default Configuration: 'conf-1'
250 13:59:34.557863 output: Configuration 0 (conf-1)
251 13:59:34.557956 output: Description: mt8192-asurada-spherion-r0
252 13:59:34.558007 output: Kernel: kernel-1
253 13:59:34.558058 output: Init Ramdisk: ramdisk-1
254 13:59:34.558109 output: FDT: fdt-1
255 13:59:34.558161 output: Loadables: kernel-1
256 13:59:34.558211 output:
257 13:59:34.558410 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 13:59:34.558509 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 13:59:34.558614 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
260 13:59:34.558708 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:25) [common]
261 13:59:34.558832 No LXC device requested
262 13:59:34.558926 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 13:59:34.559014 start: 1.7 deploy-device-env (timeout 00:09:25) [common]
264 13:59:34.559091 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 13:59:34.559159 Checking files for TFTP limit of 4294967296 bytes.
266 13:59:34.559708 end: 1 tftp-deploy (duration 00:00:35) [common]
267 13:59:34.559809 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 13:59:34.559896 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 13:59:34.560014 substitutions:
270 13:59:34.560081 - {DTB}: 11372169/tftp-deploy-yxj2t1zm/dtb/mt8192-asurada-spherion-r0.dtb
271 13:59:34.560144 - {INITRD}: 11372169/tftp-deploy-yxj2t1zm/ramdisk/ramdisk.cpio.gz
272 13:59:34.560203 - {KERNEL}: 11372169/tftp-deploy-yxj2t1zm/kernel/Image
273 13:59:34.560259 - {LAVA_MAC}: None
274 13:59:34.560315 - {PRESEED_CONFIG}: None
275 13:59:34.560369 - {PRESEED_LOCAL}: None
276 13:59:34.560423 - {RAMDISK}: 11372169/tftp-deploy-yxj2t1zm/ramdisk/ramdisk.cpio.gz
277 13:59:34.560477 - {ROOT_PART}: None
278 13:59:34.560531 - {ROOT}: None
279 13:59:34.560583 - {SERVER_IP}: 192.168.201.1
280 13:59:34.560636 - {TEE}: None
281 13:59:34.560689 Parsed boot commands:
282 13:59:34.560763 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 13:59:34.560946 Parsed boot commands: tftpboot 192.168.201.1 11372169/tftp-deploy-yxj2t1zm/kernel/image.itb 11372169/tftp-deploy-yxj2t1zm/kernel/cmdline
284 13:59:34.561038 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 13:59:34.561120 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 13:59:34.561214 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 13:59:34.561296 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 13:59:34.561365 Not connected, no need to disconnect.
289 13:59:34.561436 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 13:59:34.561515 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 13:59:34.561582 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
292 13:59:34.565685 Setting prompt string to ['lava-test: # ']
293 13:59:34.566102 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 13:59:34.566207 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 13:59:34.566330 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 13:59:34.566455 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 13:59:34.566694 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
298 13:59:39.707169 >> Command sent successfully.
299 13:59:39.709549 Returned 0 in 5 seconds
300 13:59:39.809945 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 13:59:39.810273 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 13:59:39.810373 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 13:59:39.810462 Setting prompt string to 'Starting depthcharge on Spherion...'
305 13:59:39.810532 Changing prompt to 'Starting depthcharge on Spherion...'
306 13:59:39.810602 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 13:59:39.810865 [Enter `^Ec?' for help]
308 13:59:39.982548
309 13:59:39.982692
310 13:59:39.982762 F0: 102B 0000
311 13:59:39.982823
312 13:59:39.982882 F3: 1001 0000 [0200]
313 13:59:39.986085
314 13:59:39.986171 F3: 1001 0000
315 13:59:39.986238
316 13:59:39.986299 F7: 102D 0000
317 13:59:39.986359
318 13:59:39.989009 F1: 0000 0000
319 13:59:39.989091
320 13:59:39.989156 V0: 0000 0000 [0001]
321 13:59:39.989221
322 13:59:39.992692 00: 0007 8000
323 13:59:39.992779
324 13:59:39.992844 01: 0000 0000
325 13:59:39.992906
326 13:59:39.995809 BP: 0C00 0209 [0000]
327 13:59:39.995892
328 13:59:39.995957 G0: 1182 0000
329 13:59:39.996017
330 13:59:39.999667 EC: 0000 0021 [4000]
331 13:59:39.999749
332 13:59:39.999814 S7: 0000 0000 [0000]
333 13:59:39.999874
334 13:59:40.002969 CC: 0000 0000 [0001]
335 13:59:40.003051
336 13:59:40.003116 T0: 0000 0040 [010F]
337 13:59:40.003180
338 13:59:40.003238 Jump to BL
339 13:59:40.003294
340 13:59:40.029432
341 13:59:40.029520
342 13:59:40.029585
343 13:59:40.036361 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 13:59:40.040229 ARM64: Exception handlers installed.
345 13:59:40.043785 ARM64: Testing exception
346 13:59:40.046667 ARM64: Done test exception
347 13:59:40.053499 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 13:59:40.063556 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 13:59:40.070310 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 13:59:40.080558 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 13:59:40.086734 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 13:59:40.097244 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 13:59:40.108424 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 13:59:40.114537 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 13:59:40.132539 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 13:59:40.135961 WDT: Last reset was cold boot
357 13:59:40.139281 SPI1(PAD0) initialized at 2873684 Hz
358 13:59:40.142245 SPI5(PAD0) initialized at 992727 Hz
359 13:59:40.145624 VBOOT: Loading verstage.
360 13:59:40.152192 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 13:59:40.156805 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 13:59:40.160135 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 13:59:40.163289 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 13:59:40.170464 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 13:59:40.176783 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 13:59:40.187409 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 13:59:40.187515
368 13:59:40.187657
369 13:59:40.197824 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 13:59:40.201238 ARM64: Exception handlers installed.
371 13:59:40.201357 ARM64: Testing exception
372 13:59:40.204518 ARM64: Done test exception
373 13:59:40.208212 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 13:59:40.214949 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 13:59:40.228041 Probing TPM: . done!
376 13:59:40.228213 TPM ready after 0 ms
377 13:59:40.235940 Connected to device vid:did:rid of 1ae0:0028:00
378 13:59:40.242380 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 13:59:40.301535 Initialized TPM device CR50 revision 0
380 13:59:40.313562 tlcl_send_startup: Startup return code is 0
381 13:59:40.313677 TPM: setup succeeded
382 13:59:40.324691 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 13:59:40.333597 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 13:59:40.346114 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 13:59:40.356043 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 13:59:40.359301 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 13:59:40.362914 in-header: 03 07 00 00 08 00 00 00
388 13:59:40.366900 in-data: aa e4 47 04 13 02 00 00
389 13:59:40.370759 Chrome EC: UHEPI supported
390 13:59:40.373857 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 13:59:40.378798 in-header: 03 95 00 00 08 00 00 00
392 13:59:40.382201 in-data: 18 20 20 08 00 00 00 00
393 13:59:40.382288 Phase 1
394 13:59:40.386039 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 13:59:40.393276 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 13:59:40.401000 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 13:59:40.401131 Recovery requested (1009000e)
398 13:59:40.411349 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 13:59:40.417106 tlcl_extend: response is 0
400 13:59:40.426211 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 13:59:40.431661 tlcl_extend: response is 0
402 13:59:40.438839 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 13:59:40.458338 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 13:59:40.465109 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 13:59:40.465210
406 13:59:40.465278
407 13:59:40.475006 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 13:59:40.478856 ARM64: Exception handlers installed.
409 13:59:40.481845 ARM64: Testing exception
410 13:59:40.481929 ARM64: Done test exception
411 13:59:40.504429 pmic_efuse_setting: Set efuses in 11 msecs
412 13:59:40.507490 pmwrap_interface_init: Select PMIF_VLD_RDY
413 13:59:40.514287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 13:59:40.517767 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 13:59:40.521656 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 13:59:40.528789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 13:59:40.532253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 13:59:40.535697 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 13:59:40.543276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 13:59:40.546996 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 13:59:40.550841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 13:59:40.558358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 13:59:40.562234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 13:59:40.566063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 13:59:40.569292 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 13:59:40.576686 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 13:59:40.581294 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 13:59:40.588396 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 13:59:40.592203 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 13:59:40.599184 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 13:59:40.606291 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 13:59:40.610181 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 13:59:40.617618 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 13:59:40.621234 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 13:59:40.628772 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 13:59:40.632673 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 13:59:40.636472 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 13:59:40.643619 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 13:59:40.647717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 13:59:40.654426 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 13:59:40.658463 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 13:59:40.662116 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 13:59:40.669277 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 13:59:40.673573 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 13:59:40.677050 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 13:59:40.684583 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 13:59:40.688246 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 13:59:40.692454 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 13:59:40.699800 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 13:59:40.703673 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 13:59:40.706956 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 13:59:40.711123 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 13:59:40.717752 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 13:59:40.722114 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 13:59:40.725211 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 13:59:40.729259 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 13:59:40.733313 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 13:59:40.736543 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 13:59:40.744309 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 13:59:40.748162 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 13:59:40.751794 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 13:59:40.755352 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 13:59:40.758693 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 13:59:40.766788 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 13:59:40.774678 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 13:59:40.781877 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 13:59:40.789043 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 13:59:40.796018 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 13:59:40.799739 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 13:59:40.807113 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 13:59:40.810504 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 13:59:40.817799 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1d
473 13:59:40.821341 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 13:59:40.826136 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 13:59:40.833542 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 13:59:40.842316 [RTC]rtc_get_frequency_meter,154: input=15, output=759
477 13:59:40.851530 [RTC]rtc_get_frequency_meter,154: input=23, output=943
478 13:59:40.861318 [RTC]rtc_get_frequency_meter,154: input=19, output=851
479 13:59:40.870688 [RTC]rtc_get_frequency_meter,154: input=17, output=803
480 13:59:40.880258 [RTC]rtc_get_frequency_meter,154: input=16, output=783
481 13:59:40.889596 [RTC]rtc_get_frequency_meter,154: input=16, output=782
482 13:59:40.899582 [RTC]rtc_get_frequency_meter,154: input=17, output=804
483 13:59:40.903436 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 13:59:40.906966 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 13:59:40.910392 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 13:59:40.918032 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 13:59:40.921676 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 13:59:40.925260 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 13:59:40.929447 ADC[4]: Raw value=906573 ID=7
490 13:59:40.929527 ADC[3]: Raw value=213441 ID=1
491 13:59:40.932507 RAM Code: 0x71
492 13:59:40.936586 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 13:59:40.939893 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 13:59:40.951326 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 13:59:40.955232 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 13:59:40.958694 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 13:59:40.962425 in-header: 03 07 00 00 08 00 00 00
498 13:59:40.966631 in-data: aa e4 47 04 13 02 00 00
499 13:59:40.970596 Chrome EC: UHEPI supported
500 13:59:40.974399 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 13:59:40.978997 in-header: 03 95 00 00 08 00 00 00
502 13:59:40.982353 in-data: 18 20 20 08 00 00 00 00
503 13:59:40.986390 MRC: failed to locate region type 0.
504 13:59:40.993382 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 13:59:40.997171 DRAM-K: Running full calibration
506 13:59:41.001123 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 13:59:41.004477 header.status = 0x0
508 13:59:41.008379 header.version = 0x6 (expected: 0x6)
509 13:59:41.011783 header.size = 0xd00 (expected: 0xd00)
510 13:59:41.011859 header.flags = 0x0
511 13:59:41.019067 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 13:59:41.036405 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
513 13:59:41.043923 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 13:59:41.047297 dram_init: ddr_geometry: 2
515 13:59:41.047372 [EMI] MDL number = 2
516 13:59:41.051385 [EMI] Get MDL freq = 0
517 13:59:41.051469 dram_init: ddr_type: 0
518 13:59:41.055360 is_discrete_lpddr4: 1
519 13:59:41.058666 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 13:59:41.058749
521 13:59:41.058814
522 13:59:41.058874 [Bian_co] ETT version 0.0.0.1
523 13:59:41.066279 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 13:59:41.066364
525 13:59:41.070021 dramc_set_vcore_voltage set vcore to 650000
526 13:59:41.070104 Read voltage for 800, 4
527 13:59:41.073855 Vio18 = 0
528 13:59:41.073943 Vcore = 650000
529 13:59:41.074009 Vdram = 0
530 13:59:41.074070 Vddq = 0
531 13:59:41.077772 Vmddr = 0
532 13:59:41.077856 dram_init: config_dvfs: 1
533 13:59:41.081574 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 13:59:41.088839 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 13:59:41.092713 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
536 13:59:41.096196 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
537 13:59:41.099669 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
538 13:59:41.103667 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
539 13:59:41.107219 MEM_TYPE=3, freq_sel=18
540 13:59:41.109981 sv_algorithm_assistance_LP4_1600
541 13:59:41.113641 ============ PULL DRAM RESETB DOWN ============
542 13:59:41.117096 ========== PULL DRAM RESETB DOWN end =========
543 13:59:41.120418 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 13:59:41.124100 ===================================
545 13:59:41.127482 LPDDR4 DRAM CONFIGURATION
546 13:59:41.131076 ===================================
547 13:59:41.134777 EX_ROW_EN[0] = 0x0
548 13:59:41.134860 EX_ROW_EN[1] = 0x0
549 13:59:41.138631 LP4Y_EN = 0x0
550 13:59:41.138704 WORK_FSP = 0x0
551 13:59:41.138766 WL = 0x2
552 13:59:41.141915 RL = 0x2
553 13:59:41.141999 BL = 0x2
554 13:59:41.145706 RPST = 0x0
555 13:59:41.145789 RD_PRE = 0x0
556 13:59:41.149556 WR_PRE = 0x1
557 13:59:41.149640 WR_PST = 0x0
558 13:59:41.152441 DBI_WR = 0x0
559 13:59:41.152524 DBI_RD = 0x0
560 13:59:41.155706 OTF = 0x1
561 13:59:41.159415 ===================================
562 13:59:41.162578 ===================================
563 13:59:41.162661 ANA top config
564 13:59:41.166472 ===================================
565 13:59:41.169380 DLL_ASYNC_EN = 0
566 13:59:41.172617 ALL_SLAVE_EN = 1
567 13:59:41.176062 NEW_RANK_MODE = 1
568 13:59:41.176147 DLL_IDLE_MODE = 1
569 13:59:41.179506 LP45_APHY_COMB_EN = 1
570 13:59:41.182707 TX_ODT_DIS = 1
571 13:59:41.186557 NEW_8X_MODE = 1
572 13:59:41.186641 ===================================
573 13:59:41.190169 ===================================
574 13:59:41.193250 data_rate = 1600
575 13:59:41.196632 CKR = 1
576 13:59:41.200022 DQ_P2S_RATIO = 8
577 13:59:41.203457 ===================================
578 13:59:41.206891 CA_P2S_RATIO = 8
579 13:59:41.209994 DQ_CA_OPEN = 0
580 13:59:41.210077 DQ_SEMI_OPEN = 0
581 13:59:41.213643 CA_SEMI_OPEN = 0
582 13:59:41.216604 CA_FULL_RATE = 0
583 13:59:41.219912 DQ_CKDIV4_EN = 1
584 13:59:41.223384 CA_CKDIV4_EN = 1
585 13:59:41.226764 CA_PREDIV_EN = 0
586 13:59:41.226847 PH8_DLY = 0
587 13:59:41.230543 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 13:59:41.233937 DQ_AAMCK_DIV = 4
589 13:59:41.237009 CA_AAMCK_DIV = 4
590 13:59:41.240575 CA_ADMCK_DIV = 4
591 13:59:41.240658 DQ_TRACK_CA_EN = 0
592 13:59:41.243941 CA_PICK = 800
593 13:59:41.246666 CA_MCKIO = 800
594 13:59:41.250845 MCKIO_SEMI = 0
595 13:59:41.254155 PLL_FREQ = 3068
596 13:59:41.258078 DQ_UI_PI_RATIO = 32
597 13:59:41.258162 CA_UI_PI_RATIO = 0
598 13:59:41.261527 ===================================
599 13:59:41.265125 ===================================
600 13:59:41.269194 memory_type:LPDDR4
601 13:59:41.269277 GP_NUM : 10
602 13:59:41.272729 SRAM_EN : 1
603 13:59:41.272843 MD32_EN : 0
604 13:59:41.276465 ===================================
605 13:59:41.279911 [ANA_INIT] >>>>>>>>>>>>>>
606 13:59:41.283790 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 13:59:41.287414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 13:59:41.290847 ===================================
609 13:59:41.290931 data_rate = 1600,PCW = 0X7600
610 13:59:41.294021 ===================================
611 13:59:41.297398 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 13:59:41.304203 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 13:59:41.310487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 13:59:41.313893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 13:59:41.317452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 13:59:41.320641 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 13:59:41.324049 [ANA_INIT] flow start
618 13:59:41.327307 [ANA_INIT] PLL >>>>>>>>
619 13:59:41.327383 [ANA_INIT] PLL <<<<<<<<
620 13:59:41.330637 [ANA_INIT] MIDPI >>>>>>>>
621 13:59:41.334171 [ANA_INIT] MIDPI <<<<<<<<
622 13:59:41.334253 [ANA_INIT] DLL >>>>>>>>
623 13:59:41.337381 [ANA_INIT] flow end
624 13:59:41.340801 ============ LP4 DIFF to SE enter ============
625 13:59:41.344424 ============ LP4 DIFF to SE exit ============
626 13:59:41.347514 [ANA_INIT] <<<<<<<<<<<<<
627 13:59:41.350671 [Flow] Enable top DCM control >>>>>
628 13:59:41.354109 [Flow] Enable top DCM control <<<<<
629 13:59:41.357410 Enable DLL master slave shuffle
630 13:59:41.361174 ==============================================================
631 13:59:41.364156 Gating Mode config
632 13:59:41.371237 ==============================================================
633 13:59:41.371321 Config description:
634 13:59:41.381135 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 13:59:41.387789 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 13:59:41.394254 SELPH_MODE 0: By rank 1: By Phase
637 13:59:41.397634 ==============================================================
638 13:59:41.400966 GAT_TRACK_EN = 1
639 13:59:41.404393 RX_GATING_MODE = 2
640 13:59:41.407483 RX_GATING_TRACK_MODE = 2
641 13:59:41.410793 SELPH_MODE = 1
642 13:59:41.414448 PICG_EARLY_EN = 1
643 13:59:41.417831 VALID_LAT_VALUE = 1
644 13:59:41.421096 ==============================================================
645 13:59:41.424160 Enter into Gating configuration >>>>
646 13:59:41.427545 Exit from Gating configuration <<<<
647 13:59:41.431238 Enter into DVFS_PRE_config >>>>>
648 13:59:41.441447 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 13:59:41.444369 Exit from DVFS_PRE_config <<<<<
650 13:59:41.448352 Enter into PICG configuration >>>>
651 13:59:41.451075 Exit from PICG configuration <<<<
652 13:59:41.455010 [RX_INPUT] configuration >>>>>
653 13:59:41.458102 [RX_INPUT] configuration <<<<<
654 13:59:41.464356 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 13:59:41.468018 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 13:59:41.474388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 13:59:41.481326 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 13:59:41.488293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 13:59:41.494722 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 13:59:41.497947 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 13:59:41.501129 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 13:59:41.504680 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 13:59:41.507929 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 13:59:41.514868 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 13:59:41.517920 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 13:59:41.521927 ===================================
667 13:59:41.525140 LPDDR4 DRAM CONFIGURATION
668 13:59:41.527915 ===================================
669 13:59:41.527998 EX_ROW_EN[0] = 0x0
670 13:59:41.531438 EX_ROW_EN[1] = 0x0
671 13:59:41.531547 LP4Y_EN = 0x0
672 13:59:41.534763 WORK_FSP = 0x0
673 13:59:41.534845 WL = 0x2
674 13:59:41.538210 RL = 0x2
675 13:59:41.538293 BL = 0x2
676 13:59:41.541245 RPST = 0x0
677 13:59:41.541327 RD_PRE = 0x0
678 13:59:41.544986 WR_PRE = 0x1
679 13:59:41.545069 WR_PST = 0x0
680 13:59:41.548126 DBI_WR = 0x0
681 13:59:41.548207 DBI_RD = 0x0
682 13:59:41.551387 OTF = 0x1
683 13:59:41.554918 ===================================
684 13:59:41.558335 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 13:59:41.561543 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 13:59:41.568341 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 13:59:41.571552 ===================================
688 13:59:41.571688 LPDDR4 DRAM CONFIGURATION
689 13:59:41.574889 ===================================
690 13:59:41.578395 EX_ROW_EN[0] = 0x10
691 13:59:41.581645 EX_ROW_EN[1] = 0x0
692 13:59:41.581730 LP4Y_EN = 0x0
693 13:59:41.585103 WORK_FSP = 0x0
694 13:59:41.585188 WL = 0x2
695 13:59:41.588739 RL = 0x2
696 13:59:41.588824 BL = 0x2
697 13:59:41.591835 RPST = 0x0
698 13:59:41.591920 RD_PRE = 0x0
699 13:59:41.594651 WR_PRE = 0x1
700 13:59:41.594735 WR_PST = 0x0
701 13:59:41.598069 DBI_WR = 0x0
702 13:59:41.598154 DBI_RD = 0x0
703 13:59:41.601356 OTF = 0x1
704 13:59:41.604973 ===================================
705 13:59:41.611485 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 13:59:41.614779 nWR fixed to 40
707 13:59:41.614890 [ModeRegInit_LP4] CH0 RK0
708 13:59:41.618076 [ModeRegInit_LP4] CH0 RK1
709 13:59:41.621825 [ModeRegInit_LP4] CH1 RK0
710 13:59:41.621959 [ModeRegInit_LP4] CH1 RK1
711 13:59:41.625075 match AC timing 13
712 13:59:41.628708 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 13:59:41.631716 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 13:59:41.638230 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 13:59:41.641657 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 13:59:41.648748 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 13:59:41.648834 [EMI DOE] emi_dcm 0
718 13:59:41.651893 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 13:59:41.654954 ==
720 13:59:41.658541 Dram Type= 6, Freq= 0, CH_0, rank 0
721 13:59:41.661788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 13:59:41.661899 ==
723 13:59:41.665108 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 13:59:41.672020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 13:59:41.681498 [CA 0] Center 36 (6~67) winsize 62
726 13:59:41.685053 [CA 1] Center 36 (6~67) winsize 62
727 13:59:41.688322 [CA 2] Center 34 (4~65) winsize 62
728 13:59:41.691613 [CA 3] Center 33 (3~64) winsize 62
729 13:59:41.694917 [CA 4] Center 33 (3~64) winsize 62
730 13:59:41.698506 [CA 5] Center 32 (2~62) winsize 61
731 13:59:41.698588
732 13:59:41.701749 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 13:59:41.701831
734 13:59:41.705299 [CATrainingPosCal] consider 1 rank data
735 13:59:41.708546 u2DelayCellTimex100 = 270/100 ps
736 13:59:41.711920 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
737 13:59:41.715437 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
738 13:59:41.721716 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
739 13:59:41.725298 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
740 13:59:41.728589 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
741 13:59:41.732068 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
742 13:59:41.732151
743 13:59:41.735005 CA PerBit enable=1, Macro0, CA PI delay=32
744 13:59:41.735088
745 13:59:41.738522 [CBTSetCACLKResult] CA Dly = 32
746 13:59:41.738604 CS Dly: 4 (0~35)
747 13:59:41.738669 ==
748 13:59:41.741666 Dram Type= 6, Freq= 0, CH_0, rank 1
749 13:59:41.748681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 13:59:41.748767 ==
751 13:59:41.751895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 13:59:41.758504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 13:59:41.767966 [CA 0] Center 36 (6~67) winsize 62
754 13:59:41.771508 [CA 1] Center 36 (6~67) winsize 62
755 13:59:41.774649 [CA 2] Center 34 (4~65) winsize 62
756 13:59:41.777795 [CA 3] Center 33 (3~64) winsize 62
757 13:59:41.781391 [CA 4] Center 32 (2~63) winsize 62
758 13:59:41.784583 [CA 5] Center 32 (2~63) winsize 62
759 13:59:41.784665
760 13:59:41.788084 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 13:59:41.788172
762 13:59:41.790981 [CATrainingPosCal] consider 2 rank data
763 13:59:41.794363 u2DelayCellTimex100 = 270/100 ps
764 13:59:41.797704 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
765 13:59:41.801264 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
766 13:59:41.807848 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
767 13:59:41.811056 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
768 13:59:41.814494 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
769 13:59:41.817941 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
770 13:59:41.818023
771 13:59:41.821359 CA PerBit enable=1, Macro0, CA PI delay=32
772 13:59:41.821441
773 13:59:41.825025 [CBTSetCACLKResult] CA Dly = 32
774 13:59:41.825107 CS Dly: 5 (0~37)
775 13:59:41.825173
776 13:59:41.827825 ----->DramcWriteLeveling(PI) begin...
777 13:59:41.831934 ==
778 13:59:41.832017 Dram Type= 6, Freq= 0, CH_0, rank 0
779 13:59:41.836257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 13:59:41.839260 ==
781 13:59:41.839415 Write leveling (Byte 0): 33 => 33
782 13:59:41.843321 Write leveling (Byte 1): 30 => 30
783 13:59:41.847438 DramcWriteLeveling(PI) end<-----
784 13:59:41.847546
785 13:59:41.847667 ==
786 13:59:41.849984 Dram Type= 6, Freq= 0, CH_0, rank 0
787 13:59:41.853385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 13:59:41.853468 ==
789 13:59:41.857282 [Gating] SW mode calibration
790 13:59:41.864493 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 13:59:41.867806 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 13:59:41.874419 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 13:59:41.878102 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 13:59:41.880776 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
795 13:59:41.887822 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:59:41.891122 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:59:41.894504 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:59:41.901196 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:59:41.904752 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:59:41.907771 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:59:41.914321 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:59:41.917777 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:59:41.921117 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:59:41.928213 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:59:41.930973 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:59:41.934317 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:59:41.940994 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:59:41.944296 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
809 13:59:41.947687 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 13:59:41.951552 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
811 13:59:41.957910 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:59:41.960824 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 13:59:41.964370 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 13:59:41.970969 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 13:59:41.974394 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 13:59:41.977915 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 13:59:41.984323 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 13:59:41.988221 0 9 8 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (1 1)
819 13:59:41.991170 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
820 13:59:41.997396 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 13:59:42.000983 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 13:59:42.004601 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 13:59:42.011297 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 13:59:42.014691 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 13:59:42.017470 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
826 13:59:42.024368 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 1) (0 0)
827 13:59:42.027842 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:59:42.031342 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 13:59:42.037692 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 13:59:42.040974 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 13:59:42.044442 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 13:59:42.050837 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 13:59:42.054328 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
834 13:59:42.057859 0 11 8 | B1->B0 | 2e2e 4242 | 0 0 | (0 0) (0 0)
835 13:59:42.061380 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 13:59:42.067617 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 13:59:42.071091 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 13:59:42.074227 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 13:59:42.081184 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 13:59:42.084552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 13:59:42.088092 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 13:59:42.094252 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
843 13:59:42.097661 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:59:42.101265 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:59:42.107741 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:59:42.111410 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:59:42.115012 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:59:42.121261 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:59:42.124874 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:59:42.128471 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:59:42.131512 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:59:42.138118 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 13:59:42.141659 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 13:59:42.144936 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 13:59:42.151452 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 13:59:42.154804 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 13:59:42.158297 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 13:59:42.165067 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
859 13:59:42.168432 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 13:59:42.171870 Total UI for P1: 0, mck2ui 16
861 13:59:42.175034 best dqsien dly found for B0: ( 0, 14, 8)
862 13:59:42.178321 Total UI for P1: 0, mck2ui 16
863 13:59:42.182382 best dqsien dly found for B1: ( 0, 14, 10)
864 13:59:42.186041 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
865 13:59:42.188881 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
866 13:59:42.188963
867 13:59:42.192178 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
868 13:59:42.195721 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
869 13:59:42.198927 [Gating] SW calibration Done
870 13:59:42.199009 ==
871 13:59:42.202335 Dram Type= 6, Freq= 0, CH_0, rank 0
872 13:59:42.205455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 13:59:42.205542 ==
874 13:59:42.208894 RX Vref Scan: 0
875 13:59:42.208976
876 13:59:42.209041 RX Vref 0 -> 0, step: 1
877 13:59:42.209102
878 13:59:42.212703 RX Delay -130 -> 252, step: 16
879 13:59:42.215805 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
880 13:59:42.222626 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
881 13:59:42.225779 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 13:59:42.229320 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 13:59:42.232337 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 13:59:42.235769 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
885 13:59:42.242556 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
886 13:59:42.246454 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
887 13:59:42.249886 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
888 13:59:42.252809 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
889 13:59:42.255898 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
890 13:59:42.262590 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
891 13:59:42.265989 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
892 13:59:42.269217 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
893 13:59:42.272513 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
894 13:59:42.275846 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 13:59:42.275928 ==
896 13:59:42.279419 Dram Type= 6, Freq= 0, CH_0, rank 0
897 13:59:42.286456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 13:59:42.286540 ==
899 13:59:42.286606 DQS Delay:
900 13:59:42.289839 DQS0 = 0, DQS1 = 0
901 13:59:42.289921 DQM Delay:
902 13:59:42.289986 DQM0 = 90, DQM1 = 83
903 13:59:42.292953 DQ Delay:
904 13:59:42.296490 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
905 13:59:42.299704 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
906 13:59:42.303017 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
907 13:59:42.306141 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
908 13:59:42.306223
909 13:59:42.306289
910 13:59:42.306356 ==
911 13:59:42.309901 Dram Type= 6, Freq= 0, CH_0, rank 0
912 13:59:42.312845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 13:59:42.312928 ==
914 13:59:42.312993
915 13:59:42.313052
916 13:59:42.316120 TX Vref Scan disable
917 13:59:42.316202 == TX Byte 0 ==
918 13:59:42.322939 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
919 13:59:42.326546 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
920 13:59:42.326634 == TX Byte 1 ==
921 13:59:42.333015 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
922 13:59:42.336187 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
923 13:59:42.336272 ==
924 13:59:42.339532 Dram Type= 6, Freq= 0, CH_0, rank 0
925 13:59:42.343066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 13:59:42.343152 ==
927 13:59:42.357454 TX Vref=22, minBit 7, minWin=27, winSum=445
928 13:59:42.360861 TX Vref=24, minBit 8, minWin=27, winSum=454
929 13:59:42.364352 TX Vref=26, minBit 0, minWin=28, winSum=454
930 13:59:42.367466 TX Vref=28, minBit 0, minWin=28, winSum=454
931 13:59:42.370592 TX Vref=30, minBit 0, minWin=28, winSum=453
932 13:59:42.374094 TX Vref=32, minBit 4, minWin=28, winSum=453
933 13:59:42.380788 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 26
934 13:59:42.380873
935 13:59:42.384235 Final TX Range 1 Vref 26
936 13:59:42.384320
937 13:59:42.384406 ==
938 13:59:42.387359 Dram Type= 6, Freq= 0, CH_0, rank 0
939 13:59:42.390854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 13:59:42.390939 ==
941 13:59:42.391029
942 13:59:42.391110
943 13:59:42.394048 TX Vref Scan disable
944 13:59:42.397754 == TX Byte 0 ==
945 13:59:42.400510 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
946 13:59:42.404148 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
947 13:59:42.407759 == TX Byte 1 ==
948 13:59:42.410940 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
949 13:59:42.414336 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
950 13:59:42.414421
951 13:59:42.417570 [DATLAT]
952 13:59:42.417654 Freq=800, CH0 RK0
953 13:59:42.417740
954 13:59:42.420921 DATLAT Default: 0xa
955 13:59:42.421005 0, 0xFFFF, sum = 0
956 13:59:42.424410 1, 0xFFFF, sum = 0
957 13:59:42.424496 2, 0xFFFF, sum = 0
958 13:59:42.427522 3, 0xFFFF, sum = 0
959 13:59:42.427666 4, 0xFFFF, sum = 0
960 13:59:42.431076 5, 0xFFFF, sum = 0
961 13:59:42.431162 6, 0xFFFF, sum = 0
962 13:59:42.434248 7, 0xFFFF, sum = 0
963 13:59:42.434334 8, 0xFFFF, sum = 0
964 13:59:42.437476 9, 0x0, sum = 1
965 13:59:42.437561 10, 0x0, sum = 2
966 13:59:42.440857 11, 0x0, sum = 3
967 13:59:42.440942 12, 0x0, sum = 4
968 13:59:42.444257 best_step = 10
969 13:59:42.444341
970 13:59:42.444426 ==
971 13:59:42.447641 Dram Type= 6, Freq= 0, CH_0, rank 0
972 13:59:42.450740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 13:59:42.450826 ==
974 13:59:42.454648 RX Vref Scan: 1
975 13:59:42.454732
976 13:59:42.454826 Set Vref Range= 32 -> 127
977 13:59:42.454907
978 13:59:42.457407 RX Vref 32 -> 127, step: 1
979 13:59:42.457491
980 13:59:42.461371 RX Delay -79 -> 252, step: 8
981 13:59:42.461455
982 13:59:42.464181 Set Vref, RX VrefLevel [Byte0]: 32
983 13:59:42.467439 [Byte1]: 32
984 13:59:42.467522
985 13:59:42.470929 Set Vref, RX VrefLevel [Byte0]: 33
986 13:59:42.474384 [Byte1]: 33
987 13:59:42.474467
988 13:59:42.477625 Set Vref, RX VrefLevel [Byte0]: 34
989 13:59:42.480768 [Byte1]: 34
990 13:59:42.485550
991 13:59:42.485632 Set Vref, RX VrefLevel [Byte0]: 35
992 13:59:42.488157 [Byte1]: 35
993 13:59:42.492916
994 13:59:42.492998 Set Vref, RX VrefLevel [Byte0]: 36
995 13:59:42.496336 [Byte1]: 36
996 13:59:42.500578
997 13:59:42.500660 Set Vref, RX VrefLevel [Byte0]: 37
998 13:59:42.503812 [Byte1]: 37
999 13:59:42.508441
1000 13:59:42.508524 Set Vref, RX VrefLevel [Byte0]: 38
1001 13:59:42.511175 [Byte1]: 38
1002 13:59:42.515361
1003 13:59:42.515469 Set Vref, RX VrefLevel [Byte0]: 39
1004 13:59:42.518645 [Byte1]: 39
1005 13:59:42.523047
1006 13:59:42.523129 Set Vref, RX VrefLevel [Byte0]: 40
1007 13:59:42.526266 [Byte1]: 40
1008 13:59:42.530605
1009 13:59:42.530687 Set Vref, RX VrefLevel [Byte0]: 41
1010 13:59:42.533550 [Byte1]: 41
1011 13:59:42.537659
1012 13:59:42.537742 Set Vref, RX VrefLevel [Byte0]: 42
1013 13:59:42.541110 [Byte1]: 42
1014 13:59:42.545412
1015 13:59:42.545494 Set Vref, RX VrefLevel [Byte0]: 43
1016 13:59:42.548880 [Byte1]: 43
1017 13:59:42.552848
1018 13:59:42.552931 Set Vref, RX VrefLevel [Byte0]: 44
1019 13:59:42.556086 [Byte1]: 44
1020 13:59:42.560710
1021 13:59:42.560792 Set Vref, RX VrefLevel [Byte0]: 45
1022 13:59:42.563953 [Byte1]: 45
1023 13:59:42.567944
1024 13:59:42.568026 Set Vref, RX VrefLevel [Byte0]: 46
1025 13:59:42.571056 [Byte1]: 46
1026 13:59:42.575467
1027 13:59:42.575548 Set Vref, RX VrefLevel [Byte0]: 47
1028 13:59:42.578855 [Byte1]: 47
1029 13:59:42.582982
1030 13:59:42.583063 Set Vref, RX VrefLevel [Byte0]: 48
1031 13:59:42.586423 [Byte1]: 48
1032 13:59:42.590424
1033 13:59:42.590505 Set Vref, RX VrefLevel [Byte0]: 49
1034 13:59:42.594008 [Byte1]: 49
1035 13:59:42.598606
1036 13:59:42.598686 Set Vref, RX VrefLevel [Byte0]: 50
1037 13:59:42.601555 [Byte1]: 50
1038 13:59:42.605532
1039 13:59:42.605613 Set Vref, RX VrefLevel [Byte0]: 51
1040 13:59:42.609181 [Byte1]: 51
1041 13:59:42.613082
1042 13:59:42.613162 Set Vref, RX VrefLevel [Byte0]: 52
1043 13:59:42.616421 [Byte1]: 52
1044 13:59:42.621101
1045 13:59:42.621182 Set Vref, RX VrefLevel [Byte0]: 53
1046 13:59:42.624003 [Byte1]: 53
1047 13:59:42.629036
1048 13:59:42.629155 Set Vref, RX VrefLevel [Byte0]: 54
1049 13:59:42.631655 [Byte1]: 54
1050 13:59:42.636257
1051 13:59:42.636338 Set Vref, RX VrefLevel [Byte0]: 55
1052 13:59:42.639761 [Byte1]: 55
1053 13:59:42.643640
1054 13:59:42.643721 Set Vref, RX VrefLevel [Byte0]: 56
1055 13:59:42.646959 [Byte1]: 56
1056 13:59:42.650886
1057 13:59:42.650967 Set Vref, RX VrefLevel [Byte0]: 57
1058 13:59:42.654751 [Byte1]: 57
1059 13:59:42.658570
1060 13:59:42.658650 Set Vref, RX VrefLevel [Byte0]: 58
1061 13:59:42.661854 [Byte1]: 58
1062 13:59:42.666503
1063 13:59:42.666584 Set Vref, RX VrefLevel [Byte0]: 59
1064 13:59:42.669562 [Byte1]: 59
1065 13:59:42.673750
1066 13:59:42.673830 Set Vref, RX VrefLevel [Byte0]: 60
1067 13:59:42.677052 [Byte1]: 60
1068 13:59:42.681032
1069 13:59:42.681113 Set Vref, RX VrefLevel [Byte0]: 61
1070 13:59:42.684629 [Byte1]: 61
1071 13:59:42.688772
1072 13:59:42.688853 Set Vref, RX VrefLevel [Byte0]: 62
1073 13:59:42.692027 [Byte1]: 62
1074 13:59:42.696492
1075 13:59:42.696572 Set Vref, RX VrefLevel [Byte0]: 63
1076 13:59:42.699916 [Byte1]: 63
1077 13:59:42.703796
1078 13:59:42.703877 Set Vref, RX VrefLevel [Byte0]: 64
1079 13:59:42.707760 [Byte1]: 64
1080 13:59:42.711313
1081 13:59:42.711394 Set Vref, RX VrefLevel [Byte0]: 65
1082 13:59:42.714667 [Byte1]: 65
1083 13:59:42.719056
1084 13:59:42.719137 Set Vref, RX VrefLevel [Byte0]: 66
1085 13:59:42.722601 [Byte1]: 66
1086 13:59:42.726529
1087 13:59:42.726610 Set Vref, RX VrefLevel [Byte0]: 67
1088 13:59:42.729805 [Byte1]: 67
1089 13:59:42.734013
1090 13:59:42.734094 Set Vref, RX VrefLevel [Byte0]: 68
1091 13:59:42.737267 [Byte1]: 68
1092 13:59:42.741625
1093 13:59:42.741705 Set Vref, RX VrefLevel [Byte0]: 69
1094 13:59:42.744844 [Byte1]: 69
1095 13:59:42.748993
1096 13:59:42.749074 Set Vref, RX VrefLevel [Byte0]: 70
1097 13:59:42.752424 [Byte1]: 70
1098 13:59:42.757005
1099 13:59:42.757085 Set Vref, RX VrefLevel [Byte0]: 71
1100 13:59:42.759815 [Byte1]: 71
1101 13:59:42.764354
1102 13:59:42.764435 Set Vref, RX VrefLevel [Byte0]: 72
1103 13:59:42.767601 [Byte1]: 72
1104 13:59:42.771622
1105 13:59:42.771703 Set Vref, RX VrefLevel [Byte0]: 73
1106 13:59:42.775122 [Byte1]: 73
1107 13:59:42.779874
1108 13:59:42.779954 Set Vref, RX VrefLevel [Byte0]: 74
1109 13:59:42.782383 [Byte1]: 74
1110 13:59:42.786869
1111 13:59:42.789994 Set Vref, RX VrefLevel [Byte0]: 75
1112 13:59:42.790075 [Byte1]: 75
1113 13:59:42.794640
1114 13:59:42.794721 Set Vref, RX VrefLevel [Byte0]: 76
1115 13:59:42.797797 [Byte1]: 76
1116 13:59:42.801797
1117 13:59:42.801878 Set Vref, RX VrefLevel [Byte0]: 77
1118 13:59:42.805446 [Byte1]: 77
1119 13:59:42.809486
1120 13:59:42.809567 Final RX Vref Byte 0 = 56 to rank0
1121 13:59:42.813211 Final RX Vref Byte 1 = 57 to rank0
1122 13:59:42.816123 Final RX Vref Byte 0 = 56 to rank1
1123 13:59:42.819908 Final RX Vref Byte 1 = 57 to rank1==
1124 13:59:42.823135 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 13:59:42.830033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 13:59:42.830118 ==
1127 13:59:42.830182 DQS Delay:
1128 13:59:42.830241 DQS0 = 0, DQS1 = 0
1129 13:59:42.833494 DQM Delay:
1130 13:59:42.833575 DQM0 = 92, DQM1 = 84
1131 13:59:42.836548 DQ Delay:
1132 13:59:42.839576 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1133 13:59:42.842921 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1134 13:59:42.843003 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1135 13:59:42.849432 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1136 13:59:42.849514
1137 13:59:42.849577
1138 13:59:42.856083 [DQSOSCAuto] RK0, (LSB)MR18= 0x5146, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
1139 13:59:42.859814 CH0 RK0: MR19=606, MR18=5146
1140 13:59:42.866773 CH0_RK0: MR19=0x606, MR18=0x5146, DQSOSC=389, MR23=63, INC=97, DEC=65
1141 13:59:42.866850
1142 13:59:42.870237 ----->DramcWriteLeveling(PI) begin...
1143 13:59:42.870337 ==
1144 13:59:42.873585 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 13:59:42.876638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 13:59:42.876712 ==
1147 13:59:42.879540 Write leveling (Byte 0): 33 => 33
1148 13:59:42.883195 Write leveling (Byte 1): 28 => 28
1149 13:59:42.887036 DramcWriteLeveling(PI) end<-----
1150 13:59:42.887117
1151 13:59:42.887181 ==
1152 13:59:42.889830 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 13:59:42.893096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 13:59:42.893178 ==
1155 13:59:42.896726 [Gating] SW mode calibration
1156 13:59:42.903211 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 13:59:42.947522 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 13:59:42.947652 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 13:59:42.947931 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1160 13:59:42.947997 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1161 13:59:42.948057 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:59:42.948532 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:59:42.948794 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:59:42.948873 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:59:42.948948 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:59:42.949009 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:59:42.978000 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:59:42.978264 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:59:42.978516 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:59:42.978761 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:59:42.978826 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:59:42.979438 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:59:42.981964 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:59:42.985197 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:59:42.988570 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:59:42.991875 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1177 13:59:42.995184 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:59:43.002030 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:59:43.005325 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:59:43.009050 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:59:43.015214 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:59:43.018632 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:59:43.022221 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:59:43.028594 0 9 8 | B1->B0 | 3131 2b2b | 0 1 | (0 0) (1 1)
1185 13:59:43.032076 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 13:59:43.035337 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 13:59:43.042331 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 13:59:43.045310 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 13:59:43.048629 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 13:59:43.052369 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 13:59:43.058853 0 10 4 | B1->B0 | 3333 3333 | 1 1 | (1 1) (0 1)
1192 13:59:43.062383 0 10 8 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
1193 13:59:43.065767 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 13:59:43.072533 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 13:59:43.076481 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 13:59:43.079757 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 13:59:43.083437 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 13:59:43.090479 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 13:59:43.094336 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1200 13:59:43.097255 0 11 8 | B1->B0 | 3b3b 3939 | 0 0 | (0 0) (0 0)
1201 13:59:43.100744 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 13:59:43.108037 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 13:59:43.110711 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 13:59:43.114442 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 13:59:43.120899 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 13:59:43.124312 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 13:59:43.127543 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 13:59:43.134262 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 13:59:43.137571 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1210 13:59:43.140828 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:59:43.147305 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:59:43.151017 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:59:43.153915 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:59:43.157422 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:59:43.164512 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 13:59:43.167512 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 13:59:43.170968 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 13:59:43.177610 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 13:59:43.181200 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 13:59:43.183834 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 13:59:43.190604 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 13:59:43.193893 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 13:59:43.197669 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 13:59:43.204422 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1225 13:59:43.204504 Total UI for P1: 0, mck2ui 16
1226 13:59:43.211086 best dqsien dly found for B1: ( 0, 14, 6)
1227 13:59:43.214054 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 13:59:43.217977 Total UI for P1: 0, mck2ui 16
1229 13:59:43.221011 best dqsien dly found for B0: ( 0, 14, 8)
1230 13:59:43.224699 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1231 13:59:43.227586 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1232 13:59:43.227711
1233 13:59:43.231033 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1234 13:59:43.234474 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1235 13:59:43.238069 [Gating] SW calibration Done
1236 13:59:43.238151 ==
1237 13:59:43.240695 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 13:59:43.244399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 13:59:43.244481 ==
1240 13:59:43.247514 RX Vref Scan: 0
1241 13:59:43.247619
1242 13:59:43.250901 RX Vref 0 -> 0, step: 1
1243 13:59:43.250982
1244 13:59:43.251046 RX Delay -130 -> 252, step: 16
1245 13:59:43.257721 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1246 13:59:43.261112 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1247 13:59:43.264756 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1248 13:59:43.267978 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1249 13:59:43.271282 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1250 13:59:43.277708 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1251 13:59:43.280947 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1252 13:59:43.284330 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1253 13:59:43.288095 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1254 13:59:43.290966 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1255 13:59:43.297647 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1256 13:59:43.301030 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1257 13:59:43.304532 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1258 13:59:43.308178 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1259 13:59:43.311546 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1260 13:59:43.318275 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1261 13:59:43.318357 ==
1262 13:59:43.321235 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 13:59:43.324563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 13:59:43.324645 ==
1265 13:59:43.324710 DQS Delay:
1266 13:59:43.327913 DQS0 = 0, DQS1 = 0
1267 13:59:43.327993 DQM Delay:
1268 13:59:43.331352 DQM0 = 92, DQM1 = 81
1269 13:59:43.331432 DQ Delay:
1270 13:59:43.334750 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1271 13:59:43.338314 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1272 13:59:43.342036 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1273 13:59:43.344957 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1274 13:59:43.345039
1275 13:59:43.345102
1276 13:59:43.345161 ==
1277 13:59:43.347945 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 13:59:43.351350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 13:59:43.351433 ==
1280 13:59:43.351497
1281 13:59:43.351555
1282 13:59:43.355009 TX Vref Scan disable
1283 13:59:43.357767 == TX Byte 0 ==
1284 13:59:43.361724 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1285 13:59:43.365167 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1286 13:59:43.367758 == TX Byte 1 ==
1287 13:59:43.371316 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1288 13:59:43.375114 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1289 13:59:43.375195 ==
1290 13:59:43.378185 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 13:59:43.384469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 13:59:43.384551 ==
1293 13:59:43.396622 TX Vref=22, minBit 8, minWin=27, winSum=446
1294 13:59:43.400258 TX Vref=24, minBit 8, minWin=27, winSum=449
1295 13:59:43.403564 TX Vref=26, minBit 1, minWin=28, winSum=457
1296 13:59:43.406896 TX Vref=28, minBit 4, minWin=28, winSum=457
1297 13:59:43.410486 TX Vref=30, minBit 7, minWin=28, winSum=459
1298 13:59:43.413578 TX Vref=32, minBit 7, minWin=28, winSum=457
1299 13:59:43.420445 [TxChooseVref] Worse bit 7, Min win 28, Win sum 459, Final Vref 30
1300 13:59:43.420528
1301 13:59:43.423796 Final TX Range 1 Vref 30
1302 13:59:43.423878
1303 13:59:43.423941 ==
1304 13:59:43.427305 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 13:59:43.430634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 13:59:43.430715 ==
1307 13:59:43.430778
1308 13:59:43.430836
1309 13:59:43.434394 TX Vref Scan disable
1310 13:59:43.437334 == TX Byte 0 ==
1311 13:59:43.440869 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1312 13:59:43.444059 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1313 13:59:43.447128 == TX Byte 1 ==
1314 13:59:43.450364 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1315 13:59:43.453788 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1316 13:59:43.453872
1317 13:59:43.457000 [DATLAT]
1318 13:59:43.457081 Freq=800, CH0 RK1
1319 13:59:43.457144
1320 13:59:43.460690 DATLAT Default: 0xa
1321 13:59:43.460843 0, 0xFFFF, sum = 0
1322 13:59:43.464039 1, 0xFFFF, sum = 0
1323 13:59:43.464122 2, 0xFFFF, sum = 0
1324 13:59:43.467571 3, 0xFFFF, sum = 0
1325 13:59:43.467690 4, 0xFFFF, sum = 0
1326 13:59:43.470392 5, 0xFFFF, sum = 0
1327 13:59:43.470504 6, 0xFFFF, sum = 0
1328 13:59:43.473893 7, 0xFFFF, sum = 0
1329 13:59:43.473999 8, 0xFFFF, sum = 0
1330 13:59:43.477052 9, 0x0, sum = 1
1331 13:59:43.477155 10, 0x0, sum = 2
1332 13:59:43.480693 11, 0x0, sum = 3
1333 13:59:43.480797 12, 0x0, sum = 4
1334 13:59:43.484219 best_step = 10
1335 13:59:43.484321
1336 13:59:43.484410 ==
1337 13:59:43.487003 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 13:59:43.490983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 13:59:43.491083 ==
1340 13:59:43.493937 RX Vref Scan: 0
1341 13:59:43.494036
1342 13:59:43.494127 RX Vref 0 -> 0, step: 1
1343 13:59:43.494222
1344 13:59:43.497699 RX Delay -95 -> 252, step: 8
1345 13:59:43.500663 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1346 13:59:43.507236 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1347 13:59:43.510869 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1348 13:59:43.514133 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1349 13:59:43.517368 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1350 13:59:43.521042 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1351 13:59:43.527246 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1352 13:59:43.530734 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1353 13:59:43.534491 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1354 13:59:43.537812 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1355 13:59:43.540906 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1356 13:59:43.547391 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1357 13:59:43.550669 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1358 13:59:43.554026 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1359 13:59:43.557583 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1360 13:59:43.560661 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1361 13:59:43.560775 ==
1362 13:59:43.564341 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 13:59:43.571321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 13:59:43.571403 ==
1365 13:59:43.571467 DQS Delay:
1366 13:59:43.574416 DQS0 = 0, DQS1 = 0
1367 13:59:43.574497 DQM Delay:
1368 13:59:43.577325 DQM0 = 93, DQM1 = 83
1369 13:59:43.577406 DQ Delay:
1370 13:59:43.580909 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1371 13:59:43.584195 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1372 13:59:43.587621 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1373 13:59:43.590933 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =92
1374 13:59:43.591014
1375 13:59:43.591077
1376 13:59:43.597310 [DQSOSCAuto] RK1, (LSB)MR18= 0x4212, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1377 13:59:43.601285 CH0 RK1: MR19=606, MR18=4212
1378 13:59:43.607741 CH0_RK1: MR19=0x606, MR18=0x4212, DQSOSC=393, MR23=63, INC=95, DEC=63
1379 13:59:43.610977 [RxdqsGatingPostProcess] freq 800
1380 13:59:43.614687 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 13:59:43.618002 Pre-setting of DQS Precalculation
1382 13:59:43.624316 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 13:59:43.624399 ==
1384 13:59:43.627934 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 13:59:43.631086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 13:59:43.631168 ==
1387 13:59:43.637676 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 13:59:43.644731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 13:59:43.651973 [CA 0] Center 36 (6~67) winsize 62
1390 13:59:43.654949 [CA 1] Center 36 (6~67) winsize 62
1391 13:59:43.659049 [CA 2] Center 34 (4~65) winsize 62
1392 13:59:43.662195 [CA 3] Center 34 (4~65) winsize 62
1393 13:59:43.665418 [CA 4] Center 34 (4~65) winsize 62
1394 13:59:43.668443 [CA 5] Center 34 (4~64) winsize 61
1395 13:59:43.668525
1396 13:59:43.671898 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1397 13:59:43.671980
1398 13:59:43.675204 [CATrainingPosCal] consider 1 rank data
1399 13:59:43.678788 u2DelayCellTimex100 = 270/100 ps
1400 13:59:43.681856 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1401 13:59:43.684904 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1402 13:59:43.691950 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 13:59:43.694867 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1404 13:59:43.698431 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1405 13:59:43.701791 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1406 13:59:43.701872
1407 13:59:43.705049 CA PerBit enable=1, Macro0, CA PI delay=34
1408 13:59:43.705137
1409 13:59:43.708451 [CBTSetCACLKResult] CA Dly = 34
1410 13:59:43.708533 CS Dly: 5 (0~36)
1411 13:59:43.708597 ==
1412 13:59:43.711859 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 13:59:43.718255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 13:59:43.718337 ==
1415 13:59:43.721675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 13:59:43.728696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 13:59:43.738538 [CA 0] Center 36 (6~67) winsize 62
1418 13:59:43.741935 [CA 1] Center 37 (6~68) winsize 63
1419 13:59:43.745751 [CA 2] Center 35 (5~66) winsize 62
1420 13:59:43.749168 [CA 3] Center 34 (4~65) winsize 62
1421 13:59:43.752697 [CA 4] Center 35 (4~66) winsize 63
1422 13:59:43.756672 [CA 5] Center 34 (4~65) winsize 62
1423 13:59:43.756778
1424 13:59:43.760123 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1425 13:59:43.760226
1426 13:59:43.763565 [CATrainingPosCal] consider 2 rank data
1427 13:59:43.763695 u2DelayCellTimex100 = 270/100 ps
1428 13:59:43.767674 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 13:59:43.774516 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 13:59:43.778010 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1431 13:59:43.781199 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 13:59:43.784691 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1433 13:59:43.788139 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1434 13:59:43.788218
1435 13:59:43.791194 CA PerBit enable=1, Macro0, CA PI delay=34
1436 13:59:43.791295
1437 13:59:43.794875 [CBTSetCACLKResult] CA Dly = 34
1438 13:59:43.794973 CS Dly: 6 (0~39)
1439 13:59:43.795061
1440 13:59:43.798019 ----->DramcWriteLeveling(PI) begin...
1441 13:59:43.801734 ==
1442 13:59:43.801836 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 13:59:43.808233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 13:59:43.808337 ==
1445 13:59:43.811170 Write leveling (Byte 0): 27 => 27
1446 13:59:43.815134 Write leveling (Byte 1): 29 => 29
1447 13:59:43.815243 DramcWriteLeveling(PI) end<-----
1448 13:59:43.818175
1449 13:59:43.818275 ==
1450 13:59:43.821453 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 13:59:43.824942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 13:59:43.825059 ==
1453 13:59:43.827970 [Gating] SW mode calibration
1454 13:59:43.834609 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 13:59:43.838293 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 13:59:43.844679 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1457 13:59:43.848255 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1458 13:59:43.851649 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:59:43.858095 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:59:43.861436 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:59:43.864825 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:59:43.871451 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:59:43.875271 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:59:43.878046 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:59:43.885024 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:59:43.888501 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:59:43.892182 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:59:43.894713 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:59:43.901625 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:59:43.904847 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:59:43.908080 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:59:43.915054 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1473 13:59:43.918170 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1474 13:59:43.921642 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:59:43.928090 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:59:43.932160 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:59:43.935496 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:59:43.942038 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 13:59:43.945013 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 13:59:43.948479 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:59:43.955217 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1482 13:59:43.958436 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1483 13:59:43.961564 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 13:59:43.968019 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 13:59:43.971512 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 13:59:43.975202 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 13:59:43.978209 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 13:59:43.984822 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1489 13:59:43.988120 0 10 4 | B1->B0 | 3333 2e2e | 0 0 | (1 1) (0 1)
1490 13:59:43.991691 0 10 8 | B1->B0 | 2828 2323 | 1 0 | (0 0) (0 0)
1491 13:59:43.998389 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:59:44.001943 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 13:59:44.004654 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 13:59:44.011491 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 13:59:44.014816 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 13:59:44.018206 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 13:59:44.024729 0 11 4 | B1->B0 | 2929 3636 | 1 0 | (0 0) (0 0)
1498 13:59:44.028261 0 11 8 | B1->B0 | 3938 4646 | 1 0 | (0 0) (0 0)
1499 13:59:44.031440 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 13:59:44.038276 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 13:59:44.041585 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 13:59:44.045117 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 13:59:44.051766 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 13:59:44.055400 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1505 13:59:44.058411 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1506 13:59:44.065114 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:59:44.068649 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:59:44.071555 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:59:44.075339 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:59:44.081867 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:59:44.084969 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:59:44.088086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:59:44.094774 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:59:44.098570 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 13:59:44.101492 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 13:59:44.108172 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 13:59:44.111589 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 13:59:44.114926 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 13:59:44.121666 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 13:59:44.125070 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1521 13:59:44.128459 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 13:59:44.132126 Total UI for P1: 0, mck2ui 16
1523 13:59:44.135513 best dqsien dly found for B0: ( 0, 14, 2)
1524 13:59:44.138737 Total UI for P1: 0, mck2ui 16
1525 13:59:44.142493 best dqsien dly found for B1: ( 0, 14, 0)
1526 13:59:44.145974 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1527 13:59:44.148554 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1528 13:59:44.148636
1529 13:59:44.152350 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1530 13:59:44.155200 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1531 13:59:44.158723 [Gating] SW calibration Done
1532 13:59:44.158804 ==
1533 13:59:44.162260 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 13:59:44.168467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1535 13:59:44.168550 ==
1536 13:59:44.168615 RX Vref Scan: 0
1537 13:59:44.168674
1538 13:59:44.171911 RX Vref 0 -> 0, step: 1
1539 13:59:44.171993
1540 13:59:44.175486 RX Delay -130 -> 252, step: 16
1541 13:59:44.178413 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1542 13:59:44.181991 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1543 13:59:44.186023 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1544 13:59:44.188812 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1545 13:59:44.195396 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1546 13:59:44.198628 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1547 13:59:44.202093 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1548 13:59:44.205578 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1549 13:59:44.209296 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1550 13:59:44.215287 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1551 13:59:44.218918 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1552 13:59:44.222258 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1553 13:59:44.225445 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1554 13:59:44.229029 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1555 13:59:44.235260 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1556 13:59:44.238639 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1557 13:59:44.238724 ==
1558 13:59:44.242076 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 13:59:44.245514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 13:59:44.245599 ==
1561 13:59:44.248317 DQS Delay:
1562 13:59:44.248401 DQS0 = 0, DQS1 = 0
1563 13:59:44.248487 DQM Delay:
1564 13:59:44.251763 DQM0 = 93, DQM1 = 87
1565 13:59:44.251847 DQ Delay:
1566 13:59:44.255527 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1567 13:59:44.258655 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1568 13:59:44.261557 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1569 13:59:44.265494 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1570 13:59:44.265578
1571 13:59:44.265664
1572 13:59:44.268430 ==
1573 13:59:44.268515 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 13:59:44.275313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 13:59:44.275398 ==
1576 13:59:44.275499
1577 13:59:44.275603
1578 13:59:44.275719 TX Vref Scan disable
1579 13:59:44.279232 == TX Byte 0 ==
1580 13:59:44.282779 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1581 13:59:44.285693 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1582 13:59:44.289231 == TX Byte 1 ==
1583 13:59:44.292148 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1584 13:59:44.295525 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1585 13:59:44.299263 ==
1586 13:59:44.302325 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 13:59:44.305711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 13:59:44.305796 ==
1589 13:59:44.318450 TX Vref=22, minBit 1, minWin=26, winSum=436
1590 13:59:44.322212 TX Vref=24, minBit 0, minWin=26, winSum=442
1591 13:59:44.325345 TX Vref=26, minBit 1, minWin=27, winSum=444
1592 13:59:44.329386 TX Vref=28, minBit 0, minWin=27, winSum=446
1593 13:59:44.332229 TX Vref=30, minBit 1, minWin=27, winSum=449
1594 13:59:44.335484 TX Vref=32, minBit 1, minWin=27, winSum=446
1595 13:59:44.342308 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 30
1596 13:59:44.342393
1597 13:59:44.345469 Final TX Range 1 Vref 30
1598 13:59:44.345554
1599 13:59:44.345639 ==
1600 13:59:44.348963 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 13:59:44.352518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 13:59:44.352620 ==
1603 13:59:44.352706
1604 13:59:44.352787
1605 13:59:44.355450 TX Vref Scan disable
1606 13:59:44.358844 == TX Byte 0 ==
1607 13:59:44.362244 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1608 13:59:44.365315 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1609 13:59:44.369105 == TX Byte 1 ==
1610 13:59:44.371933 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1611 13:59:44.375400 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1612 13:59:44.375497
1613 13:59:44.379102 [DATLAT]
1614 13:59:44.379175 Freq=800, CH1 RK0
1615 13:59:44.379237
1616 13:59:44.382461 DATLAT Default: 0xa
1617 13:59:44.382565 0, 0xFFFF, sum = 0
1618 13:59:44.385754 1, 0xFFFF, sum = 0
1619 13:59:44.385825 2, 0xFFFF, sum = 0
1620 13:59:44.388863 3, 0xFFFF, sum = 0
1621 13:59:44.388934 4, 0xFFFF, sum = 0
1622 13:59:44.392468 5, 0xFFFF, sum = 0
1623 13:59:44.392539 6, 0xFFFF, sum = 0
1624 13:59:44.395510 7, 0xFFFF, sum = 0
1625 13:59:44.395614 8, 0xFFFF, sum = 0
1626 13:59:44.399512 9, 0x0, sum = 1
1627 13:59:44.399616 10, 0x0, sum = 2
1628 13:59:44.402532 11, 0x0, sum = 3
1629 13:59:44.402601 12, 0x0, sum = 4
1630 13:59:44.402671 best_step = 10
1631 13:59:44.405661
1632 13:59:44.405756 ==
1633 13:59:44.408918 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 13:59:44.412182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 13:59:44.412264 ==
1636 13:59:44.412325 RX Vref Scan: 1
1637 13:59:44.412383
1638 13:59:44.415527 Set Vref Range= 32 -> 127
1639 13:59:44.415601
1640 13:59:44.419092 RX Vref 32 -> 127, step: 1
1641 13:59:44.419192
1642 13:59:44.422704 RX Delay -79 -> 252, step: 8
1643 13:59:44.422816
1644 13:59:44.425859 Set Vref, RX VrefLevel [Byte0]: 32
1645 13:59:44.429182 [Byte1]: 32
1646 13:59:44.429286
1647 13:59:44.432546 Set Vref, RX VrefLevel [Byte0]: 33
1648 13:59:44.435879 [Byte1]: 33
1649 13:59:44.435951
1650 13:59:44.439043 Set Vref, RX VrefLevel [Byte0]: 34
1651 13:59:44.442510 [Byte1]: 34
1652 13:59:44.445796
1653 13:59:44.445867 Set Vref, RX VrefLevel [Byte0]: 35
1654 13:59:44.449176 [Byte1]: 35
1655 13:59:44.453077
1656 13:59:44.453173 Set Vref, RX VrefLevel [Byte0]: 36
1657 13:59:44.456275 [Byte1]: 36
1658 13:59:44.460742
1659 13:59:44.460844 Set Vref, RX VrefLevel [Byte0]: 37
1660 13:59:44.464058 [Byte1]: 37
1661 13:59:44.468823
1662 13:59:44.468920 Set Vref, RX VrefLevel [Byte0]: 38
1663 13:59:44.471827 [Byte1]: 38
1664 13:59:44.475589
1665 13:59:44.475718 Set Vref, RX VrefLevel [Byte0]: 39
1666 13:59:44.478958 [Byte1]: 39
1667 13:59:44.483180
1668 13:59:44.483255 Set Vref, RX VrefLevel [Byte0]: 40
1669 13:59:44.486520 [Byte1]: 40
1670 13:59:44.490952
1671 13:59:44.491032 Set Vref, RX VrefLevel [Byte0]: 41
1672 13:59:44.494062 [Byte1]: 41
1673 13:59:44.498250
1674 13:59:44.498320 Set Vref, RX VrefLevel [Byte0]: 42
1675 13:59:44.501677 [Byte1]: 42
1676 13:59:44.505802
1677 13:59:44.505897 Set Vref, RX VrefLevel [Byte0]: 43
1678 13:59:44.509716 [Byte1]: 43
1679 13:59:44.513750
1680 13:59:44.513827 Set Vref, RX VrefLevel [Byte0]: 44
1681 13:59:44.517233 [Byte1]: 44
1682 13:59:44.521604
1683 13:59:44.521762 Set Vref, RX VrefLevel [Byte0]: 45
1684 13:59:44.524450 [Byte1]: 45
1685 13:59:44.528691
1686 13:59:44.528772 Set Vref, RX VrefLevel [Byte0]: 46
1687 13:59:44.532354 [Byte1]: 46
1688 13:59:44.536147
1689 13:59:44.536229 Set Vref, RX VrefLevel [Byte0]: 47
1690 13:59:44.539761 [Byte1]: 47
1691 13:59:44.543578
1692 13:59:44.543682 Set Vref, RX VrefLevel [Byte0]: 48
1693 13:59:44.547074 [Byte1]: 48
1694 13:59:44.551393
1695 13:59:44.551474 Set Vref, RX VrefLevel [Byte0]: 49
1696 13:59:44.554919 [Byte1]: 49
1697 13:59:44.559377
1698 13:59:44.559458 Set Vref, RX VrefLevel [Byte0]: 50
1699 13:59:44.562187 [Byte1]: 50
1700 13:59:44.566186
1701 13:59:44.566267 Set Vref, RX VrefLevel [Byte0]: 51
1702 13:59:44.569622 [Byte1]: 51
1703 13:59:44.573843
1704 13:59:44.573924 Set Vref, RX VrefLevel [Byte0]: 52
1705 13:59:44.577238 [Byte1]: 52
1706 13:59:44.581504
1707 13:59:44.581587 Set Vref, RX VrefLevel [Byte0]: 53
1708 13:59:44.584916 [Byte1]: 53
1709 13:59:44.589255
1710 13:59:44.589336 Set Vref, RX VrefLevel [Byte0]: 54
1711 13:59:44.592572 [Byte1]: 54
1712 13:59:44.596635
1713 13:59:44.596716 Set Vref, RX VrefLevel [Byte0]: 55
1714 13:59:44.599878 [Byte1]: 55
1715 13:59:44.604642
1716 13:59:44.604723 Set Vref, RX VrefLevel [Byte0]: 56
1717 13:59:44.607396 [Byte1]: 56
1718 13:59:44.611726
1719 13:59:44.611807 Set Vref, RX VrefLevel [Byte0]: 57
1720 13:59:44.615497 [Byte1]: 57
1721 13:59:44.619289
1722 13:59:44.619369 Set Vref, RX VrefLevel [Byte0]: 58
1723 13:59:44.622497 [Byte1]: 58
1724 13:59:44.626877
1725 13:59:44.626958 Set Vref, RX VrefLevel [Byte0]: 59
1726 13:59:44.630298 [Byte1]: 59
1727 13:59:44.634693
1728 13:59:44.634774 Set Vref, RX VrefLevel [Byte0]: 60
1729 13:59:44.638234 [Byte1]: 60
1730 13:59:44.641943
1731 13:59:44.642049 Set Vref, RX VrefLevel [Byte0]: 61
1732 13:59:44.645024 [Byte1]: 61
1733 13:59:44.649531
1734 13:59:44.649633 Set Vref, RX VrefLevel [Byte0]: 62
1735 13:59:44.652862 [Byte1]: 62
1736 13:59:44.656770
1737 13:59:44.656843 Set Vref, RX VrefLevel [Byte0]: 63
1738 13:59:44.660193 [Byte1]: 63
1739 13:59:44.664267
1740 13:59:44.664340 Set Vref, RX VrefLevel [Byte0]: 64
1741 13:59:44.667747 [Byte1]: 64
1742 13:59:44.672113
1743 13:59:44.672193 Set Vref, RX VrefLevel [Byte0]: 65
1744 13:59:44.675574 [Byte1]: 65
1745 13:59:44.679726
1746 13:59:44.679852 Set Vref, RX VrefLevel [Byte0]: 66
1747 13:59:44.682975 [Byte1]: 66
1748 13:59:44.687012
1749 13:59:44.687119 Set Vref, RX VrefLevel [Byte0]: 67
1750 13:59:44.690401 [Byte1]: 67
1751 13:59:44.694982
1752 13:59:44.695088 Set Vref, RX VrefLevel [Byte0]: 68
1753 13:59:44.697994 [Byte1]: 68
1754 13:59:44.702260
1755 13:59:44.702358 Set Vref, RX VrefLevel [Byte0]: 69
1756 13:59:44.705573 [Byte1]: 69
1757 13:59:44.709916
1758 13:59:44.710012 Set Vref, RX VrefLevel [Byte0]: 70
1759 13:59:44.713322 [Byte1]: 70
1760 13:59:44.717350
1761 13:59:44.717455 Set Vref, RX VrefLevel [Byte0]: 71
1762 13:59:44.720632 [Byte1]: 71
1763 13:59:44.725138
1764 13:59:44.725238 Set Vref, RX VrefLevel [Byte0]: 72
1765 13:59:44.727904 [Byte1]: 72
1766 13:59:44.732395
1767 13:59:44.732494 Final RX Vref Byte 0 = 56 to rank0
1768 13:59:44.736249 Final RX Vref Byte 1 = 56 to rank0
1769 13:59:44.739178 Final RX Vref Byte 0 = 56 to rank1
1770 13:59:44.742473 Final RX Vref Byte 1 = 56 to rank1==
1771 13:59:44.745797 Dram Type= 6, Freq= 0, CH_1, rank 0
1772 13:59:44.749102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1773 13:59:44.753103 ==
1774 13:59:44.753175 DQS Delay:
1775 13:59:44.753236 DQS0 = 0, DQS1 = 0
1776 13:59:44.756175 DQM Delay:
1777 13:59:44.756257 DQM0 = 95, DQM1 = 90
1778 13:59:44.759536 DQ Delay:
1779 13:59:44.759654 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =96
1780 13:59:44.762743 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1781 13:59:44.766191 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1782 13:59:44.769405 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1783 13:59:44.773038
1784 13:59:44.773118
1785 13:59:44.779803 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1786 13:59:44.782925 CH1 RK0: MR19=606, MR18=2D49
1787 13:59:44.789598 CH1_RK0: MR19=0x606, MR18=0x2D49, DQSOSC=391, MR23=63, INC=96, DEC=64
1788 13:59:44.789680
1789 13:59:44.792453 ----->DramcWriteLeveling(PI) begin...
1790 13:59:44.792539 ==
1791 13:59:44.796261 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 13:59:44.799566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 13:59:44.799654 ==
1794 13:59:44.802924 Write leveling (Byte 0): 27 => 27
1795 13:59:44.806024 Write leveling (Byte 1): 29 => 29
1796 13:59:44.809377 DramcWriteLeveling(PI) end<-----
1797 13:59:44.809458
1798 13:59:44.809521 ==
1799 13:59:44.812500 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 13:59:44.815887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 13:59:44.815995 ==
1802 13:59:44.819232 [Gating] SW mode calibration
1803 13:59:44.826037 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1804 13:59:44.832710 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1805 13:59:44.836123 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1806 13:59:44.839622 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1807 13:59:44.846173 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 13:59:44.849818 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 13:59:44.853015 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 13:59:44.859852 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 13:59:44.862850 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:59:44.866097 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:59:44.869568 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:59:44.876060 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:59:44.879791 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:59:44.882995 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:59:44.889842 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:59:44.893362 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:59:44.896488 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:59:44.903001 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1821 13:59:44.906342 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1822 13:59:44.909406 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1823 13:59:44.916190 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:59:44.919561 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:59:44.922851 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:59:44.929652 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:59:44.933104 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:59:44.936318 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:59:44.942838 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:59:44.946363 0 9 4 | B1->B0 | 2929 2323 | 1 1 | (1 1) (1 1)
1831 13:59:44.949620 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1832 13:59:44.953145 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 13:59:44.960137 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 13:59:44.963244 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 13:59:44.966125 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 13:59:44.973089 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 13:59:44.976616 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1838 13:59:44.979951 0 10 4 | B1->B0 | 2c2c 2f2f | 0 1 | (1 0) (1 0)
1839 13:59:44.986372 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:59:44.989421 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:59:44.993120 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:59:44.999557 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:59:45.003508 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 13:59:45.006559 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:59:45.013288 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:59:45.016577 0 11 4 | B1->B0 | 3939 2b2b | 1 0 | (0 0) (0 0)
1847 13:59:45.019956 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1848 13:59:45.026548 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 13:59:45.029734 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 13:59:45.033200 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 13:59:45.036421 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 13:59:45.042973 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 13:59:45.046484 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 13:59:45.050333 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1855 13:59:45.056833 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 13:59:45.060218 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 13:59:45.063114 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 13:59:45.070033 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 13:59:45.073324 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 13:59:45.076361 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 13:59:45.083037 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:59:45.086260 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:59:45.089588 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:59:45.096614 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:59:45.099631 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:59:45.103129 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:59:45.110353 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:59:45.113393 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:59:45.116424 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:59:45.123146 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1871 13:59:45.126424 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 13:59:45.129561 Total UI for P1: 0, mck2ui 16
1873 13:59:45.133022 best dqsien dly found for B0: ( 0, 14, 4)
1874 13:59:45.136366 Total UI for P1: 0, mck2ui 16
1875 13:59:45.139825 best dqsien dly found for B1: ( 0, 14, 4)
1876 13:59:45.143619 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1877 13:59:45.146786 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1878 13:59:45.146869
1879 13:59:45.149458 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1880 13:59:45.152922 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1881 13:59:45.156289 [Gating] SW calibration Done
1882 13:59:45.156371 ==
1883 13:59:45.159856 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 13:59:45.163145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1885 13:59:45.163227 ==
1886 13:59:45.166550 RX Vref Scan: 0
1887 13:59:45.166632
1888 13:59:45.166695 RX Vref 0 -> 0, step: 1
1889 13:59:45.169908
1890 13:59:45.169992 RX Delay -130 -> 252, step: 16
1891 13:59:45.176805 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1892 13:59:45.179781 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1893 13:59:45.182855 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1894 13:59:45.186446 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1895 13:59:45.189581 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1896 13:59:45.196473 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1897 13:59:45.199889 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1898 13:59:45.203202 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1899 13:59:45.206691 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1900 13:59:45.209589 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1901 13:59:45.213401 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1902 13:59:45.219798 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1903 13:59:45.223066 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1904 13:59:45.226923 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1905 13:59:45.229757 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1906 13:59:45.236287 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1907 13:59:45.236372 ==
1908 13:59:45.239516 Dram Type= 6, Freq= 0, CH_1, rank 1
1909 13:59:45.242960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1910 13:59:45.243045 ==
1911 13:59:45.243132 DQS Delay:
1912 13:59:45.246295 DQS0 = 0, DQS1 = 0
1913 13:59:45.246380 DQM Delay:
1914 13:59:45.249515 DQM0 = 93, DQM1 = 88
1915 13:59:45.249600 DQ Delay:
1916 13:59:45.253357 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1917 13:59:45.256740 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1918 13:59:45.259926 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1919 13:59:45.263483 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1920 13:59:45.263617
1921 13:59:45.263698
1922 13:59:45.263772 ==
1923 13:59:45.266366 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 13:59:45.270116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 13:59:45.270197 ==
1926 13:59:45.270272
1927 13:59:45.270333
1928 13:59:45.273524 TX Vref Scan disable
1929 13:59:45.276191 == TX Byte 0 ==
1930 13:59:45.279689 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1931 13:59:45.283070 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1932 13:59:45.286489 == TX Byte 1 ==
1933 13:59:45.289983 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1934 13:59:45.293161 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1935 13:59:45.293236 ==
1936 13:59:45.296684 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 13:59:45.299946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 13:59:45.303027 ==
1939 13:59:45.314686 TX Vref=22, minBit 1, minWin=26, winSum=442
1940 13:59:45.318068 TX Vref=24, minBit 3, minWin=26, winSum=445
1941 13:59:45.321293 TX Vref=26, minBit 2, minWin=27, winSum=449
1942 13:59:45.325043 TX Vref=28, minBit 2, minWin=27, winSum=452
1943 13:59:45.328355 TX Vref=30, minBit 2, minWin=27, winSum=451
1944 13:59:45.331240 TX Vref=32, minBit 2, minWin=27, winSum=450
1945 13:59:45.338165 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 28
1946 13:59:45.338246
1947 13:59:45.341769 Final TX Range 1 Vref 28
1948 13:59:45.341859
1949 13:59:45.341930 ==
1950 13:59:45.344765 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 13:59:45.347967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 13:59:45.348082 ==
1953 13:59:45.348157
1954 13:59:45.348216
1955 13:59:45.351643 TX Vref Scan disable
1956 13:59:45.354903 == TX Byte 0 ==
1957 13:59:45.358268 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1958 13:59:45.361467 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1959 13:59:45.364724 == TX Byte 1 ==
1960 13:59:45.368052 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1961 13:59:45.371691 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1962 13:59:45.371797
1963 13:59:45.374991 [DATLAT]
1964 13:59:45.375071 Freq=800, CH1 RK1
1965 13:59:45.375134
1966 13:59:45.378199 DATLAT Default: 0xa
1967 13:59:45.378279 0, 0xFFFF, sum = 0
1968 13:59:45.381691 1, 0xFFFF, sum = 0
1969 13:59:45.381773 2, 0xFFFF, sum = 0
1970 13:59:45.384738 3, 0xFFFF, sum = 0
1971 13:59:45.384819 4, 0xFFFF, sum = 0
1972 13:59:45.388348 5, 0xFFFF, sum = 0
1973 13:59:45.388429 6, 0xFFFF, sum = 0
1974 13:59:45.391253 7, 0xFFFF, sum = 0
1975 13:59:45.391335 8, 0xFFFF, sum = 0
1976 13:59:45.394506 9, 0x0, sum = 1
1977 13:59:45.394588 10, 0x0, sum = 2
1978 13:59:45.398494 11, 0x0, sum = 3
1979 13:59:45.398578 12, 0x0, sum = 4
1980 13:59:45.401383 best_step = 10
1981 13:59:45.401463
1982 13:59:45.401525 ==
1983 13:59:45.405017 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 13:59:45.408135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 13:59:45.408216 ==
1986 13:59:45.411426 RX Vref Scan: 0
1987 13:59:45.411531
1988 13:59:45.411658 RX Vref 0 -> 0, step: 1
1989 13:59:45.411720
1990 13:59:45.415002 RX Delay -79 -> 252, step: 8
1991 13:59:45.418810 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1992 13:59:45.425307 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1993 13:59:45.428507 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1994 13:59:45.431726 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1995 13:59:45.435808 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1996 13:59:45.438471 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1997 13:59:45.441697 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1998 13:59:45.448373 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1999 13:59:45.451977 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2000 13:59:45.455098 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2001 13:59:45.458566 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2002 13:59:45.461682 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2003 13:59:45.468960 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2004 13:59:45.472002 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2005 13:59:45.475220 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2006 13:59:45.479075 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2007 13:59:45.479160 ==
2008 13:59:45.482298 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 13:59:45.488719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 13:59:45.488804 ==
2011 13:59:45.488891 DQS Delay:
2012 13:59:45.488974 DQS0 = 0, DQS1 = 0
2013 13:59:45.491880 DQM Delay:
2014 13:59:45.491964 DQM0 = 97, DQM1 = 91
2015 13:59:45.495212 DQ Delay:
2016 13:59:45.498468 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2017 13:59:45.501785 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2018 13:59:45.505447 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2019 13:59:45.508960 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2020 13:59:45.509038
2021 13:59:45.509121
2022 13:59:45.515579 [DQSOSCAuto] RK1, (LSB)MR18= 0x4913, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2023 13:59:45.518917 CH1 RK1: MR19=606, MR18=4913
2024 13:59:45.525220 CH1_RK1: MR19=0x606, MR18=0x4913, DQSOSC=391, MR23=63, INC=96, DEC=64
2025 13:59:45.528751 [RxdqsGatingPostProcess] freq 800
2026 13:59:45.531849 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2027 13:59:45.535186 Pre-setting of DQS Precalculation
2028 13:59:45.542442 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2029 13:59:45.548760 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2030 13:59:45.555167 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2031 13:59:45.555276
2032 13:59:45.555367
2033 13:59:45.558440 [Calibration Summary] 1600 Mbps
2034 13:59:45.558547 CH 0, Rank 0
2035 13:59:45.562099 SW Impedance : PASS
2036 13:59:45.565618 DUTY Scan : NO K
2037 13:59:45.565701 ZQ Calibration : PASS
2038 13:59:45.568830 Jitter Meter : NO K
2039 13:59:45.571985 CBT Training : PASS
2040 13:59:45.572094 Write leveling : PASS
2041 13:59:45.575327 RX DQS gating : PASS
2042 13:59:45.578730 RX DQ/DQS(RDDQC) : PASS
2043 13:59:45.578840 TX DQ/DQS : PASS
2044 13:59:45.581857 RX DATLAT : PASS
2045 13:59:45.581940 RX DQ/DQS(Engine): PASS
2046 13:59:45.585350 TX OE : NO K
2047 13:59:45.585434 All Pass.
2048 13:59:45.585517
2049 13:59:45.588611 CH 0, Rank 1
2050 13:59:45.588694 SW Impedance : PASS
2051 13:59:45.592582 DUTY Scan : NO K
2052 13:59:45.595625 ZQ Calibration : PASS
2053 13:59:45.595722 Jitter Meter : NO K
2054 13:59:45.598802 CBT Training : PASS
2055 13:59:45.602097 Write leveling : PASS
2056 13:59:45.602180 RX DQS gating : PASS
2057 13:59:45.605227 RX DQ/DQS(RDDQC) : PASS
2058 13:59:45.608943 TX DQ/DQS : PASS
2059 13:59:45.609026 RX DATLAT : PASS
2060 13:59:45.612033 RX DQ/DQS(Engine): PASS
2061 13:59:45.612125 TX OE : NO K
2062 13:59:45.615686 All Pass.
2063 13:59:45.615769
2064 13:59:45.615853 CH 1, Rank 0
2065 13:59:45.619024 SW Impedance : PASS
2066 13:59:45.619121 DUTY Scan : NO K
2067 13:59:45.622087 ZQ Calibration : PASS
2068 13:59:45.625760 Jitter Meter : NO K
2069 13:59:45.625843 CBT Training : PASS
2070 13:59:45.628887 Write leveling : PASS
2071 13:59:45.632061 RX DQS gating : PASS
2072 13:59:45.632149 RX DQ/DQS(RDDQC) : PASS
2073 13:59:45.635566 TX DQ/DQS : PASS
2074 13:59:45.638762 RX DATLAT : PASS
2075 13:59:45.638847 RX DQ/DQS(Engine): PASS
2076 13:59:45.642559 TX OE : NO K
2077 13:59:45.642641 All Pass.
2078 13:59:45.642704
2079 13:59:45.645592 CH 1, Rank 1
2080 13:59:45.645667 SW Impedance : PASS
2081 13:59:45.649075 DUTY Scan : NO K
2082 13:59:45.652611 ZQ Calibration : PASS
2083 13:59:45.652687 Jitter Meter : NO K
2084 13:59:45.655906 CBT Training : PASS
2085 13:59:45.656015 Write leveling : PASS
2086 13:59:45.659155 RX DQS gating : PASS
2087 13:59:45.662608 RX DQ/DQS(RDDQC) : PASS
2088 13:59:45.662685 TX DQ/DQS : PASS
2089 13:59:45.665974 RX DATLAT : PASS
2090 13:59:45.669136 RX DQ/DQS(Engine): PASS
2091 13:59:45.669217 TX OE : NO K
2092 13:59:45.672380 All Pass.
2093 13:59:45.672453
2094 13:59:45.672524 DramC Write-DBI off
2095 13:59:45.675605 PER_BANK_REFRESH: Hybrid Mode
2096 13:59:45.675719 TX_TRACKING: ON
2097 13:59:45.679778 [GetDramInforAfterCalByMRR] Vendor 6.
2098 13:59:45.686245 [GetDramInforAfterCalByMRR] Revision 606.
2099 13:59:45.689404 [GetDramInforAfterCalByMRR] Revision 2 0.
2100 13:59:45.689485 MR0 0x3b3b
2101 13:59:45.689548 MR8 0x5151
2102 13:59:45.692500 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2103 13:59:45.692582
2104 13:59:45.695538 MR0 0x3b3b
2105 13:59:45.695641 MR8 0x5151
2106 13:59:45.699513 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 13:59:45.699665
2108 13:59:45.709381 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2109 13:59:45.712674 [FAST_K] Save calibration result to emmc
2110 13:59:45.715841 [FAST_K] Save calibration result to emmc
2111 13:59:45.719515 dram_init: config_dvfs: 1
2112 13:59:45.722507 dramc_set_vcore_voltage set vcore to 662500
2113 13:59:45.726014 Read voltage for 1200, 2
2114 13:59:45.726125 Vio18 = 0
2115 13:59:45.726194 Vcore = 662500
2116 13:59:45.728977 Vdram = 0
2117 13:59:45.729053 Vddq = 0
2118 13:59:45.729121 Vmddr = 0
2119 13:59:45.735686 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2120 13:59:45.739294 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2121 13:59:45.742611 MEM_TYPE=3, freq_sel=15
2122 13:59:45.745862 sv_algorithm_assistance_LP4_1600
2123 13:59:45.749268 ============ PULL DRAM RESETB DOWN ============
2124 13:59:45.752750 ========== PULL DRAM RESETB DOWN end =========
2125 13:59:45.759209 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2126 13:59:45.762365 ===================================
2127 13:59:45.762438 LPDDR4 DRAM CONFIGURATION
2128 13:59:45.765889 ===================================
2129 13:59:45.769229 EX_ROW_EN[0] = 0x0
2130 13:59:45.772080 EX_ROW_EN[1] = 0x0
2131 13:59:45.772155 LP4Y_EN = 0x0
2132 13:59:45.775656 WORK_FSP = 0x0
2133 13:59:45.775724 WL = 0x4
2134 13:59:45.779154 RL = 0x4
2135 13:59:45.779225 BL = 0x2
2136 13:59:45.782795 RPST = 0x0
2137 13:59:45.782869 RD_PRE = 0x0
2138 13:59:45.785821 WR_PRE = 0x1
2139 13:59:45.785893 WR_PST = 0x0
2140 13:59:45.789362 DBI_WR = 0x0
2141 13:59:45.789442 DBI_RD = 0x0
2142 13:59:45.792171 OTF = 0x1
2143 13:59:45.795906 ===================================
2144 13:59:45.799151 ===================================
2145 13:59:45.799227 ANA top config
2146 13:59:45.802448 ===================================
2147 13:59:45.805641 DLL_ASYNC_EN = 0
2148 13:59:45.808961 ALL_SLAVE_EN = 0
2149 13:59:45.809040 NEW_RANK_MODE = 1
2150 13:59:45.812768 DLL_IDLE_MODE = 1
2151 13:59:45.815700 LP45_APHY_COMB_EN = 1
2152 13:59:45.819032 TX_ODT_DIS = 1
2153 13:59:45.822420 NEW_8X_MODE = 1
2154 13:59:45.826102 ===================================
2155 13:59:45.829138 ===================================
2156 13:59:45.829219 data_rate = 2400
2157 13:59:45.832382 CKR = 1
2158 13:59:45.835864 DQ_P2S_RATIO = 8
2159 13:59:45.839230 ===================================
2160 13:59:45.842221 CA_P2S_RATIO = 8
2161 13:59:45.846044 DQ_CA_OPEN = 0
2162 13:59:45.849152 DQ_SEMI_OPEN = 0
2163 13:59:45.849232 CA_SEMI_OPEN = 0
2164 13:59:45.852816 CA_FULL_RATE = 0
2165 13:59:45.855648 DQ_CKDIV4_EN = 0
2166 13:59:45.859498 CA_CKDIV4_EN = 0
2167 13:59:45.862672 CA_PREDIV_EN = 0
2168 13:59:45.862783 PH8_DLY = 17
2169 13:59:45.866173 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2170 13:59:45.868952 DQ_AAMCK_DIV = 4
2171 13:59:45.872438 CA_AAMCK_DIV = 4
2172 13:59:45.875894 CA_ADMCK_DIV = 4
2173 13:59:45.879271 DQ_TRACK_CA_EN = 0
2174 13:59:45.882974 CA_PICK = 1200
2175 13:59:45.883074 CA_MCKIO = 1200
2176 13:59:45.885805 MCKIO_SEMI = 0
2177 13:59:45.889684 PLL_FREQ = 2366
2178 13:59:45.892362 DQ_UI_PI_RATIO = 32
2179 13:59:45.895950 CA_UI_PI_RATIO = 0
2180 13:59:45.899526 ===================================
2181 13:59:45.902939 ===================================
2182 13:59:45.905769 memory_type:LPDDR4
2183 13:59:45.905868 GP_NUM : 10
2184 13:59:45.909208 SRAM_EN : 1
2185 13:59:45.909309 MD32_EN : 0
2186 13:59:45.912334 ===================================
2187 13:59:45.916215 [ANA_INIT] >>>>>>>>>>>>>>
2188 13:59:45.919229 <<<<<< [CONFIGURE PHASE]: ANA_TX
2189 13:59:45.922586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2190 13:59:45.925859 ===================================
2191 13:59:45.929239 data_rate = 2400,PCW = 0X5b00
2192 13:59:45.932295 ===================================
2193 13:59:45.935650 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2194 13:59:45.939173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2195 13:59:45.946037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 13:59:45.949345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2197 13:59:45.952691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2198 13:59:45.959125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2199 13:59:45.959233 [ANA_INIT] flow start
2200 13:59:45.963174 [ANA_INIT] PLL >>>>>>>>
2201 13:59:45.963279 [ANA_INIT] PLL <<<<<<<<
2202 13:59:45.965936 [ANA_INIT] MIDPI >>>>>>>>
2203 13:59:45.969784 [ANA_INIT] MIDPI <<<<<<<<
2204 13:59:45.972611 [ANA_INIT] DLL >>>>>>>>
2205 13:59:45.972727 [ANA_INIT] DLL <<<<<<<<
2206 13:59:45.975825 [ANA_INIT] flow end
2207 13:59:45.979349 ============ LP4 DIFF to SE enter ============
2208 13:59:45.982497 ============ LP4 DIFF to SE exit ============
2209 13:59:45.986151 [ANA_INIT] <<<<<<<<<<<<<
2210 13:59:45.989277 [Flow] Enable top DCM control >>>>>
2211 13:59:45.993023 [Flow] Enable top DCM control <<<<<
2212 13:59:45.996598 Enable DLL master slave shuffle
2213 13:59:45.999935 ==============================================================
2214 13:59:46.002817 Gating Mode config
2215 13:59:46.009782 ==============================================================
2216 13:59:46.009892 Config description:
2217 13:59:46.019648 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2218 13:59:46.026055 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2219 13:59:46.029464 SELPH_MODE 0: By rank 1: By Phase
2220 13:59:46.036200 ==============================================================
2221 13:59:46.039843 GAT_TRACK_EN = 1
2222 13:59:46.042986 RX_GATING_MODE = 2
2223 13:59:46.046402 RX_GATING_TRACK_MODE = 2
2224 13:59:46.049581 SELPH_MODE = 1
2225 13:59:46.052725 PICG_EARLY_EN = 1
2226 13:59:46.056509 VALID_LAT_VALUE = 1
2227 13:59:46.059563 ==============================================================
2228 13:59:46.062758 Enter into Gating configuration >>>>
2229 13:59:46.066153 Exit from Gating configuration <<<<
2230 13:59:46.069600 Enter into DVFS_PRE_config >>>>>
2231 13:59:46.079836 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2232 13:59:46.083273 Exit from DVFS_PRE_config <<<<<
2233 13:59:46.086099 Enter into PICG configuration >>>>
2234 13:59:46.089510 Exit from PICG configuration <<<<
2235 13:59:46.092935 [RX_INPUT] configuration >>>>>
2236 13:59:46.096297 [RX_INPUT] configuration <<<<<
2237 13:59:46.102933 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2238 13:59:46.106594 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2239 13:59:46.113165 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 13:59:46.120025 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 13:59:46.126645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 13:59:46.133065 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 13:59:46.136361 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2244 13:59:46.139620 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2245 13:59:46.142943 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2246 13:59:46.146576 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2247 13:59:46.153135 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2248 13:59:46.156709 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2249 13:59:46.159566 ===================================
2250 13:59:46.163243 LPDDR4 DRAM CONFIGURATION
2251 13:59:46.166571 ===================================
2252 13:59:46.166678 EX_ROW_EN[0] = 0x0
2253 13:59:46.169749 EX_ROW_EN[1] = 0x0
2254 13:59:46.169823 LP4Y_EN = 0x0
2255 13:59:46.173404 WORK_FSP = 0x0
2256 13:59:46.173476 WL = 0x4
2257 13:59:46.176669 RL = 0x4
2258 13:59:46.176763 BL = 0x2
2259 13:59:46.179982 RPST = 0x0
2260 13:59:46.180055 RD_PRE = 0x0
2261 13:59:46.183999 WR_PRE = 0x1
2262 13:59:46.184099 WR_PST = 0x0
2263 13:59:46.186544 DBI_WR = 0x0
2264 13:59:46.186619 DBI_RD = 0x0
2265 13:59:46.190210 OTF = 0x1
2266 13:59:46.193284 ===================================
2267 13:59:46.196838 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2268 13:59:46.200496 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2269 13:59:46.206864 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2270 13:59:46.210172 ===================================
2271 13:59:46.213374 LPDDR4 DRAM CONFIGURATION
2272 13:59:46.213474 ===================================
2273 13:59:46.216521 EX_ROW_EN[0] = 0x10
2274 13:59:46.219677 EX_ROW_EN[1] = 0x0
2275 13:59:46.219775 LP4Y_EN = 0x0
2276 13:59:46.222997 WORK_FSP = 0x0
2277 13:59:46.223094 WL = 0x4
2278 13:59:46.226634 RL = 0x4
2279 13:59:46.226738 BL = 0x2
2280 13:59:46.230188 RPST = 0x0
2281 13:59:46.230289 RD_PRE = 0x0
2282 13:59:46.233326 WR_PRE = 0x1
2283 13:59:46.233425 WR_PST = 0x0
2284 13:59:46.236860 DBI_WR = 0x0
2285 13:59:46.236972 DBI_RD = 0x0
2286 13:59:46.239811 OTF = 0x1
2287 13:59:46.243138 ===================================
2288 13:59:46.249820 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2289 13:59:46.249925 ==
2290 13:59:46.253252 Dram Type= 6, Freq= 0, CH_0, rank 0
2291 13:59:46.256647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2292 13:59:46.256750 ==
2293 13:59:46.260000 [Duty_Offset_Calibration]
2294 13:59:46.260103 B0:2 B1:1 CA:1
2295 13:59:46.260196
2296 13:59:46.263356 [DutyScan_Calibration_Flow] k_type=0
2297 13:59:46.273564
2298 13:59:46.273670 ==CLK 0==
2299 13:59:46.276843 Final CLK duty delay cell = 0
2300 13:59:46.280115 [0] MAX Duty = 5218%(X100), DQS PI = 24
2301 13:59:46.283459 [0] MIN Duty = 4875%(X100), DQS PI = 0
2302 13:59:46.283567 [0] AVG Duty = 5046%(X100)
2303 13:59:46.286835
2304 13:59:46.286935 CH0 CLK Duty spec in!! Max-Min= 343%
2305 13:59:46.293541 [DutyScan_Calibration_Flow] ====Done====
2306 13:59:46.293642
2307 13:59:46.296864 [DutyScan_Calibration_Flow] k_type=1
2308 13:59:46.311723
2309 13:59:46.311829 ==DQS 0 ==
2310 13:59:46.315015 Final DQS duty delay cell = -4
2311 13:59:46.317790 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2312 13:59:46.321245 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2313 13:59:46.324785 [-4] AVG Duty = 4969%(X100)
2314 13:59:46.324883
2315 13:59:46.324989 ==DQS 1 ==
2316 13:59:46.328023 Final DQS duty delay cell = -4
2317 13:59:46.331323 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2318 13:59:46.334537 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2319 13:59:46.337896 [-4] AVG Duty = 4922%(X100)
2320 13:59:46.337995
2321 13:59:46.341333 CH0 DQS 0 Duty spec in!! Max-Min= 374%
2322 13:59:46.341438
2323 13:59:46.344525 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2324 13:59:46.348170 [DutyScan_Calibration_Flow] ====Done====
2325 13:59:46.348277
2326 13:59:46.351623 [DutyScan_Calibration_Flow] k_type=3
2327 13:59:46.368378
2328 13:59:46.368486 ==DQM 0 ==
2329 13:59:46.371769 Final DQM duty delay cell = 0
2330 13:59:46.375390 [0] MAX Duty = 5156%(X100), DQS PI = 24
2331 13:59:46.378341 [0] MIN Duty = 4906%(X100), DQS PI = 58
2332 13:59:46.381862 [0] AVG Duty = 5031%(X100)
2333 13:59:46.381965
2334 13:59:46.382058 ==DQM 1 ==
2335 13:59:46.385308 Final DQM duty delay cell = 0
2336 13:59:46.388683 [0] MAX Duty = 5125%(X100), DQS PI = 10
2337 13:59:46.391546 [0] MIN Duty = 5031%(X100), DQS PI = 50
2338 13:59:46.395300 [0] AVG Duty = 5078%(X100)
2339 13:59:46.395404
2340 13:59:46.398238 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2341 13:59:46.398340
2342 13:59:46.402051 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2343 13:59:46.404910 [DutyScan_Calibration_Flow] ====Done====
2344 13:59:46.405010
2345 13:59:46.408251 [DutyScan_Calibration_Flow] k_type=2
2346 13:59:46.424935
2347 13:59:46.425043 ==DQ 0 ==
2348 13:59:46.428095 Final DQ duty delay cell = 0
2349 13:59:46.431656 [0] MAX Duty = 5062%(X100), DQS PI = 32
2350 13:59:46.434701 [0] MIN Duty = 4906%(X100), DQS PI = 0
2351 13:59:46.434780 [0] AVG Duty = 4984%(X100)
2352 13:59:46.434842
2353 13:59:46.438535 ==DQ 1 ==
2354 13:59:46.441380 Final DQ duty delay cell = 0
2355 13:59:46.445133 [0] MAX Duty = 5093%(X100), DQS PI = 10
2356 13:59:46.448204 [0] MIN Duty = 4938%(X100), DQS PI = 36
2357 13:59:46.448308 [0] AVG Duty = 5015%(X100)
2358 13:59:46.448401
2359 13:59:46.451589 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2360 13:59:46.454629
2361 13:59:46.458519 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2362 13:59:46.461890 [DutyScan_Calibration_Flow] ====Done====
2363 13:59:46.461990 ==
2364 13:59:46.465266 Dram Type= 6, Freq= 0, CH_1, rank 0
2365 13:59:46.468433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2366 13:59:46.468537 ==
2367 13:59:46.471476 [Duty_Offset_Calibration]
2368 13:59:46.471587 B0:1 B1:0 CA:0
2369 13:59:46.471693
2370 13:59:46.474956 [DutyScan_Calibration_Flow] k_type=0
2371 13:59:46.484091
2372 13:59:46.484169 ==CLK 0==
2373 13:59:46.487691 Final CLK duty delay cell = -4
2374 13:59:46.490628 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2375 13:59:46.494253 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2376 13:59:46.497381 [-4] AVG Duty = 4969%(X100)
2377 13:59:46.497457
2378 13:59:46.500929 CH1 CLK Duty spec in!! Max-Min= 124%
2379 13:59:46.503923 [DutyScan_Calibration_Flow] ====Done====
2380 13:59:46.503997
2381 13:59:46.507366 [DutyScan_Calibration_Flow] k_type=1
2382 13:59:46.524131
2383 13:59:46.524207 ==DQS 0 ==
2384 13:59:46.527489 Final DQS duty delay cell = 0
2385 13:59:46.530910 [0] MAX Duty = 5094%(X100), DQS PI = 24
2386 13:59:46.534179 [0] MIN Duty = 4844%(X100), DQS PI = 0
2387 13:59:46.534285 [0] AVG Duty = 4969%(X100)
2388 13:59:46.537223
2389 13:59:46.537332 ==DQS 1 ==
2390 13:59:46.540722 Final DQS duty delay cell = 0
2391 13:59:46.544058 [0] MAX Duty = 5156%(X100), DQS PI = 18
2392 13:59:46.547881 [0] MIN Duty = 4969%(X100), DQS PI = 8
2393 13:59:46.547984 [0] AVG Duty = 5062%(X100)
2394 13:59:46.548079
2395 13:59:46.550729 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2396 13:59:46.553959
2397 13:59:46.557301 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2398 13:59:46.560573 [DutyScan_Calibration_Flow] ====Done====
2399 13:59:46.560675
2400 13:59:46.564181 [DutyScan_Calibration_Flow] k_type=3
2401 13:59:46.580329
2402 13:59:46.580411 ==DQM 0 ==
2403 13:59:46.583702 Final DQM duty delay cell = 0
2404 13:59:46.587245 [0] MAX Duty = 5156%(X100), DQS PI = 4
2405 13:59:46.590715 [0] MIN Duty = 5031%(X100), DQS PI = 0
2406 13:59:46.590796 [0] AVG Duty = 5093%(X100)
2407 13:59:46.594369
2408 13:59:46.594453 ==DQM 1 ==
2409 13:59:46.597352 Final DQM duty delay cell = 0
2410 13:59:46.600981 [0] MAX Duty = 5062%(X100), DQS PI = 26
2411 13:59:46.604283 [0] MIN Duty = 4907%(X100), DQS PI = 36
2412 13:59:46.604388 [0] AVG Duty = 4984%(X100)
2413 13:59:46.604479
2414 13:59:46.607355 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2415 13:59:46.610470
2416 13:59:46.614408 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2417 13:59:46.617578 [DutyScan_Calibration_Flow] ====Done====
2418 13:59:46.617661
2419 13:59:46.620973 [DutyScan_Calibration_Flow] k_type=2
2420 13:59:46.636340
2421 13:59:46.636422 ==DQ 0 ==
2422 13:59:46.639533 Final DQ duty delay cell = -4
2423 13:59:46.642948 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2424 13:59:46.646092 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2425 13:59:46.649488 [-4] AVG Duty = 5016%(X100)
2426 13:59:46.649586
2427 13:59:46.649679 ==DQ 1 ==
2428 13:59:46.653346 Final DQ duty delay cell = 0
2429 13:59:46.656084 [0] MAX Duty = 5125%(X100), DQS PI = 20
2430 13:59:46.659518 [0] MIN Duty = 4969%(X100), DQS PI = 10
2431 13:59:46.659656 [0] AVG Duty = 5047%(X100)
2432 13:59:46.663423
2433 13:59:46.666315 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2434 13:59:46.666416
2435 13:59:46.669553 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2436 13:59:46.672736 [DutyScan_Calibration_Flow] ====Done====
2437 13:59:46.676340 nWR fixed to 30
2438 13:59:46.676443 [ModeRegInit_LP4] CH0 RK0
2439 13:59:46.679275 [ModeRegInit_LP4] CH0 RK1
2440 13:59:46.682709 [ModeRegInit_LP4] CH1 RK0
2441 13:59:46.686128 [ModeRegInit_LP4] CH1 RK1
2442 13:59:46.686210 match AC timing 7
2443 13:59:46.689461 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2444 13:59:46.696138 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2445 13:59:46.699798 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2446 13:59:46.703001 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2447 13:59:46.709661 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2448 13:59:46.709742 ==
2449 13:59:46.712721 Dram Type= 6, Freq= 0, CH_0, rank 0
2450 13:59:46.716125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2451 13:59:46.716207 ==
2452 13:59:46.723226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2453 13:59:46.729878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2454 13:59:46.736340 [CA 0] Center 39 (8~70) winsize 63
2455 13:59:46.740304 [CA 1] Center 39 (8~70) winsize 63
2456 13:59:46.743469 [CA 2] Center 35 (5~66) winsize 62
2457 13:59:46.746688 [CA 3] Center 34 (4~65) winsize 62
2458 13:59:46.750028 [CA 4] Center 33 (3~64) winsize 62
2459 13:59:46.753111 [CA 5] Center 32 (3~62) winsize 60
2460 13:59:46.753192
2461 13:59:46.756477 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2462 13:59:46.756604
2463 13:59:46.759836 [CATrainingPosCal] consider 1 rank data
2464 13:59:46.763255 u2DelayCellTimex100 = 270/100 ps
2465 13:59:46.766851 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2466 13:59:46.769726 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2467 13:59:46.776835 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2468 13:59:46.780160 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2469 13:59:46.783267 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2470 13:59:46.786784 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2471 13:59:46.786866
2472 13:59:46.790058 CA PerBit enable=1, Macro0, CA PI delay=32
2473 13:59:46.790140
2474 13:59:46.793297 [CBTSetCACLKResult] CA Dly = 32
2475 13:59:46.793378 CS Dly: 6 (0~37)
2476 13:59:46.793442 ==
2477 13:59:46.796676 Dram Type= 6, Freq= 0, CH_0, rank 1
2478 13:59:46.803440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2479 13:59:46.803547 ==
2480 13:59:46.806686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2481 13:59:46.813422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2482 13:59:46.822080 [CA 0] Center 38 (8~69) winsize 62
2483 13:59:46.825756 [CA 1] Center 38 (8~69) winsize 62
2484 13:59:46.828920 [CA 2] Center 35 (4~66) winsize 63
2485 13:59:46.831965 [CA 3] Center 34 (4~65) winsize 62
2486 13:59:46.835452 [CA 4] Center 33 (3~64) winsize 62
2487 13:59:46.838941 [CA 5] Center 32 (3~62) winsize 60
2488 13:59:46.839023
2489 13:59:46.842615 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2490 13:59:46.842696
2491 13:59:46.845705 [CATrainingPosCal] consider 2 rank data
2492 13:59:46.849129 u2DelayCellTimex100 = 270/100 ps
2493 13:59:46.852176 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2494 13:59:46.855522 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2495 13:59:46.862162 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2496 13:59:46.865360 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2497 13:59:46.868821 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2498 13:59:46.872226 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2499 13:59:46.872307
2500 13:59:46.875366 CA PerBit enable=1, Macro0, CA PI delay=32
2501 13:59:46.875447
2502 13:59:46.879212 [CBTSetCACLKResult] CA Dly = 32
2503 13:59:46.879311 CS Dly: 6 (0~38)
2504 13:59:46.879407
2505 13:59:46.882414 ----->DramcWriteLeveling(PI) begin...
2506 13:59:46.885358 ==
2507 13:59:46.885440 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 13:59:46.892394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 13:59:46.892477 ==
2510 13:59:46.895840 Write leveling (Byte 0): 33 => 33
2511 13:59:46.899459 Write leveling (Byte 1): 29 => 29
2512 13:59:46.902586 DramcWriteLeveling(PI) end<-----
2513 13:59:46.902667
2514 13:59:46.902730 ==
2515 13:59:46.905490 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 13:59:46.908909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 13:59:46.908990 ==
2518 13:59:46.912267 [Gating] SW mode calibration
2519 13:59:46.919299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2520 13:59:46.922404 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2521 13:59:46.928842 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2522 13:59:46.932140 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2523 13:59:46.935413 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 13:59:46.942289 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 13:59:46.945243 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 13:59:46.948760 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 13:59:46.955683 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2528 13:59:46.958997 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2529 13:59:46.962254 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2530 13:59:46.969041 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 13:59:46.972087 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 13:59:46.975524 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 13:59:46.982277 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 13:59:46.985467 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 13:59:46.989061 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2536 13:59:46.995628 1 0 28 | B1->B0 | 2b2b 4545 | 0 0 | (1 1) (0 0)
2537 13:59:46.998929 1 1 0 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
2538 13:59:47.002253 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 13:59:47.005975 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 13:59:47.012688 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 13:59:47.016016 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 13:59:47.019307 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 13:59:47.025998 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 13:59:47.028898 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2545 13:59:47.032343 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2546 13:59:47.038813 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 13:59:47.042169 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 13:59:47.045880 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 13:59:47.052449 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 13:59:47.056151 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 13:59:47.059230 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 13:59:47.065910 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 13:59:47.068975 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 13:59:47.072274 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:59:47.075731 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 13:59:47.082434 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 13:59:47.085975 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 13:59:47.089852 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 13:59:47.095851 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 13:59:47.099271 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2561 13:59:47.102746 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2562 13:59:47.106045 Total UI for P1: 0, mck2ui 16
2563 13:59:47.109503 best dqsien dly found for B0: ( 1, 3, 28)
2564 13:59:47.116323 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 13:59:47.116430 Total UI for P1: 0, mck2ui 16
2566 13:59:47.122703 best dqsien dly found for B1: ( 1, 3, 30)
2567 13:59:47.125964 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2568 13:59:47.129495 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2569 13:59:47.129630
2570 13:59:47.133135 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2571 13:59:47.136240 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2572 13:59:47.139715 [Gating] SW calibration Done
2573 13:59:47.139796 ==
2574 13:59:47.142893 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 13:59:47.146208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 13:59:47.146290 ==
2577 13:59:47.149801 RX Vref Scan: 0
2578 13:59:47.149911
2579 13:59:47.149976 RX Vref 0 -> 0, step: 1
2580 13:59:47.150036
2581 13:59:47.153174 RX Delay -40 -> 252, step: 8
2582 13:59:47.156395 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2583 13:59:47.163612 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2584 13:59:47.166558 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2585 13:59:47.169589 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2586 13:59:47.173440 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2587 13:59:47.176312 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2588 13:59:47.179500 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2589 13:59:47.186380 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2590 13:59:47.189879 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2591 13:59:47.193327 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2592 13:59:47.196365 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2593 13:59:47.199636 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2594 13:59:47.206853 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2595 13:59:47.209527 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2596 13:59:47.213248 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2597 13:59:47.216353 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2598 13:59:47.216434 ==
2599 13:59:47.220203 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 13:59:47.226832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 13:59:47.226914 ==
2602 13:59:47.226978 DQS Delay:
2603 13:59:47.227037 DQS0 = 0, DQS1 = 0
2604 13:59:47.230045 DQM Delay:
2605 13:59:47.230127 DQM0 = 121, DQM1 = 113
2606 13:59:47.233349 DQ Delay:
2607 13:59:47.236720 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2608 13:59:47.240209 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2609 13:59:47.243295 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2610 13:59:47.246538 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2611 13:59:47.246619
2612 13:59:47.246682
2613 13:59:47.246741 ==
2614 13:59:47.249668 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 13:59:47.253325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 13:59:47.253406 ==
2617 13:59:47.253470
2618 13:59:47.256465
2619 13:59:47.256546 TX Vref Scan disable
2620 13:59:47.260012 == TX Byte 0 ==
2621 13:59:47.263703 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2622 13:59:47.266754 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2623 13:59:47.269806 == TX Byte 1 ==
2624 13:59:47.273444 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2625 13:59:47.276689 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2626 13:59:47.276770 ==
2627 13:59:47.279732 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 13:59:47.286805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 13:59:47.286906 ==
2630 13:59:47.297337 TX Vref=22, minBit 0, minWin=25, winSum=406
2631 13:59:47.300404 TX Vref=24, minBit 0, minWin=25, winSum=415
2632 13:59:47.304566 TX Vref=26, minBit 0, minWin=26, winSum=423
2633 13:59:47.307955 TX Vref=28, minBit 1, minWin=26, winSum=423
2634 13:59:47.310457 TX Vref=30, minBit 0, minWin=26, winSum=422
2635 13:59:47.314029 TX Vref=32, minBit 0, minWin=26, winSum=423
2636 13:59:47.320839 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 26
2637 13:59:47.320946
2638 13:59:47.324193 Final TX Range 1 Vref 26
2639 13:59:47.324276
2640 13:59:47.324381 ==
2641 13:59:47.327533 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 13:59:47.330720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 13:59:47.330825 ==
2644 13:59:47.330919
2645 13:59:47.331012
2646 13:59:47.334259 TX Vref Scan disable
2647 13:59:47.337067 == TX Byte 0 ==
2648 13:59:47.340641 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2649 13:59:47.343867 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2650 13:59:47.347270 == TX Byte 1 ==
2651 13:59:47.350697 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2652 13:59:47.354434 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2653 13:59:47.354538
2654 13:59:47.357529 [DATLAT]
2655 13:59:47.357629 Freq=1200, CH0 RK0
2656 13:59:47.357723
2657 13:59:47.360724 DATLAT Default: 0xd
2658 13:59:47.360825 0, 0xFFFF, sum = 0
2659 13:59:47.364193 1, 0xFFFF, sum = 0
2660 13:59:47.364319 2, 0xFFFF, sum = 0
2661 13:59:47.367351 3, 0xFFFF, sum = 0
2662 13:59:47.367460 4, 0xFFFF, sum = 0
2663 13:59:47.370945 5, 0xFFFF, sum = 0
2664 13:59:47.371047 6, 0xFFFF, sum = 0
2665 13:59:47.374219 7, 0xFFFF, sum = 0
2666 13:59:47.374322 8, 0xFFFF, sum = 0
2667 13:59:47.377556 9, 0xFFFF, sum = 0
2668 13:59:47.377665 10, 0xFFFF, sum = 0
2669 13:59:47.380964 11, 0xFFFF, sum = 0
2670 13:59:47.381067 12, 0x0, sum = 1
2671 13:59:47.384177 13, 0x0, sum = 2
2672 13:59:47.384282 14, 0x0, sum = 3
2673 13:59:47.387555 15, 0x0, sum = 4
2674 13:59:47.387690 best_step = 13
2675 13:59:47.387766
2676 13:59:47.387858 ==
2677 13:59:47.390970 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 13:59:47.397565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 13:59:47.397671 ==
2680 13:59:47.397765 RX Vref Scan: 1
2681 13:59:47.397856
2682 13:59:47.401175 Set Vref Range= 32 -> 127
2683 13:59:47.401277
2684 13:59:47.404220 RX Vref 32 -> 127, step: 1
2685 13:59:47.404328
2686 13:59:47.404423 RX Delay -13 -> 252, step: 4
2687 13:59:47.407925
2688 13:59:47.408027 Set Vref, RX VrefLevel [Byte0]: 32
2689 13:59:47.410730 [Byte1]: 32
2690 13:59:47.415140
2691 13:59:47.415243 Set Vref, RX VrefLevel [Byte0]: 33
2692 13:59:47.418413 [Byte1]: 33
2693 13:59:47.423654
2694 13:59:47.423756 Set Vref, RX VrefLevel [Byte0]: 34
2695 13:59:47.426470 [Byte1]: 34
2696 13:59:47.431430
2697 13:59:47.431537 Set Vref, RX VrefLevel [Byte0]: 35
2698 13:59:47.434478 [Byte1]: 35
2699 13:59:47.439122
2700 13:59:47.439225 Set Vref, RX VrefLevel [Byte0]: 36
2701 13:59:47.442644 [Byte1]: 36
2702 13:59:47.447020
2703 13:59:47.447122 Set Vref, RX VrefLevel [Byte0]: 37
2704 13:59:47.450395 [Byte1]: 37
2705 13:59:47.454947
2706 13:59:47.455048 Set Vref, RX VrefLevel [Byte0]: 38
2707 13:59:47.457956 [Byte1]: 38
2708 13:59:47.462897
2709 13:59:47.463001 Set Vref, RX VrefLevel [Byte0]: 39
2710 13:59:47.466002 [Byte1]: 39
2711 13:59:47.470828
2712 13:59:47.470932 Set Vref, RX VrefLevel [Byte0]: 40
2713 13:59:47.473969 [Byte1]: 40
2714 13:59:47.478616
2715 13:59:47.478700 Set Vref, RX VrefLevel [Byte0]: 41
2716 13:59:47.481890 [Byte1]: 41
2717 13:59:47.486480
2718 13:59:47.486582 Set Vref, RX VrefLevel [Byte0]: 42
2719 13:59:47.489747 [Byte1]: 42
2720 13:59:47.494198
2721 13:59:47.494300 Set Vref, RX VrefLevel [Byte0]: 43
2722 13:59:47.497658 [Byte1]: 43
2723 13:59:47.502681
2724 13:59:47.502783 Set Vref, RX VrefLevel [Byte0]: 44
2725 13:59:47.505758 [Byte1]: 44
2726 13:59:47.510194
2727 13:59:47.510296 Set Vref, RX VrefLevel [Byte0]: 45
2728 13:59:47.513216 [Byte1]: 45
2729 13:59:47.518000
2730 13:59:47.518103 Set Vref, RX VrefLevel [Byte0]: 46
2731 13:59:47.521366 [Byte1]: 46
2732 13:59:47.526161
2733 13:59:47.526264 Set Vref, RX VrefLevel [Byte0]: 47
2734 13:59:47.529052 [Byte1]: 47
2735 13:59:47.533810
2736 13:59:47.533914 Set Vref, RX VrefLevel [Byte0]: 48
2737 13:59:47.536883 [Byte1]: 48
2738 13:59:47.541569
2739 13:59:47.541679 Set Vref, RX VrefLevel [Byte0]: 49
2740 13:59:47.544906 [Byte1]: 49
2741 13:59:47.549673
2742 13:59:47.549775 Set Vref, RX VrefLevel [Byte0]: 50
2743 13:59:47.552935 [Byte1]: 50
2744 13:59:47.557289
2745 13:59:47.557392 Set Vref, RX VrefLevel [Byte0]: 51
2746 13:59:47.560562 [Byte1]: 51
2747 13:59:47.565651
2748 13:59:47.565757 Set Vref, RX VrefLevel [Byte0]: 52
2749 13:59:47.568550 [Byte1]: 52
2750 13:59:47.573126
2751 13:59:47.573231 Set Vref, RX VrefLevel [Byte0]: 53
2752 13:59:47.576584 [Byte1]: 53
2753 13:59:47.581253
2754 13:59:47.581358 Set Vref, RX VrefLevel [Byte0]: 54
2755 13:59:47.584482 [Byte1]: 54
2756 13:59:47.589047
2757 13:59:47.589145 Set Vref, RX VrefLevel [Byte0]: 55
2758 13:59:47.592333 [Byte1]: 55
2759 13:59:47.597122
2760 13:59:47.597225 Set Vref, RX VrefLevel [Byte0]: 56
2761 13:59:47.600506 [Byte1]: 56
2762 13:59:47.604983
2763 13:59:47.605086 Set Vref, RX VrefLevel [Byte0]: 57
2764 13:59:47.608060 [Byte1]: 57
2765 13:59:47.612891
2766 13:59:47.612990 Set Vref, RX VrefLevel [Byte0]: 58
2767 13:59:47.615744 [Byte1]: 58
2768 13:59:47.620695
2769 13:59:47.620799 Set Vref, RX VrefLevel [Byte0]: 59
2770 13:59:47.624029 [Byte1]: 59
2771 13:59:47.628152
2772 13:59:47.631490 Set Vref, RX VrefLevel [Byte0]: 60
2773 13:59:47.631621 [Byte1]: 60
2774 13:59:47.636068
2775 13:59:47.636166 Set Vref, RX VrefLevel [Byte0]: 61
2776 13:59:47.639327 [Byte1]: 61
2777 13:59:47.644242
2778 13:59:47.644346 Set Vref, RX VrefLevel [Byte0]: 62
2779 13:59:47.647615 [Byte1]: 62
2780 13:59:47.652317
2781 13:59:47.652418 Set Vref, RX VrefLevel [Byte0]: 63
2782 13:59:47.655512 [Byte1]: 63
2783 13:59:47.660016
2784 13:59:47.660114 Set Vref, RX VrefLevel [Byte0]: 64
2785 13:59:47.663283 [Byte1]: 64
2786 13:59:47.667827
2787 13:59:47.667929 Set Vref, RX VrefLevel [Byte0]: 65
2788 13:59:47.671247 [Byte1]: 65
2789 13:59:47.676138
2790 13:59:47.676238 Set Vref, RX VrefLevel [Byte0]: 66
2791 13:59:47.679188 [Byte1]: 66
2792 13:59:47.683636
2793 13:59:47.683739 Set Vref, RX VrefLevel [Byte0]: 67
2794 13:59:47.686889 [Byte1]: 67
2795 13:59:47.691589
2796 13:59:47.691702 Set Vref, RX VrefLevel [Byte0]: 68
2797 13:59:47.695032 [Byte1]: 68
2798 13:59:47.699490
2799 13:59:47.699618 Set Vref, RX VrefLevel [Byte0]: 69
2800 13:59:47.702662 [Byte1]: 69
2801 13:59:47.707052
2802 13:59:47.707149 Final RX Vref Byte 0 = 56 to rank0
2803 13:59:47.710704 Final RX Vref Byte 1 = 46 to rank0
2804 13:59:47.713993 Final RX Vref Byte 0 = 56 to rank1
2805 13:59:47.717403 Final RX Vref Byte 1 = 46 to rank1==
2806 13:59:47.720635 Dram Type= 6, Freq= 0, CH_0, rank 0
2807 13:59:47.727268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2808 13:59:47.727371 ==
2809 13:59:47.727466 DQS Delay:
2810 13:59:47.727557 DQS0 = 0, DQS1 = 0
2811 13:59:47.730790 DQM Delay:
2812 13:59:47.730898 DQM0 = 121, DQM1 = 110
2813 13:59:47.734188 DQ Delay:
2814 13:59:47.737158 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =120
2815 13:59:47.740530 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2816 13:59:47.744112 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =104
2817 13:59:47.747408 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2818 13:59:47.747490
2819 13:59:47.747554
2820 13:59:47.753987 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2821 13:59:47.757209 CH0 RK0: MR19=404, MR18=160F
2822 13:59:47.763990 CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27
2823 13:59:47.764072
2824 13:59:47.767751 ----->DramcWriteLeveling(PI) begin...
2825 13:59:47.767861 ==
2826 13:59:47.770351 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 13:59:47.774656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 13:59:47.777367 ==
2829 13:59:47.777467 Write leveling (Byte 0): 35 => 35
2830 13:59:47.780723 Write leveling (Byte 1): 29 => 29
2831 13:59:47.784400 DramcWriteLeveling(PI) end<-----
2832 13:59:47.784498
2833 13:59:47.784597 ==
2834 13:59:47.787676 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 13:59:47.794253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 13:59:47.794356 ==
2837 13:59:47.794452 [Gating] SW mode calibration
2838 13:59:47.804479 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2839 13:59:47.808046 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2840 13:59:47.811129 0 15 0 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
2841 13:59:47.817654 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 13:59:47.821215 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 13:59:47.824411 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 13:59:47.831048 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 13:59:47.834345 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 13:59:47.837765 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2847 13:59:47.844561 0 15 28 | B1->B0 | 2d2d 2d2d | 0 0 | (0 0) (0 0)
2848 13:59:47.848078 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2849 13:59:47.851319 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 13:59:47.854606 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 13:59:47.861512 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 13:59:47.864867 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 13:59:47.867748 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 13:59:47.874536 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2855 13:59:47.878047 1 0 28 | B1->B0 | 3737 3939 | 0 0 | (0 0) (0 0)
2856 13:59:47.881595 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 13:59:47.888267 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 13:59:47.891181 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 13:59:47.894569 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 13:59:47.901298 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 13:59:47.904671 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 13:59:47.908629 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2863 13:59:47.914456 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2864 13:59:47.917818 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2865 13:59:47.921250 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 13:59:47.928119 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 13:59:47.931429 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 13:59:47.934811 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 13:59:47.937984 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 13:59:47.944824 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 13:59:47.948299 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 13:59:47.951547 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 13:59:47.958269 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 13:59:47.961646 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 13:59:47.964515 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 13:59:47.971723 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 13:59:47.974573 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 13:59:47.977833 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 13:59:47.984806 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2880 13:59:47.988064 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2881 13:59:47.991648 Total UI for P1: 0, mck2ui 16
2882 13:59:47.994895 best dqsien dly found for B1: ( 1, 3, 28)
2883 13:59:47.998465 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 13:59:48.001959 Total UI for P1: 0, mck2ui 16
2885 13:59:48.004863 best dqsien dly found for B0: ( 1, 3, 30)
2886 13:59:48.008583 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2887 13:59:48.011353 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2888 13:59:48.011483
2889 13:59:48.014973 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2890 13:59:48.021787 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2891 13:59:48.021888 [Gating] SW calibration Done
2892 13:59:48.021983 ==
2893 13:59:48.025073 Dram Type= 6, Freq= 0, CH_0, rank 1
2894 13:59:48.031682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 13:59:48.031790 ==
2896 13:59:48.031884 RX Vref Scan: 0
2897 13:59:48.031977
2898 13:59:48.035227 RX Vref 0 -> 0, step: 1
2899 13:59:48.035321
2900 13:59:48.038331 RX Delay -40 -> 252, step: 8
2901 13:59:48.041736 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2902 13:59:48.045066 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2903 13:59:48.048555 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2904 13:59:48.051975 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2905 13:59:48.058512 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2906 13:59:48.061863 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2907 13:59:48.065094 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2908 13:59:48.068571 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2909 13:59:48.072121 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2910 13:59:48.079063 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2911 13:59:48.082063 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2912 13:59:48.085039 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2913 13:59:48.088467 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2914 13:59:48.092052 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2915 13:59:48.098714 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2916 13:59:48.101863 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2917 13:59:48.102006 ==
2918 13:59:48.105409 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 13:59:48.108619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 13:59:48.108701 ==
2921 13:59:48.111994 DQS Delay:
2922 13:59:48.112075 DQS0 = 0, DQS1 = 0
2923 13:59:48.112139 DQM Delay:
2924 13:59:48.115090 DQM0 = 122, DQM1 = 111
2925 13:59:48.115188 DQ Delay:
2926 13:59:48.118734 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2927 13:59:48.122022 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2928 13:59:48.125563 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
2929 13:59:48.129152 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2930 13:59:48.131779
2931 13:59:48.131888
2932 13:59:48.131952 ==
2933 13:59:48.135069 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 13:59:48.138424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 13:59:48.138507 ==
2936 13:59:48.138585
2937 13:59:48.138660
2938 13:59:48.141963 TX Vref Scan disable
2939 13:59:48.142044 == TX Byte 0 ==
2940 13:59:48.148409 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2941 13:59:48.151606 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2942 13:59:48.151726 == TX Byte 1 ==
2943 13:59:48.158424 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2944 13:59:48.162034 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2945 13:59:48.162134 ==
2946 13:59:48.165400 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 13:59:48.168483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 13:59:48.168588 ==
2949 13:59:48.181372 TX Vref=22, minBit 1, minWin=25, winSum=417
2950 13:59:48.184589 TX Vref=24, minBit 3, minWin=25, winSum=424
2951 13:59:48.187982 TX Vref=26, minBit 5, minWin=25, winSum=422
2952 13:59:48.191214 TX Vref=28, minBit 1, minWin=26, winSum=431
2953 13:59:48.194763 TX Vref=30, minBit 2, minWin=26, winSum=432
2954 13:59:48.198097 TX Vref=32, minBit 5, minWin=25, winSum=427
2955 13:59:48.204577 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 30
2956 13:59:48.204677
2957 13:59:48.208483 Final TX Range 1 Vref 30
2958 13:59:48.208565
2959 13:59:48.208629 ==
2960 13:59:48.211369 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 13:59:48.214891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 13:59:48.214990 ==
2963 13:59:48.215086
2964 13:59:48.215161
2965 13:59:48.218171 TX Vref Scan disable
2966 13:59:48.221375 == TX Byte 0 ==
2967 13:59:48.224868 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2968 13:59:48.228214 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2969 13:59:48.231427 == TX Byte 1 ==
2970 13:59:48.235080 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2971 13:59:48.238448 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2972 13:59:48.238529
2973 13:59:48.241908 [DATLAT]
2974 13:59:48.241989 Freq=1200, CH0 RK1
2975 13:59:48.242053
2976 13:59:48.244800 DATLAT Default: 0xd
2977 13:59:48.244881 0, 0xFFFF, sum = 0
2978 13:59:48.248402 1, 0xFFFF, sum = 0
2979 13:59:48.248484 2, 0xFFFF, sum = 0
2980 13:59:48.252049 3, 0xFFFF, sum = 0
2981 13:59:48.252132 4, 0xFFFF, sum = 0
2982 13:59:48.254996 5, 0xFFFF, sum = 0
2983 13:59:48.255078 6, 0xFFFF, sum = 0
2984 13:59:48.258713 7, 0xFFFF, sum = 0
2985 13:59:48.258795 8, 0xFFFF, sum = 0
2986 13:59:48.261777 9, 0xFFFF, sum = 0
2987 13:59:48.261876 10, 0xFFFF, sum = 0
2988 13:59:48.265257 11, 0xFFFF, sum = 0
2989 13:59:48.265340 12, 0x0, sum = 1
2990 13:59:48.268303 13, 0x0, sum = 2
2991 13:59:48.268385 14, 0x0, sum = 3
2992 13:59:48.271941 15, 0x0, sum = 4
2993 13:59:48.272024 best_step = 13
2994 13:59:48.272088
2995 13:59:48.272178 ==
2996 13:59:48.275044 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 13:59:48.281474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 13:59:48.281555 ==
2999 13:59:48.281619 RX Vref Scan: 0
3000 13:59:48.281678
3001 13:59:48.285340 RX Vref 0 -> 0, step: 1
3002 13:59:48.285420
3003 13:59:48.288598 RX Delay -13 -> 252, step: 4
3004 13:59:48.291676 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3005 13:59:48.295129 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3006 13:59:48.302239 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3007 13:59:48.305380 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3008 13:59:48.308890 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3009 13:59:48.312025 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3010 13:59:48.315309 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3011 13:59:48.318376 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3012 13:59:48.325092 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3013 13:59:48.328379 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3014 13:59:48.331935 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3015 13:59:48.335040 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3016 13:59:48.338856 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3017 13:59:48.345151 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3018 13:59:48.348639 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3019 13:59:48.352028 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3020 13:59:48.352132 ==
3021 13:59:48.355271 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 13:59:48.358507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 13:59:48.362277 ==
3024 13:59:48.362380 DQS Delay:
3025 13:59:48.362473 DQS0 = 0, DQS1 = 0
3026 13:59:48.365754 DQM Delay:
3027 13:59:48.365855 DQM0 = 121, DQM1 = 109
3028 13:59:48.368502 DQ Delay:
3029 13:59:48.371952 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3030 13:59:48.375198 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3031 13:59:48.378822 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3032 13:59:48.381999 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3033 13:59:48.382081
3034 13:59:48.382145
3035 13:59:48.388288 [DQSOSCAuto] RK1, (LSB)MR18= 0xeee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3036 13:59:48.391756 CH0 RK1: MR19=403, MR18=EEE
3037 13:59:48.398387 CH0_RK1: MR19=0x403, MR18=0xEEE, DQSOSC=404, MR23=63, INC=40, DEC=26
3038 13:59:48.402283 [RxdqsGatingPostProcess] freq 1200
3039 13:59:48.405296 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3040 13:59:48.408827 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 13:59:48.412084 best DQS1 dly(2T, 0.5T) = (0, 11)
3042 13:59:48.415185 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 13:59:48.418869 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3044 13:59:48.422174 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 13:59:48.425479 best DQS1 dly(2T, 0.5T) = (0, 11)
3046 13:59:48.428639 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 13:59:48.432463 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3048 13:59:48.435355 Pre-setting of DQS Precalculation
3049 13:59:48.438486 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3050 13:59:48.438587 ==
3051 13:59:48.442060 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 13:59:48.449231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 13:59:48.449339 ==
3054 13:59:48.452297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3055 13:59:48.459070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3056 13:59:48.467705 [CA 0] Center 37 (7~68) winsize 62
3057 13:59:48.471127 [CA 1] Center 37 (7~68) winsize 62
3058 13:59:48.474460 [CA 2] Center 35 (5~65) winsize 61
3059 13:59:48.477881 [CA 3] Center 34 (4~64) winsize 61
3060 13:59:48.481174 [CA 4] Center 34 (5~64) winsize 60
3061 13:59:48.484292 [CA 5] Center 33 (3~63) winsize 61
3062 13:59:48.484398
3063 13:59:48.487600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3064 13:59:48.487681
3065 13:59:48.491716 [CATrainingPosCal] consider 1 rank data
3066 13:59:48.494339 u2DelayCellTimex100 = 270/100 ps
3067 13:59:48.497694 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3068 13:59:48.500968 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3069 13:59:48.504603 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3070 13:59:48.511319 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3071 13:59:48.514319 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3072 13:59:48.517974 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3073 13:59:48.518055
3074 13:59:48.521004 CA PerBit enable=1, Macro0, CA PI delay=33
3075 13:59:48.521085
3076 13:59:48.524846 [CBTSetCACLKResult] CA Dly = 33
3077 13:59:48.524930 CS Dly: 7 (0~38)
3078 13:59:48.524994 ==
3079 13:59:48.527794 Dram Type= 6, Freq= 0, CH_1, rank 1
3080 13:59:48.534704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 13:59:48.534787 ==
3082 13:59:48.537782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3083 13:59:48.544717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3084 13:59:48.553021 [CA 0] Center 37 (7~68) winsize 62
3085 13:59:48.556337 [CA 1] Center 38 (8~68) winsize 61
3086 13:59:48.559643 [CA 2] Center 35 (5~65) winsize 61
3087 13:59:48.563233 [CA 3] Center 34 (4~65) winsize 62
3088 13:59:48.566732 [CA 4] Center 34 (4~65) winsize 62
3089 13:59:48.569910 [CA 5] Center 34 (4~64) winsize 61
3090 13:59:48.569991
3091 13:59:48.573057 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3092 13:59:48.573138
3093 13:59:48.576663 [CATrainingPosCal] consider 2 rank data
3094 13:59:48.580072 u2DelayCellTimex100 = 270/100 ps
3095 13:59:48.583318 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3096 13:59:48.586689 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3097 13:59:48.590270 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3098 13:59:48.596658 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3099 13:59:48.599819 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3100 13:59:48.603288 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3101 13:59:48.603369
3102 13:59:48.606585 CA PerBit enable=1, Macro0, CA PI delay=33
3103 13:59:48.606692
3104 13:59:48.610285 [CBTSetCACLKResult] CA Dly = 33
3105 13:59:48.610366 CS Dly: 9 (0~42)
3106 13:59:48.610430
3107 13:59:48.613884 ----->DramcWriteLeveling(PI) begin...
3108 13:59:48.613966 ==
3109 13:59:48.616760 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 13:59:48.623266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 13:59:48.623349 ==
3112 13:59:48.626700 Write leveling (Byte 0): 27 => 27
3113 13:59:48.630024 Write leveling (Byte 1): 28 => 28
3114 13:59:48.630105 DramcWriteLeveling(PI) end<-----
3115 13:59:48.633797
3116 13:59:48.633878 ==
3117 13:59:48.636911 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 13:59:48.640177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 13:59:48.640259 ==
3120 13:59:48.643213 [Gating] SW mode calibration
3121 13:59:48.650191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3122 13:59:48.653671 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3123 13:59:48.659963 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 13:59:48.663499 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 13:59:48.667029 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 13:59:48.673425 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 13:59:48.676689 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 13:59:48.680614 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 13:59:48.686887 0 15 24 | B1->B0 | 3232 2c2c | 0 0 | (0 1) (1 0)
3130 13:59:48.690463 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3131 13:59:48.693463 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 13:59:48.697108 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 13:59:48.703871 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 13:59:48.707078 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 13:59:48.710383 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 13:59:48.717031 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3137 13:59:48.720387 1 0 24 | B1->B0 | 3535 4040 | 1 1 | (0 0) (0 0)
3138 13:59:48.724003 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 13:59:48.730260 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 13:59:48.733514 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 13:59:48.737030 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 13:59:48.743583 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 13:59:48.747388 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 13:59:48.750144 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 13:59:48.756986 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3146 13:59:48.760603 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3147 13:59:48.763856 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 13:59:48.770446 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 13:59:48.773880 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 13:59:48.777438 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 13:59:48.780520 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 13:59:48.787296 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 13:59:48.790506 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 13:59:48.794036 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 13:59:48.801044 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 13:59:48.803802 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 13:59:48.806977 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 13:59:48.813549 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 13:59:48.817273 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 13:59:48.820524 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 13:59:48.827130 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3162 13:59:48.830408 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3163 13:59:48.833795 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 13:59:48.837043 Total UI for P1: 0, mck2ui 16
3165 13:59:48.840337 best dqsien dly found for B0: ( 1, 3, 26)
3166 13:59:48.843539 Total UI for P1: 0, mck2ui 16
3167 13:59:48.847247 best dqsien dly found for B1: ( 1, 3, 26)
3168 13:59:48.850512 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3169 13:59:48.853641 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3170 13:59:48.853749
3171 13:59:48.857121 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3172 13:59:48.863992 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3173 13:59:48.864073 [Gating] SW calibration Done
3174 13:59:48.864138 ==
3175 13:59:48.867244 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 13:59:48.873782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 13:59:48.873874 ==
3178 13:59:48.873942 RX Vref Scan: 0
3179 13:59:48.874002
3180 13:59:48.877532 RX Vref 0 -> 0, step: 1
3181 13:59:48.877620
3182 13:59:48.880847 RX Delay -40 -> 252, step: 8
3183 13:59:48.883978 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3184 13:59:48.887426 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3185 13:59:48.890526 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3186 13:59:48.897685 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3187 13:59:48.900802 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3188 13:59:48.904000 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3189 13:59:48.907179 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3190 13:59:48.910941 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3191 13:59:48.913769 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3192 13:59:48.920697 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3193 13:59:48.923835 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3194 13:59:48.927514 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3195 13:59:48.930720 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3196 13:59:48.937227 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3197 13:59:48.941316 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3198 13:59:48.944113 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3199 13:59:48.944196 ==
3200 13:59:48.947264 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 13:59:48.950908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 13:59:48.951016 ==
3203 13:59:48.953897 DQS Delay:
3204 13:59:48.953996 DQS0 = 0, DQS1 = 0
3205 13:59:48.954094 DQM Delay:
3206 13:59:48.957494 DQM0 = 119, DQM1 = 116
3207 13:59:48.957576 DQ Delay:
3208 13:59:48.961192 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3209 13:59:48.964184 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3210 13:59:48.970965 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3211 13:59:48.973853 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3212 13:59:48.973937
3213 13:59:48.974001
3214 13:59:48.974072 ==
3215 13:59:48.977426 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 13:59:48.980709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 13:59:48.980814 ==
3218 13:59:48.980903
3219 13:59:48.980987
3220 13:59:48.984417 TX Vref Scan disable
3221 13:59:48.984489 == TX Byte 0 ==
3222 13:59:48.991240 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3223 13:59:48.994064 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3224 13:59:48.994136 == TX Byte 1 ==
3225 13:59:49.000842 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3226 13:59:49.004026 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3227 13:59:49.004100 ==
3228 13:59:49.007845 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 13:59:49.010743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 13:59:49.010823 ==
3231 13:59:49.023942 TX Vref=22, minBit 1, minWin=25, winSum=412
3232 13:59:49.026753 TX Vref=24, minBit 9, minWin=24, winSum=412
3233 13:59:49.029983 TX Vref=26, minBit 0, minWin=26, winSum=420
3234 13:59:49.033271 TX Vref=28, minBit 1, minWin=26, winSum=425
3235 13:59:49.036784 TX Vref=30, minBit 1, minWin=26, winSum=426
3236 13:59:49.040212 TX Vref=32, minBit 9, minWin=26, winSum=434
3237 13:59:49.047169 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3238 13:59:49.047251
3239 13:59:49.050753 Final TX Range 1 Vref 32
3240 13:59:49.050844
3241 13:59:49.050963 ==
3242 13:59:49.054197 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 13:59:49.056966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 13:59:49.057050 ==
3245 13:59:49.057134
3246 13:59:49.057214
3247 13:59:49.060356 TX Vref Scan disable
3248 13:59:49.063765 == TX Byte 0 ==
3249 13:59:49.067322 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3250 13:59:49.070579 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3251 13:59:49.073763 == TX Byte 1 ==
3252 13:59:49.077087 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3253 13:59:49.080530 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3254 13:59:49.080613
3255 13:59:49.084152 [DATLAT]
3256 13:59:49.084235 Freq=1200, CH1 RK0
3257 13:59:49.084319
3258 13:59:49.087719 DATLAT Default: 0xd
3259 13:59:49.087802 0, 0xFFFF, sum = 0
3260 13:59:49.090716 1, 0xFFFF, sum = 0
3261 13:59:49.090828 2, 0xFFFF, sum = 0
3262 13:59:49.093992 3, 0xFFFF, sum = 0
3263 13:59:49.094076 4, 0xFFFF, sum = 0
3264 13:59:49.097551 5, 0xFFFF, sum = 0
3265 13:59:49.097635 6, 0xFFFF, sum = 0
3266 13:59:49.100898 7, 0xFFFF, sum = 0
3267 13:59:49.100982 8, 0xFFFF, sum = 0
3268 13:59:49.103882 9, 0xFFFF, sum = 0
3269 13:59:49.103974 10, 0xFFFF, sum = 0
3270 13:59:49.107345 11, 0xFFFF, sum = 0
3271 13:59:49.107429 12, 0x0, sum = 1
3272 13:59:49.110625 13, 0x0, sum = 2
3273 13:59:49.110709 14, 0x0, sum = 3
3274 13:59:49.114190 15, 0x0, sum = 4
3275 13:59:49.114274 best_step = 13
3276 13:59:49.114358
3277 13:59:49.114437 ==
3278 13:59:49.117365 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 13:59:49.124175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 13:59:49.124260 ==
3281 13:59:49.124345 RX Vref Scan: 1
3282 13:59:49.124423
3283 13:59:49.127569 Set Vref Range= 32 -> 127
3284 13:59:49.127690
3285 13:59:49.130518 RX Vref 32 -> 127, step: 1
3286 13:59:49.130601
3287 13:59:49.130665 RX Delay -5 -> 252, step: 4
3288 13:59:49.130725
3289 13:59:49.134070 Set Vref, RX VrefLevel [Byte0]: 32
3290 13:59:49.137364 [Byte1]: 32
3291 13:59:49.141662
3292 13:59:49.141744 Set Vref, RX VrefLevel [Byte0]: 33
3293 13:59:49.144612 [Byte1]: 33
3294 13:59:49.149356
3295 13:59:49.149438 Set Vref, RX VrefLevel [Byte0]: 34
3296 13:59:49.152968 [Byte1]: 34
3297 13:59:49.157522
3298 13:59:49.157604 Set Vref, RX VrefLevel [Byte0]: 35
3299 13:59:49.160586 [Byte1]: 35
3300 13:59:49.164785
3301 13:59:49.164866 Set Vref, RX VrefLevel [Byte0]: 36
3302 13:59:49.168441 [Byte1]: 36
3303 13:59:49.173199
3304 13:59:49.173280 Set Vref, RX VrefLevel [Byte0]: 37
3305 13:59:49.175975 [Byte1]: 37
3306 13:59:49.180457
3307 13:59:49.180538 Set Vref, RX VrefLevel [Byte0]: 38
3308 13:59:49.184348 [Byte1]: 38
3309 13:59:49.188312
3310 13:59:49.188393 Set Vref, RX VrefLevel [Byte0]: 39
3311 13:59:49.191610 [Byte1]: 39
3312 13:59:49.196250
3313 13:59:49.196378 Set Vref, RX VrefLevel [Byte0]: 40
3314 13:59:49.199625 [Byte1]: 40
3315 13:59:49.204253
3316 13:59:49.204333 Set Vref, RX VrefLevel [Byte0]: 41
3317 13:59:49.207637 [Byte1]: 41
3318 13:59:49.212434
3319 13:59:49.212516 Set Vref, RX VrefLevel [Byte0]: 42
3320 13:59:49.215596 [Byte1]: 42
3321 13:59:49.219860
3322 13:59:49.219941 Set Vref, RX VrefLevel [Byte0]: 43
3323 13:59:49.223047 [Byte1]: 43
3324 13:59:49.227753
3325 13:59:49.227834 Set Vref, RX VrefLevel [Byte0]: 44
3326 13:59:49.231271 [Byte1]: 44
3327 13:59:49.236009
3328 13:59:49.236110 Set Vref, RX VrefLevel [Byte0]: 45
3329 13:59:49.239073 [Byte1]: 45
3330 13:59:49.243548
3331 13:59:49.243666 Set Vref, RX VrefLevel [Byte0]: 46
3332 13:59:49.247021 [Byte1]: 46
3333 13:59:49.251853
3334 13:59:49.251929 Set Vref, RX VrefLevel [Byte0]: 47
3335 13:59:49.254468 [Byte1]: 47
3336 13:59:49.259381
3337 13:59:49.259460 Set Vref, RX VrefLevel [Byte0]: 48
3338 13:59:49.262637 [Byte1]: 48
3339 13:59:49.266810
3340 13:59:49.266916 Set Vref, RX VrefLevel [Byte0]: 49
3341 13:59:49.270641 [Byte1]: 49
3342 13:59:49.275382
3343 13:59:49.275490 Set Vref, RX VrefLevel [Byte0]: 50
3344 13:59:49.278332 [Byte1]: 50
3345 13:59:49.282775
3346 13:59:49.282855 Set Vref, RX VrefLevel [Byte0]: 51
3347 13:59:49.285932 [Byte1]: 51
3348 13:59:49.290612
3349 13:59:49.290719 Set Vref, RX VrefLevel [Byte0]: 52
3350 13:59:49.294296 [Byte1]: 52
3351 13:59:49.298629
3352 13:59:49.298710 Set Vref, RX VrefLevel [Byte0]: 53
3353 13:59:49.301773 [Byte1]: 53
3354 13:59:49.306647
3355 13:59:49.306719 Set Vref, RX VrefLevel [Byte0]: 54
3356 13:59:49.309567 [Byte1]: 54
3357 13:59:49.314315
3358 13:59:49.314395 Set Vref, RX VrefLevel [Byte0]: 55
3359 13:59:49.317235 [Byte1]: 55
3360 13:59:49.321971
3361 13:59:49.322051 Set Vref, RX VrefLevel [Byte0]: 56
3362 13:59:49.325197 [Byte1]: 56
3363 13:59:49.329799
3364 13:59:49.329879 Set Vref, RX VrefLevel [Byte0]: 57
3365 13:59:49.333244 [Byte1]: 57
3366 13:59:49.337849
3367 13:59:49.337929 Set Vref, RX VrefLevel [Byte0]: 58
3368 13:59:49.341203 [Byte1]: 58
3369 13:59:49.345442
3370 13:59:49.345522 Set Vref, RX VrefLevel [Byte0]: 59
3371 13:59:49.348745 [Byte1]: 59
3372 13:59:49.353532
3373 13:59:49.353621 Set Vref, RX VrefLevel [Byte0]: 60
3374 13:59:49.356937 [Byte1]: 60
3375 13:59:49.361206
3376 13:59:49.361287 Set Vref, RX VrefLevel [Byte0]: 61
3377 13:59:49.364489 [Byte1]: 61
3378 13:59:49.369138
3379 13:59:49.369218 Set Vref, RX VrefLevel [Byte0]: 62
3380 13:59:49.372306 [Byte1]: 62
3381 13:59:49.376694
3382 13:59:49.376774 Set Vref, RX VrefLevel [Byte0]: 63
3383 13:59:49.380086 [Byte1]: 63
3384 13:59:49.384852
3385 13:59:49.384975 Set Vref, RX VrefLevel [Byte0]: 64
3386 13:59:49.388275 [Byte1]: 64
3387 13:59:49.392673
3388 13:59:49.392782 Set Vref, RX VrefLevel [Byte0]: 65
3389 13:59:49.395624 [Byte1]: 65
3390 13:59:49.400539
3391 13:59:49.400648 Set Vref, RX VrefLevel [Byte0]: 66
3392 13:59:49.403989 [Byte1]: 66
3393 13:59:49.408630
3394 13:59:49.408740 Set Vref, RX VrefLevel [Byte0]: 67
3395 13:59:49.411563 [Byte1]: 67
3396 13:59:49.415956
3397 13:59:49.416069 Set Vref, RX VrefLevel [Byte0]: 68
3398 13:59:49.419345 [Byte1]: 68
3399 13:59:49.424106
3400 13:59:49.424190 Set Vref, RX VrefLevel [Byte0]: 69
3401 13:59:49.427391 [Byte1]: 69
3402 13:59:49.431842
3403 13:59:49.431927 Final RX Vref Byte 0 = 54 to rank0
3404 13:59:49.435228 Final RX Vref Byte 1 = 51 to rank0
3405 13:59:49.438668 Final RX Vref Byte 0 = 54 to rank1
3406 13:59:49.441974 Final RX Vref Byte 1 = 51 to rank1==
3407 13:59:49.445374 Dram Type= 6, Freq= 0, CH_1, rank 0
3408 13:59:49.452101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3409 13:59:49.452210 ==
3410 13:59:49.452305 DQS Delay:
3411 13:59:49.452398 DQS0 = 0, DQS1 = 0
3412 13:59:49.455401 DQM Delay:
3413 13:59:49.455510 DQM0 = 120, DQM1 = 117
3414 13:59:49.459046 DQ Delay:
3415 13:59:49.461918 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3416 13:59:49.465129 DQ4 =118, DQ5 =130, DQ6 =128, DQ7 =120
3417 13:59:49.468844 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3418 13:59:49.472195 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3419 13:59:49.472295
3420 13:59:49.472389
3421 13:59:49.478518 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3422 13:59:49.481980 CH1 RK0: MR19=404, MR18=13
3423 13:59:49.488440 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3424 13:59:49.488547
3425 13:59:49.492157 ----->DramcWriteLeveling(PI) begin...
3426 13:59:49.492244 ==
3427 13:59:49.495343 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 13:59:49.498646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 13:59:49.498754 ==
3430 13:59:49.502091 Write leveling (Byte 0): 26 => 26
3431 13:59:49.505480 Write leveling (Byte 1): 29 => 29
3432 13:59:49.508695 DramcWriteLeveling(PI) end<-----
3433 13:59:49.508800
3434 13:59:49.508894 ==
3435 13:59:49.512004 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 13:59:49.515136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 13:59:49.515249 ==
3438 13:59:49.518624 [Gating] SW mode calibration
3439 13:59:49.525497 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3440 13:59:49.531825 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3441 13:59:49.535270 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 13:59:49.542535 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 13:59:49.545715 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 13:59:49.548536 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 13:59:49.555124 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 13:59:49.558664 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3447 13:59:49.561873 0 15 24 | B1->B0 | 2e2e 3434 | 1 1 | (1 0) (1 1)
3448 13:59:49.568716 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3449 13:59:49.572278 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 13:59:49.575356 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 13:59:49.578853 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 13:59:49.585514 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 13:59:49.588782 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 13:59:49.591905 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3455 13:59:49.598514 1 0 24 | B1->B0 | 4343 2b2b | 0 1 | (0 0) (0 0)
3456 13:59:49.601959 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 13:59:49.605270 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 13:59:49.612365 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 13:59:49.615154 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 13:59:49.618759 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 13:59:49.625358 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 13:59:49.628738 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3463 13:59:49.631812 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3464 13:59:49.638804 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3465 13:59:49.641614 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 13:59:49.645431 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 13:59:49.651745 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 13:59:49.655295 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 13:59:49.658255 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 13:59:49.665089 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 13:59:49.668764 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 13:59:49.672200 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 13:59:49.678392 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 13:59:49.681966 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 13:59:49.685375 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 13:59:49.691693 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 13:59:49.694920 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 13:59:49.698374 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3479 13:59:49.701796 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3480 13:59:49.708684 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3481 13:59:49.711984 Total UI for P1: 0, mck2ui 16
3482 13:59:49.715158 best dqsien dly found for B1: ( 1, 3, 22)
3483 13:59:49.718259 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 13:59:49.721819 Total UI for P1: 0, mck2ui 16
3485 13:59:49.725182 best dqsien dly found for B0: ( 1, 3, 28)
3486 13:59:49.728636 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3487 13:59:49.731551 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3488 13:59:49.731693
3489 13:59:49.735354 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3490 13:59:49.738162 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3491 13:59:49.741717 [Gating] SW calibration Done
3492 13:59:49.741826 ==
3493 13:59:49.745229 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 13:59:49.751834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 13:59:49.751945 ==
3496 13:59:49.752039 RX Vref Scan: 0
3497 13:59:49.752131
3498 13:59:49.754894 RX Vref 0 -> 0, step: 1
3499 13:59:49.754994
3500 13:59:49.758131 RX Delay -40 -> 252, step: 8
3501 13:59:49.761603 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3502 13:59:49.765128 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3503 13:59:49.767841 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3504 13:59:49.771100 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3505 13:59:49.777876 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3506 13:59:49.781342 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3507 13:59:49.784598 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3508 13:59:49.788047 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3509 13:59:49.791294 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3510 13:59:49.797944 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3511 13:59:49.801203 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3512 13:59:49.804724 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3513 13:59:49.808062 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3514 13:59:49.814523 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3515 13:59:49.817718 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3516 13:59:49.821128 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3517 13:59:49.821214 ==
3518 13:59:49.824204 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 13:59:49.827572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 13:59:49.827680 ==
3521 13:59:49.831193 DQS Delay:
3522 13:59:49.831275 DQS0 = 0, DQS1 = 0
3523 13:59:49.834264 DQM Delay:
3524 13:59:49.834347 DQM0 = 120, DQM1 = 118
3525 13:59:49.834430 DQ Delay:
3526 13:59:49.841435 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =115
3527 13:59:49.844306 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3528 13:59:49.847473 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3529 13:59:49.850810 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3530 13:59:49.850943
3531 13:59:49.851027
3532 13:59:49.851107 ==
3533 13:59:49.854418 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 13:59:49.857489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 13:59:49.857587 ==
3536 13:59:49.857671
3537 13:59:49.857750
3538 13:59:49.860568 TX Vref Scan disable
3539 13:59:49.864197 == TX Byte 0 ==
3540 13:59:49.867524 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3541 13:59:49.870846 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3542 13:59:49.874195 == TX Byte 1 ==
3543 13:59:49.877424 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3544 13:59:49.880941 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3545 13:59:49.881044 ==
3546 13:59:49.884185 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 13:59:49.887662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 13:59:49.890526 ==
3549 13:59:49.900904 TX Vref=22, minBit 0, minWin=26, winSum=421
3550 13:59:49.904026 TX Vref=24, minBit 9, minWin=25, winSum=425
3551 13:59:49.907338 TX Vref=26, minBit 2, minWin=26, winSum=431
3552 13:59:49.910644 TX Vref=28, minBit 10, minWin=25, winSum=431
3553 13:59:49.914087 TX Vref=30, minBit 9, minWin=26, winSum=437
3554 13:59:49.920815 TX Vref=32, minBit 9, minWin=26, winSum=435
3555 13:59:49.923720 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3556 13:59:49.923832
3557 13:59:49.927211 Final TX Range 1 Vref 30
3558 13:59:49.927314
3559 13:59:49.927405 ==
3560 13:59:49.930734 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 13:59:49.933953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 13:59:49.936938 ==
3563 13:59:49.937049
3564 13:59:49.937143
3565 13:59:49.937232 TX Vref Scan disable
3566 13:59:49.940272 == TX Byte 0 ==
3567 13:59:49.943851 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3568 13:59:49.947683 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3569 13:59:49.950395 == TX Byte 1 ==
3570 13:59:49.953940 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3571 13:59:49.957225 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3572 13:59:49.960556
3573 13:59:49.960661 [DATLAT]
3574 13:59:49.960755 Freq=1200, CH1 RK1
3575 13:59:49.960846
3576 13:59:49.964184 DATLAT Default: 0xd
3577 13:59:49.964283 0, 0xFFFF, sum = 0
3578 13:59:49.967316 1, 0xFFFF, sum = 0
3579 13:59:49.967416 2, 0xFFFF, sum = 0
3580 13:59:49.970416 3, 0xFFFF, sum = 0
3581 13:59:49.973588 4, 0xFFFF, sum = 0
3582 13:59:49.973697 5, 0xFFFF, sum = 0
3583 13:59:49.977095 6, 0xFFFF, sum = 0
3584 13:59:49.977207 7, 0xFFFF, sum = 0
3585 13:59:49.980490 8, 0xFFFF, sum = 0
3586 13:59:49.980596 9, 0xFFFF, sum = 0
3587 13:59:49.984115 10, 0xFFFF, sum = 0
3588 13:59:49.984225 11, 0xFFFF, sum = 0
3589 13:59:49.987169 12, 0x0, sum = 1
3590 13:59:49.987245 13, 0x0, sum = 2
3591 13:59:49.990745 14, 0x0, sum = 3
3592 13:59:49.990814 15, 0x0, sum = 4
3593 13:59:49.993898 best_step = 13
3594 13:59:49.993978
3595 13:59:49.994041 ==
3596 13:59:49.997295 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 13:59:50.000334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 13:59:50.000414 ==
3599 13:59:50.000477 RX Vref Scan: 0
3600 13:59:50.000535
3601 13:59:50.003721 RX Vref 0 -> 0, step: 1
3602 13:59:50.003819
3603 13:59:50.007030 RX Delay -5 -> 252, step: 4
3604 13:59:50.010643 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3605 13:59:50.016900 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3606 13:59:50.020399 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3607 13:59:50.023776 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3608 13:59:50.027527 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3609 13:59:50.030647 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3610 13:59:50.037106 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3611 13:59:50.040503 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3612 13:59:50.043838 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3613 13:59:50.047307 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3614 13:59:50.050246 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3615 13:59:50.056842 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3616 13:59:50.060490 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3617 13:59:50.063687 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3618 13:59:50.067161 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3619 13:59:50.069958 iDelay=195, Bit 15, Center 126 (63 ~ 190) 128
3620 13:59:50.073396 ==
3621 13:59:50.073472 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 13:59:50.080575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 13:59:50.080680 ==
3624 13:59:50.080772 DQS Delay:
3625 13:59:50.083481 DQS0 = 0, DQS1 = 0
3626 13:59:50.083583 DQM Delay:
3627 13:59:50.086642 DQM0 = 120, DQM1 = 117
3628 13:59:50.086718 DQ Delay:
3629 13:59:50.090268 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3630 13:59:50.094056 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3631 13:59:50.096692 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3632 13:59:50.100124 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3633 13:59:50.100225
3634 13:59:50.100290
3635 13:59:50.109893 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3636 13:59:50.109998 CH1 RK1: MR19=403, MR18=11ED
3637 13:59:50.116797 CH1_RK1: MR19=0x403, MR18=0x11ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3638 13:59:50.120242 [RxdqsGatingPostProcess] freq 1200
3639 13:59:50.126800 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3640 13:59:50.130253 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 13:59:50.133649 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 13:59:50.137084 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 13:59:50.140015 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 13:59:50.143327 best DQS0 dly(2T, 0.5T) = (0, 11)
3645 13:59:50.143423 best DQS1 dly(2T, 0.5T) = (0, 11)
3646 13:59:50.146818 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3647 13:59:50.150182 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3648 13:59:50.153567 Pre-setting of DQS Precalculation
3649 13:59:50.160456 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3650 13:59:50.166787 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3651 13:59:50.173849 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3652 13:59:50.173957
3653 13:59:50.174051
3654 13:59:50.177152 [Calibration Summary] 2400 Mbps
3655 13:59:50.177254 CH 0, Rank 0
3656 13:59:50.180369 SW Impedance : PASS
3657 13:59:50.183827 DUTY Scan : NO K
3658 13:59:50.183917 ZQ Calibration : PASS
3659 13:59:50.187349 Jitter Meter : NO K
3660 13:59:50.190255 CBT Training : PASS
3661 13:59:50.190354 Write leveling : PASS
3662 13:59:50.193471 RX DQS gating : PASS
3663 13:59:50.196683 RX DQ/DQS(RDDQC) : PASS
3664 13:59:50.196788 TX DQ/DQS : PASS
3665 13:59:50.200089 RX DATLAT : PASS
3666 13:59:50.203735 RX DQ/DQS(Engine): PASS
3667 13:59:50.203838 TX OE : NO K
3668 13:59:50.206564 All Pass.
3669 13:59:50.206664
3670 13:59:50.206756 CH 0, Rank 1
3671 13:59:50.209922 SW Impedance : PASS
3672 13:59:50.210018 DUTY Scan : NO K
3673 13:59:50.213570 ZQ Calibration : PASS
3674 13:59:50.216757 Jitter Meter : NO K
3675 13:59:50.216859 CBT Training : PASS
3676 13:59:50.220251 Write leveling : PASS
3677 13:59:50.223728 RX DQS gating : PASS
3678 13:59:50.223803 RX DQ/DQS(RDDQC) : PASS
3679 13:59:50.227109 TX DQ/DQS : PASS
3680 13:59:50.227206 RX DATLAT : PASS
3681 13:59:50.230444 RX DQ/DQS(Engine): PASS
3682 13:59:50.233360 TX OE : NO K
3683 13:59:50.233443 All Pass.
3684 13:59:50.233550
3685 13:59:50.233609 CH 1, Rank 0
3686 13:59:50.236490 SW Impedance : PASS
3687 13:59:50.239934 DUTY Scan : NO K
3688 13:59:50.240010 ZQ Calibration : PASS
3689 13:59:50.243357 Jitter Meter : NO K
3690 13:59:50.246733 CBT Training : PASS
3691 13:59:50.246801 Write leveling : PASS
3692 13:59:50.250044 RX DQS gating : PASS
3693 13:59:50.253799 RX DQ/DQS(RDDQC) : PASS
3694 13:59:50.253879 TX DQ/DQS : PASS
3695 13:59:50.256923 RX DATLAT : PASS
3696 13:59:50.260152 RX DQ/DQS(Engine): PASS
3697 13:59:50.260252 TX OE : NO K
3698 13:59:50.263507 All Pass.
3699 13:59:50.263629
3700 13:59:50.263733 CH 1, Rank 1
3701 13:59:50.266972 SW Impedance : PASS
3702 13:59:50.267071 DUTY Scan : NO K
3703 13:59:50.269810 ZQ Calibration : PASS
3704 13:59:50.273363 Jitter Meter : NO K
3705 13:59:50.273464 CBT Training : PASS
3706 13:59:50.276576 Write leveling : PASS
3707 13:59:50.276681 RX DQS gating : PASS
3708 13:59:50.279921 RX DQ/DQS(RDDQC) : PASS
3709 13:59:50.283496 TX DQ/DQS : PASS
3710 13:59:50.283613 RX DATLAT : PASS
3711 13:59:50.286725 RX DQ/DQS(Engine): PASS
3712 13:59:50.289603 TX OE : NO K
3713 13:59:50.289700 All Pass.
3714 13:59:50.289792
3715 13:59:50.292910 DramC Write-DBI off
3716 13:59:50.293009 PER_BANK_REFRESH: Hybrid Mode
3717 13:59:50.296708 TX_TRACKING: ON
3718 13:59:50.306231 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3719 13:59:50.309734 [FAST_K] Save calibration result to emmc
3720 13:59:50.313100 dramc_set_vcore_voltage set vcore to 650000
3721 13:59:50.313203 Read voltage for 600, 5
3722 13:59:50.316474 Vio18 = 0
3723 13:59:50.316588 Vcore = 650000
3724 13:59:50.316684 Vdram = 0
3725 13:59:50.319773 Vddq = 0
3726 13:59:50.319874 Vmddr = 0
3727 13:59:50.326318 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3728 13:59:50.329936 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3729 13:59:50.332999 MEM_TYPE=3, freq_sel=19
3730 13:59:50.336258 sv_algorithm_assistance_LP4_1600
3731 13:59:50.339901 ============ PULL DRAM RESETB DOWN ============
3732 13:59:50.342787 ========== PULL DRAM RESETB DOWN end =========
3733 13:59:50.349545 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3734 13:59:50.353016 ===================================
3735 13:59:50.353116 LPDDR4 DRAM CONFIGURATION
3736 13:59:50.356529 ===================================
3737 13:59:50.359517 EX_ROW_EN[0] = 0x0
3738 13:59:50.359650 EX_ROW_EN[1] = 0x0
3739 13:59:50.362707 LP4Y_EN = 0x0
3740 13:59:50.362792 WORK_FSP = 0x0
3741 13:59:50.366180 WL = 0x2
3742 13:59:50.369818 RL = 0x2
3743 13:59:50.369921 BL = 0x2
3744 13:59:50.373016 RPST = 0x0
3745 13:59:50.373113 RD_PRE = 0x0
3746 13:59:50.376200 WR_PRE = 0x1
3747 13:59:50.376298 WR_PST = 0x0
3748 13:59:50.379427 DBI_WR = 0x0
3749 13:59:50.379523 DBI_RD = 0x0
3750 13:59:50.382726 OTF = 0x1
3751 13:59:50.386032 ===================================
3752 13:59:50.389480 ===================================
3753 13:59:50.389581 ANA top config
3754 13:59:50.393159 ===================================
3755 13:59:50.396510 DLL_ASYNC_EN = 0
3756 13:59:50.399700 ALL_SLAVE_EN = 1
3757 13:59:50.399786 NEW_RANK_MODE = 1
3758 13:59:50.402818 DLL_IDLE_MODE = 1
3759 13:59:50.406296 LP45_APHY_COMB_EN = 1
3760 13:59:50.409695 TX_ODT_DIS = 1
3761 13:59:50.409779 NEW_8X_MODE = 1
3762 13:59:50.412951 ===================================
3763 13:59:50.416731 ===================================
3764 13:59:50.419413 data_rate = 1200
3765 13:59:50.422899 CKR = 1
3766 13:59:50.426939 DQ_P2S_RATIO = 8
3767 13:59:50.429763 ===================================
3768 13:59:50.433043 CA_P2S_RATIO = 8
3769 13:59:50.436261 DQ_CA_OPEN = 0
3770 13:59:50.436344 DQ_SEMI_OPEN = 0
3771 13:59:50.439545 CA_SEMI_OPEN = 0
3772 13:59:50.442785 CA_FULL_RATE = 0
3773 13:59:50.446336 DQ_CKDIV4_EN = 1
3774 13:59:50.449213 CA_CKDIV4_EN = 1
3775 13:59:50.452702 CA_PREDIV_EN = 0
3776 13:59:50.452803 PH8_DLY = 0
3777 13:59:50.456390 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3778 13:59:50.459175 DQ_AAMCK_DIV = 4
3779 13:59:50.462469 CA_AAMCK_DIV = 4
3780 13:59:50.465859 CA_ADMCK_DIV = 4
3781 13:59:50.469183 DQ_TRACK_CA_EN = 0
3782 13:59:50.469284 CA_PICK = 600
3783 13:59:50.472576 CA_MCKIO = 600
3784 13:59:50.476100 MCKIO_SEMI = 0
3785 13:59:50.479490 PLL_FREQ = 2288
3786 13:59:50.482746 DQ_UI_PI_RATIO = 32
3787 13:59:50.485818 CA_UI_PI_RATIO = 0
3788 13:59:50.489279 ===================================
3789 13:59:50.492329 ===================================
3790 13:59:50.495904 memory_type:LPDDR4
3791 13:59:50.496010 GP_NUM : 10
3792 13:59:50.498896 SRAM_EN : 1
3793 13:59:50.498999 MD32_EN : 0
3794 13:59:50.502541 ===================================
3795 13:59:50.505569 [ANA_INIT] >>>>>>>>>>>>>>
3796 13:59:50.509473 <<<<<< [CONFIGURE PHASE]: ANA_TX
3797 13:59:50.512412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3798 13:59:50.515815 ===================================
3799 13:59:50.519138 data_rate = 1200,PCW = 0X5800
3800 13:59:50.522655 ===================================
3801 13:59:50.525772 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3802 13:59:50.528864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3803 13:59:50.535699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 13:59:50.539050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3805 13:59:50.545971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3806 13:59:50.548777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3807 13:59:50.548882 [ANA_INIT] flow start
3808 13:59:50.552548 [ANA_INIT] PLL >>>>>>>>
3809 13:59:50.555942 [ANA_INIT] PLL <<<<<<<<
3810 13:59:50.556045 [ANA_INIT] MIDPI >>>>>>>>
3811 13:59:50.559373 [ANA_INIT] MIDPI <<<<<<<<
3812 13:59:50.562528 [ANA_INIT] DLL >>>>>>>>
3813 13:59:50.562615 [ANA_INIT] flow end
3814 13:59:50.568598 ============ LP4 DIFF to SE enter ============
3815 13:59:50.571987 ============ LP4 DIFF to SE exit ============
3816 13:59:50.572086 [ANA_INIT] <<<<<<<<<<<<<
3817 13:59:50.575448 [Flow] Enable top DCM control >>>>>
3818 13:59:50.578696 [Flow] Enable top DCM control <<<<<
3819 13:59:50.582360 Enable DLL master slave shuffle
3820 13:59:50.588410 ==============================================================
3821 13:59:50.591979 Gating Mode config
3822 13:59:50.595144 ==============================================================
3823 13:59:50.598481 Config description:
3824 13:59:50.608092 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3825 13:59:50.614925 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3826 13:59:50.618379 SELPH_MODE 0: By rank 1: By Phase
3827 13:59:50.625119 ==============================================================
3828 13:59:50.627902 GAT_TRACK_EN = 1
3829 13:59:50.631559 RX_GATING_MODE = 2
3830 13:59:50.634748 RX_GATING_TRACK_MODE = 2
3831 13:59:50.638409 SELPH_MODE = 1
3832 13:59:50.638508 PICG_EARLY_EN = 1
3833 13:59:50.641202 VALID_LAT_VALUE = 1
3834 13:59:50.648214 ==============================================================
3835 13:59:50.651153 Enter into Gating configuration >>>>
3836 13:59:50.654783 Exit from Gating configuration <<<<
3837 13:59:50.657919 Enter into DVFS_PRE_config >>>>>
3838 13:59:50.667918 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3839 13:59:50.671154 Exit from DVFS_PRE_config <<<<<
3840 13:59:50.674671 Enter into PICG configuration >>>>
3841 13:59:50.677673 Exit from PICG configuration <<<<
3842 13:59:50.680991 [RX_INPUT] configuration >>>>>
3843 13:59:50.684463 [RX_INPUT] configuration <<<<<
3844 13:59:50.687506 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3845 13:59:50.694656 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3846 13:59:50.701106 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3847 13:59:50.707400 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3848 13:59:50.714217 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3849 13:59:50.720759 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3850 13:59:50.724389 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3851 13:59:50.727750 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3852 13:59:50.730698 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3853 13:59:50.734388 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3854 13:59:50.740600 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3855 13:59:50.744002 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3856 13:59:50.747545 ===================================
3857 13:59:50.750948 LPDDR4 DRAM CONFIGURATION
3858 13:59:50.754474 ===================================
3859 13:59:50.754576 EX_ROW_EN[0] = 0x0
3860 13:59:50.757796 EX_ROW_EN[1] = 0x0
3861 13:59:50.757897 LP4Y_EN = 0x0
3862 13:59:50.761297 WORK_FSP = 0x0
3863 13:59:50.761397 WL = 0x2
3864 13:59:50.764228 RL = 0x2
3865 13:59:50.764332 BL = 0x2
3866 13:59:50.767603 RPST = 0x0
3867 13:59:50.767721 RD_PRE = 0x0
3868 13:59:50.771191 WR_PRE = 0x1
3869 13:59:50.774178 WR_PST = 0x0
3870 13:59:50.774281 DBI_WR = 0x0
3871 13:59:50.777329 DBI_RD = 0x0
3872 13:59:50.777431 OTF = 0x1
3873 13:59:50.781649 ===================================
3874 13:59:50.784114 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3875 13:59:50.787682 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3876 13:59:50.794308 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3877 13:59:50.797431 ===================================
3878 13:59:50.800944 LPDDR4 DRAM CONFIGURATION
3879 13:59:50.803932 ===================================
3880 13:59:50.804032 EX_ROW_EN[0] = 0x10
3881 13:59:50.807461 EX_ROW_EN[1] = 0x0
3882 13:59:50.807562 LP4Y_EN = 0x0
3883 13:59:50.810908 WORK_FSP = 0x0
3884 13:59:50.811003 WL = 0x2
3885 13:59:50.813913 RL = 0x2
3886 13:59:50.814017 BL = 0x2
3887 13:59:50.817407 RPST = 0x0
3888 13:59:50.817503 RD_PRE = 0x0
3889 13:59:50.821082 WR_PRE = 0x1
3890 13:59:50.821182 WR_PST = 0x0
3891 13:59:50.824200 DBI_WR = 0x0
3892 13:59:50.824297 DBI_RD = 0x0
3893 13:59:50.827484 OTF = 0x1
3894 13:59:50.830947 ===================================
3895 13:59:50.837771 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3896 13:59:50.840732 nWR fixed to 30
3897 13:59:50.844012 [ModeRegInit_LP4] CH0 RK0
3898 13:59:50.844112 [ModeRegInit_LP4] CH0 RK1
3899 13:59:50.847304 [ModeRegInit_LP4] CH1 RK0
3900 13:59:50.850934 [ModeRegInit_LP4] CH1 RK1
3901 13:59:50.851040 match AC timing 17
3902 13:59:50.857301 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3903 13:59:50.860646 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3904 13:59:50.864062 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3905 13:59:50.870712 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3906 13:59:50.874072 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3907 13:59:50.874163 ==
3908 13:59:50.877442 Dram Type= 6, Freq= 0, CH_0, rank 0
3909 13:59:50.880679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3910 13:59:50.880782 ==
3911 13:59:50.887396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3912 13:59:50.893977 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3913 13:59:50.897185 [CA 0] Center 35 (5~66) winsize 62
3914 13:59:50.900846 [CA 1] Center 35 (5~66) winsize 62
3915 13:59:50.904279 [CA 2] Center 33 (3~64) winsize 62
3916 13:59:50.907340 [CA 3] Center 33 (2~64) winsize 63
3917 13:59:50.910209 [CA 4] Center 33 (2~64) winsize 63
3918 13:59:50.913754 [CA 5] Center 32 (2~63) winsize 62
3919 13:59:50.913857
3920 13:59:50.916935 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3921 13:59:50.917031
3922 13:59:50.920278 [CATrainingPosCal] consider 1 rank data
3923 13:59:50.923854 u2DelayCellTimex100 = 270/100 ps
3924 13:59:50.926791 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3925 13:59:50.930353 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3926 13:59:50.933644 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3927 13:59:50.937259 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3928 13:59:50.940364 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3929 13:59:50.943842 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3930 13:59:50.943947
3931 13:59:50.950671 CA PerBit enable=1, Macro0, CA PI delay=32
3932 13:59:50.950776
3933 13:59:50.950872 [CBTSetCACLKResult] CA Dly = 32
3934 13:59:50.953784 CS Dly: 4 (0~35)
3935 13:59:50.953884 ==
3936 13:59:50.957112 Dram Type= 6, Freq= 0, CH_0, rank 1
3937 13:59:50.960520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3938 13:59:50.960621 ==
3939 13:59:50.967219 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3940 13:59:50.974152 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3941 13:59:50.977635 [CA 0] Center 35 (5~66) winsize 62
3942 13:59:50.980550 [CA 1] Center 35 (5~66) winsize 62
3943 13:59:50.984046 [CA 2] Center 34 (3~65) winsize 63
3944 13:59:50.987485 [CA 3] Center 33 (3~64) winsize 62
3945 13:59:50.990683 [CA 4] Center 32 (2~63) winsize 62
3946 13:59:50.994170 [CA 5] Center 32 (2~63) winsize 62
3947 13:59:50.994267
3948 13:59:50.997499 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3949 13:59:50.997596
3950 13:59:51.000709 [CATrainingPosCal] consider 2 rank data
3951 13:59:51.003621 u2DelayCellTimex100 = 270/100 ps
3952 13:59:51.007338 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3953 13:59:51.010430 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3954 13:59:51.013447 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3955 13:59:51.016853 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3956 13:59:51.020318 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3957 13:59:51.023917 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3958 13:59:51.024019
3959 13:59:51.030381 CA PerBit enable=1, Macro0, CA PI delay=32
3960 13:59:51.030486
3961 13:59:51.033910 [CBTSetCACLKResult] CA Dly = 32
3962 13:59:51.034015 CS Dly: 4 (0~36)
3963 13:59:51.034106
3964 13:59:51.036814 ----->DramcWriteLeveling(PI) begin...
3965 13:59:51.036918 ==
3966 13:59:51.040760 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 13:59:51.043558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 13:59:51.043683 ==
3969 13:59:51.047032 Write leveling (Byte 0): 35 => 35
3970 13:59:51.050678 Write leveling (Byte 1): 31 => 31
3971 13:59:51.053793 DramcWriteLeveling(PI) end<-----
3972 13:59:51.053897
3973 13:59:51.053990 ==
3974 13:59:51.056998 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 13:59:51.063529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 13:59:51.063660 ==
3977 13:59:51.063754 [Gating] SW mode calibration
3978 13:59:51.073522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3979 13:59:51.077004 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3980 13:59:51.080377 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 13:59:51.087388 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 13:59:51.090345 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 13:59:51.093903 0 9 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
3984 13:59:51.100096 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
3985 13:59:51.103578 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 13:59:51.107022 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 13:59:51.113270 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 13:59:51.116794 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 13:59:51.119993 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 13:59:51.126624 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3991 13:59:51.130241 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
3992 13:59:51.133714 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3993 13:59:51.140383 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 13:59:51.143747 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 13:59:51.146961 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 13:59:51.153249 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 13:59:51.156760 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 13:59:51.160627 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 13:59:51.163484 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4000 13:59:51.170022 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 13:59:51.173633 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 13:59:51.176808 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 13:59:51.183660 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 13:59:51.186864 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 13:59:51.189861 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 13:59:51.196834 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 13:59:51.200193 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 13:59:51.203443 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 13:59:51.209988 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 13:59:51.213608 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 13:59:51.216358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 13:59:51.223068 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 13:59:51.226892 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 13:59:51.230434 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 13:59:51.236659 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 13:59:51.239781 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4017 13:59:51.242976 Total UI for P1: 0, mck2ui 16
4018 13:59:51.246721 best dqsien dly found for B0: ( 0, 13, 14)
4019 13:59:51.249840 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 13:59:51.253361 Total UI for P1: 0, mck2ui 16
4021 13:59:51.257135 best dqsien dly found for B1: ( 0, 13, 16)
4022 13:59:51.259790 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4023 13:59:51.263300 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4024 13:59:51.263404
4025 13:59:51.269997 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4026 13:59:51.273297 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4027 13:59:51.273400 [Gating] SW calibration Done
4028 13:59:51.276695 ==
4029 13:59:51.279803 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 13:59:51.283122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 13:59:51.283224 ==
4032 13:59:51.283324 RX Vref Scan: 0
4033 13:59:51.283419
4034 13:59:51.286476 RX Vref 0 -> 0, step: 1
4035 13:59:51.286592
4036 13:59:51.289540 RX Delay -230 -> 252, step: 16
4037 13:59:51.292972 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4038 13:59:51.296203 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4039 13:59:51.303093 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4040 13:59:51.306459 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4041 13:59:51.309779 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4042 13:59:51.313305 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4043 13:59:51.316228 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4044 13:59:51.323257 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4045 13:59:51.326182 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4046 13:59:51.329710 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4047 13:59:51.332849 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4048 13:59:51.339427 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4049 13:59:51.342719 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4050 13:59:51.346156 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4051 13:59:51.349475 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4052 13:59:51.355885 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4053 13:59:51.355994 ==
4054 13:59:51.359357 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 13:59:51.363031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 13:59:51.363116 ==
4057 13:59:51.363200 DQS Delay:
4058 13:59:51.366324 DQS0 = 0, DQS1 = 0
4059 13:59:51.366407 DQM Delay:
4060 13:59:51.369656 DQM0 = 51, DQM1 = 45
4061 13:59:51.369739 DQ Delay:
4062 13:59:51.373056 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4063 13:59:51.376635 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4064 13:59:51.379211 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4065 13:59:51.383031 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4066 13:59:51.383114
4067 13:59:51.383198
4068 13:59:51.383277 ==
4069 13:59:51.385955 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 13:59:51.389726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 13:59:51.389810 ==
4072 13:59:51.389910
4073 13:59:51.390007
4074 13:59:51.393067 TX Vref Scan disable
4075 13:59:51.396075 == TX Byte 0 ==
4076 13:59:51.399629 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4077 13:59:51.402772 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4078 13:59:51.406367 == TX Byte 1 ==
4079 13:59:51.409306 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4080 13:59:51.412876 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4081 13:59:51.412967 ==
4082 13:59:51.416049 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 13:59:51.422686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 13:59:51.422771 ==
4085 13:59:51.422855
4086 13:59:51.422933
4087 13:59:51.423028 TX Vref Scan disable
4088 13:59:51.427141 == TX Byte 0 ==
4089 13:59:51.430508 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4090 13:59:51.436917 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4091 13:59:51.437000 == TX Byte 1 ==
4092 13:59:51.440592 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4093 13:59:51.444080 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4094 13:59:51.446961
4095 13:59:51.447067 [DATLAT]
4096 13:59:51.447151 Freq=600, CH0 RK0
4097 13:59:51.447237
4098 13:59:51.450107 DATLAT Default: 0x9
4099 13:59:51.450187 0, 0xFFFF, sum = 0
4100 13:59:51.453579 1, 0xFFFF, sum = 0
4101 13:59:51.453662 2, 0xFFFF, sum = 0
4102 13:59:51.456755 3, 0xFFFF, sum = 0
4103 13:59:51.460359 4, 0xFFFF, sum = 0
4104 13:59:51.460440 5, 0xFFFF, sum = 0
4105 13:59:51.463511 6, 0xFFFF, sum = 0
4106 13:59:51.463653 7, 0xFFFF, sum = 0
4107 13:59:51.463720 8, 0x0, sum = 1
4108 13:59:51.466881 9, 0x0, sum = 2
4109 13:59:51.466965 10, 0x0, sum = 3
4110 13:59:51.470294 11, 0x0, sum = 4
4111 13:59:51.470376 best_step = 9
4112 13:59:51.470439
4113 13:59:51.470497 ==
4114 13:59:51.473747 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 13:59:51.480131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 13:59:51.480242 ==
4117 13:59:51.480340 RX Vref Scan: 1
4118 13:59:51.480431
4119 13:59:51.483564 RX Vref 0 -> 0, step: 1
4120 13:59:51.483702
4121 13:59:51.486841 RX Delay -163 -> 252, step: 8
4122 13:59:51.486942
4123 13:59:51.490755 Set Vref, RX VrefLevel [Byte0]: 56
4124 13:59:51.493736 [Byte1]: 46
4125 13:59:51.493839
4126 13:59:51.497388 Final RX Vref Byte 0 = 56 to rank0
4127 13:59:51.500397 Final RX Vref Byte 1 = 46 to rank0
4128 13:59:51.503861 Final RX Vref Byte 0 = 56 to rank1
4129 13:59:51.507423 Final RX Vref Byte 1 = 46 to rank1==
4130 13:59:51.510419 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 13:59:51.513702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 13:59:51.513800 ==
4133 13:59:51.517146 DQS Delay:
4134 13:59:51.517243 DQS0 = 0, DQS1 = 0
4135 13:59:51.517336 DQM Delay:
4136 13:59:51.520416 DQM0 = 52, DQM1 = 45
4137 13:59:51.520513 DQ Delay:
4138 13:59:51.523741 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4139 13:59:51.527133 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4140 13:59:51.530109 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4141 13:59:51.533816 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4142 13:59:51.533899
4143 13:59:51.533962
4144 13:59:51.543304 [DQSOSCAuto] RK0, (LSB)MR18= 0x7063, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4145 13:59:51.543416 CH0 RK0: MR19=808, MR18=7063
4146 13:59:51.549931 CH0_RK0: MR19=0x808, MR18=0x7063, DQSOSC=388, MR23=63, INC=174, DEC=116
4147 13:59:51.550040
4148 13:59:51.553222 ----->DramcWriteLeveling(PI) begin...
4149 13:59:51.556515 ==
4150 13:59:51.556615 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 13:59:51.563477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 13:59:51.563577 ==
4153 13:59:51.566932 Write leveling (Byte 0): 33 => 33
4154 13:59:51.569968 Write leveling (Byte 1): 30 => 30
4155 13:59:51.573605 DramcWriteLeveling(PI) end<-----
4156 13:59:51.573703
4157 13:59:51.573794 ==
4158 13:59:51.576719 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 13:59:51.579881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 13:59:51.579981 ==
4161 13:59:51.583791 [Gating] SW mode calibration
4162 13:59:51.589840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4163 13:59:51.593698 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4164 13:59:51.600145 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 13:59:51.603203 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 13:59:51.606524 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 13:59:51.613597 0 9 12 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
4168 13:59:51.617001 0 9 16 | B1->B0 | 2b2b 2929 | 0 0 | (0 0) (1 1)
4169 13:59:51.619990 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 13:59:51.626594 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 13:59:51.629954 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 13:59:51.633779 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 13:59:51.640124 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 13:59:51.643466 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 13:59:51.646996 0 10 12 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)
4176 13:59:51.653202 0 10 16 | B1->B0 | 4343 4545 | 0 1 | (0 0) (0 0)
4177 13:59:51.656864 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 13:59:51.660055 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 13:59:51.666629 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 13:59:51.669984 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 13:59:51.673245 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 13:59:51.680081 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 13:59:51.683265 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4184 13:59:51.686506 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 13:59:51.693463 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 13:59:51.696638 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 13:59:51.700121 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 13:59:51.703453 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 13:59:51.709849 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 13:59:51.712989 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 13:59:51.716230 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 13:59:51.723146 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 13:59:51.726600 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 13:59:51.730096 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 13:59:51.736389 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 13:59:51.739385 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 13:59:51.743470 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 13:59:51.749473 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 13:59:51.752837 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4200 13:59:51.756158 Total UI for P1: 0, mck2ui 16
4201 13:59:51.759714 best dqsien dly found for B0: ( 0, 13, 10)
4202 13:59:51.762816 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 13:59:51.766525 Total UI for P1: 0, mck2ui 16
4204 13:59:51.769650 best dqsien dly found for B1: ( 0, 13, 12)
4205 13:59:51.772923 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4206 13:59:51.776242 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4207 13:59:51.776323
4208 13:59:51.783630 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4209 13:59:51.786227 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4210 13:59:51.789666 [Gating] SW calibration Done
4211 13:59:51.789767 ==
4212 13:59:51.792612 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 13:59:51.795933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 13:59:51.796014 ==
4215 13:59:51.796077 RX Vref Scan: 0
4216 13:59:51.796136
4217 13:59:51.799255 RX Vref 0 -> 0, step: 1
4218 13:59:51.799336
4219 13:59:51.802666 RX Delay -230 -> 252, step: 16
4220 13:59:51.806134 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4221 13:59:51.809568 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4222 13:59:51.816256 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4223 13:59:51.819508 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4224 13:59:51.822813 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4225 13:59:51.826053 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4226 13:59:51.832457 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4227 13:59:51.835833 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4228 13:59:51.839489 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4229 13:59:51.843107 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4230 13:59:51.846011 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4231 13:59:51.852907 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4232 13:59:51.856197 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4233 13:59:51.859387 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4234 13:59:51.863150 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4235 13:59:51.869744 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4236 13:59:51.869849 ==
4237 13:59:51.872608 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 13:59:51.875955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 13:59:51.876037 ==
4240 13:59:51.876129 DQS Delay:
4241 13:59:51.879526 DQS0 = 0, DQS1 = 0
4242 13:59:51.879644 DQM Delay:
4243 13:59:51.882841 DQM0 = 49, DQM1 = 42
4244 13:59:51.882940 DQ Delay:
4245 13:59:51.885837 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4246 13:59:51.889387 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4247 13:59:51.893050 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4248 13:59:51.895975 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4249 13:59:51.896074
4250 13:59:51.896144
4251 13:59:51.896232 ==
4252 13:59:51.899450 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 13:59:51.902902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 13:59:51.903004 ==
4255 13:59:51.905889
4256 13:59:51.905987
4257 13:59:51.906076 TX Vref Scan disable
4258 13:59:51.909823 == TX Byte 0 ==
4259 13:59:51.912848 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4260 13:59:51.916142 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4261 13:59:51.919254 == TX Byte 1 ==
4262 13:59:51.922549 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4263 13:59:51.925864 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4264 13:59:51.925968 ==
4265 13:59:51.929541 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 13:59:51.935763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 13:59:51.935916 ==
4268 13:59:51.936012
4269 13:59:51.936104
4270 13:59:51.936190 TX Vref Scan disable
4271 13:59:51.940229 == TX Byte 0 ==
4272 13:59:51.944158 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4273 13:59:51.950405 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4274 13:59:51.950511 == TX Byte 1 ==
4275 13:59:51.953583 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4276 13:59:51.960466 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4277 13:59:51.960575
4278 13:59:51.960670 [DATLAT]
4279 13:59:51.960759 Freq=600, CH0 RK1
4280 13:59:51.960857
4281 13:59:51.964159 DATLAT Default: 0x9
4282 13:59:51.964258 0, 0xFFFF, sum = 0
4283 13:59:51.967252 1, 0xFFFF, sum = 0
4284 13:59:51.967360 2, 0xFFFF, sum = 0
4285 13:59:51.971024 3, 0xFFFF, sum = 0
4286 13:59:51.971137 4, 0xFFFF, sum = 0
4287 13:59:51.973733 5, 0xFFFF, sum = 0
4288 13:59:51.977187 6, 0xFFFF, sum = 0
4289 13:59:51.977291 7, 0xFFFF, sum = 0
4290 13:59:51.977394 8, 0x0, sum = 1
4291 13:59:51.980488 9, 0x0, sum = 2
4292 13:59:51.980596 10, 0x0, sum = 3
4293 13:59:51.983629 11, 0x0, sum = 4
4294 13:59:51.983739 best_step = 9
4295 13:59:51.983831
4296 13:59:51.983919 ==
4297 13:59:51.986908 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 13:59:51.993626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 13:59:51.993740 ==
4300 13:59:51.993838 RX Vref Scan: 0
4301 13:59:51.993928
4302 13:59:51.997103 RX Vref 0 -> 0, step: 1
4303 13:59:51.997206
4304 13:59:52.000387 RX Delay -163 -> 252, step: 8
4305 13:59:52.003940 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4306 13:59:52.007018 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4307 13:59:52.013707 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4308 13:59:52.016859 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4309 13:59:52.020280 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4310 13:59:52.023471 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4311 13:59:52.026806 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4312 13:59:52.033409 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4313 13:59:52.037008 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4314 13:59:52.040325 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4315 13:59:52.043576 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4316 13:59:52.046875 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4317 13:59:52.053881 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4318 13:59:52.057123 iDelay=205, Bit 13, Center 52 (-83 ~ 188) 272
4319 13:59:52.060308 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4320 13:59:52.063660 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4321 13:59:52.063761 ==
4322 13:59:52.067045 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 13:59:52.073223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 13:59:52.073327 ==
4325 13:59:52.073430 DQS Delay:
4326 13:59:52.076708 DQS0 = 0, DQS1 = 0
4327 13:59:52.076808 DQM Delay:
4328 13:59:52.080243 DQM0 = 53, DQM1 = 47
4329 13:59:52.080344 DQ Delay:
4330 13:59:52.083417 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4331 13:59:52.086898 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =64
4332 13:59:52.089855 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4333 13:59:52.093226 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4334 13:59:52.093326
4335 13:59:52.093416
4336 13:59:52.100382 [DQSOSCAuto] RK1, (LSB)MR18= 0x6525, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4337 13:59:52.103454 CH0 RK1: MR19=808, MR18=6525
4338 13:59:52.110142 CH0_RK1: MR19=0x808, MR18=0x6525, DQSOSC=390, MR23=63, INC=172, DEC=114
4339 13:59:52.113293 [RxdqsGatingPostProcess] freq 600
4340 13:59:52.116764 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4341 13:59:52.120006 Pre-setting of DQS Precalculation
4342 13:59:52.126814 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4343 13:59:52.126920 ==
4344 13:59:52.130132 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 13:59:52.133479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 13:59:52.133580 ==
4347 13:59:52.140200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4348 13:59:52.146844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4349 13:59:52.149884 [CA 0] Center 36 (5~67) winsize 63
4350 13:59:52.152984 [CA 1] Center 36 (5~67) winsize 63
4351 13:59:52.156555 [CA 2] Center 34 (4~65) winsize 62
4352 13:59:52.160466 [CA 3] Center 34 (4~65) winsize 62
4353 13:59:52.163424 [CA 4] Center 34 (4~65) winsize 62
4354 13:59:52.166597 [CA 5] Center 33 (3~64) winsize 62
4355 13:59:52.166697
4356 13:59:52.169789 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4357 13:59:52.169920
4358 13:59:52.173399 [CATrainingPosCal] consider 1 rank data
4359 13:59:52.176380 u2DelayCellTimex100 = 270/100 ps
4360 13:59:52.179719 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4361 13:59:52.183022 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4362 13:59:52.186466 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4363 13:59:52.189693 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4364 13:59:52.193275 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4365 13:59:52.196244 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4366 13:59:52.196350
4367 13:59:52.199534 CA PerBit enable=1, Macro0, CA PI delay=33
4368 13:59:52.203162
4369 13:59:52.203263 [CBTSetCACLKResult] CA Dly = 33
4370 13:59:52.206386 CS Dly: 6 (0~37)
4371 13:59:52.206483 ==
4372 13:59:52.209861 Dram Type= 6, Freq= 0, CH_1, rank 1
4373 13:59:52.212807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 13:59:52.212914 ==
4375 13:59:52.219439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 13:59:52.226550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4377 13:59:52.230063 [CA 0] Center 36 (5~67) winsize 63
4378 13:59:52.232973 [CA 1] Center 36 (5~67) winsize 63
4379 13:59:52.236189 [CA 2] Center 34 (4~65) winsize 62
4380 13:59:52.240165 [CA 3] Center 34 (4~65) winsize 62
4381 13:59:52.243104 [CA 4] Center 34 (4~65) winsize 62
4382 13:59:52.246645 [CA 5] Center 34 (3~65) winsize 63
4383 13:59:52.246748
4384 13:59:52.249786 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4385 13:59:52.249894
4386 13:59:52.253169 [CATrainingPosCal] consider 2 rank data
4387 13:59:52.256430 u2DelayCellTimex100 = 270/100 ps
4388 13:59:52.259761 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4389 13:59:52.262770 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4390 13:59:52.266121 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 13:59:52.269415 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4392 13:59:52.272793 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4393 13:59:52.276139 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4394 13:59:52.276241
4395 13:59:52.282769 CA PerBit enable=1, Macro0, CA PI delay=33
4396 13:59:52.282872
4397 13:59:52.282968 [CBTSetCACLKResult] CA Dly = 33
4398 13:59:52.286217 CS Dly: 6 (0~38)
4399 13:59:52.286318
4400 13:59:52.289565 ----->DramcWriteLeveling(PI) begin...
4401 13:59:52.289671 ==
4402 13:59:52.292967 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 13:59:52.296484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 13:59:52.296586 ==
4405 13:59:52.299543 Write leveling (Byte 0): 29 => 29
4406 13:59:52.302787 Write leveling (Byte 1): 30 => 30
4407 13:59:52.306246 DramcWriteLeveling(PI) end<-----
4408 13:59:52.306347
4409 13:59:52.306440 ==
4410 13:59:52.309124 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 13:59:52.315813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 13:59:52.315916 ==
4413 13:59:52.316011 [Gating] SW mode calibration
4414 13:59:52.325970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4415 13:59:52.329216 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4416 13:59:52.332405 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 13:59:52.339117 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 13:59:52.342587 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 13:59:52.345942 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
4420 13:59:52.352641 0 9 16 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
4421 13:59:52.356047 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 13:59:52.359320 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 13:59:52.365597 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 13:59:52.369010 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 13:59:52.372355 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 13:59:52.379228 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4427 13:59:52.382616 0 10 12 | B1->B0 | 3838 3a3a | 0 0 | (0 0) (0 0)
4428 13:59:52.386091 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 13:59:52.392392 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 13:59:52.395904 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 13:59:52.399269 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 13:59:52.405586 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 13:59:52.408840 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 13:59:52.412193 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 13:59:52.419027 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4436 13:59:52.422170 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 13:59:52.425633 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 13:59:52.428918 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 13:59:52.435473 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 13:59:52.438898 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 13:59:52.442334 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 13:59:52.448948 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 13:59:52.452414 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 13:59:52.455525 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 13:59:52.462304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 13:59:52.465327 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 13:59:52.469047 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 13:59:52.475327 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 13:59:52.478982 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 13:59:52.482389 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 13:59:52.489262 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4452 13:59:52.492644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 13:59:52.495872 Total UI for P1: 0, mck2ui 16
4454 13:59:52.498893 best dqsien dly found for B0: ( 0, 13, 12)
4455 13:59:52.502220 Total UI for P1: 0, mck2ui 16
4456 13:59:52.505570 best dqsien dly found for B1: ( 0, 13, 12)
4457 13:59:52.508891 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4458 13:59:52.512208 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4459 13:59:52.512316
4460 13:59:52.515635 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4461 13:59:52.518805 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4462 13:59:52.522369 [Gating] SW calibration Done
4463 13:59:52.522471 ==
4464 13:59:52.525740 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 13:59:52.529049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 13:59:52.532316 ==
4467 13:59:52.532417 RX Vref Scan: 0
4468 13:59:52.532520
4469 13:59:52.535748 RX Vref 0 -> 0, step: 1
4470 13:59:52.535853
4471 13:59:52.538772 RX Delay -230 -> 252, step: 16
4472 13:59:52.542283 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4473 13:59:52.545717 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4474 13:59:52.548951 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4475 13:59:52.552260 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4476 13:59:52.558950 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4477 13:59:52.561853 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4478 13:59:52.565139 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4479 13:59:52.568929 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4480 13:59:52.575443 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4481 13:59:52.578462 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4482 13:59:52.581865 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4483 13:59:52.585302 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4484 13:59:52.588562 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4485 13:59:52.595519 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4486 13:59:52.598902 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4487 13:59:52.601664 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4488 13:59:52.601765 ==
4489 13:59:52.605169 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 13:59:52.608607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 13:59:52.612060 ==
4492 13:59:52.612158 DQS Delay:
4493 13:59:52.612247 DQS0 = 0, DQS1 = 0
4494 13:59:52.614995 DQM Delay:
4495 13:59:52.615091 DQM0 = 52, DQM1 = 50
4496 13:59:52.618381 DQ Delay:
4497 13:59:52.618479 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =41
4498 13:59:52.621907 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4499 13:59:52.624984 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4500 13:59:52.628484 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4501 13:59:52.628587
4502 13:59:52.631856
4503 13:59:52.631952 ==
4504 13:59:52.635392 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 13:59:52.638882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 13:59:52.638987 ==
4507 13:59:52.639081
4508 13:59:52.639173
4509 13:59:52.641865 TX Vref Scan disable
4510 13:59:52.641965 == TX Byte 0 ==
4511 13:59:52.649045 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4512 13:59:52.651766 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4513 13:59:52.651871 == TX Byte 1 ==
4514 13:59:52.658846 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4515 13:59:52.661662 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4516 13:59:52.661759 ==
4517 13:59:52.664908 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 13:59:52.668376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 13:59:52.668480 ==
4520 13:59:52.668571
4521 13:59:52.668660
4522 13:59:52.672050 TX Vref Scan disable
4523 13:59:52.675124 == TX Byte 0 ==
4524 13:59:52.678307 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4525 13:59:52.681960 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4526 13:59:52.685033 == TX Byte 1 ==
4527 13:59:52.688269 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4528 13:59:52.691890 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4529 13:59:52.691996
4530 13:59:52.695327 [DATLAT]
4531 13:59:52.695435 Freq=600, CH1 RK0
4532 13:59:52.695534
4533 13:59:52.698343 DATLAT Default: 0x9
4534 13:59:52.698441 0, 0xFFFF, sum = 0
4535 13:59:52.701913 1, 0xFFFF, sum = 0
4536 13:59:52.702017 2, 0xFFFF, sum = 0
4537 13:59:52.705066 3, 0xFFFF, sum = 0
4538 13:59:52.705171 4, 0xFFFF, sum = 0
4539 13:59:52.708552 5, 0xFFFF, sum = 0
4540 13:59:52.708655 6, 0xFFFF, sum = 0
4541 13:59:52.711720 7, 0xFFFF, sum = 0
4542 13:59:52.711803 8, 0x0, sum = 1
4543 13:59:52.714808 9, 0x0, sum = 2
4544 13:59:52.714909 10, 0x0, sum = 3
4545 13:59:52.718272 11, 0x0, sum = 4
4546 13:59:52.718379 best_step = 9
4547 13:59:52.718470
4548 13:59:52.718560 ==
4549 13:59:52.721693 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 13:59:52.725303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 13:59:52.728307 ==
4552 13:59:52.728408 RX Vref Scan: 1
4553 13:59:52.728499
4554 13:59:52.731264 RX Vref 0 -> 0, step: 1
4555 13:59:52.731363
4556 13:59:52.734880 RX Delay -163 -> 252, step: 8
4557 13:59:52.734982
4558 13:59:52.737773 Set Vref, RX VrefLevel [Byte0]: 54
4559 13:59:52.741684 [Byte1]: 51
4560 13:59:52.741790
4561 13:59:52.744578 Final RX Vref Byte 0 = 54 to rank0
4562 13:59:52.747859 Final RX Vref Byte 1 = 51 to rank0
4563 13:59:52.750951 Final RX Vref Byte 0 = 54 to rank1
4564 13:59:52.754371 Final RX Vref Byte 1 = 51 to rank1==
4565 13:59:52.757760 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 13:59:52.761359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 13:59:52.761459 ==
4568 13:59:52.764751 DQS Delay:
4569 13:59:52.764854 DQS0 = 0, DQS1 = 0
4570 13:59:52.764944 DQM Delay:
4571 13:59:52.767874 DQM0 = 48, DQM1 = 45
4572 13:59:52.767973 DQ Delay:
4573 13:59:52.771508 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4574 13:59:52.774478 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4575 13:59:52.777822 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4576 13:59:52.780937 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4577 13:59:52.781037
4578 13:59:52.781127
4579 13:59:52.790918 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4580 13:59:52.791026 CH1 RK0: MR19=808, MR18=4C71
4581 13:59:52.797611 CH1_RK0: MR19=0x808, MR18=0x4C71, DQSOSC=388, MR23=63, INC=174, DEC=116
4582 13:59:52.797716
4583 13:59:52.801055 ----->DramcWriteLeveling(PI) begin...
4584 13:59:52.801161 ==
4585 13:59:52.804181 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 13:59:52.811446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 13:59:52.811552 ==
4588 13:59:52.814119 Write leveling (Byte 0): 28 => 28
4589 13:59:52.817558 Write leveling (Byte 1): 31 => 31
4590 13:59:52.820924 DramcWriteLeveling(PI) end<-----
4591 13:59:52.821035
4592 13:59:52.821129 ==
4593 13:59:52.824335 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 13:59:52.827588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 13:59:52.827736 ==
4596 13:59:52.831179 [Gating] SW mode calibration
4597 13:59:52.837903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4598 13:59:52.840908 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4599 13:59:52.847326 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 13:59:52.850790 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 13:59:52.854243 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 13:59:52.860465 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4603 13:59:52.864210 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 13:59:52.867453 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 13:59:52.874450 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 13:59:52.877239 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 13:59:52.880722 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 13:59:52.887157 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 13:59:52.890884 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 13:59:52.893870 0 10 12 | B1->B0 | 3a3a 3838 | 0 0 | (0 0) (1 1)
4611 13:59:52.900853 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 13:59:52.903994 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 13:59:52.907780 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 13:59:52.914421 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 13:59:52.917429 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 13:59:52.921011 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 13:59:52.927171 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 13:59:52.930579 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4619 13:59:52.933907 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 13:59:52.937372 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 13:59:52.944103 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 13:59:52.947444 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 13:59:52.950805 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 13:59:52.957534 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 13:59:52.961226 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 13:59:52.963921 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 13:59:52.970677 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 13:59:52.974141 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 13:59:52.977826 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 13:59:52.984355 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 13:59:52.987576 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 13:59:52.991212 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 13:59:52.997476 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 13:59:53.000596 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4635 13:59:53.004010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 13:59:53.007501 Total UI for P1: 0, mck2ui 16
4637 13:59:53.010469 best dqsien dly found for B0: ( 0, 13, 12)
4638 13:59:53.014826 Total UI for P1: 0, mck2ui 16
4639 13:59:53.017342 best dqsien dly found for B1: ( 0, 13, 12)
4640 13:59:53.020609 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4641 13:59:53.024133 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4642 13:59:53.024214
4643 13:59:53.027285 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4644 13:59:53.034240 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4645 13:59:53.034348 [Gating] SW calibration Done
4646 13:59:53.037574 ==
4647 13:59:53.037682 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 13:59:53.043835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 13:59:53.043940 ==
4650 13:59:53.044044 RX Vref Scan: 0
4651 13:59:53.044135
4652 13:59:53.047101 RX Vref 0 -> 0, step: 1
4653 13:59:53.047201
4654 13:59:53.050494 RX Delay -230 -> 252, step: 16
4655 13:59:53.053764 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4656 13:59:53.057386 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4657 13:59:53.063834 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4658 13:59:53.067428 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4659 13:59:53.070789 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4660 13:59:53.073961 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4661 13:59:53.077143 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4662 13:59:53.083956 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4663 13:59:53.087320 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4664 13:59:53.090517 iDelay=218, Bit 9, Center 49 (-102 ~ 201) 304
4665 13:59:53.094097 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4666 13:59:53.100772 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4667 13:59:53.103914 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4668 13:59:53.107276 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4669 13:59:53.110466 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4670 13:59:53.113919 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4671 13:59:53.117329 ==
4672 13:59:53.120817 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 13:59:53.123721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 13:59:53.123827 ==
4675 13:59:53.123918 DQS Delay:
4676 13:59:53.127123 DQS0 = 0, DQS1 = 0
4677 13:59:53.127204 DQM Delay:
4678 13:59:53.130963 DQM0 = 51, DQM1 = 50
4679 13:59:53.131043 DQ Delay:
4680 13:59:53.133994 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4681 13:59:53.136829 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4682 13:59:53.140482 DQ8 =33, DQ9 =49, DQ10 =49, DQ11 =49
4683 13:59:53.143814 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4684 13:59:53.143919
4685 13:59:53.144015
4686 13:59:53.144104 ==
4687 13:59:53.146700 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 13:59:53.150510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 13:59:53.150616 ==
4690 13:59:53.150708
4691 13:59:53.150801
4692 13:59:53.153339 TX Vref Scan disable
4693 13:59:53.156796 == TX Byte 0 ==
4694 13:59:53.160305 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4695 13:59:53.163269 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4696 13:59:53.166523 == TX Byte 1 ==
4697 13:59:53.169828 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4698 13:59:53.173306 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4699 13:59:53.173415 ==
4700 13:59:53.176453 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 13:59:53.182904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 13:59:53.183005 ==
4703 13:59:53.183107
4704 13:59:53.183196
4705 13:59:53.183289 TX Vref Scan disable
4706 13:59:53.187488 == TX Byte 0 ==
4707 13:59:53.191081 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4708 13:59:53.198103 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4709 13:59:53.198203 == TX Byte 1 ==
4710 13:59:53.200856 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4711 13:59:53.204190 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4712 13:59:53.207672
4713 13:59:53.207769 [DATLAT]
4714 13:59:53.207862 Freq=600, CH1 RK1
4715 13:59:53.207950
4716 13:59:53.211185 DATLAT Default: 0x9
4717 13:59:53.211279 0, 0xFFFF, sum = 0
4718 13:59:53.214749 1, 0xFFFF, sum = 0
4719 13:59:53.214847 2, 0xFFFF, sum = 0
4720 13:59:53.218158 3, 0xFFFF, sum = 0
4721 13:59:53.218255 4, 0xFFFF, sum = 0
4722 13:59:53.221139 5, 0xFFFF, sum = 0
4723 13:59:53.221243 6, 0xFFFF, sum = 0
4724 13:59:53.224535 7, 0xFFFF, sum = 0
4725 13:59:53.224635 8, 0x0, sum = 1
4726 13:59:53.227940 9, 0x0, sum = 2
4727 13:59:53.228041 10, 0x0, sum = 3
4728 13:59:53.231227 11, 0x0, sum = 4
4729 13:59:53.231339 best_step = 9
4730 13:59:53.231446
4731 13:59:53.231539 ==
4732 13:59:53.234383 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 13:59:53.241023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 13:59:53.241133 ==
4735 13:59:53.241226 RX Vref Scan: 0
4736 13:59:53.241320
4737 13:59:53.244414 RX Vref 0 -> 0, step: 1
4738 13:59:53.244516
4739 13:59:53.247670 RX Delay -163 -> 252, step: 8
4740 13:59:53.251093 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4741 13:59:53.254212 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4742 13:59:53.261121 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4743 13:59:53.264446 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4744 13:59:53.267961 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4745 13:59:53.270959 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4746 13:59:53.274136 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4747 13:59:53.281132 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4748 13:59:53.284662 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4749 13:59:53.287847 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4750 13:59:53.291112 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4751 13:59:53.297651 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4752 13:59:53.301254 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4753 13:59:53.303941 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4754 13:59:53.307411 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4755 13:59:53.310950 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4756 13:59:53.314606 ==
4757 13:59:53.317337 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 13:59:53.320612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 13:59:53.320713 ==
4760 13:59:53.320807 DQS Delay:
4761 13:59:53.324254 DQS0 = 0, DQS1 = 0
4762 13:59:53.324356 DQM Delay:
4763 13:59:53.327304 DQM0 = 48, DQM1 = 45
4764 13:59:53.327404 DQ Delay:
4765 13:59:53.330710 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4766 13:59:53.334445 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4767 13:59:53.337560 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4768 13:59:53.340761 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4769 13:59:53.340866
4770 13:59:53.340959
4771 13:59:53.348133 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4772 13:59:53.350955 CH1 RK1: MR19=808, MR18=6A21
4773 13:59:53.357707 CH1_RK1: MR19=0x808, MR18=0x6A21, DQSOSC=389, MR23=63, INC=173, DEC=115
4774 13:59:53.360747 [RxdqsGatingPostProcess] freq 600
4775 13:59:53.364361 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4776 13:59:53.367435 Pre-setting of DQS Precalculation
4777 13:59:53.373948 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4778 13:59:53.380978 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4779 13:59:53.387334 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4780 13:59:53.387440
4781 13:59:53.387535
4782 13:59:53.390456 [Calibration Summary] 1200 Mbps
4783 13:59:53.390559 CH 0, Rank 0
4784 13:59:53.393770 SW Impedance : PASS
4785 13:59:53.397539 DUTY Scan : NO K
4786 13:59:53.397638 ZQ Calibration : PASS
4787 13:59:53.400932 Jitter Meter : NO K
4788 13:59:53.404402 CBT Training : PASS
4789 13:59:53.404505 Write leveling : PASS
4790 13:59:53.407307 RX DQS gating : PASS
4791 13:59:53.410556 RX DQ/DQS(RDDQC) : PASS
4792 13:59:53.410654 TX DQ/DQS : PASS
4793 13:59:53.413845 RX DATLAT : PASS
4794 13:59:53.417764 RX DQ/DQS(Engine): PASS
4795 13:59:53.417862 TX OE : NO K
4796 13:59:53.420863 All Pass.
4797 13:59:53.420963
4798 13:59:53.421054 CH 0, Rank 1
4799 13:59:53.424789 SW Impedance : PASS
4800 13:59:53.424891 DUTY Scan : NO K
4801 13:59:53.426977 ZQ Calibration : PASS
4802 13:59:53.430421 Jitter Meter : NO K
4803 13:59:53.430520 CBT Training : PASS
4804 13:59:53.433631 Write leveling : PASS
4805 13:59:53.433729 RX DQS gating : PASS
4806 13:59:53.437188 RX DQ/DQS(RDDQC) : PASS
4807 13:59:53.440665 TX DQ/DQS : PASS
4808 13:59:53.440772 RX DATLAT : PASS
4809 13:59:53.443973 RX DQ/DQS(Engine): PASS
4810 13:59:53.447164 TX OE : NO K
4811 13:59:53.447263 All Pass.
4812 13:59:53.447364
4813 13:59:53.447452 CH 1, Rank 0
4814 13:59:53.450251 SW Impedance : PASS
4815 13:59:53.453883 DUTY Scan : NO K
4816 13:59:53.453989 ZQ Calibration : PASS
4817 13:59:53.457060 Jitter Meter : NO K
4818 13:59:53.460638 CBT Training : PASS
4819 13:59:53.460738 Write leveling : PASS
4820 13:59:53.463773 RX DQS gating : PASS
4821 13:59:53.467267 RX DQ/DQS(RDDQC) : PASS
4822 13:59:53.467365 TX DQ/DQS : PASS
4823 13:59:53.470145 RX DATLAT : PASS
4824 13:59:53.473477 RX DQ/DQS(Engine): PASS
4825 13:59:53.473589 TX OE : NO K
4826 13:59:53.477201 All Pass.
4827 13:59:53.477299
4828 13:59:53.477390 CH 1, Rank 1
4829 13:59:53.480337 SW Impedance : PASS
4830 13:59:53.480433 DUTY Scan : NO K
4831 13:59:53.483841 ZQ Calibration : PASS
4832 13:59:53.486793 Jitter Meter : NO K
4833 13:59:53.486893 CBT Training : PASS
4834 13:59:53.490321 Write leveling : PASS
4835 13:59:53.490427 RX DQS gating : PASS
4836 13:59:53.493542 RX DQ/DQS(RDDQC) : PASS
4837 13:59:53.496979 TX DQ/DQS : PASS
4838 13:59:53.497078 RX DATLAT : PASS
4839 13:59:53.500506 RX DQ/DQS(Engine): PASS
4840 13:59:53.504121 TX OE : NO K
4841 13:59:53.504222 All Pass.
4842 13:59:53.504315
4843 13:59:53.506963 DramC Write-DBI off
4844 13:59:53.507058 PER_BANK_REFRESH: Hybrid Mode
4845 13:59:53.510215 TX_TRACKING: ON
4846 13:59:53.516636 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4847 13:59:53.523575 [FAST_K] Save calibration result to emmc
4848 13:59:53.527129 dramc_set_vcore_voltage set vcore to 662500
4849 13:59:53.527235 Read voltage for 933, 3
4850 13:59:53.530362 Vio18 = 0
4851 13:59:53.530460 Vcore = 662500
4852 13:59:53.530550 Vdram = 0
4853 13:59:53.533646 Vddq = 0
4854 13:59:53.533742 Vmddr = 0
4855 13:59:53.536950 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4856 13:59:53.543304 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4857 13:59:53.546692 MEM_TYPE=3, freq_sel=17
4858 13:59:53.549960 sv_algorithm_assistance_LP4_1600
4859 13:59:53.553428 ============ PULL DRAM RESETB DOWN ============
4860 13:59:53.556685 ========== PULL DRAM RESETB DOWN end =========
4861 13:59:53.563493 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 13:59:53.566423 ===================================
4863 13:59:53.566531 LPDDR4 DRAM CONFIGURATION
4864 13:59:53.569695 ===================================
4865 13:59:53.573147 EX_ROW_EN[0] = 0x0
4866 13:59:53.573227 EX_ROW_EN[1] = 0x0
4867 13:59:53.576418 LP4Y_EN = 0x0
4868 13:59:53.576499 WORK_FSP = 0x0
4869 13:59:53.580065 WL = 0x3
4870 13:59:53.583234 RL = 0x3
4871 13:59:53.583341 BL = 0x2
4872 13:59:53.586886 RPST = 0x0
4873 13:59:53.586966 RD_PRE = 0x0
4874 13:59:53.589615 WR_PRE = 0x1
4875 13:59:53.589695 WR_PST = 0x0
4876 13:59:53.592858 DBI_WR = 0x0
4877 13:59:53.592938 DBI_RD = 0x0
4878 13:59:53.596531 OTF = 0x1
4879 13:59:53.600137 ===================================
4880 13:59:53.603174 ===================================
4881 13:59:53.603254 ANA top config
4882 13:59:53.606403 ===================================
4883 13:59:53.609764 DLL_ASYNC_EN = 0
4884 13:59:53.613298 ALL_SLAVE_EN = 1
4885 13:59:53.613402 NEW_RANK_MODE = 1
4886 13:59:53.616559 DLL_IDLE_MODE = 1
4887 13:59:53.619805 LP45_APHY_COMB_EN = 1
4888 13:59:53.622837 TX_ODT_DIS = 1
4889 13:59:53.622942 NEW_8X_MODE = 1
4890 13:59:53.626219 ===================================
4891 13:59:53.629615 ===================================
4892 13:59:53.632986 data_rate = 1866
4893 13:59:53.636357 CKR = 1
4894 13:59:53.639849 DQ_P2S_RATIO = 8
4895 13:59:53.642960 ===================================
4896 13:59:53.646365 CA_P2S_RATIO = 8
4897 13:59:53.649805 DQ_CA_OPEN = 0
4898 13:59:53.649911 DQ_SEMI_OPEN = 0
4899 13:59:53.652900 CA_SEMI_OPEN = 0
4900 13:59:53.656162 CA_FULL_RATE = 0
4901 13:59:53.659284 DQ_CKDIV4_EN = 1
4902 13:59:53.663120 CA_CKDIV4_EN = 1
4903 13:59:53.666462 CA_PREDIV_EN = 0
4904 13:59:53.666561 PH8_DLY = 0
4905 13:59:53.669647 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4906 13:59:53.673071 DQ_AAMCK_DIV = 4
4907 13:59:53.675902 CA_AAMCK_DIV = 4
4908 13:59:53.679628 CA_ADMCK_DIV = 4
4909 13:59:53.683173 DQ_TRACK_CA_EN = 0
4910 13:59:53.683272 CA_PICK = 933
4911 13:59:53.686563 CA_MCKIO = 933
4912 13:59:53.689719 MCKIO_SEMI = 0
4913 13:59:53.693053 PLL_FREQ = 3732
4914 13:59:53.696436 DQ_UI_PI_RATIO = 32
4915 13:59:53.699457 CA_UI_PI_RATIO = 0
4916 13:59:53.702697 ===================================
4917 13:59:53.706125 ===================================
4918 13:59:53.709455 memory_type:LPDDR4
4919 13:59:53.709536 GP_NUM : 10
4920 13:59:53.712953 SRAM_EN : 1
4921 13:59:53.713051 MD32_EN : 0
4922 13:59:53.716322 ===================================
4923 13:59:53.719413 [ANA_INIT] >>>>>>>>>>>>>>
4924 13:59:53.723156 <<<<<< [CONFIGURE PHASE]: ANA_TX
4925 13:59:53.726646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4926 13:59:53.729448 ===================================
4927 13:59:53.732787 data_rate = 1866,PCW = 0X8f00
4928 13:59:53.736220 ===================================
4929 13:59:53.739170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4930 13:59:53.742694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 13:59:53.749191 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 13:59:53.752624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4933 13:59:53.756002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4934 13:59:53.762854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4935 13:59:53.762966 [ANA_INIT] flow start
4936 13:59:53.766060 [ANA_INIT] PLL >>>>>>>>
4937 13:59:53.766163 [ANA_INIT] PLL <<<<<<<<
4938 13:59:53.769588 [ANA_INIT] MIDPI >>>>>>>>
4939 13:59:53.772623 [ANA_INIT] MIDPI <<<<<<<<
4940 13:59:53.776311 [ANA_INIT] DLL >>>>>>>>
4941 13:59:53.776420 [ANA_INIT] flow end
4942 13:59:53.779343 ============ LP4 DIFF to SE enter ============
4943 13:59:53.786042 ============ LP4 DIFF to SE exit ============
4944 13:59:53.786151 [ANA_INIT] <<<<<<<<<<<<<
4945 13:59:53.789477 [Flow] Enable top DCM control >>>>>
4946 13:59:53.792568 [Flow] Enable top DCM control <<<<<
4947 13:59:53.795767 Enable DLL master slave shuffle
4948 13:59:53.802604 ==============================================================
4949 13:59:53.802717 Gating Mode config
4950 13:59:53.809152 ==============================================================
4951 13:59:53.812898 Config description:
4952 13:59:53.822557 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4953 13:59:53.829009 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4954 13:59:53.832771 SELPH_MODE 0: By rank 1: By Phase
4955 13:59:53.839313 ==============================================================
4956 13:59:53.842747 GAT_TRACK_EN = 1
4957 13:59:53.842851 RX_GATING_MODE = 2
4958 13:59:53.846037 RX_GATING_TRACK_MODE = 2
4959 13:59:53.849485 SELPH_MODE = 1
4960 13:59:53.852091 PICG_EARLY_EN = 1
4961 13:59:53.855524 VALID_LAT_VALUE = 1
4962 13:59:53.862476 ==============================================================
4963 13:59:53.865822 Enter into Gating configuration >>>>
4964 13:59:53.868973 Exit from Gating configuration <<<<
4965 13:59:53.872385 Enter into DVFS_PRE_config >>>>>
4966 13:59:53.882659 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4967 13:59:53.885856 Exit from DVFS_PRE_config <<<<<
4968 13:59:53.889311 Enter into PICG configuration >>>>
4969 13:59:53.892201 Exit from PICG configuration <<<<
4970 13:59:53.895662 [RX_INPUT] configuration >>>>>
4971 13:59:53.899222 [RX_INPUT] configuration <<<<<
4972 13:59:53.902449 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4973 13:59:53.908851 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4974 13:59:53.915368 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 13:59:53.919107 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 13:59:53.925727 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 13:59:53.932171 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 13:59:53.935256 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4979 13:59:53.938550 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4980 13:59:53.945667 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4981 13:59:53.948769 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4982 13:59:53.952273 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4983 13:59:53.959137 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 13:59:53.962278 ===================================
4985 13:59:53.962381 LPDDR4 DRAM CONFIGURATION
4986 13:59:53.965730 ===================================
4987 13:59:53.968979 EX_ROW_EN[0] = 0x0
4988 13:59:53.972415 EX_ROW_EN[1] = 0x0
4989 13:59:53.972520 LP4Y_EN = 0x0
4990 13:59:53.975577 WORK_FSP = 0x0
4991 13:59:53.975718 WL = 0x3
4992 13:59:53.979040 RL = 0x3
4993 13:59:53.979142 BL = 0x2
4994 13:59:53.982170 RPST = 0x0
4995 13:59:53.982271 RD_PRE = 0x0
4996 13:59:53.985318 WR_PRE = 0x1
4997 13:59:53.985422 WR_PST = 0x0
4998 13:59:53.988637 DBI_WR = 0x0
4999 13:59:53.988738 DBI_RD = 0x0
5000 13:59:53.992144 OTF = 0x1
5001 13:59:53.995166 ===================================
5002 13:59:53.998801 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5003 13:59:54.002075 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5004 13:59:54.008821 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 13:59:54.008927 ===================================
5006 13:59:54.011788 LPDDR4 DRAM CONFIGURATION
5007 13:59:54.015519 ===================================
5008 13:59:54.018622 EX_ROW_EN[0] = 0x10
5009 13:59:54.018723 EX_ROW_EN[1] = 0x0
5010 13:59:54.021883 LP4Y_EN = 0x0
5011 13:59:54.021984 WORK_FSP = 0x0
5012 13:59:54.025624 WL = 0x3
5013 13:59:54.025727 RL = 0x3
5014 13:59:54.028516 BL = 0x2
5015 13:59:54.031900 RPST = 0x0
5016 13:59:54.031991 RD_PRE = 0x0
5017 13:59:54.035546 WR_PRE = 0x1
5018 13:59:54.035686 WR_PST = 0x0
5019 13:59:54.038503 DBI_WR = 0x0
5020 13:59:54.038607 DBI_RD = 0x0
5021 13:59:54.042115 OTF = 0x1
5022 13:59:54.045219 ===================================
5023 13:59:54.048880 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5024 13:59:54.054269 nWR fixed to 30
5025 13:59:54.057710 [ModeRegInit_LP4] CH0 RK0
5026 13:59:54.057814 [ModeRegInit_LP4] CH0 RK1
5027 13:59:54.060890 [ModeRegInit_LP4] CH1 RK0
5028 13:59:54.063772 [ModeRegInit_LP4] CH1 RK1
5029 13:59:54.063882 match AC timing 9
5030 13:59:54.070754 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5031 13:59:54.073886 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5032 13:59:54.077417 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5033 13:59:54.083954 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5034 13:59:54.086971 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5035 13:59:54.087075 ==
5036 13:59:54.090451 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 13:59:54.093942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5038 13:59:54.094025 ==
5039 13:59:54.100333 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5040 13:59:54.107065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5041 13:59:54.110436 [CA 0] Center 37 (6~68) winsize 63
5042 13:59:54.113926 [CA 1] Center 37 (7~68) winsize 62
5043 13:59:54.117122 [CA 2] Center 34 (4~65) winsize 62
5044 13:59:54.120455 [CA 3] Center 33 (3~64) winsize 62
5045 13:59:54.123745 [CA 4] Center 33 (3~64) winsize 62
5046 13:59:54.126528 [CA 5] Center 32 (2~62) winsize 61
5047 13:59:54.126610
5048 13:59:54.129889 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5049 13:59:54.129965
5050 13:59:54.133319 [CATrainingPosCal] consider 1 rank data
5051 13:59:54.136468 u2DelayCellTimex100 = 270/100 ps
5052 13:59:54.140259 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5053 13:59:54.143389 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5054 13:59:54.146487 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5055 13:59:54.150049 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5056 13:59:54.156866 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5057 13:59:54.159897 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5058 13:59:54.159974
5059 13:59:54.163277 CA PerBit enable=1, Macro0, CA PI delay=32
5060 13:59:54.163351
5061 13:59:54.166381 [CBTSetCACLKResult] CA Dly = 32
5062 13:59:54.166456 CS Dly: 5 (0~36)
5063 13:59:54.166577 ==
5064 13:59:54.169607 Dram Type= 6, Freq= 0, CH_0, rank 1
5065 13:59:54.173586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 13:59:54.176298 ==
5067 13:59:54.179693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 13:59:54.186526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5069 13:59:54.189701 [CA 0] Center 37 (7~68) winsize 62
5070 13:59:54.192969 [CA 1] Center 37 (6~68) winsize 63
5071 13:59:54.196412 [CA 2] Center 34 (4~65) winsize 62
5072 13:59:54.200015 [CA 3] Center 34 (4~65) winsize 62
5073 13:59:54.203175 [CA 4] Center 33 (3~63) winsize 61
5074 13:59:54.206130 [CA 5] Center 32 (2~62) winsize 61
5075 13:59:54.206213
5076 13:59:54.209785 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5077 13:59:54.209861
5078 13:59:54.213113 [CATrainingPosCal] consider 2 rank data
5079 13:59:54.216326 u2DelayCellTimex100 = 270/100 ps
5080 13:59:54.219765 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5081 13:59:54.223107 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5082 13:59:54.226234 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5083 13:59:54.232953 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5084 13:59:54.236399 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5085 13:59:54.240241 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5086 13:59:54.240331
5087 13:59:54.243325 CA PerBit enable=1, Macro0, CA PI delay=32
5088 13:59:54.243399
5089 13:59:54.246082 [CBTSetCACLKResult] CA Dly = 32
5090 13:59:54.246157 CS Dly: 5 (0~37)
5091 13:59:54.246242
5092 13:59:54.249265 ----->DramcWriteLeveling(PI) begin...
5093 13:59:54.249360 ==
5094 13:59:54.253080 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 13:59:54.259209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 13:59:54.259291 ==
5097 13:59:54.262881 Write leveling (Byte 0): 32 => 32
5098 13:59:54.266535 Write leveling (Byte 1): 30 => 30
5099 13:59:54.266616 DramcWriteLeveling(PI) end<-----
5100 13:59:54.269512
5101 13:59:54.269592 ==
5102 13:59:54.273056 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 13:59:54.276364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 13:59:54.276451 ==
5105 13:59:54.279400 [Gating] SW mode calibration
5106 13:59:54.286105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5107 13:59:54.289343 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5108 13:59:54.296673 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
5109 13:59:54.299377 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 13:59:54.302797 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 13:59:54.309827 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 13:59:54.312468 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 13:59:54.315817 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 13:59:54.322431 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5115 13:59:54.325734 0 14 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
5116 13:59:54.329506 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5117 13:59:54.336281 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 13:59:54.339461 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 13:59:54.342400 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 13:59:54.349308 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 13:59:54.352718 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 13:59:54.356034 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5123 13:59:54.362411 0 15 28 | B1->B0 | 2424 3d3d | 0 1 | (0 0) (0 0)
5124 13:59:54.365783 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5125 13:59:54.369192 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 13:59:54.372603 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 13:59:54.379127 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 13:59:54.382591 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 13:59:54.385932 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 13:59:54.392344 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5131 13:59:54.395760 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5132 13:59:54.398937 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5133 13:59:54.405763 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 13:59:54.409163 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 13:59:54.412619 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 13:59:54.419156 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 13:59:54.422691 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 13:59:54.426174 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 13:59:54.432259 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 13:59:54.435829 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 13:59:54.439058 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 13:59:54.445600 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 13:59:54.449117 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 13:59:54.452493 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 13:59:54.458819 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 13:59:54.462603 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5147 13:59:54.465824 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5148 13:59:54.472774 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 13:59:54.472894 Total UI for P1: 0, mck2ui 16
5150 13:59:54.479008 best dqsien dly found for B0: ( 1, 2, 26)
5151 13:59:54.479109 Total UI for P1: 0, mck2ui 16
5152 13:59:54.482291 best dqsien dly found for B1: ( 1, 2, 30)
5153 13:59:54.488757 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5154 13:59:54.492466 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5155 13:59:54.492547
5156 13:59:54.495483 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5157 13:59:54.498876 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5158 13:59:54.502310 [Gating] SW calibration Done
5159 13:59:54.502391 ==
5160 13:59:54.506024 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 13:59:54.508626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 13:59:54.508708 ==
5163 13:59:54.511939 RX Vref Scan: 0
5164 13:59:54.512019
5165 13:59:54.512082 RX Vref 0 -> 0, step: 1
5166 13:59:54.512141
5167 13:59:54.515777 RX Delay -80 -> 252, step: 8
5168 13:59:54.519568 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5169 13:59:54.525751 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5170 13:59:54.529122 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5171 13:59:54.532307 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5172 13:59:54.535403 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5173 13:59:54.538954 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5174 13:59:54.542334 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5175 13:59:54.548861 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5176 13:59:54.551900 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5177 13:59:54.555525 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5178 13:59:54.558954 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5179 13:59:54.561977 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5180 13:59:54.565503 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5181 13:59:54.572012 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5182 13:59:54.575381 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5183 13:59:54.578837 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5184 13:59:54.578919 ==
5185 13:59:54.582104 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 13:59:54.585007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 13:59:54.588566 ==
5188 13:59:54.588642 DQS Delay:
5189 13:59:54.588723 DQS0 = 0, DQS1 = 0
5190 13:59:54.591840 DQM Delay:
5191 13:59:54.591940 DQM0 = 104, DQM1 = 95
5192 13:59:54.595173 DQ Delay:
5193 13:59:54.598461 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5194 13:59:54.602095 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5195 13:59:54.605349 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5196 13:59:54.608842 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5197 13:59:54.608914
5198 13:59:54.608973
5199 13:59:54.609029 ==
5200 13:59:54.611802 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 13:59:54.615157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 13:59:54.615226 ==
5203 13:59:54.615297
5204 13:59:54.615356
5205 13:59:54.617969 TX Vref Scan disable
5206 13:59:54.621922 == TX Byte 0 ==
5207 13:59:54.625187 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5208 13:59:54.628426 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5209 13:59:54.631962 == TX Byte 1 ==
5210 13:59:54.635133 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5211 13:59:54.638284 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5212 13:59:54.638381 ==
5213 13:59:54.641541 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 13:59:54.644908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 13:59:54.645010 ==
5216 13:59:54.648269
5217 13:59:54.648349
5218 13:59:54.648413 TX Vref Scan disable
5219 13:59:54.651912 == TX Byte 0 ==
5220 13:59:54.655376 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5221 13:59:54.658400 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5222 13:59:54.661741 == TX Byte 1 ==
5223 13:59:54.665085 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5224 13:59:54.671533 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5225 13:59:54.671688
5226 13:59:54.671782 [DATLAT]
5227 13:59:54.671880 Freq=933, CH0 RK0
5228 13:59:54.671977
5229 13:59:54.674753 DATLAT Default: 0xd
5230 13:59:54.674826 0, 0xFFFF, sum = 0
5231 13:59:54.677910 1, 0xFFFF, sum = 0
5232 13:59:54.681507 2, 0xFFFF, sum = 0
5233 13:59:54.681605 3, 0xFFFF, sum = 0
5234 13:59:54.684695 4, 0xFFFF, sum = 0
5235 13:59:54.684792 5, 0xFFFF, sum = 0
5236 13:59:54.687847 6, 0xFFFF, sum = 0
5237 13:59:54.687952 7, 0xFFFF, sum = 0
5238 13:59:54.691269 8, 0xFFFF, sum = 0
5239 13:59:54.691344 9, 0xFFFF, sum = 0
5240 13:59:54.694498 10, 0x0, sum = 1
5241 13:59:54.694572 11, 0x0, sum = 2
5242 13:59:54.698044 12, 0x0, sum = 3
5243 13:59:54.698121 13, 0x0, sum = 4
5244 13:59:54.698184 best_step = 11
5245 13:59:54.698243
5246 13:59:54.701158 ==
5247 13:59:54.704602 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 13:59:54.707935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 13:59:54.708016 ==
5250 13:59:54.708079 RX Vref Scan: 1
5251 13:59:54.708139
5252 13:59:54.711383 RX Vref 0 -> 0, step: 1
5253 13:59:54.711471
5254 13:59:54.714814 RX Delay -53 -> 252, step: 4
5255 13:59:54.714903
5256 13:59:54.718426 Set Vref, RX VrefLevel [Byte0]: 56
5257 13:59:54.721286 [Byte1]: 46
5258 13:59:54.721367
5259 13:59:54.724749 Final RX Vref Byte 0 = 56 to rank0
5260 13:59:54.727926 Final RX Vref Byte 1 = 46 to rank0
5261 13:59:54.731372 Final RX Vref Byte 0 = 56 to rank1
5262 13:59:54.735096 Final RX Vref Byte 1 = 46 to rank1==
5263 13:59:54.737720 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 13:59:54.741151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 13:59:54.741233 ==
5266 13:59:54.744456 DQS Delay:
5267 13:59:54.744527 DQS0 = 0, DQS1 = 0
5268 13:59:54.747927 DQM Delay:
5269 13:59:54.747996 DQM0 = 104, DQM1 = 94
5270 13:59:54.748054 DQ Delay:
5271 13:59:54.754770 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5272 13:59:54.758038 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5273 13:59:54.761246 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5274 13:59:54.764409 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =100
5275 13:59:54.764490
5276 13:59:54.764552
5277 13:59:54.771421 [DQSOSCAuto] RK0, (LSB)MR18= 0x352d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
5278 13:59:54.774530 CH0 RK0: MR19=505, MR18=352D
5279 13:59:54.781876 CH0_RK0: MR19=0x505, MR18=0x352D, DQSOSC=405, MR23=63, INC=66, DEC=44
5280 13:59:54.781957
5281 13:59:54.784945 ----->DramcWriteLeveling(PI) begin...
5282 13:59:54.785030 ==
5283 13:59:54.788065 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 13:59:54.791750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 13:59:54.791832 ==
5286 13:59:54.794563 Write leveling (Byte 0): 34 => 34
5287 13:59:54.797845 Write leveling (Byte 1): 31 => 31
5288 13:59:54.801312 DramcWriteLeveling(PI) end<-----
5289 13:59:54.801392
5290 13:59:54.801455 ==
5291 13:59:54.804581 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 13:59:54.808010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 13:59:54.808091 ==
5294 13:59:54.811278 [Gating] SW mode calibration
5295 13:59:54.818004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5296 13:59:54.824275 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5297 13:59:54.827670 0 14 0 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
5298 13:59:54.834477 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 13:59:54.837702 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 13:59:54.841169 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 13:59:54.844490 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 13:59:54.851047 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 13:59:54.854918 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
5304 13:59:54.857663 0 14 28 | B1->B0 | 2d2d 2929 | 0 0 | (0 1) (0 1)
5305 13:59:54.864424 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 13:59:54.867614 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 13:59:54.871335 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 13:59:54.877615 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 13:59:54.881318 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 13:59:54.884432 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 13:59:54.890945 0 15 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5312 13:59:54.894659 0 15 28 | B1->B0 | 3d3d 3c3c | 1 0 | (0 0) (0 0)
5313 13:59:54.897531 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5314 13:59:54.904367 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 13:59:54.907922 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 13:59:54.911280 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 13:59:54.917811 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 13:59:54.921078 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 13:59:54.924371 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 13:59:54.931006 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5321 13:59:54.934274 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5322 13:59:54.938133 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 13:59:54.944294 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 13:59:54.947812 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 13:59:54.951155 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 13:59:54.954397 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 13:59:54.961067 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 13:59:54.964116 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 13:59:54.967392 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 13:59:54.974420 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 13:59:54.977608 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 13:59:54.980716 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 13:59:54.987521 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 13:59:54.990855 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 13:59:54.994213 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 13:59:55.000932 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5337 13:59:55.004110 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5338 13:59:55.007265 Total UI for P1: 0, mck2ui 16
5339 13:59:55.010498 best dqsien dly found for B1: ( 1, 2, 30)
5340 13:59:55.014403 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 13:59:55.017452 Total UI for P1: 0, mck2ui 16
5342 13:59:55.020654 best dqsien dly found for B0: ( 1, 2, 30)
5343 13:59:55.024179 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5344 13:59:55.027202 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5345 13:59:55.027283
5346 13:59:55.033799 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5347 13:59:55.037583 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5348 13:59:55.040757 [Gating] SW calibration Done
5349 13:59:55.040860 ==
5350 13:59:55.043937 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 13:59:55.047519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 13:59:55.047656 ==
5353 13:59:55.047738 RX Vref Scan: 0
5354 13:59:55.047802
5355 13:59:55.050888 RX Vref 0 -> 0, step: 1
5356 13:59:55.050978
5357 13:59:55.053644 RX Delay -80 -> 252, step: 8
5358 13:59:55.057088 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5359 13:59:55.060617 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5360 13:59:55.067494 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5361 13:59:55.070620 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5362 13:59:55.073573 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5363 13:59:55.077567 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5364 13:59:55.080577 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5365 13:59:55.084139 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5366 13:59:55.090399 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5367 13:59:55.094010 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5368 13:59:55.097044 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5369 13:59:55.100497 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5370 13:59:55.104149 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5371 13:59:55.107005 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5372 13:59:55.113733 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5373 13:59:55.117442 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5374 13:59:55.117523 ==
5375 13:59:55.120709 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 13:59:55.123807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 13:59:55.123907 ==
5378 13:59:55.124005 DQS Delay:
5379 13:59:55.127224 DQS0 = 0, DQS1 = 0
5380 13:59:55.127297 DQM Delay:
5381 13:59:55.130333 DQM0 = 104, DQM1 = 93
5382 13:59:55.130404 DQ Delay:
5383 13:59:55.133766 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5384 13:59:55.137014 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =111
5385 13:59:55.140292 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5386 13:59:55.143463 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5387 13:59:55.143560
5388 13:59:55.143713
5389 13:59:55.143776 ==
5390 13:59:55.146927 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 13:59:55.153666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 13:59:55.153767 ==
5393 13:59:55.153875
5394 13:59:55.153962
5395 13:59:55.154050 TX Vref Scan disable
5396 13:59:55.157523 == TX Byte 0 ==
5397 13:59:55.160323 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5398 13:59:55.164018 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5399 13:59:55.167231 == TX Byte 1 ==
5400 13:59:55.170667 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5401 13:59:55.174379 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5402 13:59:55.177479 ==
5403 13:59:55.181051 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 13:59:55.184123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 13:59:55.184206 ==
5406 13:59:55.184268
5407 13:59:55.184325
5408 13:59:55.187051 TX Vref Scan disable
5409 13:59:55.187145 == TX Byte 0 ==
5410 13:59:55.194063 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5411 13:59:55.197310 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5412 13:59:55.197406 == TX Byte 1 ==
5413 13:59:55.203897 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5414 13:59:55.207168 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5415 13:59:55.207264
5416 13:59:55.207352 [DATLAT]
5417 13:59:55.211134 Freq=933, CH0 RK1
5418 13:59:55.211214
5419 13:59:55.211278 DATLAT Default: 0xb
5420 13:59:55.213763 0, 0xFFFF, sum = 0
5421 13:59:55.213846 1, 0xFFFF, sum = 0
5422 13:59:55.217705 2, 0xFFFF, sum = 0
5423 13:59:55.217787 3, 0xFFFF, sum = 0
5424 13:59:55.220394 4, 0xFFFF, sum = 0
5425 13:59:55.220476 5, 0xFFFF, sum = 0
5426 13:59:55.223973 6, 0xFFFF, sum = 0
5427 13:59:55.227244 7, 0xFFFF, sum = 0
5428 13:59:55.227325 8, 0xFFFF, sum = 0
5429 13:59:55.230582 9, 0xFFFF, sum = 0
5430 13:59:55.230667 10, 0x0, sum = 1
5431 13:59:55.230737 11, 0x0, sum = 2
5432 13:59:55.234000 12, 0x0, sum = 3
5433 13:59:55.234084 13, 0x0, sum = 4
5434 13:59:55.237149 best_step = 11
5435 13:59:55.237229
5436 13:59:55.237292 ==
5437 13:59:55.240194 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 13:59:55.243630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 13:59:55.243725 ==
5440 13:59:55.246857 RX Vref Scan: 0
5441 13:59:55.246938
5442 13:59:55.247001 RX Vref 0 -> 0, step: 1
5443 13:59:55.247059
5444 13:59:55.250465 RX Delay -53 -> 252, step: 4
5445 13:59:55.258027 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5446 13:59:55.260742 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5447 13:59:55.264168 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5448 13:59:55.267504 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5449 13:59:55.270805 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5450 13:59:55.277486 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5451 13:59:55.280782 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5452 13:59:55.283997 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5453 13:59:55.287393 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5454 13:59:55.290751 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5455 13:59:55.297777 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5456 13:59:55.301112 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5457 13:59:55.304536 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5458 13:59:55.307657 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5459 13:59:55.310949 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5460 13:59:55.317352 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5461 13:59:55.317432 ==
5462 13:59:55.320776 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 13:59:55.324524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 13:59:55.324605 ==
5465 13:59:55.324669 DQS Delay:
5466 13:59:55.327765 DQS0 = 0, DQS1 = 0
5467 13:59:55.327867 DQM Delay:
5468 13:59:55.330819 DQM0 = 105, DQM1 = 94
5469 13:59:55.330899 DQ Delay:
5470 13:59:55.334196 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5471 13:59:55.337658 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5472 13:59:55.341246 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5473 13:59:55.344142 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =104
5474 13:59:55.344223
5475 13:59:55.344286
5476 13:59:55.354649 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5477 13:59:55.354732 CH0 RK1: MR19=505, MR18=2C04
5478 13:59:55.361119 CH0_RK1: MR19=0x505, MR18=0x2C04, DQSOSC=408, MR23=63, INC=65, DEC=43
5479 13:59:55.364096 [RxdqsGatingPostProcess] freq 933
5480 13:59:55.370813 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5481 13:59:55.374232 best DQS0 dly(2T, 0.5T) = (0, 10)
5482 13:59:55.377690 best DQS1 dly(2T, 0.5T) = (0, 10)
5483 13:59:55.380737 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5484 13:59:55.384243 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5485 13:59:55.384323 best DQS0 dly(2T, 0.5T) = (0, 10)
5486 13:59:55.387510 best DQS1 dly(2T, 0.5T) = (0, 10)
5487 13:59:55.391051 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5488 13:59:55.394135 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5489 13:59:55.397903 Pre-setting of DQS Precalculation
5490 13:59:55.404508 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5491 13:59:55.404589 ==
5492 13:59:55.407874 Dram Type= 6, Freq= 0, CH_1, rank 0
5493 13:59:55.410777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5494 13:59:55.410859 ==
5495 13:59:55.417358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5496 13:59:55.424011 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5497 13:59:55.427770 [CA 0] Center 36 (6~67) winsize 62
5498 13:59:55.431209 [CA 1] Center 37 (6~68) winsize 63
5499 13:59:55.434647 [CA 2] Center 34 (4~65) winsize 62
5500 13:59:55.437426 [CA 3] Center 34 (4~65) winsize 62
5501 13:59:55.440625 [CA 4] Center 34 (4~64) winsize 61
5502 13:59:55.443736 [CA 5] Center 33 (3~64) winsize 62
5503 13:59:55.443816
5504 13:59:55.447514 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5505 13:59:55.447654
5506 13:59:55.450995 [CATrainingPosCal] consider 1 rank data
5507 13:59:55.453889 u2DelayCellTimex100 = 270/100 ps
5508 13:59:55.457290 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5509 13:59:55.460676 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5510 13:59:55.463717 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5511 13:59:55.467124 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5512 13:59:55.470574 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5513 13:59:55.473906 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5514 13:59:55.474017
5515 13:59:55.477096 CA PerBit enable=1, Macro0, CA PI delay=33
5516 13:59:55.477176
5517 13:59:55.480429 [CBTSetCACLKResult] CA Dly = 33
5518 13:59:55.483879 CS Dly: 6 (0~37)
5519 13:59:55.483960 ==
5520 13:59:55.487166 Dram Type= 6, Freq= 0, CH_1, rank 1
5521 13:59:55.490973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 13:59:55.491082 ==
5523 13:59:55.497332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 13:59:55.503740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5525 13:59:55.507123 [CA 0] Center 36 (6~67) winsize 62
5526 13:59:55.510133 [CA 1] Center 37 (6~68) winsize 63
5527 13:59:55.513808 [CA 2] Center 35 (4~66) winsize 63
5528 13:59:55.516898 [CA 3] Center 34 (4~65) winsize 62
5529 13:59:55.520438 [CA 4] Center 34 (4~65) winsize 62
5530 13:59:55.523523 [CA 5] Center 34 (4~64) winsize 61
5531 13:59:55.523644
5532 13:59:55.526911 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5533 13:59:55.526981
5534 13:59:55.530293 [CATrainingPosCal] consider 2 rank data
5535 13:59:55.533400 u2DelayCellTimex100 = 270/100 ps
5536 13:59:55.537146 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5537 13:59:55.540217 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5538 13:59:55.543834 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5539 13:59:55.547163 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5540 13:59:55.550276 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5541 13:59:55.553463 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5542 13:59:55.553540
5543 13:59:55.557022 CA PerBit enable=1, Macro0, CA PI delay=34
5544 13:59:55.557095
5545 13:59:55.560700 [CBTSetCACLKResult] CA Dly = 34
5546 13:59:55.563822 CS Dly: 7 (0~39)
5547 13:59:55.563896
5548 13:59:55.566869 ----->DramcWriteLeveling(PI) begin...
5549 13:59:55.566951 ==
5550 13:59:55.570217 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 13:59:55.573575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 13:59:55.573657 ==
5553 13:59:55.577113 Write leveling (Byte 0): 26 => 26
5554 13:59:55.580485 Write leveling (Byte 1): 27 => 27
5555 13:59:55.583640 DramcWriteLeveling(PI) end<-----
5556 13:59:55.583721
5557 13:59:55.583783 ==
5558 13:59:55.586849 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 13:59:55.590224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 13:59:55.590300 ==
5561 13:59:55.593673 [Gating] SW mode calibration
5562 13:59:55.600315 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5563 13:59:55.606671 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5564 13:59:55.610011 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 13:59:55.616751 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 13:59:55.620259 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 13:59:55.623293 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 13:59:55.629886 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 13:59:55.633422 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 13:59:55.636860 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
5571 13:59:55.643121 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5572 13:59:55.646535 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 13:59:55.649702 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 13:59:55.656383 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 13:59:55.659994 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 13:59:55.663359 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 13:59:55.669539 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 13:59:55.673095 0 15 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5579 13:59:55.676328 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5580 13:59:55.683185 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 13:59:55.686214 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 13:59:55.689844 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 13:59:55.696353 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 13:59:55.699609 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 13:59:55.702919 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 13:59:55.706400 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5587 13:59:55.713044 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5588 13:59:55.716322 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 13:59:55.719556 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 13:59:55.726059 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 13:59:55.729334 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 13:59:55.732800 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 13:59:55.739786 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 13:59:55.742932 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 13:59:55.746615 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 13:59:55.752767 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 13:59:55.756325 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 13:59:55.759553 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 13:59:55.766227 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 13:59:55.769389 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 13:59:55.773122 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 13:59:55.779407 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 13:59:55.782626 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5604 13:59:55.786013 Total UI for P1: 0, mck2ui 16
5605 13:59:55.789087 best dqsien dly found for B1: ( 1, 2, 26)
5606 13:59:55.792993 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 13:59:55.795736 Total UI for P1: 0, mck2ui 16
5608 13:59:55.799447 best dqsien dly found for B0: ( 1, 2, 28)
5609 13:59:55.802884 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5610 13:59:55.805993 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5611 13:59:55.806073
5612 13:59:55.812790 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5613 13:59:55.815982 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5614 13:59:55.816057 [Gating] SW calibration Done
5615 13:59:55.819199 ==
5616 13:59:55.819279 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 13:59:55.825967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 13:59:55.826052 ==
5619 13:59:55.826117 RX Vref Scan: 0
5620 13:59:55.826175
5621 13:59:55.828930 RX Vref 0 -> 0, step: 1
5622 13:59:55.829004
5623 13:59:55.832582 RX Delay -80 -> 252, step: 8
5624 13:59:55.835811 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5625 13:59:55.839428 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5626 13:59:55.842632 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5627 13:59:55.845862 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5628 13:59:55.852452 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5629 13:59:55.855747 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5630 13:59:55.859396 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5631 13:59:55.862822 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5632 13:59:55.866050 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5633 13:59:55.869397 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5634 13:59:55.875693 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5635 13:59:55.879316 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5636 13:59:55.882234 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5637 13:59:55.886266 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5638 13:59:55.889228 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5639 13:59:55.895836 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5640 13:59:55.895920 ==
5641 13:59:55.899192 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 13:59:55.902319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 13:59:55.902388 ==
5644 13:59:55.902456 DQS Delay:
5645 13:59:55.906218 DQS0 = 0, DQS1 = 0
5646 13:59:55.906291 DQM Delay:
5647 13:59:55.909599 DQM0 = 102, DQM1 = 98
5648 13:59:55.909680 DQ Delay:
5649 13:59:55.912435 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5650 13:59:55.916407 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5651 13:59:55.919519 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5652 13:59:55.922300 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5653 13:59:55.922371
5654 13:59:55.922429
5655 13:59:55.922509 ==
5656 13:59:55.925797 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 13:59:55.929673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 13:59:55.933227 ==
5659 13:59:55.933306
5660 13:59:55.933367
5661 13:59:55.933431 TX Vref Scan disable
5662 13:59:55.936123 == TX Byte 0 ==
5663 13:59:55.939573 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5664 13:59:55.942716 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5665 13:59:55.946172 == TX Byte 1 ==
5666 13:59:55.949189 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5667 13:59:55.952961 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5668 13:59:55.953041 ==
5669 13:59:55.956135 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 13:59:55.962984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 13:59:55.963060 ==
5672 13:59:55.963122
5673 13:59:55.963187
5674 13:59:55.965823 TX Vref Scan disable
5675 13:59:55.965900 == TX Byte 0 ==
5676 13:59:55.972192 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5677 13:59:55.975587 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5678 13:59:55.975707 == TX Byte 1 ==
5679 13:59:55.982483 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5680 13:59:55.985589 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5681 13:59:55.985690
5682 13:59:55.985781 [DATLAT]
5683 13:59:55.989205 Freq=933, CH1 RK0
5684 13:59:55.989285
5685 13:59:55.989347 DATLAT Default: 0xd
5686 13:59:55.992165 0, 0xFFFF, sum = 0
5687 13:59:55.992247 1, 0xFFFF, sum = 0
5688 13:59:55.995898 2, 0xFFFF, sum = 0
5689 13:59:55.995979 3, 0xFFFF, sum = 0
5690 13:59:55.998930 4, 0xFFFF, sum = 0
5691 13:59:55.999012 5, 0xFFFF, sum = 0
5692 13:59:56.002497 6, 0xFFFF, sum = 0
5693 13:59:56.002588 7, 0xFFFF, sum = 0
5694 13:59:56.005613 8, 0xFFFF, sum = 0
5695 13:59:56.008756 9, 0xFFFF, sum = 0
5696 13:59:56.008838 10, 0x0, sum = 1
5697 13:59:56.008902 11, 0x0, sum = 2
5698 13:59:56.012337 12, 0x0, sum = 3
5699 13:59:56.012409 13, 0x0, sum = 4
5700 13:59:56.015558 best_step = 11
5701 13:59:56.015693
5702 13:59:56.015781 ==
5703 13:59:56.018770 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 13:59:56.022390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 13:59:56.022497 ==
5706 13:59:56.025817 RX Vref Scan: 1
5707 13:59:56.025897
5708 13:59:56.025959 RX Vref 0 -> 0, step: 1
5709 13:59:56.026018
5710 13:59:56.028640 RX Delay -45 -> 252, step: 4
5711 13:59:56.028720
5712 13:59:56.032068 Set Vref, RX VrefLevel [Byte0]: 54
5713 13:59:56.035103 [Byte1]: 51
5714 13:59:56.039522
5715 13:59:56.039629 Final RX Vref Byte 0 = 54 to rank0
5716 13:59:56.042896 Final RX Vref Byte 1 = 51 to rank0
5717 13:59:56.046314 Final RX Vref Byte 0 = 54 to rank1
5718 13:59:56.049392 Final RX Vref Byte 1 = 51 to rank1==
5719 13:59:56.052909 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 13:59:56.059530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 13:59:56.059651 ==
5722 13:59:56.059715 DQS Delay:
5723 13:59:56.059774 DQS0 = 0, DQS1 = 0
5724 13:59:56.062614 DQM Delay:
5725 13:59:56.062694 DQM0 = 103, DQM1 = 100
5726 13:59:56.066310 DQ Delay:
5727 13:59:56.069627 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5728 13:59:56.073076 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5729 13:59:56.076003 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5730 13:59:56.079575 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =110
5731 13:59:56.079696
5732 13:59:56.079759
5733 13:59:56.086069 [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5734 13:59:56.089282 CH1 RK0: MR19=505, MR18=1931
5735 13:59:56.095991 CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43
5736 13:59:56.096073
5737 13:59:56.099570 ----->DramcWriteLeveling(PI) begin...
5738 13:59:56.099714 ==
5739 13:59:56.102934 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 13:59:56.105851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 13:59:56.105932 ==
5742 13:59:56.109500 Write leveling (Byte 0): 28 => 28
5743 13:59:56.112820 Write leveling (Byte 1): 28 => 28
5744 13:59:56.115991 DramcWriteLeveling(PI) end<-----
5745 13:59:56.116086
5746 13:59:56.116149 ==
5747 13:59:56.119484 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 13:59:56.126091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 13:59:56.126175 ==
5750 13:59:56.126239 [Gating] SW mode calibration
5751 13:59:56.136038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5752 13:59:56.139264 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5753 13:59:56.142903 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 13:59:56.149585 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 13:59:56.152438 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 13:59:56.155924 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 13:59:56.162883 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 13:59:56.165901 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 13:59:56.169246 0 14 24 | B1->B0 | 3030 3131 | 0 0 | (0 1) (0 0)
5760 13:59:56.175963 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 13:59:56.179211 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 13:59:56.182818 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 13:59:56.189364 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 13:59:56.192338 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 13:59:56.195711 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 13:59:56.202403 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5767 13:59:56.205823 0 15 24 | B1->B0 | 3535 2727 | 1 0 | (0 0) (0 0)
5768 13:59:56.209168 0 15 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
5769 13:59:56.215583 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 13:59:56.218828 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 13:59:56.222576 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 13:59:56.228959 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 13:59:56.232956 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 13:59:56.236207 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 13:59:56.239505 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 13:59:56.245958 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 13:59:56.249230 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 13:59:56.252855 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 13:59:56.258853 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 13:59:56.262611 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 13:59:56.265910 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 13:59:56.272225 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 13:59:56.275829 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 13:59:56.279196 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 13:59:56.285756 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 13:59:56.289534 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 13:59:56.292318 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 13:59:56.299432 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 13:59:56.302252 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 13:59:56.305739 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 13:59:56.312451 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5792 13:59:56.315680 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 13:59:56.319065 Total UI for P1: 0, mck2ui 16
5794 13:59:56.322841 best dqsien dly found for B0: ( 1, 2, 24)
5795 13:59:56.325540 Total UI for P1: 0, mck2ui 16
5796 13:59:56.329034 best dqsien dly found for B1: ( 1, 2, 24)
5797 13:59:56.332150 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5798 13:59:56.336176 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5799 13:59:56.336251
5800 13:59:56.339351 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5801 13:59:56.342270 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5802 13:59:56.345644 [Gating] SW calibration Done
5803 13:59:56.345720 ==
5804 13:59:56.348896 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 13:59:56.352271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 13:59:56.352346 ==
5807 13:59:56.355676 RX Vref Scan: 0
5808 13:59:56.355748
5809 13:59:56.359202 RX Vref 0 -> 0, step: 1
5810 13:59:56.359274
5811 13:59:56.359365 RX Delay -80 -> 252, step: 8
5812 13:59:56.365942 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5813 13:59:56.369292 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5814 13:59:56.372695 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5815 13:59:56.376269 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5816 13:59:56.378916 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5817 13:59:56.382613 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5818 13:59:56.389239 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5819 13:59:56.392336 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5820 13:59:56.395886 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5821 13:59:56.398891 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5822 13:59:56.402499 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5823 13:59:56.405892 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5824 13:59:56.412289 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5825 13:59:56.415717 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5826 13:59:56.418807 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5827 13:59:56.422130 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5828 13:59:56.422212 ==
5829 13:59:56.425702 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 13:59:56.429106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 13:59:56.432448 ==
5832 13:59:56.432528 DQS Delay:
5833 13:59:56.432592 DQS0 = 0, DQS1 = 0
5834 13:59:56.435729 DQM Delay:
5835 13:59:56.435810 DQM0 = 102, DQM1 = 98
5836 13:59:56.438847 DQ Delay:
5837 13:59:56.442105 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5838 13:59:56.445546 DQ4 =95, DQ5 =111, DQ6 =115, DQ7 =99
5839 13:59:56.448989 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5840 13:59:56.452152 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5841 13:59:56.452233
5842 13:59:56.452296
5843 13:59:56.452354 ==
5844 13:59:56.455536 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 13:59:56.458907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 13:59:56.458988 ==
5847 13:59:56.459051
5848 13:59:56.459110
5849 13:59:56.462260 TX Vref Scan disable
5850 13:59:56.465373 == TX Byte 0 ==
5851 13:59:56.468952 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5852 13:59:56.472207 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5853 13:59:56.475696 == TX Byte 1 ==
5854 13:59:56.478867 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5855 13:59:56.481942 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5856 13:59:56.482023 ==
5857 13:59:56.485462 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 13:59:56.488877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 13:59:56.488957 ==
5860 13:59:56.492043
5861 13:59:56.492148
5862 13:59:56.492239 TX Vref Scan disable
5863 13:59:56.495572 == TX Byte 0 ==
5864 13:59:56.499089 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5865 13:59:56.505613 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5866 13:59:56.505694 == TX Byte 1 ==
5867 13:59:56.508921 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5868 13:59:56.512076 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5869 13:59:56.515508
5870 13:59:56.515638 [DATLAT]
5871 13:59:56.515705 Freq=933, CH1 RK1
5872 13:59:56.515765
5873 13:59:56.518920 DATLAT Default: 0xb
5874 13:59:56.519001 0, 0xFFFF, sum = 0
5875 13:59:56.522201 1, 0xFFFF, sum = 0
5876 13:59:56.522284 2, 0xFFFF, sum = 0
5877 13:59:56.525320 3, 0xFFFF, sum = 0
5878 13:59:56.525402 4, 0xFFFF, sum = 0
5879 13:59:56.528506 5, 0xFFFF, sum = 0
5880 13:59:56.532206 6, 0xFFFF, sum = 0
5881 13:59:56.532288 7, 0xFFFF, sum = 0
5882 13:59:56.535324 8, 0xFFFF, sum = 0
5883 13:59:56.535412 9, 0xFFFF, sum = 0
5884 13:59:56.538643 10, 0x0, sum = 1
5885 13:59:56.538718 11, 0x0, sum = 2
5886 13:59:56.538781 12, 0x0, sum = 3
5887 13:59:56.541824 13, 0x0, sum = 4
5888 13:59:56.541936 best_step = 11
5889 13:59:56.542024
5890 13:59:56.545592 ==
5891 13:59:56.545666 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 13:59:56.551898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 13:59:56.551976 ==
5894 13:59:56.552038 RX Vref Scan: 0
5895 13:59:56.552095
5896 13:59:56.554919 RX Vref 0 -> 0, step: 1
5897 13:59:56.554994
5898 13:59:56.558558 RX Delay -45 -> 252, step: 4
5899 13:59:56.562363 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5900 13:59:56.568798 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5901 13:59:56.572048 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5902 13:59:56.575671 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5903 13:59:56.578372 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5904 13:59:56.581862 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5905 13:59:56.588761 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5906 13:59:56.591993 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5907 13:59:56.594955 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5908 13:59:56.598609 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5909 13:59:56.601729 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5910 13:59:56.605240 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5911 13:59:56.611775 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5912 13:59:56.614804 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5913 13:59:56.618086 iDelay=203, Bit 14, Center 106 (23 ~ 190) 168
5914 13:59:56.621409 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5915 13:59:56.621483 ==
5916 13:59:56.625388 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 13:59:56.631352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 13:59:56.631426 ==
5919 13:59:56.631487 DQS Delay:
5920 13:59:56.634964 DQS0 = 0, DQS1 = 0
5921 13:59:56.635041 DQM Delay:
5922 13:59:56.638297 DQM0 = 105, DQM1 = 101
5923 13:59:56.638368 DQ Delay:
5924 13:59:56.641480 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5925 13:59:56.644893 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5926 13:59:56.648100 DQ8 =92, DQ9 =92, DQ10 =100, DQ11 =94
5927 13:59:56.651407 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5928 13:59:56.651479
5929 13:59:56.651547
5930 13:59:56.661409 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5931 13:59:56.661560 CH1 RK1: MR19=505, MR18=2F02
5932 13:59:56.667967 CH1_RK1: MR19=0x505, MR18=0x2F02, DQSOSC=407, MR23=63, INC=65, DEC=43
5933 13:59:56.671601 [RxdqsGatingPostProcess] freq 933
5934 13:59:56.678052 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5935 13:59:56.681704 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 13:59:56.684395 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 13:59:56.687903 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 13:59:56.691276 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 13:59:56.691348 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 13:59:56.694511 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 13:59:56.697954 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 13:59:56.701359 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 13:59:56.704859 Pre-setting of DQS Precalculation
5944 13:59:56.711278 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5945 13:59:56.717916 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5946 13:59:56.724801 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5947 13:59:56.724879
5948 13:59:56.724941
5949 13:59:56.727927 [Calibration Summary] 1866 Mbps
5950 13:59:56.728010 CH 0, Rank 0
5951 13:59:56.731484 SW Impedance : PASS
5952 13:59:56.734732 DUTY Scan : NO K
5953 13:59:56.734812 ZQ Calibration : PASS
5954 13:59:56.737652 Jitter Meter : NO K
5955 13:59:56.741193 CBT Training : PASS
5956 13:59:56.741272 Write leveling : PASS
5957 13:59:56.744807 RX DQS gating : PASS
5958 13:59:56.747798 RX DQ/DQS(RDDQC) : PASS
5959 13:59:56.747872 TX DQ/DQS : PASS
5960 13:59:56.751108 RX DATLAT : PASS
5961 13:59:56.754254 RX DQ/DQS(Engine): PASS
5962 13:59:56.754325 TX OE : NO K
5963 13:59:56.754392 All Pass.
5964 13:59:56.757670
5965 13:59:56.757742 CH 0, Rank 1
5966 13:59:56.760967 SW Impedance : PASS
5967 13:59:56.761040 DUTY Scan : NO K
5968 13:59:56.764574 ZQ Calibration : PASS
5969 13:59:56.764682 Jitter Meter : NO K
5970 13:59:56.767569 CBT Training : PASS
5971 13:59:56.771262 Write leveling : PASS
5972 13:59:56.771332 RX DQS gating : PASS
5973 13:59:56.774369 RX DQ/DQS(RDDQC) : PASS
5974 13:59:56.777722 TX DQ/DQS : PASS
5975 13:59:56.777809 RX DATLAT : PASS
5976 13:59:56.780775 RX DQ/DQS(Engine): PASS
5977 13:59:56.784185 TX OE : NO K
5978 13:59:56.784254 All Pass.
5979 13:59:56.784314
5980 13:59:56.784370 CH 1, Rank 0
5981 13:59:56.787711 SW Impedance : PASS
5982 13:59:56.791260 DUTY Scan : NO K
5983 13:59:56.791336 ZQ Calibration : PASS
5984 13:59:56.794180 Jitter Meter : NO K
5985 13:59:56.797644 CBT Training : PASS
5986 13:59:56.797717 Write leveling : PASS
5987 13:59:56.801123 RX DQS gating : PASS
5988 13:59:56.804312 RX DQ/DQS(RDDQC) : PASS
5989 13:59:56.804389 TX DQ/DQS : PASS
5990 13:59:56.807690 RX DATLAT : PASS
5991 13:59:56.811047 RX DQ/DQS(Engine): PASS
5992 13:59:56.811153 TX OE : NO K
5993 13:59:56.811245 All Pass.
5994 13:59:56.811331
5995 13:59:56.814409 CH 1, Rank 1
5996 13:59:56.814489 SW Impedance : PASS
5997 13:59:56.817817 DUTY Scan : NO K
5998 13:59:56.821198 ZQ Calibration : PASS
5999 13:59:56.821280 Jitter Meter : NO K
6000 13:59:56.824412 CBT Training : PASS
6001 13:59:56.827899 Write leveling : PASS
6002 13:59:56.827970 RX DQS gating : PASS
6003 13:59:56.831132 RX DQ/DQS(RDDQC) : PASS
6004 13:59:56.834409 TX DQ/DQS : PASS
6005 13:59:56.834482 RX DATLAT : PASS
6006 13:59:56.837429 RX DQ/DQS(Engine): PASS
6007 13:59:56.841241 TX OE : NO K
6008 13:59:56.841355 All Pass.
6009 13:59:56.841448
6010 13:59:56.841537 DramC Write-DBI off
6011 13:59:56.844555 PER_BANK_REFRESH: Hybrid Mode
6012 13:59:56.847790 TX_TRACKING: ON
6013 13:59:56.854205 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6014 13:59:56.857972 [FAST_K] Save calibration result to emmc
6015 13:59:56.864616 dramc_set_vcore_voltage set vcore to 650000
6016 13:59:56.864691 Read voltage for 400, 6
6017 13:59:56.867750 Vio18 = 0
6018 13:59:56.867838 Vcore = 650000
6019 13:59:56.867900 Vdram = 0
6020 13:59:56.871392 Vddq = 0
6021 13:59:56.871487 Vmddr = 0
6022 13:59:56.874566 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6023 13:59:56.881289 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6024 13:59:56.884238 MEM_TYPE=3, freq_sel=20
6025 13:59:56.884318 sv_algorithm_assistance_LP4_800
6026 13:59:56.890958 ============ PULL DRAM RESETB DOWN ============
6027 13:59:56.894244 ========== PULL DRAM RESETB DOWN end =========
6028 13:59:56.897812 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6029 13:59:56.901272 ===================================
6030 13:59:56.904360 LPDDR4 DRAM CONFIGURATION
6031 13:59:56.907233 ===================================
6032 13:59:56.910824 EX_ROW_EN[0] = 0x0
6033 13:59:56.910902 EX_ROW_EN[1] = 0x0
6034 13:59:56.914361 LP4Y_EN = 0x0
6035 13:59:56.914437 WORK_FSP = 0x0
6036 13:59:56.917795 WL = 0x2
6037 13:59:56.917866 RL = 0x2
6038 13:59:56.921030 BL = 0x2
6039 13:59:56.921100 RPST = 0x0
6040 13:59:56.923850 RD_PRE = 0x0
6041 13:59:56.923934 WR_PRE = 0x1
6042 13:59:56.927907 WR_PST = 0x0
6043 13:59:56.928004 DBI_WR = 0x0
6044 13:59:56.931000 DBI_RD = 0x0
6045 13:59:56.931098 OTF = 0x1
6046 13:59:56.933898 ===================================
6047 13:59:56.937212 ===================================
6048 13:59:56.940881 ANA top config
6049 13:59:56.943887 ===================================
6050 13:59:56.947558 DLL_ASYNC_EN = 0
6051 13:59:56.947722 ALL_SLAVE_EN = 1
6052 13:59:56.950701 NEW_RANK_MODE = 1
6053 13:59:56.954113 DLL_IDLE_MODE = 1
6054 13:59:56.957321 LP45_APHY_COMB_EN = 1
6055 13:59:56.957401 TX_ODT_DIS = 1
6056 13:59:56.961111 NEW_8X_MODE = 1
6057 13:59:56.964218 ===================================
6058 13:59:56.967543 ===================================
6059 13:59:56.970968 data_rate = 800
6060 13:59:56.974046 CKR = 1
6061 13:59:56.977404 DQ_P2S_RATIO = 4
6062 13:59:56.980651 ===================================
6063 13:59:56.984151 CA_P2S_RATIO = 4
6064 13:59:56.984226 DQ_CA_OPEN = 0
6065 13:59:56.987734 DQ_SEMI_OPEN = 1
6066 13:59:56.990746 CA_SEMI_OPEN = 1
6067 13:59:56.993958 CA_FULL_RATE = 0
6068 13:59:56.997456 DQ_CKDIV4_EN = 0
6069 13:59:57.000713 CA_CKDIV4_EN = 1
6070 13:59:57.000816 CA_PREDIV_EN = 0
6071 13:59:57.003812 PH8_DLY = 0
6072 13:59:57.007323 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6073 13:59:57.010517 DQ_AAMCK_DIV = 0
6074 13:59:57.013770 CA_AAMCK_DIV = 0
6075 13:59:57.017223 CA_ADMCK_DIV = 4
6076 13:59:57.017323 DQ_TRACK_CA_EN = 0
6077 13:59:57.020700 CA_PICK = 800
6078 13:59:57.023868 CA_MCKIO = 400
6079 13:59:57.027380 MCKIO_SEMI = 400
6080 13:59:57.030808 PLL_FREQ = 3016
6081 13:59:57.034266 DQ_UI_PI_RATIO = 32
6082 13:59:57.037269 CA_UI_PI_RATIO = 32
6083 13:59:57.040548 ===================================
6084 13:59:57.043857 ===================================
6085 13:59:57.043938 memory_type:LPDDR4
6086 13:59:57.047216 GP_NUM : 10
6087 13:59:57.050377 SRAM_EN : 1
6088 13:59:57.050482 MD32_EN : 0
6089 13:59:57.054097 ===================================
6090 13:59:57.057023 [ANA_INIT] >>>>>>>>>>>>>>
6091 13:59:57.060401 <<<<<< [CONFIGURE PHASE]: ANA_TX
6092 13:59:57.063792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6093 13:59:57.067144 ===================================
6094 13:59:57.070485 data_rate = 800,PCW = 0X7400
6095 13:59:57.074256 ===================================
6096 13:59:57.077263 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6097 13:59:57.080484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 13:59:57.093612 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 13:59:57.097280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6100 13:59:57.100485 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6101 13:59:57.103942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6102 13:59:57.107280 [ANA_INIT] flow start
6103 13:59:57.107388 [ANA_INIT] PLL >>>>>>>>
6104 13:59:57.110381 [ANA_INIT] PLL <<<<<<<<
6105 13:59:57.113556 [ANA_INIT] MIDPI >>>>>>>>
6106 13:59:57.116899 [ANA_INIT] MIDPI <<<<<<<<
6107 13:59:57.116971 [ANA_INIT] DLL >>>>>>>>
6108 13:59:57.120144 [ANA_INIT] flow end
6109 13:59:57.124083 ============ LP4 DIFF to SE enter ============
6110 13:59:57.126829 ============ LP4 DIFF to SE exit ============
6111 13:59:57.130571 [ANA_INIT] <<<<<<<<<<<<<
6112 13:59:57.133658 [Flow] Enable top DCM control >>>>>
6113 13:59:57.136978 [Flow] Enable top DCM control <<<<<
6114 13:59:57.140396 Enable DLL master slave shuffle
6115 13:59:57.147785 ==============================================================
6116 13:59:57.147873 Gating Mode config
6117 13:59:57.153805 ==============================================================
6118 13:59:57.153880 Config description:
6119 13:59:57.163437 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6120 13:59:57.170281 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6121 13:59:57.176787 SELPH_MODE 0: By rank 1: By Phase
6122 13:59:57.180210 ==============================================================
6123 13:59:57.183707 GAT_TRACK_EN = 0
6124 13:59:57.186758 RX_GATING_MODE = 2
6125 13:59:57.190417 RX_GATING_TRACK_MODE = 2
6126 13:59:57.193706 SELPH_MODE = 1
6127 13:59:57.197280 PICG_EARLY_EN = 1
6128 13:59:57.200359 VALID_LAT_VALUE = 1
6129 13:59:57.203443 ==============================================================
6130 13:59:57.206783 Enter into Gating configuration >>>>
6131 13:59:57.210187 Exit from Gating configuration <<<<
6132 13:59:57.213586 Enter into DVFS_PRE_config >>>>>
6133 13:59:57.227163 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6134 13:59:57.230393 Exit from DVFS_PRE_config <<<<<
6135 13:59:57.230474 Enter into PICG configuration >>>>
6136 13:59:57.233449 Exit from PICG configuration <<<<
6137 13:59:57.236879 [RX_INPUT] configuration >>>>>
6138 13:59:57.240397 [RX_INPUT] configuration <<<<<
6139 13:59:57.247049 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6140 13:59:57.250459 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6141 13:59:57.256741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 13:59:57.263584 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 13:59:57.270340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 13:59:57.276891 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 13:59:57.280098 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6146 13:59:57.283844 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6147 13:59:57.286757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6148 13:59:57.293574 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6149 13:59:57.296796 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6150 13:59:57.300396 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6151 13:59:57.303649 ===================================
6152 13:59:57.306730 LPDDR4 DRAM CONFIGURATION
6153 13:59:57.310277 ===================================
6154 13:59:57.313395 EX_ROW_EN[0] = 0x0
6155 13:59:57.313475 EX_ROW_EN[1] = 0x0
6156 13:59:57.317075 LP4Y_EN = 0x0
6157 13:59:57.317156 WORK_FSP = 0x0
6158 13:59:57.319863 WL = 0x2
6159 13:59:57.319943 RL = 0x2
6160 13:59:57.323160 BL = 0x2
6161 13:59:57.323240 RPST = 0x0
6162 13:59:57.326619 RD_PRE = 0x0
6163 13:59:57.326699 WR_PRE = 0x1
6164 13:59:57.330115 WR_PST = 0x0
6165 13:59:57.330217 DBI_WR = 0x0
6166 13:59:57.333610 DBI_RD = 0x0
6167 13:59:57.333691 OTF = 0x1
6168 13:59:57.336835 ===================================
6169 13:59:57.339991 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6170 13:59:57.346678 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6171 13:59:57.350063 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 13:59:57.353164 ===================================
6173 13:59:57.356748 LPDDR4 DRAM CONFIGURATION
6174 13:59:57.359803 ===================================
6175 13:59:57.359884 EX_ROW_EN[0] = 0x10
6176 13:59:57.363462 EX_ROW_EN[1] = 0x0
6177 13:59:57.366485 LP4Y_EN = 0x0
6178 13:59:57.366591 WORK_FSP = 0x0
6179 13:59:57.369752 WL = 0x2
6180 13:59:57.369832 RL = 0x2
6181 13:59:57.373336 BL = 0x2
6182 13:59:57.373417 RPST = 0x0
6183 13:59:57.376585 RD_PRE = 0x0
6184 13:59:57.376666 WR_PRE = 0x1
6185 13:59:57.379687 WR_PST = 0x0
6186 13:59:57.379767 DBI_WR = 0x0
6187 13:59:57.383295 DBI_RD = 0x0
6188 13:59:57.383401 OTF = 0x1
6189 13:59:57.386625 ===================================
6190 13:59:57.393158 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6191 13:59:57.397231 nWR fixed to 30
6192 13:59:57.400626 [ModeRegInit_LP4] CH0 RK0
6193 13:59:57.400706 [ModeRegInit_LP4] CH0 RK1
6194 13:59:57.403863 [ModeRegInit_LP4] CH1 RK0
6195 13:59:57.406996 [ModeRegInit_LP4] CH1 RK1
6196 13:59:57.407076 match AC timing 19
6197 13:59:57.414019 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6198 13:59:57.417134 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6199 13:59:57.420672 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6200 13:59:57.427288 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6201 13:59:57.430578 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6202 13:59:57.430659 ==
6203 13:59:57.433935 Dram Type= 6, Freq= 0, CH_0, rank 0
6204 13:59:57.437732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6205 13:59:57.437814 ==
6206 13:59:57.444249 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6207 13:59:57.450468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6208 13:59:57.453713 [CA 0] Center 36 (8~64) winsize 57
6209 13:59:57.457145 [CA 1] Center 36 (8~64) winsize 57
6210 13:59:57.460517 [CA 2] Center 36 (8~64) winsize 57
6211 13:59:57.460598 [CA 3] Center 36 (8~64) winsize 57
6212 13:59:57.464053 [CA 4] Center 36 (8~64) winsize 57
6213 13:59:57.466966 [CA 5] Center 36 (8~64) winsize 57
6214 13:59:57.467060
6215 13:59:57.470476 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6216 13:59:57.473831
6217 13:59:57.476938 [CATrainingPosCal] consider 1 rank data
6218 13:59:57.477018 u2DelayCellTimex100 = 270/100 ps
6219 13:59:57.484010 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 13:59:57.487163 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 13:59:57.490306 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 13:59:57.493707 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 13:59:57.497487 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 13:59:57.500583 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 13:59:57.500664
6226 13:59:57.503563 CA PerBit enable=1, Macro0, CA PI delay=36
6227 13:59:57.503648
6228 13:59:57.507514 [CBTSetCACLKResult] CA Dly = 36
6229 13:59:57.510728 CS Dly: 1 (0~32)
6230 13:59:57.510801 ==
6231 13:59:57.513827 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 13:59:57.517141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 13:59:57.517212 ==
6234 13:59:57.524051 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 13:59:57.527271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 13:59:57.530574 [CA 0] Center 36 (8~64) winsize 57
6237 13:59:57.533554 [CA 1] Center 36 (8~64) winsize 57
6238 13:59:57.537264 [CA 2] Center 36 (8~64) winsize 57
6239 13:59:57.540267 [CA 3] Center 36 (8~64) winsize 57
6240 13:59:57.544224 [CA 4] Center 36 (8~64) winsize 57
6241 13:59:57.547101 [CA 5] Center 36 (8~64) winsize 57
6242 13:59:57.547171
6243 13:59:57.550462 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 13:59:57.550528
6245 13:59:57.553966 [CATrainingPosCal] consider 2 rank data
6246 13:59:57.556894 u2DelayCellTimex100 = 270/100 ps
6247 13:59:57.560671 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 13:59:57.563525 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 13:59:57.566957 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 13:59:57.570048 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 13:59:57.576999 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 13:59:57.580100 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 13:59:57.580179
6254 13:59:57.583784 CA PerBit enable=1, Macro0, CA PI delay=36
6255 13:59:57.583863
6256 13:59:57.586920 [CBTSetCACLKResult] CA Dly = 36
6257 13:59:57.586992 CS Dly: 1 (0~32)
6258 13:59:57.587052
6259 13:59:57.590032 ----->DramcWriteLeveling(PI) begin...
6260 13:59:57.590112 ==
6261 13:59:57.593813 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 13:59:57.600470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 13:59:57.600547 ==
6264 13:59:57.603783 Write leveling (Byte 0): 40 => 8
6265 13:59:57.603856 Write leveling (Byte 1): 40 => 8
6266 13:59:57.606938 DramcWriteLeveling(PI) end<-----
6267 13:59:57.607009
6268 13:59:57.607068 ==
6269 13:59:57.609951 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 13:59:57.617409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 13:59:57.617493 ==
6272 13:59:57.620402 [Gating] SW mode calibration
6273 13:59:57.626768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6274 13:59:57.630089 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6275 13:59:57.636763 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 13:59:57.640242 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 13:59:57.643284 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 13:59:57.649798 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 13:59:57.653225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 13:59:57.656533 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 13:59:57.663367 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 13:59:57.666414 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 13:59:57.670338 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 13:59:57.673397 Total UI for P1: 0, mck2ui 16
6285 13:59:57.676529 best dqsien dly found for B0: ( 0, 14, 24)
6286 13:59:57.679744 Total UI for P1: 0, mck2ui 16
6287 13:59:57.683149 best dqsien dly found for B1: ( 0, 14, 24)
6288 13:59:57.686503 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6289 13:59:57.689759 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6290 13:59:57.689839
6291 13:59:57.696046 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 13:59:57.699304 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 13:59:57.699382 [Gating] SW calibration Done
6294 13:59:57.703520 ==
6295 13:59:57.706273 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 13:59:57.710348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 13:59:57.710431 ==
6298 13:59:57.710495 RX Vref Scan: 0
6299 13:59:57.710562
6300 13:59:57.712897 RX Vref 0 -> 0, step: 1
6301 13:59:57.712964
6302 13:59:57.716073 RX Delay -410 -> 252, step: 16
6303 13:59:57.719133 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6304 13:59:57.725980 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6305 13:59:57.729654 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6306 13:59:57.732593 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6307 13:59:57.735894 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6308 13:59:57.739228 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6309 13:59:57.746093 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6310 13:59:57.748915 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6311 13:59:57.752770 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6312 13:59:57.755838 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6313 13:59:57.762327 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6314 13:59:57.765745 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6315 13:59:57.769165 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6316 13:59:57.775772 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6317 13:59:57.779151 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6318 13:59:57.782442 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6319 13:59:57.782515 ==
6320 13:59:57.785769 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 13:59:57.789229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 13:59:57.789302 ==
6323 13:59:57.792372 DQS Delay:
6324 13:59:57.792477 DQS0 = 27, DQS1 = 35
6325 13:59:57.795727 DQM Delay:
6326 13:59:57.795831 DQM0 = 10, DQM1 = 12
6327 13:59:57.799346 DQ Delay:
6328 13:59:57.799417 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6329 13:59:57.802680 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6330 13:59:57.805542 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6331 13:59:57.808977 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6332 13:59:57.809067
6333 13:59:57.809129
6334 13:59:57.809187 ==
6335 13:59:57.812596 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 13:59:57.819072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 13:59:57.819153 ==
6338 13:59:57.819215
6339 13:59:57.819274
6340 13:59:57.819331 TX Vref Scan disable
6341 13:59:57.822578 == TX Byte 0 ==
6342 13:59:57.826005 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 13:59:57.829200 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 13:59:57.832420 == TX Byte 1 ==
6345 13:59:57.835897 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 13:59:57.839281 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 13:59:57.839361 ==
6348 13:59:57.842248 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 13:59:57.849090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 13:59:57.849173 ==
6351 13:59:57.849244
6352 13:59:57.849304
6353 13:59:57.849360 TX Vref Scan disable
6354 13:59:57.852947 == TX Byte 0 ==
6355 13:59:57.855851 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 13:59:57.859261 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 13:59:57.862256 == TX Byte 1 ==
6358 13:59:57.865477 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 13:59:57.869157 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 13:59:57.869248
6361 13:59:57.872126 [DATLAT]
6362 13:59:57.872199 Freq=400, CH0 RK0
6363 13:59:57.872267
6364 13:59:57.875742 DATLAT Default: 0xf
6365 13:59:57.875815 0, 0xFFFF, sum = 0
6366 13:59:57.878937 1, 0xFFFF, sum = 0
6367 13:59:57.879019 2, 0xFFFF, sum = 0
6368 13:59:57.882150 3, 0xFFFF, sum = 0
6369 13:59:57.882230 4, 0xFFFF, sum = 0
6370 13:59:57.885783 5, 0xFFFF, sum = 0
6371 13:59:57.885865 6, 0xFFFF, sum = 0
6372 13:59:57.888924 7, 0xFFFF, sum = 0
6373 13:59:57.889005 8, 0xFFFF, sum = 0
6374 13:59:57.892297 9, 0xFFFF, sum = 0
6375 13:59:57.895330 10, 0xFFFF, sum = 0
6376 13:59:57.895412 11, 0xFFFF, sum = 0
6377 13:59:57.898834 12, 0xFFFF, sum = 0
6378 13:59:57.898909 13, 0x0, sum = 1
6379 13:59:57.902292 14, 0x0, sum = 2
6380 13:59:57.902382 15, 0x0, sum = 3
6381 13:59:57.902442 16, 0x0, sum = 4
6382 13:59:57.905610 best_step = 14
6383 13:59:57.905691
6384 13:59:57.905752 ==
6385 13:59:57.909059 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 13:59:57.912492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 13:59:57.912577 ==
6388 13:59:57.915827 RX Vref Scan: 1
6389 13:59:57.915913
6390 13:59:57.918885 RX Vref 0 -> 0, step: 1
6391 13:59:57.918967
6392 13:59:57.919030 RX Delay -311 -> 252, step: 8
6393 13:59:57.919090
6394 13:59:57.922111 Set Vref, RX VrefLevel [Byte0]: 56
6395 13:59:57.925162 [Byte1]: 46
6396 13:59:57.930729
6397 13:59:57.930811 Final RX Vref Byte 0 = 56 to rank0
6398 13:59:57.934147 Final RX Vref Byte 1 = 46 to rank0
6399 13:59:57.936992 Final RX Vref Byte 0 = 56 to rank1
6400 13:59:57.940381 Final RX Vref Byte 1 = 46 to rank1==
6401 13:59:57.943884 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 13:59:57.950041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 13:59:57.950118 ==
6404 13:59:57.950181 DQS Delay:
6405 13:59:57.953389 DQS0 = 28, DQS1 = 36
6406 13:59:57.953460 DQM Delay:
6407 13:59:57.953520 DQM0 = 10, DQM1 = 12
6408 13:59:57.957063 DQ Delay:
6409 13:59:57.960435 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6410 13:59:57.960518 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6411 13:59:57.963569 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6412 13:59:57.966959 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6413 13:59:57.967040
6414 13:59:57.970293
6415 13:59:57.976933 [DQSOSCAuto] RK0, (LSB)MR18= 0xd3c1, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 383 ps
6416 13:59:57.980246 CH0 RK0: MR19=C0C, MR18=D3C1
6417 13:59:57.986767 CH0_RK0: MR19=0xC0C, MR18=0xD3C1, DQSOSC=383, MR23=63, INC=402, DEC=268
6418 13:59:57.986850 ==
6419 13:59:57.990169 Dram Type= 6, Freq= 0, CH_0, rank 1
6420 13:59:57.993163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 13:59:57.993264 ==
6422 13:59:57.996628 [Gating] SW mode calibration
6423 13:59:58.003180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6424 13:59:58.010007 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6425 13:59:58.013503 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 13:59:58.016914 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 13:59:58.023253 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 13:59:58.026574 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 13:59:58.029896 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 13:59:58.036305 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 13:59:58.039559 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 13:59:58.043043 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 13:59:58.049601 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 13:59:58.049683 Total UI for P1: 0, mck2ui 16
6435 13:59:58.056525 best dqsien dly found for B0: ( 0, 14, 24)
6436 13:59:58.056611 Total UI for P1: 0, mck2ui 16
6437 13:59:58.059291 best dqsien dly found for B1: ( 0, 14, 24)
6438 13:59:58.066107 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6439 13:59:58.069761 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6440 13:59:58.069843
6441 13:59:58.072766 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 13:59:58.076697 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 13:59:58.079443 [Gating] SW calibration Done
6444 13:59:58.079569 ==
6445 13:59:58.082923 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 13:59:58.086047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 13:59:58.086129 ==
6448 13:59:58.089383 RX Vref Scan: 0
6449 13:59:58.089503
6450 13:59:58.089580 RX Vref 0 -> 0, step: 1
6451 13:59:58.089640
6452 13:59:58.092576 RX Delay -410 -> 252, step: 16
6453 13:59:58.096292 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6454 13:59:58.103178 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6455 13:59:58.106348 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6456 13:59:58.109674 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6457 13:59:58.112802 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6458 13:59:58.119403 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6459 13:59:58.122865 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6460 13:59:58.126347 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6461 13:59:58.129367 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6462 13:59:58.136061 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6463 13:59:58.139327 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6464 13:59:58.142831 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6465 13:59:58.146197 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6466 13:59:58.152907 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6467 13:59:58.156311 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6468 13:59:58.159319 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6469 13:59:58.159418 ==
6470 13:59:58.162396 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 13:59:58.169276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 13:59:58.169357 ==
6473 13:59:58.169421 DQS Delay:
6474 13:59:58.172654 DQS0 = 27, DQS1 = 35
6475 13:59:58.172734 DQM Delay:
6476 13:59:58.172797 DQM0 = 12, DQM1 = 12
6477 13:59:58.176096 DQ Delay:
6478 13:59:58.176176 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6479 13:59:58.179331 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6480 13:59:58.182513 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6481 13:59:58.185864 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6482 13:59:58.185945
6483 13:59:58.186033
6484 13:59:58.189438 ==
6485 13:59:58.192649 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 13:59:58.195908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 13:59:58.196014 ==
6488 13:59:58.196105
6489 13:59:58.196191
6490 13:59:58.199118 TX Vref Scan disable
6491 13:59:58.199224 == TX Byte 0 ==
6492 13:59:58.202424 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6493 13:59:58.209157 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6494 13:59:58.209238 == TX Byte 1 ==
6495 13:59:58.212494 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6496 13:59:58.219119 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6497 13:59:58.219200 ==
6498 13:59:58.222714 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 13:59:58.225783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 13:59:58.225864 ==
6501 13:59:58.225927
6502 13:59:58.225986
6503 13:59:58.228990 TX Vref Scan disable
6504 13:59:58.229070 == TX Byte 0 ==
6505 13:59:58.232423 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6506 13:59:58.239311 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6507 13:59:58.239417 == TX Byte 1 ==
6508 13:59:58.242159 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6509 13:59:58.249099 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6510 13:59:58.249180
6511 13:59:58.249243 [DATLAT]
6512 13:59:58.249302 Freq=400, CH0 RK1
6513 13:59:58.249372
6514 13:59:58.252204 DATLAT Default: 0xe
6515 13:59:58.252285 0, 0xFFFF, sum = 0
6516 13:59:58.255723 1, 0xFFFF, sum = 0
6517 13:59:58.255830 2, 0xFFFF, sum = 0
6518 13:59:58.259089 3, 0xFFFF, sum = 0
6519 13:59:58.262795 4, 0xFFFF, sum = 0
6520 13:59:58.262877 5, 0xFFFF, sum = 0
6521 13:59:58.266118 6, 0xFFFF, sum = 0
6522 13:59:58.266199 7, 0xFFFF, sum = 0
6523 13:59:58.269282 8, 0xFFFF, sum = 0
6524 13:59:58.269363 9, 0xFFFF, sum = 0
6525 13:59:58.272647 10, 0xFFFF, sum = 0
6526 13:59:58.272729 11, 0xFFFF, sum = 0
6527 13:59:58.275919 12, 0xFFFF, sum = 0
6528 13:59:58.276016 13, 0x0, sum = 1
6529 13:59:58.278823 14, 0x0, sum = 2
6530 13:59:58.278904 15, 0x0, sum = 3
6531 13:59:58.282200 16, 0x0, sum = 4
6532 13:59:58.282282 best_step = 14
6533 13:59:58.282344
6534 13:59:58.282431 ==
6535 13:59:58.285797 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 13:59:58.289047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 13:59:58.289128 ==
6538 13:59:58.292179 RX Vref Scan: 0
6539 13:59:58.292282
6540 13:59:58.295524 RX Vref 0 -> 0, step: 1
6541 13:59:58.295666
6542 13:59:58.295752 RX Delay -311 -> 252, step: 8
6543 13:59:58.304253 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6544 13:59:58.307831 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6545 13:59:58.310864 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6546 13:59:58.314403 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6547 13:59:58.321177 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6548 13:59:58.324393 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6549 13:59:58.327752 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6550 13:59:58.331333 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6551 13:59:58.337723 iDelay=217, Bit 8, Center -36 (-255 ~ 184) 440
6552 13:59:58.341267 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6553 13:59:58.344361 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6554 13:59:58.347855 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6555 13:59:58.354202 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6556 13:59:58.358129 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6557 13:59:58.361602 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6558 13:59:58.364180 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6559 13:59:58.367622 ==
6560 13:59:58.371075 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 13:59:58.374445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 13:59:58.374526 ==
6563 13:59:58.374589 DQS Delay:
6564 13:59:58.377699 DQS0 = 24, DQS1 = 36
6565 13:59:58.377780 DQM Delay:
6566 13:59:58.381110 DQM0 = 8, DQM1 = 12
6567 13:59:58.381190 DQ Delay:
6568 13:59:58.384466 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6569 13:59:58.387768 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6570 13:59:58.391141 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6571 13:59:58.394464 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6572 13:59:58.394545
6573 13:59:58.394624
6574 13:59:58.400730 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6575 13:59:58.404373 CH0 RK1: MR19=C0C, MR18=BE5C
6576 13:59:58.411005 CH0_RK1: MR19=0xC0C, MR18=0xBE5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6577 13:59:58.414523 [RxdqsGatingPostProcess] freq 400
6578 13:59:58.417607 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6579 13:59:58.420960 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 13:59:58.424338 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 13:59:58.427781 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 13:59:58.430938 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 13:59:58.434579 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 13:59:58.438045 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 13:59:58.441167 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 13:59:58.444492 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 13:59:58.447431 Pre-setting of DQS Precalculation
6588 13:59:58.450739 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6589 13:59:58.450821 ==
6590 13:59:58.454211 Dram Type= 6, Freq= 0, CH_1, rank 0
6591 13:59:58.461078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 13:59:58.461175 ==
6593 13:59:58.464063 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6594 13:59:58.470642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6595 13:59:58.473980 [CA 0] Center 36 (8~64) winsize 57
6596 13:59:58.477191 [CA 1] Center 36 (8~64) winsize 57
6597 13:59:58.480544 [CA 2] Center 36 (8~64) winsize 57
6598 13:59:58.483994 [CA 3] Center 36 (8~64) winsize 57
6599 13:59:58.487411 [CA 4] Center 36 (8~64) winsize 57
6600 13:59:58.491015 [CA 5] Center 36 (8~64) winsize 57
6601 13:59:58.491113
6602 13:59:58.493811 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6603 13:59:58.493885
6604 13:59:58.497183 [CATrainingPosCal] consider 1 rank data
6605 13:59:58.500679 u2DelayCellTimex100 = 270/100 ps
6606 13:59:58.503750 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 13:59:58.507178 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 13:59:58.510562 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 13:59:58.513857 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 13:59:58.517060 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 13:59:58.520353 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 13:59:58.523771
6613 13:59:58.527087 CA PerBit enable=1, Macro0, CA PI delay=36
6614 13:59:58.527167
6615 13:59:58.530413 [CBTSetCACLKResult] CA Dly = 36
6616 13:59:58.530493 CS Dly: 1 (0~32)
6617 13:59:58.530599 ==
6618 13:59:58.533738 Dram Type= 6, Freq= 0, CH_1, rank 1
6619 13:59:58.536985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 13:59:58.537066 ==
6621 13:59:58.544241 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 13:59:58.550486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6623 13:59:58.553806 [CA 0] Center 36 (8~64) winsize 57
6624 13:59:58.557294 [CA 1] Center 36 (8~64) winsize 57
6625 13:59:58.560894 [CA 2] Center 36 (8~64) winsize 57
6626 13:59:58.563725 [CA 3] Center 36 (8~64) winsize 57
6627 13:59:58.567496 [CA 4] Center 36 (8~64) winsize 57
6628 13:59:58.567625 [CA 5] Center 36 (8~64) winsize 57
6629 13:59:58.570790
6630 13:59:58.574147 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6631 13:59:58.574237
6632 13:59:58.577073 [CATrainingPosCal] consider 2 rank data
6633 13:59:58.580098 u2DelayCellTimex100 = 270/100 ps
6634 13:59:58.583835 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 13:59:58.586964 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 13:59:58.590301 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 13:59:58.593399 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 13:59:58.597020 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 13:59:58.600588 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 13:59:58.600669
6641 13:59:58.603514 CA PerBit enable=1, Macro0, CA PI delay=36
6642 13:59:58.603602
6643 13:59:58.607420 [CBTSetCACLKResult] CA Dly = 36
6644 13:59:58.610196 CS Dly: 1 (0~32)
6645 13:59:58.610310
6646 13:59:58.614003 ----->DramcWriteLeveling(PI) begin...
6647 13:59:58.614085 ==
6648 13:59:58.617246 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 13:59:58.620652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 13:59:58.620734 ==
6651 13:59:58.624008 Write leveling (Byte 0): 40 => 8
6652 13:59:58.627234 Write leveling (Byte 1): 40 => 8
6653 13:59:58.630792 DramcWriteLeveling(PI) end<-----
6654 13:59:58.630873
6655 13:59:58.630936 ==
6656 13:59:58.633730 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 13:59:58.637018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 13:59:58.637099 ==
6659 13:59:58.640503 [Gating] SW mode calibration
6660 13:59:58.646919 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6661 13:59:58.653612 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6662 13:59:58.657136 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 13:59:58.660787 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 13:59:58.666728 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 13:59:58.670297 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 13:59:58.673504 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 13:59:58.680711 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 13:59:58.683817 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 13:59:58.686958 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 13:59:58.693855 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 13:59:58.693963 Total UI for P1: 0, mck2ui 16
6672 13:59:58.700353 best dqsien dly found for B0: ( 0, 14, 24)
6673 13:59:58.700435 Total UI for P1: 0, mck2ui 16
6674 13:59:58.706426 best dqsien dly found for B1: ( 0, 14, 24)
6675 13:59:58.710052 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6676 13:59:58.713456 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6677 13:59:58.713540
6678 13:59:58.716579 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 13:59:58.719925 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 13:59:58.723199 [Gating] SW calibration Done
6681 13:59:58.723273 ==
6682 13:59:58.726967 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 13:59:58.730433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 13:59:58.730515 ==
6685 13:59:58.733468 RX Vref Scan: 0
6686 13:59:58.733565
6687 13:59:58.733643 RX Vref 0 -> 0, step: 1
6688 13:59:58.733736
6689 13:59:58.736271 RX Delay -410 -> 252, step: 16
6690 13:59:58.743163 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6691 13:59:58.746681 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6692 13:59:58.749690 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6693 13:59:58.753109 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6694 13:59:58.759946 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6695 13:59:58.763254 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6696 13:59:58.766462 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6697 13:59:58.770231 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6698 13:59:58.776679 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6699 13:59:58.780113 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6700 13:59:58.783136 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6701 13:59:58.786749 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6702 13:59:58.793214 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6703 13:59:58.796666 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6704 13:59:58.800089 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6705 13:59:58.803384 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6706 13:59:58.803465 ==
6707 13:59:58.806530 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 13:59:58.813277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 13:59:58.813359 ==
6710 13:59:58.813423 DQS Delay:
6711 13:59:58.816490 DQS0 = 35, DQS1 = 35
6712 13:59:58.816573 DQM Delay:
6713 13:59:58.819853 DQM0 = 18, DQM1 = 13
6714 13:59:58.819935 DQ Delay:
6715 13:59:58.823092 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6716 13:59:58.826704 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6717 13:59:58.830067 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6718 13:59:58.832986 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6719 13:59:58.833068
6720 13:59:58.833132
6721 13:59:58.833191 ==
6722 13:59:58.836469 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 13:59:58.839771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 13:59:58.839853 ==
6725 13:59:58.839917
6726 13:59:58.839977
6727 13:59:58.843104 TX Vref Scan disable
6728 13:59:58.843186 == TX Byte 0 ==
6729 13:59:58.849680 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 13:59:58.853220 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 13:59:58.853303 == TX Byte 1 ==
6732 13:59:58.859799 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 13:59:58.863022 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 13:59:58.863104 ==
6735 13:59:58.866380 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 13:59:58.869919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 13:59:58.870001 ==
6738 13:59:58.870065
6739 13:59:58.870125
6740 13:59:58.873358 TX Vref Scan disable
6741 13:59:58.873440 == TX Byte 0 ==
6742 13:59:58.879746 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 13:59:58.883103 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 13:59:58.883211 == TX Byte 1 ==
6745 13:59:58.889584 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 13:59:58.893123 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 13:59:58.893222
6748 13:59:58.893312 [DATLAT]
6749 13:59:58.896382 Freq=400, CH1 RK0
6750 13:59:58.896489
6751 13:59:58.896553 DATLAT Default: 0xf
6752 13:59:58.899765 0, 0xFFFF, sum = 0
6753 13:59:58.899852 1, 0xFFFF, sum = 0
6754 13:59:58.903097 2, 0xFFFF, sum = 0
6755 13:59:58.903216 3, 0xFFFF, sum = 0
6756 13:59:58.906293 4, 0xFFFF, sum = 0
6757 13:59:58.906376 5, 0xFFFF, sum = 0
6758 13:59:58.909614 6, 0xFFFF, sum = 0
6759 13:59:58.909697 7, 0xFFFF, sum = 0
6760 13:59:58.913460 8, 0xFFFF, sum = 0
6761 13:59:58.913543 9, 0xFFFF, sum = 0
6762 13:59:58.916346 10, 0xFFFF, sum = 0
6763 13:59:58.916428 11, 0xFFFF, sum = 0
6764 13:59:58.919744 12, 0xFFFF, sum = 0
6765 13:59:58.919827 13, 0x0, sum = 1
6766 13:59:58.923234 14, 0x0, sum = 2
6767 13:59:58.923316 15, 0x0, sum = 3
6768 13:59:58.926625 16, 0x0, sum = 4
6769 13:59:58.926708 best_step = 14
6770 13:59:58.926771
6771 13:59:58.926831 ==
6772 13:59:58.929914 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 13:59:58.936193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 13:59:58.936275 ==
6775 13:59:58.936339 RX Vref Scan: 1
6776 13:59:58.936398
6777 13:59:58.939881 RX Vref 0 -> 0, step: 1
6778 13:59:58.939962
6779 13:59:58.943090 RX Delay -311 -> 252, step: 8
6780 13:59:58.943171
6781 13:59:58.946360 Set Vref, RX VrefLevel [Byte0]: 54
6782 13:59:58.949499 [Byte1]: 51
6783 13:59:58.949597
6784 13:59:58.952821 Final RX Vref Byte 0 = 54 to rank0
6785 13:59:58.956348 Final RX Vref Byte 1 = 51 to rank0
6786 13:59:58.959660 Final RX Vref Byte 0 = 54 to rank1
6787 13:59:58.963121 Final RX Vref Byte 1 = 51 to rank1==
6788 13:59:58.966430 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 13:59:58.969590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 13:59:58.969687 ==
6791 13:59:58.973093 DQS Delay:
6792 13:59:58.973191 DQS0 = 28, DQS1 = 32
6793 13:59:58.976646 DQM Delay:
6794 13:59:58.976729 DQM0 = 9, DQM1 = 10
6795 13:59:58.979914 DQ Delay:
6796 13:59:58.979996 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6797 13:59:58.983107 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6798 13:59:58.986422 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6799 13:59:58.989523 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6800 13:59:58.989604
6801 13:59:58.989668
6802 13:59:58.999667 [DQSOSCAuto] RK0, (LSB)MR18= 0x99d2, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6803 13:59:58.999750 CH1 RK0: MR19=C0C, MR18=99D2
6804 13:59:59.006318 CH1_RK0: MR19=0xC0C, MR18=0x99D2, DQSOSC=383, MR23=63, INC=402, DEC=268
6805 13:59:59.009844 ==
6806 13:59:59.009926 Dram Type= 6, Freq= 0, CH_1, rank 1
6807 13:59:59.016299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 13:59:59.016381 ==
6809 13:59:59.019290 [Gating] SW mode calibration
6810 13:59:59.025855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6811 13:59:59.029161 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6812 13:59:59.035960 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 13:59:59.039396 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 13:59:59.042620 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 13:59:59.048944 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 13:59:59.052324 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 13:59:59.055684 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 13:59:59.062310 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 13:59:59.066127 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 13:59:59.069456 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 13:59:59.072951 Total UI for P1: 0, mck2ui 16
6822 13:59:59.075966 best dqsien dly found for B0: ( 0, 14, 24)
6823 13:59:59.079764 Total UI for P1: 0, mck2ui 16
6824 13:59:59.082640 best dqsien dly found for B1: ( 0, 14, 24)
6825 13:59:59.085963 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6826 13:59:59.088962 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6827 13:59:59.089043
6828 13:59:59.095754 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 13:59:59.098987 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 13:59:59.099068 [Gating] SW calibration Done
6831 13:59:59.102563 ==
6832 13:59:59.102643 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 13:59:59.109332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 13:59:59.109413 ==
6835 13:59:59.109507 RX Vref Scan: 0
6836 13:59:59.109566
6837 13:59:59.112647 RX Vref 0 -> 0, step: 1
6838 13:59:59.112789
6839 13:59:59.115707 RX Delay -410 -> 252, step: 16
6840 13:59:59.118889 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6841 13:59:59.122489 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6842 13:59:59.129015 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6843 13:59:59.132281 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6844 13:59:59.135450 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6845 13:59:59.138922 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6846 13:59:59.145625 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6847 13:59:59.149238 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6848 13:59:59.152563 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6849 13:59:59.155868 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6850 13:59:59.162111 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6851 13:59:59.165529 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6852 13:59:59.169579 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6853 13:59:59.172395 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6854 13:59:59.179370 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6855 13:59:59.182071 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6856 13:59:59.182170 ==
6857 13:59:59.185506 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 13:59:59.189173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 13:59:59.189255 ==
6860 13:59:59.192564 DQS Delay:
6861 13:59:59.192645 DQS0 = 35, DQS1 = 35
6862 13:59:59.195373 DQM Delay:
6863 13:59:59.195454 DQM0 = 18, DQM1 = 15
6864 13:59:59.195518 DQ Delay:
6865 13:59:59.198757 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6866 13:59:59.202099 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6867 13:59:59.205370 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6868 13:59:59.209028 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6869 13:59:59.209109
6870 13:59:59.209172
6871 13:59:59.209231 ==
6872 13:59:59.212498 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 13:59:59.218846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 13:59:59.218928 ==
6875 13:59:59.218992
6876 13:59:59.219050
6877 13:59:59.219107 TX Vref Scan disable
6878 13:59:59.222520 == TX Byte 0 ==
6879 13:59:59.225345 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6880 13:59:59.228648 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6881 13:59:59.232100 == TX Byte 1 ==
6882 13:59:59.235475 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6883 13:59:59.238910 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6884 13:59:59.238992 ==
6885 13:59:59.242372 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 13:59:59.248715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 13:59:59.248797 ==
6888 13:59:59.248860
6889 13:59:59.248920
6890 13:59:59.248976 TX Vref Scan disable
6891 13:59:59.252127 == TX Byte 0 ==
6892 13:59:59.255772 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6893 13:59:59.258702 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6894 13:59:59.262028 == TX Byte 1 ==
6895 13:59:59.265542 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6896 13:59:59.268916 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6897 13:59:59.268998
6898 13:59:59.272610 [DATLAT]
6899 13:59:59.272691 Freq=400, CH1 RK1
6900 13:59:59.272756
6901 13:59:59.275498 DATLAT Default: 0xe
6902 13:59:59.275579 0, 0xFFFF, sum = 0
6903 13:59:59.278738 1, 0xFFFF, sum = 0
6904 13:59:59.278820 2, 0xFFFF, sum = 0
6905 13:59:59.282105 3, 0xFFFF, sum = 0
6906 13:59:59.282188 4, 0xFFFF, sum = 0
6907 13:59:59.285589 5, 0xFFFF, sum = 0
6908 13:59:59.285672 6, 0xFFFF, sum = 0
6909 13:59:59.288762 7, 0xFFFF, sum = 0
6910 13:59:59.288845 8, 0xFFFF, sum = 0
6911 13:59:59.292401 9, 0xFFFF, sum = 0
6912 13:59:59.292484 10, 0xFFFF, sum = 0
6913 13:59:59.295490 11, 0xFFFF, sum = 0
6914 13:59:59.295573 12, 0xFFFF, sum = 0
6915 13:59:59.298972 13, 0x0, sum = 1
6916 13:59:59.299055 14, 0x0, sum = 2
6917 13:59:59.302251 15, 0x0, sum = 3
6918 13:59:59.302333 16, 0x0, sum = 4
6919 13:59:59.305846 best_step = 14
6920 13:59:59.305927
6921 13:59:59.305991 ==
6922 13:59:59.309096 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 13:59:59.312146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 13:59:59.312228 ==
6925 13:59:59.315395 RX Vref Scan: 0
6926 13:59:59.315476
6927 13:59:59.315540 RX Vref 0 -> 0, step: 1
6928 13:59:59.315623
6929 13:59:59.318832 RX Delay -311 -> 252, step: 8
6930 13:59:59.326678 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6931 13:59:59.330289 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6932 13:59:59.333275 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6933 13:59:59.336744 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6934 13:59:59.343698 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6935 13:59:59.347487 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6936 13:59:59.350343 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6937 13:59:59.353381 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6938 13:59:59.360271 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6939 13:59:59.363317 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6940 13:59:59.366923 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6941 13:59:59.370415 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6942 13:59:59.376608 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6943 13:59:59.380197 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6944 13:59:59.383534 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6945 13:59:59.386985 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6946 13:59:59.390091 ==
6947 13:59:59.393309 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 13:59:59.396627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 13:59:59.396735 ==
6950 13:59:59.396827 DQS Delay:
6951 13:59:59.399903 DQS0 = 28, DQS1 = 36
6952 13:59:59.399985 DQM Delay:
6953 13:59:59.403487 DQM0 = 11, DQM1 = 15
6954 13:59:59.403568 DQ Delay:
6955 13:59:59.406778 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6956 13:59:59.409628 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6957 13:59:59.413043 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6958 13:59:59.416512 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6959 13:59:59.416594
6960 13:59:59.416658
6961 13:59:59.423081 [DQSOSCAuto] RK1, (LSB)MR18= 0xc859, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6962 13:59:59.426482 CH1 RK1: MR19=C0C, MR18=C859
6963 13:59:59.433315 CH1_RK1: MR19=0xC0C, MR18=0xC859, DQSOSC=385, MR23=63, INC=398, DEC=265
6964 13:59:59.436655 [RxdqsGatingPostProcess] freq 400
6965 13:59:59.440165 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6966 13:59:59.443248 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 13:59:59.446707 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 13:59:59.449844 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 13:59:59.453314 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 13:59:59.456661 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 13:59:59.460026 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 13:59:59.463762 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 13:59:59.466271 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 13:59:59.469804 Pre-setting of DQS Precalculation
6975 13:59:59.473197 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6976 13:59:59.482928 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6977 13:59:59.490406 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6978 13:59:59.490489
6979 13:59:59.490553
6980 13:59:59.492768 [Calibration Summary] 800 Mbps
6981 13:59:59.492849 CH 0, Rank 0
6982 13:59:59.496208 SW Impedance : PASS
6983 13:59:59.496289 DUTY Scan : NO K
6984 13:59:59.499476 ZQ Calibration : PASS
6985 13:59:59.503116 Jitter Meter : NO K
6986 13:59:59.503197 CBT Training : PASS
6987 13:59:59.506076 Write leveling : PASS
6988 13:59:59.509349 RX DQS gating : PASS
6989 13:59:59.509441 RX DQ/DQS(RDDQC) : PASS
6990 13:59:59.513162 TX DQ/DQS : PASS
6991 13:59:59.516326 RX DATLAT : PASS
6992 13:59:59.516407 RX DQ/DQS(Engine): PASS
6993 13:59:59.520423 TX OE : NO K
6994 13:59:59.520507 All Pass.
6995 13:59:59.520572
6996 13:59:59.522920 CH 0, Rank 1
6997 13:59:59.523000 SW Impedance : PASS
6998 13:59:59.526296 DUTY Scan : NO K
6999 13:59:59.526378 ZQ Calibration : PASS
7000 13:59:59.530096 Jitter Meter : NO K
7001 13:59:59.533355 CBT Training : PASS
7002 13:59:59.533437 Write leveling : NO K
7003 13:59:59.536528 RX DQS gating : PASS
7004 13:59:59.539873 RX DQ/DQS(RDDQC) : PASS
7005 13:59:59.539953 TX DQ/DQS : PASS
7006 13:59:59.543272 RX DATLAT : PASS
7007 13:59:59.546182 RX DQ/DQS(Engine): PASS
7008 13:59:59.546263 TX OE : NO K
7009 13:59:59.549657 All Pass.
7010 13:59:59.549738
7011 13:59:59.549802 CH 1, Rank 0
7012 13:59:59.552709 SW Impedance : PASS
7013 13:59:59.552790 DUTY Scan : NO K
7014 13:59:59.556009 ZQ Calibration : PASS
7015 13:59:59.560127 Jitter Meter : NO K
7016 13:59:59.560208 CBT Training : PASS
7017 13:59:59.562789 Write leveling : PASS
7018 13:59:59.566227 RX DQS gating : PASS
7019 13:59:59.566349 RX DQ/DQS(RDDQC) : PASS
7020 13:59:59.569672 TX DQ/DQS : PASS
7021 13:59:59.569754 RX DATLAT : PASS
7022 13:59:59.573116 RX DQ/DQS(Engine): PASS
7023 13:59:59.576123 TX OE : NO K
7024 13:59:59.576205 All Pass.
7025 13:59:59.576268
7026 13:59:59.576327 CH 1, Rank 1
7027 13:59:59.579366 SW Impedance : PASS
7028 13:59:59.582675 DUTY Scan : NO K
7029 13:59:59.582757 ZQ Calibration : PASS
7030 13:59:59.586132 Jitter Meter : NO K
7031 13:59:59.589745 CBT Training : PASS
7032 13:59:59.589826 Write leveling : NO K
7033 13:59:59.592617 RX DQS gating : PASS
7034 13:59:59.596208 RX DQ/DQS(RDDQC) : PASS
7035 13:59:59.596289 TX DQ/DQS : PASS
7036 13:59:59.599588 RX DATLAT : PASS
7037 13:59:59.603117 RX DQ/DQS(Engine): PASS
7038 13:59:59.603198 TX OE : NO K
7039 13:59:59.603262 All Pass.
7040 13:59:59.603337
7041 13:59:59.606101 DramC Write-DBI off
7042 13:59:59.609856 PER_BANK_REFRESH: Hybrid Mode
7043 13:59:59.609937 TX_TRACKING: ON
7044 13:59:59.619793 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7045 13:59:59.622963 [FAST_K] Save calibration result to emmc
7046 13:59:59.626110 dramc_set_vcore_voltage set vcore to 725000
7047 13:59:59.629745 Read voltage for 1600, 0
7048 13:59:59.629831 Vio18 = 0
7049 13:59:59.632592 Vcore = 725000
7050 13:59:59.632672 Vdram = 0
7051 13:59:59.632737 Vddq = 0
7052 13:59:59.632796 Vmddr = 0
7053 13:59:59.639455 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7054 13:59:59.646138 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7055 13:59:59.646220 MEM_TYPE=3, freq_sel=13
7056 13:59:59.649626 sv_algorithm_assistance_LP4_3733
7057 13:59:59.652592 ============ PULL DRAM RESETB DOWN ============
7058 13:59:59.659553 ========== PULL DRAM RESETB DOWN end =========
7059 13:59:59.662987 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7060 13:59:59.666216 ===================================
7061 13:59:59.669555 LPDDR4 DRAM CONFIGURATION
7062 13:59:59.672823 ===================================
7063 13:59:59.672904 EX_ROW_EN[0] = 0x0
7064 13:59:59.676287 EX_ROW_EN[1] = 0x0
7065 13:59:59.676368 LP4Y_EN = 0x0
7066 13:59:59.679239 WORK_FSP = 0x1
7067 13:59:59.679320 WL = 0x5
7068 13:59:59.682542 RL = 0x5
7069 13:59:59.682623 BL = 0x2
7070 13:59:59.686052 RPST = 0x0
7071 13:59:59.689287 RD_PRE = 0x0
7072 13:59:59.689368 WR_PRE = 0x1
7073 13:59:59.692705 WR_PST = 0x1
7074 13:59:59.692803 DBI_WR = 0x0
7075 13:59:59.696125 DBI_RD = 0x0
7076 13:59:59.696206 OTF = 0x1
7077 13:59:59.699221 ===================================
7078 13:59:59.703153 ===================================
7079 13:59:59.706101 ANA top config
7080 13:59:59.709451 ===================================
7081 13:59:59.709533 DLL_ASYNC_EN = 0
7082 13:59:59.712267 ALL_SLAVE_EN = 0
7083 13:59:59.715615 NEW_RANK_MODE = 1
7084 13:59:59.719086 DLL_IDLE_MODE = 1
7085 13:59:59.719170 LP45_APHY_COMB_EN = 1
7086 13:59:59.722367 TX_ODT_DIS = 0
7087 13:59:59.725866 NEW_8X_MODE = 1
7088 13:59:59.729335 ===================================
7089 13:59:59.732730 ===================================
7090 13:59:59.735846 data_rate = 3200
7091 13:59:59.739221 CKR = 1
7092 13:59:59.742375 DQ_P2S_RATIO = 8
7093 13:59:59.742461 ===================================
7094 13:59:59.746202 CA_P2S_RATIO = 8
7095 13:59:59.749384 DQ_CA_OPEN = 0
7096 13:59:59.752896 DQ_SEMI_OPEN = 0
7097 13:59:59.756149 CA_SEMI_OPEN = 0
7098 13:59:59.759370 CA_FULL_RATE = 0
7099 13:59:59.759452 DQ_CKDIV4_EN = 0
7100 13:59:59.762626 CA_CKDIV4_EN = 0
7101 13:59:59.765597 CA_PREDIV_EN = 0
7102 13:59:59.768676 PH8_DLY = 12
7103 13:59:59.772341 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7104 13:59:59.775569 DQ_AAMCK_DIV = 4
7105 13:59:59.775693 CA_AAMCK_DIV = 4
7106 13:59:59.779027 CA_ADMCK_DIV = 4
7107 13:59:59.782462 DQ_TRACK_CA_EN = 0
7108 13:59:59.785836 CA_PICK = 1600
7109 13:59:59.788863 CA_MCKIO = 1600
7110 13:59:59.792532 MCKIO_SEMI = 0
7111 13:59:59.795899 PLL_FREQ = 3068
7112 13:59:59.798872 DQ_UI_PI_RATIO = 32
7113 13:59:59.798954 CA_UI_PI_RATIO = 0
7114 13:59:59.802138 ===================================
7115 13:59:59.805726 ===================================
7116 13:59:59.809040 memory_type:LPDDR4
7117 13:59:59.812435 GP_NUM : 10
7118 13:59:59.812520 SRAM_EN : 1
7119 13:59:59.815679 MD32_EN : 0
7120 13:59:59.819010 ===================================
7121 13:59:59.822360 [ANA_INIT] >>>>>>>>>>>>>>
7122 13:59:59.822442 <<<<<< [CONFIGURE PHASE]: ANA_TX
7123 13:59:59.828753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7124 13:59:59.828836 ===================================
7125 13:59:59.832658 data_rate = 3200,PCW = 0X7600
7126 13:59:59.835316 ===================================
7127 13:59:59.839144 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7128 13:59:59.845523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 13:59:59.852134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 13:59:59.855201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7131 13:59:59.858999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7132 13:59:59.862218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7133 13:59:59.865684 [ANA_INIT] flow start
7134 13:59:59.865766 [ANA_INIT] PLL >>>>>>>>
7135 13:59:59.869084 [ANA_INIT] PLL <<<<<<<<
7136 13:59:59.872590 [ANA_INIT] MIDPI >>>>>>>>
7137 13:59:59.875386 [ANA_INIT] MIDPI <<<<<<<<
7138 13:59:59.875467 [ANA_INIT] DLL >>>>>>>>
7139 13:59:59.879294 [ANA_INIT] DLL <<<<<<<<
7140 13:59:59.879376 [ANA_INIT] flow end
7141 13:59:59.885333 ============ LP4 DIFF to SE enter ============
7142 13:59:59.889150 ============ LP4 DIFF to SE exit ============
7143 13:59:59.892026 [ANA_INIT] <<<<<<<<<<<<<
7144 13:59:59.895077 [Flow] Enable top DCM control >>>>>
7145 13:59:59.898383 [Flow] Enable top DCM control <<<<<
7146 13:59:59.898483 Enable DLL master slave shuffle
7147 13:59:59.905564 ==============================================================
7148 13:59:59.908727 Gating Mode config
7149 13:59:59.912210 ==============================================================
7150 13:59:59.915494 Config description:
7151 13:59:59.925524 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7152 13:59:59.931941 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7153 13:59:59.935264 SELPH_MODE 0: By rank 1: By Phase
7154 13:59:59.942005 ==============================================================
7155 13:59:59.944863 GAT_TRACK_EN = 1
7156 13:59:59.948334 RX_GATING_MODE = 2
7157 13:59:59.951833 RX_GATING_TRACK_MODE = 2
7158 13:59:59.955005 SELPH_MODE = 1
7159 13:59:59.955087 PICG_EARLY_EN = 1
7160 13:59:59.958430 VALID_LAT_VALUE = 1
7161 13:59:59.965163 ==============================================================
7162 13:59:59.968303 Enter into Gating configuration >>>>
7163 13:59:59.971417 Exit from Gating configuration <<<<
7164 13:59:59.974788 Enter into DVFS_PRE_config >>>>>
7165 13:59:59.984897 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7166 13:59:59.988578 Exit from DVFS_PRE_config <<<<<
7167 13:59:59.991607 Enter into PICG configuration >>>>
7168 13:59:59.994770 Exit from PICG configuration <<<<
7169 13:59:59.998267 [RX_INPUT] configuration >>>>>
7170 14:00:00.001573 [RX_INPUT] configuration <<<<<
7171 14:00:00.004968 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7172 14:00:00.011616 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7173 14:00:00.018520 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 14:00:00.025272 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 14:00:00.032143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 14:00:00.034826 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 14:00:00.041399 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7178 14:00:00.044713 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7179 14:00:00.048136 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7180 14:00:00.051690 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7181 14:00:00.058629 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7182 14:00:00.061460 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7183 14:00:00.064847 ===================================
7184 14:00:00.067877 LPDDR4 DRAM CONFIGURATION
7185 14:00:00.071133 ===================================
7186 14:00:00.071251 EX_ROW_EN[0] = 0x0
7187 14:00:00.074679 EX_ROW_EN[1] = 0x0
7188 14:00:00.074761 LP4Y_EN = 0x0
7189 14:00:00.077755 WORK_FSP = 0x1
7190 14:00:00.077853 WL = 0x5
7191 14:00:00.081454 RL = 0x5
7192 14:00:00.081536 BL = 0x2
7193 14:00:00.084598 RPST = 0x0
7194 14:00:00.084681 RD_PRE = 0x0
7195 14:00:00.088201 WR_PRE = 0x1
7196 14:00:00.088283 WR_PST = 0x1
7197 14:00:00.091386 DBI_WR = 0x0
7198 14:00:00.094748 DBI_RD = 0x0
7199 14:00:00.094830 OTF = 0x1
7200 14:00:00.098325 ===================================
7201 14:00:00.101501 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7202 14:00:00.104416 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7203 14:00:00.111222 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 14:00:00.114751 ===================================
7205 14:00:00.114855 LPDDR4 DRAM CONFIGURATION
7206 14:00:00.117955 ===================================
7207 14:00:00.121846 EX_ROW_EN[0] = 0x10
7208 14:00:00.124771 EX_ROW_EN[1] = 0x0
7209 14:00:00.124852 LP4Y_EN = 0x0
7210 14:00:00.127745 WORK_FSP = 0x1
7211 14:00:00.127827 WL = 0x5
7212 14:00:00.131147 RL = 0x5
7213 14:00:00.131229 BL = 0x2
7214 14:00:00.134498 RPST = 0x0
7215 14:00:00.134580 RD_PRE = 0x0
7216 14:00:00.138173 WR_PRE = 0x1
7217 14:00:00.138256 WR_PST = 0x1
7218 14:00:00.141583 DBI_WR = 0x0
7219 14:00:00.141666 DBI_RD = 0x0
7220 14:00:00.144801 OTF = 0x1
7221 14:00:00.148089 ===================================
7222 14:00:00.154285 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7223 14:00:00.154368 ==
7224 14:00:00.157935 Dram Type= 6, Freq= 0, CH_0, rank 0
7225 14:00:00.161298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7226 14:00:00.161382 ==
7227 14:00:00.164718 [Duty_Offset_Calibration]
7228 14:00:00.164804 B0:2 B1:1 CA:1
7229 14:00:00.164868
7230 14:00:00.167513 [DutyScan_Calibration_Flow] k_type=0
7231 14:00:00.178610
7232 14:00:00.178692 ==CLK 0==
7233 14:00:00.181790 Final CLK duty delay cell = 0
7234 14:00:00.185208 [0] MAX Duty = 5156%(X100), DQS PI = 22
7235 14:00:00.188916 [0] MIN Duty = 4907%(X100), DQS PI = 0
7236 14:00:00.188999 [0] AVG Duty = 5031%(X100)
7237 14:00:00.191832
7238 14:00:00.191914 CH0 CLK Duty spec in!! Max-Min= 249%
7239 14:00:00.198549 [DutyScan_Calibration_Flow] ====Done====
7240 14:00:00.198632
7241 14:00:00.202146 [DutyScan_Calibration_Flow] k_type=1
7242 14:00:00.217207
7243 14:00:00.217289 ==DQS 0 ==
7244 14:00:00.220711 Final DQS duty delay cell = -4
7245 14:00:00.223824 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7246 14:00:00.227484 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7247 14:00:00.230535 [-4] AVG Duty = 4906%(X100)
7248 14:00:00.230617
7249 14:00:00.230682 ==DQS 1 ==
7250 14:00:00.233551 Final DQS duty delay cell = -4
7251 14:00:00.237101 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7252 14:00:00.240755 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7253 14:00:00.243756 [-4] AVG Duty = 4891%(X100)
7254 14:00:00.243838
7255 14:00:00.247456 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7256 14:00:00.247563
7257 14:00:00.250567 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7258 14:00:00.253669 [DutyScan_Calibration_Flow] ====Done====
7259 14:00:00.253751
7260 14:00:00.256987 [DutyScan_Calibration_Flow] k_type=3
7261 14:00:00.274249
7262 14:00:00.274332 ==DQM 0 ==
7263 14:00:00.277514 Final DQM duty delay cell = 0
7264 14:00:00.280896 [0] MAX Duty = 5218%(X100), DQS PI = 34
7265 14:00:00.283807 [0] MIN Duty = 4907%(X100), DQS PI = 54
7266 14:00:00.287561 [0] AVG Duty = 5062%(X100)
7267 14:00:00.287692
7268 14:00:00.287757 ==DQM 1 ==
7269 14:00:00.290567 Final DQM duty delay cell = -4
7270 14:00:00.293921 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7271 14:00:00.297323 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7272 14:00:00.300392 [-4] AVG Duty = 4906%(X100)
7273 14:00:00.300473
7274 14:00:00.303909 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7275 14:00:00.303993
7276 14:00:00.307357 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7277 14:00:00.310770 [DutyScan_Calibration_Flow] ====Done====
7278 14:00:00.310851
7279 14:00:00.314101 [DutyScan_Calibration_Flow] k_type=2
7280 14:00:00.331681
7281 14:00:00.331775 ==DQ 0 ==
7282 14:00:00.335071 Final DQ duty delay cell = 0
7283 14:00:00.338801 [0] MAX Duty = 5062%(X100), DQS PI = 24
7284 14:00:00.341742 [0] MIN Duty = 4907%(X100), DQS PI = 0
7285 14:00:00.341824 [0] AVG Duty = 4984%(X100)
7286 14:00:00.341888
7287 14:00:00.345051 ==DQ 1 ==
7288 14:00:00.348383 Final DQ duty delay cell = 0
7289 14:00:00.351813 [0] MAX Duty = 5125%(X100), DQS PI = 6
7290 14:00:00.355460 [0] MIN Duty = 4907%(X100), DQS PI = 34
7291 14:00:00.355545 [0] AVG Duty = 5016%(X100)
7292 14:00:00.355651
7293 14:00:00.358607 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7294 14:00:00.358689
7295 14:00:00.361650 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7296 14:00:00.368338 [DutyScan_Calibration_Flow] ====Done====
7297 14:00:00.368420 ==
7298 14:00:00.371469 Dram Type= 6, Freq= 0, CH_1, rank 0
7299 14:00:00.374740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 14:00:00.374822 ==
7301 14:00:00.378377 [Duty_Offset_Calibration]
7302 14:00:00.378458 B0:1 B1:0 CA:0
7303 14:00:00.378521
7304 14:00:00.381643 [DutyScan_Calibration_Flow] k_type=0
7305 14:00:00.390645
7306 14:00:00.390726 ==CLK 0==
7307 14:00:00.394281 Final CLK duty delay cell = -4
7308 14:00:00.397697 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7309 14:00:00.400793 [-4] MIN Duty = 4875%(X100), DQS PI = 2
7310 14:00:00.404634 [-4] AVG Duty = 4937%(X100)
7311 14:00:00.404753
7312 14:00:00.407580 CH1 CLK Duty spec in!! Max-Min= 125%
7313 14:00:00.411223 [DutyScan_Calibration_Flow] ====Done====
7314 14:00:00.411303
7315 14:00:00.414415 [DutyScan_Calibration_Flow] k_type=1
7316 14:00:00.430798
7317 14:00:00.430878 ==DQS 0 ==
7318 14:00:00.434230 Final DQS duty delay cell = 0
7319 14:00:00.437669 [0] MAX Duty = 5094%(X100), DQS PI = 22
7320 14:00:00.440646 [0] MIN Duty = 4875%(X100), DQS PI = 0
7321 14:00:00.440727 [0] AVG Duty = 4984%(X100)
7322 14:00:00.444003
7323 14:00:00.444083 ==DQS 1 ==
7324 14:00:00.448015 Final DQS duty delay cell = 0
7325 14:00:00.450630 [0] MAX Duty = 5249%(X100), DQS PI = 16
7326 14:00:00.454474 [0] MIN Duty = 4938%(X100), DQS PI = 8
7327 14:00:00.454555 [0] AVG Duty = 5093%(X100)
7328 14:00:00.457565
7329 14:00:00.460833 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7330 14:00:00.460913
7331 14:00:00.464008 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7332 14:00:00.467447 [DutyScan_Calibration_Flow] ====Done====
7333 14:00:00.467543
7334 14:00:00.470879 [DutyScan_Calibration_Flow] k_type=3
7335 14:00:00.487750
7336 14:00:00.487830 ==DQM 0 ==
7337 14:00:00.491281 Final DQM duty delay cell = 0
7338 14:00:00.494377 [0] MAX Duty = 5218%(X100), DQS PI = 18
7339 14:00:00.497284 [0] MIN Duty = 4969%(X100), DQS PI = 48
7340 14:00:00.500897 [0] AVG Duty = 5093%(X100)
7341 14:00:00.500978
7342 14:00:00.501042 ==DQM 1 ==
7343 14:00:00.504369 Final DQM duty delay cell = 0
7344 14:00:00.508068 [0] MAX Duty = 5062%(X100), DQS PI = 14
7345 14:00:00.510864 [0] MIN Duty = 4907%(X100), DQS PI = 34
7346 14:00:00.514229 [0] AVG Duty = 4984%(X100)
7347 14:00:00.514309
7348 14:00:00.517693 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7349 14:00:00.517774
7350 14:00:00.521341 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7351 14:00:00.524585 [DutyScan_Calibration_Flow] ====Done====
7352 14:00:00.524665
7353 14:00:00.528004 [DutyScan_Calibration_Flow] k_type=2
7354 14:00:00.543885
7355 14:00:00.543966 ==DQ 0 ==
7356 14:00:00.547464 Final DQ duty delay cell = -4
7357 14:00:00.550634 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7358 14:00:00.553708 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7359 14:00:00.557613 [-4] AVG Duty = 4968%(X100)
7360 14:00:00.557693
7361 14:00:00.557755 ==DQ 1 ==
7362 14:00:00.560329 Final DQ duty delay cell = 0
7363 14:00:00.563623 [0] MAX Duty = 5125%(X100), DQS PI = 18
7364 14:00:00.567148 [0] MIN Duty = 4938%(X100), DQS PI = 10
7365 14:00:00.570499 [0] AVG Duty = 5031%(X100)
7366 14:00:00.570580
7367 14:00:00.573714 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7368 14:00:00.573796
7369 14:00:00.576637 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7370 14:00:00.580191 [DutyScan_Calibration_Flow] ====Done====
7371 14:00:00.583542 nWR fixed to 30
7372 14:00:00.586921 [ModeRegInit_LP4] CH0 RK0
7373 14:00:00.587003 [ModeRegInit_LP4] CH0 RK1
7374 14:00:00.590109 [ModeRegInit_LP4] CH1 RK0
7375 14:00:00.593849 [ModeRegInit_LP4] CH1 RK1
7376 14:00:00.593931 match AC timing 5
7377 14:00:00.600571 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7378 14:00:00.603342 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7379 14:00:00.606683 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7380 14:00:00.613410 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7381 14:00:00.616821 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7382 14:00:00.616904 [MiockJmeterHQA]
7383 14:00:00.616969
7384 14:00:00.620118 [DramcMiockJmeter] u1RxGatingPI = 0
7385 14:00:00.623729 0 : 4253, 4027
7386 14:00:00.623815 4 : 4253, 4026
7387 14:00:00.626711 8 : 4363, 4137
7388 14:00:00.626794 12 : 4363, 4137
7389 14:00:00.626859 16 : 4363, 4138
7390 14:00:00.629870 20 : 4253, 4026
7391 14:00:00.629953 24 : 4252, 4027
7392 14:00:00.633453 28 : 4252, 4027
7393 14:00:00.633535 32 : 4253, 4026
7394 14:00:00.636777 36 : 4255, 4030
7395 14:00:00.636860 40 : 4363, 4137
7396 14:00:00.640109 44 : 4252, 4027
7397 14:00:00.640194 48 : 4253, 4026
7398 14:00:00.640259 52 : 4253, 4026
7399 14:00:00.643195 56 : 4254, 4029
7400 14:00:00.643277 60 : 4253, 4026
7401 14:00:00.646589 64 : 4361, 4137
7402 14:00:00.646671 68 : 4361, 4138
7403 14:00:00.649869 72 : 4250, 4026
7404 14:00:00.649953 76 : 4250, 4027
7405 14:00:00.650017 80 : 4250, 4027
7406 14:00:00.653709 84 : 4250, 4026
7407 14:00:00.653792 88 : 4252, 103
7408 14:00:00.656747 92 : 4250, 0
7409 14:00:00.656829 96 : 4250, 0
7410 14:00:00.656894 100 : 4250, 0
7411 14:00:00.660321 104 : 4252, 0
7412 14:00:00.660404 108 : 4250, 0
7413 14:00:00.663400 112 : 4250, 0
7414 14:00:00.663482 116 : 4252, 0
7415 14:00:00.663548 120 : 4361, 0
7416 14:00:00.666888 124 : 4360, 0
7417 14:00:00.666970 128 : 4364, 0
7418 14:00:00.669997 132 : 4250, 0
7419 14:00:00.670080 136 : 4360, 0
7420 14:00:00.670145 140 : 4250, 0
7421 14:00:00.673313 144 : 4250, 0
7422 14:00:00.673395 148 : 4250, 0
7423 14:00:00.676512 152 : 4250, 0
7424 14:00:00.676595 156 : 4252, 0
7425 14:00:00.676660 160 : 4250, 0
7426 14:00:00.679982 164 : 4250, 0
7427 14:00:00.680065 168 : 4252, 0
7428 14:00:00.683250 172 : 4361, 0
7429 14:00:00.683332 176 : 4250, 0
7430 14:00:00.683397 180 : 4361, 0
7431 14:00:00.686952 184 : 4250, 0
7432 14:00:00.687035 188 : 4250, 0
7433 14:00:00.687100 192 : 4250, 0
7434 14:00:00.689919 196 : 4253, 0
7435 14:00:00.690002 200 : 4250, 0
7436 14:00:00.693440 204 : 4249, 1369
7437 14:00:00.693523 208 : 4250, 3994
7438 14:00:00.696844 212 : 4361, 4137
7439 14:00:00.696926 216 : 4250, 4027
7440 14:00:00.700030 220 : 4360, 4138
7441 14:00:00.700113 224 : 4360, 4137
7442 14:00:00.700177 228 : 4253, 4026
7443 14:00:00.703281 232 : 4252, 4027
7444 14:00:00.703367 236 : 4363, 4140
7445 14:00:00.706445 240 : 4250, 4027
7446 14:00:00.706528 244 : 4250, 4026
7447 14:00:00.709819 248 : 4250, 4027
7448 14:00:00.709902 252 : 4252, 4030
7449 14:00:00.712974 256 : 4250, 4027
7450 14:00:00.713056 260 : 4250, 4026
7451 14:00:00.716507 264 : 4361, 4137
7452 14:00:00.716622 268 : 4250, 4027
7453 14:00:00.720158 272 : 4250, 4027
7454 14:00:00.720241 276 : 4360, 4137
7455 14:00:00.722867 280 : 4250, 4026
7456 14:00:00.722949 284 : 4250, 4027
7457 14:00:00.726174 288 : 4363, 4140
7458 14:00:00.726257 292 : 4250, 4027
7459 14:00:00.726322 296 : 4250, 4026
7460 14:00:00.729623 300 : 4250, 4027
7461 14:00:00.729706 304 : 4252, 4030
7462 14:00:00.733062 308 : 4249, 3973
7463 14:00:00.733145 312 : 4250, 2051
7464 14:00:00.733209
7465 14:00:00.736290 MIOCK jitter meter ch=0
7466 14:00:00.736372
7467 14:00:00.739571 1T = (312-88) = 224 dly cells
7468 14:00:00.746620 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7469 14:00:00.746742 ==
7470 14:00:00.749774 Dram Type= 6, Freq= 0, CH_0, rank 0
7471 14:00:00.753201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7472 14:00:00.753282 ==
7473 14:00:00.759508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7474 14:00:00.762964 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7475 14:00:00.766059 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7476 14:00:00.772843 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7477 14:00:00.781729 [CA 0] Center 42 (12~73) winsize 62
7478 14:00:00.784622 [CA 1] Center 42 (12~73) winsize 62
7479 14:00:00.788245 [CA 2] Center 38 (8~68) winsize 61
7480 14:00:00.791385 [CA 3] Center 37 (8~67) winsize 60
7481 14:00:00.794655 [CA 4] Center 36 (6~66) winsize 61
7482 14:00:00.798042 [CA 5] Center 35 (6~64) winsize 59
7483 14:00:00.798124
7484 14:00:00.801787 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7485 14:00:00.801869
7486 14:00:00.804910 [CATrainingPosCal] consider 1 rank data
7487 14:00:00.807979 u2DelayCellTimex100 = 290/100 ps
7488 14:00:00.811132 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7489 14:00:00.817958 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7490 14:00:00.821322 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7491 14:00:00.824595 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7492 14:00:00.828191 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7493 14:00:00.831283 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7494 14:00:00.831390
7495 14:00:00.834429 CA PerBit enable=1, Macro0, CA PI delay=35
7496 14:00:00.834511
7497 14:00:00.838208 [CBTSetCACLKResult] CA Dly = 35
7498 14:00:00.841222 CS Dly: 8 (0~39)
7499 14:00:00.845123 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7500 14:00:00.848000 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7501 14:00:00.848082 ==
7502 14:00:00.851436 Dram Type= 6, Freq= 0, CH_0, rank 1
7503 14:00:00.855134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 14:00:00.855262 ==
7505 14:00:00.861230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 14:00:00.864608 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 14:00:00.870850 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 14:00:00.874732 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 14:00:00.885214 [CA 0] Center 42 (12~73) winsize 62
7510 14:00:00.888450 [CA 1] Center 42 (12~73) winsize 62
7511 14:00:00.891718 [CA 2] Center 37 (8~67) winsize 60
7512 14:00:00.894697 [CA 3] Center 37 (7~68) winsize 62
7513 14:00:00.898196 [CA 4] Center 35 (5~65) winsize 61
7514 14:00:00.901776 [CA 5] Center 35 (5~65) winsize 61
7515 14:00:00.901858
7516 14:00:00.904792 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7517 14:00:00.904873
7518 14:00:00.908104 [CATrainingPosCal] consider 2 rank data
7519 14:00:00.911306 u2DelayCellTimex100 = 290/100 ps
7520 14:00:00.914569 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7521 14:00:00.921516 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7522 14:00:00.924790 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7523 14:00:00.927861 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7524 14:00:00.931098 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7525 14:00:00.934573 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7526 14:00:00.934654
7527 14:00:00.938041 CA PerBit enable=1, Macro0, CA PI delay=35
7528 14:00:00.938123
7529 14:00:00.941634 [CBTSetCACLKResult] CA Dly = 35
7530 14:00:00.941716 CS Dly: 9 (0~42)
7531 14:00:00.947892 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 14:00:00.951671 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 14:00:00.951769
7534 14:00:00.954871 ----->DramcWriteLeveling(PI) begin...
7535 14:00:00.954954 ==
7536 14:00:00.957759 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 14:00:00.961465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 14:00:00.964528 ==
7539 14:00:00.964609 Write leveling (Byte 0): 35 => 35
7540 14:00:00.968009 Write leveling (Byte 1): 28 => 28
7541 14:00:00.971116 DramcWriteLeveling(PI) end<-----
7542 14:00:00.971215
7543 14:00:00.971294 ==
7544 14:00:00.974747 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 14:00:00.980950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 14:00:00.981032 ==
7547 14:00:00.981096 [Gating] SW mode calibration
7548 14:00:00.991236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7549 14:00:00.994347 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7550 14:00:01.001041 1 4 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7551 14:00:01.004434 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7552 14:00:01.007858 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7553 14:00:01.010726 1 4 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7554 14:00:01.017998 1 4 16 | B1->B0 | 2424 3737 | 0 1 | (0 0) (0 0)
7555 14:00:01.020835 1 4 20 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7556 14:00:01.024170 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7557 14:00:01.031390 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 14:00:01.034200 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7559 14:00:01.038324 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7560 14:00:01.044648 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 1)
7561 14:00:01.047691 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7562 14:00:01.050732 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
7563 14:00:01.057156 1 5 20 | B1->B0 | 2828 2c2b | 0 1 | (1 0) (0 0)
7564 14:00:01.060697 1 5 24 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7565 14:00:01.064183 1 5 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7566 14:00:01.070524 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7567 14:00:01.073808 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7568 14:00:01.077153 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7569 14:00:01.083809 1 6 12 | B1->B0 | 2323 4646 | 0 1 | (0 0) (0 0)
7570 14:00:01.087262 1 6 16 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
7571 14:00:01.090665 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7572 14:00:01.097481 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 14:00:01.100414 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 14:00:01.104115 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 14:00:01.110893 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 14:00:01.113770 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 14:00:01.117340 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 14:00:01.123742 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7579 14:00:01.126880 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7580 14:00:01.130841 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 14:00:01.137415 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 14:00:01.140298 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 14:00:01.144191 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 14:00:01.150226 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 14:00:01.153594 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 14:00:01.156988 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 14:00:01.160497 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 14:00:01.167362 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 14:00:01.170090 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 14:00:01.173455 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 14:00:01.180476 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 14:00:01.183801 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7593 14:00:01.186968 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 14:00:01.193823 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7595 14:00:01.197347 Total UI for P1: 0, mck2ui 16
7596 14:00:01.199971 best dqsien dly found for B0: ( 1, 9, 10)
7597 14:00:01.203664 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 14:00:01.206722 Total UI for P1: 0, mck2ui 16
7599 14:00:01.210506 best dqsien dly found for B1: ( 1, 9, 16)
7600 14:00:01.213477 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7601 14:00:01.216979 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7602 14:00:01.217085
7603 14:00:01.220541 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7604 14:00:01.224078 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7605 14:00:01.226780 [Gating] SW calibration Done
7606 14:00:01.226861 ==
7607 14:00:01.230193 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 14:00:01.236892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 14:00:01.236973 ==
7610 14:00:01.237038 RX Vref Scan: 0
7611 14:00:01.237149
7612 14:00:01.240204 RX Vref 0 -> 0, step: 1
7613 14:00:01.240286
7614 14:00:01.243527 RX Delay 0 -> 252, step: 8
7615 14:00:01.246724 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7616 14:00:01.250403 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7617 14:00:01.253493 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7618 14:00:01.257031 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7619 14:00:01.263367 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7620 14:00:01.266657 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7621 14:00:01.270298 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7622 14:00:01.273419 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7623 14:00:01.276750 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7624 14:00:01.280441 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7625 14:00:01.287106 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7626 14:00:01.290316 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7627 14:00:01.293727 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7628 14:00:01.297077 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7629 14:00:01.300423 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7630 14:00:01.306525 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7631 14:00:01.306608 ==
7632 14:00:01.309861 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 14:00:01.313270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 14:00:01.313378 ==
7635 14:00:01.313475 DQS Delay:
7636 14:00:01.316681 DQS0 = 0, DQS1 = 0
7637 14:00:01.316763 DQM Delay:
7638 14:00:01.319932 DQM0 = 136, DQM1 = 129
7639 14:00:01.320014 DQ Delay:
7640 14:00:01.323420 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7641 14:00:01.327056 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7642 14:00:01.329855 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7643 14:00:01.333420 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7644 14:00:01.337019
7645 14:00:01.337101
7646 14:00:01.337166 ==
7647 14:00:01.340178 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 14:00:01.343054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 14:00:01.343137 ==
7650 14:00:01.343202
7651 14:00:01.343279
7652 14:00:01.346647 TX Vref Scan disable
7653 14:00:01.346730 == TX Byte 0 ==
7654 14:00:01.352968 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7655 14:00:01.356564 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7656 14:00:01.356648 == TX Byte 1 ==
7657 14:00:01.363040 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7658 14:00:01.366345 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7659 14:00:01.366428 ==
7660 14:00:01.369546 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 14:00:01.372986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 14:00:01.373069 ==
7663 14:00:01.386068
7664 14:00:01.389248 TX Vref early break, caculate TX vref
7665 14:00:01.393046 TX Vref=16, minBit 7, minWin=22, winSum=380
7666 14:00:01.396249 TX Vref=18, minBit 4, minWin=23, winSum=387
7667 14:00:01.399938 TX Vref=20, minBit 1, minWin=24, winSum=397
7668 14:00:01.402739 TX Vref=22, minBit 7, minWin=24, winSum=412
7669 14:00:01.406394 TX Vref=24, minBit 7, minWin=24, winSum=416
7670 14:00:01.409418 TX Vref=26, minBit 6, minWin=25, winSum=424
7671 14:00:01.416217 TX Vref=28, minBit 6, minWin=25, winSum=422
7672 14:00:01.419641 TX Vref=30, minBit 2, minWin=24, winSum=409
7673 14:00:01.422988 TX Vref=32, minBit 6, minWin=23, winSum=398
7674 14:00:01.429466 [TxChooseVref] Worse bit 6, Min win 25, Win sum 424, Final Vref 26
7675 14:00:01.429566
7676 14:00:01.432646 Final TX Range 0 Vref 26
7677 14:00:01.432729
7678 14:00:01.432793 ==
7679 14:00:01.436111 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 14:00:01.439693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 14:00:01.439776 ==
7682 14:00:01.439840
7683 14:00:01.439900
7684 14:00:01.442674 TX Vref Scan disable
7685 14:00:01.446401 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7686 14:00:01.449479 == TX Byte 0 ==
7687 14:00:01.452679 u2DelayCellOfst[0]=10 cells (3 PI)
7688 14:00:01.456012 u2DelayCellOfst[1]=13 cells (4 PI)
7689 14:00:01.459223 u2DelayCellOfst[2]=10 cells (3 PI)
7690 14:00:01.463080 u2DelayCellOfst[3]=10 cells (3 PI)
7691 14:00:01.463163 u2DelayCellOfst[4]=6 cells (2 PI)
7692 14:00:01.466175 u2DelayCellOfst[5]=0 cells (0 PI)
7693 14:00:01.469276 u2DelayCellOfst[6]=16 cells (5 PI)
7694 14:00:01.472813 u2DelayCellOfst[7]=16 cells (5 PI)
7695 14:00:01.479494 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7696 14:00:01.482516 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7697 14:00:01.482599 == TX Byte 1 ==
7698 14:00:01.486019 u2DelayCellOfst[8]=3 cells (1 PI)
7699 14:00:01.489118 u2DelayCellOfst[9]=0 cells (0 PI)
7700 14:00:01.492481 u2DelayCellOfst[10]=10 cells (3 PI)
7701 14:00:01.495755 u2DelayCellOfst[11]=3 cells (1 PI)
7702 14:00:01.499279 u2DelayCellOfst[12]=13 cells (4 PI)
7703 14:00:01.502535 u2DelayCellOfst[13]=13 cells (4 PI)
7704 14:00:01.506229 u2DelayCellOfst[14]=16 cells (5 PI)
7705 14:00:01.509415 u2DelayCellOfst[15]=13 cells (4 PI)
7706 14:00:01.512652 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7707 14:00:01.516123 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7708 14:00:01.519427 DramC Write-DBI on
7709 14:00:01.519534 ==
7710 14:00:01.522572 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 14:00:01.525946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 14:00:01.526029 ==
7713 14:00:01.526094
7714 14:00:01.526154
7715 14:00:01.529229 TX Vref Scan disable
7716 14:00:01.532607 == TX Byte 0 ==
7717 14:00:01.535801 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7718 14:00:01.535883 == TX Byte 1 ==
7719 14:00:01.542780 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7720 14:00:01.542862 DramC Write-DBI off
7721 14:00:01.542927
7722 14:00:01.546224 [DATLAT]
7723 14:00:01.546305 Freq=1600, CH0 RK0
7724 14:00:01.546370
7725 14:00:01.549033 DATLAT Default: 0xf
7726 14:00:01.549130 0, 0xFFFF, sum = 0
7727 14:00:01.552563 1, 0xFFFF, sum = 0
7728 14:00:01.552639 2, 0xFFFF, sum = 0
7729 14:00:01.556219 3, 0xFFFF, sum = 0
7730 14:00:01.556293 4, 0xFFFF, sum = 0
7731 14:00:01.559307 5, 0xFFFF, sum = 0
7732 14:00:01.559379 6, 0xFFFF, sum = 0
7733 14:00:01.562435 7, 0xFFFF, sum = 0
7734 14:00:01.562509 8, 0xFFFF, sum = 0
7735 14:00:01.565871 9, 0xFFFF, sum = 0
7736 14:00:01.565944 10, 0xFFFF, sum = 0
7737 14:00:01.569201 11, 0xFFFF, sum = 0
7738 14:00:01.572370 12, 0xFFFF, sum = 0
7739 14:00:01.572446 13, 0xFFFF, sum = 0
7740 14:00:01.575746 14, 0x0, sum = 1
7741 14:00:01.575818 15, 0x0, sum = 2
7742 14:00:01.575878 16, 0x0, sum = 3
7743 14:00:01.579048 17, 0x0, sum = 4
7744 14:00:01.579117 best_step = 15
7745 14:00:01.579181
7746 14:00:01.582631 ==
7747 14:00:01.582708 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 14:00:01.589001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 14:00:01.589074 ==
7750 14:00:01.589134 RX Vref Scan: 1
7751 14:00:01.589199
7752 14:00:01.592999 Set Vref Range= 24 -> 127
7753 14:00:01.593066
7754 14:00:01.595635 RX Vref 24 -> 127, step: 1
7755 14:00:01.595707
7756 14:00:01.599236 RX Delay 19 -> 252, step: 4
7757 14:00:01.599305
7758 14:00:01.602405 Set Vref, RX VrefLevel [Byte0]: 24
7759 14:00:01.605566 [Byte1]: 24
7760 14:00:01.605634
7761 14:00:01.608946 Set Vref, RX VrefLevel [Byte0]: 25
7762 14:00:01.612422 [Byte1]: 25
7763 14:00:01.612493
7764 14:00:01.615805 Set Vref, RX VrefLevel [Byte0]: 26
7765 14:00:01.619129 [Byte1]: 26
7766 14:00:01.619200
7767 14:00:01.622578 Set Vref, RX VrefLevel [Byte0]: 27
7768 14:00:01.625512 [Byte1]: 27
7769 14:00:01.629869
7770 14:00:01.629946 Set Vref, RX VrefLevel [Byte0]: 28
7771 14:00:01.633544 [Byte1]: 28
7772 14:00:01.637249
7773 14:00:01.637331 Set Vref, RX VrefLevel [Byte0]: 29
7774 14:00:01.640227 [Byte1]: 29
7775 14:00:01.644938
7776 14:00:01.645013 Set Vref, RX VrefLevel [Byte0]: 30
7777 14:00:01.648092 [Byte1]: 30
7778 14:00:01.652208
7779 14:00:01.652291 Set Vref, RX VrefLevel [Byte0]: 31
7780 14:00:01.655898 [Byte1]: 31
7781 14:00:01.659946
7782 14:00:01.660020 Set Vref, RX VrefLevel [Byte0]: 32
7783 14:00:01.663407 [Byte1]: 32
7784 14:00:01.667709
7785 14:00:01.667782 Set Vref, RX VrefLevel [Byte0]: 33
7786 14:00:01.670815 [Byte1]: 33
7787 14:00:01.675084
7788 14:00:01.675166 Set Vref, RX VrefLevel [Byte0]: 34
7789 14:00:01.678243 [Byte1]: 34
7790 14:00:01.682871
7791 14:00:01.682952 Set Vref, RX VrefLevel [Byte0]: 35
7792 14:00:01.685734 [Byte1]: 35
7793 14:00:01.690375
7794 14:00:01.690451 Set Vref, RX VrefLevel [Byte0]: 36
7795 14:00:01.693861 [Byte1]: 36
7796 14:00:01.698190
7797 14:00:01.698260 Set Vref, RX VrefLevel [Byte0]: 37
7798 14:00:01.701276 [Byte1]: 37
7799 14:00:01.705408
7800 14:00:01.705481 Set Vref, RX VrefLevel [Byte0]: 38
7801 14:00:01.708818 [Byte1]: 38
7802 14:00:01.712881
7803 14:00:01.712957 Set Vref, RX VrefLevel [Byte0]: 39
7804 14:00:01.716050 [Byte1]: 39
7805 14:00:01.720506
7806 14:00:01.720577 Set Vref, RX VrefLevel [Byte0]: 40
7807 14:00:01.723763 [Byte1]: 40
7808 14:00:01.727843
7809 14:00:01.727919 Set Vref, RX VrefLevel [Byte0]: 41
7810 14:00:01.731285 [Byte1]: 41
7811 14:00:01.735732
7812 14:00:01.735809 Set Vref, RX VrefLevel [Byte0]: 42
7813 14:00:01.738808 [Byte1]: 42
7814 14:00:01.743306
7815 14:00:01.743376 Set Vref, RX VrefLevel [Byte0]: 43
7816 14:00:01.746600 [Byte1]: 43
7817 14:00:01.750654
7818 14:00:01.750732 Set Vref, RX VrefLevel [Byte0]: 44
7819 14:00:01.754018 [Byte1]: 44
7820 14:00:01.758249
7821 14:00:01.758341 Set Vref, RX VrefLevel [Byte0]: 45
7822 14:00:01.761628 [Byte1]: 45
7823 14:00:01.766054
7824 14:00:01.766124 Set Vref, RX VrefLevel [Byte0]: 46
7825 14:00:01.769415 [Byte1]: 46
7826 14:00:01.773827
7827 14:00:01.773904 Set Vref, RX VrefLevel [Byte0]: 47
7828 14:00:01.776807 [Byte1]: 47
7829 14:00:01.781310
7830 14:00:01.781386 Set Vref, RX VrefLevel [Byte0]: 48
7831 14:00:01.784235 [Byte1]: 48
7832 14:00:01.788908
7833 14:00:01.788980 Set Vref, RX VrefLevel [Byte0]: 49
7834 14:00:01.792260 [Byte1]: 49
7835 14:00:01.796466
7836 14:00:01.796542 Set Vref, RX VrefLevel [Byte0]: 50
7837 14:00:01.799778 [Byte1]: 50
7838 14:00:01.803972
7839 14:00:01.804044 Set Vref, RX VrefLevel [Byte0]: 51
7840 14:00:01.807216 [Byte1]: 51
7841 14:00:01.811214
7842 14:00:01.811310 Set Vref, RX VrefLevel [Byte0]: 52
7843 14:00:01.814672 [Byte1]: 52
7844 14:00:01.818996
7845 14:00:01.819077 Set Vref, RX VrefLevel [Byte0]: 53
7846 14:00:01.822590 [Byte1]: 53
7847 14:00:01.826368
7848 14:00:01.826482 Set Vref, RX VrefLevel [Byte0]: 54
7849 14:00:01.829713 [Byte1]: 54
7850 14:00:01.834505
7851 14:00:01.834587 Set Vref, RX VrefLevel [Byte0]: 55
7852 14:00:01.837158 [Byte1]: 55
7853 14:00:01.841815
7854 14:00:01.841896 Set Vref, RX VrefLevel [Byte0]: 56
7855 14:00:01.844939 [Byte1]: 56
7856 14:00:01.849348
7857 14:00:01.849430 Set Vref, RX VrefLevel [Byte0]: 57
7858 14:00:01.852608 [Byte1]: 57
7859 14:00:01.856757
7860 14:00:01.856838 Set Vref, RX VrefLevel [Byte0]: 58
7861 14:00:01.860184 [Byte1]: 58
7862 14:00:01.864179
7863 14:00:01.864261 Set Vref, RX VrefLevel [Byte0]: 59
7864 14:00:01.867742 [Byte1]: 59
7865 14:00:01.872011
7866 14:00:01.872093 Set Vref, RX VrefLevel [Byte0]: 60
7867 14:00:01.875541 [Byte1]: 60
7868 14:00:01.879863
7869 14:00:01.879971 Set Vref, RX VrefLevel [Byte0]: 61
7870 14:00:01.882842 [Byte1]: 61
7871 14:00:01.887391
7872 14:00:01.887472 Set Vref, RX VrefLevel [Byte0]: 62
7873 14:00:01.890758 [Byte1]: 62
7874 14:00:01.894836
7875 14:00:01.894917 Set Vref, RX VrefLevel [Byte0]: 63
7876 14:00:01.898285 [Byte1]: 63
7877 14:00:01.902206
7878 14:00:01.902287 Set Vref, RX VrefLevel [Byte0]: 64
7879 14:00:01.905518 [Byte1]: 64
7880 14:00:01.909910
7881 14:00:01.909993 Set Vref, RX VrefLevel [Byte0]: 65
7882 14:00:01.913280 [Byte1]: 65
7883 14:00:01.917291
7884 14:00:01.917373 Set Vref, RX VrefLevel [Byte0]: 66
7885 14:00:01.920879 [Byte1]: 66
7886 14:00:01.925117
7887 14:00:01.925199 Set Vref, RX VrefLevel [Byte0]: 67
7888 14:00:01.928405 [Byte1]: 67
7889 14:00:01.932733
7890 14:00:01.932833 Set Vref, RX VrefLevel [Byte0]: 68
7891 14:00:01.935919 [Byte1]: 68
7892 14:00:01.939949
7893 14:00:01.940031 Set Vref, RX VrefLevel [Byte0]: 69
7894 14:00:01.943270 [Byte1]: 69
7895 14:00:01.947833
7896 14:00:01.947915 Set Vref, RX VrefLevel [Byte0]: 70
7897 14:00:01.951069 [Byte1]: 70
7898 14:00:01.955266
7899 14:00:01.955348 Set Vref, RX VrefLevel [Byte0]: 71
7900 14:00:01.958498 [Byte1]: 71
7901 14:00:01.962959
7902 14:00:01.963040 Set Vref, RX VrefLevel [Byte0]: 72
7903 14:00:01.966246 [Byte1]: 72
7904 14:00:01.970319
7905 14:00:01.970393 Set Vref, RX VrefLevel [Byte0]: 73
7906 14:00:01.973831 [Byte1]: 73
7907 14:00:01.977719
7908 14:00:01.977796 Set Vref, RX VrefLevel [Byte0]: 74
7909 14:00:01.981070 [Byte1]: 74
7910 14:00:01.985557
7911 14:00:01.985631 Final RX Vref Byte 0 = 59 to rank0
7912 14:00:01.988719 Final RX Vref Byte 1 = 59 to rank0
7913 14:00:01.992302 Final RX Vref Byte 0 = 59 to rank1
7914 14:00:01.995207 Final RX Vref Byte 1 = 59 to rank1==
7915 14:00:01.998537 Dram Type= 6, Freq= 0, CH_0, rank 0
7916 14:00:02.005271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7917 14:00:02.005351 ==
7918 14:00:02.005414 DQS Delay:
7919 14:00:02.005474 DQS0 = 0, DQS1 = 0
7920 14:00:02.009146 DQM Delay:
7921 14:00:02.009221 DQM0 = 134, DQM1 = 127
7922 14:00:02.012101 DQ Delay:
7923 14:00:02.015629 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7924 14:00:02.018457 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7925 14:00:02.021934 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7926 14:00:02.025084 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7927 14:00:02.025153
7928 14:00:02.025213
7929 14:00:02.025275
7930 14:00:02.028430 [DramC_TX_OE_Calibration] TA2
7931 14:00:02.031712 Original DQ_B0 (3 6) =30, OEN = 27
7932 14:00:02.035419 Original DQ_B1 (3 6) =30, OEN = 27
7933 14:00:02.038695 24, 0x0, End_B0=24 End_B1=24
7934 14:00:02.038772 25, 0x0, End_B0=25 End_B1=25
7935 14:00:02.041980 26, 0x0, End_B0=26 End_B1=26
7936 14:00:02.045358 27, 0x0, End_B0=27 End_B1=27
7937 14:00:02.048873 28, 0x0, End_B0=28 End_B1=28
7938 14:00:02.052213 29, 0x0, End_B0=29 End_B1=29
7939 14:00:02.052296 30, 0x0, End_B0=30 End_B1=30
7940 14:00:02.055717 31, 0x4141, End_B0=30 End_B1=30
7941 14:00:02.058617 Byte0 end_step=30 best_step=27
7942 14:00:02.061775 Byte1 end_step=30 best_step=27
7943 14:00:02.064999 Byte0 TX OE(2T, 0.5T) = (3, 3)
7944 14:00:02.065070 Byte1 TX OE(2T, 0.5T) = (3, 3)
7945 14:00:02.068617
7946 14:00:02.068693
7947 14:00:02.075439 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
7948 14:00:02.078486 CH0 RK0: MR19=303, MR18=2824
7949 14:00:02.085286 CH0_RK0: MR19=0x303, MR18=0x2824, DQSOSC=389, MR23=63, INC=24, DEC=16
7950 14:00:02.085374
7951 14:00:02.088194 ----->DramcWriteLeveling(PI) begin...
7952 14:00:02.088263 ==
7953 14:00:02.091678 Dram Type= 6, Freq= 0, CH_0, rank 1
7954 14:00:02.094808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 14:00:02.094876 ==
7956 14:00:02.098541 Write leveling (Byte 0): 35 => 35
7957 14:00:02.101421 Write leveling (Byte 1): 26 => 26
7958 14:00:02.104877 DramcWriteLeveling(PI) end<-----
7959 14:00:02.104948
7960 14:00:02.105043 ==
7961 14:00:02.108406 Dram Type= 6, Freq= 0, CH_0, rank 1
7962 14:00:02.111362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7963 14:00:02.111430 ==
7964 14:00:02.115115 [Gating] SW mode calibration
7965 14:00:02.121397 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7966 14:00:02.128240 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7967 14:00:02.131633 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 14:00:02.134854 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7969 14:00:02.141744 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7970 14:00:02.145064 1 4 12 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7971 14:00:02.148719 1 4 16 | B1->B0 | 2e2e 3434 | 1 0 | (1 1) (0 0)
7972 14:00:02.154900 1 4 20 | B1->B0 | 3434 3939 | 1 0 | (1 1) (0 0)
7973 14:00:02.158673 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7974 14:00:02.161821 1 4 28 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7975 14:00:02.168357 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7976 14:00:02.171576 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7977 14:00:02.175215 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 1)
7978 14:00:02.181621 1 5 12 | B1->B0 | 3434 3534 | 1 1 | (1 0) (0 0)
7979 14:00:02.184504 1 5 16 | B1->B0 | 2e2e 2c2c | 0 0 | (1 0) (0 0)
7980 14:00:02.188253 1 5 20 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
7981 14:00:02.195271 1 5 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7982 14:00:02.198506 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7983 14:00:02.201560 1 6 0 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7984 14:00:02.207855 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7985 14:00:02.211373 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7986 14:00:02.214753 1 6 12 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
7987 14:00:02.221115 1 6 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7988 14:00:02.224914 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7989 14:00:02.227998 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7990 14:00:02.234791 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 14:00:02.238027 1 7 0 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7992 14:00:02.241471 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 14:00:02.245122 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 14:00:02.251564 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7995 14:00:02.254787 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7996 14:00:02.258032 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 14:00:02.264565 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 14:00:02.267826 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 14:00:02.271775 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 14:00:02.277950 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 14:00:02.281362 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 14:00:02.284787 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 14:00:02.291679 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 14:00:02.294771 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 14:00:02.298328 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 14:00:02.304856 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 14:00:02.307946 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 14:00:02.311580 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 14:00:02.318081 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8010 14:00:02.320982 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8011 14:00:02.324304 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8012 14:00:02.327871 Total UI for P1: 0, mck2ui 16
8013 14:00:02.330915 best dqsien dly found for B0: ( 1, 9, 10)
8014 14:00:02.337742 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 14:00:02.337823 Total UI for P1: 0, mck2ui 16
8016 14:00:02.341078 best dqsien dly found for B1: ( 1, 9, 14)
8017 14:00:02.347890 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8018 14:00:02.351208 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8019 14:00:02.351289
8020 14:00:02.354469 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8021 14:00:02.357818 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8022 14:00:02.361290 [Gating] SW calibration Done
8023 14:00:02.361372 ==
8024 14:00:02.364376 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 14:00:02.367817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 14:00:02.367899 ==
8027 14:00:02.371052 RX Vref Scan: 0
8028 14:00:02.371133
8029 14:00:02.371236 RX Vref 0 -> 0, step: 1
8030 14:00:02.371296
8031 14:00:02.374375 RX Delay 0 -> 252, step: 8
8032 14:00:02.377976 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8033 14:00:02.380954 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8034 14:00:02.387943 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8035 14:00:02.391288 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8036 14:00:02.394491 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8037 14:00:02.397992 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8038 14:00:02.401295 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8039 14:00:02.407678 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8040 14:00:02.411175 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8041 14:00:02.414922 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8042 14:00:02.417766 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8043 14:00:02.421012 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8044 14:00:02.427570 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8045 14:00:02.430983 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8046 14:00:02.434244 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8047 14:00:02.437748 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8048 14:00:02.437830 ==
8049 14:00:02.441242 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 14:00:02.447532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 14:00:02.447639 ==
8052 14:00:02.447706 DQS Delay:
8053 14:00:02.450937 DQS0 = 0, DQS1 = 0
8054 14:00:02.451020 DQM Delay:
8055 14:00:02.454254 DQM0 = 137, DQM1 = 128
8056 14:00:02.454336 DQ Delay:
8057 14:00:02.458309 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8058 14:00:02.460757 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8059 14:00:02.464190 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8060 14:00:02.467466 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8061 14:00:02.467550
8062 14:00:02.467639
8063 14:00:02.467700 ==
8064 14:00:02.471049 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 14:00:02.477408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 14:00:02.477491 ==
8067 14:00:02.477555
8068 14:00:02.477615
8069 14:00:02.477673 TX Vref Scan disable
8070 14:00:02.481155 == TX Byte 0 ==
8071 14:00:02.484016 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8072 14:00:02.487735 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8073 14:00:02.490711 == TX Byte 1 ==
8074 14:00:02.493983 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8075 14:00:02.497871 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8076 14:00:02.500862 ==
8077 14:00:02.500963 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 14:00:02.507474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 14:00:02.507602 ==
8080 14:00:02.521194
8081 14:00:02.523882 TX Vref early break, caculate TX vref
8082 14:00:02.527089 TX Vref=16, minBit 1, minWin=23, winSum=386
8083 14:00:02.530578 TX Vref=18, minBit 0, minWin=24, winSum=394
8084 14:00:02.533872 TX Vref=20, minBit 0, minWin=24, winSum=401
8085 14:00:02.537407 TX Vref=22, minBit 1, minWin=24, winSum=412
8086 14:00:02.540996 TX Vref=24, minBit 1, minWin=25, winSum=418
8087 14:00:02.547277 TX Vref=26, minBit 1, minWin=25, winSum=423
8088 14:00:02.550498 TX Vref=28, minBit 1, minWin=25, winSum=418
8089 14:00:02.554363 TX Vref=30, minBit 0, minWin=25, winSum=412
8090 14:00:02.557352 TX Vref=32, minBit 0, minWin=25, winSum=406
8091 14:00:02.560934 TX Vref=34, minBit 0, minWin=23, winSum=397
8092 14:00:02.567618 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 26
8093 14:00:02.567734
8094 14:00:02.570486 Final TX Range 0 Vref 26
8095 14:00:02.570585
8096 14:00:02.570680 ==
8097 14:00:02.573761 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 14:00:02.577880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 14:00:02.577963 ==
8100 14:00:02.578027
8101 14:00:02.578087
8102 14:00:02.580786 TX Vref Scan disable
8103 14:00:02.587567 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8104 14:00:02.587698 == TX Byte 0 ==
8105 14:00:02.591033 u2DelayCellOfst[0]=10 cells (3 PI)
8106 14:00:02.594106 u2DelayCellOfst[1]=16 cells (5 PI)
8107 14:00:02.597457 u2DelayCellOfst[2]=10 cells (3 PI)
8108 14:00:02.600708 u2DelayCellOfst[3]=10 cells (3 PI)
8109 14:00:02.603947 u2DelayCellOfst[4]=6 cells (2 PI)
8110 14:00:02.607539 u2DelayCellOfst[5]=0 cells (0 PI)
8111 14:00:02.607660 u2DelayCellOfst[6]=13 cells (4 PI)
8112 14:00:02.610787 u2DelayCellOfst[7]=13 cells (4 PI)
8113 14:00:02.617091 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8114 14:00:02.620587 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8115 14:00:02.620669 == TX Byte 1 ==
8116 14:00:02.624280 u2DelayCellOfst[8]=0 cells (0 PI)
8117 14:00:02.627171 u2DelayCellOfst[9]=0 cells (0 PI)
8118 14:00:02.630727 u2DelayCellOfst[10]=3 cells (1 PI)
8119 14:00:02.634006 u2DelayCellOfst[11]=0 cells (0 PI)
8120 14:00:02.637601 u2DelayCellOfst[12]=10 cells (3 PI)
8121 14:00:02.640691 u2DelayCellOfst[13]=10 cells (3 PI)
8122 14:00:02.644368 u2DelayCellOfst[14]=13 cells (4 PI)
8123 14:00:02.647491 u2DelayCellOfst[15]=10 cells (3 PI)
8124 14:00:02.650816 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8125 14:00:02.654175 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8126 14:00:02.656980 DramC Write-DBI on
8127 14:00:02.657062 ==
8128 14:00:02.660801 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 14:00:02.663554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 14:00:02.663678 ==
8131 14:00:02.663743
8132 14:00:02.667062
8133 14:00:02.667144 TX Vref Scan disable
8134 14:00:02.670731 == TX Byte 0 ==
8135 14:00:02.674187 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8136 14:00:02.677396 == TX Byte 1 ==
8137 14:00:02.681029 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8138 14:00:02.681111 DramC Write-DBI off
8139 14:00:02.683681
8140 14:00:02.683766 [DATLAT]
8141 14:00:02.683843 Freq=1600, CH0 RK1
8142 14:00:02.683905
8143 14:00:02.687040 DATLAT Default: 0xf
8144 14:00:02.687147 0, 0xFFFF, sum = 0
8145 14:00:02.690735 1, 0xFFFF, sum = 0
8146 14:00:02.690832 2, 0xFFFF, sum = 0
8147 14:00:02.693969 3, 0xFFFF, sum = 0
8148 14:00:02.694079 4, 0xFFFF, sum = 0
8149 14:00:02.697045 5, 0xFFFF, sum = 0
8150 14:00:02.700124 6, 0xFFFF, sum = 0
8151 14:00:02.700223 7, 0xFFFF, sum = 0
8152 14:00:02.703640 8, 0xFFFF, sum = 0
8153 14:00:02.703739 9, 0xFFFF, sum = 0
8154 14:00:02.707299 10, 0xFFFF, sum = 0
8155 14:00:02.707397 11, 0xFFFF, sum = 0
8156 14:00:02.710623 12, 0xFFFF, sum = 0
8157 14:00:02.710722 13, 0xFFFF, sum = 0
8158 14:00:02.713704 14, 0x0, sum = 1
8159 14:00:02.713810 15, 0x0, sum = 2
8160 14:00:02.717186 16, 0x0, sum = 3
8161 14:00:02.717291 17, 0x0, sum = 4
8162 14:00:02.720299 best_step = 15
8163 14:00:02.720370
8164 14:00:02.720429 ==
8165 14:00:02.723567 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 14:00:02.726804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 14:00:02.726876 ==
8168 14:00:02.726935 RX Vref Scan: 0
8169 14:00:02.730247
8170 14:00:02.730349 RX Vref 0 -> 0, step: 1
8171 14:00:02.730436
8172 14:00:02.733937 RX Delay 19 -> 252, step: 4
8173 14:00:02.736881 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8174 14:00:02.743607 iDelay=195, Bit 1, Center 138 (91 ~ 186) 96
8175 14:00:02.746733 iDelay=195, Bit 2, Center 130 (79 ~ 182) 104
8176 14:00:02.750299 iDelay=195, Bit 3, Center 134 (83 ~ 186) 104
8177 14:00:02.753622 iDelay=195, Bit 4, Center 136 (87 ~ 186) 100
8178 14:00:02.757387 iDelay=195, Bit 5, Center 128 (75 ~ 182) 108
8179 14:00:02.760310 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
8180 14:00:02.767099 iDelay=195, Bit 7, Center 142 (91 ~ 194) 104
8181 14:00:02.770354 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8182 14:00:02.773345 iDelay=195, Bit 9, Center 116 (63 ~ 170) 108
8183 14:00:02.776809 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8184 14:00:02.779991 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8185 14:00:02.786967 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8186 14:00:02.790110 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8187 14:00:02.793478 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8188 14:00:02.796617 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8189 14:00:02.796698 ==
8190 14:00:02.799850 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 14:00:02.806656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 14:00:02.806737 ==
8193 14:00:02.806801 DQS Delay:
8194 14:00:02.810086 DQS0 = 0, DQS1 = 0
8195 14:00:02.810166 DQM Delay:
8196 14:00:02.813228 DQM0 = 135, DQM1 = 127
8197 14:00:02.813341 DQ Delay:
8198 14:00:02.816767 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8199 14:00:02.820050 DQ4 =136, DQ5 =128, DQ6 =140, DQ7 =142
8200 14:00:02.823514 DQ8 =118, DQ9 =116, DQ10 =130, DQ11 =120
8201 14:00:02.826703 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8202 14:00:02.826784
8203 14:00:02.826847
8204 14:00:02.826906
8205 14:00:02.829984 [DramC_TX_OE_Calibration] TA2
8206 14:00:02.833327 Original DQ_B0 (3 6) =30, OEN = 27
8207 14:00:02.836751 Original DQ_B1 (3 6) =30, OEN = 27
8208 14:00:02.840383 24, 0x0, End_B0=24 End_B1=24
8209 14:00:02.840468 25, 0x0, End_B0=25 End_B1=25
8210 14:00:02.843399 26, 0x0, End_B0=26 End_B1=26
8211 14:00:02.846900 27, 0x0, End_B0=27 End_B1=27
8212 14:00:02.849916 28, 0x0, End_B0=28 End_B1=28
8213 14:00:02.853542 29, 0x0, End_B0=29 End_B1=29
8214 14:00:02.853627 30, 0x0, End_B0=30 End_B1=30
8215 14:00:02.856551 31, 0x4141, End_B0=30 End_B1=30
8216 14:00:02.860048 Byte0 end_step=30 best_step=27
8217 14:00:02.863514 Byte1 end_step=30 best_step=27
8218 14:00:02.867052 Byte0 TX OE(2T, 0.5T) = (3, 3)
8219 14:00:02.870618 Byte1 TX OE(2T, 0.5T) = (3, 3)
8220 14:00:02.870699
8221 14:00:02.870763
8222 14:00:02.877119 [DQSOSCAuto] RK1, (LSB)MR18= 0x240c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
8223 14:00:02.879916 CH0 RK1: MR19=303, MR18=240C
8224 14:00:02.887215 CH0_RK1: MR19=0x303, MR18=0x240C, DQSOSC=391, MR23=63, INC=24, DEC=16
8225 14:00:02.889919 [RxdqsGatingPostProcess] freq 1600
8226 14:00:02.893369 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8227 14:00:02.896906 best DQS0 dly(2T, 0.5T) = (1, 1)
8228 14:00:02.900194 best DQS1 dly(2T, 0.5T) = (1, 1)
8229 14:00:02.903542 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8230 14:00:02.907226 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8231 14:00:02.910467 best DQS0 dly(2T, 0.5T) = (1, 1)
8232 14:00:02.913157 best DQS1 dly(2T, 0.5T) = (1, 1)
8233 14:00:02.916954 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8234 14:00:02.919974 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8235 14:00:02.923150 Pre-setting of DQS Precalculation
8236 14:00:02.926532 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8237 14:00:02.926613 ==
8238 14:00:02.930140 Dram Type= 6, Freq= 0, CH_1, rank 0
8239 14:00:02.933082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8240 14:00:02.937011 ==
8241 14:00:02.939794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8242 14:00:02.942978 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8243 14:00:02.949798 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8244 14:00:02.953070 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8245 14:00:02.963599 [CA 0] Center 42 (13~71) winsize 59
8246 14:00:02.966927 [CA 1] Center 41 (12~71) winsize 60
8247 14:00:02.969813 [CA 2] Center 39 (10~68) winsize 59
8248 14:00:02.973258 [CA 3] Center 37 (8~66) winsize 59
8249 14:00:02.977038 [CA 4] Center 37 (8~67) winsize 60
8250 14:00:02.979971 [CA 5] Center 36 (7~66) winsize 60
8251 14:00:02.980054
8252 14:00:02.983166 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8253 14:00:02.983248
8254 14:00:02.986405 [CATrainingPosCal] consider 1 rank data
8255 14:00:02.989904 u2DelayCellTimex100 = 290/100 ps
8256 14:00:02.993500 CA0 delay=42 (13~71),Diff = 6 PI (20 cell)
8257 14:00:02.999847 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8258 14:00:03.003383 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
8259 14:00:03.006706 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8260 14:00:03.010187 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8261 14:00:03.013238 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8262 14:00:03.013320
8263 14:00:03.016106 CA PerBit enable=1, Macro0, CA PI delay=36
8264 14:00:03.016187
8265 14:00:03.019944 [CBTSetCACLKResult] CA Dly = 36
8266 14:00:03.022766 CS Dly: 11 (0~42)
8267 14:00:03.026189 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8268 14:00:03.029625 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8269 14:00:03.029708 ==
8270 14:00:03.033233 Dram Type= 6, Freq= 0, CH_1, rank 1
8271 14:00:03.039391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 14:00:03.039473 ==
8273 14:00:03.042794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8274 14:00:03.046611 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8275 14:00:03.052659 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8276 14:00:03.059121 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8277 14:00:03.066653 [CA 0] Center 41 (12~71) winsize 60
8278 14:00:03.070139 [CA 1] Center 42 (12~72) winsize 61
8279 14:00:03.073493 [CA 2] Center 38 (9~68) winsize 60
8280 14:00:03.077227 [CA 3] Center 38 (8~68) winsize 61
8281 14:00:03.080030 [CA 4] Center 38 (8~68) winsize 61
8282 14:00:03.083588 [CA 5] Center 36 (7~66) winsize 60
8283 14:00:03.083708
8284 14:00:03.086630 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8285 14:00:03.086699
8286 14:00:03.089924 [CATrainingPosCal] consider 2 rank data
8287 14:00:03.093267 u2DelayCellTimex100 = 290/100 ps
8288 14:00:03.096747 CA0 delay=42 (13~71),Diff = 6 PI (20 cell)
8289 14:00:03.103209 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8290 14:00:03.106898 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
8291 14:00:03.109729 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8292 14:00:03.113158 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8293 14:00:03.117010 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8294 14:00:03.117092
8295 14:00:03.119987 CA PerBit enable=1, Macro0, CA PI delay=36
8296 14:00:03.120088
8297 14:00:03.123521 [CBTSetCACLKResult] CA Dly = 36
8298 14:00:03.126721 CS Dly: 12 (0~44)
8299 14:00:03.129924 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8300 14:00:03.133295 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8301 14:00:03.133375
8302 14:00:03.136866 ----->DramcWriteLeveling(PI) begin...
8303 14:00:03.136947 ==
8304 14:00:03.140009 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 14:00:03.143736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 14:00:03.146665 ==
8307 14:00:03.146744 Write leveling (Byte 0): 25 => 25
8308 14:00:03.150215 Write leveling (Byte 1): 26 => 26
8309 14:00:03.153141 DramcWriteLeveling(PI) end<-----
8310 14:00:03.153221
8311 14:00:03.153301 ==
8312 14:00:03.156764 Dram Type= 6, Freq= 0, CH_1, rank 0
8313 14:00:03.163292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 14:00:03.163397 ==
8315 14:00:03.166513 [Gating] SW mode calibration
8316 14:00:03.172979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8317 14:00:03.176621 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8318 14:00:03.183115 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 14:00:03.186312 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 14:00:03.189870 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8321 14:00:03.196242 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
8322 14:00:03.199586 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 14:00:03.203071 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 14:00:03.209404 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 14:00:03.212944 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 14:00:03.216375 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 14:00:03.223172 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 14:00:03.225817 1 5 8 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
8329 14:00:03.229422 1 5 12 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
8330 14:00:03.236098 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 14:00:03.239723 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 14:00:03.242402 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 14:00:03.249282 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 14:00:03.252287 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 14:00:03.255749 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 14:00:03.262359 1 6 8 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
8337 14:00:03.265480 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8338 14:00:03.268922 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 14:00:03.275700 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 14:00:03.279138 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 14:00:03.282342 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 14:00:03.285819 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 14:00:03.292100 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 14:00:03.295384 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8345 14:00:03.298709 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8346 14:00:03.305799 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8347 14:00:03.308876 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 14:00:03.312186 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 14:00:03.319033 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 14:00:03.322139 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 14:00:03.325388 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 14:00:03.332523 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 14:00:03.335563 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 14:00:03.338676 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 14:00:03.345742 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 14:00:03.348951 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 14:00:03.352573 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 14:00:03.359588 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 14:00:03.362790 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 14:00:03.366273 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8361 14:00:03.368935 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8362 14:00:03.375719 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 14:00:03.378928 Total UI for P1: 0, mck2ui 16
8364 14:00:03.382377 best dqsien dly found for B0: ( 1, 9, 10)
8365 14:00:03.385571 Total UI for P1: 0, mck2ui 16
8366 14:00:03.388925 best dqsien dly found for B1: ( 1, 9, 10)
8367 14:00:03.392107 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8368 14:00:03.396094 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8369 14:00:03.396176
8370 14:00:03.398882 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8371 14:00:03.402420 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8372 14:00:03.405700 [Gating] SW calibration Done
8373 14:00:03.405781 ==
8374 14:00:03.408815 Dram Type= 6, Freq= 0, CH_1, rank 0
8375 14:00:03.412046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8376 14:00:03.412128 ==
8377 14:00:03.415872 RX Vref Scan: 0
8378 14:00:03.415953
8379 14:00:03.418678 RX Vref 0 -> 0, step: 1
8380 14:00:03.418759
8381 14:00:03.418823 RX Delay 0 -> 252, step: 8
8382 14:00:03.425455 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8383 14:00:03.428756 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8384 14:00:03.432303 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8385 14:00:03.435480 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8386 14:00:03.438835 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8387 14:00:03.442320 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8388 14:00:03.449138 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8389 14:00:03.452402 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8390 14:00:03.455368 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8391 14:00:03.458984 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8392 14:00:03.462117 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8393 14:00:03.468677 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8394 14:00:03.472237 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8395 14:00:03.475470 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8396 14:00:03.478632 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8397 14:00:03.485596 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8398 14:00:03.485678 ==
8399 14:00:03.488299 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 14:00:03.491751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 14:00:03.491857 ==
8402 14:00:03.491953 DQS Delay:
8403 14:00:03.494981 DQS0 = 0, DQS1 = 0
8404 14:00:03.495083 DQM Delay:
8405 14:00:03.498364 DQM0 = 137, DQM1 = 132
8406 14:00:03.498479 DQ Delay:
8407 14:00:03.502042 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8408 14:00:03.504860 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8409 14:00:03.508419 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8410 14:00:03.511680 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8411 14:00:03.511784
8412 14:00:03.511877
8413 14:00:03.514921 ==
8414 14:00:03.518165 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 14:00:03.521518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 14:00:03.521623 ==
8417 14:00:03.521719
8418 14:00:03.521808
8419 14:00:03.524994 TX Vref Scan disable
8420 14:00:03.525093 == TX Byte 0 ==
8421 14:00:03.528490 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8422 14:00:03.534689 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8423 14:00:03.534794 == TX Byte 1 ==
8424 14:00:03.537928 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8425 14:00:03.545018 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8426 14:00:03.545122 ==
8427 14:00:03.548259 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 14:00:03.551535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 14:00:03.551682 ==
8430 14:00:03.564434
8431 14:00:03.567531 TX Vref early break, caculate TX vref
8432 14:00:03.570822 TX Vref=16, minBit 1, minWin=22, winSum=379
8433 14:00:03.574101 TX Vref=18, minBit 1, minWin=23, winSum=391
8434 14:00:03.577835 TX Vref=20, minBit 0, minWin=23, winSum=396
8435 14:00:03.581062 TX Vref=22, minBit 0, minWin=25, winSum=410
8436 14:00:03.584148 TX Vref=24, minBit 0, minWin=25, winSum=416
8437 14:00:03.591323 TX Vref=26, minBit 0, minWin=25, winSum=426
8438 14:00:03.593947 TX Vref=28, minBit 0, minWin=25, winSum=427
8439 14:00:03.597198 TX Vref=30, minBit 0, minWin=25, winSum=424
8440 14:00:03.600646 TX Vref=32, minBit 2, minWin=24, winSum=415
8441 14:00:03.603866 TX Vref=34, minBit 0, minWin=23, winSum=404
8442 14:00:03.610799 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 28
8443 14:00:03.610903
8444 14:00:03.614125 Final TX Range 0 Vref 28
8445 14:00:03.614236
8446 14:00:03.614328 ==
8447 14:00:03.617757 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 14:00:03.620574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 14:00:03.620674 ==
8450 14:00:03.620802
8451 14:00:03.620891
8452 14:00:03.623724 TX Vref Scan disable
8453 14:00:03.630877 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8454 14:00:03.630981 == TX Byte 0 ==
8455 14:00:03.633893 u2DelayCellOfst[0]=20 cells (6 PI)
8456 14:00:03.637386 u2DelayCellOfst[1]=13 cells (4 PI)
8457 14:00:03.640586 u2DelayCellOfst[2]=0 cells (0 PI)
8458 14:00:03.643739 u2DelayCellOfst[3]=10 cells (3 PI)
8459 14:00:03.647657 u2DelayCellOfst[4]=10 cells (3 PI)
8460 14:00:03.650263 u2DelayCellOfst[5]=20 cells (6 PI)
8461 14:00:03.653770 u2DelayCellOfst[6]=20 cells (6 PI)
8462 14:00:03.657134 u2DelayCellOfst[7]=10 cells (3 PI)
8463 14:00:03.660287 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8464 14:00:03.663942 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8465 14:00:03.666955 == TX Byte 1 ==
8466 14:00:03.667062 u2DelayCellOfst[8]=0 cells (0 PI)
8467 14:00:03.670567 u2DelayCellOfst[9]=3 cells (1 PI)
8468 14:00:03.673877 u2DelayCellOfst[10]=13 cells (4 PI)
8469 14:00:03.677088 u2DelayCellOfst[11]=3 cells (1 PI)
8470 14:00:03.680257 u2DelayCellOfst[12]=16 cells (5 PI)
8471 14:00:03.684020 u2DelayCellOfst[13]=16 cells (5 PI)
8472 14:00:03.686764 u2DelayCellOfst[14]=20 cells (6 PI)
8473 14:00:03.690188 u2DelayCellOfst[15]=16 cells (5 PI)
8474 14:00:03.693923 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8475 14:00:03.700239 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8476 14:00:03.700320 DramC Write-DBI on
8477 14:00:03.700384 ==
8478 14:00:03.704024 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 14:00:03.707357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 14:00:03.709994 ==
8481 14:00:03.710095
8482 14:00:03.710190
8483 14:00:03.710281 TX Vref Scan disable
8484 14:00:03.713745 == TX Byte 0 ==
8485 14:00:03.716868 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8486 14:00:03.720276 == TX Byte 1 ==
8487 14:00:03.723881 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8488 14:00:03.723980 DramC Write-DBI off
8489 14:00:03.727385
8490 14:00:03.727488 [DATLAT]
8491 14:00:03.727589 Freq=1600, CH1 RK0
8492 14:00:03.727691
8493 14:00:03.730761 DATLAT Default: 0xf
8494 14:00:03.730869 0, 0xFFFF, sum = 0
8495 14:00:03.733763 1, 0xFFFF, sum = 0
8496 14:00:03.733874 2, 0xFFFF, sum = 0
8497 14:00:03.736853 3, 0xFFFF, sum = 0
8498 14:00:03.740364 4, 0xFFFF, sum = 0
8499 14:00:03.740466 5, 0xFFFF, sum = 0
8500 14:00:03.743437 6, 0xFFFF, sum = 0
8501 14:00:03.743536 7, 0xFFFF, sum = 0
8502 14:00:03.746798 8, 0xFFFF, sum = 0
8503 14:00:03.746905 9, 0xFFFF, sum = 0
8504 14:00:03.750085 10, 0xFFFF, sum = 0
8505 14:00:03.750186 11, 0xFFFF, sum = 0
8506 14:00:03.753756 12, 0xFFFF, sum = 0
8507 14:00:03.753866 13, 0xFFFF, sum = 0
8508 14:00:03.756713 14, 0x0, sum = 1
8509 14:00:03.756814 15, 0x0, sum = 2
8510 14:00:03.760208 16, 0x0, sum = 3
8511 14:00:03.760310 17, 0x0, sum = 4
8512 14:00:03.763708 best_step = 15
8513 14:00:03.763805
8514 14:00:03.763905 ==
8515 14:00:03.766802 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 14:00:03.770209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 14:00:03.770312 ==
8518 14:00:03.770406 RX Vref Scan: 1
8519 14:00:03.773566
8520 14:00:03.773664 Set Vref Range= 24 -> 127
8521 14:00:03.773792
8522 14:00:03.776808 RX Vref 24 -> 127, step: 1
8523 14:00:03.776907
8524 14:00:03.780341 RX Delay 27 -> 252, step: 4
8525 14:00:03.780442
8526 14:00:03.783558 Set Vref, RX VrefLevel [Byte0]: 24
8527 14:00:03.786773 [Byte1]: 24
8528 14:00:03.786880
8529 14:00:03.790592 Set Vref, RX VrefLevel [Byte0]: 25
8530 14:00:03.793557 [Byte1]: 25
8531 14:00:03.793666
8532 14:00:03.796616 Set Vref, RX VrefLevel [Byte0]: 26
8533 14:00:03.800129 [Byte1]: 26
8534 14:00:03.803440
8535 14:00:03.803545 Set Vref, RX VrefLevel [Byte0]: 27
8536 14:00:03.807037 [Byte1]: 27
8537 14:00:03.811456
8538 14:00:03.811557 Set Vref, RX VrefLevel [Byte0]: 28
8539 14:00:03.814351 [Byte1]: 28
8540 14:00:03.818888
8541 14:00:03.818991 Set Vref, RX VrefLevel [Byte0]: 29
8542 14:00:03.822199 [Byte1]: 29
8543 14:00:03.826443
8544 14:00:03.826545 Set Vref, RX VrefLevel [Byte0]: 30
8545 14:00:03.829650 [Byte1]: 30
8546 14:00:03.833996
8547 14:00:03.834108 Set Vref, RX VrefLevel [Byte0]: 31
8548 14:00:03.836923 [Byte1]: 31
8549 14:00:03.841686
8550 14:00:03.841798 Set Vref, RX VrefLevel [Byte0]: 32
8551 14:00:03.844558 [Byte1]: 32
8552 14:00:03.849330
8553 14:00:03.849438 Set Vref, RX VrefLevel [Byte0]: 33
8554 14:00:03.852122 [Byte1]: 33
8555 14:00:03.856830
8556 14:00:03.856911 Set Vref, RX VrefLevel [Byte0]: 34
8557 14:00:03.859628 [Byte1]: 34
8558 14:00:03.864230
8559 14:00:03.864311 Set Vref, RX VrefLevel [Byte0]: 35
8560 14:00:03.867777 [Byte1]: 35
8561 14:00:03.872207
8562 14:00:03.872287 Set Vref, RX VrefLevel [Byte0]: 36
8563 14:00:03.874760 [Byte1]: 36
8564 14:00:03.879556
8565 14:00:03.879675 Set Vref, RX VrefLevel [Byte0]: 37
8566 14:00:03.882182 [Byte1]: 37
8567 14:00:03.886459
8568 14:00:03.886559 Set Vref, RX VrefLevel [Byte0]: 38
8569 14:00:03.889979 [Byte1]: 38
8570 14:00:03.894092
8571 14:00:03.894201 Set Vref, RX VrefLevel [Byte0]: 39
8572 14:00:03.897636 [Byte1]: 39
8573 14:00:03.901945
8574 14:00:03.902018 Set Vref, RX VrefLevel [Byte0]: 40
8575 14:00:03.904902 [Byte1]: 40
8576 14:00:03.908937
8577 14:00:03.909013 Set Vref, RX VrefLevel [Byte0]: 41
8578 14:00:03.912752 [Byte1]: 41
8579 14:00:03.916849
8580 14:00:03.916928 Set Vref, RX VrefLevel [Byte0]: 42
8581 14:00:03.919795 [Byte1]: 42
8582 14:00:03.924193
8583 14:00:03.924270 Set Vref, RX VrefLevel [Byte0]: 43
8584 14:00:03.927636 [Byte1]: 43
8585 14:00:03.931628
8586 14:00:03.931727 Set Vref, RX VrefLevel [Byte0]: 44
8587 14:00:03.935313 [Byte1]: 44
8588 14:00:03.939373
8589 14:00:03.939446 Set Vref, RX VrefLevel [Byte0]: 45
8590 14:00:03.942428 [Byte1]: 45
8591 14:00:03.947128
8592 14:00:03.947205 Set Vref, RX VrefLevel [Byte0]: 46
8593 14:00:03.950387 [Byte1]: 46
8594 14:00:03.954377
8595 14:00:03.954479 Set Vref, RX VrefLevel [Byte0]: 47
8596 14:00:03.957669 [Byte1]: 47
8597 14:00:03.962126
8598 14:00:03.962229 Set Vref, RX VrefLevel [Byte0]: 48
8599 14:00:03.965464 [Byte1]: 48
8600 14:00:03.969832
8601 14:00:03.969938 Set Vref, RX VrefLevel [Byte0]: 49
8602 14:00:03.972919 [Byte1]: 49
8603 14:00:03.977021
8604 14:00:03.977129 Set Vref, RX VrefLevel [Byte0]: 50
8605 14:00:03.980098 [Byte1]: 50
8606 14:00:03.984340
8607 14:00:03.984443 Set Vref, RX VrefLevel [Byte0]: 51
8608 14:00:03.987881 [Byte1]: 51
8609 14:00:03.992127
8610 14:00:03.992225 Set Vref, RX VrefLevel [Byte0]: 52
8611 14:00:03.995461 [Byte1]: 52
8612 14:00:03.999537
8613 14:00:03.999668 Set Vref, RX VrefLevel [Byte0]: 53
8614 14:00:04.002639 [Byte1]: 53
8615 14:00:04.007044
8616 14:00:04.007159 Set Vref, RX VrefLevel [Byte0]: 54
8617 14:00:04.010847 [Byte1]: 54
8618 14:00:04.014736
8619 14:00:04.014845 Set Vref, RX VrefLevel [Byte0]: 55
8620 14:00:04.018019 [Byte1]: 55
8621 14:00:04.022337
8622 14:00:04.022443 Set Vref, RX VrefLevel [Byte0]: 56
8623 14:00:04.025409 [Byte1]: 56
8624 14:00:04.029898
8625 14:00:04.029999 Set Vref, RX VrefLevel [Byte0]: 57
8626 14:00:04.032795 [Byte1]: 57
8627 14:00:04.037449
8628 14:00:04.037551 Set Vref, RX VrefLevel [Byte0]: 58
8629 14:00:04.040662 [Byte1]: 58
8630 14:00:04.045000
8631 14:00:04.045107 Set Vref, RX VrefLevel [Byte0]: 59
8632 14:00:04.048058 [Byte1]: 59
8633 14:00:04.052184
8634 14:00:04.052282 Set Vref, RX VrefLevel [Byte0]: 60
8635 14:00:04.055512 [Byte1]: 60
8636 14:00:04.059740
8637 14:00:04.059816 Set Vref, RX VrefLevel [Byte0]: 61
8638 14:00:04.063172 [Byte1]: 61
8639 14:00:04.067166
8640 14:00:04.067265 Set Vref, RX VrefLevel [Byte0]: 62
8641 14:00:04.070865 [Byte1]: 62
8642 14:00:04.074754
8643 14:00:04.074870 Set Vref, RX VrefLevel [Byte0]: 63
8644 14:00:04.078216 [Byte1]: 63
8645 14:00:04.082375
8646 14:00:04.082476 Set Vref, RX VrefLevel [Byte0]: 64
8647 14:00:04.085570 [Byte1]: 64
8648 14:00:04.090174
8649 14:00:04.090246 Set Vref, RX VrefLevel [Byte0]: 65
8650 14:00:04.093094 [Byte1]: 65
8651 14:00:04.097649
8652 14:00:04.097746 Set Vref, RX VrefLevel [Byte0]: 66
8653 14:00:04.100997 [Byte1]: 66
8654 14:00:04.105324
8655 14:00:04.105403 Set Vref, RX VrefLevel [Byte0]: 67
8656 14:00:04.108135 [Byte1]: 67
8657 14:00:04.112421
8658 14:00:04.112522 Set Vref, RX VrefLevel [Byte0]: 68
8659 14:00:04.115894 [Byte1]: 68
8660 14:00:04.120368
8661 14:00:04.120441 Set Vref, RX VrefLevel [Byte0]: 69
8662 14:00:04.123452 [Byte1]: 69
8663 14:00:04.127770
8664 14:00:04.127841 Set Vref, RX VrefLevel [Byte0]: 70
8665 14:00:04.130946 [Byte1]: 70
8666 14:00:04.135162
8667 14:00:04.135293 Set Vref, RX VrefLevel [Byte0]: 71
8668 14:00:04.138523 [Byte1]: 71
8669 14:00:04.142473
8670 14:00:04.142544 Set Vref, RX VrefLevel [Byte0]: 72
8671 14:00:04.145696 [Byte1]: 72
8672 14:00:04.150130
8673 14:00:04.150230 Set Vref, RX VrefLevel [Byte0]: 73
8674 14:00:04.153381 [Byte1]: 73
8675 14:00:04.157557
8676 14:00:04.157659 Set Vref, RX VrefLevel [Byte0]: 74
8677 14:00:04.161290 [Byte1]: 74
8678 14:00:04.165257
8679 14:00:04.165332 Set Vref, RX VrefLevel [Byte0]: 75
8680 14:00:04.168534 [Byte1]: 75
8681 14:00:04.172709
8682 14:00:04.172786 Set Vref, RX VrefLevel [Byte0]: 76
8683 14:00:04.175918 [Byte1]: 76
8684 14:00:04.180381
8685 14:00:04.180453 Set Vref, RX VrefLevel [Byte0]: 77
8686 14:00:04.183888 [Byte1]: 77
8687 14:00:04.188007
8688 14:00:04.188080 Set Vref, RX VrefLevel [Byte0]: 78
8689 14:00:04.191102 [Byte1]: 78
8690 14:00:04.195449
8691 14:00:04.195552 Final RX Vref Byte 0 = 57 to rank0
8692 14:00:04.198785 Final RX Vref Byte 1 = 51 to rank0
8693 14:00:04.202237 Final RX Vref Byte 0 = 57 to rank1
8694 14:00:04.205646 Final RX Vref Byte 1 = 51 to rank1==
8695 14:00:04.208781 Dram Type= 6, Freq= 0, CH_1, rank 0
8696 14:00:04.215408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8697 14:00:04.215509 ==
8698 14:00:04.215637 DQS Delay:
8699 14:00:04.215725 DQS0 = 0, DQS1 = 0
8700 14:00:04.218458 DQM Delay:
8701 14:00:04.218531 DQM0 = 134, DQM1 = 130
8702 14:00:04.221720 DQ Delay:
8703 14:00:04.225245 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8704 14:00:04.228795 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =132
8705 14:00:04.231797 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8706 14:00:04.235024 DQ12 =136, DQ13 =136, DQ14 =140, DQ15 =140
8707 14:00:04.235122
8708 14:00:04.235210
8709 14:00:04.235365
8710 14:00:04.238871 [DramC_TX_OE_Calibration] TA2
8711 14:00:04.241760 Original DQ_B0 (3 6) =30, OEN = 27
8712 14:00:04.245390 Original DQ_B1 (3 6) =30, OEN = 27
8713 14:00:04.248806 24, 0x0, End_B0=24 End_B1=24
8714 14:00:04.248895 25, 0x0, End_B0=25 End_B1=25
8715 14:00:04.252020 26, 0x0, End_B0=26 End_B1=26
8716 14:00:04.254840 27, 0x0, End_B0=27 End_B1=27
8717 14:00:04.258398 28, 0x0, End_B0=28 End_B1=28
8718 14:00:04.258506 29, 0x0, End_B0=29 End_B1=29
8719 14:00:04.261622 30, 0x0, End_B0=30 End_B1=30
8720 14:00:04.264930 31, 0x4141, End_B0=30 End_B1=30
8721 14:00:04.268446 Byte0 end_step=30 best_step=27
8722 14:00:04.271773 Byte1 end_step=30 best_step=27
8723 14:00:04.275218 Byte0 TX OE(2T, 0.5T) = (3, 3)
8724 14:00:04.275341 Byte1 TX OE(2T, 0.5T) = (3, 3)
8725 14:00:04.278869
8726 14:00:04.278979
8727 14:00:04.284999 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8728 14:00:04.288446 CH1 RK0: MR19=303, MR18=1523
8729 14:00:04.295114 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8730 14:00:04.295219
8731 14:00:04.298562 ----->DramcWriteLeveling(PI) begin...
8732 14:00:04.298665 ==
8733 14:00:04.301953 Dram Type= 6, Freq= 0, CH_1, rank 1
8734 14:00:04.304825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8735 14:00:04.304927 ==
8736 14:00:04.308360 Write leveling (Byte 0): 27 => 27
8737 14:00:04.311584 Write leveling (Byte 1): 27 => 27
8738 14:00:04.315120 DramcWriteLeveling(PI) end<-----
8739 14:00:04.315219
8740 14:00:04.315311 ==
8741 14:00:04.318348 Dram Type= 6, Freq= 0, CH_1, rank 1
8742 14:00:04.321775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 14:00:04.321880 ==
8744 14:00:04.325072 [Gating] SW mode calibration
8745 14:00:04.331525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8746 14:00:04.338522 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8747 14:00:04.341765 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 14:00:04.345208 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 14:00:04.351919 1 4 8 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
8750 14:00:04.354982 1 4 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8751 14:00:04.358543 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 14:00:04.364793 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 14:00:04.368377 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 14:00:04.371288 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 14:00:04.378217 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 14:00:04.381528 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8757 14:00:04.384614 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8758 14:00:04.391349 1 5 12 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
8759 14:00:04.394913 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 14:00:04.398147 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 14:00:04.404561 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 14:00:04.407818 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 14:00:04.411455 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 14:00:04.418236 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 14:00:04.421143 1 6 8 | B1->B0 | 3939 2525 | 0 0 | (0 0) (1 1)
8766 14:00:04.424441 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8767 14:00:04.431397 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 14:00:04.435074 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 14:00:04.438494 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 14:00:04.444747 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 14:00:04.447896 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 14:00:04.451108 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8773 14:00:04.454577 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8774 14:00:04.461242 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8775 14:00:04.464839 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8776 14:00:04.468048 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 14:00:04.474670 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 14:00:04.478160 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 14:00:04.481560 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 14:00:04.488343 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 14:00:04.491115 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 14:00:04.494576 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 14:00:04.501329 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 14:00:04.504444 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 14:00:04.507915 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 14:00:04.514882 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 14:00:04.521579 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 14:00:04.521725 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8789 14:00:04.527562 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8790 14:00:04.531122 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8791 14:00:04.534643 Total UI for P1: 0, mck2ui 16
8792 14:00:04.537675 best dqsien dly found for B1: ( 1, 9, 6)
8793 14:00:04.541131 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8794 14:00:04.544669 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 14:00:04.547940 Total UI for P1: 0, mck2ui 16
8796 14:00:04.551309 best dqsien dly found for B0: ( 1, 9, 12)
8797 14:00:04.554549 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8798 14:00:04.561621 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8799 14:00:04.561721
8800 14:00:04.564706 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8801 14:00:04.567950 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8802 14:00:04.571139 [Gating] SW calibration Done
8803 14:00:04.571236 ==
8804 14:00:04.574844 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 14:00:04.577983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 14:00:04.578082 ==
8807 14:00:04.580981 RX Vref Scan: 0
8808 14:00:04.581078
8809 14:00:04.581168 RX Vref 0 -> 0, step: 1
8810 14:00:04.581256
8811 14:00:04.584184 RX Delay 0 -> 252, step: 8
8812 14:00:04.588003 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8813 14:00:04.590905 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8814 14:00:04.597824 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8815 14:00:04.601088 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8816 14:00:04.604006 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8817 14:00:04.607698 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8818 14:00:04.611243 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8819 14:00:04.618165 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8820 14:00:04.621217 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8821 14:00:04.624179 iDelay=208, Bit 9, Center 127 (72 ~ 183) 112
8822 14:00:04.627526 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8823 14:00:04.631190 iDelay=208, Bit 11, Center 131 (80 ~ 183) 104
8824 14:00:04.637771 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8825 14:00:04.640856 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8826 14:00:04.644092 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8827 14:00:04.647456 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8828 14:00:04.647557 ==
8829 14:00:04.651001 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 14:00:04.657386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 14:00:04.657491 ==
8832 14:00:04.657588 DQS Delay:
8833 14:00:04.657679 DQS0 = 0, DQS1 = 0
8834 14:00:04.660849 DQM Delay:
8835 14:00:04.660948 DQM0 = 136, DQM1 = 135
8836 14:00:04.664248 DQ Delay:
8837 14:00:04.667559 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8838 14:00:04.670971 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8839 14:00:04.673825 DQ8 =119, DQ9 =127, DQ10 =135, DQ11 =131
8840 14:00:04.677467 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8841 14:00:04.677573
8842 14:00:04.677666
8843 14:00:04.677755 ==
8844 14:00:04.680707 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 14:00:04.683913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 14:00:04.687730 ==
8847 14:00:04.687812
8848 14:00:04.687875
8849 14:00:04.687934 TX Vref Scan disable
8850 14:00:04.690895 == TX Byte 0 ==
8851 14:00:04.694364 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8852 14:00:04.697226 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8853 14:00:04.701001 == TX Byte 1 ==
8854 14:00:04.704206 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8855 14:00:04.707407 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8856 14:00:04.707506 ==
8857 14:00:04.710800 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 14:00:04.717267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 14:00:04.717342 ==
8860 14:00:04.729052
8861 14:00:04.732477 TX Vref early break, caculate TX vref
8862 14:00:04.735908 TX Vref=16, minBit 1, minWin=23, winSum=384
8863 14:00:04.739426 TX Vref=18, minBit 0, minWin=23, winSum=394
8864 14:00:04.742667 TX Vref=20, minBit 0, minWin=24, winSum=403
8865 14:00:04.745674 TX Vref=22, minBit 0, minWin=24, winSum=412
8866 14:00:04.749238 TX Vref=24, minBit 0, minWin=25, winSum=419
8867 14:00:04.755512 TX Vref=26, minBit 0, minWin=25, winSum=426
8868 14:00:04.758691 TX Vref=28, minBit 0, minWin=26, winSum=429
8869 14:00:04.762496 TX Vref=30, minBit 0, minWin=25, winSum=423
8870 14:00:04.765355 TX Vref=32, minBit 0, minWin=24, winSum=408
8871 14:00:04.769207 TX Vref=34, minBit 0, minWin=24, winSum=402
8872 14:00:04.775715 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8873 14:00:04.775788
8874 14:00:04.779159 Final TX Range 0 Vref 28
8875 14:00:04.779259
8876 14:00:04.779348 ==
8877 14:00:04.782321 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 14:00:04.785634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 14:00:04.785740 ==
8880 14:00:04.785830
8881 14:00:04.785927
8882 14:00:04.789229 TX Vref Scan disable
8883 14:00:04.795458 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8884 14:00:04.795554 == TX Byte 0 ==
8885 14:00:04.798877 u2DelayCellOfst[0]=16 cells (5 PI)
8886 14:00:04.802644 u2DelayCellOfst[1]=10 cells (3 PI)
8887 14:00:04.805693 u2DelayCellOfst[2]=0 cells (0 PI)
8888 14:00:04.809019 u2DelayCellOfst[3]=6 cells (2 PI)
8889 14:00:04.812378 u2DelayCellOfst[4]=6 cells (2 PI)
8890 14:00:04.815767 u2DelayCellOfst[5]=16 cells (5 PI)
8891 14:00:04.815876 u2DelayCellOfst[6]=16 cells (5 PI)
8892 14:00:04.818737 u2DelayCellOfst[7]=6 cells (2 PI)
8893 14:00:04.825723 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8894 14:00:04.828947 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8895 14:00:04.829050 == TX Byte 1 ==
8896 14:00:04.832421 u2DelayCellOfst[8]=0 cells (0 PI)
8897 14:00:04.835553 u2DelayCellOfst[9]=3 cells (1 PI)
8898 14:00:04.839003 u2DelayCellOfst[10]=10 cells (3 PI)
8899 14:00:04.842071 u2DelayCellOfst[11]=3 cells (1 PI)
8900 14:00:04.845376 u2DelayCellOfst[12]=13 cells (4 PI)
8901 14:00:04.848647 u2DelayCellOfst[13]=16 cells (5 PI)
8902 14:00:04.852192 u2DelayCellOfst[14]=13 cells (4 PI)
8903 14:00:04.855524 u2DelayCellOfst[15]=16 cells (5 PI)
8904 14:00:04.858696 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8905 14:00:04.862044 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8906 14:00:04.865312 DramC Write-DBI on
8907 14:00:04.865414 ==
8908 14:00:04.869036 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 14:00:04.872157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 14:00:04.872270 ==
8911 14:00:04.872363
8912 14:00:04.872461
8913 14:00:04.875419 TX Vref Scan disable
8914 14:00:04.879033 == TX Byte 0 ==
8915 14:00:04.882281 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8916 14:00:04.885679 == TX Byte 1 ==
8917 14:00:04.889133 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8918 14:00:04.889218 DramC Write-DBI off
8919 14:00:04.889310
8920 14:00:04.892370 [DATLAT]
8921 14:00:04.892474 Freq=1600, CH1 RK1
8922 14:00:04.892569
8923 14:00:04.895491 DATLAT Default: 0xf
8924 14:00:04.895599 0, 0xFFFF, sum = 0
8925 14:00:04.899047 1, 0xFFFF, sum = 0
8926 14:00:04.899150 2, 0xFFFF, sum = 0
8927 14:00:04.902399 3, 0xFFFF, sum = 0
8928 14:00:04.902510 4, 0xFFFF, sum = 0
8929 14:00:04.905544 5, 0xFFFF, sum = 0
8930 14:00:04.905648 6, 0xFFFF, sum = 0
8931 14:00:04.909011 7, 0xFFFF, sum = 0
8932 14:00:04.909095 8, 0xFFFF, sum = 0
8933 14:00:04.912460 9, 0xFFFF, sum = 0
8934 14:00:04.912543 10, 0xFFFF, sum = 0
8935 14:00:04.915786 11, 0xFFFF, sum = 0
8936 14:00:04.918662 12, 0xFFFF, sum = 0
8937 14:00:04.918745 13, 0xFFFF, sum = 0
8938 14:00:04.922050 14, 0x0, sum = 1
8939 14:00:04.922133 15, 0x0, sum = 2
8940 14:00:04.922198 16, 0x0, sum = 3
8941 14:00:04.925759 17, 0x0, sum = 4
8942 14:00:04.925841 best_step = 15
8943 14:00:04.925906
8944 14:00:04.929072 ==
8945 14:00:04.929154 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 14:00:04.935922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 14:00:04.936005 ==
8948 14:00:04.936070 RX Vref Scan: 0
8949 14:00:04.936130
8950 14:00:04.938814 RX Vref 0 -> 0, step: 1
8951 14:00:04.938921
8952 14:00:04.942194 RX Delay 19 -> 252, step: 4
8953 14:00:04.945888 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8954 14:00:04.948747 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8955 14:00:04.955701 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8956 14:00:04.958845 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8957 14:00:04.962066 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8958 14:00:04.966117 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8959 14:00:04.969105 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8960 14:00:04.972509 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8961 14:00:04.975428 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8962 14:00:04.982248 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8963 14:00:04.986148 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8964 14:00:04.989117 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8965 14:00:04.992154 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8966 14:00:04.998669 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
8967 14:00:05.002111 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8968 14:00:05.005660 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8969 14:00:05.005765 ==
8970 14:00:05.009251 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 14:00:05.012525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 14:00:05.012631 ==
8973 14:00:05.015921 DQS Delay:
8974 14:00:05.016021 DQS0 = 0, DQS1 = 0
8975 14:00:05.018505 DQM Delay:
8976 14:00:05.018601 DQM0 = 134, DQM1 = 131
8977 14:00:05.021753 DQ Delay:
8978 14:00:05.025147 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8979 14:00:05.028426 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8980 14:00:05.032269 DQ8 =118, DQ9 =120, DQ10 =132, DQ11 =126
8981 14:00:05.035460 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =140
8982 14:00:05.035562
8983 14:00:05.035687
8984 14:00:05.035774
8985 14:00:05.038426 [DramC_TX_OE_Calibration] TA2
8986 14:00:05.042124 Original DQ_B0 (3 6) =30, OEN = 27
8987 14:00:05.045156 Original DQ_B1 (3 6) =30, OEN = 27
8988 14:00:05.045258 24, 0x0, End_B0=24 End_B1=24
8989 14:00:05.048320 25, 0x0, End_B0=25 End_B1=25
8990 14:00:05.051912 26, 0x0, End_B0=26 End_B1=26
8991 14:00:05.055156 27, 0x0, End_B0=27 End_B1=27
8992 14:00:05.058499 28, 0x0, End_B0=28 End_B1=28
8993 14:00:05.058602 29, 0x0, End_B0=29 End_B1=29
8994 14:00:05.061671 30, 0x0, End_B0=30 End_B1=30
8995 14:00:05.065131 31, 0x4141, End_B0=30 End_B1=30
8996 14:00:05.068634 Byte0 end_step=30 best_step=27
8997 14:00:05.071938 Byte1 end_step=30 best_step=27
8998 14:00:05.072044 Byte0 TX OE(2T, 0.5T) = (3, 3)
8999 14:00:05.075149 Byte1 TX OE(2T, 0.5T) = (3, 3)
9000 14:00:05.075251
9001 14:00:05.075342
9002 14:00:05.085343 [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9003 14:00:05.088119 CH1 RK1: MR19=303, MR18=2308
9004 14:00:05.095243 CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16
9005 14:00:05.095344 [RxdqsGatingPostProcess] freq 1600
9006 14:00:05.101851 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9007 14:00:05.104882 best DQS0 dly(2T, 0.5T) = (1, 1)
9008 14:00:05.108281 best DQS1 dly(2T, 0.5T) = (1, 1)
9009 14:00:05.111679 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9010 14:00:05.115457 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9011 14:00:05.118376 best DQS0 dly(2T, 0.5T) = (1, 1)
9012 14:00:05.121650 best DQS1 dly(2T, 0.5T) = (1, 1)
9013 14:00:05.125227 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9014 14:00:05.128118 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9015 14:00:05.128218 Pre-setting of DQS Precalculation
9016 14:00:05.134708 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9017 14:00:05.142030 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9018 14:00:05.148041 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9019 14:00:05.148146
9020 14:00:05.148240
9021 14:00:05.151572 [Calibration Summary] 3200 Mbps
9022 14:00:05.154912 CH 0, Rank 0
9023 14:00:05.155016 SW Impedance : PASS
9024 14:00:05.158198 DUTY Scan : NO K
9025 14:00:05.161652 ZQ Calibration : PASS
9026 14:00:05.161750 Jitter Meter : NO K
9027 14:00:05.165059 CBT Training : PASS
9028 14:00:05.165155 Write leveling : PASS
9029 14:00:05.168042 RX DQS gating : PASS
9030 14:00:05.171434 RX DQ/DQS(RDDQC) : PASS
9031 14:00:05.171553 TX DQ/DQS : PASS
9032 14:00:05.175081 RX DATLAT : PASS
9033 14:00:05.178275 RX DQ/DQS(Engine): PASS
9034 14:00:05.178414 TX OE : PASS
9035 14:00:05.181707 All Pass.
9036 14:00:05.181809
9037 14:00:05.181902 CH 0, Rank 1
9038 14:00:05.184910 SW Impedance : PASS
9039 14:00:05.185012 DUTY Scan : NO K
9040 14:00:05.188571 ZQ Calibration : PASS
9041 14:00:05.191462 Jitter Meter : NO K
9042 14:00:05.191563 CBT Training : PASS
9043 14:00:05.194751 Write leveling : PASS
9044 14:00:05.198255 RX DQS gating : PASS
9045 14:00:05.198365 RX DQ/DQS(RDDQC) : PASS
9046 14:00:05.201525 TX DQ/DQS : PASS
9047 14:00:05.204677 RX DATLAT : PASS
9048 14:00:05.204777 RX DQ/DQS(Engine): PASS
9049 14:00:05.208376 TX OE : PASS
9050 14:00:05.208486 All Pass.
9051 14:00:05.208579
9052 14:00:05.211092 CH 1, Rank 0
9053 14:00:05.211190 SW Impedance : PASS
9054 14:00:05.214540 DUTY Scan : NO K
9055 14:00:05.218128 ZQ Calibration : PASS
9056 14:00:05.218230 Jitter Meter : NO K
9057 14:00:05.221286 CBT Training : PASS
9058 14:00:05.221368 Write leveling : PASS
9059 14:00:05.224596 RX DQS gating : PASS
9060 14:00:05.228101 RX DQ/DQS(RDDQC) : PASS
9061 14:00:05.228202 TX DQ/DQS : PASS
9062 14:00:05.231708 RX DATLAT : PASS
9063 14:00:05.234207 RX DQ/DQS(Engine): PASS
9064 14:00:05.234315 TX OE : PASS
9065 14:00:05.237559 All Pass.
9066 14:00:05.237667
9067 14:00:05.237758 CH 1, Rank 1
9068 14:00:05.240923 SW Impedance : PASS
9069 14:00:05.241026 DUTY Scan : NO K
9070 14:00:05.244223 ZQ Calibration : PASS
9071 14:00:05.248111 Jitter Meter : NO K
9072 14:00:05.248211 CBT Training : PASS
9073 14:00:05.251319 Write leveling : PASS
9074 14:00:05.254135 RX DQS gating : PASS
9075 14:00:05.254241 RX DQ/DQS(RDDQC) : PASS
9076 14:00:05.257480 TX DQ/DQS : PASS
9077 14:00:05.260820 RX DATLAT : PASS
9078 14:00:05.260931 RX DQ/DQS(Engine): PASS
9079 14:00:05.264520 TX OE : PASS
9080 14:00:05.264626 All Pass.
9081 14:00:05.264719
9082 14:00:05.267743 DramC Write-DBI on
9083 14:00:05.271137 PER_BANK_REFRESH: Hybrid Mode
9084 14:00:05.271240 TX_TRACKING: ON
9085 14:00:05.280832 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9086 14:00:05.288087 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9087 14:00:05.294469 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9088 14:00:05.297790 [FAST_K] Save calibration result to emmc
9089 14:00:05.301285 sync common calibartion params.
9090 14:00:05.304310 sync cbt_mode0:1, 1:1
9091 14:00:05.304415 dram_init: ddr_geometry: 2
9092 14:00:05.307597 dram_init: ddr_geometry: 2
9093 14:00:05.311201 dram_init: ddr_geometry: 2
9094 14:00:05.314152 0:dram_rank_size:100000000
9095 14:00:05.314262 1:dram_rank_size:100000000
9096 14:00:05.321079 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9097 14:00:05.324032 DFS_SHUFFLE_HW_MODE: ON
9098 14:00:05.327463 dramc_set_vcore_voltage set vcore to 725000
9099 14:00:05.330946 Read voltage for 1600, 0
9100 14:00:05.331049 Vio18 = 0
9101 14:00:05.331143 Vcore = 725000
9102 14:00:05.334569 Vdram = 0
9103 14:00:05.334684 Vddq = 0
9104 14:00:05.334788 Vmddr = 0
9105 14:00:05.337696 switch to 3200 Mbps bootup
9106 14:00:05.337817 [DramcRunTimeConfig]
9107 14:00:05.340978 PHYPLL
9108 14:00:05.341074 DPM_CONTROL_AFTERK: ON
9109 14:00:05.344112 PER_BANK_REFRESH: ON
9110 14:00:05.347271 REFRESH_OVERHEAD_REDUCTION: ON
9111 14:00:05.347365 CMD_PICG_NEW_MODE: OFF
9112 14:00:05.351158 XRTWTW_NEW_MODE: ON
9113 14:00:05.351256 XRTRTR_NEW_MODE: ON
9114 14:00:05.354174 TX_TRACKING: ON
9115 14:00:05.354287 RDSEL_TRACKING: OFF
9116 14:00:05.357401 DQS Precalculation for DVFS: ON
9117 14:00:05.360604 RX_TRACKING: OFF
9118 14:00:05.360704 HW_GATING DBG: ON
9119 14:00:05.364212 ZQCS_ENABLE_LP4: ON
9120 14:00:05.364314 RX_PICG_NEW_MODE: ON
9121 14:00:05.367542 TX_PICG_NEW_MODE: ON
9122 14:00:05.367669 ENABLE_RX_DCM_DPHY: ON
9123 14:00:05.370844 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9124 14:00:05.374263 DUMMY_READ_FOR_TRACKING: OFF
9125 14:00:05.377929 !!! SPM_CONTROL_AFTERK: OFF
9126 14:00:05.380767 !!! SPM could not control APHY
9127 14:00:05.380872 IMPEDANCE_TRACKING: ON
9128 14:00:05.384213 TEMP_SENSOR: ON
9129 14:00:05.384310 HW_SAVE_FOR_SR: OFF
9130 14:00:05.387543 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9131 14:00:05.390570 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9132 14:00:05.394261 Read ODT Tracking: ON
9133 14:00:05.397578 Refresh Rate DeBounce: ON
9134 14:00:05.397682 DFS_NO_QUEUE_FLUSH: ON
9135 14:00:05.401128 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9136 14:00:05.404215 ENABLE_DFS_RUNTIME_MRW: OFF
9137 14:00:05.407587 DDR_RESERVE_NEW_MODE: ON
9138 14:00:05.407719 MR_CBT_SWITCH_FREQ: ON
9139 14:00:05.410434 =========================
9140 14:00:05.429829 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9141 14:00:05.432695 dram_init: ddr_geometry: 2
9142 14:00:05.450682 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9143 14:00:05.453843 dram_init: dram init end (result: 0)
9144 14:00:05.460701 DRAM-K: Full calibration passed in 24453 msecs
9145 14:00:05.464224 MRC: failed to locate region type 0.
9146 14:00:05.464327 DRAM rank0 size:0x100000000,
9147 14:00:05.467804 DRAM rank1 size=0x100000000
9148 14:00:05.477459 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9149 14:00:05.483838 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9150 14:00:05.490652 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9151 14:00:05.497239 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9152 14:00:05.500262 DRAM rank0 size:0x100000000,
9153 14:00:05.503554 DRAM rank1 size=0x100000000
9154 14:00:05.503682 CBMEM:
9155 14:00:05.507228 IMD: root @ 0xfffff000 254 entries.
9156 14:00:05.510242 IMD: root @ 0xffffec00 62 entries.
9157 14:00:05.513932 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9158 14:00:05.520369 WARNING: RO_VPD is uninitialized or empty.
9159 14:00:05.524037 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9160 14:00:05.530775 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9161 14:00:05.543665 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9162 14:00:05.555204 BS: romstage times (exec / console): total (unknown) / 23987 ms
9163 14:00:05.555309
9164 14:00:05.555406
9165 14:00:05.565136 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9166 14:00:05.568484 ARM64: Exception handlers installed.
9167 14:00:05.571610 ARM64: Testing exception
9168 14:00:05.575184 ARM64: Done test exception
9169 14:00:05.575289 Enumerating buses...
9170 14:00:05.578445 Show all devs... Before device enumeration.
9171 14:00:05.581452 Root Device: enabled 1
9172 14:00:05.585109 CPU_CLUSTER: 0: enabled 1
9173 14:00:05.585265 CPU: 00: enabled 1
9174 14:00:05.588182 Compare with tree...
9175 14:00:05.588257 Root Device: enabled 1
9176 14:00:05.591452 CPU_CLUSTER: 0: enabled 1
9177 14:00:05.594794 CPU: 00: enabled 1
9178 14:00:05.594874 Root Device scanning...
9179 14:00:05.598263 scan_static_bus for Root Device
9180 14:00:05.601581 CPU_CLUSTER: 0 enabled
9181 14:00:05.604818 scan_static_bus for Root Device done
9182 14:00:05.608291 scan_bus: bus Root Device finished in 8 msecs
9183 14:00:05.608372 done
9184 14:00:05.614733 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9185 14:00:05.618247 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9186 14:00:05.625527 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9187 14:00:05.627969 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9188 14:00:05.631761 Allocating resources...
9189 14:00:05.634631 Reading resources...
9190 14:00:05.638061 Root Device read_resources bus 0 link: 0
9191 14:00:05.638200 DRAM rank0 size:0x100000000,
9192 14:00:05.641628 DRAM rank1 size=0x100000000
9193 14:00:05.644572 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9194 14:00:05.648193 CPU: 00 missing read_resources
9195 14:00:05.651459 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9196 14:00:05.658291 Root Device read_resources bus 0 link: 0 done
9197 14:00:05.658373 Done reading resources.
9198 14:00:05.664735 Show resources in subtree (Root Device)...After reading.
9199 14:00:05.667982 Root Device child on link 0 CPU_CLUSTER: 0
9200 14:00:05.671462 CPU_CLUSTER: 0 child on link 0 CPU: 00
9201 14:00:05.681074 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9202 14:00:05.681156 CPU: 00
9203 14:00:05.684472 Root Device assign_resources, bus 0 link: 0
9204 14:00:05.687947 CPU_CLUSTER: 0 missing set_resources
9205 14:00:05.691369 Root Device assign_resources, bus 0 link: 0 done
9206 14:00:05.694400 Done setting resources.
9207 14:00:05.701543 Show resources in subtree (Root Device)...After assigning values.
9208 14:00:05.704754 Root Device child on link 0 CPU_CLUSTER: 0
9209 14:00:05.707908 CPU_CLUSTER: 0 child on link 0 CPU: 00
9210 14:00:05.718050 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9211 14:00:05.718132 CPU: 00
9212 14:00:05.721525 Done allocating resources.
9213 14:00:05.724845 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9214 14:00:05.728016 Enabling resources...
9215 14:00:05.728100 done.
9216 14:00:05.735155 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9217 14:00:05.735236 Initializing devices...
9218 14:00:05.738033 Root Device init
9219 14:00:05.738114 init hardware done!
9220 14:00:05.741726 0x00000018: ctrlr->caps
9221 14:00:05.744945 52.000 MHz: ctrlr->f_max
9222 14:00:05.745028 0.400 MHz: ctrlr->f_min
9223 14:00:05.747967 0x40ff8080: ctrlr->voltages
9224 14:00:05.748049 sclk: 390625
9225 14:00:05.751523 Bus Width = 1
9226 14:00:05.751646 sclk: 390625
9227 14:00:05.751712 Bus Width = 1
9228 14:00:05.754832 Early init status = 3
9229 14:00:05.758294 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9230 14:00:05.762666 in-header: 03 fc 00 00 01 00 00 00
9231 14:00:05.766044 in-data: 00
9232 14:00:05.769328 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9233 14:00:05.774600 in-header: 03 fd 00 00 00 00 00 00
9234 14:00:05.777799 in-data:
9235 14:00:05.780705 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9236 14:00:05.785134 in-header: 03 fc 00 00 01 00 00 00
9237 14:00:05.788311 in-data: 00
9238 14:00:05.791861 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9239 14:00:05.796830 in-header: 03 fd 00 00 00 00 00 00
9240 14:00:05.800298 in-data:
9241 14:00:05.803333 [SSUSB] Setting up USB HOST controller...
9242 14:00:05.806839 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9243 14:00:05.810359 [SSUSB] phy power-on done.
9244 14:00:05.813595 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9245 14:00:05.820473 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9246 14:00:05.823872 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9247 14:00:05.830280 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9248 14:00:05.837118 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9249 14:00:05.843451 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9250 14:00:05.849928 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9251 14:00:05.856840 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9252 14:00:05.860275 SPM: binary array size = 0x9dc
9253 14:00:05.863538 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9254 14:00:05.869929 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9255 14:00:05.876695 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9256 14:00:05.880083 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9257 14:00:05.883488 configure_display: Starting display init
9258 14:00:05.920767 anx7625_power_on_init: Init interface.
9259 14:00:05.923509 anx7625_disable_pd_protocol: Disabled PD feature.
9260 14:00:05.926850 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9261 14:00:05.954822 anx7625_start_dp_work: Secure OCM version=00
9262 14:00:05.957688 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9263 14:00:05.972641 sp_tx_get_edid_block: EDID Block = 1
9264 14:00:06.075429 Extracted contents:
9265 14:00:06.078589 header: 00 ff ff ff ff ff ff 00
9266 14:00:06.082252 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9267 14:00:06.085780 version: 01 04
9268 14:00:06.088869 basic params: 95 1f 11 78 0a
9269 14:00:06.092308 chroma info: 76 90 94 55 54 90 27 21 50 54
9270 14:00:06.095373 established: 00 00 00
9271 14:00:06.098641 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9272 14:00:06.105475 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9273 14:00:06.111892 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9274 14:00:06.118544 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9275 14:00:06.125012 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9276 14:00:06.128612 extensions: 00
9277 14:00:06.128689 checksum: fb
9278 14:00:06.128762
9279 14:00:06.132228 Manufacturer: IVO Model 57d Serial Number 0
9280 14:00:06.135060 Made week 0 of 2020
9281 14:00:06.135155 EDID version: 1.4
9282 14:00:06.138544 Digital display
9283 14:00:06.141623 6 bits per primary color channel
9284 14:00:06.141702 DisplayPort interface
9285 14:00:06.145509 Maximum image size: 31 cm x 17 cm
9286 14:00:06.148569 Gamma: 220%
9287 14:00:06.148664 Check DPMS levels
9288 14:00:06.151873 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9289 14:00:06.155094 First detailed timing is preferred timing
9290 14:00:06.158225 Established timings supported:
9291 14:00:06.161899 Standard timings supported:
9292 14:00:06.161993 Detailed timings
9293 14:00:06.168373 Hex of detail: 383680a07038204018303c0035ae10000019
9294 14:00:06.171993 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9295 14:00:06.178166 0780 0798 07c8 0820 hborder 0
9296 14:00:06.181792 0438 043b 0447 0458 vborder 0
9297 14:00:06.185025 -hsync -vsync
9298 14:00:06.185102 Did detailed timing
9299 14:00:06.188142 Hex of detail: 000000000000000000000000000000000000
9300 14:00:06.191600 Manufacturer-specified data, tag 0
9301 14:00:06.198585 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9302 14:00:06.198687 ASCII string: InfoVision
9303 14:00:06.205047 Hex of detail: 000000fe00523134304e574635205248200a
9304 14:00:06.208248 ASCII string: R140NWF5 RH
9305 14:00:06.208347 Checksum
9306 14:00:06.208413 Checksum: 0xfb (valid)
9307 14:00:06.214765 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9308 14:00:06.218027 DSI data_rate: 832800000 bps
9309 14:00:06.221491 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9310 14:00:06.224669 anx7625_parse_edid: pixelclock(138800).
9311 14:00:06.231499 hactive(1920), hsync(48), hfp(24), hbp(88)
9312 14:00:06.234738 vactive(1080), vsync(12), vfp(3), vbp(17)
9313 14:00:06.238101 anx7625_dsi_config: config dsi.
9314 14:00:06.244773 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9315 14:00:06.257030 anx7625_dsi_config: success to config DSI
9316 14:00:06.260519 anx7625_dp_start: MIPI phy setup OK.
9317 14:00:06.263754 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9318 14:00:06.267233 mtk_ddp_mode_set invalid vrefresh 60
9319 14:00:06.270707 main_disp_path_setup
9320 14:00:06.270777 ovl_layer_smi_id_en
9321 14:00:06.273960 ovl_layer_smi_id_en
9322 14:00:06.274058 ccorr_config
9323 14:00:06.274150 aal_config
9324 14:00:06.277128 gamma_config
9325 14:00:06.277200 postmask_config
9326 14:00:06.280288 dither_config
9327 14:00:06.283900 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9328 14:00:06.290671 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9329 14:00:06.293794 Root Device init finished in 553 msecs
9330 14:00:06.293892 CPU_CLUSTER: 0 init
9331 14:00:06.303696 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9332 14:00:06.307118 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9333 14:00:06.310365 APU_MBOX 0x190000b0 = 0x10001
9334 14:00:06.313700 APU_MBOX 0x190001b0 = 0x10001
9335 14:00:06.317273 APU_MBOX 0x190005b0 = 0x10001
9336 14:00:06.320741 APU_MBOX 0x190006b0 = 0x10001
9337 14:00:06.323641 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9338 14:00:06.336494 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9339 14:00:06.348832 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9340 14:00:06.355332 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9341 14:00:06.366667 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9342 14:00:06.376190 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9343 14:00:06.379861 CPU_CLUSTER: 0 init finished in 81 msecs
9344 14:00:06.382731 Devices initialized
9345 14:00:06.385844 Show all devs... After init.
9346 14:00:06.385962 Root Device: enabled 1
9347 14:00:06.389082 CPU_CLUSTER: 0: enabled 1
9348 14:00:06.392706 CPU: 00: enabled 1
9349 14:00:06.396028 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9350 14:00:06.399333 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9351 14:00:06.402633 ELOG: NV offset 0x57f000 size 0x1000
9352 14:00:06.409064 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9353 14:00:06.415873 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9354 14:00:06.419020 ELOG: Event(17) added with size 13 at 2023-08-28 13:59:02 UTC
9355 14:00:06.422413 out: cmd=0x121: 03 db 21 01 00 00 00 00
9356 14:00:06.426738 in-header: 03 e4 00 00 2c 00 00 00
9357 14:00:06.439620 in-data: 7b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9358 14:00:06.446247 ELOG: Event(A1) added with size 10 at 2023-08-28 13:59:02 UTC
9359 14:00:06.452967 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9360 14:00:06.459884 ELOG: Event(A0) added with size 9 at 2023-08-28 13:59:02 UTC
9361 14:00:06.462704 elog_add_boot_reason: Logged dev mode boot
9362 14:00:06.466425 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9363 14:00:06.469330 Finalize devices...
9364 14:00:06.469429 Devices finalized
9365 14:00:06.476185 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9366 14:00:06.479627 Writing coreboot table at 0xffe64000
9367 14:00:06.482671 0. 000000000010a000-0000000000113fff: RAMSTAGE
9368 14:00:06.486782 1. 0000000040000000-00000000400fffff: RAM
9369 14:00:06.489787 2. 0000000040100000-000000004032afff: RAMSTAGE
9370 14:00:06.496206 3. 000000004032b000-00000000545fffff: RAM
9371 14:00:06.499610 4. 0000000054600000-000000005465ffff: BL31
9372 14:00:06.503108 5. 0000000054660000-00000000ffe63fff: RAM
9373 14:00:06.506211 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9374 14:00:06.512820 7. 0000000100000000-000000023fffffff: RAM
9375 14:00:06.512899 Passing 5 GPIOs to payload:
9376 14:00:06.519784 NAME | PORT | POLARITY | VALUE
9377 14:00:06.522560 EC in RW | 0x000000aa | low | undefined
9378 14:00:06.529206 EC interrupt | 0x00000005 | low | undefined
9379 14:00:06.532454 TPM interrupt | 0x000000ab | high | undefined
9380 14:00:06.535913 SD card detect | 0x00000011 | high | undefined
9381 14:00:06.542814 speaker enable | 0x00000093 | high | undefined
9382 14:00:06.546496 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9383 14:00:06.549227 in-header: 03 f9 00 00 02 00 00 00
9384 14:00:06.549325 in-data: 02 00
9385 14:00:06.552424 ADC[4]: Raw value=903988 ID=7
9386 14:00:06.556189 ADC[3]: Raw value=213441 ID=1
9387 14:00:06.556268 RAM Code: 0x71
9388 14:00:06.559199 ADC[6]: Raw value=75332 ID=0
9389 14:00:06.562322 ADC[5]: Raw value=213072 ID=1
9390 14:00:06.562422 SKU Code: 0x1
9391 14:00:06.569036 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2fd0
9392 14:00:06.573030 coreboot table: 964 bytes.
9393 14:00:06.575718 IMD ROOT 0. 0xfffff000 0x00001000
9394 14:00:06.579233 IMD SMALL 1. 0xffffe000 0x00001000
9395 14:00:06.582742 RO MCACHE 2. 0xffffc000 0x00001104
9396 14:00:06.586175 CONSOLE 3. 0xfff7c000 0x00080000
9397 14:00:06.589381 FMAP 4. 0xfff7b000 0x00000452
9398 14:00:06.592248 TIME STAMP 5. 0xfff7a000 0x00000910
9399 14:00:06.595539 VBOOT WORK 6. 0xfff66000 0x00014000
9400 14:00:06.598941 RAMOOPS 7. 0xffe66000 0x00100000
9401 14:00:06.602418 COREBOOT 8. 0xffe64000 0x00002000
9402 14:00:06.602515 IMD small region:
9403 14:00:06.605625 IMD ROOT 0. 0xffffec00 0x00000400
9404 14:00:06.609550 VPD 1. 0xffffeb80 0x0000006c
9405 14:00:06.612621 MMC STATUS 2. 0xffffeb60 0x00000004
9406 14:00:06.619263 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9407 14:00:06.622557 Probing TPM: done!
9408 14:00:06.625918 Connected to device vid:did:rid of 1ae0:0028:00
9409 14:00:06.635916 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9410 14:00:06.639009 Initialized TPM device CR50 revision 0
9411 14:00:06.643207 Checking cr50 for pending updates
9412 14:00:06.646274 Reading cr50 TPM mode
9413 14:00:06.654767 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9414 14:00:06.661417 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9415 14:00:06.701920 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9416 14:00:06.704748 Checking segment from ROM address 0x40100000
9417 14:00:06.708093 Checking segment from ROM address 0x4010001c
9418 14:00:06.714657 Loading segment from ROM address 0x40100000
9419 14:00:06.714764 code (compression=0)
9420 14:00:06.724997 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9421 14:00:06.731564 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9422 14:00:06.731674 it's not compressed!
9423 14:00:06.738122 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9424 14:00:06.741695 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9425 14:00:06.761906 Loading segment from ROM address 0x4010001c
9426 14:00:06.762012 Entry Point 0x80000000
9427 14:00:06.765268 Loaded segments
9428 14:00:06.768524 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9429 14:00:06.775260 Jumping to boot code at 0x80000000(0xffe64000)
9430 14:00:06.782198 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9431 14:00:06.788742 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9432 14:00:06.796575 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9433 14:00:06.799488 Checking segment from ROM address 0x40100000
9434 14:00:06.802930 Checking segment from ROM address 0x4010001c
9435 14:00:06.809866 Loading segment from ROM address 0x40100000
9436 14:00:06.809970 code (compression=1)
9437 14:00:06.816361 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9438 14:00:06.826334 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9439 14:00:06.826438 using LZMA
9440 14:00:06.834711 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9441 14:00:06.841504 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9442 14:00:06.844877 Loading segment from ROM address 0x4010001c
9443 14:00:06.844950 Entry Point 0x54601000
9444 14:00:06.848646 Loaded segments
9445 14:00:06.851257 NOTICE: MT8192 bl31_setup
9446 14:00:06.858717 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9447 14:00:06.861583 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9448 14:00:06.865233 WARNING: region 0:
9449 14:00:06.868621 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9450 14:00:06.868712 WARNING: region 1:
9451 14:00:06.875017 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9452 14:00:06.878622 WARNING: region 2:
9453 14:00:06.881766 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9454 14:00:06.885389 WARNING: region 3:
9455 14:00:06.888813 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9456 14:00:06.892065 WARNING: region 4:
9457 14:00:06.895058 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9458 14:00:06.898539 WARNING: region 5:
9459 14:00:06.901909 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 14:00:06.905217 WARNING: region 6:
9461 14:00:06.908885 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 14:00:06.908983 WARNING: region 7:
9463 14:00:06.915365 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 14:00:06.922182 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9465 14:00:06.925391 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9466 14:00:06.928927 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9467 14:00:06.935150 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9468 14:00:06.938719 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9469 14:00:06.941970 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9470 14:00:06.948459 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9471 14:00:06.952246 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9472 14:00:06.955489 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9473 14:00:06.961836 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9474 14:00:06.965619 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9475 14:00:06.968531 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9476 14:00:06.975462 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9477 14:00:06.978986 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9478 14:00:06.985581 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9479 14:00:06.988544 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9480 14:00:06.991896 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9481 14:00:06.999008 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9482 14:00:07.002123 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9483 14:00:07.005733 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9484 14:00:07.011866 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9485 14:00:07.015792 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9486 14:00:07.022175 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9487 14:00:07.025368 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9488 14:00:07.029038 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9489 14:00:07.035830 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9490 14:00:07.039020 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9491 14:00:07.045292 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9492 14:00:07.049124 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9493 14:00:07.052140 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9494 14:00:07.058777 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9495 14:00:07.062244 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9496 14:00:07.065358 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9497 14:00:07.072127 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9498 14:00:07.075467 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9499 14:00:07.078807 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9500 14:00:07.082410 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9501 14:00:07.088831 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9502 14:00:07.092056 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9503 14:00:07.095465 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9504 14:00:07.098899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9505 14:00:07.105342 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9506 14:00:07.109036 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9507 14:00:07.112366 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9508 14:00:07.115643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9509 14:00:07.122361 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9510 14:00:07.125766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9511 14:00:07.128905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9512 14:00:07.132614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9513 14:00:07.139654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9514 14:00:07.142519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9515 14:00:07.149254 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9516 14:00:07.152695 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9517 14:00:07.159481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9518 14:00:07.162538 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9519 14:00:07.166213 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9520 14:00:07.172337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9521 14:00:07.175559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9522 14:00:07.182637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9523 14:00:07.185642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9524 14:00:07.192497 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9525 14:00:07.195753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9526 14:00:07.202448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9527 14:00:07.206100 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9528 14:00:07.209046 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9529 14:00:07.215661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9530 14:00:07.219025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9531 14:00:07.225647 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9532 14:00:07.229401 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9533 14:00:07.232813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9534 14:00:07.239760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9535 14:00:07.242383 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9536 14:00:07.249529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9537 14:00:07.252352 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9538 14:00:07.259653 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9539 14:00:07.262849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9540 14:00:07.265995 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9541 14:00:07.272706 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9542 14:00:07.275890 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9543 14:00:07.282781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9544 14:00:07.286006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9545 14:00:07.292564 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9546 14:00:07.295881 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9547 14:00:07.299626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9548 14:00:07.306143 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9549 14:00:07.309586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9550 14:00:07.316292 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9551 14:00:07.319627 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9552 14:00:07.325869 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9553 14:00:07.329615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9554 14:00:07.332801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9555 14:00:07.339329 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9556 14:00:07.342814 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9557 14:00:07.349118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9558 14:00:07.352914 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9559 14:00:07.359390 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9560 14:00:07.362641 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9561 14:00:07.366451 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9562 14:00:07.369172 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9563 14:00:07.376204 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9564 14:00:07.379454 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9565 14:00:07.382824 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9566 14:00:07.389453 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9567 14:00:07.392711 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9568 14:00:07.399780 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9569 14:00:07.402758 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9570 14:00:07.406319 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9571 14:00:07.412723 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9572 14:00:07.416037 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9573 14:00:07.423009 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9574 14:00:07.425908 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9575 14:00:07.429368 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9576 14:00:07.436166 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9577 14:00:07.439822 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9578 14:00:07.442764 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9579 14:00:07.449820 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9580 14:00:07.453192 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9581 14:00:07.456249 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9582 14:00:07.463199 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9583 14:00:07.466712 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9584 14:00:07.469562 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9585 14:00:07.473034 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9586 14:00:07.476359 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9587 14:00:07.483014 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9588 14:00:07.486488 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9589 14:00:07.493419 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9590 14:00:07.496344 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9591 14:00:07.499825 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9592 14:00:07.506431 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9593 14:00:07.509892 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9594 14:00:07.513584 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9595 14:00:07.520185 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9596 14:00:07.523678 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9597 14:00:07.530061 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9598 14:00:07.533353 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9599 14:00:07.536725 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9600 14:00:07.543308 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9601 14:00:07.546651 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9602 14:00:07.550102 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9603 14:00:07.556926 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9604 14:00:07.560114 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9605 14:00:07.566610 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9606 14:00:07.570452 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9607 14:00:07.573808 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9608 14:00:07.580058 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9609 14:00:07.583795 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9610 14:00:07.590102 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9611 14:00:07.593602 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9612 14:00:07.597512 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9613 14:00:07.604046 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9614 14:00:07.607280 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9615 14:00:07.610523 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9616 14:00:07.617176 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9617 14:00:07.620838 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9618 14:00:07.626996 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9619 14:00:07.630972 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9620 14:00:07.634025 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9621 14:00:07.640611 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9622 14:00:07.643884 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9623 14:00:07.647537 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9624 14:00:07.653783 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9625 14:00:07.657237 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9626 14:00:07.663774 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9627 14:00:07.667065 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9628 14:00:07.670848 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9629 14:00:07.677070 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9630 14:00:07.680627 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9631 14:00:07.686870 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9632 14:00:07.690768 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9633 14:00:07.693601 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9634 14:00:07.700529 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9635 14:00:07.703880 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9636 14:00:07.706739 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9637 14:00:07.713661 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9638 14:00:07.716880 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9639 14:00:07.723525 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9640 14:00:07.726750 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9641 14:00:07.730288 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9642 14:00:07.736752 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9643 14:00:07.740527 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9644 14:00:07.746688 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9645 14:00:07.750259 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9646 14:00:07.753698 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9647 14:00:07.760014 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9648 14:00:07.763288 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9649 14:00:07.769999 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9650 14:00:07.773324 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9651 14:00:07.776817 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9652 14:00:07.783443 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9653 14:00:07.786914 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9654 14:00:07.793714 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9655 14:00:07.796729 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9656 14:00:07.800110 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9657 14:00:07.806781 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9658 14:00:07.810116 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9659 14:00:07.816732 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9660 14:00:07.820041 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9661 14:00:07.826941 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9662 14:00:07.829954 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9663 14:00:07.833270 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9664 14:00:07.839881 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9665 14:00:07.843277 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9666 14:00:07.849653 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9667 14:00:07.853361 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9668 14:00:07.856180 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9669 14:00:07.863119 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9670 14:00:07.866490 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9671 14:00:07.873615 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9672 14:00:07.876568 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9673 14:00:07.883230 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9674 14:00:07.886670 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9675 14:00:07.889573 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9676 14:00:07.896205 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9677 14:00:07.899546 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9678 14:00:07.906304 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9679 14:00:07.909730 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9680 14:00:07.913062 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9681 14:00:07.919439 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9682 14:00:07.923182 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9683 14:00:07.929727 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9684 14:00:07.932908 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9685 14:00:07.936401 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9686 14:00:07.942776 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9687 14:00:07.946039 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9688 14:00:07.952771 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9689 14:00:07.956102 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9690 14:00:07.963207 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9691 14:00:07.966104 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9692 14:00:07.969382 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9693 14:00:07.976245 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9694 14:00:07.979549 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9695 14:00:07.982856 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9696 14:00:07.986424 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9697 14:00:07.989671 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9698 14:00:07.996197 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9699 14:00:07.999581 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9700 14:00:08.006257 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9701 14:00:08.009531 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9702 14:00:08.012830 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9703 14:00:08.019680 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9704 14:00:08.022700 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9705 14:00:08.026138 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9706 14:00:08.032461 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9707 14:00:08.036012 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9708 14:00:08.039821 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9709 14:00:08.046199 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9710 14:00:08.049122 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9711 14:00:08.055910 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9712 14:00:08.059331 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9713 14:00:08.063100 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9714 14:00:08.069457 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9715 14:00:08.072895 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9716 14:00:08.076547 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9717 14:00:08.082679 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9718 14:00:08.086205 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9719 14:00:08.089289 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9720 14:00:08.096358 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9721 14:00:08.099282 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9722 14:00:08.106077 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9723 14:00:08.109094 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9724 14:00:08.112849 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9725 14:00:08.119299 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9726 14:00:08.122347 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9727 14:00:08.125586 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9728 14:00:08.132206 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9729 14:00:08.135610 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9730 14:00:08.142567 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9731 14:00:08.145593 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9732 14:00:08.148727 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9733 14:00:08.152283 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9734 14:00:08.159224 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9735 14:00:08.162213 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9736 14:00:08.165484 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9737 14:00:08.168694 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9738 14:00:08.175750 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9739 14:00:08.178853 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9740 14:00:08.182148 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9741 14:00:08.185488 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9742 14:00:08.192334 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9743 14:00:08.195259 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9744 14:00:08.198872 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9745 14:00:08.202583 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9746 14:00:08.208824 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9747 14:00:08.212386 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9748 14:00:08.218963 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9749 14:00:08.222323 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9750 14:00:08.225831 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9751 14:00:08.232218 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9752 14:00:08.236108 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9753 14:00:08.242441 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9754 14:00:08.245906 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9755 14:00:08.248957 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9756 14:00:08.255510 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9757 14:00:08.258803 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9758 14:00:08.265664 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9759 14:00:08.269173 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9760 14:00:08.275531 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9761 14:00:08.278951 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9762 14:00:08.282263 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9763 14:00:08.288586 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9764 14:00:08.292008 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9765 14:00:08.299064 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9766 14:00:08.302183 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9767 14:00:08.305461 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9768 14:00:08.312258 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9769 14:00:08.315288 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9770 14:00:08.318729 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9771 14:00:08.325408 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9772 14:00:08.328826 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9773 14:00:08.335126 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9774 14:00:08.338801 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9775 14:00:08.345308 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9776 14:00:08.348624 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9777 14:00:08.351734 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9778 14:00:08.358667 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9779 14:00:08.361817 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9780 14:00:08.368774 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9781 14:00:08.371790 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9782 14:00:08.375082 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9783 14:00:08.382270 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9784 14:00:08.385245 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9785 14:00:08.392271 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9786 14:00:08.395251 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9787 14:00:08.398505 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9788 14:00:08.405408 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9789 14:00:08.408656 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9790 14:00:08.415267 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9791 14:00:08.418578 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9792 14:00:08.425285 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9793 14:00:08.428354 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9794 14:00:08.432141 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9795 14:00:08.438947 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9796 14:00:08.441762 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9797 14:00:08.445238 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9798 14:00:08.452018 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9799 14:00:08.455489 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9800 14:00:08.462014 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9801 14:00:08.465266 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9802 14:00:08.468449 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9803 14:00:08.475051 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9804 14:00:08.478452 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9805 14:00:08.485336 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9806 14:00:08.488670 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9807 14:00:08.495000 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9808 14:00:08.498677 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9809 14:00:08.502168 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9810 14:00:08.508832 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9811 14:00:08.511837 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9812 14:00:08.518380 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9813 14:00:08.522346 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9814 14:00:08.525119 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9815 14:00:08.531691 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9816 14:00:08.534770 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9817 14:00:08.541725 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9818 14:00:08.544880 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9819 14:00:08.548249 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9820 14:00:08.555143 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9821 14:00:08.558408 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9822 14:00:08.564646 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9823 14:00:08.568145 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9824 14:00:08.574838 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9825 14:00:08.578212 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9826 14:00:08.581786 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9827 14:00:08.588228 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9828 14:00:08.591553 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9829 14:00:08.597949 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9830 14:00:08.601216 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9831 14:00:08.608099 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9832 14:00:08.611406 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9833 14:00:08.614351 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9834 14:00:08.620989 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9835 14:00:08.624445 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9836 14:00:08.631140 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9837 14:00:08.634560 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9838 14:00:08.641084 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9839 14:00:08.644269 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9840 14:00:08.650960 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9841 14:00:08.654688 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9842 14:00:08.657618 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9843 14:00:08.664429 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9844 14:00:08.667644 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9845 14:00:08.674789 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9846 14:00:08.678085 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9847 14:00:08.684682 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9848 14:00:08.687577 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9849 14:00:08.690939 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9850 14:00:08.697797 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9851 14:00:08.701260 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9852 14:00:08.707742 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9853 14:00:08.711000 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9854 14:00:08.717656 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9855 14:00:08.721130 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9856 14:00:08.727628 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9857 14:00:08.730983 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9858 14:00:08.734446 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9859 14:00:08.740526 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9860 14:00:08.744144 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9861 14:00:08.750851 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9862 14:00:08.753823 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9863 14:00:08.760563 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9864 14:00:08.763903 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9865 14:00:08.767113 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9866 14:00:08.773706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9867 14:00:08.777067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9868 14:00:08.784103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9869 14:00:08.787167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9870 14:00:08.794118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9871 14:00:08.797423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9872 14:00:08.803557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9873 14:00:08.806849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9874 14:00:08.813813 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9875 14:00:08.816984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9876 14:00:08.820280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9877 14:00:08.827168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9878 14:00:08.830503 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9879 14:00:08.836825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9880 14:00:08.840364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9881 14:00:08.847124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9882 14:00:08.850563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9883 14:00:08.857324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9884 14:00:08.860392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9885 14:00:08.866789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9886 14:00:08.870115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9887 14:00:08.877193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9888 14:00:08.880178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9889 14:00:08.886699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9890 14:00:08.890472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9891 14:00:08.896708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9892 14:00:08.900182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9893 14:00:08.906780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9894 14:00:08.910201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9895 14:00:08.917101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9896 14:00:08.920199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9897 14:00:08.927032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9898 14:00:08.930124 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9899 14:00:08.933425 INFO: [APUAPC] vio 0
9900 14:00:08.936775 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9901 14:00:08.943694 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9902 14:00:08.943769 INFO: [APUAPC] D0_APC_0: 0x400510
9903 14:00:08.946696 INFO: [APUAPC] D0_APC_1: 0x0
9904 14:00:08.950044 INFO: [APUAPC] D0_APC_2: 0x1540
9905 14:00:08.953474 INFO: [APUAPC] D0_APC_3: 0x0
9906 14:00:08.956923 INFO: [APUAPC] D1_APC_0: 0xffffffff
9907 14:00:08.960122 INFO: [APUAPC] D1_APC_1: 0xffffffff
9908 14:00:08.963475 INFO: [APUAPC] D1_APC_2: 0x3fffff
9909 14:00:08.966757 INFO: [APUAPC] D1_APC_3: 0x0
9910 14:00:08.969793 INFO: [APUAPC] D2_APC_0: 0xffffffff
9911 14:00:08.973436 INFO: [APUAPC] D2_APC_1: 0xffffffff
9912 14:00:08.976848 INFO: [APUAPC] D2_APC_2: 0x3fffff
9913 14:00:08.979745 INFO: [APUAPC] D2_APC_3: 0x0
9914 14:00:08.983431 INFO: [APUAPC] D3_APC_0: 0xffffffff
9915 14:00:08.986519 INFO: [APUAPC] D3_APC_1: 0xffffffff
9916 14:00:08.989690 INFO: [APUAPC] D3_APC_2: 0x3fffff
9917 14:00:08.993442 INFO: [APUAPC] D3_APC_3: 0x0
9918 14:00:08.996551 INFO: [APUAPC] D4_APC_0: 0xffffffff
9919 14:00:08.999981 INFO: [APUAPC] D4_APC_1: 0xffffffff
9920 14:00:09.003046 INFO: [APUAPC] D4_APC_2: 0x3fffff
9921 14:00:09.006622 INFO: [APUAPC] D4_APC_3: 0x0
9922 14:00:09.010033 INFO: [APUAPC] D5_APC_0: 0xffffffff
9923 14:00:09.013170 INFO: [APUAPC] D5_APC_1: 0xffffffff
9924 14:00:09.016277 INFO: [APUAPC] D5_APC_2: 0x3fffff
9925 14:00:09.020025 INFO: [APUAPC] D5_APC_3: 0x0
9926 14:00:09.023110 INFO: [APUAPC] D6_APC_0: 0xffffffff
9927 14:00:09.026498 INFO: [APUAPC] D6_APC_1: 0xffffffff
9928 14:00:09.029765 INFO: [APUAPC] D6_APC_2: 0x3fffff
9929 14:00:09.033166 INFO: [APUAPC] D6_APC_3: 0x0
9930 14:00:09.036897 INFO: [APUAPC] D7_APC_0: 0xffffffff
9931 14:00:09.039957 INFO: [APUAPC] D7_APC_1: 0xffffffff
9932 14:00:09.042942 INFO: [APUAPC] D7_APC_2: 0x3fffff
9933 14:00:09.046521 INFO: [APUAPC] D7_APC_3: 0x0
9934 14:00:09.050088 INFO: [APUAPC] D8_APC_0: 0xffffffff
9935 14:00:09.052737 INFO: [APUAPC] D8_APC_1: 0xffffffff
9936 14:00:09.055948 INFO: [APUAPC] D8_APC_2: 0x3fffff
9937 14:00:09.059474 INFO: [APUAPC] D8_APC_3: 0x0
9938 14:00:09.062485 INFO: [APUAPC] D9_APC_0: 0xffffffff
9939 14:00:09.066172 INFO: [APUAPC] D9_APC_1: 0xffffffff
9940 14:00:09.069685 INFO: [APUAPC] D9_APC_2: 0x3fffff
9941 14:00:09.069788 INFO: [APUAPC] D9_APC_3: 0x0
9942 14:00:09.076289 INFO: [APUAPC] D10_APC_0: 0xffffffff
9943 14:00:09.079856 INFO: [APUAPC] D10_APC_1: 0xffffffff
9944 14:00:09.082664 INFO: [APUAPC] D10_APC_2: 0x3fffff
9945 14:00:09.082737 INFO: [APUAPC] D10_APC_3: 0x0
9946 14:00:09.089360 INFO: [APUAPC] D11_APC_0: 0xffffffff
9947 14:00:09.092504 INFO: [APUAPC] D11_APC_1: 0xffffffff
9948 14:00:09.095892 INFO: [APUAPC] D11_APC_2: 0x3fffff
9949 14:00:09.099483 INFO: [APUAPC] D11_APC_3: 0x0
9950 14:00:09.102683 INFO: [APUAPC] D12_APC_0: 0xffffffff
9951 14:00:09.106260 INFO: [APUAPC] D12_APC_1: 0xffffffff
9952 14:00:09.109448 INFO: [APUAPC] D12_APC_2: 0x3fffff
9953 14:00:09.112780 INFO: [APUAPC] D12_APC_3: 0x0
9954 14:00:09.116248 INFO: [APUAPC] D13_APC_0: 0xffffffff
9955 14:00:09.119562 INFO: [APUAPC] D13_APC_1: 0xffffffff
9956 14:00:09.122573 INFO: [APUAPC] D13_APC_2: 0x3fffff
9957 14:00:09.125815 INFO: [APUAPC] D13_APC_3: 0x0
9958 14:00:09.129394 INFO: [APUAPC] D14_APC_0: 0xffffffff
9959 14:00:09.132837 INFO: [APUAPC] D14_APC_1: 0xffffffff
9960 14:00:09.135939 INFO: [APUAPC] D14_APC_2: 0x3fffff
9961 14:00:09.139685 INFO: [APUAPC] D14_APC_3: 0x0
9962 14:00:09.143257 INFO: [APUAPC] D15_APC_0: 0xffffffff
9963 14:00:09.146117 INFO: [APUAPC] D15_APC_1: 0xffffffff
9964 14:00:09.149243 INFO: [APUAPC] D15_APC_2: 0x3fffff
9965 14:00:09.152765 INFO: [APUAPC] D15_APC_3: 0x0
9966 14:00:09.152835 INFO: [APUAPC] APC_CON: 0x4
9967 14:00:09.156482 INFO: [NOCDAPC] D0_APC_0: 0x0
9968 14:00:09.159324 INFO: [NOCDAPC] D0_APC_1: 0x0
9969 14:00:09.162636 INFO: [NOCDAPC] D1_APC_0: 0x0
9970 14:00:09.165872 INFO: [NOCDAPC] D1_APC_1: 0xfff
9971 14:00:09.169268 INFO: [NOCDAPC] D2_APC_0: 0x0
9972 14:00:09.172429 INFO: [NOCDAPC] D2_APC_1: 0xfff
9973 14:00:09.175734 INFO: [NOCDAPC] D3_APC_0: 0x0
9974 14:00:09.179455 INFO: [NOCDAPC] D3_APC_1: 0xfff
9975 14:00:09.179568 INFO: [NOCDAPC] D4_APC_0: 0x0
9976 14:00:09.182392 INFO: [NOCDAPC] D4_APC_1: 0xfff
9977 14:00:09.185925 INFO: [NOCDAPC] D5_APC_0: 0x0
9978 14:00:09.189347 INFO: [NOCDAPC] D5_APC_1: 0xfff
9979 14:00:09.192691 INFO: [NOCDAPC] D6_APC_0: 0x0
9980 14:00:09.195934 INFO: [NOCDAPC] D6_APC_1: 0xfff
9981 14:00:09.199225 INFO: [NOCDAPC] D7_APC_0: 0x0
9982 14:00:09.202410 INFO: [NOCDAPC] D7_APC_1: 0xfff
9983 14:00:09.205788 INFO: [NOCDAPC] D8_APC_0: 0x0
9984 14:00:09.209446 INFO: [NOCDAPC] D8_APC_1: 0xfff
9985 14:00:09.209521 INFO: [NOCDAPC] D9_APC_0: 0x0
9986 14:00:09.212673 INFO: [NOCDAPC] D9_APC_1: 0xfff
9987 14:00:09.216184 INFO: [NOCDAPC] D10_APC_0: 0x0
9988 14:00:09.219490 INFO: [NOCDAPC] D10_APC_1: 0xfff
9989 14:00:09.222920 INFO: [NOCDAPC] D11_APC_0: 0x0
9990 14:00:09.226438 INFO: [NOCDAPC] D11_APC_1: 0xfff
9991 14:00:09.229107 INFO: [NOCDAPC] D12_APC_0: 0x0
9992 14:00:09.232607 INFO: [NOCDAPC] D12_APC_1: 0xfff
9993 14:00:09.236072 INFO: [NOCDAPC] D13_APC_0: 0x0
9994 14:00:09.239211 INFO: [NOCDAPC] D13_APC_1: 0xfff
9995 14:00:09.242603 INFO: [NOCDAPC] D14_APC_0: 0x0
9996 14:00:09.245860 INFO: [NOCDAPC] D14_APC_1: 0xfff
9997 14:00:09.249329 INFO: [NOCDAPC] D15_APC_0: 0x0
9998 14:00:09.252353 INFO: [NOCDAPC] D15_APC_1: 0xfff
9999 14:00:09.252428 INFO: [NOCDAPC] APC_CON: 0x4
10000 14:00:09.256107 INFO: [APUAPC] set_apusys_apc done
10001 14:00:09.259333 INFO: [DEVAPC] devapc_init done
10002 14:00:09.266133 INFO: GICv3 without legacy support detected.
10003 14:00:09.269330 INFO: ARM GICv3 driver initialized in EL3
10004 14:00:09.272829 INFO: Maximum SPI INTID supported: 639
10005 14:00:09.275975 INFO: BL31: Initializing runtime services
10006 14:00:09.282501 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10007 14:00:09.285809 INFO: SPM: enable CPC mode
10008 14:00:09.289490 INFO: mcdi ready for mcusys-off-idle and system suspend
10009 14:00:09.295932 INFO: BL31: Preparing for EL3 exit to normal world
10010 14:00:09.299186 INFO: Entry point address = 0x80000000
10011 14:00:09.299262 INFO: SPSR = 0x8
10012 14:00:09.306179
10013 14:00:09.306284
10014 14:00:09.306381
10015 14:00:09.309793 Starting depthcharge on Spherion...
10016 14:00:09.309868
10017 14:00:09.309930 Wipe memory regions:
10018 14:00:09.309989
10019 14:00:09.310781 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10020 14:00:09.310908 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10021 14:00:09.311025 Setting prompt string to ['asurada:']
10022 14:00:09.311137 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10023 14:00:09.312608 [0x00000040000000, 0x00000054600000)
10024 14:00:09.434931
10025 14:00:09.435053 [0x00000054660000, 0x00000080000000)
10026 14:00:09.695784
10027 14:00:09.695951 [0x000000821a7280, 0x000000ffe64000)
10028 14:00:10.440500
10029 14:00:10.440643 [0x00000100000000, 0x00000240000000)
10030 14:00:12.331333
10031 14:00:12.334179 Initializing XHCI USB controller at 0x11200000.
10032 14:00:13.374243
10033 14:00:13.376965 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10034 14:00:13.377432
10035 14:00:13.377795
10036 14:00:13.378131
10037 14:00:13.378934 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10039 14:00:13.480306 asurada: tftpboot 192.168.201.1 11372169/tftp-deploy-yxj2t1zm/kernel/image.itb 11372169/tftp-deploy-yxj2t1zm/kernel/cmdline
10040 14:00:13.480967 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10041 14:00:13.481461 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10042 14:00:13.487034 tftpboot 192.168.201.1 11372169/tftp-deploy-yxj2t1zm/kernel/image.itp-deploy-yxj2t1zm/kernel/cmdline
10043 14:00:13.487663
10044 14:00:13.488039 Waiting for link
10045 14:00:13.647294
10046 14:00:13.647907 R8152: Initializing
10047 14:00:13.648282
10048 14:00:13.650736 Version 9 (ocp_data = 6010)
10049 14:00:13.651304
10050 14:00:13.653169 R8152: Done initializing
10051 14:00:13.653638
10052 14:00:13.654006 Adding net device
10053 14:00:15.522089
10054 14:00:15.522585 done.
10055 14:00:15.522929
10056 14:00:15.523239 MAC: 00:e0:4c:78:7a:aa
10057 14:00:15.523725
10058 14:00:15.525298 Sending DHCP discover... done.
10059 14:00:15.525717
10060 14:00:15.527957 Waiting for reply... done.
10061 14:00:15.528376
10062 14:00:15.531702 Sending DHCP request... done.
10063 14:00:15.532125
10064 14:00:15.535222 Waiting for reply... done.
10065 14:00:15.535789
10066 14:00:15.536127 My ip is 192.168.201.12
10067 14:00:15.536440
10068 14:00:15.538320 The DHCP server ip is 192.168.201.1
10069 14:00:15.538765
10070 14:00:15.545005 TFTP server IP predefined by user: 192.168.201.1
10071 14:00:15.545540
10072 14:00:15.551282 Bootfile predefined by user: 11372169/tftp-deploy-yxj2t1zm/kernel/image.itb
10073 14:00:15.552025
10074 14:00:15.552417 Sending tftp read request... done.
10075 14:00:15.554297
10076 14:00:15.560717 Waiting for the transfer...
10077 14:00:15.561300
10078 14:00:15.849052 00000000 ################################################################
10079 14:00:15.849218
10080 14:00:16.104853 00080000 ################################################################
10081 14:00:16.104981
10082 14:00:16.366480 00100000 ################################################################
10083 14:00:16.366643
10084 14:00:16.624634 00180000 ################################################################
10085 14:00:16.624777
10086 14:00:16.881715 00200000 ################################################################
10087 14:00:16.881857
10088 14:00:17.134586 00280000 ################################################################
10089 14:00:17.134731
10090 14:00:17.390677 00300000 ################################################################
10091 14:00:17.390822
10092 14:00:17.646356 00380000 ################################################################
10093 14:00:17.646503
10094 14:00:17.901429 00400000 ################################################################
10095 14:00:17.901577
10096 14:00:18.154438 00480000 ################################################################
10097 14:00:18.154601
10098 14:00:18.409340 00500000 ################################################################
10099 14:00:18.409515
10100 14:00:18.671579 00580000 ################################################################
10101 14:00:18.671767
10102 14:00:18.963755 00600000 ################################################################
10103 14:00:18.963902
10104 14:00:19.233776 00680000 ################################################################
10105 14:00:19.233917
10106 14:00:19.488912 00700000 ################################################################
10107 14:00:19.489076
10108 14:00:19.745792 00780000 ################################################################
10109 14:00:19.745936
10110 14:00:19.999187 00800000 ################################################################
10111 14:00:19.999352
10112 14:00:20.256341 00880000 ################################################################
10113 14:00:20.256483
10114 14:00:20.508823 00900000 ################################################################
10115 14:00:20.508974
10116 14:00:20.769340 00980000 ################################################################
10117 14:00:20.769482
10118 14:00:21.023621 00a00000 ################################################################
10119 14:00:21.023800
10120 14:00:21.280251 00a80000 ################################################################
10121 14:00:21.280395
10122 14:00:21.534702 00b00000 ################################################################
10123 14:00:21.534842
10124 14:00:21.788406 00b80000 ################################################################
10125 14:00:21.788550
10126 14:00:22.040689 00c00000 ################################################################
10127 14:00:22.040833
10128 14:00:22.289595 00c80000 ################################################################
10129 14:00:22.289745
10130 14:00:22.574977 00d00000 ################################################################
10131 14:00:22.575124
10132 14:00:22.828435 00d80000 ################################################################
10133 14:00:22.828580
10134 14:00:23.085731 00e00000 ################################################################
10135 14:00:23.085900
10136 14:00:23.339220 00e80000 ################################################################
10137 14:00:23.339394
10138 14:00:23.597978 00f00000 ################################################################
10139 14:00:23.598115
10140 14:00:23.860054 00f80000 ################################################################
10141 14:00:23.860186
10142 14:00:24.120282 01000000 ################################################################
10143 14:00:24.120413
10144 14:00:24.385448 01080000 ################################################################
10145 14:00:24.385579
10146 14:00:24.643183 01100000 ################################################################
10147 14:00:24.643317
10148 14:00:24.905081 01180000 ################################################################
10149 14:00:24.905218
10150 14:00:25.175141 01200000 ################################################################
10151 14:00:25.175274
10152 14:00:25.455880 01280000 ################################################################
10153 14:00:25.456014
10154 14:00:25.721221 01300000 ################################################################
10155 14:00:25.721383
10156 14:00:25.982609 01380000 ################################################################
10157 14:00:25.982827
10158 14:00:26.246876 01400000 ################################################################
10159 14:00:26.247046
10160 14:00:26.501737 01480000 ################################################################
10161 14:00:26.501898
10162 14:00:26.755627 01500000 ################################################################
10163 14:00:26.755771
10164 14:00:27.012400 01580000 ################################################################
10165 14:00:27.012532
10166 14:00:27.267576 01600000 ################################################################
10167 14:00:27.267746
10168 14:00:27.518944 01680000 ################################################################
10169 14:00:27.519080
10170 14:00:27.770802 01700000 ################################################################
10171 14:00:27.770944
10172 14:00:28.023043 01780000 ################################################################
10173 14:00:28.023194
10174 14:00:28.277836 01800000 ################################################################
10175 14:00:28.277966
10176 14:00:28.534958 01880000 ################################################################
10177 14:00:28.535098
10178 14:00:28.795488 01900000 ################################################################
10179 14:00:28.795640
10180 14:00:29.054294 01980000 ################################################################
10181 14:00:29.054434
10182 14:00:29.305642 01a00000 ################################################################
10183 14:00:29.305783
10184 14:00:29.558074 01a80000 ################################################################
10185 14:00:29.558222
10186 14:00:29.817534 01b00000 ################################################################
10187 14:00:29.817687
10188 14:00:30.095484 01b80000 ################################################################
10189 14:00:30.095672
10190 14:00:30.353452 01c00000 ################################################################
10191 14:00:30.353607
10192 14:00:30.613219 01c80000 ################################################################
10193 14:00:30.613367
10194 14:00:30.865072 01d00000 ################################################################
10195 14:00:30.865215
10196 14:00:31.116605 01d80000 ################################################################
10197 14:00:31.116767
10198 14:00:31.371512 01e00000 ################################################################
10199 14:00:31.371666
10200 14:00:31.628362 01e80000 ################################################################
10201 14:00:31.628498
10202 14:00:31.896096 01f00000 ################################################################
10203 14:00:31.896227
10204 14:00:32.154328 01f80000 ################################################################
10205 14:00:32.154473
10206 14:00:32.410301 02000000 ################################################################
10207 14:00:32.410444
10208 14:00:32.689909 02080000 ################################################################
10209 14:00:32.690052
10210 14:00:32.939426 02100000 ################################################################
10211 14:00:32.939566
10212 14:00:33.203773 02180000 ################################################################
10213 14:00:33.203919
10214 14:00:33.485988 02200000 ################################################################
10215 14:00:33.486139
10216 14:00:33.738230 02280000 ################################################################
10217 14:00:33.738374
10218 14:00:34.020669 02300000 ################################################################
10219 14:00:34.020809
10220 14:00:34.299887 02380000 ################################################################
10221 14:00:34.300029
10222 14:00:34.576549 02400000 ################################################################
10223 14:00:34.576697
10224 14:00:34.857563 02480000 ################################################################
10225 14:00:34.857704
10226 14:00:35.142541 02500000 ################################################################
10227 14:00:35.142710
10228 14:00:35.423503 02580000 ################################################################
10229 14:00:35.423698
10230 14:00:35.679880 02600000 ################################################################
10231 14:00:35.680056
10232 14:00:35.956013 02680000 ################################################################
10233 14:00:35.956182
10234 14:00:36.216561 02700000 ################################################################
10235 14:00:36.216701
10236 14:00:36.490933 02780000 ################################################################
10237 14:00:36.491075
10238 14:00:36.741486 02800000 ################################################################
10239 14:00:36.741656
10240 14:00:37.016273 02880000 ################################################################
10241 14:00:37.016432
10242 14:00:37.294968 02900000 ################################################################
10243 14:00:37.295132
10244 14:00:37.578032 02980000 ################################################################
10245 14:00:37.578206
10246 14:00:37.848167 02a00000 ################################################################
10247 14:00:37.848301
10248 14:00:38.122543 02a80000 ################################################################
10249 14:00:38.122712
10250 14:00:38.404780 02b00000 ################################################################
10251 14:00:38.404924
10252 14:00:38.658615 02b80000 ################################################################
10253 14:00:38.658755
10254 14:00:38.955139 02c00000 ################################################################
10255 14:00:38.955278
10256 14:00:39.239696 02c80000 ################################################################
10257 14:00:39.239833
10258 14:00:39.506887 02d00000 ################################################################
10259 14:00:39.507029
10260 14:00:39.762294 02d80000 ################################################################
10261 14:00:39.762440
10262 14:00:40.048772 02e00000 ################################################################
10263 14:00:40.048913
10264 14:00:40.344361 02e80000 ################################################################
10265 14:00:40.344503
10266 14:00:40.637672 02f00000 ################################################################
10267 14:00:40.637817
10268 14:00:40.924303 02f80000 ################################################################
10269 14:00:40.924468
10270 14:00:41.195201 03000000 ################################################################
10271 14:00:41.195339
10272 14:00:41.493395 03080000 ################################################################
10273 14:00:41.493534
10274 14:00:41.789554 03100000 ################################################################
10275 14:00:41.789727
10276 14:00:42.063220 03180000 ################################################################
10277 14:00:42.063356
10278 14:00:42.329344 03200000 ################################################################
10279 14:00:42.329514
10280 14:00:42.596389 03280000 ################################################################
10281 14:00:42.596525
10282 14:00:42.845924 03300000 ################################################################
10283 14:00:42.846058
10284 14:00:43.099018 03380000 ################################################################
10285 14:00:43.099154
10286 14:00:43.351572 03400000 ################################################################
10287 14:00:43.351741
10288 14:00:43.601361 03480000 ################################################################
10289 14:00:43.601495
10290 14:00:43.864912 03500000 ################################################################
10291 14:00:43.865045
10292 14:00:44.121522 03580000 ################################################################
10293 14:00:44.121650
10294 14:00:44.382576 03600000 ################################################################
10295 14:00:44.382709
10296 14:00:44.634258 03680000 ################################################################
10297 14:00:44.634389
10298 14:00:44.884157 03700000 ################################################################
10299 14:00:44.884289
10300 14:00:45.133832 03780000 ################################################################
10301 14:00:45.133972
10302 14:00:45.386422 03800000 ################################################################
10303 14:00:45.386572
10304 14:00:45.636176 03880000 ################################################################
10305 14:00:45.636314
10306 14:00:45.885514 03900000 ################################################################
10307 14:00:45.885647
10308 14:00:46.138524 03980000 ################################################################
10309 14:00:46.138673
10310 14:00:46.393674 03a00000 ################################################################
10311 14:00:46.393813
10312 14:00:46.655522 03a80000 ################################################################
10313 14:00:46.655687
10314 14:00:46.905410 03b00000 ################################################################
10315 14:00:46.905548
10316 14:00:47.154945 03b80000 ################################################################
10317 14:00:47.155082
10318 14:00:47.404502 03c00000 ################################################################
10319 14:00:47.404662
10320 14:00:47.655800 03c80000 ################################################################
10321 14:00:47.655964
10322 14:00:47.928067 03d00000 ################################################################
10323 14:00:47.928215
10324 14:00:48.206858 03d80000 ################################################################
10325 14:00:48.207006
10326 14:00:48.499439 03e00000 ################################################################
10327 14:00:48.499582
10328 14:00:48.764787 03e80000 ################################################################
10329 14:00:48.764935
10330 14:00:49.038214 03f00000 ################################################################
10331 14:00:49.038361
10332 14:00:49.332642 03f80000 ################################################################
10333 14:00:49.332809
10334 14:00:49.626972 04000000 ################################################################
10335 14:00:49.627121
10336 14:00:49.919351 04080000 ################################################################
10337 14:00:49.919499
10338 14:00:50.196389 04100000 ################################################################
10339 14:00:50.196534
10340 14:00:50.491116 04180000 ################################################################
10341 14:00:50.491263
10342 14:00:50.768453 04200000 ################################################################
10343 14:00:50.768605
10344 14:00:51.055405 04280000 ################################################################
10345 14:00:51.055550
10346 14:00:51.347101 04300000 ################################################################
10347 14:00:51.347243
10348 14:00:51.641843 04380000 ################################################################
10349 14:00:51.642005
10350 14:00:51.936488 04400000 ################################################################
10351 14:00:51.936631
10352 14:00:52.216456 04480000 ################################################################
10353 14:00:52.216597
10354 14:00:52.500477 04500000 ################################################################
10355 14:00:52.500618
10356 14:00:52.763011 04580000 ################################################################
10357 14:00:52.763152
10358 14:00:53.043213 04600000 ################################################################
10359 14:00:53.043357
10360 14:00:53.339625 04680000 ################################################################
10361 14:00:53.339777
10362 14:00:53.611973 04700000 ################################################################
10363 14:00:53.612116
10364 14:00:53.865169 04780000 ################################################################
10365 14:00:53.865320
10366 14:00:54.114681 04800000 ################################################################
10367 14:00:54.114818
10368 14:00:54.401476 04880000 ################################################################
10369 14:00:54.401616
10370 14:00:54.698936 04900000 ################################################################
10371 14:00:54.699078
10372 14:00:54.996099 04980000 ################################################################
10373 14:00:54.996246
10374 14:00:55.284405 04a00000 ################################################################
10375 14:00:55.284545
10376 14:00:55.545900 04a80000 ################################################################
10377 14:00:55.546078
10378 14:00:55.838171 04b00000 ################################################################
10379 14:00:55.838320
10380 14:00:56.134645 04b80000 ################################################################
10381 14:00:56.134802
10382 14:00:56.427289 04c00000 ################################################################
10383 14:00:56.427441
10384 14:00:56.717686 04c80000 ################################################################
10385 14:00:56.717835
10386 14:00:56.996097 04d00000 ################################################################
10387 14:00:56.996239
10388 14:00:57.290782 04d80000 ################################################################
10389 14:00:57.290925
10390 14:00:57.587759 04e00000 ################################################################
10391 14:00:57.587895
10392 14:00:57.881981 04e80000 ################################################################
10393 14:00:57.882124
10394 14:00:58.177576 04f00000 ################################################################
10395 14:00:58.177720
10396 14:00:58.474231 04f80000 ################################################################
10397 14:00:58.474395
10398 14:00:58.763410 05000000 ################################################################
10399 14:00:58.763549
10400 14:00:59.013607 05080000 ################################################################
10401 14:00:59.013773
10402 14:00:59.269130 05100000 ################################################################
10403 14:00:59.269293
10404 14:00:59.544708 05180000 ################################################################
10405 14:00:59.544873
10406 14:00:59.829136 05200000 ################################################################
10407 14:00:59.829304
10408 14:01:00.094544 05280000 ################################################################
10409 14:01:00.094710
10410 14:01:00.390392 05300000 ################################################################
10411 14:01:00.390561
10412 14:01:00.688442 05380000 ################################################################
10413 14:01:00.688605
10414 14:01:00.971126 05400000 ################################################################
10415 14:01:00.971295
10416 14:01:01.266285 05480000 ################################################################
10417 14:01:01.266451
10418 14:01:01.545461 05500000 ################################################################
10419 14:01:01.545622
10420 14:01:01.806457 05580000 ################################################################
10421 14:01:01.806605
10422 14:01:02.070853 05600000 ################################################################
10423 14:01:02.071020
10424 14:01:02.340308 05680000 ################################################################
10425 14:01:02.340448
10426 14:01:02.631506 05700000 ################################################################
10427 14:01:02.631663
10428 14:01:02.905101 05780000 ################################################################
10429 14:01:02.905268
10430 14:01:03.182405 05800000 ################################################################
10431 14:01:03.182567
10432 14:01:03.455702 05880000 ################################################################
10433 14:01:03.455873
10434 14:01:03.723568 05900000 ################################################################
10435 14:01:03.723715
10436 14:01:03.994431 05980000 ################################################################
10437 14:01:03.994607
10438 14:01:04.258862 05a00000 ################################################################
10439 14:01:04.259020
10440 14:01:04.539006 05a80000 ################################################################
10441 14:01:04.539186
10442 14:01:04.812959 05b00000 ################################################################
10443 14:01:04.813126
10444 14:01:05.107529 05b80000 ################################################################
10445 14:01:05.107694
10446 14:01:05.397102 05c00000 ################################################################
10447 14:01:05.397282
10448 14:01:05.668805 05c80000 ################################################################
10449 14:01:05.668979
10450 14:01:05.931541 05d00000 ################################################################
10451 14:01:05.931700
10452 14:01:06.217115 05d80000 ################################################################
10453 14:01:06.217291
10454 14:01:06.497987 05e00000 ################################################################
10455 14:01:06.498165
10456 14:01:06.756599 05e80000 ################################################################
10457 14:01:06.756775
10458 14:01:07.032015 05f00000 ################################################################
10459 14:01:07.032193
10460 14:01:07.306083 05f80000 ################################################################
10461 14:01:07.306258
10462 14:01:07.601679 06000000 ################################################################
10463 14:01:07.601854
10464 14:01:07.868435 06080000 ################################################################
10465 14:01:07.868628
10466 14:01:08.147662 06100000 ################################################################
10467 14:01:08.147812
10468 14:01:08.397850 06180000 ################################################################
10469 14:01:08.397996
10470 14:01:08.681858 06200000 ################################################################
10471 14:01:08.682030
10472 14:01:08.970517 06280000 ################################################################
10473 14:01:08.970662
10474 14:01:09.265071 06300000 ################################################################
10475 14:01:09.265248
10476 14:01:09.540564 06380000 ################################################################
10477 14:01:09.540711
10478 14:01:09.819657 06400000 ################################################################
10479 14:01:09.819803
10480 14:01:10.107487 06480000 ################################################################
10481 14:01:10.107677
10482 14:01:10.390424 06500000 ################################################################
10483 14:01:10.390600
10484 14:01:10.657975 06580000 ################################################################
10485 14:01:10.658122
10486 14:01:10.925229 06600000 ################################################################
10487 14:01:10.925382
10488 14:01:11.190834 06680000 ################################################################
10489 14:01:11.191007
10490 14:01:11.466038 06700000 ################################################################
10491 14:01:11.466185
10492 14:01:11.732627 06780000 ################################################################
10493 14:01:11.732776
10494 14:01:11.902742 06800000 ########################################### done.
10495 14:01:11.902887
10496 14:01:11.906203 The bootfile was 109396562 bytes long.
10497 14:01:11.906291
10498 14:01:11.909494 Sending tftp read request... done.
10499 14:01:11.909577
10500 14:01:11.912666 Waiting for the transfer...
10501 14:01:11.912750
10502 14:01:11.912815 00000000 # done.
10503 14:01:11.912879
10504 14:01:11.919377 Command line loaded dynamically from TFTP file: 11372169/tftp-deploy-yxj2t1zm/kernel/cmdline
10505 14:01:11.919461
10506 14:01:11.932673 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10507 14:01:11.935730
10508 14:01:11.935811 Loading FIT.
10509 14:01:11.935874
10510 14:01:11.939385 Image ramdisk-1 has 98307415 bytes.
10511 14:01:11.939465
10512 14:01:11.942848 Image fdt-1 has 47278 bytes.
10513 14:01:11.942930
10514 14:01:11.942995 Image kernel-1 has 11039834 bytes.
10515 14:01:11.946056
10516 14:01:11.952634 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10517 14:01:11.952717
10518 14:01:11.972242 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10519 14:01:11.972331
10520 14:01:11.975762 Choosing best match conf-1 for compat google,spherion-rev2.
10521 14:01:11.979975
10522 14:01:11.984768 Connected to device vid:did:rid of 1ae0:0028:00
10523 14:01:11.992785
10524 14:01:11.996429 tpm_get_response: command 0x17b, return code 0x0
10525 14:01:11.996512
10526 14:01:11.999410 ec_init: CrosEC protocol v3 supported (256, 248)
10527 14:01:12.004917
10528 14:01:12.007961 tpm_cleanup: add release locality here.
10529 14:01:12.008044
10530 14:01:12.008109 Shutting down all USB controllers.
10531 14:01:12.008169
10532 14:01:12.011013 Removing current net device
10533 14:01:12.011095
10534 14:01:12.017613 Exiting depthcharge with code 4 at timestamp: 91984368
10535 14:01:12.017696
10536 14:01:12.020912 LZMA decompressing kernel-1 to 0x821a6718
10537 14:01:12.020995
10538 14:01:12.024901 LZMA decompressing kernel-1 to 0x40000000
10539 14:01:13.412958
10540 14:01:13.413116 jumping to kernel
10541 14:01:13.413583 end: 2.2.4 bootloader-commands (duration 00:01:04) [common]
10542 14:01:13.413688 start: 2.2.5 auto-login-action (timeout 00:03:21) [common]
10543 14:01:13.413764 Setting prompt string to ['Linux version [0-9]']
10544 14:01:13.413832 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10545 14:01:13.413900 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10546 14:01:13.495426
10547 14:01:13.498658 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10548 14:01:13.502239 start: 2.2.5.1 login-action (timeout 00:03:21) [common]
10549 14:01:13.502342 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10550 14:01:13.502416 Setting prompt string to []
10551 14:01:13.502499 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10552 14:01:13.502575 Using line separator: #'\n'#
10553 14:01:13.502636 No login prompt set.
10554 14:01:13.502697 Parsing kernel messages
10555 14:01:13.502753 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10556 14:01:13.502854 [login-action] Waiting for messages, (timeout 00:03:21)
10557 14:01:13.522181 [ 0.000000] Linux version 6.1.46-cip4-rt2 (KernelCI@build-j25372-arm64-gcc-10-defconfig-arm64-chromebook-2wz78) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 28 13:41:26 UTC 2023
10558 14:01:13.525442 [ 0.000000] random: crng init done
10559 14:01:13.531824 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10560 14:01:13.535450 [ 0.000000] efi: UEFI not found.
10561 14:01:13.541948 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10562 14:01:13.548928 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10563 14:01:13.558601 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10564 14:01:13.568335 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10565 14:01:13.575355 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10566 14:01:13.581455 [ 0.000000] printk: bootconsole [mtk8250] enabled
10567 14:01:13.588197 [ 0.000000] NUMA: No NUMA configuration found
10568 14:01:13.594742 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10569 14:01:13.598095 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10570 14:01:13.601268 [ 0.000000] Zone ranges:
10571 14:01:13.608224 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10572 14:01:13.612095 [ 0.000000] DMA32 empty
10573 14:01:13.617991 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10574 14:01:13.621304 [ 0.000000] Movable zone start for each node
10575 14:01:13.624678 [ 0.000000] Early memory node ranges
10576 14:01:13.631545 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10577 14:01:13.638090 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10578 14:01:13.644748 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10579 14:01:13.651337 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10580 14:01:13.657770 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10581 14:01:13.664145 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10582 14:01:13.719596 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10583 14:01:13.726333 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10584 14:01:13.733231 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10585 14:01:13.736288 [ 0.000000] psci: probing for conduit method from DT.
10586 14:01:13.743124 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10587 14:01:13.746226 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10588 14:01:13.752987 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10589 14:01:13.756323 [ 0.000000] psci: SMC Calling Convention v1.2
10590 14:01:13.763159 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10591 14:01:13.766117 [ 0.000000] Detected VIPT I-cache on CPU0
10592 14:01:13.773019 [ 0.000000] CPU features: detected: GIC system register CPU interface
10593 14:01:13.779485 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10594 14:01:13.786654 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10595 14:01:13.793026 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10596 14:01:13.799931 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10597 14:01:13.806456 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10598 14:01:13.813190 [ 0.000000] alternatives: applying boot alternatives
10599 14:01:13.816259 [ 0.000000] Fallback order for Node 0: 0
10600 14:01:13.822811 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10601 14:01:13.826037 [ 0.000000] Policy zone: Normal
10602 14:01:13.843023 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10603 14:01:13.852624 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10604 14:01:13.864289 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10605 14:01:13.874050 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10606 14:01:13.880928 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10607 14:01:13.884021 <6>[ 0.000000] software IO TLB: area num 8.
10608 14:01:13.940672 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10609 14:01:14.089664 <6>[ 0.000000] Memory: 7873488K/8385536K available (17984K kernel code, 4100K rwdata, 17468K rodata, 8384K init, 615K bss, 479280K reserved, 32768K cma-reserved)
10610 14:01:14.096542 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10611 14:01:14.102890 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10612 14:01:14.106329 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10613 14:01:14.112721 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10614 14:01:14.119309 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10615 14:01:14.123137 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10616 14:01:14.132900 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10617 14:01:14.139131 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10618 14:01:14.146020 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10619 14:01:14.152495 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10620 14:01:14.156191 <6>[ 0.000000] GICv3: 608 SPIs implemented
10621 14:01:14.159044 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10622 14:01:14.165899 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10623 14:01:14.168991 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10624 14:01:14.175717 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10625 14:01:14.188844 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10626 14:01:14.202497 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10627 14:01:14.208383 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10628 14:01:14.216586 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10629 14:01:14.229595 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10630 14:01:14.236141 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10631 14:01:14.243296 <6>[ 0.009234] Console: colour dummy device 80x25
10632 14:01:14.253307 <6>[ 0.013955] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10633 14:01:14.256668 <6>[ 0.024399] pid_max: default: 32768 minimum: 301
10634 14:01:14.262979 <6>[ 0.029269] LSM: Security Framework initializing
10635 14:01:14.269747 <6>[ 0.034208] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10636 14:01:14.279573 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10637 14:01:14.286196 <6>[ 0.051491] cblist_init_generic: Setting adjustable number of callback queues.
10638 14:01:14.293069 <6>[ 0.058983] cblist_init_generic: Setting shift to 3 and lim to 1.
10639 14:01:14.303060 <6>[ 0.065322] cblist_init_generic: Setting adjustable number of callback queues.
10640 14:01:14.306299 <6>[ 0.072748] cblist_init_generic: Setting shift to 3 and lim to 1.
10641 14:01:14.313495 <6>[ 0.079187] rcu: Hierarchical SRCU implementation.
10642 14:01:14.319510 <6>[ 0.079189] rcu: Max phase no-delay instances is 1000.
10643 14:01:14.326837 <6>[ 0.079214] printk: bootconsole [mtk8250] printing thread started
10644 14:01:14.332918 <6>[ 0.097514] EFI services will not be available.
10645 14:01:14.336441 <6>[ 0.097715] smp: Bringing up secondary CPUs ...
10646 14:01:14.339343 <6>[ 0.098025] Detected VIPT I-cache on CPU1
10647 14:01:14.346617 <6>[ 0.098095] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10648 14:01:14.353160 <6>[ 0.098126] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10649 14:01:14.364878 <6>[ 0.125951] Detected VIPT I-cache on CPU2
10650 14:01:14.371020 <6>[ 0.126001] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10651 14:01:14.381112 <6>[ 0.126018] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10652 14:01:14.384550 <6>[ 0.126281] Detected VIPT I-cache on CPU3
10653 14:01:14.391554 <6>[ 0.126328] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10654 14:01:14.397737 <6>[ 0.126341] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10655 14:01:14.401522 <6>[ 0.126651] CPU features: detected: Spectre-v4
10656 14:01:14.407749 <6>[ 0.126657] CPU features: detected: Spectre-BHB
10657 14:01:14.411132 <6>[ 0.126663] Detected PIPT I-cache on CPU4
10658 14:01:14.417767 <6>[ 0.126724] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10659 14:01:14.424289 <6>[ 0.126741] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10660 14:01:14.431126 <6>[ 0.127032] Detected PIPT I-cache on CPU5
10661 14:01:14.437467 <6>[ 0.127093] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10662 14:01:14.444171 <6>[ 0.127110] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10663 14:01:14.448021 <6>[ 0.127385] Detected PIPT I-cache on CPU6
10664 14:01:14.454121 <6>[ 0.127450] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10665 14:01:14.460842 <6>[ 0.127466] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10666 14:01:14.467653 <6>[ 0.127759] Detected PIPT I-cache on CPU7
10667 14:01:14.474209 <6>[ 0.127824] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10668 14:01:14.481012 <6>[ 0.127840] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10669 14:01:14.484172 <6>[ 0.127886] smp: Brought up 1 node, 8 CPUs
10670 14:01:14.490758 <6>[ 0.127891] SMP: Total of 8 processors activated.
10671 14:01:14.493996 <6>[ 0.127894] CPU features: detected: 32-bit EL0 Support
10672 14:01:14.504239 <6>[ 0.127896] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10673 14:01:14.510723 <6>[ 0.127898] CPU features: detected: Common not Private translations
10674 14:01:14.517541 <6>[ 0.127900] CPU features: detected: CRC32 instructions
10675 14:01:14.520761 <6>[ 0.127902] CPU features: detected: RCpc load-acquire (LDAPR)
10676 14:01:14.527207 <6>[ 0.127904] CPU features: detected: LSE atomic instructions
10677 14:01:14.533962 <6>[ 0.127906] CPU features: detected: Privileged Access Never
10678 14:01:14.540558 <6>[ 0.127907] CPU features: detected: RAS Extension Support
10679 14:01:14.547493 <6>[ 0.127910] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10680 14:01:14.550508 <6>[ 0.127976] CPU: All CPU(s) started at EL2
10681 14:01:14.556924 <6>[ 0.127977] alternatives: applying system-wide alternatives
10682 14:01:14.584632 ��}ٳ�r�jR�<6>[ 0.3<48523] printk: console [ttyS0] printing thread started
10683 14:01:14.587630 6<6>[ 0.348554] printk: console [ttyS0] enabled
10684 14:01:14.594445 >[ 0.225494] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10685 14:01:14.603255 <6>[ 0.348558] printk: bootconsole [mtk8250] disabled
10686 14:01:14.609616 <6>[ 0.365939] printk: bootconsole [mtk8250] printing thread stopped
10687 14:01:14.613494 <6>[ 0.366910] SuperH (H)SCI(F) driver initialized
10688 14:01:14.619707 <6>[ 0.367382] msm_serial: driver initialized
10689 14:01:14.626184 <6>[ 0.371881] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10690 14:01:14.636287 <6>[ 0.371909] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10691 14:01:14.642956 <6>[ 0.371938] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10692 14:01:14.662341 <6>[ 0.371967] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10693 14:01:14.671167 <6>[ 0.371987] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10694 14:01:14.671528 <6>[ 0.372017] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10695 14:01:14.687822 <6>[ 0.372046] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10696 14:01:14.687968 <6>[ 0.372149] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10697 14:01:14.697599 <6>[ 0.372178] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10698 14:01:14.701975 <6>[ 0.384374] loop: module loaded
10699 14:01:14.705686 <6>[ 0.386936] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10700 14:01:14.710226 <4>[ 0.403427] mtk-pmic-keys: Failed to locate of_node [id: -1]
10701 14:01:14.717056 <6>[ 0.404183] megasas: 07.719.03.00-rc1
10702 14:01:14.723741 <6>[ 0.416777] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10703 14:01:14.727224 <6>[ 0.416862] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10704 14:01:14.733606 <6>[ 0.428630] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10705 14:01:14.743751 <6>[ 0.482931] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10706 14:01:18.430685 <6>[ 4.196949] Freeing initrd memory: 96000K
10707 14:01:18.438751 <6>[ 4.203068] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10708 14:01:18.445559 <6>[ 4.207636] tun: Universal TUN/TAP device driver, 1.6
10709 14:01:18.448625 <6>[ 4.208380] thunder_xcv, ver 1.0
10710 14:01:18.452018 <6>[ 4.208397] thunder_bgx, ver 1.0
10711 14:01:18.454991 <6>[ 4.208413] nicpf, ver 1.0
10712 14:01:18.461840 <6>[ 4.209474] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10713 14:01:18.468246 <6>[ 4.209477] hns3: Copyright (c) 2017 Huawei Corporation.
10714 14:01:18.471901 <6>[ 4.209501] hclge is initializing
10715 14:01:18.478328 <6>[ 4.209517] e1000: Intel(R) PRO/1000 Network Driver
10716 14:01:18.482231 <6>[ 4.209519] e1000: Copyright (c) 1999-2006 Intel Corporation.
10717 14:01:18.489233 <6>[ 4.209538] e1000e: Intel(R) PRO/1000 Network Driver
10718 14:01:18.496029 <6>[ 4.209540] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10719 14:01:18.499306 <6>[ 4.209555] igb: Intel(R) Gigabit Ethernet Network Driver
10720 14:01:18.505888 <6>[ 4.209557] igb: Copyright (c) 2007-2014 Intel Corporation.
10721 14:01:18.512797 <6>[ 4.209570] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10722 14:01:18.519820 <6>[ 4.209572] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10723 14:01:18.522724 <6>[ 4.209865] sky2: driver version 1.30
10724 14:01:18.526130 <6>[ 4.210927] VFIO - User Level meta-driver version: 0.3
10725 14:01:18.532663 <6>[ 4.213732] usbcore: registered new interface driver usb-storage
10726 14:01:18.539562 <6>[ 4.213917] usbcore: registered new device driver onboard-usb-hub
10727 14:01:18.546058 <6>[ 4.216643] mt6397-rtc mt6359-rtc: registered as rtc0
10728 14:01:18.555577 <6>[ 4.216792] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-28T14:00:14 UTC (1693231214)
10729 14:01:18.559181 <6>[ 4.217407] i2c_dev: i2c /dev entries driver
10730 14:01:18.566010 <6>[ 4.224494] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10731 14:01:18.572606 <6>[ 4.239486] cpu cpu0: EM: created perf domain
10732 14:01:18.575886 <6>[ 4.239721] cpu cpu4: EM: created perf domain
10733 14:01:18.582398 <6>[ 4.243551] sdhci: Secure Digital Host Controller Interface driver
10734 14:01:18.588725 <6>[ 4.243552] sdhci: Copyright(c) Pierre Ossman
10735 14:01:18.592334 <6>[ 4.243921] Synopsys Designware Multimedia Card Interface Driver
10736 14:01:18.599058 <6>[ 4.244298] sdhci-pltfm: SDHCI platform and OF driver helper
10737 14:01:18.605882 <6>[ 4.248559] ledtrig-cpu: registered to indicate activity on CPUs
10738 14:01:18.609276 <6>[ 4.249223] mmc0: CQHCI version 5.10
10739 14:01:18.615515 <6>[ 4.249245] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10740 14:01:18.622134 <6>[ 4.249536] usbcore: registered new interface driver usbhid
10741 14:01:18.625532 <6>[ 4.249537] usbhid: USB HID core driver
10742 14:01:18.632490 <6>[ 4.249664] spi_master spi0: will run message pump with realtime priority
10743 14:01:18.645648 <6>[ 4.281386] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10744 14:01:18.658389 <6>[ 4.284066] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10745 14:01:18.665154 <6>[ 4.285132] cros-ec-spi spi0.0: Chrome EC device registered
10746 14:01:18.675258 <6>[ 4.297334] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10747 14:01:18.678539 <6>[ 4.298279] NET: Registered PF_PACKET protocol family
10748 14:01:18.685304 <6>[ 4.298346] 9pnet: Installing 9P2000 support
10749 14:01:18.688772 <5>[ 4.298381] Key type dns_resolver registered
10750 14:01:18.691625 <6>[ 4.298738] registered taskstats version 1
10751 14:01:18.698395 <5>[ 4.298752] Loading compiled-in X.509 certificates
10752 14:01:18.708440 <4>[ 4.314933] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10753 14:01:18.718159 <4>[ 4.315118] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10754 14:01:18.725123 <3>[ 4.315128] debugfs: File 'uA_load' in directory '/' already present!
10755 14:01:18.731521 <3>[ 4.315136] debugfs: File 'min_uV' in directory '/' already present!
10756 14:01:18.738096 <3>[ 4.315139] debugfs: File 'max_uV' in directory '/' already present!
10757 14:01:18.744790 <3>[ 4.315142] debugfs: File 'constraint_flags' in directory '/' already present!
10758 14:01:18.755010 <3>[ 4.317063] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10759 14:01:18.761808 <6>[ 4.324223] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10760 14:01:18.767859 <6>[ 4.324781] xhci-mtk 11200000.usb: xHCI Host Controller
10761 14:01:18.774478 <6>[ 4.324797] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10762 14:01:18.784496 <6>[ 4.325010] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10763 14:01:18.791425 <6>[ 4.325059] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10764 14:01:18.794536 <6>[ 4.325153] xhci-mtk 11200000.usb: xHCI Host Controller
10765 14:01:18.804543 <6>[ 4.325160] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10766 14:01:18.810961 <6>[ 4.325166] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10767 14:01:18.814311 <6>[ 4.325716] hub 1-0:1.0: USB hub found
10768 14:01:18.817659 <6>[ 4.325741] hub 1-0:1.0: 1 port detected
10769 14:01:18.827473 <6>[ 4.326313] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10770 14:01:18.831111 <6>[ 4.326866] hub 2-0:1.0: USB hub found
10771 14:01:18.834267 <6>[ 4.326935] hub 2-0:1.0: 1 port detected
10772 14:01:18.840630 <6>[ 4.329489] mtk-msdc 11f70000.mmc: Got CD GPIO
10773 14:01:18.847782 <6>[ 4.336525] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10774 14:01:18.854141 <6>[ 4.336532] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10775 14:01:18.864265 <4>[ 4.336624] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10776 14:01:18.870852 <6>[ 4.337117] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10777 14:01:18.881126 <6>[ 4.337118] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10778 14:01:18.887623 <6>[ 4.337460] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10779 14:01:18.897260 <6>[ 4.337474] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10780 14:01:18.903766 <6>[ 4.337477] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10781 14:01:18.913801 <6>[ 4.337482] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10782 14:01:18.920332 <6>[ 4.338882] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10783 14:01:18.930174 <6>[ 4.338896] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10784 14:01:18.936927 <6>[ 4.338898] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10785 14:01:18.947147 <6>[ 4.338901] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10786 14:01:18.953376 <6>[ 4.338904] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10787 14:01:18.963619 <6>[ 4.338907] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10788 14:01:18.970213 <6>[ 4.338911] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10789 14:01:18.980094 <6>[ 4.338913] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10790 14:01:18.986400 <6>[ 4.338916] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10791 14:01:18.996645 <6>[ 4.338920] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10792 14:01:19.003113 <6>[ 4.338923] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10793 14:01:19.013745 <6>[ 4.338926] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10794 14:01:19.020212 <6>[ 4.338929] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10795 14:01:19.030022 <6>[ 4.338932] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10796 14:01:19.036483 <6>[ 4.338935] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10797 14:01:19.042900 <6>[ 4.339284] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10798 14:01:19.049428 <6>[ 4.339849] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10799 14:01:19.056562 <6>[ 4.340069] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10800 14:01:19.062549 <6>[ 4.340301] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10801 14:01:19.069509 <6>[ 4.340536] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10802 14:01:19.079151 <6>[ 4.340703] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10803 14:01:19.089363 <6>[ 4.340717] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10804 14:01:19.099101 <6>[ 4.340722] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10805 14:01:19.108923 <6>[ 4.340726] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10806 14:01:19.115398 <6>[ 4.340730] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10807 14:01:19.125327 <6>[ 4.340735] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10808 14:01:19.135625 <6>[ 4.340739] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10809 14:01:19.145534 <6>[ 4.340743] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10810 14:01:19.155146 <6>[ 4.340748] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10811 14:01:19.165222 <6>[ 4.340753] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10812 14:01:19.175192 <6>[ 4.340756] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10813 14:01:19.181740 <6>[ 4.341214] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10814 14:01:19.188643 <6>[ 4.343480] mmc0: Command Queue Engine enabled
10815 14:01:19.195110 <6>[ 4.343494] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10816 14:01:19.198403 <6>[ 4.343948] mmcblk0: mmc0:0001 DA4128 116 GiB
10817 14:01:19.205230 <6>[ 4.347185] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10818 14:01:19.211468 <6>[ 4.348410] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10819 14:01:19.215069 <6>[ 4.348965] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10820 14:01:19.221771 <6>[ 4.349763] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10821 14:01:19.228145 <6>[ 4.709700] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10822 14:01:19.231602 <6>[ 4.736729] hub 2-1:1.0: USB hub found
10823 14:01:19.238538 <6>[ 4.737171] hub 2-1:1.0: 3 ports detected
10824 14:01:19.244982 <6>[ 4.857426] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10825 14:01:19.248217 <6>[ 5.010543] hub 1-1:1.0: USB hub found
10826 14:01:19.251341 <6>[ 5.010918] hub 1-1:1.0: 4 ports detected
10827 14:01:19.326446 <6>[ 5.085876] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10828 14:01:19.562001 <6>[ 5.321676] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10829 14:01:19.686637 <6>[ 5.449507] hub 1-1.4:1.0: USB hub found
10830 14:01:19.689867 <6>[ 5.449977] hub 1-1.4:1.0: 2 ports detected
10831 14:01:19.977890 <6>[ 5.737642] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10832 14:01:20.161957 <6>[ 5.921648] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10833 14:01:30.875096 <6>[ 16.642469] ALSA device list:
10834 14:01:30.881816 <6>[ 16.642490] No soundcards found.
10835 14:01:30.884721 <6>[ 16.647006] Freeing unused kernel memory: 8384K
10836 14:01:30.887586 <6>[ 16.647176] Run /init as init process
10837 14:01:30.922056 <6>[ 16.689009] NET: Registered PF_INET6 protocol family
10838 14:01:30.924836 <6>[ 16.690298] Segment Routing with IPv6
10839 14:01:30.931174 <6>[ 16.690311] In-situ OAM (IOAM) with IPv6
10840 14:01:30.938356
10841 14:01:30.961514 Welcome to [1mD<30>[ 16.708246] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10842 14:01:30.968449 <30>[ 16.708809] systemd[1]: Detected architecture arm64.
10843 14:01:30.971545 ebian GNU/Linux 11 (bullseye)[0m!
10844 14:01:30.972145
10845 14:01:30.989883 <30>[ 16.753539] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10846 14:01:31.157474 <30>[ 16.920554] systemd[1]: Queued start job for default target Graphical Interface.
10847 14:01:31.187194 [[0;32m OK [0m] Created slic<30>[ 16.950668] systemd[1]: Created slice system-getty.slice.
10848 14:01:31.189998 e [0;1;39msystem-getty.slice[0m.
10849 14:01:31.210934 [[0;32m OK [0m] Created slic<30>[ 16.975126] systemd[1]: Created slice system-modprobe.slice.
10850 14:01:31.214631 e [0;1;39msystem-modprobe.slice[0m.
10851 14:01:31.234977 [[0;32m OK [0m] Created slic<30>[ 16.998533] systemd[1]: Created slice system-serial\x2dgetty.slice.
10852 14:01:31.240735 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10853 14:01:31.259239 [[0;32m OK [0m] Created slic<30>[ 17.023414] systemd[1]: Created slice User and Session Slice.
10854 14:01:31.262683 e [0;1;39mUser and Session Slice[0m.
10855 14:01:31.285787 [[0;32m OK [0m] Started [0;<30>[ 17.046475] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10856 14:01:31.289067 1;39mDispatch Password …ts to Console Directory Watch[0m.
10857 14:01:31.314161 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 17.074375] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10858 14:01:31.317368 sword R…uests to Wall Directory Watch[0m.
10859 14:01:31.344648 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 17.102126] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10860 14:01:31.351358 <30>[ 17.102371] systemd[1]: Reached target Local Encrypted Volumes.
10861 14:01:31.355052 l Encrypted Volumes[0m.
10862 14:01:31.374170 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 17.138147] systemd[1]: Reached target Paths.
10863 14:01:31.374718 s[0m.
10864 14:01:31.393514 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 17.157623] systemd[1]: Reached target Remote File Systems.
10865 14:01:31.397111 te File Systems[0m.
10866 14:01:31.418404 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 17.182012] systemd[1]: Reached target Slices.
10867 14:01:31.418971 es[0m.
10868 14:01:31.437350 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 17.201660] systemd[1]: Reached target Swap.
10869 14:01:31.437895 [0m.
10870 14:01:31.461501 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 17.222146] systemd[1]: Listening on initctl Compatibility Named Pipe.
10871 14:01:31.464616 l Compatibility Named Pipe[0m.
10872 14:01:31.471308 <30>[ 17.237297] systemd[1]: Listening on Journal Audit Socket.
10873 14:01:31.477987 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10874 14:01:31.494815 [[0;32m OK [0m] Listening on<30>[ 17.258811] systemd[1]: Listening on Journal Socket (/dev/log).
10875 14:01:31.498276 [0;1;39mJournal Socket (/dev/log)[0m.
10876 14:01:31.518853 [[0;32m OK [0m] Listening on<30>[ 17.282857] systemd[1]: Listening on Journal Socket.
10877 14:01:31.522017 [0;1;39mJournal Socket[0m.
10878 14:01:31.538356 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 17.302199] systemd[1]: Listening on udev Control Socket.
10879 14:01:31.541306 ontrol Socket[0m.
10880 14:01:31.563142 [[0;32m OK [0m] Listening on<30>[ 17.326660] systemd[1]: Listening on udev Kernel Socket.
10881 14:01:31.566084 [0;1;39mudev Kernel Socket[0m.
10882 14:01:31.618267 Mounting [0;1;39mHuge Pages File Syste<30>[ 17.382144] systemd[1]: Mounting Huge Pages File System...
10883 14:01:31.621429 m[0m...
10884 14:01:31.644782 Mounting [0;1;39mPOSIX Message Queue F<30>[ 17.405797] systemd[1]: Mounting POSIX Message Queue File System...
10885 14:01:31.645332 ile System[0m...
10886 14:01:31.673112 Mounting [0;1;39mKernel Debug File Sys<30>[ 17.433766] systemd[1]: Mounting Kernel Debug File System...
10887 14:01:31.673698 tem[0m...
10888 14:01:31.693099 <30>[ 17.454250] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10889 14:01:31.702821 <30>[ 17.458774] systemd[1]: Starting Create list of static device nodes for the current kernel...
10890 14:01:31.710021 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10891 14:01:31.737611 Starting [0;1;39mLoad Kernel Module co<30>[ 17.498139] systemd[1]: Starting Load Kernel Module configfs...
10892 14:01:31.738154 nfigfs[0m...
10893 14:01:31.758024 Starting [0;1;39mLoad Kernel Module dr<30>[ 17.522109] systemd[1]: Starting Load Kernel Module drm...
10894 14:01:31.761648 m[0m...
10895 14:01:31.780858 <30>[ 17.542087] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10896 14:01:31.794980 Starting [0;1;39mJourn<30>[ 17.558812] systemd[1]: Starting Journal Service...
10897 14:01:31.795559 al Service[0m...
10898 14:01:31.818676 Starting [0;1;39mLoad <30>[ 17.582519] systemd[1]: Starting Load Kernel Modules...
10899 14:01:31.821909 Kernel Modules[0m...
10900 14:01:31.845436 Starting [0;1;39mRemount Root and Kern<30>[ 17.606048] systemd[1]: Starting Remount Root and Kernel File Systems...
10901 14:01:31.848497 el File Systems[0m...
10902 14:01:31.872482 Starting [0;1;39mColdplug All udev Dev<30>[ 17.633528] systemd[1]: Starting Coldplug All udev Devices...
10903 14:01:31.873011 ices[0m...
10904 14:01:31.888937 [[0;32m OK [<30>[ 17.656432] systemd[1]: Started Journal Service.
10905 14:01:31.895188 0m] Started [0;1;39mJournal Service[0m.
10906 14:01:31.912292 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10907 14:01:31.926443 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10908 14:01:31.942502 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10909 14:01:31.963981 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10910 14:01:31.979347 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10911 14:01:31.995414 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10912 14:01:32.015196 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10913 14:01:32.057888 Mounting [0;1;39mKernel Configuration File System[0m...
10914 14:01:32.084079 Starting [0;1;39mApply Kernel Variables[0m...
10915 14:01:32.105833 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10916 14:01:32.118111 See 'systemctl status systemd-remount-fs.service' for details.
10917 14:01:32.135851 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10918 14:01:32.152299 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10919 14:01:32.171771 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10920 14:01:32.214563 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10921 14:01:32.229508 <46>[ 17.991303] systemd-journald[191]: Received client request to flush runtime journal.
10922 14:01:32.237608 Starting [0;1;39mLoad/Save Random Seed[0m...
10923 14:01:32.256756 Starting [0;1;39mCreate System Users[0m...
10924 14:01:32.274879 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10925 14:01:32.287574 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10926 14:01:32.303503 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10927 14:01:32.347066 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10928 14:01:32.366706 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10929 14:01:32.377828 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10930 14:01:32.397650 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10931 14:01:32.451034 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10932 14:01:32.474171 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10933 14:01:32.495816 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10934 14:01:32.517138 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10935 14:01:32.573559 Starting [0;1;39mNetwork Time Synchronization[0m...
10936 14:01:32.591733 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10937 14:01:32.628917 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10938 14:01:32.644986 <6>[ 18.407418] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10939 14:01:32.655072 <6>[ 18.407457] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10940 14:01:32.665075 <6>[ 18.407464] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10941 14:01:32.671289 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10942 14:01:32.697105 <6>[ 18.458247] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10943 14:01:32.703282 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10944 14:01:32.717447 <6>[ 18.482141] remoteproc remoteproc0: scp is available
10945 14:01:32.724547 <6>[ 18.482313] remoteproc remoteproc0: powering up scp
10946 14:01:32.731130 <6>[ 18.482327] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10947 14:01:32.737422 [[0;32m OK [<6>[ 18.482359] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10948 14:01:32.747436 0m] Created slic<6>[ 18.496530] usbcore: registered new interface driver r8152
10949 14:01:32.754201 e [0;1;39msyste<4>[ 18.500008] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10950 14:01:32.760898 <4>[ 18.513745] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10951 14:01:32.764115 m-systemd\x2dbacklight.slice[0m.
10952 14:01:32.774118 <6>[ 18.538030] mc: Linux media interface: v0.10
10953 14:01:32.780396 <6>[ 18.538238] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10954 14:01:32.787457 <6>[ 18.538269] pci_bus 0000:00: root bus resource [bus 00-ff]
10955 14:01:32.794021 [[0;32m OK [<6>[ 18.538287] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10956 14:01:32.807057 0m] Reached targ<6>[ 18.538297] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10957 14:01:32.814002 et [0;1;39mSyst<6>[ 18.538470] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10958 14:01:32.823961 em Time Set[0m.<6>[ 18.538549] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10959 14:01:32.824514
10960 14:01:32.827481 <6>[ 18.538761] pci 0000:00:00.0: supports D1 D2
10961 14:01:32.834088 <6>[ 18.538764] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10962 14:01:32.843639 <3>[ 18.542666] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10963 14:01:32.849980 <3>[ 18.542709] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10964 14:01:32.857221 <3>[ 18.542718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10965 14:01:32.867687 <3>[ 18.547683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10966 14:01:32.874166 <3>[ 18.547706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10967 14:01:32.884489 <3>[ 18.547715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10968 14:01:32.891223 <3>[ 18.547730] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10969 14:01:32.897391 <3>[ 18.547736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10970 14:01:32.908345 [[0;32m OK [<3>[ 18.547822] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10971 14:01:32.918461 0m] Reached targ<3>[ 18.548910] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10972 14:01:32.928380 et [0;1;39mSyst<3>[ 18.548956] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10973 14:01:32.938105 em Time Synchron<3>[ 18.548966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10974 14:01:32.944975 <3>[ 18.552402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10975 14:01:32.951675 <3>[ 18.552429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10976 14:01:32.954876 ized[0m.
10977 14:01:32.961865 <3>[ 18.552437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10978 14:01:32.972255 <3>[ 18.552447] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10979 14:01:32.980164 <3>[ 18.552816] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10980 14:01:32.985997 <6>[ 18.556275] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10981 14:01:32.992563 <6>[ 18.556459] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10982 14:01:32.999161 <6>[ 18.556496] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10983 14:01:33.010107 <6>[ 18.556524] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10984 14:01:33.016286 <6>[ 18.556542] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10985 14:01:33.022675 Startin<6>[ 18.556680] pci 0000:01:00.0: supports D1 D2
10986 14:01:33.032992 g [0;1;39mLoad/<6>[ 18.556683] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10987 14:01:33.042820 Save Screen …o<6>[ 18.567728] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10988 14:01:33.053073 f leds:white:kbd<3>[ 18.568000] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10989 14:01:33.064058 _backlight[0m..<6>[ 18.570712] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10990 14:01:33.064501 .
10991 14:01:33.070974 <6>[ 18.591064] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10992 14:01:33.078110 <6>[ 18.591121] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10993 14:01:33.085101 <6>[ 18.591128] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10994 14:01:33.098592 [[0;32m OK [0m] Finished [0<6>[ 18.591143] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10995 14:01:33.108449 ;1;39mLoad/Save <6>[ 18.591160] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10996 14:01:33.115338 Screen …s of l<6>[ 18.591175] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10997 14:01:33.121796 eds:white:kbd_ba<6>[ 18.591194] pci 0000:00:00.0: PCI bridge to [bus 01]
10998 14:01:33.125018 cklight[0m.
10999 14:01:33.131738 <6>[ 18.591207] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11000 14:01:33.138329 <6>[ 18.591829] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11001 14:01:33.145594 <6>[ 18.594007] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11002 14:01:33.155757 <6>[ 18.607763] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11003 14:01:33.162598 <6>[ 18.607768] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11004 14:01:33.168881 <6>[ 18.607778] remoteproc remoteproc0: remote processor scp is now up
11005 14:01:33.175710 <4>[ 18.614929] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11006 14:01:33.182387 <4>[ 18.614929] Fallback method does not support PEC.
11007 14:01:33.192464 <6>[ 18.633975] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11008 14:01:33.199453 <3>[ 18.635879] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 14:01:33.206330 <6>[ 18.666152] videodev: Linux video capture interface: v2.00
11010 14:01:33.213256 <3>[ 18.682753] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 14:01:33.216852 <6>[ 18.687391] Bluetooth: Core ver 2.22
11012 14:01:33.223414 <6>[ 18.688006] NET: Registered PF_BLUETOOTH protocol family
11013 14:01:33.230470 <6>[ 18.688024] Bluetooth: HCI device and connection manager initialized
11014 14:01:33.236831 [[0;32m OK [<6>[ 18.688067] Bluetooth: HCI socket layer initialized
11015 14:01:33.244600 0m] Reached targ<6>[ 18.688076] Bluetooth: L2CAP socket layer initialized
11016 14:01:33.247747 <6>[ 18.688097] Bluetooth: SCO socket layer initialized
11017 14:01:33.258094 et [0;1;39mBlue<6>[ 18.690821] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11018 14:01:33.258541 tooth[0m.
11019 14:01:33.265031 <6>[ 18.716096] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11020 14:01:33.271744 <6>[ 18.716400] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11021 14:01:33.278921 [[0;32m OK [0m] Reached targ<6>[ 18.718640] usbcore: registered new interface driver cdc_ether
11022 14:01:33.286115 et [0;1;39mSyst<6>[ 18.726768] usbcore: registered new interface driver r8153_ecm
11023 14:01:33.296413 em Initializatio<3>[ 18.730184] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 14:01:33.299871 n[0m.
11025 14:01:33.303269 <6>[ 18.738891] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11026 14:01:33.316513 <6>[ 18.742762] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11027 14:01:33.323515 <6>[ 18.743008] usbcore: registered new interface driver uvcvideo
11028 14:01:33.333021 <3>[ 18.752213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11029 14:01:33.340012 [[0;32m OK [<6>[ 18.753474] usbcore: registered new interface driver btusb
11030 14:01:33.349684 0m] Started [0;<4>[ 18.755876] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11031 14:01:33.360113 1;39mDiscard unu<3>[ 18.755906] Bluetooth: hci0: Failed to load firmware file (-2)
11032 14:01:33.366898 sed blocks once <3>[ 18.755910] Bluetooth: hci0: Failed to set up firmware (-2)
11033 14:01:33.376309 <4>[ 18.755917] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11034 14:01:33.376990 a week[0m.
11035 14:01:33.382701 <6>[ 18.762318] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11036 14:01:33.392879 <3>[ 18.782452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11037 14:01:33.402611 <6>[ 18.789285] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11038 14:01:33.409143 <5>[ 18.792402] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11039 14:01:33.415964 <6>[ 18.803170] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11040 14:01:33.423130 <5>[ 18.808796] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11041 14:01:33.433135 <4>[ 18.808916] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11042 14:01:33.439230 <6>[ 18.808924] cfg80211: failed to load regulatory.db
11043 14:01:33.445888 <4>[ 18.846150] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11044 14:01:33.456124 <4>[ 18.846161] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11045 14:01:33.466019 <3>[ 18.850013] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11046 14:01:33.472138 <3>[ 18.862627] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11047 14:01:33.479113 <6>[ 18.897581] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11048 14:01:33.485617 <6>[ 18.897689] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11049 14:01:33.491937 <6>[ 18.918068] mt7921e 0000:01:00.0: ASIC revision: 79610010
11050 14:01:33.502329 <3>[ 18.922812] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11051 14:01:33.508830 <3>[ 18.926055] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11052 14:01:33.515812 <6>[ 18.937604] r8152 2-1.3:1.0 eth0: v1.12.13
11053 14:01:33.519094 <6>[ 18.947726] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11054 14:01:33.529089 <3>[ 18.989739] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11055 14:01:33.538849 <4>[ 19.011973] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11056 14:01:33.552123 <4>[ 19.115946] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11057 14:01:33.561978 <4>[ 19.223307] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11058 14:01:33.575422 <4>[ 19.327038] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11059 14:01:33.581417 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11060 14:01:33.598103 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11061 14:01:33.621918 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11062 14:01:33.637853 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11063 14:01:33.658703 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11064 14:01:33.673114 <4>[ 19.431439] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11065 14:01:33.682928 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11066 14:01:33.722649 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11067 14:01:33.767160 Starting [0;1;39mUser Login Management[0m...
11068 14:01:33.786567 <4>[ 19.541891] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11069 14:01:33.795774 Starting [0;1;39mPermit User Sessions[0m...
11070 14:01:33.825056 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11071 14:01:33.843468 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11072 14:01:33.884302 <4>[ 19.645157] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11073 14:01:33.900357 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11074 14:01:33.920554 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11075 14:01:33.938898 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11076 14:01:33.954418 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11077 14:01:33.970912 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11078 14:01:33.992592 <4>[ 19.752455] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11079 14:01:34.015978 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11080 14:01:34.037991 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11081 14:01:34.052574 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11082 14:01:34.101262 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System R<4>[ 19.860987] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11083 14:01:34.101865 unlevel Changes[0m.
11084 14:01:34.146265
11085 14:01:34.146808
11086 14:01:34.149150 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11087 14:01:34.149701
11088 14:01:34.152660 debian-bullseye-arm64 login: root (automatic login)
11089 14:01:34.153122
11090 14:01:34.153486
11091 14:01:34.168836 Linux debian-bullseye-arm64 6.1.46-cip4-rt2 #1 SMP PREEMPT Mon Aug 28 13:41:26 UTC 2023 aarch64
11092 14:01:34.169436
11093 14:01:34.175523 The programs included with the Debian GNU/Linux system are free software;
11094 14:01:34.181849 the exact distribution terms for each program are described in the
11095 14:01:34.185332 individual files in /usr/share/doc/*/copyright.
11096 14:01:34.185926
11097 14:01:34.191642 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11098 14:01:34.195043 permitted by applicable law.
11099 14:01:34.196372 Matched prompt #10: / #
11101 14:01:34.197475 Setting prompt string to ['/ #']
11102 14:01:34.197966 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11104 14:01:34.199051 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11105 14:01:34.199523 start: 2.2.6 expect-shell-connection (timeout 00:03:00) [common]
11106 14:01:34.199979 Setting prompt string to ['/ #']
11107 14:01:34.200325 Forcing a shell prompt, looking for ['/ #']
11109 14:01:34.251197 / #
11110 14:01:34.251903 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11111 14:01:34.252335 Waiting using forced prompt support (timeout 00:02:30)
11112 14:01:34.252899 <4>[ 19.968184] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11113 14:01:34.257844
11114 14:01:34.258766 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11115 14:01:34.259292 start: 2.2.7 export-device-env (timeout 00:03:00) [common]
11116 14:01:34.259962 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11117 14:01:34.260462 end: 2.2 depthcharge-retry (duration 00:02:00) [common]
11118 14:01:34.260954 end: 2 depthcharge-action (duration 00:02:00) [common]
11119 14:01:34.261418 start: 3 lava-test-retry (timeout 00:05:00) [common]
11120 14:01:34.261907 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11121 14:01:34.262300 Using namespace: common
11123 14:01:34.363502 / # #
11124 14:01:34.364323 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11125 14:01:34.365179 <3>[ 20.073727] mt7921e 0000:01:00.0: hardware init failed
11126 14:01:34.370546 #
11127 14:01:34.371497 Using /lava-11372169
11129 14:01:34.473047 / # export SHELL=/bin/sh
11130 14:01:34.479476 export SHELL=/bin/sh
11132 14:01:34.581399 / # . /lava-11372169/environment
11133 14:01:34.587764 . /lava-11372169/environment
11135 14:01:34.689543 / # /lava-11372169/bin/lava-test-runner /lava-11372169/0
11136 14:01:34.690317 Test shell timeout: 10s (minimum of the action and connection timeout)
11137 14:01:34.695976 /lava-11372169/bin/lava-test-runner /lava-11372169/0
11138 14:01:34.718086 + export TESTRUN_ID=0_sleep
11139 14:01:34.721556 + cd /lava-11372169/0/tests/0_sleep
11140 14:01:34.724402 + cat uuid
11141 14:01:34.724970 + UUID=11372169_1.5.2.3.1
11142 14:01:34.725339 + set +x
11143 14:01:34.731038 <LAVA_SIGNAL_STARTRUN 0_sleep 11372169_1.5.2.3.1>
11144 14:01:34.731936 Received signal: <STARTRUN> 0_sleep 11372169_1.5.2.3.1
11145 14:01:34.732414 Starting test lava.0_sleep (11372169_1.5.2.3.1)
11146 14:01:34.732877 Skipping test definition patterns.
11147 14:01:34.734425 + ./config/lava/sleep/sleep.sh mem freeze
11148 14:01:34.737511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11149 14:01:34.738248 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11151 14:01:34.744198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11152 14:01:34.745001 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11154 14:01:34.747352 rtcwake: assuming RTC uses UTC ...
11155 14:01:34.754486 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 14:00:37 2023
11156 14:01:34.761895 <6>[ 20.526325] PM: suspend entry (deep)
11157 14:01:34.764753 <6>[ 20.526357] Filesystems sync: 0.000 seconds
11158 14:01:34.767965 <6>[ 20.528120] Freezing user space processes
11159 14:01:34.774569 <6>[ 20.533508] Freezing user space processes completed (elapsed 0.005 seconds)
11160 14:01:34.778322 <6>[ 20.533523] OOM killer disabled.
11161 14:01:34.784420 <6>[ 20.533526] Freezing remaining freezable tasks
11162 14:01:34.791239 <6>[ 20.534830] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11163 14:01:34.797409 <6>[ 20.534839] printk: Suspending console(s) (use no_console_suspend to debug)
11164 14:01:38.272852 <3>[ 23.809732] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11165 14:01:38.282987 <3>[ 23.809772] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11166 14:01:38.292627 <3>[ 23.809816] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11167 14:01:38.299121 <3>[ 23.809852] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11168 14:01:38.305868 <3>[ 23.810148] PM: Some devices failed to suspend, or early wake event detected
11169 14:01:38.315579 <4>[ 23.823970] typec port0-partner: PM: parent port0 should not be sleeping
11170 14:01:38.382216 <6>[ 24.145750] OOM killer enabled.
11171 14:01:38.385321 <6>[ 24.145761] Restarting tasks ... done.
11172 14:01:38.389022 <5>[ 24.150792] random: crng reseeded on system resumption
11173 14:01:38.392121 rtcwake: write error
11174 14:01:38.395257 <6>[ 24.164005] PM: suspend exit
11175 14:01:38.402012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11176 14:01:38.402272 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11178 14:01:38.405672 rtcwake: assuming RTC uses UTC ...
11179 14:01:38.411778 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 14:00:40 2023
11180 14:01:38.424800 <6>[ 24.192841] PM: suspend entry (deep)
11181 14:01:38.428202 <6>[ 24.192883] Filesystems sync: 0.000 seconds
11182 14:01:38.431240 <6>[ 24.193614] Freezing user space processes
11183 14:01:38.438043 <6>[ 24.197581] Freezing user space processes completed (elapsed 0.003 seconds)
11184 14:01:38.444828 <6>[ 24.197589] OOM killer disabled.
11185 14:01:38.448081 <6>[ 24.197591] Freezing remaining freezable tasks
11186 14:01:38.454733 <6>[ 24.198976] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11187 14:01:38.461054 <6>[ 24.198987] printk: Suspending console(s) (use no_console_suspend to debug)
11188 14:01:41.852127 <3>[ 27.393642] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11189 14:01:41.862350 <3>[ 27.393664] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11190 14:01:41.872443 <3>[ 27.393693] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11191 14:01:41.878656 <3>[ 27.393718] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11192 14:01:41.885497 <3>[ 27.394153] PM: Some devices failed to suspend, or early wake event detected
11193 14:01:41.960372 rtcwake: <6>[ 27.725751] OOM killer enabled.
11194 14:01:41.960465 write error
11195 14:01:41.963502 <6>[ 27.725762] Restarting tasks ... done.
11196 14:01:41.970315 <5>[ 27.728322] random: crng reseeded on system resumption
11197 14:01:41.973911 <LAVA_SIGNAL_TES<6>[ 27.729251] PM: suspend exit
11198 14:01:41.976763 TCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11199 14:01:41.977023 Received signal: <TES<6>[> 27.729251] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11200 14:01:41.980259 rtcwake: assuming RTC uses UTC ...
11201 14:01:41.986896 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 14:00:44 2023
11202 14:01:42.004191 <6>[ 27.769963] PM: suspend entry (deep)
11203 14:01:42.007863 <6>[ 27.770006] Filesystems sync: 0.000 seconds
11204 14:01:42.011080 <6>[ 27.770551] Freezing user space processes
11205 14:01:42.017683 <6>[ 27.772320] Freezing user space processes completed (elapsed 0.001 seconds)
11206 14:01:42.021151 <6>[ 27.772329] OOM killer disabled.
11207 14:01:42.027603 <6>[ 27.772331] Freezing remaining freezable tasks
11208 14:01:42.034379 <6>[ 27.773453] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11209 14:01:42.040658 <6>[ 27.773459] printk: Suspending console(s) (use no_console_suspend to debug)
11210 14:01:45.444100 <3>[ 30.977669] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11211 14:01:45.453969 <3>[ 30.977697] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11212 14:01:45.464361 <3>[ 30.977741] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11213 14:01:45.470584 <3>[ 30.977784] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11214 14:01:45.477809 <3>[ 30.978042] PM: Some devices failed to suspend, or early wake event detected
11215 14:01:45.551639 <6>[ 31.317713] OOM killer enabled.
11216 14:01:45.555125 <6>[ 31.317724] Restarting tasks ... done.
11217 14:01:45.558385 <5>[ 31.325321] random: crng reseeded on system resumption
11218 14:01:45.562451 rtcwake: write error
11219 14:01:45.565915 <6>[ 31.335333] PM: suspend exit
11220 14:01:45.572694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11221 14:01:45.573034 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11223 14:01:45.575907 rtcwake: assuming RTC uses UTC ...
11224 14:01:45.578839 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 14:00:47 2023
11225 14:01:45.595485 <6>[ 31.363245] PM: suspend entry (deep)
11226 14:01:45.599362 <6>[ 31.363293] Filesystems sync: 0.000 seconds
11227 14:01:45.602859 <6>[ 31.363827] Freezing user space processes
11228 14:01:45.609263 <6>[ 31.365451] Freezing user space processes completed (elapsed 0.001 seconds)
11229 14:01:45.612653 <6>[ 31.365461] OOM killer disabled.
11230 14:01:45.619085 <6>[ 31.365463] Freezing remaining freezable tasks
11231 14:01:45.625884 <6>[ 31.366644] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11232 14:01:45.632511 <6>[ 31.366648] printk: Suspending console(s) (use no_console_suspend to debug)
11233 14:01:49.023161 <3>[ 34.561695] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11234 14:01:49.033315 <3>[ 34.561729] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11235 14:01:49.043224 <3>[ 34.561770] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11236 14:01:49.050348 <3>[ 34.561801] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11237 14:01:49.057172 <3>[ 34.562030] PM: Some devices failed to suspend, or early wake event detected
11238 14:01:49.130924 rtcwake: write e<6>[ 34.897718] OOM killer enabled.
11239 14:01:49.131025 rror
11240 14:01:49.134474 <6>[ 34.897729] Restarting tasks ... done.
11241 14:01:49.141112 <5>[ 34.899936] random: crng reseeded on system resumption
11242 14:01:49.144371 <LAVA_SIGNAL_TES<6>[ 34.900945] PM: suspend exit
11243 14:01:49.147884 TCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11244 14:01:49.148144 Received signal: <TES<6>[> 34.900945] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11245 14:01:49.151289 rtcwake: assuming RTC uses UTC ...
11246 14:01:49.158139 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 14:00:51 2023
11247 14:01:49.175183 <6>[ 34.941652] PM: suspend entry (deep)
11248 14:01:49.178544 <6>[ 34.941699] Filesystems sync: 0.000 seconds
11249 14:01:49.182146 <6>[ 34.942250] Freezing user space processes
11250 14:01:49.188605 <6>[ 34.943971] Freezing user space processes completed (elapsed 0.001 seconds)
11251 14:01:49.192583 <6>[ 34.943982] OOM killer disabled.
11252 14:01:49.198789 <6>[ 34.943984] Freezing remaining freezable tasks
11253 14:01:49.205786 <6>[ 34.945374] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11254 14:01:49.211841 <6>[ 34.945392] printk: Suspending console(s) (use no_console_suspend to debug)
11255 14:01:52.610819 <3>[ 38.145752] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11256 14:01:52.621743 <3>[ 38.145790] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11257 14:01:52.630749 <3>[ 38.145837] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11258 14:01:52.638148 <3>[ 38.145879] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11259 14:01:52.644437 <3>[ 38.146112] PM: Some devices failed to suspend, or early wake event detected
11260 14:01:52.715968 <6>[ 38.485728] OOM killer enabled.
11261 14:01:52.722583 <6>[ 38.485740] Restarting tasks ... done.
11262 14:01:52.725617 <5>[ 38.490124] random: crng reseeded on system resumption
11263 14:01:52.728839 rtcwake: write error
11264 14:01:52.732245 <6>[ 38.502491] PM: suspend exit
11265 14:01:52.739097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11266 14:01:52.739390 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11268 14:01:52.742500 rtcwake: assuming RTC uses UTC ...
11269 14:01:52.749125 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 14:00:55 2023
11270 14:01:52.763308 <6>[ 38.531369] PM: suspend entry (deep)
11271 14:01:52.766301 <6>[ 38.531409] Filesystems sync: 0.000 seconds
11272 14:01:52.770035 <6>[ 38.531945] Freezing user space processes
11273 14:01:52.776753 <6>[ 38.533561] Freezing user space processes completed (elapsed 0.001 seconds)
11274 14:01:52.779537 <6>[ 38.533566] OOM killer disabled.
11275 14:01:52.786401 <6>[ 38.533568] Freezing remaining freezable tasks
11276 14:01:52.793643 <6>[ 38.534887] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11277 14:01:52.800119 <6>[ 38.534897] printk: Suspending console(s) (use no_console_suspend to debug)
11278 14:01:56.190720 <3>[ 41.729669] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11279 14:01:56.200587 <3>[ 41.729708] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11280 14:01:56.210734 <3>[ 41.729747] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11281 14:01:56.216928 <3>[ 41.729789] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11282 14:01:56.226932 <3>[ 41.730278] PM: Some devices failed to suspend, or early wake event detected
11283 14:01:56.294683 rtcwake: write error
11284 14:01:56.298026 <6>[ 42.065729] OOM killer enabled.
11285 14:01:56.305078 <LAVA_SIGNAL_TES<6>[ 42.065741] Restarting tasks ... done.
11286 14:01:56.305337 Received signal: <TES<6>[> 42.065741] Restarting tasks ... done.
TCASE TEST_CASE_<5
11287 14:01:56.311470 TCASE TEST_CASE_<5>[ 42.067580] random: crng reseeded on system resumption
11288 14:01:56.314662 ID=rtcwake-mem-6<6>[ 42.068545] PM: suspend exit
11289 14:01:56.314743 RESULT=fail>
11290 14:01:56.317898 rtcwake: assuming RTC uses UTC ...
11291 14:01:56.324334 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 14:00:58 2023
11292 14:01:56.338508 <6>[ 42.106609] PM: suspend entry (deep)
11293 14:01:56.341786 <6>[ 42.106656] Filesystems sync: 0.000 seconds
11294 14:01:56.345059 <6>[ 42.107213] Freezing user space processes
11295 14:01:56.351962 <6>[ 42.108948] Freezing user space processes completed (elapsed 0.001 seconds)
11296 14:01:56.355150 <6>[ 42.108959] OOM killer disabled.
11297 14:01:56.361796 <6>[ 42.108961] Freezing remaining freezable tasks
11298 14:01:56.368598 <6>[ 42.110150] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11299 14:01:56.374804 <6>[ 42.110155] printk: Suspending console(s) (use no_console_suspend to debug)
11300 14:01:59.770439 <3>[ 45.313668] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11301 14:01:59.780623 <3>[ 45.313701] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11302 14:01:59.790495 <3>[ 45.313750] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11303 14:01:59.797136 <3>[ 45.313792] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11304 14:01:59.803431 <3>[ 45.314070] PM: Some devices failed to suspend, or early wake event detected
11305 14:01:59.878054 rtcwake: <6>[ 45.645727] OOM killer enabled.
11306 14:01:59.878150 write error
11307 14:01:59.881891 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7<6
11308 14:01:59.881991 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'rtcwake-mem-7<6', 'result': 'unknown'}
11309 14:01:59.887837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7<6>[ 45.645737] Restarting tasks ... done.
11310 14:01:59.887921 RESULT=fail>
11311 14:01:59.894724 r<5>[ 45.647855] random: crng reseeded on system resumption
11312 14:01:59.898271 tcwake: assuming<6>[ 45.649260] PM: suspend exit
11313 14:01:59.898354 RTC uses UTC ...
11314 14:01:59.904744 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 14:01:02 2023
11315 14:01:59.908791 <6>[ 45.677350] PM: suspend entry (deep)
11316 14:01:59.915080 <6>[ 45.677402] Filesystems sync: 0.000 seconds
11317 14:01:59.918092 <6>[ 45.677972] Freezing user space processes
11318 14:01:59.925379 <6>[ 45.679612] Freezing user space processes completed (elapsed 0.001 seconds)
11319 14:01:59.928231 <6>[ 45.679622] OOM killer disabled.
11320 14:01:59.934718 <6>[ 45.679625] Freezing remaining freezable tasks
11321 14:01:59.941750 <6>[ 45.680975] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11322 14:01:59.947931 <6>[ 45.680989] printk: Suspending console(s) (use no_console_suspend to debug)
11323 14:02:03.354768 <6>[ 48.129720] vpu: disabling
11324 14:02:03.358056 <6>[ 48.129828] vproc2: disabling
11325 14:02:03.361096 <6>[ 48.129870] vproc1: disabling
11326 14:02:03.364722 <6>[ 48.129914] vaud18: disabling
11327 14:02:03.367849 <6>[ 48.130113] vsram_others: disabling
11328 14:02:03.371165 <6>[ 48.130273] va09: disabling
11329 14:02:03.374212 <6>[ 48.130335] vsram_md: disabling
11330 14:02:03.377976 <6>[ 48.130441] Vgpu: disabling
11331 14:02:03.384521 <3>[ 48.897626] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11332 14:02:03.394098 <3>[ 48.897651] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11333 14:02:03.404593 <3>[ 48.897682] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11334 14:02:03.411356 <3>[ 48.897710] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11335 14:02:03.417530 <3>[ 48.897945] PM: Some devices failed to suspend, or early wake event detected
11336 14:02:03.462631 <6>[ 49.233694] OOM killer enabled.
11337 14:02:03.469770 <6>[ 49.233705] Restarting tasks ... done.
11338 14:02:03.473061 <5>[ 49.241066] random: crng reseeded on system resumption
11339 14:02:03.476448 rtcwake: write error
11340 14:02:03.479794 <6>[ 49.250982] PM: suspend exit
11341 14:02:03.486397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11342 14:02:03.486660 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11344 14:02:03.489414 rtcwake: assuming RTC uses UTC ...
11345 14:02:03.493129 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 14:01:05 2023
11346 14:02:03.509532 <6>[ 49.279062] PM: suspend entry (deep)
11347 14:02:03.513020 <6>[ 49.279117] Filesystems sync: 0.000 seconds
11348 14:02:03.516367 <6>[ 49.279690] Freezing user space processes
11349 14:02:03.522858 <6>[ 49.281426] Freezing user space processes completed (elapsed 0.001 seconds)
11350 14:02:03.526464 <6>[ 49.281442] OOM killer disabled.
11351 14:02:03.532794 <6>[ 49.281446] Freezing remaining freezable tasks
11352 14:02:03.539522 <6>[ 49.282835] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11353 14:02:03.546195 <6>[ 49.282848] printk: Suspending console(s) (use no_console_suspend to debug)
11354 14:02:06.945274 <3>[ 52.481677] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11355 14:02:06.955189 <3>[ 52.481707] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11356 14:02:06.965511 <3>[ 52.481750] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11357 14:02:06.971941 <3>[ 52.481794] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11358 14:02:06.979060 <3>[ 52.482061] PM: Some devices failed to suspend, or early wake event detected
11359 14:02:07.053409 <6>[ 52.821729] OOM killer enabled.
11360 14:02:07.056476 <6>[ 52.821740] Restarting tasks ... done.
11361 14:02:07.059925 <5>[ 52.826848] random: crng reseeded on system resumption
11362 14:02:07.063191 rtcwake: write error
11363 14:02:07.066899 <6>[ 52.838453] PM: suspend exit
11364 14:02:07.073371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11365 14:02:07.073630 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11367 14:02:07.076544 rtcwake: assuming RTC uses UTC ...
11368 14:02:07.083402 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 14:01:09 2023
11369 14:02:07.097392 <6>[ 52.867298] PM: suspend entry (deep)
11370 14:02:07.101439 <6>[ 52.867346] Filesystems sync: 0.000 seconds
11371 14:02:07.104543 <6>[ 52.867866] Freezing user space processes
11372 14:02:07.110714 <6>[ 52.869666] Freezing user space processes completed (elapsed 0.001 seconds)
11373 14:02:07.114137 <6>[ 52.869675] OOM killer disabled.
11374 14:02:07.120682 <6>[ 52.869677] Freezing remaining freezable tasks
11375 14:02:07.127890 <6>[ 52.871001] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11376 14:02:07.134061 <6>[ 52.871012] printk: Suspending console(s) (use no_console_suspend to debug)
11377 14:02:10.529043 <3>[ 56.065738] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11378 14:02:10.538971 <3>[ 56.065770] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11379 14:02:10.548971 <3>[ 56.065815] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11380 14:02:10.555437 <3>[ 56.065855] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11381 14:02:10.561942 <3>[ 56.066125] PM: Some devices failed to suspend, or early wake event detected
11382 14:02:10.636812 <6>[ 56.405731] OOM killer enabled.
11383 14:02:10.640494 <6>[ 56.405742] Restarting tasks ... done.
11384 14:02:10.644040 rtcwake: write error
11385 14:02:10.650275 <5>[ 56.412967] random: crng reseeded on system resumption
11386 14:02:10.653409 <6>[ 56.417583] PM: suspend exit
11387 14:02:10.656987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11388 14:02:10.657247 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11390 14:02:10.660280 rtcwake: assuming RTC uses UTC ...
11391 14:02:10.667071 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 14:01:13 2023
11392 14:02:10.681040 <6>[ 56.451346] PM: suspend entry (s2idle)
11393 14:02:10.684731 <6>[ 56.451396] Filesystems sync: 0.000 seconds
11394 14:02:10.688107 <6>[ 56.451951] Freezing user space processes
11395 14:02:10.694621 <6>[ 56.453701] Freezing user space processes completed (elapsed 0.001 seconds)
11396 14:02:10.697971 <6>[ 56.453713] OOM killer disabled.
11397 14:02:10.704257 <6>[ 56.453715] Freezing remaining freezable tasks
11398 14:02:10.711086 <6>[ 56.455057] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11399 14:02:10.717986 <6>[ 56.455068] printk: Suspending console(s) (use no_console_suspend to debug)
11400 14:02:14.113262 <3>[ 59.649707] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11401 14:02:14.123102 <3>[ 59.649739] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11402 14:02:14.133029 <3>[ 59.649786] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11403 14:02:14.139504 <3>[ 59.649830] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11404 14:02:14.146106 <3>[ 59.650168] PM: Some devices failed to suspend, or early wake event detected
11405 14:02:14.217552 <6>[ 59.989728] OOM killer enabled.
11406 14:02:14.224502 <6>[ 59.989739] Restarting tasks ... done.
11407 14:02:14.231428 rtcwake: write e<5>[ 59.995059] random: crng reseeded on system resumption
11408 14:02:14.234412 <6>[ 60.000913] PM: suspend exit
11409 14:02:14.234879 rror
11410 14:02:14.241548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11411 14:02:14.242296 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11413 14:02:14.244133 rtcwake: assuming RTC uses UTC ...
11414 14:02:14.248359 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 14:01:16 2023
11415 14:02:14.264655 <6>[ 60.033562] PM: suspend entry (s2idle)
11416 14:02:14.268261 <6>[ 60.033608] Filesystems sync: 0.000 seconds
11417 14:02:14.271519 <6>[ 60.034166] Freezing user space processes
11418 14:02:14.278740 <6>[ 60.035871] Freezing user space processes completed (elapsed 0.001 seconds)
11419 14:02:14.285416 <6>[ 60.035883] OOM killer disabled.
11420 14:02:14.288645 <6>[ 60.035885] Freezing remaining freezable tasks
11421 14:02:14.295450 <6>[ 60.037402] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11422 14:02:14.301499 <6>[ 60.037425] printk: Suspending console(s) (use no_console_suspend to debug)
11423 14:02:17.689094 <3>[ 63.233666] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11424 14:02:17.698800 <3>[ 63.233695] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11425 14:02:17.708848 <3>[ 63.233739] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11426 14:02:17.715524 <3>[ 63.233778] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11427 14:02:17.721978 <3>[ 63.234085] PM: Some devices failed to suspend, or early wake event detected
11428 14:02:17.796533 <6>[ 63.565718] OOM killer enabled.
11429 14:02:17.800168 <6>[ 63.565729] Restarting tasks ... done.
11430 14:02:17.806794 rtcwake: <5>[ 63.567799] random: crng reseeded on system resumption
11431 14:02:17.807365 write error
11432 14:02:17.809965 <6>[ 63.576989] PM: suspend exit
11433 14:02:17.816641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11434 14:02:17.817518 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11436 14:02:17.820117 rtcwake: assuming RTC uses UTC ...
11437 14:02:17.823381 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 14:01:20 2023
11438 14:02:17.840812 <6>[ 63.610024] PM: suspend entry (s2idle)
11439 14:02:17.844075 <6>[ 63.610069] Filesystems sync: 0.000 seconds
11440 14:02:17.847107 <6>[ 63.610624] Freezing user space processes
11441 14:02:17.857214 <6>[ 63.612343] Freezing user space processes completed (elapsed 0.001 seconds)
11442 14:02:17.860645 <6>[ 63.612355] OOM killer disabled.
11443 14:02:17.864007 <6>[ 63.612357] Freezing remaining freezable tasks
11444 14:02:17.870542 <6>[ 63.613647] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11445 14:02:17.880613 <6>[ 63.613659] printk: Suspending console(s) (use no_console_suspend to debug)
11446 14:02:21.280494 <3>[ 66.817681] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11447 14:02:21.290426 <3>[ 66.817710] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11448 14:02:21.300213 <3>[ 66.817750] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11449 14:02:21.306870 <3>[ 66.817790] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11450 14:02:21.313535 <3>[ 66.818310] PM: Some devices failed to suspend, or early wake event detected
11451 14:02:21.388009 <6>[ 67.157727] OOM killer enabled.
11452 14:02:21.392141 rtcwake: <6>[ 67.157738] Restarting tasks ... done.
11453 14:02:21.392727 write error
11454 14:02:21.398591 <5>[ 67.159773] random: crng reseeded on system resumption
11455 14:02:21.402021 <LAVA_SIGNAL_TES<6>[ 67.164880] PM: suspend exit
11456 14:02:21.408934 TCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11457 14:02:21.409523 rtcwake: assuming RTC uses UTC ...
11458 14:02:21.410324 Received signal: <TES<6>[> 67.164880] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11459 14:02:21.415552 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 14:01:23 2023
11460 14:02:21.432307 <6>[ 67.203304] PM: suspend entry (s2idle)
11461 14:02:21.435843 <6>[ 67.203350] Filesystems sync: 0.000 seconds
11462 14:02:21.439322 <6>[ 67.203918] Freezing user space processes
11463 14:02:21.445735 <6>[ 67.205624] Freezing user space processes completed (elapsed 0.001 seconds)
11464 14:02:21.453017 <6>[ 67.205634] OOM killer disabled.
11465 14:02:21.456175 <6>[ 67.205637] Freezing remaining freezable tasks
11466 14:02:21.462737 <6>[ 67.206963] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11467 14:02:21.469194 <6>[ 67.206973] printk: Suspending console(s) (use no_console_suspend to debug)
11468 14:02:24.855813 <3>[ 70.401640] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11469 14:02:24.865616 <3>[ 70.401664] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11470 14:02:24.876018 <3>[ 70.401696] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11471 14:02:24.882341 <3>[ 70.401724] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11472 14:02:24.888906 <3>[ 70.401971] PM: Some devices failed to suspend, or early wake event detected
11473 14:02:24.964284 <6>[ 70.733767] OOM killer enabled.
11474 14:02:24.967463 rtcwake: write error
11475 14:02:24.970572 <6>[ 70.733778] Restarting tasks ... done.
11476 14:02:24.977461 <LAVA_SIGNAL_TES<5>[ 70.742573] random: crng reseeded on system resumption
11477 14:02:24.980467 Received signal: <TES<5>[> 70.742573] random: crng reseeded on system resumption
TCASE TEST_CASE_<6
11478 14:02:24.984511 TCASE TEST_CASE_<6>[ 70.743942] PM: suspend exit
11479 14:02:24.987326 ID=rtcwake-freeze-4 RESULT=fail>
11480 14:02:24.990673 rtcwake: assuming RTC uses UTC ...
11481 14:02:24.993368 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 14:01:27 2023
11482 14:02:25.011888 <6>[ 70.782675] PM: suspend entry (s2idle)
11483 14:02:25.015489 <6>[ 70.782721] Filesystems sync: 0.000 seconds
11484 14:02:25.018887 <6>[ 70.783258] Freezing user space processes
11485 14:02:25.028342 <6>[ 70.784947] Freezing user space processes completed (elapsed 0.001 seconds)
11486 14:02:25.031936 <6>[ 70.784960] OOM killer disabled.
11487 14:02:25.035282 <6>[ 70.784962] Freezing remaining freezable tasks
11488 14:02:25.041813 <6>[ 70.786414] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11489 14:02:25.048119 <6>[ 70.786428] printk: Suspending console(s) (use no_console_suspend to debug)
11490 14:02:28.444230 <3>[ 73.985678] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11491 14:02:28.453601 <3>[ 73.985707] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11492 14:02:28.464058 <3>[ 73.985751] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11493 14:02:28.470511 <3>[ 73.985791] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11494 14:02:28.477173 <3>[ 73.986089] PM: Some devices failed to suspend, or early wake event detected
11495 14:02:28.547763 rtcwake: write error
11496 14:02:28.550863 <6>[ 74.321729] OOM killer enabled.
11497 14:02:28.557745 <LAVA_SIGNAL_TES<6>[ 74.321741] Restarting tasks ... done.
11498 14:02:28.558607 Received signal: <TES<6>[> 74.321741] Restarting tasks ... done.
TCASE TEST_CASE_<5
11499 14:02:28.564609 TCASE TEST_CASE_<5>[ 74.323689] random: crng reseeded on system resumption
11500 14:02:28.567994 ID=rtcwake-freez<6>[ 74.324779] PM: suspend exit
11501 14:02:28.571266 e-5 RESULT=fail>
11502 14:02:28.571873 rtcwake: assuming RTC uses UTC ...
11503 14:02:28.577860 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 14:01:30 2023
11504 14:02:28.595472 <6>[ 74.367267] PM: suspend entry (s2idle)
11505 14:02:28.598790 <6>[ 74.367319] Filesystems sync: 0.000 seconds
11506 14:02:28.602302 <6>[ 74.367841] Freezing user space processes
11507 14:02:28.608897 <6>[ 74.369518] Freezing user space processes completed (elapsed 0.001 seconds)
11508 14:02:28.616210 <6>[ 74.369532] OOM killer disabled.
11509 14:02:28.618930 <6>[ 74.369538] Freezing remaining freezable tasks
11510 14:02:28.625881 <6>[ 74.370918] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11511 14:02:28.632027 <6>[ 74.370929] printk: Suspending console(s) (use no_console_suspend to debug)
11512 14:02:32.031462 <3>[ 77.569647] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11513 14:02:32.041263 <3>[ 77.569673] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11514 14:02:32.051265 <3>[ 77.569710] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11515 14:02:32.058451 <3>[ 77.569743] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11516 14:02:32.064316 <3>[ 77.570014] PM: Some devices failed to suspend, or early wake event detected
11517 14:02:32.138938 <6>[ 77.909730] OOM killer enabled.
11518 14:02:32.141909 <6>[ 77.909741] Restarting tasks ... done.
11519 14:02:32.145778 <5>[ 77.913074] random: crng reseeded on system resumption
11520 14:02:32.148807 rtcwake: write error
11521 14:02:32.152339 <6>[ 77.926320] PM: suspend exit
11522 14:02:32.158665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11523 14:02:32.159528 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11525 14:02:32.162262 rtcwake: assuming RTC uses UTC ...
11526 14:02:32.168707 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 14:01:34 2023
11527 14:02:32.183202 <6>[ 77.955144] PM: suspend entry (s2idle)
11528 14:02:32.186070 <6>[ 77.955190] Filesystems sync: 0.000 seconds
11529 14:02:32.189738 <6>[ 77.955724] Freezing user space processes
11530 14:02:32.196129 <6>[ 77.957464] Freezing user space processes completed (elapsed 0.001 seconds)
11531 14:02:32.199703 <6>[ 77.957479] OOM killer disabled.
11532 14:02:32.207001 <6>[ 77.957481] Freezing remaining freezable tasks
11533 14:02:32.213301 <6>[ 77.958903] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11534 14:02:32.219660 <6>[ 77.958914] printk: Suspending console(s) (use no_console_suspend to debug)
11535 14:02:35.615045 <3>[ 81.153661] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11536 14:02:35.625037 <3>[ 81.153691] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11537 14:02:35.634657 <3>[ 81.153735] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11538 14:02:35.641337 <3>[ 81.153775] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11539 14:02:35.648052 <3>[ 81.154071] PM: Some devices failed to suspend, or early wake event detected
11540 14:02:35.722566 <6>[ 81.493728] OOM killer enabled.
11541 14:02:35.726018 rtcwake: <6>[ 81.493740] Restarting tasks ... done.
11542 14:02:35.729444 write error
11543 14:02:35.736064 <LAVA_SIGNAL_TESTCA<5>[ 81.501062] random: crng reseeded on system resumption
11544 14:02:35.736926 Received signal: <TESTCA<5>[> 81.501062] random: crng reseeded on system resumption
SE TEST_CASE_ID=<6
11545 14:02:35.739373 SE TEST_CASE_ID=<6>[ 81.502054] PM: suspend exit
11546 14:02:35.742865 rtcwake-freeze-7 RESULT=fail>
11547 14:02:35.746138 rtcwake: assuming RTC uses UTC ...
11548 14:02:35.752451 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 14:01:38 2023
11549 14:02:35.762369 <6>[ 81.535550] PM: suspend entry (s2idle)
11550 14:02:35.765921 <6>[ 81.535610] Filesystems sync: 0.000 seconds
11551 14:02:35.772626 <6>[ 81.536135] Freezing user space processes
11552 14:02:35.779414 <6>[ 81.537479] Freezing user space processes completed (elapsed 0.001 seconds)
11553 14:02:35.782990 <6>[ 81.537488] OOM killer disabled.
11554 14:02:35.786352 <6>[ 81.537490] Freezing remaining freezable tasks
11555 14:02:35.792960 <6>[ 81.538832] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11556 14:02:35.802880 <6>[ 81.538843] printk: Suspending console(s) (use no_console_suspend to debug)
11557 14:02:39.198454 <3>[ 84.737716] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11558 14:02:39.207984 <3>[ 84.737752] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11559 14:02:39.218282 <3>[ 84.737799] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11560 14:02:39.224788 <3>[ 84.737834] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11561 14:02:39.231583 <3>[ 84.738080] PM: Some devices failed to suspend, or early wake event detected
11562 14:02:39.306698 <6>[ 85.077728] OOM killer enabled.
11563 14:02:39.309820 rtcwake: <6>[ 85.077740] Restarting tasks ... done.
11564 14:02:39.310436 write error
11565 14:02:39.316340 <LA<5>[ 85.079734] random: crng reseeded on system resumption
11566 14:02:39.319523 VA_SIGNAL_TESTCA<6>[ 85.084929] PM: suspend exit
11567 14:02:39.326287 SE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11568 14:02:39.329580 rtcwake: assuming RTC uses UTC ...
11569 14:02:39.333074 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 14:01:41 2023
11570 14:02:39.350253 <6>[ 85.121576] PM: suspend entry (s2idle)
11571 14:02:39.353475 <6>[ 85.121620] Filesystems sync: 0.000 seconds
11572 14:02:39.357008 <6>[ 85.122157] Freezing user space processes
11573 14:02:39.363705 <6>[ 85.123838] Freezing user space processes completed (elapsed 0.001 seconds)
11574 14:02:39.370023 <6>[ 85.123849] OOM killer disabled.
11575 14:02:39.373518 <6>[ 85.123851] Freezing remaining freezable tasks
11576 14:02:39.380615 <6>[ 85.125199] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11577 14:02:39.387680 <6>[ 85.125212] printk: Suspending console(s) (use no_console_suspend to debug)
11578 14:02:42.781577 <3>[ 88.321783] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11579 14:02:42.791698 <3>[ 88.321835] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11580 14:02:42.801970 <3>[ 88.321895] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11581 14:02:42.808661 <3>[ 88.321947] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11582 14:02:42.815306 <3>[ 88.322126] PM: Some devices failed to suspend, or early wake event detected
11583 14:02:42.889747 <6>[ 88.661729] OOM killer enabled.
11584 14:02:42.893317 rtcwake: <6>[ 88.661741] Restarting tasks ... done.
11585 14:02:42.893879 write error
11586 14:02:42.899818 <5>[ 88.663644] random: crng reseeded on system resumption
11587 14:02:42.903417 <LAVA_SIGNAL_TES<6>[ 88.668924] PM: suspend exit
11588 14:02:42.910202 TCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11589 14:02:42.911068 Received signal: <TES<6>[> 88.668924] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11590 14:02:42.913150 rtcwake: assuming RTC uses UTC ...
11591 14:02:42.916141 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 14:01:45 2023
11592 14:02:42.934079 <6>[ 88.706074] PM: suspend entry (s2idle)
11593 14:02:42.937628 <6>[ 88.706120] Filesystems sync: 0.000 seconds
11594 14:02:42.940437 <6>[ 88.706663] Freezing user space processes
11595 14:02:42.947580 <6>[ 88.708391] Freezing user space processes completed (elapsed 0.001 seconds)
11596 14:02:42.950943 <6>[ 88.708403] OOM killer disabled.
11597 14:02:42.957515 <6>[ 88.708406] Freezing remaining freezable tasks
11598 14:02:42.964548 <6>[ 88.709391] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11599 14:02:42.970961 <6>[ 88.709396] printk: Suspending console(s) (use no_console_suspend to debug)
11600 14:02:46.366152 <3>[ 91.905690] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11601 14:02:46.375524 <3>[ 91.905723] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11602 14:02:46.385335 <3>[ 91.905777] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11603 14:02:46.392033 <3>[ 91.905825] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11604 14:02:46.398595 <3>[ 91.906132] PM: Some devices failed to suspend, or early wake event detected
11605 14:02:46.473990 <6>[ 92.245730] OOM killer enabled.
11606 14:02:46.476870 <6>[ 92.245742] Restarting tasks ... done.
11607 14:02:46.480295 <5>[ 92.251760] random: crng reseeded on system resumption
11608 14:02:46.483464 rtcwake: write error
11609 14:02:46.486644 <6>[ 92.262552] PM: suspend exit
11610 14:02:46.493738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11611 14:02:46.494461 + set +x
11612 14:02:46.495310 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11614 14:02:46.500306 <LAVA_SIGNAL_ENDRUN 0_sleep 11372169_1.5.2.3.1>
11615 14:02:46.500790 <LAVA_TEST_RUNNER EXIT>
11616 14:02:46.501419 Received signal: <ENDRUN> 0_sleep 11372169_1.5.2.3.1
11617 14:02:46.501837 Ending use of test pattern.
11618 14:02:46.502179 Ending test lava.0_sleep (11372169_1.5.2.3.1), duration 71.77
11620 14:02:46.503379 ok: lava_test_shell seems to have completed
11621 14:02:46.504179 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-6: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-3: fail
rtcwake-mem-5: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11622 14:02:46.504629 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11623 14:02:46.505105 end: 3 lava-test-retry (duration 00:01:12) [common]
11624 14:02:46.505611 start: 4 finalize (timeout 00:06:13) [common]
11625 14:02:46.506086 start: 4.1 power-off (timeout 00:00:30) [common]
11626 14:02:46.506888 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11627 14:02:46.598715 >> Command sent successfully.
11628 14:02:46.610750 Returned 0 in 0 seconds
11629 14:02:46.712107 end: 4.1 power-off (duration 00:00:00) [common]
11631 14:02:46.713727 start: 4.2 read-feedback (timeout 00:06:13) [common]
11632 14:02:46.715258 Listened to connection for namespace 'common' for up to 1s
11633 14:02:47.715803 Finalising connection for namespace 'common'
11634 14:02:47.716677 Disconnecting from shell: Finalise
11635 14:02:47.717162 / #
11636 14:02:47.818169 end: 4.2 read-feedback (duration 00:00:01) [common]
11637 14:02:47.818873 end: 4 finalize (duration 00:00:01) [common]
11638 14:02:47.819506 Cleaning after the job
11639 14:02:47.820278 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/ramdisk
11640 14:02:47.862614 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/kernel
11641 14:02:47.890656 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/dtb
11642 14:02:47.890884 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372169/tftp-deploy-yxj2t1zm/modules
11643 14:02:47.898174 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11372169
11644 14:02:48.069266 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11372169
11645 14:02:48.069449 Job finished correctly