Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 36
- Boot result: FAIL
- Warnings: 1
- Errors: 2
- Kernel Warnings: 24
1 13:57:30.517095 lava-dispatcher, installed at version: 2023.06
2 13:57:30.517329 start: 0 validate
3 13:57:30.517483 Start time: 2023-08-28 13:57:30.517475+00:00 (UTC)
4 13:57:30.517645 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:57:30.517796 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 13:57:30.786591 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:57:30.786899 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:57:31.054611 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:57:31.055394 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:57:55.614622 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:57:55.615298 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:57:56.144208 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:57:56.144949 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:57:56.422859 validate duration: 25.91
16 13:57:56.424097 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:57:56.424647 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:57:56.425297 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:57:56.425956 Not decompressing ramdisk as can be used compressed.
20 13:57:56.426435 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 13:57:56.426788 saving as /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/ramdisk/initrd.cpio.gz
22 13:57:56.427145 total size: 4665412 (4 MB)
23 13:57:59.524477 progress 0 % (0 MB)
24 13:57:59.529049 progress 5 % (0 MB)
25 13:57:59.530293 progress 10 % (0 MB)
26 13:57:59.531523 progress 15 % (0 MB)
27 13:57:59.532843 progress 20 % (0 MB)
28 13:57:59.534117 progress 25 % (1 MB)
29 13:57:59.535470 progress 30 % (1 MB)
30 13:57:59.536691 progress 35 % (1 MB)
31 13:57:59.537939 progress 40 % (1 MB)
32 13:57:59.539348 progress 45 % (2 MB)
33 13:57:59.540630 progress 50 % (2 MB)
34 13:57:59.541898 progress 55 % (2 MB)
35 13:57:59.543148 progress 60 % (2 MB)
36 13:57:59.544416 progress 65 % (2 MB)
37 13:57:59.545686 progress 70 % (3 MB)
38 13:57:59.546892 progress 75 % (3 MB)
39 13:57:59.548157 progress 80 % (3 MB)
40 13:57:59.549652 progress 85 % (3 MB)
41 13:57:59.550862 progress 90 % (4 MB)
42 13:57:59.552070 progress 95 % (4 MB)
43 13:57:59.553339 progress 100 % (4 MB)
44 13:57:59.553495 4 MB downloaded in 3.13 s (1.42 MB/s)
45 13:57:59.553643 end: 1.1.1 http-download (duration 00:00:03) [common]
47 13:57:59.553875 end: 1.1 download-retry (duration 00:00:03) [common]
48 13:57:59.553959 start: 1.2 download-retry (timeout 00:09:57) [common]
49 13:57:59.554042 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 13:57:59.554177 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:57:59.554247 saving as /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/kernel/Image
52 13:57:59.554307 total size: 49222144 (46 MB)
53 13:57:59.554366 No compression specified
54 13:57:59.555571 progress 0 % (0 MB)
55 13:57:59.568411 progress 5 % (2 MB)
56 13:57:59.581130 progress 10 % (4 MB)
57 13:57:59.593835 progress 15 % (7 MB)
58 13:57:59.606703 progress 20 % (9 MB)
59 13:57:59.619497 progress 25 % (11 MB)
60 13:57:59.632187 progress 30 % (14 MB)
61 13:57:59.644885 progress 35 % (16 MB)
62 13:57:59.657567 progress 40 % (18 MB)
63 13:57:59.670454 progress 45 % (21 MB)
64 13:57:59.683334 progress 50 % (23 MB)
65 13:57:59.696185 progress 55 % (25 MB)
66 13:57:59.709158 progress 60 % (28 MB)
67 13:57:59.721871 progress 65 % (30 MB)
68 13:57:59.734601 progress 70 % (32 MB)
69 13:57:59.747358 progress 75 % (35 MB)
70 13:57:59.760071 progress 80 % (37 MB)
71 13:57:59.772849 progress 85 % (39 MB)
72 13:57:59.785755 progress 90 % (42 MB)
73 13:57:59.798744 progress 95 % (44 MB)
74 13:57:59.811404 progress 100 % (46 MB)
75 13:57:59.811586 46 MB downloaded in 0.26 s (182.46 MB/s)
76 13:57:59.811755 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:57:59.811996 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:57:59.812083 start: 1.3 download-retry (timeout 00:09:57) [common]
80 13:57:59.812177 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 13:57:59.812323 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:57:59.812395 saving as /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/dtb/mt8192-asurada-spherion-r0.dtb
83 13:57:59.812455 total size: 47278 (0 MB)
84 13:57:59.812516 No compression specified
85 13:57:59.813658 progress 69 % (0 MB)
86 13:57:59.813940 progress 100 % (0 MB)
87 13:57:59.814095 0 MB downloaded in 0.00 s (27.53 MB/s)
88 13:57:59.814217 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:57:59.814436 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:57:59.814521 start: 1.4 download-retry (timeout 00:09:57) [common]
92 13:57:59.814602 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 13:57:59.814713 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 13:57:59.814780 saving as /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/nfsrootfs/full.rootfs.tar
95 13:57:59.814841 total size: 125290964 (119 MB)
96 13:57:59.814901 Using unxz to decompress xz
97 13:57:59.819126 progress 0 % (0 MB)
98 13:58:00.144652 progress 5 % (6 MB)
99 13:58:00.482618 progress 10 % (11 MB)
100 13:58:00.825651 progress 15 % (17 MB)
101 13:58:01.011215 progress 20 % (23 MB)
102 13:58:01.187627 progress 25 % (29 MB)
103 13:58:01.540080 progress 30 % (35 MB)
104 13:58:01.892616 progress 35 % (41 MB)
105 13:58:02.278025 progress 40 % (47 MB)
106 13:58:02.650898 progress 45 % (53 MB)
107 13:58:03.033315 progress 50 % (59 MB)
108 13:58:03.382011 progress 55 % (65 MB)
109 13:58:03.741654 progress 60 % (71 MB)
110 13:58:04.077882 progress 65 % (77 MB)
111 13:58:04.442763 progress 70 % (83 MB)
112 13:58:04.833536 progress 75 % (89 MB)
113 13:58:05.262919 progress 80 % (95 MB)
114 13:58:05.700677 progress 85 % (101 MB)
115 13:58:05.957852 progress 90 % (107 MB)
116 13:58:06.315361 progress 95 % (113 MB)
117 13:58:06.690611 progress 100 % (119 MB)
118 13:58:06.696298 119 MB downloaded in 6.88 s (17.36 MB/s)
119 13:58:06.696606 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:58:06.696954 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:58:06.697060 start: 1.5 download-retry (timeout 00:09:50) [common]
123 13:58:06.697165 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 13:58:06.697345 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:58:06.697420 saving as /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/modules/modules.tar
126 13:58:06.697501 total size: 8615960 (8 MB)
127 13:58:06.697604 Using unxz to decompress xz
128 13:58:06.702188 progress 0 % (0 MB)
129 13:58:06.723997 progress 5 % (0 MB)
130 13:58:06.746524 progress 10 % (0 MB)
131 13:58:06.773089 progress 15 % (1 MB)
132 13:58:06.798668 progress 20 % (1 MB)
133 13:58:06.825051 progress 25 % (2 MB)
134 13:58:06.851593 progress 30 % (2 MB)
135 13:58:06.879049 progress 35 % (2 MB)
136 13:58:06.904277 progress 40 % (3 MB)
137 13:58:06.929187 progress 45 % (3 MB)
138 13:58:06.955820 progress 50 % (4 MB)
139 13:58:06.981564 progress 55 % (4 MB)
140 13:58:07.006660 progress 60 % (4 MB)
141 13:58:07.029826 progress 65 % (5 MB)
142 13:58:07.057471 progress 70 % (5 MB)
143 13:58:07.081957 progress 75 % (6 MB)
144 13:58:07.108852 progress 80 % (6 MB)
145 13:58:07.139215 progress 85 % (7 MB)
146 13:58:07.166111 progress 90 % (7 MB)
147 13:58:07.190567 progress 95 % (7 MB)
148 13:58:07.215074 progress 100 % (8 MB)
149 13:58:07.221483 8 MB downloaded in 0.52 s (15.68 MB/s)
150 13:58:07.221858 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:58:07.222130 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:58:07.222223 start: 1.6 prepare-tftp-overlay (timeout 00:09:49) [common]
154 13:58:07.222316 start: 1.6.1 extract-nfsrootfs (timeout 00:09:49) [common]
155 13:58:09.398971 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11372189/extract-nfsrootfs-khc8asxh
156 13:58:09.399187 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 13:58:09.399291 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 13:58:09.399474 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i
159 13:58:09.399609 makedir: /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin
160 13:58:09.399711 makedir: /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/tests
161 13:58:09.399810 makedir: /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/results
162 13:58:09.399913 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-add-keys
163 13:58:09.400059 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-add-sources
164 13:58:09.400205 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-background-process-start
165 13:58:09.400334 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-background-process-stop
166 13:58:09.400462 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-common-functions
167 13:58:09.400586 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-echo-ipv4
168 13:58:09.400723 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-install-packages
169 13:58:09.400848 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-installed-packages
170 13:58:09.400974 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-os-build
171 13:58:09.401097 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-probe-channel
172 13:58:09.401220 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-probe-ip
173 13:58:09.401343 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-target-ip
174 13:58:09.401467 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-target-mac
175 13:58:09.401590 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-target-storage
176 13:58:09.401715 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-test-case
177 13:58:09.401843 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-test-event
178 13:58:09.401965 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-test-feedback
179 13:58:09.402090 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-test-raise
180 13:58:09.402213 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-test-reference
181 13:58:09.402338 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-test-runner
182 13:58:09.402464 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-test-set
183 13:58:09.402588 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-test-shell
184 13:58:09.402714 Updating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-install-packages (oe)
185 13:58:09.402871 Updating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/bin/lava-installed-packages (oe)
186 13:58:09.402995 Creating /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/environment
187 13:58:09.403091 LAVA metadata
188 13:58:09.403162 - LAVA_JOB_ID=11372189
189 13:58:09.403225 - LAVA_DISPATCHER_IP=192.168.201.1
190 13:58:09.403332 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
191 13:58:09.403399 skipped lava-vland-overlay
192 13:58:09.403474 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 13:58:09.403555 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
194 13:58:09.403615 skipped lava-multinode-overlay
195 13:58:09.403686 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 13:58:09.403763 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
197 13:58:09.403837 Loading test definitions
198 13:58:09.403928 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
199 13:58:09.403998 Using /lava-11372189 at stage 0
200 13:58:09.404318 uuid=11372189_1.6.2.3.1 testdef=None
201 13:58:09.404408 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 13:58:09.404493 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
203 13:58:09.405327 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 13:58:09.405554 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
206 13:58:09.406249 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 13:58:09.406478 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
209 13:58:09.407101 runner path: /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/0/tests/0_dmesg test_uuid 11372189_1.6.2.3.1
210 13:58:09.407260 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 13:58:09.407485 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:47) [common]
213 13:58:09.407557 Using /lava-11372189 at stage 1
214 13:58:09.407867 uuid=11372189_1.6.2.3.5 testdef=None
215 13:58:09.407955 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 13:58:09.408041 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
217 13:58:09.408554 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 13:58:09.408818 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
220 13:58:09.409463 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 13:58:09.409689 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
223 13:58:09.410347 runner path: /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/1/tests/1_bootrr test_uuid 11372189_1.6.2.3.5
224 13:58:09.410502 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 13:58:09.410705 Creating lava-test-runner.conf files
227 13:58:09.410768 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/0 for stage 0
228 13:58:09.410859 - 0_dmesg
229 13:58:09.410939 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11372189/lava-overlay-0bek_y4i/lava-11372189/1 for stage 1
230 13:58:09.411030 - 1_bootrr
231 13:58:09.411125 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 13:58:09.411209 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
233 13:58:09.418782 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 13:58:09.418936 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:47) [common]
235 13:58:09.419028 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 13:58:09.419115 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 13:58:09.419200 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:47) [common]
238 13:58:09.540439 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 13:58:09.540874 start: 1.6.4 extract-modules (timeout 00:09:47) [common]
240 13:58:09.540995 extracting modules file /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11372189/extract-nfsrootfs-khc8asxh
241 13:58:09.764409 extracting modules file /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11372189/extract-overlay-ramdisk-f9pxbc6v/ramdisk
242 13:58:09.994050 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 13:58:09.994236 start: 1.6.5 apply-overlay-tftp (timeout 00:09:46) [common]
244 13:58:09.994338 [common] Applying overlay to NFS
245 13:58:09.994412 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11372189/compress-overlay-j8xa1af5/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11372189/extract-nfsrootfs-khc8asxh
246 13:58:10.002591 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 13:58:10.002754 start: 1.6.6 configure-preseed-file (timeout 00:09:46) [common]
248 13:58:10.002849 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 13:58:10.002934 start: 1.6.7 compress-ramdisk (timeout 00:09:46) [common]
250 13:58:10.003014 Building ramdisk /var/lib/lava/dispatcher/tmp/11372189/extract-overlay-ramdisk-f9pxbc6v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11372189/extract-overlay-ramdisk-f9pxbc6v/ramdisk
251 13:58:10.327666 >> 119225 blocks
252 13:58:12.253375 rename /var/lib/lava/dispatcher/tmp/11372189/extract-overlay-ramdisk-f9pxbc6v/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/ramdisk/ramdisk.cpio.gz
253 13:58:12.253829 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 13:58:12.253950 start: 1.6.8 prepare-kernel (timeout 00:09:44) [common]
255 13:58:12.254057 start: 1.6.8.1 prepare-fit (timeout 00:09:44) [common]
256 13:58:12.254174 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/kernel/Image'
257 13:58:24.726808 Returned 0 in 12 seconds
258 13:58:24.827893 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/kernel/image.itb
259 13:58:25.190136 output: FIT description: Kernel Image image with one or more FDT blobs
260 13:58:25.190489 output: Created: Mon Aug 28 14:58:25 2023
261 13:58:25.190563 output: Image 0 (kernel-1)
262 13:58:25.190630 output: Description:
263 13:58:25.190693 output: Created: Mon Aug 28 14:58:25 2023
264 13:58:25.190755 output: Type: Kernel Image
265 13:58:25.190813 output: Compression: lzma compressed
266 13:58:25.190872 output: Data Size: 11039834 Bytes = 10781.09 KiB = 10.53 MiB
267 13:58:25.190928 output: Architecture: AArch64
268 13:58:25.190985 output: OS: Linux
269 13:58:25.191043 output: Load Address: 0x00000000
270 13:58:25.191095 output: Entry Point: 0x00000000
271 13:58:25.191147 output: Hash algo: crc32
272 13:58:25.191198 output: Hash value: 946c5cd4
273 13:58:25.191282 output: Image 1 (fdt-1)
274 13:58:25.191355 output: Description: mt8192-asurada-spherion-r0
275 13:58:25.191422 output: Created: Mon Aug 28 14:58:25 2023
276 13:58:25.191489 output: Type: Flat Device Tree
277 13:58:25.191569 output: Compression: uncompressed
278 13:58:25.191633 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 13:58:25.191684 output: Architecture: AArch64
280 13:58:25.191735 output: Hash algo: crc32
281 13:58:25.191787 output: Hash value: cc4352de
282 13:58:25.191837 output: Image 2 (ramdisk-1)
283 13:58:25.191889 output: Description: unavailable
284 13:58:25.191939 output: Created: Mon Aug 28 14:58:25 2023
285 13:58:25.191990 output: Type: RAMDisk Image
286 13:58:25.192041 output: Compression: Unknown Compression
287 13:58:25.192091 output: Data Size: 17773769 Bytes = 17357.20 KiB = 16.95 MiB
288 13:58:25.192142 output: Architecture: AArch64
289 13:58:25.192193 output: OS: Linux
290 13:58:25.192244 output: Load Address: unavailable
291 13:58:25.192295 output: Entry Point: unavailable
292 13:58:25.192345 output: Hash algo: crc32
293 13:58:25.192396 output: Hash value: 19889468
294 13:58:25.192447 output: Default Configuration: 'conf-1'
295 13:58:25.192498 output: Configuration 0 (conf-1)
296 13:58:25.192548 output: Description: mt8192-asurada-spherion-r0
297 13:58:25.192599 output: Kernel: kernel-1
298 13:58:25.192650 output: Init Ramdisk: ramdisk-1
299 13:58:25.192743 output: FDT: fdt-1
300 13:58:25.192795 output: Loadables: kernel-1
301 13:58:25.192845 output:
302 13:58:25.193043 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 13:58:25.193142 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 13:58:25.193239 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 13:58:25.193333 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
306 13:58:25.193412 No LXC device requested
307 13:58:25.193490 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 13:58:25.193571 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
309 13:58:25.193647 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 13:58:25.193717 Checking files for TFTP limit of 4294967296 bytes.
311 13:58:25.194217 end: 1 tftp-deploy (duration 00:00:29) [common]
312 13:58:25.194319 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 13:58:25.194408 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 13:58:25.194532 substitutions:
315 13:58:25.194596 - {DTB}: 11372189/tftp-deploy-2hykufja/dtb/mt8192-asurada-spherion-r0.dtb
316 13:58:25.194658 - {INITRD}: 11372189/tftp-deploy-2hykufja/ramdisk/ramdisk.cpio.gz
317 13:58:25.194715 - {KERNEL}: 11372189/tftp-deploy-2hykufja/kernel/Image
318 13:58:25.194770 - {LAVA_MAC}: None
319 13:58:25.194825 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11372189/extract-nfsrootfs-khc8asxh
320 13:58:25.194880 - {NFS_SERVER_IP}: 192.168.201.1
321 13:58:25.194934 - {PRESEED_CONFIG}: None
322 13:58:25.194987 - {PRESEED_LOCAL}: None
323 13:58:25.195039 - {RAMDISK}: 11372189/tftp-deploy-2hykufja/ramdisk/ramdisk.cpio.gz
324 13:58:25.195091 - {ROOT_PART}: None
325 13:58:25.195145 - {ROOT}: None
326 13:58:25.195198 - {SERVER_IP}: 192.168.201.1
327 13:58:25.195252 - {TEE}: None
328 13:58:25.195352 Parsed boot commands:
329 13:58:25.195450 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 13:58:25.195633 Parsed boot commands: tftpboot 192.168.201.1 11372189/tftp-deploy-2hykufja/kernel/image.itb 11372189/tftp-deploy-2hykufja/kernel/cmdline
331 13:58:25.195718 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 13:58:25.195802 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 13:58:25.195894 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 13:58:25.195980 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 13:58:25.196052 Not connected, no need to disconnect.
336 13:58:25.196125 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 13:58:25.196204 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 13:58:25.196271 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
339 13:58:25.200388 Setting prompt string to ['lava-test: # ']
340 13:58:25.200779 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 13:58:25.200885 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 13:58:25.200982 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 13:58:25.201117 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 13:58:25.201355 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
345 13:58:30.338796 >> Command sent successfully.
346 13:58:30.341306 Returned 0 in 5 seconds
347 13:58:30.441675 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 13:58:30.442002 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 13:58:30.442108 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 13:58:30.442204 Setting prompt string to 'Starting depthcharge on Spherion...'
352 13:58:30.442277 Changing prompt to 'Starting depthcharge on Spherion...'
353 13:58:30.442353 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 13:58:30.442644 [Enter `^Ec?' for help]
355 13:58:30.616811
356 13:58:30.616965
357 13:58:30.617041 F0: 102B 0000
358 13:58:30.617106
359 13:58:30.617166 F3: 1001 0000 [0200]
360 13:58:30.617232
361 13:58:30.620258 F3: 1001 0000
362 13:58:30.620366
363 13:58:30.620445 F7: 102D 0000
364 13:58:30.620506
365 13:58:30.623320 F1: 0000 0000
366 13:58:30.623403
367 13:58:30.623462 V0: 0000 0000 [0001]
368 13:58:30.623533
369 13:58:30.623593 00: 0007 8000
370 13:58:30.626929
371 13:58:30.627000 01: 0000 0000
372 13:58:30.627099
373 13:58:30.627160 BP: 0C00 0209 [0000]
374 13:58:30.627217
375 13:58:30.629919 G0: 1182 0000
376 13:58:30.630000
377 13:58:30.630065 EC: 0000 0021 [4000]
378 13:58:30.630124
379 13:58:30.633777 S7: 0000 0000 [0000]
380 13:58:30.633851
381 13:58:30.633921 CC: 0000 0000 [0001]
382 13:58:30.633983
383 13:58:30.637229 T0: 0000 0040 [010F]
384 13:58:30.637313
385 13:58:30.637380 Jump to BL
386 13:58:30.637439
387 13:58:30.663334
388 13:58:30.663433
389 13:58:30.663501
390 13:58:30.670747 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 13:58:30.674658 ARM64: Exception handlers installed.
392 13:58:30.678435 ARM64: Testing exception
393 13:58:30.681521 ARM64: Done test exception
394 13:58:30.688361 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 13:58:30.698602 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 13:58:30.705675 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 13:58:30.715689 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 13:58:30.722488 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 13:58:30.729031 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 13:58:30.740013 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 13:58:30.747063 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 13:58:30.766491 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 13:58:30.769405 WDT: Last reset was cold boot
404 13:58:30.772792 SPI1(PAD0) initialized at 2873684 Hz
405 13:58:30.776167 SPI5(PAD0) initialized at 992727 Hz
406 13:58:30.779509 VBOOT: Loading verstage.
407 13:58:30.786017 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 13:58:30.789796 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 13:58:30.793027 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 13:58:30.795889 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 13:58:30.803445 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 13:58:30.810554 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 13:58:30.821159 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 13:58:30.821240
415 13:58:30.821312
416 13:58:30.830957 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 13:58:30.834463 ARM64: Exception handlers installed.
418 13:58:30.838285 ARM64: Testing exception
419 13:58:30.838389 ARM64: Done test exception
420 13:58:30.844933 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 13:58:30.848306 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 13:58:30.861996 Probing TPM: . done!
423 13:58:30.862111 TPM ready after 0 ms
424 13:58:30.867215 Connected to device vid:did:rid of 1ae0:0028:00
425 13:58:30.878219 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 13:58:30.935181 Initialized TPM device CR50 revision 0
427 13:58:30.946600 tlcl_send_startup: Startup return code is 0
428 13:58:30.946698 TPM: setup succeeded
429 13:58:30.958213 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 13:58:30.966806 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 13:58:30.979054 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 13:58:30.989096 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 13:58:30.992582 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 13:58:30.997332 in-header: 03 07 00 00 08 00 00 00
435 13:58:31.001268 in-data: aa e4 47 04 13 02 00 00
436 13:58:31.004825 Chrome EC: UHEPI supported
437 13:58:31.012429 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 13:58:31.016114 in-header: 03 ad 00 00 08 00 00 00
439 13:58:31.016197 in-data: 00 20 20 08 00 00 00 00
440 13:58:31.019677 Phase 1
441 13:58:31.023498 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 13:58:31.027236 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 13:58:31.034641 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 13:58:31.038234 Recovery requested (1009000e)
445 13:58:31.046063 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 13:58:31.051405 tlcl_extend: response is 0
447 13:58:31.060997 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 13:58:31.066512 tlcl_extend: response is 0
449 13:58:31.073662 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 13:58:31.093536 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 13:58:31.100325 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 13:58:31.100406
453 13:58:31.100471
454 13:58:31.110983 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 13:58:31.114767 ARM64: Exception handlers installed.
456 13:58:31.114850 ARM64: Testing exception
457 13:58:31.117873 ARM64: Done test exception
458 13:58:31.138774 pmic_efuse_setting: Set efuses in 11 msecs
459 13:58:31.143024 pmwrap_interface_init: Select PMIF_VLD_RDY
460 13:58:31.149410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 13:58:31.152676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 13:58:31.156505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 13:58:31.163985 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 13:58:31.168251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 13:58:31.171325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 13:58:31.179297 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 13:58:31.182650 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 13:58:31.186313 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 13:58:31.190479 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 13:58:31.194261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 13:58:31.202034 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 13:58:31.206160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 13:58:31.209383 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 13:58:31.216606 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 13:58:31.224305 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 13:58:31.228225 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 13:58:31.235249 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 13:58:31.238965 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 13:58:31.246697 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 13:58:31.250170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 13:58:31.257463 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 13:58:31.261478 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 13:58:31.268746 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 13:58:31.272714 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 13:58:31.280398 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 13:58:31.283949 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 13:58:31.287325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 13:58:31.294513 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 13:58:31.297905 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 13:58:31.302202 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 13:58:31.309120 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 13:58:31.313272 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 13:58:31.316557 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 13:58:31.323923 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 13:58:31.327934 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 13:58:31.331539 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 13:58:31.339029 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 13:58:31.343133 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 13:58:31.346181 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 13:58:31.349988 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 13:58:31.357251 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 13:58:31.361057 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 13:58:31.365248 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 13:58:31.368906 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 13:58:31.372516 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 13:58:31.375936 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 13:58:31.379734 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 13:58:31.387235 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 13:58:31.390632 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 13:58:31.394535 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 13:58:31.402120 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 13:58:31.409431 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 13:58:31.416702 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 13:58:31.423927 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 13:58:31.431735 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 13:58:31.435194 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 13:58:31.439561 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 13:58:31.446542 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 13:58:31.453491 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x19
520 13:58:31.456352 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 13:58:31.463972 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 13:58:31.467415 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 13:58:31.476206 [RTC]rtc_get_frequency_meter,154: input=15, output=790
524 13:58:31.485868 [RTC]rtc_get_frequency_meter,154: input=23, output=980
525 13:58:31.495295 [RTC]rtc_get_frequency_meter,154: input=19, output=884
526 13:58:31.505306 [RTC]rtc_get_frequency_meter,154: input=17, output=838
527 13:58:31.515118 [RTC]rtc_get_frequency_meter,154: input=16, output=813
528 13:58:31.524134 [RTC]rtc_get_frequency_meter,154: input=15, output=790
529 13:58:31.533940 [RTC]rtc_get_frequency_meter,154: input=16, output=815
530 13:58:31.537692 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
531 13:58:31.541419 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
532 13:58:31.545059 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 13:58:31.553279 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 13:58:31.556657 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 13:58:31.560050 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 13:58:31.563712 ADC[4]: Raw value=901328 ID=7
537 13:58:31.563818 ADC[3]: Raw value=213336 ID=1
538 13:58:31.567574 RAM Code: 0x71
539 13:58:31.571588 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 13:58:31.575448 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 13:58:31.586159 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 13:58:31.589672 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 13:58:31.592775 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 13:58:31.596943 in-header: 03 07 00 00 08 00 00 00
545 13:58:31.600636 in-data: aa e4 47 04 13 02 00 00
546 13:58:31.603795 Chrome EC: UHEPI supported
547 13:58:31.611492 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 13:58:31.614964 in-header: 03 ed 00 00 08 00 00 00
549 13:58:31.618936 in-data: 80 20 60 08 00 00 00 00
550 13:58:31.622535 MRC: failed to locate region type 0.
551 13:58:31.626597 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 13:58:31.630468 DRAM-K: Running full calibration
553 13:58:31.637628 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 13:58:31.637713 header.status = 0x0
555 13:58:31.641200 header.version = 0x6 (expected: 0x6)
556 13:58:31.645242 header.size = 0xd00 (expected: 0xd00)
557 13:58:31.649162 header.flags = 0x0
558 13:58:31.651965 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 13:58:31.671095 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
560 13:58:31.678533 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 13:58:31.682297 dram_init: ddr_geometry: 2
562 13:58:31.682372 [EMI] MDL number = 2
563 13:58:31.686386 [EMI] Get MDL freq = 0
564 13:58:31.686479 dram_init: ddr_type: 0
565 13:58:31.689773 is_discrete_lpddr4: 1
566 13:58:31.693353 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 13:58:31.693462
568 13:58:31.693606
569 13:58:31.693740 [Bian_co] ETT version 0.0.0.1
570 13:58:31.701115 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 13:58:31.701198
572 13:58:31.704800 dramc_set_vcore_voltage set vcore to 650000
573 13:58:31.704915 Read voltage for 800, 4
574 13:58:31.708562 Vio18 = 0
575 13:58:31.708720 Vcore = 650000
576 13:58:31.708804 Vdram = 0
577 13:58:31.708878 Vddq = 0
578 13:58:31.712463 Vmddr = 0
579 13:58:31.712576 dram_init: config_dvfs: 1
580 13:58:31.719729 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 13:58:31.723315 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 13:58:31.726839 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
583 13:58:31.730580 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
584 13:58:31.733786 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
585 13:58:31.737197 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
586 13:58:31.740495 MEM_TYPE=3, freq_sel=18
587 13:58:31.743781 sv_algorithm_assistance_LP4_1600
588 13:58:31.747325 ============ PULL DRAM RESETB DOWN ============
589 13:58:31.750735 ========== PULL DRAM RESETB DOWN end =========
590 13:58:31.757416 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 13:58:31.760846 ===================================
592 13:58:31.760924 LPDDR4 DRAM CONFIGURATION
593 13:58:31.764559 ===================================
594 13:58:31.767903 EX_ROW_EN[0] = 0x0
595 13:58:31.770784 EX_ROW_EN[1] = 0x0
596 13:58:31.770883 LP4Y_EN = 0x0
597 13:58:31.774212 WORK_FSP = 0x0
598 13:58:31.774315 WL = 0x2
599 13:58:31.777825 RL = 0x2
600 13:58:31.777927 BL = 0x2
601 13:58:31.781150 RPST = 0x0
602 13:58:31.781237 RD_PRE = 0x0
603 13:58:31.784386 WR_PRE = 0x1
604 13:58:31.784503 WR_PST = 0x0
605 13:58:31.787967 DBI_WR = 0x0
606 13:58:31.788065 DBI_RD = 0x0
607 13:58:31.791095 OTF = 0x1
608 13:58:31.794672 ===================================
609 13:58:31.798024 ===================================
610 13:58:31.798124 ANA top config
611 13:58:31.801160 ===================================
612 13:58:31.804770 DLL_ASYNC_EN = 0
613 13:58:31.808413 ALL_SLAVE_EN = 1
614 13:58:31.808514 NEW_RANK_MODE = 1
615 13:58:31.811377 DLL_IDLE_MODE = 1
616 13:58:31.814580 LP45_APHY_COMB_EN = 1
617 13:58:31.818227 TX_ODT_DIS = 1
618 13:58:31.818367 NEW_8X_MODE = 1
619 13:58:31.821425 ===================================
620 13:58:31.824762 ===================================
621 13:58:31.828133 data_rate = 1600
622 13:58:31.831598 CKR = 1
623 13:58:31.835234 DQ_P2S_RATIO = 8
624 13:58:31.838138 ===================================
625 13:58:31.841892 CA_P2S_RATIO = 8
626 13:58:31.844991 DQ_CA_OPEN = 0
627 13:58:31.845101 DQ_SEMI_OPEN = 0
628 13:58:31.848283 CA_SEMI_OPEN = 0
629 13:58:31.851767 CA_FULL_RATE = 0
630 13:58:31.854770 DQ_CKDIV4_EN = 1
631 13:58:31.858673 CA_CKDIV4_EN = 1
632 13:58:31.861541 CA_PREDIV_EN = 0
633 13:58:31.861642 PH8_DLY = 0
634 13:58:31.864987 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 13:58:31.868876 DQ_AAMCK_DIV = 4
636 13:58:31.871844 CA_AAMCK_DIV = 4
637 13:58:31.875380 CA_ADMCK_DIV = 4
638 13:58:31.875499 DQ_TRACK_CA_EN = 0
639 13:58:31.878481 CA_PICK = 800
640 13:58:31.882420 CA_MCKIO = 800
641 13:58:31.885237 MCKIO_SEMI = 0
642 13:58:31.888846 PLL_FREQ = 3068
643 13:58:31.892760 DQ_UI_PI_RATIO = 32
644 13:58:31.892862 CA_UI_PI_RATIO = 0
645 13:58:31.896094 ===================================
646 13:58:31.899801 ===================================
647 13:58:31.903731 memory_type:LPDDR4
648 13:58:31.903833 GP_NUM : 10
649 13:58:31.907508 SRAM_EN : 1
650 13:58:31.907581 MD32_EN : 0
651 13:58:31.911833 ===================================
652 13:58:31.915529 [ANA_INIT] >>>>>>>>>>>>>>
653 13:58:31.919450 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 13:58:31.923072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 13:58:31.923148 ===================================
656 13:58:31.927002 data_rate = 1600,PCW = 0X7600
657 13:58:31.929994 ===================================
658 13:58:31.933196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 13:58:31.939858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 13:58:31.943224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 13:58:31.949892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 13:58:31.953197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 13:58:31.956588 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 13:58:31.956721 [ANA_INIT] flow start
665 13:58:31.959909 [ANA_INIT] PLL >>>>>>>>
666 13:58:31.963230 [ANA_INIT] PLL <<<<<<<<
667 13:58:31.966676 [ANA_INIT] MIDPI >>>>>>>>
668 13:58:31.966749 [ANA_INIT] MIDPI <<<<<<<<
669 13:58:31.970060 [ANA_INIT] DLL >>>>>>>>
670 13:58:31.973682 [ANA_INIT] flow end
671 13:58:31.976778 ============ LP4 DIFF to SE enter ============
672 13:58:31.979834 ============ LP4 DIFF to SE exit ============
673 13:58:31.983230 [ANA_INIT] <<<<<<<<<<<<<
674 13:58:31.986550 [Flow] Enable top DCM control >>>>>
675 13:58:31.990077 [Flow] Enable top DCM control <<<<<
676 13:58:31.990182 Enable DLL master slave shuffle
677 13:58:31.996821 ==============================================================
678 13:58:32.000119 Gating Mode config
679 13:58:32.003746 ==============================================================
680 13:58:32.007168 Config description:
681 13:58:32.017227 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 13:58:32.023553 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 13:58:32.026869 SELPH_MODE 0: By rank 1: By Phase
684 13:58:32.033979 ==============================================================
685 13:58:32.037053 GAT_TRACK_EN = 1
686 13:58:32.040456 RX_GATING_MODE = 2
687 13:58:32.043928 RX_GATING_TRACK_MODE = 2
688 13:58:32.044012 SELPH_MODE = 1
689 13:58:32.047298 PICG_EARLY_EN = 1
690 13:58:32.050666 VALID_LAT_VALUE = 1
691 13:58:32.057382 ==============================================================
692 13:58:32.060699 Enter into Gating configuration >>>>
693 13:58:32.064053 Exit from Gating configuration <<<<
694 13:58:32.067131 Enter into DVFS_PRE_config >>>>>
695 13:58:32.077323 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 13:58:32.080778 Exit from DVFS_PRE_config <<<<<
697 13:58:32.084198 Enter into PICG configuration >>>>
698 13:58:32.087587 Exit from PICG configuration <<<<
699 13:58:32.091060 [RX_INPUT] configuration >>>>>
700 13:58:32.093989 [RX_INPUT] configuration <<<<<
701 13:58:32.097441 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 13:58:32.104253 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 13:58:32.108068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 13:58:32.115438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 13:58:32.121736 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 13:58:32.128589 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 13:58:32.132129 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 13:58:32.135431 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 13:58:32.138780 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 13:58:32.145666 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 13:58:32.148673 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 13:58:32.152229 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 13:58:32.155338 ===================================
714 13:58:32.158596 LPDDR4 DRAM CONFIGURATION
715 13:58:32.162300 ===================================
716 13:58:32.162388 EX_ROW_EN[0] = 0x0
717 13:58:32.165719 EX_ROW_EN[1] = 0x0
718 13:58:32.168937 LP4Y_EN = 0x0
719 13:58:32.169023 WORK_FSP = 0x0
720 13:58:32.172328 WL = 0x2
721 13:58:32.172413 RL = 0x2
722 13:58:32.175702 BL = 0x2
723 13:58:32.175789 RPST = 0x0
724 13:58:32.179112 RD_PRE = 0x0
725 13:58:32.179198 WR_PRE = 0x1
726 13:58:32.182290 WR_PST = 0x0
727 13:58:32.182375 DBI_WR = 0x0
728 13:58:32.186253 DBI_RD = 0x0
729 13:58:32.186338 OTF = 0x1
730 13:58:32.189290 ===================================
731 13:58:32.192632 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 13:58:32.196172 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 13:58:32.202783 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 13:58:32.206419 ===================================
735 13:58:32.206505 LPDDR4 DRAM CONFIGURATION
736 13:58:32.209762 ===================================
737 13:58:32.213247 EX_ROW_EN[0] = 0x10
738 13:58:32.216580 EX_ROW_EN[1] = 0x0
739 13:58:32.216722 LP4Y_EN = 0x0
740 13:58:32.219881 WORK_FSP = 0x0
741 13:58:32.219959 WL = 0x2
742 13:58:32.223892 RL = 0x2
743 13:58:32.223977 BL = 0x2
744 13:58:32.226484 RPST = 0x0
745 13:58:32.226567 RD_PRE = 0x0
746 13:58:32.229631 WR_PRE = 0x1
747 13:58:32.229715 WR_PST = 0x0
748 13:58:32.233443 DBI_WR = 0x0
749 13:58:32.233527 DBI_RD = 0x0
750 13:58:32.237122 OTF = 0x1
751 13:58:32.240014 ===================================
752 13:58:32.246691 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 13:58:32.250251 nWR fixed to 40
754 13:58:32.250331 [ModeRegInit_LP4] CH0 RK0
755 13:58:32.253910 [ModeRegInit_LP4] CH0 RK1
756 13:58:32.256740 [ModeRegInit_LP4] CH1 RK0
757 13:58:32.256820 [ModeRegInit_LP4] CH1 RK1
758 13:58:32.260045 match AC timing 13
759 13:58:32.263387 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 13:58:32.267026 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 13:58:32.273695 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 13:58:32.277171 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 13:58:32.283732 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 13:58:32.283837 [EMI DOE] emi_dcm 0
765 13:58:32.286919 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 13:58:32.286997 ==
767 13:58:32.290506 Dram Type= 6, Freq= 0, CH_0, rank 0
768 13:58:32.297217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 13:58:32.297300 ==
770 13:58:32.300577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 13:58:32.307172 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 13:58:32.316591 [CA 0] Center 37 (7~68) winsize 62
773 13:58:32.320002 [CA 1] Center 37 (6~68) winsize 63
774 13:58:32.323335 [CA 2] Center 35 (5~66) winsize 62
775 13:58:32.326624 [CA 3] Center 34 (4~65) winsize 62
776 13:58:32.330055 [CA 4] Center 34 (3~65) winsize 63
777 13:58:32.333219 [CA 5] Center 33 (3~64) winsize 62
778 13:58:32.333301
779 13:58:32.336816 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 13:58:32.336898
781 13:58:32.340345 [CATrainingPosCal] consider 1 rank data
782 13:58:32.343397 u2DelayCellTimex100 = 270/100 ps
783 13:58:32.346845 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 13:58:32.350297 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
785 13:58:32.353906 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
786 13:58:32.360670 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
787 13:58:32.363806 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
788 13:58:32.367020 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 13:58:32.367129
790 13:58:32.370586 CA PerBit enable=1, Macro0, CA PI delay=33
791 13:58:32.370667
792 13:58:32.373574 [CBTSetCACLKResult] CA Dly = 33
793 13:58:32.373656 CS Dly: 5 (0~36)
794 13:58:32.373721 ==
795 13:58:32.377570 Dram Type= 6, Freq= 0, CH_0, rank 1
796 13:58:32.383438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 13:58:32.383521 ==
798 13:58:32.387241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 13:58:32.393635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 13:58:32.403034 [CA 0] Center 37 (6~68) winsize 63
801 13:58:32.406111 [CA 1] Center 37 (6~68) winsize 63
802 13:58:32.409861 [CA 2] Center 35 (4~66) winsize 63
803 13:58:32.412928 [CA 3] Center 35 (4~66) winsize 63
804 13:58:32.416548 [CA 4] Center 33 (3~64) winsize 62
805 13:58:32.419404 [CA 5] Center 33 (3~64) winsize 62
806 13:58:32.419486
807 13:58:32.422902 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 13:58:32.423011
809 13:58:32.426362 [CATrainingPosCal] consider 2 rank data
810 13:58:32.429415 u2DelayCellTimex100 = 270/100 ps
811 13:58:32.433465 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 13:58:32.436916 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
813 13:58:32.439941 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
814 13:58:32.446864 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 13:58:32.450408 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 13:58:32.453179 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 13:58:32.453261
818 13:58:32.456599 CA PerBit enable=1, Macro0, CA PI delay=33
819 13:58:32.456719
820 13:58:32.459975 [CBTSetCACLKResult] CA Dly = 33
821 13:58:32.460087 CS Dly: 5 (0~37)
822 13:58:32.460183
823 13:58:32.463747 ----->DramcWriteLeveling(PI) begin...
824 13:58:32.463830 ==
825 13:58:32.466874 Dram Type= 6, Freq= 0, CH_0, rank 0
826 13:58:32.473951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 13:58:32.474033 ==
828 13:58:32.474098 Write leveling (Byte 0): 27 => 27
829 13:58:32.477366 Write leveling (Byte 1): 27 => 27
830 13:58:32.481055 DramcWriteLeveling(PI) end<-----
831 13:58:32.481138
832 13:58:32.481203 ==
833 13:58:32.485019 Dram Type= 6, Freq= 0, CH_0, rank 0
834 13:58:32.488368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 13:58:32.488447 ==
836 13:58:32.492374 [Gating] SW mode calibration
837 13:58:32.498839 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 13:58:32.506258 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 13:58:32.509450 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 13:58:32.512536 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
841 13:58:32.515814 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
842 13:58:32.522840 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 13:58:32.526633 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 13:58:32.529419 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 13:58:32.536237 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 13:58:32.539432 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 13:58:32.542800 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 13:58:32.549557 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 13:58:32.553142 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 13:58:32.556367 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 13:58:32.560247 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 13:58:32.566606 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 13:58:32.569681 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 13:58:32.573807 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 13:58:32.579925 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:58:32.583509 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:58:32.587147 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
858 13:58:32.594045 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
859 13:58:32.597010 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:58:32.600339 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:58:32.606956 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:58:32.610139 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:58:32.613740 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:58:32.617536 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 13:58:32.624300 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 13:58:32.627374 0 9 12 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
867 13:58:32.630936 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 13:58:32.637205 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 13:58:32.640480 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 13:58:32.644002 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 13:58:32.650599 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 13:58:32.653969 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
873 13:58:32.657718 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
874 13:58:32.664190 0 10 12 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
875 13:58:32.667877 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 13:58:32.671021 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 13:58:32.674322 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 13:58:32.680963 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 13:58:32.684135 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 13:58:32.687593 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
881 13:58:32.694832 0 11 8 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
882 13:58:32.697784 0 11 12 | B1->B0 | 3737 4040 | 0 0 | (1 1) (0 0)
883 13:58:32.701218 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 13:58:32.707783 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 13:58:32.710991 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 13:58:32.714697 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 13:58:32.721367 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 13:58:32.724438 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 13:58:32.727874 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
890 13:58:32.731559 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
891 13:58:32.738162 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 13:58:32.741642 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 13:58:32.745295 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 13:58:32.751769 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 13:58:32.754761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 13:58:32.758333 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 13:58:32.765076 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 13:58:32.768339 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 13:58:32.771469 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 13:58:32.778422 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 13:58:32.781473 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 13:58:32.785125 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 13:58:32.788387 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 13:58:32.795304 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:58:32.799153 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
906 13:58:32.802207 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
907 13:58:32.805252 Total UI for P1: 0, mck2ui 16
908 13:58:32.808444 best dqsien dly found for B0: ( 0, 14, 8)
909 13:58:32.811907 Total UI for P1: 0, mck2ui 16
910 13:58:32.815379 best dqsien dly found for B1: ( 0, 14, 8)
911 13:58:32.818890 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
912 13:58:32.822286 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
913 13:58:32.822367
914 13:58:32.825805 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
915 13:58:32.832162 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
916 13:58:32.832244 [Gating] SW calibration Done
917 13:58:32.832309 ==
918 13:58:32.835740 Dram Type= 6, Freq= 0, CH_0, rank 0
919 13:58:32.842323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 13:58:32.842437 ==
921 13:58:32.842531 RX Vref Scan: 0
922 13:58:32.842592
923 13:58:32.845607 RX Vref 0 -> 0, step: 1
924 13:58:32.845732
925 13:58:32.849230 RX Delay -130 -> 252, step: 16
926 13:58:32.852322 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
927 13:58:32.855810 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
928 13:58:32.859457 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
929 13:58:32.862667 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
930 13:58:32.869152 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
931 13:58:32.872825 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
932 13:58:32.876231 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
933 13:58:32.879481 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
934 13:58:32.882548 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
935 13:58:32.889280 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
936 13:58:32.892974 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
937 13:58:32.896143 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
938 13:58:32.899818 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
939 13:58:32.903298 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
940 13:58:32.909554 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
941 13:58:32.912836 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
942 13:58:32.912917 ==
943 13:58:32.916188 Dram Type= 6, Freq= 0, CH_0, rank 0
944 13:58:32.919513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 13:58:32.919596 ==
946 13:58:32.919660 DQS Delay:
947 13:58:32.923210 DQS0 = 0, DQS1 = 0
948 13:58:32.923322 DQM Delay:
949 13:58:32.926275 DQM0 = 81, DQM1 = 78
950 13:58:32.926356 DQ Delay:
951 13:58:32.929460 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
952 13:58:32.932974 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
953 13:58:32.936526 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
954 13:58:32.939720 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
955 13:58:32.939801
956 13:58:32.939865
957 13:58:32.939924 ==
958 13:58:32.943208 Dram Type= 6, Freq= 0, CH_0, rank 0
959 13:58:32.946774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 13:58:32.946855 ==
961 13:58:32.946919
962 13:58:32.949803
963 13:58:32.949884 TX Vref Scan disable
964 13:58:32.953628 == TX Byte 0 ==
965 13:58:32.956846 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
966 13:58:32.960041 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
967 13:58:32.963425 == TX Byte 1 ==
968 13:58:32.966963 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
969 13:58:32.970365 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
970 13:58:32.970451 ==
971 13:58:32.973631 Dram Type= 6, Freq= 0, CH_0, rank 0
972 13:58:32.976823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 13:58:32.980294 ==
974 13:58:32.991507 TX Vref=22, minBit 12, minWin=26, winSum=433
975 13:58:32.995156 TX Vref=24, minBit 12, minWin=26, winSum=436
976 13:58:32.998531 TX Vref=26, minBit 1, minWin=27, winSum=440
977 13:58:33.001968 TX Vref=28, minBit 5, minWin=27, winSum=451
978 13:58:33.005266 TX Vref=30, minBit 5, minWin=27, winSum=449
979 13:58:33.008578 TX Vref=32, minBit 3, minWin=27, winSum=448
980 13:58:33.015183 [TxChooseVref] Worse bit 5, Min win 27, Win sum 451, Final Vref 28
981 13:58:33.015266
982 13:58:33.018450 Final TX Range 1 Vref 28
983 13:58:33.018532
984 13:58:33.018597 ==
985 13:58:33.021824 Dram Type= 6, Freq= 0, CH_0, rank 0
986 13:58:33.025476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 13:58:33.025558 ==
988 13:58:33.025624
989 13:58:33.025701
990 13:58:33.028720 TX Vref Scan disable
991 13:58:33.032288 == TX Byte 0 ==
992 13:58:33.035420 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
993 13:58:33.039133 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
994 13:58:33.042326 == TX Byte 1 ==
995 13:58:33.045762 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
996 13:58:33.048906 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
997 13:58:33.048987
998 13:58:33.052230 [DATLAT]
999 13:58:33.052311 Freq=800, CH0 RK0
1000 13:58:33.052376
1001 13:58:33.055665 DATLAT Default: 0xa
1002 13:58:33.055747 0, 0xFFFF, sum = 0
1003 13:58:33.058992 1, 0xFFFF, sum = 0
1004 13:58:33.059080 2, 0xFFFF, sum = 0
1005 13:58:33.062378 3, 0xFFFF, sum = 0
1006 13:58:33.062461 4, 0xFFFF, sum = 0
1007 13:58:33.065835 5, 0xFFFF, sum = 0
1008 13:58:33.065918 6, 0xFFFF, sum = 0
1009 13:58:33.069259 7, 0xFFFF, sum = 0
1010 13:58:33.069342 8, 0xFFFF, sum = 0
1011 13:58:33.072437 9, 0x0, sum = 1
1012 13:58:33.072546 10, 0x0, sum = 2
1013 13:58:33.075624 11, 0x0, sum = 3
1014 13:58:33.075705 12, 0x0, sum = 4
1015 13:58:33.079238 best_step = 10
1016 13:58:33.079318
1017 13:58:33.079382 ==
1018 13:58:33.082521 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 13:58:33.086610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 13:58:33.086733 ==
1021 13:58:33.086834 RX Vref Scan: 1
1022 13:58:33.086910
1023 13:58:33.089140 Set Vref Range= 32 -> 127
1024 13:58:33.089250
1025 13:58:33.092601 RX Vref 32 -> 127, step: 1
1026 13:58:33.092728
1027 13:58:33.095694 RX Delay -95 -> 252, step: 8
1028 13:58:33.095795
1029 13:58:33.099423 Set Vref, RX VrefLevel [Byte0]: 32
1030 13:58:33.102954 [Byte1]: 32
1031 13:58:33.103055
1032 13:58:33.106155 Set Vref, RX VrefLevel [Byte0]: 33
1033 13:58:33.109528 [Byte1]: 33
1034 13:58:33.109599
1035 13:58:33.113701 Set Vref, RX VrefLevel [Byte0]: 34
1036 13:58:33.116962 [Byte1]: 34
1037 13:58:33.117064
1038 13:58:33.120167 Set Vref, RX VrefLevel [Byte0]: 35
1039 13:58:33.124038 [Byte1]: 35
1040 13:58:33.127019
1041 13:58:33.127117 Set Vref, RX VrefLevel [Byte0]: 36
1042 13:58:33.130264 [Byte1]: 36
1043 13:58:33.134589
1044 13:58:33.134690 Set Vref, RX VrefLevel [Byte0]: 37
1045 13:58:33.137916 [Byte1]: 37
1046 13:58:33.142521
1047 13:58:33.142598 Set Vref, RX VrefLevel [Byte0]: 38
1048 13:58:33.145680 [Byte1]: 38
1049 13:58:33.149968
1050 13:58:33.150050 Set Vref, RX VrefLevel [Byte0]: 39
1051 13:58:33.154087 [Byte1]: 39
1052 13:58:33.157572
1053 13:58:33.157706 Set Vref, RX VrefLevel [Byte0]: 40
1054 13:58:33.161191 [Byte1]: 40
1055 13:58:33.165809
1056 13:58:33.165888 Set Vref, RX VrefLevel [Byte0]: 41
1057 13:58:33.169058 [Byte1]: 41
1058 13:58:33.172787
1059 13:58:33.172866 Set Vref, RX VrefLevel [Byte0]: 42
1060 13:58:33.176567 [Byte1]: 42
1061 13:58:33.180457
1062 13:58:33.180564 Set Vref, RX VrefLevel [Byte0]: 43
1063 13:58:33.183447 [Byte1]: 43
1064 13:58:33.188257
1065 13:58:33.188358 Set Vref, RX VrefLevel [Byte0]: 44
1066 13:58:33.191327 [Byte1]: 44
1067 13:58:33.195527
1068 13:58:33.195627 Set Vref, RX VrefLevel [Byte0]: 45
1069 13:58:33.198775 [Byte1]: 45
1070 13:58:33.203334
1071 13:58:33.203436 Set Vref, RX VrefLevel [Byte0]: 46
1072 13:58:33.206541 [Byte1]: 46
1073 13:58:33.211043
1074 13:58:33.211119 Set Vref, RX VrefLevel [Byte0]: 47
1075 13:58:33.214002 [Byte1]: 47
1076 13:58:33.218139
1077 13:58:33.218215 Set Vref, RX VrefLevel [Byte0]: 48
1078 13:58:33.221643 [Byte1]: 48
1079 13:58:33.226252
1080 13:58:33.226335 Set Vref, RX VrefLevel [Byte0]: 49
1081 13:58:33.229155 [Byte1]: 49
1082 13:58:33.233762
1083 13:58:33.233838 Set Vref, RX VrefLevel [Byte0]: 50
1084 13:58:33.236592 [Byte1]: 50
1085 13:58:33.240897
1086 13:58:33.240972 Set Vref, RX VrefLevel [Byte0]: 51
1087 13:58:33.244771 [Byte1]: 51
1088 13:58:33.248513
1089 13:58:33.248618 Set Vref, RX VrefLevel [Byte0]: 52
1090 13:58:33.251948 [Byte1]: 52
1091 13:58:33.256044
1092 13:58:33.256154 Set Vref, RX VrefLevel [Byte0]: 53
1093 13:58:33.259478 [Byte1]: 53
1094 13:58:33.263612
1095 13:58:33.263723 Set Vref, RX VrefLevel [Byte0]: 54
1096 13:58:33.267253 [Byte1]: 54
1097 13:58:33.271506
1098 13:58:33.271609 Set Vref, RX VrefLevel [Byte0]: 55
1099 13:58:33.274590 [Byte1]: 55
1100 13:58:33.278844
1101 13:58:33.278943 Set Vref, RX VrefLevel [Byte0]: 56
1102 13:58:33.282928 [Byte1]: 56
1103 13:58:33.286571
1104 13:58:33.286676 Set Vref, RX VrefLevel [Byte0]: 57
1105 13:58:33.290026 [Byte1]: 57
1106 13:58:33.293947
1107 13:58:33.294054 Set Vref, RX VrefLevel [Byte0]: 58
1108 13:58:33.297829 [Byte1]: 58
1109 13:58:33.301891
1110 13:58:33.301970 Set Vref, RX VrefLevel [Byte0]: 59
1111 13:58:33.305217 [Byte1]: 59
1112 13:58:33.309652
1113 13:58:33.309740 Set Vref, RX VrefLevel [Byte0]: 60
1114 13:58:33.312781 [Byte1]: 60
1115 13:58:33.316780
1116 13:58:33.316887 Set Vref, RX VrefLevel [Byte0]: 61
1117 13:58:33.320269 [Byte1]: 61
1118 13:58:33.324650
1119 13:58:33.324788 Set Vref, RX VrefLevel [Byte0]: 62
1120 13:58:33.328079 [Byte1]: 62
1121 13:58:33.332138
1122 13:58:33.332235 Set Vref, RX VrefLevel [Byte0]: 63
1123 13:58:33.335426 [Byte1]: 63
1124 13:58:33.339880
1125 13:58:33.339978 Set Vref, RX VrefLevel [Byte0]: 64
1126 13:58:33.343351 [Byte1]: 64
1127 13:58:33.347263
1128 13:58:33.347364 Set Vref, RX VrefLevel [Byte0]: 65
1129 13:58:33.350752 [Byte1]: 65
1130 13:58:33.355201
1131 13:58:33.355298 Set Vref, RX VrefLevel [Byte0]: 66
1132 13:58:33.358277 [Byte1]: 66
1133 13:58:33.362559
1134 13:58:33.362663 Set Vref, RX VrefLevel [Byte0]: 67
1135 13:58:33.365783 [Byte1]: 67
1136 13:58:33.370209
1137 13:58:33.370310 Set Vref, RX VrefLevel [Byte0]: 68
1138 13:58:33.373576 [Byte1]: 68
1139 13:58:33.377607
1140 13:58:33.377680 Set Vref, RX VrefLevel [Byte0]: 69
1141 13:58:33.381017 [Byte1]: 69
1142 13:58:33.385217
1143 13:58:33.385328 Set Vref, RX VrefLevel [Byte0]: 70
1144 13:58:33.388670 [Byte1]: 70
1145 13:58:33.392816
1146 13:58:33.392887 Set Vref, RX VrefLevel [Byte0]: 71
1147 13:58:33.396027 [Byte1]: 71
1148 13:58:33.400263
1149 13:58:33.400364 Set Vref, RX VrefLevel [Byte0]: 72
1150 13:58:33.403687 [Byte1]: 72
1151 13:58:33.408005
1152 13:58:33.408106 Set Vref, RX VrefLevel [Byte0]: 73
1153 13:58:33.411253 [Byte1]: 73
1154 13:58:33.415764
1155 13:58:33.415873 Set Vref, RX VrefLevel [Byte0]: 74
1156 13:58:33.418968 [Byte1]: 74
1157 13:58:33.423353
1158 13:58:33.423455 Set Vref, RX VrefLevel [Byte0]: 75
1159 13:58:33.426465 [Byte1]: 75
1160 13:58:33.430955
1161 13:58:33.431028 Final RX Vref Byte 0 = 60 to rank0
1162 13:58:33.434161 Final RX Vref Byte 1 = 56 to rank0
1163 13:58:33.437512 Final RX Vref Byte 0 = 60 to rank1
1164 13:58:33.440790 Final RX Vref Byte 1 = 56 to rank1==
1165 13:58:33.444323 Dram Type= 6, Freq= 0, CH_0, rank 0
1166 13:58:33.447750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1167 13:58:33.451337 ==
1168 13:58:33.451415 DQS Delay:
1169 13:58:33.451477 DQS0 = 0, DQS1 = 0
1170 13:58:33.454453 DQM Delay:
1171 13:58:33.454524 DQM0 = 86, DQM1 = 79
1172 13:58:33.458046 DQ Delay:
1173 13:58:33.458149 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1174 13:58:33.461104 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1175 13:58:33.464371 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1176 13:58:33.468229 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =92
1177 13:58:33.468329
1178 13:58:33.468423
1179 13:58:33.477814 [DQSOSCAuto] RK0, (LSB)MR18= 0x260e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1180 13:58:33.481085 CH0 RK0: MR19=606, MR18=260E
1181 13:58:33.484462 CH0_RK0: MR19=0x606, MR18=0x260E, DQSOSC=400, MR23=63, INC=92, DEC=61
1182 13:58:33.487920
1183 13:58:33.491784 ----->DramcWriteLeveling(PI) begin...
1184 13:58:33.491886 ==
1185 13:58:33.494750 Dram Type= 6, Freq= 0, CH_0, rank 1
1186 13:58:33.498152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 13:58:33.498241 ==
1188 13:58:33.501526 Write leveling (Byte 0): 32 => 32
1189 13:58:33.504625 Write leveling (Byte 1): 31 => 31
1190 13:58:33.508222 DramcWriteLeveling(PI) end<-----
1191 13:58:33.508349
1192 13:58:33.508474 ==
1193 13:58:33.511595 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 13:58:33.515155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1195 13:58:33.515256 ==
1196 13:58:33.518219 [Gating] SW mode calibration
1197 13:58:33.524945 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1198 13:58:33.528303 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1199 13:58:33.535310 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1200 13:58:33.538416 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1201 13:58:33.541558 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1202 13:58:33.548589 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1203 13:58:33.552307 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 13:58:33.595610 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 13:58:33.596108 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 13:58:33.596594 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 13:58:33.596740 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 13:58:33.597028 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 13:58:33.597141 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 13:58:33.597442 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 13:58:33.597560 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 13:58:33.597670 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 13:58:33.597787 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 13:58:33.609913 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 13:58:33.610225 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 13:58:33.613119 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1217 13:58:33.613220 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1218 13:58:33.616026 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 13:58:33.622798 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 13:58:33.626076 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 13:58:33.629718 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 13:58:33.636642 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 13:58:33.639753 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 13:58:33.643262 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:58:33.649595 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1226 13:58:33.653223 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1227 13:58:33.656453 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1228 13:58:33.663175 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 13:58:33.666404 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 13:58:33.669870 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 13:58:33.673524 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 13:58:33.680191 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1233 13:58:33.683154 0 10 8 | B1->B0 | 3232 2727 | 1 1 | (1 0) (0 0)
1234 13:58:33.686561 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1235 13:58:33.693516 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 13:58:33.696963 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 13:58:33.699951 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 13:58:33.707068 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 13:58:33.710153 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 13:58:33.713420 0 11 4 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
1241 13:58:33.720472 0 11 8 | B1->B0 | 2929 4040 | 0 1 | (0 0) (0 0)
1242 13:58:33.723861 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
1243 13:58:33.727972 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 13:58:33.732029 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 13:58:33.736004 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 13:58:33.739766 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 13:58:33.746228 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 13:58:33.749585 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 13:58:33.752973 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1250 13:58:33.756635 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1251 13:58:33.763773 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 13:58:33.766580 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 13:58:33.769927 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 13:58:33.776514 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 13:58:33.780240 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 13:58:33.783622 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 13:58:33.790050 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 13:58:33.793410 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 13:58:33.797311 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 13:58:33.803791 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 13:58:33.807428 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 13:58:33.810308 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 13:58:33.817273 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 13:58:33.820360 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1265 13:58:33.823680 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1266 13:58:33.827378 Total UI for P1: 0, mck2ui 16
1267 13:58:33.830715 best dqsien dly found for B0: ( 0, 14, 4)
1268 13:58:33.834025 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 13:58:33.837053 Total UI for P1: 0, mck2ui 16
1270 13:58:33.840528 best dqsien dly found for B1: ( 0, 14, 8)
1271 13:58:33.843831 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1272 13:58:33.847604 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1273 13:58:33.847684
1274 13:58:33.850855 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1275 13:58:33.857478 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1276 13:58:33.857583 [Gating] SW calibration Done
1277 13:58:33.857685 ==
1278 13:58:33.860831 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 13:58:33.867416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1280 13:58:33.867520 ==
1281 13:58:33.867622 RX Vref Scan: 0
1282 13:58:33.867721
1283 13:58:33.871333 RX Vref 0 -> 0, step: 1
1284 13:58:33.871444
1285 13:58:33.874705 RX Delay -130 -> 252, step: 16
1286 13:58:33.877691 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1287 13:58:33.881230 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1288 13:58:33.884329 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1289 13:58:33.891161 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1290 13:58:33.894598 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1291 13:58:33.897937 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1292 13:58:33.901532 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1293 13:58:33.904913 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1294 13:58:33.908053 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1295 13:58:33.914694 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1296 13:58:33.917962 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1297 13:58:33.921265 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1298 13:58:33.924864 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1299 13:58:33.928036 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1300 13:58:33.934741 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1301 13:58:33.938477 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1302 13:58:33.938557 ==
1303 13:58:33.941476 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 13:58:33.945303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 13:58:33.945406 ==
1306 13:58:33.945506 DQS Delay:
1307 13:58:33.948220 DQS0 = 0, DQS1 = 0
1308 13:58:33.948319 DQM Delay:
1309 13:58:33.951615 DQM0 = 85, DQM1 = 75
1310 13:58:33.951714 DQ Delay:
1311 13:58:33.954732 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1312 13:58:33.958064 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1313 13:58:33.961661 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1314 13:58:33.965135 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1315 13:58:33.965212
1316 13:58:33.965276
1317 13:58:33.965336 ==
1318 13:58:33.968359 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 13:58:33.971649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 13:58:33.974912 ==
1321 13:58:33.975013
1322 13:58:33.975103
1323 13:58:33.975189 TX Vref Scan disable
1324 13:58:33.978871 == TX Byte 0 ==
1325 13:58:33.981977 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1326 13:58:33.985164 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1327 13:58:33.988726 == TX Byte 1 ==
1328 13:58:33.991664 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1329 13:58:33.995194 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1330 13:58:33.995321 ==
1331 13:58:33.998701 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 13:58:34.005115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 13:58:34.005191 ==
1334 13:58:34.017254 TX Vref=22, minBit 9, minWin=27, winSum=445
1335 13:58:34.020298 TX Vref=24, minBit 9, minWin=27, winSum=449
1336 13:58:34.024051 TX Vref=26, minBit 9, minWin=27, winSum=450
1337 13:58:34.027469 TX Vref=28, minBit 9, minWin=27, winSum=455
1338 13:58:34.030686 TX Vref=30, minBit 3, minWin=28, winSum=457
1339 13:58:34.033786 TX Vref=32, minBit 4, minWin=28, winSum=457
1340 13:58:34.040438 [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 30
1341 13:58:34.040518
1342 13:58:34.044050 Final TX Range 1 Vref 30
1343 13:58:34.044130
1344 13:58:34.044192 ==
1345 13:58:34.047491 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 13:58:34.050789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 13:58:34.050900 ==
1348 13:58:34.050962
1349 13:58:34.051019
1350 13:58:34.054433 TX Vref Scan disable
1351 13:58:34.057545 == TX Byte 0 ==
1352 13:58:34.060850 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1353 13:58:34.064307 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1354 13:58:34.067637 == TX Byte 1 ==
1355 13:58:34.071143 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1356 13:58:34.074136 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1357 13:58:34.074215
1358 13:58:34.077627 [DATLAT]
1359 13:58:34.077706 Freq=800, CH0 RK1
1360 13:58:34.077768
1361 13:58:34.081005 DATLAT Default: 0xa
1362 13:58:34.081085 0, 0xFFFF, sum = 0
1363 13:58:34.084270 1, 0xFFFF, sum = 0
1364 13:58:34.084345 2, 0xFFFF, sum = 0
1365 13:58:34.087665 3, 0xFFFF, sum = 0
1366 13:58:34.087774 4, 0xFFFF, sum = 0
1367 13:58:34.090961 5, 0xFFFF, sum = 0
1368 13:58:34.091069 6, 0xFFFF, sum = 0
1369 13:58:34.094561 7, 0xFFFF, sum = 0
1370 13:58:34.094629 8, 0xFFFF, sum = 0
1371 13:58:34.098045 9, 0x0, sum = 1
1372 13:58:34.098141 10, 0x0, sum = 2
1373 13:58:34.101774 11, 0x0, sum = 3
1374 13:58:34.101848 12, 0x0, sum = 4
1375 13:58:34.104712 best_step = 10
1376 13:58:34.104810
1377 13:58:34.104897 ==
1378 13:58:34.108203 Dram Type= 6, Freq= 0, CH_0, rank 1
1379 13:58:34.111150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 13:58:34.111234 ==
1381 13:58:34.111299 RX Vref Scan: 0
1382 13:58:34.111364
1383 13:58:34.114586 RX Vref 0 -> 0, step: 1
1384 13:58:34.114660
1385 13:58:34.117851 RX Delay -95 -> 252, step: 8
1386 13:58:34.121477 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1387 13:58:34.128195 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1388 13:58:34.131629 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1389 13:58:34.134818 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1390 13:58:34.138465 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1391 13:58:34.141415 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1392 13:58:34.145008 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1393 13:58:34.151616 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1394 13:58:34.155372 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1395 13:58:34.158470 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1396 13:58:34.162453 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1397 13:58:34.165307 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1398 13:58:34.171838 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1399 13:58:34.175033 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1400 13:58:34.178583 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1401 13:58:34.182088 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1402 13:58:34.182166 ==
1403 13:58:34.185101 Dram Type= 6, Freq= 0, CH_0, rank 1
1404 13:58:34.188695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 13:58:34.192173 ==
1406 13:58:34.192251 DQS Delay:
1407 13:58:34.192313 DQS0 = 0, DQS1 = 0
1408 13:58:34.195285 DQM Delay:
1409 13:58:34.195363 DQM0 = 87, DQM1 = 78
1410 13:58:34.198435 DQ Delay:
1411 13:58:34.202400 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1412 13:58:34.202478 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1413 13:58:34.205542 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1414 13:58:34.209287 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1415 13:58:34.209384
1416 13:58:34.212266
1417 13:58:34.218712 [DQSOSCAuto] RK1, (LSB)MR18= 0x311a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1418 13:58:34.222303 CH0 RK1: MR19=606, MR18=311A
1419 13:58:34.228879 CH0_RK1: MR19=0x606, MR18=0x311A, DQSOSC=397, MR23=63, INC=93, DEC=62
1420 13:58:34.228959 [RxdqsGatingPostProcess] freq 800
1421 13:58:34.235955 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1422 13:58:34.238889 Pre-setting of DQS Precalculation
1423 13:58:34.242130 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1424 13:58:34.245703 ==
1425 13:58:34.248882 Dram Type= 6, Freq= 0, CH_1, rank 0
1426 13:58:34.252388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 13:58:34.252468 ==
1428 13:58:34.255768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1429 13:58:34.262548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1430 13:58:34.271823 [CA 0] Center 36 (6~66) winsize 61
1431 13:58:34.275325 [CA 1] Center 36 (6~66) winsize 61
1432 13:58:34.278509 [CA 2] Center 34 (4~65) winsize 62
1433 13:58:34.282455 [CA 3] Center 34 (3~65) winsize 63
1434 13:58:34.285180 [CA 4] Center 34 (4~65) winsize 62
1435 13:58:34.288700 [CA 5] Center 33 (3~64) winsize 62
1436 13:58:34.288795
1437 13:58:34.292223 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1438 13:58:34.292303
1439 13:58:34.296104 [CATrainingPosCal] consider 1 rank data
1440 13:58:34.299268 u2DelayCellTimex100 = 270/100 ps
1441 13:58:34.301772 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1442 13:58:34.305329 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1443 13:58:34.308564 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1444 13:58:34.315432 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1445 13:58:34.318616 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1446 13:58:34.322011 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1447 13:58:34.322090
1448 13:58:34.325559 CA PerBit enable=1, Macro0, CA PI delay=33
1449 13:58:34.325640
1450 13:58:34.328636 [CBTSetCACLKResult] CA Dly = 33
1451 13:58:34.328736 CS Dly: 4 (0~35)
1452 13:58:34.328800 ==
1453 13:58:34.332159 Dram Type= 6, Freq= 0, CH_1, rank 1
1454 13:58:34.338973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 13:58:34.339057 ==
1456 13:58:34.342501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1457 13:58:34.349262 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1458 13:58:34.357900 [CA 0] Center 36 (6~66) winsize 61
1459 13:58:34.361475 [CA 1] Center 36 (6~66) winsize 61
1460 13:58:34.364856 [CA 2] Center 34 (4~64) winsize 61
1461 13:58:34.368219 [CA 3] Center 33 (3~64) winsize 62
1462 13:58:34.371171 [CA 4] Center 34 (4~65) winsize 62
1463 13:58:34.374765 [CA 5] Center 33 (3~64) winsize 62
1464 13:58:34.374868
1465 13:58:34.377888 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1466 13:58:34.377964
1467 13:58:34.381296 [CATrainingPosCal] consider 2 rank data
1468 13:58:34.384732 u2DelayCellTimex100 = 270/100 ps
1469 13:58:34.388466 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1470 13:58:34.391974 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1471 13:58:34.395445 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1472 13:58:34.399133 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1473 13:58:34.402879 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1474 13:58:34.406874 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1475 13:58:34.406954
1476 13:58:34.410591 CA PerBit enable=1, Macro0, CA PI delay=33
1477 13:58:34.410685
1478 13:58:34.413822 [CBTSetCACLKResult] CA Dly = 33
1479 13:58:34.418327 CS Dly: 5 (0~37)
1480 13:58:34.418437
1481 13:58:34.418529 ----->DramcWriteLeveling(PI) begin...
1482 13:58:34.422063 ==
1483 13:58:34.422139 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 13:58:34.425499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 13:58:34.428954 ==
1486 13:58:34.429028 Write leveling (Byte 0): 25 => 25
1487 13:58:34.432107 Write leveling (Byte 1): 31 => 31
1488 13:58:34.435481 DramcWriteLeveling(PI) end<-----
1489 13:58:34.435580
1490 13:58:34.435669 ==
1491 13:58:34.439352 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 13:58:34.445569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 13:58:34.445651 ==
1494 13:58:34.445715 [Gating] SW mode calibration
1495 13:58:34.455577 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1496 13:58:34.459659 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1497 13:58:34.462289 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1498 13:58:34.469170 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1499 13:58:34.472571 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1500 13:58:34.476019 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 13:58:34.482416 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 13:58:34.486353 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 13:58:34.489342 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 13:58:34.495937 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 13:58:34.499549 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 13:58:34.502768 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 13:58:34.506380 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 13:58:34.512758 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 13:58:34.516266 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1510 13:58:34.519629 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1511 13:58:34.526547 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 13:58:34.529612 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 13:58:34.532897 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 13:58:34.539863 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1515 13:58:34.543457 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1516 13:58:34.546607 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 13:58:34.549866 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 13:58:34.556870 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 13:58:34.559824 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 13:58:34.563121 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 13:58:34.569939 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 13:58:34.573438 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:58:34.576694 0 9 8 | B1->B0 | 2626 2323 | 0 1 | (0 0) (0 0)
1524 13:58:34.583598 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1525 13:58:34.586761 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 13:58:34.590577 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 13:58:34.596988 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1528 13:58:34.600564 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 13:58:34.603666 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 13:58:34.607351 0 10 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1531 13:58:34.613970 0 10 8 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (0 0)
1532 13:58:34.617188 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 13:58:34.620859 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 13:58:34.627206 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 13:58:34.630599 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 13:58:34.633849 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 13:58:34.641047 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 13:58:34.644140 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 13:58:34.647379 0 11 8 | B1->B0 | 3636 3535 | 0 1 | (1 1) (0 0)
1540 13:58:34.653975 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 13:58:34.657221 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 13:58:34.660742 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 13:58:34.667386 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 13:58:34.670867 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 13:58:34.673998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 13:58:34.680524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 13:58:34.684074 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1548 13:58:34.687411 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 13:58:34.691011 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 13:58:34.697648 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 13:58:34.700950 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 13:58:34.704257 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 13:58:34.711125 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 13:58:34.714930 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 13:58:34.717781 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 13:58:34.724117 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 13:58:34.727687 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 13:58:34.731414 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 13:58:34.734449 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 13:58:34.741461 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 13:58:34.744550 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 13:58:34.747738 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1563 13:58:34.755019 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1564 13:58:34.758179 Total UI for P1: 0, mck2ui 16
1565 13:58:34.761854 best dqsien dly found for B1: ( 0, 14, 4)
1566 13:58:34.764692 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 13:58:34.768290 Total UI for P1: 0, mck2ui 16
1568 13:58:34.772009 best dqsien dly found for B0: ( 0, 14, 6)
1569 13:58:34.775288 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1570 13:58:34.778319 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1571 13:58:34.778399
1572 13:58:34.781552 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1573 13:58:34.784927 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1574 13:58:34.788478 [Gating] SW calibration Done
1575 13:58:34.788558 ==
1576 13:58:34.791924 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 13:58:34.795001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 13:58:34.795081 ==
1579 13:58:34.798737 RX Vref Scan: 0
1580 13:58:34.798816
1581 13:58:34.798878 RX Vref 0 -> 0, step: 1
1582 13:58:34.798936
1583 13:58:34.801886 RX Delay -130 -> 252, step: 16
1584 13:58:34.805916 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1585 13:58:34.812278 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1586 13:58:34.815389 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1587 13:58:34.818753 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1588 13:58:34.822056 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1589 13:58:34.825763 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1590 13:58:34.832049 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1591 13:58:34.835824 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1592 13:58:34.839350 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1593 13:58:34.842517 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1594 13:58:34.845724 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1595 13:58:34.852751 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1596 13:58:34.855897 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1597 13:58:34.859499 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1598 13:58:34.862610 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1599 13:58:34.865983 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1600 13:58:34.866106 ==
1601 13:58:34.869448 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 13:58:34.876075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 13:58:34.876159 ==
1604 13:58:34.876246 DQS Delay:
1605 13:58:34.879716 DQS0 = 0, DQS1 = 0
1606 13:58:34.879799 DQM Delay:
1607 13:58:34.879884 DQM0 = 85, DQM1 = 76
1608 13:58:34.883060 DQ Delay:
1609 13:58:34.886257 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1610 13:58:34.889447 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =77
1611 13:58:34.892702 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1612 13:58:34.896331 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1613 13:58:34.896415
1614 13:58:34.896500
1615 13:58:34.896599 ==
1616 13:58:34.899440 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 13:58:34.903008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 13:58:34.903092 ==
1619 13:58:34.903178
1620 13:58:34.903259
1621 13:58:34.906477 TX Vref Scan disable
1622 13:58:34.906561 == TX Byte 0 ==
1623 13:58:34.913662 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1624 13:58:34.916185 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1625 13:58:34.916292 == TX Byte 1 ==
1626 13:58:34.923137 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1627 13:58:34.926260 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1628 13:58:34.926344 ==
1629 13:58:34.929776 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 13:58:34.933199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 13:58:34.933284 ==
1632 13:58:34.947243 TX Vref=22, minBit 11, minWin=26, winSum=437
1633 13:58:34.950984 TX Vref=24, minBit 11, minWin=26, winSum=439
1634 13:58:34.954145 TX Vref=26, minBit 1, minWin=27, winSum=444
1635 13:58:34.957314 TX Vref=28, minBit 0, minWin=27, winSum=445
1636 13:58:34.960822 TX Vref=30, minBit 1, minWin=27, winSum=448
1637 13:58:34.964081 TX Vref=32, minBit 0, minWin=27, winSum=446
1638 13:58:34.971182 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 30
1639 13:58:34.971266
1640 13:58:34.975171 Final TX Range 1 Vref 30
1641 13:58:34.975255
1642 13:58:34.975340 ==
1643 13:58:34.978889 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 13:58:34.982008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 13:58:34.982092 ==
1646 13:58:34.982178
1647 13:58:34.982259
1648 13:58:34.985639 TX Vref Scan disable
1649 13:58:34.988791 == TX Byte 0 ==
1650 13:58:34.991731 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1651 13:58:34.995043 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1652 13:58:34.998479 == TX Byte 1 ==
1653 13:58:35.001999 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1654 13:58:35.005311 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1655 13:58:35.005395
1656 13:58:35.005481 [DATLAT]
1657 13:58:35.008450 Freq=800, CH1 RK0
1658 13:58:35.008534
1659 13:58:35.011861 DATLAT Default: 0xa
1660 13:58:35.011945 0, 0xFFFF, sum = 0
1661 13:58:35.015863 1, 0xFFFF, sum = 0
1662 13:58:35.015947 2, 0xFFFF, sum = 0
1663 13:58:35.018891 3, 0xFFFF, sum = 0
1664 13:58:35.018976 4, 0xFFFF, sum = 0
1665 13:58:35.021995 5, 0xFFFF, sum = 0
1666 13:58:35.022080 6, 0xFFFF, sum = 0
1667 13:58:35.025551 7, 0xFFFF, sum = 0
1668 13:58:35.025651 8, 0xFFFF, sum = 0
1669 13:58:35.028904 9, 0x0, sum = 1
1670 13:58:35.028989 10, 0x0, sum = 2
1671 13:58:35.029076 11, 0x0, sum = 3
1672 13:58:35.032176 12, 0x0, sum = 4
1673 13:58:35.032261 best_step = 10
1674 13:58:35.032347
1675 13:58:35.032428 ==
1676 13:58:35.035346 Dram Type= 6, Freq= 0, CH_1, rank 0
1677 13:58:35.042522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1678 13:58:35.042606 ==
1679 13:58:35.042692 RX Vref Scan: 1
1680 13:58:35.042774
1681 13:58:35.045559 Set Vref Range= 32 -> 127
1682 13:58:35.045641
1683 13:58:35.049018 RX Vref 32 -> 127, step: 1
1684 13:58:35.049101
1685 13:58:35.052288 RX Delay -95 -> 252, step: 8
1686 13:58:35.052372
1687 13:58:35.055764 Set Vref, RX VrefLevel [Byte0]: 32
1688 13:58:35.055848 [Byte1]: 32
1689 13:58:35.060350
1690 13:58:35.060433 Set Vref, RX VrefLevel [Byte0]: 33
1691 13:58:35.063290 [Byte1]: 33
1692 13:58:35.067696
1693 13:58:35.067779 Set Vref, RX VrefLevel [Byte0]: 34
1694 13:58:35.071301 [Byte1]: 34
1695 13:58:35.075319
1696 13:58:35.075406 Set Vref, RX VrefLevel [Byte0]: 35
1697 13:58:35.078514 [Byte1]: 35
1698 13:58:35.083399
1699 13:58:35.083521 Set Vref, RX VrefLevel [Byte0]: 36
1700 13:58:35.086144 [Byte1]: 36
1701 13:58:35.090596
1702 13:58:35.090679 Set Vref, RX VrefLevel [Byte0]: 37
1703 13:58:35.093855 [Byte1]: 37
1704 13:58:35.097973
1705 13:58:35.098056 Set Vref, RX VrefLevel [Byte0]: 38
1706 13:58:35.101567 [Byte1]: 38
1707 13:58:35.105918
1708 13:58:35.106001 Set Vref, RX VrefLevel [Byte0]: 39
1709 13:58:35.108906 [Byte1]: 39
1710 13:58:35.113212
1711 13:58:35.113295 Set Vref, RX VrefLevel [Byte0]: 40
1712 13:58:35.116931 [Byte1]: 40
1713 13:58:35.120994
1714 13:58:35.121077 Set Vref, RX VrefLevel [Byte0]: 41
1715 13:58:35.124485 [Byte1]: 41
1716 13:58:35.128689
1717 13:58:35.128773 Set Vref, RX VrefLevel [Byte0]: 42
1718 13:58:35.131870 [Byte1]: 42
1719 13:58:35.136569
1720 13:58:35.136701 Set Vref, RX VrefLevel [Byte0]: 43
1721 13:58:35.139234 [Byte1]: 43
1722 13:58:35.143873
1723 13:58:35.143981 Set Vref, RX VrefLevel [Byte0]: 44
1724 13:58:35.146821 [Byte1]: 44
1725 13:58:35.152187
1726 13:58:35.152293 Set Vref, RX VrefLevel [Byte0]: 45
1727 13:58:35.154753 [Byte1]: 45
1728 13:58:35.159273
1729 13:58:35.159353 Set Vref, RX VrefLevel [Byte0]: 46
1730 13:58:35.162327 [Byte1]: 46
1731 13:58:35.166756
1732 13:58:35.166836 Set Vref, RX VrefLevel [Byte0]: 47
1733 13:58:35.169843 [Byte1]: 47
1734 13:58:35.174174
1735 13:58:35.174255 Set Vref, RX VrefLevel [Byte0]: 48
1736 13:58:35.177286 [Byte1]: 48
1737 13:58:35.181892
1738 13:58:35.181973 Set Vref, RX VrefLevel [Byte0]: 49
1739 13:58:35.185236 [Byte1]: 49
1740 13:58:35.188985
1741 13:58:35.189065 Set Vref, RX VrefLevel [Byte0]: 50
1742 13:58:35.192465 [Byte1]: 50
1743 13:58:35.197614
1744 13:58:35.197694 Set Vref, RX VrefLevel [Byte0]: 51
1745 13:58:35.200351 [Byte1]: 51
1746 13:58:35.204328
1747 13:58:35.204408 Set Vref, RX VrefLevel [Byte0]: 52
1748 13:58:35.207905 [Byte1]: 52
1749 13:58:35.212318
1750 13:58:35.212406 Set Vref, RX VrefLevel [Byte0]: 53
1751 13:58:35.215342 [Byte1]: 53
1752 13:58:35.219721
1753 13:58:35.219801 Set Vref, RX VrefLevel [Byte0]: 54
1754 13:58:35.222941 [Byte1]: 54
1755 13:58:35.227297
1756 13:58:35.227378 Set Vref, RX VrefLevel [Byte0]: 55
1757 13:58:35.230490 [Byte1]: 55
1758 13:58:35.234971
1759 13:58:35.235081 Set Vref, RX VrefLevel [Byte0]: 56
1760 13:58:35.238382 [Byte1]: 56
1761 13:58:35.242552
1762 13:58:35.242632 Set Vref, RX VrefLevel [Byte0]: 57
1763 13:58:35.246168 [Byte1]: 57
1764 13:58:35.250118
1765 13:58:35.250198 Set Vref, RX VrefLevel [Byte0]: 58
1766 13:58:35.253229 [Byte1]: 58
1767 13:58:35.257370
1768 13:58:35.257450 Set Vref, RX VrefLevel [Byte0]: 59
1769 13:58:35.260703 [Byte1]: 59
1770 13:58:35.265084
1771 13:58:35.265165 Set Vref, RX VrefLevel [Byte0]: 60
1772 13:58:35.268704 [Byte1]: 60
1773 13:58:35.272569
1774 13:58:35.272651 Set Vref, RX VrefLevel [Byte0]: 61
1775 13:58:35.276100 [Byte1]: 61
1776 13:58:35.280421
1777 13:58:35.280501 Set Vref, RX VrefLevel [Byte0]: 62
1778 13:58:35.283612 [Byte1]: 62
1779 13:58:35.287898
1780 13:58:35.287978 Set Vref, RX VrefLevel [Byte0]: 63
1781 13:58:35.291591 [Byte1]: 63
1782 13:58:35.295444
1783 13:58:35.295516 Set Vref, RX VrefLevel [Byte0]: 64
1784 13:58:35.299304 [Byte1]: 64
1785 13:58:35.303551
1786 13:58:35.303629 Set Vref, RX VrefLevel [Byte0]: 65
1787 13:58:35.306368 [Byte1]: 65
1788 13:58:35.311286
1789 13:58:35.311366 Set Vref, RX VrefLevel [Byte0]: 66
1790 13:58:35.314120 [Byte1]: 66
1791 13:58:35.318744
1792 13:58:35.318823 Set Vref, RX VrefLevel [Byte0]: 67
1793 13:58:35.321561 [Byte1]: 67
1794 13:58:35.325922
1795 13:58:35.326001 Set Vref, RX VrefLevel [Byte0]: 68
1796 13:58:35.329354 [Byte1]: 68
1797 13:58:35.333824
1798 13:58:35.333903 Set Vref, RX VrefLevel [Byte0]: 69
1799 13:58:35.337236 [Byte1]: 69
1800 13:58:35.341133
1801 13:58:35.341212 Set Vref, RX VrefLevel [Byte0]: 70
1802 13:58:35.344492 [Byte1]: 70
1803 13:58:35.348929
1804 13:58:35.349008 Set Vref, RX VrefLevel [Byte0]: 71
1805 13:58:35.352174 [Byte1]: 71
1806 13:58:35.356367
1807 13:58:35.356448 Set Vref, RX VrefLevel [Byte0]: 72
1808 13:58:35.359999 [Byte1]: 72
1809 13:58:35.364275
1810 13:58:35.364357 Set Vref, RX VrefLevel [Byte0]: 73
1811 13:58:35.367364 [Byte1]: 73
1812 13:58:35.371489
1813 13:58:35.371571 Set Vref, RX VrefLevel [Byte0]: 74
1814 13:58:35.374669 [Byte1]: 74
1815 13:58:35.379089
1816 13:58:35.379169 Set Vref, RX VrefLevel [Byte0]: 75
1817 13:58:35.382607 [Byte1]: 75
1818 13:58:35.387019
1819 13:58:35.387099 Set Vref, RX VrefLevel [Byte0]: 76
1820 13:58:35.390081 [Byte1]: 76
1821 13:58:35.395050
1822 13:58:35.395134 Set Vref, RX VrefLevel [Byte0]: 77
1823 13:58:35.397987 [Byte1]: 77
1824 13:58:35.401826
1825 13:58:35.401907 Set Vref, RX VrefLevel [Byte0]: 78
1826 13:58:35.405402 [Byte1]: 78
1827 13:58:35.409485
1828 13:58:35.409566 Set Vref, RX VrefLevel [Byte0]: 79
1829 13:58:35.413002 [Byte1]: 79
1830 13:58:35.417358
1831 13:58:35.417438 Set Vref, RX VrefLevel [Byte0]: 80
1832 13:58:35.420501 [Byte1]: 80
1833 13:58:35.424642
1834 13:58:35.424729 Final RX Vref Byte 0 = 61 to rank0
1835 13:58:35.428070 Final RX Vref Byte 1 = 55 to rank0
1836 13:58:35.431720 Final RX Vref Byte 0 = 61 to rank1
1837 13:58:35.434927 Final RX Vref Byte 1 = 55 to rank1==
1838 13:58:35.438521 Dram Type= 6, Freq= 0, CH_1, rank 0
1839 13:58:35.441725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 13:58:35.444953 ==
1841 13:58:35.445034 DQS Delay:
1842 13:58:35.445098 DQS0 = 0, DQS1 = 0
1843 13:58:35.448876 DQM Delay:
1844 13:58:35.448974 DQM0 = 84, DQM1 = 73
1845 13:58:35.451581 DQ Delay:
1846 13:58:35.451660 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1847 13:58:35.455216 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80
1848 13:58:35.458641 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1849 13:58:35.461851 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1850 13:58:35.461932
1851 13:58:35.461995
1852 13:58:35.471947 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c01, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1853 13:58:35.475920 CH1 RK0: MR19=606, MR18=2C01
1854 13:58:35.478524 CH1_RK0: MR19=0x606, MR18=0x2C01, DQSOSC=398, MR23=63, INC=93, DEC=62
1855 13:58:35.478606
1856 13:58:35.481936 ----->DramcWriteLeveling(PI) begin...
1857 13:58:35.485827 ==
1858 13:58:35.489056 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 13:58:35.492159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 13:58:35.492241 ==
1861 13:58:35.495752 Write leveling (Byte 0): 30 => 30
1862 13:58:35.498698 Write leveling (Byte 1): 30 => 30
1863 13:58:35.502311 DramcWriteLeveling(PI) end<-----
1864 13:58:35.502394
1865 13:58:35.502459 ==
1866 13:58:35.505422 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 13:58:35.509009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 13:58:35.509091 ==
1869 13:58:35.512816 [Gating] SW mode calibration
1870 13:58:35.519359 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1871 13:58:35.522267 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1872 13:58:35.529413 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1873 13:58:35.532627 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1874 13:58:35.535989 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 13:58:35.542568 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 13:58:35.545996 0 6 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1877 13:58:35.549277 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 13:58:35.556073 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 13:58:35.559662 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 13:58:35.562680 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 13:58:35.565861 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 13:58:35.572514 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 13:58:35.576479 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 13:58:35.579626 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 13:58:35.586189 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1886 13:58:35.589558 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 13:58:35.592839 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 13:58:35.599783 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1889 13:58:35.602917 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1890 13:58:35.606324 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 13:58:35.612951 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 13:58:35.616552 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 13:58:35.619653 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1894 13:58:35.623100 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 13:58:35.629854 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 13:58:35.633113 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 13:58:35.636497 0 9 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
1898 13:58:35.643272 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
1899 13:58:35.646785 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1900 13:58:35.649814 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 13:58:35.656584 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 13:58:35.660311 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 13:58:35.663283 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 13:58:35.670002 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1905 13:58:35.673379 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
1906 13:58:35.676712 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1907 13:58:35.680133 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 13:58:35.686990 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 13:58:35.690334 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 13:58:35.693626 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 13:58:35.700456 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 13:58:35.703569 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1913 13:58:35.707218 0 11 4 | B1->B0 | 2727 3939 | 1 0 | (0 0) (0 0)
1914 13:58:35.714355 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1915 13:58:35.716921 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 13:58:35.720832 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 13:58:35.727413 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 13:58:35.730565 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 13:58:35.733688 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 13:58:35.740565 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1921 13:58:35.743819 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1922 13:58:35.747362 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1923 13:58:35.750856 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 13:58:35.757497 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 13:58:35.760709 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 13:58:35.764383 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 13:58:35.770891 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 13:58:35.774416 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 13:58:35.777675 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 13:58:35.784229 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 13:58:35.787767 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 13:58:35.790935 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 13:58:35.795003 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 13:58:35.801348 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 13:58:35.804455 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 13:58:35.808164 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 13:58:35.815029 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1938 13:58:35.817890 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 13:58:35.821911 Total UI for P1: 0, mck2ui 16
1940 13:58:35.824868 best dqsien dly found for B0: ( 0, 14, 4)
1941 13:58:35.828083 Total UI for P1: 0, mck2ui 16
1942 13:58:35.832022 best dqsien dly found for B1: ( 0, 14, 4)
1943 13:58:35.835192 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1944 13:58:35.838379 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1945 13:58:35.838477
1946 13:58:35.841557 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1947 13:58:35.845526 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1948 13:58:35.848627 [Gating] SW calibration Done
1949 13:58:35.848737 ==
1950 13:58:35.851712 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 13:58:35.855219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 13:58:35.855318 ==
1953 13:58:35.858456 RX Vref Scan: 0
1954 13:58:35.858539
1955 13:58:35.861757 RX Vref 0 -> 0, step: 1
1956 13:58:35.861841
1957 13:58:35.861927 RX Delay -130 -> 252, step: 16
1958 13:58:35.868688 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1959 13:58:35.871780 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1960 13:58:35.874835 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1961 13:58:35.878440 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1962 13:58:35.881716 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1963 13:58:35.888294 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1964 13:58:35.891842 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1965 13:58:35.895172 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1966 13:58:35.898808 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1967 13:58:35.902138 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1968 13:58:35.905234 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1969 13:58:35.912245 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1970 13:58:35.915540 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1971 13:58:35.918942 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1972 13:58:35.922350 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1973 13:58:35.925624 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1974 13:58:35.928922 ==
1975 13:58:35.929001 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 13:58:35.935316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 13:58:35.935411 ==
1978 13:58:35.935475 DQS Delay:
1979 13:58:35.939312 DQS0 = 0, DQS1 = 0
1980 13:58:35.939405 DQM Delay:
1981 13:58:35.942787 DQM0 = 80, DQM1 = 76
1982 13:58:35.942866 DQ Delay:
1983 13:58:35.945545 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1984 13:58:35.949452 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =69
1985 13:58:35.952345 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1986 13:58:35.955909 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1987 13:58:35.955988
1988 13:58:35.956050
1989 13:58:35.956108 ==
1990 13:58:35.958980 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 13:58:35.962173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 13:58:35.962282 ==
1993 13:58:35.962379
1994 13:58:35.962480
1995 13:58:35.965782 TX Vref Scan disable
1996 13:58:35.965861 == TX Byte 0 ==
1997 13:58:35.972327 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1998 13:58:35.975675 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1999 13:58:35.975781 == TX Byte 1 ==
2000 13:58:35.982731 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2001 13:58:35.986223 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2002 13:58:35.986303 ==
2003 13:58:35.989215 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 13:58:35.992860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 13:58:35.992939 ==
2006 13:58:36.006236 TX Vref=22, minBit 0, minWin=27, winSum=439
2007 13:58:36.009673 TX Vref=24, minBit 2, minWin=27, winSum=442
2008 13:58:36.013219 TX Vref=26, minBit 2, minWin=27, winSum=447
2009 13:58:36.016334 TX Vref=28, minBit 0, minWin=28, winSum=454
2010 13:58:36.019976 TX Vref=30, minBit 7, minWin=27, winSum=451
2011 13:58:36.023216 TX Vref=32, minBit 0, minWin=27, winSum=448
2012 13:58:36.030194 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 28
2013 13:58:36.030274
2014 13:58:36.033263 Final TX Range 1 Vref 28
2015 13:58:36.033343
2016 13:58:36.033405 ==
2017 13:58:36.036852 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 13:58:36.039910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 13:58:36.039990 ==
2020 13:58:36.040052
2021 13:58:36.040110
2022 13:58:36.043122 TX Vref Scan disable
2023 13:58:36.046494 == TX Byte 0 ==
2024 13:58:36.050044 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2025 13:58:36.053110 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2026 13:58:36.056560 == TX Byte 1 ==
2027 13:58:36.060156 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2028 13:58:36.063556 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2029 13:58:36.063637
2030 13:58:36.066519 [DATLAT]
2031 13:58:36.066598 Freq=800, CH1 RK1
2032 13:58:36.066660
2033 13:58:36.070138 DATLAT Default: 0xa
2034 13:58:36.070217 0, 0xFFFF, sum = 0
2035 13:58:36.073699 1, 0xFFFF, sum = 0
2036 13:58:36.073794 2, 0xFFFF, sum = 0
2037 13:58:36.077124 3, 0xFFFF, sum = 0
2038 13:58:36.077205 4, 0xFFFF, sum = 0
2039 13:58:36.080323 5, 0xFFFF, sum = 0
2040 13:58:36.080404 6, 0xFFFF, sum = 0
2041 13:58:36.083439 7, 0xFFFF, sum = 0
2042 13:58:36.083521 8, 0xFFFF, sum = 0
2043 13:58:36.087035 9, 0x0, sum = 1
2044 13:58:36.087116 10, 0x0, sum = 2
2045 13:58:36.090348 11, 0x0, sum = 3
2046 13:58:36.090428 12, 0x0, sum = 4
2047 13:58:36.093565 best_step = 10
2048 13:58:36.093701
2049 13:58:36.093810 ==
2050 13:58:36.097545 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 13:58:36.100590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 13:58:36.100731 ==
2053 13:58:36.100799 RX Vref Scan: 0
2054 13:58:36.100880
2055 13:58:36.103687 RX Vref 0 -> 0, step: 1
2056 13:58:36.103793
2057 13:58:36.107309 RX Delay -95 -> 252, step: 8
2058 13:58:36.110372 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2059 13:58:36.117086 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2060 13:58:36.120950 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2061 13:58:36.123933 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2062 13:58:36.127248 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2063 13:58:36.130780 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2064 13:58:36.134158 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2065 13:58:36.140637 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2066 13:58:36.144008 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2067 13:58:36.147581 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2068 13:58:36.150928 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2069 13:58:36.154314 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2070 13:58:36.160854 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2071 13:58:36.164779 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2072 13:58:36.168026 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2073 13:58:36.171098 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2074 13:58:36.171198 ==
2075 13:58:36.174516 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 13:58:36.177843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 13:58:36.181489 ==
2078 13:58:36.181566 DQS Delay:
2079 13:58:36.181692 DQS0 = 0, DQS1 = 0
2080 13:58:36.184472 DQM Delay:
2081 13:58:36.184580 DQM0 = 81, DQM1 = 76
2082 13:58:36.188047 DQ Delay:
2083 13:58:36.188148 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2084 13:58:36.191536 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =76
2085 13:58:36.194743 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =72
2086 13:58:36.198141 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2087 13:58:36.198239
2088 13:58:36.201376
2089 13:58:36.207760 [DQSOSCAuto] RK1, (LSB)MR18= 0x202b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2090 13:58:36.211188 CH1 RK1: MR19=606, MR18=202B
2091 13:58:36.217954 CH1_RK1: MR19=0x606, MR18=0x202B, DQSOSC=398, MR23=63, INC=93, DEC=62
2092 13:58:36.218035 [RxdqsGatingPostProcess] freq 800
2093 13:58:36.224900 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2094 13:58:36.228948 Pre-setting of DQS Precalculation
2095 13:58:36.231672 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2096 13:58:36.241762 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2097 13:58:36.248632 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2098 13:58:36.248741
2099 13:58:36.248832
2100 13:58:36.251814 [Calibration Summary] 1600 Mbps
2101 13:58:36.251913 CH 0, Rank 0
2102 13:58:36.254867 SW Impedance : PASS
2103 13:58:36.254963 DUTY Scan : NO K
2104 13:58:36.258370 ZQ Calibration : PASS
2105 13:58:36.261747 Jitter Meter : NO K
2106 13:58:36.261864 CBT Training : PASS
2107 13:58:36.264910 Write leveling : PASS
2108 13:58:36.268712 RX DQS gating : PASS
2109 13:58:36.268801 RX DQ/DQS(RDDQC) : PASS
2110 13:58:36.272040 TX DQ/DQS : PASS
2111 13:58:36.272112 RX DATLAT : PASS
2112 13:58:36.275766 RX DQ/DQS(Engine): PASS
2113 13:58:36.278701 TX OE : NO K
2114 13:58:36.278799 All Pass.
2115 13:58:36.278891
2116 13:58:36.278976 CH 0, Rank 1
2117 13:58:36.281810 SW Impedance : PASS
2118 13:58:36.285701 DUTY Scan : NO K
2119 13:58:36.285773 ZQ Calibration : PASS
2120 13:58:36.288514 Jitter Meter : NO K
2121 13:58:36.291911 CBT Training : PASS
2122 13:58:36.291989 Write leveling : PASS
2123 13:58:36.295199 RX DQS gating : PASS
2124 13:58:36.298963 RX DQ/DQS(RDDQC) : PASS
2125 13:58:36.299064 TX DQ/DQS : PASS
2126 13:58:36.302419 RX DATLAT : PASS
2127 13:58:36.302515 RX DQ/DQS(Engine): PASS
2128 13:58:36.305254 TX OE : NO K
2129 13:58:36.305325 All Pass.
2130 13:58:36.305386
2131 13:58:36.309022 CH 1, Rank 0
2132 13:58:36.309094 SW Impedance : PASS
2133 13:58:36.312289 DUTY Scan : NO K
2134 13:58:36.315375 ZQ Calibration : PASS
2135 13:58:36.315474 Jitter Meter : NO K
2136 13:58:36.319076 CBT Training : PASS
2137 13:58:36.322132 Write leveling : PASS
2138 13:58:36.322235 RX DQS gating : PASS
2139 13:58:36.325613 RX DQ/DQS(RDDQC) : PASS
2140 13:58:36.329276 TX DQ/DQS : PASS
2141 13:58:36.329349 RX DATLAT : PASS
2142 13:58:36.332208 RX DQ/DQS(Engine): PASS
2143 13:58:36.332281 TX OE : NO K
2144 13:58:36.335726 All Pass.
2145 13:58:36.335798
2146 13:58:36.335874 CH 1, Rank 1
2147 13:58:36.339198 SW Impedance : PASS
2148 13:58:36.339290 DUTY Scan : NO K
2149 13:58:36.342212 ZQ Calibration : PASS
2150 13:58:36.345993 Jitter Meter : NO K
2151 13:58:36.346065 CBT Training : PASS
2152 13:58:36.349001 Write leveling : PASS
2153 13:58:36.352504 RX DQS gating : PASS
2154 13:58:36.352603 RX DQ/DQS(RDDQC) : PASS
2155 13:58:36.355734 TX DQ/DQS : PASS
2156 13:58:36.359292 RX DATLAT : PASS
2157 13:58:36.359392 RX DQ/DQS(Engine): PASS
2158 13:58:36.362664 TX OE : NO K
2159 13:58:36.362766 All Pass.
2160 13:58:36.362859
2161 13:58:36.365880 DramC Write-DBI off
2162 13:58:36.369130 PER_BANK_REFRESH: Hybrid Mode
2163 13:58:36.369211 TX_TRACKING: ON
2164 13:58:36.373061 [GetDramInforAfterCalByMRR] Vendor 6.
2165 13:58:36.376394 [GetDramInforAfterCalByMRR] Revision 606.
2166 13:58:36.379455 [GetDramInforAfterCalByMRR] Revision 2 0.
2167 13:58:36.382982 MR0 0x3b3b
2168 13:58:36.383082 MR8 0x5151
2169 13:58:36.385913 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 13:58:36.385987
2171 13:58:36.386069 MR0 0x3b3b
2172 13:58:36.389852 MR8 0x5151
2173 13:58:36.392979 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 13:58:36.393054
2175 13:58:36.399399 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2176 13:58:36.402713 [FAST_K] Save calibration result to emmc
2177 13:58:36.410019 [FAST_K] Save calibration result to emmc
2178 13:58:36.410127 dram_init: config_dvfs: 1
2179 13:58:36.412841 dramc_set_vcore_voltage set vcore to 662500
2180 13:58:36.416556 Read voltage for 1200, 2
2181 13:58:36.416654 Vio18 = 0
2182 13:58:36.419961 Vcore = 662500
2183 13:58:36.420059 Vdram = 0
2184 13:58:36.420152 Vddq = 0
2185 13:58:36.423451 Vmddr = 0
2186 13:58:36.426490 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2187 13:58:36.433291 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2188 13:58:36.433368 MEM_TYPE=3, freq_sel=15
2189 13:58:36.436326 sv_algorithm_assistance_LP4_1600
2190 13:58:36.439883 ============ PULL DRAM RESETB DOWN ============
2191 13:58:36.446471 ========== PULL DRAM RESETB DOWN end =========
2192 13:58:36.449766 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2193 13:58:36.453541 ===================================
2194 13:58:36.456386 LPDDR4 DRAM CONFIGURATION
2195 13:58:36.459954 ===================================
2196 13:58:36.460053 EX_ROW_EN[0] = 0x0
2197 13:58:36.463024 EX_ROW_EN[1] = 0x0
2198 13:58:36.463124 LP4Y_EN = 0x0
2199 13:58:36.466574 WORK_FSP = 0x0
2200 13:58:36.466674 WL = 0x4
2201 13:58:36.470053 RL = 0x4
2202 13:58:36.470150 BL = 0x2
2203 13:58:36.473135 RPST = 0x0
2204 13:58:36.476725 RD_PRE = 0x0
2205 13:58:36.476831 WR_PRE = 0x1
2206 13:58:36.480095 WR_PST = 0x0
2207 13:58:36.480196 DBI_WR = 0x0
2208 13:58:36.483594 DBI_RD = 0x0
2209 13:58:36.483670 OTF = 0x1
2210 13:58:36.486550 ===================================
2211 13:58:36.489966 ===================================
2212 13:58:36.490040 ANA top config
2213 13:58:36.493479 ===================================
2214 13:58:36.496871 DLL_ASYNC_EN = 0
2215 13:58:36.500012 ALL_SLAVE_EN = 0
2216 13:58:36.503998 NEW_RANK_MODE = 1
2217 13:58:36.504073 DLL_IDLE_MODE = 1
2218 13:58:36.507242 LP45_APHY_COMB_EN = 1
2219 13:58:36.510311 TX_ODT_DIS = 1
2220 13:58:36.513781 NEW_8X_MODE = 1
2221 13:58:36.516994 ===================================
2222 13:58:36.520189 ===================================
2223 13:58:36.524203 data_rate = 2400
2224 13:58:36.524279 CKR = 1
2225 13:58:36.526908 DQ_P2S_RATIO = 8
2226 13:58:36.530512 ===================================
2227 13:58:36.533732 CA_P2S_RATIO = 8
2228 13:58:36.537063 DQ_CA_OPEN = 0
2229 13:58:36.540368 DQ_SEMI_OPEN = 0
2230 13:58:36.543787 CA_SEMI_OPEN = 0
2231 13:58:36.543867 CA_FULL_RATE = 0
2232 13:58:36.547204 DQ_CKDIV4_EN = 0
2233 13:58:36.550690 CA_CKDIV4_EN = 0
2234 13:58:36.553979 CA_PREDIV_EN = 0
2235 13:58:36.557237 PH8_DLY = 17
2236 13:58:36.557310 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2237 13:58:36.560915 DQ_AAMCK_DIV = 4
2238 13:58:36.564042 CA_AAMCK_DIV = 4
2239 13:58:36.567506 CA_ADMCK_DIV = 4
2240 13:58:36.570659 DQ_TRACK_CA_EN = 0
2241 13:58:36.574011 CA_PICK = 1200
2242 13:58:36.577440 CA_MCKIO = 1200
2243 13:58:36.577515 MCKIO_SEMI = 0
2244 13:58:36.580937 PLL_FREQ = 2366
2245 13:58:36.584077 DQ_UI_PI_RATIO = 32
2246 13:58:36.587447 CA_UI_PI_RATIO = 0
2247 13:58:36.591174 ===================================
2248 13:58:36.594589 ===================================
2249 13:58:36.597549 memory_type:LPDDR4
2250 13:58:36.597641 GP_NUM : 10
2251 13:58:36.601337 SRAM_EN : 1
2252 13:58:36.601410 MD32_EN : 0
2253 13:58:36.604654 ===================================
2254 13:58:36.607846 [ANA_INIT] >>>>>>>>>>>>>>
2255 13:58:36.611138 <<<<<< [CONFIGURE PHASE]: ANA_TX
2256 13:58:36.614498 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2257 13:58:36.618070 ===================================
2258 13:58:36.621394 data_rate = 2400,PCW = 0X5b00
2259 13:58:36.624807 ===================================
2260 13:58:36.628273 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2261 13:58:36.631653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 13:58:36.637939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 13:58:36.641723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2264 13:58:36.644792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2265 13:58:36.648164 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2266 13:58:36.651423 [ANA_INIT] flow start
2267 13:58:36.654767 [ANA_INIT] PLL >>>>>>>>
2268 13:58:36.654847 [ANA_INIT] PLL <<<<<<<<
2269 13:58:36.658625 [ANA_INIT] MIDPI >>>>>>>>
2270 13:58:36.661928 [ANA_INIT] MIDPI <<<<<<<<
2271 13:58:36.662008 [ANA_INIT] DLL >>>>>>>>
2272 13:58:36.664992 [ANA_INIT] DLL <<<<<<<<
2273 13:58:36.668374 [ANA_INIT] flow end
2274 13:58:36.671760 ============ LP4 DIFF to SE enter ============
2275 13:58:36.675348 ============ LP4 DIFF to SE exit ============
2276 13:58:36.678744 [ANA_INIT] <<<<<<<<<<<<<
2277 13:58:36.681597 [Flow] Enable top DCM control >>>>>
2278 13:58:36.685159 [Flow] Enable top DCM control <<<<<
2279 13:58:36.688685 Enable DLL master slave shuffle
2280 13:58:36.691909 ==============================================================
2281 13:58:36.694976 Gating Mode config
2282 13:58:36.701831 ==============================================================
2283 13:58:36.701929 Config description:
2284 13:58:36.711904 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2285 13:58:36.718923 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2286 13:58:36.722174 SELPH_MODE 0: By rank 1: By Phase
2287 13:58:36.728589 ==============================================================
2288 13:58:36.731942 GAT_TRACK_EN = 1
2289 13:58:36.735384 RX_GATING_MODE = 2
2290 13:58:36.738908 RX_GATING_TRACK_MODE = 2
2291 13:58:36.742058 SELPH_MODE = 1
2292 13:58:36.742138 PICG_EARLY_EN = 1
2293 13:58:36.745555 VALID_LAT_VALUE = 1
2294 13:58:36.752250 ==============================================================
2295 13:58:36.755785 Enter into Gating configuration >>>>
2296 13:58:36.759314 Exit from Gating configuration <<<<
2297 13:58:36.762722 Enter into DVFS_PRE_config >>>>>
2298 13:58:36.772675 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2299 13:58:36.776004 Exit from DVFS_PRE_config <<<<<
2300 13:58:36.779367 Enter into PICG configuration >>>>
2301 13:58:36.782737 Exit from PICG configuration <<<<
2302 13:58:36.786252 [RX_INPUT] configuration >>>>>
2303 13:58:36.789388 [RX_INPUT] configuration <<<<<
2304 13:58:36.792702 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2305 13:58:36.799551 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2306 13:58:36.806086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 13:58:36.813048 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 13:58:36.816025 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 13:58:36.822620 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 13:58:36.826318 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2311 13:58:36.829795 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2312 13:58:36.836586 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2313 13:58:36.839746 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2314 13:58:36.842889 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2315 13:58:36.849957 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 13:58:36.853238 ===================================
2317 13:58:36.853328 LPDDR4 DRAM CONFIGURATION
2318 13:58:36.856377 ===================================
2319 13:58:36.859719 EX_ROW_EN[0] = 0x0
2320 13:58:36.859820 EX_ROW_EN[1] = 0x0
2321 13:58:36.863219 LP4Y_EN = 0x0
2322 13:58:36.863333 WORK_FSP = 0x0
2323 13:58:36.866628 WL = 0x4
2324 13:58:36.866727 RL = 0x4
2325 13:58:36.870165 BL = 0x2
2326 13:58:36.873430 RPST = 0x0
2327 13:58:36.873507 RD_PRE = 0x0
2328 13:58:36.876606 WR_PRE = 0x1
2329 13:58:36.876733 WR_PST = 0x0
2330 13:58:36.879782 DBI_WR = 0x0
2331 13:58:36.879877 DBI_RD = 0x0
2332 13:58:36.883361 OTF = 0x1
2333 13:58:36.886965 ===================================
2334 13:58:36.890396 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2335 13:58:36.893608 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2336 13:58:36.896708 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2337 13:58:36.900753 ===================================
2338 13:58:36.904416 LPDDR4 DRAM CONFIGURATION
2339 13:58:36.907038 ===================================
2340 13:58:36.910241 EX_ROW_EN[0] = 0x10
2341 13:58:36.910318 EX_ROW_EN[1] = 0x0
2342 13:58:36.913525 LP4Y_EN = 0x0
2343 13:58:36.913599 WORK_FSP = 0x0
2344 13:58:36.917192 WL = 0x4
2345 13:58:36.917266 RL = 0x4
2346 13:58:36.920580 BL = 0x2
2347 13:58:36.920703 RPST = 0x0
2348 13:58:36.923649 RD_PRE = 0x0
2349 13:58:36.923722 WR_PRE = 0x1
2350 13:58:36.927654 WR_PST = 0x0
2351 13:58:36.927754 DBI_WR = 0x0
2352 13:58:36.930453 DBI_RD = 0x0
2353 13:58:36.930548 OTF = 0x1
2354 13:58:36.934183 ===================================
2355 13:58:36.940931 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2356 13:58:36.941004 ==
2357 13:58:36.944311 Dram Type= 6, Freq= 0, CH_0, rank 0
2358 13:58:36.947160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 13:58:36.947256 ==
2360 13:58:36.950925 [Duty_Offset_Calibration]
2361 13:58:36.954372 B0:3 B1:-1 CA:1
2362 13:58:36.954469
2363 13:58:36.957664 [DutyScan_Calibration_Flow] k_type=0
2364 13:58:36.964786
2365 13:58:36.964887 ==CLK 0==
2366 13:58:36.968591 Final CLK duty delay cell = -4
2367 13:58:36.971443 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2368 13:58:36.975196 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2369 13:58:36.975295 [-4] AVG Duty = 4953%(X100)
2370 13:58:36.978805
2371 13:58:36.981518 CH0 CLK Duty spec in!! Max-Min= 156%
2372 13:58:36.985670 [DutyScan_Calibration_Flow] ====Done====
2373 13:58:36.985769
2374 13:58:36.988554 [DutyScan_Calibration_Flow] k_type=1
2375 13:58:37.003657
2376 13:58:37.003734 ==DQS 0 ==
2377 13:58:37.007241 Final DQS duty delay cell = 0
2378 13:58:37.010434 [0] MAX Duty = 5125%(X100), DQS PI = 42
2379 13:58:37.014136 [0] MIN Duty = 4969%(X100), DQS PI = 14
2380 13:58:37.014217 [0] AVG Duty = 5047%(X100)
2381 13:58:37.017377
2382 13:58:37.017447 ==DQS 1 ==
2383 13:58:37.020374 Final DQS duty delay cell = -4
2384 13:58:37.023908 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2385 13:58:37.027426 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2386 13:58:37.027498 [-4] AVG Duty = 5062%(X100)
2387 13:58:37.030652
2388 13:58:37.034370 CH0 DQS 0 Duty spec in!! Max-Min= 156%
2389 13:58:37.034468
2390 13:58:37.037399 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2391 13:58:37.040987 [DutyScan_Calibration_Flow] ====Done====
2392 13:58:37.041089
2393 13:58:37.044265 [DutyScan_Calibration_Flow] k_type=3
2394 13:58:37.060431
2395 13:58:37.060533 ==DQM 0 ==
2396 13:58:37.064309 Final DQM duty delay cell = 0
2397 13:58:37.067146 [0] MAX Duty = 5000%(X100), DQS PI = 54
2398 13:58:37.070669 [0] MIN Duty = 4906%(X100), DQS PI = 2
2399 13:58:37.070769 [0] AVG Duty = 4953%(X100)
2400 13:58:37.070870
2401 13:58:37.073989 ==DQM 1 ==
2402 13:58:37.077430 Final DQM duty delay cell = 0
2403 13:58:37.081042 [0] MAX Duty = 5124%(X100), DQS PI = 32
2404 13:58:37.083878 [0] MIN Duty = 4969%(X100), DQS PI = 8
2405 13:58:37.083987 [0] AVG Duty = 5046%(X100)
2406 13:58:37.084070
2407 13:58:37.087396 CH0 DQM 0 Duty spec in!! Max-Min= 94%
2408 13:58:37.090972
2409 13:58:37.094615 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2410 13:58:37.097365 [DutyScan_Calibration_Flow] ====Done====
2411 13:58:37.097444
2412 13:58:37.100573 [DutyScan_Calibration_Flow] k_type=2
2413 13:58:37.115860
2414 13:58:37.115968 ==DQ 0 ==
2415 13:58:37.119794 Final DQ duty delay cell = -4
2416 13:58:37.123077 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2417 13:58:37.126080 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2418 13:58:37.129518 [-4] AVG Duty = 4968%(X100)
2419 13:58:37.129593
2420 13:58:37.129691 ==DQ 1 ==
2421 13:58:37.133146 Final DQ duty delay cell = 0
2422 13:58:37.136309 [0] MAX Duty = 5031%(X100), DQS PI = 18
2423 13:58:37.139656 [0] MIN Duty = 4907%(X100), DQS PI = 46
2424 13:58:37.139755 [0] AVG Duty = 4969%(X100)
2425 13:58:37.139836
2426 13:58:37.143017 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2427 13:58:37.146186
2428 13:58:37.149457 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2429 13:58:37.152813 [DutyScan_Calibration_Flow] ====Done====
2430 13:58:37.152902 ==
2431 13:58:37.157255 Dram Type= 6, Freq= 0, CH_1, rank 0
2432 13:58:37.159755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2433 13:58:37.159855 ==
2434 13:58:37.163067 [Duty_Offset_Calibration]
2435 13:58:37.163168 B0:1 B1:1 CA:2
2436 13:58:37.163253
2437 13:58:37.166333 [DutyScan_Calibration_Flow] k_type=0
2438 13:58:37.176595
2439 13:58:37.176731 ==CLK 0==
2440 13:58:37.179937 Final CLK duty delay cell = 0
2441 13:58:37.183245 [0] MAX Duty = 5125%(X100), DQS PI = 24
2442 13:58:37.186655 [0] MIN Duty = 4969%(X100), DQS PI = 40
2443 13:58:37.186756 [0] AVG Duty = 5047%(X100)
2444 13:58:37.186858
2445 13:58:37.190365 CH1 CLK Duty spec in!! Max-Min= 156%
2446 13:58:37.196640 [DutyScan_Calibration_Flow] ====Done====
2447 13:58:37.196763
2448 13:58:37.200232 [DutyScan_Calibration_Flow] k_type=1
2449 13:58:37.215654
2450 13:58:37.215765 ==DQS 0 ==
2451 13:58:37.219357 Final DQS duty delay cell = 0
2452 13:58:37.222865 [0] MAX Duty = 5031%(X100), DQS PI = 18
2453 13:58:37.225902 [0] MIN Duty = 4844%(X100), DQS PI = 50
2454 13:58:37.225981 [0] AVG Duty = 4937%(X100)
2455 13:58:37.229143
2456 13:58:37.229218 ==DQS 1 ==
2457 13:58:37.232794 Final DQS duty delay cell = 0
2458 13:58:37.236211 [0] MAX Duty = 5062%(X100), DQS PI = 36
2459 13:58:37.239376 [0] MIN Duty = 4907%(X100), DQS PI = 16
2460 13:58:37.239478 [0] AVG Duty = 4984%(X100)
2461 13:58:37.239579
2462 13:58:37.242777 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2463 13:58:37.246253
2464 13:58:37.249405 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2465 13:58:37.252700 [DutyScan_Calibration_Flow] ====Done====
2466 13:58:37.252814
2467 13:58:37.256111 [DutyScan_Calibration_Flow] k_type=3
2468 13:58:37.272163
2469 13:58:37.272243 ==DQM 0 ==
2470 13:58:37.275530 Final DQM duty delay cell = 0
2471 13:58:37.278899 [0] MAX Duty = 5093%(X100), DQS PI = 16
2472 13:58:37.282503 [0] MIN Duty = 4907%(X100), DQS PI = 48
2473 13:58:37.282604 [0] AVG Duty = 5000%(X100)
2474 13:58:37.285985
2475 13:58:37.286057 ==DQM 1 ==
2476 13:58:37.288946 Final DQM duty delay cell = 0
2477 13:58:37.292181 [0] MAX Duty = 5156%(X100), DQS PI = 62
2478 13:58:37.295794 [0] MIN Duty = 4938%(X100), DQS PI = 22
2479 13:58:37.295868 [0] AVG Duty = 5047%(X100)
2480 13:58:37.299259
2481 13:58:37.302420 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2482 13:58:37.302509
2483 13:58:37.305899 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2484 13:58:37.309469 [DutyScan_Calibration_Flow] ====Done====
2485 13:58:37.309569
2486 13:58:37.312641 [DutyScan_Calibration_Flow] k_type=2
2487 13:58:37.329143
2488 13:58:37.329221 ==DQ 0 ==
2489 13:58:37.332124 Final DQ duty delay cell = 0
2490 13:58:37.335899 [0] MAX Duty = 5156%(X100), DQS PI = 18
2491 13:58:37.338679 [0] MIN Duty = 4907%(X100), DQS PI = 50
2492 13:58:37.338767 [0] AVG Duty = 5031%(X100)
2493 13:58:37.338849
2494 13:58:37.342215 ==DQ 1 ==
2495 13:58:37.345564 Final DQ duty delay cell = 0
2496 13:58:37.349195 [0] MAX Duty = 5093%(X100), DQS PI = 10
2497 13:58:37.352243 [0] MIN Duty = 5031%(X100), DQS PI = 2
2498 13:58:37.352373 [0] AVG Duty = 5062%(X100)
2499 13:58:37.352519
2500 13:58:37.355830 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2501 13:58:37.355947
2502 13:58:37.359050 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2503 13:58:37.362738 [DutyScan_Calibration_Flow] ====Done====
2504 13:58:37.367674 nWR fixed to 30
2505 13:58:37.370906 [ModeRegInit_LP4] CH0 RK0
2506 13:58:37.371009 [ModeRegInit_LP4] CH0 RK1
2507 13:58:37.374294 [ModeRegInit_LP4] CH1 RK0
2508 13:58:37.377875 [ModeRegInit_LP4] CH1 RK1
2509 13:58:37.377979 match AC timing 7
2510 13:58:37.384317 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2511 13:58:37.388268 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2512 13:58:37.391521 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2513 13:58:37.397978 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2514 13:58:37.401328 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2515 13:58:37.401514 ==
2516 13:58:37.404906 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 13:58:37.407970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 13:58:37.408048 ==
2519 13:58:37.414537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 13:58:37.421343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2521 13:58:37.428980 [CA 0] Center 40 (10~71) winsize 62
2522 13:58:37.432364 [CA 1] Center 39 (9~70) winsize 62
2523 13:58:37.435408 [CA 2] Center 36 (6~67) winsize 62
2524 13:58:37.438784 [CA 3] Center 36 (6~66) winsize 61
2525 13:58:37.442539 [CA 4] Center 34 (4~65) winsize 62
2526 13:58:37.445664 [CA 5] Center 34 (4~64) winsize 61
2527 13:58:37.445794
2528 13:58:37.448964 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2529 13:58:37.449077
2530 13:58:37.452196 [CATrainingPosCal] consider 1 rank data
2531 13:58:37.455933 u2DelayCellTimex100 = 270/100 ps
2532 13:58:37.459099 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2533 13:58:37.462570 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2534 13:58:37.469061 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2535 13:58:37.472259 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2536 13:58:37.476122 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2537 13:58:37.479195 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2538 13:58:37.479294
2539 13:58:37.482405 CA PerBit enable=1, Macro0, CA PI delay=34
2540 13:58:37.482507
2541 13:58:37.486114 [CBTSetCACLKResult] CA Dly = 34
2542 13:58:37.486212 CS Dly: 7 (0~38)
2543 13:58:37.486312 ==
2544 13:58:37.489398 Dram Type= 6, Freq= 0, CH_0, rank 1
2545 13:58:37.495921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 13:58:37.496024 ==
2547 13:58:37.499731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2548 13:58:37.506063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2549 13:58:37.515048 [CA 0] Center 39 (9~70) winsize 62
2550 13:58:37.517774 [CA 1] Center 39 (9~70) winsize 62
2551 13:58:37.521768 [CA 2] Center 36 (6~67) winsize 62
2552 13:58:37.524738 [CA 3] Center 35 (5~66) winsize 62
2553 13:58:37.527937 [CA 4] Center 34 (4~65) winsize 62
2554 13:58:37.531384 [CA 5] Center 34 (4~64) winsize 61
2555 13:58:37.531485
2556 13:58:37.534811 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2557 13:58:37.534908
2558 13:58:37.537932 [CATrainingPosCal] consider 2 rank data
2559 13:58:37.541528 u2DelayCellTimex100 = 270/100 ps
2560 13:58:37.544955 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2561 13:58:37.547972 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2562 13:58:37.555080 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2563 13:58:37.558505 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2564 13:58:37.561701 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2565 13:58:37.564883 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2566 13:58:37.564967
2567 13:58:37.568355 CA PerBit enable=1, Macro0, CA PI delay=34
2568 13:58:37.568458
2569 13:58:37.571770 [CBTSetCACLKResult] CA Dly = 34
2570 13:58:37.571867 CS Dly: 8 (0~41)
2571 13:58:37.571948
2572 13:58:37.575349 ----->DramcWriteLeveling(PI) begin...
2573 13:58:37.575449 ==
2574 13:58:37.578282 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 13:58:37.585090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 13:58:37.585166 ==
2577 13:58:37.588687 Write leveling (Byte 0): 31 => 31
2578 13:58:37.591536 Write leveling (Byte 1): 29 => 29
2579 13:58:37.591632 DramcWriteLeveling(PI) end<-----
2580 13:58:37.591730
2581 13:58:37.594956 ==
2582 13:58:37.598223 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 13:58:37.601960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 13:58:37.602034 ==
2585 13:58:37.605544 [Gating] SW mode calibration
2586 13:58:37.611770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2587 13:58:37.615342 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2588 13:58:37.622105 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 13:58:37.625233 0 15 4 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)
2590 13:58:37.628990 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 13:58:37.635585 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 13:58:37.638623 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 13:58:37.642385 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 13:58:37.645884 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 13:58:37.651921 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 13:58:37.655751 1 0 0 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
2597 13:58:37.658906 1 0 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
2598 13:58:37.665575 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 13:58:37.668987 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 13:58:37.672614 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 13:58:37.678993 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 13:58:37.682372 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 13:58:37.685647 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 13:58:37.692205 1 1 0 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
2605 13:58:37.695733 1 1 4 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
2606 13:58:37.699315 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 13:58:37.702841 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 13:58:37.709670 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 13:58:37.712886 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 13:58:37.715676 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 13:58:37.722734 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 13:58:37.725800 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2613 13:58:37.729703 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 13:58:37.735814 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 13:58:37.739635 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 13:58:37.742706 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 13:58:37.749382 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 13:58:37.753302 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 13:58:37.756330 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 13:58:37.759792 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 13:58:37.766503 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 13:58:37.769752 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 13:58:37.773054 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 13:58:37.779749 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 13:58:37.783227 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 13:58:37.786321 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 13:58:37.793369 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 13:58:37.796507 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2629 13:58:37.799777 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 13:58:37.803277 Total UI for P1: 0, mck2ui 16
2631 13:58:37.806472 best dqsien dly found for B0: ( 1, 4, 0)
2632 13:58:37.810089 Total UI for P1: 0, mck2ui 16
2633 13:58:37.813589 best dqsien dly found for B1: ( 1, 4, 0)
2634 13:58:37.817239 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2635 13:58:37.820261 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2636 13:58:37.820358
2637 13:58:37.823770 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2638 13:58:37.826864 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2639 13:58:37.829986 [Gating] SW calibration Done
2640 13:58:37.830083 ==
2641 13:58:37.833628 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 13:58:37.837086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 13:58:37.840729 ==
2644 13:58:37.840829 RX Vref Scan: 0
2645 13:58:37.840920
2646 13:58:37.843640 RX Vref 0 -> 0, step: 1
2647 13:58:37.843735
2648 13:58:37.843797 RX Delay -40 -> 252, step: 8
2649 13:58:37.850344 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2650 13:58:37.853740 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2651 13:58:37.857186 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2652 13:58:37.860498 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2653 13:58:37.863900 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2654 13:58:37.870740 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2655 13:58:37.874391 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2656 13:58:37.877416 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2657 13:58:37.880820 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2658 13:58:37.884251 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2659 13:58:37.887924 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2660 13:58:37.894293 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2661 13:58:37.897674 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2662 13:58:37.901112 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2663 13:58:37.904412 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2664 13:58:37.907559 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2665 13:58:37.911231 ==
2666 13:58:37.911333 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 13:58:37.918128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 13:58:37.918235 ==
2669 13:58:37.918305 DQS Delay:
2670 13:58:37.921353 DQS0 = 0, DQS1 = 0
2671 13:58:37.921444 DQM Delay:
2672 13:58:37.924590 DQM0 = 115, DQM1 = 107
2673 13:58:37.924697 DQ Delay:
2674 13:58:37.927863 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2675 13:58:37.931320 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2676 13:58:37.934736 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2677 13:58:37.938075 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2678 13:58:37.938176
2679 13:58:37.938276
2680 13:58:37.938364 ==
2681 13:58:37.941191 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 13:58:37.944812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 13:58:37.947878 ==
2684 13:58:37.947976
2685 13:58:37.948065
2686 13:58:37.948155 TX Vref Scan disable
2687 13:58:37.951799 == TX Byte 0 ==
2688 13:58:37.955370 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2689 13:58:37.958124 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2690 13:58:37.961386 == TX Byte 1 ==
2691 13:58:37.965309 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2692 13:58:37.968521 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2693 13:58:37.968622 ==
2694 13:58:37.971486 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 13:58:37.978182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 13:58:37.978266 ==
2697 13:58:37.989140 TX Vref=22, minBit 1, minWin=25, winSum=416
2698 13:58:37.992444 TX Vref=24, minBit 7, minWin=25, winSum=425
2699 13:58:37.995845 TX Vref=26, minBit 0, minWin=26, winSum=431
2700 13:58:37.999018 TX Vref=28, minBit 1, minWin=25, winSum=432
2701 13:58:38.002815 TX Vref=30, minBit 7, minWin=26, winSum=433
2702 13:58:38.006087 TX Vref=32, minBit 0, minWin=26, winSum=432
2703 13:58:38.012860 [TxChooseVref] Worse bit 7, Min win 26, Win sum 433, Final Vref 30
2704 13:58:38.012972
2705 13:58:38.016120 Final TX Range 1 Vref 30
2706 13:58:38.016221
2707 13:58:38.016311 ==
2708 13:58:38.019410 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 13:58:38.022525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 13:58:38.022633 ==
2711 13:58:38.022725
2712 13:58:38.022810
2713 13:58:38.025920 TX Vref Scan disable
2714 13:58:38.029660 == TX Byte 0 ==
2715 13:58:38.032996 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2716 13:58:38.035990 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2717 13:58:38.039398 == TX Byte 1 ==
2718 13:58:38.042948 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2719 13:58:38.046078 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2720 13:58:38.046179
2721 13:58:38.049488 [DATLAT]
2722 13:58:38.049596 Freq=1200, CH0 RK0
2723 13:58:38.049690
2724 13:58:38.053124 DATLAT Default: 0xd
2725 13:58:38.053227 0, 0xFFFF, sum = 0
2726 13:58:38.056133 1, 0xFFFF, sum = 0
2727 13:58:38.056242 2, 0xFFFF, sum = 0
2728 13:58:38.059554 3, 0xFFFF, sum = 0
2729 13:58:38.059661 4, 0xFFFF, sum = 0
2730 13:58:38.063046 5, 0xFFFF, sum = 0
2731 13:58:38.063144 6, 0xFFFF, sum = 0
2732 13:58:38.066333 7, 0xFFFF, sum = 0
2733 13:58:38.066461 8, 0xFFFF, sum = 0
2734 13:58:38.069520 9, 0xFFFF, sum = 0
2735 13:58:38.069627 10, 0xFFFF, sum = 0
2736 13:58:38.072811 11, 0xFFFF, sum = 0
2737 13:58:38.072912 12, 0x0, sum = 1
2738 13:58:38.076721 13, 0x0, sum = 2
2739 13:58:38.076831 14, 0x0, sum = 3
2740 13:58:38.079741 15, 0x0, sum = 4
2741 13:58:38.079836 best_step = 13
2742 13:58:38.079923
2743 13:58:38.080014 ==
2744 13:58:38.083595 Dram Type= 6, Freq= 0, CH_0, rank 0
2745 13:58:38.086444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2746 13:58:38.089888 ==
2747 13:58:38.089990 RX Vref Scan: 1
2748 13:58:38.090080
2749 13:58:38.093073 Set Vref Range= 32 -> 127
2750 13:58:38.093184
2751 13:58:38.096419 RX Vref 32 -> 127, step: 1
2752 13:58:38.096520
2753 13:58:38.096611 RX Delay -21 -> 252, step: 4
2754 13:58:38.096734
2755 13:58:38.100297 Set Vref, RX VrefLevel [Byte0]: 32
2756 13:58:38.103239 [Byte1]: 32
2757 13:58:38.107245
2758 13:58:38.107343 Set Vref, RX VrefLevel [Byte0]: 33
2759 13:58:38.110797 [Byte1]: 33
2760 13:58:38.115138
2761 13:58:38.115221 Set Vref, RX VrefLevel [Byte0]: 34
2762 13:58:38.118591 [Byte1]: 34
2763 13:58:38.123150
2764 13:58:38.123259 Set Vref, RX VrefLevel [Byte0]: 35
2765 13:58:38.126620 [Byte1]: 35
2766 13:58:38.131453
2767 13:58:38.131558 Set Vref, RX VrefLevel [Byte0]: 36
2768 13:58:38.134643 [Byte1]: 36
2769 13:58:38.138923
2770 13:58:38.139053 Set Vref, RX VrefLevel [Byte0]: 37
2771 13:58:38.142392 [Byte1]: 37
2772 13:58:38.146966
2773 13:58:38.147070 Set Vref, RX VrefLevel [Byte0]: 38
2774 13:58:38.150156 [Byte1]: 38
2775 13:58:38.154703
2776 13:58:38.154805 Set Vref, RX VrefLevel [Byte0]: 39
2777 13:58:38.158171 [Byte1]: 39
2778 13:58:38.162642
2779 13:58:38.162740 Set Vref, RX VrefLevel [Byte0]: 40
2780 13:58:38.165879 [Byte1]: 40
2781 13:58:38.170722
2782 13:58:38.170825 Set Vref, RX VrefLevel [Byte0]: 41
2783 13:58:38.173966 [Byte1]: 41
2784 13:58:38.179360
2785 13:58:38.179459 Set Vref, RX VrefLevel [Byte0]: 42
2786 13:58:38.181785 [Byte1]: 42
2787 13:58:38.186491
2788 13:58:38.186588 Set Vref, RX VrefLevel [Byte0]: 43
2789 13:58:38.189913 [Byte1]: 43
2790 13:58:38.194728
2791 13:58:38.194835 Set Vref, RX VrefLevel [Byte0]: 44
2792 13:58:38.198092 [Byte1]: 44
2793 13:58:38.202566
2794 13:58:38.202651 Set Vref, RX VrefLevel [Byte0]: 45
2795 13:58:38.205881 [Byte1]: 45
2796 13:58:38.210481
2797 13:58:38.210578 Set Vref, RX VrefLevel [Byte0]: 46
2798 13:58:38.213534 [Byte1]: 46
2799 13:58:38.218467
2800 13:58:38.218565 Set Vref, RX VrefLevel [Byte0]: 47
2801 13:58:38.222050 [Byte1]: 47
2802 13:58:38.226279
2803 13:58:38.226375 Set Vref, RX VrefLevel [Byte0]: 48
2804 13:58:38.229834 [Byte1]: 48
2805 13:58:38.233889
2806 13:58:38.233998 Set Vref, RX VrefLevel [Byte0]: 49
2807 13:58:38.237435 [Byte1]: 49
2808 13:58:38.242018
2809 13:58:38.242090 Set Vref, RX VrefLevel [Byte0]: 50
2810 13:58:38.245655 [Byte1]: 50
2811 13:58:38.249727
2812 13:58:38.249850 Set Vref, RX VrefLevel [Byte0]: 51
2813 13:58:38.253223 [Byte1]: 51
2814 13:58:38.258241
2815 13:58:38.258342 Set Vref, RX VrefLevel [Byte0]: 52
2816 13:58:38.261540 [Byte1]: 52
2817 13:58:38.265798
2818 13:58:38.265905 Set Vref, RX VrefLevel [Byte0]: 53
2819 13:58:38.268854 [Byte1]: 53
2820 13:58:38.273890
2821 13:58:38.273992 Set Vref, RX VrefLevel [Byte0]: 54
2822 13:58:38.276997 [Byte1]: 54
2823 13:58:38.281678
2824 13:58:38.281779 Set Vref, RX VrefLevel [Byte0]: 55
2825 13:58:38.285108 [Byte1]: 55
2826 13:58:38.289628
2827 13:58:38.289713 Set Vref, RX VrefLevel [Byte0]: 56
2828 13:58:38.293389 [Byte1]: 56
2829 13:58:38.297405
2830 13:58:38.297489 Set Vref, RX VrefLevel [Byte0]: 57
2831 13:58:38.300829 [Byte1]: 57
2832 13:58:38.305667
2833 13:58:38.305769 Set Vref, RX VrefLevel [Byte0]: 58
2834 13:58:38.308690 [Byte1]: 58
2835 13:58:38.313261
2836 13:58:38.313359 Set Vref, RX VrefLevel [Byte0]: 59
2837 13:58:38.316676 [Byte1]: 59
2838 13:58:38.321176
2839 13:58:38.321272 Set Vref, RX VrefLevel [Byte0]: 60
2840 13:58:38.324741 [Byte1]: 60
2841 13:58:38.329023
2842 13:58:38.329098 Set Vref, RX VrefLevel [Byte0]: 61
2843 13:58:38.332932 [Byte1]: 61
2844 13:58:38.337084
2845 13:58:38.337160 Set Vref, RX VrefLevel [Byte0]: 62
2846 13:58:38.340414 [Byte1]: 62
2847 13:58:38.344897
2848 13:58:38.344997 Set Vref, RX VrefLevel [Byte0]: 63
2849 13:58:38.348204 [Byte1]: 63
2850 13:58:38.353063
2851 13:58:38.353171 Set Vref, RX VrefLevel [Byte0]: 64
2852 13:58:38.356628 [Byte1]: 64
2853 13:58:38.361153
2854 13:58:38.361224 Set Vref, RX VrefLevel [Byte0]: 65
2855 13:58:38.364156 [Byte1]: 65
2856 13:58:38.369125
2857 13:58:38.369229 Set Vref, RX VrefLevel [Byte0]: 66
2858 13:58:38.371942 [Byte1]: 66
2859 13:58:38.377175
2860 13:58:38.377273 Set Vref, RX VrefLevel [Byte0]: 67
2861 13:58:38.379985 [Byte1]: 67
2862 13:58:38.384877
2863 13:58:38.384957 Set Vref, RX VrefLevel [Byte0]: 68
2864 13:58:38.387874 [Byte1]: 68
2865 13:58:38.392796
2866 13:58:38.392895 Final RX Vref Byte 0 = 54 to rank0
2867 13:58:38.396278 Final RX Vref Byte 1 = 52 to rank0
2868 13:58:38.399383 Final RX Vref Byte 0 = 54 to rank1
2869 13:58:38.402896 Final RX Vref Byte 1 = 52 to rank1==
2870 13:58:38.405903 Dram Type= 6, Freq= 0, CH_0, rank 0
2871 13:58:38.409632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 13:58:38.412958 ==
2873 13:58:38.413059 DQS Delay:
2874 13:58:38.413161 DQS0 = 0, DQS1 = 0
2875 13:58:38.416026 DQM Delay:
2876 13:58:38.416124 DQM0 = 115, DQM1 = 106
2877 13:58:38.419411 DQ Delay:
2878 13:58:38.422837 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2879 13:58:38.426406 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2880 13:58:38.430223 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
2881 13:58:38.433437 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =116
2882 13:58:38.433523
2883 13:58:38.433587
2884 13:58:38.439967 [DQSOSCAuto] RK0, (LSB)MR18= 0xef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2885 13:58:38.443836 CH0 RK0: MR19=403, MR18=EF
2886 13:58:38.449803 CH0_RK0: MR19=0x403, MR18=0xEF, DQSOSC=410, MR23=63, INC=39, DEC=26
2887 13:58:38.449903
2888 13:58:38.453175 ----->DramcWriteLeveling(PI) begin...
2889 13:58:38.453277 ==
2890 13:58:38.456478 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 13:58:38.460074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 13:58:38.460168 ==
2893 13:58:38.463524 Write leveling (Byte 0): 33 => 33
2894 13:58:38.466762 Write leveling (Byte 1): 27 => 27
2895 13:58:38.470304 DramcWriteLeveling(PI) end<-----
2896 13:58:38.470403
2897 13:58:38.470492 ==
2898 13:58:38.473947 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 13:58:38.477262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 13:58:38.477357 ==
2901 13:58:38.480112 [Gating] SW mode calibration
2902 13:58:38.487129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2903 13:58:38.493958 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2904 13:58:38.497330 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2905 13:58:38.500460 0 15 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2906 13:58:38.507172 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 13:58:38.510335 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 13:58:38.514292 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 13:58:38.517385 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 13:58:38.523748 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2911 13:58:38.527752 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2912 13:58:38.530879 1 0 0 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (0 0)
2913 13:58:38.537426 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 13:58:38.540844 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 13:58:38.543967 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 13:58:38.550963 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 13:58:38.554371 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 13:58:38.557955 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
2919 13:58:38.564280 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2920 13:58:38.567839 1 1 0 | B1->B0 | 3837 4545 | 1 0 | (0 0) (1 1)
2921 13:58:38.571018 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 13:58:38.574768 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 13:58:38.581196 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 13:58:38.584599 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 13:58:38.587737 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 13:58:38.594861 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 13:58:38.597971 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2928 13:58:38.601306 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2929 13:58:38.607899 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2930 13:58:38.611396 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 13:58:38.615231 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 13:58:38.618317 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 13:58:38.624832 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 13:58:38.628519 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 13:58:38.632041 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 13:58:38.638317 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 13:58:38.641877 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 13:58:38.645432 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 13:58:38.651831 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 13:58:38.655067 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 13:58:38.658538 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 13:58:38.665436 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2943 13:58:38.668901 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2944 13:58:38.671971 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2945 13:58:38.675218 Total UI for P1: 0, mck2ui 16
2946 13:58:38.679424 best dqsien dly found for B0: ( 1, 3, 26)
2947 13:58:38.681943 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 13:58:38.685856 Total UI for P1: 0, mck2ui 16
2949 13:58:38.688643 best dqsien dly found for B1: ( 1, 3, 30)
2950 13:58:38.692148 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2951 13:58:38.695417 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2952 13:58:38.695492
2953 13:58:38.702001 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2954 13:58:38.706263 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2955 13:58:38.709128 [Gating] SW calibration Done
2956 13:58:38.709227 ==
2957 13:58:38.712175 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 13:58:38.715728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 13:58:38.715828 ==
2960 13:58:38.715917 RX Vref Scan: 0
2961 13:58:38.716010
2962 13:58:38.718864 RX Vref 0 -> 0, step: 1
2963 13:58:38.718988
2964 13:58:38.722385 RX Delay -40 -> 252, step: 8
2965 13:58:38.725894 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2966 13:58:38.729075 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2967 13:58:38.732878 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2968 13:58:38.739402 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2969 13:58:38.742837 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2970 13:58:38.745951 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2971 13:58:38.749268 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2972 13:58:38.752573 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2973 13:58:38.755946 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2974 13:58:38.762953 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2975 13:58:38.766069 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2976 13:58:38.769928 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2977 13:58:38.773142 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2978 13:58:38.776879 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2979 13:58:38.782797 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2980 13:58:38.786308 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2981 13:58:38.786408 ==
2982 13:58:38.789477 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 13:58:38.793082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 13:58:38.793191 ==
2985 13:58:38.796624 DQS Delay:
2986 13:58:38.796736 DQS0 = 0, DQS1 = 0
2987 13:58:38.796812 DQM Delay:
2988 13:58:38.799708 DQM0 = 115, DQM1 = 106
2989 13:58:38.799806 DQ Delay:
2990 13:58:38.803259 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2991 13:58:38.806717 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2992 13:58:38.810493 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2993 13:58:38.813216 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =111
2994 13:58:38.813291
2995 13:58:38.816873
2996 13:58:38.817044 ==
2997 13:58:38.819795 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 13:58:38.823307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 13:58:38.823413 ==
3000 13:58:38.823505
3001 13:58:38.823591
3002 13:58:38.826814 TX Vref Scan disable
3003 13:58:38.826911 == TX Byte 0 ==
3004 13:58:38.829793 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3005 13:58:38.836646 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3006 13:58:38.836737 == TX Byte 1 ==
3007 13:58:38.840023 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3008 13:58:38.846662 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3009 13:58:38.846763 ==
3010 13:58:38.850053 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 13:58:38.853502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 13:58:38.853603 ==
3013 13:58:38.865871 TX Vref=22, minBit 1, minWin=25, winSum=421
3014 13:58:38.869078 TX Vref=24, minBit 0, minWin=26, winSum=424
3015 13:58:38.872305 TX Vref=26, minBit 1, minWin=25, winSum=431
3016 13:58:38.875772 TX Vref=28, minBit 3, minWin=26, winSum=435
3017 13:58:38.879086 TX Vref=30, minBit 3, minWin=26, winSum=435
3018 13:58:38.882324 TX Vref=32, minBit 3, minWin=26, winSum=433
3019 13:58:38.889123 [TxChooseVref] Worse bit 3, Min win 26, Win sum 435, Final Vref 28
3020 13:58:38.889221
3021 13:58:38.892734 Final TX Range 1 Vref 28
3022 13:58:38.892829
3023 13:58:38.892906 ==
3024 13:58:38.895722 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 13:58:38.899310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 13:58:38.899410 ==
3027 13:58:38.899501
3028 13:58:38.899586
3029 13:58:38.902719 TX Vref Scan disable
3030 13:58:38.905705 == TX Byte 0 ==
3031 13:58:38.909656 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3032 13:58:38.913174 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3033 13:58:38.916293 == TX Byte 1 ==
3034 13:58:38.919442 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3035 13:58:38.923090 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3036 13:58:38.923190
3037 13:58:38.926225 [DATLAT]
3038 13:58:38.926323 Freq=1200, CH0 RK1
3039 13:58:38.926414
3040 13:58:38.929396 DATLAT Default: 0xd
3041 13:58:38.929491 0, 0xFFFF, sum = 0
3042 13:58:38.932804 1, 0xFFFF, sum = 0
3043 13:58:38.932875 2, 0xFFFF, sum = 0
3044 13:58:38.936103 3, 0xFFFF, sum = 0
3045 13:58:38.936203 4, 0xFFFF, sum = 0
3046 13:58:38.939518 5, 0xFFFF, sum = 0
3047 13:58:38.939620 6, 0xFFFF, sum = 0
3048 13:58:38.942951 7, 0xFFFF, sum = 0
3049 13:58:38.943089 8, 0xFFFF, sum = 0
3050 13:58:38.946077 9, 0xFFFF, sum = 0
3051 13:58:38.946181 10, 0xFFFF, sum = 0
3052 13:58:38.949399 11, 0xFFFF, sum = 0
3053 13:58:38.949490 12, 0x0, sum = 1
3054 13:58:38.953291 13, 0x0, sum = 2
3055 13:58:38.953401 14, 0x0, sum = 3
3056 13:58:38.956171 15, 0x0, sum = 4
3057 13:58:38.956268 best_step = 13
3058 13:58:38.956368
3059 13:58:38.956453 ==
3060 13:58:38.959768 Dram Type= 6, Freq= 0, CH_0, rank 1
3061 13:58:38.966232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 13:58:38.966333 ==
3063 13:58:38.966425 RX Vref Scan: 0
3064 13:58:38.966524
3065 13:58:38.969880 RX Vref 0 -> 0, step: 1
3066 13:58:38.969977
3067 13:58:38.973392 RX Delay -21 -> 252, step: 4
3068 13:58:38.976450 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3069 13:58:38.980551 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3070 13:58:38.983079 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3071 13:58:38.990074 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3072 13:58:38.993230 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3073 13:58:38.996641 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3074 13:58:38.999913 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3075 13:58:39.003424 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3076 13:58:39.007213 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3077 13:58:39.013603 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3078 13:58:39.016913 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3079 13:58:39.020118 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3080 13:58:39.023428 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3081 13:58:39.026807 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3082 13:58:39.033483 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3083 13:58:39.036936 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3084 13:58:39.037016 ==
3085 13:58:39.040651 Dram Type= 6, Freq= 0, CH_0, rank 1
3086 13:58:39.043686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 13:58:39.043766 ==
3088 13:58:39.047153 DQS Delay:
3089 13:58:39.047256 DQS0 = 0, DQS1 = 0
3090 13:58:39.047385 DQM Delay:
3091 13:58:39.051013 DQM0 = 114, DQM1 = 104
3092 13:58:39.051110 DQ Delay:
3093 13:58:39.053697 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3094 13:58:39.057701 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3095 13:58:39.060285 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3096 13:58:39.063643 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3097 13:58:39.067098
3098 13:58:39.067200
3099 13:58:39.074012 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3100 13:58:39.077241 CH0 RK1: MR19=403, MR18=3F3
3101 13:58:39.080546 CH0_RK1: MR19=0x403, MR18=0x3F3, DQSOSC=408, MR23=63, INC=39, DEC=26
3102 13:58:39.084022 [RxdqsGatingPostProcess] freq 1200
3103 13:58:39.090975 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3104 13:58:39.094091 best DQS0 dly(2T, 0.5T) = (0, 12)
3105 13:58:39.097478 best DQS1 dly(2T, 0.5T) = (0, 12)
3106 13:58:39.100642 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3107 13:58:39.104258 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3108 13:58:39.107534 best DQS0 dly(2T, 0.5T) = (0, 11)
3109 13:58:39.110830 best DQS1 dly(2T, 0.5T) = (0, 11)
3110 13:58:39.114342 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3111 13:58:39.117512 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3112 13:58:39.117612 Pre-setting of DQS Precalculation
3113 13:58:39.124261 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3114 13:58:39.124363 ==
3115 13:58:39.127888 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 13:58:39.131064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 13:58:39.131164 ==
3118 13:58:39.137912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3119 13:58:39.144124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3120 13:58:39.151585 [CA 0] Center 38 (8~68) winsize 61
3121 13:58:39.154979 [CA 1] Center 38 (8~68) winsize 61
3122 13:58:39.158152 [CA 2] Center 35 (5~65) winsize 61
3123 13:58:39.161664 [CA 3] Center 34 (4~65) winsize 62
3124 13:58:39.164946 [CA 4] Center 34 (4~65) winsize 62
3125 13:58:39.168253 [CA 5] Center 34 (4~64) winsize 61
3126 13:58:39.168361
3127 13:58:39.171544 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3128 13:58:39.171653
3129 13:58:39.174923 [CATrainingPosCal] consider 1 rank data
3130 13:58:39.178422 u2DelayCellTimex100 = 270/100 ps
3131 13:58:39.182069 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3132 13:58:39.185106 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3133 13:58:39.188786 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3134 13:58:39.195334 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3135 13:58:39.198556 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3136 13:58:39.201678 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3137 13:58:39.201788
3138 13:58:39.204951 CA PerBit enable=1, Macro0, CA PI delay=34
3139 13:58:39.205050
3140 13:58:39.208626 [CBTSetCACLKResult] CA Dly = 34
3141 13:58:39.208759 CS Dly: 6 (0~37)
3142 13:58:39.208848 ==
3143 13:58:39.212041 Dram Type= 6, Freq= 0, CH_1, rank 1
3144 13:58:39.218372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 13:58:39.218494 ==
3146 13:58:39.221744 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3147 13:58:39.228499 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3148 13:58:39.236807 [CA 0] Center 38 (8~68) winsize 61
3149 13:58:39.240418 [CA 1] Center 38 (9~68) winsize 60
3150 13:58:39.243319 [CA 2] Center 34 (4~65) winsize 62
3151 13:58:39.246739 [CA 3] Center 34 (4~65) winsize 62
3152 13:58:39.250303 [CA 4] Center 34 (4~65) winsize 62
3153 13:58:39.253968 [CA 5] Center 33 (3~63) winsize 61
3154 13:58:39.254075
3155 13:58:39.257262 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3156 13:58:39.257336
3157 13:58:39.260364 [CATrainingPosCal] consider 2 rank data
3158 13:58:39.263736 u2DelayCellTimex100 = 270/100 ps
3159 13:58:39.266773 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3160 13:58:39.270426 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3161 13:58:39.277050 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3162 13:58:39.280637 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3163 13:58:39.283553 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3164 13:58:39.287112 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3165 13:58:39.287212
3166 13:58:39.290511 CA PerBit enable=1, Macro0, CA PI delay=33
3167 13:58:39.290609
3168 13:58:39.293878 [CBTSetCACLKResult] CA Dly = 33
3169 13:58:39.293985 CS Dly: 7 (0~40)
3170 13:58:39.294074
3171 13:58:39.297324 ----->DramcWriteLeveling(PI) begin...
3172 13:58:39.297415 ==
3173 13:58:39.300513 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 13:58:39.307632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 13:58:39.307740 ==
3176 13:58:39.310479 Write leveling (Byte 0): 26 => 26
3177 13:58:39.313907 Write leveling (Byte 1): 29 => 29
3178 13:58:39.314011 DramcWriteLeveling(PI) end<-----
3179 13:58:39.314144
3180 13:58:39.317559 ==
3181 13:58:39.320808 Dram Type= 6, Freq= 0, CH_1, rank 0
3182 13:58:39.324137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3183 13:58:39.324234 ==
3184 13:58:39.327509 [Gating] SW mode calibration
3185 13:58:39.334024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3186 13:58:39.337217 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3187 13:58:39.343961 0 15 0 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
3188 13:58:39.347409 0 15 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
3189 13:58:39.351226 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3190 13:58:39.358086 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 13:58:39.361124 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 13:58:39.364531 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 13:58:39.367948 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 13:58:39.374645 0 15 28 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 0)
3195 13:58:39.377697 1 0 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
3196 13:58:39.381192 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 13:58:39.388083 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 13:58:39.391618 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 13:58:39.394695 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 13:58:39.401439 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 13:58:39.404663 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 13:58:39.408003 1 0 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3203 13:58:39.415488 1 1 0 | B1->B0 | 4545 3636 | 0 0 | (0 0) (0 0)
3204 13:58:39.418390 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 13:58:39.421404 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 13:58:39.425143 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 13:58:39.431416 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 13:58:39.435097 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 13:58:39.438578 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 13:58:39.445169 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3211 13:58:39.448305 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3212 13:58:39.452003 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 13:58:39.458384 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 13:58:39.462116 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 13:58:39.465285 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 13:58:39.468650 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 13:58:39.475603 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 13:58:39.478860 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 13:58:39.482257 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 13:58:39.488929 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 13:58:39.491954 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 13:58:39.495769 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 13:58:39.502336 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 13:58:39.505473 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 13:58:39.508883 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 13:58:39.515556 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3227 13:58:39.518856 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3228 13:58:39.522889 Total UI for P1: 0, mck2ui 16
3229 13:58:39.525579 best dqsien dly found for B1: ( 1, 3, 30)
3230 13:58:39.529443 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 13:58:39.532669 Total UI for P1: 0, mck2ui 16
3232 13:58:39.535726 best dqsien dly found for B0: ( 1, 3, 30)
3233 13:58:39.539304 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3234 13:58:39.542833 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3235 13:58:39.542939
3236 13:58:39.546091 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3237 13:58:39.549607 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3238 13:58:39.552705 [Gating] SW calibration Done
3239 13:58:39.552820 ==
3240 13:58:39.556119 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 13:58:39.559549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 13:58:39.563192 ==
3243 13:58:39.563275 RX Vref Scan: 0
3244 13:58:39.563339
3245 13:58:39.566472 RX Vref 0 -> 0, step: 1
3246 13:58:39.566553
3247 13:58:39.569513 RX Delay -40 -> 252, step: 8
3248 13:58:39.573134 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3249 13:58:39.576564 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3250 13:58:39.579440 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3251 13:58:39.582914 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3252 13:58:39.586148 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3253 13:58:39.593362 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3254 13:58:39.596640 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3255 13:58:39.600271 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3256 13:58:39.602954 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3257 13:58:39.606678 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3258 13:58:39.610311 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3259 13:58:39.616910 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3260 13:58:39.619940 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3261 13:58:39.623191 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3262 13:58:39.626548 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3263 13:58:39.633224 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3264 13:58:39.633332 ==
3265 13:58:39.636835 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 13:58:39.640165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 13:58:39.640247 ==
3268 13:58:39.640311 DQS Delay:
3269 13:58:39.643340 DQS0 = 0, DQS1 = 0
3270 13:58:39.643420 DQM Delay:
3271 13:58:39.647503 DQM0 = 116, DQM1 = 109
3272 13:58:39.647583 DQ Delay:
3273 13:58:39.650254 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3274 13:58:39.653497 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3275 13:58:39.657202 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3276 13:58:39.660164 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3277 13:58:39.660245
3278 13:58:39.660391
3279 13:58:39.660515 ==
3280 13:58:39.663817 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 13:58:39.670487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 13:58:39.670592 ==
3283 13:58:39.670687
3284 13:58:39.670776
3285 13:58:39.670864 TX Vref Scan disable
3286 13:58:39.673572 == TX Byte 0 ==
3287 13:58:39.677090 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3288 13:58:39.680226 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3289 13:58:39.683492 == TX Byte 1 ==
3290 13:58:39.687491 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3291 13:58:39.690704 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3292 13:58:39.693770 ==
3293 13:58:39.697025 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 13:58:39.700382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 13:58:39.700480 ==
3296 13:58:39.711748 TX Vref=22, minBit 1, minWin=24, winSum=408
3297 13:58:39.714713 TX Vref=24, minBit 1, minWin=26, winSum=423
3298 13:58:39.718349 TX Vref=26, minBit 0, minWin=26, winSum=422
3299 13:58:39.721761 TX Vref=28, minBit 0, minWin=26, winSum=423
3300 13:58:39.725000 TX Vref=30, minBit 1, minWin=26, winSum=429
3301 13:58:39.728202 TX Vref=32, minBit 1, minWin=26, winSum=426
3302 13:58:39.735121 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3303 13:58:39.735199
3304 13:58:39.738542 Final TX Range 1 Vref 30
3305 13:58:39.738647
3306 13:58:39.738742 ==
3307 13:58:39.741899 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 13:58:39.745149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 13:58:39.745247 ==
3310 13:58:39.745318
3311 13:58:39.745375
3312 13:58:39.748711 TX Vref Scan disable
3313 13:58:39.752612 == TX Byte 0 ==
3314 13:58:39.755315 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3315 13:58:39.759163 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3316 13:58:39.762496 == TX Byte 1 ==
3317 13:58:39.765354 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3318 13:58:39.768941 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3319 13:58:39.769045
3320 13:58:39.772502 [DATLAT]
3321 13:58:39.772597 Freq=1200, CH1 RK0
3322 13:58:39.772730
3323 13:58:39.775256 DATLAT Default: 0xd
3324 13:58:39.775353 0, 0xFFFF, sum = 0
3325 13:58:39.779027 1, 0xFFFF, sum = 0
3326 13:58:39.779130 2, 0xFFFF, sum = 0
3327 13:58:39.782157 3, 0xFFFF, sum = 0
3328 13:58:39.782255 4, 0xFFFF, sum = 0
3329 13:58:39.785369 5, 0xFFFF, sum = 0
3330 13:58:39.785472 6, 0xFFFF, sum = 0
3331 13:58:39.788863 7, 0xFFFF, sum = 0
3332 13:58:39.788962 8, 0xFFFF, sum = 0
3333 13:58:39.792318 9, 0xFFFF, sum = 0
3334 13:58:39.792419 10, 0xFFFF, sum = 0
3335 13:58:39.795809 11, 0xFFFF, sum = 0
3336 13:58:39.795884 12, 0x0, sum = 1
3337 13:58:39.798972 13, 0x0, sum = 2
3338 13:58:39.799075 14, 0x0, sum = 3
3339 13:58:39.802130 15, 0x0, sum = 4
3340 13:58:39.802233 best_step = 13
3341 13:58:39.802322
3342 13:58:39.802410 ==
3343 13:58:39.805674 Dram Type= 6, Freq= 0, CH_1, rank 0
3344 13:58:39.809178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3345 13:58:39.812400 ==
3346 13:58:39.812497 RX Vref Scan: 1
3347 13:58:39.812585
3348 13:58:39.815901 Set Vref Range= 32 -> 127
3349 13:58:39.816025
3350 13:58:39.818810 RX Vref 32 -> 127, step: 1
3351 13:58:39.818903
3352 13:58:39.818991 RX Delay -21 -> 252, step: 4
3353 13:58:39.819079
3354 13:58:39.822199 Set Vref, RX VrefLevel [Byte0]: 32
3355 13:58:39.825525 [Byte1]: 32
3356 13:58:39.829800
3357 13:58:39.829901 Set Vref, RX VrefLevel [Byte0]: 33
3358 13:58:39.833158 [Byte1]: 33
3359 13:58:39.837924
3360 13:58:39.838026 Set Vref, RX VrefLevel [Byte0]: 34
3361 13:58:39.844275 [Byte1]: 34
3362 13:58:39.844389
3363 13:58:39.847687 Set Vref, RX VrefLevel [Byte0]: 35
3364 13:58:39.851428 [Byte1]: 35
3365 13:58:39.851527
3366 13:58:39.853970 Set Vref, RX VrefLevel [Byte0]: 36
3367 13:58:39.857757 [Byte1]: 36
3368 13:58:39.861926
3369 13:58:39.862025 Set Vref, RX VrefLevel [Byte0]: 37
3370 13:58:39.865168 [Byte1]: 37
3371 13:58:39.869206
3372 13:58:39.869306 Set Vref, RX VrefLevel [Byte0]: 38
3373 13:58:39.873051 [Byte1]: 38
3374 13:58:39.877038
3375 13:58:39.877114 Set Vref, RX VrefLevel [Byte0]: 39
3376 13:58:39.880506 [Byte1]: 39
3377 13:58:39.885222
3378 13:58:39.885297 Set Vref, RX VrefLevel [Byte0]: 40
3379 13:58:39.888583 [Byte1]: 40
3380 13:58:39.893335
3381 13:58:39.893413 Set Vref, RX VrefLevel [Byte0]: 41
3382 13:58:39.896299 [Byte1]: 41
3383 13:58:39.900991
3384 13:58:39.901091 Set Vref, RX VrefLevel [Byte0]: 42
3385 13:58:39.904855 [Byte1]: 42
3386 13:58:39.908978
3387 13:58:39.909065 Set Vref, RX VrefLevel [Byte0]: 43
3388 13:58:39.912888 [Byte1]: 43
3389 13:58:39.917008
3390 13:58:39.917086 Set Vref, RX VrefLevel [Byte0]: 44
3391 13:58:39.920168 [Byte1]: 44
3392 13:58:39.925043
3393 13:58:39.925119 Set Vref, RX VrefLevel [Byte0]: 45
3394 13:58:39.928213 [Byte1]: 45
3395 13:58:39.932543
3396 13:58:39.932642 Set Vref, RX VrefLevel [Byte0]: 46
3397 13:58:39.936631 [Byte1]: 46
3398 13:58:39.940645
3399 13:58:39.940762 Set Vref, RX VrefLevel [Byte0]: 47
3400 13:58:39.943680 [Byte1]: 47
3401 13:58:39.948310
3402 13:58:39.948399 Set Vref, RX VrefLevel [Byte0]: 48
3403 13:58:39.952066 [Byte1]: 48
3404 13:58:39.956854
3405 13:58:39.956963 Set Vref, RX VrefLevel [Byte0]: 49
3406 13:58:39.959880 [Byte1]: 49
3407 13:58:39.964389
3408 13:58:39.964487 Set Vref, RX VrefLevel [Byte0]: 50
3409 13:58:39.967853 [Byte1]: 50
3410 13:58:39.972515
3411 13:58:39.972619 Set Vref, RX VrefLevel [Byte0]: 51
3412 13:58:39.975383 [Byte1]: 51
3413 13:58:39.980030
3414 13:58:39.980126 Set Vref, RX VrefLevel [Byte0]: 52
3415 13:58:39.983507 [Byte1]: 52
3416 13:58:39.988021
3417 13:58:39.988093 Set Vref, RX VrefLevel [Byte0]: 53
3418 13:58:39.991426 [Byte1]: 53
3419 13:58:39.996260
3420 13:58:39.996365 Set Vref, RX VrefLevel [Byte0]: 54
3421 13:58:39.999225 [Byte1]: 54
3422 13:58:40.003754
3423 13:58:40.003856 Set Vref, RX VrefLevel [Byte0]: 55
3424 13:58:40.007058 [Byte1]: 55
3425 13:58:40.012207
3426 13:58:40.012312 Set Vref, RX VrefLevel [Byte0]: 56
3427 13:58:40.015158 [Byte1]: 56
3428 13:58:40.019704
3429 13:58:40.019801 Set Vref, RX VrefLevel [Byte0]: 57
3430 13:58:40.022803 [Byte1]: 57
3431 13:58:40.028002
3432 13:58:40.028080 Set Vref, RX VrefLevel [Byte0]: 58
3433 13:58:40.031008 [Byte1]: 58
3434 13:58:40.035925
3435 13:58:40.035998 Set Vref, RX VrefLevel [Byte0]: 59
3436 13:58:40.038958 [Byte1]: 59
3437 13:58:40.043892
3438 13:58:40.043976 Set Vref, RX VrefLevel [Byte0]: 60
3439 13:58:40.046761 [Byte1]: 60
3440 13:58:40.051587
3441 13:58:40.051685 Set Vref, RX VrefLevel [Byte0]: 61
3442 13:58:40.055164 [Byte1]: 61
3443 13:58:40.059425
3444 13:58:40.059516 Set Vref, RX VrefLevel [Byte0]: 62
3445 13:58:40.062588 [Byte1]: 62
3446 13:58:40.067197
3447 13:58:40.067296 Set Vref, RX VrefLevel [Byte0]: 63
3448 13:58:40.070439 [Byte1]: 63
3449 13:58:40.075404
3450 13:58:40.075513 Set Vref, RX VrefLevel [Byte0]: 64
3451 13:58:40.078518 [Byte1]: 64
3452 13:58:40.082888
3453 13:58:40.083002 Set Vref, RX VrefLevel [Byte0]: 65
3454 13:58:40.086415 [Byte1]: 65
3455 13:58:40.091536
3456 13:58:40.091637 Set Vref, RX VrefLevel [Byte0]: 66
3457 13:58:40.094527 [Byte1]: 66
3458 13:58:40.098856
3459 13:58:40.098959 Set Vref, RX VrefLevel [Byte0]: 67
3460 13:58:40.102378 [Byte1]: 67
3461 13:58:40.107076
3462 13:58:40.107179 Set Vref, RX VrefLevel [Byte0]: 68
3463 13:58:40.110104 [Byte1]: 68
3464 13:58:40.115235
3465 13:58:40.115335 Set Vref, RX VrefLevel [Byte0]: 69
3466 13:58:40.118031 [Byte1]: 69
3467 13:58:40.122495
3468 13:58:40.122597 Set Vref, RX VrefLevel [Byte0]: 70
3469 13:58:40.126200 [Byte1]: 70
3470 13:58:40.130741
3471 13:58:40.130846 Final RX Vref Byte 0 = 52 to rank0
3472 13:58:40.133933 Final RX Vref Byte 1 = 53 to rank0
3473 13:58:40.137248 Final RX Vref Byte 0 = 52 to rank1
3474 13:58:40.140581 Final RX Vref Byte 1 = 53 to rank1==
3475 13:58:40.143990 Dram Type= 6, Freq= 0, CH_1, rank 0
3476 13:58:40.147626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 13:58:40.150702 ==
3478 13:58:40.150802 DQS Delay:
3479 13:58:40.150891 DQS0 = 0, DQS1 = 0
3480 13:58:40.154457 DQM Delay:
3481 13:58:40.154565 DQM0 = 115, DQM1 = 109
3482 13:58:40.157737 DQ Delay:
3483 13:58:40.161150 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =114
3484 13:58:40.164201 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =112
3485 13:58:40.167579 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3486 13:58:40.170890 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =114
3487 13:58:40.171002
3488 13:58:40.171094
3489 13:58:40.177827 [DQSOSCAuto] RK0, (LSB)MR18= 0xe3, (MSB)MR19= 0x403, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3490 13:58:40.181282 CH1 RK0: MR19=403, MR18=E3
3491 13:58:40.187790 CH1_RK0: MR19=0x403, MR18=0xE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3492 13:58:40.187896
3493 13:58:40.191088 ----->DramcWriteLeveling(PI) begin...
3494 13:58:40.191190 ==
3495 13:58:40.194812 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 13:58:40.197982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 13:58:40.198067 ==
3498 13:58:40.201294 Write leveling (Byte 0): 25 => 25
3499 13:58:40.204663 Write leveling (Byte 1): 31 => 31
3500 13:58:40.208018 DramcWriteLeveling(PI) end<-----
3501 13:58:40.208119
3502 13:58:40.208211 ==
3503 13:58:40.211717 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 13:58:40.214965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 13:58:40.215114 ==
3506 13:58:40.218496 [Gating] SW mode calibration
3507 13:58:40.225286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3508 13:58:40.231435 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3509 13:58:40.235231 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3510 13:58:40.238405 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 13:58:40.244970 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 13:58:40.248757 0 15 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
3513 13:58:40.251742 0 15 16 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
3514 13:58:40.258885 0 15 20 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 0)
3515 13:58:40.262002 0 15 24 | B1->B0 | 3434 2525 | 0 0 | (0 0) (1 0)
3516 13:58:40.265506 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
3517 13:58:40.268422 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 13:58:40.275611 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 13:58:40.278883 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 13:58:40.282277 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 13:58:40.288628 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3522 13:58:40.292107 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3523 13:58:40.295428 1 0 24 | B1->B0 | 2626 4040 | 0 0 | (0 0) (0 0)
3524 13:58:40.302522 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3525 13:58:40.305868 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 13:58:40.308800 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 13:58:40.316097 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 13:58:40.318964 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 13:58:40.322763 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 13:58:40.326704 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3531 13:58:40.332233 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3532 13:58:40.335675 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3533 13:58:40.339273 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 13:58:40.345780 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 13:58:40.348880 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 13:58:40.352317 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 13:58:40.359160 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 13:58:40.362341 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 13:58:40.365806 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 13:58:40.372266 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 13:58:40.375630 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 13:58:40.378906 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 13:58:40.385754 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 13:58:40.389056 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 13:58:40.393063 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 13:58:40.399091 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3547 13:58:40.402663 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3548 13:58:40.406137 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3549 13:58:40.409241 Total UI for P1: 0, mck2ui 16
3550 13:58:40.413015 best dqsien dly found for B0: ( 1, 3, 22)
3551 13:58:40.415836 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 13:58:40.419423 Total UI for P1: 0, mck2ui 16
3553 13:58:40.422709 best dqsien dly found for B1: ( 1, 3, 28)
3554 13:58:40.425901 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3555 13:58:40.429380 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3556 13:58:40.429447
3557 13:58:40.435827 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3558 13:58:40.439475 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3559 13:58:40.442685 [Gating] SW calibration Done
3560 13:58:40.442781 ==
3561 13:58:40.446141 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 13:58:40.449385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 13:58:40.449453 ==
3564 13:58:40.449512 RX Vref Scan: 0
3565 13:58:40.449577
3566 13:58:40.452807 RX Vref 0 -> 0, step: 1
3567 13:58:40.452901
3568 13:58:40.456050 RX Delay -40 -> 252, step: 8
3569 13:58:40.459692 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3570 13:58:40.462707 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3571 13:58:40.466000 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3572 13:58:40.472895 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3573 13:58:40.476002 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3574 13:58:40.479394 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3575 13:58:40.482609 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3576 13:58:40.486249 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3577 13:58:40.492853 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3578 13:58:40.496092 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3579 13:58:40.499942 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3580 13:58:40.503155 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3581 13:58:40.506575 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3582 13:58:40.512722 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3583 13:58:40.516318 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3584 13:58:40.519628 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3585 13:58:40.519728 ==
3586 13:58:40.522741 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 13:58:40.526222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 13:58:40.526291 ==
3589 13:58:40.529427 DQS Delay:
3590 13:58:40.529498 DQS0 = 0, DQS1 = 0
3591 13:58:40.532951 DQM Delay:
3592 13:58:40.533019 DQM0 = 113, DQM1 = 110
3593 13:58:40.533079 DQ Delay:
3594 13:58:40.539292 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3595 13:58:40.542790 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3596 13:58:40.546052 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3597 13:58:40.549655 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3598 13:58:40.549729
3599 13:58:40.549795
3600 13:58:40.549854 ==
3601 13:58:40.552819 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 13:58:40.556324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 13:58:40.556422 ==
3604 13:58:40.556509
3605 13:58:40.556593
3606 13:58:40.559685 TX Vref Scan disable
3607 13:58:40.562682 == TX Byte 0 ==
3608 13:58:40.566362 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3609 13:58:40.569754 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3610 13:58:40.573003 == TX Byte 1 ==
3611 13:58:40.576264 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3612 13:58:40.579362 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3613 13:58:40.579465 ==
3614 13:58:40.582875 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 13:58:40.586096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 13:58:40.586195 ==
3617 13:58:40.599659 TX Vref=22, minBit 7, minWin=25, winSum=411
3618 13:58:40.603738 TX Vref=24, minBit 15, minWin=25, winSum=421
3619 13:58:40.606161 TX Vref=26, minBit 15, minWin=25, winSum=428
3620 13:58:40.609720 TX Vref=28, minBit 13, minWin=25, winSum=427
3621 13:58:40.613108 TX Vref=30, minBit 12, minWin=26, winSum=431
3622 13:58:40.619749 TX Vref=32, minBit 14, minWin=26, winSum=431
3623 13:58:40.623305 [TxChooseVref] Worse bit 12, Min win 26, Win sum 431, Final Vref 30
3624 13:58:40.623412
3625 13:58:40.626584 Final TX Range 1 Vref 30
3626 13:58:40.626682
3627 13:58:40.626771 ==
3628 13:58:40.629532 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 13:58:40.632908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 13:58:40.636282 ==
3631 13:58:40.636384
3632 13:58:40.636487
3633 13:58:40.636577 TX Vref Scan disable
3634 13:58:40.639904 == TX Byte 0 ==
3635 13:58:40.643190 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3636 13:58:40.646654 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3637 13:58:40.649872 == TX Byte 1 ==
3638 13:58:40.653023 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3639 13:58:40.656755 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3640 13:58:40.659946
3641 13:58:40.660021 [DATLAT]
3642 13:58:40.660083 Freq=1200, CH1 RK1
3643 13:58:40.660142
3644 13:58:40.663157 DATLAT Default: 0xd
3645 13:58:40.663232 0, 0xFFFF, sum = 0
3646 13:58:40.666857 1, 0xFFFF, sum = 0
3647 13:58:40.666958 2, 0xFFFF, sum = 0
3648 13:58:40.669894 3, 0xFFFF, sum = 0
3649 13:58:40.669967 4, 0xFFFF, sum = 0
3650 13:58:40.673297 5, 0xFFFF, sum = 0
3651 13:58:40.676566 6, 0xFFFF, sum = 0
3652 13:58:40.676688 7, 0xFFFF, sum = 0
3653 13:58:40.680487 8, 0xFFFF, sum = 0
3654 13:58:40.680588 9, 0xFFFF, sum = 0
3655 13:58:40.683763 10, 0xFFFF, sum = 0
3656 13:58:40.683863 11, 0xFFFF, sum = 0
3657 13:58:40.686476 12, 0x0, sum = 1
3658 13:58:40.686575 13, 0x0, sum = 2
3659 13:58:40.690364 14, 0x0, sum = 3
3660 13:58:40.690463 15, 0x0, sum = 4
3661 13:58:40.690560 best_step = 13
3662 13:58:40.690651
3663 13:58:40.693400 ==
3664 13:58:40.696553 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 13:58:40.700156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 13:58:40.700264 ==
3667 13:58:40.700355 RX Vref Scan: 0
3668 13:58:40.700440
3669 13:58:40.703237 RX Vref 0 -> 0, step: 1
3670 13:58:40.703334
3671 13:58:40.706746 RX Delay -21 -> 252, step: 4
3672 13:58:40.710146 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3673 13:58:40.713339 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3674 13:58:40.720156 iDelay=195, Bit 2, Center 104 (39 ~ 170) 132
3675 13:58:40.723394 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3676 13:58:40.726770 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3677 13:58:40.730116 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3678 13:58:40.733534 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3679 13:58:40.740469 iDelay=195, Bit 7, Center 112 (47 ~ 178) 132
3680 13:58:40.743630 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3681 13:58:40.746684 iDelay=195, Bit 9, Center 98 (35 ~ 162) 128
3682 13:58:40.750341 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3683 13:58:40.753549 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3684 13:58:40.760403 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3685 13:58:40.763500 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3686 13:58:40.767037 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3687 13:58:40.770763 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3688 13:58:40.770868 ==
3689 13:58:40.773624 Dram Type= 6, Freq= 0, CH_1, rank 1
3690 13:58:40.780189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3691 13:58:40.780289 ==
3692 13:58:40.780391 DQS Delay:
3693 13:58:40.780481 DQS0 = 0, DQS1 = 0
3694 13:58:40.783752 DQM Delay:
3695 13:58:40.783849 DQM0 = 114, DQM1 = 109
3696 13:58:40.787204 DQ Delay:
3697 13:58:40.790275 DQ0 =114, DQ1 =110, DQ2 =104, DQ3 =112
3698 13:58:40.793486 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3699 13:58:40.797118 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =104
3700 13:58:40.800294 DQ12 =114, DQ13 =118, DQ14 =116, DQ15 =116
3701 13:58:40.800392
3702 13:58:40.800491
3703 13:58:40.806907 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa01, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3704 13:58:40.810610 CH1 RK1: MR19=304, MR18=FA01
3705 13:58:40.816882 CH1_RK1: MR19=0x304, MR18=0xFA01, DQSOSC=409, MR23=63, INC=39, DEC=26
3706 13:58:40.820355 [RxdqsGatingPostProcess] freq 1200
3707 13:58:40.827042 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3708 13:58:40.830368 best DQS0 dly(2T, 0.5T) = (0, 11)
3709 13:58:40.830443 best DQS1 dly(2T, 0.5T) = (0, 11)
3710 13:58:40.834246 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3711 13:58:40.837093 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3712 13:58:40.840555 best DQS0 dly(2T, 0.5T) = (0, 11)
3713 13:58:40.843862 best DQS1 dly(2T, 0.5T) = (0, 11)
3714 13:58:40.847089 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3715 13:58:40.850831 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3716 13:58:40.853857 Pre-setting of DQS Precalculation
3717 13:58:40.860815 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3718 13:58:40.867123 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3719 13:58:40.874041 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3720 13:58:40.874121
3721 13:58:40.874190
3722 13:58:40.877405 [Calibration Summary] 2400 Mbps
3723 13:58:40.877482 CH 0, Rank 0
3724 13:58:40.880780 SW Impedance : PASS
3725 13:58:40.880854 DUTY Scan : NO K
3726 13:58:40.884542 ZQ Calibration : PASS
3727 13:58:40.887394 Jitter Meter : NO K
3728 13:58:40.887493 CBT Training : PASS
3729 13:58:40.891023 Write leveling : PASS
3730 13:58:40.893914 RX DQS gating : PASS
3731 13:58:40.894013 RX DQ/DQS(RDDQC) : PASS
3732 13:58:40.897828 TX DQ/DQS : PASS
3733 13:58:40.900568 RX DATLAT : PASS
3734 13:58:40.900675 RX DQ/DQS(Engine): PASS
3735 13:58:40.904096 TX OE : NO K
3736 13:58:40.904193 All Pass.
3737 13:58:40.904280
3738 13:58:40.907568 CH 0, Rank 1
3739 13:58:40.907664 SW Impedance : PASS
3740 13:58:40.910689 DUTY Scan : NO K
3741 13:58:40.913956 ZQ Calibration : PASS
3742 13:58:40.914061 Jitter Meter : NO K
3743 13:58:40.917300 CBT Training : PASS
3744 13:58:40.917403 Write leveling : PASS
3745 13:58:40.920977 RX DQS gating : PASS
3746 13:58:40.924811 RX DQ/DQS(RDDQC) : PASS
3747 13:58:40.924912 TX DQ/DQS : PASS
3748 13:58:40.927383 RX DATLAT : PASS
3749 13:58:40.930910 RX DQ/DQS(Engine): PASS
3750 13:58:40.931011 TX OE : NO K
3751 13:58:40.934321 All Pass.
3752 13:58:40.934419
3753 13:58:40.934507 CH 1, Rank 0
3754 13:58:40.937879 SW Impedance : PASS
3755 13:58:40.937974 DUTY Scan : NO K
3756 13:58:40.941187 ZQ Calibration : PASS
3757 13:58:40.944164 Jitter Meter : NO K
3758 13:58:40.944271 CBT Training : PASS
3759 13:58:40.947344 Write leveling : PASS
3760 13:58:40.951181 RX DQS gating : PASS
3761 13:58:40.951282 RX DQ/DQS(RDDQC) : PASS
3762 13:58:40.954208 TX DQ/DQS : PASS
3763 13:58:40.957428 RX DATLAT : PASS
3764 13:58:40.957570 RX DQ/DQS(Engine): PASS
3765 13:58:40.960758 TX OE : NO K
3766 13:58:40.960855 All Pass.
3767 13:58:40.960947
3768 13:58:40.964045 CH 1, Rank 1
3769 13:58:40.964143 SW Impedance : PASS
3770 13:58:40.967192 DUTY Scan : NO K
3771 13:58:40.970334 ZQ Calibration : PASS
3772 13:58:40.970438 Jitter Meter : NO K
3773 13:58:40.973946 CBT Training : PASS
3774 13:58:40.974047 Write leveling : PASS
3775 13:58:40.977244 RX DQS gating : PASS
3776 13:58:40.980655 RX DQ/DQS(RDDQC) : PASS
3777 13:58:40.980794 TX DQ/DQS : PASS
3778 13:58:40.984019 RX DATLAT : PASS
3779 13:58:40.987830 RX DQ/DQS(Engine): PASS
3780 13:58:40.987936 TX OE : NO K
3781 13:58:40.990408 All Pass.
3782 13:58:40.990508
3783 13:58:40.990597 DramC Write-DBI off
3784 13:58:40.993990 PER_BANK_REFRESH: Hybrid Mode
3785 13:58:40.994094 TX_TRACKING: ON
3786 13:58:41.004141 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3787 13:58:41.007072 [FAST_K] Save calibration result to emmc
3788 13:58:41.010494 dramc_set_vcore_voltage set vcore to 650000
3789 13:58:41.013640 Read voltage for 600, 5
3790 13:58:41.013740 Vio18 = 0
3791 13:58:41.017112 Vcore = 650000
3792 13:58:41.017214 Vdram = 0
3793 13:58:41.017304 Vddq = 0
3794 13:58:41.020603 Vmddr = 0
3795 13:58:41.023878 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3796 13:58:41.030597 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3797 13:58:41.030697 MEM_TYPE=3, freq_sel=19
3798 13:58:41.033850 sv_algorithm_assistance_LP4_1600
3799 13:58:41.040549 ============ PULL DRAM RESETB DOWN ============
3800 13:58:41.043808 ========== PULL DRAM RESETB DOWN end =========
3801 13:58:41.047009 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3802 13:58:41.050376 ===================================
3803 13:58:41.053631 LPDDR4 DRAM CONFIGURATION
3804 13:58:41.057010 ===================================
3805 13:58:41.057112 EX_ROW_EN[0] = 0x0
3806 13:58:41.060303 EX_ROW_EN[1] = 0x0
3807 13:58:41.063574 LP4Y_EN = 0x0
3808 13:58:41.063670 WORK_FSP = 0x0
3809 13:58:41.067120 WL = 0x2
3810 13:58:41.067216 RL = 0x2
3811 13:58:41.070458 BL = 0x2
3812 13:58:41.070567 RPST = 0x0
3813 13:58:41.073793 RD_PRE = 0x0
3814 13:58:41.073894 WR_PRE = 0x1
3815 13:58:41.076901 WR_PST = 0x0
3816 13:58:41.076999 DBI_WR = 0x0
3817 13:58:41.080411 DBI_RD = 0x0
3818 13:58:41.080519 OTF = 0x1
3819 13:58:41.083540 ===================================
3820 13:58:41.086973 ===================================
3821 13:58:41.090372 ANA top config
3822 13:58:41.093798 ===================================
3823 13:58:41.093898 DLL_ASYNC_EN = 0
3824 13:58:41.097118 ALL_SLAVE_EN = 1
3825 13:58:41.100627 NEW_RANK_MODE = 1
3826 13:58:41.103738 DLL_IDLE_MODE = 1
3827 13:58:41.103814 LP45_APHY_COMB_EN = 1
3828 13:58:41.107113 TX_ODT_DIS = 1
3829 13:58:41.110681 NEW_8X_MODE = 1
3830 13:58:41.113891 ===================================
3831 13:58:41.117246 ===================================
3832 13:58:41.120622 data_rate = 1200
3833 13:58:41.124013 CKR = 1
3834 13:58:41.124112 DQ_P2S_RATIO = 8
3835 13:58:41.127194 ===================================
3836 13:58:41.130653 CA_P2S_RATIO = 8
3837 13:58:41.134224 DQ_CA_OPEN = 0
3838 13:58:41.137128 DQ_SEMI_OPEN = 0
3839 13:58:41.140432 CA_SEMI_OPEN = 0
3840 13:58:41.144210 CA_FULL_RATE = 0
3841 13:58:41.144306 DQ_CKDIV4_EN = 1
3842 13:58:41.147358 CA_CKDIV4_EN = 1
3843 13:58:41.150917 CA_PREDIV_EN = 0
3844 13:58:41.154014 PH8_DLY = 0
3845 13:58:41.157605 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3846 13:58:41.157678 DQ_AAMCK_DIV = 4
3847 13:58:41.160784 CA_AAMCK_DIV = 4
3848 13:58:41.163999 CA_ADMCK_DIV = 4
3849 13:58:41.167746 DQ_TRACK_CA_EN = 0
3850 13:58:41.170984 CA_PICK = 600
3851 13:58:41.174205 CA_MCKIO = 600
3852 13:58:41.177270 MCKIO_SEMI = 0
3853 13:58:41.177366 PLL_FREQ = 2288
3854 13:58:41.181320 DQ_UI_PI_RATIO = 32
3855 13:58:41.184385 CA_UI_PI_RATIO = 0
3856 13:58:41.187584 ===================================
3857 13:58:41.191144 ===================================
3858 13:58:41.194543 memory_type:LPDDR4
3859 13:58:41.194640 GP_NUM : 10
3860 13:58:41.197660 SRAM_EN : 1
3861 13:58:41.201085 MD32_EN : 0
3862 13:58:41.204515 ===================================
3863 13:58:41.204614 [ANA_INIT] >>>>>>>>>>>>>>
3864 13:58:41.207411 <<<<<< [CONFIGURE PHASE]: ANA_TX
3865 13:58:41.210724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3866 13:58:41.214410 ===================================
3867 13:58:41.217821 data_rate = 1200,PCW = 0X5800
3868 13:58:41.220847 ===================================
3869 13:58:41.224602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3870 13:58:41.230897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3871 13:58:41.234216 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3872 13:58:41.240920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3873 13:58:41.244849 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3874 13:58:41.248302 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3875 13:58:41.248384 [ANA_INIT] flow start
3876 13:58:41.251499 [ANA_INIT] PLL >>>>>>>>
3877 13:58:41.254344 [ANA_INIT] PLL <<<<<<<<
3878 13:58:41.254441 [ANA_INIT] MIDPI >>>>>>>>
3879 13:58:41.257865 [ANA_INIT] MIDPI <<<<<<<<
3880 13:58:41.261201 [ANA_INIT] DLL >>>>>>>>
3881 13:58:41.261273 [ANA_INIT] flow end
3882 13:58:41.267738 ============ LP4 DIFF to SE enter ============
3883 13:58:41.271351 ============ LP4 DIFF to SE exit ============
3884 13:58:41.274759 [ANA_INIT] <<<<<<<<<<<<<
3885 13:58:41.277896 [Flow] Enable top DCM control >>>>>
3886 13:58:41.280888 [Flow] Enable top DCM control <<<<<
3887 13:58:41.280989 Enable DLL master slave shuffle
3888 13:58:41.287613 ==============================================================
3889 13:58:41.290980 Gating Mode config
3890 13:58:41.294413 ==============================================================
3891 13:58:41.297846 Config description:
3892 13:58:41.307787 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3893 13:58:41.314559 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3894 13:58:41.317769 SELPH_MODE 0: By rank 1: By Phase
3895 13:58:41.324463 ==============================================================
3896 13:58:41.327856 GAT_TRACK_EN = 1
3897 13:58:41.331222 RX_GATING_MODE = 2
3898 13:58:41.331296 RX_GATING_TRACK_MODE = 2
3899 13:58:41.334541 SELPH_MODE = 1
3900 13:58:41.338300 PICG_EARLY_EN = 1
3901 13:58:41.341288 VALID_LAT_VALUE = 1
3902 13:58:41.347879 ==============================================================
3903 13:58:41.351166 Enter into Gating configuration >>>>
3904 13:58:41.354617 Exit from Gating configuration <<<<
3905 13:58:41.358199 Enter into DVFS_PRE_config >>>>>
3906 13:58:41.367966 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3907 13:58:41.371495 Exit from DVFS_PRE_config <<<<<
3908 13:58:41.375212 Enter into PICG configuration >>>>
3909 13:58:41.378635 Exit from PICG configuration <<<<
3910 13:58:41.381240 [RX_INPUT] configuration >>>>>
3911 13:58:41.384942 [RX_INPUT] configuration <<<<<
3912 13:58:41.388017 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3913 13:58:41.394778 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3914 13:58:41.401939 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3915 13:58:41.404885 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3916 13:58:41.411370 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3917 13:58:41.418408 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3918 13:58:41.421658 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3919 13:58:41.424987 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3920 13:58:41.431691 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3921 13:58:41.435309 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3922 13:58:41.438665 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3923 13:58:41.445040 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3924 13:58:41.445140 ===================================
3925 13:58:41.448214 LPDDR4 DRAM CONFIGURATION
3926 13:58:41.451825 ===================================
3927 13:58:41.454856 EX_ROW_EN[0] = 0x0
3928 13:58:41.454955 EX_ROW_EN[1] = 0x0
3929 13:58:41.458309 LP4Y_EN = 0x0
3930 13:58:41.458383 WORK_FSP = 0x0
3931 13:58:41.461672 WL = 0x2
3932 13:58:41.461770 RL = 0x2
3933 13:58:41.464964 BL = 0x2
3934 13:58:41.465054 RPST = 0x0
3935 13:58:41.468652 RD_PRE = 0x0
3936 13:58:41.471586 WR_PRE = 0x1
3937 13:58:41.471696 WR_PST = 0x0
3938 13:58:41.475094 DBI_WR = 0x0
3939 13:58:41.475197 DBI_RD = 0x0
3940 13:58:41.478353 OTF = 0x1
3941 13:58:41.481932 ===================================
3942 13:58:41.485184 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3943 13:58:41.488701 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3944 13:58:41.491764 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3945 13:58:41.495091 ===================================
3946 13:58:41.498568 LPDDR4 DRAM CONFIGURATION
3947 13:58:41.501916 ===================================
3948 13:58:41.505021 EX_ROW_EN[0] = 0x10
3949 13:58:41.505125 EX_ROW_EN[1] = 0x0
3950 13:58:41.508583 LP4Y_EN = 0x0
3951 13:58:41.508703 WORK_FSP = 0x0
3952 13:58:41.512076 WL = 0x2
3953 13:58:41.512171 RL = 0x2
3954 13:58:41.515322 BL = 0x2
3955 13:58:41.515394 RPST = 0x0
3956 13:58:41.518411 RD_PRE = 0x0
3957 13:58:41.518508 WR_PRE = 0x1
3958 13:58:41.521861 WR_PST = 0x0
3959 13:58:41.521932 DBI_WR = 0x0
3960 13:58:41.525516 DBI_RD = 0x0
3961 13:58:41.525590 OTF = 0x1
3962 13:58:41.528790 ===================================
3963 13:58:41.535366 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3964 13:58:41.539882 nWR fixed to 30
3965 13:58:41.543024 [ModeRegInit_LP4] CH0 RK0
3966 13:58:41.543119 [ModeRegInit_LP4] CH0 RK1
3967 13:58:41.546654 [ModeRegInit_LP4] CH1 RK0
3968 13:58:41.549703 [ModeRegInit_LP4] CH1 RK1
3969 13:58:41.549783 match AC timing 17
3970 13:58:41.556532 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3971 13:58:41.559929 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3972 13:58:41.563094 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3973 13:58:41.569801 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3974 13:58:41.573173 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3975 13:58:41.573251 ==
3976 13:58:41.577102 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 13:58:41.579720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 13:58:41.579816 ==
3979 13:58:41.587146 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3980 13:58:41.593054 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3981 13:58:41.596599 [CA 0] Center 36 (6~67) winsize 62
3982 13:58:41.599897 [CA 1] Center 36 (6~66) winsize 61
3983 13:58:41.603382 [CA 2] Center 34 (4~65) winsize 62
3984 13:58:41.606822 [CA 3] Center 34 (4~65) winsize 62
3985 13:58:41.610416 [CA 4] Center 33 (3~64) winsize 62
3986 13:58:41.613349 [CA 5] Center 33 (3~64) winsize 62
3987 13:58:41.613454
3988 13:58:41.616852 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3989 13:58:41.616925
3990 13:58:41.620338 [CATrainingPosCal] consider 1 rank data
3991 13:58:41.623281 u2DelayCellTimex100 = 270/100 ps
3992 13:58:41.626847 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3993 13:58:41.630188 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3994 13:58:41.633780 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3995 13:58:41.637213 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 13:58:41.640219 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3997 13:58:41.643612 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 13:58:41.643713
3999 13:58:41.646922 CA PerBit enable=1, Macro0, CA PI delay=33
4000 13:58:41.646995
4001 13:58:41.650579 [CBTSetCACLKResult] CA Dly = 33
4002 13:58:41.653806 CS Dly: 5 (0~36)
4003 13:58:41.653907 ==
4004 13:58:41.657155 Dram Type= 6, Freq= 0, CH_0, rank 1
4005 13:58:41.660115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 13:58:41.660196 ==
4007 13:58:41.666980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4008 13:58:41.673729 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4009 13:58:41.677159 [CA 0] Center 36 (6~66) winsize 61
4010 13:58:41.680129 [CA 1] Center 36 (6~66) winsize 61
4011 13:58:41.683994 [CA 2] Center 34 (4~65) winsize 62
4012 13:58:41.686800 [CA 3] Center 34 (4~64) winsize 61
4013 13:58:41.690528 [CA 4] Center 33 (3~64) winsize 62
4014 13:58:41.693541 [CA 5] Center 33 (3~64) winsize 62
4015 13:58:41.693640
4016 13:58:41.696915 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4017 13:58:41.697026
4018 13:58:41.700574 [CATrainingPosCal] consider 2 rank data
4019 13:58:41.703750 u2DelayCellTimex100 = 270/100 ps
4020 13:58:41.707375 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4021 13:58:41.710521 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4022 13:58:41.714011 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4023 13:58:41.717238 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4024 13:58:41.720266 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4025 13:58:41.723676 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 13:58:41.723777
4027 13:58:41.727698 CA PerBit enable=1, Macro0, CA PI delay=33
4028 13:58:41.727820
4029 13:58:41.730361 [CBTSetCACLKResult] CA Dly = 33
4030 13:58:41.733980 CS Dly: 5 (0~36)
4031 13:58:41.734078
4032 13:58:41.737473 ----->DramcWriteLeveling(PI) begin...
4033 13:58:41.737552 ==
4034 13:58:41.740917 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 13:58:41.743954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 13:58:41.744054 ==
4037 13:58:41.747013 Write leveling (Byte 0): 32 => 32
4038 13:58:41.750436 Write leveling (Byte 1): 31 => 31
4039 13:58:41.753787 DramcWriteLeveling(PI) end<-----
4040 13:58:41.753882
4041 13:58:41.753971 ==
4042 13:58:41.757625 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 13:58:41.760556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 13:58:41.760653 ==
4045 13:58:41.764155 [Gating] SW mode calibration
4046 13:58:41.770659 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4047 13:58:41.777545 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4048 13:58:41.781054 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 13:58:41.784301 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 13:58:41.790800 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 13:58:41.794263 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 13:58:41.797630 0 9 16 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (0 1)
4053 13:58:41.804342 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 13:58:41.807615 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 13:58:41.811111 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 13:58:41.817783 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 13:58:41.821309 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 13:58:41.824677 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 13:58:41.830730 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4060 13:58:41.834339 0 10 16 | B1->B0 | 3131 4141 | 0 0 | (0 0) (0 0)
4061 13:58:41.837758 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 13:58:41.840967 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 13:58:41.847335 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 13:58:41.850635 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 13:58:41.854394 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 13:58:41.860885 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 13:58:41.864219 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 13:58:41.867406 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4069 13:58:41.874427 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 13:58:41.878416 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 13:58:41.881092 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 13:58:41.887748 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 13:58:41.891358 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 13:58:41.894828 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 13:58:41.901817 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 13:58:41.904265 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 13:58:41.908067 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 13:58:41.914645 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 13:58:41.918484 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 13:58:41.921124 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 13:58:41.924591 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 13:58:41.931390 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 13:58:41.934526 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 13:58:41.938176 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 13:58:41.941644 Total UI for P1: 0, mck2ui 16
4086 13:58:41.944645 best dqsien dly found for B0: ( 0, 13, 14)
4087 13:58:41.948152 Total UI for P1: 0, mck2ui 16
4088 13:58:41.951438 best dqsien dly found for B1: ( 0, 13, 14)
4089 13:58:41.954419 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4090 13:58:41.958341 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4091 13:58:41.958424
4092 13:58:41.964459 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4093 13:58:41.967948 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4094 13:58:41.968028 [Gating] SW calibration Done
4095 13:58:41.971593 ==
4096 13:58:41.974994 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 13:58:41.978014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 13:58:41.978136 ==
4099 13:58:41.978231 RX Vref Scan: 0
4100 13:58:41.978319
4101 13:58:41.981531 RX Vref 0 -> 0, step: 1
4102 13:58:41.981639
4103 13:58:41.984837 RX Delay -230 -> 252, step: 16
4104 13:58:41.988078 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4105 13:58:41.991396 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4106 13:58:41.998026 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4107 13:58:42.001277 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4108 13:58:42.004460 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4109 13:58:42.008305 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4110 13:58:42.011053 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4111 13:58:42.018000 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4112 13:58:42.021545 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4113 13:58:42.024542 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4114 13:58:42.027868 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4115 13:58:42.034526 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4116 13:58:42.037604 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4117 13:58:42.041073 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4118 13:58:42.044342 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4119 13:58:42.051286 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4120 13:58:42.051390 ==
4121 13:58:42.054541 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 13:58:42.057812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 13:58:42.057926 ==
4124 13:58:42.058018 DQS Delay:
4125 13:58:42.061219 DQS0 = 0, DQS1 = 0
4126 13:58:42.061340 DQM Delay:
4127 13:58:42.064585 DQM0 = 40, DQM1 = 32
4128 13:58:42.064732 DQ Delay:
4129 13:58:42.067969 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4130 13:58:42.071437 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4131 13:58:42.074582 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4132 13:58:42.077871 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4133 13:58:42.077982
4134 13:58:42.078073
4135 13:58:42.078159 ==
4136 13:58:42.081272 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 13:58:42.084538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 13:58:42.084641 ==
4139 13:58:42.084781
4140 13:58:42.084868
4141 13:58:42.088051 TX Vref Scan disable
4142 13:58:42.091257 == TX Byte 0 ==
4143 13:58:42.095111 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4144 13:58:42.098220 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4145 13:58:42.101368 == TX Byte 1 ==
4146 13:58:42.104606 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4147 13:58:42.108013 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4148 13:58:42.108127 ==
4149 13:58:42.111648 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 13:58:42.114550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 13:58:42.118144 ==
4152 13:58:42.118245
4153 13:58:42.118335
4154 13:58:42.118420 TX Vref Scan disable
4155 13:58:42.122127 == TX Byte 0 ==
4156 13:58:42.125309 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4157 13:58:42.128613 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4158 13:58:42.131873 == TX Byte 1 ==
4159 13:58:42.135386 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4160 13:58:42.138988 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4161 13:58:42.142504
4162 13:58:42.142616 [DATLAT]
4163 13:58:42.142713 Freq=600, CH0 RK0
4164 13:58:42.142789
4165 13:58:42.145297 DATLAT Default: 0x9
4166 13:58:42.145394 0, 0xFFFF, sum = 0
4167 13:58:42.148722 1, 0xFFFF, sum = 0
4168 13:58:42.148836 2, 0xFFFF, sum = 0
4169 13:58:42.152793 3, 0xFFFF, sum = 0
4170 13:58:42.152892 4, 0xFFFF, sum = 0
4171 13:58:42.155545 5, 0xFFFF, sum = 0
4172 13:58:42.155629 6, 0xFFFF, sum = 0
4173 13:58:42.158785 7, 0xFFFF, sum = 0
4174 13:58:42.158914 8, 0x0, sum = 1
4175 13:58:42.162029 9, 0x0, sum = 2
4176 13:58:42.162147 10, 0x0, sum = 3
4177 13:58:42.165314 11, 0x0, sum = 4
4178 13:58:42.165413 best_step = 9
4179 13:58:42.165509
4180 13:58:42.165584 ==
4181 13:58:42.168701 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 13:58:42.175404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 13:58:42.175504 ==
4184 13:58:42.175600 RX Vref Scan: 1
4185 13:58:42.175662
4186 13:58:42.178916 RX Vref 0 -> 0, step: 1
4187 13:58:42.178997
4188 13:58:42.182310 RX Delay -195 -> 252, step: 8
4189 13:58:42.182408
4190 13:58:42.185734 Set Vref, RX VrefLevel [Byte0]: 54
4191 13:58:42.188980 [Byte1]: 52
4192 13:58:42.189078
4193 13:58:42.192443 Final RX Vref Byte 0 = 54 to rank0
4194 13:58:42.195396 Final RX Vref Byte 1 = 52 to rank0
4195 13:58:42.199201 Final RX Vref Byte 0 = 54 to rank1
4196 13:58:42.201982 Final RX Vref Byte 1 = 52 to rank1==
4197 13:58:42.205318 Dram Type= 6, Freq= 0, CH_0, rank 0
4198 13:58:42.208847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 13:58:42.208943 ==
4200 13:58:42.211840 DQS Delay:
4201 13:58:42.211920 DQS0 = 0, DQS1 = 0
4202 13:58:42.212015 DQM Delay:
4203 13:58:42.215613 DQM0 = 42, DQM1 = 33
4204 13:58:42.215710 DQ Delay:
4205 13:58:42.218880 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4206 13:58:42.222259 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4207 13:58:42.225801 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4208 13:58:42.228799 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4209 13:58:42.228913
4210 13:58:42.229024
4211 13:58:42.238727 [DQSOSCAuto] RK0, (LSB)MR18= 0x4928, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4212 13:58:42.238826 CH0 RK0: MR19=808, MR18=4928
4213 13:58:42.245954 CH0_RK0: MR19=0x808, MR18=0x4928, DQSOSC=396, MR23=63, INC=167, DEC=111
4214 13:58:42.246052
4215 13:58:42.248848 ----->DramcWriteLeveling(PI) begin...
4216 13:58:42.248980 ==
4217 13:58:42.252114 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 13:58:42.259302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 13:58:42.259439 ==
4220 13:58:42.262485 Write leveling (Byte 0): 33 => 33
4221 13:58:42.262616 Write leveling (Byte 1): 29 => 29
4222 13:58:42.265681 DramcWriteLeveling(PI) end<-----
4223 13:58:42.265778
4224 13:58:42.269226 ==
4225 13:58:42.269332 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 13:58:42.276136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 13:58:42.276250 ==
4228 13:58:42.279335 [Gating] SW mode calibration
4229 13:58:42.286255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4230 13:58:42.289604 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4231 13:58:42.296136 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 13:58:42.298912 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 13:58:42.302468 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 13:58:42.308891 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
4235 13:58:42.312837 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
4236 13:58:42.316123 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 13:58:42.322775 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 13:58:42.325537 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 13:58:42.329352 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 13:58:42.332373 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 13:58:42.339051 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4242 13:58:42.342415 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4243 13:58:42.345779 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4244 13:58:42.352349 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 13:58:42.355816 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 13:58:42.359107 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 13:58:42.366099 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 13:58:42.369297 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 13:58:42.372450 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 13:58:42.378943 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4251 13:58:42.382447 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4252 13:58:42.385735 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4253 13:58:42.392346 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 13:58:42.395906 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 13:58:42.399154 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 13:58:42.405813 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 13:58:42.409742 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 13:58:42.412605 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 13:58:42.415994 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 13:58:42.422866 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 13:58:42.425930 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 13:58:42.429743 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 13:58:42.436005 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 13:58:42.439391 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 13:58:42.442611 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4266 13:58:42.449834 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4267 13:58:42.452913 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4268 13:58:42.456072 Total UI for P1: 0, mck2ui 16
4269 13:58:42.459335 best dqsien dly found for B0: ( 0, 13, 10)
4270 13:58:42.462763 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 13:58:42.466283 Total UI for P1: 0, mck2ui 16
4272 13:58:42.469616 best dqsien dly found for B1: ( 0, 13, 16)
4273 13:58:42.472642 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4274 13:58:42.476059 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4275 13:58:42.476191
4276 13:58:42.482677 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4277 13:58:42.486109 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4278 13:58:42.486217 [Gating] SW calibration Done
4279 13:58:42.489270 ==
4280 13:58:42.489387 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 13:58:42.496202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 13:58:42.496299 ==
4283 13:58:42.496371 RX Vref Scan: 0
4284 13:58:42.496432
4285 13:58:42.499426 RX Vref 0 -> 0, step: 1
4286 13:58:42.499533
4287 13:58:42.503125 RX Delay -230 -> 252, step: 16
4288 13:58:42.506638 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4289 13:58:42.509634 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4290 13:58:42.516397 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4291 13:58:42.519517 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4292 13:58:42.522757 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4293 13:58:42.526184 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
4294 13:58:42.530052 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4295 13:58:42.536352 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4296 13:58:42.539922 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4297 13:58:42.542766 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4298 13:58:42.546293 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4299 13:58:42.549646 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4300 13:58:42.556701 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4301 13:58:42.559736 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4302 13:58:42.562794 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4303 13:58:42.566271 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4304 13:58:42.566346 ==
4305 13:58:42.570242 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 13:58:42.576436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 13:58:42.576571 ==
4308 13:58:42.576687 DQS Delay:
4309 13:58:42.579620 DQS0 = 0, DQS1 = 0
4310 13:58:42.579698 DQM Delay:
4311 13:58:42.582995 DQM0 = 42, DQM1 = 35
4312 13:58:42.583067 DQ Delay:
4313 13:58:42.586608 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4314 13:58:42.590415 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4315 13:58:42.593002 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4316 13:58:42.596592 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4317 13:58:42.596740
4318 13:58:42.596836
4319 13:58:42.596925 ==
4320 13:58:42.600186 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 13:58:42.603142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 13:58:42.603243 ==
4323 13:58:42.603333
4324 13:58:42.603418
4325 13:58:42.606614 TX Vref Scan disable
4326 13:58:42.606712 == TX Byte 0 ==
4327 13:58:42.613739 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4328 13:58:42.616608 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4329 13:58:42.616750 == TX Byte 1 ==
4330 13:58:42.623376 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4331 13:58:42.626815 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4332 13:58:42.626929 ==
4333 13:58:42.629952 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 13:58:42.633254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 13:58:42.633335 ==
4336 13:58:42.633397
4337 13:58:42.636652
4338 13:58:42.636776 TX Vref Scan disable
4339 13:58:42.640317 == TX Byte 0 ==
4340 13:58:42.643849 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4341 13:58:42.647626 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4342 13:58:42.650039 == TX Byte 1 ==
4343 13:58:42.653653 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4344 13:58:42.656547 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4345 13:58:42.660358
4346 13:58:42.660433 [DATLAT]
4347 13:58:42.660519 Freq=600, CH0 RK1
4348 13:58:42.660617
4349 13:58:42.663416 DATLAT Default: 0x9
4350 13:58:42.663485 0, 0xFFFF, sum = 0
4351 13:58:42.666808 1, 0xFFFF, sum = 0
4352 13:58:42.666891 2, 0xFFFF, sum = 0
4353 13:58:42.670022 3, 0xFFFF, sum = 0
4354 13:58:42.670095 4, 0xFFFF, sum = 0
4355 13:58:42.673641 5, 0xFFFF, sum = 0
4356 13:58:42.673719 6, 0xFFFF, sum = 0
4357 13:58:42.676870 7, 0xFFFF, sum = 0
4358 13:58:42.676948 8, 0x0, sum = 1
4359 13:58:42.680277 9, 0x0, sum = 2
4360 13:58:42.680349 10, 0x0, sum = 3
4361 13:58:42.683392 11, 0x0, sum = 4
4362 13:58:42.683471 best_step = 9
4363 13:58:42.683531
4364 13:58:42.683588 ==
4365 13:58:42.686751 Dram Type= 6, Freq= 0, CH_0, rank 1
4366 13:58:42.693614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 13:58:42.693701 ==
4368 13:58:42.693772 RX Vref Scan: 0
4369 13:58:42.693832
4370 13:58:42.696896 RX Vref 0 -> 0, step: 1
4371 13:58:42.696966
4372 13:58:42.700487 RX Delay -195 -> 252, step: 8
4373 13:58:42.703657 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4374 13:58:42.706808 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4375 13:58:42.713588 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4376 13:58:42.717237 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4377 13:58:42.720160 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4378 13:58:42.723798 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4379 13:58:42.730322 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4380 13:58:42.733488 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4381 13:58:42.736702 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4382 13:58:42.740344 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4383 13:58:42.743994 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4384 13:58:42.750183 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4385 13:58:42.753325 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4386 13:58:42.756802 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4387 13:58:42.760412 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4388 13:58:42.766837 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4389 13:58:42.766916 ==
4390 13:58:42.770096 Dram Type= 6, Freq= 0, CH_0, rank 1
4391 13:58:42.773182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 13:58:42.773288 ==
4393 13:58:42.773380 DQS Delay:
4394 13:58:42.776560 DQS0 = 0, DQS1 = 0
4395 13:58:42.776674 DQM Delay:
4396 13:58:42.780125 DQM0 = 39, DQM1 = 33
4397 13:58:42.780196 DQ Delay:
4398 13:58:42.783750 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4399 13:58:42.786811 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4400 13:58:42.790095 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4401 13:58:42.793502 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4402 13:58:42.793609
4403 13:58:42.793699
4404 13:58:42.800257 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4405 13:58:42.803374 CH0 RK1: MR19=808, MR18=4F31
4406 13:58:42.810464 CH0_RK1: MR19=0x808, MR18=0x4F31, DQSOSC=394, MR23=63, INC=168, DEC=112
4407 13:58:42.813690 [RxdqsGatingPostProcess] freq 600
4408 13:58:42.820174 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4409 13:58:42.824107 Pre-setting of DQS Precalculation
4410 13:58:42.827340 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4411 13:58:42.827415 ==
4412 13:58:42.830658 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 13:58:42.834183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 13:58:42.834258 ==
4415 13:58:42.840576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4416 13:58:42.847423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4417 13:58:42.850626 [CA 0] Center 35 (5~65) winsize 61
4418 13:58:42.853911 [CA 1] Center 35 (5~66) winsize 62
4419 13:58:42.857234 [CA 2] Center 34 (4~65) winsize 62
4420 13:58:42.860689 [CA 3] Center 33 (3~64) winsize 62
4421 13:58:42.864470 [CA 4] Center 34 (3~65) winsize 63
4422 13:58:42.867370 [CA 5] Center 33 (3~64) winsize 62
4423 13:58:42.867471
4424 13:58:42.870616 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4425 13:58:42.870717
4426 13:58:42.874227 [CATrainingPosCal] consider 1 rank data
4427 13:58:42.877578 u2DelayCellTimex100 = 270/100 ps
4428 13:58:42.880558 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4429 13:58:42.884041 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4430 13:58:42.887573 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 13:58:42.890766 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 13:58:42.894360 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4433 13:58:42.897562 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 13:58:42.897673
4435 13:58:42.900979 CA PerBit enable=1, Macro0, CA PI delay=33
4436 13:58:42.904276
4437 13:58:42.904394 [CBTSetCACLKResult] CA Dly = 33
4438 13:58:42.907337 CS Dly: 5 (0~36)
4439 13:58:42.907438 ==
4440 13:58:42.910677 Dram Type= 6, Freq= 0, CH_1, rank 1
4441 13:58:42.914018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 13:58:42.914125 ==
4443 13:58:42.920975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4444 13:58:42.927494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4445 13:58:42.930837 [CA 0] Center 35 (5~66) winsize 62
4446 13:58:42.934188 [CA 1] Center 36 (6~66) winsize 61
4447 13:58:42.937427 [CA 2] Center 34 (4~65) winsize 62
4448 13:58:42.941127 [CA 3] Center 34 (3~65) winsize 63
4449 13:58:42.944327 [CA 4] Center 34 (3~65) winsize 63
4450 13:58:42.947386 [CA 5] Center 33 (3~64) winsize 62
4451 13:58:42.947459
4452 13:58:42.951248 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4453 13:58:42.951346
4454 13:58:42.954665 [CATrainingPosCal] consider 2 rank data
4455 13:58:42.957867 u2DelayCellTimex100 = 270/100 ps
4456 13:58:42.961125 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4457 13:58:42.964658 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4458 13:58:42.967515 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4459 13:58:42.970796 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4460 13:58:42.974358 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4461 13:58:42.977521 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4462 13:58:42.977600
4463 13:58:42.981313 CA PerBit enable=1, Macro0, CA PI delay=33
4464 13:58:42.984089
4465 13:58:42.984173 [CBTSetCACLKResult] CA Dly = 33
4466 13:58:42.987547 CS Dly: 5 (0~36)
4467 13:58:42.987621
4468 13:58:42.990992 ----->DramcWriteLeveling(PI) begin...
4469 13:58:42.991102 ==
4470 13:58:42.994140 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 13:58:42.997708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 13:58:42.997809 ==
4473 13:58:43.001657 Write leveling (Byte 0): 29 => 29
4474 13:58:43.004283 Write leveling (Byte 1): 29 => 29
4475 13:58:43.007555 DramcWriteLeveling(PI) end<-----
4476 13:58:43.007661
4477 13:58:43.007763 ==
4478 13:58:43.010819 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 13:58:43.014182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 13:58:43.014280 ==
4481 13:58:43.017679 [Gating] SW mode calibration
4482 13:58:43.024592 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4483 13:58:43.030868 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4484 13:58:43.034119 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4485 13:58:43.040877 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4486 13:58:43.044081 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 13:58:43.047757 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
4488 13:58:43.051089 0 9 16 | B1->B0 | 2828 2525 | 0 0 | (0 0) (1 0)
4489 13:58:43.057499 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 13:58:43.060863 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4491 13:58:43.064309 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 13:58:43.071408 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 13:58:43.074596 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 13:58:43.077918 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 13:58:43.084794 0 10 12 | B1->B0 | 2828 2d2d | 0 0 | (0 0) (0 0)
4496 13:58:43.087747 0 10 16 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
4497 13:58:43.091218 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 13:58:43.097668 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 13:58:43.101379 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 13:58:43.104916 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 13:58:43.111560 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 13:58:43.114465 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 13:58:43.118064 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4504 13:58:43.124386 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 13:58:43.127598 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 13:58:43.131210 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 13:58:43.134379 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 13:58:43.141035 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 13:58:43.144481 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 13:58:43.148060 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 13:58:43.154416 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 13:58:43.157642 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 13:58:43.160841 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 13:58:43.167580 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 13:58:43.170893 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 13:58:43.174194 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 13:58:43.181170 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 13:58:43.184228 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 13:58:43.187682 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 13:58:43.194486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 13:58:43.194560 Total UI for P1: 0, mck2ui 16
4522 13:58:43.201667 best dqsien dly found for B0: ( 0, 13, 14)
4523 13:58:43.201762 Total UI for P1: 0, mck2ui 16
4524 13:58:43.205020 best dqsien dly found for B1: ( 0, 13, 14)
4525 13:58:43.211561 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4526 13:58:43.214764 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4527 13:58:43.214846
4528 13:58:43.217800 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4529 13:58:43.220975 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4530 13:58:43.224524 [Gating] SW calibration Done
4531 13:58:43.224605 ==
4532 13:58:43.227837 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 13:58:43.231427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 13:58:43.231509 ==
4535 13:58:43.234833 RX Vref Scan: 0
4536 13:58:43.234914
4537 13:58:43.234978 RX Vref 0 -> 0, step: 1
4538 13:58:43.235038
4539 13:58:43.237702 RX Delay -230 -> 252, step: 16
4540 13:58:43.241366 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4541 13:58:43.247860 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4542 13:58:43.251670 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4543 13:58:43.254644 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4544 13:58:43.258117 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4545 13:58:43.261550 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4546 13:58:43.268354 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4547 13:58:43.271290 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4548 13:58:43.274654 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4549 13:58:43.278470 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4550 13:58:43.284812 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4551 13:58:43.288472 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4552 13:58:43.291851 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4553 13:58:43.294728 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4554 13:58:43.298199 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4555 13:58:43.305025 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4556 13:58:43.305107 ==
4557 13:58:43.308236 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 13:58:43.311964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 13:58:43.312047 ==
4560 13:58:43.312111 DQS Delay:
4561 13:58:43.315283 DQS0 = 0, DQS1 = 0
4562 13:58:43.315364 DQM Delay:
4563 13:58:43.318555 DQM0 = 44, DQM1 = 37
4564 13:58:43.318635 DQ Delay:
4565 13:58:43.321489 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4566 13:58:43.324775 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4567 13:58:43.328424 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =41
4568 13:58:43.331499 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4569 13:58:43.331607
4570 13:58:43.331699
4571 13:58:43.331800 ==
4572 13:58:43.335450 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 13:58:43.338275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 13:58:43.338375 ==
4575 13:58:43.341501
4576 13:58:43.341598
4577 13:58:43.341685 TX Vref Scan disable
4578 13:58:43.344823 == TX Byte 0 ==
4579 13:58:43.348057 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4580 13:58:43.351557 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4581 13:58:43.354672 == TX Byte 1 ==
4582 13:58:43.358283 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4583 13:58:43.361978 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4584 13:58:43.362087 ==
4585 13:58:43.364928 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 13:58:43.371491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 13:58:43.371602 ==
4588 13:58:43.371692
4589 13:58:43.371779
4590 13:58:43.371867 TX Vref Scan disable
4591 13:58:43.376248 == TX Byte 0 ==
4592 13:58:43.379318 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4593 13:58:43.382749 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4594 13:58:43.386528 == TX Byte 1 ==
4595 13:58:43.389928 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4596 13:58:43.392980 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4597 13:58:43.396539
4598 13:58:43.396636 [DATLAT]
4599 13:58:43.396799 Freq=600, CH1 RK0
4600 13:58:43.396888
4601 13:58:43.399834 DATLAT Default: 0x9
4602 13:58:43.399905 0, 0xFFFF, sum = 0
4603 13:58:43.402850 1, 0xFFFF, sum = 0
4604 13:58:43.402949 2, 0xFFFF, sum = 0
4605 13:58:43.406576 3, 0xFFFF, sum = 0
4606 13:58:43.406713 4, 0xFFFF, sum = 0
4607 13:58:43.409587 5, 0xFFFF, sum = 0
4608 13:58:43.409666 6, 0xFFFF, sum = 0
4609 13:58:43.413050 7, 0xFFFF, sum = 0
4610 13:58:43.413150 8, 0x0, sum = 1
4611 13:58:43.416548 9, 0x0, sum = 2
4612 13:58:43.416651 10, 0x0, sum = 3
4613 13:58:43.419416 11, 0x0, sum = 4
4614 13:58:43.419516 best_step = 9
4615 13:58:43.419603
4616 13:58:43.419687 ==
4617 13:58:43.422681 Dram Type= 6, Freq= 0, CH_1, rank 0
4618 13:58:43.429690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 13:58:43.429790 ==
4620 13:58:43.429882 RX Vref Scan: 1
4621 13:58:43.429972
4622 13:58:43.433225 RX Vref 0 -> 0, step: 1
4623 13:58:43.433320
4624 13:58:43.436254 RX Delay -195 -> 252, step: 8
4625 13:58:43.436352
4626 13:58:43.439783 Set Vref, RX VrefLevel [Byte0]: 52
4627 13:58:43.443299 [Byte1]: 53
4628 13:58:43.443395
4629 13:58:43.446435 Final RX Vref Byte 0 = 52 to rank0
4630 13:58:43.449873 Final RX Vref Byte 1 = 53 to rank0
4631 13:58:43.453035 Final RX Vref Byte 0 = 52 to rank1
4632 13:58:43.456169 Final RX Vref Byte 1 = 53 to rank1==
4633 13:58:43.460089 Dram Type= 6, Freq= 0, CH_1, rank 0
4634 13:58:43.463209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 13:58:43.463311 ==
4636 13:58:43.466281 DQS Delay:
4637 13:58:43.466378 DQS0 = 0, DQS1 = 0
4638 13:58:43.466470 DQM Delay:
4639 13:58:43.469600 DQM0 = 40, DQM1 = 33
4640 13:58:43.469696 DQ Delay:
4641 13:58:43.472946 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4642 13:58:43.476252 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4643 13:58:43.479827 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4644 13:58:43.482970 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4645 13:58:43.483069
4646 13:58:43.483159
4647 13:58:43.492808 [DQSOSCAuto] RK0, (LSB)MR18= 0x460b, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4648 13:58:43.492884 CH1 RK0: MR19=808, MR18=460B
4649 13:58:43.499516 CH1_RK0: MR19=0x808, MR18=0x460B, DQSOSC=396, MR23=63, INC=167, DEC=111
4650 13:58:43.499617
4651 13:58:43.502861 ----->DramcWriteLeveling(PI) begin...
4652 13:58:43.506248 ==
4653 13:58:43.506348 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 13:58:43.512828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 13:58:43.512903 ==
4656 13:58:43.516104 Write leveling (Byte 0): 30 => 30
4657 13:58:43.519455 Write leveling (Byte 1): 29 => 29
4658 13:58:43.519556 DramcWriteLeveling(PI) end<-----
4659 13:58:43.522930
4660 13:58:43.523028 ==
4661 13:58:43.526335 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 13:58:43.529304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 13:58:43.529402 ==
4664 13:58:43.532629 [Gating] SW mode calibration
4665 13:58:43.539523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4666 13:58:43.542868 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4667 13:58:43.549438 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4668 13:58:43.552792 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4669 13:58:43.556026 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4670 13:58:43.563087 0 9 12 | B1->B0 | 3030 2929 | 1 1 | (1 1) (1 0)
4671 13:58:43.566536 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4672 13:58:43.569441 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 13:58:43.576552 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 13:58:43.579507 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 13:58:43.582777 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 13:58:43.586498 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 13:58:43.593597 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4678 13:58:43.596463 0 10 12 | B1->B0 | 3131 3e3e | 0 0 | (0 0) (1 1)
4679 13:58:43.599747 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4680 13:58:43.606652 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 13:58:43.610207 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 13:58:43.613358 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 13:58:43.620016 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 13:58:43.623075 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 13:58:43.626766 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4686 13:58:43.633054 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 13:58:43.636503 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 13:58:43.639889 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 13:58:43.646853 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 13:58:43.649798 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 13:58:43.653106 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 13:58:43.659876 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 13:58:43.663353 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 13:58:43.666832 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 13:58:43.669972 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 13:58:43.677022 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 13:58:43.679966 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 13:58:43.683824 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 13:58:43.690785 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 13:58:43.693866 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 13:58:43.696926 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4702 13:58:43.700267 Total UI for P1: 0, mck2ui 16
4703 13:58:43.703720 best dqsien dly found for B0: ( 0, 13, 6)
4704 13:58:43.710705 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4705 13:58:43.713442 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 13:58:43.717182 Total UI for P1: 0, mck2ui 16
4707 13:58:43.720386 best dqsien dly found for B1: ( 0, 13, 12)
4708 13:58:43.723538 best DQS0 dly(MCK, UI, PI) = (0, 13, 6)
4709 13:58:43.727148 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4710 13:58:43.727245
4711 13:58:43.730268 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 6)
4712 13:58:43.733477 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4713 13:58:43.737075 [Gating] SW calibration Done
4714 13:58:43.737170 ==
4715 13:58:43.740328 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 13:58:43.743916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 13:58:43.743990 ==
4718 13:58:43.747041 RX Vref Scan: 0
4719 13:58:43.747138
4720 13:58:43.750837 RX Vref 0 -> 0, step: 1
4721 13:58:43.750933
4722 13:58:43.751025 RX Delay -230 -> 252, step: 16
4723 13:58:43.757093 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4724 13:58:43.761092 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4725 13:58:43.763908 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4726 13:58:43.767458 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4727 13:58:43.770339 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4728 13:58:43.777620 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4729 13:58:43.780706 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4730 13:58:43.784191 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4731 13:58:43.787266 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4732 13:58:43.793835 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4733 13:58:43.797124 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4734 13:58:43.800555 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4735 13:58:43.804297 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4736 13:58:43.810702 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4737 13:58:43.813870 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4738 13:58:43.817760 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4739 13:58:43.817858 ==
4740 13:58:43.820674 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 13:58:43.824136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 13:58:43.824234 ==
4743 13:58:43.827684 DQS Delay:
4744 13:58:43.827779 DQS0 = 0, DQS1 = 0
4745 13:58:43.827865 DQM Delay:
4746 13:58:43.830643 DQM0 = 41, DQM1 = 37
4747 13:58:43.830737 DQ Delay:
4748 13:58:43.834366 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4749 13:58:43.837608 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4750 13:58:43.840891 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4751 13:58:43.844002 DQ12 =41, DQ13 =57, DQ14 =41, DQ15 =41
4752 13:58:43.844102
4753 13:58:43.844192
4754 13:58:43.844280 ==
4755 13:58:43.847705 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 13:58:43.853871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 13:58:43.853976 ==
4758 13:58:43.854067
4759 13:58:43.854155
4760 13:58:43.854242 TX Vref Scan disable
4761 13:58:43.857944 == TX Byte 0 ==
4762 13:58:43.861195 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4763 13:58:43.867803 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4764 13:58:43.867902 == TX Byte 1 ==
4765 13:58:43.871319 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4766 13:58:43.874609 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4767 13:58:43.877754 ==
4768 13:58:43.881018 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 13:58:43.884328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 13:58:43.884426 ==
4771 13:58:43.884514
4772 13:58:43.884602
4773 13:58:43.887854 TX Vref Scan disable
4774 13:58:43.887948 == TX Byte 0 ==
4775 13:58:43.894069 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4776 13:58:43.897905 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4777 13:58:43.898001 == TX Byte 1 ==
4778 13:58:43.904080 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4779 13:58:43.907657 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4780 13:58:43.907757
4781 13:58:43.907850 [DATLAT]
4782 13:58:43.910952 Freq=600, CH1 RK1
4783 13:58:43.911054
4784 13:58:43.911144 DATLAT Default: 0x9
4785 13:58:43.914270 0, 0xFFFF, sum = 0
4786 13:58:43.914368 1, 0xFFFF, sum = 0
4787 13:58:43.917928 2, 0xFFFF, sum = 0
4788 13:58:43.920736 3, 0xFFFF, sum = 0
4789 13:58:43.920838 4, 0xFFFF, sum = 0
4790 13:58:43.924670 5, 0xFFFF, sum = 0
4791 13:58:43.924750 6, 0xFFFF, sum = 0
4792 13:58:43.927672 7, 0xFFFF, sum = 0
4793 13:58:43.927749 8, 0x0, sum = 1
4794 13:58:43.927839 9, 0x0, sum = 2
4795 13:58:43.930813 10, 0x0, sum = 3
4796 13:58:43.930914 11, 0x0, sum = 4
4797 13:58:43.934628 best_step = 9
4798 13:58:43.934726
4799 13:58:43.934804 ==
4800 13:58:43.937571 Dram Type= 6, Freq= 0, CH_1, rank 1
4801 13:58:43.941224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4802 13:58:43.941323 ==
4803 13:58:43.944682 RX Vref Scan: 0
4804 13:58:43.944756
4805 13:58:43.944847 RX Vref 0 -> 0, step: 1
4806 13:58:43.944935
4807 13:58:43.948059 RX Delay -179 -> 252, step: 8
4808 13:58:43.954702 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4809 13:58:43.958174 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4810 13:58:43.961660 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4811 13:58:43.964924 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4812 13:58:43.971495 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4813 13:58:43.975182 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4814 13:58:43.978219 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4815 13:58:43.981796 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4816 13:58:43.985364 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4817 13:58:43.991774 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4818 13:58:43.995035 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4819 13:58:43.998400 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4820 13:58:44.001713 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4821 13:58:44.008170 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4822 13:58:44.011784 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4823 13:58:44.014926 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4824 13:58:44.015006 ==
4825 13:58:44.018414 Dram Type= 6, Freq= 0, CH_1, rank 1
4826 13:58:44.021417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4827 13:58:44.021499 ==
4828 13:58:44.024683 DQS Delay:
4829 13:58:44.024763 DQS0 = 0, DQS1 = 0
4830 13:58:44.028269 DQM Delay:
4831 13:58:44.028349 DQM0 = 37, DQM1 = 33
4832 13:58:44.028413 DQ Delay:
4833 13:58:44.031704 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4834 13:58:44.035073 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4835 13:58:44.038195 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4836 13:58:44.041954 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4837 13:58:44.042035
4838 13:58:44.042099
4839 13:58:44.051860 [DQSOSCAuto] RK1, (LSB)MR18= 0x414f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 397 ps
4840 13:58:44.055334 CH1 RK1: MR19=808, MR18=414F
4841 13:58:44.058316 CH1_RK1: MR19=0x808, MR18=0x414F, DQSOSC=394, MR23=63, INC=168, DEC=112
4842 13:58:44.062000 [RxdqsGatingPostProcess] freq 600
4843 13:58:44.068520 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4844 13:58:44.072157 Pre-setting of DQS Precalculation
4845 13:58:44.075330 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4846 13:58:44.081705 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4847 13:58:44.092253 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4848 13:58:44.092334
4849 13:58:44.092397
4850 13:58:44.095158 [Calibration Summary] 1200 Mbps
4851 13:58:44.095238 CH 0, Rank 0
4852 13:58:44.098779 SW Impedance : PASS
4853 13:58:44.098859 DUTY Scan : NO K
4854 13:58:44.102512 ZQ Calibration : PASS
4855 13:58:44.105213 Jitter Meter : NO K
4856 13:58:44.105294 CBT Training : PASS
4857 13:58:44.108730 Write leveling : PASS
4858 13:58:44.108811 RX DQS gating : PASS
4859 13:58:44.112031 RX DQ/DQS(RDDQC) : PASS
4860 13:58:44.115267 TX DQ/DQS : PASS
4861 13:58:44.115348 RX DATLAT : PASS
4862 13:58:44.118578 RX DQ/DQS(Engine): PASS
4863 13:58:44.121852 TX OE : NO K
4864 13:58:44.121933 All Pass.
4865 13:58:44.121996
4866 13:58:44.122055 CH 0, Rank 1
4867 13:58:44.125162 SW Impedance : PASS
4868 13:58:44.128577 DUTY Scan : NO K
4869 13:58:44.128657 ZQ Calibration : PASS
4870 13:58:44.132189 Jitter Meter : NO K
4871 13:58:44.135382 CBT Training : PASS
4872 13:58:44.135463 Write leveling : PASS
4873 13:58:44.138476 RX DQS gating : PASS
4874 13:58:44.142789 RX DQ/DQS(RDDQC) : PASS
4875 13:58:44.142870 TX DQ/DQS : PASS
4876 13:58:44.145601 RX DATLAT : PASS
4877 13:58:44.145681 RX DQ/DQS(Engine): PASS
4878 13:58:44.148952 TX OE : NO K
4879 13:58:44.149033 All Pass.
4880 13:58:44.149097
4881 13:58:44.152024 CH 1, Rank 0
4882 13:58:44.152103 SW Impedance : PASS
4883 13:58:44.155441 DUTY Scan : NO K
4884 13:58:44.158716 ZQ Calibration : PASS
4885 13:58:44.158796 Jitter Meter : NO K
4886 13:58:44.162622 CBT Training : PASS
4887 13:58:44.165603 Write leveling : PASS
4888 13:58:44.165684 RX DQS gating : PASS
4889 13:58:44.168968 RX DQ/DQS(RDDQC) : PASS
4890 13:58:44.172296 TX DQ/DQS : PASS
4891 13:58:44.172376 RX DATLAT : PASS
4892 13:58:44.175964 RX DQ/DQS(Engine): PASS
4893 13:58:44.179138 TX OE : NO K
4894 13:58:44.179219 All Pass.
4895 13:58:44.179283
4896 13:58:44.179341 CH 1, Rank 1
4897 13:58:44.182149 SW Impedance : PASS
4898 13:58:44.185443 DUTY Scan : NO K
4899 13:58:44.185524 ZQ Calibration : PASS
4900 13:58:44.188649 Jitter Meter : NO K
4901 13:58:44.188772 CBT Training : PASS
4902 13:58:44.192230 Write leveling : PASS
4903 13:58:44.195560 RX DQS gating : PASS
4904 13:58:44.195640 RX DQ/DQS(RDDQC) : PASS
4905 13:58:44.198693 TX DQ/DQS : PASS
4906 13:58:44.202303 RX DATLAT : PASS
4907 13:58:44.202384 RX DQ/DQS(Engine): PASS
4908 13:58:44.205364 TX OE : NO K
4909 13:58:44.205444 All Pass.
4910 13:58:44.205508
4911 13:58:44.208649 DramC Write-DBI off
4912 13:58:44.212125 PER_BANK_REFRESH: Hybrid Mode
4913 13:58:44.212227 TX_TRACKING: ON
4914 13:58:44.222460 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4915 13:58:44.225270 [FAST_K] Save calibration result to emmc
4916 13:58:44.228848 dramc_set_vcore_voltage set vcore to 662500
4917 13:58:44.231923 Read voltage for 933, 3
4918 13:58:44.232022 Vio18 = 0
4919 13:58:44.232114 Vcore = 662500
4920 13:58:44.235387 Vdram = 0
4921 13:58:44.235485 Vddq = 0
4922 13:58:44.235572 Vmddr = 0
4923 13:58:44.242338 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4924 13:58:44.245287 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4925 13:58:44.249036 MEM_TYPE=3, freq_sel=17
4926 13:58:44.251919 sv_algorithm_assistance_LP4_1600
4927 13:58:44.256012 ============ PULL DRAM RESETB DOWN ============
4928 13:58:44.258909 ========== PULL DRAM RESETB DOWN end =========
4929 13:58:44.265613 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4930 13:58:44.268607 ===================================
4931 13:58:44.268718 LPDDR4 DRAM CONFIGURATION
4932 13:58:44.272597 ===================================
4933 13:58:44.275849 EX_ROW_EN[0] = 0x0
4934 13:58:44.279286 EX_ROW_EN[1] = 0x0
4935 13:58:44.279393 LP4Y_EN = 0x0
4936 13:58:44.282289 WORK_FSP = 0x0
4937 13:58:44.282398 WL = 0x3
4938 13:58:44.285483 RL = 0x3
4939 13:58:44.285599 BL = 0x2
4940 13:58:44.288717 RPST = 0x0
4941 13:58:44.288830 RD_PRE = 0x0
4942 13:58:44.292325 WR_PRE = 0x1
4943 13:58:44.292425 WR_PST = 0x0
4944 13:58:44.295987 DBI_WR = 0x0
4945 13:58:44.296087 DBI_RD = 0x0
4946 13:58:44.299005 OTF = 0x1
4947 13:58:44.302253 ===================================
4948 13:58:44.305431 ===================================
4949 13:58:44.305504 ANA top config
4950 13:58:44.309069 ===================================
4951 13:58:44.312503 DLL_ASYNC_EN = 0
4952 13:58:44.315438 ALL_SLAVE_EN = 1
4953 13:58:44.315537 NEW_RANK_MODE = 1
4954 13:58:44.318923 DLL_IDLE_MODE = 1
4955 13:58:44.322514 LP45_APHY_COMB_EN = 1
4956 13:58:44.325610 TX_ODT_DIS = 1
4957 13:58:44.328880 NEW_8X_MODE = 1
4958 13:58:44.332170 ===================================
4959 13:58:44.335677 ===================================
4960 13:58:44.335778 data_rate = 1866
4961 13:58:44.338933 CKR = 1
4962 13:58:44.342283 DQ_P2S_RATIO = 8
4963 13:58:44.345578 ===================================
4964 13:58:44.348995 CA_P2S_RATIO = 8
4965 13:58:44.352404 DQ_CA_OPEN = 0
4966 13:58:44.355676 DQ_SEMI_OPEN = 0
4967 13:58:44.355749 CA_SEMI_OPEN = 0
4968 13:58:44.359043 CA_FULL_RATE = 0
4969 13:58:44.362478 DQ_CKDIV4_EN = 1
4970 13:58:44.366257 CA_CKDIV4_EN = 1
4971 13:58:44.369224 CA_PREDIV_EN = 0
4972 13:58:44.369334 PH8_DLY = 0
4973 13:58:44.372536 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4974 13:58:44.376005 DQ_AAMCK_DIV = 4
4975 13:58:44.379260 CA_AAMCK_DIV = 4
4976 13:58:44.382829 CA_ADMCK_DIV = 4
4977 13:58:44.385940 DQ_TRACK_CA_EN = 0
4978 13:58:44.386043 CA_PICK = 933
4979 13:58:44.389050 CA_MCKIO = 933
4980 13:58:44.392419 MCKIO_SEMI = 0
4981 13:58:44.395835 PLL_FREQ = 3732
4982 13:58:44.399176 DQ_UI_PI_RATIO = 32
4983 13:58:44.402659 CA_UI_PI_RATIO = 0
4984 13:58:44.406060 ===================================
4985 13:58:44.409213 ===================================
4986 13:58:44.409288 memory_type:LPDDR4
4987 13:58:44.413006 GP_NUM : 10
4988 13:58:44.416279 SRAM_EN : 1
4989 13:58:44.416380 MD32_EN : 0
4990 13:58:44.419378 ===================================
4991 13:58:44.422697 [ANA_INIT] >>>>>>>>>>>>>>
4992 13:58:44.426100 <<<<<< [CONFIGURE PHASE]: ANA_TX
4993 13:58:44.429399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4994 13:58:44.432737 ===================================
4995 13:58:44.436599 data_rate = 1866,PCW = 0X8f00
4996 13:58:44.440059 ===================================
4997 13:58:44.442506 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4998 13:58:44.446297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4999 13:58:44.452583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5000 13:58:44.456498 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5001 13:58:44.459917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5002 13:58:44.462979 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5003 13:58:44.466281 [ANA_INIT] flow start
5004 13:58:44.469626 [ANA_INIT] PLL >>>>>>>>
5005 13:58:44.469762 [ANA_INIT] PLL <<<<<<<<
5006 13:58:44.473060 [ANA_INIT] MIDPI >>>>>>>>
5007 13:58:44.476064 [ANA_INIT] MIDPI <<<<<<<<
5008 13:58:44.476165 [ANA_INIT] DLL >>>>>>>>
5009 13:58:44.479762 [ANA_INIT] flow end
5010 13:58:44.482937 ============ LP4 DIFF to SE enter ============
5011 13:58:44.486038 ============ LP4 DIFF to SE exit ============
5012 13:58:44.489613 [ANA_INIT] <<<<<<<<<<<<<
5013 13:58:44.492637 [Flow] Enable top DCM control >>>>>
5014 13:58:44.496735 [Flow] Enable top DCM control <<<<<
5015 13:58:44.499333 Enable DLL master slave shuffle
5016 13:58:44.506304 ==============================================================
5017 13:58:44.506379 Gating Mode config
5018 13:58:44.512805 ==============================================================
5019 13:58:44.512879 Config description:
5020 13:58:44.523318 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5021 13:58:44.529908 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5022 13:58:44.536342 SELPH_MODE 0: By rank 1: By Phase
5023 13:58:44.540045 ==============================================================
5024 13:58:44.542925 GAT_TRACK_EN = 1
5025 13:58:44.546887 RX_GATING_MODE = 2
5026 13:58:44.550100 RX_GATING_TRACK_MODE = 2
5027 13:58:44.553204 SELPH_MODE = 1
5028 13:58:44.556578 PICG_EARLY_EN = 1
5029 13:58:44.560209 VALID_LAT_VALUE = 1
5030 13:58:44.563225 ==============================================================
5031 13:58:44.566425 Enter into Gating configuration >>>>
5032 13:58:44.570583 Exit from Gating configuration <<<<
5033 13:58:44.573149 Enter into DVFS_PRE_config >>>>>
5034 13:58:44.587020 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5035 13:58:44.589713 Exit from DVFS_PRE_config <<<<<
5036 13:58:44.589794 Enter into PICG configuration >>>>
5037 13:58:44.593299 Exit from PICG configuration <<<<
5038 13:58:44.596548 [RX_INPUT] configuration >>>>>
5039 13:58:44.599902 [RX_INPUT] configuration <<<<<
5040 13:58:44.607256 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5041 13:58:44.610300 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5042 13:58:44.616479 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5043 13:58:44.623301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5044 13:58:44.630308 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 13:58:44.636529 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 13:58:44.639851 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5047 13:58:44.643066 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5048 13:58:44.647158 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5049 13:58:44.653643 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5050 13:58:44.657074 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5051 13:58:44.660093 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5052 13:58:44.663635 ===================================
5053 13:58:44.666593 LPDDR4 DRAM CONFIGURATION
5054 13:58:44.670178 ===================================
5055 13:58:44.670274 EX_ROW_EN[0] = 0x0
5056 13:58:44.673521 EX_ROW_EN[1] = 0x0
5057 13:58:44.676609 LP4Y_EN = 0x0
5058 13:58:44.676718 WORK_FSP = 0x0
5059 13:58:44.679937 WL = 0x3
5060 13:58:44.680018 RL = 0x3
5061 13:58:44.683533 BL = 0x2
5062 13:58:44.683625 RPST = 0x0
5063 13:58:44.686888 RD_PRE = 0x0
5064 13:58:44.686980 WR_PRE = 0x1
5065 13:58:44.689848 WR_PST = 0x0
5066 13:58:44.689940 DBI_WR = 0x0
5067 13:58:44.693410 DBI_RD = 0x0
5068 13:58:44.693499 OTF = 0x1
5069 13:58:44.696528 ===================================
5070 13:58:44.700088 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5071 13:58:44.706644 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5072 13:58:44.710263 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5073 13:58:44.713729 ===================================
5074 13:58:44.717156 LPDDR4 DRAM CONFIGURATION
5075 13:58:44.720474 ===================================
5076 13:58:44.720575 EX_ROW_EN[0] = 0x10
5077 13:58:44.723851 EX_ROW_EN[1] = 0x0
5078 13:58:44.723950 LP4Y_EN = 0x0
5079 13:58:44.726744 WORK_FSP = 0x0
5080 13:58:44.726844 WL = 0x3
5081 13:58:44.730016 RL = 0x3
5082 13:58:44.730109 BL = 0x2
5083 13:58:44.733387 RPST = 0x0
5084 13:58:44.733457 RD_PRE = 0x0
5085 13:58:44.737421 WR_PRE = 0x1
5086 13:58:44.737488 WR_PST = 0x0
5087 13:58:44.740215 DBI_WR = 0x0
5088 13:58:44.740311 DBI_RD = 0x0
5089 13:58:44.743717 OTF = 0x1
5090 13:58:44.747318 ===================================
5091 13:58:44.753747 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5092 13:58:44.757104 nWR fixed to 30
5093 13:58:44.760391 [ModeRegInit_LP4] CH0 RK0
5094 13:58:44.760485 [ModeRegInit_LP4] CH0 RK1
5095 13:58:44.763827 [ModeRegInit_LP4] CH1 RK0
5096 13:58:44.766985 [ModeRegInit_LP4] CH1 RK1
5097 13:58:44.767080 match AC timing 9
5098 13:58:44.773648 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5099 13:58:44.777464 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5100 13:58:44.780638 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5101 13:58:44.787008 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5102 13:58:44.790739 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5103 13:58:44.790837 ==
5104 13:58:44.793869 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 13:58:44.797522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 13:58:44.797615 ==
5107 13:58:44.804325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5108 13:58:44.810418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5109 13:58:44.813930 [CA 0] Center 38 (8~69) winsize 62
5110 13:58:44.817098 [CA 1] Center 38 (7~69) winsize 63
5111 13:58:44.820397 [CA 2] Center 35 (5~66) winsize 62
5112 13:58:44.824460 [CA 3] Center 35 (5~65) winsize 61
5113 13:58:44.827242 [CA 4] Center 34 (4~64) winsize 61
5114 13:58:44.827339 [CA 5] Center 34 (4~64) winsize 61
5115 13:58:44.830568
5116 13:58:44.833877 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5117 13:58:44.833979
5118 13:58:44.837137 [CATrainingPosCal] consider 1 rank data
5119 13:58:44.840556 u2DelayCellTimex100 = 270/100 ps
5120 13:58:44.843725 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5121 13:58:44.847028 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5122 13:58:44.850859 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5123 13:58:44.853934 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5124 13:58:44.857533 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5125 13:58:44.860707 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5126 13:58:44.860824
5127 13:58:44.864238 CA PerBit enable=1, Macro0, CA PI delay=34
5128 13:58:44.864336
5129 13:58:44.868091 [CBTSetCACLKResult] CA Dly = 34
5130 13:58:44.871115 CS Dly: 6 (0~37)
5131 13:58:44.871213 ==
5132 13:58:44.874094 Dram Type= 6, Freq= 0, CH_0, rank 1
5133 13:58:44.877432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5134 13:58:44.877533 ==
5135 13:58:44.884280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5136 13:58:44.887552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5137 13:58:44.891932 [CA 0] Center 38 (8~69) winsize 62
5138 13:58:44.895295 [CA 1] Center 38 (8~69) winsize 62
5139 13:58:44.898948 [CA 2] Center 35 (5~66) winsize 62
5140 13:58:44.901827 [CA 3] Center 35 (5~65) winsize 61
5141 13:58:44.905325 [CA 4] Center 33 (3~64) winsize 62
5142 13:58:44.908568 [CA 5] Center 33 (3~64) winsize 62
5143 13:58:44.908661
5144 13:58:44.911749 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5145 13:58:44.911842
5146 13:58:44.915202 [CATrainingPosCal] consider 2 rank data
5147 13:58:44.918840 u2DelayCellTimex100 = 270/100 ps
5148 13:58:44.921860 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5149 13:58:44.924961 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5150 13:58:44.932165 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5151 13:58:44.935677 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5152 13:58:44.938650 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5153 13:58:44.941945 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5154 13:58:44.942022
5155 13:58:44.945099 CA PerBit enable=1, Macro0, CA PI delay=34
5156 13:58:44.945174
5157 13:58:44.948572 [CBTSetCACLKResult] CA Dly = 34
5158 13:58:44.948691 CS Dly: 7 (0~39)
5159 13:58:44.948767
5160 13:58:44.952132 ----->DramcWriteLeveling(PI) begin...
5161 13:58:44.952235 ==
5162 13:58:44.955627 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 13:58:44.962074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 13:58:44.962175 ==
5165 13:58:44.965451 Write leveling (Byte 0): 31 => 31
5166 13:58:44.968770 Write leveling (Byte 1): 26 => 26
5167 13:58:44.968845 DramcWriteLeveling(PI) end<-----
5168 13:58:44.971982
5169 13:58:44.972081 ==
5170 13:58:44.975175 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 13:58:44.978672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 13:58:44.978779 ==
5173 13:58:44.981761 [Gating] SW mode calibration
5174 13:58:44.988925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5175 13:58:44.991837 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5176 13:58:44.998846 0 14 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
5177 13:58:45.002167 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5178 13:58:45.005291 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 13:58:45.012152 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 13:58:45.015416 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 13:58:45.018807 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 13:58:45.025432 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 13:58:45.029243 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5184 13:58:45.032462 0 15 0 | B1->B0 | 3131 2525 | 0 0 | (0 1) (0 0)
5185 13:58:45.038969 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5186 13:58:45.042422 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 13:58:45.045558 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 13:58:45.049167 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 13:58:45.055553 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 13:58:45.059005 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 13:58:45.062324 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5192 13:58:45.069464 1 0 0 | B1->B0 | 3434 3c3c | 0 0 | (0 0) (0 0)
5193 13:58:45.072397 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 13:58:45.076374 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 13:58:45.082690 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 13:58:45.086261 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 13:58:45.089239 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 13:58:45.096029 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 13:58:45.099482 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5200 13:58:45.102621 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5201 13:58:45.105871 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 13:58:45.112654 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 13:58:45.116059 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 13:58:45.119346 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 13:58:45.126104 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 13:58:45.129213 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 13:58:45.132864 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 13:58:45.139282 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 13:58:45.142845 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 13:58:45.146522 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 13:58:45.152923 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 13:58:45.156183 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 13:58:45.159639 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 13:58:45.165849 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 13:58:45.169257 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5216 13:58:45.172781 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5217 13:58:45.179626 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5218 13:58:45.179721 Total UI for P1: 0, mck2ui 16
5219 13:58:45.183175 best dqsien dly found for B0: ( 1, 2, 30)
5220 13:58:45.189389 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 13:58:45.193154 Total UI for P1: 0, mck2ui 16
5222 13:58:45.196358 best dqsien dly found for B1: ( 1, 3, 2)
5223 13:58:45.199872 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5224 13:58:45.203518 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5225 13:58:45.203625
5226 13:58:45.206209 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5227 13:58:45.209680 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5228 13:58:45.213177 [Gating] SW calibration Done
5229 13:58:45.213253 ==
5230 13:58:45.216272 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 13:58:45.219846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 13:58:45.219945 ==
5233 13:58:45.223190 RX Vref Scan: 0
5234 13:58:45.223289
5235 13:58:45.223379 RX Vref 0 -> 0, step: 1
5236 13:58:45.223465
5237 13:58:45.226432 RX Delay -80 -> 252, step: 8
5238 13:58:45.230075 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5239 13:58:45.236544 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5240 13:58:45.239771 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5241 13:58:45.243147 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5242 13:58:45.246459 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5243 13:58:45.249626 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5244 13:58:45.252811 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5245 13:58:45.259713 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5246 13:58:45.263299 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5247 13:58:45.266220 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5248 13:58:45.269590 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5249 13:58:45.272791 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5250 13:58:45.276249 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5251 13:58:45.282893 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5252 13:58:45.286844 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5253 13:58:45.289797 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5254 13:58:45.289902 ==
5255 13:58:45.293057 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 13:58:45.296449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 13:58:45.296554 ==
5258 13:58:45.299945 DQS Delay:
5259 13:58:45.300043 DQS0 = 0, DQS1 = 0
5260 13:58:45.300142 DQM Delay:
5261 13:58:45.303768 DQM0 = 96, DQM1 = 87
5262 13:58:45.303866 DQ Delay:
5263 13:58:45.306385 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5264 13:58:45.309711 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5265 13:58:45.313692 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5266 13:58:45.316350 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5267 13:58:45.316453
5268 13:58:45.316542
5269 13:58:45.316626 ==
5270 13:58:45.320152 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 13:58:45.326619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 13:58:45.326725 ==
5273 13:58:45.326818
5274 13:58:45.326903
5275 13:58:45.326998 TX Vref Scan disable
5276 13:58:45.330189 == TX Byte 0 ==
5277 13:58:45.333621 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5278 13:58:45.337723 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5279 13:58:45.340259 == TX Byte 1 ==
5280 13:58:45.343599 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5281 13:58:45.346939 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5282 13:58:45.350406 ==
5283 13:58:45.354042 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 13:58:45.357747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 13:58:45.357853 ==
5286 13:58:45.357945
5287 13:58:45.358030
5288 13:58:45.360552 TX Vref Scan disable
5289 13:58:45.360647 == TX Byte 0 ==
5290 13:58:45.367261 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5291 13:58:45.370362 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5292 13:58:45.370459 == TX Byte 1 ==
5293 13:58:45.377230 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5294 13:58:45.380276 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5295 13:58:45.380381
5296 13:58:45.380472 [DATLAT]
5297 13:58:45.384044 Freq=933, CH0 RK0
5298 13:58:45.384143
5299 13:58:45.384236 DATLAT Default: 0xd
5300 13:58:45.387082 0, 0xFFFF, sum = 0
5301 13:58:45.387188 1, 0xFFFF, sum = 0
5302 13:58:45.390937 2, 0xFFFF, sum = 0
5303 13:58:45.391040 3, 0xFFFF, sum = 0
5304 13:58:45.394014 4, 0xFFFF, sum = 0
5305 13:58:45.394104 5, 0xFFFF, sum = 0
5306 13:58:45.397249 6, 0xFFFF, sum = 0
5307 13:58:45.397335 7, 0xFFFF, sum = 0
5308 13:58:45.400652 8, 0xFFFF, sum = 0
5309 13:58:45.400799 9, 0xFFFF, sum = 0
5310 13:58:45.404118 10, 0x0, sum = 1
5311 13:58:45.404199 11, 0x0, sum = 2
5312 13:58:45.407584 12, 0x0, sum = 3
5313 13:58:45.407665 13, 0x0, sum = 4
5314 13:58:45.410508 best_step = 11
5315 13:58:45.410589
5316 13:58:45.410653 ==
5317 13:58:45.414072 Dram Type= 6, Freq= 0, CH_0, rank 0
5318 13:58:45.417467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 13:58:45.417549 ==
5320 13:58:45.420699 RX Vref Scan: 1
5321 13:58:45.420794
5322 13:58:45.420857 RX Vref 0 -> 0, step: 1
5323 13:58:45.420916
5324 13:58:45.424245 RX Delay -61 -> 252, step: 4
5325 13:58:45.424326
5326 13:58:45.427694 Set Vref, RX VrefLevel [Byte0]: 54
5327 13:58:45.430520 [Byte1]: 52
5328 13:58:45.434538
5329 13:58:45.434619 Final RX Vref Byte 0 = 54 to rank0
5330 13:58:45.437591 Final RX Vref Byte 1 = 52 to rank0
5331 13:58:45.441698 Final RX Vref Byte 0 = 54 to rank1
5332 13:58:45.444289 Final RX Vref Byte 1 = 52 to rank1==
5333 13:58:45.447713 Dram Type= 6, Freq= 0, CH_0, rank 0
5334 13:58:45.451314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 13:58:45.454705 ==
5336 13:58:45.454803 DQS Delay:
5337 13:58:45.454895 DQS0 = 0, DQS1 = 0
5338 13:58:45.458026 DQM Delay:
5339 13:58:45.458120 DQM0 = 97, DQM1 = 89
5340 13:58:45.461439 DQ Delay:
5341 13:58:45.461540 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5342 13:58:45.464649 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =102
5343 13:58:45.467789 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =80
5344 13:58:45.474317 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =98
5345 13:58:45.474421
5346 13:58:45.474510
5347 13:58:45.481476 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5348 13:58:45.484409 CH0 RK0: MR19=504, MR18=13FE
5349 13:58:45.491383 CH0_RK0: MR19=0x504, MR18=0x13FE, DQSOSC=415, MR23=63, INC=62, DEC=41
5350 13:58:45.491487
5351 13:58:45.494376 ----->DramcWriteLeveling(PI) begin...
5352 13:58:45.494479 ==
5353 13:58:45.497717 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 13:58:45.501445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 13:58:45.501520 ==
5356 13:58:45.505015 Write leveling (Byte 0): 31 => 31
5357 13:58:45.507636 Write leveling (Byte 1): 29 => 29
5358 13:58:45.511287 DramcWriteLeveling(PI) end<-----
5359 13:58:45.511390
5360 13:58:45.511468 ==
5361 13:58:45.514663 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 13:58:45.518037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 13:58:45.518137 ==
5364 13:58:45.520996 [Gating] SW mode calibration
5365 13:58:45.528184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5366 13:58:45.534449 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5367 13:58:45.537648 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5368 13:58:45.540746 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5369 13:58:45.547712 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 13:58:45.551407 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 13:58:45.554661 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 13:58:45.561037 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 13:58:45.564546 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5374 13:58:45.568296 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
5375 13:58:45.574443 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5376 13:58:45.578249 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 13:58:45.581695 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 13:58:45.588413 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 13:58:45.591492 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 13:58:45.594596 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 13:58:45.598207 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 13:58:45.604785 0 15 28 | B1->B0 | 2929 3434 | 0 0 | (1 1) (0 0)
5383 13:58:45.608038 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5384 13:58:45.611252 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5385 13:58:45.618313 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 13:58:45.621187 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 13:58:45.624552 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 13:58:45.631682 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 13:58:45.634783 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5390 13:58:45.638906 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5391 13:58:45.645245 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5392 13:58:45.648139 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5393 13:58:45.651415 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 13:58:45.658155 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 13:58:45.661783 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 13:58:45.665182 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 13:58:45.668440 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 13:58:45.675334 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 13:58:45.678458 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 13:58:45.681620 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 13:58:45.689074 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 13:58:45.691983 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 13:58:45.694775 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 13:58:45.701926 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 13:58:45.705401 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 13:58:45.708457 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5407 13:58:45.714974 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5408 13:58:45.715077 Total UI for P1: 0, mck2ui 16
5409 13:58:45.722015 best dqsien dly found for B0: ( 1, 2, 28)
5410 13:58:45.725649 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 13:58:45.728417 Total UI for P1: 0, mck2ui 16
5412 13:58:45.731997 best dqsien dly found for B1: ( 1, 3, 0)
5413 13:58:45.735220 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5414 13:58:45.738798 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5415 13:58:45.738903
5416 13:58:45.742308 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5417 13:58:45.745802 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5418 13:58:45.748737 [Gating] SW calibration Done
5419 13:58:45.748839 ==
5420 13:58:45.751767 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 13:58:45.755159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 13:58:45.755257 ==
5423 13:58:45.758745 RX Vref Scan: 0
5424 13:58:45.758845
5425 13:58:45.758933 RX Vref 0 -> 0, step: 1
5426 13:58:45.761716
5427 13:58:45.761811 RX Delay -80 -> 252, step: 8
5428 13:58:45.768833 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5429 13:58:45.771905 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5430 13:58:45.775000 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5431 13:58:45.778440 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5432 13:58:45.782033 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5433 13:58:45.785231 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5434 13:58:45.788655 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5435 13:58:45.795317 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5436 13:58:45.798777 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5437 13:58:45.801762 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5438 13:58:45.805015 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5439 13:58:45.808369 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5440 13:58:45.815376 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5441 13:58:45.819109 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5442 13:58:45.822178 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5443 13:58:45.825757 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5444 13:58:45.825838 ==
5445 13:58:45.828393 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 13:58:45.831747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 13:58:45.835320 ==
5448 13:58:45.835399 DQS Delay:
5449 13:58:45.835463 DQS0 = 0, DQS1 = 0
5450 13:58:45.838444 DQM Delay:
5451 13:58:45.838524 DQM0 = 96, DQM1 = 86
5452 13:58:45.841958 DQ Delay:
5453 13:58:45.842038 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5454 13:58:45.845461 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5455 13:58:45.848460 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =79
5456 13:58:45.851865 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5457 13:58:45.851946
5458 13:58:45.855175
5459 13:58:45.855255 ==
5460 13:58:45.858539 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 13:58:45.862087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 13:58:45.862178 ==
5463 13:58:45.862243
5464 13:58:45.862302
5465 13:58:45.865317 TX Vref Scan disable
5466 13:58:45.865397 == TX Byte 0 ==
5467 13:58:45.872128 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5468 13:58:45.875413 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5469 13:58:45.875494 == TX Byte 1 ==
5470 13:58:45.878898 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5471 13:58:45.885455 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5472 13:58:45.885537 ==
5473 13:58:45.888531 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 13:58:45.892346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 13:58:45.892428 ==
5476 13:58:45.892491
5477 13:58:45.892550
5478 13:58:45.896071 TX Vref Scan disable
5479 13:58:45.898736 == TX Byte 0 ==
5480 13:58:45.901943 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5481 13:58:45.905182 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5482 13:58:45.908549 == TX Byte 1 ==
5483 13:58:45.912108 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5484 13:58:45.915808 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5485 13:58:45.915888
5486 13:58:45.915952 [DATLAT]
5487 13:58:45.918621 Freq=933, CH0 RK1
5488 13:58:45.918702
5489 13:58:45.922398 DATLAT Default: 0xb
5490 13:58:45.922478 0, 0xFFFF, sum = 0
5491 13:58:45.925573 1, 0xFFFF, sum = 0
5492 13:58:45.925655 2, 0xFFFF, sum = 0
5493 13:58:45.928881 3, 0xFFFF, sum = 0
5494 13:58:45.928963 4, 0xFFFF, sum = 0
5495 13:58:45.932117 5, 0xFFFF, sum = 0
5496 13:58:45.932198 6, 0xFFFF, sum = 0
5497 13:58:45.935414 7, 0xFFFF, sum = 0
5498 13:58:45.935496 8, 0xFFFF, sum = 0
5499 13:58:45.939014 9, 0xFFFF, sum = 0
5500 13:58:45.939096 10, 0x0, sum = 1
5501 13:58:45.942146 11, 0x0, sum = 2
5502 13:58:45.942228 12, 0x0, sum = 3
5503 13:58:45.945540 13, 0x0, sum = 4
5504 13:58:45.945622 best_step = 11
5505 13:58:45.945686
5506 13:58:45.945744 ==
5507 13:58:45.948982 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 13:58:45.952535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 13:58:45.952615 ==
5510 13:58:45.955767 RX Vref Scan: 0
5511 13:58:45.955848
5512 13:58:45.959099 RX Vref 0 -> 0, step: 1
5513 13:58:45.959179
5514 13:58:45.959243 RX Delay -69 -> 252, step: 4
5515 13:58:45.966546 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5516 13:58:45.969891 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5517 13:58:45.973470 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5518 13:58:45.976620 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5519 13:58:45.980003 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5520 13:58:45.983839 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5521 13:58:45.990366 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5522 13:58:45.993612 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5523 13:58:45.997046 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5524 13:58:46.000139 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5525 13:58:46.003655 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5526 13:58:46.006633 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5527 13:58:46.013450 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5528 13:58:46.016585 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5529 13:58:46.020343 iDelay=199, Bit 14, Center 94 (7 ~ 182) 176
5530 13:58:46.023982 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5531 13:58:46.024082 ==
5532 13:58:46.027032 Dram Type= 6, Freq= 0, CH_0, rank 1
5533 13:58:46.030258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 13:58:46.030337 ==
5535 13:58:46.033679 DQS Delay:
5536 13:58:46.033754 DQS0 = 0, DQS1 = 0
5537 13:58:46.036737 DQM Delay:
5538 13:58:46.036808 DQM0 = 95, DQM1 = 88
5539 13:58:46.036877 DQ Delay:
5540 13:58:46.040227 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5541 13:58:46.043446 DQ4 =94, DQ5 =84, DQ6 =106, DQ7 =102
5542 13:58:46.046587 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =80
5543 13:58:46.050044 DQ12 =92, DQ13 =94, DQ14 =94, DQ15 =96
5544 13:58:46.050143
5545 13:58:46.050231
5546 13:58:46.060159 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5547 13:58:46.063588 CH0 RK1: MR19=505, MR18=1F0C
5548 13:58:46.070349 CH0_RK1: MR19=0x505, MR18=0x1F0C, DQSOSC=412, MR23=63, INC=63, DEC=42
5549 13:58:46.070451 [RxdqsGatingPostProcess] freq 933
5550 13:58:46.077267 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5551 13:58:46.080272 best DQS0 dly(2T, 0.5T) = (0, 10)
5552 13:58:46.083641 best DQS1 dly(2T, 0.5T) = (0, 11)
5553 13:58:46.086968 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5554 13:58:46.090604 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5555 13:58:46.093893 best DQS0 dly(2T, 0.5T) = (0, 10)
5556 13:58:46.097161 best DQS1 dly(2T, 0.5T) = (0, 11)
5557 13:58:46.101036 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5558 13:58:46.103999 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5559 13:58:46.104096 Pre-setting of DQS Precalculation
5560 13:58:46.110623 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5561 13:58:46.110723 ==
5562 13:58:46.114087 Dram Type= 6, Freq= 0, CH_1, rank 0
5563 13:58:46.117216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 13:58:46.117289 ==
5565 13:58:46.123995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5566 13:58:46.130651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5567 13:58:46.134720 [CA 0] Center 36 (6~67) winsize 62
5568 13:58:46.137404 [CA 1] Center 36 (6~67) winsize 62
5569 13:58:46.140502 [CA 2] Center 34 (4~64) winsize 61
5570 13:58:46.143857 [CA 3] Center 33 (3~64) winsize 62
5571 13:58:46.147048 [CA 4] Center 34 (4~64) winsize 61
5572 13:58:46.150779 [CA 5] Center 33 (3~64) winsize 62
5573 13:58:46.150870
5574 13:58:46.153854 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5575 13:58:46.153926
5576 13:58:46.157600 [CATrainingPosCal] consider 1 rank data
5577 13:58:46.160966 u2DelayCellTimex100 = 270/100 ps
5578 13:58:46.164040 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5579 13:58:46.167235 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5580 13:58:46.170325 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5581 13:58:46.173792 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5582 13:58:46.177252 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5583 13:58:46.180578 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5584 13:58:46.180716
5585 13:58:46.183884 CA PerBit enable=1, Macro0, CA PI delay=33
5586 13:58:46.187518
5587 13:58:46.187624 [CBTSetCACLKResult] CA Dly = 33
5588 13:58:46.190596 CS Dly: 5 (0~36)
5589 13:58:46.190692 ==
5590 13:58:46.194013 Dram Type= 6, Freq= 0, CH_1, rank 1
5591 13:58:46.197476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 13:58:46.197560 ==
5593 13:58:46.203858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5594 13:58:46.210591 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5595 13:58:46.213894 [CA 0] Center 36 (6~67) winsize 62
5596 13:58:46.217519 [CA 1] Center 36 (6~67) winsize 62
5597 13:58:46.220525 [CA 2] Center 33 (3~64) winsize 62
5598 13:58:46.224354 [CA 3] Center 33 (3~64) winsize 62
5599 13:58:46.227747 [CA 4] Center 34 (4~64) winsize 61
5600 13:58:46.231132 [CA 5] Center 33 (3~64) winsize 62
5601 13:58:46.231203
5602 13:58:46.234428 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5603 13:58:46.234528
5604 13:58:46.237722 [CATrainingPosCal] consider 2 rank data
5605 13:58:46.240985 u2DelayCellTimex100 = 270/100 ps
5606 13:58:46.243968 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5607 13:58:46.247308 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5608 13:58:46.250659 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5609 13:58:46.254556 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5610 13:58:46.257718 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5611 13:58:46.261085 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5612 13:58:46.261182
5613 13:58:46.264895 CA PerBit enable=1, Macro0, CA PI delay=33
5614 13:58:46.264969
5615 13:58:46.267453 [CBTSetCACLKResult] CA Dly = 33
5616 13:58:46.271096 CS Dly: 5 (0~37)
5617 13:58:46.271195
5618 13:58:46.274139 ----->DramcWriteLeveling(PI) begin...
5619 13:58:46.274235 ==
5620 13:58:46.277491 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 13:58:46.280949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 13:58:46.281034 ==
5623 13:58:46.284141 Write leveling (Byte 0): 28 => 28
5624 13:58:46.287432 Write leveling (Byte 1): 29 => 29
5625 13:58:46.290948 DramcWriteLeveling(PI) end<-----
5626 13:58:46.291051
5627 13:58:46.291146 ==
5628 13:58:46.294622 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 13:58:46.297660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 13:58:46.297759 ==
5631 13:58:46.300923 [Gating] SW mode calibration
5632 13:58:46.307660 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5633 13:58:46.314609 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5634 13:58:46.317551 0 14 0 | B1->B0 | 2f2f 3232 | 1 1 | (1 1) (1 1)
5635 13:58:46.320821 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 13:58:46.327445 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 13:58:46.331050 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5638 13:58:46.334182 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5639 13:58:46.341333 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 13:58:46.344814 0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5641 13:58:46.347576 0 14 28 | B1->B0 | 3030 3232 | 1 0 | (1 0) (0 1)
5642 13:58:46.354702 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5643 13:58:46.357982 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 13:58:46.361294 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 13:58:46.367678 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 13:58:46.371040 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 13:58:46.374540 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 13:58:46.381509 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 13:58:46.384523 0 15 28 | B1->B0 | 3030 3333 | 0 0 | (0 0) (1 1)
5650 13:58:46.387830 1 0 0 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5651 13:58:46.391228 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 13:58:46.398061 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 13:58:46.401297 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 13:58:46.404659 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 13:58:46.411286 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 13:58:46.414456 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5657 13:58:46.418172 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5658 13:58:46.424570 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5659 13:58:46.428066 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 13:58:46.431595 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 13:58:46.438058 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 13:58:46.441726 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 13:58:46.444917 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 13:58:46.451769 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 13:58:46.455221 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 13:58:46.458115 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 13:58:46.461390 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 13:58:46.468187 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 13:58:46.471988 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 13:58:46.474797 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 13:58:46.481966 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 13:58:46.484828 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5673 13:58:46.488054 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 13:58:46.495023 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5675 13:58:46.495104 Total UI for P1: 0, mck2ui 16
5676 13:58:46.501736 best dqsien dly found for B1: ( 1, 2, 30)
5677 13:58:46.505346 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 13:58:46.509083 Total UI for P1: 0, mck2ui 16
5679 13:58:46.511886 best dqsien dly found for B0: ( 1, 3, 0)
5680 13:58:46.515253 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5681 13:58:46.518280 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5682 13:58:46.518361
5683 13:58:46.521921 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5684 13:58:46.525261 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5685 13:58:46.528693 [Gating] SW calibration Done
5686 13:58:46.528788 ==
5687 13:58:46.531672 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 13:58:46.535516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 13:58:46.535597 ==
5690 13:58:46.538309 RX Vref Scan: 0
5691 13:58:46.538389
5692 13:58:46.542379 RX Vref 0 -> 0, step: 1
5693 13:58:46.542460
5694 13:58:46.542523 RX Delay -80 -> 252, step: 8
5695 13:58:46.548644 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5696 13:58:46.552450 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5697 13:58:46.555147 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5698 13:58:46.558435 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5699 13:58:46.561588 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5700 13:58:46.564972 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5701 13:58:46.571603 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5702 13:58:46.575351 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5703 13:58:46.578335 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5704 13:58:46.581804 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5705 13:58:46.585131 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5706 13:58:46.591633 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5707 13:58:46.595010 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5708 13:58:46.598393 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5709 13:58:46.602023 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5710 13:58:46.605476 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5711 13:58:46.605557 ==
5712 13:58:46.608647 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 13:58:46.612228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 13:58:46.612310 ==
5715 13:58:46.615302 DQS Delay:
5716 13:58:46.615382 DQS0 = 0, DQS1 = 0
5717 13:58:46.618729 DQM Delay:
5718 13:58:46.618810 DQM0 = 95, DQM1 = 89
5719 13:58:46.618874 DQ Delay:
5720 13:58:46.622092 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5721 13:58:46.625315 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5722 13:58:46.628474 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5723 13:58:46.631935 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5724 13:58:46.632016
5725 13:58:46.632080
5726 13:58:46.635624 ==
5727 13:58:46.638580 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 13:58:46.642256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 13:58:46.642338 ==
5730 13:58:46.642401
5731 13:58:46.642460
5732 13:58:46.645246 TX Vref Scan disable
5733 13:58:46.645327 == TX Byte 0 ==
5734 13:58:46.648657 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5735 13:58:46.655296 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5736 13:58:46.655377 == TX Byte 1 ==
5737 13:58:46.659000 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5738 13:58:46.665609 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5739 13:58:46.665690 ==
5740 13:58:46.668616 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 13:58:46.672044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 13:58:46.672125 ==
5743 13:58:46.672189
5744 13:58:46.672248
5745 13:58:46.675639 TX Vref Scan disable
5746 13:58:46.679151 == TX Byte 0 ==
5747 13:58:46.682196 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5748 13:58:46.685466 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5749 13:58:46.688837 == TX Byte 1 ==
5750 13:58:46.692523 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5751 13:58:46.695614 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5752 13:58:46.695694
5753 13:58:46.695758 [DATLAT]
5754 13:58:46.699132 Freq=933, CH1 RK0
5755 13:58:46.699213
5756 13:58:46.699276 DATLAT Default: 0xd
5757 13:58:46.702206 0, 0xFFFF, sum = 0
5758 13:58:46.705572 1, 0xFFFF, sum = 0
5759 13:58:46.705654 2, 0xFFFF, sum = 0
5760 13:58:46.708707 3, 0xFFFF, sum = 0
5761 13:58:46.708789 4, 0xFFFF, sum = 0
5762 13:58:46.712262 5, 0xFFFF, sum = 0
5763 13:58:46.712343 6, 0xFFFF, sum = 0
5764 13:58:46.715583 7, 0xFFFF, sum = 0
5765 13:58:46.715665 8, 0xFFFF, sum = 0
5766 13:58:46.718937 9, 0xFFFF, sum = 0
5767 13:58:46.719019 10, 0x0, sum = 1
5768 13:58:46.722124 11, 0x0, sum = 2
5769 13:58:46.722210 12, 0x0, sum = 3
5770 13:58:46.725587 13, 0x0, sum = 4
5771 13:58:46.725669 best_step = 11
5772 13:58:46.725733
5773 13:58:46.725792 ==
5774 13:58:46.728833 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 13:58:46.732126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 13:58:46.732206 ==
5777 13:58:46.735815 RX Vref Scan: 1
5778 13:58:46.735896
5779 13:58:46.735959 RX Vref 0 -> 0, step: 1
5780 13:58:46.738786
5781 13:58:46.738866 RX Delay -61 -> 252, step: 4
5782 13:58:46.738929
5783 13:58:46.742944 Set Vref, RX VrefLevel [Byte0]: 52
5784 13:58:46.745365 [Byte1]: 53
5785 13:58:46.750111
5786 13:58:46.750191 Final RX Vref Byte 0 = 52 to rank0
5787 13:58:46.753380 Final RX Vref Byte 1 = 53 to rank0
5788 13:58:46.756527 Final RX Vref Byte 0 = 52 to rank1
5789 13:58:46.760345 Final RX Vref Byte 1 = 53 to rank1==
5790 13:58:46.763157 Dram Type= 6, Freq= 0, CH_1, rank 0
5791 13:58:46.767495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 13:58:46.770196 ==
5793 13:58:46.770277 DQS Delay:
5794 13:58:46.770341 DQS0 = 0, DQS1 = 0
5795 13:58:46.773327 DQM Delay:
5796 13:58:46.773408 DQM0 = 98, DQM1 = 90
5797 13:58:46.777464 DQ Delay:
5798 13:58:46.780096 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =98
5799 13:58:46.783580 DQ4 =98, DQ5 =108, DQ6 =110, DQ7 =92
5800 13:58:46.783661 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =86
5801 13:58:46.790256 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =98
5802 13:58:46.790346
5803 13:58:46.790439
5804 13:58:46.797323 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5805 13:58:46.800325 CH1 RK0: MR19=504, MR18=17F3
5806 13:58:46.806898 CH1_RK0: MR19=0x504, MR18=0x17F3, DQSOSC=414, MR23=63, INC=63, DEC=42
5807 13:58:46.807002
5808 13:58:46.810541 ----->DramcWriteLeveling(PI) begin...
5809 13:58:46.810645 ==
5810 13:58:46.813924 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 13:58:46.816795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 13:58:46.816870 ==
5813 13:58:46.820397 Write leveling (Byte 0): 29 => 29
5814 13:58:46.823622 Write leveling (Byte 1): 30 => 30
5815 13:58:46.826938 DramcWriteLeveling(PI) end<-----
5816 13:58:46.827040
5817 13:58:46.827129 ==
5818 13:58:46.830399 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 13:58:46.833439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 13:58:46.833559 ==
5821 13:58:46.836977 [Gating] SW mode calibration
5822 13:58:46.843944 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5823 13:58:46.850076 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5824 13:58:46.853553 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 13:58:46.857088 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5826 13:58:46.863764 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5827 13:58:46.866698 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 13:58:46.870180 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5829 13:58:46.876928 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 13:58:46.880401 0 14 24 | B1->B0 | 3131 2f2f | 0 0 | (1 0) (1 1)
5831 13:58:46.883712 0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
5832 13:58:46.890438 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 13:58:46.894127 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 13:58:46.897221 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 13:58:46.903920 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5836 13:58:46.907193 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 13:58:46.910464 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 13:58:46.913680 0 15 24 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
5839 13:58:46.920164 0 15 28 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
5840 13:58:46.923735 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 13:58:46.926662 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 13:58:46.933780 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 13:58:46.936826 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 13:58:46.940112 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 13:58:46.947024 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 13:58:46.950149 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5847 13:58:46.953776 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5848 13:58:46.960393 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 13:58:46.964164 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 13:58:46.966922 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 13:58:46.973551 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 13:58:46.976865 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 13:58:46.980293 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 13:58:46.987300 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 13:58:46.990225 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 13:58:46.993961 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 13:58:46.997139 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 13:58:47.003846 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 13:58:47.007107 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 13:58:47.010314 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 13:58:47.016963 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 13:58:47.020231 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5863 13:58:47.023920 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5864 13:58:47.027049 Total UI for P1: 0, mck2ui 16
5865 13:58:47.030378 best dqsien dly found for B0: ( 1, 2, 24)
5866 13:58:47.037050 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 13:58:47.037130 Total UI for P1: 0, mck2ui 16
5868 13:58:47.044132 best dqsien dly found for B1: ( 1, 2, 28)
5869 13:58:47.047240 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5870 13:58:47.050232 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5871 13:58:47.050330
5872 13:58:47.053886 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5873 13:58:47.057047 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5874 13:58:47.060325 [Gating] SW calibration Done
5875 13:58:47.060426 ==
5876 13:58:47.064050 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 13:58:47.067137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 13:58:47.067235 ==
5879 13:58:47.070279 RX Vref Scan: 0
5880 13:58:47.070378
5881 13:58:47.070472 RX Vref 0 -> 0, step: 1
5882 13:58:47.070559
5883 13:58:47.074204 RX Delay -80 -> 252, step: 8
5884 13:58:47.077207 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5885 13:58:47.083717 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5886 13:58:47.087374 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5887 13:58:47.090389 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5888 13:58:47.093795 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5889 13:58:47.097486 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5890 13:58:47.100736 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5891 13:58:47.107045 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5892 13:58:47.110514 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5893 13:58:47.113683 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5894 13:58:47.117082 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5895 13:58:47.120496 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5896 13:58:47.123713 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5897 13:58:47.130617 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5898 13:58:47.133933 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5899 13:58:47.137261 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5900 13:58:47.137362 ==
5901 13:58:47.140656 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 13:58:47.143775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 13:58:47.143875 ==
5904 13:58:47.147512 DQS Delay:
5905 13:58:47.147608 DQS0 = 0, DQS1 = 0
5906 13:58:47.147694 DQM Delay:
5907 13:58:47.150463 DQM0 = 93, DQM1 = 88
5908 13:58:47.150563 DQ Delay:
5909 13:58:47.153921 DQ0 =95, DQ1 =87, DQ2 =79, DQ3 =95
5910 13:58:47.157309 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5911 13:58:47.161153 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5912 13:58:47.164128 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5913 13:58:47.164236
5914 13:58:47.164327
5915 13:58:47.164412 ==
5916 13:58:47.167622 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 13:58:47.174134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 13:58:47.174244 ==
5919 13:58:47.174335
5920 13:58:47.174420
5921 13:58:47.174516 TX Vref Scan disable
5922 13:58:47.177671 == TX Byte 0 ==
5923 13:58:47.180872 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5924 13:58:47.188119 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5925 13:58:47.188231 == TX Byte 1 ==
5926 13:58:47.191410 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5927 13:58:47.194270 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5928 13:58:47.197845 ==
5929 13:58:47.200997 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 13:58:47.204390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 13:58:47.204490 ==
5932 13:58:47.204587
5933 13:58:47.204683
5934 13:58:47.207795 TX Vref Scan disable
5935 13:58:47.207892 == TX Byte 0 ==
5936 13:58:47.214343 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5937 13:58:47.218041 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5938 13:58:47.218142 == TX Byte 1 ==
5939 13:58:47.224307 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5940 13:58:47.227929 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5941 13:58:47.228043
5942 13:58:47.228113 [DATLAT]
5943 13:58:47.231144 Freq=933, CH1 RK1
5944 13:58:47.231251
5945 13:58:47.231342 DATLAT Default: 0xb
5946 13:58:47.234202 0, 0xFFFF, sum = 0
5947 13:58:47.234302 1, 0xFFFF, sum = 0
5948 13:58:47.237703 2, 0xFFFF, sum = 0
5949 13:58:47.237805 3, 0xFFFF, sum = 0
5950 13:58:47.241526 4, 0xFFFF, sum = 0
5951 13:58:47.241602 5, 0xFFFF, sum = 0
5952 13:58:47.244374 6, 0xFFFF, sum = 0
5953 13:58:47.244481 7, 0xFFFF, sum = 0
5954 13:58:47.247996 8, 0xFFFF, sum = 0
5955 13:58:47.248108 9, 0xFFFF, sum = 0
5956 13:58:47.251508 10, 0x0, sum = 1
5957 13:58:47.251609 11, 0x0, sum = 2
5958 13:58:47.254417 12, 0x0, sum = 3
5959 13:58:47.254526 13, 0x0, sum = 4
5960 13:58:47.258153 best_step = 11
5961 13:58:47.258256
5962 13:58:47.258348 ==
5963 13:58:47.261103 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 13:58:47.264359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 13:58:47.264465 ==
5966 13:58:47.267885 RX Vref Scan: 0
5967 13:58:47.267982
5968 13:58:47.268082 RX Vref 0 -> 0, step: 1
5969 13:58:47.268168
5970 13:58:47.271278 RX Delay -61 -> 252, step: 4
5971 13:58:47.278138 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5972 13:58:47.281357 iDelay=199, Bit 1, Center 88 (-1 ~ 178) 180
5973 13:58:47.284636 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5974 13:58:47.287758 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5975 13:58:47.291376 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5976 13:58:47.294960 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5977 13:58:47.301075 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5978 13:58:47.304542 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5979 13:58:47.307893 iDelay=199, Bit 8, Center 84 (-5 ~ 174) 180
5980 13:58:47.311038 iDelay=199, Bit 9, Center 82 (-5 ~ 170) 176
5981 13:58:47.314563 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5982 13:58:47.317956 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5983 13:58:47.324493 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5984 13:58:47.327897 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5985 13:58:47.331179 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5986 13:58:47.334533 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5987 13:58:47.334630 ==
5988 13:58:47.338217 Dram Type= 6, Freq= 0, CH_1, rank 1
5989 13:58:47.341373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5990 13:58:47.341470 ==
5991 13:58:47.345098 DQS Delay:
5992 13:58:47.345186 DQS0 = 0, DQS1 = 0
5993 13:58:47.348383 DQM Delay:
5994 13:58:47.348479 DQM0 = 94, DQM1 = 91
5995 13:58:47.348576 DQ Delay:
5996 13:58:47.351513 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5997 13:58:47.355258 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =90
5998 13:58:47.357989 DQ8 =84, DQ9 =82, DQ10 =92, DQ11 =84
5999 13:58:47.361605 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
6000 13:58:47.361706
6001 13:58:47.361796
6002 13:58:47.372088 [DQSOSCAuto] RK1, (LSB)MR18= 0x131d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
6003 13:58:47.375206 CH1 RK1: MR19=505, MR18=131D
6004 13:58:47.378233 CH1_RK1: MR19=0x505, MR18=0x131D, DQSOSC=412, MR23=63, INC=63, DEC=42
6005 13:58:47.381458 [RxdqsGatingPostProcess] freq 933
6006 13:58:47.388206 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6007 13:58:47.391763 best DQS0 dly(2T, 0.5T) = (0, 11)
6008 13:58:47.395039 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 13:58:47.398503 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
6010 13:58:47.401653 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 13:58:47.405124 best DQS0 dly(2T, 0.5T) = (0, 10)
6012 13:58:47.408520 best DQS1 dly(2T, 0.5T) = (0, 10)
6013 13:58:47.411934 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6014 13:58:47.414955 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6015 13:58:47.415055 Pre-setting of DQS Precalculation
6016 13:58:47.421746 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6017 13:58:47.428511 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6018 13:58:47.435171 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6019 13:58:47.435275
6020 13:58:47.435364
6021 13:58:47.438525 [Calibration Summary] 1866 Mbps
6022 13:58:47.441711 CH 0, Rank 0
6023 13:58:47.441817 SW Impedance : PASS
6024 13:58:47.445198 DUTY Scan : NO K
6025 13:58:47.448259 ZQ Calibration : PASS
6026 13:58:47.448360 Jitter Meter : NO K
6027 13:58:47.451644 CBT Training : PASS
6028 13:58:47.451745 Write leveling : PASS
6029 13:58:47.455545 RX DQS gating : PASS
6030 13:58:47.458648 RX DQ/DQS(RDDQC) : PASS
6031 13:58:47.458756 TX DQ/DQS : PASS
6032 13:58:47.461894 RX DATLAT : PASS
6033 13:58:47.465544 RX DQ/DQS(Engine): PASS
6034 13:58:47.465647 TX OE : NO K
6035 13:58:47.468518 All Pass.
6036 13:58:47.468614
6037 13:58:47.468738 CH 0, Rank 1
6038 13:58:47.471946 SW Impedance : PASS
6039 13:58:47.472044 DUTY Scan : NO K
6040 13:58:47.475021 ZQ Calibration : PASS
6041 13:58:47.478631 Jitter Meter : NO K
6042 13:58:47.478730 CBT Training : PASS
6043 13:58:47.481640 Write leveling : PASS
6044 13:58:47.485258 RX DQS gating : PASS
6045 13:58:47.485358 RX DQ/DQS(RDDQC) : PASS
6046 13:58:47.488328 TX DQ/DQS : PASS
6047 13:58:47.491869 RX DATLAT : PASS
6048 13:58:47.491967 RX DQ/DQS(Engine): PASS
6049 13:58:47.495531 TX OE : NO K
6050 13:58:47.495632 All Pass.
6051 13:58:47.495734
6052 13:58:47.495823 CH 1, Rank 0
6053 13:58:47.498675 SW Impedance : PASS
6054 13:58:47.502085 DUTY Scan : NO K
6055 13:58:47.502184 ZQ Calibration : PASS
6056 13:58:47.505230 Jitter Meter : NO K
6057 13:58:47.509139 CBT Training : PASS
6058 13:58:47.509213 Write leveling : PASS
6059 13:58:47.512119 RX DQS gating : PASS
6060 13:58:47.515474 RX DQ/DQS(RDDQC) : PASS
6061 13:58:47.515549 TX DQ/DQS : PASS
6062 13:58:47.519194 RX DATLAT : PASS
6063 13:58:47.521976 RX DQ/DQS(Engine): PASS
6064 13:58:47.522077 TX OE : NO K
6065 13:58:47.522169 All Pass.
6066 13:58:47.522256
6067 13:58:47.525461 CH 1, Rank 1
6068 13:58:47.528611 SW Impedance : PASS
6069 13:58:47.528708 DUTY Scan : NO K
6070 13:58:47.531887 ZQ Calibration : PASS
6071 13:58:47.531984 Jitter Meter : NO K
6072 13:58:47.535261 CBT Training : PASS
6073 13:58:47.538575 Write leveling : PASS
6074 13:58:47.538675 RX DQS gating : PASS
6075 13:58:47.542110 RX DQ/DQS(RDDQC) : PASS
6076 13:58:47.545291 TX DQ/DQS : PASS
6077 13:58:47.545364 RX DATLAT : PASS
6078 13:58:47.548679 RX DQ/DQS(Engine): PASS
6079 13:58:47.552121 TX OE : NO K
6080 13:58:47.552222 All Pass.
6081 13:58:47.552311
6082 13:58:47.555599 DramC Write-DBI off
6083 13:58:47.555699 PER_BANK_REFRESH: Hybrid Mode
6084 13:58:47.558557 TX_TRACKING: ON
6085 13:58:47.565812 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6086 13:58:47.569037 [FAST_K] Save calibration result to emmc
6087 13:58:47.575388 dramc_set_vcore_voltage set vcore to 650000
6088 13:58:47.575490 Read voltage for 400, 6
6089 13:58:47.578581 Vio18 = 0
6090 13:58:47.578677 Vcore = 650000
6091 13:58:47.578756 Vdram = 0
6092 13:58:47.582235 Vddq = 0
6093 13:58:47.582336 Vmddr = 0
6094 13:58:47.585851 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6095 13:58:47.592022 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6096 13:58:47.595593 MEM_TYPE=3, freq_sel=20
6097 13:58:47.595703 sv_algorithm_assistance_LP4_800
6098 13:58:47.602201 ============ PULL DRAM RESETB DOWN ============
6099 13:58:47.605581 ========== PULL DRAM RESETB DOWN end =========
6100 13:58:47.609250 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6101 13:58:47.612322 ===================================
6102 13:58:47.615399 LPDDR4 DRAM CONFIGURATION
6103 13:58:47.618869 ===================================
6104 13:58:47.622389 EX_ROW_EN[0] = 0x0
6105 13:58:47.622493 EX_ROW_EN[1] = 0x0
6106 13:58:47.625700 LP4Y_EN = 0x0
6107 13:58:47.625780 WORK_FSP = 0x0
6108 13:58:47.629636 WL = 0x2
6109 13:58:47.629739 RL = 0x2
6110 13:58:47.632288 BL = 0x2
6111 13:58:47.632388 RPST = 0x0
6112 13:58:47.635740 RD_PRE = 0x0
6113 13:58:47.635842 WR_PRE = 0x1
6114 13:58:47.640138 WR_PST = 0x0
6115 13:58:47.640240 DBI_WR = 0x0
6116 13:58:47.642373 DBI_RD = 0x0
6117 13:58:47.642472 OTF = 0x1
6118 13:58:47.645571 ===================================
6119 13:58:47.648846 ===================================
6120 13:58:47.652319 ANA top config
6121 13:58:47.655886 ===================================
6122 13:58:47.658963 DLL_ASYNC_EN = 0
6123 13:58:47.659064 ALL_SLAVE_EN = 1
6124 13:58:47.662239 NEW_RANK_MODE = 1
6125 13:58:47.666307 DLL_IDLE_MODE = 1
6126 13:58:47.669156 LP45_APHY_COMB_EN = 1
6127 13:58:47.669257 TX_ODT_DIS = 1
6128 13:58:47.672426 NEW_8X_MODE = 1
6129 13:58:47.675616 ===================================
6130 13:58:47.679476 ===================================
6131 13:58:47.682614 data_rate = 800
6132 13:58:47.685805 CKR = 1
6133 13:58:47.689096 DQ_P2S_RATIO = 4
6134 13:58:47.692351 ===================================
6135 13:58:47.692456 CA_P2S_RATIO = 4
6136 13:58:47.695990 DQ_CA_OPEN = 0
6137 13:58:47.699469 DQ_SEMI_OPEN = 1
6138 13:58:47.702793 CA_SEMI_OPEN = 1
6139 13:58:47.705899 CA_FULL_RATE = 0
6140 13:58:47.709553 DQ_CKDIV4_EN = 0
6141 13:58:47.709655 CA_CKDIV4_EN = 1
6142 13:58:47.712604 CA_PREDIV_EN = 0
6143 13:58:47.715830 PH8_DLY = 0
6144 13:58:47.719617 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6145 13:58:47.722806 DQ_AAMCK_DIV = 0
6146 13:58:47.722907 CA_AAMCK_DIV = 0
6147 13:58:47.726134 CA_ADMCK_DIV = 4
6148 13:58:47.729301 DQ_TRACK_CA_EN = 0
6149 13:58:47.733000 CA_PICK = 800
6150 13:58:47.735862 CA_MCKIO = 400
6151 13:58:47.739378 MCKIO_SEMI = 400
6152 13:58:47.743012 PLL_FREQ = 3016
6153 13:58:47.743113 DQ_UI_PI_RATIO = 32
6154 13:58:47.746093 CA_UI_PI_RATIO = 32
6155 13:58:47.749570 ===================================
6156 13:58:47.753048 ===================================
6157 13:58:47.756224 memory_type:LPDDR4
6158 13:58:47.759676 GP_NUM : 10
6159 13:58:47.759778 SRAM_EN : 1
6160 13:58:47.762800 MD32_EN : 0
6161 13:58:47.766400 ===================================
6162 13:58:47.769665 [ANA_INIT] >>>>>>>>>>>>>>
6163 13:58:47.769768 <<<<<< [CONFIGURE PHASE]: ANA_TX
6164 13:58:47.773097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6165 13:58:47.776583 ===================================
6166 13:58:47.779959 data_rate = 800,PCW = 0X7400
6167 13:58:47.783327 ===================================
6168 13:58:47.786762 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6169 13:58:47.793365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6170 13:58:47.803093 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 13:58:47.810713 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6172 13:58:47.813587 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6173 13:58:47.817329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6174 13:58:47.817405 [ANA_INIT] flow start
6175 13:58:47.820410 [ANA_INIT] PLL >>>>>>>>
6176 13:58:47.823081 [ANA_INIT] PLL <<<<<<<<
6177 13:58:47.823182 [ANA_INIT] MIDPI >>>>>>>>
6178 13:58:47.826998 [ANA_INIT] MIDPI <<<<<<<<
6179 13:58:47.830245 [ANA_INIT] DLL >>>>>>>>
6180 13:58:47.830349 [ANA_INIT] flow end
6181 13:58:47.833666 ============ LP4 DIFF to SE enter ============
6182 13:58:47.840199 ============ LP4 DIFF to SE exit ============
6183 13:58:47.840303 [ANA_INIT] <<<<<<<<<<<<<
6184 13:58:47.843365 [Flow] Enable top DCM control >>>>>
6185 13:58:47.846639 [Flow] Enable top DCM control <<<<<
6186 13:58:47.849948 Enable DLL master slave shuffle
6187 13:58:47.856815 ==============================================================
6188 13:58:47.856918 Gating Mode config
6189 13:58:47.863446 ==============================================================
6190 13:58:47.866569 Config description:
6191 13:58:47.876570 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6192 13:58:47.883326 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6193 13:58:47.886855 SELPH_MODE 0: By rank 1: By Phase
6194 13:58:47.893559 ==============================================================
6195 13:58:47.896714 GAT_TRACK_EN = 0
6196 13:58:47.900266 RX_GATING_MODE = 2
6197 13:58:47.900367 RX_GATING_TRACK_MODE = 2
6198 13:58:47.903554 SELPH_MODE = 1
6199 13:58:47.906736 PICG_EARLY_EN = 1
6200 13:58:47.910027 VALID_LAT_VALUE = 1
6201 13:58:47.916863 ==============================================================
6202 13:58:47.919834 Enter into Gating configuration >>>>
6203 13:58:47.923601 Exit from Gating configuration <<<<
6204 13:58:47.926536 Enter into DVFS_PRE_config >>>>>
6205 13:58:47.936452 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6206 13:58:47.939856 Exit from DVFS_PRE_config <<<<<
6207 13:58:47.943218 Enter into PICG configuration >>>>
6208 13:58:47.946631 Exit from PICG configuration <<<<
6209 13:58:47.950243 [RX_INPUT] configuration >>>>>
6210 13:58:47.953544 [RX_INPUT] configuration <<<<<
6211 13:58:47.956645 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6212 13:58:47.963363 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6213 13:58:47.970202 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6214 13:58:47.973750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6215 13:58:47.980397 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6216 13:58:47.987484 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6217 13:58:47.990374 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6218 13:58:47.993441 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6219 13:58:48.000268 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6220 13:58:48.003512 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6221 13:58:48.007278 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6222 13:58:48.013619 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 13:58:48.016843 ===================================
6224 13:58:48.016978 LPDDR4 DRAM CONFIGURATION
6225 13:58:48.020405 ===================================
6226 13:58:48.023940 EX_ROW_EN[0] = 0x0
6227 13:58:48.024178 EX_ROW_EN[1] = 0x0
6228 13:58:48.026914 LP4Y_EN = 0x0
6229 13:58:48.027083 WORK_FSP = 0x0
6230 13:58:48.030851 WL = 0x2
6231 13:58:48.031049 RL = 0x2
6232 13:58:48.033644 BL = 0x2
6233 13:58:48.033749 RPST = 0x0
6234 13:58:48.037160 RD_PRE = 0x0
6235 13:58:48.040129 WR_PRE = 0x1
6236 13:58:48.040208 WR_PST = 0x0
6237 13:58:48.043454 DBI_WR = 0x0
6238 13:58:48.043535 DBI_RD = 0x0
6239 13:58:48.046901 OTF = 0x1
6240 13:58:48.050476 ===================================
6241 13:58:48.053579 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6242 13:58:48.057437 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6243 13:58:48.060286 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6244 13:58:48.064082 ===================================
6245 13:58:48.067243 LPDDR4 DRAM CONFIGURATION
6246 13:58:48.070257 ===================================
6247 13:58:48.073814 EX_ROW_EN[0] = 0x10
6248 13:58:48.073910 EX_ROW_EN[1] = 0x0
6249 13:58:48.077271 LP4Y_EN = 0x0
6250 13:58:48.077369 WORK_FSP = 0x0
6251 13:58:48.080388 WL = 0x2
6252 13:58:48.080504 RL = 0x2
6253 13:58:48.083891 BL = 0x2
6254 13:58:48.083992 RPST = 0x0
6255 13:58:48.086791 RD_PRE = 0x0
6256 13:58:48.086885 WR_PRE = 0x1
6257 13:58:48.090433 WR_PST = 0x0
6258 13:58:48.090529 DBI_WR = 0x0
6259 13:58:48.093686 DBI_RD = 0x0
6260 13:58:48.093794 OTF = 0x1
6261 13:58:48.096991 ===================================
6262 13:58:48.103848 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6263 13:58:48.108778 nWR fixed to 30
6264 13:58:48.111484 [ModeRegInit_LP4] CH0 RK0
6265 13:58:48.111571 [ModeRegInit_LP4] CH0 RK1
6266 13:58:48.115027 [ModeRegInit_LP4] CH1 RK0
6267 13:58:48.118289 [ModeRegInit_LP4] CH1 RK1
6268 13:58:48.118370 match AC timing 19
6269 13:58:48.125573 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6270 13:58:48.128291 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6271 13:58:48.131918 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6272 13:58:48.138699 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6273 13:58:48.141863 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6274 13:58:48.141944 ==
6275 13:58:48.145337 Dram Type= 6, Freq= 0, CH_0, rank 0
6276 13:58:48.148671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 13:58:48.148815 ==
6278 13:58:48.155162 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6279 13:58:48.161709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6280 13:58:48.165485 [CA 0] Center 36 (8~64) winsize 57
6281 13:58:48.168828 [CA 1] Center 36 (8~64) winsize 57
6282 13:58:48.168909 [CA 2] Center 36 (8~64) winsize 57
6283 13:58:48.171889 [CA 3] Center 36 (8~64) winsize 57
6284 13:58:48.175164 [CA 4] Center 36 (8~64) winsize 57
6285 13:58:48.178927 [CA 5] Center 36 (8~64) winsize 57
6286 13:58:48.179007
6287 13:58:48.182189 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6288 13:58:48.182296
6289 13:58:48.185248 [CATrainingPosCal] consider 1 rank data
6290 13:58:48.188456 u2DelayCellTimex100 = 270/100 ps
6291 13:58:48.191940 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 13:58:48.198326 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 13:58:48.202142 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 13:58:48.205051 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 13:58:48.208592 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 13:58:48.211817 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 13:58:48.211898
6298 13:58:48.215001 CA PerBit enable=1, Macro0, CA PI delay=36
6299 13:58:48.215082
6300 13:58:48.218400 [CBTSetCACLKResult] CA Dly = 36
6301 13:58:48.218481 CS Dly: 1 (0~32)
6302 13:58:48.222169 ==
6303 13:58:48.225373 Dram Type= 6, Freq= 0, CH_0, rank 1
6304 13:58:48.228527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 13:58:48.228608 ==
6306 13:58:48.232391 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6307 13:58:48.238691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6308 13:58:48.241966 [CA 0] Center 36 (8~64) winsize 57
6309 13:58:48.245850 [CA 1] Center 36 (8~64) winsize 57
6310 13:58:48.248312 [CA 2] Center 36 (8~64) winsize 57
6311 13:58:48.252395 [CA 3] Center 36 (8~64) winsize 57
6312 13:58:48.255267 [CA 4] Center 36 (8~64) winsize 57
6313 13:58:48.258817 [CA 5] Center 36 (8~64) winsize 57
6314 13:58:48.258897
6315 13:58:48.262050 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6316 13:58:48.262130
6317 13:58:48.265553 [CATrainingPosCal] consider 2 rank data
6318 13:58:48.268844 u2DelayCellTimex100 = 270/100 ps
6319 13:58:48.271794 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 13:58:48.275230 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 13:58:48.278879 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 13:58:48.282552 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 13:58:48.285564 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 13:58:48.289008 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 13:58:48.291929
6326 13:58:48.295218 CA PerBit enable=1, Macro0, CA PI delay=36
6327 13:58:48.295298
6328 13:58:48.299091 [CBTSetCACLKResult] CA Dly = 36
6329 13:58:48.299172 CS Dly: 1 (0~32)
6330 13:58:48.299236
6331 13:58:48.302270 ----->DramcWriteLeveling(PI) begin...
6332 13:58:48.302386 ==
6333 13:58:48.305881 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 13:58:48.309111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 13:58:48.309217 ==
6336 13:58:48.312188 Write leveling (Byte 0): 40 => 8
6337 13:58:48.315354 Write leveling (Byte 1): 32 => 0
6338 13:58:48.319009 DramcWriteLeveling(PI) end<-----
6339 13:58:48.319114
6340 13:58:48.319205 ==
6341 13:58:48.322542 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 13:58:48.325571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 13:58:48.329105 ==
6344 13:58:48.329204 [Gating] SW mode calibration
6345 13:58:48.335844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6346 13:58:48.342061 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6347 13:58:48.345938 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6348 13:58:48.352207 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 13:58:48.355698 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6350 13:58:48.358608 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 13:58:48.365477 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 13:58:48.369206 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 13:58:48.372350 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 13:58:48.378834 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 13:58:48.381948 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 13:58:48.385552 Total UI for P1: 0, mck2ui 16
6357 13:58:48.388909 best dqsien dly found for B0: ( 0, 14, 24)
6358 13:58:48.392293 Total UI for P1: 0, mck2ui 16
6359 13:58:48.395293 best dqsien dly found for B1: ( 0, 14, 24)
6360 13:58:48.398685 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6361 13:58:48.401880 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6362 13:58:48.401976
6363 13:58:48.405431 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6364 13:58:48.408702 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 13:58:48.411818 [Gating] SW calibration Done
6366 13:58:48.411913 ==
6367 13:58:48.415493 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 13:58:48.418758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 13:58:48.418858 ==
6370 13:58:48.422198 RX Vref Scan: 0
6371 13:58:48.422292
6372 13:58:48.425482 RX Vref 0 -> 0, step: 1
6373 13:58:48.425576
6374 13:58:48.425665 RX Delay -410 -> 252, step: 16
6375 13:58:48.432479 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6376 13:58:48.435703 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6377 13:58:48.438901 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6378 13:58:48.442256 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6379 13:58:48.449143 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6380 13:58:48.452412 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6381 13:58:48.455780 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6382 13:58:48.459319 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6383 13:58:48.466279 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6384 13:58:48.469423 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6385 13:58:48.472208 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6386 13:58:48.475506 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6387 13:58:48.482686 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6388 13:58:48.486163 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6389 13:58:48.489056 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6390 13:58:48.492520 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6391 13:58:48.495701 ==
6392 13:58:48.499554 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 13:58:48.502788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 13:58:48.502875 ==
6395 13:58:48.502943 DQS Delay:
6396 13:58:48.505878 DQS0 = 35, DQS1 = 51
6397 13:58:48.505970 DQM Delay:
6398 13:58:48.509652 DQM0 = 7, DQM1 = 10
6399 13:58:48.509752 DQ Delay:
6400 13:58:48.513087 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6401 13:58:48.516438 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6402 13:58:48.516547 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6403 13:58:48.519797 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6404 13:58:48.519916
6405 13:58:48.522585
6406 13:58:48.522703 ==
6407 13:58:48.525996 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 13:58:48.529593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 13:58:48.529764 ==
6410 13:58:48.529930
6411 13:58:48.530071
6412 13:58:48.532990 TX Vref Scan disable
6413 13:58:48.533137 == TX Byte 0 ==
6414 13:58:48.536183 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 13:58:48.542969 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 13:58:48.543166 == TX Byte 1 ==
6417 13:58:48.546217 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6418 13:58:48.552948 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6419 13:58:48.553240 ==
6420 13:58:48.556555 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 13:58:48.560143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 13:58:48.560556 ==
6423 13:58:48.560934
6424 13:58:48.561247
6425 13:58:48.563188 TX Vref Scan disable
6426 13:58:48.563635 == TX Byte 0 ==
6427 13:58:48.566693 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6428 13:58:48.572865 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6429 13:58:48.572986 == TX Byte 1 ==
6430 13:58:48.576302 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6431 13:58:48.582801 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6432 13:58:48.582903
6433 13:58:48.582982 [DATLAT]
6434 13:58:48.583071 Freq=400, CH0 RK0
6435 13:58:48.586312
6436 13:58:48.586448 DATLAT Default: 0xf
6437 13:58:48.589759 0, 0xFFFF, sum = 0
6438 13:58:48.589869 1, 0xFFFF, sum = 0
6439 13:58:48.592917 2, 0xFFFF, sum = 0
6440 13:58:48.593024 3, 0xFFFF, sum = 0
6441 13:58:48.596586 4, 0xFFFF, sum = 0
6442 13:58:48.596756 5, 0xFFFF, sum = 0
6443 13:58:48.600037 6, 0xFFFF, sum = 0
6444 13:58:48.600188 7, 0xFFFF, sum = 0
6445 13:58:48.603656 8, 0xFFFF, sum = 0
6446 13:58:48.603876 9, 0xFFFF, sum = 0
6447 13:58:48.606490 10, 0xFFFF, sum = 0
6448 13:58:48.606709 11, 0xFFFF, sum = 0
6449 13:58:48.609622 12, 0xFFFF, sum = 0
6450 13:58:48.609846 13, 0x0, sum = 1
6451 13:58:48.612996 14, 0x0, sum = 2
6452 13:58:48.613201 15, 0x0, sum = 3
6453 13:58:48.617101 16, 0x0, sum = 4
6454 13:58:48.617326 best_step = 14
6455 13:58:48.617507
6456 13:58:48.617675 ==
6457 13:58:48.620237 Dram Type= 6, Freq= 0, CH_0, rank 0
6458 13:58:48.622890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 13:58:48.626758 ==
6460 13:58:48.627136 RX Vref Scan: 1
6461 13:58:48.627433
6462 13:58:48.630413 RX Vref 0 -> 0, step: 1
6463 13:58:48.630823
6464 13:58:48.633381 RX Delay -343 -> 252, step: 8
6465 13:58:48.633793
6466 13:58:48.636374 Set Vref, RX VrefLevel [Byte0]: 54
6467 13:58:48.639594 [Byte1]: 52
6468 13:58:48.639673
6469 13:58:48.642984 Final RX Vref Byte 0 = 54 to rank0
6470 13:58:48.646194 Final RX Vref Byte 1 = 52 to rank0
6471 13:58:48.649443 Final RX Vref Byte 0 = 54 to rank1
6472 13:58:48.653338 Final RX Vref Byte 1 = 52 to rank1==
6473 13:58:48.656356 Dram Type= 6, Freq= 0, CH_0, rank 0
6474 13:58:48.659688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 13:58:48.659768 ==
6476 13:58:48.662798 DQS Delay:
6477 13:58:48.662878 DQS0 = 44, DQS1 = 60
6478 13:58:48.666250 DQM Delay:
6479 13:58:48.666329 DQM0 = 11, DQM1 = 15
6480 13:58:48.666393 DQ Delay:
6481 13:58:48.669554 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6482 13:58:48.673111 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6483 13:58:48.676083 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6484 13:58:48.679202 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6485 13:58:48.679283
6486 13:58:48.679346
6487 13:58:48.689697 [DQSOSCAuto] RK0, (LSB)MR18= 0x9260, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6488 13:58:48.692691 CH0 RK0: MR19=C0C, MR18=9260
6489 13:58:48.696127 CH0_RK0: MR19=0xC0C, MR18=0x9260, DQSOSC=391, MR23=63, INC=386, DEC=257
6490 13:58:48.699225 ==
6491 13:58:48.703144 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 13:58:48.706156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 13:58:48.706236 ==
6494 13:58:48.709565 [Gating] SW mode calibration
6495 13:58:48.716003 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6496 13:58:48.719422 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6497 13:58:48.725890 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6498 13:58:48.729396 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 13:58:48.732919 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 13:58:48.739145 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 13:58:48.742548 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 13:58:48.746798 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 13:58:48.752914 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 13:58:48.755937 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 13:58:48.759313 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 13:58:48.762723 Total UI for P1: 0, mck2ui 16
6507 13:58:48.766284 best dqsien dly found for B0: ( 0, 14, 24)
6508 13:58:48.769510 Total UI for P1: 0, mck2ui 16
6509 13:58:48.772644 best dqsien dly found for B1: ( 0, 14, 24)
6510 13:58:48.776042 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6511 13:58:48.779512 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6512 13:58:48.779598
6513 13:58:48.782971 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6514 13:58:48.789323 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 13:58:48.789406 [Gating] SW calibration Done
6516 13:58:48.789470 ==
6517 13:58:48.792554 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 13:58:48.799425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 13:58:48.799501 ==
6520 13:58:48.799570 RX Vref Scan: 0
6521 13:58:48.799633
6522 13:58:48.802687 RX Vref 0 -> 0, step: 1
6523 13:58:48.802759
6524 13:58:48.806031 RX Delay -410 -> 252, step: 16
6525 13:58:48.809359 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6526 13:58:48.812723 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6527 13:58:48.816358 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6528 13:58:48.822823 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6529 13:58:48.826251 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6530 13:58:48.830000 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6531 13:58:48.833182 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6532 13:58:48.839743 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6533 13:58:48.842777 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6534 13:58:48.846601 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6535 13:58:48.849832 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6536 13:58:48.856282 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6537 13:58:48.859620 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6538 13:58:48.863115 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6539 13:58:48.866492 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6540 13:58:48.873349 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6541 13:58:48.873465 ==
6542 13:58:48.876300 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 13:58:48.879765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 13:58:48.879878 ==
6545 13:58:48.879968 DQS Delay:
6546 13:58:48.883151 DQS0 = 43, DQS1 = 51
6547 13:58:48.883228 DQM Delay:
6548 13:58:48.886649 DQM0 = 11, DQM1 = 10
6549 13:58:48.886722 DQ Delay:
6550 13:58:48.889670 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6551 13:58:48.893264 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6552 13:58:48.896569 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6553 13:58:48.899736 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6554 13:58:48.899816
6555 13:58:48.899879
6556 13:58:48.899937 ==
6557 13:58:48.903334 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 13:58:48.906760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 13:58:48.906840 ==
6560 13:58:48.906904
6561 13:58:48.906961
6562 13:58:48.909711 TX Vref Scan disable
6563 13:58:48.909804 == TX Byte 0 ==
6564 13:58:48.916564 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6565 13:58:48.920016 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6566 13:58:48.920096 == TX Byte 1 ==
6567 13:58:48.926779 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6568 13:58:48.929902 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6569 13:58:48.929982 ==
6570 13:58:48.933092 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 13:58:48.936469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 13:58:48.936552 ==
6573 13:58:48.936615
6574 13:58:48.936698
6575 13:58:48.939971 TX Vref Scan disable
6576 13:58:48.940051 == TX Byte 0 ==
6577 13:58:48.946973 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6578 13:58:48.950077 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6579 13:58:48.950158 == TX Byte 1 ==
6580 13:58:48.956810 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6581 13:58:48.960093 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6582 13:58:48.960173
6583 13:58:48.960237 [DATLAT]
6584 13:58:48.963307 Freq=400, CH0 RK1
6585 13:58:48.963388
6586 13:58:48.963452 DATLAT Default: 0xe
6587 13:58:48.966648 0, 0xFFFF, sum = 0
6588 13:58:48.966730 1, 0xFFFF, sum = 0
6589 13:58:48.969855 2, 0xFFFF, sum = 0
6590 13:58:48.969936 3, 0xFFFF, sum = 0
6591 13:58:48.973023 4, 0xFFFF, sum = 0
6592 13:58:48.973105 5, 0xFFFF, sum = 0
6593 13:58:48.976703 6, 0xFFFF, sum = 0
6594 13:58:48.976797 7, 0xFFFF, sum = 0
6595 13:58:48.980101 8, 0xFFFF, sum = 0
6596 13:58:48.980183 9, 0xFFFF, sum = 0
6597 13:58:48.983297 10, 0xFFFF, sum = 0
6598 13:58:48.986828 11, 0xFFFF, sum = 0
6599 13:58:48.986911 12, 0xFFFF, sum = 0
6600 13:58:48.989936 13, 0x0, sum = 1
6601 13:58:48.990018 14, 0x0, sum = 2
6602 13:58:48.990083 15, 0x0, sum = 3
6603 13:58:48.993206 16, 0x0, sum = 4
6604 13:58:48.993291 best_step = 14
6605 13:58:48.993382
6606 13:58:48.993461 ==
6607 13:58:48.997034 Dram Type= 6, Freq= 0, CH_0, rank 1
6608 13:58:49.003141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 13:58:49.003222 ==
6610 13:58:49.003306 RX Vref Scan: 0
6611 13:58:49.003383
6612 13:58:49.006709 RX Vref 0 -> 0, step: 1
6613 13:58:49.006785
6614 13:58:49.009954 RX Delay -343 -> 252, step: 8
6615 13:58:49.016776 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6616 13:58:49.020220 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6617 13:58:49.023740 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6618 13:58:49.026939 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6619 13:58:49.033859 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6620 13:58:49.036825 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6621 13:58:49.040215 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6622 13:58:49.043499 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6623 13:58:49.050224 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6624 13:58:49.053444 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6625 13:58:49.056837 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6626 13:58:49.060193 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6627 13:58:49.066869 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6628 13:58:49.070105 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6629 13:58:49.073598 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6630 13:58:49.077184 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6631 13:58:49.077265 ==
6632 13:58:49.080487 Dram Type= 6, Freq= 0, CH_0, rank 1
6633 13:58:49.086689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 13:58:49.086770 ==
6635 13:58:49.086862 DQS Delay:
6636 13:58:49.089946 DQS0 = 48, DQS1 = 60
6637 13:58:49.090020 DQM Delay:
6638 13:58:49.093657 DQM0 = 13, DQM1 = 13
6639 13:58:49.093731 DQ Delay:
6640 13:58:49.096755 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6641 13:58:49.100723 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6642 13:58:49.103411 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6643 13:58:49.107057 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6644 13:58:49.107136
6645 13:58:49.107219
6646 13:58:49.113369 [DQSOSCAuto] RK1, (LSB)MR18= 0xa073, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 389 ps
6647 13:58:49.117022 CH0 RK1: MR19=C0C, MR18=A073
6648 13:58:49.123403 CH0_RK1: MR19=0xC0C, MR18=0xA073, DQSOSC=389, MR23=63, INC=390, DEC=260
6649 13:58:49.126853 [RxdqsGatingPostProcess] freq 400
6650 13:58:49.130013 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6651 13:58:49.133682 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 13:58:49.136583 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 13:58:49.140277 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 13:58:49.143561 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 13:58:49.146749 best DQS0 dly(2T, 0.5T) = (0, 10)
6656 13:58:49.150716 best DQS1 dly(2T, 0.5T) = (0, 10)
6657 13:58:49.153573 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6658 13:58:49.157521 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6659 13:58:49.159984 Pre-setting of DQS Precalculation
6660 13:58:49.163641 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6661 13:58:49.163721 ==
6662 13:58:49.167132 Dram Type= 6, Freq= 0, CH_1, rank 0
6663 13:58:49.173429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 13:58:49.173508 ==
6665 13:58:49.176939 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6666 13:58:49.183470 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6667 13:58:49.186979 [CA 0] Center 36 (8~64) winsize 57
6668 13:58:49.190561 [CA 1] Center 36 (8~64) winsize 57
6669 13:58:49.194236 [CA 2] Center 36 (8~64) winsize 57
6670 13:58:49.197332 [CA 3] Center 36 (8~64) winsize 57
6671 13:58:49.200289 [CA 4] Center 36 (8~64) winsize 57
6672 13:58:49.203715 [CA 5] Center 36 (8~64) winsize 57
6673 13:58:49.203793
6674 13:58:49.206907 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6675 13:58:49.206982
6676 13:58:49.210287 [CATrainingPosCal] consider 1 rank data
6677 13:58:49.213581 u2DelayCellTimex100 = 270/100 ps
6678 13:58:49.217078 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 13:58:49.220469 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 13:58:49.223622 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 13:58:49.227239 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 13:58:49.230383 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 13:58:49.233931 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 13:58:49.234007
6685 13:58:49.236994 CA PerBit enable=1, Macro0, CA PI delay=36
6686 13:58:49.240464
6687 13:58:49.240537 [CBTSetCACLKResult] CA Dly = 36
6688 13:58:49.243595 CS Dly: 1 (0~32)
6689 13:58:49.243666 ==
6690 13:58:49.247284 Dram Type= 6, Freq= 0, CH_1, rank 1
6691 13:58:49.250718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 13:58:49.250796 ==
6693 13:58:49.257176 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6694 13:58:49.263753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6695 13:58:49.267378 [CA 0] Center 36 (8~64) winsize 57
6696 13:58:49.270280 [CA 1] Center 36 (8~64) winsize 57
6697 13:58:49.270356 [CA 2] Center 36 (8~64) winsize 57
6698 13:58:49.274076 [CA 3] Center 36 (8~64) winsize 57
6699 13:58:49.277043 [CA 4] Center 36 (8~64) winsize 57
6700 13:58:49.280481 [CA 5] Center 36 (8~64) winsize 57
6701 13:58:49.280554
6702 13:58:49.283821 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6703 13:58:49.283903
6704 13:58:49.290450 [CATrainingPosCal] consider 2 rank data
6705 13:58:49.290535 u2DelayCellTimex100 = 270/100 ps
6706 13:58:49.293527 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 13:58:49.300961 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 13:58:49.303746 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 13:58:49.307035 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 13:58:49.310275 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 13:58:49.313660 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 13:58:49.313737
6713 13:58:49.316992 CA PerBit enable=1, Macro0, CA PI delay=36
6714 13:58:49.317079
6715 13:58:49.320250 [CBTSetCACLKResult] CA Dly = 36
6716 13:58:49.320328 CS Dly: 1 (0~32)
6717 13:58:49.323762
6718 13:58:49.327075 ----->DramcWriteLeveling(PI) begin...
6719 13:58:49.327153 ==
6720 13:58:49.330273 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 13:58:49.333648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 13:58:49.333723 ==
6723 13:58:49.337232 Write leveling (Byte 0): 40 => 8
6724 13:58:49.340498 Write leveling (Byte 1): 40 => 8
6725 13:58:49.343934 DramcWriteLeveling(PI) end<-----
6726 13:58:49.344013
6727 13:58:49.344097 ==
6728 13:58:49.347063 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 13:58:49.350307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 13:58:49.350386 ==
6731 13:58:49.353693 [Gating] SW mode calibration
6732 13:58:49.360823 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6733 13:58:49.363556 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6734 13:58:49.370350 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6735 13:58:49.373814 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6736 13:58:49.377200 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6737 13:58:49.383967 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 13:58:49.386943 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 13:58:49.390907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 13:58:49.397472 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 13:58:49.400557 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 13:58:49.403982 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 13:58:49.407323 Total UI for P1: 0, mck2ui 16
6744 13:58:49.410902 best dqsien dly found for B0: ( 0, 14, 24)
6745 13:58:49.413727 Total UI for P1: 0, mck2ui 16
6746 13:58:49.417298 best dqsien dly found for B1: ( 0, 14, 24)
6747 13:58:49.420944 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6748 13:58:49.423783 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6749 13:58:49.423858
6750 13:58:49.430700 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6751 13:58:49.434119 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 13:58:49.434196 [Gating] SW calibration Done
6753 13:58:49.437508 ==
6754 13:58:49.437587 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 13:58:49.444102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 13:58:49.444182 ==
6757 13:58:49.444247 RX Vref Scan: 0
6758 13:58:49.444308
6759 13:58:49.447316 RX Vref 0 -> 0, step: 1
6760 13:58:49.447403
6761 13:58:49.450953 RX Delay -410 -> 252, step: 16
6762 13:58:49.454165 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6763 13:58:49.457554 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6764 13:58:49.464414 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6765 13:58:49.468044 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6766 13:58:49.470566 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6767 13:58:49.474076 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6768 13:58:49.480526 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6769 13:58:49.484152 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6770 13:58:49.487925 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6771 13:58:49.490913 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6772 13:58:49.497701 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6773 13:58:49.500972 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6774 13:58:49.504613 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6775 13:58:49.507898 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6776 13:58:49.514342 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6777 13:58:49.518082 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6778 13:58:49.518163 ==
6779 13:58:49.520972 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 13:58:49.524434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 13:58:49.524515 ==
6782 13:58:49.527605 DQS Delay:
6783 13:58:49.527685 DQS0 = 51, DQS1 = 59
6784 13:58:49.527749 DQM Delay:
6785 13:58:49.531158 DQM0 = 19, DQM1 = 17
6786 13:58:49.531238 DQ Delay:
6787 13:58:49.534775 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6788 13:58:49.538178 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6789 13:58:49.540940 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6790 13:58:49.544401 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6791 13:58:49.544482
6792 13:58:49.544545
6793 13:58:49.544604 ==
6794 13:58:49.547807 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 13:58:49.551006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 13:58:49.554754 ==
6797 13:58:49.554834
6798 13:58:49.554897
6799 13:58:49.554956 TX Vref Scan disable
6800 13:58:49.557793 == TX Byte 0 ==
6801 13:58:49.561340 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 13:58:49.564633 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 13:58:49.568141 == TX Byte 1 ==
6804 13:58:49.571364 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 13:58:49.575119 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 13:58:49.575228 ==
6807 13:58:49.577671 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 13:58:49.581105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 13:58:49.584514 ==
6810 13:58:49.584630
6811 13:58:49.584754
6812 13:58:49.584816 TX Vref Scan disable
6813 13:58:49.588023 == TX Byte 0 ==
6814 13:58:49.591188 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 13:58:49.594457 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 13:58:49.598150 == TX Byte 1 ==
6817 13:58:49.601214 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6818 13:58:49.604508 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6819 13:58:49.604614
6820 13:58:49.604739 [DATLAT]
6821 13:58:49.607961 Freq=400, CH1 RK0
6822 13:58:49.608041
6823 13:58:49.611470 DATLAT Default: 0xf
6824 13:58:49.611550 0, 0xFFFF, sum = 0
6825 13:58:49.614906 1, 0xFFFF, sum = 0
6826 13:58:49.614988 2, 0xFFFF, sum = 0
6827 13:58:49.618099 3, 0xFFFF, sum = 0
6828 13:58:49.618181 4, 0xFFFF, sum = 0
6829 13:58:49.621750 5, 0xFFFF, sum = 0
6830 13:58:49.621832 6, 0xFFFF, sum = 0
6831 13:58:49.624821 7, 0xFFFF, sum = 0
6832 13:58:49.624903 8, 0xFFFF, sum = 0
6833 13:58:49.628261 9, 0xFFFF, sum = 0
6834 13:58:49.628343 10, 0xFFFF, sum = 0
6835 13:58:49.631262 11, 0xFFFF, sum = 0
6836 13:58:49.631352 12, 0xFFFF, sum = 0
6837 13:58:49.634966 13, 0x0, sum = 1
6838 13:58:49.635048 14, 0x0, sum = 2
6839 13:58:49.638349 15, 0x0, sum = 3
6840 13:58:49.638431 16, 0x0, sum = 4
6841 13:58:49.641294 best_step = 14
6842 13:58:49.641374
6843 13:58:49.641438 ==
6844 13:58:49.644787 Dram Type= 6, Freq= 0, CH_1, rank 0
6845 13:58:49.647916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 13:58:49.647996 ==
6847 13:58:49.648060 RX Vref Scan: 1
6848 13:58:49.651764
6849 13:58:49.651844 RX Vref 0 -> 0, step: 1
6850 13:58:49.651908
6851 13:58:49.654960 RX Delay -359 -> 252, step: 8
6852 13:58:49.655041
6853 13:58:49.658281 Set Vref, RX VrefLevel [Byte0]: 52
6854 13:58:49.661709 [Byte1]: 53
6855 13:58:49.665415
6856 13:58:49.665495 Final RX Vref Byte 0 = 52 to rank0
6857 13:58:49.668859 Final RX Vref Byte 1 = 53 to rank0
6858 13:58:49.672223 Final RX Vref Byte 0 = 52 to rank1
6859 13:58:49.675429 Final RX Vref Byte 1 = 53 to rank1==
6860 13:58:49.678854 Dram Type= 6, Freq= 0, CH_1, rank 0
6861 13:58:49.685457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 13:58:49.685539 ==
6863 13:58:49.685604 DQS Delay:
6864 13:58:49.689057 DQS0 = 48, DQS1 = 64
6865 13:58:49.689138 DQM Delay:
6866 13:58:49.689226 DQM0 = 12, DQM1 = 16
6867 13:58:49.692431 DQ Delay:
6868 13:58:49.695410 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6869 13:58:49.695491 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6870 13:58:49.698990 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =16
6871 13:58:49.702068 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6872 13:58:49.702149
6873 13:58:49.705634
6874 13:58:49.712523 [DQSOSCAuto] RK0, (LSB)MR18= 0x943a, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
6875 13:58:49.715599 CH1 RK0: MR19=C0C, MR18=943A
6876 13:58:49.722549 CH1_RK0: MR19=0xC0C, MR18=0x943A, DQSOSC=391, MR23=63, INC=386, DEC=257
6877 13:58:49.722630 ==
6878 13:58:49.725912 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 13:58:49.729249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 13:58:49.729356 ==
6881 13:58:49.733160 [Gating] SW mode calibration
6882 13:58:49.739092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6883 13:58:49.742321 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6884 13:58:49.748946 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6885 13:58:49.752595 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 13:58:49.755499 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6887 13:58:49.762438 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 13:58:49.765610 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 13:58:49.768936 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 13:58:49.776284 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 13:58:49.779009 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 13:58:49.782722 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 13:58:49.786123 Total UI for P1: 0, mck2ui 16
6894 13:58:49.789487 best dqsien dly found for B0: ( 0, 14, 24)
6895 13:58:49.793255 Total UI for P1: 0, mck2ui 16
6896 13:58:49.796136 best dqsien dly found for B1: ( 0, 14, 24)
6897 13:58:49.799457 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6898 13:58:49.802832 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6899 13:58:49.802913
6900 13:58:49.806388 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6901 13:58:49.812977 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 13:58:49.813058 [Gating] SW calibration Done
6903 13:58:49.813122 ==
6904 13:58:49.816163 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 13:58:49.823205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 13:58:49.823286 ==
6907 13:58:49.823353 RX Vref Scan: 0
6908 13:58:49.823415
6909 13:58:49.825950 RX Vref 0 -> 0, step: 1
6910 13:58:49.826023
6911 13:58:49.829531 RX Delay -410 -> 252, step: 16
6912 13:58:49.833167 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6913 13:58:49.836425 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6914 13:58:49.842857 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6915 13:58:49.846005 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6916 13:58:49.849340 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6917 13:58:49.853084 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6918 13:58:49.859440 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6919 13:58:49.863135 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6920 13:58:49.866024 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6921 13:58:49.869167 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6922 13:58:49.875958 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6923 13:58:49.879415 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6924 13:58:49.882556 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6925 13:58:49.885999 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6926 13:58:49.892856 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6927 13:58:49.896011 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6928 13:58:49.896085 ==
6929 13:58:49.899537 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 13:58:49.902957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 13:58:49.903040 ==
6932 13:58:49.906154 DQS Delay:
6933 13:58:49.906234 DQS0 = 51, DQS1 = 59
6934 13:58:49.906298 DQM Delay:
6935 13:58:49.909752 DQM0 = 18, DQM1 = 20
6936 13:58:49.909832 DQ Delay:
6937 13:58:49.912833 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6938 13:58:49.916278 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6939 13:58:49.919677 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6940 13:58:49.922728 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6941 13:58:49.922808
6942 13:58:49.922871
6943 13:58:49.922929 ==
6944 13:58:49.926148 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 13:58:49.929656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 13:58:49.933091 ==
6947 13:58:49.933171
6948 13:58:49.933235
6949 13:58:49.933294 TX Vref Scan disable
6950 13:58:49.936513 == TX Byte 0 ==
6951 13:58:49.939519 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6952 13:58:49.943107 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6953 13:58:49.946496 == TX Byte 1 ==
6954 13:58:49.949935 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6955 13:58:49.953331 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6956 13:58:49.953411 ==
6957 13:58:49.956263 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 13:58:49.959959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 13:58:49.960040 ==
6960 13:58:49.963147
6961 13:58:49.963227
6962 13:58:49.963322 TX Vref Scan disable
6963 13:58:49.966350 == TX Byte 0 ==
6964 13:58:49.969950 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6965 13:58:49.973608 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6966 13:58:49.976592 == TX Byte 1 ==
6967 13:58:49.980149 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6968 13:58:49.983269 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6969 13:58:49.983350
6970 13:58:49.983413 [DATLAT]
6971 13:58:49.986807 Freq=400, CH1 RK1
6972 13:58:49.986887
6973 13:58:49.986952 DATLAT Default: 0xe
6974 13:58:49.989896 0, 0xFFFF, sum = 0
6975 13:58:49.989978 1, 0xFFFF, sum = 0
6976 13:58:49.993691 2, 0xFFFF, sum = 0
6977 13:58:49.993773 3, 0xFFFF, sum = 0
6978 13:58:49.996525 4, 0xFFFF, sum = 0
6979 13:58:49.996633 5, 0xFFFF, sum = 0
6980 13:58:50.000407 6, 0xFFFF, sum = 0
6981 13:58:50.003591 7, 0xFFFF, sum = 0
6982 13:58:50.003673 8, 0xFFFF, sum = 0
6983 13:58:50.006681 9, 0xFFFF, sum = 0
6984 13:58:50.006762 10, 0xFFFF, sum = 0
6985 13:58:50.010200 11, 0xFFFF, sum = 0
6986 13:58:50.010282 12, 0xFFFF, sum = 0
6987 13:58:50.013240 13, 0x0, sum = 1
6988 13:58:50.013322 14, 0x0, sum = 2
6989 13:58:50.016695 15, 0x0, sum = 3
6990 13:58:50.016790 16, 0x0, sum = 4
6991 13:58:50.016856 best_step = 14
6992 13:58:50.016915
6993 13:58:50.020209 ==
6994 13:58:50.023635 Dram Type= 6, Freq= 0, CH_1, rank 1
6995 13:58:50.027060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6996 13:58:50.027155 ==
6997 13:58:50.027221 RX Vref Scan: 0
6998 13:58:50.027281
6999 13:58:50.030508 RX Vref 0 -> 0, step: 1
7000 13:58:50.030588
7001 13:58:50.033392 RX Delay -359 -> 252, step: 8
7002 13:58:50.040797 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7003 13:58:50.043590 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7004 13:58:50.047003 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7005 13:58:50.050851 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7006 13:58:50.057130 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7007 13:58:50.060616 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7008 13:58:50.064134 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7009 13:58:50.067254 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7010 13:58:50.074010 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7011 13:58:50.077068 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7012 13:58:50.080670 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7013 13:58:50.083946 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7014 13:58:50.090784 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7015 13:58:50.094117 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7016 13:58:50.098096 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7017 13:58:50.100528 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7018 13:58:50.103913 ==
7019 13:58:50.103994 Dram Type= 6, Freq= 0, CH_1, rank 1
7020 13:58:50.110708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7021 13:58:50.110808 ==
7022 13:58:50.110885 DQS Delay:
7023 13:58:50.113998 DQS0 = 52, DQS1 = 56
7024 13:58:50.114078 DQM Delay:
7025 13:58:50.117276 DQM0 = 13, DQM1 = 9
7026 13:58:50.117356 DQ Delay:
7027 13:58:50.121265 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7028 13:58:50.124518 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7029 13:58:50.124599 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7030 13:58:50.127668 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7031 13:58:50.130753
7032 13:58:50.130833
7033 13:58:50.138168 [DQSOSCAuto] RK1, (LSB)MR18= 0x7d92, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
7034 13:58:50.140883 CH1 RK1: MR19=C0C, MR18=7D92
7035 13:58:50.147912 CH1_RK1: MR19=0xC0C, MR18=0x7D92, DQSOSC=391, MR23=63, INC=386, DEC=257
7036 13:58:50.150996 [RxdqsGatingPostProcess] freq 400
7037 13:58:50.154010 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7038 13:58:50.157410 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 13:58:50.160806 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 13:58:50.163988 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 13:58:50.167450 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 13:58:50.170852 best DQS0 dly(2T, 0.5T) = (0, 10)
7043 13:58:50.174415 best DQS1 dly(2T, 0.5T) = (0, 10)
7044 13:58:50.177660 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7045 13:58:50.181078 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7046 13:58:50.184127 Pre-setting of DQS Precalculation
7047 13:58:50.187588 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7048 13:58:50.194677 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7049 13:58:50.204416 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7050 13:58:50.204497
7051 13:58:50.204563
7052 13:58:50.204622 [Calibration Summary] 800 Mbps
7053 13:58:50.207744 CH 0, Rank 0
7054 13:58:50.207831 SW Impedance : PASS
7055 13:58:50.210715 DUTY Scan : NO K
7056 13:58:50.214713 ZQ Calibration : PASS
7057 13:58:50.214788 Jitter Meter : NO K
7058 13:58:50.217605 CBT Training : PASS
7059 13:58:50.220826 Write leveling : PASS
7060 13:58:50.220898 RX DQS gating : PASS
7061 13:58:50.224113 RX DQ/DQS(RDDQC) : PASS
7062 13:58:50.227500 TX DQ/DQS : PASS
7063 13:58:50.227577 RX DATLAT : PASS
7064 13:58:50.230985 RX DQ/DQS(Engine): PASS
7065 13:58:50.234253 TX OE : NO K
7066 13:58:50.234335 All Pass.
7067 13:58:50.234398
7068 13:58:50.234454 CH 0, Rank 1
7069 13:58:50.237508 SW Impedance : PASS
7070 13:58:50.240647 DUTY Scan : NO K
7071 13:58:50.240725 ZQ Calibration : PASS
7072 13:58:50.244617 Jitter Meter : NO K
7073 13:58:50.244698 CBT Training : PASS
7074 13:58:50.247525 Write leveling : NO K
7075 13:58:50.250864 RX DQS gating : PASS
7076 13:58:50.250934 RX DQ/DQS(RDDQC) : PASS
7077 13:58:50.254274 TX DQ/DQS : PASS
7078 13:58:50.257733 RX DATLAT : PASS
7079 13:58:50.257806 RX DQ/DQS(Engine): PASS
7080 13:58:50.260963 TX OE : NO K
7081 13:58:50.261031 All Pass.
7082 13:58:50.261091
7083 13:58:50.264565 CH 1, Rank 0
7084 13:58:50.264641 SW Impedance : PASS
7085 13:58:50.267790 DUTY Scan : NO K
7086 13:58:50.271097 ZQ Calibration : PASS
7087 13:58:50.271169 Jitter Meter : NO K
7088 13:58:50.274600 CBT Training : PASS
7089 13:58:50.277685 Write leveling : PASS
7090 13:58:50.277756 RX DQS gating : PASS
7091 13:58:50.281249 RX DQ/DQS(RDDQC) : PASS
7092 13:58:50.281326 TX DQ/DQS : PASS
7093 13:58:50.284480 RX DATLAT : PASS
7094 13:58:50.287754 RX DQ/DQS(Engine): PASS
7095 13:58:50.287832 TX OE : NO K
7096 13:58:50.291206 All Pass.
7097 13:58:50.291279
7098 13:58:50.291339 CH 1, Rank 1
7099 13:58:50.294916 SW Impedance : PASS
7100 13:58:50.294991 DUTY Scan : NO K
7101 13:58:50.297850 ZQ Calibration : PASS
7102 13:58:50.301100 Jitter Meter : NO K
7103 13:58:50.301170 CBT Training : PASS
7104 13:58:50.304799 Write leveling : NO K
7105 13:58:50.307925 RX DQS gating : PASS
7106 13:58:50.307997 RX DQ/DQS(RDDQC) : PASS
7107 13:58:50.311229 TX DQ/DQS : PASS
7108 13:58:50.314891 RX DATLAT : PASS
7109 13:58:50.314964 RX DQ/DQS(Engine): PASS
7110 13:58:50.318287 TX OE : NO K
7111 13:58:50.318361 All Pass.
7112 13:58:50.318422
7113 13:58:50.321431 DramC Write-DBI off
7114 13:58:50.324567 PER_BANK_REFRESH: Hybrid Mode
7115 13:58:50.324635 TX_TRACKING: ON
7116 13:58:50.335025 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7117 13:58:50.337894 [FAST_K] Save calibration result to emmc
7118 13:58:50.341418 dramc_set_vcore_voltage set vcore to 725000
7119 13:58:50.344611 Read voltage for 1600, 0
7120 13:58:50.344721 Vio18 = 0
7121 13:58:50.344782 Vcore = 725000
7122 13:58:50.344839 Vdram = 0
7123 13:58:50.348195 Vddq = 0
7124 13:58:50.348259 Vmddr = 0
7125 13:58:50.354837 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7126 13:58:50.357791 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7127 13:58:50.361634 MEM_TYPE=3, freq_sel=13
7128 13:58:50.364610 sv_algorithm_assistance_LP4_3733
7129 13:58:50.367859 ============ PULL DRAM RESETB DOWN ============
7130 13:58:50.371145 ========== PULL DRAM RESETB DOWN end =========
7131 13:58:50.378416 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7132 13:58:50.381406 ===================================
7133 13:58:50.381477 LPDDR4 DRAM CONFIGURATION
7134 13:58:50.384817 ===================================
7135 13:58:50.388644 EX_ROW_EN[0] = 0x0
7136 13:58:50.388760 EX_ROW_EN[1] = 0x0
7137 13:58:50.391422 LP4Y_EN = 0x0
7138 13:58:50.391493 WORK_FSP = 0x1
7139 13:58:50.394991 WL = 0x5
7140 13:58:50.395115 RL = 0x5
7141 13:58:50.398610 BL = 0x2
7142 13:58:50.401529 RPST = 0x0
7143 13:58:50.401601 RD_PRE = 0x0
7144 13:58:50.404760 WR_PRE = 0x1
7145 13:58:50.404848 WR_PST = 0x1
7146 13:58:50.408053 DBI_WR = 0x0
7147 13:58:50.408133 DBI_RD = 0x0
7148 13:58:50.411326 OTF = 0x1
7149 13:58:50.415331 ===================================
7150 13:58:50.418168 ===================================
7151 13:58:50.418303 ANA top config
7152 13:58:50.421791 ===================================
7153 13:58:50.425233 DLL_ASYNC_EN = 0
7154 13:58:50.428390 ALL_SLAVE_EN = 0
7155 13:58:50.428471 NEW_RANK_MODE = 1
7156 13:58:50.431658 DLL_IDLE_MODE = 1
7157 13:58:50.435136 LP45_APHY_COMB_EN = 1
7158 13:58:50.438196 TX_ODT_DIS = 0
7159 13:58:50.438276 NEW_8X_MODE = 1
7160 13:58:50.441894 ===================================
7161 13:58:50.445060 ===================================
7162 13:58:50.448501 data_rate = 3200
7163 13:58:50.451691 CKR = 1
7164 13:58:50.455247 DQ_P2S_RATIO = 8
7165 13:58:50.458243 ===================================
7166 13:58:50.462255 CA_P2S_RATIO = 8
7167 13:58:50.462335 DQ_CA_OPEN = 0
7168 13:58:50.465272 DQ_SEMI_OPEN = 0
7169 13:58:50.468426 CA_SEMI_OPEN = 0
7170 13:58:50.471529 CA_FULL_RATE = 0
7171 13:58:50.474958 DQ_CKDIV4_EN = 0
7172 13:58:50.478928 CA_CKDIV4_EN = 0
7173 13:58:50.479009 CA_PREDIV_EN = 0
7174 13:58:50.481918 PH8_DLY = 12
7175 13:58:50.485644 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7176 13:58:50.488529 DQ_AAMCK_DIV = 4
7177 13:58:50.492220 CA_AAMCK_DIV = 4
7178 13:58:50.495705 CA_ADMCK_DIV = 4
7179 13:58:50.495786 DQ_TRACK_CA_EN = 0
7180 13:58:50.498773 CA_PICK = 1600
7181 13:58:50.502454 CA_MCKIO = 1600
7182 13:58:50.505355 MCKIO_SEMI = 0
7183 13:58:50.508992 PLL_FREQ = 3068
7184 13:58:50.512115 DQ_UI_PI_RATIO = 32
7185 13:58:50.515492 CA_UI_PI_RATIO = 0
7186 13:58:50.518937 ===================================
7187 13:58:50.521958 ===================================
7188 13:58:50.522039 memory_type:LPDDR4
7189 13:58:50.525440 GP_NUM : 10
7190 13:58:50.525521 SRAM_EN : 1
7191 13:58:50.528869 MD32_EN : 0
7192 13:58:50.532362 ===================================
7193 13:58:50.535887 [ANA_INIT] >>>>>>>>>>>>>>
7194 13:58:50.539029 <<<<<< [CONFIGURE PHASE]: ANA_TX
7195 13:58:50.542209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7196 13:58:50.545747 ===================================
7197 13:58:50.545828 data_rate = 3200,PCW = 0X7600
7198 13:58:50.548798 ===================================
7199 13:58:50.552285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7200 13:58:50.559120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7201 13:58:50.566043 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 13:58:50.568981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7203 13:58:50.572415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7204 13:58:50.575590 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7205 13:58:50.579397 [ANA_INIT] flow start
7206 13:58:50.579478 [ANA_INIT] PLL >>>>>>>>
7207 13:58:50.582265 [ANA_INIT] PLL <<<<<<<<
7208 13:58:50.585863 [ANA_INIT] MIDPI >>>>>>>>
7209 13:58:50.589155 [ANA_INIT] MIDPI <<<<<<<<
7210 13:58:50.589235 [ANA_INIT] DLL >>>>>>>>
7211 13:58:50.593096 [ANA_INIT] DLL <<<<<<<<
7212 13:58:50.593176 [ANA_INIT] flow end
7213 13:58:50.599293 ============ LP4 DIFF to SE enter ============
7214 13:58:50.602654 ============ LP4 DIFF to SE exit ============
7215 13:58:50.606225 [ANA_INIT] <<<<<<<<<<<<<
7216 13:58:50.609281 [Flow] Enable top DCM control >>>>>
7217 13:58:50.612682 [Flow] Enable top DCM control <<<<<
7218 13:58:50.612763 Enable DLL master slave shuffle
7219 13:58:50.619222 ==============================================================
7220 13:58:50.622912 Gating Mode config
7221 13:58:50.625794 ==============================================================
7222 13:58:50.629403 Config description:
7223 13:58:50.639402 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7224 13:58:50.646274 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7225 13:58:50.649547 SELPH_MODE 0: By rank 1: By Phase
7226 13:58:50.656228 ==============================================================
7227 13:58:50.659172 GAT_TRACK_EN = 1
7228 13:58:50.662902 RX_GATING_MODE = 2
7229 13:58:50.666036 RX_GATING_TRACK_MODE = 2
7230 13:58:50.666116 SELPH_MODE = 1
7231 13:58:50.669243 PICG_EARLY_EN = 1
7232 13:58:50.672800 VALID_LAT_VALUE = 1
7233 13:58:50.679627 ==============================================================
7234 13:58:50.682535 Enter into Gating configuration >>>>
7235 13:58:50.686341 Exit from Gating configuration <<<<
7236 13:58:50.689400 Enter into DVFS_PRE_config >>>>>
7237 13:58:50.699346 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7238 13:58:50.702794 Exit from DVFS_PRE_config <<<<<
7239 13:58:50.706076 Enter into PICG configuration >>>>
7240 13:58:50.709385 Exit from PICG configuration <<<<
7241 13:58:50.713015 [RX_INPUT] configuration >>>>>
7242 13:58:50.716275 [RX_INPUT] configuration <<<<<
7243 13:58:50.719341 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7244 13:58:50.725998 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7245 13:58:50.732957 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7246 13:58:50.736576 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7247 13:58:50.742806 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7248 13:58:50.749770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7249 13:58:50.753105 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7250 13:58:50.756254 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7251 13:58:50.762952 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7252 13:58:50.766501 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7253 13:58:50.769787 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7254 13:58:50.776290 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 13:58:50.779635 ===================================
7256 13:58:50.779716 LPDDR4 DRAM CONFIGURATION
7257 13:58:50.783000 ===================================
7258 13:58:50.786105 EX_ROW_EN[0] = 0x0
7259 13:58:50.786186 EX_ROW_EN[1] = 0x0
7260 13:58:50.789671 LP4Y_EN = 0x0
7261 13:58:50.793020 WORK_FSP = 0x1
7262 13:58:50.793101 WL = 0x5
7263 13:58:50.796462 RL = 0x5
7264 13:58:50.796568 BL = 0x2
7265 13:58:50.799667 RPST = 0x0
7266 13:58:50.799747 RD_PRE = 0x0
7267 13:58:50.803182 WR_PRE = 0x1
7268 13:58:50.803263 WR_PST = 0x1
7269 13:58:50.806506 DBI_WR = 0x0
7270 13:58:50.806586 DBI_RD = 0x0
7271 13:58:50.809943 OTF = 0x1
7272 13:58:50.813185 ===================================
7273 13:58:50.816898 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7274 13:58:50.819682 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7275 13:58:50.823357 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7276 13:58:50.826919 ===================================
7277 13:58:50.830145 LPDDR4 DRAM CONFIGURATION
7278 13:58:50.833736 ===================================
7279 13:58:50.836737 EX_ROW_EN[0] = 0x10
7280 13:58:50.836818 EX_ROW_EN[1] = 0x0
7281 13:58:50.840522 LP4Y_EN = 0x0
7282 13:58:50.840602 WORK_FSP = 0x1
7283 13:58:50.843601 WL = 0x5
7284 13:58:50.843681 RL = 0x5
7285 13:58:50.846680 BL = 0x2
7286 13:58:50.846760 RPST = 0x0
7287 13:58:50.850228 RD_PRE = 0x0
7288 13:58:50.850308 WR_PRE = 0x1
7289 13:58:50.853235 WR_PST = 0x1
7290 13:58:50.853316 DBI_WR = 0x0
7291 13:58:50.856992 DBI_RD = 0x0
7292 13:58:50.857072 OTF = 0x1
7293 13:58:50.859858 ===================================
7294 13:58:50.866776 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7295 13:58:50.866858 ==
7296 13:58:50.870114 Dram Type= 6, Freq= 0, CH_0, rank 0
7297 13:58:50.876900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 13:58:50.876981 ==
7299 13:58:50.877045 [Duty_Offset_Calibration]
7300 13:58:50.879848 B0:2 B1:-1 CA:1
7301 13:58:50.879928
7302 13:58:50.883397 [DutyScan_Calibration_Flow] k_type=0
7303 13:58:50.892036
7304 13:58:50.892117 ==CLK 0==
7305 13:58:50.895105 Final CLK duty delay cell = -4
7306 13:58:50.898517 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7307 13:58:50.901924 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7308 13:58:50.905210 [-4] AVG Duty = 4937%(X100)
7309 13:58:50.905291
7310 13:58:50.908577 CH0 CLK Duty spec in!! Max-Min= 187%
7311 13:58:50.911662 [DutyScan_Calibration_Flow] ====Done====
7312 13:58:50.911743
7313 13:58:50.915245 [DutyScan_Calibration_Flow] k_type=1
7314 13:58:50.931019
7315 13:58:50.931105 ==DQS 0 ==
7316 13:58:50.934643 Final DQS duty delay cell = 0
7317 13:58:50.938118 [0] MAX Duty = 5125%(X100), DQS PI = 46
7318 13:58:50.941391 [0] MIN Duty = 5000%(X100), DQS PI = 16
7319 13:58:50.941468 [0] AVG Duty = 5062%(X100)
7320 13:58:50.944605
7321 13:58:50.944702 ==DQS 1 ==
7322 13:58:50.948022 Final DQS duty delay cell = -4
7323 13:58:50.951358 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7324 13:58:50.954582 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7325 13:58:50.958120 [-4] AVG Duty = 5046%(X100)
7326 13:58:50.958196
7327 13:58:50.961276 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7328 13:58:50.961354
7329 13:58:50.965016 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7330 13:58:50.968181 [DutyScan_Calibration_Flow] ====Done====
7331 13:58:50.968258
7332 13:58:50.971767 [DutyScan_Calibration_Flow] k_type=3
7333 13:58:50.988903
7334 13:58:50.988983 ==DQM 0 ==
7335 13:58:50.991808 Final DQM duty delay cell = 0
7336 13:58:50.995627 [0] MAX Duty = 5000%(X100), DQS PI = 18
7337 13:58:50.998478 [0] MIN Duty = 4844%(X100), DQS PI = 6
7338 13:58:50.998547 [0] AVG Duty = 4922%(X100)
7339 13:58:51.002232
7340 13:58:51.002305 ==DQM 1 ==
7341 13:58:51.005421 Final DQM duty delay cell = 0
7342 13:58:51.008832 [0] MAX Duty = 5218%(X100), DQS PI = 58
7343 13:58:51.011720 [0] MIN Duty = 4969%(X100), DQS PI = 20
7344 13:58:51.015091 [0] AVG Duty = 5093%(X100)
7345 13:58:51.015164
7346 13:58:51.018319 CH0 DQM 0 Duty spec in!! Max-Min= 156%
7347 13:58:51.018389
7348 13:58:51.021773 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7349 13:58:51.025153 [DutyScan_Calibration_Flow] ====Done====
7350 13:58:51.025229
7351 13:58:51.028523 [DutyScan_Calibration_Flow] k_type=2
7352 13:58:51.044772
7353 13:58:51.044857 ==DQ 0 ==
7354 13:58:51.048561 Final DQ duty delay cell = -4
7355 13:58:51.052005 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7356 13:58:51.055475 [-4] MIN Duty = 4844%(X100), DQS PI = 26
7357 13:58:51.058717 [-4] AVG Duty = 4922%(X100)
7358 13:58:51.058793
7359 13:58:51.058856 ==DQ 1 ==
7360 13:58:51.062226 Final DQ duty delay cell = 0
7361 13:58:51.065101 [0] MAX Duty = 5031%(X100), DQS PI = 30
7362 13:58:51.068495 [0] MIN Duty = 4907%(X100), DQS PI = 18
7363 13:58:51.068570 [0] AVG Duty = 4969%(X100)
7364 13:58:51.071744
7365 13:58:51.075197 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7366 13:58:51.075267
7367 13:58:51.078407 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7368 13:58:51.081786 [DutyScan_Calibration_Flow] ====Done====
7369 13:58:51.081854 ==
7370 13:58:51.084938 Dram Type= 6, Freq= 0, CH_1, rank 0
7371 13:58:51.088327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7372 13:58:51.088404 ==
7373 13:58:51.092020 [Duty_Offset_Calibration]
7374 13:58:51.092093 B0:1 B1:1 CA:2
7375 13:58:51.092153
7376 13:58:51.094945 [DutyScan_Calibration_Flow] k_type=0
7377 13:58:51.105428
7378 13:58:51.105501 ==CLK 0==
7379 13:58:51.108776 Final CLK duty delay cell = 0
7380 13:58:51.112055 [0] MAX Duty = 5187%(X100), DQS PI = 24
7381 13:58:51.115575 [0] MIN Duty = 4969%(X100), DQS PI = 40
7382 13:58:51.115645 [0] AVG Duty = 5078%(X100)
7383 13:58:51.118686
7384 13:58:51.121984 CH1 CLK Duty spec in!! Max-Min= 218%
7385 13:58:51.125409 [DutyScan_Calibration_Flow] ====Done====
7386 13:58:51.125481
7387 13:58:51.128947 [DutyScan_Calibration_Flow] k_type=1
7388 13:58:51.145127
7389 13:58:51.145206 ==DQS 0 ==
7390 13:58:51.148565 Final DQS duty delay cell = 0
7391 13:58:51.151839 [0] MAX Duty = 5062%(X100), DQS PI = 20
7392 13:58:51.155720 [0] MIN Duty = 4813%(X100), DQS PI = 52
7393 13:58:51.158561 [0] AVG Duty = 4937%(X100)
7394 13:58:51.158630
7395 13:58:51.158691 ==DQS 1 ==
7396 13:58:51.162088 Final DQS duty delay cell = 0
7397 13:58:51.165047 [0] MAX Duty = 5062%(X100), DQS PI = 34
7398 13:58:51.168461 [0] MIN Duty = 4938%(X100), DQS PI = 14
7399 13:58:51.171771 [0] AVG Duty = 5000%(X100)
7400 13:58:51.171840
7401 13:58:51.175560 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7402 13:58:51.175632
7403 13:58:51.178459 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7404 13:58:51.181945 [DutyScan_Calibration_Flow] ====Done====
7405 13:58:51.182014
7406 13:58:51.185676 [DutyScan_Calibration_Flow] k_type=3
7407 13:58:51.202451
7408 13:58:51.202532 ==DQM 0 ==
7409 13:58:51.205417 Final DQM duty delay cell = 0
7410 13:58:51.209312 [0] MAX Duty = 5187%(X100), DQS PI = 20
7411 13:58:51.212123 [0] MIN Duty = 4844%(X100), DQS PI = 50
7412 13:58:51.212205 [0] AVG Duty = 5015%(X100)
7413 13:58:51.215417
7414 13:58:51.215487 ==DQM 1 ==
7415 13:58:51.219075 Final DQM duty delay cell = 0
7416 13:58:51.222017 [0] MAX Duty = 5125%(X100), DQS PI = 8
7417 13:58:51.225387 [0] MIN Duty = 4907%(X100), DQS PI = 20
7418 13:58:51.225460 [0] AVG Duty = 5016%(X100)
7419 13:58:51.228741
7420 13:58:51.232083 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7421 13:58:51.232154
7422 13:58:51.235629 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7423 13:58:51.240166 [DutyScan_Calibration_Flow] ====Done====
7424 13:58:51.240245
7425 13:58:51.241959 [DutyScan_Calibration_Flow] k_type=2
7426 13:58:51.259110
7427 13:58:51.259186 ==DQ 0 ==
7428 13:58:51.262360 Final DQ duty delay cell = 0
7429 13:58:51.265774 [0] MAX Duty = 5156%(X100), DQS PI = 20
7430 13:58:51.269157 [0] MIN Duty = 4938%(X100), DQS PI = 52
7431 13:58:51.269233 [0] AVG Duty = 5047%(X100)
7432 13:58:51.269296
7433 13:58:51.272432 ==DQ 1 ==
7434 13:58:51.275770 Final DQ duty delay cell = 0
7435 13:58:51.278904 [0] MAX Duty = 5093%(X100), DQS PI = 6
7436 13:58:51.282195 [0] MIN Duty = 5031%(X100), DQS PI = 2
7437 13:58:51.282268 [0] AVG Duty = 5062%(X100)
7438 13:58:51.282328
7439 13:58:51.285584 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7440 13:58:51.285661
7441 13:58:51.289112 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7442 13:58:51.295700 [DutyScan_Calibration_Flow] ====Done====
7443 13:58:51.299305 nWR fixed to 30
7444 13:58:51.299375 [ModeRegInit_LP4] CH0 RK0
7445 13:58:51.302621 [ModeRegInit_LP4] CH0 RK1
7446 13:58:51.305624 [ModeRegInit_LP4] CH1 RK0
7447 13:58:51.305696 [ModeRegInit_LP4] CH1 RK1
7448 13:58:51.308949 match AC timing 5
7449 13:58:51.312822 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7450 13:58:51.315657 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7451 13:58:51.322266 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7452 13:58:51.325904 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7453 13:58:51.332829 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7454 13:58:51.332910 [MiockJmeterHQA]
7455 13:58:51.332975
7456 13:58:51.335687 [DramcMiockJmeter] u1RxGatingPI = 0
7457 13:58:51.335755 0 : 4363, 4137
7458 13:58:51.339365 4 : 4255, 4030
7459 13:58:51.339436 8 : 4252, 4027
7460 13:58:51.342329 12 : 4253, 4026
7461 13:58:51.342403 16 : 4252, 4027
7462 13:58:51.345599 20 : 4252, 4027
7463 13:58:51.345670 24 : 4253, 4027
7464 13:58:51.345730 28 : 4363, 4138
7465 13:58:51.349455 32 : 4253, 4026
7466 13:58:51.349548 36 : 4252, 4027
7467 13:58:51.352377 40 : 4252, 4027
7468 13:58:51.352449 44 : 4255, 4029
7469 13:58:51.355715 48 : 4252, 4027
7470 13:58:51.355786 52 : 4363, 4137
7471 13:58:51.359299 56 : 4363, 4138
7472 13:58:51.359370 60 : 4250, 4027
7473 13:58:51.359432 64 : 4253, 4026
7474 13:58:51.362493 68 : 4250, 4027
7475 13:58:51.362559 72 : 4250, 4027
7476 13:58:51.365956 76 : 4252, 4030
7477 13:58:51.366027 80 : 4360, 4137
7478 13:58:51.369346 84 : 4253, 4026
7479 13:58:51.369420 88 : 4250, 4027
7480 13:58:51.369482 92 : 4250, 4027
7481 13:58:51.372941 96 : 4252, 3435
7482 13:58:51.373014 100 : 4250, 0
7483 13:58:51.376275 104 : 4253, 0
7484 13:58:51.376345 108 : 4363, 0
7485 13:58:51.376408 112 : 4249, 0
7486 13:58:51.379622 116 : 4361, 0
7487 13:58:51.379733 120 : 4250, 0
7488 13:58:51.382728 124 : 4250, 0
7489 13:58:51.382809 128 : 4363, 0
7490 13:58:51.382874 132 : 4252, 0
7491 13:58:51.386299 136 : 4253, 0
7492 13:58:51.386388 140 : 4249, 0
7493 13:58:51.386453 144 : 4253, 0
7494 13:58:51.389500 148 : 4250, 0
7495 13:58:51.389585 152 : 4250, 0
7496 13:58:51.392954 156 : 4253, 0
7497 13:58:51.393036 160 : 4363, 0
7498 13:58:51.393101 164 : 4250, 0
7499 13:58:51.396385 168 : 4250, 0
7500 13:58:51.396466 172 : 4361, 0
7501 13:58:51.399572 176 : 4360, 0
7502 13:58:51.399654 180 : 4250, 0
7503 13:58:51.399752 184 : 4250, 0
7504 13:58:51.403228 188 : 4250, 0
7505 13:58:51.403310 192 : 4250, 0
7506 13:58:51.406464 196 : 4250, 0
7507 13:58:51.406546 200 : 4250, 0
7508 13:58:51.406610 204 : 4250, 0
7509 13:58:51.409836 208 : 4253, 0
7510 13:58:51.409931 212 : 4360, 23
7511 13:58:51.413079 216 : 4250, 3485
7512 13:58:51.413161 220 : 4250, 4027
7513 13:58:51.413226 224 : 4360, 4137
7514 13:58:51.416599 228 : 4250, 4026
7515 13:58:51.416705 232 : 4250, 4027
7516 13:58:51.420254 236 : 4361, 4137
7517 13:58:51.420336 240 : 4250, 4027
7518 13:58:51.423019 244 : 4250, 4026
7519 13:58:51.423101 248 : 4363, 4140
7520 13:58:51.426642 252 : 4250, 4027
7521 13:58:51.426723 256 : 4252, 4027
7522 13:58:51.429670 260 : 4250, 4026
7523 13:58:51.429752 264 : 4253, 4029
7524 13:58:51.433226 268 : 4250, 4027
7525 13:58:51.433308 272 : 4250, 4027
7526 13:58:51.433373 276 : 4360, 4137
7527 13:58:51.436425 280 : 4250, 4027
7528 13:58:51.436506 284 : 4250, 4027
7529 13:58:51.440240 288 : 4361, 4138
7530 13:58:51.440321 292 : 4250, 4027
7531 13:58:51.443089 296 : 4250, 4026
7532 13:58:51.443171 300 : 4363, 4140
7533 13:58:51.446311 304 : 4250, 4027
7534 13:58:51.446392 308 : 4250, 4027
7535 13:58:51.449954 312 : 4250, 4026
7536 13:58:51.450046 316 : 4253, 4029
7537 13:58:51.453668 320 : 4250, 4027
7538 13:58:51.453746 324 : 4250, 4027
7539 13:58:51.453828 328 : 4360, 4137
7540 13:58:51.456460 332 : 4250, 3077
7541 13:58:51.456533 336 : 4250, 79
7542 13:58:51.456643
7543 13:58:51.459652 MIOCK jitter meter ch=0
7544 13:58:51.459724
7545 13:58:51.463210 1T = (336-100) = 236 dly cells
7546 13:58:51.469976 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7547 13:58:51.470063 ==
7548 13:58:51.473607 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 13:58:51.476335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 13:58:51.476415 ==
7551 13:58:51.483433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7552 13:58:51.486545 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7553 13:58:51.489953 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7554 13:58:51.496828 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7555 13:58:51.505321 [CA 0] Center 44 (14~75) winsize 62
7556 13:58:51.508661 [CA 1] Center 43 (13~74) winsize 62
7557 13:58:51.511863 [CA 2] Center 39 (10~68) winsize 59
7558 13:58:51.515402 [CA 3] Center 39 (10~68) winsize 59
7559 13:58:51.518490 [CA 4] Center 37 (7~67) winsize 61
7560 13:58:51.522672 [CA 5] Center 37 (7~67) winsize 61
7561 13:58:51.522753
7562 13:58:51.525470 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7563 13:58:51.525550
7564 13:58:51.528930 [CATrainingPosCal] consider 1 rank data
7565 13:58:51.531793 u2DelayCellTimex100 = 275/100 ps
7566 13:58:51.535691 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7567 13:58:51.541740 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7568 13:58:51.545271 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7569 13:58:51.548805 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7570 13:58:51.552179 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7571 13:58:51.555711 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7572 13:58:51.555791
7573 13:58:51.558957 CA PerBit enable=1, Macro0, CA PI delay=37
7574 13:58:51.559037
7575 13:58:51.562194 [CBTSetCACLKResult] CA Dly = 37
7576 13:58:51.565559 CS Dly: 11 (0~42)
7577 13:58:51.569038 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7578 13:58:51.572321 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7579 13:58:51.572403 ==
7580 13:58:51.575515 Dram Type= 6, Freq= 0, CH_0, rank 1
7581 13:58:51.578697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7582 13:58:51.582324 ==
7583 13:58:51.585617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7584 13:58:51.588556 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7585 13:58:51.595841 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7586 13:58:51.598745 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7587 13:58:51.609042 [CA 0] Center 43 (13~74) winsize 62
7588 13:58:51.612275 [CA 1] Center 43 (13~74) winsize 62
7589 13:58:51.615518 [CA 2] Center 39 (10~69) winsize 60
7590 13:58:51.618900 [CA 3] Center 38 (9~68) winsize 60
7591 13:58:51.622640 [CA 4] Center 37 (7~67) winsize 61
7592 13:58:51.625633 [CA 5] Center 37 (7~67) winsize 61
7593 13:58:51.625713
7594 13:58:51.629299 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7595 13:58:51.629380
7596 13:58:51.632652 [CATrainingPosCal] consider 2 rank data
7597 13:58:51.635727 u2DelayCellTimex100 = 275/100 ps
7598 13:58:51.639141 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7599 13:58:51.645957 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7600 13:58:51.649128 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7601 13:58:51.652914 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7602 13:58:51.656223 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7603 13:58:51.659337 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7604 13:58:51.659418
7605 13:58:51.662466 CA PerBit enable=1, Macro0, CA PI delay=37
7606 13:58:51.662547
7607 13:58:51.665826 [CBTSetCACLKResult] CA Dly = 37
7608 13:58:51.669131 CS Dly: 11 (0~43)
7609 13:58:51.672877 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7610 13:58:51.676087 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7611 13:58:51.676166
7612 13:58:51.679394 ----->DramcWriteLeveling(PI) begin...
7613 13:58:51.679476 ==
7614 13:58:51.682888 Dram Type= 6, Freq= 0, CH_0, rank 0
7615 13:58:51.685892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 13:58:51.685974 ==
7617 13:58:51.689557 Write leveling (Byte 0): 34 => 34
7618 13:58:51.692729 Write leveling (Byte 1): 28 => 28
7619 13:58:51.696093 DramcWriteLeveling(PI) end<-----
7620 13:58:51.696199
7621 13:58:51.696290 ==
7622 13:58:51.699406 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 13:58:51.706121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 13:58:51.706203 ==
7625 13:58:51.706267 [Gating] SW mode calibration
7626 13:58:51.716190 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7627 13:58:51.719656 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7628 13:58:51.723006 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 13:58:51.729928 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 13:58:51.733088 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 13:58:51.736128 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 13:58:51.743098 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 13:58:51.746325 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7634 13:58:51.749704 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
7635 13:58:51.756363 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 13:58:51.759616 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 13:58:51.763067 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 13:58:51.769573 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 13:58:51.772980 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7640 13:58:51.776174 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7641 13:58:51.783100 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7642 13:58:51.786352 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 13:58:51.789568 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 13:58:51.792892 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 13:58:51.799529 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 13:58:51.802977 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 13:58:51.806743 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 13:58:51.813244 1 6 16 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
7649 13:58:51.816289 1 6 20 | B1->B0 | 2c2c 4545 | 0 0 | (1 1) (0 0)
7650 13:58:51.820119 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7651 13:58:51.826182 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 13:58:51.829617 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 13:58:51.832989 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 13:58:51.839585 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 13:58:51.843133 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 13:58:51.846327 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7657 13:58:51.853253 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7658 13:58:51.856497 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 13:58:51.859831 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 13:58:51.866209 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 13:58:51.869868 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 13:58:51.873408 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 13:58:51.876287 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 13:58:51.883027 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 13:58:51.886152 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 13:58:51.889706 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 13:58:51.896298 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 13:58:51.899770 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 13:58:51.902656 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 13:58:51.909754 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 13:58:51.912935 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7672 13:58:51.916150 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7673 13:58:51.923078 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7674 13:58:51.923159 Total UI for P1: 0, mck2ui 16
7675 13:58:51.929544 best dqsien dly found for B0: ( 1, 9, 14)
7676 13:58:51.933065 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7677 13:58:51.936205 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 13:58:51.939654 Total UI for P1: 0, mck2ui 16
7679 13:58:51.942778 best dqsien dly found for B1: ( 1, 9, 20)
7680 13:58:51.946181 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7681 13:58:51.949683 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7682 13:58:51.949764
7683 13:58:51.956312 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7684 13:58:51.959492 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7685 13:58:51.959574 [Gating] SW calibration Done
7686 13:58:51.962808 ==
7687 13:58:51.966500 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 13:58:51.969704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 13:58:51.969804 ==
7690 13:58:51.969869 RX Vref Scan: 0
7691 13:58:51.969929
7692 13:58:51.972607 RX Vref 0 -> 0, step: 1
7693 13:58:51.972728
7694 13:58:51.975861 RX Delay 0 -> 252, step: 8
7695 13:58:51.979388 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7696 13:58:51.982629 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7697 13:58:51.985935 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7698 13:58:51.992582 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7699 13:58:51.996378 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7700 13:58:51.999193 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7701 13:58:52.002473 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7702 13:58:52.005929 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7703 13:58:52.013145 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7704 13:58:52.015869 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7705 13:58:52.019365 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7706 13:58:52.022569 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7707 13:58:52.026272 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7708 13:58:52.032525 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7709 13:58:52.036063 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7710 13:58:52.039278 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7711 13:58:52.039359 ==
7712 13:58:52.042890 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 13:58:52.045837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 13:58:52.045919 ==
7715 13:58:52.049473 DQS Delay:
7716 13:58:52.049553 DQS0 = 0, DQS1 = 0
7717 13:58:52.052769 DQM Delay:
7718 13:58:52.052850 DQM0 = 132, DQM1 = 125
7719 13:58:52.056076 DQ Delay:
7720 13:58:52.059371 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7721 13:58:52.062923 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7722 13:58:52.066309 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7723 13:58:52.069805 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7724 13:58:52.069910
7725 13:58:52.069976
7726 13:58:52.070035 ==
7727 13:58:52.073203 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 13:58:52.076112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 13:58:52.076193 ==
7730 13:58:52.076257
7731 13:58:52.076315
7732 13:58:52.079574 TX Vref Scan disable
7733 13:58:52.082891 == TX Byte 0 ==
7734 13:58:52.086221 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7735 13:58:52.089495 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7736 13:58:52.092921 == TX Byte 1 ==
7737 13:58:52.096644 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7738 13:58:52.099381 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7739 13:58:52.099462 ==
7740 13:58:52.102896 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 13:58:52.106543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 13:58:52.106624 ==
7743 13:58:52.122345
7744 13:58:52.125851 TX Vref early break, caculate TX vref
7745 13:58:52.128862 TX Vref=16, minBit 4, minWin=21, winSum=364
7746 13:58:52.132283 TX Vref=18, minBit 0, minWin=22, winSum=370
7747 13:58:52.135591 TX Vref=20, minBit 1, minWin=23, winSum=385
7748 13:58:52.138850 TX Vref=22, minBit 4, minWin=23, winSum=393
7749 13:58:52.142724 TX Vref=24, minBit 1, minWin=23, winSum=402
7750 13:58:52.148918 TX Vref=26, minBit 1, minWin=24, winSum=412
7751 13:58:52.152629 TX Vref=28, minBit 4, minWin=24, winSum=416
7752 13:58:52.155524 TX Vref=30, minBit 4, minWin=25, winSum=420
7753 13:58:52.158775 TX Vref=32, minBit 4, minWin=24, winSum=415
7754 13:58:52.162308 TX Vref=34, minBit 0, minWin=24, winSum=400
7755 13:58:52.165836 TX Vref=36, minBit 0, minWin=23, winSum=394
7756 13:58:52.172325 [TxChooseVref] Worse bit 4, Min win 25, Win sum 420, Final Vref 30
7757 13:58:52.172407
7758 13:58:52.175666 Final TX Range 0 Vref 30
7759 13:58:52.175747
7760 13:58:52.175810 ==
7761 13:58:52.179280 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 13:58:52.182521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 13:58:52.182603 ==
7764 13:58:52.182683
7765 13:58:52.182781
7766 13:58:52.185569 TX Vref Scan disable
7767 13:58:52.192563 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7768 13:58:52.192676 == TX Byte 0 ==
7769 13:58:52.195978 u2DelayCellOfst[0]=14 cells (4 PI)
7770 13:58:52.199288 u2DelayCellOfst[1]=17 cells (5 PI)
7771 13:58:52.202886 u2DelayCellOfst[2]=10 cells (3 PI)
7772 13:58:52.206328 u2DelayCellOfst[3]=10 cells (3 PI)
7773 13:58:52.208968 u2DelayCellOfst[4]=7 cells (2 PI)
7774 13:58:52.212647 u2DelayCellOfst[5]=0 cells (0 PI)
7775 13:58:52.216133 u2DelayCellOfst[6]=21 cells (6 PI)
7776 13:58:52.216213 u2DelayCellOfst[7]=17 cells (5 PI)
7777 13:58:52.222669 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7778 13:58:52.226161 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7779 13:58:52.226242 == TX Byte 1 ==
7780 13:58:52.229573 u2DelayCellOfst[8]=0 cells (0 PI)
7781 13:58:52.232403 u2DelayCellOfst[9]=3 cells (1 PI)
7782 13:58:52.235908 u2DelayCellOfst[10]=7 cells (2 PI)
7783 13:58:52.239218 u2DelayCellOfst[11]=0 cells (0 PI)
7784 13:58:52.242747 u2DelayCellOfst[12]=14 cells (4 PI)
7785 13:58:52.245660 u2DelayCellOfst[13]=10 cells (3 PI)
7786 13:58:52.249468 u2DelayCellOfst[14]=17 cells (5 PI)
7787 13:58:52.252533 u2DelayCellOfst[15]=14 cells (4 PI)
7788 13:58:52.256095 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7789 13:58:52.262644 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7790 13:58:52.262725 DramC Write-DBI on
7791 13:58:52.262790 ==
7792 13:58:52.265988 Dram Type= 6, Freq= 0, CH_0, rank 0
7793 13:58:52.269191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7794 13:58:52.269272 ==
7795 13:58:52.269335
7796 13:58:52.272816
7797 13:58:52.272896 TX Vref Scan disable
7798 13:58:52.276161 == TX Byte 0 ==
7799 13:58:52.279369 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7800 13:58:52.282685 == TX Byte 1 ==
7801 13:58:52.286030 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7802 13:58:52.286111 DramC Write-DBI off
7803 13:58:52.286175
7804 13:58:52.289585 [DATLAT]
7805 13:58:52.289666 Freq=1600, CH0 RK0
7806 13:58:52.289729
7807 13:58:52.292575 DATLAT Default: 0xf
7808 13:58:52.292705 0, 0xFFFF, sum = 0
7809 13:58:52.296277 1, 0xFFFF, sum = 0
7810 13:58:52.296359 2, 0xFFFF, sum = 0
7811 13:58:52.299651 3, 0xFFFF, sum = 0
7812 13:58:52.299733 4, 0xFFFF, sum = 0
7813 13:58:52.303120 5, 0xFFFF, sum = 0
7814 13:58:52.303202 6, 0xFFFF, sum = 0
7815 13:58:52.306224 7, 0xFFFF, sum = 0
7816 13:58:52.306306 8, 0xFFFF, sum = 0
7817 13:58:52.309442 9, 0xFFFF, sum = 0
7818 13:58:52.309524 10, 0xFFFF, sum = 0
7819 13:58:52.313241 11, 0xFFFF, sum = 0
7820 13:58:52.316005 12, 0xFFFF, sum = 0
7821 13:58:52.316087 13, 0xFFFF, sum = 0
7822 13:58:52.319571 14, 0x0, sum = 1
7823 13:58:52.319652 15, 0x0, sum = 2
7824 13:58:52.319717 16, 0x0, sum = 3
7825 13:58:52.322993 17, 0x0, sum = 4
7826 13:58:52.323075 best_step = 15
7827 13:58:52.323139
7828 13:58:52.326245 ==
7829 13:58:52.326326 Dram Type= 6, Freq= 0, CH_0, rank 0
7830 13:58:52.333036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7831 13:58:52.333118 ==
7832 13:58:52.333183 RX Vref Scan: 1
7833 13:58:52.333242
7834 13:58:52.336199 Set Vref Range= 24 -> 127
7835 13:58:52.336279
7836 13:58:52.339386 RX Vref 24 -> 127, step: 1
7837 13:58:52.339467
7838 13:58:52.343057 RX Delay 11 -> 252, step: 4
7839 13:58:52.343137
7840 13:58:52.346249 Set Vref, RX VrefLevel [Byte0]: 24
7841 13:58:52.349699 [Byte1]: 24
7842 13:58:52.349780
7843 13:58:52.353314 Set Vref, RX VrefLevel [Byte0]: 25
7844 13:58:52.356282 [Byte1]: 25
7845 13:58:52.356363
7846 13:58:52.359499 Set Vref, RX VrefLevel [Byte0]: 26
7847 13:58:52.362830 [Byte1]: 26
7848 13:58:52.362911
7849 13:58:52.366037 Set Vref, RX VrefLevel [Byte0]: 27
7850 13:58:52.369513 [Byte1]: 27
7851 13:58:52.373927
7852 13:58:52.374007 Set Vref, RX VrefLevel [Byte0]: 28
7853 13:58:52.376788 [Byte1]: 28
7854 13:58:52.381122
7855 13:58:52.381264 Set Vref, RX VrefLevel [Byte0]: 29
7856 13:58:52.384775 [Byte1]: 29
7857 13:58:52.388839
7858 13:58:52.388919 Set Vref, RX VrefLevel [Byte0]: 30
7859 13:58:52.393008 [Byte1]: 30
7860 13:58:52.396606
7861 13:58:52.396743 Set Vref, RX VrefLevel [Byte0]: 31
7862 13:58:52.399625 [Byte1]: 31
7863 13:58:52.404573
7864 13:58:52.404703 Set Vref, RX VrefLevel [Byte0]: 32
7865 13:58:52.407607 [Byte1]: 32
7866 13:58:52.411689
7867 13:58:52.411770 Set Vref, RX VrefLevel [Byte0]: 33
7868 13:58:52.415066 [Byte1]: 33
7869 13:58:52.419412
7870 13:58:52.419492 Set Vref, RX VrefLevel [Byte0]: 34
7871 13:58:52.423167 [Byte1]: 34
7872 13:58:52.427079
7873 13:58:52.427159 Set Vref, RX VrefLevel [Byte0]: 35
7874 13:58:52.430310 [Byte1]: 35
7875 13:58:52.434407
7876 13:58:52.434487 Set Vref, RX VrefLevel [Byte0]: 36
7877 13:58:52.437929 [Byte1]: 36
7878 13:58:52.442387
7879 13:58:52.442467 Set Vref, RX VrefLevel [Byte0]: 37
7880 13:58:52.445361 [Byte1]: 37
7881 13:58:52.449927
7882 13:58:52.450007 Set Vref, RX VrefLevel [Byte0]: 38
7883 13:58:52.452869 [Byte1]: 38
7884 13:58:52.457334
7885 13:58:52.457414 Set Vref, RX VrefLevel [Byte0]: 39
7886 13:58:52.460623 [Byte1]: 39
7887 13:58:52.465512
7888 13:58:52.465592 Set Vref, RX VrefLevel [Byte0]: 40
7889 13:58:52.468219 [Byte1]: 40
7890 13:58:52.472624
7891 13:58:52.472729 Set Vref, RX VrefLevel [Byte0]: 41
7892 13:58:52.475881 [Byte1]: 41
7893 13:58:52.480053
7894 13:58:52.480133 Set Vref, RX VrefLevel [Byte0]: 42
7895 13:58:52.483401 [Byte1]: 42
7896 13:58:52.488056
7897 13:58:52.488137 Set Vref, RX VrefLevel [Byte0]: 43
7898 13:58:52.491008 [Byte1]: 43
7899 13:58:52.495320
7900 13:58:52.495400 Set Vref, RX VrefLevel [Byte0]: 44
7901 13:58:52.498921 [Byte1]: 44
7902 13:58:52.502972
7903 13:58:52.503053 Set Vref, RX VrefLevel [Byte0]: 45
7904 13:58:52.506128 [Byte1]: 45
7905 13:58:52.510697
7906 13:58:52.510777 Set Vref, RX VrefLevel [Byte0]: 46
7907 13:58:52.513969 [Byte1]: 46
7908 13:58:52.518324
7909 13:58:52.518404 Set Vref, RX VrefLevel [Byte0]: 47
7910 13:58:52.521377 [Byte1]: 47
7911 13:58:52.526170
7912 13:58:52.526251 Set Vref, RX VrefLevel [Byte0]: 48
7913 13:58:52.529396 [Byte1]: 48
7914 13:58:52.533583
7915 13:58:52.533664 Set Vref, RX VrefLevel [Byte0]: 49
7916 13:58:52.537017 [Byte1]: 49
7917 13:58:52.541048
7918 13:58:52.541128 Set Vref, RX VrefLevel [Byte0]: 50
7919 13:58:52.544427 [Byte1]: 50
7920 13:58:52.548992
7921 13:58:52.549073 Set Vref, RX VrefLevel [Byte0]: 51
7922 13:58:52.552240 [Byte1]: 51
7923 13:58:52.556329
7924 13:58:52.556409 Set Vref, RX VrefLevel [Byte0]: 52
7925 13:58:52.559644 [Byte1]: 52
7926 13:58:52.563724
7927 13:58:52.563804 Set Vref, RX VrefLevel [Byte0]: 53
7928 13:58:52.567147 [Byte1]: 53
7929 13:58:52.571790
7930 13:58:52.571869 Set Vref, RX VrefLevel [Byte0]: 54
7931 13:58:52.574655 [Byte1]: 54
7932 13:58:52.579221
7933 13:58:52.579301 Set Vref, RX VrefLevel [Byte0]: 55
7934 13:58:52.582828 [Byte1]: 55
7935 13:58:52.586697
7936 13:58:52.586777 Set Vref, RX VrefLevel [Byte0]: 56
7937 13:58:52.590492 [Byte1]: 56
7938 13:58:52.594304
7939 13:58:52.594385 Set Vref, RX VrefLevel [Byte0]: 57
7940 13:58:52.597534 [Byte1]: 57
7941 13:58:52.602058
7942 13:58:52.602138 Set Vref, RX VrefLevel [Byte0]: 58
7943 13:58:52.605304 [Byte1]: 58
7944 13:58:52.609467
7945 13:58:52.609548 Set Vref, RX VrefLevel [Byte0]: 59
7946 13:58:52.613390 [Byte1]: 59
7947 13:58:52.617121
7948 13:58:52.617202 Set Vref, RX VrefLevel [Byte0]: 60
7949 13:58:52.620219 [Byte1]: 60
7950 13:58:52.625245
7951 13:58:52.625336 Set Vref, RX VrefLevel [Byte0]: 61
7952 13:58:52.628412 [Byte1]: 61
7953 13:58:52.632580
7954 13:58:52.632727 Set Vref, RX VrefLevel [Byte0]: 62
7955 13:58:52.635819 [Byte1]: 62
7956 13:58:52.640244
7957 13:58:52.640324 Set Vref, RX VrefLevel [Byte0]: 63
7958 13:58:52.643339 [Byte1]: 63
7959 13:58:52.647479
7960 13:58:52.647560 Set Vref, RX VrefLevel [Byte0]: 64
7961 13:58:52.650958 [Byte1]: 64
7962 13:58:52.655553
7963 13:58:52.655633 Set Vref, RX VrefLevel [Byte0]: 65
7964 13:58:52.658729 [Byte1]: 65
7965 13:58:52.662635
7966 13:58:52.662715 Set Vref, RX VrefLevel [Byte0]: 66
7967 13:58:52.665947 [Byte1]: 66
7968 13:58:52.670517
7969 13:58:52.670623 Set Vref, RX VrefLevel [Byte0]: 67
7970 13:58:52.673638 [Byte1]: 67
7971 13:58:52.677941
7972 13:58:52.678021 Set Vref, RX VrefLevel [Byte0]: 68
7973 13:58:52.681420 [Byte1]: 68
7974 13:58:52.685883
7975 13:58:52.685963 Set Vref, RX VrefLevel [Byte0]: 69
7976 13:58:52.689245 [Byte1]: 69
7977 13:58:52.693525
7978 13:58:52.693606 Set Vref, RX VrefLevel [Byte0]: 70
7979 13:58:52.696605 [Byte1]: 70
7980 13:58:52.701149
7981 13:58:52.701230 Set Vref, RX VrefLevel [Byte0]: 71
7982 13:58:52.704133 [Byte1]: 71
7983 13:58:52.708484
7984 13:58:52.708564 Set Vref, RX VrefLevel [Byte0]: 72
7985 13:58:52.712065 [Byte1]: 72
7986 13:58:52.716152
7987 13:58:52.716232 Set Vref, RX VrefLevel [Byte0]: 73
7988 13:58:52.719351 [Byte1]: 73
7989 13:58:52.723883
7990 13:58:52.723962 Set Vref, RX VrefLevel [Byte0]: 74
7991 13:58:52.727295 [Byte1]: 74
7992 13:58:52.731175
7993 13:58:52.731255 Set Vref, RX VrefLevel [Byte0]: 75
7994 13:58:52.734838 [Byte1]: 75
7995 13:58:52.738948
7996 13:58:52.739028 Set Vref, RX VrefLevel [Byte0]: 76
7997 13:58:52.742558 [Byte1]: 76
7998 13:58:52.746629
7999 13:58:52.746709 Final RX Vref Byte 0 = 57 to rank0
8000 13:58:52.749791 Final RX Vref Byte 1 = 61 to rank0
8001 13:58:52.753138 Final RX Vref Byte 0 = 57 to rank1
8002 13:58:52.756941 Final RX Vref Byte 1 = 61 to rank1==
8003 13:58:52.759914 Dram Type= 6, Freq= 0, CH_0, rank 0
8004 13:58:52.766709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8005 13:58:52.766790 ==
8006 13:58:52.766855 DQS Delay:
8007 13:58:52.766913 DQS0 = 0, DQS1 = 0
8008 13:58:52.769902 DQM Delay:
8009 13:58:52.769982 DQM0 = 129, DQM1 = 122
8010 13:58:52.773263 DQ Delay:
8011 13:58:52.776711 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =126
8012 13:58:52.780191 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
8013 13:58:52.783300 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
8014 13:58:52.786750 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8015 13:58:52.786831
8016 13:58:52.786894
8017 13:58:52.786952
8018 13:58:52.789930 [DramC_TX_OE_Calibration] TA2
8019 13:58:52.793782 Original DQ_B0 (3 6) =30, OEN = 27
8020 13:58:52.796907 Original DQ_B1 (3 6) =30, OEN = 27
8021 13:58:52.800059 24, 0x0, End_B0=24 End_B1=24
8022 13:58:52.800140 25, 0x0, End_B0=25 End_B1=25
8023 13:58:52.803420 26, 0x0, End_B0=26 End_B1=26
8024 13:58:52.806744 27, 0x0, End_B0=27 End_B1=27
8025 13:58:52.809863 28, 0x0, End_B0=28 End_B1=28
8026 13:58:52.809945 29, 0x0, End_B0=29 End_B1=29
8027 13:58:52.813454 30, 0x0, End_B0=30 End_B1=30
8028 13:58:52.816916 31, 0x4141, End_B0=30 End_B1=30
8029 13:58:52.819802 Byte0 end_step=30 best_step=27
8030 13:58:52.823825 Byte1 end_step=30 best_step=27
8031 13:58:52.826858 Byte0 TX OE(2T, 0.5T) = (3, 3)
8032 13:58:52.826939 Byte1 TX OE(2T, 0.5T) = (3, 3)
8033 13:58:52.827003
8034 13:58:52.827062
8035 13:58:52.836901 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8036 13:58:52.840179 CH0 RK0: MR19=303, MR18=1509
8037 13:58:52.843623 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
8038 13:58:52.846831
8039 13:58:52.846911 ----->DramcWriteLeveling(PI) begin...
8040 13:58:52.850220 ==
8041 13:58:52.853879 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 13:58:52.857002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 13:58:52.857084 ==
8044 13:58:52.860465 Write leveling (Byte 0): 30 => 30
8045 13:58:52.863699 Write leveling (Byte 1): 26 => 26
8046 13:58:52.866996 DramcWriteLeveling(PI) end<-----
8047 13:58:52.867076
8048 13:58:52.867139 ==
8049 13:58:52.870316 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 13:58:52.874034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 13:58:52.874115 ==
8052 13:58:52.876941 [Gating] SW mode calibration
8053 13:58:52.883956 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8054 13:58:52.887147 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8055 13:58:52.893724 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 13:58:52.897039 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 13:58:52.900590 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 13:58:52.907379 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8059 13:58:52.910261 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8060 13:58:52.913689 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8061 13:58:52.920248 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 13:58:52.924035 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 13:58:52.926830 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 13:58:52.933646 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8065 13:58:52.937135 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8066 13:58:52.940470 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8067 13:58:52.947369 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8068 13:58:52.950466 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8069 13:58:52.953677 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8070 13:58:52.960752 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 13:58:52.964196 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 13:58:52.967114 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 13:58:52.973586 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8074 13:58:52.977223 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8075 13:58:52.980548 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8076 13:58:52.984082 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8077 13:58:52.990530 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 13:58:52.994018 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 13:58:52.997132 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 13:58:53.004224 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 13:58:53.007696 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8082 13:58:53.010669 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8083 13:58:53.017623 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8084 13:58:53.020848 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8085 13:58:53.023914 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 13:58:53.030487 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 13:58:53.033859 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 13:58:53.037576 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 13:58:53.044070 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 13:58:53.047499 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 13:58:53.050755 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 13:58:53.054455 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 13:58:53.060562 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 13:58:53.063893 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 13:58:53.067321 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 13:58:53.074270 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8097 13:58:53.077605 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8098 13:58:53.080797 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8099 13:58:53.087621 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8100 13:58:53.090755 Total UI for P1: 0, mck2ui 16
8101 13:58:53.094300 best dqsien dly found for B0: ( 1, 9, 8)
8102 13:58:53.097605 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8103 13:58:53.100617 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 13:58:53.103859 Total UI for P1: 0, mck2ui 16
8105 13:58:53.107233 best dqsien dly found for B1: ( 1, 9, 18)
8106 13:58:53.110791 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8107 13:58:53.114256 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8108 13:58:53.114356
8109 13:58:53.117364 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8110 13:58:53.123831 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8111 13:58:53.123906 [Gating] SW calibration Done
8112 13:58:53.127257 ==
8113 13:58:53.130686 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 13:58:53.134002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 13:58:53.134099 ==
8116 13:58:53.134187 RX Vref Scan: 0
8117 13:58:53.134277
8118 13:58:53.137192 RX Vref 0 -> 0, step: 1
8119 13:58:53.137287
8120 13:58:53.140525 RX Delay 0 -> 252, step: 8
8121 13:58:53.144305 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8122 13:58:53.147298 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8123 13:58:53.150626 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8124 13:58:53.157592 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8125 13:58:53.160862 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8126 13:58:53.164212 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8127 13:58:53.167441 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8128 13:58:53.170853 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8129 13:58:53.177576 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8130 13:58:53.180932 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8131 13:58:53.184472 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8132 13:58:53.187685 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8133 13:58:53.191202 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8134 13:58:53.197669 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8135 13:58:53.200855 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8136 13:58:53.204359 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8137 13:58:53.204456 ==
8138 13:58:53.207466 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 13:58:53.210850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 13:58:53.210955 ==
8141 13:58:53.214397 DQS Delay:
8142 13:58:53.214495 DQS0 = 0, DQS1 = 0
8143 13:58:53.214586 DQM Delay:
8144 13:58:53.217368 DQM0 = 131, DQM1 = 125
8145 13:58:53.217468 DQ Delay:
8146 13:58:53.221121 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8147 13:58:53.224429 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8148 13:58:53.231014 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8149 13:58:53.234278 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8150 13:58:53.234381
8151 13:58:53.234472
8152 13:58:53.234560 ==
8153 13:58:53.238045 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 13:58:53.240896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 13:58:53.240984 ==
8156 13:58:53.241073
8157 13:58:53.241157
8158 13:58:53.244346 TX Vref Scan disable
8159 13:58:53.244446 == TX Byte 0 ==
8160 13:58:53.250898 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8161 13:58:53.254186 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8162 13:58:53.254284 == TX Byte 1 ==
8163 13:58:53.260806 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8164 13:58:53.264737 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8165 13:58:53.264810 ==
8166 13:58:53.267835 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 13:58:53.270961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 13:58:53.271060 ==
8169 13:58:53.285124
8170 13:58:53.288734 TX Vref early break, caculate TX vref
8171 13:58:53.292112 TX Vref=16, minBit 5, minWin=22, winSum=371
8172 13:58:53.294965 TX Vref=18, minBit 8, minWin=22, winSum=378
8173 13:58:53.298905 TX Vref=20, minBit 9, minWin=23, winSum=390
8174 13:58:53.302020 TX Vref=22, minBit 8, minWin=23, winSum=396
8175 13:58:53.305302 TX Vref=24, minBit 9, minWin=23, winSum=401
8176 13:58:53.308627 TX Vref=26, minBit 1, minWin=25, winSum=412
8177 13:58:53.315673 TX Vref=28, minBit 4, minWin=25, winSum=418
8178 13:58:53.318720 TX Vref=30, minBit 1, minWin=25, winSum=410
8179 13:58:53.322445 TX Vref=32, minBit 4, minWin=24, winSum=409
8180 13:58:53.325256 TX Vref=34, minBit 1, minWin=23, winSum=395
8181 13:58:53.331940 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 28
8182 13:58:53.332025
8183 13:58:53.335620 Final TX Range 0 Vref 28
8184 13:58:53.335701
8185 13:58:53.335765 ==
8186 13:58:53.338815 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 13:58:53.342185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 13:58:53.342266 ==
8189 13:58:53.342330
8190 13:58:53.342389
8191 13:58:53.345319 TX Vref Scan disable
8192 13:58:53.348650 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8193 13:58:53.352347 == TX Byte 0 ==
8194 13:58:53.355590 u2DelayCellOfst[0]=14 cells (4 PI)
8195 13:58:53.358985 u2DelayCellOfst[1]=21 cells (6 PI)
8196 13:58:53.362476 u2DelayCellOfst[2]=10 cells (3 PI)
8197 13:58:53.365578 u2DelayCellOfst[3]=14 cells (4 PI)
8198 13:58:53.369051 u2DelayCellOfst[4]=10 cells (3 PI)
8199 13:58:53.369131 u2DelayCellOfst[5]=0 cells (0 PI)
8200 13:58:53.372460 u2DelayCellOfst[6]=21 cells (6 PI)
8201 13:58:53.376217 u2DelayCellOfst[7]=21 cells (6 PI)
8202 13:58:53.382306 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8203 13:58:53.385726 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8204 13:58:53.385806 == TX Byte 1 ==
8205 13:58:53.388868 u2DelayCellOfst[8]=0 cells (0 PI)
8206 13:58:53.392687 u2DelayCellOfst[9]=3 cells (1 PI)
8207 13:58:53.395779 u2DelayCellOfst[10]=10 cells (3 PI)
8208 13:58:53.398850 u2DelayCellOfst[11]=3 cells (1 PI)
8209 13:58:53.402411 u2DelayCellOfst[12]=14 cells (4 PI)
8210 13:58:53.405798 u2DelayCellOfst[13]=14 cells (4 PI)
8211 13:58:53.409364 u2DelayCellOfst[14]=17 cells (5 PI)
8212 13:58:53.412780 u2DelayCellOfst[15]=14 cells (4 PI)
8213 13:58:53.415901 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8214 13:58:53.419139 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8215 13:58:53.422776 DramC Write-DBI on
8216 13:58:53.422883 ==
8217 13:58:53.426106 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 13:58:53.429314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 13:58:53.429418 ==
8220 13:58:53.429510
8221 13:58:53.429595
8222 13:58:53.432651 TX Vref Scan disable
8223 13:58:53.435664 == TX Byte 0 ==
8224 13:58:53.439136 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
8225 13:58:53.439241 == TX Byte 1 ==
8226 13:58:53.446222 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8227 13:58:53.446324 DramC Write-DBI off
8228 13:58:53.446413
8229 13:58:53.446511 [DATLAT]
8230 13:58:53.449184 Freq=1600, CH0 RK1
8231 13:58:53.449252
8232 13:58:53.452657 DATLAT Default: 0xf
8233 13:58:53.452733 0, 0xFFFF, sum = 0
8234 13:58:53.456193 1, 0xFFFF, sum = 0
8235 13:58:53.456291 2, 0xFFFF, sum = 0
8236 13:58:53.459687 3, 0xFFFF, sum = 0
8237 13:58:53.459784 4, 0xFFFF, sum = 0
8238 13:58:53.463247 5, 0xFFFF, sum = 0
8239 13:58:53.463354 6, 0xFFFF, sum = 0
8240 13:58:53.466110 7, 0xFFFF, sum = 0
8241 13:58:53.466214 8, 0xFFFF, sum = 0
8242 13:58:53.469695 9, 0xFFFF, sum = 0
8243 13:58:53.469770 10, 0xFFFF, sum = 0
8244 13:58:53.472566 11, 0xFFFF, sum = 0
8245 13:58:53.472662 12, 0xFFFF, sum = 0
8246 13:58:53.476032 13, 0xFFFF, sum = 0
8247 13:58:53.476098 14, 0x0, sum = 1
8248 13:58:53.479773 15, 0x0, sum = 2
8249 13:58:53.479869 16, 0x0, sum = 3
8250 13:58:53.482691 17, 0x0, sum = 4
8251 13:58:53.482764 best_step = 15
8252 13:58:53.482828
8253 13:58:53.482884 ==
8254 13:58:53.486374 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 13:58:53.489798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 13:58:53.492889 ==
8257 13:58:53.492972 RX Vref Scan: 0
8258 13:58:53.493053
8259 13:58:53.496249 RX Vref 0 -> 0, step: 1
8260 13:58:53.496343
8261 13:58:53.496432 RX Delay 11 -> 252, step: 4
8262 13:58:53.503932 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8263 13:58:53.507557 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8264 13:58:53.510595 iDelay=191, Bit 2, Center 124 (67 ~ 182) 116
8265 13:58:53.514077 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8266 13:58:53.517306 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8267 13:58:53.524049 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8268 13:58:53.527282 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8269 13:58:53.530659 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8270 13:58:53.534168 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8271 13:58:53.537372 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8272 13:58:53.543734 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8273 13:58:53.547354 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8274 13:58:53.550641 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8275 13:58:53.554182 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8276 13:58:53.557164 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8277 13:58:53.563984 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8278 13:58:53.564083 ==
8279 13:58:53.567447 Dram Type= 6, Freq= 0, CH_0, rank 1
8280 13:58:53.570654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 13:58:53.570757 ==
8282 13:58:53.570844 DQS Delay:
8283 13:58:53.574109 DQS0 = 0, DQS1 = 0
8284 13:58:53.574205 DQM Delay:
8285 13:58:53.577163 DQM0 = 126, DQM1 = 122
8286 13:58:53.577235 DQ Delay:
8287 13:58:53.581003 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8288 13:58:53.583926 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =134
8289 13:58:53.587193 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =118
8290 13:58:53.590742 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8291 13:58:53.590845
8292 13:58:53.590934
8293 13:58:53.591022
8294 13:58:53.594083 [DramC_TX_OE_Calibration] TA2
8295 13:58:53.597479 Original DQ_B0 (3 6) =30, OEN = 27
8296 13:58:53.600854 Original DQ_B1 (3 6) =30, OEN = 27
8297 13:58:53.604195 24, 0x0, End_B0=24 End_B1=24
8298 13:58:53.607280 25, 0x0, End_B0=25 End_B1=25
8299 13:58:53.607379 26, 0x0, End_B0=26 End_B1=26
8300 13:58:53.610811 27, 0x0, End_B0=27 End_B1=27
8301 13:58:53.614104 28, 0x0, End_B0=28 End_B1=28
8302 13:58:53.617454 29, 0x0, End_B0=29 End_B1=29
8303 13:58:53.621057 30, 0x0, End_B0=30 End_B1=30
8304 13:58:53.621154 31, 0x4141, End_B0=30 End_B1=30
8305 13:58:53.623936 Byte0 end_step=30 best_step=27
8306 13:58:53.627648 Byte1 end_step=30 best_step=27
8307 13:58:53.630842 Byte0 TX OE(2T, 0.5T) = (3, 3)
8308 13:58:53.634190 Byte1 TX OE(2T, 0.5T) = (3, 3)
8309 13:58:53.634289
8310 13:58:53.634382
8311 13:58:53.640889 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8312 13:58:53.644168 CH0 RK1: MR19=303, MR18=1B10
8313 13:58:53.651095 CH0_RK1: MR19=0x303, MR18=0x1B10, DQSOSC=396, MR23=63, INC=23, DEC=15
8314 13:58:53.654663 [RxdqsGatingPostProcess] freq 1600
8315 13:58:53.657603 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8316 13:58:53.661039 best DQS0 dly(2T, 0.5T) = (1, 1)
8317 13:58:53.664166 best DQS1 dly(2T, 0.5T) = (1, 1)
8318 13:58:53.667579 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8319 13:58:53.670843 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8320 13:58:53.674276 best DQS0 dly(2T, 0.5T) = (1, 1)
8321 13:58:53.678042 best DQS1 dly(2T, 0.5T) = (1, 1)
8322 13:58:53.681361 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8323 13:58:53.684526 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8324 13:58:53.688176 Pre-setting of DQS Precalculation
8325 13:58:53.691435 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8326 13:58:53.691519 ==
8327 13:58:53.694469 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 13:58:53.698018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 13:58:53.700943 ==
8330 13:58:53.704615 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8331 13:58:53.707626 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8332 13:58:53.714703 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8333 13:58:53.717712 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8334 13:58:53.727910 [CA 0] Center 43 (15~72) winsize 58
8335 13:58:53.731506 [CA 1] Center 43 (14~72) winsize 59
8336 13:58:53.734662 [CA 2] Center 38 (10~67) winsize 58
8337 13:58:53.738275 [CA 3] Center 37 (8~67) winsize 60
8338 13:58:53.741328 [CA 4] Center 38 (10~67) winsize 58
8339 13:58:53.744769 [CA 5] Center 37 (8~66) winsize 59
8340 13:58:53.744841
8341 13:58:53.748381 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8342 13:58:53.748477
8343 13:58:53.751328 [CATrainingPosCal] consider 1 rank data
8344 13:58:53.754874 u2DelayCellTimex100 = 275/100 ps
8345 13:58:53.758131 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8346 13:58:53.764641 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8347 13:58:53.768325 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8348 13:58:53.771859 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8349 13:58:53.774946 CA4 delay=38 (10~67),Diff = 1 PI (3 cell)
8350 13:58:53.778290 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8351 13:58:53.778386
8352 13:58:53.781338 CA PerBit enable=1, Macro0, CA PI delay=37
8353 13:58:53.781433
8354 13:58:53.784738 [CBTSetCACLKResult] CA Dly = 37
8355 13:58:53.784834 CS Dly: 9 (0~40)
8356 13:58:53.791570 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8357 13:58:53.794807 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8358 13:58:53.794907 ==
8359 13:58:53.798776 Dram Type= 6, Freq= 0, CH_1, rank 1
8360 13:58:53.801439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 13:58:53.801513 ==
8362 13:58:53.808129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8363 13:58:53.811580 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8364 13:58:53.818260 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8365 13:58:53.821710 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8366 13:58:53.831456 [CA 0] Center 42 (13~72) winsize 60
8367 13:58:53.834899 [CA 1] Center 43 (14~72) winsize 59
8368 13:58:53.837898 [CA 2] Center 38 (9~67) winsize 59
8369 13:58:53.841193 [CA 3] Center 37 (8~66) winsize 59
8370 13:58:53.844543 [CA 4] Center 37 (8~67) winsize 60
8371 13:58:53.848073 [CA 5] Center 36 (6~66) winsize 61
8372 13:58:53.848169
8373 13:58:53.851762 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8374 13:58:53.851859
8375 13:58:53.854965 [CATrainingPosCal] consider 2 rank data
8376 13:58:53.857870 u2DelayCellTimex100 = 275/100 ps
8377 13:58:53.861083 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8378 13:58:53.868083 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8379 13:58:53.871967 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8380 13:58:53.874432 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8381 13:58:53.878213 CA4 delay=38 (10~67),Diff = 1 PI (3 cell)
8382 13:58:53.881544 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8383 13:58:53.881614
8384 13:58:53.884594 CA PerBit enable=1, Macro0, CA PI delay=37
8385 13:58:53.884692
8386 13:58:53.887873 [CBTSetCACLKResult] CA Dly = 37
8387 13:58:53.891665 CS Dly: 11 (0~45)
8388 13:58:53.894960 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8389 13:58:53.898208 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8390 13:58:53.898281
8391 13:58:53.901752 ----->DramcWriteLeveling(PI) begin...
8392 13:58:53.901851 ==
8393 13:58:53.904843 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 13:58:53.907983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 13:58:53.908079 ==
8396 13:58:53.912007 Write leveling (Byte 0): 24 => 24
8397 13:58:53.914786 Write leveling (Byte 1): 27 => 27
8398 13:58:53.918108 DramcWriteLeveling(PI) end<-----
8399 13:58:53.918183
8400 13:58:53.918244 ==
8401 13:58:53.921638 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 13:58:53.928448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 13:58:53.928559 ==
8404 13:58:53.928660 [Gating] SW mode calibration
8405 13:58:53.938311 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8406 13:58:53.941834 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8407 13:58:53.945221 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 13:58:53.951674 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 13:58:53.954902 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 13:58:53.958668 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 13:58:53.965558 1 4 16 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
8412 13:58:53.969069 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 13:58:53.971803 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 13:58:53.978557 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 13:58:53.982103 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 13:58:53.985356 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 13:58:53.988715 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 13:58:53.995265 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8419 13:58:53.998625 1 5 16 | B1->B0 | 2828 3131 | 0 0 | (1 0) (1 0)
8420 13:58:54.002060 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8421 13:58:54.008819 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 13:58:54.012136 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 13:58:54.015487 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 13:58:54.022251 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 13:58:54.025317 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 13:58:54.028848 1 6 12 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
8427 13:58:54.035538 1 6 16 | B1->B0 | 3636 2626 | 0 0 | (1 1) (0 0)
8428 13:58:54.038580 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 13:58:54.042032 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 13:58:54.048814 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 13:58:54.052129 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 13:58:54.055095 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 13:58:54.062121 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 13:58:54.065252 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 13:58:54.068334 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8436 13:58:54.075280 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 13:58:54.078466 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 13:58:54.081703 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 13:58:54.084990 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 13:58:54.091619 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 13:58:54.095092 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 13:58:54.098556 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 13:58:54.105391 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 13:58:54.108381 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 13:58:54.111770 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 13:58:54.118508 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 13:58:54.122060 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 13:58:54.125214 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 13:58:54.131947 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 13:58:54.136034 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 13:58:54.138885 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8452 13:58:54.145435 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 13:58:54.145517 Total UI for P1: 0, mck2ui 16
8454 13:58:54.148802 best dqsien dly found for B0: ( 1, 9, 16)
8455 13:58:54.151996 Total UI for P1: 0, mck2ui 16
8456 13:58:54.155826 best dqsien dly found for B1: ( 1, 9, 16)
8457 13:58:54.158750 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8458 13:58:54.165739 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8459 13:58:54.165838
8460 13:58:54.168959 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8461 13:58:54.172135 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8462 13:58:54.175741 [Gating] SW calibration Done
8463 13:58:54.175838 ==
8464 13:58:54.179429 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 13:58:54.182162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 13:58:54.182238 ==
8467 13:58:54.186020 RX Vref Scan: 0
8468 13:58:54.186093
8469 13:58:54.186153 RX Vref 0 -> 0, step: 1
8470 13:58:54.186233
8471 13:58:54.189397 RX Delay 0 -> 252, step: 8
8472 13:58:54.192325 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8473 13:58:54.195636 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8474 13:58:54.202469 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8475 13:58:54.205650 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8476 13:58:54.209234 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8477 13:58:54.212230 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8478 13:58:54.215785 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8479 13:58:54.219018 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8480 13:58:54.225639 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8481 13:58:54.229065 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8482 13:58:54.232184 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8483 13:58:54.235491 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8484 13:58:54.239263 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8485 13:58:54.246348 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8486 13:58:54.249108 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8487 13:58:54.252501 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8488 13:58:54.252599 ==
8489 13:58:54.255861 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 13:58:54.259263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 13:58:54.262525 ==
8492 13:58:54.262623 DQS Delay:
8493 13:58:54.262711 DQS0 = 0, DQS1 = 0
8494 13:58:54.266436 DQM Delay:
8495 13:58:54.266533 DQM0 = 133, DQM1 = 127
8496 13:58:54.269373 DQ Delay:
8497 13:58:54.272526 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8498 13:58:54.275999 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8499 13:58:54.279104 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8500 13:58:54.282480 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8501 13:58:54.282575
8502 13:58:54.282662
8503 13:58:54.282746 ==
8504 13:58:54.285977 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 13:58:54.289219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 13:58:54.289304 ==
8507 13:58:54.289392
8508 13:58:54.289476
8509 13:58:54.292416 TX Vref Scan disable
8510 13:58:54.295844 == TX Byte 0 ==
8511 13:58:54.299437 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8512 13:58:54.303087 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8513 13:58:54.305849 == TX Byte 1 ==
8514 13:58:54.309876 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8515 13:58:54.312595 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8516 13:58:54.312722 ==
8517 13:58:54.315879 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 13:58:54.319431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 13:58:54.322516 ==
8520 13:58:54.334727
8521 13:58:54.338466 TX Vref early break, caculate TX vref
8522 13:58:54.341742 TX Vref=16, minBit 8, minWin=21, winSum=363
8523 13:58:54.344975 TX Vref=18, minBit 8, minWin=22, winSum=376
8524 13:58:54.348436 TX Vref=20, minBit 8, minWin=21, winSum=385
8525 13:58:54.351882 TX Vref=22, minBit 8, minWin=23, winSum=394
8526 13:58:54.354677 TX Vref=24, minBit 8, minWin=23, winSum=402
8527 13:58:54.361294 TX Vref=26, minBit 6, minWin=25, winSum=412
8528 13:58:54.365201 TX Vref=28, minBit 15, minWin=25, winSum=422
8529 13:58:54.368386 TX Vref=30, minBit 0, minWin=25, winSum=420
8530 13:58:54.371424 TX Vref=32, minBit 0, minWin=25, winSum=412
8531 13:58:54.375061 TX Vref=34, minBit 11, minWin=23, winSum=402
8532 13:58:54.378375 TX Vref=36, minBit 9, minWin=23, winSum=392
8533 13:58:54.384932 [TxChooseVref] Worse bit 15, Min win 25, Win sum 422, Final Vref 28
8534 13:58:54.385039
8535 13:58:54.388337 Final TX Range 0 Vref 28
8536 13:58:54.388440
8537 13:58:54.388529 ==
8538 13:58:54.391726 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 13:58:54.394794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 13:58:54.394892 ==
8541 13:58:54.394988
8542 13:58:54.395077
8543 13:58:54.398025 TX Vref Scan disable
8544 13:58:54.404764 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8545 13:58:54.404863 == TX Byte 0 ==
8546 13:58:54.408227 u2DelayCellOfst[0]=17 cells (5 PI)
8547 13:58:54.411454 u2DelayCellOfst[1]=10 cells (3 PI)
8548 13:58:54.415089 u2DelayCellOfst[2]=0 cells (0 PI)
8549 13:58:54.418062 u2DelayCellOfst[3]=7 cells (2 PI)
8550 13:58:54.421553 u2DelayCellOfst[4]=7 cells (2 PI)
8551 13:58:54.424855 u2DelayCellOfst[5]=17 cells (5 PI)
8552 13:58:54.428201 u2DelayCellOfst[6]=14 cells (4 PI)
8553 13:58:54.431621 u2DelayCellOfst[7]=3 cells (1 PI)
8554 13:58:54.434917 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8555 13:58:54.438179 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8556 13:58:54.441781 == TX Byte 1 ==
8557 13:58:54.441855 u2DelayCellOfst[8]=0 cells (0 PI)
8558 13:58:54.445199 u2DelayCellOfst[9]=3 cells (1 PI)
8559 13:58:54.448618 u2DelayCellOfst[10]=10 cells (3 PI)
8560 13:58:54.451900 u2DelayCellOfst[11]=3 cells (1 PI)
8561 13:58:54.455029 u2DelayCellOfst[12]=14 cells (4 PI)
8562 13:58:54.458258 u2DelayCellOfst[13]=14 cells (4 PI)
8563 13:58:54.461727 u2DelayCellOfst[14]=17 cells (5 PI)
8564 13:58:54.465083 u2DelayCellOfst[15]=17 cells (5 PI)
8565 13:58:54.468303 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8566 13:58:54.475398 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8567 13:58:54.475501 DramC Write-DBI on
8568 13:58:54.475593 ==
8569 13:58:54.478540 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 13:58:54.481909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 13:58:54.482006 ==
8572 13:58:54.482095
8573 13:58:54.485568
8574 13:58:54.485658 TX Vref Scan disable
8575 13:58:54.488649 == TX Byte 0 ==
8576 13:58:54.492329 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8577 13:58:54.495026 == TX Byte 1 ==
8578 13:58:54.498661 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8579 13:58:54.498767 DramC Write-DBI off
8580 13:58:54.498856
8581 13:58:54.502272 [DATLAT]
8582 13:58:54.502373 Freq=1600, CH1 RK0
8583 13:58:54.502467
8584 13:58:54.505655 DATLAT Default: 0xf
8585 13:58:54.505748 0, 0xFFFF, sum = 0
8586 13:58:54.508535 1, 0xFFFF, sum = 0
8587 13:58:54.508629 2, 0xFFFF, sum = 0
8588 13:58:54.512085 3, 0xFFFF, sum = 0
8589 13:58:54.512192 4, 0xFFFF, sum = 0
8590 13:58:54.515486 5, 0xFFFF, sum = 0
8591 13:58:54.515591 6, 0xFFFF, sum = 0
8592 13:58:54.518707 7, 0xFFFF, sum = 0
8593 13:58:54.518813 8, 0xFFFF, sum = 0
8594 13:58:54.521859 9, 0xFFFF, sum = 0
8595 13:58:54.525072 10, 0xFFFF, sum = 0
8596 13:58:54.525162 11, 0xFFFF, sum = 0
8597 13:58:54.528759 12, 0xFFFF, sum = 0
8598 13:58:54.528855 13, 0xFFFF, sum = 0
8599 13:58:54.531921 14, 0x0, sum = 1
8600 13:58:54.532026 15, 0x0, sum = 2
8601 13:58:54.535377 16, 0x0, sum = 3
8602 13:58:54.535484 17, 0x0, sum = 4
8603 13:58:54.535573 best_step = 15
8604 13:58:54.535658
8605 13:58:54.538769 ==
8606 13:58:54.538840 Dram Type= 6, Freq= 0, CH_1, rank 0
8607 13:58:54.545700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8608 13:58:54.545807 ==
8609 13:58:54.545896 RX Vref Scan: 1
8610 13:58:54.545990
8611 13:58:54.548670 Set Vref Range= 24 -> 127
8612 13:58:54.548766
8613 13:58:54.551939 RX Vref 24 -> 127, step: 1
8614 13:58:54.552042
8615 13:58:54.555742 RX Delay 19 -> 252, step: 4
8616 13:58:54.555814
8617 13:58:54.558617 Set Vref, RX VrefLevel [Byte0]: 24
8618 13:58:54.562287 [Byte1]: 24
8619 13:58:54.562382
8620 13:58:54.565325 Set Vref, RX VrefLevel [Byte0]: 25
8621 13:58:54.568780 [Byte1]: 25
8622 13:58:54.568882
8623 13:58:54.571857 Set Vref, RX VrefLevel [Byte0]: 26
8624 13:58:54.575248 [Byte1]: 26
8625 13:58:54.575347
8626 13:58:54.579003 Set Vref, RX VrefLevel [Byte0]: 27
8627 13:58:54.582142 [Byte1]: 27
8628 13:58:54.586095
8629 13:58:54.586192 Set Vref, RX VrefLevel [Byte0]: 28
8630 13:58:54.589513 [Byte1]: 28
8631 13:58:54.593669
8632 13:58:54.593767 Set Vref, RX VrefLevel [Byte0]: 29
8633 13:58:54.596971 [Byte1]: 29
8634 13:58:54.601158
8635 13:58:54.601251 Set Vref, RX VrefLevel [Byte0]: 30
8636 13:58:54.604552 [Byte1]: 30
8637 13:58:54.608568
8638 13:58:54.608662 Set Vref, RX VrefLevel [Byte0]: 31
8639 13:58:54.612112 [Byte1]: 31
8640 13:58:54.616178
8641 13:58:54.616273 Set Vref, RX VrefLevel [Byte0]: 32
8642 13:58:54.619309 [Byte1]: 32
8643 13:58:54.624209
8644 13:58:54.624308 Set Vref, RX VrefLevel [Byte0]: 33
8645 13:58:54.627194 [Byte1]: 33
8646 13:58:54.631334
8647 13:58:54.631433 Set Vref, RX VrefLevel [Byte0]: 34
8648 13:58:54.634685 [Byte1]: 34
8649 13:58:54.638852
8650 13:58:54.638949 Set Vref, RX VrefLevel [Byte0]: 35
8651 13:58:54.642482 [Byte1]: 35
8652 13:58:54.646794
8653 13:58:54.646891 Set Vref, RX VrefLevel [Byte0]: 36
8654 13:58:54.649935 [Byte1]: 36
8655 13:58:54.654215
8656 13:58:54.654307 Set Vref, RX VrefLevel [Byte0]: 37
8657 13:58:54.657477 [Byte1]: 37
8658 13:58:54.661639
8659 13:58:54.661737 Set Vref, RX VrefLevel [Byte0]: 38
8660 13:58:54.664997 [Byte1]: 38
8661 13:58:54.669387
8662 13:58:54.669489 Set Vref, RX VrefLevel [Byte0]: 39
8663 13:58:54.672751 [Byte1]: 39
8664 13:58:54.676821
8665 13:58:54.676924 Set Vref, RX VrefLevel [Byte0]: 40
8666 13:58:54.680233 [Byte1]: 40
8667 13:58:54.684224
8668 13:58:54.684324 Set Vref, RX VrefLevel [Byte0]: 41
8669 13:58:54.687974 [Byte1]: 41
8670 13:58:54.691857
8671 13:58:54.691930 Set Vref, RX VrefLevel [Byte0]: 42
8672 13:58:54.695250 [Byte1]: 42
8673 13:58:54.699395
8674 13:58:54.699499 Set Vref, RX VrefLevel [Byte0]: 43
8675 13:58:54.702790 [Byte1]: 43
8676 13:58:54.707564
8677 13:58:54.707662 Set Vref, RX VrefLevel [Byte0]: 44
8678 13:58:54.710556 [Byte1]: 44
8679 13:58:54.714580
8680 13:58:54.714678 Set Vref, RX VrefLevel [Byte0]: 45
8681 13:58:54.717999 [Byte1]: 45
8682 13:58:54.722029
8683 13:58:54.722131 Set Vref, RX VrefLevel [Byte0]: 46
8684 13:58:54.725566 [Byte1]: 46
8685 13:58:54.730325
8686 13:58:54.730430 Set Vref, RX VrefLevel [Byte0]: 47
8687 13:58:54.732918 [Byte1]: 47
8688 13:58:54.737977
8689 13:58:54.738088 Set Vref, RX VrefLevel [Byte0]: 48
8690 13:58:54.740838 [Byte1]: 48
8691 13:58:54.744845
8692 13:58:54.744951 Set Vref, RX VrefLevel [Byte0]: 49
8693 13:58:54.748305 [Byte1]: 49
8694 13:58:54.752293
8695 13:58:54.752390 Set Vref, RX VrefLevel [Byte0]: 50
8696 13:58:54.755710 [Byte1]: 50
8697 13:58:54.760168
8698 13:58:54.760262 Set Vref, RX VrefLevel [Byte0]: 51
8699 13:58:54.763332 [Byte1]: 51
8700 13:58:54.768137
8701 13:58:54.768231 Set Vref, RX VrefLevel [Byte0]: 52
8702 13:58:54.771157 [Byte1]: 52
8703 13:58:54.775197
8704 13:58:54.775295 Set Vref, RX VrefLevel [Byte0]: 53
8705 13:58:54.778379 [Byte1]: 53
8706 13:58:54.782794
8707 13:58:54.782898 Set Vref, RX VrefLevel [Byte0]: 54
8708 13:58:54.786112 [Byte1]: 54
8709 13:58:54.790300
8710 13:58:54.790405 Set Vref, RX VrefLevel [Byte0]: 55
8711 13:58:54.794097 [Byte1]: 55
8712 13:58:54.798028
8713 13:58:54.798125 Set Vref, RX VrefLevel [Byte0]: 56
8714 13:58:54.801376 [Byte1]: 56
8715 13:58:54.805444
8716 13:58:54.805514 Set Vref, RX VrefLevel [Byte0]: 57
8717 13:58:54.808897 [Byte1]: 57
8718 13:58:54.813062
8719 13:58:54.813160 Set Vref, RX VrefLevel [Byte0]: 58
8720 13:58:54.816562 [Byte1]: 58
8721 13:58:54.820753
8722 13:58:54.820824 Set Vref, RX VrefLevel [Byte0]: 59
8723 13:58:54.823792 [Byte1]: 59
8724 13:58:54.828162
8725 13:58:54.828260 Set Vref, RX VrefLevel [Byte0]: 60
8726 13:58:54.831432 [Byte1]: 60
8727 13:58:54.836103
8728 13:58:54.836204 Set Vref, RX VrefLevel [Byte0]: 61
8729 13:58:54.839155 [Byte1]: 61
8730 13:58:54.843324
8731 13:58:54.843424 Set Vref, RX VrefLevel [Byte0]: 62
8732 13:58:54.847086 [Byte1]: 62
8733 13:58:54.851049
8734 13:58:54.851150 Set Vref, RX VrefLevel [Byte0]: 63
8735 13:58:54.854499 [Byte1]: 63
8736 13:58:54.858573
8737 13:58:54.858671 Set Vref, RX VrefLevel [Byte0]: 64
8738 13:58:54.862038 [Byte1]: 64
8739 13:58:54.866001
8740 13:58:54.866074 Set Vref, RX VrefLevel [Byte0]: 65
8741 13:58:54.869645 [Byte1]: 65
8742 13:58:54.873614
8743 13:58:54.873684 Set Vref, RX VrefLevel [Byte0]: 66
8744 13:58:54.877136 [Byte1]: 66
8745 13:58:54.881363
8746 13:58:54.881433 Set Vref, RX VrefLevel [Byte0]: 67
8747 13:58:54.884616 [Byte1]: 67
8748 13:58:54.888600
8749 13:58:54.888743 Set Vref, RX VrefLevel [Byte0]: 68
8750 13:58:54.892309 [Byte1]: 68
8751 13:58:54.896827
8752 13:58:54.896925 Set Vref, RX VrefLevel [Byte0]: 69
8753 13:58:54.899550 [Byte1]: 69
8754 13:58:54.903992
8755 13:58:54.904092 Set Vref, RX VrefLevel [Byte0]: 70
8756 13:58:54.907178 [Byte1]: 70
8757 13:58:54.911378
8758 13:58:54.911477 Set Vref, RX VrefLevel [Byte0]: 71
8759 13:58:54.915012 [Byte1]: 71
8760 13:58:54.919004
8761 13:58:54.919101 Set Vref, RX VrefLevel [Byte0]: 72
8762 13:58:54.922755 [Byte1]: 72
8763 13:58:54.926818
8764 13:58:54.926922 Set Vref, RX VrefLevel [Byte0]: 73
8765 13:58:54.929982 [Byte1]: 73
8766 13:58:54.934624
8767 13:58:54.934719 Set Vref, RX VrefLevel [Byte0]: 74
8768 13:58:54.937822 [Byte1]: 74
8769 13:58:54.941942
8770 13:58:54.942040 Set Vref, RX VrefLevel [Byte0]: 75
8771 13:58:54.945122 [Byte1]: 75
8772 13:58:54.949314
8773 13:58:54.949410 Final RX Vref Byte 0 = 56 to rank0
8774 13:58:54.952951 Final RX Vref Byte 1 = 54 to rank0
8775 13:58:54.955999 Final RX Vref Byte 0 = 56 to rank1
8776 13:58:54.959564 Final RX Vref Byte 1 = 54 to rank1==
8777 13:58:54.963079 Dram Type= 6, Freq= 0, CH_1, rank 0
8778 13:58:54.965972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 13:58:54.969299 ==
8780 13:58:54.969396 DQS Delay:
8781 13:58:54.969489 DQS0 = 0, DQS1 = 0
8782 13:58:54.972847 DQM Delay:
8783 13:58:54.972921 DQM0 = 131, DQM1 = 124
8784 13:58:54.976002 DQ Delay:
8785 13:58:54.979424 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8786 13:58:54.983000 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =128
8787 13:58:54.986251 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8788 13:58:54.989577 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8789 13:58:54.989677
8790 13:58:54.989770
8791 13:58:54.989855
8792 13:58:54.993053 [DramC_TX_OE_Calibration] TA2
8793 13:58:54.996769 Original DQ_B0 (3 6) =30, OEN = 27
8794 13:58:54.999635 Original DQ_B1 (3 6) =30, OEN = 27
8795 13:58:54.999743 24, 0x0, End_B0=24 End_B1=24
8796 13:58:55.002797 25, 0x0, End_B0=25 End_B1=25
8797 13:58:55.006309 26, 0x0, End_B0=26 End_B1=26
8798 13:58:55.009562 27, 0x0, End_B0=27 End_B1=27
8799 13:58:55.012935 28, 0x0, End_B0=28 End_B1=28
8800 13:58:55.013012 29, 0x0, End_B0=29 End_B1=29
8801 13:58:55.016589 30, 0x0, End_B0=30 End_B1=30
8802 13:58:55.019672 31, 0x5151, End_B0=30 End_B1=30
8803 13:58:55.023281 Byte0 end_step=30 best_step=27
8804 13:58:55.026619 Byte1 end_step=30 best_step=27
8805 13:58:55.026718 Byte0 TX OE(2T, 0.5T) = (3, 3)
8806 13:58:55.029900 Byte1 TX OE(2T, 0.5T) = (3, 3)
8807 13:58:55.029970
8808 13:58:55.030031
8809 13:58:55.039690 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8810 13:58:55.042965 CH1 RK0: MR19=303, MR18=1601
8811 13:58:55.046752 CH1_RK0: MR19=0x303, MR18=0x1601, DQSOSC=398, MR23=63, INC=23, DEC=15
8812 13:58:55.046849
8813 13:58:55.053432 ----->DramcWriteLeveling(PI) begin...
8814 13:58:55.053514 ==
8815 13:58:55.056451 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 13:58:55.060050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 13:58:55.060145 ==
8818 13:58:55.062924 Write leveling (Byte 0): 24 => 24
8819 13:58:55.066534 Write leveling (Byte 1): 25 => 25
8820 13:58:55.070007 DramcWriteLeveling(PI) end<-----
8821 13:58:55.070102
8822 13:58:55.070188 ==
8823 13:58:55.073232 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 13:58:55.076995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 13:58:55.077068 ==
8826 13:58:55.079784 [Gating] SW mode calibration
8827 13:58:55.086937 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8828 13:58:55.090671 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8829 13:58:55.096986 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 13:58:55.100067 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 13:58:55.103444 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
8832 13:58:55.110221 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8833 13:58:55.113377 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 13:58:55.117139 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 13:58:55.123379 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 13:58:55.126725 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 13:58:55.130071 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 13:58:55.136687 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8839 13:58:55.139948 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
8840 13:58:55.143490 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8841 13:58:55.149978 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8842 13:58:55.153472 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 13:58:55.156742 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 13:58:55.163328 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 13:58:55.166824 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 13:58:55.170130 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8847 13:58:55.173654 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
8848 13:58:55.180225 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8849 13:58:55.183386 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 13:58:55.186955 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 13:58:55.194024 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 13:58:55.197359 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 13:58:55.200534 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 13:58:55.207092 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 13:58:55.210551 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8856 13:58:55.213608 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8857 13:58:55.220333 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 13:58:55.223527 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 13:58:55.226882 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 13:58:55.233535 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 13:58:55.237083 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 13:58:55.240497 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 13:58:55.243579 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 13:58:55.250209 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 13:58:55.253865 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 13:58:55.257018 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 13:58:55.263619 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 13:58:55.266964 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 13:58:55.270725 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 13:58:55.277104 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 13:58:55.280559 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8872 13:58:55.284079 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8873 13:58:55.290465 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8874 13:58:55.290545 Total UI for P1: 0, mck2ui 16
8875 13:58:55.297258 best dqsien dly found for B0: ( 1, 9, 10)
8876 13:58:55.300605 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8877 13:58:55.303949 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 13:58:55.307555 Total UI for P1: 0, mck2ui 16
8879 13:58:55.310817 best dqsien dly found for B1: ( 1, 9, 14)
8880 13:58:55.314024 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8881 13:58:55.317268 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8882 13:58:55.317341
8883 13:58:55.320814 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8884 13:58:55.327522 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8885 13:58:55.327599 [Gating] SW calibration Done
8886 13:58:55.327662 ==
8887 13:58:55.330537 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 13:58:55.337364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 13:58:55.337445 ==
8890 13:58:55.337508 RX Vref Scan: 0
8891 13:58:55.337567
8892 13:58:55.340560 RX Vref 0 -> 0, step: 1
8893 13:58:55.340672
8894 13:58:55.343982 RX Delay 0 -> 252, step: 8
8895 13:58:55.347488 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8896 13:58:55.351045 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8897 13:58:55.354346 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8898 13:58:55.357611 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8899 13:58:55.364354 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8900 13:58:55.368002 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8901 13:58:55.371058 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8902 13:58:55.374100 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8903 13:58:55.377553 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8904 13:58:55.385001 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8905 13:58:55.387894 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8906 13:58:55.391315 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8907 13:58:55.394424 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8908 13:58:55.398256 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8909 13:58:55.404914 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8910 13:58:55.408015 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8911 13:58:55.408403 ==
8912 13:58:55.411717 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 13:58:55.415282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 13:58:55.415856 ==
8915 13:58:55.418024 DQS Delay:
8916 13:58:55.418479 DQS0 = 0, DQS1 = 0
8917 13:58:55.418837 DQM Delay:
8918 13:58:55.421418 DQM0 = 132, DQM1 = 127
8919 13:58:55.421872 DQ Delay:
8920 13:58:55.424864 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8921 13:58:55.428102 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8922 13:58:55.431842 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8923 13:58:55.438316 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8924 13:58:55.438866
8925 13:58:55.439227
8926 13:58:55.439559 ==
8927 13:58:55.441584 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 13:58:55.445147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 13:58:55.445699 ==
8930 13:58:55.446065
8931 13:58:55.446396
8932 13:58:55.448407 TX Vref Scan disable
8933 13:58:55.448943 == TX Byte 0 ==
8934 13:58:55.455809 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8935 13:58:55.458552 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8936 13:58:55.459007 == TX Byte 1 ==
8937 13:58:55.465107 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8938 13:58:55.468817 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8939 13:58:55.469434 ==
8940 13:58:55.472169 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 13:58:55.474998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 13:58:55.475456 ==
8943 13:58:55.489542
8944 13:58:55.492858 TX Vref early break, caculate TX vref
8945 13:58:55.495764 TX Vref=16, minBit 0, minWin=23, winSum=385
8946 13:58:55.499598 TX Vref=18, minBit 6, minWin=23, winSum=394
8947 13:58:55.502437 TX Vref=20, minBit 0, minWin=24, winSum=404
8948 13:58:55.505784 TX Vref=22, minBit 5, minWin=24, winSum=410
8949 13:58:55.509287 TX Vref=24, minBit 5, minWin=25, winSum=421
8950 13:58:55.512467 TX Vref=26, minBit 0, minWin=25, winSum=429
8951 13:58:55.519762 TX Vref=28, minBit 0, minWin=26, winSum=433
8952 13:58:55.522797 TX Vref=30, minBit 0, minWin=25, winSum=430
8953 13:58:55.526382 TX Vref=32, minBit 0, minWin=25, winSum=422
8954 13:58:55.529460 TX Vref=34, minBit 0, minWin=25, winSum=418
8955 13:58:55.533190 TX Vref=36, minBit 0, minWin=24, winSum=406
8956 13:58:55.539515 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
8957 13:58:55.540065
8958 13:58:55.543390 Final TX Range 0 Vref 28
8959 13:58:55.543943
8960 13:58:55.544305 ==
8961 13:58:55.546348 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 13:58:55.549708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 13:58:55.550182 ==
8964 13:58:55.550540
8965 13:58:55.550870
8966 13:58:55.553121 TX Vref Scan disable
8967 13:58:55.560093 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8968 13:58:55.560642 == TX Byte 0 ==
8969 13:58:55.562987 u2DelayCellOfst[0]=17 cells (5 PI)
8970 13:58:55.566887 u2DelayCellOfst[1]=10 cells (3 PI)
8971 13:58:55.569937 u2DelayCellOfst[2]=0 cells (0 PI)
8972 13:58:55.572990 u2DelayCellOfst[3]=7 cells (2 PI)
8973 13:58:55.576729 u2DelayCellOfst[4]=7 cells (2 PI)
8974 13:58:55.579851 u2DelayCellOfst[5]=17 cells (5 PI)
8975 13:58:55.580406 u2DelayCellOfst[6]=14 cells (4 PI)
8976 13:58:55.583331 u2DelayCellOfst[7]=3 cells (1 PI)
8977 13:58:55.589882 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8978 13:58:55.593181 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8979 13:58:55.593746 == TX Byte 1 ==
8980 13:58:55.596481 u2DelayCellOfst[8]=0 cells (0 PI)
8981 13:58:55.599633 u2DelayCellOfst[9]=3 cells (1 PI)
8982 13:58:55.603513 u2DelayCellOfst[10]=10 cells (3 PI)
8983 13:58:55.606650 u2DelayCellOfst[11]=3 cells (1 PI)
8984 13:58:55.609842 u2DelayCellOfst[12]=10 cells (3 PI)
8985 13:58:55.613323 u2DelayCellOfst[13]=14 cells (4 PI)
8986 13:58:55.616832 u2DelayCellOfst[14]=14 cells (4 PI)
8987 13:58:55.619827 u2DelayCellOfst[15]=14 cells (4 PI)
8988 13:58:55.623230 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8989 13:58:55.626817 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8990 13:58:55.630200 DramC Write-DBI on
8991 13:58:55.630787 ==
8992 13:58:55.633300 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 13:58:55.636777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 13:58:55.637233 ==
8995 13:58:55.637591
8996 13:58:55.637920
8997 13:58:55.640026 TX Vref Scan disable
8998 13:58:55.643121 == TX Byte 0 ==
8999 13:58:55.646326 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9000 13:58:55.646781 == TX Byte 1 ==
9001 13:58:55.653462 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9002 13:58:55.654003 DramC Write-DBI off
9003 13:58:55.654366
9004 13:58:55.656959 [DATLAT]
9005 13:58:55.657507 Freq=1600, CH1 RK1
9006 13:58:55.657871
9007 13:58:55.660033 DATLAT Default: 0xf
9008 13:58:55.660582 0, 0xFFFF, sum = 0
9009 13:58:55.663559 1, 0xFFFF, sum = 0
9010 13:58:55.664110 2, 0xFFFF, sum = 0
9011 13:58:55.667134 3, 0xFFFF, sum = 0
9012 13:58:55.667690 4, 0xFFFF, sum = 0
9013 13:58:55.670113 5, 0xFFFF, sum = 0
9014 13:58:55.670573 6, 0xFFFF, sum = 0
9015 13:58:55.673933 7, 0xFFFF, sum = 0
9016 13:58:55.674537 8, 0xFFFF, sum = 0
9017 13:58:55.676887 9, 0xFFFF, sum = 0
9018 13:58:55.677343 10, 0xFFFF, sum = 0
9019 13:58:55.680604 11, 0xFFFF, sum = 0
9020 13:58:55.681241 12, 0xFFFF, sum = 0
9021 13:58:55.683269 13, 0xFFFF, sum = 0
9022 13:58:55.683820 14, 0x0, sum = 1
9023 13:58:55.686436 15, 0x0, sum = 2
9024 13:58:55.686917 16, 0x0, sum = 3
9025 13:58:55.690564 17, 0x0, sum = 4
9026 13:58:55.691188 best_step = 15
9027 13:58:55.691594
9028 13:58:55.691949 ==
9029 13:58:55.693033 Dram Type= 6, Freq= 0, CH_1, rank 1
9030 13:58:55.699938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9031 13:58:55.700413 ==
9032 13:58:55.701044 RX Vref Scan: 0
9033 13:58:55.701574
9034 13:58:55.703486 RX Vref 0 -> 0, step: 1
9035 13:58:55.704010
9036 13:58:55.706815 RX Delay 11 -> 252, step: 4
9037 13:58:55.709861 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9038 13:58:55.713225 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9039 13:58:55.716786 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9040 13:58:55.723363 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9041 13:58:55.727066 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9042 13:58:55.730136 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9043 13:58:55.733493 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9044 13:58:55.736833 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9045 13:58:55.743681 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9046 13:58:55.746656 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
9047 13:58:55.750199 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9048 13:58:55.752996 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9049 13:58:55.756960 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9050 13:58:55.763222 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9051 13:58:55.767126 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9052 13:58:55.770028 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9053 13:58:55.770482 ==
9054 13:58:55.773073 Dram Type= 6, Freq= 0, CH_1, rank 1
9055 13:58:55.776977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9056 13:58:55.777530 ==
9057 13:58:55.780379 DQS Delay:
9058 13:58:55.780975 DQS0 = 0, DQS1 = 0
9059 13:58:55.783097 DQM Delay:
9060 13:58:55.783577 DQM0 = 129, DQM1 = 126
9061 13:58:55.783937 DQ Delay:
9062 13:58:55.790479 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
9063 13:58:55.793654 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9064 13:58:55.796628 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =118
9065 13:58:55.799696 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9066 13:58:55.800149
9067 13:58:55.800508
9068 13:58:55.800878
9069 13:58:55.803430 [DramC_TX_OE_Calibration] TA2
9070 13:58:55.807019 Original DQ_B0 (3 6) =30, OEN = 27
9071 13:58:55.810562 Original DQ_B1 (3 6) =30, OEN = 27
9072 13:58:55.811114 24, 0x0, End_B0=24 End_B1=24
9073 13:58:55.813408 25, 0x0, End_B0=25 End_B1=25
9074 13:58:55.816907 26, 0x0, End_B0=26 End_B1=26
9075 13:58:55.819830 27, 0x0, End_B0=27 End_B1=27
9076 13:58:55.820290 28, 0x0, End_B0=28 End_B1=28
9077 13:58:55.823608 29, 0x0, End_B0=29 End_B1=29
9078 13:58:55.826711 30, 0x0, End_B0=30 End_B1=30
9079 13:58:55.830060 31, 0x4141, End_B0=30 End_B1=30
9080 13:58:55.833311 Byte0 end_step=30 best_step=27
9081 13:58:55.836759 Byte1 end_step=30 best_step=27
9082 13:58:55.837229 Byte0 TX OE(2T, 0.5T) = (3, 3)
9083 13:58:55.839898 Byte1 TX OE(2T, 0.5T) = (3, 3)
9084 13:58:55.840471
9085 13:58:55.840903
9086 13:58:55.850099 [DQSOSCAuto] RK1, (LSB)MR18= 0x1217, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 400 ps
9087 13:58:55.853649 CH1 RK1: MR19=303, MR18=1217
9088 13:58:55.857156 CH1_RK1: MR19=0x303, MR18=0x1217, DQSOSC=398, MR23=63, INC=23, DEC=15
9089 13:58:55.860493 [RxdqsGatingPostProcess] freq 1600
9090 13:58:55.866912 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9091 13:58:55.870520 best DQS0 dly(2T, 0.5T) = (1, 1)
9092 13:58:55.873634 best DQS1 dly(2T, 0.5T) = (1, 1)
9093 13:58:55.876892 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9094 13:58:55.880546 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9095 13:58:55.881149 best DQS0 dly(2T, 0.5T) = (1, 1)
9096 13:58:55.883764 best DQS1 dly(2T, 0.5T) = (1, 1)
9097 13:58:55.887249 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9098 13:58:55.890613 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9099 13:58:55.894339 Pre-setting of DQS Precalculation
9100 13:58:55.900459 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9101 13:58:55.907091 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9102 13:58:55.913680 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9103 13:58:55.914228
9104 13:58:55.914590
9105 13:58:55.917174 [Calibration Summary] 3200 Mbps
9106 13:58:55.917632 CH 0, Rank 0
9107 13:58:55.920413 SW Impedance : PASS
9108 13:58:55.924020 DUTY Scan : NO K
9109 13:58:55.924570 ZQ Calibration : PASS
9110 13:58:55.926823 Jitter Meter : NO K
9111 13:58:55.930697 CBT Training : PASS
9112 13:58:55.931244 Write leveling : PASS
9113 13:58:55.934021 RX DQS gating : PASS
9114 13:58:55.934474 RX DQ/DQS(RDDQC) : PASS
9115 13:58:55.936853 TX DQ/DQS : PASS
9116 13:58:55.940807 RX DATLAT : PASS
9117 13:58:55.941375 RX DQ/DQS(Engine): PASS
9118 13:58:55.944626 TX OE : PASS
9119 13:58:55.945238 All Pass.
9120 13:58:55.945602
9121 13:58:55.947064 CH 0, Rank 1
9122 13:58:55.947526 SW Impedance : PASS
9123 13:58:55.950845 DUTY Scan : NO K
9124 13:58:55.954559 ZQ Calibration : PASS
9125 13:58:55.955139 Jitter Meter : NO K
9126 13:58:55.956921 CBT Training : PASS
9127 13:58:55.960551 Write leveling : PASS
9128 13:58:55.961072 RX DQS gating : PASS
9129 13:58:55.963682 RX DQ/DQS(RDDQC) : PASS
9130 13:58:55.967262 TX DQ/DQS : PASS
9131 13:58:55.967827 RX DATLAT : PASS
9132 13:58:55.970488 RX DQ/DQS(Engine): PASS
9133 13:58:55.971084 TX OE : PASS
9134 13:58:55.973682 All Pass.
9135 13:58:55.974198
9136 13:58:55.974672 CH 1, Rank 0
9137 13:58:55.977241 SW Impedance : PASS
9138 13:58:55.977711 DUTY Scan : NO K
9139 13:58:55.980415 ZQ Calibration : PASS
9140 13:58:55.984245 Jitter Meter : NO K
9141 13:58:55.984883 CBT Training : PASS
9142 13:58:55.986926 Write leveling : PASS
9143 13:58:55.990773 RX DQS gating : PASS
9144 13:58:55.991405 RX DQ/DQS(RDDQC) : PASS
9145 13:58:55.994088 TX DQ/DQS : PASS
9146 13:58:55.997426 RX DATLAT : PASS
9147 13:58:55.998142 RX DQ/DQS(Engine): PASS
9148 13:58:56.000633 TX OE : PASS
9149 13:58:56.001137 All Pass.
9150 13:58:56.001496
9151 13:58:56.003931 CH 1, Rank 1
9152 13:58:56.004482 SW Impedance : PASS
9153 13:58:56.007237 DUTY Scan : NO K
9154 13:58:56.010845 ZQ Calibration : PASS
9155 13:58:56.011400 Jitter Meter : NO K
9156 13:58:56.014043 CBT Training : PASS
9157 13:58:56.014599 Write leveling : PASS
9158 13:58:56.017694 RX DQS gating : PASS
9159 13:58:56.020466 RX DQ/DQS(RDDQC) : PASS
9160 13:58:56.020982 TX DQ/DQS : PASS
9161 13:58:56.024221 RX DATLAT : PASS
9162 13:58:56.027070 RX DQ/DQS(Engine): PASS
9163 13:58:56.027541 TX OE : PASS
9164 13:58:56.030638 All Pass.
9165 13:58:56.031191
9166 13:58:56.031551 DramC Write-DBI on
9167 13:58:56.034001 PER_BANK_REFRESH: Hybrid Mode
9168 13:58:56.034561 TX_TRACKING: ON
9169 13:58:56.044022 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9170 13:58:56.054147 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9171 13:58:56.060778 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9172 13:58:56.064098 [FAST_K] Save calibration result to emmc
9173 13:58:56.067528 sync common calibartion params.
9174 13:58:56.068097 sync cbt_mode0:1, 1:1
9175 13:58:56.070765 dram_init: ddr_geometry: 2
9176 13:58:56.074503 dram_init: ddr_geometry: 2
9177 13:58:56.075050 dram_init: ddr_geometry: 2
9178 13:58:56.077579 0:dram_rank_size:100000000
9179 13:58:56.081316 1:dram_rank_size:100000000
9180 13:58:56.084431 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9181 13:58:56.087274 DFS_SHUFFLE_HW_MODE: ON
9182 13:58:56.091140 dramc_set_vcore_voltage set vcore to 725000
9183 13:58:56.094272 Read voltage for 1600, 0
9184 13:58:56.094830 Vio18 = 0
9185 13:58:56.097311 Vcore = 725000
9186 13:58:56.097875 Vdram = 0
9187 13:58:56.098318 Vddq = 0
9188 13:58:56.098876 Vmddr = 0
9189 13:58:56.100812 switch to 3200 Mbps bootup
9190 13:58:56.104215 [DramcRunTimeConfig]
9191 13:58:56.104821 PHYPLL
9192 13:58:56.107819 DPM_CONTROL_AFTERK: ON
9193 13:58:56.108399 PER_BANK_REFRESH: ON
9194 13:58:56.110880 REFRESH_OVERHEAD_REDUCTION: ON
9195 13:58:56.114691 CMD_PICG_NEW_MODE: OFF
9196 13:58:56.115247 XRTWTW_NEW_MODE: ON
9197 13:58:56.117732 XRTRTR_NEW_MODE: ON
9198 13:58:56.118187 TX_TRACKING: ON
9199 13:58:56.121301 RDSEL_TRACKING: OFF
9200 13:58:56.121823 DQS Precalculation for DVFS: ON
9201 13:58:56.124386 RX_TRACKING: OFF
9202 13:58:56.124979 HW_GATING DBG: ON
9203 13:58:56.127689 ZQCS_ENABLE_LP4: ON
9204 13:58:56.128140 RX_PICG_NEW_MODE: ON
9205 13:58:56.130852 TX_PICG_NEW_MODE: ON
9206 13:58:56.134889 ENABLE_RX_DCM_DPHY: ON
9207 13:58:56.138132 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9208 13:58:56.138693 DUMMY_READ_FOR_TRACKING: OFF
9209 13:58:56.141623 !!! SPM_CONTROL_AFTERK: OFF
9210 13:58:56.144833 !!! SPM could not control APHY
9211 13:58:56.148362 IMPEDANCE_TRACKING: ON
9212 13:58:56.149000 TEMP_SENSOR: ON
9213 13:58:56.150844 HW_SAVE_FOR_SR: OFF
9214 13:58:56.151296 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9215 13:58:56.157940 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9216 13:58:56.158492 Read ODT Tracking: ON
9217 13:58:56.161376 Refresh Rate DeBounce: ON
9218 13:58:56.161926 DFS_NO_QUEUE_FLUSH: ON
9219 13:58:56.164573 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9220 13:58:56.167858 ENABLE_DFS_RUNTIME_MRW: OFF
9221 13:58:56.171425 DDR_RESERVE_NEW_MODE: ON
9222 13:58:56.172078 MR_CBT_SWITCH_FREQ: ON
9223 13:58:56.174312 =========================
9224 13:58:56.194001 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9225 13:58:56.197326 dram_init: ddr_geometry: 2
9226 13:58:56.215616 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9227 13:58:56.218645 dram_init: dram init end (result: 0)
9228 13:58:56.225458 DRAM-K: Full calibration passed in 24582 msecs
9229 13:58:56.228907 MRC: failed to locate region type 0.
9230 13:58:56.229364 DRAM rank0 size:0x100000000,
9231 13:58:56.232141 DRAM rank1 size=0x100000000
9232 13:58:56.242113 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9233 13:58:56.248791 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9234 13:58:56.255564 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9235 13:58:56.262090 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9236 13:58:56.265455 DRAM rank0 size:0x100000000,
9237 13:58:56.269620 DRAM rank1 size=0x100000000
9238 13:58:56.270183 CBMEM:
9239 13:58:56.272245 IMD: root @ 0xfffff000 254 entries.
9240 13:58:56.275888 IMD: root @ 0xffffec00 62 entries.
9241 13:58:56.278905 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9242 13:58:56.282354 WARNING: RO_VPD is uninitialized or empty.
9243 13:58:56.289243 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9244 13:58:56.295688 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9245 13:58:56.308146 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9246 13:58:56.319718 BS: romstage times (exec / console): total (unknown) / 24089 ms
9247 13:58:56.320262
9248 13:58:56.320623
9249 13:58:56.329870 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9250 13:58:56.333118 ARM64: Exception handlers installed.
9251 13:58:56.336254 ARM64: Testing exception
9252 13:58:56.339450 ARM64: Done test exception
9253 13:58:56.339907 Enumerating buses...
9254 13:58:56.343384 Show all devs... Before device enumeration.
9255 13:58:56.347048 Root Device: enabled 1
9256 13:58:56.349785 CPU_CLUSTER: 0: enabled 1
9257 13:58:56.350243 CPU: 00: enabled 1
9258 13:58:56.352915 Compare with tree...
9259 13:58:56.353368 Root Device: enabled 1
9260 13:58:56.356135 CPU_CLUSTER: 0: enabled 1
9261 13:58:56.360158 CPU: 00: enabled 1
9262 13:58:56.360776 Root Device scanning...
9263 13:58:56.363426 scan_static_bus for Root Device
9264 13:58:56.366400 CPU_CLUSTER: 0 enabled
9265 13:58:56.370088 scan_static_bus for Root Device done
9266 13:58:56.373094 scan_bus: bus Root Device finished in 8 msecs
9267 13:58:56.373641 done
9268 13:58:56.379651 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9269 13:58:56.382941 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9270 13:58:56.389979 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9271 13:58:56.393400 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9272 13:58:56.396789 Allocating resources...
9273 13:58:56.397247 Reading resources...
9274 13:58:56.402842 Root Device read_resources bus 0 link: 0
9275 13:58:56.403305 DRAM rank0 size:0x100000000,
9276 13:58:56.406307 DRAM rank1 size=0x100000000
9277 13:58:56.410093 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9278 13:58:56.412873 CPU: 00 missing read_resources
9279 13:58:56.416484 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9280 13:58:56.423234 Root Device read_resources bus 0 link: 0 done
9281 13:58:56.423793 Done reading resources.
9282 13:58:56.429711 Show resources in subtree (Root Device)...After reading.
9283 13:58:56.432911 Root Device child on link 0 CPU_CLUSTER: 0
9284 13:58:56.436818 CPU_CLUSTER: 0 child on link 0 CPU: 00
9285 13:58:56.446562 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9286 13:58:56.447125 CPU: 00
9287 13:58:56.449694 Root Device assign_resources, bus 0 link: 0
9288 13:58:56.453146 CPU_CLUSTER: 0 missing set_resources
9289 13:58:56.456890 Root Device assign_resources, bus 0 link: 0 done
9290 13:58:56.460075 Done setting resources.
9291 13:58:56.466557 Show resources in subtree (Root Device)...After assigning values.
9292 13:58:56.470360 Root Device child on link 0 CPU_CLUSTER: 0
9293 13:58:56.473657 CPU_CLUSTER: 0 child on link 0 CPU: 00
9294 13:58:56.480050 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9295 13:58:56.483292 CPU: 00
9296 13:58:56.487563 Done allocating resources.
9297 13:58:56.490487 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9298 13:58:56.493448 Enabling resources...
9299 13:58:56.494000 done.
9300 13:58:56.496976 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9301 13:58:56.500192 Initializing devices...
9302 13:58:56.500814 Root Device init
9303 13:58:56.503698 init hardware done!
9304 13:58:56.507638 0x00000018: ctrlr->caps
9305 13:58:56.508105 52.000 MHz: ctrlr->f_max
9306 13:58:56.510575 0.400 MHz: ctrlr->f_min
9307 13:58:56.513421 0x40ff8080: ctrlr->voltages
9308 13:58:56.513889 sclk: 390625
9309 13:58:56.514251 Bus Width = 1
9310 13:58:56.516562 sclk: 390625
9311 13:58:56.517165 Bus Width = 1
9312 13:58:56.520843 Early init status = 3
9313 13:58:56.523507 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9314 13:58:56.528450 in-header: 03 fc 00 00 01 00 00 00
9315 13:58:56.531593 in-data: 00
9316 13:58:56.534852 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9317 13:58:56.540633 in-header: 03 fd 00 00 00 00 00 00
9318 13:58:56.544015 in-data:
9319 13:58:56.547182 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9320 13:58:56.551692 in-header: 03 fc 00 00 01 00 00 00
9321 13:58:56.555248 in-data: 00
9322 13:58:56.558363 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9323 13:58:56.564210 in-header: 03 fd 00 00 00 00 00 00
9324 13:58:56.566927 in-data:
9325 13:58:56.570437 [SSUSB] Setting up USB HOST controller...
9326 13:58:56.573866 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9327 13:58:56.577353 [SSUSB] phy power-on done.
9328 13:58:56.580232 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9329 13:58:56.587275 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9330 13:58:56.590987 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9331 13:58:56.597555 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9332 13:58:56.603926 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9333 13:58:56.611072 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9334 13:58:56.617740 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9335 13:58:56.620602 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9336 13:58:56.624343 SPM: binary array size = 0x9dc
9337 13:58:56.630896 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9338 13:58:56.637298 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9339 13:58:56.644301 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9340 13:58:56.647636 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9341 13:58:56.651112 configure_display: Starting display init
9342 13:58:56.687299 anx7625_power_on_init: Init interface.
9343 13:58:56.690543 anx7625_disable_pd_protocol: Disabled PD feature.
9344 13:58:56.693630 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9345 13:58:56.721230 anx7625_start_dp_work: Secure OCM version=00
9346 13:58:56.724805 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9347 13:58:56.739200 sp_tx_get_edid_block: EDID Block = 1
9348 13:58:56.842363 Extracted contents:
9349 13:58:56.846330 header: 00 ff ff ff ff ff ff 00
9350 13:58:56.848889 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9351 13:58:56.852009 version: 01 04
9352 13:58:56.855328 basic params: 95 1f 11 78 0a
9353 13:58:56.858979 chroma info: 76 90 94 55 54 90 27 21 50 54
9354 13:58:56.862406 established: 00 00 00
9355 13:58:56.869105 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9356 13:58:56.871955 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9357 13:58:56.878415 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9358 13:58:56.885619 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9359 13:58:56.891956 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9360 13:58:56.895293 extensions: 00
9361 13:58:56.895840 checksum: fb
9362 13:58:56.896202
9363 13:58:56.898610 Manufacturer: IVO Model 57d Serial Number 0
9364 13:58:56.901847 Made week 0 of 2020
9365 13:58:56.902444 EDID version: 1.4
9366 13:58:56.905589 Digital display
9367 13:58:56.908846 6 bits per primary color channel
9368 13:58:56.909397 DisplayPort interface
9369 13:58:56.912357 Maximum image size: 31 cm x 17 cm
9370 13:58:56.915526 Gamma: 220%
9371 13:58:56.916067 Check DPMS levels
9372 13:58:56.918760 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9373 13:58:56.922220 First detailed timing is preferred timing
9374 13:58:56.925375 Established timings supported:
9375 13:58:56.928735 Standard timings supported:
9376 13:58:56.929195 Detailed timings
9377 13:58:56.935665 Hex of detail: 383680a07038204018303c0035ae10000019
9378 13:58:56.938418 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9379 13:58:56.941879 0780 0798 07c8 0820 hborder 0
9380 13:58:56.948537 0438 043b 0447 0458 vborder 0
9381 13:58:56.949055 -hsync -vsync
9382 13:58:56.952154 Did detailed timing
9383 13:58:56.955410 Hex of detail: 000000000000000000000000000000000000
9384 13:58:56.958738 Manufacturer-specified data, tag 0
9385 13:58:56.965548 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9386 13:58:56.966113 ASCII string: InfoVision
9387 13:58:56.972331 Hex of detail: 000000fe00523134304e574635205248200a
9388 13:58:56.972944 ASCII string: R140NWF5 RH
9389 13:58:56.975255 Checksum
9390 13:58:56.975813 Checksum: 0xfb (valid)
9391 13:58:56.981843 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9392 13:58:56.982404 DSI data_rate: 832800000 bps
9393 13:58:56.989625 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9394 13:58:56.993577 anx7625_parse_edid: pixelclock(138800).
9395 13:58:56.996437 hactive(1920), hsync(48), hfp(24), hbp(88)
9396 13:58:56.999704 vactive(1080), vsync(12), vfp(3), vbp(17)
9397 13:58:57.002739 anx7625_dsi_config: config dsi.
9398 13:58:57.010283 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9399 13:58:57.023979 anx7625_dsi_config: success to config DSI
9400 13:58:57.027438 anx7625_dp_start: MIPI phy setup OK.
9401 13:58:57.031063 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9402 13:58:57.034131 mtk_ddp_mode_set invalid vrefresh 60
9403 13:58:57.037679 main_disp_path_setup
9404 13:58:57.038238 ovl_layer_smi_id_en
9405 13:58:57.040976 ovl_layer_smi_id_en
9406 13:58:57.041556 ccorr_config
9407 13:58:57.041924 aal_config
9408 13:58:57.044407 gamma_config
9409 13:58:57.044928 postmask_config
9410 13:58:57.047545 dither_config
9411 13:58:57.050488 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9412 13:58:57.057143 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9413 13:58:57.060804 Root Device init finished in 555 msecs
9414 13:58:57.061269 CPU_CLUSTER: 0 init
9415 13:58:57.070812 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9416 13:58:57.074765 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9417 13:58:57.077188 APU_MBOX 0x190000b0 = 0x10001
9418 13:58:57.081123 APU_MBOX 0x190001b0 = 0x10001
9419 13:58:57.084227 APU_MBOX 0x190005b0 = 0x10001
9420 13:58:57.087553 APU_MBOX 0x190006b0 = 0x10001
9421 13:58:57.090907 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9422 13:58:57.103053 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9423 13:58:57.115828 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9424 13:58:57.121780 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9425 13:58:57.134130 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9426 13:58:57.142730 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9427 13:58:57.145940 CPU_CLUSTER: 0 init finished in 81 msecs
9428 13:58:57.149424 Devices initialized
9429 13:58:57.152828 Show all devs... After init.
9430 13:58:57.153380 Root Device: enabled 1
9431 13:58:57.156492 CPU_CLUSTER: 0: enabled 1
9432 13:58:57.160121 CPU: 00: enabled 1
9433 13:58:57.163097 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9434 13:58:57.166363 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9435 13:58:57.169625 ELOG: NV offset 0x57f000 size 0x1000
9436 13:58:57.176100 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9437 13:58:57.183219 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9438 13:58:57.186103 ELOG: Event(17) added with size 13 at 2023-08-28 13:59:00 UTC
9439 13:58:57.189588 out: cmd=0x121: 03 db 21 01 00 00 00 00
9440 13:58:57.193853 in-header: 03 d4 00 00 2c 00 00 00
9441 13:58:57.207077 in-data: 8b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9442 13:58:57.214735 ELOG: Event(A1) added with size 10 at 2023-08-28 13:59:00 UTC
9443 13:58:57.221316 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9444 13:58:57.224422 ELOG: Event(A0) added with size 9 at 2023-08-28 13:59:00 UTC
9445 13:58:57.230965 elog_add_boot_reason: Logged dev mode boot
9446 13:58:57.234583 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9447 13:58:57.237867 Finalize devices...
9448 13:58:57.238415 Devices finalized
9449 13:58:57.244730 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9450 13:58:57.247594 Writing coreboot table at 0xffe64000
9451 13:58:57.250926 0. 000000000010a000-0000000000113fff: RAMSTAGE
9452 13:58:57.254273 1. 0000000040000000-00000000400fffff: RAM
9453 13:58:57.257741 2. 0000000040100000-000000004032afff: RAMSTAGE
9454 13:58:57.264445 3. 000000004032b000-00000000545fffff: RAM
9455 13:58:57.267558 4. 0000000054600000-000000005465ffff: BL31
9456 13:58:57.271305 5. 0000000054660000-00000000ffe63fff: RAM
9457 13:58:57.274376 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9458 13:58:57.280993 7. 0000000100000000-000000023fffffff: RAM
9459 13:58:57.281568 Passing 5 GPIOs to payload:
9460 13:58:57.287695 NAME | PORT | POLARITY | VALUE
9461 13:58:57.291425 EC in RW | 0x000000aa | low | undefined
9462 13:58:57.294222 EC interrupt | 0x00000005 | low | undefined
9463 13:58:57.301322 TPM interrupt | 0x000000ab | high | undefined
9464 13:58:57.304250 SD card detect | 0x00000011 | high | undefined
9465 13:58:57.311181 speaker enable | 0x00000093 | high | undefined
9466 13:58:57.314388 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9467 13:58:57.317960 in-header: 03 f9 00 00 02 00 00 00
9468 13:58:57.318424 in-data: 02 00
9469 13:58:57.321491 ADC[4]: Raw value=899483 ID=7
9470 13:58:57.324153 ADC[3]: Raw value=212967 ID=1
9471 13:58:57.324618 RAM Code: 0x71
9472 13:58:57.328081 ADC[6]: Raw value=74557 ID=0
9473 13:58:57.330789 ADC[5]: Raw value=211860 ID=1
9474 13:58:57.331238 SKU Code: 0x1
9475 13:58:57.337684 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ae81
9476 13:58:57.340808 coreboot table: 964 bytes.
9477 13:58:57.344166 IMD ROOT 0. 0xfffff000 0x00001000
9478 13:58:57.347510 IMD SMALL 1. 0xffffe000 0x00001000
9479 13:58:57.351117 RO MCACHE 2. 0xffffc000 0x00001104
9480 13:58:57.354251 CONSOLE 3. 0xfff7c000 0x00080000
9481 13:58:57.357928 FMAP 4. 0xfff7b000 0x00000452
9482 13:58:57.360895 TIME STAMP 5. 0xfff7a000 0x00000910
9483 13:58:57.361344 VBOOT WORK 6. 0xfff66000 0x00014000
9484 13:58:57.363954 RAMOOPS 7. 0xffe66000 0x00100000
9485 13:58:57.367369 COREBOOT 8. 0xffe64000 0x00002000
9486 13:58:57.370926 IMD small region:
9487 13:58:57.374422 IMD ROOT 0. 0xffffec00 0x00000400
9488 13:58:57.377541 VPD 1. 0xffffeb80 0x0000006c
9489 13:58:57.380720 MMC STATUS 2. 0xffffeb60 0x00000004
9490 13:58:57.387410 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9491 13:58:57.387989 Probing TPM: done!
9492 13:58:57.394624 Connected to device vid:did:rid of 1ae0:0028:00
9493 13:58:57.401360 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9494 13:58:57.404348 Initialized TPM device CR50 revision 0
9495 13:58:57.407844 Checking cr50 for pending updates
9496 13:58:57.413399 Reading cr50 TPM mode
9497 13:58:57.422489 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9498 13:58:57.428987 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9499 13:58:57.468605 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9500 13:58:57.471935 Checking segment from ROM address 0x40100000
9501 13:58:57.475313 Checking segment from ROM address 0x4010001c
9502 13:58:57.482526 Loading segment from ROM address 0x40100000
9503 13:58:57.482942 code (compression=0)
9504 13:58:57.489221 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9505 13:58:57.498941 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9506 13:58:57.499362 it's not compressed!
9507 13:58:57.506286 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9508 13:58:57.508986 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9509 13:58:57.529465 Loading segment from ROM address 0x4010001c
9510 13:58:57.529886 Entry Point 0x80000000
9511 13:58:57.532638 Loaded segments
9512 13:58:57.536407 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9513 13:58:57.542598 Jumping to boot code at 0x80000000(0xffe64000)
9514 13:58:57.549176 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9515 13:58:57.555671 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9516 13:58:57.563839 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9517 13:58:57.566962 Checking segment from ROM address 0x40100000
9518 13:58:57.570320 Checking segment from ROM address 0x4010001c
9519 13:58:57.577111 Loading segment from ROM address 0x40100000
9520 13:58:57.577528 code (compression=1)
9521 13:58:57.583803 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9522 13:58:57.593787 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9523 13:58:57.593868 using LZMA
9524 13:58:57.602036 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9525 13:58:57.608495 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9526 13:58:57.611884 Loading segment from ROM address 0x4010001c
9527 13:58:57.611966 Entry Point 0x54601000
9528 13:58:57.615269 Loaded segments
9529 13:58:57.618528 NOTICE: MT8192 bl31_setup
9530 13:58:57.625237 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9531 13:58:57.628776 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9532 13:58:57.632416 WARNING: region 0:
9533 13:58:57.635768 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9534 13:58:57.635869 WARNING: region 1:
9535 13:58:57.642326 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9536 13:58:57.642508 WARNING: region 2:
9537 13:58:57.649031 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9538 13:58:57.652235 WARNING: region 3:
9539 13:58:57.655703 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9540 13:58:57.659518 WARNING: region 4:
9541 13:58:57.662662 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9542 13:58:57.666047 WARNING: region 5:
9543 13:58:57.669440 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 13:58:57.672474 WARNING: region 6:
9545 13:58:57.676054 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 13:58:57.676440 WARNING: region 7:
9547 13:58:57.683278 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 13:58:57.689790 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9549 13:58:57.693102 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9550 13:58:57.696401 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9551 13:58:57.699619 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9552 13:58:57.706264 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9553 13:58:57.709524 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9554 13:58:57.716080 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9555 13:58:57.719598 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9556 13:58:57.722822 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9557 13:58:57.729403 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9558 13:58:57.732928 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9559 13:58:57.736761 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9560 13:58:57.742878 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9561 13:58:57.746692 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9562 13:58:57.749675 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9563 13:58:57.756438 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9564 13:58:57.760015 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9565 13:58:57.763261 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9566 13:58:57.770132 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9567 13:58:57.773273 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9568 13:58:57.779620 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9569 13:58:57.783296 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9570 13:58:57.786445 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9571 13:58:57.793551 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9572 13:58:57.796508 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9573 13:58:57.803343 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9574 13:58:57.806804 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9575 13:58:57.810484 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9576 13:58:57.817118 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9577 13:58:57.820164 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9578 13:58:57.827056 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9579 13:58:57.830299 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9580 13:58:57.833674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9581 13:58:57.837489 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9582 13:58:57.840468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9583 13:58:57.847134 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9584 13:58:57.850447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9585 13:58:57.853971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9586 13:58:57.857382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9587 13:58:57.863956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9588 13:58:57.867417 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9589 13:58:57.870634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9590 13:58:57.873744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9591 13:58:57.880707 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9592 13:58:57.883980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9593 13:58:57.888065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9594 13:58:57.891306 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9595 13:58:57.896911 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9596 13:58:57.900491 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9597 13:58:57.907147 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9598 13:58:57.910232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9599 13:58:57.913811 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9600 13:58:57.920753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9601 13:58:57.923815 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9602 13:58:57.930561 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9603 13:58:57.934122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9604 13:58:57.937187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9605 13:58:57.943994 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9606 13:58:57.947549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9607 13:58:57.954026 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9608 13:58:57.957517 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9609 13:58:57.964338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9610 13:58:57.967559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9611 13:58:57.970941 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9612 13:58:57.977986 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9613 13:58:57.980808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9614 13:58:57.987490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9615 13:58:57.990941 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9616 13:58:57.998031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9617 13:58:58.001069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9618 13:58:58.005069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9619 13:58:58.011501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9620 13:58:58.014941 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9621 13:58:58.021282 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9622 13:58:58.024862 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9623 13:58:58.028363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9624 13:58:58.034892 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9625 13:58:58.038450 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9626 13:58:58.044981 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9627 13:58:58.048144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9628 13:58:58.054949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9629 13:58:58.058201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9630 13:58:58.061831 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9631 13:58:58.068490 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9632 13:58:58.071881 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9633 13:58:58.078419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9634 13:58:58.082148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9635 13:58:58.089051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9636 13:58:58.091752 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9637 13:58:58.095105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9638 13:58:58.101881 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9639 13:58:58.105253 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9640 13:58:58.112198 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9641 13:58:58.115411 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9642 13:58:58.122304 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9643 13:58:58.125278 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9644 13:58:58.128832 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9645 13:58:58.132271 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9646 13:58:58.139014 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9647 13:58:58.142462 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9648 13:58:58.145828 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9649 13:58:58.152729 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9650 13:58:58.155481 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9651 13:58:58.159225 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9652 13:58:58.165634 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9653 13:58:58.169079 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9654 13:58:58.172271 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9655 13:58:58.179290 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9656 13:58:58.182475 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9657 13:58:58.189340 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9658 13:58:58.192229 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9659 13:58:58.196209 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9660 13:58:58.202659 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9661 13:58:58.205907 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9662 13:58:58.212476 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9663 13:58:58.215902 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9664 13:58:58.219188 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9665 13:58:58.222537 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9666 13:58:58.229005 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9667 13:58:58.232611 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9668 13:58:58.235991 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9669 13:58:58.239371 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9670 13:58:58.246737 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9671 13:58:58.249463 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9672 13:58:58.253009 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9673 13:58:58.259458 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9674 13:58:58.263240 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9675 13:58:58.266481 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9676 13:58:58.273371 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9677 13:58:58.276313 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9678 13:58:58.283160 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9679 13:58:58.286848 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9680 13:58:58.289928 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9681 13:58:58.296451 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9682 13:58:58.299771 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9683 13:58:58.303324 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9684 13:58:58.310294 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9685 13:58:58.313243 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9686 13:58:58.320026 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9687 13:58:58.323613 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9688 13:58:58.327311 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9689 13:58:58.333759 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9690 13:58:58.336653 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9691 13:58:58.343871 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9692 13:58:58.346789 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9693 13:58:58.350187 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9694 13:58:58.357346 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9695 13:58:58.360375 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9696 13:58:58.364307 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9697 13:58:58.370458 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9698 13:58:58.373896 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9699 13:58:58.377445 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9700 13:58:58.384644 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9701 13:58:58.387819 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9702 13:58:58.393976 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9703 13:58:58.397681 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9704 13:58:58.401082 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9705 13:58:58.407931 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9706 13:58:58.411468 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9707 13:58:58.414783 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9708 13:58:58.421640 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9709 13:58:58.424663 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9710 13:58:58.432318 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9711 13:58:58.435150 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9712 13:58:58.438000 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9713 13:58:58.444852 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9714 13:58:58.447988 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9715 13:58:58.451747 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9716 13:58:58.458636 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9717 13:58:58.461734 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9718 13:58:58.468824 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9719 13:58:58.472144 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9720 13:58:58.474983 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9721 13:58:58.481717 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9722 13:58:58.485408 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9723 13:58:58.488784 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9724 13:58:58.495557 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9725 13:58:58.498587 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9726 13:58:58.505260 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9727 13:58:58.509166 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9728 13:58:58.511767 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9729 13:58:58.519066 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9730 13:58:58.522205 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9731 13:58:58.528769 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9732 13:58:58.532145 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9733 13:58:58.535756 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9734 13:58:58.542235 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9735 13:58:58.545192 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9736 13:58:58.548622 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9737 13:58:58.555152 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9738 13:58:58.558927 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9739 13:58:58.565305 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9740 13:58:58.569474 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9741 13:58:58.573059 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9742 13:58:58.578938 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9743 13:58:58.582174 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9744 13:58:58.589024 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9745 13:58:58.592472 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9746 13:58:58.599289 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9747 13:58:58.603000 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9748 13:58:58.605302 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9749 13:58:58.612343 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9750 13:58:58.615535 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9751 13:58:58.622595 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9752 13:58:58.625408 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9753 13:58:58.629413 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9754 13:58:58.635768 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9755 13:58:58.639247 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9756 13:58:58.645510 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9757 13:58:58.649151 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9758 13:58:58.652832 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9759 13:58:58.659449 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9760 13:58:58.662654 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9761 13:58:58.669069 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9762 13:58:58.672299 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9763 13:58:58.675926 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9764 13:58:58.682687 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9765 13:58:58.686060 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9766 13:58:58.693082 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9767 13:58:58.696097 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9768 13:58:58.702837 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9769 13:58:58.706161 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9770 13:58:58.708946 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9771 13:58:58.715484 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9772 13:58:58.719119 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9773 13:58:58.725612 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9774 13:58:58.729678 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9775 13:58:58.732936 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9776 13:58:58.739411 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9777 13:58:58.742735 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9778 13:58:58.745846 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9779 13:58:58.749828 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9780 13:58:58.752755 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9781 13:58:58.759855 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9782 13:58:58.763299 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9783 13:58:58.766151 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9784 13:58:58.773321 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9785 13:58:58.776505 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9786 13:58:58.779457 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9787 13:58:58.786374 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9788 13:58:58.789590 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9789 13:58:58.796245 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9790 13:58:58.799688 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9791 13:58:58.803148 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9792 13:58:58.809549 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9793 13:58:58.812628 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9794 13:58:58.815819 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9795 13:58:58.823303 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9796 13:58:58.826060 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9797 13:58:58.829570 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9798 13:58:58.836405 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9799 13:58:58.839810 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9800 13:58:58.846867 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9801 13:58:58.849425 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9802 13:58:58.852990 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9803 13:58:58.860167 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9804 13:58:58.863271 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9805 13:58:58.866331 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9806 13:58:58.873214 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9807 13:58:58.876948 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9808 13:58:58.880567 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9809 13:58:58.886891 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9810 13:58:58.890066 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9811 13:58:58.893701 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9812 13:58:58.900158 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9813 13:58:58.903448 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9814 13:58:58.909876 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9815 13:58:58.913298 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9816 13:58:58.916745 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9817 13:58:58.920196 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9818 13:58:58.926728 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9819 13:58:58.930389 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9820 13:58:58.933393 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9821 13:58:58.936894 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9822 13:58:58.939863 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9823 13:58:58.946878 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9824 13:58:58.950249 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9825 13:58:58.953452 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9826 13:58:58.956755 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9827 13:58:58.963906 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9828 13:58:58.966916 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9829 13:58:58.970060 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9830 13:58:58.976921 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9831 13:58:58.980191 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9832 13:58:58.983421 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9833 13:58:58.990707 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9834 13:58:58.993736 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9835 13:58:59.000789 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9836 13:58:59.003783 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9837 13:58:59.007538 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9838 13:58:59.013894 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9839 13:58:59.017033 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9840 13:58:59.023926 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9841 13:58:59.026805 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9842 13:58:59.030039 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9843 13:58:59.037312 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9844 13:58:59.040856 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9845 13:58:59.047069 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9846 13:58:59.050406 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9847 13:58:59.054365 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9848 13:58:59.060338 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9849 13:58:59.064136 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9850 13:58:59.070194 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9851 13:58:59.073756 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9852 13:58:59.080178 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9853 13:58:59.083865 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9854 13:58:59.086895 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9855 13:58:59.093518 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9856 13:58:59.096611 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9857 13:58:59.103593 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9858 13:58:59.107409 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9859 13:58:59.110030 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9860 13:58:59.116483 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9861 13:58:59.120312 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9862 13:58:59.126858 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9863 13:58:59.130118 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9864 13:58:59.133403 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9865 13:58:59.140197 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9866 13:58:59.143710 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9867 13:58:59.150137 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9868 13:58:59.153441 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9869 13:58:59.156925 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9870 13:58:59.163812 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9871 13:58:59.166939 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9872 13:58:59.173742 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9873 13:58:59.177164 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9874 13:58:59.180183 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9875 13:58:59.186786 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9876 13:58:59.190319 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9877 13:58:59.196925 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9878 13:58:59.200148 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9879 13:58:59.203798 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9880 13:58:59.210450 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9881 13:58:59.213414 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9882 13:58:59.220450 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9883 13:58:59.223411 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9884 13:58:59.226552 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9885 13:58:59.233627 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9886 13:58:59.236574 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9887 13:58:59.243448 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9888 13:58:59.246876 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9889 13:58:59.250364 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9890 13:58:59.257114 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9891 13:58:59.260418 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9892 13:58:59.267153 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9893 13:58:59.270062 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9894 13:58:59.273654 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9895 13:58:59.280428 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9896 13:58:59.283897 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9897 13:58:59.290639 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9898 13:58:59.293422 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9899 13:58:59.297135 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9900 13:58:59.303685 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9901 13:58:59.307329 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9902 13:58:59.313782 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9903 13:58:59.316780 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9904 13:58:59.323265 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9905 13:58:59.327063 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9906 13:58:59.329968 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9907 13:58:59.336646 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9908 13:58:59.339984 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9909 13:58:59.346940 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9910 13:58:59.350420 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9911 13:58:59.353705 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9912 13:58:59.359898 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9913 13:58:59.363577 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9914 13:58:59.369807 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9915 13:58:59.373088 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9916 13:58:59.380003 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9917 13:58:59.383262 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9918 13:58:59.386365 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9919 13:58:59.392966 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9920 13:58:59.396547 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9921 13:58:59.403141 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9922 13:58:59.406346 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9923 13:58:59.413294 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9924 13:58:59.416267 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9925 13:58:59.420245 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9926 13:58:59.426470 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9927 13:58:59.429887 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9928 13:58:59.436580 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9929 13:58:59.439775 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9930 13:58:59.446399 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9931 13:58:59.449722 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9932 13:58:59.456069 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9933 13:58:59.459861 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9934 13:58:59.463002 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9935 13:58:59.469599 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9936 13:58:59.472862 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9937 13:58:59.479731 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9938 13:58:59.483119 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9939 13:58:59.489875 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9940 13:58:59.493217 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9941 13:58:59.496643 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9942 13:58:59.503832 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9943 13:58:59.506727 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9944 13:58:59.513349 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9945 13:58:59.516482 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9946 13:58:59.523635 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9947 13:58:59.526959 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9948 13:58:59.530111 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9949 13:58:59.536638 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9950 13:58:59.540303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9951 13:58:59.543308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9952 13:58:59.550108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9953 13:58:59.553251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9954 13:58:59.559898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9955 13:58:59.563275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9956 13:58:59.570264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9957 13:58:59.573284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9958 13:58:59.579807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9959 13:58:59.583180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9960 13:58:59.589628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9961 13:58:59.592954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9962 13:58:59.599848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9963 13:58:59.603014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9964 13:58:59.609577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9965 13:58:59.613048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9966 13:58:59.620188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9967 13:58:59.622927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9968 13:58:59.629927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9969 13:58:59.632734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9970 13:58:59.636121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9971 13:58:59.643375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9972 13:58:59.646116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9973 13:58:59.652995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9974 13:58:59.656216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9975 13:58:59.662962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9976 13:58:59.666556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9977 13:58:59.672919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9978 13:58:59.676193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9979 13:58:59.683004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9980 13:58:59.686587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9981 13:58:59.693687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9982 13:58:59.697081 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9983 13:58:59.700057 INFO: [APUAPC] vio 0
9984 13:58:59.703538 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9985 13:58:59.709953 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9986 13:58:59.713294 INFO: [APUAPC] D0_APC_0: 0x400510
9987 13:58:59.716681 INFO: [APUAPC] D0_APC_1: 0x0
9988 13:58:59.716885 INFO: [APUAPC] D0_APC_2: 0x1540
9989 13:58:59.719974 INFO: [APUAPC] D0_APC_3: 0x0
9990 13:58:59.723673 INFO: [APUAPC] D1_APC_0: 0xffffffff
9991 13:58:59.726601 INFO: [APUAPC] D1_APC_1: 0xffffffff
9992 13:58:59.730663 INFO: [APUAPC] D1_APC_2: 0x3fffff
9993 13:58:59.733350 INFO: [APUAPC] D1_APC_3: 0x0
9994 13:58:59.736661 INFO: [APUAPC] D2_APC_0: 0xffffffff
9995 13:58:59.740298 INFO: [APUAPC] D2_APC_1: 0xffffffff
9996 13:58:59.743217 INFO: [APUAPC] D2_APC_2: 0x3fffff
9997 13:58:59.747211 INFO: [APUAPC] D2_APC_3: 0x0
9998 13:58:59.750489 INFO: [APUAPC] D3_APC_0: 0xffffffff
9999 13:58:59.753267 INFO: [APUAPC] D3_APC_1: 0xffffffff
10000 13:58:59.756660 INFO: [APUAPC] D3_APC_2: 0x3fffff
10001 13:58:59.759997 INFO: [APUAPC] D3_APC_3: 0x0
10002 13:58:59.763486 INFO: [APUAPC] D4_APC_0: 0xffffffff
10003 13:58:59.767485 INFO: [APUAPC] D4_APC_1: 0xffffffff
10004 13:58:59.770617 INFO: [APUAPC] D4_APC_2: 0x3fffff
10005 13:58:59.773841 INFO: [APUAPC] D4_APC_3: 0x0
10006 13:58:59.777160 INFO: [APUAPC] D5_APC_0: 0xffffffff
10007 13:58:59.780444 INFO: [APUAPC] D5_APC_1: 0xffffffff
10008 13:58:59.783657 INFO: [APUAPC] D5_APC_2: 0x3fffff
10009 13:58:59.787055 INFO: [APUAPC] D5_APC_3: 0x0
10010 13:58:59.791391 INFO: [APUAPC] D6_APC_0: 0xffffffff
10011 13:58:59.793973 INFO: [APUAPC] D6_APC_1: 0xffffffff
10012 13:58:59.797248 INFO: [APUAPC] D6_APC_2: 0x3fffff
10013 13:58:59.800322 INFO: [APUAPC] D6_APC_3: 0x0
10014 13:58:59.803865 INFO: [APUAPC] D7_APC_0: 0xffffffff
10015 13:58:59.807186 INFO: [APUAPC] D7_APC_1: 0xffffffff
10016 13:58:59.810360 INFO: [APUAPC] D7_APC_2: 0x3fffff
10017 13:58:59.813778 INFO: [APUAPC] D7_APC_3: 0x0
10018 13:58:59.817677 INFO: [APUAPC] D8_APC_0: 0xffffffff
10019 13:58:59.820243 INFO: [APUAPC] D8_APC_1: 0xffffffff
10020 13:58:59.823896 INFO: [APUAPC] D8_APC_2: 0x3fffff
10021 13:58:59.824312 INFO: [APUAPC] D8_APC_3: 0x0
10022 13:58:59.827177 INFO: [APUAPC] D9_APC_0: 0xffffffff
10023 13:58:59.830522 INFO: [APUAPC] D9_APC_1: 0xffffffff
10024 13:58:59.833799 INFO: [APUAPC] D9_APC_2: 0x3fffff
10025 13:58:59.837048 INFO: [APUAPC] D9_APC_3: 0x0
10026 13:58:59.840071 INFO: [APUAPC] D10_APC_0: 0xffffffff
10027 13:58:59.843637 INFO: [APUAPC] D10_APC_1: 0xffffffff
10028 13:58:59.846748 INFO: [APUAPC] D10_APC_2: 0x3fffff
10029 13:58:59.850217 INFO: [APUAPC] D10_APC_3: 0x0
10030 13:58:59.853780 INFO: [APUAPC] D11_APC_0: 0xffffffff
10031 13:58:59.857113 INFO: [APUAPC] D11_APC_1: 0xffffffff
10032 13:58:59.860223 INFO: [APUAPC] D11_APC_2: 0x3fffff
10033 13:58:59.864131 INFO: [APUAPC] D11_APC_3: 0x0
10034 13:58:59.866839 INFO: [APUAPC] D12_APC_0: 0xffffffff
10035 13:58:59.870139 INFO: [APUAPC] D12_APC_1: 0xffffffff
10036 13:58:59.873735 INFO: [APUAPC] D12_APC_2: 0x3fffff
10037 13:58:59.877285 INFO: [APUAPC] D12_APC_3: 0x0
10038 13:58:59.880642 INFO: [APUAPC] D13_APC_0: 0xffffffff
10039 13:58:59.884334 INFO: [APUAPC] D13_APC_1: 0xffffffff
10040 13:58:59.887304 INFO: [APUAPC] D13_APC_2: 0x3fffff
10041 13:58:59.890439 INFO: [APUAPC] D13_APC_3: 0x0
10042 13:58:59.894323 INFO: [APUAPC] D14_APC_0: 0xffffffff
10043 13:58:59.897415 INFO: [APUAPC] D14_APC_1: 0xffffffff
10044 13:58:59.900684 INFO: [APUAPC] D14_APC_2: 0x3fffff
10045 13:58:59.903737 INFO: [APUAPC] D14_APC_3: 0x0
10046 13:58:59.907488 INFO: [APUAPC] D15_APC_0: 0xffffffff
10047 13:58:59.911077 INFO: [APUAPC] D15_APC_1: 0xffffffff
10048 13:58:59.914013 INFO: [APUAPC] D15_APC_2: 0x3fffff
10049 13:58:59.917490 INFO: [APUAPC] D15_APC_3: 0x0
10050 13:58:59.921214 INFO: [APUAPC] APC_CON: 0x4
10051 13:58:59.924171 INFO: [NOCDAPC] D0_APC_0: 0x0
10052 13:58:59.928234 INFO: [NOCDAPC] D0_APC_1: 0x0
10053 13:58:59.930686 INFO: [NOCDAPC] D1_APC_0: 0x0
10054 13:58:59.934447 INFO: [NOCDAPC] D1_APC_1: 0xfff
10055 13:58:59.937302 INFO: [NOCDAPC] D2_APC_0: 0x0
10056 13:58:59.937874 INFO: [NOCDAPC] D2_APC_1: 0xfff
10057 13:58:59.941202 INFO: [NOCDAPC] D3_APC_0: 0x0
10058 13:58:59.944057 INFO: [NOCDAPC] D3_APC_1: 0xfff
10059 13:58:59.947821 INFO: [NOCDAPC] D4_APC_0: 0x0
10060 13:58:59.951101 INFO: [NOCDAPC] D4_APC_1: 0xfff
10061 13:58:59.954539 INFO: [NOCDAPC] D5_APC_0: 0x0
10062 13:58:59.957319 INFO: [NOCDAPC] D5_APC_1: 0xfff
10063 13:58:59.960740 INFO: [NOCDAPC] D6_APC_0: 0x0
10064 13:58:59.964324 INFO: [NOCDAPC] D6_APC_1: 0xfff
10065 13:58:59.967846 INFO: [NOCDAPC] D7_APC_0: 0x0
10066 13:58:59.970608 INFO: [NOCDAPC] D7_APC_1: 0xfff
10067 13:58:59.971026 INFO: [NOCDAPC] D8_APC_0: 0x0
10068 13:58:59.973973 INFO: [NOCDAPC] D8_APC_1: 0xfff
10069 13:58:59.977575 INFO: [NOCDAPC] D9_APC_0: 0x0
10070 13:58:59.980773 INFO: [NOCDAPC] D9_APC_1: 0xfff
10071 13:58:59.984428 INFO: [NOCDAPC] D10_APC_0: 0x0
10072 13:58:59.987631 INFO: [NOCDAPC] D10_APC_1: 0xfff
10073 13:58:59.991118 INFO: [NOCDAPC] D11_APC_0: 0x0
10074 13:58:59.994167 INFO: [NOCDAPC] D11_APC_1: 0xfff
10075 13:58:59.997596 INFO: [NOCDAPC] D12_APC_0: 0x0
10076 13:59:00.001140 INFO: [NOCDAPC] D12_APC_1: 0xfff
10077 13:59:00.004831 INFO: [NOCDAPC] D13_APC_0: 0x0
10078 13:59:00.007642 INFO: [NOCDAPC] D13_APC_1: 0xfff
10079 13:59:00.010734 INFO: [NOCDAPC] D14_APC_0: 0x0
10080 13:59:00.014107 INFO: [NOCDAPC] D14_APC_1: 0xfff
10081 13:59:00.014562 INFO: [NOCDAPC] D15_APC_0: 0x0
10082 13:59:00.017366 INFO: [NOCDAPC] D15_APC_1: 0xfff
10083 13:59:00.020788 INFO: [NOCDAPC] APC_CON: 0x4
10084 13:59:00.024385 INFO: [APUAPC] set_apusys_apc done
10085 13:59:00.027119 INFO: [DEVAPC] devapc_init done
10086 13:59:00.030782 INFO: GICv3 without legacy support detected.
10087 13:59:00.037411 INFO: ARM GICv3 driver initialized in EL3
10088 13:59:00.040845 INFO: Maximum SPI INTID supported: 639
10089 13:59:00.044199 INFO: BL31: Initializing runtime services
10090 13:59:00.051283 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10091 13:59:00.051837 INFO: SPM: enable CPC mode
10092 13:59:00.058118 INFO: mcdi ready for mcusys-off-idle and system suspend
10093 13:59:00.061007 INFO: BL31: Preparing for EL3 exit to normal world
10094 13:59:00.067272 INFO: Entry point address = 0x80000000
10095 13:59:00.067812 INFO: SPSR = 0x8
10096 13:59:00.073718
10097 13:59:00.074238
10098 13:59:00.074603
10099 13:59:00.077336 Starting depthcharge on Spherion...
10100 13:59:00.077794
10101 13:59:00.078155 Wipe memory regions:
10102 13:59:00.078492
10103 13:59:00.081466 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10104 13:59:00.082113 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10105 13:59:00.083808 Setting prompt string to ['asurada:']
10106 13:59:00.084257 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10107 13:59:00.085081 [0x00000040000000, 0x00000054600000)
10108 13:59:00.202240
10109 13:59:00.202375 [0x00000054660000, 0x00000080000000)
10110 13:59:00.462761
10111 13:59:00.462949 [0x000000821a7280, 0x000000ffe64000)
10112 13:59:01.208525
10113 13:59:01.209160 [0x00000100000000, 0x00000240000000)
10114 13:59:03.097698
10115 13:59:03.101280 Initializing XHCI USB controller at 0x11200000.
10116 13:59:04.139033
10117 13:59:04.142129 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10118 13:59:04.142857
10119 13:59:04.143312
10120 13:59:04.143661
10121 13:59:04.144501 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10123 13:59:04.246110 asurada: tftpboot 192.168.201.1 11372189/tftp-deploy-2hykufja/kernel/image.itb 11372189/tftp-deploy-2hykufja/kernel/cmdline
10124 13:59:04.246748 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10125 13:59:04.247250 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10126 13:59:04.252268 tftpboot 192.168.201.1 11372189/tftp-deploy-2hykufja/kernel/image.ittp-deploy-2hykufja/kernel/cmdline
10127 13:59:04.252901
10128 13:59:04.253277 Waiting for link
10129 13:59:04.412113
10130 13:59:04.412704 R8152: Initializing
10131 13:59:04.413099
10132 13:59:04.415688 Version 6 (ocp_data = 5c30)
10133 13:59:04.416239
10134 13:59:04.418530 R8152: Done initializing
10135 13:59:04.418989
10136 13:59:04.419355 Adding net device
10137 13:59:06.380901
10138 13:59:06.381492 done.
10139 13:59:06.381872
10140 13:59:06.382217 MAC: 00:24:32:30:78:52
10141 13:59:06.382549
10142 13:59:06.383619 Sending DHCP discover... done.
10143 13:59:06.384077
10144 13:59:06.387447 Waiting for reply... done.
10145 13:59:06.387902
10146 13:59:06.390376 Sending DHCP request... done.
10147 13:59:06.391020
10148 13:59:06.395489 Waiting for reply... done.
10149 13:59:06.396058
10150 13:59:06.396432 My ip is 192.168.201.14
10151 13:59:06.396858
10152 13:59:06.398534 The DHCP server ip is 192.168.201.1
10153 13:59:06.398995
10154 13:59:06.405635 TFTP server IP predefined by user: 192.168.201.1
10155 13:59:06.406187
10156 13:59:06.412354 Bootfile predefined by user: 11372189/tftp-deploy-2hykufja/kernel/image.itb
10157 13:59:06.412980
10158 13:59:06.413436 Sending tftp read request... done.
10159 13:59:06.413786
10160 13:59:06.422429 Waiting for the transfer...
10161 13:59:06.423019
10162 13:59:07.116525 00000000 ################################################################
10163 13:59:07.117093
10164 13:59:07.849881 00080000 ################################################################
10165 13:59:07.850424
10166 13:59:08.544441 00100000 ################################################################
10167 13:59:08.544970
10168 13:59:09.223553 00180000 ################################################################
10169 13:59:09.224088
10170 13:59:09.950491 00200000 ################################################################
10171 13:59:09.950662
10172 13:59:10.657103 00280000 ################################################################
10173 13:59:10.657635
10174 13:59:11.385320 00300000 ################################################################
10175 13:59:11.385898
10176 13:59:12.098920 00380000 ################################################################
10177 13:59:12.099470
10178 13:59:12.831754 00400000 ################################################################
10179 13:59:12.832285
10180 13:59:13.540440 00480000 ################################################################
10181 13:59:13.541085
10182 13:59:14.252531 00500000 ################################################################
10183 13:59:14.253178
10184 13:59:14.965417 00580000 ################################################################
10185 13:59:14.966048
10186 13:59:15.691263 00600000 ################################################################
10187 13:59:15.691863
10188 13:59:16.403570 00680000 ################################################################
10189 13:59:16.404228
10190 13:59:17.070113 00700000 ################################################################
10191 13:59:17.070610
10192 13:59:17.763003 00780000 ################################################################
10193 13:59:17.763534
10194 13:59:18.451390 00800000 ################################################################
10195 13:59:18.451837
10196 13:59:19.133729 00880000 ################################################################
10197 13:59:19.134261
10198 13:59:19.835328 00900000 ################################################################
10199 13:59:19.835837
10200 13:59:20.527862 00980000 ################################################################
10201 13:59:20.528370
10202 13:59:21.241771 00a00000 ################################################################
10203 13:59:21.242287
10204 13:59:21.935521 00a80000 ################################################################
10205 13:59:21.936040
10206 13:59:22.624349 00b00000 ################################################################
10207 13:59:22.624899
10208 13:59:23.320076 00b80000 ################################################################
10209 13:59:23.320617
10210 13:59:24.014358 00c00000 ################################################################
10211 13:59:24.014861
10212 13:59:24.638099 00c80000 ################################################################
10213 13:59:24.638611
10214 13:59:25.345887 00d00000 ################################################################
10215 13:59:25.346481
10216 13:59:26.070026 00d80000 ################################################################
10217 13:59:26.070544
10218 13:59:26.788815 00e00000 ################################################################
10219 13:59:26.789332
10220 13:59:27.496164 00e80000 ################################################################
10221 13:59:27.496738
10222 13:59:28.184400 00f00000 ################################################################
10223 13:59:28.184974
10224 13:59:28.867720 00f80000 ################################################################
10225 13:59:28.868224
10226 13:59:29.566334 01000000 ################################################################
10227 13:59:29.566851
10228 13:59:30.274416 01080000 ################################################################
10229 13:59:30.274899
10230 13:59:30.997705 01100000 ################################################################
10231 13:59:30.998218
10232 13:59:31.680059 01180000 ################################################################
10233 13:59:31.680564
10234 13:59:32.398258 01200000 ################################################################
10235 13:59:32.398790
10236 13:59:33.061167 01280000 ################################################################
10237 13:59:33.061716
10238 13:59:33.789080 01300000 ################################################################
10239 13:59:33.789599
10240 13:59:34.518234 01380000 ################################################################
10241 13:59:34.518750
10242 13:59:35.246423 01400000 ################################################################
10243 13:59:35.246969
10244 13:59:35.983753 01480000 ################################################################
10245 13:59:35.984265
10246 13:59:36.711592 01500000 ################################################################
10247 13:59:36.712100
10248 13:59:37.405628 01580000 ################################################################
10249 13:59:37.406169
10250 13:59:38.117385 01600000 ################################################################
10251 13:59:38.117946
10252 13:59:38.830393 01680000 ################################################################
10253 13:59:38.830899
10254 13:59:39.534843 01700000 ################################################################
10255 13:59:39.535420
10256 13:59:40.258427 01780000 ################################################################
10257 13:59:40.258933
10258 13:59:40.957358 01800000 ################################################################
10259 13:59:40.957887
10260 13:59:41.692090 01880000 ################################################################
10261 13:59:41.692611
10262 13:59:42.424147 01900000 ################################################################
10263 13:59:42.424657
10264 13:59:43.152153 01980000 ################################################################
10265 13:59:43.152757
10266 13:59:43.870663 01a00000 ################################################################
10267 13:59:43.871241
10268 13:59:44.562460 01a80000 ################################################################
10269 13:59:44.562971
10270 13:59:45.242573 01b00000 ################################################################
10271 13:59:45.243087
10272 13:59:45.278440 01b80000 #### done.
10273 13:59:45.278874
10274 13:59:45.281830 The bootfile was 28862918 bytes long.
10275 13:59:45.282250
10276 13:59:45.282582 Sending tftp read request... done.
10277 13:59:45.285226
10278 13:59:45.288502 Waiting for the transfer...
10279 13:59:45.288962
10280 13:59:45.289298 00000000 # done.
10281 13:59:45.289618
10282 13:59:45.295518 Command line loaded dynamically from TFTP file: 11372189/tftp-deploy-2hykufja/kernel/cmdline
10283 13:59:45.296065
10284 13:59:45.318339 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11372189/extract-nfsrootfs-khc8asxh,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10285 13:59:45.318863
10286 13:59:45.319206 Loading FIT.
10287 13:59:45.319518
10288 13:59:45.322043 Image ramdisk-1 has 17773769 bytes.
10289 13:59:45.322474
10290 13:59:45.325507 Image fdt-1 has 47278 bytes.
10291 13:59:45.325923
10292 13:59:45.328690 Image kernel-1 has 11039834 bytes.
10293 13:59:45.329108
10294 13:59:45.338667 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10295 13:59:45.339211
10296 13:59:45.355655 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10297 13:59:45.356203
10298 13:59:45.358681 Choosing best match conf-1 for compat google,spherion-rev2.
10299 13:59:45.364313
10300 13:59:45.369068 Connected to device vid:did:rid of 1ae0:0028:00
10301 13:59:45.377323
10302 13:59:45.381328 tpm_get_response: command 0x17b, return code 0x0
10303 13:59:45.381838
10304 13:59:45.387288 ec_init: CrosEC protocol v3 supported (256, 248)
10305 13:59:45.387790
10306 13:59:45.390831 tpm_cleanup: add release locality here.
10307 13:59:45.391344
10308 13:59:45.394138 Shutting down all USB controllers.
10309 13:59:45.394645
10310 13:59:45.397157 Removing current net device
10311 13:59:45.397572
10312 13:59:45.400771 Exiting depthcharge with code 4 at timestamp: 74735518
10313 13:59:45.401281
10314 13:59:45.404368 LZMA decompressing kernel-1 to 0x821a6718
10315 13:59:45.404927
10316 13:59:45.407858 LZMA decompressing kernel-1 to 0x40000000
10317 13:59:46.797669
10318 13:59:46.798215 jumping to kernel
10319 13:59:46.799665 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10320 13:59:46.800210 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10321 13:59:46.800617 Setting prompt string to ['Linux version [0-9]']
10322 13:59:46.801038 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10323 13:59:46.801597 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10324 13:59:46.879142
10325 13:59:46.882160 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10326 13:59:46.886016 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10327 13:59:46.886522 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10328 13:59:46.886914 Setting prompt string to []
10329 13:59:46.887327 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10330 13:59:46.887715 Using line separator: #'\n'#
10331 13:59:46.888049 No login prompt set.
10332 13:59:46.888380 Parsing kernel messages
10333 13:59:46.888723 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10334 13:59:46.889297 [login-action] Waiting for messages, (timeout 00:03:38)
10335 13:59:46.905979 [ 0.000000] Linux version 6.1.46-cip4-rt2 (KernelCI@build-j25372-arm64-gcc-10-defconfig-arm64-chromebook-2wz78) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 28 13:41:26 UTC 2023
10336 13:59:46.908959 [ 0.000000] random: crng init done
10337 13:59:46.915313 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10338 13:59:46.919266 [ 0.000000] efi: UEFI not found.
10339 13:59:46.925721 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10340 13:59:46.932526 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10341 13:59:46.942097 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10342 13:59:46.952206 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10343 13:59:46.958738 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10344 13:59:46.965631 [ 0.000000] printk: bootconsole [mtk8250] enabled
10345 13:59:46.968730 [ 0.000000] NUMA: No NUMA configuration found
10346 13:59:46.979141 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10347 13:59:46.982263 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10348 13:59:46.985617 [ 0.000000] Zone ranges:
10349 13:59:46.992284 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10350 13:59:46.995623 [ 0.000000] DMA32 empty
10351 13:59:47.002061 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10352 13:59:47.005630 [ 0.000000] Movable zone start for each node
10353 13:59:47.008550 [ 0.000000] Early memory node ranges
10354 13:59:47.015528 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10355 13:59:47.022038 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10356 13:59:47.025418 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10357 13:59:47.032313 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10358 13:59:47.039190 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10359 13:59:47.045544 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10360 13:59:47.103582 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10361 13:59:47.110203 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10362 13:59:47.117315 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10363 13:59:47.120277 [ 0.000000] psci: probing for conduit method from DT.
10364 13:59:47.126617 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10365 13:59:47.129807 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10366 13:59:47.136486 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10367 13:59:47.139797 [ 0.000000] psci: SMC Calling Convention v1.2
10368 13:59:47.146685 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10369 13:59:47.150179 [ 0.000000] Detected VIPT I-cache on CPU0
10370 13:59:47.156872 [ 0.000000] CPU features: detected: GIC system register CPU interface
10371 13:59:47.163043 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10372 13:59:47.170145 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10373 13:59:47.177461 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10374 13:59:47.183753 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10375 13:59:47.190452 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10376 13:59:47.196926 [ 0.000000] alternatives: applying boot alternatives
10377 13:59:47.200516 [ 0.000000] Fallback order for Node 0: 0
10378 13:59:47.207234 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10379 13:59:47.210543 [ 0.000000] Policy zone: Normal
10380 13:59:47.233722 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11372189/extract-nfsrootfs-khc8asxh,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10381 13:59:47.243918 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10382 13:59:47.256936 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10383 13:59:47.266245 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10384 13:59:47.273412 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10385 13:59:47.276370 <6>[ 0.000000] software IO TLB: area num 8.
10386 13:59:47.333266 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10387 13:59:47.481704 <6>[ 0.000000] Memory: 7952132K/8385536K available (17984K kernel code, 4100K rwdata, 17468K rodata, 8384K init, 615K bss, 400636K reserved, 32768K cma-reserved)
10388 13:59:47.488395 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10389 13:59:47.495572 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10390 13:59:47.499159 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10391 13:59:47.505266 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10392 13:59:47.512844 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10393 13:59:47.515413 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10394 13:59:47.525620 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10395 13:59:47.532082 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10396 13:59:47.535123 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10397 13:59:47.543134 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10398 13:59:47.545992 <6>[ 0.000000] GICv3: 608 SPIs implemented
10399 13:59:47.553664 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10400 13:59:47.556373 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10401 13:59:47.559482 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10402 13:59:47.569926 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10403 13:59:47.580524 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10404 13:59:47.593052 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10405 13:59:47.600086 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10406 13:59:47.608813 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10407 13:59:47.621672 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10408 13:59:47.629093 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10409 13:59:47.635324 <6>[ 0.009232] Console: colour dummy device 80x25
10410 13:59:47.645692 <6>[ 0.013981] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10411 13:59:47.652095 <6>[ 0.024467] pid_max: default: 32768 minimum: 301
10412 13:59:47.655181 <6>[ 0.029368] LSM: Security Framework initializing
10413 13:59:47.661679 <6>[ 0.034338] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 13:59:47.672007 <6>[ 0.042150] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10415 13:59:47.678426 <6>[ 0.051565] cblist_init_generic: Setting adjustable number of callback queues.
10416 13:59:47.685225 <6>[ 0.059010] cblist_init_generic: Setting shift to 3 and lim to 1.
10417 13:59:47.695161 <6>[ 0.065350] cblist_init_generic: Setting adjustable number of callback queues.
10418 13:59:47.698400 <6>[ 0.072822] cblist_init_generic: Setting shift to 3 and lim to 1.
10419 13:59:47.705272 <6>[ 0.079260] rcu: Hierarchical SRCU implementation.
10420 13:59:47.712039 <6>[ 0.079262] rcu: Max phase no-delay instances is 1000.
10421 13:59:47.718604 <6>[ 0.079286] printk: bootconsole [mtk8250] printing thread started
10422 13:59:47.725216 <6>[ 0.097637] EFI services will not be available.
10423 13:59:47.728840 <6>[ 0.097841] smp: Bringing up secondary CPUs ...
10424 13:59:47.732229 <6>[ 0.098154] Detected VIPT I-cache on CPU1
10425 13:59:47.738681 <6>[ 0.098223] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10426 13:59:47.745130 <6>[ 0.098255] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10427 13:59:47.757033 <6>[ 0.126121] Detected VIPT I-cache on CPU2
10428 13:59:47.763635 <6>[ 0.126173] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10429 13:59:47.770092 <6>[ 0.126191] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10430 13:59:47.776772 <6>[ 0.126452] Detected VIPT I-cache on CPU3
10431 13:59:47.783945 <6>[ 0.126499] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10432 13:59:47.790040 <6>[ 0.126512] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10433 13:59:47.793798 <6>[ 0.126823] CPU features: detected: Spectre-v4
10434 13:59:47.800273 <6>[ 0.126829] CPU features: detected: Spectre-BHB
10435 13:59:47.803698 <6>[ 0.126834] Detected PIPT I-cache on CPU4
10436 13:59:47.810004 <6>[ 0.126896] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10437 13:59:47.816839 <6>[ 0.126912] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10438 13:59:47.823743 <6>[ 0.127205] Detected PIPT I-cache on CPU5
10439 13:59:47.830184 <6>[ 0.127267] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10440 13:59:47.837136 <6>[ 0.127284] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10441 13:59:47.840293 <6>[ 0.127558] Detected PIPT I-cache on CPU6
10442 13:59:47.846638 <6>[ 0.127624] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10443 13:59:47.853584 <6>[ 0.127640] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10444 13:59:47.860228 <6>[ 0.127931] Detected PIPT I-cache on CPU7
10445 13:59:47.866764 <6>[ 0.127998] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10446 13:59:47.873216 <6>[ 0.128015] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10447 13:59:47.876643 <6>[ 0.128062] smp: Brought up 1 node, 8 CPUs
10448 13:59:47.883630 <6>[ 0.128067] SMP: Total of 8 processors activated.
10449 13:59:47.887602 <6>[ 0.128070] CPU features: detected: 32-bit EL0 Support
10450 13:59:47.897288 <6>[ 0.128071] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10451 13:59:47.903589 <6>[ 0.128074] CPU features: detected: Common not Private translations
10452 13:59:47.907243 <6>[ 0.128076] CPU features: detected: CRC32 instructions
10453 13:59:47.913225 <6>[ 0.128078] CPU features: detected: RCpc load-acquire (LDAPR)
10454 13:59:47.920494 <6>[ 0.128080] CPU features: detected: LSE atomic instructions
10455 13:59:47.926859 <6>[ 0.128081] CPU features: detected: Privileged Access Never
10456 13:59:47.930371 <6>[ 0.128083] CPU features: detected: RAS Extension Support
10457 13:59:47.936988 <6>[ 0.128086] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10458 13:59:47.943407 <6>[ 0.128149] CPU: All CPU(s) started at EL2
10459 13:59:47.950180 <6>[ 0.128150] alternatives: applying system-wide alternatives
10460 13:59:47.953552 <6>[ 0.141167] devtmpfs: initialized
10461 13:59:47.963802 <6>[ 0.147408] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10462 13:59:47.970124 <6>[ 0.147423] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10463 13:59:47.997355 � �����Bzɑ����b���ª���ѕͱb����ɥjR�<6>[ 0.372257] p<rintk: console [ttyS0] printing thread started
10464 13:59:48.007928 6>[ 0.233639] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10465 13:59:48.015991 <6>[ 0.372263] printk: console [ttyS0] enabled
10466 13:59:48.019041 <6>[ 0.372266] printk: bootconsole [mtk8250] disabled
10467 13:59:48.025576 <6>[ 0.386897] printk: bootconsole [mtk8250] printing thread stopped
10468 13:59:48.032531 <6>[ 0.387883] SuperH (H)SCI(F) driver initialized
10469 13:59:48.035820 <6>[ 0.388369] msm_serial: driver initialized
10470 13:59:48.045567 <6>[ 0.393052] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10471 13:59:48.052268 <6>[ 0.393082] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10472 13:59:48.064961 <6>[ 0.393112] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10473 13:59:48.075280 <6>[ 0.393141] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10474 13:59:48.083484 <6>[ 0.393163] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10475 13:59:48.099901 <6>[ 0.393190] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10476 13:59:48.100466 <6>[ 0.393218] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10477 13:59:48.109455 <6>[ 0.393336] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10478 13:59:48.119676 <6>[ 0.393366] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10479 13:59:48.120233 <6>[ 0.403115] loop: module loaded
10480 13:59:48.123569 <6>[ 0.405598] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10481 13:59:48.129994 <4>[ 0.422135] mtk-pmic-keys: Failed to locate of_node [id: -1]
10482 13:59:48.133557 <6>[ 0.422920] megasas: 07.719.03.00-rc1
10483 13:59:48.136586 <6>[ 0.433156] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10484 13:59:48.143629 <6>[ 0.437211] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10485 13:59:48.150206 <6>[ 0.449029] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10486 13:59:48.163283 <6>[ 0.502538] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10487 13:59:48.595634 <6>[ 0.966348] Freeing initrd memory: 17356K
10488 13:59:48.602160 <6>[ 0.972298] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10489 13:59:48.605566 <6>[ 0.976980] tun: Universal TUN/TAP device driver, 1.6
10490 13:59:48.608897 <6>[ 0.977776] thunder_xcv, ver 1.0
10491 13:59:48.612262 <6>[ 0.977793] thunder_bgx, ver 1.0
10492 13:59:48.615791 <6>[ 0.977808] nicpf, ver 1.0
10493 13:59:48.622583 <6>[ 0.978902] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10494 13:59:48.628647 <6>[ 0.978905] hns3: Copyright (c) 2017 Huawei Corporation.
10495 13:59:48.632062 <6>[ 0.978929] hclge is initializing
10496 13:59:48.638867 <6>[ 0.978943] e1000: Intel(R) PRO/1000 Network Driver
10497 13:59:48.642612 <6>[ 0.978945] e1000: Copyright (c) 1999-2006 Intel Corporation.
10498 13:59:48.650266 <6>[ 0.978961] e1000e: Intel(R) PRO/1000 Network Driver
10499 13:59:48.653819 <6>[ 0.978963] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10500 13:59:48.660728 <6>[ 0.978981] igb: Intel(R) Gigabit Ethernet Network Driver
10501 13:59:48.667017 <6>[ 0.978983] igb: Copyright (c) 2007-2014 Intel Corporation.
10502 13:59:48.674589 <6>[ 0.978996] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10503 13:59:48.677794 <6>[ 0.978998] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10504 13:59:48.684324 <6>[ 0.979292] sky2: driver version 1.30
10505 13:59:48.688589 <6>[ 0.980417] VFIO - User Level meta-driver version: 0.3
10506 13:59:48.694646 <6>[ 0.983366] usbcore: registered new interface driver usb-storage
10507 13:59:48.701373 <6>[ 0.983548] usbcore: registered new device driver onboard-usb-hub
10508 13:59:48.708154 <6>[ 0.986340] mt6397-rtc mt6359-rtc: registered as rtc0
10509 13:59:48.714766 <6>[ 0.986492] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-28T13:59:51 UTC (1693231191)
10510 13:59:48.721535 <6>[ 0.987134] i2c_dev: i2c /dev entries driver
10511 13:59:48.728252 <6>[ 0.994420] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10512 13:59:48.731751 <6>[ 1.009412] cpu cpu0: EM: created perf domain
10513 13:59:48.738238 <6>[ 1.009653] cpu cpu4: EM: created perf domain
10514 13:59:48.744860 <6>[ 1.012609] sdhci: Secure Digital Host Controller Interface driver
10515 13:59:48.748496 <6>[ 1.012610] sdhci: Copyright(c) Pierre Ossman
10516 13:59:48.754778 <6>[ 1.012988] Synopsys Designware Multimedia Card Interface Driver
10517 13:59:48.761836 <6>[ 1.013379] sdhci-pltfm: SDHCI platform and OF driver helper
10518 13:59:48.768206 <6>[ 1.017276] ledtrig-cpu: registered to indicate activity on CPUs
10519 13:59:48.771466 <6>[ 1.017926] mmc0: CQHCI version 5.10
10520 13:59:48.778664 <6>[ 1.018103] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10521 13:59:48.781503 <6>[ 1.018394] usbcore: registered new interface driver usbhid
10522 13:59:48.788441 <6>[ 1.018395] usbhid: USB HID core driver
10523 13:59:48.795213 <6>[ 1.018532] spi_master spi0: will run message pump with realtime priority
10524 13:59:48.808550 <6>[ 1.046260] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10525 13:59:48.821667 <6>[ 1.049037] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10526 13:59:48.824943 <6>[ 1.050089] cros-ec-spi spi0.0: Chrome EC device registered
10527 13:59:48.835182 <6>[ 1.062094] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10528 13:59:48.841626 <6>[ 1.063050] NET: Registered PF_PACKET protocol family
10529 13:59:48.845044 <6>[ 1.063115] 9pnet: Installing 9P2000 support
10530 13:59:48.848625 <5>[ 1.063152] Key type dns_resolver registered
10531 13:59:48.855037 <6>[ 1.063531] registered taskstats version 1
10532 13:59:48.858607 <5>[ 1.063546] Loading compiled-in X.509 certificates
10533 13:59:48.868315 <4>[ 1.079348] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10534 13:59:48.881576 <4>[ 1.079606] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10535 13:59:48.888527 <3>[ 1.079624] debugfs: File 'uA_load' in directory '/' already present!
10536 13:59:48.894804 <3>[ 1.079641] debugfs: File 'min_uV' in directory '/' already present!
10537 13:59:48.898643 <3>[ 1.079648] debugfs: File 'max_uV' in directory '/' already present!
10538 13:59:48.908837 <3>[ 1.079653] debugfs: File 'constraint_flags' in directory '/' already present!
10539 13:59:48.915098 <3>[ 1.082549] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10540 13:59:48.922377 <6>[ 1.090448] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10541 13:59:48.928285 <6>[ 1.091076] xhci-mtk 11200000.usb: xHCI Host Controller
10542 13:59:48.935455 <6>[ 1.091090] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10543 13:59:48.945636 <6>[ 1.091312] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10544 13:59:48.952110 <6>[ 1.091375] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10545 13:59:48.955380 <6>[ 1.091463] xhci-mtk 11200000.usb: xHCI Host Controller
10546 13:59:48.965311 <6>[ 1.091471] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10547 13:59:48.972020 <6>[ 1.091480] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10548 13:59:48.974961 <6>[ 1.092102] hub 1-0:1.0: USB hub found
10549 13:59:48.978242 <6>[ 1.092122] hub 1-0:1.0: 1 port detected
10550 13:59:48.988381 <6>[ 1.092440] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10551 13:59:48.991952 <6>[ 1.093266] hub 2-0:1.0: USB hub found
10552 13:59:48.995118 <6>[ 1.093347] hub 2-0:1.0: 1 port detected
10553 13:59:49.001933 <6>[ 1.096282] mtk-msdc 11f70000.mmc: Got CD GPIO
10554 13:59:49.008737 <6>[ 1.102407] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10555 13:59:49.015107 <6>[ 1.102415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10556 13:59:49.025202 <4>[ 1.102495] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10557 13:59:49.032630 <6>[ 1.102988] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10558 13:59:49.042397 <6>[ 1.102990] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10559 13:59:49.049185 <6>[ 1.103268] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10560 13:59:49.055948 <6>[ 1.103283] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10561 13:59:49.065348 <6>[ 1.103287] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10562 13:59:49.075847 <6>[ 1.103294] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10563 13:59:49.081998 <6>[ 1.105089] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10564 13:59:49.092769 <6>[ 1.105106] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10565 13:59:49.098858 <6>[ 1.105112] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10566 13:59:49.108944 <6>[ 1.105118] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10567 13:59:49.115282 <6>[ 1.105124] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10568 13:59:49.125452 <6>[ 1.105130] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10569 13:59:49.132274 <6>[ 1.105136] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10570 13:59:49.142707 <6>[ 1.105141] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10571 13:59:49.148502 <6>[ 1.105147] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10572 13:59:49.158840 <6>[ 1.105153] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10573 13:59:49.165693 <6>[ 1.105159] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10574 13:59:49.175065 <6>[ 1.105164] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10575 13:59:49.181659 <6>[ 1.105171] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10576 13:59:49.191550 <6>[ 1.105176] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10577 13:59:49.198134 <6>[ 1.105182] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10578 13:59:49.205143 <6>[ 1.105709] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10579 13:59:49.211626 <6>[ 1.106640] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10580 13:59:49.217729 <6>[ 1.107190] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10581 13:59:49.224794 <6>[ 1.107816] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10582 13:59:49.231589 <6>[ 1.108452] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10583 13:59:49.241252 <6>[ 1.108656] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10584 13:59:49.250843 <6>[ 1.108669] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10585 13:59:49.260821 <6>[ 1.108676] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10586 13:59:49.267867 <6>[ 1.108683] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10587 13:59:49.277489 <6>[ 1.108690] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10588 13:59:49.288122 <6>[ 1.108696] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10589 13:59:49.298059 <6>[ 1.108703] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10590 13:59:49.307796 <6>[ 1.108710] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10591 13:59:49.314273 <6>[ 1.108716] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10592 13:59:49.324218 <6>[ 1.108723] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10593 13:59:49.334555 <6>[ 1.108728] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10594 13:59:49.344537 <6>[ 1.109222] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10595 13:59:49.347824 <6>[ 1.116769] mmc0: Command Queue Engine enabled
10596 13:59:49.354404 <6>[ 1.116780] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10597 13:59:49.361223 <6>[ 1.117231] mmcblk0: mmc0:0001 DA4128 116 GiB
10598 13:59:49.364806 <6>[ 1.120466] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10599 13:59:49.371040 <6>[ 1.121354] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10600 13:59:49.377526 <6>[ 1.122000] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10601 13:59:49.384509 <6>[ 1.122532] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10602 13:59:49.388241 <6>[ 1.130205] Trying to probe devices needed for running init ...
10603 13:59:49.397542 <6>[ 1.513869] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10604 13:59:49.401304 <6>[ 1.666071] hub 1-1:1.0: USB hub found
10605 13:59:49.404161 <6>[ 1.666431] hub 1-1:1.0: 4 ports detected
10606 13:59:49.422594 <6>[ 1.790097] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10607 13:59:49.443969 <6>[ 1.816351] hub 2-1:1.0: USB hub found
10608 13:59:49.446984 <6>[ 1.816848] hub 2-1:1.0: 3 ports detected
10609 13:59:49.614994 <6>[ 1.982096] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10610 13:59:49.735737 <6>[ 2.108836] hub 1-1.4:1.0: USB hub found
10611 13:59:49.738960 <6>[ 2.109147] hub 1-1.4:1.0: 2 ports detected
10612 13:59:49.818749 <6>[ 2.186182] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10613 13:59:50.031183 <6>[ 2.398068] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10614 13:59:50.215071 <6>[ 2.582075] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10615 14:00:01.034470 <6>[ 13.411034] ALSA device list:
10616 14:00:01.041238 <6>[ 13.411056] No soundcards found.
10617 14:00:01.044075 <6>[ 13.415464] Freeing unused kernel memory: 8384K
10618 14:00:01.050853 Loading, please <6>[ 13.415553] Run /init as init process
10619 14:00:01.050978 wait...
10620 14:00:01.065231 Starting version 247.3-7+deb11u2
10621 14:00:01.296831 <6>[ 13.667646] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10622 14:00:01.300211 <6>[ 13.672682] remoteproc remoteproc0: scp is available
10623 14:00:01.306877 <6>[ 13.672901] remoteproc remoteproc0: powering up scp
10624 14:00:01.313500 <6>[ 13.672918] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10625 14:00:01.320198 <6>[ 13.672976] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10626 14:00:01.352642 <3>[ 13.724443] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 14:00:01.359303 <3>[ 13.724468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10628 14:00:01.369707 <3>[ 13.724473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10629 14:00:01.380942 <3>[ 13.750445] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 14:00:01.387670 <3>[ 13.750480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10631 14:00:01.397656 <3>[ 13.750487] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10632 14:00:01.404350 <3>[ 13.750496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10633 14:00:01.413971 <3>[ 13.750500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10634 14:00:01.420597 <3>[ 13.773059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10635 14:00:01.428814 <6>[ 13.795212] mc: Linux media interface: v0.10
10636 14:00:01.434109 <6>[ 13.796820] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10637 14:00:01.440617 <6>[ 13.796833] remoteproc remoteproc0: remote processor scp is now up
10638 14:00:01.447230 <6>[ 13.796840] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10639 14:00:01.453966 <6>[ 13.798483] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10640 14:00:01.464575 <4>[ 13.799569] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10641 14:00:01.471197 <3>[ 13.799622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10642 14:00:01.477765 <3>[ 13.799641] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10643 14:00:01.487683 <3>[ 13.799652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10644 14:00:01.495144 <3>[ 13.806938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10645 14:00:01.502319 <3>[ 13.807002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10646 14:00:01.511803 <3>[ 13.807007] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10647 14:00:01.518385 <3>[ 13.807018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10648 14:00:01.528843 <3>[ 13.807030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10649 14:00:01.534795 <4>[ 13.807073] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10650 14:00:01.541477 <6>[ 13.807799] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10651 14:00:01.551613 <6>[ 13.807857] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10652 14:00:01.558114 <6>[ 13.807867] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10653 14:00:01.568655 <3>[ 13.808916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10654 14:00:01.575002 <6>[ 13.813007] videodev: Linux video capture interface: v2.00
10655 14:00:01.581272 <4>[ 13.824915] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10656 14:00:01.587836 <4>[ 13.824915] Fallback method does not support PEC.
10657 14:00:01.594720 <3>[ 13.850545] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10658 14:00:01.601272 <6>[ 13.855762] usbcore: registered new interface driver r8152
10659 14:00:01.611335 <6>[ 13.870296] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10660 14:00:01.618097 <6>[ 13.873965] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10661 14:00:01.627832 <3>[ 13.876893] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10662 14:00:01.635523 <6>[ 13.914018] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10663 14:00:01.644594 <6>[ 13.931217] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10664 14:00:01.647638 <6>[ 13.931224] pci_bus 0000:00: root bus resource [bus 00-ff]
10665 14:00:01.654949 <6>[ 13.931228] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10666 14:00:01.664492 <6>[ 13.931231] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10667 14:00:01.671427 <6>[ 13.931258] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10668 14:00:01.680986 <6>[ 13.931271] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10669 14:00:01.684404 <6>[ 13.931346] pci 0000:00:00.0: supports D1 D2
10670 14:00:01.690795 <6>[ 13.931348] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10671 14:00:01.700918 <6>[ 13.932282] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10672 14:00:01.704577 <6>[ 13.932356] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10673 14:00:01.714122 <6>[ 13.932380] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10674 14:00:01.721341 <6>[ 13.932396] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10675 14:00:01.727507 <6>[ 13.932410] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10676 14:00:01.730801 <6>[ 13.932514] pci 0000:01:00.0: supports D1 D2
10677 14:00:01.740543 <6>[ 13.932515] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10678 14:00:01.747209 <6>[ 13.934312] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10679 14:00:01.757641 <6>[ 13.938841] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10680 14:00:01.763805 <6>[ 13.939294] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10681 14:00:01.773742 <6>[ 13.942593] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10682 14:00:01.780848 <6>[ 13.942639] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10683 14:00:01.787577 <6>[ 13.942643] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10684 14:00:01.797319 <6>[ 13.942654] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10685 14:00:01.804010 <6>[ 13.942668] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10686 14:00:01.814069 <6>[ 13.942681] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10687 14:00:01.817482 <6>[ 13.942694] pci 0000:00:00.0: PCI bridge to [bus 01]
10688 14:00:01.827212 <6>[ 13.942701] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10689 14:00:01.830388 <6>[ 13.944776] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10690 14:00:01.837130 <6>[ 13.947837] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10691 14:00:01.843856 <6>[ 13.948226] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10692 14:00:01.850589 <5>[ 13.973379] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10693 14:00:01.860293 <4>[ 13.974883] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10694 14:00:01.870579 <4>[ 13.974902] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10695 14:00:01.873911 <6>[ 13.979410] usbcore: registered new interface driver cdc_ether
10696 14:00:01.880374 <6>[ 13.984197] Bluetooth: Core ver 2.22
10697 14:00:01.883761 <6>[ 13.984320] NET: Registered PF_BLUETOOTH protocol family
10698 14:00:01.890826 <6>[ 13.984324] Bluetooth: HCI device and connection manager initialized
10699 14:00:01.897341 <6>[ 13.984349] Bluetooth: HCI socket layer initialized
10700 14:00:01.900945 <6>[ 13.984361] Bluetooth: L2CAP socket layer initialized
10701 14:00:01.907282 <6>[ 13.984376] Bluetooth: SCO socket layer initialized
10702 14:00:01.913799 <6>[ 13.989544] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10703 14:00:01.916993 <6>[ 13.989907] r8152 2-1.3:1.0 eth0: v1.12.13
10704 14:00:01.923709 <5>[ 13.990048] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10705 14:00:01.933614 <4>[ 13.990110] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10706 14:00:01.936948 <6>[ 13.990117] cfg80211: failed to load regulatory.db
10707 14:00:01.950643 <6>[ 13.991015] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10708 14:00:01.957272 <6>[ 13.991115] usbcore: registered new interface driver uvcvideo
10709 14:00:01.963519 <6>[ 13.992018] usbcore: registered new interface driver r8153_ecm
10710 14:00:01.970217 <6>[ 13.999787] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10711 14:00:01.977922 <6>[ 14.031288] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10712 14:00:01.980169 <6>[ 14.061570] usbcore: registered new interface driver btusb
10713 14:00:01.993635 <4>[ 14.062444] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10714 14:00:01.996983 <3>[ 14.062458] Bluetooth: hci0: Failed to load firmware file (-2)
10715 14:00:02.003657 <3>[ 14.062461] Bluetooth: hci0: Failed to set up firmware (-2)
10716 14:00:02.013355 <4>[ 14.062464] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10717 14:00:02.028769 <6>[ 14.400115] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10718 14:00:02.035337 <6>[ 14.400221] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10719 14:00:02.045883 <6>[ 14.418048] mt7921e 0000:01:00.0: ASIC revision: 79610010
10720 14:00:02.144114 <4>[ 14.513729] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10721 14:00:02.147243 Begin: Loading essential drivers ... done.
10722 14:00:02.154173 Begin: Running /scripts/init-premount ... done.
10723 14:00:02.160910 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10724 14:00:02.170793 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10725 14:00:02.173934 Device /sys/class/net/enx002432307852 found
10726 14:00:02.174026 done.
10727 14:00:02.244993 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10728 14:00:02.264097 <4>[ 14.632905] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10729 14:00:02.372268 <4>[ 14.739053] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10730 14:00:02.476384 <4>[ 14.842872] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10731 14:00:02.580296 <4>[ 14.946810] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10732 14:00:02.684728 <4>[ 15.050707] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10733 14:00:02.788027 <4>[ 15.154680] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10734 14:00:02.892021 <4>[ 15.258624] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10735 14:00:02.996243 <4>[ 15.362604] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10736 14:00:03.099989 <4>[ 15.466570] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10737 14:00:03.193114 <3>[ 15.568537] mt7921e 0000:01:00.0: hardware init failed
10738 14:00:03.297270 <6>[ 15.670519] r8152 2-1.3:1.0 enx002432307852: carrier on
10739 14:00:04.109908 IP-Config: no response after 2 secs - giving up
10740 14:00:04.157872 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10741 14:00:04.164308 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10742 14:00:04.170834 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10743 14:00:04.177727 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10744 14:00:04.184222 host : mt8192-asurada-spherion-r0-cbg-3
10745 14:00:04.191048 domain : lava-rack
10746 14:00:04.194539 rootserver: 192.168.201.1 rootpath:
10747 14:00:04.197378 filename :
10748 14:00:04.250698 done.
10749 14:00:04.257969 Begin: Running /scripts/nfs-bottom ... done.
10750 14:00:04.276103 Begin: Running /scripts/init-bottom ... done.
10751 14:00:05.509655 <6>[ 17.883658] NET: Registered PF_INET6 protocol family
10752 14:00:05.512406 <6>[ 17.885577] Segment Routing with IPv6
10753 14:00:05.518620 <6>[ 17.885601] In-situ OAM (IOAM) with IPv6
10754 14:00:05.648717 <30>[ 18.003265] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10755 14:00:05.651999 <30>[ 18.004267] systemd[1]: Detected architecture arm64.
10756 14:00:05.666491
10757 14:00:05.669672 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10758 14:00:05.669766
10759 14:00:05.692968 <30>[ 18.068753] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10760 14:00:06.604117 <30>[ 18.975219] systemd[1]: Queued start job for default target Graphical Interface.
10761 14:00:06.651152 [[0;32m OK [<30>[ 19.024371] systemd[1]: Created slice system-getty.slice.
10762 14:00:06.654523 0m] Created slice [0;1;39msystem-getty.slice[0m.
10763 14:00:06.674126 [[0;32m OK [0m] Created slic<30>[ 19.047402] systemd[1]: Created slice system-modprobe.slice.
10764 14:00:06.677144 e [0;1;39msystem-modprobe.slice[0m.
10765 14:00:06.697977 [[0;32m OK [0m] Created slic<30>[ 19.071262] systemd[1]: Created slice system-serial\x2dgetty.slice.
10766 14:00:06.704464 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10767 14:00:06.722200 [[0;32m OK [0m] Created slic<30>[ 19.095825] systemd[1]: Created slice User and Session Slice.
10768 14:00:06.725513 e [0;1;39mUser and Session Slice[0m.
10769 14:00:06.749086 [[0;32m OK [0m] Started [0;<30>[ 19.118887] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10770 14:00:06.752394 1;39mDispatch Password …ts to Console Directory Watch[0m.
10771 14:00:06.776766 [[0;32m OK [0m] Started [0;<30>[ 19.146866] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10772 14:00:06.780428 1;39mForward Password R…uests to Wall Directory Watch[0m.
10773 14:00:06.808032 [[0;32m OK [0m] Reached targ<30>[ 19.174588] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10774 14:00:06.814981 et [0;1;39mLoca<30>[ 19.174847] systemd[1]: Reached target Local Encrypted Volumes.
10775 14:00:06.818303 l Encrypted Volumes[0m.
10776 14:00:06.837168 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.210574] systemd[1]: Reached target Paths.
10777 14:00:06.837313 s[0m.
10778 14:00:06.859951 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.230072] systemd[1]: Reached target Remote File Systems.
10779 14:00:06.860098 te File Systems[0m.
10780 14:00:06.881165 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.254408] systemd[1]: Reached target Slices.
10781 14:00:06.881314 es[0m.
10782 14:00:06.900525 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.274088] systemd[1]: Reached target Swap.
10783 14:00:06.900680 [0m.
10784 14:00:06.924405 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.294557] systemd[1]: Listening on initctl Compatibility Named Pipe.
10785 14:00:06.927590 l Compatibility Named Pipe[0m.
10786 14:00:06.937536 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.310795] systemd[1]: Listening on Journal Audit Socket.
10787 14:00:06.940922 l Audit Socket[0m.
10788 14:00:06.962213 [[0;32m OK [0m] Listening on<30>[ 19.335532] systemd[1]: Listening on Journal Socket (/dev/log).
10789 14:00:06.965363 [0;1;39mJournal Socket (/dev/log)[0m.
10790 14:00:06.986236 [[0;32m OK [0m] Listening on<30>[ 19.359373] systemd[1]: Listening on Journal Socket.
10791 14:00:06.989117 [0;1;39mJournal Socket[0m.
10792 14:00:07.006310 [[0;32m OK [0m] Listening on<30>[ 19.379945] systemd[1]: Listening on Network Service Netlink Socket.
10793 14:00:07.013125 [0;1;39mNetwork Service Netlink Socket[0m.
10794 14:00:07.032474 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 19.406180] systemd[1]: Listening on udev Control Socket.
10795 14:00:07.035815 ontrol Socket[0m.
10796 14:00:07.057162 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 19.430594] systemd[1]: Listening on udev Kernel Socket.
10797 14:00:07.060092 ernel Socket[0m.
10798 14:00:07.116633 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.486550] systemd[1]: Mounting Huge Pages File System...
10799 14:00:07.116809 m[0m...
10800 14:00:07.134948 Mountin<30>[ 19.508411] systemd[1]: Mounting POSIX Message Queue File System...
10801 14:00:07.138084 g [0;1;39mPOSIX Message Queue File System[0m...
10802 14:00:07.160560 Mountin<30>[ 19.533240] systemd[1]: Mounting Kernel Debug File System...
10803 14:00:07.162993 g [0;1;39mKernel Debug File System[0m...
10804 14:00:07.184277 <30>[ 19.554674] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10805 14:00:07.225325 Starting [0;1;39mCreat<30>[ 19.594924] systemd[1]: Starting Create list of static device nodes for the current kernel...
10806 14:00:07.228172 e list of st…odes for the current kernel[0m...
10807 14:00:07.254288 Starting [0;1;39mLoad <30>[ 19.627110] systemd[1]: Starting Load Kernel Module configfs...
10808 14:00:07.256991 Kernel Module configfs[0m...
10809 14:00:07.282292 Starting [0;1;39mLoad <30>[ 19.655228] systemd[1]: Starting Load Kernel Module drm...
10810 14:00:07.285309 Kernel Module drm[0m...
10811 14:00:07.306018 Starting [0;1;39mLoad <30>[ 19.679238] systemd[1]: Starting Load Kernel Module fuse...
10812 14:00:07.309234 Kernel Module fuse[0m...
10813 14:00:07.332033 <30>[ 19.704150] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10814 14:00:07.346109 Starting [0;1;39mJourn<30>[ 19.719669] systemd[1]: Starting Journal Service...
10815 14:00:07.346255 al Service[0m...
10816 14:00:07.360850 <6>[ 19.735693] fuse: init (API version 7.37)
10817 14:00:07.371751 Startin<30>[ 19.745190] systemd[1]: Starting Load Kernel Modules...
10818 14:00:07.374977 g [0;1;39mLoad Kernel Modules[0m...
10819 14:00:07.397887 Starting [0;1;39mRemou<30>[ 19.771347] systemd[1]: Starting Remount Root and Kernel File Systems...
10820 14:00:07.401503 nt Root and Kernel File Systems[0m...
10821 14:00:07.426206 Starting [0;1;39mColdp<30>[ 19.799432] systemd[1]: Starting Coldplug All udev Devices...
10822 14:00:07.429474 lug All udev Devices[0m...
10823 14:00:07.454007 [[0;32m OK [0m] Mounted [0;<30>[ 19.827602] systemd[1]: Mounted Huge Pages File System.
10824 14:00:07.458255 1;39mHuge Pages File System[0m.
10825 14:00:07.477757 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Messa<30>[ 19.850550] systemd[1]: Mounted POSIX Message Queue File System.
10826 14:00:07.487888 ge Queue File Sy<3>[ 19.859914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10827 14:00:07.490988 stem[0m.
10828 14:00:07.512445 <3>[ 19.883322] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10829 14:00:07.522244 [[0;32m OK [0m] Mounted [0;<30>[ 19.895707] systemd[1]: Mounted Kernel Debug File System.
10830 14:00:07.525298 1;39mKernel Debug File System[0m.
10831 14:00:07.549638 [[0;32m OK [0m] Finished [0<30>[ 19.919378] systemd[1]: Finished Create list of static device nodes for the current kernel.
10832 14:00:07.559838 ;1;39mCreate lis<3>[ 19.925689] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10833 14:00:07.563140 t of st… nodes for the current kernel[0m.
10834 14:00:07.576030 <3>[ 19.947455] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 14:00:07.588622 [[0;32m OK [<30>[ 19.960194] systemd[1]: modprobe@configfs.service: Succeeded.
10836 14:00:07.595056 0m] Finished [0<30>[ 19.961289] systemd[1]: Finished Load Kernel Module configfs.
10837 14:00:07.598549 ;1;39mLoad Kernel Module configfs[0m.
10838 14:00:07.608470 <3>[ 19.977966] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10839 14:00:07.621766 [[0;32m OK [0m] Finished [0<30>[ 19.994704] systemd[1]: modprobe@drm.service: Succeeded.
10840 14:00:07.628412 ;1;39mLoad Kerne<30>[ 19.995311] systemd[1]: Finished Load Kernel Module drm.
10841 14:00:07.638164 <3>[ 19.998018] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10842 14:00:07.638303 l Module drm[0m.
10843 14:00:07.660635 <3>[ 20.033793] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10844 14:00:07.667519 <30>[ 20.035344] systemd[1]: modprobe@fuse.service: Succeeded.
10845 14:00:07.674616 [[0;32m OK [0m] Finished [0<30>[ 20.036504] systemd[1]: Finished Load Kernel Module fuse.
10846 14:00:07.684601 ;1;39mLoad Kerne<3>[ 20.055347] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10847 14:00:07.688124 l Module fuse[0m.
10848 14:00:07.704426 <3>[ 20.075837] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10849 14:00:07.710949 <30>[ 20.079310] systemd[1]: Finished Load Kernel Modules.
10850 14:00:07.714921 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10851 14:00:07.724629 <3>[ 20.097363] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10852 14:00:07.739086 [[0;32m OK [0m] Finished [0<30>[ 20.112361] systemd[1]: Finished Remount Root and Kernel File Systems.
10853 14:00:07.745999 ;1;39mRemount Root and Kernel File Systems[0m.
10854 14:00:07.805706 [[0;32m OK [0m] Started [0;<30>[ 20.179072] systemd[1]: Started Journal Service.
10855 14:00:07.809182 1;39mJournal Service[0m.
10856 14:00:07.832924 Mounting [0;1;39mFUSE Control File System[0m...
10857 14:00:07.854659 Mounting [0;1;39mKernel Configuration File System[0m...
10858 14:00:07.881506 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10859 14:00:07.903616 Starting [0;1;39mLoad/Save Random Seed[0m...
10860 14:00:07.926967 Starting [0;1;39mApply Kernel Variables[0m...
10861 14:00:07.940390 <46>[ 20.312593] systemd-journald[307]: Received client request to flush runtime journal.
10862 14:00:07.953420 Starting [0;1;39mCreate System Users[0m...
10863 14:00:07.974027 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10864 14:00:08.003266 <4>[ 20.369358] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10865 14:00:08.012550 <3>[ 20.369374] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10866 14:00:08.019113 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10867 14:00:08.036685 See 'systemctl status systemd-udev-trigger.service' for details.
10868 14:00:08.054185 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10869 14:00:08.070474 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10870 14:00:08.090373 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10871 14:00:09.356632 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10872 14:00:09.389433 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10873 14:00:09.441780 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10874 14:00:09.562768 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10875 14:00:09.581198 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10876 14:00:09.600678 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10877 14:00:09.653459 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10878 14:00:09.681202 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10879 14:00:09.833290 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10880 14:00:09.898292 Starting [0;1;39mNetwork Service[0m...
10881 14:00:10.005673 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10882 14:00:10.113187 Starting [0;1;39mNetwork Time Synchronization[0m...
10883 14:00:10.157739 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10884 14:00:10.279917 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10885 14:00:10.553880 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10886 14:00:10.569091 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10887 14:00:10.588603 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10888 14:00:10.628999 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10889 14:00:10.655938 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10890 14:00:10.709571 Starting [0;1;39mNetwork Name Resolution[0m...
10891 14:00:10.730621 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10892 14:00:10.750141 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10893 14:00:10.765540 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10894 14:00:10.781591 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10895 14:00:10.801672 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10896 14:00:10.821887 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10897 14:00:10.840299 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10898 14:00:10.852959 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10899 14:00:10.869016 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10900 14:00:10.912088 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10901 14:00:10.957091 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10902 14:00:10.981490 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10903 14:00:11.013709 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10904 14:00:11.020814 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10905 14:00:11.230070 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10906 14:00:11.240969 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10907 14:00:11.256837 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10908 14:00:11.306062 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10909 14:00:11.861367 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10910 14:00:12.258316 Starting [0;1;39mUser Login Management[0m...
10911 14:00:12.394121 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10912 14:00:12.409143 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10913 14:00:12.431770 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10914 14:00:12.465411 Starting [0;1;39mPermit User Sessions[0m...
10915 14:00:12.525837 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10916 14:00:12.569575 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10917 14:00:12.620990 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10918 14:00:12.639793 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10919 14:00:12.660640 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10920 14:00:12.682742 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10921 14:00:12.706613 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10922 14:00:12.725774 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10923 14:00:12.787128 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10924 14:00:12.836146 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10925 14:00:12.890576
10926 14:00:12.890727
10927 14:00:12.893702 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10928 14:00:12.893785
10929 14:00:12.897102 debian-bullseye-arm64 login: root (automatic login)
10930 14:00:12.897185
10931 14:00:12.897250
10932 14:00:13.225481 Linux debian-bullseye-arm64 6.1.46-cip4-rt2 #1 SMP PREEMPT Mon Aug 28 13:41:26 UTC 2023 aarch64
10933 14:00:13.225648
10934 14:00:13.231838 The programs included with the Debian GNU/Linux system are free software;
10935 14:00:13.239085 the exact distribution terms for each program are described in the
10936 14:00:13.241946 individual files in /usr/share/doc/*/copyright.
10937 14:00:13.242045
10938 14:00:13.248478 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10939 14:00:13.251933 permitted by applicable law.
10940 14:00:13.362891 Matched prompt #10: / #
10942 14:00:13.363172 Setting prompt string to ['/ #']
10943 14:00:13.363266 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10945 14:00:13.363458 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10946 14:00:13.363545 start: 2.2.6 expect-shell-connection (timeout 00:03:12) [common]
10947 14:00:13.363612 Setting prompt string to ['/ #']
10948 14:00:13.363670 Forcing a shell prompt, looking for ['/ #']
10950 14:00:13.413890 / #
10951 14:00:13.414061 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10952 14:00:13.414144 Waiting using forced prompt support (timeout 00:02:30)
10953 14:00:13.419065
10954 14:00:13.419346 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10955 14:00:13.419439 start: 2.2.7 export-device-env (timeout 00:03:12) [common]
10957 14:00:13.519832 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11372189/extract-nfsrootfs-khc8asxh'
10958 14:00:13.525074 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11372189/extract-nfsrootfs-khc8asxh'
10960 14:00:13.625653 / # export NFS_SERVER_IP='192.168.201.1'
10961 14:00:13.631042 export NFS_SERVER_IP='192.168.201.1'
10962 14:00:13.631352 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10963 14:00:13.631451 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
10964 14:00:13.631538 end: 2 depthcharge-action (duration 00:01:48) [common]
10965 14:00:13.631628 start: 3 lava-test-retry (timeout 00:01:00) [common]
10966 14:00:13.631715 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10967 14:00:13.631787 Using namespace: common
10969 14:00:13.732154 / # #
10970 14:00:13.732345 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10971 14:00:13.738109 #
10972 14:00:13.738373 Using /lava-11372189
10974 14:00:13.838733 / # export SHELL=/bin/sh
10975 14:00:13.844298 export SHELL=/bin/sh
10977 14:00:13.944809 / # . /lava-11372189/environment
10978 14:00:13.950222 . /lava-11372189/environment
10980 14:00:14.056853 / # /lava-11372189/bin/lava-test-runner /lava-11372189/0
10981 14:00:14.057028 Test shell timeout: 10s (minimum of the action and connection timeout)
10982 14:00:14.062635 /lava-11372189/bin/lava-test-runner /lava-11372189/0
10983 14:00:14.338795 + export TESTRUN_ID=0_dmesg
10984 14:00:14.342031 + cd /lava-11372189/0/tests/0_dmesg
10985 14:00:14.345291 + cat uuid
10986 14:00:14.362496 + UUID=11372189_<8>[ 26.737121] <LAVA_SIGNAL_STARTRUN 0_dmesg 11372189_1.6.2.3.1>
10987 14:00:14.362592 1.6.2.3.1
10988 14:00:14.362661 + set +x
10989 14:00:14.362901 Received signal: <STARTRUN> 0_dmesg 11372189_1.6.2.3.1
10990 14:00:14.362971 Starting test lava.0_dmesg (11372189_1.6.2.3.1)
10991 14:00:14.363052 Skipping test definition patterns.
10992 14:00:14.369210 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10993 14:00:14.471555 <8>[ 26.843308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10994 14:00:14.471878 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10996 14:00:14.551994 <8>[ 26.922840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10997 14:00:14.552317 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10999 14:00:14.630548 + set +x
11000 14:00:14.640396 <8>[ 27.010719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11001 14:00:14.640699 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11003 14:00:14.647025 <LAVA_TEST_RUNNE<8>[ 27.011769] <LAVA_SIGNAL_ENDRUN 0_dmesg 11372189_1.6.2.3.1>
11004 14:00:14.647214 R EXIT>
11005 14:00:14.647505 Received signal: <ENDRUN> 0_dmesg 11372189_1.6.2.3.1
11006 14:00:14.647627 Ending use of test pattern.
11007 14:00:14.647720 Ending test lava.0_dmesg (11372189_1.6.2.3.1), duration 0.28
11009 14:00:31.654925 / # <6>[ 44.034217] vpu: disabling
11010 14:00:31.657839 <6>[ 44.034345] vproc2: disabling
11011 14:00:31.661290 <6>[ 44.034400] vproc1: disabling
11012 14:00:31.664377 <6>[ 44.034455] vaud18: disabling
11013 14:00:31.667673 <6>[ 44.034707] vsram_others: disabling
11014 14:00:31.671532 <6>[ 44.034891] va09: disabling
11015 14:00:31.674567 <6>[ 44.034969] vsram_md: disabling
11016 14:00:31.678111 <6>[ 44.035101] Vgpu: disabling
11018 14:01:13.632793 end: 3.1 lava-test-shell (duration 00:01:00) [common]
11020 14:01:13.633832 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
11022 14:01:13.634612 end: 3 lava-test-retry (duration 00:01:00) [common]
11024 14:01:13.635758 Cleaning after the job
11025 14:01:13.636246 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/ramdisk
11026 14:01:13.649557 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/kernel
11027 14:01:13.684871 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/dtb
11028 14:01:13.685145 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/nfsrootfs
11029 14:01:13.763355 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372189/tftp-deploy-2hykufja/modules
11030 14:01:13.770888 start: 5.1 power-off (timeout 00:00:30) [common]
11031 14:01:13.771068 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11032 14:01:13.848192 >> Command sent successfully.
11033 14:01:13.853581 Returned 0 in 0 seconds
11034 14:01:13.954533 end: 5.1 power-off (duration 00:00:00) [common]
11036 14:01:13.956411 start: 5.2 read-feedback (timeout 00:10:00) [common]
11037 14:01:13.957868 Listened to connection for namespace 'common' for up to 1s
11038 14:01:14.958375 Finalising connection for namespace 'common'
11039 14:01:14.959109 Disconnecting from shell: Finalise
11040 14:01:15.060267 end: 5.2 read-feedback (duration 00:00:01) [common]
11041 14:01:15.060931 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11372189
11042 14:01:15.462647 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11372189
11043 14:01:15.462835 TestError: A test failed to run, look at the error message.