Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 19
1 13:57:31.455898 lava-dispatcher, installed at version: 2023.06
2 13:57:31.456125 start: 0 validate
3 13:57:31.456259 Start time: 2023-08-28 13:57:31.456251+00:00 (UTC)
4 13:57:31.456390 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:57:31.456543 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:57:31.730217 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:57:31.731001 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:57:48.753254 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:57:48.753995 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:57:49.022200 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:57:49.022897 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:57:52.794414 validate duration: 21.34
14 13:57:52.794665 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:57:52.794761 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:57:52.794850 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:57:52.794991 Not decompressing ramdisk as can be used compressed.
18 13:57:52.795134 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 13:57:52.795217 saving as /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/ramdisk/rootfs.cpio.gz
20 13:57:52.795280 total size: 34390042 (32 MB)
21 13:57:53.060297 progress 0 % (0 MB)
22 13:57:53.075186 progress 5 % (1 MB)
23 13:57:53.089987 progress 10 % (3 MB)
24 13:57:53.104737 progress 15 % (4 MB)
25 13:57:53.119057 progress 20 % (6 MB)
26 13:57:53.133187 progress 25 % (8 MB)
27 13:57:53.142441 progress 30 % (9 MB)
28 13:57:53.151617 progress 35 % (11 MB)
29 13:57:53.161413 progress 40 % (13 MB)
30 13:57:53.171311 progress 45 % (14 MB)
31 13:57:53.180866 progress 50 % (16 MB)
32 13:57:53.190289 progress 55 % (18 MB)
33 13:57:53.199660 progress 60 % (19 MB)
34 13:57:53.209072 progress 65 % (21 MB)
35 13:57:53.218146 progress 70 % (22 MB)
36 13:57:53.227408 progress 75 % (24 MB)
37 13:57:53.237005 progress 80 % (26 MB)
38 13:57:53.247015 progress 85 % (27 MB)
39 13:57:53.256971 progress 90 % (29 MB)
40 13:57:53.266593 progress 95 % (31 MB)
41 13:57:53.276008 progress 100 % (32 MB)
42 13:57:53.276246 32 MB downloaded in 0.48 s (68.19 MB/s)
43 13:57:53.276415 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:57:53.276751 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:57:53.276877 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:57:53.276973 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:57:53.277110 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:57:53.277182 saving as /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/kernel/Image
50 13:57:53.277244 total size: 49222144 (46 MB)
51 13:57:53.277307 No compression specified
52 13:57:53.278473 progress 0 % (0 MB)
53 13:57:53.292311 progress 5 % (2 MB)
54 13:57:53.305857 progress 10 % (4 MB)
55 13:57:53.319416 progress 15 % (7 MB)
56 13:57:53.333038 progress 20 % (9 MB)
57 13:57:53.347506 progress 25 % (11 MB)
58 13:57:53.361928 progress 30 % (14 MB)
59 13:57:53.375760 progress 35 % (16 MB)
60 13:57:53.389437 progress 40 % (18 MB)
61 13:57:53.403065 progress 45 % (21 MB)
62 13:57:53.416068 progress 50 % (23 MB)
63 13:57:53.428849 progress 55 % (25 MB)
64 13:57:53.441824 progress 60 % (28 MB)
65 13:57:53.454849 progress 65 % (30 MB)
66 13:57:53.467740 progress 70 % (32 MB)
67 13:57:53.480912 progress 75 % (35 MB)
68 13:57:53.493846 progress 80 % (37 MB)
69 13:57:53.506638 progress 85 % (39 MB)
70 13:57:53.519500 progress 90 % (42 MB)
71 13:57:53.532342 progress 95 % (44 MB)
72 13:57:53.544971 progress 100 % (46 MB)
73 13:57:53.545165 46 MB downloaded in 0.27 s (175.21 MB/s)
74 13:57:53.545334 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:57:53.545564 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:57:53.545692 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:57:53.545789 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:57:53.545930 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:57:53.546001 saving as /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/dtb/mt8192-asurada-spherion-r0.dtb
81 13:57:53.546063 total size: 47278 (0 MB)
82 13:57:53.546124 No compression specified
83 13:57:53.547337 progress 69 % (0 MB)
84 13:57:53.547653 progress 100 % (0 MB)
85 13:57:53.547810 0 MB downloaded in 0.00 s (25.84 MB/s)
86 13:57:53.547977 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:57:53.548202 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:57:53.548287 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:57:53.548370 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:57:53.548484 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:57:53.548552 saving as /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/modules/modules.tar
93 13:57:53.548614 total size: 8615960 (8 MB)
94 13:57:53.548675 Using unxz to decompress xz
95 13:57:53.553071 progress 0 % (0 MB)
96 13:57:53.574665 progress 5 % (0 MB)
97 13:57:53.597196 progress 10 % (0 MB)
98 13:57:53.623957 progress 15 % (1 MB)
99 13:57:53.649539 progress 20 % (1 MB)
100 13:57:53.675783 progress 25 % (2 MB)
101 13:57:53.702085 progress 30 % (2 MB)
102 13:57:53.728993 progress 35 % (2 MB)
103 13:57:53.754421 progress 40 % (3 MB)
104 13:57:53.778856 progress 45 % (3 MB)
105 13:57:53.805309 progress 50 % (4 MB)
106 13:57:53.830409 progress 55 % (4 MB)
107 13:57:53.855341 progress 60 % (4 MB)
108 13:57:53.877867 progress 65 % (5 MB)
109 13:57:53.905103 progress 70 % (5 MB)
110 13:57:53.929105 progress 75 % (6 MB)
111 13:57:53.955766 progress 80 % (6 MB)
112 13:57:53.985652 progress 85 % (7 MB)
113 13:57:54.011651 progress 90 % (7 MB)
114 13:57:54.036828 progress 95 % (7 MB)
115 13:57:54.060495 progress 100 % (8 MB)
116 13:57:54.066784 8 MB downloaded in 0.52 s (15.86 MB/s)
117 13:57:54.067071 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:57:54.067364 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:57:54.067472 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:57:54.067584 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:57:54.067681 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:57:54.067797 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:57:54.068114 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs
125 13:57:54.068293 makedir: /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin
126 13:57:54.068473 makedir: /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/tests
127 13:57:54.068613 makedir: /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/results
128 13:57:54.068746 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-add-keys
129 13:57:54.068912 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-add-sources
130 13:57:54.069061 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-background-process-start
131 13:57:54.069210 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-background-process-stop
132 13:57:54.069360 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-common-functions
133 13:57:54.069533 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-echo-ipv4
134 13:57:54.069707 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-install-packages
135 13:57:54.069875 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-installed-packages
136 13:57:54.070018 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-os-build
137 13:57:54.070164 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-probe-channel
138 13:57:54.070308 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-probe-ip
139 13:57:54.070452 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-target-ip
140 13:57:54.070596 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-target-mac
141 13:57:54.070744 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-target-storage
142 13:57:54.070921 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-test-case
143 13:57:54.071092 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-test-event
144 13:57:54.071263 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-test-feedback
145 13:57:54.071432 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-test-raise
146 13:57:54.071577 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-test-reference
147 13:57:54.071724 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-test-runner
148 13:57:54.071872 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-test-set
149 13:57:54.072074 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-test-shell
150 13:57:54.072223 Updating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-install-packages (oe)
151 13:57:54.072401 Updating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/bin/lava-installed-packages (oe)
152 13:57:54.072569 Creating /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/environment
153 13:57:54.072709 LAVA metadata
154 13:57:54.072793 - LAVA_JOB_ID=11372179
155 13:57:54.072872 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:57:54.073000 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:57:54.073105 skipped lava-vland-overlay
158 13:57:54.073204 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:57:54.073304 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:57:54.073381 skipped lava-multinode-overlay
161 13:57:54.073500 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:57:54.073630 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:57:54.073753 Loading test definitions
164 13:57:54.073869 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:57:54.073981 Using /lava-11372179 at stage 0
166 13:57:54.074438 uuid=11372179_1.5.2.3.1 testdef=None
167 13:57:54.074629 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:57:54.074765 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:57:54.075487 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:57:54.075836 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:57:54.076521 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:57:54.076747 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:57:54.077346 runner path: /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/0/tests/0_cros-ec test_uuid 11372179_1.5.2.3.1
176 13:57:54.077500 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:57:54.077706 Creating lava-test-runner.conf files
179 13:57:54.077769 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11372179/lava-overlay-fnfs6qhs/lava-11372179/0 for stage 0
180 13:57:54.077858 - 0_cros-ec
181 13:57:54.077954 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:57:54.078040 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:57:54.084735 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:57:54.084848 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:57:54.084937 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:57:54.085026 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:57:54.085113 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:57:55.088476 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:57:55.088875 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:57:55.089002 extracting modules file /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11372179/extract-overlay-ramdisk-svhv5v_y/ramdisk
191 13:57:55.320557 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:57:55.320740 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 13:57:55.320837 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11372179/compress-overlay-5bm60ib6/overlay-1.5.2.4.tar.gz to ramdisk
194 13:57:55.320910 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11372179/compress-overlay-5bm60ib6/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11372179/extract-overlay-ramdisk-svhv5v_y/ramdisk
195 13:57:55.327568 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:57:55.327687 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 13:57:55.327777 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:57:55.327871 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 13:57:55.328001 Building ramdisk /var/lib/lava/dispatcher/tmp/11372179/extract-overlay-ramdisk-svhv5v_y/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11372179/extract-overlay-ramdisk-svhv5v_y/ramdisk
200 13:57:56.114920 >> 270894 blocks
201 13:58:00.865300 rename /var/lib/lava/dispatcher/tmp/11372179/extract-overlay-ramdisk-svhv5v_y/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/ramdisk/ramdisk.cpio.gz
202 13:58:00.865772 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 13:58:00.865950 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 13:58:00.866102 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 13:58:00.866257 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/kernel/Image'
206 13:58:13.776047 Returned 0 in 12 seconds
207 13:58:13.876787 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/kernel/image.itb
208 13:58:14.600952 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:58:14.601416 output: Created: Mon Aug 28 14:58:14 2023
210 13:58:14.601531 output: Image 0 (kernel-1)
211 13:58:14.601629 output: Description:
212 13:58:14.601726 output: Created: Mon Aug 28 14:58:14 2023
213 13:58:14.601822 output: Type: Kernel Image
214 13:58:14.601918 output: Compression: lzma compressed
215 13:58:14.602009 output: Data Size: 11039834 Bytes = 10781.09 KiB = 10.53 MiB
216 13:58:14.602104 output: Architecture: AArch64
217 13:58:14.602195 output: OS: Linux
218 13:58:14.602287 output: Load Address: 0x00000000
219 13:58:14.602375 output: Entry Point: 0x00000000
220 13:58:14.602463 output: Hash algo: crc32
221 13:58:14.602551 output: Hash value: 946c5cd4
222 13:58:14.602639 output: Image 1 (fdt-1)
223 13:58:14.602728 output: Description: mt8192-asurada-spherion-r0
224 13:58:14.602816 output: Created: Mon Aug 28 14:58:14 2023
225 13:58:14.602905 output: Type: Flat Device Tree
226 13:58:14.602995 output: Compression: uncompressed
227 13:58:14.603084 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:58:14.603172 output: Architecture: AArch64
229 13:58:14.603260 output: Hash algo: crc32
230 13:58:14.603346 output: Hash value: cc4352de
231 13:58:14.603434 output: Image 2 (ramdisk-1)
232 13:58:14.603525 output: Description: unavailable
233 13:58:14.603612 output: Created: Mon Aug 28 14:58:14 2023
234 13:58:14.603700 output: Type: RAMDisk Image
235 13:58:14.603787 output: Compression: Unknown Compression
236 13:58:14.603874 output: Data Size: 47508781 Bytes = 46395.29 KiB = 45.31 MiB
237 13:58:14.604006 output: Architecture: AArch64
238 13:58:14.604093 output: OS: Linux
239 13:58:14.604180 output: Load Address: unavailable
240 13:58:14.604267 output: Entry Point: unavailable
241 13:58:14.604353 output: Hash algo: crc32
242 13:58:14.604441 output: Hash value: 677a3b25
243 13:58:14.604528 output: Default Configuration: 'conf-1'
244 13:58:14.604616 output: Configuration 0 (conf-1)
245 13:58:14.604704 output: Description: mt8192-asurada-spherion-r0
246 13:58:14.604792 output: Kernel: kernel-1
247 13:58:14.604880 output: Init Ramdisk: ramdisk-1
248 13:58:14.604967 output: FDT: fdt-1
249 13:58:14.605054 output: Loadables: kernel-1
250 13:58:14.605140 output:
251 13:58:14.605411 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 13:58:14.605564 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 13:58:14.605713 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 13:58:14.605856 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 13:58:14.605974 No LXC device requested
256 13:58:14.606098 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:58:14.606231 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 13:58:14.606350 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:58:14.606454 Checking files for TFTP limit of 4294967296 bytes.
260 13:58:14.607142 end: 1 tftp-deploy (duration 00:00:22) [common]
261 13:58:14.607279 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:58:14.607408 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:58:14.607572 substitutions:
264 13:58:14.607672 - {DTB}: 11372179/tftp-deploy-x_1saco3/dtb/mt8192-asurada-spherion-r0.dtb
265 13:58:14.607770 - {INITRD}: 11372179/tftp-deploy-x_1saco3/ramdisk/ramdisk.cpio.gz
266 13:58:14.607861 - {KERNEL}: 11372179/tftp-deploy-x_1saco3/kernel/Image
267 13:58:14.607990 - {LAVA_MAC}: None
268 13:58:14.608080 - {PRESEED_CONFIG}: None
269 13:58:14.608167 - {PRESEED_LOCAL}: None
270 13:58:14.608254 - {RAMDISK}: 11372179/tftp-deploy-x_1saco3/ramdisk/ramdisk.cpio.gz
271 13:58:14.608342 - {ROOT_PART}: None
272 13:58:14.608428 - {ROOT}: None
273 13:58:14.608514 - {SERVER_IP}: 192.168.201.1
274 13:58:14.608599 - {TEE}: None
275 13:58:14.608683 Parsed boot commands:
276 13:58:14.608768 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:58:14.609020 Parsed boot commands: tftpboot 192.168.201.1 11372179/tftp-deploy-x_1saco3/kernel/image.itb 11372179/tftp-deploy-x_1saco3/kernel/cmdline
278 13:58:14.609154 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:58:14.609278 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:58:14.609414 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:58:14.609566 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:58:14.609687 Not connected, no need to disconnect.
283 13:58:14.609798 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:58:14.609916 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:58:14.610020 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 13:58:14.615030 Setting prompt string to ['lava-test: # ']
287 13:58:14.615502 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:58:14.615694 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:58:14.615866 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:58:14.616033 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:58:14.616344 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 13:58:19.762182 >> Command sent successfully.
293 13:58:19.772538 Returned 0 in 5 seconds
294 13:58:19.873689 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:58:19.875194 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:58:19.875691 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:58:19.876176 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:58:19.876542 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:58:19.876896 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:58:19.878115 [Enter `^Ec?' for help]
302 13:58:20.039660
303 13:58:20.040237
304 13:58:20.040649 F0: 102B 0000
305 13:58:20.040992
306 13:58:20.041298 F3: 1001 0000 [0200]
307 13:58:20.041600
308 13:58:20.044594 F3: 1001 0000
309 13:58:20.045014
310 13:58:20.045346 F7: 102D 0000
311 13:58:20.045657
312 13:58:20.045955 F1: 0000 0000
313 13:58:20.046249
314 13:58:20.047434 V0: 0000 0000 [0001]
315 13:58:20.047868
316 13:58:20.048255 00: 0007 8000
317 13:58:20.048593
318 13:58:20.050788 01: 0000 0000
319 13:58:20.051323
320 13:58:20.051783 BP: 0C00 0209 [0000]
321 13:58:20.052177
322 13:58:20.054630 G0: 1182 0000
323 13:58:20.055164
324 13:58:20.055508 EC: 0000 0021 [4000]
325 13:58:20.055985
326 13:58:20.058951 S7: 0000 0000 [0000]
327 13:58:20.059544
328 13:58:20.059888 CC: 0000 0000 [0001]
329 13:58:20.060265
330 13:58:20.062078 T0: 0000 0040 [010F]
331 13:58:20.062505
332 13:58:20.062841 Jump to BL
333 13:58:20.063154
334 13:58:20.086803
335 13:58:20.087336
336 13:58:20.087844
337 13:58:20.093281 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 13:58:20.097099 ARM64: Exception handlers installed.
339 13:58:20.099746 ARM64: Testing exception
340 13:58:20.103255 ARM64: Done test exception
341 13:58:20.110910 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 13:58:20.121307 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 13:58:20.129231 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 13:58:20.138711 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 13:58:20.145108 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 13:58:20.151537 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 13:58:20.163578 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 13:58:20.170627 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 13:58:20.189191 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 13:58:20.192634 WDT: Last reset was cold boot
351 13:58:20.196082 SPI1(PAD0) initialized at 2873684 Hz
352 13:58:20.199343 SPI5(PAD0) initialized at 992727 Hz
353 13:58:20.202607 VBOOT: Loading verstage.
354 13:58:20.209558 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 13:58:20.212567 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 13:58:20.216173 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 13:58:20.219976 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 13:58:20.226782 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 13:58:20.234209 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 13:58:20.244443 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 13:58:20.244994
362 13:58:20.245444
363 13:58:20.254741 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 13:58:20.257410 ARM64: Exception handlers installed.
365 13:58:20.260777 ARM64: Testing exception
366 13:58:20.261225 ARM64: Done test exception
367 13:58:20.268085 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 13:58:20.271525 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 13:58:20.285463 Probing TPM: . done!
370 13:58:20.285997 TPM ready after 0 ms
371 13:58:20.291768 Connected to device vid:did:rid of 1ae0:0028:00
372 13:58:20.298897 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 13:58:20.358984 Initialized TPM device CR50 revision 0
374 13:58:20.370633 tlcl_send_startup: Startup return code is 0
375 13:58:20.371156 TPM: setup succeeded
376 13:58:20.381812 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 13:58:20.390708 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:58:20.404590 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 13:58:20.411050 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 13:58:20.414746 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 13:58:20.421860 in-header: 03 07 00 00 08 00 00 00
382 13:58:20.425049 in-data: aa e4 47 04 13 02 00 00
383 13:58:20.429209 Chrome EC: UHEPI supported
384 13:58:20.435781 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 13:58:20.439325 in-header: 03 95 00 00 08 00 00 00
386 13:58:20.443397 in-data: 18 20 20 08 00 00 00 00
387 13:58:20.443978 Phase 1
388 13:58:20.447187 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 13:58:20.454579 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 13:58:20.458684 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 13:58:20.462844 Recovery requested (1009000e)
392 13:58:20.470696 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:58:20.476069 tlcl_extend: response is 0
394 13:58:20.485528 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:58:20.491245 tlcl_extend: response is 0
396 13:58:20.498173 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:58:20.517809 read SPI 0x210d4 0x2173b: 15142 us, 9048 KB/s, 72.384 Mbps
398 13:58:20.524662 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:58:20.525083
400 13:58:20.525416
401 13:58:20.534636 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:58:20.538064 ARM64: Exception handlers installed.
403 13:58:20.540819 ARM64: Testing exception
404 13:58:20.541338 ARM64: Done test exception
405 13:58:20.564320 pmic_efuse_setting: Set efuses in 11 msecs
406 13:58:20.566768 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:58:20.573763 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:58:20.576815 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:58:20.583573 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:58:20.587478 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:58:20.590583 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:58:20.597905 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:58:20.601945 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:58:20.605106 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:58:20.608770 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:58:20.616080 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:58:20.619841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:58:20.624188 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:58:20.627083 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:58:20.635644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:58:20.643105 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:58:20.646660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:58:20.653538 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:58:20.657241 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:58:20.665125 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:58:20.668524 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:58:20.675428 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:58:20.679010 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:58:20.686512 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:58:20.690537 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:58:20.697587 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:58:20.701401 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:58:20.708436 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:58:20.712233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:58:20.716048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:58:20.723317 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:58:20.727180 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:58:20.731181 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:58:20.737870 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:58:20.740984 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:58:20.748189 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:58:20.752990 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:58:20.756028 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:58:20.762993 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:58:20.766974 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:58:20.770171 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:58:20.774054 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:58:20.781197 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:58:20.785769 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:58:20.788735 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:58:20.792087 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:58:20.796048 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:58:20.803738 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:58:20.806913 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:58:20.810794 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:58:20.813938 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:58:20.817574 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:58:20.824985 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 13:58:20.836570 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:58:20.839717 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:58:20.846743 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:58:20.854727 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:58:20.862413 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:58:20.865293 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:58:20.868739 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:58:20.876094 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x5
467 13:58:20.883402 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:58:20.887157 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 13:58:20.890441 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:58:20.900355 [RTC]rtc_get_frequency_meter,154: input=15, output=853
471 13:58:20.910664 [RTC]rtc_get_frequency_meter,154: input=7, output=725
472 13:58:20.919537 [RTC]rtc_get_frequency_meter,154: input=11, output=789
473 13:58:20.929098 [RTC]rtc_get_frequency_meter,154: input=13, output=822
474 13:58:20.938267 [RTC]rtc_get_frequency_meter,154: input=12, output=806
475 13:58:20.948212 [RTC]rtc_get_frequency_meter,154: input=11, output=790
476 13:58:20.958361 [RTC]rtc_get_frequency_meter,154: input=12, output=805
477 13:58:20.961812 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 13:58:20.965519 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 13:58:20.972909 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 13:58:20.976655 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 13:58:20.980320 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 13:58:20.984585 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 13:58:20.987825 ADC[4]: Raw value=905541 ID=7
484 13:58:20.988302 ADC[3]: Raw value=213546 ID=1
485 13:58:20.991191 RAM Code: 0x71
486 13:58:20.995167 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 13:58:20.999202 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 13:58:21.009055 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 13:58:21.016813 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 13:58:21.017294 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 13:58:21.020830 in-header: 03 07 00 00 08 00 00 00
492 13:58:21.025086 in-data: aa e4 47 04 13 02 00 00
493 13:58:21.028606 Chrome EC: UHEPI supported
494 13:58:21.035865 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 13:58:21.039255 in-header: 03 95 00 00 08 00 00 00
496 13:58:21.043335 in-data: 18 20 20 08 00 00 00 00
497 13:58:21.043861 MRC: failed to locate region type 0.
498 13:58:21.049752 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 13:58:21.053700 DRAM-K: Running full calibration
500 13:58:21.060984 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 13:58:21.061595 header.status = 0x0
502 13:58:21.064688 header.version = 0x6 (expected: 0x6)
503 13:58:21.068239 header.size = 0xd00 (expected: 0xd00)
504 13:58:21.071776 header.flags = 0x0
505 13:58:21.075121 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 13:58:21.094849 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 13:58:21.102114 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 13:58:21.106177 dram_init: ddr_geometry: 2
509 13:58:21.106641 [EMI] MDL number = 2
510 13:58:21.109299 [EMI] Get MDL freq = 0
511 13:58:21.109877 dram_init: ddr_type: 0
512 13:58:21.112957 is_discrete_lpddr4: 1
513 13:58:21.116835 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 13:58:21.117265
515 13:58:21.117601
516 13:58:21.117913 [Bian_co] ETT version 0.0.0.1
517 13:58:21.123975 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 13:58:21.124415
519 13:58:21.127120 dramc_set_vcore_voltage set vcore to 650000
520 13:58:21.130656 Read voltage for 800, 4
521 13:58:21.131081 Vio18 = 0
522 13:58:21.131421 Vcore = 650000
523 13:58:21.134120 Vdram = 0
524 13:58:21.134661 Vddq = 0
525 13:58:21.135001 Vmddr = 0
526 13:58:21.136908 dram_init: config_dvfs: 1
527 13:58:21.140473 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 13:58:21.148763 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 13:58:21.151204 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 13:58:21.155426 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 13:58:21.159361 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 13:58:21.162187 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 13:58:21.165704 MEM_TYPE=3, freq_sel=18
534 13:58:21.166227 sv_algorithm_assistance_LP4_1600
535 13:58:21.172512 ============ PULL DRAM RESETB DOWN ============
536 13:58:21.176041 ========== PULL DRAM RESETB DOWN end =========
537 13:58:21.179759 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 13:58:21.184004 ===================================
539 13:58:21.186791 LPDDR4 DRAM CONFIGURATION
540 13:58:21.189783 ===================================
541 13:58:21.190244 EX_ROW_EN[0] = 0x0
542 13:58:21.193343 EX_ROW_EN[1] = 0x0
543 13:58:21.193774 LP4Y_EN = 0x0
544 13:58:21.196481 WORK_FSP = 0x0
545 13:58:21.200435 WL = 0x2
546 13:58:21.200957 RL = 0x2
547 13:58:21.203107 BL = 0x2
548 13:58:21.203626 RPST = 0x0
549 13:58:21.206602 RD_PRE = 0x0
550 13:58:21.207067 WR_PRE = 0x1
551 13:58:21.210476 WR_PST = 0x0
552 13:58:21.211029 DBI_WR = 0x0
553 13:58:21.213685 DBI_RD = 0x0
554 13:58:21.214208 OTF = 0x1
555 13:58:21.216815 ===================================
556 13:58:21.219969 ===================================
557 13:58:21.223414 ANA top config
558 13:58:21.226307 ===================================
559 13:58:21.226728 DLL_ASYNC_EN = 0
560 13:58:21.229587 ALL_SLAVE_EN = 1
561 13:58:21.232846 NEW_RANK_MODE = 1
562 13:58:21.236206 DLL_IDLE_MODE = 1
563 13:58:21.236633 LP45_APHY_COMB_EN = 1
564 13:58:21.239580 TX_ODT_DIS = 1
565 13:58:21.242974 NEW_8X_MODE = 1
566 13:58:21.246092 ===================================
567 13:58:21.249459 ===================================
568 13:58:21.252763 data_rate = 1600
569 13:58:21.256403 CKR = 1
570 13:58:21.259857 DQ_P2S_RATIO = 8
571 13:58:21.263177 ===================================
572 13:58:21.263712 CA_P2S_RATIO = 8
573 13:58:21.267226 DQ_CA_OPEN = 0
574 13:58:21.270349 DQ_SEMI_OPEN = 0
575 13:58:21.274087 CA_SEMI_OPEN = 0
576 13:58:21.274610 CA_FULL_RATE = 0
577 13:58:21.276955 DQ_CKDIV4_EN = 1
578 13:58:21.280171 CA_CKDIV4_EN = 1
579 13:58:21.284285 CA_PREDIV_EN = 0
580 13:58:21.287030 PH8_DLY = 0
581 13:58:21.290190 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 13:58:21.290614 DQ_AAMCK_DIV = 4
583 13:58:21.293518 CA_AAMCK_DIV = 4
584 13:58:21.297070 CA_ADMCK_DIV = 4
585 13:58:21.300547 DQ_TRACK_CA_EN = 0
586 13:58:21.303796 CA_PICK = 800
587 13:58:21.306742 CA_MCKIO = 800
588 13:58:21.311133 MCKIO_SEMI = 0
589 13:58:21.311731 PLL_FREQ = 3068
590 13:58:21.314712 DQ_UI_PI_RATIO = 32
591 13:58:21.317728 CA_UI_PI_RATIO = 0
592 13:58:21.321076 ===================================
593 13:58:21.325314 ===================================
594 13:58:21.325834 memory_type:LPDDR4
595 13:58:21.328658 GP_NUM : 10
596 13:58:21.329084 SRAM_EN : 1
597 13:58:21.332174 MD32_EN : 0
598 13:58:21.336098 ===================================
599 13:58:21.339646 [ANA_INIT] >>>>>>>>>>>>>>
600 13:58:21.340204 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 13:58:21.343734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 13:58:21.347278 ===================================
603 13:58:21.350535 data_rate = 1600,PCW = 0X7600
604 13:58:21.353483 ===================================
605 13:58:21.357050 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 13:58:21.363504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:58:21.366709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 13:58:21.373222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 13:58:21.377252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:58:21.380075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 13:58:21.380636 [ANA_INIT] flow start
612 13:58:21.383380 [ANA_INIT] PLL >>>>>>>>
613 13:58:21.386428 [ANA_INIT] PLL <<<<<<<<
614 13:58:21.389659 [ANA_INIT] MIDPI >>>>>>>>
615 13:58:21.390152 [ANA_INIT] MIDPI <<<<<<<<
616 13:58:21.393911 [ANA_INIT] DLL >>>>>>>>
617 13:58:21.396786 [ANA_INIT] flow end
618 13:58:21.399868 ============ LP4 DIFF to SE enter ============
619 13:58:21.403245 ============ LP4 DIFF to SE exit ============
620 13:58:21.406824 [ANA_INIT] <<<<<<<<<<<<<
621 13:58:21.410294 [Flow] Enable top DCM control >>>>>
622 13:58:21.413436 [Flow] Enable top DCM control <<<<<
623 13:58:21.416580 Enable DLL master slave shuffle
624 13:58:21.419758 ==============================================================
625 13:58:21.423212 Gating Mode config
626 13:58:21.429938 ==============================================================
627 13:58:21.430475 Config description:
628 13:58:21.439886 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 13:58:21.446508 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 13:58:21.450189 SELPH_MODE 0: By rank 1: By Phase
631 13:58:21.456479 ==============================================================
632 13:58:21.459606 GAT_TRACK_EN = 1
633 13:58:21.463110 RX_GATING_MODE = 2
634 13:58:21.466321 RX_GATING_TRACK_MODE = 2
635 13:58:21.469391 SELPH_MODE = 1
636 13:58:21.472811 PICG_EARLY_EN = 1
637 13:58:21.475973 VALID_LAT_VALUE = 1
638 13:58:21.479737 ==============================================================
639 13:58:21.482590 Enter into Gating configuration >>>>
640 13:58:21.486465 Exit from Gating configuration <<<<
641 13:58:21.489869 Enter into DVFS_PRE_config >>>>>
642 13:58:21.499248 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 13:58:21.502644 Exit from DVFS_PRE_config <<<<<
644 13:58:21.505647 Enter into PICG configuration >>>>
645 13:58:21.509488 Exit from PICG configuration <<<<
646 13:58:21.512493 [RX_INPUT] configuration >>>>>
647 13:58:21.516285 [RX_INPUT] configuration <<<<<
648 13:58:21.522750 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 13:58:21.526301 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 13:58:21.532575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 13:58:21.539748 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 13:58:21.546540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 13:58:21.552852 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 13:58:21.556035 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 13:58:21.559104 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 13:58:21.562352 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 13:58:21.569081 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 13:58:21.572769 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 13:58:21.576127 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 13:58:21.579017 ===================================
661 13:58:21.582554 LPDDR4 DRAM CONFIGURATION
662 13:58:21.585601 ===================================
663 13:58:21.586174 EX_ROW_EN[0] = 0x0
664 13:58:21.588516 EX_ROW_EN[1] = 0x0
665 13:58:21.592086 LP4Y_EN = 0x0
666 13:58:21.592512 WORK_FSP = 0x0
667 13:58:21.595510 WL = 0x2
668 13:58:21.596178 RL = 0x2
669 13:58:21.598311 BL = 0x2
670 13:58:21.598734 RPST = 0x0
671 13:58:21.602107 RD_PRE = 0x0
672 13:58:21.602568 WR_PRE = 0x1
673 13:58:21.605051 WR_PST = 0x0
674 13:58:21.605474 DBI_WR = 0x0
675 13:58:21.608413 DBI_RD = 0x0
676 13:58:21.608842 OTF = 0x1
677 13:58:21.611832 ===================================
678 13:58:21.615706 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 13:58:21.622501 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 13:58:21.625490 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 13:58:21.628353 ===================================
682 13:58:21.631688 LPDDR4 DRAM CONFIGURATION
683 13:58:21.635024 ===================================
684 13:58:21.635448 EX_ROW_EN[0] = 0x10
685 13:58:21.638370 EX_ROW_EN[1] = 0x0
686 13:58:21.642024 LP4Y_EN = 0x0
687 13:58:21.642455 WORK_FSP = 0x0
688 13:58:21.645159 WL = 0x2
689 13:58:21.645583 RL = 0x2
690 13:58:21.648312 BL = 0x2
691 13:58:21.648733 RPST = 0x0
692 13:58:21.651333 RD_PRE = 0x0
693 13:58:21.651754 WR_PRE = 0x1
694 13:58:21.655123 WR_PST = 0x0
695 13:58:21.655653 DBI_WR = 0x0
696 13:58:21.658694 DBI_RD = 0x0
697 13:58:21.659227 OTF = 0x1
698 13:58:21.661679 ===================================
699 13:58:21.668623 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 13:58:21.672871 nWR fixed to 40
701 13:58:21.675765 [ModeRegInit_LP4] CH0 RK0
702 13:58:21.676348 [ModeRegInit_LP4] CH0 RK1
703 13:58:21.679659 [ModeRegInit_LP4] CH1 RK0
704 13:58:21.682611 [ModeRegInit_LP4] CH1 RK1
705 13:58:21.683130 match AC timing 13
706 13:58:21.689292 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 13:58:21.692397 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 13:58:21.695474 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 13:58:21.702133 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 13:58:21.705329 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 13:58:21.708738 [EMI DOE] emi_dcm 0
712 13:58:21.712165 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 13:58:21.712599 ==
714 13:58:21.715524 Dram Type= 6, Freq= 0, CH_0, rank 0
715 13:58:21.718807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 13:58:21.719451 ==
717 13:58:21.725595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 13:58:21.732099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 13:58:21.740029 [CA 0] Center 37 (7~68) winsize 62
720 13:58:21.743769 [CA 1] Center 37 (6~68) winsize 63
721 13:58:21.747709 [CA 2] Center 34 (4~65) winsize 62
722 13:58:21.750394 [CA 3] Center 34 (4~65) winsize 62
723 13:58:21.754416 [CA 4] Center 33 (3~64) winsize 62
724 13:58:21.756623 [CA 5] Center 33 (3~64) winsize 62
725 13:58:21.757051
726 13:58:21.759860 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 13:58:21.760331
728 13:58:21.763430 [CATrainingPosCal] consider 1 rank data
729 13:58:21.767244 u2DelayCellTimex100 = 270/100 ps
730 13:58:21.770197 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 13:58:21.774051 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 13:58:21.780964 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 13:58:21.783191 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 13:58:21.786702 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 13:58:21.789628 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 13:58:21.790056
737 13:58:21.793055 CA PerBit enable=1, Macro0, CA PI delay=33
738 13:58:21.793480
739 13:58:21.796160 [CBTSetCACLKResult] CA Dly = 33
740 13:58:21.796818 CS Dly: 6 (0~37)
741 13:58:21.799639 ==
742 13:58:21.802910 Dram Type= 6, Freq= 0, CH_0, rank 1
743 13:58:21.806310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 13:58:21.806738 ==
745 13:58:21.809380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 13:58:21.816375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 13:58:21.826721 [CA 0] Center 38 (7~69) winsize 63
748 13:58:21.829523 [CA 1] Center 37 (7~68) winsize 62
749 13:58:21.832935 [CA 2] Center 35 (4~66) winsize 63
750 13:58:21.835812 [CA 3] Center 35 (4~66) winsize 63
751 13:58:21.839152 [CA 4] Center 34 (3~65) winsize 63
752 13:58:21.842956 [CA 5] Center 33 (3~64) winsize 62
753 13:58:21.843584
754 13:58:21.845862 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 13:58:21.846393
756 13:58:21.849562 [CATrainingPosCal] consider 2 rank data
757 13:58:21.853647 u2DelayCellTimex100 = 270/100 ps
758 13:58:21.856303 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 13:58:21.862904 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 13:58:21.866327 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 13:58:21.869314 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 13:58:21.872820 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 13:58:21.876055 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 13:58:21.876691
765 13:58:21.879810 CA PerBit enable=1, Macro0, CA PI delay=33
766 13:58:21.880470
767 13:58:21.882231 [CBTSetCACLKResult] CA Dly = 33
768 13:58:21.882695 CS Dly: 6 (0~38)
769 13:58:21.886035
770 13:58:21.889256 ----->DramcWriteLeveling(PI) begin...
771 13:58:21.889696 ==
772 13:58:21.892930 Dram Type= 6, Freq= 0, CH_0, rank 0
773 13:58:21.896759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 13:58:21.897289 ==
775 13:58:21.900829 Write leveling (Byte 0): 30 => 30
776 13:58:21.901251 Write leveling (Byte 1): 30 => 30
777 13:58:21.904447 DramcWriteLeveling(PI) end<-----
778 13:58:21.905002
779 13:58:21.905351 ==
780 13:58:21.908188 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:58:21.911128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:58:21.911557 ==
783 13:58:21.914429 [Gating] SW mode calibration
784 13:58:21.921810 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 13:58:21.929282 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 13:58:21.932290 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:58:21.935206 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 13:58:21.941879 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 13:58:21.945542 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 13:58:21.948699 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:58:21.955350 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:58:21.958489 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:58:21.962175 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:58:21.968681 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:58:21.972296 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:58:21.975142 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:58:21.981654 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:58:21.984872 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:58:21.988620 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:58:21.994920 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:58:21.997885 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:58:22.002053 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 13:58:22.008466 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
804 13:58:22.011570 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 13:58:22.015139 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:58:22.018488 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:58:22.025006 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:58:22.028289 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:58:22.032166 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:58:22.038051 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:58:22.041675 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:58:22.045338 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
813 13:58:22.051607 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
814 13:58:22.054862 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:58:22.057849 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:58:22.064558 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:58:22.068108 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:58:22.071762 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 13:58:22.078357 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
820 13:58:22.081397 0 10 8 | B1->B0 | 3131 2424 | 0 0 | (0 1) (1 1)
821 13:58:22.084749 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
822 13:58:22.091271 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:58:22.094752 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:58:22.097786 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:58:22.104841 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:58:22.107877 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:58:22.111390 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
828 13:58:22.118219 0 11 8 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
829 13:58:22.121440 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
830 13:58:22.124617 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:58:22.131343 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:58:22.135813 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:58:22.138344 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:58:22.144481 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:58:22.147841 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 13:58:22.151212 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 13:58:22.158216 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:58:22.161189 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:58:22.164345 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:58:22.168070 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:58:22.174363 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:58:22.177874 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:58:22.181019 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:58:22.187376 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:58:22.190913 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:58:22.194190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:58:22.200563 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:58:22.203963 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:58:22.208248 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:58:22.214079 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:58:22.217614 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 13:58:22.221120 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 13:58:22.224193 Total UI for P1: 0, mck2ui 16
854 13:58:22.227624 best dqsien dly found for B0: ( 0, 14, 4)
855 13:58:22.234078 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 13:58:22.234614 Total UI for P1: 0, mck2ui 16
857 13:58:22.240616 best dqsien dly found for B1: ( 0, 14, 8)
858 13:58:22.244629 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 13:58:22.247223 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 13:58:22.247658
861 13:58:22.250798 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 13:58:22.254401 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 13:58:22.257409 [Gating] SW calibration Done
864 13:58:22.258051 ==
865 13:58:22.260435 Dram Type= 6, Freq= 0, CH_0, rank 0
866 13:58:22.263827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 13:58:22.264541 ==
868 13:58:22.267640 RX Vref Scan: 0
869 13:58:22.268255
870 13:58:22.268800 RX Vref 0 -> 0, step: 1
871 13:58:22.269341
872 13:58:22.271091 RX Delay -130 -> 252, step: 16
873 13:58:22.274833 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 13:58:22.277649 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 13:58:22.284785 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 13:58:22.287584 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 13:58:22.291556 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 13:58:22.294298 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 13:58:22.297500 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 13:58:22.304437 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 13:58:22.307785 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
882 13:58:22.311219 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 13:58:22.314779 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 13:58:22.318058 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 13:58:22.324063 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 13:58:22.327476 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 13:58:22.330848 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 13:58:22.334182 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 13:58:22.334742 ==
890 13:58:22.337462 Dram Type= 6, Freq= 0, CH_0, rank 0
891 13:58:22.344213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 13:58:22.344670 ==
893 13:58:22.345013 DQS Delay:
894 13:58:22.347376 DQS0 = 0, DQS1 = 0
895 13:58:22.347804 DQM Delay:
896 13:58:22.348208 DQM0 = 87, DQM1 = 75
897 13:58:22.351413 DQ Delay:
898 13:58:22.353947 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 13:58:22.357325 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
900 13:58:22.360882 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
901 13:58:22.364187 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 13:58:22.364731
903 13:58:22.365220
904 13:58:22.365553 ==
905 13:58:22.367582 Dram Type= 6, Freq= 0, CH_0, rank 0
906 13:58:22.370912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 13:58:22.371343 ==
908 13:58:22.371683
909 13:58:22.372048
910 13:58:22.374305 TX Vref Scan disable
911 13:58:22.374732 == TX Byte 0 ==
912 13:58:22.380639 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 13:58:22.383875 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 13:58:22.384348 == TX Byte 1 ==
915 13:58:22.391131 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 13:58:22.393700 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 13:58:22.394130 ==
918 13:58:22.396985 Dram Type= 6, Freq= 0, CH_0, rank 0
919 13:58:22.400635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 13:58:22.401230 ==
921 13:58:22.414471 TX Vref=22, minBit 7, minWin=26, winSum=439
922 13:58:22.417937 TX Vref=24, minBit 0, minWin=27, winSum=445
923 13:58:22.421285 TX Vref=26, minBit 0, minWin=27, winSum=446
924 13:58:22.424586 TX Vref=28, minBit 3, minWin=27, winSum=453
925 13:58:22.427986 TX Vref=30, minBit 1, minWin=28, winSum=457
926 13:58:22.434410 TX Vref=32, minBit 2, minWin=27, winSum=454
927 13:58:22.438034 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 30
928 13:58:22.438577
929 13:58:22.440993 Final TX Range 1 Vref 30
930 13:58:22.441521
931 13:58:22.441947 ==
932 13:58:22.444263 Dram Type= 6, Freq= 0, CH_0, rank 0
933 13:58:22.447628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 13:58:22.448274 ==
935 13:58:22.451199
936 13:58:22.451282
937 13:58:22.451348 TX Vref Scan disable
938 13:58:22.454329 == TX Byte 0 ==
939 13:58:22.457327 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 13:58:22.460946 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 13:58:22.465701 == TX Byte 1 ==
942 13:58:22.468112 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
943 13:58:22.471172 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
944 13:58:22.474289
945 13:58:22.474454 [DATLAT]
946 13:58:22.474542 Freq=800, CH0 RK0
947 13:58:22.474633
948 13:58:22.477484 DATLAT Default: 0xa
949 13:58:22.477588 0, 0xFFFF, sum = 0
950 13:58:22.480718 1, 0xFFFF, sum = 0
951 13:58:22.480811 2, 0xFFFF, sum = 0
952 13:58:22.484051 3, 0xFFFF, sum = 0
953 13:58:22.484147 4, 0xFFFF, sum = 0
954 13:58:22.488059 5, 0xFFFF, sum = 0
955 13:58:22.491311 6, 0xFFFF, sum = 0
956 13:58:22.491471 7, 0xFFFF, sum = 0
957 13:58:22.494347 8, 0xFFFF, sum = 0
958 13:58:22.494480 9, 0x0, sum = 1
959 13:58:22.494571 10, 0x0, sum = 2
960 13:58:22.497206 11, 0x0, sum = 3
961 13:58:22.497330 12, 0x0, sum = 4
962 13:58:22.500539 best_step = 10
963 13:58:22.500666
964 13:58:22.500763 ==
965 13:58:22.504743 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:58:22.507413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 13:58:22.507614 ==
968 13:58:22.510877 RX Vref Scan: 1
969 13:58:22.511030
970 13:58:22.511152 Set Vref Range= 32 -> 127
971 13:58:22.514001
972 13:58:22.514175 RX Vref 32 -> 127, step: 1
973 13:58:22.514314
974 13:58:22.517051 RX Delay -111 -> 252, step: 8
975 13:58:22.517311
976 13:58:22.520804 Set Vref, RX VrefLevel [Byte0]: 32
977 13:58:22.524145 [Byte1]: 32
978 13:58:22.524388
979 13:58:22.527725 Set Vref, RX VrefLevel [Byte0]: 33
980 13:58:22.530900 [Byte1]: 33
981 13:58:22.535830
982 13:58:22.536370 Set Vref, RX VrefLevel [Byte0]: 34
983 13:58:22.538343 [Byte1]: 34
984 13:58:22.543785
985 13:58:22.544346 Set Vref, RX VrefLevel [Byte0]: 35
986 13:58:22.546076 [Byte1]: 35
987 13:58:22.550420
988 13:58:22.550942 Set Vref, RX VrefLevel [Byte0]: 36
989 13:58:22.553853 [Byte1]: 36
990 13:58:22.558664
991 13:58:22.559185 Set Vref, RX VrefLevel [Byte0]: 37
992 13:58:22.561475 [Byte1]: 37
993 13:58:22.565659
994 13:58:22.566093 Set Vref, RX VrefLevel [Byte0]: 38
995 13:58:22.569342 [Byte1]: 38
996 13:58:22.573720
997 13:58:22.574253 Set Vref, RX VrefLevel [Byte0]: 39
998 13:58:22.576799 [Byte1]: 39
999 13:58:22.582034
1000 13:58:22.582553 Set Vref, RX VrefLevel [Byte0]: 40
1001 13:58:22.584599 [Byte1]: 40
1002 13:58:22.589696
1003 13:58:22.590209 Set Vref, RX VrefLevel [Byte0]: 41
1004 13:58:22.592584 [Byte1]: 41
1005 13:58:22.596179
1006 13:58:22.596665 Set Vref, RX VrefLevel [Byte0]: 42
1007 13:58:22.599602 [Byte1]: 42
1008 13:58:22.603937
1009 13:58:22.607374 Set Vref, RX VrefLevel [Byte0]: 43
1010 13:58:22.607958 [Byte1]: 43
1011 13:58:22.611064
1012 13:58:22.611491 Set Vref, RX VrefLevel [Byte0]: 44
1013 13:58:22.614593 [Byte1]: 44
1014 13:58:22.619256
1015 13:58:22.619683 Set Vref, RX VrefLevel [Byte0]: 45
1016 13:58:22.622498 [Byte1]: 45
1017 13:58:22.626726
1018 13:58:22.627291 Set Vref, RX VrefLevel [Byte0]: 46
1019 13:58:22.629774 [Byte1]: 46
1020 13:58:22.634350
1021 13:58:22.634772 Set Vref, RX VrefLevel [Byte0]: 47
1022 13:58:22.637462 [Byte1]: 47
1023 13:58:22.642231
1024 13:58:22.642653 Set Vref, RX VrefLevel [Byte0]: 48
1025 13:58:22.645462 [Byte1]: 48
1026 13:58:22.649942
1027 13:58:22.650447 Set Vref, RX VrefLevel [Byte0]: 49
1028 13:58:22.653180 [Byte1]: 49
1029 13:58:22.657560
1030 13:58:22.658040 Set Vref, RX VrefLevel [Byte0]: 50
1031 13:58:22.660801 [Byte1]: 50
1032 13:58:22.664599
1033 13:58:22.665215 Set Vref, RX VrefLevel [Byte0]: 51
1034 13:58:22.668357 [Byte1]: 51
1035 13:58:22.673590
1036 13:58:22.674010 Set Vref, RX VrefLevel [Byte0]: 52
1037 13:58:22.675281 [Byte1]: 52
1038 13:58:22.680029
1039 13:58:22.680110 Set Vref, RX VrefLevel [Byte0]: 53
1040 13:58:22.683465 [Byte1]: 53
1041 13:58:22.687603
1042 13:58:22.687706 Set Vref, RX VrefLevel [Byte0]: 54
1043 13:58:22.691344 [Byte1]: 54
1044 13:58:22.695420
1045 13:58:22.695514 Set Vref, RX VrefLevel [Byte0]: 55
1046 13:58:22.698568 [Byte1]: 55
1047 13:58:22.703509
1048 13:58:22.703695 Set Vref, RX VrefLevel [Byte0]: 56
1049 13:58:22.706583 [Byte1]: 56
1050 13:58:22.710737
1051 13:58:22.710934 Set Vref, RX VrefLevel [Byte0]: 57
1052 13:58:22.713785 [Byte1]: 57
1053 13:58:22.719165
1054 13:58:22.719640 Set Vref, RX VrefLevel [Byte0]: 58
1055 13:58:22.722154 [Byte1]: 58
1056 13:58:22.726691
1057 13:58:22.727203 Set Vref, RX VrefLevel [Byte0]: 59
1058 13:58:22.729880 [Byte1]: 59
1059 13:58:22.734224
1060 13:58:22.734733 Set Vref, RX VrefLevel [Byte0]: 60
1061 13:58:22.737637 [Byte1]: 60
1062 13:58:22.741822
1063 13:58:22.742334 Set Vref, RX VrefLevel [Byte0]: 61
1064 13:58:22.745220 [Byte1]: 61
1065 13:58:22.749132
1066 13:58:22.749635 Set Vref, RX VrefLevel [Byte0]: 62
1067 13:58:22.752780 [Byte1]: 62
1068 13:58:22.757110
1069 13:58:22.757673 Set Vref, RX VrefLevel [Byte0]: 63
1070 13:58:22.760447 [Byte1]: 63
1071 13:58:22.764616
1072 13:58:22.765163 Set Vref, RX VrefLevel [Byte0]: 64
1073 13:58:22.767705 [Byte1]: 64
1074 13:58:22.772228
1075 13:58:22.772729 Set Vref, RX VrefLevel [Byte0]: 65
1076 13:58:22.776565 [Byte1]: 65
1077 13:58:22.780039
1078 13:58:22.780584 Set Vref, RX VrefLevel [Byte0]: 66
1079 13:58:22.783560 [Byte1]: 66
1080 13:58:22.787648
1081 13:58:22.788211 Set Vref, RX VrefLevel [Byte0]: 67
1082 13:58:22.790855 [Byte1]: 67
1083 13:58:22.795193
1084 13:58:22.795707 Set Vref, RX VrefLevel [Byte0]: 68
1085 13:58:22.798467 [Byte1]: 68
1086 13:58:22.802701
1087 13:58:22.803117 Set Vref, RX VrefLevel [Byte0]: 69
1088 13:58:22.805758 [Byte1]: 69
1089 13:58:22.810653
1090 13:58:22.811158 Set Vref, RX VrefLevel [Byte0]: 70
1091 13:58:22.813818 [Byte1]: 70
1092 13:58:22.817862
1093 13:58:22.818277 Set Vref, RX VrefLevel [Byte0]: 71
1094 13:58:22.821590 [Byte1]: 71
1095 13:58:22.825527
1096 13:58:22.825967 Set Vref, RX VrefLevel [Byte0]: 72
1097 13:58:22.828845 [Byte1]: 72
1098 13:58:22.833349
1099 13:58:22.833767 Set Vref, RX VrefLevel [Byte0]: 73
1100 13:58:22.836619 [Byte1]: 73
1101 13:58:22.840831
1102 13:58:22.841249 Set Vref, RX VrefLevel [Byte0]: 74
1103 13:58:22.844302 [Byte1]: 74
1104 13:58:22.848513
1105 13:58:22.848929 Set Vref, RX VrefLevel [Byte0]: 75
1106 13:58:22.851980 [Byte1]: 75
1107 13:58:22.855783
1108 13:58:22.856348 Final RX Vref Byte 0 = 56 to rank0
1109 13:58:22.859410 Final RX Vref Byte 1 = 57 to rank0
1110 13:58:22.862410 Final RX Vref Byte 0 = 56 to rank1
1111 13:58:22.866467 Final RX Vref Byte 1 = 57 to rank1==
1112 13:58:22.869209 Dram Type= 6, Freq= 0, CH_0, rank 0
1113 13:58:22.876016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1114 13:58:22.876432 ==
1115 13:58:22.876759 DQS Delay:
1116 13:58:22.877065 DQS0 = 0, DQS1 = 0
1117 13:58:22.879334 DQM Delay:
1118 13:58:22.879741 DQM0 = 88, DQM1 = 75
1119 13:58:22.883087 DQ Delay:
1120 13:58:22.886102 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1121 13:58:22.886568 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1122 13:58:22.889434 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1123 13:58:22.893038 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1124 13:58:22.895899
1125 13:58:22.896426
1126 13:58:22.902807 [DQSOSCAuto] RK0, (LSB)MR18= 0x3831, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
1127 13:58:22.906018 CH0 RK0: MR19=606, MR18=3831
1128 13:58:22.912648 CH0_RK0: MR19=0x606, MR18=0x3831, DQSOSC=395, MR23=63, INC=94, DEC=63
1129 13:58:22.913059
1130 13:58:22.916111 ----->DramcWriteLeveling(PI) begin...
1131 13:58:22.916570 ==
1132 13:58:22.919659 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 13:58:22.922493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 13:58:22.923096 ==
1135 13:58:22.925835 Write leveling (Byte 0): 32 => 32
1136 13:58:22.929674 Write leveling (Byte 1): 26 => 26
1137 13:58:22.932372 DramcWriteLeveling(PI) end<-----
1138 13:58:22.933076
1139 13:58:22.933540 ==
1140 13:58:22.935822 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 13:58:22.938929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 13:58:22.939363 ==
1143 13:58:22.942568 [Gating] SW mode calibration
1144 13:58:22.949647 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1145 13:58:22.955786 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1146 13:58:23.000049 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1147 13:58:23.001044 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1148 13:58:23.001668 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 13:58:23.002200 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 13:58:23.002643 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 13:58:23.003021 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 13:58:23.003457 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:58:23.003935 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:58:23.004421 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:58:23.004772 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:58:23.020923 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:58:23.021791 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:58:23.022164 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:58:23.022485 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:58:23.024840 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:58:23.028463 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:58:23.032278 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1163 13:58:23.034213 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1164 13:58:23.037739 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1165 13:58:23.044834 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:58:23.047941 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:58:23.051243 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:58:23.057619 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:58:23.061448 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:58:23.064303 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:58:23.067860 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1172 13:58:23.074662 0 9 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
1173 13:58:23.078064 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1174 13:58:23.081272 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 13:58:23.087623 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 13:58:23.090706 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 13:58:23.094081 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 13:58:23.100926 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 13:58:23.104224 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1180 13:58:23.107854 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (0 1) (0 0)
1181 13:58:23.113912 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:58:23.117346 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:58:23.120462 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:58:23.127839 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:58:23.130397 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:58:23.133687 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:58:23.140946 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1188 13:58:23.144737 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
1189 13:58:23.148587 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 13:58:23.152342 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 13:58:23.155826 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 13:58:23.162295 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 13:58:23.166035 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 13:58:23.169480 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 13:58:23.172923 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 13:58:23.179720 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1197 13:58:23.182811 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 13:58:23.186675 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 13:58:23.192758 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:58:23.196870 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:58:23.199084 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:58:23.206720 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:58:23.209432 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:58:23.213404 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:58:23.219289 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:58:23.222995 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:58:23.226431 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:58:23.232614 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:58:23.236798 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:58:23.239727 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:58:23.245973 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:58:23.249791 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1213 13:58:23.253412 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 13:58:23.256637 Total UI for P1: 0, mck2ui 16
1215 13:58:23.259686 best dqsien dly found for B0: ( 0, 14, 8)
1216 13:58:23.262777 Total UI for P1: 0, mck2ui 16
1217 13:58:23.267188 best dqsien dly found for B1: ( 0, 14, 8)
1218 13:58:23.270061 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1219 13:58:23.273526 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1220 13:58:23.273743
1221 13:58:23.278179 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1222 13:58:23.279724 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1223 13:58:23.282776 [Gating] SW calibration Done
1224 13:58:23.283043 ==
1225 13:58:23.286322 Dram Type= 6, Freq= 0, CH_0, rank 1
1226 13:58:23.292694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1227 13:58:23.293098 ==
1228 13:58:23.293455 RX Vref Scan: 0
1229 13:58:23.293720
1230 13:58:23.296195 RX Vref 0 -> 0, step: 1
1231 13:58:23.296436
1232 13:58:23.299434 RX Delay -130 -> 252, step: 16
1233 13:58:23.303100 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1234 13:58:23.306344 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1235 13:58:23.309962 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1236 13:58:23.316629 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1237 13:58:23.319649 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1238 13:58:23.323307 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1239 13:58:23.326122 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1240 13:58:23.329858 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1241 13:58:23.336035 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1242 13:58:23.340109 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1243 13:58:23.342818 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1244 13:58:23.346599 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1245 13:58:23.349546 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1246 13:58:23.356652 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1247 13:58:23.359521 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1248 13:58:23.363057 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1249 13:58:23.363616 ==
1250 13:58:23.366242 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 13:58:23.369736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1252 13:58:23.370290 ==
1253 13:58:23.372642 DQS Delay:
1254 13:58:23.373103 DQS0 = 0, DQS1 = 0
1255 13:58:23.375987 DQM Delay:
1256 13:58:23.376546 DQM0 = 85, DQM1 = 76
1257 13:58:23.376920 DQ Delay:
1258 13:58:23.379303 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1259 13:58:23.382801 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1260 13:58:23.386143 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1261 13:58:23.389732 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1262 13:58:23.390241
1263 13:58:23.390576
1264 13:58:23.392454 ==
1265 13:58:23.396026 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 13:58:23.399475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 13:58:23.399969 ==
1268 13:58:23.400422
1269 13:58:23.400747
1270 13:58:23.402827 TX Vref Scan disable
1271 13:58:23.403247 == TX Byte 0 ==
1272 13:58:23.406902 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1273 13:58:23.412626 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1274 13:58:23.413139 == TX Byte 1 ==
1275 13:58:23.416580 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1276 13:58:23.422624 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1277 13:58:23.423180 ==
1278 13:58:23.425756 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 13:58:23.429132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1280 13:58:23.429597 ==
1281 13:58:23.443362 TX Vref=22, minBit 1, minWin=27, winSum=440
1282 13:58:23.447288 TX Vref=24, minBit 1, minWin=27, winSum=447
1283 13:58:23.450230 TX Vref=26, minBit 1, minWin=27, winSum=448
1284 13:58:23.453724 TX Vref=28, minBit 2, minWin=27, winSum=449
1285 13:58:23.456699 TX Vref=30, minBit 0, minWin=28, winSum=451
1286 13:58:23.460072 TX Vref=32, minBit 4, minWin=27, winSum=450
1287 13:58:23.466658 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
1288 13:58:23.467215
1289 13:58:23.469958 Final TX Range 1 Vref 30
1290 13:58:23.470512
1291 13:58:23.470883 ==
1292 13:58:23.473290 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 13:58:23.476305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 13:58:23.476767 ==
1295 13:58:23.477131
1296 13:58:23.477470
1297 13:58:23.479654 TX Vref Scan disable
1298 13:58:23.483142 == TX Byte 0 ==
1299 13:58:23.486151 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1300 13:58:23.489967 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1301 13:58:23.492954 == TX Byte 1 ==
1302 13:58:23.496427 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1303 13:58:23.499465 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1304 13:58:23.503097
1305 13:58:23.503602 [DATLAT]
1306 13:58:23.503960 Freq=800, CH0 RK1
1307 13:58:23.504280
1308 13:58:23.506267 DATLAT Default: 0xa
1309 13:58:23.506683 0, 0xFFFF, sum = 0
1310 13:58:23.509742 1, 0xFFFF, sum = 0
1311 13:58:23.510326 2, 0xFFFF, sum = 0
1312 13:58:23.512820 3, 0xFFFF, sum = 0
1313 13:58:23.513248 4, 0xFFFF, sum = 0
1314 13:58:23.516813 5, 0xFFFF, sum = 0
1315 13:58:23.519973 6, 0xFFFF, sum = 0
1316 13:58:23.520405 7, 0xFFFF, sum = 0
1317 13:58:23.523464 8, 0xFFFF, sum = 0
1318 13:58:23.523886 9, 0x0, sum = 1
1319 13:58:23.524271 10, 0x0, sum = 2
1320 13:58:23.526460 11, 0x0, sum = 3
1321 13:58:23.527042 12, 0x0, sum = 4
1322 13:58:23.529701 best_step = 10
1323 13:58:23.530117
1324 13:58:23.530448 ==
1325 13:58:23.533202 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 13:58:23.536560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 13:58:23.537079 ==
1328 13:58:23.539699 RX Vref Scan: 0
1329 13:58:23.540198
1330 13:58:23.540536 RX Vref 0 -> 0, step: 1
1331 13:58:23.540849
1332 13:58:23.543009 RX Delay -95 -> 252, step: 8
1333 13:58:23.550197 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1334 13:58:23.553449 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1335 13:58:23.556709 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1336 13:58:23.560029 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1337 13:58:23.563705 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1338 13:58:23.570356 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1339 13:58:23.573404 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1340 13:58:23.576667 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1341 13:58:23.579604 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1342 13:58:23.582720 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1343 13:58:23.589192 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1344 13:58:23.592715 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1345 13:58:23.595728 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1346 13:58:23.599125 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1347 13:58:23.605692 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1348 13:58:23.609500 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1349 13:58:23.609917 ==
1350 13:58:23.612722 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 13:58:23.615740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 13:58:23.616194 ==
1353 13:58:23.616531 DQS Delay:
1354 13:58:23.619133 DQS0 = 0, DQS1 = 0
1355 13:58:23.619844 DQM Delay:
1356 13:58:23.622596 DQM0 = 86, DQM1 = 76
1357 13:58:23.623008 DQ Delay:
1358 13:58:23.625651 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1359 13:58:23.629215 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1360 13:58:23.632203 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1361 13:58:23.636170 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1362 13:58:23.636578
1363 13:58:23.636899
1364 13:58:23.645983 [DQSOSCAuto] RK1, (LSB)MR18= 0x2825, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1365 13:58:23.646395 CH0 RK1: MR19=606, MR18=2825
1366 13:58:23.652678 CH0_RK1: MR19=0x606, MR18=0x2825, DQSOSC=399, MR23=63, INC=92, DEC=61
1367 13:58:23.655452 [RxdqsGatingPostProcess] freq 800
1368 13:58:23.661957 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1369 13:58:23.665623 Pre-setting of DQS Precalculation
1370 13:58:23.668414 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1371 13:58:23.668496 ==
1372 13:58:23.672323 Dram Type= 6, Freq= 0, CH_1, rank 0
1373 13:58:23.675515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 13:58:23.678648 ==
1375 13:58:23.681998 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1376 13:58:23.688407 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1377 13:58:23.697715 [CA 0] Center 36 (6~67) winsize 62
1378 13:58:23.700613 [CA 1] Center 37 (6~68) winsize 63
1379 13:58:23.704364 [CA 2] Center 35 (5~65) winsize 61
1380 13:58:23.707856 [CA 3] Center 34 (4~65) winsize 62
1381 13:58:23.710599 [CA 4] Center 34 (4~65) winsize 62
1382 13:58:23.714824 [CA 5] Center 34 (3~65) winsize 63
1383 13:58:23.714905
1384 13:58:23.717360 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1385 13:58:23.717439
1386 13:58:23.720694 [CATrainingPosCal] consider 1 rank data
1387 13:58:23.724103 u2DelayCellTimex100 = 270/100 ps
1388 13:58:23.727457 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1389 13:58:23.730979 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1390 13:58:23.737624 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1391 13:58:23.740975 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1392 13:58:23.743815 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1393 13:58:23.747660 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1394 13:58:23.747791
1395 13:58:23.750923 CA PerBit enable=1, Macro0, CA PI delay=34
1396 13:58:23.751045
1397 13:58:23.753730 [CBTSetCACLKResult] CA Dly = 34
1398 13:58:23.753884 CS Dly: 4 (0~35)
1399 13:58:23.757653 ==
1400 13:58:23.761225 Dram Type= 6, Freq= 0, CH_1, rank 1
1401 13:58:23.763537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 13:58:23.763673 ==
1403 13:58:23.767637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1404 13:58:23.773815 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1405 13:58:23.783733 [CA 0] Center 36 (6~67) winsize 62
1406 13:58:23.786836 [CA 1] Center 36 (6~67) winsize 62
1407 13:58:23.790527 [CA 2] Center 34 (4~65) winsize 62
1408 13:58:23.793639 [CA 3] Center 34 (3~65) winsize 63
1409 13:58:23.797222 [CA 4] Center 34 (3~65) winsize 63
1410 13:58:23.800517 [CA 5] Center 34 (3~65) winsize 63
1411 13:58:23.800869
1412 13:58:23.804249 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1413 13:58:23.804649
1414 13:58:23.808605 [CATrainingPosCal] consider 2 rank data
1415 13:58:23.811549 u2DelayCellTimex100 = 270/100 ps
1416 13:58:23.815027 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1417 13:58:23.818632 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1418 13:58:23.823360 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1419 13:58:23.826031 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1420 13:58:23.830225 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1421 13:58:23.833966 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1422 13:58:23.834387
1423 13:58:23.837700 CA PerBit enable=1, Macro0, CA PI delay=34
1424 13:58:23.838120
1425 13:58:23.840730 [CBTSetCACLKResult] CA Dly = 34
1426 13:58:23.841150 CS Dly: 5 (0~37)
1427 13:58:23.841548
1428 13:58:23.844976 ----->DramcWriteLeveling(PI) begin...
1429 13:58:23.845435 ==
1430 13:58:23.847445 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 13:58:23.854035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 13:58:23.854463 ==
1433 13:58:23.857378 Write leveling (Byte 0): 28 => 28
1434 13:58:23.860648 Write leveling (Byte 1): 30 => 30
1435 13:58:23.861170 DramcWriteLeveling(PI) end<-----
1436 13:58:23.864190
1437 13:58:23.864610 ==
1438 13:58:23.867419 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 13:58:23.870908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 13:58:23.871479 ==
1441 13:58:23.873945 [Gating] SW mode calibration
1442 13:58:23.880478 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1443 13:58:23.884099 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1444 13:58:23.890493 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1445 13:58:23.894067 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1446 13:58:23.897993 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1447 13:58:23.903796 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 13:58:23.907200 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 13:58:23.910398 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 13:58:23.917442 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:58:23.920548 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:58:23.924553 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:58:23.931175 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:58:23.934314 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:58:23.937147 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:58:23.944313 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:58:23.947513 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:58:23.950928 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:58:23.957393 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:58:23.960284 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1461 13:58:23.964006 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1462 13:58:23.970278 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1463 13:58:23.974116 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:58:23.977455 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:58:23.984137 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:58:23.987238 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:58:23.990430 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:58:23.993709 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:58:24.000354 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1470 13:58:24.003264 0 9 8 | B1->B0 | 2e2e 3333 | 1 1 | (1 1) (1 1)
1471 13:58:24.007334 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 13:58:24.013630 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 13:58:24.017650 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 13:58:24.020582 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 13:58:24.027165 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 13:58:24.030283 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 13:58:24.033237 0 10 4 | B1->B0 | 3232 3030 | 1 0 | (0 1) (0 0)
1478 13:58:24.040054 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
1479 13:58:24.043452 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 13:58:24.046918 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:58:24.053416 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:58:24.057188 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 13:58:24.059773 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:58:24.066799 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:58:24.069966 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1486 13:58:24.073412 0 11 8 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
1487 13:58:24.079977 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 13:58:24.083650 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 13:58:24.086846 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 13:58:24.093561 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 13:58:24.096500 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 13:58:24.100006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 13:58:24.106195 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1494 13:58:24.109641 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 13:58:24.113331 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 13:58:24.119944 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 13:58:24.123215 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 13:58:24.125901 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:58:24.133214 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:58:24.136321 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:58:24.139891 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:58:24.145933 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:58:24.149341 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:58:24.152592 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:58:24.159471 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:58:24.163318 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:58:24.165983 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:58:24.173071 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:58:24.175954 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1510 13:58:24.178934 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 13:58:24.182148 Total UI for P1: 0, mck2ui 16
1512 13:58:24.185464 best dqsien dly found for B0: ( 0, 14, 4)
1513 13:58:24.188932 Total UI for P1: 0, mck2ui 16
1514 13:58:24.192005 best dqsien dly found for B1: ( 0, 14, 6)
1515 13:58:24.195887 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1516 13:58:24.199030 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1517 13:58:24.199448
1518 13:58:24.202042 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1519 13:58:24.209179 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1520 13:58:24.209702 [Gating] SW calibration Done
1521 13:58:24.210039 ==
1522 13:58:24.212882 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 13:58:24.218895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1524 13:58:24.219445 ==
1525 13:58:24.219811 RX Vref Scan: 0
1526 13:58:24.220198
1527 13:58:24.222058 RX Vref 0 -> 0, step: 1
1528 13:58:24.222709
1529 13:58:24.225558 RX Delay -130 -> 252, step: 16
1530 13:58:24.228949 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1531 13:58:24.232296 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1532 13:58:24.235446 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1533 13:58:24.241772 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1534 13:58:24.245159 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1535 13:58:24.248691 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1536 13:58:24.252294 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1537 13:58:24.256020 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1538 13:58:24.262104 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1539 13:58:24.266441 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1540 13:58:24.268525 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1541 13:58:24.272005 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1542 13:58:24.275570 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1543 13:58:24.282622 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1544 13:58:24.285739 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1545 13:58:24.288478 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1546 13:58:24.288992 ==
1547 13:58:24.292384 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 13:58:24.295987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1549 13:58:24.298836 ==
1550 13:58:24.299408 DQS Delay:
1551 13:58:24.299774 DQS0 = 0, DQS1 = 0
1552 13:58:24.302524 DQM Delay:
1553 13:58:24.302979 DQM0 = 86, DQM1 = 78
1554 13:58:24.305452 DQ Delay:
1555 13:58:24.305915 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1556 13:58:24.308603 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =77
1557 13:58:24.311588 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1558 13:58:24.314912 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1559 13:58:24.319014
1560 13:58:24.319518
1561 13:58:24.319849 ==
1562 13:58:24.321508 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 13:58:24.325091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 13:58:24.325544 ==
1565 13:58:24.325872
1566 13:58:24.326259
1567 13:58:24.328512 TX Vref Scan disable
1568 13:58:24.328924 == TX Byte 0 ==
1569 13:58:24.335594 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1570 13:58:24.338193 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1571 13:58:24.338607 == TX Byte 1 ==
1572 13:58:24.345302 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1573 13:58:24.348409 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1574 13:58:24.348827 ==
1575 13:58:24.351937 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 13:58:24.354927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 13:58:24.355459 ==
1578 13:58:24.368589 TX Vref=22, minBit 1, minWin=27, winSum=442
1579 13:58:24.371867 TX Vref=24, minBit 1, minWin=27, winSum=444
1580 13:58:24.375046 TX Vref=26, minBit 5, minWin=27, winSum=452
1581 13:58:24.378410 TX Vref=28, minBit 3, minWin=27, winSum=453
1582 13:58:24.382331 TX Vref=30, minBit 1, minWin=27, winSum=452
1583 13:58:24.386242 TX Vref=32, minBit 1, minWin=27, winSum=449
1584 13:58:24.393215 [TxChooseVref] Worse bit 3, Min win 27, Win sum 453, Final Vref 28
1585 13:58:24.393691
1586 13:58:24.396042 Final TX Range 1 Vref 28
1587 13:58:24.396457
1588 13:58:24.396780 ==
1589 13:58:24.399242 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 13:58:24.402412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 13:58:24.402847 ==
1592 13:58:24.403185
1593 13:58:24.403563
1594 13:58:24.406117 TX Vref Scan disable
1595 13:58:24.409266 == TX Byte 0 ==
1596 13:58:24.412974 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1597 13:58:24.416546 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1598 13:58:24.419565 == TX Byte 1 ==
1599 13:58:24.422712 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1600 13:58:24.425712 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1601 13:58:24.426133
1602 13:58:24.429323 [DATLAT]
1603 13:58:24.429737 Freq=800, CH1 RK0
1604 13:58:24.430069
1605 13:58:24.432957 DATLAT Default: 0xa
1606 13:58:24.433374 0, 0xFFFF, sum = 0
1607 13:58:24.435669 1, 0xFFFF, sum = 0
1608 13:58:24.436135 2, 0xFFFF, sum = 0
1609 13:58:24.439362 3, 0xFFFF, sum = 0
1610 13:58:24.439886 4, 0xFFFF, sum = 0
1611 13:58:24.442906 5, 0xFFFF, sum = 0
1612 13:58:24.443434 6, 0xFFFF, sum = 0
1613 13:58:24.445828 7, 0xFFFF, sum = 0
1614 13:58:24.446351 8, 0xFFFF, sum = 0
1615 13:58:24.449689 9, 0x0, sum = 1
1616 13:58:24.450217 10, 0x0, sum = 2
1617 13:58:24.452720 11, 0x0, sum = 3
1618 13:58:24.453148 12, 0x0, sum = 4
1619 13:58:24.455955 best_step = 10
1620 13:58:24.456378
1621 13:58:24.456709 ==
1622 13:58:24.459386 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 13:58:24.462912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 13:58:24.463437 ==
1625 13:58:24.465773 RX Vref Scan: 1
1626 13:58:24.466294
1627 13:58:24.466635 Set Vref Range= 32 -> 127
1628 13:58:24.466947
1629 13:58:24.469081 RX Vref 32 -> 127, step: 1
1630 13:58:24.469804
1631 13:58:24.472506 RX Delay -95 -> 252, step: 8
1632 13:58:24.472929
1633 13:58:24.475749 Set Vref, RX VrefLevel [Byte0]: 32
1634 13:58:24.479580 [Byte1]: 32
1635 13:58:24.480126
1636 13:58:24.482159 Set Vref, RX VrefLevel [Byte0]: 33
1637 13:58:24.485807 [Byte1]: 33
1638 13:58:24.489450
1639 13:58:24.489970 Set Vref, RX VrefLevel [Byte0]: 34
1640 13:58:24.492475 [Byte1]: 34
1641 13:58:24.496508
1642 13:58:24.496920 Set Vref, RX VrefLevel [Byte0]: 35
1643 13:58:24.499880 [Byte1]: 35
1644 13:58:24.503791
1645 13:58:24.504285 Set Vref, RX VrefLevel [Byte0]: 36
1646 13:58:24.508200 [Byte1]: 36
1647 13:58:24.512067
1648 13:58:24.512629 Set Vref, RX VrefLevel [Byte0]: 37
1649 13:58:24.515356 [Byte1]: 37
1650 13:58:24.519360
1651 13:58:24.519810 Set Vref, RX VrefLevel [Byte0]: 38
1652 13:58:24.522730 [Byte1]: 38
1653 13:58:24.527142
1654 13:58:24.527590 Set Vref, RX VrefLevel [Byte0]: 39
1655 13:58:24.530605 [Byte1]: 39
1656 13:58:24.535064
1657 13:58:24.535615 Set Vref, RX VrefLevel [Byte0]: 40
1658 13:58:24.538168 [Byte1]: 40
1659 13:58:24.542215
1660 13:58:24.542776 Set Vref, RX VrefLevel [Byte0]: 41
1661 13:58:24.545420 [Byte1]: 41
1662 13:58:24.550039
1663 13:58:24.550600 Set Vref, RX VrefLevel [Byte0]: 42
1664 13:58:24.552892 [Byte1]: 42
1665 13:58:24.557376
1666 13:58:24.557798 Set Vref, RX VrefLevel [Byte0]: 43
1667 13:58:24.560706 [Byte1]: 43
1668 13:58:24.565467
1669 13:58:24.565884 Set Vref, RX VrefLevel [Byte0]: 44
1670 13:58:24.568133 [Byte1]: 44
1671 13:58:24.572393
1672 13:58:24.572812 Set Vref, RX VrefLevel [Byte0]: 45
1673 13:58:24.575750 [Byte1]: 45
1674 13:58:24.580448
1675 13:58:24.580965 Set Vref, RX VrefLevel [Byte0]: 46
1676 13:58:24.583688 [Byte1]: 46
1677 13:58:24.588366
1678 13:58:24.588886 Set Vref, RX VrefLevel [Byte0]: 47
1679 13:58:24.590855 [Byte1]: 47
1680 13:58:24.595055
1681 13:58:24.595470 Set Vref, RX VrefLevel [Byte0]: 48
1682 13:58:24.598370 [Byte1]: 48
1683 13:58:24.602496
1684 13:58:24.603102 Set Vref, RX VrefLevel [Byte0]: 49
1685 13:58:24.606275 [Byte1]: 49
1686 13:58:24.610960
1687 13:58:24.611379 Set Vref, RX VrefLevel [Byte0]: 50
1688 13:58:24.613623 [Byte1]: 50
1689 13:58:24.618559
1690 13:58:24.619207 Set Vref, RX VrefLevel [Byte0]: 51
1691 13:58:24.621689 [Byte1]: 51
1692 13:58:24.625400
1693 13:58:24.625814 Set Vref, RX VrefLevel [Byte0]: 52
1694 13:58:24.629247 [Byte1]: 52
1695 13:58:24.633471
1696 13:58:24.633978 Set Vref, RX VrefLevel [Byte0]: 53
1697 13:58:24.637247 [Byte1]: 53
1698 13:58:24.640777
1699 13:58:24.641213 Set Vref, RX VrefLevel [Byte0]: 54
1700 13:58:24.643847 [Byte1]: 54
1701 13:58:24.648519
1702 13:58:24.649007 Set Vref, RX VrefLevel [Byte0]: 55
1703 13:58:24.652338 [Byte1]: 55
1704 13:58:24.655984
1705 13:58:24.656406 Set Vref, RX VrefLevel [Byte0]: 56
1706 13:58:24.659835 [Byte1]: 56
1707 13:58:24.664191
1708 13:58:24.664714 Set Vref, RX VrefLevel [Byte0]: 57
1709 13:58:24.667500 [Byte1]: 57
1710 13:58:24.671437
1711 13:58:24.672040 Set Vref, RX VrefLevel [Byte0]: 58
1712 13:58:24.674640 [Byte1]: 58
1713 13:58:24.679601
1714 13:58:24.680224 Set Vref, RX VrefLevel [Byte0]: 59
1715 13:58:24.682380 [Byte1]: 59
1716 13:58:24.686849
1717 13:58:24.687369 Set Vref, RX VrefLevel [Byte0]: 60
1718 13:58:24.689963 [Byte1]: 60
1719 13:58:24.694191
1720 13:58:24.694739 Set Vref, RX VrefLevel [Byte0]: 61
1721 13:58:24.697795 [Byte1]: 61
1722 13:58:24.701586
1723 13:58:24.702020 Set Vref, RX VrefLevel [Byte0]: 62
1724 13:58:24.704741 [Byte1]: 62
1725 13:58:24.709343
1726 13:58:24.709865 Set Vref, RX VrefLevel [Byte0]: 63
1727 13:58:24.712406 [Byte1]: 63
1728 13:58:24.716906
1729 13:58:24.717429 Set Vref, RX VrefLevel [Byte0]: 64
1730 13:58:24.720605 [Byte1]: 64
1731 13:58:24.724196
1732 13:58:24.724620 Set Vref, RX VrefLevel [Byte0]: 65
1733 13:58:24.727709 [Byte1]: 65
1734 13:58:24.731976
1735 13:58:24.732397 Set Vref, RX VrefLevel [Byte0]: 66
1736 13:58:24.735694 [Byte1]: 66
1737 13:58:24.739627
1738 13:58:24.740081 Set Vref, RX VrefLevel [Byte0]: 67
1739 13:58:24.743179 [Byte1]: 67
1740 13:58:24.747055
1741 13:58:24.747542 Set Vref, RX VrefLevel [Byte0]: 68
1742 13:58:24.750488 [Byte1]: 68
1743 13:58:24.754740
1744 13:58:24.755149 Set Vref, RX VrefLevel [Byte0]: 69
1745 13:58:24.758331 [Byte1]: 69
1746 13:58:24.762629
1747 13:58:24.763146 Set Vref, RX VrefLevel [Byte0]: 70
1748 13:58:24.765597 [Byte1]: 70
1749 13:58:24.770127
1750 13:58:24.770638 Set Vref, RX VrefLevel [Byte0]: 71
1751 13:58:24.773812 [Byte1]: 71
1752 13:58:24.777857
1753 13:58:24.778411 Set Vref, RX VrefLevel [Byte0]: 72
1754 13:58:24.781852 [Byte1]: 72
1755 13:58:24.785761
1756 13:58:24.786296 Set Vref, RX VrefLevel [Byte0]: 73
1757 13:58:24.788867 [Byte1]: 73
1758 13:58:24.792775
1759 13:58:24.793325 Set Vref, RX VrefLevel [Byte0]: 74
1760 13:58:24.796039 [Byte1]: 74
1761 13:58:24.800660
1762 13:58:24.801204 Set Vref, RX VrefLevel [Byte0]: 75
1763 13:58:24.803878 [Byte1]: 75
1764 13:58:24.808253
1765 13:58:24.808817 Final RX Vref Byte 0 = 55 to rank0
1766 13:58:24.811819 Final RX Vref Byte 1 = 52 to rank0
1767 13:58:24.814694 Final RX Vref Byte 0 = 55 to rank1
1768 13:58:24.818055 Final RX Vref Byte 1 = 52 to rank1==
1769 13:58:24.821291 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 13:58:24.827975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 13:58:24.828404 ==
1772 13:58:24.828742 DQS Delay:
1773 13:58:24.829054 DQS0 = 0, DQS1 = 0
1774 13:58:24.831094 DQM Delay:
1775 13:58:24.831510 DQM0 = 85, DQM1 = 80
1776 13:58:24.834610 DQ Delay:
1777 13:58:24.838304 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1778 13:58:24.841284 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1779 13:58:24.841808 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =76
1780 13:58:24.847778 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1781 13:58:24.848306
1782 13:58:24.848642
1783 13:58:24.854637 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e31, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1784 13:58:24.857787 CH1 RK0: MR19=606, MR18=1E31
1785 13:58:24.864213 CH1_RK0: MR19=0x606, MR18=0x1E31, DQSOSC=397, MR23=63, INC=93, DEC=62
1786 13:58:24.864636
1787 13:58:24.867873 ----->DramcWriteLeveling(PI) begin...
1788 13:58:24.868455 ==
1789 13:58:24.871459 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 13:58:24.874892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 13:58:24.875414 ==
1792 13:58:24.877626 Write leveling (Byte 0): 26 => 26
1793 13:58:24.881259 Write leveling (Byte 1): 27 => 27
1794 13:58:24.884617 DramcWriteLeveling(PI) end<-----
1795 13:58:24.885038
1796 13:58:24.885368 ==
1797 13:58:24.887901 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 13:58:24.891308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 13:58:24.891833 ==
1800 13:58:24.895156 [Gating] SW mode calibration
1801 13:58:24.901166 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 13:58:24.907762 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 13:58:24.911022 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1804 13:58:24.914227 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1805 13:58:24.920728 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 13:58:24.924027 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 13:58:24.927567 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 13:58:24.934092 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 13:58:24.937582 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 13:58:24.940903 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 13:58:24.947470 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:58:24.950566 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:58:24.954180 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:58:24.960734 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:58:24.964120 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:58:24.967464 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:58:24.973942 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:58:24.977410 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:58:24.980618 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1820 13:58:24.987200 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1821 13:58:24.990269 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:58:24.993489 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:58:25.000694 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:58:25.004356 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:58:25.007714 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:58:25.013800 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:58:25.017318 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:58:25.020745 0 9 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1829 13:58:25.027560 0 9 8 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
1830 13:58:25.030603 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 13:58:25.033621 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 13:58:25.040691 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 13:58:25.043635 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 13:58:25.047388 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 13:58:25.050369 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 13:58:25.057083 0 10 4 | B1->B0 | 3333 2727 | 0 0 | (1 0) (0 0)
1837 13:58:25.060948 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1838 13:58:25.064042 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:58:25.070525 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:58:25.073863 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:58:25.077128 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:58:25.083761 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:58:25.087259 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 13:58:25.090910 0 11 4 | B1->B0 | 2a2a 3b3b | 0 1 | (0 0) (0 0)
1845 13:58:25.097025 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1846 13:58:25.100321 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 13:58:25.103571 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 13:58:25.110337 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 13:58:25.113797 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 13:58:25.117337 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 13:58:25.124092 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 13:58:25.126945 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1853 13:58:25.130348 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1854 13:58:25.136763 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 13:58:25.139952 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 13:58:25.144054 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 13:58:25.150115 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 13:58:25.153719 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 13:58:25.156408 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 13:58:25.163667 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 13:58:25.166932 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:58:25.169894 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:58:25.176453 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:58:25.179556 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:58:25.183771 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:58:25.189577 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:58:25.192921 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1868 13:58:25.196622 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1869 13:58:25.199733 Total UI for P1: 0, mck2ui 16
1870 13:58:25.203197 best dqsien dly found for B0: ( 0, 14, 0)
1871 13:58:25.209551 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 13:58:25.210117 Total UI for P1: 0, mck2ui 16
1873 13:58:25.212504 best dqsien dly found for B1: ( 0, 14, 4)
1874 13:58:25.219280 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1875 13:58:25.223007 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1876 13:58:25.223569
1877 13:58:25.225978 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1878 13:58:25.229191 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1879 13:58:25.232499 [Gating] SW calibration Done
1880 13:58:25.232960 ==
1881 13:58:25.236192 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 13:58:25.239554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 13:58:25.240170 ==
1884 13:58:25.242664 RX Vref Scan: 0
1885 13:58:25.243223
1886 13:58:25.243590 RX Vref 0 -> 0, step: 1
1887 13:58:25.243981
1888 13:58:25.245809 RX Delay -130 -> 252, step: 16
1889 13:58:25.249308 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1890 13:58:25.255434 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1891 13:58:25.259204 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1892 13:58:25.262056 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1893 13:58:25.265393 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1894 13:58:25.269067 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1895 13:58:25.275885 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1896 13:58:25.278896 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1897 13:58:25.282408 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1898 13:58:25.285040 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1899 13:58:25.288297 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1900 13:58:25.295227 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1901 13:58:25.298460 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1902 13:58:25.302158 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1903 13:58:25.305301 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1904 13:58:25.312044 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1905 13:58:25.312518 ==
1906 13:58:25.315153 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 13:58:25.318792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1908 13:58:25.319210 ==
1909 13:58:25.319537 DQS Delay:
1910 13:58:25.321692 DQS0 = 0, DQS1 = 0
1911 13:58:25.322104 DQM Delay:
1912 13:58:25.324904 DQM0 = 84, DQM1 = 82
1913 13:58:25.325311 DQ Delay:
1914 13:58:25.328411 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1915 13:58:25.331558 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1916 13:58:25.335027 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1917 13:58:25.338958 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1918 13:58:25.339586
1919 13:58:25.340130
1920 13:58:25.340456 ==
1921 13:58:25.342397 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 13:58:25.345401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 13:58:25.345918 ==
1924 13:58:25.346274
1925 13:58:25.348262
1926 13:58:25.348680 TX Vref Scan disable
1927 13:58:25.351255 == TX Byte 0 ==
1928 13:58:25.354690 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1929 13:58:25.357699 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1930 13:58:25.361528 == TX Byte 1 ==
1931 13:58:25.364639 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1932 13:58:25.368001 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1933 13:58:25.368422 ==
1934 13:58:25.371153 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 13:58:25.378443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 13:58:25.378973 ==
1937 13:58:25.390146 TX Vref=22, minBit 0, minWin=27, winSum=447
1938 13:58:25.393136 TX Vref=24, minBit 1, minWin=27, winSum=448
1939 13:58:25.396022 TX Vref=26, minBit 1, minWin=27, winSum=452
1940 13:58:25.400088 TX Vref=28, minBit 6, minWin=27, winSum=456
1941 13:58:25.402945 TX Vref=30, minBit 3, minWin=27, winSum=453
1942 13:58:25.410234 TX Vref=32, minBit 5, minWin=27, winSum=455
1943 13:58:25.412690 [TxChooseVref] Worse bit 6, Min win 27, Win sum 456, Final Vref 28
1944 13:58:25.413150
1945 13:58:25.416614 Final TX Range 1 Vref 28
1946 13:58:25.417192
1947 13:58:25.417566 ==
1948 13:58:25.419391 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 13:58:25.422858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 13:58:25.423318 ==
1951 13:58:25.426193
1952 13:58:25.426734
1953 13:58:25.427118 TX Vref Scan disable
1954 13:58:25.429412 == TX Byte 0 ==
1955 13:58:25.433227 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1956 13:58:25.439843 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1957 13:58:25.440410 == TX Byte 1 ==
1958 13:58:25.443286 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1959 13:58:25.449850 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1960 13:58:25.450358
1961 13:58:25.450685 [DATLAT]
1962 13:58:25.450990 Freq=800, CH1 RK1
1963 13:58:25.451285
1964 13:58:25.452432 DATLAT Default: 0xa
1965 13:58:25.452840 0, 0xFFFF, sum = 0
1966 13:58:25.456241 1, 0xFFFF, sum = 0
1967 13:58:25.456660 2, 0xFFFF, sum = 0
1968 13:58:25.459850 3, 0xFFFF, sum = 0
1969 13:58:25.463352 4, 0xFFFF, sum = 0
1970 13:58:25.463868 5, 0xFFFF, sum = 0
1971 13:58:25.466403 6, 0xFFFF, sum = 0
1972 13:58:25.466919 7, 0xFFFF, sum = 0
1973 13:58:25.469828 8, 0xFFFF, sum = 0
1974 13:58:25.470344 9, 0x0, sum = 1
1975 13:58:25.472663 10, 0x0, sum = 2
1976 13:58:25.473083 11, 0x0, sum = 3
1977 13:58:25.473417 12, 0x0, sum = 4
1978 13:58:25.476051 best_step = 10
1979 13:58:25.476464
1980 13:58:25.476787 ==
1981 13:58:25.479543 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 13:58:25.482914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 13:58:25.483424 ==
1984 13:58:25.486471 RX Vref Scan: 0
1985 13:58:25.486982
1986 13:58:25.487307 RX Vref 0 -> 0, step: 1
1987 13:58:25.489087
1988 13:58:25.489594 RX Delay -95 -> 252, step: 8
1989 13:58:25.496373 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1990 13:58:25.499269 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1991 13:58:25.502471 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1992 13:58:25.505951 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1993 13:58:25.509752 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1994 13:58:25.516590 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1995 13:58:25.519277 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1996 13:58:25.522734 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1997 13:58:25.525795 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1998 13:58:25.529387 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1999 13:58:25.536238 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2000 13:58:25.539688 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2001 13:58:25.542910 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2002 13:58:25.546676 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2003 13:58:25.552924 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2004 13:58:25.556070 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2005 13:58:25.556553 ==
2006 13:58:25.559871 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 13:58:25.563598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 13:58:25.564222 ==
2009 13:58:25.564721 DQS Delay:
2010 13:58:25.565839 DQS0 = 0, DQS1 = 0
2011 13:58:25.566313 DQM Delay:
2012 13:58:25.569318 DQM0 = 87, DQM1 = 81
2013 13:58:25.569884 DQ Delay:
2014 13:58:25.572866 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2015 13:58:25.576568 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2016 13:58:25.579329 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
2017 13:58:25.583090 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2018 13:58:25.583657
2019 13:58:25.584216
2020 13:58:25.593001 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 402 ps
2021 13:58:25.593625 CH1 RK1: MR19=606, MR18=1F3B
2022 13:58:25.599148 CH1_RK1: MR19=0x606, MR18=0x1F3B, DQSOSC=394, MR23=63, INC=95, DEC=63
2023 13:58:25.602388 [RxdqsGatingPostProcess] freq 800
2024 13:58:25.609173 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2025 13:58:25.612900 Pre-setting of DQS Precalculation
2026 13:58:25.616274 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2027 13:58:25.622331 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2028 13:58:25.632122 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2029 13:58:25.632563
2030 13:58:25.633002
2031 13:58:25.633418 [Calibration Summary] 1600 Mbps
2032 13:58:25.635674 CH 0, Rank 0
2033 13:58:25.636141 SW Impedance : PASS
2034 13:58:25.639002 DUTY Scan : NO K
2035 13:58:25.642337 ZQ Calibration : PASS
2036 13:58:25.642770 Jitter Meter : NO K
2037 13:58:25.645486 CBT Training : PASS
2038 13:58:25.649121 Write leveling : PASS
2039 13:58:25.649558 RX DQS gating : PASS
2040 13:58:25.652372 RX DQ/DQS(RDDQC) : PASS
2041 13:58:25.655780 TX DQ/DQS : PASS
2042 13:58:25.656247 RX DATLAT : PASS
2043 13:58:25.659109 RX DQ/DQS(Engine): PASS
2044 13:58:25.662263 TX OE : NO K
2045 13:58:25.662798 All Pass.
2046 13:58:25.663249
2047 13:58:25.663667 CH 0, Rank 1
2048 13:58:25.665318 SW Impedance : PASS
2049 13:58:25.669675 DUTY Scan : NO K
2050 13:58:25.670198 ZQ Calibration : PASS
2051 13:58:25.672474 Jitter Meter : NO K
2052 13:58:25.676400 CBT Training : PASS
2053 13:58:25.676895 Write leveling : PASS
2054 13:58:25.679422 RX DQS gating : PASS
2055 13:58:25.679973 RX DQ/DQS(RDDQC) : PASS
2056 13:58:25.682344 TX DQ/DQS : PASS
2057 13:58:25.686529 RX DATLAT : PASS
2058 13:58:25.687052 RX DQ/DQS(Engine): PASS
2059 13:58:25.688970 TX OE : NO K
2060 13:58:25.689404 All Pass.
2061 13:58:25.689846
2062 13:58:25.691944 CH 1, Rank 0
2063 13:58:25.692382 SW Impedance : PASS
2064 13:58:25.695683 DUTY Scan : NO K
2065 13:58:25.698977 ZQ Calibration : PASS
2066 13:58:25.699413 Jitter Meter : NO K
2067 13:58:25.702074 CBT Training : PASS
2068 13:58:25.705475 Write leveling : PASS
2069 13:58:25.705917 RX DQS gating : PASS
2070 13:58:25.708859 RX DQ/DQS(RDDQC) : PASS
2071 13:58:25.712146 TX DQ/DQS : PASS
2072 13:58:25.712830 RX DATLAT : PASS
2073 13:58:25.716030 RX DQ/DQS(Engine): PASS
2074 13:58:25.718967 TX OE : NO K
2075 13:58:25.719485 All Pass.
2076 13:58:25.719820
2077 13:58:25.720172 CH 1, Rank 1
2078 13:58:25.722640 SW Impedance : PASS
2079 13:58:25.725282 DUTY Scan : NO K
2080 13:58:25.725717 ZQ Calibration : PASS
2081 13:58:25.728272 Jitter Meter : NO K
2082 13:58:25.731838 CBT Training : PASS
2083 13:58:25.732325 Write leveling : PASS
2084 13:58:25.735023 RX DQS gating : PASS
2085 13:58:25.738414 RX DQ/DQS(RDDQC) : PASS
2086 13:58:25.738836 TX DQ/DQS : PASS
2087 13:58:25.741515 RX DATLAT : PASS
2088 13:58:25.741937 RX DQ/DQS(Engine): PASS
2089 13:58:25.745031 TX OE : NO K
2090 13:58:25.745451 All Pass.
2091 13:58:25.745784
2092 13:58:25.748431 DramC Write-DBI off
2093 13:58:25.751675 PER_BANK_REFRESH: Hybrid Mode
2094 13:58:25.752221 TX_TRACKING: ON
2095 13:58:25.754901 [GetDramInforAfterCalByMRR] Vendor 6.
2096 13:58:25.758311 [GetDramInforAfterCalByMRR] Revision 606.
2097 13:58:25.765005 [GetDramInforAfterCalByMRR] Revision 2 0.
2098 13:58:25.765452 MR0 0x3b3b
2099 13:58:25.765893 MR8 0x5151
2100 13:58:25.768387 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 13:58:25.768819
2102 13:58:25.772007 MR0 0x3b3b
2103 13:58:25.772437 MR8 0x5151
2104 13:58:25.774796 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 13:58:25.775232
2106 13:58:25.784715 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2107 13:58:25.788136 [FAST_K] Save calibration result to emmc
2108 13:58:25.791178 [FAST_K] Save calibration result to emmc
2109 13:58:25.795018 dram_init: config_dvfs: 1
2110 13:58:25.798193 dramc_set_vcore_voltage set vcore to 662500
2111 13:58:25.801407 Read voltage for 1200, 2
2112 13:58:25.801841 Vio18 = 0
2113 13:58:25.802278 Vcore = 662500
2114 13:58:25.802692 Vdram = 0
2115 13:58:25.804757 Vddq = 0
2116 13:58:25.805187 Vmddr = 0
2117 13:58:25.811268 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2118 13:58:25.814630 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2119 13:58:25.817855 MEM_TYPE=3, freq_sel=15
2120 13:58:25.821301 sv_algorithm_assistance_LP4_1600
2121 13:58:25.824897 ============ PULL DRAM RESETB DOWN ============
2122 13:58:25.828929 ========== PULL DRAM RESETB DOWN end =========
2123 13:58:25.834575 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 13:58:25.837820 ===================================
2125 13:58:25.838316 LPDDR4 DRAM CONFIGURATION
2126 13:58:25.840974 ===================================
2127 13:58:25.844323 EX_ROW_EN[0] = 0x0
2128 13:58:25.847763 EX_ROW_EN[1] = 0x0
2129 13:58:25.848386 LP4Y_EN = 0x0
2130 13:58:25.851325 WORK_FSP = 0x0
2131 13:58:25.851852 WL = 0x4
2132 13:58:25.854445 RL = 0x4
2133 13:58:25.854969 BL = 0x2
2134 13:58:25.857740 RPST = 0x0
2135 13:58:25.858245 RD_PRE = 0x0
2136 13:58:25.861121 WR_PRE = 0x1
2137 13:58:25.861587 WR_PST = 0x0
2138 13:58:25.864660 DBI_WR = 0x0
2139 13:58:25.865162 DBI_RD = 0x0
2140 13:58:25.867717 OTF = 0x1
2141 13:58:25.871491 ===================================
2142 13:58:25.875282 ===================================
2143 13:58:25.875889 ANA top config
2144 13:58:25.877894 ===================================
2145 13:58:25.880961 DLL_ASYNC_EN = 0
2146 13:58:25.884796 ALL_SLAVE_EN = 0
2147 13:58:25.885295 NEW_RANK_MODE = 1
2148 13:58:25.887675 DLL_IDLE_MODE = 1
2149 13:58:25.891386 LP45_APHY_COMB_EN = 1
2150 13:58:25.894574 TX_ODT_DIS = 1
2151 13:58:25.897861 NEW_8X_MODE = 1
2152 13:58:25.901080 ===================================
2153 13:58:25.904558 ===================================
2154 13:58:25.905097 data_rate = 2400
2155 13:58:25.907744 CKR = 1
2156 13:58:25.911233 DQ_P2S_RATIO = 8
2157 13:58:25.914654 ===================================
2158 13:58:25.917932 CA_P2S_RATIO = 8
2159 13:58:25.922013 DQ_CA_OPEN = 0
2160 13:58:25.924195 DQ_SEMI_OPEN = 0
2161 13:58:25.924645 CA_SEMI_OPEN = 0
2162 13:58:25.927951 CA_FULL_RATE = 0
2163 13:58:25.930820 DQ_CKDIV4_EN = 0
2164 13:58:25.934226 CA_CKDIV4_EN = 0
2165 13:58:25.937681 CA_PREDIV_EN = 0
2166 13:58:25.940929 PH8_DLY = 17
2167 13:58:25.941345 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2168 13:58:25.944669 DQ_AAMCK_DIV = 4
2169 13:58:25.947348 CA_AAMCK_DIV = 4
2170 13:58:25.950810 CA_ADMCK_DIV = 4
2171 13:58:25.953972 DQ_TRACK_CA_EN = 0
2172 13:58:25.957137 CA_PICK = 1200
2173 13:58:25.960658 CA_MCKIO = 1200
2174 13:58:25.961249 MCKIO_SEMI = 0
2175 13:58:25.964008 PLL_FREQ = 2366
2176 13:58:25.967345 DQ_UI_PI_RATIO = 32
2177 13:58:25.971105 CA_UI_PI_RATIO = 0
2178 13:58:25.974250 ===================================
2179 13:58:25.977307 ===================================
2180 13:58:25.980484 memory_type:LPDDR4
2181 13:58:25.980917 GP_NUM : 10
2182 13:58:25.983760 SRAM_EN : 1
2183 13:58:25.983845 MD32_EN : 0
2184 13:58:25.987214 ===================================
2185 13:58:25.990380 [ANA_INIT] >>>>>>>>>>>>>>
2186 13:58:25.993600 <<<<<< [CONFIGURE PHASE]: ANA_TX
2187 13:58:25.997443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2188 13:58:26.000515 ===================================
2189 13:58:26.003813 data_rate = 2400,PCW = 0X5b00
2190 13:58:26.007474 ===================================
2191 13:58:26.010312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2192 13:58:26.017366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 13:58:26.020405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 13:58:26.026896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2195 13:58:26.030914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2196 13:58:26.033845 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2197 13:58:26.033930 [ANA_INIT] flow start
2198 13:58:26.036821 [ANA_INIT] PLL >>>>>>>>
2199 13:58:26.040223 [ANA_INIT] PLL <<<<<<<<
2200 13:58:26.040308 [ANA_INIT] MIDPI >>>>>>>>
2201 13:58:26.043871 [ANA_INIT] MIDPI <<<<<<<<
2202 13:58:26.047663 [ANA_INIT] DLL >>>>>>>>
2203 13:58:26.047747 [ANA_INIT] DLL <<<<<<<<
2204 13:58:26.050080 [ANA_INIT] flow end
2205 13:58:26.053648 ============ LP4 DIFF to SE enter ============
2206 13:58:26.059958 ============ LP4 DIFF to SE exit ============
2207 13:58:26.060044 [ANA_INIT] <<<<<<<<<<<<<
2208 13:58:26.063228 [Flow] Enable top DCM control >>>>>
2209 13:58:26.067098 [Flow] Enable top DCM control <<<<<
2210 13:58:26.071027 Enable DLL master slave shuffle
2211 13:58:26.076745 ==============================================================
2212 13:58:26.076830 Gating Mode config
2213 13:58:26.083399 ==============================================================
2214 13:58:26.086823 Config description:
2215 13:58:26.093601 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2216 13:58:26.099584 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2217 13:58:26.106202 SELPH_MODE 0: By rank 1: By Phase
2218 13:58:26.112917 ==============================================================
2219 13:58:26.113002 GAT_TRACK_EN = 1
2220 13:58:26.116478 RX_GATING_MODE = 2
2221 13:58:26.119640 RX_GATING_TRACK_MODE = 2
2222 13:58:26.123179 SELPH_MODE = 1
2223 13:58:26.126746 PICG_EARLY_EN = 1
2224 13:58:26.129973 VALID_LAT_VALUE = 1
2225 13:58:26.136384 ==============================================================
2226 13:58:26.139672 Enter into Gating configuration >>>>
2227 13:58:26.143083 Exit from Gating configuration <<<<
2228 13:58:26.146307 Enter into DVFS_PRE_config >>>>>
2229 13:58:26.156434 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2230 13:58:26.159915 Exit from DVFS_PRE_config <<<<<
2231 13:58:26.163329 Enter into PICG configuration >>>>
2232 13:58:26.166030 Exit from PICG configuration <<<<
2233 13:58:26.169344 [RX_INPUT] configuration >>>>>
2234 13:58:26.172627 [RX_INPUT] configuration <<<<<
2235 13:58:26.176154 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2236 13:58:26.183358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2237 13:58:26.189335 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 13:58:26.192574 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 13:58:26.199312 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 13:58:26.206216 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 13:58:26.209175 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2242 13:58:26.212695 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2243 13:58:26.219424 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2244 13:58:26.222960 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2245 13:58:26.225664 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2246 13:58:26.232361 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2247 13:58:26.235621 ===================================
2248 13:58:26.235707 LPDDR4 DRAM CONFIGURATION
2249 13:58:26.239093 ===================================
2250 13:58:26.242243 EX_ROW_EN[0] = 0x0
2251 13:58:26.245656 EX_ROW_EN[1] = 0x0
2252 13:58:26.245739 LP4Y_EN = 0x0
2253 13:58:26.249062 WORK_FSP = 0x0
2254 13:58:26.249172 WL = 0x4
2255 13:58:26.252410 RL = 0x4
2256 13:58:26.252491 BL = 0x2
2257 13:58:26.255729 RPST = 0x0
2258 13:58:26.255810 RD_PRE = 0x0
2259 13:58:26.259058 WR_PRE = 0x1
2260 13:58:26.259140 WR_PST = 0x0
2261 13:58:26.262728 DBI_WR = 0x0
2262 13:58:26.262810 DBI_RD = 0x0
2263 13:58:26.265600 OTF = 0x1
2264 13:58:26.269189 ===================================
2265 13:58:26.272440 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2266 13:58:26.275577 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2267 13:58:26.282641 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 13:58:26.285760 ===================================
2269 13:58:26.285842 LPDDR4 DRAM CONFIGURATION
2270 13:58:26.289146 ===================================
2271 13:58:26.292390 EX_ROW_EN[0] = 0x10
2272 13:58:26.292472 EX_ROW_EN[1] = 0x0
2273 13:58:26.296202 LP4Y_EN = 0x0
2274 13:58:26.296282 WORK_FSP = 0x0
2275 13:58:26.299560 WL = 0x4
2276 13:58:26.299641 RL = 0x4
2277 13:58:26.302108 BL = 0x2
2278 13:58:26.305557 RPST = 0x0
2279 13:58:26.305638 RD_PRE = 0x0
2280 13:58:26.309425 WR_PRE = 0x1
2281 13:58:26.309506 WR_PST = 0x0
2282 13:58:26.312091 DBI_WR = 0x0
2283 13:58:26.312172 DBI_RD = 0x0
2284 13:58:26.317214 OTF = 0x1
2285 13:58:26.318969 ===================================
2286 13:58:26.322098 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2287 13:58:26.325557 ==
2288 13:58:26.328940 Dram Type= 6, Freq= 0, CH_0, rank 0
2289 13:58:26.332222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2290 13:58:26.332312 ==
2291 13:58:26.335332 [Duty_Offset_Calibration]
2292 13:58:26.335416 B0:2 B1:0 CA:4
2293 13:58:26.335514
2294 13:58:26.338841 [DutyScan_Calibration_Flow] k_type=0
2295 13:58:26.348567
2296 13:58:26.348649 ==CLK 0==
2297 13:58:26.351461 Final CLK duty delay cell = 0
2298 13:58:26.355296 [0] MAX Duty = 5156%(X100), DQS PI = 14
2299 13:58:26.358163 [0] MIN Duty = 5000%(X100), DQS PI = 8
2300 13:58:26.358249 [0] AVG Duty = 5078%(X100)
2301 13:58:26.362131
2302 13:58:26.364916 CH0 CLK Duty spec in!! Max-Min= 156%
2303 13:58:26.368522 [DutyScan_Calibration_Flow] ====Done====
2304 13:58:26.368605
2305 13:58:26.371461 [DutyScan_Calibration_Flow] k_type=1
2306 13:58:26.387565
2307 13:58:26.387645 ==DQS 0 ==
2308 13:58:26.390115 Final DQS duty delay cell = -4
2309 13:58:26.393556 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2310 13:58:26.396806 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2311 13:58:26.400020 [-4] AVG Duty = 4922%(X100)
2312 13:58:26.400100
2313 13:58:26.400163 ==DQS 1 ==
2314 13:58:26.404032 Final DQS duty delay cell = 0
2315 13:58:26.406950 [0] MAX Duty = 5125%(X100), DQS PI = 4
2316 13:58:26.410133 [0] MIN Duty = 5000%(X100), DQS PI = 0
2317 13:58:26.413136 [0] AVG Duty = 5062%(X100)
2318 13:58:26.413241
2319 13:58:26.416869 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2320 13:58:26.416953
2321 13:58:26.420150 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2322 13:58:26.423524 [DutyScan_Calibration_Flow] ====Done====
2323 13:58:26.423604
2324 13:58:26.426687 [DutyScan_Calibration_Flow] k_type=3
2325 13:58:26.443380
2326 13:58:26.443473 ==DQM 0 ==
2327 13:58:26.446742 Final DQM duty delay cell = 0
2328 13:58:26.450462 [0] MAX Duty = 5125%(X100), DQS PI = 20
2329 13:58:26.453498 [0] MIN Duty = 4844%(X100), DQS PI = 54
2330 13:58:26.456907 [0] AVG Duty = 4984%(X100)
2331 13:58:26.456991
2332 13:58:26.457077 ==DQM 1 ==
2333 13:58:26.459843 Final DQM duty delay cell = 0
2334 13:58:26.463733 [0] MAX Duty = 4969%(X100), DQS PI = 2
2335 13:58:26.466810 [0] MIN Duty = 4907%(X100), DQS PI = 12
2336 13:58:26.469952 [0] AVG Duty = 4938%(X100)
2337 13:58:26.470036
2338 13:58:26.473310 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2339 13:58:26.473393
2340 13:58:26.476936 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2341 13:58:26.480059 [DutyScan_Calibration_Flow] ====Done====
2342 13:58:26.480169
2343 13:58:26.483151 [DutyScan_Calibration_Flow] k_type=2
2344 13:58:26.500407
2345 13:58:26.500488 ==DQ 0 ==
2346 13:58:26.503124 Final DQ duty delay cell = 0
2347 13:58:26.506505 [0] MAX Duty = 5125%(X100), DQS PI = 18
2348 13:58:26.509964 [0] MIN Duty = 4969%(X100), DQS PI = 52
2349 13:58:26.513363 [0] AVG Duty = 5047%(X100)
2350 13:58:26.513444
2351 13:58:26.513508 ==DQ 1 ==
2352 13:58:26.516772 Final DQ duty delay cell = 0
2353 13:58:26.519574 [0] MAX Duty = 5156%(X100), DQS PI = 6
2354 13:58:26.523235 [0] MIN Duty = 4938%(X100), DQS PI = 16
2355 13:58:26.523317 [0] AVG Duty = 5047%(X100)
2356 13:58:26.526121
2357 13:58:26.529328 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2358 13:58:26.529410
2359 13:58:26.532890 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2360 13:58:26.536015 [DutyScan_Calibration_Flow] ====Done====
2361 13:58:26.536097 ==
2362 13:58:26.539408 Dram Type= 6, Freq= 0, CH_1, rank 0
2363 13:58:26.542919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 13:58:26.543001 ==
2365 13:58:26.546865 [Duty_Offset_Calibration]
2366 13:58:26.546972 B0:0 B1:-1 CA:3
2367 13:58:26.547067
2368 13:58:26.549660 [DutyScan_Calibration_Flow] k_type=0
2369 13:58:26.559432
2370 13:58:26.559513 ==CLK 0==
2371 13:58:26.562968 Final CLK duty delay cell = -4
2372 13:58:26.565960 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2373 13:58:26.569059 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2374 13:58:26.572564 [-4] AVG Duty = 4938%(X100)
2375 13:58:26.572646
2376 13:58:26.575831 CH1 CLK Duty spec in!! Max-Min= 124%
2377 13:58:26.579037 [DutyScan_Calibration_Flow] ====Done====
2378 13:58:26.579119
2379 13:58:26.582396 [DutyScan_Calibration_Flow] k_type=1
2380 13:58:26.598260
2381 13:58:26.598340 ==DQS 0 ==
2382 13:58:26.601444 Final DQS duty delay cell = 0
2383 13:58:26.604768 [0] MAX Duty = 5187%(X100), DQS PI = 18
2384 13:58:26.608094 [0] MIN Duty = 4907%(X100), DQS PI = 38
2385 13:58:26.608176 [0] AVG Duty = 5047%(X100)
2386 13:58:26.611359
2387 13:58:26.611439 ==DQS 1 ==
2388 13:58:26.614876 Final DQS duty delay cell = -4
2389 13:58:26.618277 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2390 13:58:26.621126 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2391 13:58:26.624189 [-4] AVG Duty = 4937%(X100)
2392 13:58:26.624271
2393 13:58:26.628415 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2394 13:58:26.628496
2395 13:58:26.631050 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2396 13:58:26.634558 [DutyScan_Calibration_Flow] ====Done====
2397 13:58:26.634641
2398 13:58:26.637862 [DutyScan_Calibration_Flow] k_type=3
2399 13:58:26.654863
2400 13:58:26.654944 ==DQM 0 ==
2401 13:58:26.657894 Final DQM duty delay cell = 0
2402 13:58:26.661577 [0] MAX Duty = 5031%(X100), DQS PI = 28
2403 13:58:26.664645 [0] MIN Duty = 4813%(X100), DQS PI = 38
2404 13:58:26.668822 [0] AVG Duty = 4922%(X100)
2405 13:58:26.668903
2406 13:58:26.668968 ==DQM 1 ==
2407 13:58:26.671098 Final DQM duty delay cell = 0
2408 13:58:26.674718 [0] MAX Duty = 5000%(X100), DQS PI = 34
2409 13:58:26.678143 [0] MIN Duty = 4844%(X100), DQS PI = 0
2410 13:58:26.681111 [0] AVG Duty = 4922%(X100)
2411 13:58:26.681192
2412 13:58:26.685131 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2413 13:58:26.685212
2414 13:58:26.687972 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2415 13:58:26.691178 [DutyScan_Calibration_Flow] ====Done====
2416 13:58:26.691258
2417 13:58:26.694448 [DutyScan_Calibration_Flow] k_type=2
2418 13:58:26.711617
2419 13:58:26.711701 ==DQ 0 ==
2420 13:58:26.714951 Final DQ duty delay cell = -4
2421 13:58:26.718741 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2422 13:58:26.721180 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2423 13:58:26.724284 [-4] AVG Duty = 4937%(X100)
2424 13:58:26.724366
2425 13:58:26.724431 ==DQ 1 ==
2426 13:58:26.727784 Final DQ duty delay cell = 4
2427 13:58:26.731062 [4] MAX Duty = 5187%(X100), DQS PI = 34
2428 13:58:26.734353 [4] MIN Duty = 5062%(X100), DQS PI = 0
2429 13:58:26.737538 [4] AVG Duty = 5124%(X100)
2430 13:58:26.737620
2431 13:58:26.741073 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2432 13:58:26.741155
2433 13:58:26.744176 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2434 13:58:26.747775 [DutyScan_Calibration_Flow] ====Done====
2435 13:58:26.751419 nWR fixed to 30
2436 13:58:26.751500 [ModeRegInit_LP4] CH0 RK0
2437 13:58:26.754685 [ModeRegInit_LP4] CH0 RK1
2438 13:58:26.757559 [ModeRegInit_LP4] CH1 RK0
2439 13:58:26.761149 [ModeRegInit_LP4] CH1 RK1
2440 13:58:26.761230 match AC timing 7
2441 13:58:26.768003 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2442 13:58:26.770995 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2443 13:58:26.774738 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2444 13:58:26.780681 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2445 13:58:26.784202 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2446 13:58:26.784317 ==
2447 13:58:26.787267 Dram Type= 6, Freq= 0, CH_0, rank 0
2448 13:58:26.790929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 13:58:26.791023 ==
2450 13:58:26.797153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2451 13:58:26.804083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2452 13:58:26.811175 [CA 0] Center 39 (9~70) winsize 62
2453 13:58:26.815135 [CA 1] Center 39 (9~69) winsize 61
2454 13:58:26.818305 [CA 2] Center 35 (5~66) winsize 62
2455 13:58:26.821304 [CA 3] Center 35 (4~66) winsize 63
2456 13:58:26.824506 [CA 4] Center 33 (3~64) winsize 62
2457 13:58:26.828284 [CA 5] Center 33 (3~63) winsize 61
2458 13:58:26.828369
2459 13:58:26.831377 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2460 13:58:26.831461
2461 13:58:26.834502 [CATrainingPosCal] consider 1 rank data
2462 13:58:26.837769 u2DelayCellTimex100 = 270/100 ps
2463 13:58:26.841327 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2464 13:58:26.844561 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2465 13:58:26.851093 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2466 13:58:26.854637 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2467 13:58:26.857757 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2468 13:58:26.861345 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2469 13:58:26.861425
2470 13:58:26.864741 CA PerBit enable=1, Macro0, CA PI delay=33
2471 13:58:26.864821
2472 13:58:26.867529 [CBTSetCACLKResult] CA Dly = 33
2473 13:58:26.867608 CS Dly: 7 (0~38)
2474 13:58:26.871403 ==
2475 13:58:26.874657 Dram Type= 6, Freq= 0, CH_0, rank 1
2476 13:58:26.877600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 13:58:26.877681 ==
2478 13:58:26.881054 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 13:58:26.887843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2480 13:58:26.897463 [CA 0] Center 39 (9~70) winsize 62
2481 13:58:26.900777 [CA 1] Center 39 (9~70) winsize 62
2482 13:58:26.903704 [CA 2] Center 35 (5~66) winsize 62
2483 13:58:26.907700 [CA 3] Center 35 (4~66) winsize 63
2484 13:58:26.910940 [CA 4] Center 34 (4~65) winsize 62
2485 13:58:26.914305 [CA 5] Center 33 (3~64) winsize 62
2486 13:58:26.914385
2487 13:58:26.917715 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2488 13:58:26.917795
2489 13:58:26.921494 [CATrainingPosCal] consider 2 rank data
2490 13:58:26.923873 u2DelayCellTimex100 = 270/100 ps
2491 13:58:26.927429 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2492 13:58:26.930692 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2493 13:58:26.934143 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2494 13:58:26.940958 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2495 13:58:26.943918 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2496 13:58:26.947129 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2497 13:58:26.947208
2498 13:58:26.951540 CA PerBit enable=1, Macro0, CA PI delay=33
2499 13:58:26.951620
2500 13:58:26.954008 [CBTSetCACLKResult] CA Dly = 33
2501 13:58:26.954088 CS Dly: 8 (0~41)
2502 13:58:26.954151
2503 13:58:26.957254 ----->DramcWriteLeveling(PI) begin...
2504 13:58:26.960728 ==
2505 13:58:26.963546 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 13:58:26.967617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 13:58:26.967698 ==
2508 13:58:26.970531 Write leveling (Byte 0): 30 => 30
2509 13:58:26.973769 Write leveling (Byte 1): 27 => 27
2510 13:58:26.976820 DramcWriteLeveling(PI) end<-----
2511 13:58:26.976899
2512 13:58:26.976963 ==
2513 13:58:26.980764 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 13:58:26.983639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 13:58:26.983719 ==
2516 13:58:26.987232 [Gating] SW mode calibration
2517 13:58:26.993504 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2518 13:58:27.000519 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2519 13:58:27.003791 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2520 13:58:27.006912 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2521 13:58:27.010085 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 13:58:27.016908 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 13:58:27.020222 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 13:58:27.023469 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2525 13:58:27.030149 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2526 13:58:27.033873 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
2527 13:58:27.036790 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2528 13:58:27.043422 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 13:58:27.047140 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 13:58:27.050162 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 13:58:27.056860 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 13:58:27.060325 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 13:58:27.063631 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2534 13:58:27.070536 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2535 13:58:27.073052 1 1 0 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
2536 13:58:27.076628 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 13:58:27.083529 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 13:58:27.086260 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 13:58:27.090201 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 13:58:27.097047 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 13:58:27.099959 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2542 13:58:27.102914 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2543 13:58:27.110113 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 13:58:27.113195 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 13:58:27.116886 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 13:58:27.123155 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 13:58:27.126803 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 13:58:27.129638 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 13:58:27.136948 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 13:58:27.139643 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 13:58:27.142795 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 13:58:27.146456 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 13:58:27.153155 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 13:58:27.156279 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:58:27.159762 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 13:58:27.166376 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 13:58:27.169397 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 13:58:27.172689 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 13:58:27.176426 Total UI for P1: 0, mck2ui 16
2560 13:58:27.179439 best dqsien dly found for B0: ( 1, 3, 24)
2561 13:58:27.186085 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2562 13:58:27.189300 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 13:58:27.192944 Total UI for P1: 0, mck2ui 16
2564 13:58:27.196196 best dqsien dly found for B1: ( 1, 3, 30)
2565 13:58:27.199366 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2566 13:58:27.202948 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2567 13:58:27.203028
2568 13:58:27.206009 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2569 13:58:27.210355 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2570 13:58:27.212513 [Gating] SW calibration Done
2571 13:58:27.212592 ==
2572 13:58:27.216309 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 13:58:27.222610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 13:58:27.222691 ==
2575 13:58:27.222754 RX Vref Scan: 0
2576 13:58:27.222813
2577 13:58:27.226125 RX Vref 0 -> 0, step: 1
2578 13:58:27.226205
2579 13:58:27.229427 RX Delay -40 -> 252, step: 8
2580 13:58:27.232611 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2581 13:58:27.235947 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2582 13:58:27.239786 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2583 13:58:27.243073 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2584 13:58:27.249208 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2585 13:58:27.252410 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2586 13:58:27.255864 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2587 13:58:27.258871 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2588 13:58:27.262705 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2589 13:58:27.269480 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2590 13:58:27.272791 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2591 13:58:27.275826 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2592 13:58:27.279050 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2593 13:58:27.282569 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2594 13:58:27.289238 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2595 13:58:27.292346 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2596 13:58:27.292426 ==
2597 13:58:27.296041 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 13:58:27.299137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 13:58:27.299216 ==
2600 13:58:27.302303 DQS Delay:
2601 13:58:27.302383 DQS0 = 0, DQS1 = 0
2602 13:58:27.302447 DQM Delay:
2603 13:58:27.305602 DQM0 = 120, DQM1 = 107
2604 13:58:27.305682 DQ Delay:
2605 13:58:27.309137 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2606 13:58:27.312198 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2607 13:58:27.315701 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2608 13:58:27.322431 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2609 13:58:27.322510
2610 13:58:27.322573
2611 13:58:27.322630 ==
2612 13:58:27.325883 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 13:58:27.329162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 13:58:27.329242 ==
2615 13:58:27.329305
2616 13:58:27.329364
2617 13:58:27.332018 TX Vref Scan disable
2618 13:58:27.332098 == TX Byte 0 ==
2619 13:58:27.338826 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2620 13:58:27.341965 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2621 13:58:27.342044 == TX Byte 1 ==
2622 13:58:27.348582 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2623 13:58:27.352489 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2624 13:58:27.352568 ==
2625 13:58:27.355280 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 13:58:27.358421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 13:58:27.358501 ==
2628 13:58:27.371870 TX Vref=22, minBit 4, minWin=25, winSum=409
2629 13:58:27.375139 TX Vref=24, minBit 3, minWin=25, winSum=416
2630 13:58:27.379089 TX Vref=26, minBit 15, minWin=25, winSum=422
2631 13:58:27.382056 TX Vref=28, minBit 5, minWin=26, winSum=430
2632 13:58:27.385082 TX Vref=30, minBit 5, minWin=26, winSum=432
2633 13:58:27.389039 TX Vref=32, minBit 5, minWin=26, winSum=429
2634 13:58:27.395029 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 30
2635 13:58:27.395109
2636 13:58:27.398230 Final TX Range 1 Vref 30
2637 13:58:27.398310
2638 13:58:27.398372 ==
2639 13:58:27.401680 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 13:58:27.404934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 13:58:27.405013 ==
2642 13:58:27.408542
2643 13:58:27.408620
2644 13:58:27.408683 TX Vref Scan disable
2645 13:58:27.411464 == TX Byte 0 ==
2646 13:58:27.415529 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2647 13:58:27.418236 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2648 13:58:27.421421 == TX Byte 1 ==
2649 13:58:27.425038 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2650 13:58:27.428636 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2651 13:58:27.431661
2652 13:58:27.431740 [DATLAT]
2653 13:58:27.431802 Freq=1200, CH0 RK0
2654 13:58:27.431861
2655 13:58:27.435082 DATLAT Default: 0xd
2656 13:58:27.435162 0, 0xFFFF, sum = 0
2657 13:58:27.438164 1, 0xFFFF, sum = 0
2658 13:58:27.438245 2, 0xFFFF, sum = 0
2659 13:58:27.441935 3, 0xFFFF, sum = 0
2660 13:58:27.445135 4, 0xFFFF, sum = 0
2661 13:58:27.445215 5, 0xFFFF, sum = 0
2662 13:58:27.448153 6, 0xFFFF, sum = 0
2663 13:58:27.448257 7, 0xFFFF, sum = 0
2664 13:58:27.451530 8, 0xFFFF, sum = 0
2665 13:58:27.451611 9, 0xFFFF, sum = 0
2666 13:58:27.454864 10, 0xFFFF, sum = 0
2667 13:58:27.454946 11, 0xFFFF, sum = 0
2668 13:58:27.457927 12, 0x0, sum = 1
2669 13:58:27.458007 13, 0x0, sum = 2
2670 13:58:27.461948 14, 0x0, sum = 3
2671 13:58:27.462028 15, 0x0, sum = 4
2672 13:58:27.464738 best_step = 13
2673 13:58:27.464842
2674 13:58:27.464929 ==
2675 13:58:27.468276 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 13:58:27.471313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 13:58:27.471392 ==
2678 13:58:27.471456 RX Vref Scan: 1
2679 13:58:27.471515
2680 13:58:27.474429 Set Vref Range= 32 -> 127
2681 13:58:27.474508
2682 13:58:27.477991 RX Vref 32 -> 127, step: 1
2683 13:58:27.478071
2684 13:58:27.481520 RX Delay -21 -> 252, step: 4
2685 13:58:27.481600
2686 13:58:27.484886 Set Vref, RX VrefLevel [Byte0]: 32
2687 13:58:27.488102 [Byte1]: 32
2688 13:58:27.488181
2689 13:58:27.492142 Set Vref, RX VrefLevel [Byte0]: 33
2690 13:58:27.494363 [Byte1]: 33
2691 13:58:27.498216
2692 13:58:27.498295 Set Vref, RX VrefLevel [Byte0]: 34
2693 13:58:27.501505 [Byte1]: 34
2694 13:58:27.505930
2695 13:58:27.506009 Set Vref, RX VrefLevel [Byte0]: 35
2696 13:58:27.509380 [Byte1]: 35
2697 13:58:27.514021
2698 13:58:27.514100 Set Vref, RX VrefLevel [Byte0]: 36
2699 13:58:27.517422 [Byte1]: 36
2700 13:58:27.521921
2701 13:58:27.522000 Set Vref, RX VrefLevel [Byte0]: 37
2702 13:58:27.525165 [Byte1]: 37
2703 13:58:27.529580
2704 13:58:27.529659 Set Vref, RX VrefLevel [Byte0]: 38
2705 13:58:27.533231 [Byte1]: 38
2706 13:58:27.537917
2707 13:58:27.537997 Set Vref, RX VrefLevel [Byte0]: 39
2708 13:58:27.540877 [Byte1]: 39
2709 13:58:27.545732
2710 13:58:27.545811 Set Vref, RX VrefLevel [Byte0]: 40
2711 13:58:27.548902 [Byte1]: 40
2712 13:58:27.553623
2713 13:58:27.553702 Set Vref, RX VrefLevel [Byte0]: 41
2714 13:58:27.557552 [Byte1]: 41
2715 13:58:27.561699
2716 13:58:27.561782 Set Vref, RX VrefLevel [Byte0]: 42
2717 13:58:27.564665 [Byte1]: 42
2718 13:58:27.569410
2719 13:58:27.569490 Set Vref, RX VrefLevel [Byte0]: 43
2720 13:58:27.572650 [Byte1]: 43
2721 13:58:27.577408
2722 13:58:27.577488 Set Vref, RX VrefLevel [Byte0]: 44
2723 13:58:27.580682 [Byte1]: 44
2724 13:58:27.585268
2725 13:58:27.585347 Set Vref, RX VrefLevel [Byte0]: 45
2726 13:58:27.588347 [Byte1]: 45
2727 13:58:27.593440
2728 13:58:27.593519 Set Vref, RX VrefLevel [Byte0]: 46
2729 13:58:27.596731 [Byte1]: 46
2730 13:58:27.601303
2731 13:58:27.601382 Set Vref, RX VrefLevel [Byte0]: 47
2732 13:58:27.604483 [Byte1]: 47
2733 13:58:27.609245
2734 13:58:27.609324 Set Vref, RX VrefLevel [Byte0]: 48
2735 13:58:27.612683 [Byte1]: 48
2736 13:58:27.616982
2737 13:58:27.617061 Set Vref, RX VrefLevel [Byte0]: 49
2738 13:58:27.620658 [Byte1]: 49
2739 13:58:27.625195
2740 13:58:27.625274 Set Vref, RX VrefLevel [Byte0]: 50
2741 13:58:27.628558 [Byte1]: 50
2742 13:58:27.633260
2743 13:58:27.633340 Set Vref, RX VrefLevel [Byte0]: 51
2744 13:58:27.635944 [Byte1]: 51
2745 13:58:27.640432
2746 13:58:27.640515 Set Vref, RX VrefLevel [Byte0]: 52
2747 13:58:27.643908 [Byte1]: 52
2748 13:58:27.648880
2749 13:58:27.648960 Set Vref, RX VrefLevel [Byte0]: 53
2750 13:58:27.651932 [Byte1]: 53
2751 13:58:27.656735
2752 13:58:27.656815 Set Vref, RX VrefLevel [Byte0]: 54
2753 13:58:27.660297 [Byte1]: 54
2754 13:58:27.664617
2755 13:58:27.664697 Set Vref, RX VrefLevel [Byte0]: 55
2756 13:58:27.667670 [Byte1]: 55
2757 13:58:27.672427
2758 13:58:27.672506 Set Vref, RX VrefLevel [Byte0]: 56
2759 13:58:27.675503 [Byte1]: 56
2760 13:58:27.680768
2761 13:58:27.680847 Set Vref, RX VrefLevel [Byte0]: 57
2762 13:58:27.683938 [Byte1]: 57
2763 13:58:27.688089
2764 13:58:27.688168 Set Vref, RX VrefLevel [Byte0]: 58
2765 13:58:27.691409 [Byte1]: 58
2766 13:58:27.696297
2767 13:58:27.696376 Set Vref, RX VrefLevel [Byte0]: 59
2768 13:58:27.699597 [Byte1]: 59
2769 13:58:27.704250
2770 13:58:27.704329 Set Vref, RX VrefLevel [Byte0]: 60
2771 13:58:27.707308 [Byte1]: 60
2772 13:58:27.712456
2773 13:58:27.712535 Set Vref, RX VrefLevel [Byte0]: 61
2774 13:58:27.715610 [Byte1]: 61
2775 13:58:27.719741
2776 13:58:27.719820 Set Vref, RX VrefLevel [Byte0]: 62
2777 13:58:27.723664 [Byte1]: 62
2778 13:58:27.728031
2779 13:58:27.728109 Set Vref, RX VrefLevel [Byte0]: 63
2780 13:58:27.730898 [Byte1]: 63
2781 13:58:27.735868
2782 13:58:27.735957 Set Vref, RX VrefLevel [Byte0]: 64
2783 13:58:27.738965 [Byte1]: 64
2784 13:58:27.744319
2785 13:58:27.744391 Set Vref, RX VrefLevel [Byte0]: 65
2786 13:58:27.747200 [Byte1]: 65
2787 13:58:27.751929
2788 13:58:27.752008 Set Vref, RX VrefLevel [Byte0]: 66
2789 13:58:27.754956 [Byte1]: 66
2790 13:58:27.759575
2791 13:58:27.759654 Set Vref, RX VrefLevel [Byte0]: 67
2792 13:58:27.762767 [Byte1]: 67
2793 13:58:27.767478
2794 13:58:27.767556 Set Vref, RX VrefLevel [Byte0]: 68
2795 13:58:27.770949 [Byte1]: 68
2796 13:58:27.775457
2797 13:58:27.775536 Final RX Vref Byte 0 = 56 to rank0
2798 13:58:27.778602 Final RX Vref Byte 1 = 49 to rank0
2799 13:58:27.781839 Final RX Vref Byte 0 = 56 to rank1
2800 13:58:27.785819 Final RX Vref Byte 1 = 49 to rank1==
2801 13:58:27.788443 Dram Type= 6, Freq= 0, CH_0, rank 0
2802 13:58:27.795717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2803 13:58:27.795798 ==
2804 13:58:27.795862 DQS Delay:
2805 13:58:27.795930 DQS0 = 0, DQS1 = 0
2806 13:58:27.798791 DQM Delay:
2807 13:58:27.798871 DQM0 = 119, DQM1 = 105
2808 13:58:27.802686 DQ Delay:
2809 13:58:27.805215 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =116
2810 13:58:27.808843 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =122
2811 13:58:27.812093 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2812 13:58:27.815424 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =114
2813 13:58:27.815589
2814 13:58:27.815748
2815 13:58:27.821825 [DQSOSCAuto] RK0, (LSB)MR18= 0x3fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2816 13:58:27.825743 CH0 RK0: MR19=403, MR18=3FE
2817 13:58:27.831978 CH0_RK0: MR19=0x403, MR18=0x3FE, DQSOSC=408, MR23=63, INC=39, DEC=26
2818 13:58:27.832059
2819 13:58:27.835359 ----->DramcWriteLeveling(PI) begin...
2820 13:58:27.835436 ==
2821 13:58:27.838820 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 13:58:27.841951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 13:58:27.845100 ==
2824 13:58:27.845179 Write leveling (Byte 0): 31 => 31
2825 13:58:27.848160 Write leveling (Byte 1): 27 => 27
2826 13:58:27.851629 DramcWriteLeveling(PI) end<-----
2827 13:58:27.851728
2828 13:58:27.851817 ==
2829 13:58:27.855109 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 13:58:27.861628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 13:58:27.861712 ==
2832 13:58:27.861776 [Gating] SW mode calibration
2833 13:58:27.871621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2834 13:58:27.874861 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2835 13:58:27.881722 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2836 13:58:27.885282 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 13:58:27.888297 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 13:58:27.891320 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 13:58:27.898147 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 13:58:27.901940 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2841 13:58:27.904589 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2842 13:58:27.911855 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2843 13:58:27.914763 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2844 13:58:27.918180 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 13:58:27.924258 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 13:58:27.927971 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 13:58:27.931475 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 13:58:27.937893 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 13:58:27.941222 1 0 24 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
2850 13:58:27.944439 1 0 28 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
2851 13:58:27.951113 1 1 0 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
2852 13:58:27.954486 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 13:58:27.958205 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 13:58:27.964547 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 13:58:27.968194 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 13:58:27.971196 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2857 13:58:27.978000 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2858 13:58:27.981352 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2859 13:58:27.984656 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 13:58:27.991086 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 13:58:27.994584 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 13:58:27.998061 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 13:58:28.004360 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 13:58:28.007515 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 13:58:28.010847 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 13:58:28.017976 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 13:58:28.021299 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 13:58:28.024072 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 13:58:28.031421 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 13:58:28.034104 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 13:58:28.037885 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 13:58:28.044323 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2873 13:58:28.047698 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2874 13:58:28.050671 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2875 13:58:28.054032 Total UI for P1: 0, mck2ui 16
2876 13:58:28.057304 best dqsien dly found for B0: ( 1, 3, 22)
2877 13:58:28.060890 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 13:58:28.064408 Total UI for P1: 0, mck2ui 16
2879 13:58:28.067609 best dqsien dly found for B1: ( 1, 3, 28)
2880 13:58:28.070714 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2881 13:58:28.077268 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2882 13:58:28.077349
2883 13:58:28.080682 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2884 13:58:28.084144 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2885 13:58:28.087918 [Gating] SW calibration Done
2886 13:58:28.087998 ==
2887 13:58:28.090835 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 13:58:28.093848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 13:58:28.093930 ==
2890 13:58:28.093994 RX Vref Scan: 0
2891 13:58:28.097722
2892 13:58:28.097803 RX Vref 0 -> 0, step: 1
2893 13:58:28.097868
2894 13:58:28.101128 RX Delay -40 -> 252, step: 8
2895 13:58:28.103880 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2896 13:58:28.107312 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2897 13:58:28.113866 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2898 13:58:28.117852 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2899 13:58:28.120849 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2900 13:58:28.124225 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2901 13:58:28.127175 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2902 13:58:28.134654 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2903 13:58:28.137017 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2904 13:58:28.140432 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2905 13:58:28.143666 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2906 13:58:28.147188 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2907 13:58:28.153654 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2908 13:58:28.157794 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2909 13:58:28.160196 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2910 13:58:28.163787 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2911 13:58:28.163868 ==
2912 13:58:28.166983 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 13:58:28.173524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 13:58:28.173613 ==
2915 13:58:28.173678 DQS Delay:
2916 13:58:28.173737 DQS0 = 0, DQS1 = 0
2917 13:58:28.177121 DQM Delay:
2918 13:58:28.177201 DQM0 = 119, DQM1 = 107
2919 13:58:28.180791 DQ Delay:
2920 13:58:28.184161 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2921 13:58:28.187143 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2922 13:58:28.190177 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2923 13:58:28.193485 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2924 13:58:28.193566
2925 13:58:28.193630
2926 13:58:28.193689 ==
2927 13:58:28.198245 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 13:58:28.200244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 13:58:28.200326 ==
2930 13:58:28.203891
2931 13:58:28.204010
2932 13:58:28.204076 TX Vref Scan disable
2933 13:58:28.207085 == TX Byte 0 ==
2934 13:58:28.210471 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2935 13:58:28.213798 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2936 13:58:28.217304 == TX Byte 1 ==
2937 13:58:28.220782 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2938 13:58:28.223587 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2939 13:58:28.223668 ==
2940 13:58:28.227205 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 13:58:28.233916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 13:58:28.233997 ==
2943 13:58:28.244327 TX Vref=22, minBit 13, minWin=25, winSum=420
2944 13:58:28.247982 TX Vref=24, minBit 13, minWin=25, winSum=423
2945 13:58:28.251103 TX Vref=26, minBit 2, minWin=26, winSum=428
2946 13:58:28.255139 TX Vref=28, minBit 5, minWin=26, winSum=430
2947 13:58:28.257770 TX Vref=30, minBit 12, minWin=26, winSum=434
2948 13:58:28.264681 TX Vref=32, minBit 14, minWin=25, winSum=427
2949 13:58:28.268050 [TxChooseVref] Worse bit 12, Min win 26, Win sum 434, Final Vref 30
2950 13:58:28.268132
2951 13:58:28.271145 Final TX Range 1 Vref 30
2952 13:58:28.271227
2953 13:58:28.271290 ==
2954 13:58:28.274316 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 13:58:28.281008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 13:58:28.281089 ==
2957 13:58:28.281154
2958 13:58:28.281213
2959 13:58:28.281270 TX Vref Scan disable
2960 13:58:28.284831 == TX Byte 0 ==
2961 13:58:28.288148 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2962 13:58:28.294612 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2963 13:58:28.294693 == TX Byte 1 ==
2964 13:58:28.298323 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2965 13:58:28.304600 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2966 13:58:28.304681
2967 13:58:28.304746 [DATLAT]
2968 13:58:28.304806 Freq=1200, CH0 RK1
2969 13:58:28.304864
2970 13:58:28.308637 DATLAT Default: 0xd
2971 13:58:28.308717 0, 0xFFFF, sum = 0
2972 13:58:28.311302 1, 0xFFFF, sum = 0
2973 13:58:28.311384 2, 0xFFFF, sum = 0
2974 13:58:28.314473 3, 0xFFFF, sum = 0
2975 13:58:28.319143 4, 0xFFFF, sum = 0
2976 13:58:28.319226 5, 0xFFFF, sum = 0
2977 13:58:28.321160 6, 0xFFFF, sum = 0
2978 13:58:28.321243 7, 0xFFFF, sum = 0
2979 13:58:28.324896 8, 0xFFFF, sum = 0
2980 13:58:28.324979 9, 0xFFFF, sum = 0
2981 13:58:28.328154 10, 0xFFFF, sum = 0
2982 13:58:28.328237 11, 0xFFFF, sum = 0
2983 13:58:28.331472 12, 0x0, sum = 1
2984 13:58:28.331553 13, 0x0, sum = 2
2985 13:58:28.334876 14, 0x0, sum = 3
2986 13:58:28.334959 15, 0x0, sum = 4
2987 13:58:28.338084 best_step = 13
2988 13:58:28.338165
2989 13:58:28.338229 ==
2990 13:58:28.341375 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 13:58:28.345051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 13:58:28.345133 ==
2993 13:58:28.345198 RX Vref Scan: 0
2994 13:58:28.345257
2995 13:58:28.347798 RX Vref 0 -> 0, step: 1
2996 13:58:28.347879
2997 13:58:28.351256 RX Delay -21 -> 252, step: 4
2998 13:58:28.354426 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2999 13:58:28.360982 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3000 13:58:28.364278 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3001 13:58:28.367495 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3002 13:58:28.371057 iDelay=195, Bit 4, Center 122 (59 ~ 186) 128
3003 13:58:28.374447 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3004 13:58:28.380913 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3005 13:58:28.385096 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3006 13:58:28.387390 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3007 13:58:28.391219 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3008 13:58:28.394274 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3009 13:58:28.400487 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3010 13:58:28.404245 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3011 13:58:28.407581 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3012 13:58:28.411075 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3013 13:58:28.417099 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3014 13:58:28.417179 ==
3015 13:58:28.420567 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 13:58:28.424118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 13:58:28.424198 ==
3018 13:58:28.424261 DQS Delay:
3019 13:58:28.427149 DQS0 = 0, DQS1 = 0
3020 13:58:28.427228 DQM Delay:
3021 13:58:28.430529 DQM0 = 118, DQM1 = 106
3022 13:58:28.430609 DQ Delay:
3023 13:58:28.433753 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3024 13:58:28.437405 DQ4 =122, DQ5 =112, DQ6 =128, DQ7 =124
3025 13:58:28.440709 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3026 13:58:28.443861 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =114
3027 13:58:28.443985
3028 13:58:28.444050
3029 13:58:28.454267 [DQSOSCAuto] RK1, (LSB)MR18= 0xfefc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3030 13:58:28.454350 CH0 RK1: MR19=303, MR18=FEFC
3031 13:58:28.461067 CH0_RK1: MR19=0x303, MR18=0xFEFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3032 13:58:28.464054 [RxdqsGatingPostProcess] freq 1200
3033 13:58:28.470709 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3034 13:58:28.474242 best DQS0 dly(2T, 0.5T) = (0, 11)
3035 13:58:28.477049 best DQS1 dly(2T, 0.5T) = (0, 11)
3036 13:58:28.480923 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3037 13:58:28.484374 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3038 13:58:28.487232 best DQS0 dly(2T, 0.5T) = (0, 11)
3039 13:58:28.490623 best DQS1 dly(2T, 0.5T) = (0, 11)
3040 13:58:28.494343 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3041 13:58:28.496871 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3042 13:58:28.500226 Pre-setting of DQS Precalculation
3043 13:58:28.504008 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3044 13:58:28.504089 ==
3045 13:58:28.507414 Dram Type= 6, Freq= 0, CH_1, rank 0
3046 13:58:28.511153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 13:58:28.511239 ==
3048 13:58:28.516511 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3049 13:58:28.523338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3050 13:58:28.530926 [CA 0] Center 37 (7~68) winsize 62
3051 13:58:28.534123 [CA 1] Center 37 (7~68) winsize 62
3052 13:58:28.537329 [CA 2] Center 35 (5~65) winsize 61
3053 13:58:28.541238 [CA 3] Center 34 (4~64) winsize 61
3054 13:58:28.544329 [CA 4] Center 34 (4~64) winsize 61
3055 13:58:28.547318 [CA 5] Center 33 (3~64) winsize 62
3056 13:58:28.547399
3057 13:58:28.550962 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3058 13:58:28.551044
3059 13:58:28.554495 [CATrainingPosCal] consider 1 rank data
3060 13:58:28.557258 u2DelayCellTimex100 = 270/100 ps
3061 13:58:28.561653 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3062 13:58:28.567430 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3063 13:58:28.570687 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3064 13:58:28.574165 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3065 13:58:28.577636 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3066 13:58:28.581143 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3067 13:58:28.581225
3068 13:58:28.583850 CA PerBit enable=1, Macro0, CA PI delay=33
3069 13:58:28.583967
3070 13:58:28.587301 [CBTSetCACLKResult] CA Dly = 33
3071 13:58:28.587382 CS Dly: 4 (0~35)
3072 13:58:28.590553 ==
3073 13:58:28.594743 Dram Type= 6, Freq= 0, CH_1, rank 1
3074 13:58:28.597246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 13:58:28.597328 ==
3076 13:58:28.600734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3077 13:58:28.607401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3078 13:58:28.617382 [CA 0] Center 37 (7~68) winsize 62
3079 13:58:28.619818 [CA 1] Center 38 (8~68) winsize 61
3080 13:58:28.623287 [CA 2] Center 35 (5~65) winsize 61
3081 13:58:28.627123 [CA 3] Center 33 (3~64) winsize 62
3082 13:58:28.630833 [CA 4] Center 34 (4~64) winsize 61
3083 13:58:28.633117 [CA 5] Center 34 (4~64) winsize 61
3084 13:58:28.633198
3085 13:58:28.636840 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3086 13:58:28.636921
3087 13:58:28.640022 [CATrainingPosCal] consider 2 rank data
3088 13:58:28.643273 u2DelayCellTimex100 = 270/100 ps
3089 13:58:28.646613 CA0 delay=37 (7~68),Diff = 3 PI (14 cell)
3090 13:58:28.649946 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3091 13:58:28.656781 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3092 13:58:28.659961 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3093 13:58:28.663184 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3094 13:58:28.666590 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3095 13:58:28.666672
3096 13:58:28.670399 CA PerBit enable=1, Macro0, CA PI delay=34
3097 13:58:28.670481
3098 13:58:28.673049 [CBTSetCACLKResult] CA Dly = 34
3099 13:58:28.673130 CS Dly: 5 (0~38)
3100 13:58:28.673195
3101 13:58:28.676587 ----->DramcWriteLeveling(PI) begin...
3102 13:58:28.680115 ==
3103 13:58:28.682953 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 13:58:28.686568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 13:58:28.686650 ==
3106 13:58:28.689771 Write leveling (Byte 0): 24 => 24
3107 13:58:28.692775 Write leveling (Byte 1): 26 => 26
3108 13:58:28.696258 DramcWriteLeveling(PI) end<-----
3109 13:58:28.696339
3110 13:58:28.696437 ==
3111 13:58:28.699449 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 13:58:28.702847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 13:58:28.702928 ==
3114 13:58:28.706212 [Gating] SW mode calibration
3115 13:58:28.712926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3116 13:58:28.719623 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3117 13:58:28.723503 0 15 0 | B1->B0 | 3131 3333 | 1 1 | (1 1) (1 1)
3118 13:58:28.726407 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 13:58:28.730250 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 13:58:28.736079 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 13:58:28.739660 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 13:58:28.742810 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 13:58:28.749609 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3124 13:58:28.752660 0 15 28 | B1->B0 | 2929 2424 | 0 0 | (0 0) (1 0)
3125 13:58:28.756690 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 13:58:28.762641 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 13:58:28.766074 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 13:58:28.769888 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 13:58:28.776031 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 13:58:28.779730 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 13:58:28.783387 1 0 24 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
3132 13:58:28.789855 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
3133 13:58:28.792989 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 13:58:28.796222 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 13:58:28.803005 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 13:58:28.806074 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 13:58:28.809645 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 13:58:28.816592 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 13:58:28.819888 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3140 13:58:28.822450 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3141 13:58:28.828950 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 13:58:28.832568 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 13:58:28.836146 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 13:58:28.842221 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 13:58:28.846382 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 13:58:28.849052 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 13:58:28.855750 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 13:58:28.858870 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 13:58:28.862392 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 13:58:28.869216 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 13:58:28.872293 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 13:58:28.875959 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 13:58:28.882817 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 13:58:28.885933 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 13:58:28.889418 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3156 13:58:28.892692 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3157 13:58:28.898769 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 13:58:28.902519 Total UI for P1: 0, mck2ui 16
3159 13:58:28.905759 best dqsien dly found for B0: ( 1, 3, 26)
3160 13:58:28.909113 Total UI for P1: 0, mck2ui 16
3161 13:58:28.912314 best dqsien dly found for B1: ( 1, 3, 28)
3162 13:58:28.915739 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3163 13:58:28.918867 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3164 13:58:28.918947
3165 13:58:28.922224 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3166 13:58:28.925187 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3167 13:58:28.928727 [Gating] SW calibration Done
3168 13:58:28.928823 ==
3169 13:58:28.932267 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 13:58:28.935123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 13:58:28.935224 ==
3172 13:58:28.938806 RX Vref Scan: 0
3173 13:58:28.938879
3174 13:58:28.941704 RX Vref 0 -> 0, step: 1
3175 13:58:28.941778
3176 13:58:28.941839 RX Delay -40 -> 252, step: 8
3177 13:58:28.948459 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3178 13:58:28.952023 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3179 13:58:28.955206 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3180 13:58:28.958244 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3181 13:58:28.962080 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3182 13:58:28.969037 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3183 13:58:28.971843 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3184 13:58:28.975802 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3185 13:58:28.978473 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3186 13:58:28.981855 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3187 13:58:28.988440 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3188 13:58:28.991827 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3189 13:58:28.994987 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3190 13:58:28.998045 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3191 13:58:29.001613 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3192 13:58:29.008044 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3193 13:58:29.008125 ==
3194 13:58:29.012434 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 13:58:29.015033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 13:58:29.015131 ==
3197 13:58:29.015195 DQS Delay:
3198 13:58:29.018082 DQS0 = 0, DQS1 = 0
3199 13:58:29.018163 DQM Delay:
3200 13:58:29.022282 DQM0 = 115, DQM1 = 112
3201 13:58:29.022362 DQ Delay:
3202 13:58:29.025125 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3203 13:58:29.028065 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3204 13:58:29.031458 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3205 13:58:29.034554 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3206 13:58:29.034637
3207 13:58:29.038725
3208 13:58:29.038806 ==
3209 13:58:29.041449 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 13:58:29.045180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 13:58:29.045262 ==
3212 13:58:29.045326
3213 13:58:29.045385
3214 13:58:29.047971 TX Vref Scan disable
3215 13:58:29.048054 == TX Byte 0 ==
3216 13:58:29.054437 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3217 13:58:29.057945 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3218 13:58:29.058028 == TX Byte 1 ==
3219 13:58:29.064608 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3220 13:58:29.069145 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3221 13:58:29.069226 ==
3222 13:58:29.071329 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 13:58:29.074691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 13:58:29.074775 ==
3225 13:58:29.087022 TX Vref=22, minBit 3, minWin=24, winSum=404
3226 13:58:29.089953 TX Vref=24, minBit 2, minWin=25, winSum=410
3227 13:58:29.093744 TX Vref=26, minBit 3, minWin=25, winSum=416
3228 13:58:29.096605 TX Vref=28, minBit 9, minWin=24, winSum=421
3229 13:58:29.100384 TX Vref=30, minBit 2, minWin=25, winSum=422
3230 13:58:29.107198 TX Vref=32, minBit 9, minWin=24, winSum=423
3231 13:58:29.110330 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 30
3232 13:58:29.110415
3233 13:58:29.113406 Final TX Range 1 Vref 30
3234 13:58:29.113477
3235 13:58:29.113537 ==
3236 13:58:29.116458 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 13:58:29.119971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 13:58:29.120045 ==
3239 13:58:29.123425
3240 13:58:29.123507
3241 13:58:29.123571 TX Vref Scan disable
3242 13:58:29.127257 == TX Byte 0 ==
3243 13:58:29.129945 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3244 13:58:29.133104 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3245 13:58:29.136361 == TX Byte 1 ==
3246 13:58:29.139677 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3247 13:58:29.143457 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3248 13:58:29.146970
3249 13:58:29.147051 [DATLAT]
3250 13:58:29.147117 Freq=1200, CH1 RK0
3251 13:58:29.147176
3252 13:58:29.149890 DATLAT Default: 0xd
3253 13:58:29.149971 0, 0xFFFF, sum = 0
3254 13:58:29.153628 1, 0xFFFF, sum = 0
3255 13:58:29.153710 2, 0xFFFF, sum = 0
3256 13:58:29.156366 3, 0xFFFF, sum = 0
3257 13:58:29.156449 4, 0xFFFF, sum = 0
3258 13:58:29.159957 5, 0xFFFF, sum = 0
3259 13:58:29.160056 6, 0xFFFF, sum = 0
3260 13:58:29.163328 7, 0xFFFF, sum = 0
3261 13:58:29.166372 8, 0xFFFF, sum = 0
3262 13:58:29.166455 9, 0xFFFF, sum = 0
3263 13:58:29.170370 10, 0xFFFF, sum = 0
3264 13:58:29.170452 11, 0xFFFF, sum = 0
3265 13:58:29.173153 12, 0x0, sum = 1
3266 13:58:29.173236 13, 0x0, sum = 2
3267 13:58:29.176538 14, 0x0, sum = 3
3268 13:58:29.176622 15, 0x0, sum = 4
3269 13:58:29.176690 best_step = 13
3270 13:58:29.176765
3271 13:58:29.179678 ==
3272 13:58:29.183105 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 13:58:29.186276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 13:58:29.186357 ==
3275 13:58:29.186422 RX Vref Scan: 1
3276 13:58:29.186481
3277 13:58:29.189641 Set Vref Range= 32 -> 127
3278 13:58:29.189722
3279 13:58:29.193477 RX Vref 32 -> 127, step: 1
3280 13:58:29.193558
3281 13:58:29.196670 RX Delay -13 -> 252, step: 4
3282 13:58:29.196751
3283 13:58:29.199388 Set Vref, RX VrefLevel [Byte0]: 32
3284 13:58:29.202932 [Byte1]: 32
3285 13:58:29.203014
3286 13:58:29.206235 Set Vref, RX VrefLevel [Byte0]: 33
3287 13:58:29.210220 [Byte1]: 33
3288 13:58:29.212608
3289 13:58:29.212689 Set Vref, RX VrefLevel [Byte0]: 34
3290 13:58:29.216389 [Byte1]: 34
3291 13:58:29.220856
3292 13:58:29.220936 Set Vref, RX VrefLevel [Byte0]: 35
3293 13:58:29.224219 [Byte1]: 35
3294 13:58:29.228704
3295 13:58:29.228785 Set Vref, RX VrefLevel [Byte0]: 36
3296 13:58:29.232140 [Byte1]: 36
3297 13:58:29.236536
3298 13:58:29.236616 Set Vref, RX VrefLevel [Byte0]: 37
3299 13:58:29.239623 [Byte1]: 37
3300 13:58:29.244418
3301 13:58:29.244498 Set Vref, RX VrefLevel [Byte0]: 38
3302 13:58:29.247940 [Byte1]: 38
3303 13:58:29.252588
3304 13:58:29.252667 Set Vref, RX VrefLevel [Byte0]: 39
3305 13:58:29.255721 [Byte1]: 39
3306 13:58:29.260201
3307 13:58:29.260281 Set Vref, RX VrefLevel [Byte0]: 40
3308 13:58:29.263702 [Byte1]: 40
3309 13:58:29.268140
3310 13:58:29.268251 Set Vref, RX VrefLevel [Byte0]: 41
3311 13:58:29.271118 [Byte1]: 41
3312 13:58:29.275665
3313 13:58:29.275740 Set Vref, RX VrefLevel [Byte0]: 42
3314 13:58:29.279154 [Byte1]: 42
3315 13:58:29.283488
3316 13:58:29.283568 Set Vref, RX VrefLevel [Byte0]: 43
3317 13:58:29.287073 [Byte1]: 43
3318 13:58:29.291824
3319 13:58:29.291930 Set Vref, RX VrefLevel [Byte0]: 44
3320 13:58:29.295265 [Byte1]: 44
3321 13:58:29.299635
3322 13:58:29.299714 Set Vref, RX VrefLevel [Byte0]: 45
3323 13:58:29.303667 [Byte1]: 45
3324 13:58:29.307547
3325 13:58:29.307626 Set Vref, RX VrefLevel [Byte0]: 46
3326 13:58:29.311084 [Byte1]: 46
3327 13:58:29.315596
3328 13:58:29.315678 Set Vref, RX VrefLevel [Byte0]: 47
3329 13:58:29.318670 [Byte1]: 47
3330 13:58:29.323097
3331 13:58:29.323194 Set Vref, RX VrefLevel [Byte0]: 48
3332 13:58:29.326552 [Byte1]: 48
3333 13:58:29.331258
3334 13:58:29.331338 Set Vref, RX VrefLevel [Byte0]: 49
3335 13:58:29.334257 [Byte1]: 49
3336 13:58:29.338854
3337 13:58:29.338936 Set Vref, RX VrefLevel [Byte0]: 50
3338 13:58:29.342200 [Byte1]: 50
3339 13:58:29.347108
3340 13:58:29.347189 Set Vref, RX VrefLevel [Byte0]: 51
3341 13:58:29.350157 [Byte1]: 51
3342 13:58:29.354571
3343 13:58:29.354651 Set Vref, RX VrefLevel [Byte0]: 52
3344 13:58:29.358224 [Byte1]: 52
3345 13:58:29.362928
3346 13:58:29.363008 Set Vref, RX VrefLevel [Byte0]: 53
3347 13:58:29.366722 [Byte1]: 53
3348 13:58:29.370529
3349 13:58:29.370610 Set Vref, RX VrefLevel [Byte0]: 54
3350 13:58:29.373821 [Byte1]: 54
3351 13:58:29.378380
3352 13:58:29.378461 Set Vref, RX VrefLevel [Byte0]: 55
3353 13:58:29.381598 [Byte1]: 55
3354 13:58:29.386103
3355 13:58:29.386184 Set Vref, RX VrefLevel [Byte0]: 56
3356 13:58:29.389860 [Byte1]: 56
3357 13:58:29.393954
3358 13:58:29.394034 Set Vref, RX VrefLevel [Byte0]: 57
3359 13:58:29.397218 [Byte1]: 57
3360 13:58:29.401849
3361 13:58:29.401924 Set Vref, RX VrefLevel [Byte0]: 58
3362 13:58:29.405257 [Byte1]: 58
3363 13:58:29.409651
3364 13:58:29.409726 Set Vref, RX VrefLevel [Byte0]: 59
3365 13:58:29.413021 [Byte1]: 59
3366 13:58:29.417814
3367 13:58:29.417891 Set Vref, RX VrefLevel [Byte0]: 60
3368 13:58:29.421240 [Byte1]: 60
3369 13:58:29.425721
3370 13:58:29.425793 Set Vref, RX VrefLevel [Byte0]: 61
3371 13:58:29.429018 [Byte1]: 61
3372 13:58:29.433795
3373 13:58:29.433876 Set Vref, RX VrefLevel [Byte0]: 62
3374 13:58:29.437007 [Byte1]: 62
3375 13:58:29.441790
3376 13:58:29.441912 Set Vref, RX VrefLevel [Byte0]: 63
3377 13:58:29.445142 [Byte1]: 63
3378 13:58:29.449395
3379 13:58:29.449476 Set Vref, RX VrefLevel [Byte0]: 64
3380 13:58:29.452691 [Byte1]: 64
3381 13:58:29.457265
3382 13:58:29.457346 Final RX Vref Byte 0 = 50 to rank0
3383 13:58:29.460527 Final RX Vref Byte 1 = 54 to rank0
3384 13:58:29.464139 Final RX Vref Byte 0 = 50 to rank1
3385 13:58:29.467258 Final RX Vref Byte 1 = 54 to rank1==
3386 13:58:29.470392 Dram Type= 6, Freq= 0, CH_1, rank 0
3387 13:58:29.477098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3388 13:58:29.477181 ==
3389 13:58:29.477264 DQS Delay:
3390 13:58:29.477370 DQS0 = 0, DQS1 = 0
3391 13:58:29.480284 DQM Delay:
3392 13:58:29.480365 DQM0 = 115, DQM1 = 113
3393 13:58:29.483867 DQ Delay:
3394 13:58:29.487160 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3395 13:58:29.490490 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3396 13:58:29.493390 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =108
3397 13:58:29.496795 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3398 13:58:29.496877
3399 13:58:29.496942
3400 13:58:29.507166 [DQSOSCAuto] RK0, (LSB)MR18= 0xf703, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3401 13:58:29.507249 CH1 RK0: MR19=304, MR18=F703
3402 13:58:29.513376 CH1_RK0: MR19=0x304, MR18=0xF703, DQSOSC=408, MR23=63, INC=39, DEC=26
3403 13:58:29.513457
3404 13:58:29.517055 ----->DramcWriteLeveling(PI) begin...
3405 13:58:29.517138 ==
3406 13:58:29.520648 Dram Type= 6, Freq= 0, CH_1, rank 1
3407 13:58:29.526647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3408 13:58:29.526729 ==
3409 13:58:29.530114 Write leveling (Byte 0): 26 => 26
3410 13:58:29.530195 Write leveling (Byte 1): 29 => 29
3411 13:58:29.533824 DramcWriteLeveling(PI) end<-----
3412 13:58:29.533906
3413 13:58:29.536513 ==
3414 13:58:29.536594 Dram Type= 6, Freq= 0, CH_1, rank 1
3415 13:58:29.543290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3416 13:58:29.543372 ==
3417 13:58:29.547143 [Gating] SW mode calibration
3418 13:58:29.553566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3419 13:58:29.556704 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3420 13:58:29.563300 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3421 13:58:29.566608 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3422 13:58:29.570380 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3423 13:58:29.576832 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3424 13:58:29.580155 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 13:58:29.583354 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3426 13:58:29.589831 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
3427 13:58:29.592920 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
3428 13:58:29.596710 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3429 13:58:29.603042 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3430 13:58:29.606511 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3431 13:58:29.609268 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3432 13:58:29.615851 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 13:58:29.619315 1 0 20 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
3434 13:58:29.622729 1 0 24 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
3435 13:58:29.629911 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3436 13:58:29.632965 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3437 13:58:29.635945 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3438 13:58:29.642668 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3439 13:58:29.645773 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3440 13:58:29.649248 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 13:58:29.656239 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3442 13:58:29.658992 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3443 13:58:29.662317 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3444 13:58:29.669098 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 13:58:29.672397 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 13:58:29.675760 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 13:58:29.682470 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 13:58:29.686589 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 13:58:29.689001 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 13:58:29.695600 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 13:58:29.698508 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 13:58:29.701628 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 13:58:29.708690 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 13:58:29.712335 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 13:58:29.715168 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 13:58:29.721841 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 13:58:29.724678 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3458 13:58:29.728213 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3459 13:58:29.734790 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3460 13:58:29.734872 Total UI for P1: 0, mck2ui 16
3461 13:58:29.741172 best dqsien dly found for B0: ( 1, 3, 22)
3462 13:58:29.744736 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 13:58:29.747841 Total UI for P1: 0, mck2ui 16
3464 13:58:29.751076 best dqsien dly found for B1: ( 1, 3, 26)
3465 13:58:29.754417 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3466 13:58:29.757732 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3467 13:58:29.757832
3468 13:58:29.761361 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3469 13:58:29.764509 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3470 13:58:29.768489 [Gating] SW calibration Done
3471 13:58:29.768570 ==
3472 13:58:29.771352 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 13:58:29.774745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 13:58:29.777648 ==
3475 13:58:29.777731 RX Vref Scan: 0
3476 13:58:29.777797
3477 13:58:29.780913 RX Vref 0 -> 0, step: 1
3478 13:58:29.780994
3479 13:58:29.784248 RX Delay -40 -> 252, step: 8
3480 13:58:29.787499 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3481 13:58:29.791063 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3482 13:58:29.794115 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3483 13:58:29.797641 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3484 13:58:29.804085 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3485 13:58:29.807348 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3486 13:58:29.810602 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3487 13:58:29.814060 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3488 13:58:29.817217 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3489 13:58:29.823590 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3490 13:58:29.827070 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3491 13:58:29.830057 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3492 13:58:29.833840 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3493 13:58:29.840452 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3494 13:58:29.843213 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3495 13:58:29.846560 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3496 13:58:29.846650 ==
3497 13:58:29.849876 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 13:58:29.853290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 13:58:29.853370 ==
3500 13:58:29.856803 DQS Delay:
3501 13:58:29.856883 DQS0 = 0, DQS1 = 0
3502 13:58:29.859572 DQM Delay:
3503 13:58:29.859650 DQM0 = 114, DQM1 = 111
3504 13:58:29.863007 DQ Delay:
3505 13:58:29.866237 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3506 13:58:29.870402 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =111
3507 13:58:29.872983 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3508 13:58:29.876250 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3509 13:58:29.876331
3510 13:58:29.876396
3511 13:58:29.876454 ==
3512 13:58:29.879743 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 13:58:29.882893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 13:58:29.882965 ==
3515 13:58:29.883033
3516 13:58:29.883096
3517 13:58:29.886293 TX Vref Scan disable
3518 13:58:29.889854 == TX Byte 0 ==
3519 13:58:29.892677 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3520 13:58:29.896043 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3521 13:58:29.899657 == TX Byte 1 ==
3522 13:58:29.903247 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3523 13:58:29.906119 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3524 13:58:29.906193 ==
3525 13:58:29.909303 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 13:58:29.915990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 13:58:29.916069 ==
3528 13:58:29.926529 TX Vref=22, minBit 1, minWin=25, winSum=417
3529 13:58:29.930002 TX Vref=24, minBit 13, minWin=25, winSum=421
3530 13:58:29.933385 TX Vref=26, minBit 1, minWin=26, winSum=428
3531 13:58:29.936670 TX Vref=28, minBit 1, minWin=26, winSum=429
3532 13:58:29.940118 TX Vref=30, minBit 1, minWin=26, winSum=431
3533 13:58:29.946976 TX Vref=32, minBit 2, minWin=26, winSum=428
3534 13:58:29.949472 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3535 13:58:29.949547
3536 13:58:29.953005 Final TX Range 1 Vref 30
3537 13:58:29.953082
3538 13:58:29.953143 ==
3539 13:58:29.956060 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 13:58:29.959671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 13:58:29.962864 ==
3542 13:58:29.962941
3543 13:58:29.963006
3544 13:58:29.963072 TX Vref Scan disable
3545 13:58:29.966430 == TX Byte 0 ==
3546 13:58:29.969383 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3547 13:58:29.975799 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3548 13:58:29.975874 == TX Byte 1 ==
3549 13:58:29.979969 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3550 13:58:29.985863 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3551 13:58:29.985936
3552 13:58:29.986005 [DATLAT]
3553 13:58:29.986067 Freq=1200, CH1 RK1
3554 13:58:29.986145
3555 13:58:29.988932 DATLAT Default: 0xd
3556 13:58:29.992331 0, 0xFFFF, sum = 0
3557 13:58:29.992407 1, 0xFFFF, sum = 0
3558 13:58:29.995665 2, 0xFFFF, sum = 0
3559 13:58:29.995743 3, 0xFFFF, sum = 0
3560 13:58:30.000361 4, 0xFFFF, sum = 0
3561 13:58:30.000440 5, 0xFFFF, sum = 0
3562 13:58:30.002473 6, 0xFFFF, sum = 0
3563 13:58:30.002555 7, 0xFFFF, sum = 0
3564 13:58:30.005889 8, 0xFFFF, sum = 0
3565 13:58:30.006005 9, 0xFFFF, sum = 0
3566 13:58:30.009060 10, 0xFFFF, sum = 0
3567 13:58:30.009141 11, 0xFFFF, sum = 0
3568 13:58:30.012676 12, 0x0, sum = 1
3569 13:58:30.012760 13, 0x0, sum = 2
3570 13:58:30.015669 14, 0x0, sum = 3
3571 13:58:30.015754 15, 0x0, sum = 4
3572 13:58:30.019560 best_step = 13
3573 13:58:30.019641
3574 13:58:30.019702 ==
3575 13:58:30.022721 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 13:58:30.025969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 13:58:30.026043 ==
3578 13:58:30.028942 RX Vref Scan: 0
3579 13:58:30.029042
3580 13:58:30.029139 RX Vref 0 -> 0, step: 1
3581 13:58:30.029201
3582 13:58:30.032100 RX Delay -13 -> 252, step: 4
3583 13:58:30.039109 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3584 13:58:30.042213 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3585 13:58:30.045685 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3586 13:58:30.048569 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3587 13:58:30.052283 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3588 13:58:30.058725 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3589 13:58:30.062280 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3590 13:58:30.065102 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3591 13:58:30.068691 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3592 13:58:30.071862 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3593 13:58:30.078718 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3594 13:58:30.081561 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3595 13:58:30.085167 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3596 13:58:30.088314 iDelay=195, Bit 13, Center 120 (55 ~ 186) 132
3597 13:58:30.095088 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3598 13:58:30.098299 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3599 13:58:30.098380 ==
3600 13:58:30.101763 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 13:58:30.104723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 13:58:30.104805 ==
3603 13:58:30.107850 DQS Delay:
3604 13:58:30.107971 DQS0 = 0, DQS1 = 0
3605 13:58:30.108052 DQM Delay:
3606 13:58:30.111342 DQM0 = 114, DQM1 = 112
3607 13:58:30.111423 DQ Delay:
3608 13:58:30.114825 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3609 13:58:30.117789 DQ4 =112, DQ5 =124, DQ6 =122, DQ7 =112
3610 13:58:30.121157 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3611 13:58:30.127619 DQ12 =122, DQ13 =120, DQ14 =118, DQ15 =120
3612 13:58:30.127700
3613 13:58:30.127764
3614 13:58:30.134608 [DQSOSCAuto] RK1, (LSB)MR18= 0xfd10, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 411 ps
3615 13:58:30.137982 CH1 RK1: MR19=304, MR18=FD10
3616 13:58:30.144504 CH1_RK1: MR19=0x304, MR18=0xFD10, DQSOSC=403, MR23=63, INC=40, DEC=26
3617 13:58:30.147788 [RxdqsGatingPostProcess] freq 1200
3618 13:58:30.151089 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3619 13:58:30.154354 best DQS0 dly(2T, 0.5T) = (0, 11)
3620 13:58:30.157660 best DQS1 dly(2T, 0.5T) = (0, 11)
3621 13:58:30.160630 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3622 13:58:30.164258 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3623 13:58:30.167395 best DQS0 dly(2T, 0.5T) = (0, 11)
3624 13:58:30.170539 best DQS1 dly(2T, 0.5T) = (0, 11)
3625 13:58:30.174070 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3626 13:58:30.177625 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3627 13:58:30.180437 Pre-setting of DQS Precalculation
3628 13:58:30.184388 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3629 13:58:30.193677 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3630 13:58:30.200410 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3631 13:58:30.200492
3632 13:58:30.200556
3633 13:58:30.203933 [Calibration Summary] 2400 Mbps
3634 13:58:30.204029 CH 0, Rank 0
3635 13:58:30.206955 SW Impedance : PASS
3636 13:58:30.207036 DUTY Scan : NO K
3637 13:58:30.210458 ZQ Calibration : PASS
3638 13:58:30.213384 Jitter Meter : NO K
3639 13:58:30.213465 CBT Training : PASS
3640 13:58:30.216865 Write leveling : PASS
3641 13:58:30.220579 RX DQS gating : PASS
3642 13:58:30.220661 RX DQ/DQS(RDDQC) : PASS
3643 13:58:30.223284 TX DQ/DQS : PASS
3644 13:58:30.226954 RX DATLAT : PASS
3645 13:58:30.227035 RX DQ/DQS(Engine): PASS
3646 13:58:30.230091 TX OE : NO K
3647 13:58:30.230172 All Pass.
3648 13:58:30.230236
3649 13:58:30.233614 CH 0, Rank 1
3650 13:58:30.233695 SW Impedance : PASS
3651 13:58:30.236822 DUTY Scan : NO K
3652 13:58:30.239849 ZQ Calibration : PASS
3653 13:58:30.240074 Jitter Meter : NO K
3654 13:58:30.243736 CBT Training : PASS
3655 13:58:30.246929 Write leveling : PASS
3656 13:58:30.247010 RX DQS gating : PASS
3657 13:58:30.250130 RX DQ/DQS(RDDQC) : PASS
3658 13:58:30.253417 TX DQ/DQS : PASS
3659 13:58:30.253499 RX DATLAT : PASS
3660 13:58:30.256576 RX DQ/DQS(Engine): PASS
3661 13:58:30.260095 TX OE : NO K
3662 13:58:30.260176 All Pass.
3663 13:58:30.260240
3664 13:58:30.260300 CH 1, Rank 0
3665 13:58:30.263265 SW Impedance : PASS
3666 13:58:30.266498 DUTY Scan : NO K
3667 13:58:30.266579 ZQ Calibration : PASS
3668 13:58:30.269656 Jitter Meter : NO K
3669 13:58:30.269737 CBT Training : PASS
3670 13:58:30.273371 Write leveling : PASS
3671 13:58:30.276442 RX DQS gating : PASS
3672 13:58:30.276538 RX DQ/DQS(RDDQC) : PASS
3673 13:58:30.280013 TX DQ/DQS : PASS
3674 13:58:30.282729 RX DATLAT : PASS
3675 13:58:30.282825 RX DQ/DQS(Engine): PASS
3676 13:58:30.286087 TX OE : NO K
3677 13:58:30.286168 All Pass.
3678 13:58:30.286232
3679 13:58:30.290039 CH 1, Rank 1
3680 13:58:30.290120 SW Impedance : PASS
3681 13:58:30.292891 DUTY Scan : NO K
3682 13:58:30.296094 ZQ Calibration : PASS
3683 13:58:30.296175 Jitter Meter : NO K
3684 13:58:30.299764 CBT Training : PASS
3685 13:58:30.303034 Write leveling : PASS
3686 13:58:30.303114 RX DQS gating : PASS
3687 13:58:30.306269 RX DQ/DQS(RDDQC) : PASS
3688 13:58:30.309281 TX DQ/DQS : PASS
3689 13:58:30.309363 RX DATLAT : PASS
3690 13:58:30.312652 RX DQ/DQS(Engine): PASS
3691 13:58:30.316119 TX OE : NO K
3692 13:58:30.316217 All Pass.
3693 13:58:30.316315
3694 13:58:30.316442 DramC Write-DBI off
3695 13:58:30.319008 PER_BANK_REFRESH: Hybrid Mode
3696 13:58:30.322885 TX_TRACKING: ON
3697 13:58:30.328869 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3698 13:58:30.336080 [FAST_K] Save calibration result to emmc
3699 13:58:30.338992 dramc_set_vcore_voltage set vcore to 650000
3700 13:58:30.339073 Read voltage for 600, 5
3701 13:58:30.342095 Vio18 = 0
3702 13:58:30.342202 Vcore = 650000
3703 13:58:30.342269 Vdram = 0
3704 13:58:30.345578 Vddq = 0
3705 13:58:30.345690 Vmddr = 0
3706 13:58:30.348868 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3707 13:58:30.355467 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3708 13:58:30.358760 MEM_TYPE=3, freq_sel=19
3709 13:58:30.361903 sv_algorithm_assistance_LP4_1600
3710 13:58:30.365451 ============ PULL DRAM RESETB DOWN ============
3711 13:58:30.368718 ========== PULL DRAM RESETB DOWN end =========
3712 13:58:30.375724 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3713 13:58:30.379116 ===================================
3714 13:58:30.379197 LPDDR4 DRAM CONFIGURATION
3715 13:58:30.381624 ===================================
3716 13:58:30.385056 EX_ROW_EN[0] = 0x0
3717 13:58:30.385138 EX_ROW_EN[1] = 0x0
3718 13:58:30.388696 LP4Y_EN = 0x0
3719 13:58:30.392030 WORK_FSP = 0x0
3720 13:58:30.392129 WL = 0x2
3721 13:58:30.394958 RL = 0x2
3722 13:58:30.395038 BL = 0x2
3723 13:58:30.398141 RPST = 0x0
3724 13:58:30.398221 RD_PRE = 0x0
3725 13:58:30.401842 WR_PRE = 0x1
3726 13:58:30.401924 WR_PST = 0x0
3727 13:58:30.404865 DBI_WR = 0x0
3728 13:58:30.404946 DBI_RD = 0x0
3729 13:58:30.408076 OTF = 0x1
3730 13:58:30.411458 ===================================
3731 13:58:30.415236 ===================================
3732 13:58:30.415318 ANA top config
3733 13:58:30.418407 ===================================
3734 13:58:30.421911 DLL_ASYNC_EN = 0
3735 13:58:30.425338 ALL_SLAVE_EN = 1
3736 13:58:30.425419 NEW_RANK_MODE = 1
3737 13:58:30.429229 DLL_IDLE_MODE = 1
3738 13:58:30.431386 LP45_APHY_COMB_EN = 1
3739 13:58:30.434659 TX_ODT_DIS = 1
3740 13:58:30.438487 NEW_8X_MODE = 1
3741 13:58:30.441325 ===================================
3742 13:58:30.444836 ===================================
3743 13:58:30.447738 data_rate = 1200
3744 13:58:30.447818 CKR = 1
3745 13:58:30.451354 DQ_P2S_RATIO = 8
3746 13:58:30.454825 ===================================
3747 13:58:30.457887 CA_P2S_RATIO = 8
3748 13:58:30.461292 DQ_CA_OPEN = 0
3749 13:58:30.464241 DQ_SEMI_OPEN = 0
3750 13:58:30.467954 CA_SEMI_OPEN = 0
3751 13:58:30.468060 CA_FULL_RATE = 0
3752 13:58:30.471136 DQ_CKDIV4_EN = 1
3753 13:58:30.474289 CA_CKDIV4_EN = 1
3754 13:58:30.477512 CA_PREDIV_EN = 0
3755 13:58:30.481076 PH8_DLY = 0
3756 13:58:30.484679 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3757 13:58:30.484757 DQ_AAMCK_DIV = 4
3758 13:58:30.487280 CA_AAMCK_DIV = 4
3759 13:58:30.490805 CA_ADMCK_DIV = 4
3760 13:58:30.494102 DQ_TRACK_CA_EN = 0
3761 13:58:30.497107 CA_PICK = 600
3762 13:58:30.501275 CA_MCKIO = 600
3763 13:58:30.501348 MCKIO_SEMI = 0
3764 13:58:30.504048 PLL_FREQ = 2288
3765 13:58:30.507341 DQ_UI_PI_RATIO = 32
3766 13:58:30.510414 CA_UI_PI_RATIO = 0
3767 13:58:30.513832 ===================================
3768 13:58:30.517073 ===================================
3769 13:58:30.520422 memory_type:LPDDR4
3770 13:58:30.523337 GP_NUM : 10
3771 13:58:30.523433 SRAM_EN : 1
3772 13:58:30.527321 MD32_EN : 0
3773 13:58:30.530224 ===================================
3774 13:58:30.530315 [ANA_INIT] >>>>>>>>>>>>>>
3775 13:58:30.533279 <<<<<< [CONFIGURE PHASE]: ANA_TX
3776 13:58:30.536983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3777 13:58:30.540391 ===================================
3778 13:58:30.544262 data_rate = 1200,PCW = 0X5800
3779 13:58:30.546703 ===================================
3780 13:58:30.550655 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3781 13:58:30.557046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3782 13:58:30.560408 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3783 13:58:30.567185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3784 13:58:30.570394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3785 13:58:30.573594 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3786 13:58:30.576937 [ANA_INIT] flow start
3787 13:58:30.577018 [ANA_INIT] PLL >>>>>>>>
3788 13:58:30.580187 [ANA_INIT] PLL <<<<<<<<
3789 13:58:30.583351 [ANA_INIT] MIDPI >>>>>>>>
3790 13:58:30.583432 [ANA_INIT] MIDPI <<<<<<<<
3791 13:58:30.586749 [ANA_INIT] DLL >>>>>>>>
3792 13:58:30.589974 [ANA_INIT] flow end
3793 13:58:30.593371 ============ LP4 DIFF to SE enter ============
3794 13:58:30.597052 ============ LP4 DIFF to SE exit ============
3795 13:58:30.600061 [ANA_INIT] <<<<<<<<<<<<<
3796 13:58:30.603162 [Flow] Enable top DCM control >>>>>
3797 13:58:30.606396 [Flow] Enable top DCM control <<<<<
3798 13:58:30.609806 Enable DLL master slave shuffle
3799 13:58:30.613365 ==============================================================
3800 13:58:30.616444 Gating Mode config
3801 13:58:30.622871 ==============================================================
3802 13:58:30.622954 Config description:
3803 13:58:30.632580 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3804 13:58:30.639114 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3805 13:58:30.645967 SELPH_MODE 0: By rank 1: By Phase
3806 13:58:30.649366 ==============================================================
3807 13:58:30.652347 GAT_TRACK_EN = 1
3808 13:58:30.655737 RX_GATING_MODE = 2
3809 13:58:30.659888 RX_GATING_TRACK_MODE = 2
3810 13:58:30.662300 SELPH_MODE = 1
3811 13:58:30.665637 PICG_EARLY_EN = 1
3812 13:58:30.669130 VALID_LAT_VALUE = 1
3813 13:58:30.672482 ==============================================================
3814 13:58:30.675936 Enter into Gating configuration >>>>
3815 13:58:30.679015 Exit from Gating configuration <<<<
3816 13:58:30.682642 Enter into DVFS_PRE_config >>>>>
3817 13:58:30.695286 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3818 13:58:30.698462 Exit from DVFS_PRE_config <<<<<
3819 13:58:30.702079 Enter into PICG configuration >>>>
3820 13:58:30.705687 Exit from PICG configuration <<<<
3821 13:58:30.705768 [RX_INPUT] configuration >>>>>
3822 13:58:30.709279 [RX_INPUT] configuration <<<<<
3823 13:58:30.715037 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3824 13:58:30.718590 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3825 13:58:30.726122 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3826 13:58:30.731391 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3827 13:58:30.737923 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3828 13:58:30.744428 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3829 13:58:30.747875 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3830 13:58:30.751228 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3831 13:58:30.758383 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3832 13:58:30.761140 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3833 13:58:30.764662 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3834 13:58:30.771224 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3835 13:58:30.774817 ===================================
3836 13:58:30.774899 LPDDR4 DRAM CONFIGURATION
3837 13:58:30.777884 ===================================
3838 13:58:30.780930 EX_ROW_EN[0] = 0x0
3839 13:58:30.784083 EX_ROW_EN[1] = 0x0
3840 13:58:30.784167 LP4Y_EN = 0x0
3841 13:58:30.787783 WORK_FSP = 0x0
3842 13:58:30.787893 WL = 0x2
3843 13:58:30.791166 RL = 0x2
3844 13:58:30.791283 BL = 0x2
3845 13:58:30.794172 RPST = 0x0
3846 13:58:30.794254 RD_PRE = 0x0
3847 13:58:30.797110 WR_PRE = 0x1
3848 13:58:30.797192 WR_PST = 0x0
3849 13:58:30.801132 DBI_WR = 0x0
3850 13:58:30.801205 DBI_RD = 0x0
3851 13:58:30.804058 OTF = 0x1
3852 13:58:30.807601 ===================================
3853 13:58:30.810942 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3854 13:58:30.814414 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3855 13:58:30.820400 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3856 13:58:30.823832 ===================================
3857 13:58:30.823923 LPDDR4 DRAM CONFIGURATION
3858 13:58:30.827423 ===================================
3859 13:58:30.830304 EX_ROW_EN[0] = 0x10
3860 13:58:30.834021 EX_ROW_EN[1] = 0x0
3861 13:58:30.834101 LP4Y_EN = 0x0
3862 13:58:30.836926 WORK_FSP = 0x0
3863 13:58:30.837007 WL = 0x2
3864 13:58:30.840221 RL = 0x2
3865 13:58:30.840303 BL = 0x2
3866 13:58:30.844113 RPST = 0x0
3867 13:58:30.844194 RD_PRE = 0x0
3868 13:58:30.846876 WR_PRE = 0x1
3869 13:58:30.846999 WR_PST = 0x0
3870 13:58:30.850095 DBI_WR = 0x0
3871 13:58:30.850176 DBI_RD = 0x0
3872 13:58:30.853258 OTF = 0x1
3873 13:58:30.856635 ===================================
3874 13:58:30.863501 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3875 13:58:30.866509 nWR fixed to 30
3876 13:58:30.870775 [ModeRegInit_LP4] CH0 RK0
3877 13:58:30.870857 [ModeRegInit_LP4] CH0 RK1
3878 13:58:30.873106 [ModeRegInit_LP4] CH1 RK0
3879 13:58:30.876472 [ModeRegInit_LP4] CH1 RK1
3880 13:58:30.876552 match AC timing 17
3881 13:58:30.883253 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3882 13:58:30.886761 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3883 13:58:30.889756 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3884 13:58:30.896340 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3885 13:58:30.899413 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3886 13:58:30.899507 ==
3887 13:58:30.902673 Dram Type= 6, Freq= 0, CH_0, rank 0
3888 13:58:30.906230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3889 13:58:30.906327 ==
3890 13:58:30.912977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3891 13:58:30.919062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3892 13:58:30.922560 [CA 0] Center 36 (6~67) winsize 62
3893 13:58:30.925651 [CA 1] Center 36 (6~67) winsize 62
3894 13:58:30.929350 [CA 2] Center 34 (4~65) winsize 62
3895 13:58:30.932269 [CA 3] Center 34 (3~65) winsize 63
3896 13:58:30.935648 [CA 4] Center 33 (3~64) winsize 62
3897 13:58:30.939027 [CA 5] Center 33 (3~64) winsize 62
3898 13:58:30.939147
3899 13:58:30.942783 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3900 13:58:30.942904
3901 13:58:30.946085 [CATrainingPosCal] consider 1 rank data
3902 13:58:30.948655 u2DelayCellTimex100 = 270/100 ps
3903 13:58:30.952360 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3904 13:58:30.955187 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3905 13:58:30.958647 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3906 13:58:30.962225 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3907 13:58:30.968982 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3908 13:58:30.971887 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3909 13:58:30.971991
3910 13:58:30.975606 CA PerBit enable=1, Macro0, CA PI delay=33
3911 13:58:30.975732
3912 13:58:30.978392 [CBTSetCACLKResult] CA Dly = 33
3913 13:58:30.978551 CS Dly: 4 (0~35)
3914 13:58:30.978616 ==
3915 13:58:30.981808 Dram Type= 6, Freq= 0, CH_0, rank 1
3916 13:58:30.988457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3917 13:58:30.988538 ==
3918 13:58:30.991432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3919 13:58:30.997978 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3920 13:58:31.001416 [CA 0] Center 36 (6~67) winsize 62
3921 13:58:31.005248 [CA 1] Center 36 (6~67) winsize 62
3922 13:58:31.008001 [CA 2] Center 34 (4~65) winsize 62
3923 13:58:31.011378 [CA 3] Center 34 (4~65) winsize 62
3924 13:58:31.015288 [CA 4] Center 34 (4~65) winsize 62
3925 13:58:31.018330 [CA 5] Center 33 (3~64) winsize 62
3926 13:58:31.018411
3927 13:58:31.021639 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3928 13:58:31.021735
3929 13:58:31.024418 [CATrainingPosCal] consider 2 rank data
3930 13:58:31.027640 u2DelayCellTimex100 = 270/100 ps
3931 13:58:31.031477 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3932 13:58:31.038272 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3933 13:58:31.040954 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3934 13:58:31.044253 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3935 13:58:31.047612 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3936 13:58:31.051334 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3937 13:58:31.051416
3938 13:58:31.054510 CA PerBit enable=1, Macro0, CA PI delay=33
3939 13:58:31.054591
3940 13:58:31.057740 [CBTSetCACLKResult] CA Dly = 33
3941 13:58:31.061185 CS Dly: 5 (0~37)
3942 13:58:31.061266
3943 13:58:31.064223 ----->DramcWriteLeveling(PI) begin...
3944 13:58:31.064305 ==
3945 13:58:31.067335 Dram Type= 6, Freq= 0, CH_0, rank 0
3946 13:58:31.070652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3947 13:58:31.070735 ==
3948 13:58:31.074376 Write leveling (Byte 0): 32 => 32
3949 13:58:31.077727 Write leveling (Byte 1): 31 => 31
3950 13:58:31.080803 DramcWriteLeveling(PI) end<-----
3951 13:58:31.080884
3952 13:58:31.080949 ==
3953 13:58:31.084825 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 13:58:31.087786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 13:58:31.087867 ==
3956 13:58:31.090777 [Gating] SW mode calibration
3957 13:58:31.097438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3958 13:58:31.103554 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3959 13:58:31.106984 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3960 13:58:31.110121 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3961 13:58:31.117187 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3962 13:58:31.119883 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3963 13:58:31.123199 0 9 16 | B1->B0 | 2f2f 2828 | 1 0 | (0 0) (0 0)
3964 13:58:31.130002 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3965 13:58:31.133015 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3966 13:58:31.136449 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 13:58:31.143546 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 13:58:31.146749 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 13:58:31.150039 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 13:58:31.156311 0 10 12 | B1->B0 | 2929 2f2f | 1 0 | (0 0) (0 0)
3971 13:58:31.160074 0 10 16 | B1->B0 | 3e3e 4141 | 0 0 | (0 0) (0 0)
3972 13:58:31.162905 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3973 13:58:31.169611 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3974 13:58:31.172744 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 13:58:31.176393 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 13:58:31.182861 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 13:58:31.186109 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 13:58:31.189892 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3979 13:58:31.195991 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3980 13:58:31.199198 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 13:58:31.202602 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 13:58:31.209408 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 13:58:31.212337 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 13:58:31.215876 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 13:58:31.222351 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 13:58:31.225409 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 13:58:31.228881 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 13:58:31.235293 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 13:58:31.238807 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 13:58:31.242306 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 13:58:31.248338 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 13:58:31.251700 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 13:58:31.258496 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 13:58:31.261997 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3995 13:58:31.265229 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 13:58:31.268204 Total UI for P1: 0, mck2ui 16
3997 13:58:31.271658 best dqsien dly found for B0: ( 0, 13, 12)
3998 13:58:31.275022 Total UI for P1: 0, mck2ui 16
3999 13:58:31.278180 best dqsien dly found for B1: ( 0, 13, 12)
4000 13:58:31.281699 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4001 13:58:31.285206 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4002 13:58:31.285306
4003 13:58:31.288232 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4004 13:58:31.294500 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4005 13:58:31.294574 [Gating] SW calibration Done
4006 13:58:31.298426 ==
4007 13:58:31.298496 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 13:58:31.305150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 13:58:31.305227 ==
4010 13:58:31.305296 RX Vref Scan: 0
4011 13:58:31.305358
4012 13:58:31.307883 RX Vref 0 -> 0, step: 1
4013 13:58:31.307975
4014 13:58:31.311258 RX Delay -230 -> 252, step: 16
4015 13:58:31.314432 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4016 13:58:31.317716 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4017 13:58:31.324410 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4018 13:58:31.327638 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4019 13:58:31.330820 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4020 13:58:31.334170 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4021 13:58:31.340632 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4022 13:58:31.344557 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4023 13:58:31.347070 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4024 13:58:31.351162 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4025 13:58:31.357212 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4026 13:58:31.360230 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4027 13:58:31.363639 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4028 13:58:31.366879 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4029 13:58:31.373415 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4030 13:58:31.376846 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4031 13:58:31.376932 ==
4032 13:58:31.379799 Dram Type= 6, Freq= 0, CH_0, rank 0
4033 13:58:31.383478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 13:58:31.383565 ==
4035 13:58:31.386697 DQS Delay:
4036 13:58:31.386769 DQS0 = 0, DQS1 = 0
4037 13:58:31.386836 DQM Delay:
4038 13:58:31.389909 DQM0 = 45, DQM1 = 35
4039 13:58:31.389982 DQ Delay:
4040 13:58:31.393286 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4041 13:58:31.396808 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4042 13:58:31.399682 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4043 13:58:31.403223 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4044 13:58:31.403299
4045 13:58:31.403369
4046 13:58:31.403432 ==
4047 13:58:31.407107 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 13:58:31.412965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 13:58:31.413043 ==
4050 13:58:31.413107
4051 13:58:31.413198
4052 13:58:31.413258 TX Vref Scan disable
4053 13:58:31.417439 == TX Byte 0 ==
4054 13:58:31.420255 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4055 13:58:31.427224 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4056 13:58:31.427298 == TX Byte 1 ==
4057 13:58:31.429881 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4058 13:58:31.436599 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4059 13:58:31.436680 ==
4060 13:58:31.439564 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 13:58:31.442867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 13:58:31.442955 ==
4063 13:58:31.443021
4064 13:58:31.443081
4065 13:58:31.446322 TX Vref Scan disable
4066 13:58:31.449735 == TX Byte 0 ==
4067 13:58:31.452911 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4068 13:58:31.456118 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4069 13:58:31.459254 == TX Byte 1 ==
4070 13:58:31.463155 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4071 13:58:31.466772 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4072 13:58:31.466856
4073 13:58:31.469615 [DATLAT]
4074 13:58:31.469698 Freq=600, CH0 RK0
4075 13:58:31.469764
4076 13:58:31.472509 DATLAT Default: 0x9
4077 13:58:31.472592 0, 0xFFFF, sum = 0
4078 13:58:31.476013 1, 0xFFFF, sum = 0
4079 13:58:31.476101 2, 0xFFFF, sum = 0
4080 13:58:31.479317 3, 0xFFFF, sum = 0
4081 13:58:31.479400 4, 0xFFFF, sum = 0
4082 13:58:31.482210 5, 0xFFFF, sum = 0
4083 13:58:31.482294 6, 0xFFFF, sum = 0
4084 13:58:31.486214 7, 0xFFFF, sum = 0
4085 13:58:31.486298 8, 0x0, sum = 1
4086 13:58:31.489119 9, 0x0, sum = 2
4087 13:58:31.489203 10, 0x0, sum = 3
4088 13:58:31.492308 11, 0x0, sum = 4
4089 13:58:31.492392 best_step = 9
4090 13:58:31.492457
4091 13:58:31.492517 ==
4092 13:58:31.495962 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 13:58:31.498861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 13:58:31.502038 ==
4095 13:58:31.502121 RX Vref Scan: 1
4096 13:58:31.502186
4097 13:58:31.505562 RX Vref 0 -> 0, step: 1
4098 13:58:31.505661
4099 13:58:31.508754 RX Delay -179 -> 252, step: 8
4100 13:58:31.508836
4101 13:58:31.512699 Set Vref, RX VrefLevel [Byte0]: 56
4102 13:58:31.515077 [Byte1]: 49
4103 13:58:31.515174
4104 13:58:31.518241 Final RX Vref Byte 0 = 56 to rank0
4105 13:58:31.521732 Final RX Vref Byte 1 = 49 to rank0
4106 13:58:31.524935 Final RX Vref Byte 0 = 56 to rank1
4107 13:58:31.528433 Final RX Vref Byte 1 = 49 to rank1==
4108 13:58:31.531927 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 13:58:31.535390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 13:58:31.535474 ==
4111 13:58:31.538371 DQS Delay:
4112 13:58:31.538454 DQS0 = 0, DQS1 = 0
4113 13:58:31.538520 DQM Delay:
4114 13:58:31.541587 DQM0 = 44, DQM1 = 36
4115 13:58:31.541673 DQ Delay:
4116 13:58:31.545154 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4117 13:58:31.548201 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4118 13:58:31.551463 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4119 13:58:31.555003 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4120 13:58:31.555084
4121 13:58:31.555145
4122 13:58:31.564844 [DQSOSCAuto] RK0, (LSB)MR18= 0x534a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
4123 13:58:31.567642 CH0 RK0: MR19=808, MR18=534A
4124 13:58:31.574379 CH0_RK0: MR19=0x808, MR18=0x534A, DQSOSC=394, MR23=63, INC=168, DEC=112
4125 13:58:31.574457
4126 13:58:31.577576 ----->DramcWriteLeveling(PI) begin...
4127 13:58:31.577651 ==
4128 13:58:31.580964 Dram Type= 6, Freq= 0, CH_0, rank 1
4129 13:58:31.584440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 13:58:31.584512 ==
4131 13:58:31.587456 Write leveling (Byte 0): 32 => 32
4132 13:58:31.590792 Write leveling (Byte 1): 28 => 28
4133 13:58:31.594128 DramcWriteLeveling(PI) end<-----
4134 13:58:31.594206
4135 13:58:31.594271 ==
4136 13:58:31.597167 Dram Type= 6, Freq= 0, CH_0, rank 1
4137 13:58:31.600326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 13:58:31.600398 ==
4139 13:58:31.603891 [Gating] SW mode calibration
4140 13:58:31.611039 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4141 13:58:31.616909 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4142 13:58:31.620584 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4143 13:58:31.623824 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4144 13:58:31.630297 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4145 13:58:31.633724 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4146 13:58:31.637022 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
4147 13:58:31.643344 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4148 13:58:31.646899 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4149 13:58:31.649987 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4150 13:58:31.656357 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4151 13:58:31.659702 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4152 13:58:31.663013 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 13:58:31.669972 0 10 12 | B1->B0 | 2c2c 3c3c | 0 0 | (0 0) (0 0)
4154 13:58:31.672964 0 10 16 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
4155 13:58:31.676483 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4156 13:58:31.682853 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4157 13:58:31.686465 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4158 13:58:31.689855 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4159 13:58:31.696310 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4160 13:58:31.699265 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 13:58:31.703303 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4162 13:58:31.709381 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 13:58:31.712605 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 13:58:31.715923 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 13:58:31.722504 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 13:58:31.725942 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 13:58:31.728950 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 13:58:31.735828 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 13:58:31.739027 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 13:58:31.742240 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 13:58:31.748970 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 13:58:31.751938 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 13:58:31.755773 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 13:58:31.762222 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 13:58:31.765781 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 13:58:31.768408 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 13:58:31.775499 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4178 13:58:31.778594 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 13:58:31.782060 Total UI for P1: 0, mck2ui 16
4180 13:58:31.785348 best dqsien dly found for B0: ( 0, 13, 12)
4181 13:58:31.788620 Total UI for P1: 0, mck2ui 16
4182 13:58:31.791657 best dqsien dly found for B1: ( 0, 13, 12)
4183 13:58:31.794854 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4184 13:58:31.798810 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4185 13:58:31.798892
4186 13:58:31.801599 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4187 13:58:31.809081 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4188 13:58:31.809162 [Gating] SW calibration Done
4189 13:58:31.809227 ==
4190 13:58:31.812016 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 13:58:31.818952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 13:58:31.819034 ==
4193 13:58:31.819099 RX Vref Scan: 0
4194 13:58:31.819159
4195 13:58:31.821627 RX Vref 0 -> 0, step: 1
4196 13:58:31.821708
4197 13:58:31.825055 RX Delay -230 -> 252, step: 16
4198 13:58:31.828097 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4199 13:58:31.831705 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4200 13:58:31.838015 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4201 13:58:31.841367 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4202 13:58:31.844326 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4203 13:58:31.847896 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4204 13:58:31.850797 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4205 13:58:31.857637 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4206 13:58:31.860785 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4207 13:58:31.864102 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4208 13:58:31.867802 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4209 13:58:31.873836 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4210 13:58:31.877286 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4211 13:58:31.880834 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4212 13:58:31.883847 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4213 13:58:31.890457 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4214 13:58:31.890532 ==
4215 13:58:31.893540 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 13:58:31.896938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 13:58:31.897017 ==
4218 13:58:31.897078 DQS Delay:
4219 13:58:31.900331 DQS0 = 0, DQS1 = 0
4220 13:58:31.900412 DQM Delay:
4221 13:58:31.903804 DQM0 = 47, DQM1 = 35
4222 13:58:31.903872 DQ Delay:
4223 13:58:31.906589 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4224 13:58:31.910271 DQ4 =49, DQ5 =33, DQ6 =65, DQ7 =57
4225 13:58:31.913331 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4226 13:58:31.916932 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4227 13:58:31.917007
4228 13:58:31.917077
4229 13:58:31.917167 ==
4230 13:58:31.919841 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 13:58:31.927632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 13:58:31.927707 ==
4233 13:58:31.927775
4234 13:58:31.927837
4235 13:58:31.927894 TX Vref Scan disable
4236 13:58:31.930028 == TX Byte 0 ==
4237 13:58:31.933405 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4238 13:58:31.937245 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4239 13:58:31.940048 == TX Byte 1 ==
4240 13:58:31.943292 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4241 13:58:31.949883 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4242 13:58:31.949962 ==
4243 13:58:31.953278 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 13:58:31.956934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 13:58:31.957011 ==
4246 13:58:31.957083
4247 13:58:31.957142
4248 13:58:31.959982 TX Vref Scan disable
4249 13:58:31.963617 == TX Byte 0 ==
4250 13:58:31.966931 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4251 13:58:31.970222 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4252 13:58:31.973359 == TX Byte 1 ==
4253 13:58:31.976336 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4254 13:58:31.979663 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4255 13:58:31.979746
4256 13:58:31.979811 [DATLAT]
4257 13:58:31.983426 Freq=600, CH0 RK1
4258 13:58:31.983508
4259 13:58:31.986251 DATLAT Default: 0x9
4260 13:58:31.986332 0, 0xFFFF, sum = 0
4261 13:58:31.989303 1, 0xFFFF, sum = 0
4262 13:58:31.989403 2, 0xFFFF, sum = 0
4263 13:58:31.992925 3, 0xFFFF, sum = 0
4264 13:58:31.993007 4, 0xFFFF, sum = 0
4265 13:58:31.996049 5, 0xFFFF, sum = 0
4266 13:58:31.996178 6, 0xFFFF, sum = 0
4267 13:58:31.999225 7, 0xFFFF, sum = 0
4268 13:58:31.999307 8, 0x0, sum = 1
4269 13:58:32.002748 9, 0x0, sum = 2
4270 13:58:32.002830 10, 0x0, sum = 3
4271 13:58:32.006077 11, 0x0, sum = 4
4272 13:58:32.006160 best_step = 9
4273 13:58:32.006224
4274 13:58:32.006284 ==
4275 13:58:32.009327 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 13:58:32.012618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 13:58:32.012700 ==
4278 13:58:32.015786 RX Vref Scan: 0
4279 13:58:32.015896
4280 13:58:32.019626 RX Vref 0 -> 0, step: 1
4281 13:58:32.019734
4282 13:58:32.022206 RX Delay -195 -> 252, step: 8
4283 13:58:32.025885 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4284 13:58:32.028824 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4285 13:58:32.035163 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4286 13:58:32.038574 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4287 13:58:32.041861 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4288 13:58:32.045232 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4289 13:58:32.051523 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4290 13:58:32.055104 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4291 13:58:32.058038 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4292 13:58:32.061761 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4293 13:58:32.068041 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4294 13:58:32.071450 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4295 13:58:32.074935 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4296 13:58:32.078440 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4297 13:58:32.084713 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4298 13:58:32.088107 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4299 13:58:32.088218 ==
4300 13:58:32.091117 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 13:58:32.094522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 13:58:32.094618 ==
4303 13:58:32.097743 DQS Delay:
4304 13:58:32.097868 DQS0 = 0, DQS1 = 0
4305 13:58:32.097975 DQM Delay:
4306 13:58:32.101102 DQM0 = 44, DQM1 = 36
4307 13:58:32.101196 DQ Delay:
4308 13:58:32.104529 DQ0 =40, DQ1 =48, DQ2 =40, DQ3 =40
4309 13:58:32.107287 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =52
4310 13:58:32.111092 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4311 13:58:32.114170 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4312 13:58:32.114334
4313 13:58:32.114444
4314 13:58:32.124037 [DQSOSCAuto] RK1, (LSB)MR18= 0x433e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4315 13:58:32.127234 CH0 RK1: MR19=808, MR18=433E
4316 13:58:32.130392 CH0_RK1: MR19=0x808, MR18=0x433E, DQSOSC=397, MR23=63, INC=166, DEC=110
4317 13:58:32.133783 [RxdqsGatingPostProcess] freq 600
4318 13:58:32.140453 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4319 13:58:32.143660 Pre-setting of DQS Precalculation
4320 13:58:32.147272 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4321 13:58:32.147352 ==
4322 13:58:32.150285 Dram Type= 6, Freq= 0, CH_1, rank 0
4323 13:58:32.157153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 13:58:32.157234 ==
4325 13:58:32.161019 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4326 13:58:32.167122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4327 13:58:32.170278 [CA 0] Center 35 (5~66) winsize 62
4328 13:58:32.174527 [CA 1] Center 35 (5~66) winsize 62
4329 13:58:32.176977 [CA 2] Center 34 (4~65) winsize 62
4330 13:58:32.180716 [CA 3] Center 34 (4~65) winsize 62
4331 13:58:32.183989 [CA 4] Center 34 (4~65) winsize 62
4332 13:58:32.186914 [CA 5] Center 34 (3~65) winsize 63
4333 13:58:32.186988
4334 13:58:32.190129 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4335 13:58:32.190207
4336 13:58:32.194124 [CATrainingPosCal] consider 1 rank data
4337 13:58:32.196812 u2DelayCellTimex100 = 270/100 ps
4338 13:58:32.199878 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4339 13:58:32.203590 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4340 13:58:32.210025 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4341 13:58:32.213202 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4342 13:58:32.216522 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4343 13:58:32.220124 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4344 13:58:32.220199
4345 13:58:32.223074 CA PerBit enable=1, Macro0, CA PI delay=34
4346 13:58:32.223147
4347 13:58:32.226531 [CBTSetCACLKResult] CA Dly = 34
4348 13:58:32.226603 CS Dly: 4 (0~35)
4349 13:58:32.230614 ==
4350 13:58:32.233260 Dram Type= 6, Freq= 0, CH_1, rank 1
4351 13:58:32.236353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 13:58:32.236428 ==
4353 13:58:32.243412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4354 13:58:32.246915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4355 13:58:32.250493 [CA 0] Center 35 (5~66) winsize 62
4356 13:58:32.253711 [CA 1] Center 36 (6~66) winsize 61
4357 13:58:32.256856 [CA 2] Center 34 (4~65) winsize 62
4358 13:58:32.259995 [CA 3] Center 34 (3~65) winsize 63
4359 13:58:32.263459 [CA 4] Center 34 (3~65) winsize 63
4360 13:58:32.266976 [CA 5] Center 34 (3~65) winsize 63
4361 13:58:32.267058
4362 13:58:32.269953 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4363 13:58:32.270027
4364 13:58:32.274034 [CATrainingPosCal] consider 2 rank data
4365 13:58:32.276672 u2DelayCellTimex100 = 270/100 ps
4366 13:58:32.280219 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4367 13:58:32.286390 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4368 13:58:32.290151 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4369 13:58:32.293214 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4370 13:58:32.297824 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4371 13:58:32.300296 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4372 13:58:32.300377
4373 13:58:32.303509 CA PerBit enable=1, Macro0, CA PI delay=34
4374 13:58:32.303590
4375 13:58:32.306625 [CBTSetCACLKResult] CA Dly = 34
4376 13:58:32.306721 CS Dly: 5 (0~37)
4377 13:58:32.309811
4378 13:58:32.313040 ----->DramcWriteLeveling(PI) begin...
4379 13:58:32.313122 ==
4380 13:58:32.316527 Dram Type= 6, Freq= 0, CH_1, rank 0
4381 13:58:32.319790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 13:58:32.319873 ==
4383 13:58:32.322822 Write leveling (Byte 0): 29 => 29
4384 13:58:32.326431 Write leveling (Byte 1): 30 => 30
4385 13:58:32.329765 DramcWriteLeveling(PI) end<-----
4386 13:58:32.329847
4387 13:58:32.329912 ==
4388 13:58:32.333080 Dram Type= 6, Freq= 0, CH_1, rank 0
4389 13:58:32.336314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 13:58:32.336396 ==
4391 13:58:32.339349 [Gating] SW mode calibration
4392 13:58:32.346331 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4393 13:58:32.352745 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4394 13:58:32.356100 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4395 13:58:32.359142 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4396 13:58:32.366293 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4397 13:58:32.369475 0 9 12 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 0)
4398 13:58:32.372706 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
4399 13:58:32.378725 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 13:58:32.382591 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 13:58:32.385282 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 13:58:32.392101 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 13:58:32.395737 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 13:58:32.398542 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 13:58:32.405391 0 10 12 | B1->B0 | 3333 3939 | 0 1 | (0 0) (0 0)
4406 13:58:32.408334 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 13:58:32.411733 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 13:58:32.418269 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 13:58:32.421872 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 13:58:32.425042 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 13:58:32.431901 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 13:58:32.434961 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 13:58:32.438245 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4414 13:58:32.444934 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 13:58:32.448180 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 13:58:32.451252 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 13:58:32.458498 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 13:58:32.462389 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 13:58:32.464646 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 13:58:32.471237 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 13:58:32.474708 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 13:58:32.478043 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 13:58:32.484778 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 13:58:32.487809 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 13:58:32.491206 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 13:58:32.497462 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 13:58:32.500921 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 13:58:32.503882 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 13:58:32.511753 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 13:58:32.514025 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 13:58:32.517477 Total UI for P1: 0, mck2ui 16
4432 13:58:32.521107 best dqsien dly found for B0: ( 0, 13, 14)
4433 13:58:32.523720 Total UI for P1: 0, mck2ui 16
4434 13:58:32.527574 best dqsien dly found for B1: ( 0, 13, 14)
4435 13:58:32.530471 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4436 13:58:32.533905 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4437 13:58:32.533980
4438 13:58:32.537274 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4439 13:58:32.541025 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4440 13:58:32.544038 [Gating] SW calibration Done
4441 13:58:32.544116 ==
4442 13:58:32.546986 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 13:58:32.554120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 13:58:32.554195 ==
4445 13:58:32.554268 RX Vref Scan: 0
4446 13:58:32.554328
4447 13:58:32.556888 RX Vref 0 -> 0, step: 1
4448 13:58:32.556967
4449 13:58:32.560411 RX Delay -230 -> 252, step: 16
4450 13:58:32.563672 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4451 13:58:32.567277 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4452 13:58:32.570288 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4453 13:58:32.576832 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4454 13:58:32.580586 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4455 13:58:32.583560 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4456 13:58:32.586507 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4457 13:58:32.593358 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4458 13:58:32.596626 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4459 13:58:32.600480 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4460 13:58:32.603100 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4461 13:58:32.609765 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4462 13:58:32.613123 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4463 13:58:32.616629 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4464 13:58:32.620065 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4465 13:58:32.626310 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4466 13:58:32.626400 ==
4467 13:58:32.630010 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 13:58:32.632971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 13:58:32.633075 ==
4470 13:58:32.633139 DQS Delay:
4471 13:58:32.636335 DQS0 = 0, DQS1 = 0
4472 13:58:32.636404 DQM Delay:
4473 13:58:32.639373 DQM0 = 46, DQM1 = 38
4474 13:58:32.639448 DQ Delay:
4475 13:58:32.643073 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4476 13:58:32.646247 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4477 13:58:32.649950 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4478 13:58:32.652680 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4479 13:58:32.652757
4480 13:58:32.652822
4481 13:58:32.652882 ==
4482 13:58:32.656440 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 13:58:32.659557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 13:58:32.659634 ==
4485 13:58:32.659699
4486 13:58:32.662849
4487 13:58:32.662927 TX Vref Scan disable
4488 13:58:32.666394 == TX Byte 0 ==
4489 13:58:32.669247 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4490 13:58:32.672721 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4491 13:58:32.675990 == TX Byte 1 ==
4492 13:58:32.679320 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4493 13:58:32.682867 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4494 13:58:32.682940 ==
4495 13:58:32.686053 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 13:58:32.692596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 13:58:32.692674 ==
4498 13:58:32.692743
4499 13:58:32.692806
4500 13:58:32.692864 TX Vref Scan disable
4501 13:58:32.697467 == TX Byte 0 ==
4502 13:58:32.700473 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4503 13:58:32.706895 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4504 13:58:32.706973 == TX Byte 1 ==
4505 13:58:32.710047 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4506 13:58:32.716934 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4507 13:58:32.717026
4508 13:58:32.717101 [DATLAT]
4509 13:58:32.717162 Freq=600, CH1 RK0
4510 13:58:32.717222
4511 13:58:32.720283 DATLAT Default: 0x9
4512 13:58:32.723567 0, 0xFFFF, sum = 0
4513 13:58:32.723643 1, 0xFFFF, sum = 0
4514 13:58:32.727059 2, 0xFFFF, sum = 0
4515 13:58:32.727131 3, 0xFFFF, sum = 0
4516 13:58:32.730414 4, 0xFFFF, sum = 0
4517 13:58:32.730493 5, 0xFFFF, sum = 0
4518 13:58:32.733371 6, 0xFFFF, sum = 0
4519 13:58:32.733458 7, 0xFFFF, sum = 0
4520 13:58:32.736490 8, 0x0, sum = 1
4521 13:58:32.736561 9, 0x0, sum = 2
4522 13:58:32.739900 10, 0x0, sum = 3
4523 13:58:32.740040 11, 0x0, sum = 4
4524 13:58:32.740106 best_step = 9
4525 13:58:32.740165
4526 13:58:32.743032 ==
4527 13:58:32.747018 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 13:58:32.749702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 13:58:32.749779 ==
4530 13:58:32.749843 RX Vref Scan: 1
4531 13:58:32.749902
4532 13:58:32.753342 RX Vref 0 -> 0, step: 1
4533 13:58:32.753429
4534 13:58:32.756686 RX Delay -179 -> 252, step: 8
4535 13:58:32.756767
4536 13:58:32.759779 Set Vref, RX VrefLevel [Byte0]: 50
4537 13:58:32.763216 [Byte1]: 54
4538 13:58:32.763300
4539 13:58:32.766197 Final RX Vref Byte 0 = 50 to rank0
4540 13:58:32.769367 Final RX Vref Byte 1 = 54 to rank0
4541 13:58:32.773351 Final RX Vref Byte 0 = 50 to rank1
4542 13:58:32.776715 Final RX Vref Byte 1 = 54 to rank1==
4543 13:58:32.779439 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 13:58:32.782560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 13:58:32.786053 ==
4546 13:58:32.786134 DQS Delay:
4547 13:58:32.786197 DQS0 = 0, DQS1 = 0
4548 13:58:32.789526 DQM Delay:
4549 13:58:32.789602 DQM0 = 41, DQM1 = 33
4550 13:58:32.792651 DQ Delay:
4551 13:58:32.795998 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4552 13:58:32.796071 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4553 13:58:32.799245 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4554 13:58:32.806133 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4555 13:58:32.806243
4556 13:58:32.806367
4557 13:58:32.812223 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d47, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4558 13:58:32.815678 CH1 RK0: MR19=808, MR18=2D47
4559 13:58:32.822360 CH1_RK0: MR19=0x808, MR18=0x2D47, DQSOSC=396, MR23=63, INC=167, DEC=111
4560 13:58:32.822452
4561 13:58:32.825589 ----->DramcWriteLeveling(PI) begin...
4562 13:58:32.825665 ==
4563 13:58:32.829136 Dram Type= 6, Freq= 0, CH_1, rank 1
4564 13:58:32.832300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 13:58:32.832380 ==
4566 13:58:32.835429 Write leveling (Byte 0): 28 => 28
4567 13:58:32.838645 Write leveling (Byte 1): 31 => 31
4568 13:58:32.841827 DramcWriteLeveling(PI) end<-----
4569 13:58:32.841916
4570 13:58:32.842003 ==
4571 13:58:32.844958 Dram Type= 6, Freq= 0, CH_1, rank 1
4572 13:58:32.848736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 13:58:32.851709 ==
4574 13:58:32.851811 [Gating] SW mode calibration
4575 13:58:32.862109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4576 13:58:32.864724 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4577 13:58:32.868216 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4578 13:58:32.874897 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4579 13:58:32.877956 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4580 13:58:32.881297 0 9 12 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (1 1)
4581 13:58:32.888283 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4582 13:58:32.891537 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4583 13:58:32.894333 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4584 13:58:32.900859 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4585 13:58:32.904705 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4586 13:58:32.907522 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4587 13:58:32.914419 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4588 13:58:32.917636 0 10 12 | B1->B0 | 3232 4545 | 1 0 | (0 0) (0 0)
4589 13:58:32.920899 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4590 13:58:32.927644 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4591 13:58:32.930831 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4592 13:58:32.934491 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4593 13:58:32.940604 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4594 13:58:32.944178 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 13:58:32.947464 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 13:58:32.954163 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 13:58:32.957505 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 13:58:32.961015 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 13:58:32.967101 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 13:58:32.970403 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 13:58:32.974348 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 13:58:32.980472 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 13:58:32.983820 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 13:58:32.987232 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 13:58:32.993728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 13:58:32.997209 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 13:58:33.000754 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 13:58:33.006815 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 13:58:33.009972 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 13:58:33.013220 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 13:58:33.020052 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 13:58:33.023670 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4613 13:58:33.026856 Total UI for P1: 0, mck2ui 16
4614 13:58:33.029795 best dqsien dly found for B1: ( 0, 13, 10)
4615 13:58:33.033887 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 13:58:33.036916 Total UI for P1: 0, mck2ui 16
4617 13:58:33.039910 best dqsien dly found for B0: ( 0, 13, 12)
4618 13:58:33.043606 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4619 13:58:33.046619 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4620 13:58:33.046722
4621 13:58:33.053500 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4622 13:58:33.056420 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4623 13:58:33.056522 [Gating] SW calibration Done
4624 13:58:33.060496 ==
4625 13:58:33.063281 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 13:58:33.066091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 13:58:33.066186 ==
4628 13:58:33.066249 RX Vref Scan: 0
4629 13:58:33.066308
4630 13:58:33.070218 RX Vref 0 -> 0, step: 1
4631 13:58:33.070295
4632 13:58:33.072831 RX Delay -230 -> 252, step: 16
4633 13:58:33.076245 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4634 13:58:33.079638 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4635 13:58:33.085958 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4636 13:58:33.089941 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4637 13:58:33.092613 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4638 13:58:33.095827 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4639 13:58:33.102777 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4640 13:58:33.106000 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4641 13:58:33.109273 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4642 13:58:33.112606 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4643 13:58:33.119556 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4644 13:58:33.122820 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4645 13:58:33.126635 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4646 13:58:33.129033 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4647 13:58:33.135669 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4648 13:58:33.139319 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4649 13:58:33.139428 ==
4650 13:58:33.142624 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 13:58:33.145747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 13:58:33.145849 ==
4653 13:58:33.145939 DQS Delay:
4654 13:58:33.149665 DQS0 = 0, DQS1 = 0
4655 13:58:33.149773 DQM Delay:
4656 13:58:33.152444 DQM0 = 41, DQM1 = 40
4657 13:58:33.152541 DQ Delay:
4658 13:58:33.155653 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4659 13:58:33.159428 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4660 13:58:33.162697 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4661 13:58:33.165722 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4662 13:58:33.165817
4663 13:58:33.165917
4664 13:58:33.166003 ==
4665 13:58:33.169376 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 13:58:33.175791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 13:58:33.175888 ==
4668 13:58:33.175983
4669 13:58:33.176045
4670 13:58:33.176102 TX Vref Scan disable
4671 13:58:33.178986 == TX Byte 0 ==
4672 13:58:33.182083 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4673 13:58:33.188772 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4674 13:58:33.188849 == TX Byte 1 ==
4675 13:58:33.192249 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4676 13:58:33.198286 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4677 13:58:33.198386 ==
4678 13:58:33.201909 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 13:58:33.204895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 13:58:33.205002 ==
4681 13:58:33.205091
4682 13:58:33.205181
4683 13:58:33.208338 TX Vref Scan disable
4684 13:58:33.211828 == TX Byte 0 ==
4685 13:58:33.214849 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4686 13:58:33.218492 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4687 13:58:33.221396 == TX Byte 1 ==
4688 13:58:33.225113 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4689 13:58:33.228276 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4690 13:58:33.228352
4691 13:58:33.232066 [DATLAT]
4692 13:58:33.232133 Freq=600, CH1 RK1
4693 13:58:33.232193
4694 13:58:33.235460 DATLAT Default: 0x9
4695 13:58:33.235554 0, 0xFFFF, sum = 0
4696 13:58:33.238458 1, 0xFFFF, sum = 0
4697 13:58:33.238556 2, 0xFFFF, sum = 0
4698 13:58:33.241484 3, 0xFFFF, sum = 0
4699 13:58:33.241583 4, 0xFFFF, sum = 0
4700 13:58:33.245011 5, 0xFFFF, sum = 0
4701 13:58:33.245114 6, 0xFFFF, sum = 0
4702 13:58:33.248424 7, 0xFFFF, sum = 0
4703 13:58:33.248532 8, 0x0, sum = 1
4704 13:58:33.251608 9, 0x0, sum = 2
4705 13:58:33.251721 10, 0x0, sum = 3
4706 13:58:33.254962 11, 0x0, sum = 4
4707 13:58:33.255068 best_step = 9
4708 13:58:33.255157
4709 13:58:33.255243 ==
4710 13:58:33.257885 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 13:58:33.261380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 13:58:33.261456 ==
4713 13:58:33.264982 RX Vref Scan: 0
4714 13:58:33.265065
4715 13:58:33.267754 RX Vref 0 -> 0, step: 1
4716 13:58:33.267852
4717 13:58:33.267960 RX Delay -179 -> 252, step: 8
4718 13:58:33.276463 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4719 13:58:33.279379 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4720 13:58:33.282267 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4721 13:58:33.286118 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4722 13:58:33.292704 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4723 13:58:33.295750 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4724 13:58:33.298545 iDelay=205, Bit 6, Center 40 (-115 ~ 196) 312
4725 13:58:33.302011 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4726 13:58:33.308595 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4727 13:58:33.312440 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4728 13:58:33.315637 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4729 13:58:33.319040 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4730 13:58:33.325004 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4731 13:58:33.329196 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4732 13:58:33.331956 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4733 13:58:33.335299 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4734 13:58:33.335406 ==
4735 13:58:33.338644 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 13:58:33.344982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 13:58:33.345103 ==
4738 13:58:33.345198 DQS Delay:
4739 13:58:33.348317 DQS0 = 0, DQS1 = 0
4740 13:58:33.348416 DQM Delay:
4741 13:58:33.351656 DQM0 = 37, DQM1 = 35
4742 13:58:33.351754 DQ Delay:
4743 13:58:33.355176 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4744 13:58:33.358355 DQ4 =40, DQ5 =48, DQ6 =40, DQ7 =32
4745 13:58:33.361576 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4746 13:58:33.365078 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4747 13:58:33.365183
4748 13:58:33.365278
4749 13:58:33.371252 [DQSOSCAuto] RK1, (LSB)MR18= 0x395e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4750 13:58:33.374971 CH1 RK1: MR19=808, MR18=395E
4751 13:58:33.381022 CH1_RK1: MR19=0x808, MR18=0x395E, DQSOSC=392, MR23=63, INC=170, DEC=113
4752 13:58:33.384548 [RxdqsGatingPostProcess] freq 600
4753 13:58:33.391112 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4754 13:58:33.391211 Pre-setting of DQS Precalculation
4755 13:58:33.398368 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4756 13:58:33.404544 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4757 13:58:33.411020 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4758 13:58:33.411128
4759 13:58:33.411231
4760 13:58:33.414079 [Calibration Summary] 1200 Mbps
4761 13:58:33.417683 CH 0, Rank 0
4762 13:58:33.417790 SW Impedance : PASS
4763 13:58:33.420881 DUTY Scan : NO K
4764 13:58:33.423785 ZQ Calibration : PASS
4765 13:58:33.423900 Jitter Meter : NO K
4766 13:58:33.427248 CBT Training : PASS
4767 13:58:33.430757 Write leveling : PASS
4768 13:58:33.430854 RX DQS gating : PASS
4769 13:58:33.434353 RX DQ/DQS(RDDQC) : PASS
4770 13:58:33.437207 TX DQ/DQS : PASS
4771 13:58:33.437284 RX DATLAT : PASS
4772 13:58:33.440329 RX DQ/DQS(Engine): PASS
4773 13:58:33.440428 TX OE : NO K
4774 13:58:33.443480 All Pass.
4775 13:58:33.443593
4776 13:58:33.443684 CH 0, Rank 1
4777 13:58:33.447071 SW Impedance : PASS
4778 13:58:33.447174 DUTY Scan : NO K
4779 13:58:33.450819 ZQ Calibration : PASS
4780 13:58:33.453768 Jitter Meter : NO K
4781 13:58:33.453872 CBT Training : PASS
4782 13:58:33.457309 Write leveling : PASS
4783 13:58:33.459999 RX DQS gating : PASS
4784 13:58:33.460075 RX DQ/DQS(RDDQC) : PASS
4785 13:58:33.463479 TX DQ/DQS : PASS
4786 13:58:33.467362 RX DATLAT : PASS
4787 13:58:33.467462 RX DQ/DQS(Engine): PASS
4788 13:58:33.470259 TX OE : NO K
4789 13:58:33.470377 All Pass.
4790 13:58:33.470468
4791 13:58:33.473121 CH 1, Rank 0
4792 13:58:33.473217 SW Impedance : PASS
4793 13:58:33.476497 DUTY Scan : NO K
4794 13:58:33.480224 ZQ Calibration : PASS
4795 13:58:33.480297 Jitter Meter : NO K
4796 13:58:33.483427 CBT Training : PASS
4797 13:58:33.486384 Write leveling : PASS
4798 13:58:33.486492 RX DQS gating : PASS
4799 13:58:33.489960 RX DQ/DQS(RDDQC) : PASS
4800 13:58:33.493280 TX DQ/DQS : PASS
4801 13:58:33.493354 RX DATLAT : PASS
4802 13:58:33.496333 RX DQ/DQS(Engine): PASS
4803 13:58:33.500116 TX OE : NO K
4804 13:58:33.500194 All Pass.
4805 13:58:33.500262
4806 13:58:33.500341 CH 1, Rank 1
4807 13:58:33.503005 SW Impedance : PASS
4808 13:58:33.506505 DUTY Scan : NO K
4809 13:58:33.506610 ZQ Calibration : PASS
4810 13:58:33.509946 Jitter Meter : NO K
4811 13:58:33.513036 CBT Training : PASS
4812 13:58:33.513139 Write leveling : PASS
4813 13:58:33.515973 RX DQS gating : PASS
4814 13:58:33.520171 RX DQ/DQS(RDDQC) : PASS
4815 13:58:33.520250 TX DQ/DQS : PASS
4816 13:58:33.522622 RX DATLAT : PASS
4817 13:58:33.522724 RX DQ/DQS(Engine): PASS
4818 13:58:33.526115 TX OE : NO K
4819 13:58:33.526225 All Pass.
4820 13:58:33.526319
4821 13:58:33.529445 DramC Write-DBI off
4822 13:58:33.532604 PER_BANK_REFRESH: Hybrid Mode
4823 13:58:33.532681 TX_TRACKING: ON
4824 13:58:33.542619 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4825 13:58:33.545807 [FAST_K] Save calibration result to emmc
4826 13:58:33.549713 dramc_set_vcore_voltage set vcore to 662500
4827 13:58:33.552866 Read voltage for 933, 3
4828 13:58:33.552942 Vio18 = 0
4829 13:58:33.556335 Vcore = 662500
4830 13:58:33.556426 Vdram = 0
4831 13:58:33.556495 Vddq = 0
4832 13:58:33.556559 Vmddr = 0
4833 13:58:33.562319 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4834 13:58:33.568984 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4835 13:58:33.569127 MEM_TYPE=3, freq_sel=17
4836 13:58:33.572329 sv_algorithm_assistance_LP4_1600
4837 13:58:33.575596 ============ PULL DRAM RESETB DOWN ============
4838 13:58:33.582113 ========== PULL DRAM RESETB DOWN end =========
4839 13:58:33.585257 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4840 13:58:33.588953 ===================================
4841 13:58:33.591885 LPDDR4 DRAM CONFIGURATION
4842 13:58:33.595549 ===================================
4843 13:58:33.595622 EX_ROW_EN[0] = 0x0
4844 13:58:33.598641 EX_ROW_EN[1] = 0x0
4845 13:58:33.601819 LP4Y_EN = 0x0
4846 13:58:33.601962 WORK_FSP = 0x0
4847 13:58:33.605152 WL = 0x3
4848 13:58:33.605230 RL = 0x3
4849 13:58:33.608518 BL = 0x2
4850 13:58:33.608601 RPST = 0x0
4851 13:58:33.612012 RD_PRE = 0x0
4852 13:58:33.612115 WR_PRE = 0x1
4853 13:58:33.614956 WR_PST = 0x0
4854 13:58:33.615056 DBI_WR = 0x0
4855 13:58:33.618552 DBI_RD = 0x0
4856 13:58:33.618662 OTF = 0x1
4857 13:58:33.621681 ===================================
4858 13:58:33.625357 ===================================
4859 13:58:33.628410 ANA top config
4860 13:58:33.631023 ===================================
4861 13:58:33.634408 DLL_ASYNC_EN = 0
4862 13:58:33.634519 ALL_SLAVE_EN = 1
4863 13:58:33.637714 NEW_RANK_MODE = 1
4864 13:58:33.641340 DLL_IDLE_MODE = 1
4865 13:58:33.644600 LP45_APHY_COMB_EN = 1
4866 13:58:33.644716 TX_ODT_DIS = 1
4867 13:58:33.648137 NEW_8X_MODE = 1
4868 13:58:33.650949 ===================================
4869 13:58:33.654355 ===================================
4870 13:58:33.658008 data_rate = 1866
4871 13:58:33.661361 CKR = 1
4872 13:58:33.664864 DQ_P2S_RATIO = 8
4873 13:58:33.667878 ===================================
4874 13:58:33.672032 CA_P2S_RATIO = 8
4875 13:58:33.672142 DQ_CA_OPEN = 0
4876 13:58:33.674315 DQ_SEMI_OPEN = 0
4877 13:58:33.677744 CA_SEMI_OPEN = 0
4878 13:58:33.681291 CA_FULL_RATE = 0
4879 13:58:33.684330 DQ_CKDIV4_EN = 1
4880 13:58:33.687457 CA_CKDIV4_EN = 1
4881 13:58:33.687597 CA_PREDIV_EN = 0
4882 13:58:33.690685 PH8_DLY = 0
4883 13:58:33.694151 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4884 13:58:33.697594 DQ_AAMCK_DIV = 4
4885 13:58:33.700864 CA_AAMCK_DIV = 4
4886 13:58:33.703812 CA_ADMCK_DIV = 4
4887 13:58:33.703936 DQ_TRACK_CA_EN = 0
4888 13:58:33.707592 CA_PICK = 933
4889 13:58:33.710811 CA_MCKIO = 933
4890 13:58:33.713623 MCKIO_SEMI = 0
4891 13:58:33.717198 PLL_FREQ = 3732
4892 13:58:33.720304 DQ_UI_PI_RATIO = 32
4893 13:58:33.723464 CA_UI_PI_RATIO = 0
4894 13:58:33.727129 ===================================
4895 13:58:33.730385 ===================================
4896 13:58:33.730477 memory_type:LPDDR4
4897 13:58:33.733544 GP_NUM : 10
4898 13:58:33.736847 SRAM_EN : 1
4899 13:58:33.736928 MD32_EN : 0
4900 13:58:33.740403 ===================================
4901 13:58:33.743333 [ANA_INIT] >>>>>>>>>>>>>>
4902 13:58:33.747210 <<<<<< [CONFIGURE PHASE]: ANA_TX
4903 13:58:33.749896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4904 13:58:33.753451 ===================================
4905 13:58:33.757646 data_rate = 1866,PCW = 0X8f00
4906 13:58:33.759886 ===================================
4907 13:58:33.763328 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4908 13:58:33.766382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4909 13:58:33.773294 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4910 13:58:33.779587 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4911 13:58:33.813075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4912 13:58:33.813187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4913 13:58:33.813256 [ANA_INIT] flow start
4914 13:58:33.813318 [ANA_INIT] PLL >>>>>>>>
4915 13:58:33.813377 [ANA_INIT] PLL <<<<<<<<
4916 13:58:33.813434 [ANA_INIT] MIDPI >>>>>>>>
4917 13:58:33.813491 [ANA_INIT] MIDPI <<<<<<<<
4918 13:58:33.813547 [ANA_INIT] DLL >>>>>>>>
4919 13:58:33.813603 [ANA_INIT] flow end
4920 13:58:33.813657 ============ LP4 DIFF to SE enter ============
4921 13:58:33.813713 ============ LP4 DIFF to SE exit ============
4922 13:58:33.813768 [ANA_INIT] <<<<<<<<<<<<<
4923 13:58:33.815734 [Flow] Enable top DCM control >>>>>
4924 13:58:33.819440 [Flow] Enable top DCM control <<<<<
4925 13:58:33.819522 Enable DLL master slave shuffle
4926 13:58:33.825627 ==============================================================
4927 13:58:33.829032 Gating Mode config
4928 13:58:33.832368 ==============================================================
4929 13:58:33.836055 Config description:
4930 13:58:33.845563 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4931 13:58:33.851794 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4932 13:58:33.855495 SELPH_MODE 0: By rank 1: By Phase
4933 13:58:33.861737 ==============================================================
4934 13:58:33.865738 GAT_TRACK_EN = 1
4935 13:58:33.868791 RX_GATING_MODE = 2
4936 13:58:33.871879 RX_GATING_TRACK_MODE = 2
4937 13:58:33.875288 SELPH_MODE = 1
4938 13:58:33.878480 PICG_EARLY_EN = 1
4939 13:58:33.878568 VALID_LAT_VALUE = 1
4940 13:58:33.884881 ==============================================================
4941 13:58:33.888100 Enter into Gating configuration >>>>
4942 13:58:33.891713 Exit from Gating configuration <<<<
4943 13:58:33.894753 Enter into DVFS_PRE_config >>>>>
4944 13:58:33.904780 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4945 13:58:33.908265 Exit from DVFS_PRE_config <<<<<
4946 13:58:33.911724 Enter into PICG configuration >>>>
4947 13:58:33.914462 Exit from PICG configuration <<<<
4948 13:58:33.918261 [RX_INPUT] configuration >>>>>
4949 13:58:33.921420 [RX_INPUT] configuration <<<<<
4950 13:58:33.928324 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4951 13:58:33.931045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4952 13:58:33.938050 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4953 13:58:33.944332 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4954 13:58:33.950688 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4955 13:58:33.957267 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4956 13:58:33.960517 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4957 13:58:33.964548 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4958 13:58:33.967717 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4959 13:58:33.973763 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4960 13:58:33.977435 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4961 13:58:33.980209 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4962 13:58:33.984035 ===================================
4963 13:58:33.986870 LPDDR4 DRAM CONFIGURATION
4964 13:58:33.991291 ===================================
4965 13:58:33.993545 EX_ROW_EN[0] = 0x0
4966 13:58:33.993624 EX_ROW_EN[1] = 0x0
4967 13:58:33.997124 LP4Y_EN = 0x0
4968 13:58:33.997201 WORK_FSP = 0x0
4969 13:58:34.000536 WL = 0x3
4970 13:58:34.000615 RL = 0x3
4971 13:58:34.003560 BL = 0x2
4972 13:58:34.003662 RPST = 0x0
4973 13:58:34.007626 RD_PRE = 0x0
4974 13:58:34.007736 WR_PRE = 0x1
4975 13:58:34.010325 WR_PST = 0x0
4976 13:58:34.010429 DBI_WR = 0x0
4977 13:58:34.013436 DBI_RD = 0x0
4978 13:58:34.016839 OTF = 0x1
4979 13:58:34.020031 ===================================
4980 13:58:34.023697 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4981 13:58:34.027081 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4982 13:58:34.029996 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4983 13:58:34.033134 ===================================
4984 13:58:34.036719 LPDDR4 DRAM CONFIGURATION
4985 13:58:34.040002 ===================================
4986 13:58:34.043619 EX_ROW_EN[0] = 0x10
4987 13:58:34.043704 EX_ROW_EN[1] = 0x0
4988 13:58:34.046405 LP4Y_EN = 0x0
4989 13:58:34.046513 WORK_FSP = 0x0
4990 13:58:34.049652 WL = 0x3
4991 13:58:34.049752 RL = 0x3
4992 13:58:34.052679 BL = 0x2
4993 13:58:34.052782 RPST = 0x0
4994 13:58:34.056732 RD_PRE = 0x0
4995 13:58:34.056858 WR_PRE = 0x1
4996 13:58:34.059424 WR_PST = 0x0
4997 13:58:34.063152 DBI_WR = 0x0
4998 13:58:34.063224 DBI_RD = 0x0
4999 13:58:34.066614 OTF = 0x1
5000 13:58:34.069626 ===================================
5001 13:58:34.072593 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5002 13:58:34.078161 nWR fixed to 30
5003 13:58:34.081381 [ModeRegInit_LP4] CH0 RK0
5004 13:58:34.081513 [ModeRegInit_LP4] CH0 RK1
5005 13:58:34.084660 [ModeRegInit_LP4] CH1 RK0
5006 13:58:34.088038 [ModeRegInit_LP4] CH1 RK1
5007 13:58:34.088150 match AC timing 9
5008 13:58:34.094227 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5009 13:58:34.098080 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5010 13:58:34.102050 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5011 13:58:34.108037 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5012 13:58:34.110835 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5013 13:58:34.110935 ==
5014 13:58:34.114334 Dram Type= 6, Freq= 0, CH_0, rank 0
5015 13:58:34.117840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5016 13:58:34.117917 ==
5017 13:58:34.123915 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5018 13:58:34.130606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5019 13:58:34.134428 [CA 0] Center 38 (7~69) winsize 63
5020 13:58:34.137168 [CA 1] Center 37 (7~68) winsize 62
5021 13:58:34.140292 [CA 2] Center 34 (4~65) winsize 62
5022 13:58:34.143965 [CA 3] Center 34 (4~65) winsize 62
5023 13:58:34.147078 [CA 4] Center 33 (2~64) winsize 63
5024 13:58:34.150468 [CA 5] Center 32 (2~63) winsize 62
5025 13:58:34.150545
5026 13:58:34.153577 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5027 13:58:34.153654
5028 13:58:34.157130 [CATrainingPosCal] consider 1 rank data
5029 13:58:34.160147 u2DelayCellTimex100 = 270/100 ps
5030 13:58:34.163598 CA0 delay=38 (7~69),Diff = 6 PI (37 cell)
5031 13:58:34.166838 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5032 13:58:34.170251 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5033 13:58:34.176777 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5034 13:58:34.180321 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5035 13:58:34.183070 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5036 13:58:34.183155
5037 13:58:34.186464 CA PerBit enable=1, Macro0, CA PI delay=32
5038 13:58:34.186549
5039 13:58:34.189997 [CBTSetCACLKResult] CA Dly = 32
5040 13:58:34.190083 CS Dly: 5 (0~36)
5041 13:58:34.190169 ==
5042 13:58:34.193636 Dram Type= 6, Freq= 0, CH_0, rank 1
5043 13:58:34.199675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5044 13:58:34.199761 ==
5045 13:58:34.202655 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5046 13:58:34.209725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5047 13:58:34.213120 [CA 0] Center 38 (8~69) winsize 62
5048 13:58:34.216876 [CA 1] Center 37 (7~68) winsize 62
5049 13:58:34.219601 [CA 2] Center 34 (4~65) winsize 62
5050 13:58:34.222796 [CA 3] Center 34 (4~65) winsize 62
5051 13:58:34.226527 [CA 4] Center 33 (3~64) winsize 62
5052 13:58:34.229925 [CA 5] Center 32 (2~63) winsize 62
5053 13:58:34.230010
5054 13:58:34.233056 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5055 13:58:34.233141
5056 13:58:34.236405 [CATrainingPosCal] consider 2 rank data
5057 13:58:34.239768 u2DelayCellTimex100 = 270/100 ps
5058 13:58:34.243249 CA0 delay=38 (8~69),Diff = 6 PI (37 cell)
5059 13:58:34.249882 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5060 13:58:34.253236 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5061 13:58:34.256306 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5062 13:58:34.259687 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5063 13:58:34.262502 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5064 13:58:34.262586
5065 13:58:34.266191 CA PerBit enable=1, Macro0, CA PI delay=32
5066 13:58:34.266274
5067 13:58:34.269582 [CBTSetCACLKResult] CA Dly = 32
5068 13:58:34.272480 CS Dly: 6 (0~39)
5069 13:58:34.272564
5070 13:58:34.275780 ----->DramcWriteLeveling(PI) begin...
5071 13:58:34.275864 ==
5072 13:58:34.279183 Dram Type= 6, Freq= 0, CH_0, rank 0
5073 13:58:34.282519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 13:58:34.282603 ==
5075 13:58:34.285586 Write leveling (Byte 0): 29 => 29
5076 13:58:34.288836 Write leveling (Byte 1): 26 => 26
5077 13:58:34.292193 DramcWriteLeveling(PI) end<-----
5078 13:58:34.292274
5079 13:58:34.292337 ==
5080 13:58:34.295611 Dram Type= 6, Freq= 0, CH_0, rank 0
5081 13:58:34.298736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5082 13:58:34.298817 ==
5083 13:58:34.302293 [Gating] SW mode calibration
5084 13:58:34.308913 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5085 13:58:34.315660 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5086 13:58:34.318296 0 14 0 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
5087 13:58:34.325204 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 13:58:34.328686 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5089 13:58:34.331940 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5090 13:58:34.338606 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 13:58:34.341598 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 13:58:34.344986 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5093 13:58:34.348618 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
5094 13:58:34.354880 0 15 0 | B1->B0 | 3131 2525 | 1 0 | (1 0) (0 0)
5095 13:58:34.358751 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 13:58:34.361477 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 13:58:34.368332 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 13:58:34.371523 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 13:58:34.374481 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 13:58:34.381257 0 15 24 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
5101 13:58:34.384620 0 15 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
5102 13:58:34.388136 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5103 13:58:34.394550 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 13:58:34.397932 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 13:58:34.401204 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 13:58:34.407676 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 13:58:34.410947 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 13:58:34.414112 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5109 13:58:34.420670 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5110 13:58:34.423861 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5111 13:58:34.430704 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 13:58:34.434286 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 13:58:34.437911 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 13:58:34.444269 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 13:58:34.447243 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 13:58:34.450379 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 13:58:34.457274 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 13:58:34.460165 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 13:58:34.463610 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 13:58:34.470749 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 13:58:34.473527 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 13:58:34.476727 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 13:58:34.483443 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 13:58:34.486527 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5125 13:58:34.490171 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5126 13:58:34.493353 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5127 13:58:34.497188 Total UI for P1: 0, mck2ui 16
5128 13:58:34.499954 best dqsien dly found for B0: ( 1, 2, 26)
5129 13:58:34.506339 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 13:58:34.509749 Total UI for P1: 0, mck2ui 16
5131 13:58:34.512889 best dqsien dly found for B1: ( 1, 3, 0)
5132 13:58:34.516144 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5133 13:58:34.520255 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5134 13:58:34.520336
5135 13:58:34.522976 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5136 13:58:34.525960 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5137 13:58:34.530120 [Gating] SW calibration Done
5138 13:58:34.530200 ==
5139 13:58:34.532761 Dram Type= 6, Freq= 0, CH_0, rank 0
5140 13:58:34.536105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 13:58:34.536186 ==
5142 13:58:34.540130 RX Vref Scan: 0
5143 13:58:34.540226
5144 13:58:34.542854 RX Vref 0 -> 0, step: 1
5145 13:58:34.542934
5146 13:58:34.542997 RX Delay -80 -> 252, step: 8
5147 13:58:34.549424 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5148 13:58:34.552611 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5149 13:58:34.556295 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5150 13:58:34.559372 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5151 13:58:34.562412 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5152 13:58:34.565512 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5153 13:58:34.572085 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5154 13:58:34.575766 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5155 13:58:34.579353 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5156 13:58:34.582863 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5157 13:58:34.585480 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5158 13:58:34.592582 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5159 13:58:34.595474 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5160 13:58:34.598624 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5161 13:58:34.602041 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5162 13:58:34.605755 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5163 13:58:34.608712 ==
5164 13:58:34.611998 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 13:58:34.615295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 13:58:34.615376 ==
5167 13:58:34.615441 DQS Delay:
5168 13:58:34.618814 DQS0 = 0, DQS1 = 0
5169 13:58:34.618895 DQM Delay:
5170 13:58:34.621846 DQM0 = 101, DQM1 = 86
5171 13:58:34.621926 DQ Delay:
5172 13:58:34.625345 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =99
5173 13:58:34.628488 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5174 13:58:34.631567 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5175 13:58:34.634848 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5176 13:58:34.634928
5177 13:58:34.634992
5178 13:58:34.635052 ==
5179 13:58:34.638589 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 13:58:34.641459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 13:58:34.644920 ==
5182 13:58:34.645001
5183 13:58:34.645064
5184 13:58:34.645124 TX Vref Scan disable
5185 13:58:34.648658 == TX Byte 0 ==
5186 13:58:34.651266 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5187 13:58:34.655289 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5188 13:58:34.658359 == TX Byte 1 ==
5189 13:58:34.661480 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5190 13:58:34.664874 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5191 13:58:34.668186 ==
5192 13:58:34.671154 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 13:58:34.674562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 13:58:34.674643 ==
5195 13:58:34.674708
5196 13:58:34.674796
5197 13:58:34.677762 TX Vref Scan disable
5198 13:58:34.677842 == TX Byte 0 ==
5199 13:58:34.684344 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5200 13:58:34.687889 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5201 13:58:34.688011 == TX Byte 1 ==
5202 13:58:34.694574 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5203 13:58:34.697937 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5204 13:58:34.698020
5205 13:58:34.698105 [DATLAT]
5206 13:58:34.701203 Freq=933, CH0 RK0
5207 13:58:34.701326
5208 13:58:34.701412 DATLAT Default: 0xd
5209 13:58:34.704224 0, 0xFFFF, sum = 0
5210 13:58:34.704308 1, 0xFFFF, sum = 0
5211 13:58:34.707157 2, 0xFFFF, sum = 0
5212 13:58:34.711219 3, 0xFFFF, sum = 0
5213 13:58:34.711303 4, 0xFFFF, sum = 0
5214 13:58:34.713615 5, 0xFFFF, sum = 0
5215 13:58:34.713712 6, 0xFFFF, sum = 0
5216 13:58:34.717614 7, 0xFFFF, sum = 0
5217 13:58:34.717713 8, 0xFFFF, sum = 0
5218 13:58:34.721349 9, 0xFFFF, sum = 0
5219 13:58:34.721449 10, 0x0, sum = 1
5220 13:58:34.723651 11, 0x0, sum = 2
5221 13:58:34.723735 12, 0x0, sum = 3
5222 13:58:34.727539 13, 0x0, sum = 4
5223 13:58:34.727623 best_step = 11
5224 13:58:34.727707
5225 13:58:34.727788 ==
5226 13:58:34.730478 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 13:58:34.733662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 13:58:34.733746 ==
5229 13:58:34.737000 RX Vref Scan: 1
5230 13:58:34.737083
5231 13:58:34.739941 RX Vref 0 -> 0, step: 1
5232 13:58:34.740039
5233 13:58:34.740123 RX Delay -69 -> 252, step: 4
5234 13:58:34.743618
5235 13:58:34.743701 Set Vref, RX VrefLevel [Byte0]: 56
5236 13:58:34.747026 [Byte1]: 49
5237 13:58:34.751847
5238 13:58:34.751968 Final RX Vref Byte 0 = 56 to rank0
5239 13:58:34.755215 Final RX Vref Byte 1 = 49 to rank0
5240 13:58:34.758932 Final RX Vref Byte 0 = 56 to rank1
5241 13:58:34.761564 Final RX Vref Byte 1 = 49 to rank1==
5242 13:58:34.765254 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 13:58:34.771455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 13:58:34.771539 ==
5245 13:58:34.771624 DQS Delay:
5246 13:58:34.775044 DQS0 = 0, DQS1 = 0
5247 13:58:34.775126 DQM Delay:
5248 13:58:34.775211 DQM0 = 102, DQM1 = 89
5249 13:58:34.778354 DQ Delay:
5250 13:58:34.781628 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =100
5251 13:58:34.784839 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =106
5252 13:58:34.788013 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =84
5253 13:58:34.791481 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =98
5254 13:58:34.791579
5255 13:58:34.791669
5256 13:58:34.798025 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5257 13:58:34.801194 CH0 RK0: MR19=505, MR18=1E18
5258 13:58:34.808698 CH0_RK0: MR19=0x505, MR18=0x1E18, DQSOSC=412, MR23=63, INC=63, DEC=42
5259 13:58:34.808778
5260 13:58:34.810877 ----->DramcWriteLeveling(PI) begin...
5261 13:58:34.810967 ==
5262 13:58:34.814510 Dram Type= 6, Freq= 0, CH_0, rank 1
5263 13:58:34.818075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 13:58:34.818150 ==
5265 13:58:34.821451 Write leveling (Byte 0): 29 => 29
5266 13:58:34.824148 Write leveling (Byte 1): 27 => 27
5267 13:58:34.827581 DramcWriteLeveling(PI) end<-----
5268 13:58:34.827676
5269 13:58:34.827763 ==
5270 13:58:34.831241 Dram Type= 6, Freq= 0, CH_0, rank 1
5271 13:58:34.837663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 13:58:34.837739 ==
5273 13:58:34.840621 [Gating] SW mode calibration
5274 13:58:34.847624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5275 13:58:34.850501 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5276 13:58:34.857207 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5277 13:58:34.860242 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5278 13:58:34.863855 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5279 13:58:34.870210 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5280 13:58:34.873714 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5281 13:58:34.877319 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5282 13:58:34.883412 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 13:58:34.887011 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
5284 13:58:34.889817 0 15 0 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 0)
5285 13:58:34.897027 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5286 13:58:34.899764 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5287 13:58:34.903233 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5288 13:58:34.909999 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5289 13:58:34.913415 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5290 13:58:34.916577 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5291 13:58:34.923406 0 15 28 | B1->B0 | 2b2b 4242 | 0 1 | (1 1) (0 0)
5292 13:58:34.926323 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5293 13:58:34.929550 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5294 13:58:34.936398 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5295 13:58:34.940041 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5296 13:58:34.943221 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5297 13:58:34.949744 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5298 13:58:34.952369 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 13:58:34.956705 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5300 13:58:34.962616 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5301 13:58:34.965876 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 13:58:34.969111 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 13:58:34.975970 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 13:58:34.980065 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 13:58:34.982592 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 13:58:34.989329 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 13:58:34.992431 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 13:58:34.995603 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 13:58:35.002335 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 13:58:35.005725 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 13:58:35.008988 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 13:58:35.015475 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 13:58:35.018630 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 13:58:35.022034 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5315 13:58:35.028687 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5316 13:58:35.028768 Total UI for P1: 0, mck2ui 16
5317 13:58:35.034987 best dqsien dly found for B0: ( 1, 2, 24)
5318 13:58:35.039034 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 13:58:35.041764 Total UI for P1: 0, mck2ui 16
5320 13:58:35.045134 best dqsien dly found for B1: ( 1, 2, 30)
5321 13:58:35.048752 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5322 13:58:35.051639 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5323 13:58:35.051720
5324 13:58:35.055007 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5325 13:58:35.058224 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5326 13:58:35.061495 [Gating] SW calibration Done
5327 13:58:35.061575 ==
5328 13:58:35.064702 Dram Type= 6, Freq= 0, CH_0, rank 1
5329 13:58:35.068166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 13:58:35.071382 ==
5331 13:58:35.071463 RX Vref Scan: 0
5332 13:58:35.071531
5333 13:58:35.074574 RX Vref 0 -> 0, step: 1
5334 13:58:35.074653
5335 13:58:35.078080 RX Delay -80 -> 252, step: 8
5336 13:58:35.081651 iDelay=200, Bit 0, Center 103 (16 ~ 191) 176
5337 13:58:35.085003 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5338 13:58:35.087802 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5339 13:58:35.091171 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5340 13:58:35.098049 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5341 13:58:35.101020 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5342 13:58:35.104199 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5343 13:58:35.107680 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5344 13:58:35.110791 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5345 13:58:35.117463 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5346 13:58:35.120695 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5347 13:58:35.124150 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5348 13:58:35.127732 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5349 13:58:35.130614 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5350 13:58:35.133852 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5351 13:58:35.140673 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5352 13:58:35.140754 ==
5353 13:58:35.143864 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 13:58:35.147062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 13:58:35.147154 ==
5356 13:58:35.147222 DQS Delay:
5357 13:58:35.150447 DQS0 = 0, DQS1 = 0
5358 13:58:35.150528 DQM Delay:
5359 13:58:35.153840 DQM0 = 101, DQM1 = 88
5360 13:58:35.153920 DQ Delay:
5361 13:58:35.157168 DQ0 =103, DQ1 =107, DQ2 =95, DQ3 =99
5362 13:58:35.160525 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5363 13:58:35.163668 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5364 13:58:35.167044 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5365 13:58:35.167125
5366 13:58:35.167188
5367 13:58:35.167247 ==
5368 13:58:35.170528 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 13:58:35.177138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 13:58:35.177220 ==
5371 13:58:35.177324
5372 13:58:35.177385
5373 13:58:35.177442 TX Vref Scan disable
5374 13:58:35.180226 == TX Byte 0 ==
5375 13:58:35.184136 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5376 13:58:35.190195 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5377 13:58:35.190279 == TX Byte 1 ==
5378 13:58:35.193760 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5379 13:58:35.199706 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5380 13:58:35.199810 ==
5381 13:58:35.203548 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 13:58:35.206563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 13:58:35.206646 ==
5384 13:58:35.206730
5385 13:58:35.206809
5386 13:58:35.209662 TX Vref Scan disable
5387 13:58:35.209746 == TX Byte 0 ==
5388 13:58:35.216710 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5389 13:58:35.220887 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5390 13:58:35.220971 == TX Byte 1 ==
5391 13:58:35.226746 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5392 13:58:35.229809 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5393 13:58:35.229892
5394 13:58:35.229976 [DATLAT]
5395 13:58:35.232933 Freq=933, CH0 RK1
5396 13:58:35.233016
5397 13:58:35.233101 DATLAT Default: 0xb
5398 13:58:35.236544 0, 0xFFFF, sum = 0
5399 13:58:35.239825 1, 0xFFFF, sum = 0
5400 13:58:35.239916 2, 0xFFFF, sum = 0
5401 13:58:35.242611 3, 0xFFFF, sum = 0
5402 13:58:35.242695 4, 0xFFFF, sum = 0
5403 13:58:35.245956 5, 0xFFFF, sum = 0
5404 13:58:35.246041 6, 0xFFFF, sum = 0
5405 13:58:35.249089 7, 0xFFFF, sum = 0
5406 13:58:35.249174 8, 0xFFFF, sum = 0
5407 13:58:35.252876 9, 0xFFFF, sum = 0
5408 13:58:35.252961 10, 0x0, sum = 1
5409 13:58:35.255869 11, 0x0, sum = 2
5410 13:58:35.256004 12, 0x0, sum = 3
5411 13:58:35.259214 13, 0x0, sum = 4
5412 13:58:35.259298 best_step = 11
5413 13:58:35.259392
5414 13:58:35.259471 ==
5415 13:58:35.262846 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 13:58:35.265722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 13:58:35.269158 ==
5418 13:58:35.269242 RX Vref Scan: 0
5419 13:58:35.269326
5420 13:58:35.272687 RX Vref 0 -> 0, step: 1
5421 13:58:35.272770
5422 13:58:35.276136 RX Delay -61 -> 252, step: 4
5423 13:58:35.279225 iDelay=195, Bit 0, Center 100 (15 ~ 186) 172
5424 13:58:35.282166 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5425 13:58:35.289150 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5426 13:58:35.292075 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5427 13:58:35.295163 iDelay=195, Bit 4, Center 102 (15 ~ 190) 176
5428 13:58:35.298452 iDelay=195, Bit 5, Center 94 (11 ~ 178) 168
5429 13:58:35.301557 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5430 13:58:35.308151 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5431 13:58:35.311702 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5432 13:58:35.315215 iDelay=195, Bit 9, Center 78 (-9 ~ 166) 176
5433 13:58:35.318384 iDelay=195, Bit 10, Center 90 (3 ~ 178) 176
5434 13:58:35.321965 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5435 13:58:35.324859 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5436 13:58:35.331317 iDelay=195, Bit 13, Center 96 (11 ~ 182) 172
5437 13:58:35.335570 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5438 13:58:35.338398 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5439 13:58:35.338481 ==
5440 13:58:35.341451 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 13:58:35.344760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 13:58:35.347813 ==
5443 13:58:35.347944 DQS Delay:
5444 13:58:35.348029 DQS0 = 0, DQS1 = 0
5445 13:58:35.352049 DQM Delay:
5446 13:58:35.352131 DQM0 = 101, DQM1 = 90
5447 13:58:35.354510 DQ Delay:
5448 13:58:35.357991 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =98
5449 13:58:35.361340 DQ4 =102, DQ5 =94, DQ6 =110, DQ7 =108
5450 13:58:35.364311 DQ8 =82, DQ9 =78, DQ10 =90, DQ11 =84
5451 13:58:35.368549 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =96
5452 13:58:35.368637
5453 13:58:35.368709
5454 13:58:35.374146 [DQSOSCAuto] RK1, (LSB)MR18= 0x1511, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5455 13:58:35.377891 CH0 RK1: MR19=505, MR18=1511
5456 13:58:35.384688 CH0_RK1: MR19=0x505, MR18=0x1511, DQSOSC=415, MR23=63, INC=62, DEC=41
5457 13:58:35.387616 [RxdqsGatingPostProcess] freq 933
5458 13:58:35.390765 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5459 13:58:35.394661 best DQS0 dly(2T, 0.5T) = (0, 10)
5460 13:58:35.397686 best DQS1 dly(2T, 0.5T) = (0, 11)
5461 13:58:35.400578 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5462 13:58:35.404050 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5463 13:58:35.407307 best DQS0 dly(2T, 0.5T) = (0, 10)
5464 13:58:35.410480 best DQS1 dly(2T, 0.5T) = (0, 10)
5465 13:58:35.413797 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5466 13:58:35.417222 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5467 13:58:35.420268 Pre-setting of DQS Precalculation
5468 13:58:35.427350 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5469 13:58:35.427434 ==
5470 13:58:35.430093 Dram Type= 6, Freq= 0, CH_1, rank 0
5471 13:58:35.433437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 13:58:35.433521 ==
5473 13:58:35.440368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5474 13:58:35.443711 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5475 13:58:35.447268 [CA 0] Center 36 (6~67) winsize 62
5476 13:58:35.450960 [CA 1] Center 36 (6~67) winsize 62
5477 13:58:35.454094 [CA 2] Center 34 (4~64) winsize 61
5478 13:58:35.457497 [CA 3] Center 33 (3~64) winsize 62
5479 13:58:35.460561 [CA 4] Center 34 (3~65) winsize 63
5480 13:58:35.464404 [CA 5] Center 33 (3~64) winsize 62
5481 13:58:35.464503
5482 13:58:35.467015 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5483 13:58:35.467098
5484 13:58:35.470673 [CATrainingPosCal] consider 1 rank data
5485 13:58:35.473659 u2DelayCellTimex100 = 270/100 ps
5486 13:58:35.477112 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5487 13:58:35.483530 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5488 13:58:35.487204 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5489 13:58:35.490429 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5490 13:58:35.493721 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5491 13:58:35.497733 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5492 13:58:35.497817
5493 13:58:35.500318 CA PerBit enable=1, Macro0, CA PI delay=33
5494 13:58:35.500425
5495 13:58:35.503577 [CBTSetCACLKResult] CA Dly = 33
5496 13:58:35.503657 CS Dly: 5 (0~36)
5497 13:58:35.507537 ==
5498 13:58:35.510415 Dram Type= 6, Freq= 0, CH_1, rank 1
5499 13:58:35.513469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 13:58:35.513550 ==
5501 13:58:35.517040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5502 13:58:35.523613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5503 13:58:35.527451 [CA 0] Center 36 (6~67) winsize 62
5504 13:58:35.530619 [CA 1] Center 36 (6~67) winsize 62
5505 13:58:35.534263 [CA 2] Center 34 (4~64) winsize 61
5506 13:58:35.537195 [CA 3] Center 33 (3~64) winsize 62
5507 13:58:35.540529 [CA 4] Center 33 (3~64) winsize 62
5508 13:58:35.543820 [CA 5] Center 33 (3~64) winsize 62
5509 13:58:35.543908
5510 13:58:35.546874 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5511 13:58:35.547009
5512 13:58:35.550342 [CATrainingPosCal] consider 2 rank data
5513 13:58:35.553541 u2DelayCellTimex100 = 270/100 ps
5514 13:58:35.557255 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5515 13:58:35.563546 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5516 13:58:35.566975 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5517 13:58:35.570224 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5518 13:58:35.573805 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5519 13:58:35.576668 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5520 13:58:35.576748
5521 13:58:35.580119 CA PerBit enable=1, Macro0, CA PI delay=33
5522 13:58:35.580200
5523 13:58:35.583236 [CBTSetCACLKResult] CA Dly = 33
5524 13:58:35.586505 CS Dly: 6 (0~38)
5525 13:58:35.586585
5526 13:58:35.590114 ----->DramcWriteLeveling(PI) begin...
5527 13:58:35.590196 ==
5528 13:58:35.593695 Dram Type= 6, Freq= 0, CH_1, rank 0
5529 13:58:35.596585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 13:58:35.596666 ==
5531 13:58:35.600077 Write leveling (Byte 0): 24 => 24
5532 13:58:35.603472 Write leveling (Byte 1): 25 => 25
5533 13:58:35.606520 DramcWriteLeveling(PI) end<-----
5534 13:58:35.606601
5535 13:58:35.606665 ==
5536 13:58:35.609943 Dram Type= 6, Freq= 0, CH_1, rank 0
5537 13:58:35.613219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 13:58:35.613300 ==
5539 13:58:35.616772 [Gating] SW mode calibration
5540 13:58:35.622947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5541 13:58:35.629626 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5542 13:58:35.632852 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 13:58:35.636340 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 13:58:35.642881 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 13:58:35.646112 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 13:58:35.649411 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 13:58:35.655872 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 13:58:35.659138 0 14 24 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
5549 13:58:35.662761 0 14 28 | B1->B0 | 2b2b 2525 | 0 0 | (1 1) (0 0)
5550 13:58:35.669133 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5551 13:58:35.672669 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 13:58:35.675605 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 13:58:35.682577 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 13:58:35.685949 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 13:58:35.689166 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 13:58:35.695362 0 15 24 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
5557 13:58:35.698963 0 15 28 | B1->B0 | 3838 3d3d | 1 0 | (0 0) (0 0)
5558 13:58:35.702218 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 13:58:35.708851 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 13:58:35.712812 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 13:58:35.715462 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 13:58:35.722588 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 13:58:35.725209 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 13:58:35.728468 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5565 13:58:35.735432 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5566 13:58:35.738868 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 13:58:35.742254 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 13:58:35.748439 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 13:58:35.751758 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 13:58:35.754945 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 13:58:35.761313 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 13:58:35.764494 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 13:58:35.768520 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 13:58:35.774657 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 13:58:35.778056 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 13:58:35.781141 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 13:58:35.787593 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 13:58:35.791124 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 13:58:35.794269 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 13:58:35.801171 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5581 13:58:35.804446 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5582 13:58:35.807650 Total UI for P1: 0, mck2ui 16
5583 13:58:35.810934 best dqsien dly found for B0: ( 1, 2, 26)
5584 13:58:35.814276 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 13:58:35.817337 Total UI for P1: 0, mck2ui 16
5586 13:58:35.820700 best dqsien dly found for B1: ( 1, 2, 26)
5587 13:58:35.823846 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5588 13:58:35.827308 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5589 13:58:35.830841
5590 13:58:35.833830 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5591 13:58:35.837309 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5592 13:58:35.840154 [Gating] SW calibration Done
5593 13:58:35.840232 ==
5594 13:58:35.843858 Dram Type= 6, Freq= 0, CH_1, rank 0
5595 13:58:35.846739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 13:58:35.846816 ==
5597 13:58:35.850076 RX Vref Scan: 0
5598 13:58:35.850154
5599 13:58:35.850219 RX Vref 0 -> 0, step: 1
5600 13:58:35.850280
5601 13:58:35.853642 RX Delay -80 -> 252, step: 8
5602 13:58:35.856766 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5603 13:58:35.860346 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5604 13:58:35.867007 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5605 13:58:35.869881 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5606 13:58:35.873528 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5607 13:58:35.876588 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5608 13:58:35.880587 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5609 13:58:35.883344 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5610 13:58:35.890408 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5611 13:58:35.893296 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5612 13:58:35.896266 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5613 13:58:35.899819 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5614 13:58:35.903386 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5615 13:58:35.909315 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5616 13:58:35.913361 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5617 13:58:35.916293 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5618 13:58:35.916364 ==
5619 13:58:35.919513 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 13:58:35.922855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 13:58:35.922932 ==
5622 13:58:35.926351 DQS Delay:
5623 13:58:35.926423 DQS0 = 0, DQS1 = 0
5624 13:58:35.930264 DQM Delay:
5625 13:58:35.930336 DQM0 = 99, DQM1 = 95
5626 13:58:35.930397 DQ Delay:
5627 13:58:35.932530 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5628 13:58:35.936041 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =95
5629 13:58:35.939078 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =87
5630 13:58:35.945911 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5631 13:58:35.945997
5632 13:58:35.946063
5633 13:58:35.946122 ==
5634 13:58:35.949046 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 13:58:35.952574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 13:58:35.952647 ==
5637 13:58:35.952709
5638 13:58:35.952767
5639 13:58:35.956441 TX Vref Scan disable
5640 13:58:35.956530 == TX Byte 0 ==
5641 13:58:35.962640 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5642 13:58:35.965545 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5643 13:58:35.965622 == TX Byte 1 ==
5644 13:58:35.972573 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5645 13:58:35.975469 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5646 13:58:35.975548 ==
5647 13:58:35.979173 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 13:58:35.982108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 13:58:35.982184 ==
5650 13:58:35.982245
5651 13:58:35.985735
5652 13:58:35.985808 TX Vref Scan disable
5653 13:58:35.988504 == TX Byte 0 ==
5654 13:58:35.992045 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5655 13:58:35.995864 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5656 13:58:35.998802 == TX Byte 1 ==
5657 13:58:36.001998 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5658 13:58:36.008471 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5659 13:58:36.008545
5660 13:58:36.008605 [DATLAT]
5661 13:58:36.008661 Freq=933, CH1 RK0
5662 13:58:36.008720
5663 13:58:36.011632 DATLAT Default: 0xd
5664 13:58:36.011703 0, 0xFFFF, sum = 0
5665 13:58:36.015173 1, 0xFFFF, sum = 0
5666 13:58:36.015242 2, 0xFFFF, sum = 0
5667 13:58:36.018553 3, 0xFFFF, sum = 0
5668 13:58:36.021520 4, 0xFFFF, sum = 0
5669 13:58:36.021608 5, 0xFFFF, sum = 0
5670 13:58:36.025670 6, 0xFFFF, sum = 0
5671 13:58:36.025740 7, 0xFFFF, sum = 0
5672 13:58:36.028206 8, 0xFFFF, sum = 0
5673 13:58:36.028289 9, 0xFFFF, sum = 0
5674 13:58:36.031458 10, 0x0, sum = 1
5675 13:58:36.031545 11, 0x0, sum = 2
5676 13:58:36.035253 12, 0x0, sum = 3
5677 13:58:36.035322 13, 0x0, sum = 4
5678 13:58:36.035384 best_step = 11
5679 13:58:36.035442
5680 13:58:36.038271 ==
5681 13:58:36.042017 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 13:58:36.044967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 13:58:36.045033 ==
5684 13:58:36.045091 RX Vref Scan: 1
5685 13:58:36.045151
5686 13:58:36.049269 RX Vref 0 -> 0, step: 1
5687 13:58:36.049345
5688 13:58:36.051592 RX Delay -61 -> 252, step: 4
5689 13:58:36.051659
5690 13:58:36.054884 Set Vref, RX VrefLevel [Byte0]: 50
5691 13:58:36.057982 [Byte1]: 54
5692 13:58:36.058050
5693 13:58:36.061330 Final RX Vref Byte 0 = 50 to rank0
5694 13:58:36.064804 Final RX Vref Byte 1 = 54 to rank0
5695 13:58:36.067987 Final RX Vref Byte 0 = 50 to rank1
5696 13:58:36.071337 Final RX Vref Byte 1 = 54 to rank1==
5697 13:58:36.074634 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 13:58:36.078123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 13:58:36.081800 ==
5700 13:58:36.081884 DQS Delay:
5701 13:58:36.081947 DQS0 = 0, DQS1 = 0
5702 13:58:36.084603 DQM Delay:
5703 13:58:36.084707 DQM0 = 98, DQM1 = 94
5704 13:58:36.088216 DQ Delay:
5705 13:58:36.091285 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =98
5706 13:58:36.094382 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5707 13:58:36.097568 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =90
5708 13:58:36.100960 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5709 13:58:36.101041
5710 13:58:36.101105
5711 13:58:36.107655 [DQSOSCAuto] RK0, (LSB)MR18= 0x717, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5712 13:58:36.110938 CH1 RK0: MR19=505, MR18=717
5713 13:58:36.117600 CH1_RK0: MR19=0x505, MR18=0x717, DQSOSC=414, MR23=63, INC=63, DEC=42
5714 13:58:36.117722
5715 13:58:36.120981 ----->DramcWriteLeveling(PI) begin...
5716 13:58:36.121053 ==
5717 13:58:36.124094 Dram Type= 6, Freq= 0, CH_1, rank 1
5718 13:58:36.127898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 13:58:36.127977 ==
5720 13:58:36.130675 Write leveling (Byte 0): 28 => 28
5721 13:58:36.134279 Write leveling (Byte 1): 29 => 29
5722 13:58:36.137395 DramcWriteLeveling(PI) end<-----
5723 13:58:36.137459
5724 13:58:36.137516 ==
5725 13:58:36.140859 Dram Type= 6, Freq= 0, CH_1, rank 1
5726 13:58:36.144127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 13:58:36.147363 ==
5728 13:58:36.147464 [Gating] SW mode calibration
5729 13:58:36.154231 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5730 13:58:36.160584 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5731 13:58:36.164007 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5732 13:58:36.170421 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5733 13:58:36.173507 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5734 13:58:36.177101 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5735 13:58:36.183869 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5736 13:58:36.186773 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 13:58:36.189914 0 14 24 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (0 0)
5738 13:58:36.196885 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
5739 13:58:36.199809 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5740 13:58:36.203144 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5741 13:58:36.209789 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5742 13:58:36.213302 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5743 13:58:36.216446 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5744 13:58:36.222926 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 13:58:36.226647 0 15 24 | B1->B0 | 2525 3434 | 0 1 | (0 0) (0 0)
5746 13:58:36.229565 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5747 13:58:36.236305 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5748 13:58:36.239660 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5749 13:58:36.243444 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5750 13:58:36.249185 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5751 13:58:36.253587 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 13:58:36.256536 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 13:58:36.262395 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5754 13:58:36.265803 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 13:58:36.269336 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 13:58:36.275617 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 13:58:36.278794 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 13:58:36.282019 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 13:58:36.288392 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 13:58:36.291753 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 13:58:36.295610 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 13:58:36.302005 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 13:58:36.305639 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 13:58:36.308449 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 13:58:36.314885 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 13:58:36.318423 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 13:58:36.321621 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 13:58:36.328255 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 13:58:36.331653 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5770 13:58:36.335018 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 13:58:36.337948 Total UI for P1: 0, mck2ui 16
5772 13:58:36.341456 best dqsien dly found for B0: ( 1, 2, 24)
5773 13:58:36.345001 Total UI for P1: 0, mck2ui 16
5774 13:58:36.348145 best dqsien dly found for B1: ( 1, 2, 26)
5775 13:58:36.351761 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5776 13:58:36.354631 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5777 13:58:36.357794
5778 13:58:36.361125 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5779 13:58:36.364303 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5780 13:58:36.368267 [Gating] SW calibration Done
5781 13:58:36.368336 ==
5782 13:58:36.370807 Dram Type= 6, Freq= 0, CH_1, rank 1
5783 13:58:36.375014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 13:58:36.375085 ==
5785 13:58:36.375185 RX Vref Scan: 0
5786 13:58:36.377946
5787 13:58:36.378019 RX Vref 0 -> 0, step: 1
5788 13:58:36.378080
5789 13:58:36.381108 RX Delay -80 -> 252, step: 8
5790 13:58:36.384489 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5791 13:58:36.388339 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5792 13:58:36.394465 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5793 13:58:36.398041 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5794 13:58:36.400612 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5795 13:58:36.404798 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5796 13:58:36.407317 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5797 13:58:36.410605 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5798 13:58:36.417378 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5799 13:58:36.421236 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5800 13:58:36.424016 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5801 13:58:36.427186 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5802 13:58:36.430876 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5803 13:58:36.437049 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5804 13:58:36.440544 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5805 13:58:36.443546 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5806 13:58:36.443618 ==
5807 13:58:36.447350 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 13:58:36.450127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 13:58:36.450203 ==
5810 13:58:36.453635 DQS Delay:
5811 13:58:36.453736 DQS0 = 0, DQS1 = 0
5812 13:58:36.456918 DQM Delay:
5813 13:58:36.456988 DQM0 = 97, DQM1 = 94
5814 13:58:36.457047 DQ Delay:
5815 13:58:36.460128 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5816 13:58:36.463379 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5817 13:58:36.467132 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5818 13:58:36.470181 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5819 13:58:36.473724
5820 13:58:36.473797
5821 13:58:36.473858 ==
5822 13:58:36.476736 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 13:58:36.480029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 13:58:36.480100 ==
5825 13:58:36.480163
5826 13:58:36.480220
5827 13:58:36.483107 TX Vref Scan disable
5828 13:58:36.483177 == TX Byte 0 ==
5829 13:58:36.490109 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5830 13:58:36.493416 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5831 13:58:36.493487 == TX Byte 1 ==
5832 13:58:36.499889 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5833 13:58:36.502912 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5834 13:58:36.502983 ==
5835 13:58:36.506542 Dram Type= 6, Freq= 0, CH_1, rank 1
5836 13:58:36.510032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5837 13:58:36.510101 ==
5838 13:58:36.510161
5839 13:58:36.510221
5840 13:58:36.512745 TX Vref Scan disable
5841 13:58:36.515891 == TX Byte 0 ==
5842 13:58:36.519612 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5843 13:58:36.522763 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5844 13:58:36.525796 == TX Byte 1 ==
5845 13:58:36.529765 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5846 13:58:36.533074 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5847 13:58:36.533149
5848 13:58:36.536667 [DATLAT]
5849 13:58:36.536743 Freq=933, CH1 RK1
5850 13:58:36.536804
5851 13:58:36.539401 DATLAT Default: 0xb
5852 13:58:36.539471 0, 0xFFFF, sum = 0
5853 13:58:36.542558 1, 0xFFFF, sum = 0
5854 13:58:36.542632 2, 0xFFFF, sum = 0
5855 13:58:36.546056 3, 0xFFFF, sum = 0
5856 13:58:36.546131 4, 0xFFFF, sum = 0
5857 13:58:36.549050 5, 0xFFFF, sum = 0
5858 13:58:36.549146 6, 0xFFFF, sum = 0
5859 13:58:36.552449 7, 0xFFFF, sum = 0
5860 13:58:36.556019 8, 0xFFFF, sum = 0
5861 13:58:36.556097 9, 0xFFFF, sum = 0
5862 13:58:36.559289 10, 0x0, sum = 1
5863 13:58:36.559358 11, 0x0, sum = 2
5864 13:58:36.559422 12, 0x0, sum = 3
5865 13:58:36.562790 13, 0x0, sum = 4
5866 13:58:36.562864 best_step = 11
5867 13:58:36.562923
5868 13:58:36.562979 ==
5869 13:58:36.565853 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 13:58:36.572665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 13:58:36.572740 ==
5872 13:58:36.572806 RX Vref Scan: 0
5873 13:58:36.572863
5874 13:58:36.575669 RX Vref 0 -> 0, step: 1
5875 13:58:36.575740
5876 13:58:36.579094 RX Delay -53 -> 252, step: 4
5877 13:58:36.582595 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5878 13:58:36.588753 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5879 13:58:36.592024 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5880 13:58:36.595130 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5881 13:58:36.598772 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5882 13:58:36.602022 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5883 13:58:36.605235 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5884 13:58:36.611756 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5885 13:58:36.615352 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5886 13:58:36.618492 iDelay=199, Bit 9, Center 86 (-5 ~ 178) 184
5887 13:58:36.621647 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5888 13:58:36.625054 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5889 13:58:36.631514 iDelay=199, Bit 12, Center 100 (7 ~ 194) 188
5890 13:58:36.634795 iDelay=199, Bit 13, Center 100 (7 ~ 194) 188
5891 13:58:36.639475 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5892 13:58:36.641297 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5893 13:58:36.641367 ==
5894 13:58:36.645196 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 13:58:36.652516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 13:58:36.652618 ==
5897 13:58:36.652715 DQS Delay:
5898 13:58:36.654524 DQS0 = 0, DQS1 = 0
5899 13:58:36.654623 DQM Delay:
5900 13:58:36.654689 DQM0 = 96, DQM1 = 93
5901 13:58:36.658784 DQ Delay:
5902 13:58:36.661538 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5903 13:58:36.664757 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =92
5904 13:58:36.668387 DQ8 =82, DQ9 =86, DQ10 =92, DQ11 =86
5905 13:58:36.671522 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5906 13:58:36.671603
5907 13:58:36.671667
5908 13:58:36.678809 [DQSOSCAuto] RK1, (LSB)MR18= 0xd25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5909 13:58:36.681375 CH1 RK1: MR19=505, MR18=D25
5910 13:58:36.687785 CH1_RK1: MR19=0x505, MR18=0xD25, DQSOSC=410, MR23=63, INC=64, DEC=42
5911 13:58:36.691049 [RxdqsGatingPostProcess] freq 933
5912 13:58:36.698016 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5913 13:58:36.698098 best DQS0 dly(2T, 0.5T) = (0, 10)
5914 13:58:36.701157 best DQS1 dly(2T, 0.5T) = (0, 10)
5915 13:58:36.703812 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5916 13:58:36.707673 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5917 13:58:36.711115 best DQS0 dly(2T, 0.5T) = (0, 10)
5918 13:58:36.715051 best DQS1 dly(2T, 0.5T) = (0, 10)
5919 13:58:36.717326 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5920 13:58:36.720812 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5921 13:58:36.724101 Pre-setting of DQS Precalculation
5922 13:58:36.730505 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5923 13:58:36.737302 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5924 13:58:36.743777 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5925 13:58:36.743858
5926 13:58:36.743946
5927 13:58:36.746896 [Calibration Summary] 1866 Mbps
5928 13:58:36.746977 CH 0, Rank 0
5929 13:58:36.750655 SW Impedance : PASS
5930 13:58:36.754099 DUTY Scan : NO K
5931 13:58:36.754180 ZQ Calibration : PASS
5932 13:58:36.756865 Jitter Meter : NO K
5933 13:58:36.760693 CBT Training : PASS
5934 13:58:36.760789 Write leveling : PASS
5935 13:58:36.763440 RX DQS gating : PASS
5936 13:58:36.763521 RX DQ/DQS(RDDQC) : PASS
5937 13:58:36.766732 TX DQ/DQS : PASS
5938 13:58:36.770441 RX DATLAT : PASS
5939 13:58:36.770540 RX DQ/DQS(Engine): PASS
5940 13:58:36.773223 TX OE : NO K
5941 13:58:36.773320 All Pass.
5942 13:58:36.773423
5943 13:58:36.777021 CH 0, Rank 1
5944 13:58:36.777119 SW Impedance : PASS
5945 13:58:36.779866 DUTY Scan : NO K
5946 13:58:36.783294 ZQ Calibration : PASS
5947 13:58:36.783393 Jitter Meter : NO K
5948 13:58:36.786450 CBT Training : PASS
5949 13:58:36.789816 Write leveling : PASS
5950 13:58:36.789915 RX DQS gating : PASS
5951 13:58:36.793710 RX DQ/DQS(RDDQC) : PASS
5952 13:58:36.796686 TX DQ/DQS : PASS
5953 13:58:36.796784 RX DATLAT : PASS
5954 13:58:36.799967 RX DQ/DQS(Engine): PASS
5955 13:58:36.802836 TX OE : NO K
5956 13:58:36.802934 All Pass.
5957 13:58:36.803030
5958 13:58:36.803105 CH 1, Rank 0
5959 13:58:36.806699 SW Impedance : PASS
5960 13:58:36.809893 DUTY Scan : NO K
5961 13:58:36.810017 ZQ Calibration : PASS
5962 13:58:36.812901 Jitter Meter : NO K
5963 13:58:36.816108 CBT Training : PASS
5964 13:58:36.816188 Write leveling : PASS
5965 13:58:36.819410 RX DQS gating : PASS
5966 13:58:36.823073 RX DQ/DQS(RDDQC) : PASS
5967 13:58:36.823171 TX DQ/DQS : PASS
5968 13:58:36.826256 RX DATLAT : PASS
5969 13:58:36.829594 RX DQ/DQS(Engine): PASS
5970 13:58:36.829692 TX OE : NO K
5971 13:58:36.832675 All Pass.
5972 13:58:36.832773
5973 13:58:36.832870 CH 1, Rank 1
5974 13:58:36.836236 SW Impedance : PASS
5975 13:58:36.836338 DUTY Scan : NO K
5976 13:58:36.839477 ZQ Calibration : PASS
5977 13:58:36.842395 Jitter Meter : NO K
5978 13:58:36.842493 CBT Training : PASS
5979 13:58:36.845748 Write leveling : PASS
5980 13:58:36.849339 RX DQS gating : PASS
5981 13:58:36.849421 RX DQ/DQS(RDDQC) : PASS
5982 13:58:36.852950 TX DQ/DQS : PASS
5983 13:58:36.853031 RX DATLAT : PASS
5984 13:58:36.856197 RX DQ/DQS(Engine): PASS
5985 13:58:36.858923 TX OE : NO K
5986 13:58:36.859007 All Pass.
5987 13:58:36.859073
5988 13:58:36.862483 DramC Write-DBI off
5989 13:58:36.862567 PER_BANK_REFRESH: Hybrid Mode
5990 13:58:36.865562 TX_TRACKING: ON
5991 13:58:36.875815 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5992 13:58:36.879465 [FAST_K] Save calibration result to emmc
5993 13:58:36.881941 dramc_set_vcore_voltage set vcore to 650000
5994 13:58:36.885470 Read voltage for 400, 6
5995 13:58:36.885546 Vio18 = 0
5996 13:58:36.885609 Vcore = 650000
5997 13:58:36.888827 Vdram = 0
5998 13:58:36.888895 Vddq = 0
5999 13:58:36.888959 Vmddr = 0
6000 13:58:36.895097 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6001 13:58:36.898448 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6002 13:58:36.901864 MEM_TYPE=3, freq_sel=20
6003 13:58:36.905719 sv_algorithm_assistance_LP4_800
6004 13:58:36.908184 ============ PULL DRAM RESETB DOWN ============
6005 13:58:36.911534 ========== PULL DRAM RESETB DOWN end =========
6006 13:58:36.918398 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6007 13:58:36.921790 ===================================
6008 13:58:36.921866 LPDDR4 DRAM CONFIGURATION
6009 13:58:36.924755 ===================================
6010 13:58:36.928200 EX_ROW_EN[0] = 0x0
6011 13:58:36.931810 EX_ROW_EN[1] = 0x0
6012 13:58:36.931914 LP4Y_EN = 0x0
6013 13:58:36.935181 WORK_FSP = 0x0
6014 13:58:36.935249 WL = 0x2
6015 13:58:36.938209 RL = 0x2
6016 13:58:36.938307 BL = 0x2
6017 13:58:36.941783 RPST = 0x0
6018 13:58:36.941859 RD_PRE = 0x0
6019 13:58:36.944526 WR_PRE = 0x1
6020 13:58:36.944598 WR_PST = 0x0
6021 13:58:36.948258 DBI_WR = 0x0
6022 13:58:36.948366 DBI_RD = 0x0
6023 13:58:36.951365 OTF = 0x1
6024 13:58:36.954615 ===================================
6025 13:58:36.958279 ===================================
6026 13:58:36.958350 ANA top config
6027 13:58:36.961849 ===================================
6028 13:58:36.964886 DLL_ASYNC_EN = 0
6029 13:58:36.967600 ALL_SLAVE_EN = 1
6030 13:58:36.971687 NEW_RANK_MODE = 1
6031 13:58:36.971785 DLL_IDLE_MODE = 1
6032 13:58:36.974561 LP45_APHY_COMB_EN = 1
6033 13:58:36.977874 TX_ODT_DIS = 1
6034 13:58:36.981116 NEW_8X_MODE = 1
6035 13:58:36.984735 ===================================
6036 13:58:36.988066 ===================================
6037 13:58:36.991074 data_rate = 800
6038 13:58:36.991188 CKR = 1
6039 13:58:36.994637 DQ_P2S_RATIO = 4
6040 13:58:36.997987 ===================================
6041 13:58:37.000854 CA_P2S_RATIO = 4
6042 13:58:37.003900 DQ_CA_OPEN = 0
6043 13:58:37.007571 DQ_SEMI_OPEN = 1
6044 13:58:37.010744 CA_SEMI_OPEN = 1
6045 13:58:37.010842 CA_FULL_RATE = 0
6046 13:58:37.014316 DQ_CKDIV4_EN = 0
6047 13:58:37.017237 CA_CKDIV4_EN = 1
6048 13:58:37.020975 CA_PREDIV_EN = 0
6049 13:58:37.024155 PH8_DLY = 0
6050 13:58:37.026978 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6051 13:58:37.030574 DQ_AAMCK_DIV = 0
6052 13:58:37.030644 CA_AAMCK_DIV = 0
6053 13:58:37.034674 CA_ADMCK_DIV = 4
6054 13:58:37.037103 DQ_TRACK_CA_EN = 0
6055 13:58:37.040880 CA_PICK = 800
6056 13:58:37.043877 CA_MCKIO = 400
6057 13:58:37.047560 MCKIO_SEMI = 400
6058 13:58:37.050671 PLL_FREQ = 3016
6059 13:58:37.050773 DQ_UI_PI_RATIO = 32
6060 13:58:37.053647 CA_UI_PI_RATIO = 32
6061 13:58:37.057061 ===================================
6062 13:58:37.060640 ===================================
6063 13:58:37.063669 memory_type:LPDDR4
6064 13:58:37.067384 GP_NUM : 10
6065 13:58:37.067489 SRAM_EN : 1
6066 13:58:37.070043 MD32_EN : 0
6067 13:58:37.073741 ===================================
6068 13:58:37.076421 [ANA_INIT] >>>>>>>>>>>>>>
6069 13:58:37.080558 <<<<<< [CONFIGURE PHASE]: ANA_TX
6070 13:58:37.083440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6071 13:58:37.087014 ===================================
6072 13:58:37.087084 data_rate = 800,PCW = 0X7400
6073 13:58:37.090075 ===================================
6074 13:58:37.092997 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6075 13:58:37.099741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6076 13:58:37.113014 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6077 13:58:37.116255 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6078 13:58:37.119657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6079 13:58:37.123096 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6080 13:58:37.126173 [ANA_INIT] flow start
6081 13:58:37.126251 [ANA_INIT] PLL >>>>>>>>
6082 13:58:37.129083 [ANA_INIT] PLL <<<<<<<<
6083 13:58:37.132527 [ANA_INIT] MIDPI >>>>>>>>
6084 13:58:37.132648 [ANA_INIT] MIDPI <<<<<<<<
6085 13:58:37.135818 [ANA_INIT] DLL >>>>>>>>
6086 13:58:37.140155 [ANA_INIT] flow end
6087 13:58:37.142405 ============ LP4 DIFF to SE enter ============
6088 13:58:37.145991 ============ LP4 DIFF to SE exit ============
6089 13:58:37.149127 [ANA_INIT] <<<<<<<<<<<<<
6090 13:58:37.152493 [Flow] Enable top DCM control >>>>>
6091 13:58:37.156059 [Flow] Enable top DCM control <<<<<
6092 13:58:37.159450 Enable DLL master slave shuffle
6093 13:58:37.165912 ==============================================================
6094 13:58:37.165988 Gating Mode config
6095 13:58:37.172212 ==============================================================
6096 13:58:37.172287 Config description:
6097 13:58:37.182199 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6098 13:58:37.188684 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6099 13:58:37.195518 SELPH_MODE 0: By rank 1: By Phase
6100 13:58:37.198393 ==============================================================
6101 13:58:37.201954 GAT_TRACK_EN = 0
6102 13:58:37.205261 RX_GATING_MODE = 2
6103 13:58:37.208737 RX_GATING_TRACK_MODE = 2
6104 13:58:37.212007 SELPH_MODE = 1
6105 13:58:37.215426 PICG_EARLY_EN = 1
6106 13:58:37.218195 VALID_LAT_VALUE = 1
6107 13:58:37.224755 ==============================================================
6108 13:58:37.228115 Enter into Gating configuration >>>>
6109 13:58:37.231383 Exit from Gating configuration <<<<
6110 13:58:37.234671 Enter into DVFS_PRE_config >>>>>
6111 13:58:37.244638 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6112 13:58:37.248307 Exit from DVFS_PRE_config <<<<<
6113 13:58:37.251229 Enter into PICG configuration >>>>
6114 13:58:37.254873 Exit from PICG configuration <<<<
6115 13:58:37.257808 [RX_INPUT] configuration >>>>>
6116 13:58:37.257880 [RX_INPUT] configuration <<<<<
6117 13:58:37.264522 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6118 13:58:37.271155 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6119 13:58:37.274757 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6120 13:58:37.281162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6121 13:58:37.287812 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6122 13:58:37.294155 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6123 13:58:37.297605 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6124 13:58:37.301329 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6125 13:58:37.307468 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6126 13:58:37.310625 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6127 13:58:37.314548 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6128 13:58:37.320722 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6129 13:58:37.324106 ===================================
6130 13:58:37.324191 LPDDR4 DRAM CONFIGURATION
6131 13:58:37.327174 ===================================
6132 13:58:37.330545 EX_ROW_EN[0] = 0x0
6133 13:58:37.333848 EX_ROW_EN[1] = 0x0
6134 13:58:37.333931 LP4Y_EN = 0x0
6135 13:58:37.337084 WORK_FSP = 0x0
6136 13:58:37.337167 WL = 0x2
6137 13:58:37.340361 RL = 0x2
6138 13:58:37.340443 BL = 0x2
6139 13:58:37.343933 RPST = 0x0
6140 13:58:37.344032 RD_PRE = 0x0
6141 13:58:37.347141 WR_PRE = 0x1
6142 13:58:37.347238 WR_PST = 0x0
6143 13:58:37.350407 DBI_WR = 0x0
6144 13:58:37.350491 DBI_RD = 0x0
6145 13:58:37.353242 OTF = 0x1
6146 13:58:37.356588 ===================================
6147 13:58:37.360272 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6148 13:58:37.363828 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6149 13:58:37.369892 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6150 13:58:37.373634 ===================================
6151 13:58:37.373717 LPDDR4 DRAM CONFIGURATION
6152 13:58:37.376686 ===================================
6153 13:58:37.379805 EX_ROW_EN[0] = 0x10
6154 13:58:37.382842 EX_ROW_EN[1] = 0x0
6155 13:58:37.382979 LP4Y_EN = 0x0
6156 13:58:37.386366 WORK_FSP = 0x0
6157 13:58:37.386449 WL = 0x2
6158 13:58:37.389489 RL = 0x2
6159 13:58:37.389572 BL = 0x2
6160 13:58:37.392856 RPST = 0x0
6161 13:58:37.392939 RD_PRE = 0x0
6162 13:58:37.396503 WR_PRE = 0x1
6163 13:58:37.396585 WR_PST = 0x0
6164 13:58:37.399604 DBI_WR = 0x0
6165 13:58:37.399686 DBI_RD = 0x0
6166 13:58:37.402923 OTF = 0x1
6167 13:58:37.406066 ===================================
6168 13:58:37.412884 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6169 13:58:37.415773 nWR fixed to 30
6170 13:58:37.419507 [ModeRegInit_LP4] CH0 RK0
6171 13:58:37.419593 [ModeRegInit_LP4] CH0 RK1
6172 13:58:37.423174 [ModeRegInit_LP4] CH1 RK0
6173 13:58:37.426245 [ModeRegInit_LP4] CH1 RK1
6174 13:58:37.426328 match AC timing 19
6175 13:58:37.432823 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6176 13:58:37.435710 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6177 13:58:37.439193 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6178 13:58:37.445976 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6179 13:58:37.449092 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6180 13:58:37.449226 ==
6181 13:58:37.452526 Dram Type= 6, Freq= 0, CH_0, rank 0
6182 13:58:37.455395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6183 13:58:37.455465 ==
6184 13:58:37.462153 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6185 13:58:37.468940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6186 13:58:37.472038 [CA 0] Center 36 (8~64) winsize 57
6187 13:58:37.475414 [CA 1] Center 36 (8~64) winsize 57
6188 13:58:37.478543 [CA 2] Center 36 (8~64) winsize 57
6189 13:58:37.482535 [CA 3] Center 36 (8~64) winsize 57
6190 13:58:37.482622 [CA 4] Center 36 (8~64) winsize 57
6191 13:58:37.485121 [CA 5] Center 36 (8~64) winsize 57
6192 13:58:37.485192
6193 13:58:37.491812 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6194 13:58:37.491885
6195 13:58:37.495313 [CATrainingPosCal] consider 1 rank data
6196 13:58:37.498716 u2DelayCellTimex100 = 270/100 ps
6197 13:58:37.501996 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6198 13:58:37.505317 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6199 13:58:37.508336 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6200 13:58:37.512027 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6201 13:58:37.515195 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6202 13:58:37.518374 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 13:58:37.518444
6204 13:58:37.521813 CA PerBit enable=1, Macro0, CA PI delay=36
6205 13:58:37.521891
6206 13:58:37.524577 [CBTSetCACLKResult] CA Dly = 36
6207 13:58:37.528507 CS Dly: 1 (0~32)
6208 13:58:37.528583 ==
6209 13:58:37.531584 Dram Type= 6, Freq= 0, CH_0, rank 1
6210 13:58:37.535099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6211 13:58:37.535168 ==
6212 13:58:37.541163 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6213 13:58:37.547898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6214 13:58:37.551303 [CA 0] Center 36 (8~64) winsize 57
6215 13:58:37.554977 [CA 1] Center 36 (8~64) winsize 57
6216 13:58:37.555047 [CA 2] Center 36 (8~64) winsize 57
6217 13:58:37.557617 [CA 3] Center 36 (8~64) winsize 57
6218 13:58:37.561043 [CA 4] Center 36 (8~64) winsize 57
6219 13:58:37.564477 [CA 5] Center 36 (8~64) winsize 57
6220 13:58:37.564548
6221 13:58:37.567934 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6222 13:58:37.571267
6223 13:58:37.574113 [CATrainingPosCal] consider 2 rank data
6224 13:58:37.574182 u2DelayCellTimex100 = 270/100 ps
6225 13:58:37.581041 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 13:58:37.584345 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 13:58:37.587706 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 13:58:37.590799 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 13:58:37.594188 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 13:58:37.597290 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 13:58:37.597360
6232 13:58:37.600856 CA PerBit enable=1, Macro0, CA PI delay=36
6233 13:58:37.600927
6234 13:58:37.604235 [CBTSetCACLKResult] CA Dly = 36
6235 13:58:37.607411 CS Dly: 1 (0~32)
6236 13:58:37.607497
6237 13:58:37.611279 ----->DramcWriteLeveling(PI) begin...
6238 13:58:37.611355 ==
6239 13:58:37.614155 Dram Type= 6, Freq= 0, CH_0, rank 0
6240 13:58:37.617545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 13:58:37.617615 ==
6242 13:58:37.620575 Write leveling (Byte 0): 40 => 8
6243 13:58:37.623812 Write leveling (Byte 1): 40 => 8
6244 13:58:37.627100 DramcWriteLeveling(PI) end<-----
6245 13:58:37.627170
6246 13:58:37.627233 ==
6247 13:58:37.630454 Dram Type= 6, Freq= 0, CH_0, rank 0
6248 13:58:37.633777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6249 13:58:37.633848 ==
6250 13:58:37.636929 [Gating] SW mode calibration
6251 13:58:37.643443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6252 13:58:37.650499 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6253 13:58:37.653353 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6254 13:58:37.659946 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6255 13:58:37.663218 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6256 13:58:37.666288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6257 13:58:37.673040 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6258 13:58:37.676617 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6259 13:58:37.679381 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6260 13:58:37.686084 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6261 13:58:37.689235 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6262 13:58:37.692711 Total UI for P1: 0, mck2ui 16
6263 13:58:37.696164 best dqsien dly found for B0: ( 0, 14, 24)
6264 13:58:37.699876 Total UI for P1: 0, mck2ui 16
6265 13:58:37.702545 best dqsien dly found for B1: ( 0, 14, 24)
6266 13:58:37.705630 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6267 13:58:37.709920 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6268 13:58:37.710012
6269 13:58:37.712254 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6270 13:58:37.715809 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6271 13:58:37.719256 [Gating] SW calibration Done
6272 13:58:37.719330 ==
6273 13:58:37.722374 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 13:58:37.725587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 13:58:37.729141 ==
6276 13:58:37.729209 RX Vref Scan: 0
6277 13:58:37.729294
6278 13:58:37.732384 RX Vref 0 -> 0, step: 1
6279 13:58:37.732455
6280 13:58:37.735434 RX Delay -410 -> 252, step: 16
6281 13:58:37.739024 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6282 13:58:37.742185 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6283 13:58:37.745533 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6284 13:58:37.752295 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6285 13:58:37.755282 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6286 13:58:37.759003 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6287 13:58:37.762028 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6288 13:58:37.768593 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6289 13:58:37.772218 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6290 13:58:37.775400 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6291 13:58:37.782016 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6292 13:58:37.785009 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6293 13:58:37.788408 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6294 13:58:37.791398 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6295 13:58:37.798575 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6296 13:58:37.801817 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6297 13:58:37.801885 ==
6298 13:58:37.804999 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 13:58:37.808208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 13:58:37.808286 ==
6301 13:58:37.811699 DQS Delay:
6302 13:58:37.811766 DQS0 = 35, DQS1 = 59
6303 13:58:37.815275 DQM Delay:
6304 13:58:37.815345 DQM0 = 5, DQM1 = 18
6305 13:58:37.815408 DQ Delay:
6306 13:58:37.818026 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6307 13:58:37.821213 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6308 13:58:37.825034 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6309 13:58:37.827859 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6310 13:58:37.827940
6311 13:58:37.828001
6312 13:58:37.828058 ==
6313 13:58:37.831253 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 13:58:37.837620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 13:58:37.837692 ==
6316 13:58:37.837752
6317 13:58:37.837813
6318 13:58:37.837868 TX Vref Scan disable
6319 13:58:37.841109 == TX Byte 0 ==
6320 13:58:37.844341 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6321 13:58:37.848143 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6322 13:58:37.850915 == TX Byte 1 ==
6323 13:58:37.854029 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6324 13:58:37.857863 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6325 13:58:37.857935 ==
6326 13:58:37.860887 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 13:58:37.867372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 13:58:37.867447 ==
6329 13:58:37.867509
6330 13:58:37.867566
6331 13:58:37.871191 TX Vref Scan disable
6332 13:58:37.871257 == TX Byte 0 ==
6333 13:58:37.873881 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6334 13:58:37.880451 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6335 13:58:37.880530 == TX Byte 1 ==
6336 13:58:37.884347 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6337 13:58:37.887175 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6338 13:58:37.890377
6339 13:58:37.890517 [DATLAT]
6340 13:58:37.890578 Freq=400, CH0 RK0
6341 13:58:37.890635
6342 13:58:37.894159 DATLAT Default: 0xf
6343 13:58:37.894223 0, 0xFFFF, sum = 0
6344 13:58:37.897135 1, 0xFFFF, sum = 0
6345 13:58:37.897202 2, 0xFFFF, sum = 0
6346 13:58:37.900852 3, 0xFFFF, sum = 0
6347 13:58:37.900919 4, 0xFFFF, sum = 0
6348 13:58:37.903790 5, 0xFFFF, sum = 0
6349 13:58:37.907267 6, 0xFFFF, sum = 0
6350 13:58:37.907351 7, 0xFFFF, sum = 0
6351 13:58:37.910460 8, 0xFFFF, sum = 0
6352 13:58:37.910532 9, 0xFFFF, sum = 0
6353 13:58:37.913989 10, 0xFFFF, sum = 0
6354 13:58:37.914065 11, 0xFFFF, sum = 0
6355 13:58:37.917091 12, 0xFFFF, sum = 0
6356 13:58:37.917161 13, 0x0, sum = 1
6357 13:58:37.920488 14, 0x0, sum = 2
6358 13:58:37.920558 15, 0x0, sum = 3
6359 13:58:37.923469 16, 0x0, sum = 4
6360 13:58:37.923538 best_step = 14
6361 13:58:37.923599
6362 13:58:37.923657 ==
6363 13:58:37.927311 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 13:58:37.930522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 13:58:37.933676 ==
6366 13:58:37.933774 RX Vref Scan: 1
6367 13:58:37.933837
6368 13:58:37.937433 RX Vref 0 -> 0, step: 1
6369 13:58:37.937497
6370 13:58:37.937554 RX Delay -359 -> 252, step: 8
6371 13:58:37.939988
6372 13:58:37.940054 Set Vref, RX VrefLevel [Byte0]: 56
6373 13:58:37.943822 [Byte1]: 49
6374 13:58:37.949057
6375 13:58:37.949128 Final RX Vref Byte 0 = 56 to rank0
6376 13:58:37.952355 Final RX Vref Byte 1 = 49 to rank0
6377 13:58:37.955836 Final RX Vref Byte 0 = 56 to rank1
6378 13:58:37.959134 Final RX Vref Byte 1 = 49 to rank1==
6379 13:58:37.962203 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 13:58:37.968752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 13:58:37.968831 ==
6382 13:58:37.968893 DQS Delay:
6383 13:58:37.972242 DQS0 = 44, DQS1 = 56
6384 13:58:37.972310 DQM Delay:
6385 13:58:37.972367 DQM0 = 10, DQM1 = 14
6386 13:58:37.975790 DQ Delay:
6387 13:58:37.978618 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6388 13:58:37.981902 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6389 13:58:37.981974 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6390 13:58:37.989135 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6391 13:58:37.989207
6392 13:58:37.989271
6393 13:58:37.995051 [DQSOSCAuto] RK0, (LSB)MR18= 0x998c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6394 13:58:37.998173 CH0 RK0: MR19=C0C, MR18=998C
6395 13:58:38.005111 CH0_RK0: MR19=0xC0C, MR18=0x998C, DQSOSC=390, MR23=63, INC=388, DEC=258
6396 13:58:38.005181 ==
6397 13:58:38.008296 Dram Type= 6, Freq= 0, CH_0, rank 1
6398 13:58:38.011714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 13:58:38.011786 ==
6400 13:58:38.014804 [Gating] SW mode calibration
6401 13:58:38.022067 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6402 13:58:38.028378 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6403 13:58:38.031618 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6404 13:58:38.034984 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6405 13:58:38.041302 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6406 13:58:38.044586 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6407 13:58:38.048108 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6408 13:58:38.054418 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6409 13:58:38.058292 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6410 13:58:38.061008 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6411 13:58:38.067750 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6412 13:58:38.070931 Total UI for P1: 0, mck2ui 16
6413 13:58:38.074181 best dqsien dly found for B0: ( 0, 14, 24)
6414 13:58:38.077353 Total UI for P1: 0, mck2ui 16
6415 13:58:38.081146 best dqsien dly found for B1: ( 0, 14, 24)
6416 13:58:38.084031 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6417 13:58:38.087681 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6418 13:58:38.087777
6419 13:58:38.090917 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6420 13:58:38.094530 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6421 13:58:38.097560 [Gating] SW calibration Done
6422 13:58:38.097658 ==
6423 13:58:38.101381 Dram Type= 6, Freq= 0, CH_0, rank 1
6424 13:58:38.104110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 13:58:38.104192 ==
6426 13:58:38.107485 RX Vref Scan: 0
6427 13:58:38.107598
6428 13:58:38.110790 RX Vref 0 -> 0, step: 1
6429 13:58:38.110888
6430 13:58:38.110984 RX Delay -410 -> 252, step: 16
6431 13:58:38.117626 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6432 13:58:38.121114 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6433 13:58:38.124030 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6434 13:58:38.130784 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6435 13:58:38.134326 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6436 13:58:38.137444 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6437 13:58:38.140498 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6438 13:58:38.147003 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6439 13:58:38.150119 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6440 13:58:38.154062 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6441 13:58:38.156877 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6442 13:58:38.163556 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6443 13:58:38.167111 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6444 13:58:38.170409 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6445 13:58:38.173522 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6446 13:58:38.179860 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6447 13:58:38.179986 ==
6448 13:58:38.183310 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 13:58:38.186706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 13:58:38.186788 ==
6451 13:58:38.186851 DQS Delay:
6452 13:58:38.189905 DQS0 = 35, DQS1 = 59
6453 13:58:38.190026 DQM Delay:
6454 13:58:38.193270 DQM0 = 7, DQM1 = 17
6455 13:58:38.193350 DQ Delay:
6456 13:58:38.196299 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6457 13:58:38.200083 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6458 13:58:38.203111 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6459 13:58:38.206399 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6460 13:58:38.206478
6461 13:58:38.206541
6462 13:58:38.206599 ==
6463 13:58:38.209802 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 13:58:38.213284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 13:58:38.213365 ==
6466 13:58:38.213429
6467 13:58:38.216340
6468 13:58:38.216449 TX Vref Scan disable
6469 13:58:38.219648 == TX Byte 0 ==
6470 13:58:38.223280 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6471 13:58:38.226330 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6472 13:58:38.229292 == TX Byte 1 ==
6473 13:58:38.232923 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6474 13:58:38.236117 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6475 13:58:38.236212 ==
6476 13:58:38.239358 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 13:58:38.242766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 13:58:38.246082 ==
6479 13:58:38.246179
6480 13:58:38.246275
6481 13:58:38.246351 TX Vref Scan disable
6482 13:58:38.249367 == TX Byte 0 ==
6483 13:58:38.252378 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6484 13:58:38.255646 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6485 13:58:38.259348 == TX Byte 1 ==
6486 13:58:38.262549 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6487 13:58:38.265621 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6488 13:58:38.265702
6489 13:58:38.268903 [DATLAT]
6490 13:58:38.268982 Freq=400, CH0 RK1
6491 13:58:38.269047
6492 13:58:38.272607 DATLAT Default: 0xe
6493 13:58:38.272688 0, 0xFFFF, sum = 0
6494 13:58:38.275608 1, 0xFFFF, sum = 0
6495 13:58:38.275690 2, 0xFFFF, sum = 0
6496 13:58:38.278744 3, 0xFFFF, sum = 0
6497 13:58:38.278826 4, 0xFFFF, sum = 0
6498 13:58:38.281918 5, 0xFFFF, sum = 0
6499 13:58:38.282000 6, 0xFFFF, sum = 0
6500 13:58:38.284953 7, 0xFFFF, sum = 0
6501 13:58:38.285034 8, 0xFFFF, sum = 0
6502 13:58:38.288947 9, 0xFFFF, sum = 0
6503 13:58:38.289029 10, 0xFFFF, sum = 0
6504 13:58:38.291945 11, 0xFFFF, sum = 0
6505 13:58:38.294964 12, 0xFFFF, sum = 0
6506 13:58:38.295045 13, 0x0, sum = 1
6507 13:58:38.295148 14, 0x0, sum = 2
6508 13:58:38.298293 15, 0x0, sum = 3
6509 13:58:38.298374 16, 0x0, sum = 4
6510 13:58:38.301504 best_step = 14
6511 13:58:38.301583
6512 13:58:38.301661 ==
6513 13:58:38.304930 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 13:58:38.308200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 13:58:38.308284 ==
6516 13:58:38.311583 RX Vref Scan: 0
6517 13:58:38.311680
6518 13:58:38.314844 RX Vref 0 -> 0, step: 1
6519 13:58:38.314941
6520 13:58:38.315036 RX Delay -359 -> 252, step: 8
6521 13:58:38.323255 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6522 13:58:38.327231 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6523 13:58:38.330612 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6524 13:58:38.333692 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6525 13:58:38.340015 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6526 13:58:38.343150 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6527 13:58:38.346780 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6528 13:58:38.350060 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6529 13:58:38.357246 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6530 13:58:38.360183 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6531 13:58:38.363363 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6532 13:58:38.369722 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6533 13:58:38.373450 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6534 13:58:38.376791 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6535 13:58:38.379583 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6536 13:58:38.386029 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6537 13:58:38.386105 ==
6538 13:58:38.389614 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 13:58:38.392551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 13:58:38.392623 ==
6541 13:58:38.392685 DQS Delay:
6542 13:58:38.395981 DQS0 = 40, DQS1 = 60
6543 13:58:38.396054 DQM Delay:
6544 13:58:38.399170 DQM0 = 6, DQM1 = 14
6545 13:58:38.399239 DQ Delay:
6546 13:58:38.402955 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =4
6547 13:58:38.406070 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6548 13:58:38.409130 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6549 13:58:38.412623 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6550 13:58:38.412745
6551 13:58:38.412842
6552 13:58:38.419107 [DQSOSCAuto] RK1, (LSB)MR18= 0x948e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6553 13:58:38.422519 CH0 RK1: MR19=C0C, MR18=948E
6554 13:58:38.429301 CH0_RK1: MR19=0xC0C, MR18=0x948E, DQSOSC=391, MR23=63, INC=386, DEC=257
6555 13:58:38.432529 [RxdqsGatingPostProcess] freq 400
6556 13:58:38.439165 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6557 13:58:38.441879 best DQS0 dly(2T, 0.5T) = (0, 10)
6558 13:58:38.445640 best DQS1 dly(2T, 0.5T) = (0, 10)
6559 13:58:38.448572 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6560 13:58:38.451731 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6561 13:58:38.451813 best DQS0 dly(2T, 0.5T) = (0, 10)
6562 13:58:38.455063 best DQS1 dly(2T, 0.5T) = (0, 10)
6563 13:58:38.458568 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6564 13:58:38.461954 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6565 13:58:38.465472 Pre-setting of DQS Precalculation
6566 13:58:38.471639 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6567 13:58:38.471721 ==
6568 13:58:38.475123 Dram Type= 6, Freq= 0, CH_1, rank 0
6569 13:58:38.478066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 13:58:38.478147 ==
6571 13:58:38.484709 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6572 13:58:38.491359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6573 13:58:38.494517 [CA 0] Center 36 (8~64) winsize 57
6574 13:58:38.498057 [CA 1] Center 36 (8~64) winsize 57
6575 13:58:38.501466 [CA 2] Center 36 (8~64) winsize 57
6576 13:58:38.501563 [CA 3] Center 36 (8~64) winsize 57
6577 13:58:38.504960 [CA 4] Center 36 (8~64) winsize 57
6578 13:58:38.508087 [CA 5] Center 36 (8~64) winsize 57
6579 13:58:38.508186
6580 13:58:38.514545 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6581 13:58:38.514662
6582 13:58:38.518091 [CATrainingPosCal] consider 1 rank data
6583 13:58:38.521031 u2DelayCellTimex100 = 270/100 ps
6584 13:58:38.524532 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6585 13:58:38.527892 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6586 13:58:38.531375 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6587 13:58:38.534600 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6588 13:58:38.537677 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6589 13:58:38.541602 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 13:58:38.541700
6591 13:58:38.543954 CA PerBit enable=1, Macro0, CA PI delay=36
6592 13:58:38.544067
6593 13:58:38.547822 [CBTSetCACLKResult] CA Dly = 36
6594 13:58:38.551149 CS Dly: 1 (0~32)
6595 13:58:38.551248 ==
6596 13:58:38.554468 Dram Type= 6, Freq= 0, CH_1, rank 1
6597 13:58:38.557392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 13:58:38.557473 ==
6599 13:58:38.563795 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6600 13:58:38.570858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6601 13:58:38.573882 [CA 0] Center 36 (8~64) winsize 57
6602 13:58:38.573980 [CA 1] Center 36 (8~64) winsize 57
6603 13:58:38.577159 [CA 2] Center 36 (8~64) winsize 57
6604 13:58:38.580275 [CA 3] Center 36 (8~64) winsize 57
6605 13:58:38.583657 [CA 4] Center 36 (8~64) winsize 57
6606 13:58:38.586980 [CA 5] Center 36 (8~64) winsize 57
6607 13:58:38.587078
6608 13:58:38.590964 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6609 13:58:38.591046
6610 13:58:38.596597 [CATrainingPosCal] consider 2 rank data
6611 13:58:38.596678 u2DelayCellTimex100 = 270/100 ps
6612 13:58:38.603608 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 13:58:38.606997 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 13:58:38.610256 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 13:58:38.613226 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 13:58:38.616524 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 13:58:38.620121 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 13:58:38.620211
6619 13:58:38.623046 CA PerBit enable=1, Macro0, CA PI delay=36
6620 13:58:38.623121
6621 13:58:38.626763 [CBTSetCACLKResult] CA Dly = 36
6622 13:58:38.630149 CS Dly: 1 (0~32)
6623 13:58:38.630220
6624 13:58:38.633498 ----->DramcWriteLeveling(PI) begin...
6625 13:58:38.633570 ==
6626 13:58:38.636803 Dram Type= 6, Freq= 0, CH_1, rank 0
6627 13:58:38.640068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 13:58:38.640138 ==
6629 13:58:38.643562 Write leveling (Byte 0): 40 => 8
6630 13:58:38.646398 Write leveling (Byte 1): 40 => 8
6631 13:58:38.649581 DramcWriteLeveling(PI) end<-----
6632 13:58:38.649649
6633 13:58:38.649712 ==
6634 13:58:38.652863 Dram Type= 6, Freq= 0, CH_1, rank 0
6635 13:58:38.656384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 13:58:38.656457 ==
6637 13:58:38.659431 [Gating] SW mode calibration
6638 13:58:38.666366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6639 13:58:38.672786 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6640 13:58:38.676332 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6641 13:58:38.679182 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6642 13:58:38.685809 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6643 13:58:38.689012 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6644 13:58:38.692698 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6645 13:58:38.699246 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6646 13:58:38.702359 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6647 13:58:38.705717 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6648 13:58:38.712473 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6649 13:58:38.715214 Total UI for P1: 0, mck2ui 16
6650 13:58:38.718713 best dqsien dly found for B0: ( 0, 14, 24)
6651 13:58:38.722347 Total UI for P1: 0, mck2ui 16
6652 13:58:38.725398 best dqsien dly found for B1: ( 0, 14, 24)
6653 13:58:38.728465 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6654 13:58:38.732157 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6655 13:58:38.732240
6656 13:58:38.735225 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6657 13:58:38.739171 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6658 13:58:38.741722 [Gating] SW calibration Done
6659 13:58:38.741806 ==
6660 13:58:38.745396 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 13:58:38.748932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 13:58:38.749016 ==
6663 13:58:38.752133 RX Vref Scan: 0
6664 13:58:38.752228
6665 13:58:38.755170 RX Vref 0 -> 0, step: 1
6666 13:58:38.755238
6667 13:58:38.759201 RX Delay -410 -> 252, step: 16
6668 13:58:38.761552 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6669 13:58:38.765054 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6670 13:58:38.768285 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6671 13:58:38.775198 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6672 13:58:38.777827 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6673 13:58:38.781345 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6674 13:58:38.786457 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6675 13:58:38.791103 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6676 13:58:38.794557 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6677 13:58:38.797958 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6678 13:58:38.801020 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6679 13:58:38.807385 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6680 13:58:38.811330 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6681 13:58:38.814210 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6682 13:58:38.821387 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6683 13:58:38.824207 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6684 13:58:38.824294 ==
6685 13:58:38.827891 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 13:58:38.831340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 13:58:38.831424 ==
6688 13:58:38.834051 DQS Delay:
6689 13:58:38.834135 DQS0 = 35, DQS1 = 51
6690 13:58:38.834220 DQM Delay:
6691 13:58:38.837229 DQM0 = 6, DQM1 = 13
6692 13:58:38.837313 DQ Delay:
6693 13:58:38.840706 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6694 13:58:38.843920 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6695 13:58:38.847587 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6696 13:58:38.850474 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6697 13:58:38.850557
6698 13:58:38.850642
6699 13:58:38.850722 ==
6700 13:58:38.853945 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 13:58:38.860512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 13:58:38.860596 ==
6703 13:58:38.860681
6704 13:58:38.860761
6705 13:58:38.860839 TX Vref Scan disable
6706 13:58:38.863781 == TX Byte 0 ==
6707 13:58:38.867110 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6708 13:58:38.870235 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6709 13:58:38.874002 == TX Byte 1 ==
6710 13:58:38.876607 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6711 13:58:38.880125 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6712 13:58:38.880208 ==
6713 13:58:38.883370 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 13:58:38.889721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 13:58:38.889805 ==
6716 13:58:38.889890
6717 13:58:38.889969
6718 13:58:38.890047 TX Vref Scan disable
6719 13:58:38.893584 == TX Byte 0 ==
6720 13:58:38.896672 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6721 13:58:38.899728 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6722 13:58:38.903540 == TX Byte 1 ==
6723 13:58:38.906267 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6724 13:58:38.910344 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6725 13:58:38.912642
6726 13:58:38.912724 [DATLAT]
6727 13:58:38.912809 Freq=400, CH1 RK0
6728 13:58:38.912907
6729 13:58:38.915957 DATLAT Default: 0xf
6730 13:58:38.916040 0, 0xFFFF, sum = 0
6731 13:58:38.919640 1, 0xFFFF, sum = 0
6732 13:58:38.919743 2, 0xFFFF, sum = 0
6733 13:58:38.922698 3, 0xFFFF, sum = 0
6734 13:58:38.926301 4, 0xFFFF, sum = 0
6735 13:58:38.926383 5, 0xFFFF, sum = 0
6736 13:58:38.929429 6, 0xFFFF, sum = 0
6737 13:58:38.929510 7, 0xFFFF, sum = 0
6738 13:58:38.933156 8, 0xFFFF, sum = 0
6739 13:58:38.933239 9, 0xFFFF, sum = 0
6740 13:58:38.936122 10, 0xFFFF, sum = 0
6741 13:58:38.936204 11, 0xFFFF, sum = 0
6742 13:58:38.939289 12, 0xFFFF, sum = 0
6743 13:58:38.939370 13, 0x0, sum = 1
6744 13:58:38.943009 14, 0x0, sum = 2
6745 13:58:38.943091 15, 0x0, sum = 3
6746 13:58:38.945824 16, 0x0, sum = 4
6747 13:58:38.945906 best_step = 14
6748 13:58:38.945970
6749 13:58:38.946030 ==
6750 13:58:38.949325 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 13:58:38.952298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 13:58:38.955659 ==
6753 13:58:38.955738 RX Vref Scan: 1
6754 13:58:38.955802
6755 13:58:38.958954 RX Vref 0 -> 0, step: 1
6756 13:58:38.959034
6757 13:58:38.962047 RX Delay -343 -> 252, step: 8
6758 13:58:38.962130
6759 13:58:38.967112 Set Vref, RX VrefLevel [Byte0]: 50
6760 13:58:38.968836 [Byte1]: 54
6761 13:58:38.968929
6762 13:58:38.972212 Final RX Vref Byte 0 = 50 to rank0
6763 13:58:38.975631 Final RX Vref Byte 1 = 54 to rank0
6764 13:58:38.978838 Final RX Vref Byte 0 = 50 to rank1
6765 13:58:38.982306 Final RX Vref Byte 1 = 54 to rank1==
6766 13:58:38.985146 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 13:58:38.988919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 13:58:38.991604 ==
6769 13:58:38.991687 DQS Delay:
6770 13:58:38.991787 DQS0 = 44, DQS1 = 52
6771 13:58:38.995640 DQM Delay:
6772 13:58:38.995723 DQM0 = 12, DQM1 = 10
6773 13:58:38.998229 DQ Delay:
6774 13:58:38.998312 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6775 13:58:39.001931 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6776 13:58:39.004918 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6777 13:58:39.008196 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6778 13:58:39.008279
6779 13:58:39.008363
6780 13:58:39.018018 [DQSOSCAuto] RK0, (LSB)MR18= 0x6990, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6781 13:58:39.021947 CH1 RK0: MR19=C0C, MR18=6990
6782 13:58:39.028507 CH1_RK0: MR19=0xC0C, MR18=0x6990, DQSOSC=391, MR23=63, INC=386, DEC=257
6783 13:58:39.028590 ==
6784 13:58:39.031520 Dram Type= 6, Freq= 0, CH_1, rank 1
6785 13:58:39.034783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 13:58:39.034866 ==
6787 13:58:39.037962 [Gating] SW mode calibration
6788 13:58:39.044737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6789 13:58:39.051402 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6790 13:58:39.054488 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6791 13:58:39.057816 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6792 13:58:39.061085 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6793 13:58:39.068053 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6794 13:58:39.071188 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6795 13:58:39.077811 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6796 13:58:39.080589 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6797 13:58:39.083866 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6798 13:58:39.090671 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6799 13:58:39.090755 Total UI for P1: 0, mck2ui 16
6800 13:58:39.094141 best dqsien dly found for B0: ( 0, 14, 24)
6801 13:58:39.097043 Total UI for P1: 0, mck2ui 16
6802 13:58:39.100293 best dqsien dly found for B1: ( 0, 14, 24)
6803 13:58:39.106869 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6804 13:58:39.110438 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6805 13:58:39.110522
6806 13:58:39.114135 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6807 13:58:39.116778 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6808 13:58:39.120511 [Gating] SW calibration Done
6809 13:58:39.120594 ==
6810 13:58:39.123471 Dram Type= 6, Freq= 0, CH_1, rank 1
6811 13:58:39.126933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 13:58:39.127068 ==
6813 13:58:39.129900 RX Vref Scan: 0
6814 13:58:39.129983
6815 13:58:39.130098 RX Vref 0 -> 0, step: 1
6816 13:58:39.130179
6817 13:58:39.133783 RX Delay -410 -> 252, step: 16
6818 13:58:39.140088 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6819 13:58:39.143256 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6820 13:58:39.146783 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6821 13:58:39.149844 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6822 13:58:39.156687 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6823 13:58:39.159873 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6824 13:58:39.163204 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6825 13:58:39.166500 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6826 13:58:39.173040 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6827 13:58:39.176547 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6828 13:58:39.179248 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6829 13:58:39.182670 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6830 13:58:39.189566 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6831 13:58:39.192829 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6832 13:58:39.196127 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6833 13:58:39.203023 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6834 13:58:39.203106 ==
6835 13:58:39.206329 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 13:58:39.209336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 13:58:39.209419 ==
6838 13:58:39.209505 DQS Delay:
6839 13:58:39.212770 DQS0 = 43, DQS1 = 51
6840 13:58:39.212850 DQM Delay:
6841 13:58:39.216242 DQM0 = 10, DQM1 = 14
6842 13:58:39.216317 DQ Delay:
6843 13:58:39.219068 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6844 13:58:39.222408 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6845 13:58:39.225773 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6846 13:58:39.229485 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6847 13:58:39.229562
6848 13:58:39.229624
6849 13:58:39.229681 ==
6850 13:58:39.232021 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 13:58:39.235834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 13:58:39.235952 ==
6853 13:58:39.236016
6854 13:58:39.236075
6855 13:58:39.239129 TX Vref Scan disable
6856 13:58:39.242117 == TX Byte 0 ==
6857 13:58:39.245493 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6858 13:58:39.248773 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6859 13:58:39.248858 == TX Byte 1 ==
6860 13:58:39.255619 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6861 13:58:39.258736 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6862 13:58:39.258838 ==
6863 13:58:39.262259 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 13:58:39.265473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 13:58:39.265558 ==
6866 13:58:39.265642
6867 13:58:39.265722
6868 13:58:39.268855 TX Vref Scan disable
6869 13:58:39.272297 == TX Byte 0 ==
6870 13:58:39.275181 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6871 13:58:39.278619 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6872 13:58:39.282119 == TX Byte 1 ==
6873 13:58:39.285175 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6874 13:58:39.289233 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6875 13:58:39.289316
6876 13:58:39.289401 [DATLAT]
6877 13:58:39.291767 Freq=400, CH1 RK1
6878 13:58:39.291850
6879 13:58:39.291980 DATLAT Default: 0xe
6880 13:58:39.295533 0, 0xFFFF, sum = 0
6881 13:58:39.298338 1, 0xFFFF, sum = 0
6882 13:58:39.298423 2, 0xFFFF, sum = 0
6883 13:58:39.302146 3, 0xFFFF, sum = 0
6884 13:58:39.302230 4, 0xFFFF, sum = 0
6885 13:58:39.304833 5, 0xFFFF, sum = 0
6886 13:58:39.304918 6, 0xFFFF, sum = 0
6887 13:58:39.308530 7, 0xFFFF, sum = 0
6888 13:58:39.308615 8, 0xFFFF, sum = 0
6889 13:58:39.311289 9, 0xFFFF, sum = 0
6890 13:58:39.311399 10, 0xFFFF, sum = 0
6891 13:58:39.314746 11, 0xFFFF, sum = 0
6892 13:58:39.314832 12, 0xFFFF, sum = 0
6893 13:58:39.318495 13, 0x0, sum = 1
6894 13:58:39.318580 14, 0x0, sum = 2
6895 13:58:39.321477 15, 0x0, sum = 3
6896 13:58:39.321595 16, 0x0, sum = 4
6897 13:58:39.324705 best_step = 14
6898 13:58:39.324821
6899 13:58:39.324903 ==
6900 13:58:39.328112 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 13:58:39.331517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 13:58:39.331601 ==
6903 13:58:39.334486 RX Vref Scan: 0
6904 13:58:39.334569
6905 13:58:39.334654 RX Vref 0 -> 0, step: 1
6906 13:58:39.334735
6907 13:58:39.338182 RX Delay -343 -> 252, step: 8
6908 13:58:39.345810 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6909 13:58:39.348773 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6910 13:58:39.352105 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6911 13:58:39.358612 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6912 13:58:39.362099 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6913 13:58:39.365672 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6914 13:58:39.368828 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6915 13:58:39.375257 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6916 13:58:39.378300 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6917 13:58:39.382315 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6918 13:58:39.385052 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6919 13:58:39.391708 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6920 13:58:39.395042 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6921 13:58:39.398165 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6922 13:58:39.404606 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6923 13:58:39.408031 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6924 13:58:39.408114 ==
6925 13:58:39.411853 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 13:58:39.414400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 13:58:39.414500 ==
6928 13:58:39.418364 DQS Delay:
6929 13:58:39.418447 DQS0 = 44, DQS1 = 52
6930 13:58:39.418531 DQM Delay:
6931 13:58:39.421306 DQM0 = 9, DQM1 = 10
6932 13:58:39.421390 DQ Delay:
6933 13:58:39.425217 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6934 13:58:39.428241 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6935 13:58:39.431218 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6936 13:58:39.434433 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6937 13:58:39.434516
6938 13:58:39.434600
6939 13:58:39.441019 [DQSOSCAuto] RK1, (LSB)MR18= 0x81b9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 393 ps
6940 13:58:39.444402 CH1 RK1: MR19=C0C, MR18=81B9
6941 13:58:39.450932 CH1_RK1: MR19=0xC0C, MR18=0x81B9, DQSOSC=386, MR23=63, INC=396, DEC=264
6942 13:58:39.454773 [RxdqsGatingPostProcess] freq 400
6943 13:58:39.461255 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6944 13:58:39.464391 best DQS0 dly(2T, 0.5T) = (0, 10)
6945 13:58:39.467463 best DQS1 dly(2T, 0.5T) = (0, 10)
6946 13:58:39.471134 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6947 13:58:39.474212 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6948 13:58:39.474312 best DQS0 dly(2T, 0.5T) = (0, 10)
6949 13:58:39.477429 best DQS1 dly(2T, 0.5T) = (0, 10)
6950 13:58:39.481499 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6951 13:58:39.484109 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6952 13:58:39.487672 Pre-setting of DQS Precalculation
6953 13:58:39.494524 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6954 13:58:39.501026 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6955 13:58:39.507692 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6956 13:58:39.507791
6957 13:58:39.507892
6958 13:58:39.510869 [Calibration Summary] 800 Mbps
6959 13:58:39.510965 CH 0, Rank 0
6960 13:58:39.514479 SW Impedance : PASS
6961 13:58:39.517392 DUTY Scan : NO K
6962 13:58:39.517491 ZQ Calibration : PASS
6963 13:58:39.520711 Jitter Meter : NO K
6964 13:58:39.524277 CBT Training : PASS
6965 13:58:39.524356 Write leveling : PASS
6966 13:58:39.527409 RX DQS gating : PASS
6967 13:58:39.530536 RX DQ/DQS(RDDQC) : PASS
6968 13:58:39.530633 TX DQ/DQS : PASS
6969 13:58:39.533994 RX DATLAT : PASS
6970 13:58:39.537362 RX DQ/DQS(Engine): PASS
6971 13:58:39.537433 TX OE : NO K
6972 13:58:39.540160 All Pass.
6973 13:58:39.540246
6974 13:58:39.540311 CH 0, Rank 1
6975 13:58:39.543790 SW Impedance : PASS
6976 13:58:39.543893 DUTY Scan : NO K
6977 13:58:39.546909 ZQ Calibration : PASS
6978 13:58:39.550038 Jitter Meter : NO K
6979 13:58:39.550150 CBT Training : PASS
6980 13:58:39.553741 Write leveling : NO K
6981 13:58:39.557118 RX DQS gating : PASS
6982 13:58:39.557192 RX DQ/DQS(RDDQC) : PASS
6983 13:58:39.560124 TX DQ/DQS : PASS
6984 13:58:39.560197 RX DATLAT : PASS
6985 13:58:39.563612 RX DQ/DQS(Engine): PASS
6986 13:58:39.566682 TX OE : NO K
6987 13:58:39.566786 All Pass.
6988 13:58:39.566880
6989 13:58:39.570530 CH 1, Rank 0
6990 13:58:39.570627 SW Impedance : PASS
6991 13:58:39.573157 DUTY Scan : NO K
6992 13:58:39.573233 ZQ Calibration : PASS
6993 13:58:39.576799 Jitter Meter : NO K
6994 13:58:39.579914 CBT Training : PASS
6995 13:58:39.579993 Write leveling : PASS
6996 13:58:39.583206 RX DQS gating : PASS
6997 13:58:39.586473 RX DQ/DQS(RDDQC) : PASS
6998 13:58:39.586574 TX DQ/DQS : PASS
6999 13:58:39.589908 RX DATLAT : PASS
7000 13:58:39.593494 RX DQ/DQS(Engine): PASS
7001 13:58:39.593612 TX OE : NO K
7002 13:58:39.596807 All Pass.
7003 13:58:39.596875
7004 13:58:39.596936 CH 1, Rank 1
7005 13:58:39.600080 SW Impedance : PASS
7006 13:58:39.600165 DUTY Scan : NO K
7007 13:58:39.602820 ZQ Calibration : PASS
7008 13:58:39.606735 Jitter Meter : NO K
7009 13:58:39.606841 CBT Training : PASS
7010 13:58:39.609994 Write leveling : NO K
7011 13:58:39.613085 RX DQS gating : PASS
7012 13:58:39.613153 RX DQ/DQS(RDDQC) : PASS
7013 13:58:39.616503 TX DQ/DQS : PASS
7014 13:58:39.619345 RX DATLAT : PASS
7015 13:58:39.619441 RX DQ/DQS(Engine): PASS
7016 13:58:39.622912 TX OE : NO K
7017 13:58:39.623011 All Pass.
7018 13:58:39.623079
7019 13:58:39.626904 DramC Write-DBI off
7020 13:58:39.629489 PER_BANK_REFRESH: Hybrid Mode
7021 13:58:39.629565 TX_TRACKING: ON
7022 13:58:39.639455 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7023 13:58:39.642694 [FAST_K] Save calibration result to emmc
7024 13:58:39.645875 dramc_set_vcore_voltage set vcore to 725000
7025 13:58:39.650022 Read voltage for 1600, 0
7026 13:58:39.650089 Vio18 = 0
7027 13:58:39.650150 Vcore = 725000
7028 13:58:39.652636 Vdram = 0
7029 13:58:39.652707 Vddq = 0
7030 13:58:39.652767 Vmddr = 0
7031 13:58:39.659563 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7032 13:58:39.662485 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7033 13:58:39.665758 MEM_TYPE=3, freq_sel=13
7034 13:58:39.669059 sv_algorithm_assistance_LP4_3733
7035 13:58:39.672549 ============ PULL DRAM RESETB DOWN ============
7036 13:58:39.675900 ========== PULL DRAM RESETB DOWN end =========
7037 13:58:39.682664 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7038 13:58:39.686403 ===================================
7039 13:58:39.688946 LPDDR4 DRAM CONFIGURATION
7040 13:58:39.692176 ===================================
7041 13:58:39.692250 EX_ROW_EN[0] = 0x0
7042 13:58:39.695391 EX_ROW_EN[1] = 0x0
7043 13:58:39.695503 LP4Y_EN = 0x0
7044 13:58:39.698764 WORK_FSP = 0x1
7045 13:58:39.698875 WL = 0x5
7046 13:58:39.702190 RL = 0x5
7047 13:58:39.702298 BL = 0x2
7048 13:58:39.705984 RPST = 0x0
7049 13:58:39.706082 RD_PRE = 0x0
7050 13:58:39.708782 WR_PRE = 0x1
7051 13:58:39.708869 WR_PST = 0x1
7052 13:58:39.711640 DBI_WR = 0x0
7053 13:58:39.715134 DBI_RD = 0x0
7054 13:58:39.715216 OTF = 0x1
7055 13:58:39.718225 ===================================
7056 13:58:39.721892 ===================================
7057 13:58:39.722000 ANA top config
7058 13:58:39.724900 ===================================
7059 13:58:39.728529 DLL_ASYNC_EN = 0
7060 13:58:39.731597 ALL_SLAVE_EN = 0
7061 13:58:39.734993 NEW_RANK_MODE = 1
7062 13:58:39.738374 DLL_IDLE_MODE = 1
7063 13:58:39.738473 LP45_APHY_COMB_EN = 1
7064 13:58:39.741725 TX_ODT_DIS = 0
7065 13:58:39.744733 NEW_8X_MODE = 1
7066 13:58:39.748116 ===================================
7067 13:58:39.751548 ===================================
7068 13:58:39.754831 data_rate = 3200
7069 13:58:39.757957 CKR = 1
7070 13:58:39.758051 DQ_P2S_RATIO = 8
7071 13:58:39.761808 ===================================
7072 13:58:39.764541 CA_P2S_RATIO = 8
7073 13:58:39.768038 DQ_CA_OPEN = 0
7074 13:58:39.771600 DQ_SEMI_OPEN = 0
7075 13:58:39.775050 CA_SEMI_OPEN = 0
7076 13:58:39.778184 CA_FULL_RATE = 0
7077 13:58:39.778284 DQ_CKDIV4_EN = 0
7078 13:58:39.781304 CA_CKDIV4_EN = 0
7079 13:58:39.784466 CA_PREDIV_EN = 0
7080 13:58:39.788549 PH8_DLY = 12
7081 13:58:39.791327 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7082 13:58:39.794731 DQ_AAMCK_DIV = 4
7083 13:58:39.797598 CA_AAMCK_DIV = 4
7084 13:58:39.797694 CA_ADMCK_DIV = 4
7085 13:58:39.800969 DQ_TRACK_CA_EN = 0
7086 13:58:39.804265 CA_PICK = 1600
7087 13:58:39.807661 CA_MCKIO = 1600
7088 13:58:39.810851 MCKIO_SEMI = 0
7089 13:58:39.814423 PLL_FREQ = 3068
7090 13:58:39.817454 DQ_UI_PI_RATIO = 32
7091 13:58:39.817538 CA_UI_PI_RATIO = 0
7092 13:58:39.820817 ===================================
7093 13:58:39.824015 ===================================
7094 13:58:39.827354 memory_type:LPDDR4
7095 13:58:39.830885 GP_NUM : 10
7096 13:58:39.830990 SRAM_EN : 1
7097 13:58:39.833946 MD32_EN : 0
7098 13:58:39.837349 ===================================
7099 13:58:39.840847 [ANA_INIT] >>>>>>>>>>>>>>
7100 13:58:39.844992 <<<<<< [CONFIGURE PHASE]: ANA_TX
7101 13:58:39.847181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7102 13:58:39.851052 ===================================
7103 13:58:39.851124 data_rate = 3200,PCW = 0X7600
7104 13:58:39.853822 ===================================
7105 13:58:39.860686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7106 13:58:39.863807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7107 13:58:39.870392 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7108 13:58:39.873578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7109 13:58:39.877463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7110 13:58:39.880317 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7111 13:58:39.883853 [ANA_INIT] flow start
7112 13:58:39.886899 [ANA_INIT] PLL >>>>>>>>
7113 13:58:39.886994 [ANA_INIT] PLL <<<<<<<<
7114 13:58:39.890808 [ANA_INIT] MIDPI >>>>>>>>
7115 13:58:39.893633 [ANA_INIT] MIDPI <<<<<<<<
7116 13:58:39.893701 [ANA_INIT] DLL >>>>>>>>
7117 13:58:39.897006 [ANA_INIT] DLL <<<<<<<<
7118 13:58:39.901157 [ANA_INIT] flow end
7119 13:58:39.903547 ============ LP4 DIFF to SE enter ============
7120 13:58:39.906967 ============ LP4 DIFF to SE exit ============
7121 13:58:39.909801 [ANA_INIT] <<<<<<<<<<<<<
7122 13:58:39.913655 [Flow] Enable top DCM control >>>>>
7123 13:58:39.916522 [Flow] Enable top DCM control <<<<<
7124 13:58:39.919818 Enable DLL master slave shuffle
7125 13:58:39.923172 ==============================================================
7126 13:58:39.926710 Gating Mode config
7127 13:58:39.933223 ==============================================================
7128 13:58:39.933301 Config description:
7129 13:58:39.944044 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7130 13:58:39.949413 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7131 13:58:39.956258 SELPH_MODE 0: By rank 1: By Phase
7132 13:58:39.959663 ==============================================================
7133 13:58:39.963020 GAT_TRACK_EN = 1
7134 13:58:39.966583 RX_GATING_MODE = 2
7135 13:58:39.969586 RX_GATING_TRACK_MODE = 2
7136 13:58:39.972854 SELPH_MODE = 1
7137 13:58:39.976957 PICG_EARLY_EN = 1
7138 13:58:39.979538 VALID_LAT_VALUE = 1
7139 13:58:39.982850 ==============================================================
7140 13:58:39.989168 Enter into Gating configuration >>>>
7141 13:58:39.992816 Exit from Gating configuration <<<<
7142 13:58:39.992889 Enter into DVFS_PRE_config >>>>>
7143 13:58:40.005875 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7144 13:58:40.009028 Exit from DVFS_PRE_config <<<<<
7145 13:58:40.012388 Enter into PICG configuration >>>>
7146 13:58:40.015401 Exit from PICG configuration <<<<
7147 13:58:40.015475 [RX_INPUT] configuration >>>>>
7148 13:58:40.018827 [RX_INPUT] configuration <<<<<
7149 13:58:40.026163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7150 13:58:40.032184 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7151 13:58:40.035204 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7152 13:58:40.041987 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7153 13:58:40.048267 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7154 13:58:40.054939 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7155 13:58:40.058444 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7156 13:58:40.061777 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7157 13:58:40.068252 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7158 13:58:40.072248 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7159 13:58:40.074768 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7160 13:58:40.081148 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7161 13:58:40.085282 ===================================
7162 13:58:40.085386 LPDDR4 DRAM CONFIGURATION
7163 13:58:40.088052 ===================================
7164 13:58:40.091117 EX_ROW_EN[0] = 0x0
7165 13:58:40.091189 EX_ROW_EN[1] = 0x0
7166 13:58:40.095106 LP4Y_EN = 0x0
7167 13:58:40.097884 WORK_FSP = 0x1
7168 13:58:40.097984 WL = 0x5
7169 13:58:40.101220 RL = 0x5
7170 13:58:40.101290 BL = 0x2
7171 13:58:40.104427 RPST = 0x0
7172 13:58:40.104523 RD_PRE = 0x0
7173 13:58:40.108125 WR_PRE = 0x1
7174 13:58:40.108208 WR_PST = 0x1
7175 13:58:40.111298 DBI_WR = 0x0
7176 13:58:40.111403 DBI_RD = 0x0
7177 13:58:40.114636 OTF = 0x1
7178 13:58:40.117851 ===================================
7179 13:58:40.120850 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7180 13:58:40.124590 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7181 13:58:40.130703 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7182 13:58:40.134048 ===================================
7183 13:58:40.134152 LPDDR4 DRAM CONFIGURATION
7184 13:58:40.137517 ===================================
7185 13:58:40.141251 EX_ROW_EN[0] = 0x10
7186 13:58:40.144519 EX_ROW_EN[1] = 0x0
7187 13:58:40.144592 LP4Y_EN = 0x0
7188 13:58:40.147427 WORK_FSP = 0x1
7189 13:58:40.147494 WL = 0x5
7190 13:58:40.150857 RL = 0x5
7191 13:58:40.150933 BL = 0x2
7192 13:58:40.154154 RPST = 0x0
7193 13:58:40.154257 RD_PRE = 0x0
7194 13:58:40.157558 WR_PRE = 0x1
7195 13:58:40.157631 WR_PST = 0x1
7196 13:58:40.160684 DBI_WR = 0x0
7197 13:58:40.160770 DBI_RD = 0x0
7198 13:58:40.164324 OTF = 0x1
7199 13:58:40.167586 ===================================
7200 13:58:40.174093 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7201 13:58:40.174193 ==
7202 13:58:40.177502 Dram Type= 6, Freq= 0, CH_0, rank 0
7203 13:58:40.180364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7204 13:58:40.180440 ==
7205 13:58:40.183585 [Duty_Offset_Calibration]
7206 13:58:40.183682 B0:2 B1:0 CA:4
7207 13:58:40.183771
7208 13:58:40.187050 [DutyScan_Calibration_Flow] k_type=0
7209 13:58:40.197314
7210 13:58:40.197418 ==CLK 0==
7211 13:58:40.200345 Final CLK duty delay cell = -4
7212 13:58:40.203634 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7213 13:58:40.206695 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7214 13:58:40.209823 [-4] AVG Duty = 4937%(X100)
7215 13:58:40.209927
7216 13:58:40.213282 CH0 CLK Duty spec in!! Max-Min= 187%
7217 13:58:40.216684 [DutyScan_Calibration_Flow] ====Done====
7218 13:58:40.216763
7219 13:58:40.220004 [DutyScan_Calibration_Flow] k_type=1
7220 13:58:40.237310
7221 13:58:40.237413 ==DQS 0 ==
7222 13:58:40.240354 Final DQS duty delay cell = 0
7223 13:58:40.243506 [0] MAX Duty = 5218%(X100), DQS PI = 22
7224 13:58:40.246773 [0] MIN Duty = 5093%(X100), DQS PI = 14
7225 13:58:40.250239 [0] AVG Duty = 5155%(X100)
7226 13:58:40.250314
7227 13:58:40.250376 ==DQS 1 ==
7228 13:58:40.253637 Final DQS duty delay cell = 0
7229 13:58:40.256717 [0] MAX Duty = 5156%(X100), DQS PI = 2
7230 13:58:40.259917 [0] MIN Duty = 4969%(X100), DQS PI = 12
7231 13:58:40.263680 [0] AVG Duty = 5062%(X100)
7232 13:58:40.263759
7233 13:58:40.266808 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7234 13:58:40.266878
7235 13:58:40.270108 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7236 13:58:40.273523 [DutyScan_Calibration_Flow] ====Done====
7237 13:58:40.273597
7238 13:58:40.276844 [DutyScan_Calibration_Flow] k_type=3
7239 13:58:40.294405
7240 13:58:40.294509 ==DQM 0 ==
7241 13:58:40.297780 Final DQM duty delay cell = 0
7242 13:58:40.301040 [0] MAX Duty = 5124%(X100), DQS PI = 20
7243 13:58:40.303939 [0] MIN Duty = 4875%(X100), DQS PI = 56
7244 13:58:40.307380 [0] AVG Duty = 4999%(X100)
7245 13:58:40.307448
7246 13:58:40.307508 ==DQM 1 ==
7247 13:58:40.310355 Final DQM duty delay cell = 0
7248 13:58:40.313865 [0] MAX Duty = 5000%(X100), DQS PI = 4
7249 13:58:40.317546 [0] MIN Duty = 4844%(X100), DQS PI = 16
7250 13:58:40.320536 [0] AVG Duty = 4922%(X100)
7251 13:58:40.320610
7252 13:58:40.324527 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7253 13:58:40.324601
7254 13:58:40.327512 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7255 13:58:40.330226 [DutyScan_Calibration_Flow] ====Done====
7256 13:58:40.330297
7257 13:58:40.333438 [DutyScan_Calibration_Flow] k_type=2
7258 13:58:40.351385
7259 13:58:40.351487 ==DQ 0 ==
7260 13:58:40.354609 Final DQ duty delay cell = 0
7261 13:58:40.358072 [0] MAX Duty = 5124%(X100), DQS PI = 20
7262 13:58:40.361048 [0] MIN Duty = 4969%(X100), DQS PI = 10
7263 13:58:40.364572 [0] AVG Duty = 5046%(X100)
7264 13:58:40.364681
7265 13:58:40.364753 ==DQ 1 ==
7266 13:58:40.367613 Final DQ duty delay cell = 0
7267 13:58:40.371457 [0] MAX Duty = 5187%(X100), DQS PI = 2
7268 13:58:40.374390 [0] MIN Duty = 4938%(X100), DQS PI = 12
7269 13:58:40.374490 [0] AVG Duty = 5062%(X100)
7270 13:58:40.377943
7271 13:58:40.380980 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7272 13:58:40.381056
7273 13:58:40.384756 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7274 13:58:40.387391 [DutyScan_Calibration_Flow] ====Done====
7275 13:58:40.387463 ==
7276 13:58:40.390889 Dram Type= 6, Freq= 0, CH_1, rank 0
7277 13:58:40.394005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7278 13:58:40.394110 ==
7279 13:58:40.397615 [Duty_Offset_Calibration]
7280 13:58:40.397713 B0:0 B1:-1 CA:3
7281 13:58:40.397807
7282 13:58:40.401213 [DutyScan_Calibration_Flow] k_type=0
7283 13:58:40.410987
7284 13:58:40.411065 ==CLK 0==
7285 13:58:40.414046 Final CLK duty delay cell = -4
7286 13:58:40.417530 [-4] MAX Duty = 5000%(X100), DQS PI = 6
7287 13:58:40.420466 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7288 13:58:40.424148 [-4] AVG Duty = 4937%(X100)
7289 13:58:40.424227
7290 13:58:40.427692 CH1 CLK Duty spec in!! Max-Min= 125%
7291 13:58:40.430908 [DutyScan_Calibration_Flow] ====Done====
7292 13:58:40.430993
7293 13:58:40.433852 [DutyScan_Calibration_Flow] k_type=1
7294 13:58:40.450323
7295 13:58:40.450403 ==DQS 0 ==
7296 13:58:40.453197 Final DQS duty delay cell = 0
7297 13:58:40.456571 [0] MAX Duty = 5250%(X100), DQS PI = 20
7298 13:58:40.459918 [0] MIN Duty = 4907%(X100), DQS PI = 58
7299 13:58:40.462981 [0] AVG Duty = 5078%(X100)
7300 13:58:40.463061
7301 13:58:40.463125 ==DQS 1 ==
7302 13:58:40.466496 Final DQS duty delay cell = -4
7303 13:58:40.469356 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7304 13:58:40.472940 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7305 13:58:40.476039 [-4] AVG Duty = 4922%(X100)
7306 13:58:40.476118
7307 13:58:40.479583 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7308 13:58:40.479663
7309 13:58:40.483025 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7310 13:58:40.486224 [DutyScan_Calibration_Flow] ====Done====
7311 13:58:40.486304
7312 13:58:40.489585 [DutyScan_Calibration_Flow] k_type=3
7313 13:58:40.506872
7314 13:58:40.506951 ==DQM 0 ==
7315 13:58:40.510831 Final DQM duty delay cell = 0
7316 13:58:40.513943 [0] MAX Duty = 5062%(X100), DQS PI = 30
7317 13:58:40.517306 [0] MIN Duty = 4750%(X100), DQS PI = 40
7318 13:58:40.520453 [0] AVG Duty = 4906%(X100)
7319 13:58:40.520559
7320 13:58:40.520650 ==DQM 1 ==
7321 13:58:40.523357 Final DQM duty delay cell = 0
7322 13:58:40.526816 [0] MAX Duty = 5000%(X100), DQS PI = 32
7323 13:58:40.530455 [0] MIN Duty = 4813%(X100), DQS PI = 14
7324 13:58:40.533539 [0] AVG Duty = 4906%(X100)
7325 13:58:40.533620
7326 13:58:40.537083 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7327 13:58:40.537164
7328 13:58:40.540264 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7329 13:58:40.543496 [DutyScan_Calibration_Flow] ====Done====
7330 13:58:40.543577
7331 13:58:40.546582 [DutyScan_Calibration_Flow] k_type=2
7332 13:58:40.563014
7333 13:58:40.563119 ==DQ 0 ==
7334 13:58:40.566686 Final DQ duty delay cell = -4
7335 13:58:40.570156 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7336 13:58:40.574082 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7337 13:58:40.576320 [-4] AVG Duty = 4875%(X100)
7338 13:58:40.576428
7339 13:58:40.576529 ==DQ 1 ==
7340 13:58:40.579680 Final DQ duty delay cell = 0
7341 13:58:40.583132 [0] MAX Duty = 5031%(X100), DQS PI = 32
7342 13:58:40.586425 [0] MIN Duty = 4875%(X100), DQS PI = 0
7343 13:58:40.590057 [0] AVG Duty = 4953%(X100)
7344 13:58:40.590140
7345 13:58:40.593212 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7346 13:58:40.593295
7347 13:58:40.596721 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7348 13:58:40.599773 [DutyScan_Calibration_Flow] ====Done====
7349 13:58:40.603235 nWR fixed to 30
7350 13:58:40.606241 [ModeRegInit_LP4] CH0 RK0
7351 13:58:40.606324 [ModeRegInit_LP4] CH0 RK1
7352 13:58:40.609343 [ModeRegInit_LP4] CH1 RK0
7353 13:58:40.613050 [ModeRegInit_LP4] CH1 RK1
7354 13:58:40.613149 match AC timing 5
7355 13:58:40.619338 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7356 13:58:40.622422 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7357 13:58:40.625595 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7358 13:58:40.632413 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7359 13:58:40.635892 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7360 13:58:40.636016 [MiockJmeterHQA]
7361 13:58:40.639228
7362 13:58:40.642052 [DramcMiockJmeter] u1RxGatingPI = 0
7363 13:58:40.642135 0 : 4365, 4138
7364 13:58:40.642222 4 : 4252, 4027
7365 13:58:40.645295 8 : 4363, 4137
7366 13:58:40.645380 12 : 4253, 4027
7367 13:58:40.649041 16 : 4252, 4027
7368 13:58:40.649126 20 : 4253, 4026
7369 13:58:40.652268 24 : 4257, 4029
7370 13:58:40.652352 28 : 4250, 4027
7371 13:58:40.652437 32 : 4252, 4027
7372 13:58:40.655586 36 : 4368, 4140
7373 13:58:40.655670 40 : 4252, 4027
7374 13:58:40.659208 44 : 4252, 4027
7375 13:58:40.659293 48 : 4255, 4029
7376 13:58:40.662143 52 : 4255, 4029
7377 13:58:40.662228 56 : 4255, 4029
7378 13:58:40.665503 60 : 4363, 4137
7379 13:58:40.665587 64 : 4363, 4138
7380 13:58:40.665673 68 : 4366, 4139
7381 13:58:40.668270 72 : 4253, 4029
7382 13:58:40.668355 76 : 4253, 4029
7383 13:58:40.671517 80 : 4253, 4029
7384 13:58:40.671618 84 : 4252, 4029
7385 13:58:40.675323 88 : 4360, 4137
7386 13:58:40.675408 92 : 4250, 4027
7387 13:58:40.678396 96 : 4250, 3042
7388 13:58:40.678480 100 : 4250, 0
7389 13:58:40.678566 104 : 4360, 0
7390 13:58:40.681545 108 : 4252, 0
7391 13:58:40.681629 112 : 4250, 0
7392 13:58:40.685217 116 : 4250, 0
7393 13:58:40.685301 120 : 4252, 0
7394 13:58:40.685386 124 : 4250, 0
7395 13:58:40.688138 128 : 4250, 0
7396 13:58:40.688222 132 : 4252, 0
7397 13:58:40.688308 136 : 4363, 0
7398 13:58:40.691370 140 : 4250, 0
7399 13:58:40.691455 144 : 4363, 0
7400 13:58:40.694997 148 : 4255, 0
7401 13:58:40.695081 152 : 4250, 0
7402 13:58:40.695167 156 : 4250, 0
7403 13:58:40.697863 160 : 4255, 0
7404 13:58:40.697946 164 : 4250, 0
7405 13:58:40.702028 168 : 4250, 0
7406 13:58:40.702112 172 : 4252, 0
7407 13:58:40.702198 176 : 4250, 0
7408 13:58:40.704578 180 : 4250, 0
7409 13:58:40.704663 184 : 4252, 0
7410 13:58:40.708616 188 : 4361, 0
7411 13:58:40.708700 192 : 4250, 0
7412 13:58:40.708787 196 : 4363, 0
7413 13:58:40.711532 200 : 4255, 0
7414 13:58:40.711617 204 : 4250, 0
7415 13:58:40.714737 208 : 4250, 0
7416 13:58:40.714822 212 : 4255, 0
7417 13:58:40.714924 216 : 4250, 0
7418 13:58:40.717638 220 : 4250, 702
7419 13:58:40.717720 224 : 4250, 3998
7420 13:58:40.720894 228 : 4250, 4027
7421 13:58:40.720984 232 : 4360, 4138
7422 13:58:40.724189 236 : 4250, 4027
7423 13:58:40.724271 240 : 4250, 4027
7424 13:58:40.727379 244 : 4250, 4027
7425 13:58:40.727462 248 : 4364, 4140
7426 13:58:40.731059 252 : 4250, 4027
7427 13:58:40.731144 256 : 4250, 4027
7428 13:58:40.734488 260 : 4361, 4137
7429 13:58:40.734573 264 : 4250, 4027
7430 13:58:40.737107 268 : 4249, 4027
7431 13:58:40.737191 272 : 4360, 4137
7432 13:58:40.737278 276 : 4360, 4138
7433 13:58:40.740727 280 : 4250, 4027
7434 13:58:40.740812 284 : 4250, 4026
7435 13:58:40.744148 288 : 4249, 4027
7436 13:58:40.744233 292 : 4250, 4027
7437 13:58:40.747233 296 : 4250, 4027
7438 13:58:40.747318 300 : 4363, 4140
7439 13:58:40.750822 304 : 4252, 4029
7440 13:58:40.750907 308 : 4250, 4027
7441 13:58:40.753917 312 : 4361, 4137
7442 13:58:40.754002 316 : 4249, 4027
7443 13:58:40.757163 320 : 4249, 4027
7444 13:58:40.757248 324 : 4360, 4137
7445 13:58:40.760747 328 : 4360, 4138
7446 13:58:40.760831 332 : 4249, 3997
7447 13:58:40.760919 336 : 4249, 1801
7448 13:58:40.763697
7449 13:58:40.763781 MIOCK jitter meter ch=0
7450 13:58:40.763881
7451 13:58:40.766961 1T = (336-100) = 236 dly cells
7452 13:58:40.773772 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7453 13:58:40.773856 ==
7454 13:58:40.777111 Dram Type= 6, Freq= 0, CH_0, rank 0
7455 13:58:40.780302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7456 13:58:40.780386 ==
7457 13:58:40.787808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7458 13:58:40.790522 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7459 13:58:40.793594 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7460 13:58:40.800294 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7461 13:58:40.809743 [CA 0] Center 43 (13~73) winsize 61
7462 13:58:40.812969 [CA 1] Center 42 (12~73) winsize 62
7463 13:58:40.816879 [CA 2] Center 37 (8~67) winsize 60
7464 13:58:40.819552 [CA 3] Center 37 (8~67) winsize 60
7465 13:58:40.823065 [CA 4] Center 36 (6~66) winsize 61
7466 13:58:40.825982 [CA 5] Center 35 (5~66) winsize 62
7467 13:58:40.826065
7468 13:58:40.829490 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7469 13:58:40.829574
7470 13:58:40.832852 [CATrainingPosCal] consider 1 rank data
7471 13:58:40.836672 u2DelayCellTimex100 = 275/100 ps
7472 13:58:40.839354 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7473 13:58:40.846473 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7474 13:58:40.849536 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7475 13:58:40.852669 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7476 13:58:40.855791 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7477 13:58:40.859242 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7478 13:58:40.859325
7479 13:58:40.863071 CA PerBit enable=1, Macro0, CA PI delay=35
7480 13:58:40.863154
7481 13:58:40.865920 [CBTSetCACLKResult] CA Dly = 35
7482 13:58:40.869140 CS Dly: 10 (0~41)
7483 13:58:40.872743 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7484 13:58:40.875444 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7485 13:58:40.875528 ==
7486 13:58:40.879189 Dram Type= 6, Freq= 0, CH_0, rank 1
7487 13:58:40.885758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7488 13:58:40.885843 ==
7489 13:58:40.888951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7490 13:58:40.895989 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7491 13:58:40.898613 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7492 13:58:40.905144 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7493 13:58:40.913656 [CA 0] Center 44 (14~75) winsize 62
7494 13:58:40.916925 [CA 1] Center 44 (14~74) winsize 61
7495 13:58:40.920009 [CA 2] Center 39 (10~69) winsize 60
7496 13:58:40.922672 [CA 3] Center 39 (10~68) winsize 59
7497 13:58:40.926570 [CA 4] Center 37 (7~67) winsize 61
7498 13:58:40.929664 [CA 5] Center 36 (7~66) winsize 60
7499 13:58:40.929748
7500 13:58:40.932511 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7501 13:58:40.936088
7502 13:58:40.939495 [CATrainingPosCal] consider 2 rank data
7503 13:58:40.939578 u2DelayCellTimex100 = 275/100 ps
7504 13:58:40.945931 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7505 13:58:40.949803 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7506 13:58:40.952573 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7507 13:58:40.955859 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7508 13:58:40.959382 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7509 13:58:40.962793 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7510 13:58:40.962876
7511 13:58:40.965741 CA PerBit enable=1, Macro0, CA PI delay=36
7512 13:58:40.965825
7513 13:58:40.968932 [CBTSetCACLKResult] CA Dly = 36
7514 13:58:40.972258 CS Dly: 11 (0~43)
7515 13:58:40.975377 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7516 13:58:40.978711 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7517 13:58:40.978794
7518 13:58:40.983023 ----->DramcWriteLeveling(PI) begin...
7519 13:58:40.985643 ==
7520 13:58:40.988590 Dram Type= 6, Freq= 0, CH_0, rank 0
7521 13:58:40.992732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7522 13:58:40.992817 ==
7523 13:58:40.996035 Write leveling (Byte 0): 35 => 35
7524 13:58:40.998578 Write leveling (Byte 1): 29 => 29
7525 13:58:41.002103 DramcWriteLeveling(PI) end<-----
7526 13:58:41.002187
7527 13:58:41.002271 ==
7528 13:58:41.005270 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 13:58:41.008467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 13:58:41.008550 ==
7531 13:58:41.012257 [Gating] SW mode calibration
7532 13:58:41.018335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7533 13:58:41.024899 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7534 13:58:41.028465 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7535 13:58:41.031458 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7536 13:58:41.038827 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7537 13:58:41.042022 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7538 13:58:41.044654 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7539 13:58:41.051262 1 4 20 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7540 13:58:41.054952 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7541 13:58:41.058343 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7542 13:58:41.064960 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7543 13:58:41.068325 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7544 13:58:41.071206 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7545 13:58:41.078564 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
7546 13:58:41.081263 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7547 13:58:41.084435 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
7548 13:58:41.091409 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 13:58:41.094324 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 13:58:41.097742 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 13:58:41.104180 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 13:58:41.107820 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7553 13:58:41.110967 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7554 13:58:41.117439 1 6 16 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
7555 13:58:41.120907 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7556 13:58:41.124311 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 13:58:41.130671 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 13:58:41.133844 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 13:58:41.137376 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 13:58:41.143853 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 13:58:41.147656 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7562 13:58:41.150682 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7563 13:58:41.158117 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7564 13:58:41.160603 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7565 13:58:41.163670 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 13:58:41.170725 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 13:58:41.173692 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 13:58:41.177066 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 13:58:41.183587 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 13:58:41.186544 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 13:58:41.190214 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 13:58:41.196382 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 13:58:41.200090 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 13:58:41.203035 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 13:58:41.209829 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 13:58:41.213041 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7577 13:58:41.216331 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7578 13:58:41.223107 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7579 13:58:41.223184 Total UI for P1: 0, mck2ui 16
7580 13:58:41.229602 best dqsien dly found for B0: ( 1, 9, 10)
7581 13:58:41.232814 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7582 13:58:41.236296 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 13:58:41.239611 Total UI for P1: 0, mck2ui 16
7584 13:58:41.242583 best dqsien dly found for B1: ( 1, 9, 20)
7585 13:58:41.245942 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7586 13:58:41.249715 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7587 13:58:41.249814
7588 13:58:41.256081 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7589 13:58:41.259454 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7590 13:58:41.259528 [Gating] SW calibration Done
7591 13:58:41.262591 ==
7592 13:58:41.266038 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 13:58:41.269221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 13:58:41.269319 ==
7595 13:58:41.269408 RX Vref Scan: 0
7596 13:58:41.269494
7597 13:58:41.272540 RX Vref 0 -> 0, step: 1
7598 13:58:41.272608
7599 13:58:41.275842 RX Delay 0 -> 252, step: 8
7600 13:58:41.279460 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7601 13:58:41.282982 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7602 13:58:41.286015 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7603 13:58:41.292542 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7604 13:58:41.296080 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7605 13:58:41.299502 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7606 13:58:41.302192 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7607 13:58:41.305870 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7608 13:58:41.311842 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7609 13:58:41.315714 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7610 13:58:41.318836 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7611 13:58:41.322330 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7612 13:58:41.328829 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7613 13:58:41.331889 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7614 13:58:41.335576 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7615 13:58:41.338436 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7616 13:58:41.338534 ==
7617 13:58:41.341966 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 13:58:41.349400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 13:58:41.349498 ==
7620 13:58:41.349590 DQS Delay:
7621 13:58:41.349677 DQS0 = 0, DQS1 = 0
7622 13:58:41.351628 DQM Delay:
7623 13:58:41.351725 DQM0 = 130, DQM1 = 125
7624 13:58:41.355212 DQ Delay:
7625 13:58:41.358320 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7626 13:58:41.361515 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7627 13:58:41.364983 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7628 13:58:41.368089 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7629 13:58:41.368163
7630 13:58:41.368225
7631 13:58:41.368283 ==
7632 13:58:41.371403 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 13:58:41.374546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 13:58:41.377982 ==
7635 13:58:41.378051
7636 13:58:41.378111
7637 13:58:41.378187 TX Vref Scan disable
7638 13:58:41.381186 == TX Byte 0 ==
7639 13:58:41.384585 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7640 13:58:41.387998 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7641 13:58:41.391483 == TX Byte 1 ==
7642 13:58:41.394373 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7643 13:58:41.400995 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7644 13:58:41.401071 ==
7645 13:58:41.404178 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 13:58:41.407522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 13:58:41.407592 ==
7648 13:58:41.420838
7649 13:58:41.424073 TX Vref early break, caculate TX vref
7650 13:58:41.426943 TX Vref=16, minBit 8, minWin=21, winSum=369
7651 13:58:41.430471 TX Vref=18, minBit 8, minWin=22, winSum=382
7652 13:58:41.433405 TX Vref=20, minBit 1, minWin=23, winSum=389
7653 13:58:41.437334 TX Vref=22, minBit 4, minWin=24, winSum=398
7654 13:58:41.440153 TX Vref=24, minBit 7, minWin=24, winSum=409
7655 13:58:41.447213 TX Vref=26, minBit 1, minWin=25, winSum=417
7656 13:58:41.450096 TX Vref=28, minBit 2, minWin=25, winSum=419
7657 13:58:41.453152 TX Vref=30, minBit 2, minWin=25, winSum=419
7658 13:58:41.457216 TX Vref=32, minBit 1, minWin=25, winSum=408
7659 13:58:41.460140 TX Vref=34, minBit 2, minWin=23, winSum=396
7660 13:58:41.466809 [TxChooseVref] Worse bit 2, Min win 25, Win sum 419, Final Vref 28
7661 13:58:41.466906
7662 13:58:41.469887 Final TX Range 0 Vref 28
7663 13:58:41.469958
7664 13:58:41.470017 ==
7665 13:58:41.473128 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 13:58:41.476910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 13:58:41.477009 ==
7668 13:58:41.477097
7669 13:58:41.477183
7670 13:58:41.480744 TX Vref Scan disable
7671 13:58:41.486904 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7672 13:58:41.486982 == TX Byte 0 ==
7673 13:58:41.489926 u2DelayCellOfst[0]=14 cells (4 PI)
7674 13:58:41.493333 u2DelayCellOfst[1]=17 cells (5 PI)
7675 13:58:41.496176 u2DelayCellOfst[2]=14 cells (4 PI)
7676 13:58:41.499498 u2DelayCellOfst[3]=14 cells (4 PI)
7677 13:58:41.503158 u2DelayCellOfst[4]=10 cells (3 PI)
7678 13:58:41.506080 u2DelayCellOfst[5]=0 cells (0 PI)
7679 13:58:41.509841 u2DelayCellOfst[6]=17 cells (5 PI)
7680 13:58:41.512822 u2DelayCellOfst[7]=21 cells (6 PI)
7681 13:58:41.516368 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7682 13:58:41.519391 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7683 13:58:41.522634 == TX Byte 1 ==
7684 13:58:41.525969 u2DelayCellOfst[8]=0 cells (0 PI)
7685 13:58:41.529287 u2DelayCellOfst[9]=0 cells (0 PI)
7686 13:58:41.529367 u2DelayCellOfst[10]=7 cells (2 PI)
7687 13:58:41.532650 u2DelayCellOfst[11]=0 cells (0 PI)
7688 13:58:41.536107 u2DelayCellOfst[12]=10 cells (3 PI)
7689 13:58:41.539374 u2DelayCellOfst[13]=10 cells (3 PI)
7690 13:58:41.542541 u2DelayCellOfst[14]=14 cells (4 PI)
7691 13:58:41.546074 u2DelayCellOfst[15]=10 cells (3 PI)
7692 13:58:41.552616 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7693 13:58:41.555867 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7694 13:58:41.555965 DramC Write-DBI on
7695 13:58:41.556031 ==
7696 13:58:41.559052 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 13:58:41.565653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 13:58:41.565735 ==
7699 13:58:41.565799
7700 13:58:41.565858
7701 13:58:41.565915 TX Vref Scan disable
7702 13:58:41.570405 == TX Byte 0 ==
7703 13:58:41.573680 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7704 13:58:41.576617 == TX Byte 1 ==
7705 13:58:41.579796 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7706 13:58:41.582823 DramC Write-DBI off
7707 13:58:41.582903
7708 13:58:41.582967 [DATLAT]
7709 13:58:41.583027 Freq=1600, CH0 RK0
7710 13:58:41.583085
7711 13:58:41.586803 DATLAT Default: 0xf
7712 13:58:41.589942 0, 0xFFFF, sum = 0
7713 13:58:41.590024 1, 0xFFFF, sum = 0
7714 13:58:41.592871 2, 0xFFFF, sum = 0
7715 13:58:41.592953 3, 0xFFFF, sum = 0
7716 13:58:41.596647 4, 0xFFFF, sum = 0
7717 13:58:41.596729 5, 0xFFFF, sum = 0
7718 13:58:41.599658 6, 0xFFFF, sum = 0
7719 13:58:41.599739 7, 0xFFFF, sum = 0
7720 13:58:41.602808 8, 0xFFFF, sum = 0
7721 13:58:41.602889 9, 0xFFFF, sum = 0
7722 13:58:41.606675 10, 0xFFFF, sum = 0
7723 13:58:41.606757 11, 0xFFFF, sum = 0
7724 13:58:41.609568 12, 0xFFFF, sum = 0
7725 13:58:41.609650 13, 0xFFFF, sum = 0
7726 13:58:41.612818 14, 0x0, sum = 1
7727 13:58:41.612900 15, 0x0, sum = 2
7728 13:58:41.616224 16, 0x0, sum = 3
7729 13:58:41.616305 17, 0x0, sum = 4
7730 13:58:41.619365 best_step = 15
7731 13:58:41.619445
7732 13:58:41.619509 ==
7733 13:58:41.622906 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 13:58:41.626313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 13:58:41.626395 ==
7736 13:58:41.629385 RX Vref Scan: 1
7737 13:58:41.629465
7738 13:58:41.629529 Set Vref Range= 24 -> 127
7739 13:58:41.629589
7740 13:58:41.632774 RX Vref 24 -> 127, step: 1
7741 13:58:41.632854
7742 13:58:41.636149 RX Delay 11 -> 252, step: 4
7743 13:58:41.636230
7744 13:58:41.639334 Set Vref, RX VrefLevel [Byte0]: 24
7745 13:58:41.643143 [Byte1]: 24
7746 13:58:41.643223
7747 13:58:41.646489 Set Vref, RX VrefLevel [Byte0]: 25
7748 13:58:41.649101 [Byte1]: 25
7749 13:58:41.653080
7750 13:58:41.653159 Set Vref, RX VrefLevel [Byte0]: 26
7751 13:58:41.656250 [Byte1]: 26
7752 13:58:41.660530
7753 13:58:41.660609 Set Vref, RX VrefLevel [Byte0]: 27
7754 13:58:41.663402 [Byte1]: 27
7755 13:58:41.668090
7756 13:58:41.668170 Set Vref, RX VrefLevel [Byte0]: 28
7757 13:58:41.671498 [Byte1]: 28
7758 13:58:41.675750
7759 13:58:41.675830 Set Vref, RX VrefLevel [Byte0]: 29
7760 13:58:41.679138 [Byte1]: 29
7761 13:58:41.683411
7762 13:58:41.683491 Set Vref, RX VrefLevel [Byte0]: 30
7763 13:58:41.686293 [Byte1]: 30
7764 13:58:41.690575
7765 13:58:41.690654 Set Vref, RX VrefLevel [Byte0]: 31
7766 13:58:41.694391 [Byte1]: 31
7767 13:58:41.699114
7768 13:58:41.699194 Set Vref, RX VrefLevel [Byte0]: 32
7769 13:58:41.701600 [Byte1]: 32
7770 13:58:41.705818
7771 13:58:41.705898 Set Vref, RX VrefLevel [Byte0]: 33
7772 13:58:41.709251 [Byte1]: 33
7773 13:58:41.713406
7774 13:58:41.713486 Set Vref, RX VrefLevel [Byte0]: 34
7775 13:58:41.716702 [Byte1]: 34
7776 13:58:41.721654
7777 13:58:41.721734 Set Vref, RX VrefLevel [Byte0]: 35
7778 13:58:41.724740 [Byte1]: 35
7779 13:58:41.728975
7780 13:58:41.729055 Set Vref, RX VrefLevel [Byte0]: 36
7781 13:58:41.732782 [Byte1]: 36
7782 13:58:41.736438
7783 13:58:41.736518 Set Vref, RX VrefLevel [Byte0]: 37
7784 13:58:41.740182 [Byte1]: 37
7785 13:58:41.744432
7786 13:58:41.744512 Set Vref, RX VrefLevel [Byte0]: 38
7787 13:58:41.747339 [Byte1]: 38
7788 13:58:41.752048
7789 13:58:41.752128 Set Vref, RX VrefLevel [Byte0]: 39
7790 13:58:41.755455 [Byte1]: 39
7791 13:58:41.759368
7792 13:58:41.759449 Set Vref, RX VrefLevel [Byte0]: 40
7793 13:58:41.762617 [Byte1]: 40
7794 13:58:41.767033
7795 13:58:41.767113 Set Vref, RX VrefLevel [Byte0]: 41
7796 13:58:41.770381 [Byte1]: 41
7797 13:58:41.774882
7798 13:58:41.774962 Set Vref, RX VrefLevel [Byte0]: 42
7799 13:58:41.777818 [Byte1]: 42
7800 13:58:41.782418
7801 13:58:41.782498 Set Vref, RX VrefLevel [Byte0]: 43
7802 13:58:41.785490 [Byte1]: 43
7803 13:58:41.789846
7804 13:58:41.789926 Set Vref, RX VrefLevel [Byte0]: 44
7805 13:58:41.793332 [Byte1]: 44
7806 13:58:41.797656
7807 13:58:41.797736 Set Vref, RX VrefLevel [Byte0]: 45
7808 13:58:41.801097 [Byte1]: 45
7809 13:58:41.805227
7810 13:58:41.805307 Set Vref, RX VrefLevel [Byte0]: 46
7811 13:58:41.808363 [Byte1]: 46
7812 13:58:41.812492
7813 13:58:41.812572 Set Vref, RX VrefLevel [Byte0]: 47
7814 13:58:41.816144 [Byte1]: 47
7815 13:58:41.820069
7816 13:58:41.820149 Set Vref, RX VrefLevel [Byte0]: 48
7817 13:58:41.823231 [Byte1]: 48
7818 13:58:41.827850
7819 13:58:41.827936 Set Vref, RX VrefLevel [Byte0]: 49
7820 13:58:41.831032 [Byte1]: 49
7821 13:58:41.835499
7822 13:58:41.835579 Set Vref, RX VrefLevel [Byte0]: 50
7823 13:58:41.838523 [Byte1]: 50
7824 13:58:41.843235
7825 13:58:41.843316 Set Vref, RX VrefLevel [Byte0]: 51
7826 13:58:41.846521 [Byte1]: 51
7827 13:58:41.850510
7828 13:58:41.850590 Set Vref, RX VrefLevel [Byte0]: 52
7829 13:58:41.854222 [Byte1]: 52
7830 13:58:41.858989
7831 13:58:41.859096 Set Vref, RX VrefLevel [Byte0]: 53
7832 13:58:41.861812 [Byte1]: 53
7833 13:58:41.865820
7834 13:58:41.865919 Set Vref, RX VrefLevel [Byte0]: 54
7835 13:58:41.869092 [Byte1]: 54
7836 13:58:41.873755
7837 13:58:41.873826 Set Vref, RX VrefLevel [Byte0]: 55
7838 13:58:41.877441 [Byte1]: 55
7839 13:58:41.880915
7840 13:58:41.881013 Set Vref, RX VrefLevel [Byte0]: 56
7841 13:58:41.884692 [Byte1]: 56
7842 13:58:41.888411
7843 13:58:41.888482 Set Vref, RX VrefLevel [Byte0]: 57
7844 13:58:41.892179 [Byte1]: 57
7845 13:58:41.896343
7846 13:58:41.896416 Set Vref, RX VrefLevel [Byte0]: 58
7847 13:58:41.900025 [Byte1]: 58
7848 13:58:41.903915
7849 13:58:41.903990 Set Vref, RX VrefLevel [Byte0]: 59
7850 13:58:41.906976 [Byte1]: 59
7851 13:58:41.911470
7852 13:58:41.911542 Set Vref, RX VrefLevel [Byte0]: 60
7853 13:58:41.914762 [Byte1]: 60
7854 13:58:41.919537
7855 13:58:41.919614 Set Vref, RX VrefLevel [Byte0]: 61
7856 13:58:41.922550 [Byte1]: 61
7857 13:58:41.926969
7858 13:58:41.927044 Set Vref, RX VrefLevel [Byte0]: 62
7859 13:58:41.929890 [Byte1]: 62
7860 13:58:41.934356
7861 13:58:41.934436 Set Vref, RX VrefLevel [Byte0]: 63
7862 13:58:41.938072 [Byte1]: 63
7863 13:58:41.942204
7864 13:58:41.942284 Set Vref, RX VrefLevel [Byte0]: 64
7865 13:58:41.945314 [Byte1]: 64
7866 13:58:41.949494
7867 13:58:41.949574 Set Vref, RX VrefLevel [Byte0]: 65
7868 13:58:41.952929 [Byte1]: 65
7869 13:58:41.957038
7870 13:58:41.957119 Set Vref, RX VrefLevel [Byte0]: 66
7871 13:58:41.960846 [Byte1]: 66
7872 13:58:41.964596
7873 13:58:41.964675 Set Vref, RX VrefLevel [Byte0]: 67
7874 13:58:41.969199 [Byte1]: 67
7875 13:58:41.973009
7876 13:58:41.973089 Set Vref, RX VrefLevel [Byte0]: 68
7877 13:58:41.976311 [Byte1]: 68
7878 13:58:41.980051
7879 13:58:41.980132 Set Vref, RX VrefLevel [Byte0]: 69
7880 13:58:41.983724 [Byte1]: 69
7881 13:58:41.987480
7882 13:58:41.987561 Set Vref, RX VrefLevel [Byte0]: 70
7883 13:58:41.991047 [Byte1]: 70
7884 13:58:41.995687
7885 13:58:41.995768 Set Vref, RX VrefLevel [Byte0]: 71
7886 13:58:41.998836 [Byte1]: 71
7887 13:58:42.003170
7888 13:58:42.003252 Set Vref, RX VrefLevel [Byte0]: 72
7889 13:58:42.005961 [Byte1]: 72
7890 13:58:42.010467
7891 13:58:42.010548 Set Vref, RX VrefLevel [Byte0]: 73
7892 13:58:42.013878 [Byte1]: 73
7893 13:58:42.018507
7894 13:58:42.018587 Final RX Vref Byte 0 = 56 to rank0
7895 13:58:42.021290 Final RX Vref Byte 1 = 60 to rank0
7896 13:58:42.024782 Final RX Vref Byte 0 = 56 to rank1
7897 13:58:42.027836 Final RX Vref Byte 1 = 60 to rank1==
7898 13:58:42.031222 Dram Type= 6, Freq= 0, CH_0, rank 0
7899 13:58:42.038700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7900 13:58:42.038783 ==
7901 13:58:42.038879 DQS Delay:
7902 13:58:42.038971 DQS0 = 0, DQS1 = 0
7903 13:58:42.041436 DQM Delay:
7904 13:58:42.041517 DQM0 = 128, DQM1 = 124
7905 13:58:42.044540 DQ Delay:
7906 13:58:42.047939 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7907 13:58:42.051197 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7908 13:58:42.054553 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7909 13:58:42.057954 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =130
7910 13:58:42.058037
7911 13:58:42.058101
7912 13:58:42.058160
7913 13:58:42.060908 [DramC_TX_OE_Calibration] TA2
7914 13:58:42.064521 Original DQ_B0 (3 6) =30, OEN = 27
7915 13:58:42.068069 Original DQ_B1 (3 6) =30, OEN = 27
7916 13:58:42.070781 24, 0x0, End_B0=24 End_B1=24
7917 13:58:42.070864 25, 0x0, End_B0=25 End_B1=25
7918 13:58:42.074104 26, 0x0, End_B0=26 End_B1=26
7919 13:58:42.077682 27, 0x0, End_B0=27 End_B1=27
7920 13:58:42.081071 28, 0x0, End_B0=28 End_B1=28
7921 13:58:42.083814 29, 0x0, End_B0=29 End_B1=29
7922 13:58:42.083897 30, 0x0, End_B0=30 End_B1=30
7923 13:58:42.087101 31, 0x4141, End_B0=30 End_B1=30
7924 13:58:42.090475 Byte0 end_step=30 best_step=27
7925 13:58:42.094286 Byte1 end_step=30 best_step=27
7926 13:58:42.097956 Byte0 TX OE(2T, 0.5T) = (3, 3)
7927 13:58:42.101210 Byte1 TX OE(2T, 0.5T) = (3, 3)
7928 13:58:42.101292
7929 13:58:42.101356
7930 13:58:42.106968 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7931 13:58:42.110526 CH0 RK0: MR19=303, MR18=1A17
7932 13:58:42.117457 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
7933 13:58:42.117567
7934 13:58:42.120276 ----->DramcWriteLeveling(PI) begin...
7935 13:58:42.120383 ==
7936 13:58:42.123646 Dram Type= 6, Freq= 0, CH_0, rank 1
7937 13:58:42.127040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7938 13:58:42.127176 ==
7939 13:58:42.130357 Write leveling (Byte 0): 34 => 34
7940 13:58:42.133606 Write leveling (Byte 1): 30 => 30
7941 13:58:42.136690 DramcWriteLeveling(PI) end<-----
7942 13:58:42.136774
7943 13:58:42.136859 ==
7944 13:58:42.140014 Dram Type= 6, Freq= 0, CH_0, rank 1
7945 13:58:42.143125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7946 13:58:42.146724 ==
7947 13:58:42.146808 [Gating] SW mode calibration
7948 13:58:42.156285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7949 13:58:42.159928 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7950 13:58:42.163178 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7951 13:58:42.169834 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7952 13:58:42.173095 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7953 13:58:42.176114 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7954 13:58:42.182801 1 4 16 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7955 13:58:42.186714 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
7956 13:58:42.189211 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7957 13:58:42.196139 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7958 13:58:42.199211 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7959 13:58:42.202894 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7960 13:58:42.209637 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7961 13:58:42.212804 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7962 13:58:42.215797 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7963 13:58:42.222335 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7964 13:58:42.225758 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7965 13:58:42.228966 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7966 13:58:42.236176 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 13:58:42.238825 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7968 13:58:42.242520 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7969 13:58:42.249253 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7970 13:58:42.252121 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7971 13:58:42.255899 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7972 13:58:42.262544 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7973 13:58:42.265686 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7974 13:58:42.269103 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7975 13:58:42.275621 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7976 13:58:42.278337 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7977 13:58:42.281785 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7978 13:58:42.288309 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7979 13:58:42.291846 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7980 13:58:42.295179 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7981 13:58:42.301411 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7982 13:58:42.305147 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 13:58:42.308409 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 13:58:42.315025 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 13:58:42.318003 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 13:58:42.321105 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 13:58:42.327763 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 13:58:42.331249 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 13:58:42.334504 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 13:58:42.341004 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 13:58:42.344882 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7992 13:58:42.347534 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7993 13:58:42.354249 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7994 13:58:42.357648 Total UI for P1: 0, mck2ui 16
7995 13:58:42.360726 best dqsien dly found for B0: ( 1, 9, 6)
7996 13:58:42.364052 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7997 13:58:42.367058 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7998 13:58:42.374212 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 13:58:42.377232 Total UI for P1: 0, mck2ui 16
8000 13:58:42.380502 best dqsien dly found for B1: ( 1, 9, 18)
8001 13:58:42.383586 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8002 13:58:42.386734 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8003 13:58:42.386810
8004 13:58:42.390295 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8005 13:58:42.393940 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8006 13:58:42.397047 [Gating] SW calibration Done
8007 13:58:42.397122 ==
8008 13:58:42.400677 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 13:58:42.403133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 13:58:42.403204 ==
8011 13:58:42.406804 RX Vref Scan: 0
8012 13:58:42.406874
8013 13:58:42.410472 RX Vref 0 -> 0, step: 1
8014 13:58:42.410540
8015 13:58:42.410608 RX Delay 0 -> 252, step: 8
8016 13:58:42.417605 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8017 13:58:42.420359 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8018 13:58:42.423083 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8019 13:58:42.426637 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8020 13:58:42.430203 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8021 13:58:42.436269 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8022 13:58:42.439715 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8023 13:58:42.443250 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8024 13:58:42.446272 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8025 13:58:42.449834 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8026 13:58:42.456726 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8027 13:58:42.459300 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8028 13:58:42.462959 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8029 13:58:42.466187 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8030 13:58:42.472737 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8031 13:58:42.476176 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8032 13:58:42.476250 ==
8033 13:58:42.479826 Dram Type= 6, Freq= 0, CH_0, rank 1
8034 13:58:42.482981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 13:58:42.483052 ==
8036 13:58:42.486075 DQS Delay:
8037 13:58:42.486172 DQS0 = 0, DQS1 = 0
8038 13:58:42.486262 DQM Delay:
8039 13:58:42.489410 DQM0 = 133, DQM1 = 124
8040 13:58:42.489507 DQ Delay:
8041 13:58:42.492846 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8042 13:58:42.496346 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =139
8043 13:58:42.499399 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8044 13:58:42.505483 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8045 13:58:42.505583
8046 13:58:42.505672
8047 13:58:42.505761 ==
8048 13:58:42.509067 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 13:58:42.512302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 13:58:42.512381 ==
8051 13:58:42.512456
8052 13:58:42.512546
8053 13:58:42.515782 TX Vref Scan disable
8054 13:58:42.515882 == TX Byte 0 ==
8055 13:58:42.522945 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8056 13:58:42.526089 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8057 13:58:42.529023 == TX Byte 1 ==
8058 13:58:42.531929 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8059 13:58:42.536140 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8060 13:58:42.536221 ==
8061 13:58:42.538697 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 13:58:42.542131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 13:58:42.542212 ==
8064 13:58:42.557798
8065 13:58:42.561008 TX Vref early break, caculate TX vref
8066 13:58:42.564244 TX Vref=16, minBit 9, minWin=22, winSum=381
8067 13:58:42.567297 TX Vref=18, minBit 1, minWin=23, winSum=390
8068 13:58:42.570657 TX Vref=20, minBit 4, minWin=24, winSum=398
8069 13:58:42.574084 TX Vref=22, minBit 9, minWin=24, winSum=405
8070 13:58:42.577120 TX Vref=24, minBit 1, minWin=25, winSum=413
8071 13:58:42.584566 TX Vref=26, minBit 1, minWin=25, winSum=421
8072 13:58:42.587245 TX Vref=28, minBit 4, minWin=25, winSum=421
8073 13:58:42.590307 TX Vref=30, minBit 1, minWin=25, winSum=415
8074 13:58:42.593916 TX Vref=32, minBit 1, minWin=24, winSum=405
8075 13:58:42.597545 TX Vref=34, minBit 1, minWin=24, winSum=401
8076 13:58:42.603767 TX Vref=36, minBit 1, minWin=23, winSum=391
8077 13:58:42.606900 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 26
8078 13:58:42.606982
8079 13:58:42.610407 Final TX Range 0 Vref 26
8080 13:58:42.610488
8081 13:58:42.610566 ==
8082 13:58:42.613698 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 13:58:42.616856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 13:58:42.620246 ==
8085 13:58:42.620354
8086 13:58:42.620421
8087 13:58:42.620481 TX Vref Scan disable
8088 13:58:42.626836 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8089 13:58:42.626954 == TX Byte 0 ==
8090 13:58:42.630667 u2DelayCellOfst[0]=14 cells (4 PI)
8091 13:58:42.634150 u2DelayCellOfst[1]=17 cells (5 PI)
8092 13:58:42.636479 u2DelayCellOfst[2]=10 cells (3 PI)
8093 13:58:42.640266 u2DelayCellOfst[3]=10 cells (3 PI)
8094 13:58:42.643333 u2DelayCellOfst[4]=7 cells (2 PI)
8095 13:58:42.646866 u2DelayCellOfst[5]=0 cells (0 PI)
8096 13:58:42.649769 u2DelayCellOfst[6]=17 cells (5 PI)
8097 13:58:42.653134 u2DelayCellOfst[7]=17 cells (5 PI)
8098 13:58:42.656899 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8099 13:58:42.659775 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8100 13:58:42.663479 == TX Byte 1 ==
8101 13:58:42.666658 u2DelayCellOfst[8]=0 cells (0 PI)
8102 13:58:42.669789 u2DelayCellOfst[9]=0 cells (0 PI)
8103 13:58:42.673222 u2DelayCellOfst[10]=3 cells (1 PI)
8104 13:58:42.676623 u2DelayCellOfst[11]=3 cells (1 PI)
8105 13:58:42.680093 u2DelayCellOfst[12]=10 cells (3 PI)
8106 13:58:42.683521 u2DelayCellOfst[13]=10 cells (3 PI)
8107 13:58:42.686294 u2DelayCellOfst[14]=14 cells (4 PI)
8108 13:58:42.686367 u2DelayCellOfst[15]=10 cells (3 PI)
8109 13:58:42.692807 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8110 13:58:42.696331 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8111 13:58:42.699546 DramC Write-DBI on
8112 13:58:42.699616 ==
8113 13:58:42.702647 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 13:58:42.706076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 13:58:42.706146 ==
8116 13:58:42.706209
8117 13:58:42.706268
8118 13:58:42.709288 TX Vref Scan disable
8119 13:58:42.709359 == TX Byte 0 ==
8120 13:58:42.716933 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8121 13:58:42.717005 == TX Byte 1 ==
8122 13:58:42.722419 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8123 13:58:42.722509 DramC Write-DBI off
8124 13:58:42.722588
8125 13:58:42.722647 [DATLAT]
8126 13:58:42.725920 Freq=1600, CH0 RK1
8127 13:58:42.726048
8128 13:58:42.728906 DATLAT Default: 0xf
8129 13:58:42.729004 0, 0xFFFF, sum = 0
8130 13:58:42.732102 1, 0xFFFF, sum = 0
8131 13:58:42.732175 2, 0xFFFF, sum = 0
8132 13:58:42.735043 3, 0xFFFF, sum = 0
8133 13:58:42.735141 4, 0xFFFF, sum = 0
8134 13:58:42.738608 5, 0xFFFF, sum = 0
8135 13:58:42.738680 6, 0xFFFF, sum = 0
8136 13:58:42.741999 7, 0xFFFF, sum = 0
8137 13:58:42.742085 8, 0xFFFF, sum = 0
8138 13:58:42.745915 9, 0xFFFF, sum = 0
8139 13:58:42.746015 10, 0xFFFF, sum = 0
8140 13:58:42.749588 11, 0xFFFF, sum = 0
8141 13:58:42.749729 12, 0xFFFF, sum = 0
8142 13:58:42.751891 13, 0xFFFF, sum = 0
8143 13:58:42.752027 14, 0x0, sum = 1
8144 13:58:42.755174 15, 0x0, sum = 2
8145 13:58:42.755274 16, 0x0, sum = 3
8146 13:58:42.758156 17, 0x0, sum = 4
8147 13:58:42.758264 best_step = 15
8148 13:58:42.758359
8149 13:58:42.758449 ==
8150 13:58:42.761907 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 13:58:42.768846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 13:58:42.768927 ==
8153 13:58:42.768991 RX Vref Scan: 0
8154 13:58:42.769051
8155 13:58:42.771813 RX Vref 0 -> 0, step: 1
8156 13:58:42.771918
8157 13:58:42.774765 RX Delay 11 -> 252, step: 4
8158 13:58:42.778238 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8159 13:58:42.781814 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8160 13:58:42.788786 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8161 13:58:42.791187 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8162 13:58:42.794671 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8163 13:58:42.797763 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8164 13:58:42.801221 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8165 13:58:42.807627 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8166 13:58:42.811494 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8167 13:58:42.814447 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8168 13:58:42.817898 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8169 13:58:42.821014 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8170 13:58:42.827677 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8171 13:58:42.831064 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8172 13:58:42.834512 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8173 13:58:42.837037 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8174 13:58:42.837116 ==
8175 13:58:42.840659 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 13:58:42.847038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 13:58:42.847143 ==
8178 13:58:42.847235 DQS Delay:
8179 13:58:42.850875 DQS0 = 0, DQS1 = 0
8180 13:58:42.850953 DQM Delay:
8181 13:58:42.853641 DQM0 = 128, DQM1 = 123
8182 13:58:42.853716 DQ Delay:
8183 13:58:42.857233 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8184 13:58:42.860282 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
8185 13:58:42.863870 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8186 13:58:42.867048 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8187 13:58:42.867121
8188 13:58:42.867184
8189 13:58:42.867241
8190 13:58:42.870421 [DramC_TX_OE_Calibration] TA2
8191 13:58:42.873452 Original DQ_B0 (3 6) =30, OEN = 27
8192 13:58:42.876882 Original DQ_B1 (3 6) =30, OEN = 27
8193 13:58:42.880080 24, 0x0, End_B0=24 End_B1=24
8194 13:58:42.883203 25, 0x0, End_B0=25 End_B1=25
8195 13:58:42.883275 26, 0x0, End_B0=26 End_B1=26
8196 13:58:42.886665 27, 0x0, End_B0=27 End_B1=27
8197 13:58:42.889783 28, 0x0, End_B0=28 End_B1=28
8198 13:58:42.893817 29, 0x0, End_B0=29 End_B1=29
8199 13:58:42.896643 30, 0x0, End_B0=30 End_B1=30
8200 13:58:42.896713 31, 0x4141, End_B0=30 End_B1=30
8201 13:58:42.899769 Byte0 end_step=30 best_step=27
8202 13:58:42.903318 Byte1 end_step=30 best_step=27
8203 13:58:42.907296 Byte0 TX OE(2T, 0.5T) = (3, 3)
8204 13:58:42.909578 Byte1 TX OE(2T, 0.5T) = (3, 3)
8205 13:58:42.909678
8206 13:58:42.909737
8207 13:58:42.916311 [DQSOSCAuto] RK1, (LSB)MR18= 0x1715, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8208 13:58:42.919791 CH0 RK1: MR19=303, MR18=1715
8209 13:58:42.926196 CH0_RK1: MR19=0x303, MR18=0x1715, DQSOSC=398, MR23=63, INC=23, DEC=15
8210 13:58:42.929407 [RxdqsGatingPostProcess] freq 1600
8211 13:58:42.936149 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8212 13:58:42.939197 best DQS0 dly(2T, 0.5T) = (1, 1)
8213 13:58:42.939271 best DQS1 dly(2T, 0.5T) = (1, 1)
8214 13:58:42.942867 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8215 13:58:42.945961 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8216 13:58:42.949393 best DQS0 dly(2T, 0.5T) = (1, 1)
8217 13:58:42.952633 best DQS1 dly(2T, 0.5T) = (1, 1)
8218 13:58:42.956146 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8219 13:58:42.958898 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8220 13:58:42.962901 Pre-setting of DQS Precalculation
8221 13:58:42.968906 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8222 13:58:42.969018 ==
8223 13:58:42.972330 Dram Type= 6, Freq= 0, CH_1, rank 0
8224 13:58:42.975276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 13:58:42.975361 ==
8226 13:58:42.982147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8227 13:58:42.985848 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8228 13:58:42.988995 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8229 13:58:42.995363 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8230 13:58:43.004087 [CA 0] Center 42 (12~72) winsize 61
8231 13:58:43.007024 [CA 1] Center 42 (12~72) winsize 61
8232 13:58:43.011106 [CA 2] Center 38 (9~67) winsize 59
8233 13:58:43.014134 [CA 3] Center 37 (8~66) winsize 59
8234 13:58:43.017145 [CA 4] Center 37 (7~67) winsize 61
8235 13:58:43.021235 [CA 5] Center 36 (7~66) winsize 60
8236 13:58:43.021315
8237 13:58:43.023716 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8238 13:58:43.023792
8239 13:58:43.030148 [CATrainingPosCal] consider 1 rank data
8240 13:58:43.030228 u2DelayCellTimex100 = 275/100 ps
8241 13:58:43.036776 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8242 13:58:43.040407 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8243 13:58:43.043311 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8244 13:58:43.046912 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8245 13:58:43.050000 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8246 13:58:43.053476 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8247 13:58:43.053574
8248 13:58:43.056497 CA PerBit enable=1, Macro0, CA PI delay=36
8249 13:58:43.056576
8250 13:58:43.059914 [CBTSetCACLKResult] CA Dly = 36
8251 13:58:43.063051 CS Dly: 8 (0~39)
8252 13:58:43.066800 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8253 13:58:43.070230 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8254 13:58:43.070310 ==
8255 13:58:43.072976 Dram Type= 6, Freq= 0, CH_1, rank 1
8256 13:58:43.079533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8257 13:58:43.079644 ==
8258 13:58:43.082951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8259 13:58:43.089537 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8260 13:58:43.092875 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8261 13:58:43.099285 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8262 13:58:43.106800 [CA 0] Center 41 (11~71) winsize 61
8263 13:58:43.110660 [CA 1] Center 41 (12~71) winsize 60
8264 13:58:43.113549 [CA 2] Center 37 (8~67) winsize 60
8265 13:58:43.117195 [CA 3] Center 36 (7~66) winsize 60
8266 13:58:43.120046 [CA 4] Center 36 (7~66) winsize 60
8267 13:58:43.123275 [CA 5] Center 36 (6~66) winsize 61
8268 13:58:43.123356
8269 13:58:43.126945 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8270 13:58:43.127050
8271 13:58:43.130149 [CATrainingPosCal] consider 2 rank data
8272 13:58:43.133743 u2DelayCellTimex100 = 275/100 ps
8273 13:58:43.140464 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8274 13:58:43.144122 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8275 13:58:43.146995 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8276 13:58:43.150502 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8277 13:58:43.154006 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8278 13:58:43.157048 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8279 13:58:43.157280
8280 13:58:43.159722 CA PerBit enable=1, Macro0, CA PI delay=36
8281 13:58:43.159967
8282 13:58:43.163447 [CBTSetCACLKResult] CA Dly = 36
8283 13:58:43.166384 CS Dly: 9 (0~42)
8284 13:58:43.170271 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8285 13:58:43.173516 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8286 13:58:43.173810
8287 13:58:43.177432 ----->DramcWriteLeveling(PI) begin...
8288 13:58:43.177647 ==
8289 13:58:43.179795 Dram Type= 6, Freq= 0, CH_1, rank 0
8290 13:58:43.186758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8291 13:58:43.187147 ==
8292 13:58:43.189596 Write leveling (Byte 0): 26 => 26
8293 13:58:43.193587 Write leveling (Byte 1): 28 => 28
8294 13:58:43.193962 DramcWriteLeveling(PI) end<-----
8295 13:58:43.196329
8296 13:58:43.196698 ==
8297 13:58:43.199580 Dram Type= 6, Freq= 0, CH_1, rank 0
8298 13:58:43.203326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 13:58:43.203702 ==
8300 13:58:43.206866 [Gating] SW mode calibration
8301 13:58:43.213234 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8302 13:58:43.216081 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8303 13:58:43.223041 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8304 13:58:43.225819 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8305 13:58:43.233915 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8306 13:58:43.235690 1 4 12 | B1->B0 | 2424 3232 | 0 1 | (0 0) (1 1)
8307 13:58:43.239442 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8308 13:58:43.245898 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8309 13:58:43.249637 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 13:58:43.252425 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 13:58:43.258770 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 13:58:43.262511 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 13:58:43.265818 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8314 13:58:43.272147 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
8315 13:58:43.275986 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)
8316 13:58:43.278905 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 13:58:43.285431 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 13:58:43.288719 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 13:58:43.292198 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 13:58:43.298468 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 13:58:43.301569 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8322 13:58:43.305060 1 6 12 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
8323 13:58:43.311813 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8324 13:58:43.315370 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8325 13:58:43.318834 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 13:58:43.324757 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 13:58:43.327809 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 13:58:43.331260 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 13:58:43.337898 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8330 13:58:43.341211 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8331 13:58:43.344531 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8332 13:58:43.351590 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8333 13:58:43.354568 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 13:58:43.357347 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 13:58:43.364343 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 13:58:43.367582 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 13:58:43.371042 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 13:58:43.377860 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 13:58:43.380479 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 13:58:43.383774 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 13:58:43.390931 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 13:58:43.394375 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 13:58:43.397682 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 13:58:43.404618 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 13:58:43.408427 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8346 13:58:43.410861 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8347 13:58:43.417097 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8348 13:58:43.420226 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 13:58:43.424020 Total UI for P1: 0, mck2ui 16
8350 13:58:43.427051 best dqsien dly found for B0: ( 1, 9, 12)
8351 13:58:43.430260 Total UI for P1: 0, mck2ui 16
8352 13:58:43.433902 best dqsien dly found for B1: ( 1, 9, 14)
8353 13:58:43.437165 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8354 13:58:43.440235 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8355 13:58:43.440789
8356 13:58:43.443675 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8357 13:58:43.446862 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8358 13:58:43.450773 [Gating] SW calibration Done
8359 13:58:43.451337 ==
8360 13:58:43.453768 Dram Type= 6, Freq= 0, CH_1, rank 0
8361 13:58:43.456874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8362 13:58:43.460121 ==
8363 13:58:43.460598 RX Vref Scan: 0
8364 13:58:43.460963
8365 13:58:43.463533 RX Vref 0 -> 0, step: 1
8366 13:58:43.464019
8367 13:58:43.464387 RX Delay 0 -> 252, step: 8
8368 13:58:43.470605 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8369 13:58:43.473780 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8370 13:58:43.476365 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8371 13:58:43.480544 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8372 13:58:43.486731 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8373 13:58:43.489634 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8374 13:58:43.493102 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8375 13:58:43.496677 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8376 13:58:43.500020 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8377 13:58:43.506352 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8378 13:58:43.509830 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8379 13:58:43.512670 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8380 13:58:43.515999 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8381 13:58:43.519574 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8382 13:58:43.525657 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8383 13:58:43.528864 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8384 13:58:43.529399 ==
8385 13:58:43.532235 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 13:58:43.535278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 13:58:43.535700 ==
8388 13:58:43.538788 DQS Delay:
8389 13:58:43.539203 DQS0 = 0, DQS1 = 0
8390 13:58:43.542889 DQM Delay:
8391 13:58:43.543303 DQM0 = 133, DQM1 = 129
8392 13:58:43.543635 DQ Delay:
8393 13:58:43.545625 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8394 13:58:43.552398 DQ4 =127, DQ5 =143, DQ6 =147, DQ7 =127
8395 13:58:43.555728 DQ8 =115, DQ9 =119, DQ10 =127, DQ11 =123
8396 13:58:43.558712 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8397 13:58:43.559145
8398 13:58:43.559475
8399 13:58:43.559956 ==
8400 13:58:43.561979 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 13:58:43.565333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 13:58:43.565813 ==
8403 13:58:43.566222
8404 13:58:43.566550
8405 13:58:43.568272 TX Vref Scan disable
8406 13:58:43.571439 == TX Byte 0 ==
8407 13:58:43.575181 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8408 13:58:43.578409 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8409 13:58:43.581153 == TX Byte 1 ==
8410 13:58:43.584582 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8411 13:58:43.587846 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8412 13:58:43.588359 ==
8413 13:58:43.591486 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 13:58:43.598328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 13:58:43.598816 ==
8416 13:58:43.609468
8417 13:58:43.612663 TX Vref early break, caculate TX vref
8418 13:58:43.616116 TX Vref=16, minBit 8, minWin=21, winSum=368
8419 13:58:43.618917 TX Vref=18, minBit 8, minWin=22, winSum=377
8420 13:58:43.623005 TX Vref=20, minBit 8, minWin=23, winSum=386
8421 13:58:43.625934 TX Vref=22, minBit 8, minWin=23, winSum=396
8422 13:58:43.629480 TX Vref=24, minBit 8, minWin=24, winSum=406
8423 13:58:43.635784 TX Vref=26, minBit 3, minWin=25, winSum=416
8424 13:58:43.639104 TX Vref=28, minBit 13, minWin=25, winSum=419
8425 13:58:43.642049 TX Vref=30, minBit 0, minWin=25, winSum=416
8426 13:58:43.645445 TX Vref=32, minBit 9, minWin=24, winSum=405
8427 13:58:43.648658 TX Vref=34, minBit 11, minWin=23, winSum=396
8428 13:58:43.655715 [TxChooseVref] Worse bit 13, Min win 25, Win sum 419, Final Vref 28
8429 13:58:43.655959
8430 13:58:43.659174 Final TX Range 0 Vref 28
8431 13:58:43.659417
8432 13:58:43.659597 ==
8433 13:58:43.662003 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 13:58:43.666284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 13:58:43.666622 ==
8436 13:58:43.666823
8437 13:58:43.666994
8438 13:58:43.668742 TX Vref Scan disable
8439 13:58:43.675731 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8440 13:58:43.675981 == TX Byte 0 ==
8441 13:58:43.678707 u2DelayCellOfst[0]=17 cells (5 PI)
8442 13:58:43.682136 u2DelayCellOfst[1]=10 cells (3 PI)
8443 13:58:43.685803 u2DelayCellOfst[2]=0 cells (0 PI)
8444 13:58:43.689314 u2DelayCellOfst[3]=7 cells (2 PI)
8445 13:58:43.692546 u2DelayCellOfst[4]=10 cells (3 PI)
8446 13:58:43.696073 u2DelayCellOfst[5]=17 cells (5 PI)
8447 13:58:43.699136 u2DelayCellOfst[6]=17 cells (5 PI)
8448 13:58:43.702101 u2DelayCellOfst[7]=7 cells (2 PI)
8449 13:58:43.705765 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8450 13:58:43.709218 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8451 13:58:43.711981 == TX Byte 1 ==
8452 13:58:43.715384 u2DelayCellOfst[8]=0 cells (0 PI)
8453 13:58:43.718209 u2DelayCellOfst[9]=3 cells (1 PI)
8454 13:58:43.721632 u2DelayCellOfst[10]=14 cells (4 PI)
8455 13:58:43.725139 u2DelayCellOfst[11]=7 cells (2 PI)
8456 13:58:43.725589 u2DelayCellOfst[12]=14 cells (4 PI)
8457 13:58:43.728119 u2DelayCellOfst[13]=17 cells (5 PI)
8458 13:58:43.731154 u2DelayCellOfst[14]=17 cells (5 PI)
8459 13:58:43.734640 u2DelayCellOfst[15]=17 cells (5 PI)
8460 13:58:43.741601 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8461 13:58:43.744871 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8462 13:58:43.745290 DramC Write-DBI on
8463 13:58:43.747970 ==
8464 13:58:43.751293 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 13:58:43.754402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 13:58:43.754820 ==
8467 13:58:43.755148
8468 13:58:43.755456
8469 13:58:43.758290 TX Vref Scan disable
8470 13:58:43.758707 == TX Byte 0 ==
8471 13:58:43.764351 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8472 13:58:43.764872 == TX Byte 1 ==
8473 13:58:43.767596 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8474 13:58:43.771025 DramC Write-DBI off
8475 13:58:43.771471
8476 13:58:43.771830 [DATLAT]
8477 13:58:43.774229 Freq=1600, CH1 RK0
8478 13:58:43.774754
8479 13:58:43.775202 DATLAT Default: 0xf
8480 13:58:43.778344 0, 0xFFFF, sum = 0
8481 13:58:43.778938 1, 0xFFFF, sum = 0
8482 13:58:43.783144 2, 0xFFFF, sum = 0
8483 13:58:43.783569 3, 0xFFFF, sum = 0
8484 13:58:43.784250 4, 0xFFFF, sum = 0
8485 13:58:43.787878 5, 0xFFFF, sum = 0
8486 13:58:43.788343 6, 0xFFFF, sum = 0
8487 13:58:43.791486 7, 0xFFFF, sum = 0
8488 13:58:43.792188 8, 0xFFFF, sum = 0
8489 13:58:43.794214 9, 0xFFFF, sum = 0
8490 13:58:43.794823 10, 0xFFFF, sum = 0
8491 13:58:43.797333 11, 0xFFFF, sum = 0
8492 13:58:43.797916 12, 0xFFFF, sum = 0
8493 13:58:43.800941 13, 0xFFFF, sum = 0
8494 13:58:43.801472 14, 0x0, sum = 1
8495 13:58:43.804067 15, 0x0, sum = 2
8496 13:58:43.804548 16, 0x0, sum = 3
8497 13:58:43.806987 17, 0x0, sum = 4
8498 13:58:43.807544 best_step = 15
8499 13:58:43.808054
8500 13:58:43.808380 ==
8501 13:58:43.810974 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 13:58:43.814589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 13:58:43.817240 ==
8504 13:58:43.817652 RX Vref Scan: 1
8505 13:58:43.817982
8506 13:58:43.820666 Set Vref Range= 24 -> 127
8507 13:58:43.821081
8508 13:58:43.823528 RX Vref 24 -> 127, step: 1
8509 13:58:43.823823
8510 13:58:43.824097 RX Delay 19 -> 252, step: 4
8511 13:58:43.824324
8512 13:58:43.826899 Set Vref, RX VrefLevel [Byte0]: 24
8513 13:58:43.830023 [Byte1]: 24
8514 13:58:43.833809
8515 13:58:43.834040 Set Vref, RX VrefLevel [Byte0]: 25
8516 13:58:43.837564 [Byte1]: 25
8517 13:58:43.841816
8518 13:58:43.842039 Set Vref, RX VrefLevel [Byte0]: 26
8519 13:58:43.845091 [Byte1]: 26
8520 13:58:43.849054
8521 13:58:43.849275 Set Vref, RX VrefLevel [Byte0]: 27
8522 13:58:43.852277 [Byte1]: 27
8523 13:58:43.856761
8524 13:58:43.856843 Set Vref, RX VrefLevel [Byte0]: 28
8525 13:58:43.859726 [Byte1]: 28
8526 13:58:43.863937
8527 13:58:43.864020 Set Vref, RX VrefLevel [Byte0]: 29
8528 13:58:43.867729 [Byte1]: 29
8529 13:58:43.871502
8530 13:58:43.871583 Set Vref, RX VrefLevel [Byte0]: 30
8531 13:58:43.875252 [Byte1]: 30
8532 13:58:43.879402
8533 13:58:43.879489 Set Vref, RX VrefLevel [Byte0]: 31
8534 13:58:43.882852 [Byte1]: 31
8535 13:58:43.886898
8536 13:58:43.887032 Set Vref, RX VrefLevel [Byte0]: 32
8537 13:58:43.890461 [Byte1]: 32
8538 13:58:43.894782
8539 13:58:43.894972 Set Vref, RX VrefLevel [Byte0]: 33
8540 13:58:43.897946 [Byte1]: 33
8541 13:58:43.902311
8542 13:58:43.902528 Set Vref, RX VrefLevel [Byte0]: 34
8543 13:58:43.905647 [Byte1]: 34
8544 13:58:43.909933
8545 13:58:43.910169 Set Vref, RX VrefLevel [Byte0]: 35
8546 13:58:43.913369 [Byte1]: 35
8547 13:58:43.917529
8548 13:58:43.917824 Set Vref, RX VrefLevel [Byte0]: 36
8549 13:58:43.920451 [Byte1]: 36
8550 13:58:43.924887
8551 13:58:43.925141 Set Vref, RX VrefLevel [Byte0]: 37
8552 13:58:43.927886 [Byte1]: 37
8553 13:58:43.933060
8554 13:58:43.933473 Set Vref, RX VrefLevel [Byte0]: 38
8555 13:58:43.936034 [Byte1]: 38
8556 13:58:43.940013
8557 13:58:43.940431 Set Vref, RX VrefLevel [Byte0]: 39
8558 13:58:43.943466 [Byte1]: 39
8559 13:58:43.947777
8560 13:58:43.948271 Set Vref, RX VrefLevel [Byte0]: 40
8561 13:58:43.951042 [Byte1]: 40
8562 13:58:43.955719
8563 13:58:43.956184 Set Vref, RX VrefLevel [Byte0]: 41
8564 13:58:43.958588 [Byte1]: 41
8565 13:58:43.963035
8566 13:58:43.963507 Set Vref, RX VrefLevel [Byte0]: 42
8567 13:58:43.966756 [Byte1]: 42
8568 13:58:43.970635
8569 13:58:43.971075 Set Vref, RX VrefLevel [Byte0]: 43
8570 13:58:43.974070 [Byte1]: 43
8571 13:58:43.978291
8572 13:58:43.978718 Set Vref, RX VrefLevel [Byte0]: 44
8573 13:58:43.981545 [Byte1]: 44
8574 13:58:43.985460
8575 13:58:43.986005 Set Vref, RX VrefLevel [Byte0]: 45
8576 13:58:43.989403 [Byte1]: 45
8577 13:58:43.993251
8578 13:58:43.993667 Set Vref, RX VrefLevel [Byte0]: 46
8579 13:58:43.996432 [Byte1]: 46
8580 13:58:44.000872
8581 13:58:44.001374 Set Vref, RX VrefLevel [Byte0]: 47
8582 13:58:44.004101 [Byte1]: 47
8583 13:58:44.008508
8584 13:58:44.009008 Set Vref, RX VrefLevel [Byte0]: 48
8585 13:58:44.012068 [Byte1]: 48
8586 13:58:44.016232
8587 13:58:44.016737 Set Vref, RX VrefLevel [Byte0]: 49
8588 13:58:44.019283 [Byte1]: 49
8589 13:58:44.023695
8590 13:58:44.024251 Set Vref, RX VrefLevel [Byte0]: 50
8591 13:58:44.027021 [Byte1]: 50
8592 13:58:44.031058
8593 13:58:44.031477 Set Vref, RX VrefLevel [Byte0]: 51
8594 13:58:44.034586 [Byte1]: 51
8595 13:58:44.039068
8596 13:58:44.039578 Set Vref, RX VrefLevel [Byte0]: 52
8597 13:58:44.042125 [Byte1]: 52
8598 13:58:44.046774
8599 13:58:44.047274 Set Vref, RX VrefLevel [Byte0]: 53
8600 13:58:44.049266 [Byte1]: 53
8601 13:58:44.053806
8602 13:58:44.054311 Set Vref, RX VrefLevel [Byte0]: 54
8603 13:58:44.057139 [Byte1]: 54
8604 13:58:44.061428
8605 13:58:44.062149 Set Vref, RX VrefLevel [Byte0]: 55
8606 13:58:44.064529 [Byte1]: 55
8607 13:58:44.069068
8608 13:58:44.069619 Set Vref, RX VrefLevel [Byte0]: 56
8609 13:58:44.072320 [Byte1]: 56
8610 13:58:44.077673
8611 13:58:44.078349 Set Vref, RX VrefLevel [Byte0]: 57
8612 13:58:44.080325 [Byte1]: 57
8613 13:58:44.084411
8614 13:58:44.084959 Set Vref, RX VrefLevel [Byte0]: 58
8615 13:58:44.087585 [Byte1]: 58
8616 13:58:44.092146
8617 13:58:44.092690 Set Vref, RX VrefLevel [Byte0]: 59
8618 13:58:44.095134 [Byte1]: 59
8619 13:58:44.099442
8620 13:58:44.100036 Set Vref, RX VrefLevel [Byte0]: 60
8621 13:58:44.103200 [Byte1]: 60
8622 13:58:44.107376
8623 13:58:44.107981 Set Vref, RX VrefLevel [Byte0]: 61
8624 13:58:44.110454 [Byte1]: 61
8625 13:58:44.115106
8626 13:58:44.115652 Set Vref, RX VrefLevel [Byte0]: 62
8627 13:58:44.118142 [Byte1]: 62
8628 13:58:44.122126
8629 13:58:44.122677 Set Vref, RX VrefLevel [Byte0]: 63
8630 13:58:44.125932 [Byte1]: 63
8631 13:58:44.129648
8632 13:58:44.130332 Set Vref, RX VrefLevel [Byte0]: 64
8633 13:58:44.133070 [Byte1]: 64
8634 13:58:44.137176
8635 13:58:44.137725 Set Vref, RX VrefLevel [Byte0]: 65
8636 13:58:44.141008 [Byte1]: 65
8637 13:58:44.145263
8638 13:58:44.145810 Set Vref, RX VrefLevel [Byte0]: 66
8639 13:58:44.148071 [Byte1]: 66
8640 13:58:44.152542
8641 13:58:44.153092 Set Vref, RX VrefLevel [Byte0]: 67
8642 13:58:44.155382 [Byte1]: 67
8643 13:58:44.160281
8644 13:58:44.160954 Set Vref, RX VrefLevel [Byte0]: 68
8645 13:58:44.163386 [Byte1]: 68
8646 13:58:44.167806
8647 13:58:44.168434 Set Vref, RX VrefLevel [Byte0]: 69
8648 13:58:44.170993 [Byte1]: 69
8649 13:58:44.175722
8650 13:58:44.176360 Set Vref, RX VrefLevel [Byte0]: 70
8651 13:58:44.178274 [Byte1]: 70
8652 13:58:44.183069
8653 13:58:44.183618 Set Vref, RX VrefLevel [Byte0]: 71
8654 13:58:44.186142 [Byte1]: 71
8655 13:58:44.190596
8656 13:58:44.191140 Set Vref, RX VrefLevel [Byte0]: 72
8657 13:58:44.193492 [Byte1]: 72
8658 13:58:44.198461
8659 13:58:44.199008 Final RX Vref Byte 0 = 58 to rank0
8660 13:58:44.200907 Final RX Vref Byte 1 = 61 to rank0
8661 13:58:44.204950 Final RX Vref Byte 0 = 58 to rank1
8662 13:58:44.207997 Final RX Vref Byte 1 = 61 to rank1==
8663 13:58:44.210878 Dram Type= 6, Freq= 0, CH_1, rank 0
8664 13:58:44.218111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8665 13:58:44.218669 ==
8666 13:58:44.219032 DQS Delay:
8667 13:58:44.220540 DQS0 = 0, DQS1 = 0
8668 13:58:44.220996 DQM Delay:
8669 13:58:44.221406 DQM0 = 133, DQM1 = 129
8670 13:58:44.224393 DQ Delay:
8671 13:58:44.227741 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =132
8672 13:58:44.231204 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =130
8673 13:58:44.234566 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
8674 13:58:44.237662 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8675 13:58:44.238218
8676 13:58:44.238583
8677 13:58:44.238924
8678 13:58:44.240814 [DramC_TX_OE_Calibration] TA2
8679 13:58:44.244082 Original DQ_B0 (3 6) =30, OEN = 27
8680 13:58:44.247376 Original DQ_B1 (3 6) =30, OEN = 27
8681 13:58:44.250724 24, 0x0, End_B0=24 End_B1=24
8682 13:58:44.253887 25, 0x0, End_B0=25 End_B1=25
8683 13:58:44.254356 26, 0x0, End_B0=26 End_B1=26
8684 13:58:44.257436 27, 0x0, End_B0=27 End_B1=27
8685 13:58:44.260851 28, 0x0, End_B0=28 End_B1=28
8686 13:58:44.263819 29, 0x0, End_B0=29 End_B1=29
8687 13:58:44.264325 30, 0x0, End_B0=30 End_B1=30
8688 13:58:44.267071 31, 0x4141, End_B0=30 End_B1=30
8689 13:58:44.270249 Byte0 end_step=30 best_step=27
8690 13:58:44.273591 Byte1 end_step=30 best_step=27
8691 13:58:44.277052 Byte0 TX OE(2T, 0.5T) = (3, 3)
8692 13:58:44.280038 Byte1 TX OE(2T, 0.5T) = (3, 3)
8693 13:58:44.280457
8694 13:58:44.280786
8695 13:58:44.286697 [DQSOSCAuto] RK0, (LSB)MR18= 0x111a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
8696 13:58:44.289790 CH1 RK0: MR19=303, MR18=111A
8697 13:58:44.296271 CH1_RK0: MR19=0x303, MR18=0x111A, DQSOSC=396, MR23=63, INC=23, DEC=15
8698 13:58:44.296499
8699 13:58:44.299429 ----->DramcWriteLeveling(PI) begin...
8700 13:58:44.299612 ==
8701 13:58:44.302579 Dram Type= 6, Freq= 0, CH_1, rank 1
8702 13:58:44.306046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8703 13:58:44.306241 ==
8704 13:58:44.309984 Write leveling (Byte 0): 26 => 26
8705 13:58:44.313225 Write leveling (Byte 1): 26 => 26
8706 13:58:44.315861 DramcWriteLeveling(PI) end<-----
8707 13:58:44.316033
8708 13:58:44.316152 ==
8709 13:58:44.319225 Dram Type= 6, Freq= 0, CH_1, rank 1
8710 13:58:44.325994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8711 13:58:44.326145 ==
8712 13:58:44.326265 [Gating] SW mode calibration
8713 13:58:44.336307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8714 13:58:44.339575 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8715 13:58:44.342731 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8716 13:58:44.349208 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8717 13:58:44.352974 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8718 13:58:44.355970 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8719 13:58:44.362375 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8720 13:58:44.366124 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8721 13:58:44.369090 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8722 13:58:44.375996 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8723 13:58:44.378964 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8724 13:58:44.382433 1 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8725 13:58:44.389140 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8726 13:58:44.392221 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8727 13:58:44.395390 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 13:58:44.402541 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 13:58:44.405098 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8730 13:58:44.408651 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 13:58:44.415349 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 13:58:44.418725 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 13:58:44.421935 1 6 8 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8734 13:58:44.428442 1 6 12 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
8735 13:58:44.431538 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8736 13:58:44.435193 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8737 13:58:44.441509 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8738 13:58:44.444895 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8739 13:58:44.448149 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8740 13:58:44.454821 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8741 13:58:44.458277 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8742 13:58:44.461779 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8743 13:58:44.467990 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8744 13:58:44.471328 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 13:58:44.474506 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 13:58:44.481452 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 13:58:44.484550 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 13:58:44.488025 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 13:58:44.494713 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 13:58:44.498014 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 13:58:44.501185 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 13:58:44.507302 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 13:58:44.510513 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 13:58:44.514009 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 13:58:44.520144 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 13:58:44.523865 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8757 13:58:44.527507 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8758 13:58:44.533659 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8759 13:58:44.537532 Total UI for P1: 0, mck2ui 16
8760 13:58:44.540061 best dqsien dly found for B0: ( 1, 9, 6)
8761 13:58:44.543966 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 13:58:44.546598 Total UI for P1: 0, mck2ui 16
8763 13:58:44.550278 best dqsien dly found for B1: ( 1, 9, 12)
8764 13:58:44.553789 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8765 13:58:44.556902 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8766 13:58:44.557068
8767 13:58:44.559857 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8768 13:58:44.566953 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8769 13:58:44.567032 [Gating] SW calibration Done
8770 13:58:44.567100 ==
8771 13:58:44.569919 Dram Type= 6, Freq= 0, CH_1, rank 1
8772 13:58:44.576565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8773 13:58:44.576638 ==
8774 13:58:44.576699 RX Vref Scan: 0
8775 13:58:44.576756
8776 13:58:44.579848 RX Vref 0 -> 0, step: 1
8777 13:58:44.579971
8778 13:58:44.582874 RX Delay 0 -> 252, step: 8
8779 13:58:44.586165 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8780 13:58:44.589377 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8781 13:58:44.592729 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8782 13:58:44.599362 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8783 13:58:44.602465 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8784 13:58:44.605993 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8785 13:58:44.609226 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8786 13:58:44.612276 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8787 13:58:44.619227 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8788 13:58:44.622526 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8789 13:58:44.625848 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8790 13:58:44.628825 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8791 13:58:44.632885 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8792 13:58:44.638909 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8793 13:58:44.642467 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8794 13:58:44.645502 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8795 13:58:44.645821 ==
8796 13:58:44.649284 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 13:58:44.652031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 13:58:44.655148 ==
8799 13:58:44.655253 DQS Delay:
8800 13:58:44.655351 DQS0 = 0, DQS1 = 0
8801 13:58:44.658681 DQM Delay:
8802 13:58:44.658787 DQM0 = 132, DQM1 = 130
8803 13:58:44.661711 DQ Delay:
8804 13:58:44.665547 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8805 13:58:44.669345 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8806 13:58:44.672097 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8807 13:58:44.675202 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8808 13:58:44.675297
8809 13:58:44.675370
8810 13:58:44.675437 ==
8811 13:58:44.678694 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 13:58:44.682121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 13:58:44.682202 ==
8814 13:58:44.685671
8815 13:58:44.685753
8816 13:58:44.685822 TX Vref Scan disable
8817 13:58:44.688417 == TX Byte 0 ==
8818 13:58:44.692183 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8819 13:58:44.695146 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8820 13:58:44.698303 == TX Byte 1 ==
8821 13:58:44.701549 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8822 13:58:44.705282 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8823 13:58:44.708249 ==
8824 13:58:44.708360 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 13:58:44.714932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 13:58:44.715083 ==
8827 13:58:44.727358
8828 13:58:44.730739 TX Vref early break, caculate TX vref
8829 13:58:44.734366 TX Vref=16, minBit 9, minWin=21, winSum=377
8830 13:58:44.737344 TX Vref=18, minBit 9, minWin=22, winSum=380
8831 13:58:44.740887 TX Vref=20, minBit 9, minWin=23, winSum=395
8832 13:58:44.744118 TX Vref=22, minBit 3, minWin=24, winSum=405
8833 13:58:44.747854 TX Vref=24, minBit 9, minWin=24, winSum=412
8834 13:58:44.753950 TX Vref=26, minBit 9, minWin=24, winSum=421
8835 13:58:44.757217 TX Vref=28, minBit 9, minWin=24, winSum=420
8836 13:58:44.760739 TX Vref=30, minBit 8, minWin=25, winSum=421
8837 13:58:44.763867 TX Vref=32, minBit 8, minWin=24, winSum=411
8838 13:58:44.767739 TX Vref=34, minBit 8, minWin=24, winSum=403
8839 13:58:44.770667 TX Vref=36, minBit 8, minWin=23, winSum=398
8840 13:58:44.777676 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 30
8841 13:58:44.777842
8842 13:58:44.780490 Final TX Range 0 Vref 30
8843 13:58:44.780610
8844 13:58:44.780704 ==
8845 13:58:44.784164 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 13:58:44.787132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 13:58:44.787280 ==
8848 13:58:44.790686
8849 13:58:44.790902
8850 13:58:44.791093 TX Vref Scan disable
8851 13:58:44.797444 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8852 13:58:44.797726 == TX Byte 0 ==
8853 13:58:44.800866 u2DelayCellOfst[0]=14 cells (4 PI)
8854 13:58:44.804017 u2DelayCellOfst[1]=10 cells (3 PI)
8855 13:58:44.806753 u2DelayCellOfst[2]=0 cells (0 PI)
8856 13:58:44.810164 u2DelayCellOfst[3]=7 cells (2 PI)
8857 13:58:44.813885 u2DelayCellOfst[4]=7 cells (2 PI)
8858 13:58:44.817507 u2DelayCellOfst[5]=17 cells (5 PI)
8859 13:58:44.820904 u2DelayCellOfst[6]=17 cells (5 PI)
8860 13:58:44.824153 u2DelayCellOfst[7]=7 cells (2 PI)
8861 13:58:44.827272 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8862 13:58:44.830879 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8863 13:58:44.834015 == TX Byte 1 ==
8864 13:58:44.838059 u2DelayCellOfst[8]=0 cells (0 PI)
8865 13:58:44.840575 u2DelayCellOfst[9]=3 cells (1 PI)
8866 13:58:44.843823 u2DelayCellOfst[10]=10 cells (3 PI)
8867 13:58:44.847574 u2DelayCellOfst[11]=3 cells (1 PI)
8868 13:58:44.850602 u2DelayCellOfst[12]=14 cells (4 PI)
8869 13:58:44.851166 u2DelayCellOfst[13]=17 cells (5 PI)
8870 13:58:44.853644 u2DelayCellOfst[14]=17 cells (5 PI)
8871 13:58:44.856705 u2DelayCellOfst[15]=21 cells (6 PI)
8872 13:58:44.863610 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8873 13:58:44.866547 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8874 13:58:44.869999 DramC Write-DBI on
8875 13:58:44.870563 ==
8876 13:58:44.873548 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 13:58:44.876450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 13:58:44.876925 ==
8879 13:58:44.877403
8880 13:58:44.877848
8881 13:58:44.879799 TX Vref Scan disable
8882 13:58:44.880338 == TX Byte 0 ==
8883 13:58:44.886905 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8884 13:58:44.887381 == TX Byte 1 ==
8885 13:58:44.889498 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8886 13:58:44.892618 DramC Write-DBI off
8887 13:58:44.893138
8888 13:58:44.893574 [DATLAT]
8889 13:58:44.896017 Freq=1600, CH1 RK1
8890 13:58:44.896430
8891 13:58:44.896825 DATLAT Default: 0xf
8892 13:58:44.899321 0, 0xFFFF, sum = 0
8893 13:58:44.899896 1, 0xFFFF, sum = 0
8894 13:58:44.903629 2, 0xFFFF, sum = 0
8895 13:58:44.904084 3, 0xFFFF, sum = 0
8896 13:58:44.906820 4, 0xFFFF, sum = 0
8897 13:58:44.907238 5, 0xFFFF, sum = 0
8898 13:58:44.910265 6, 0xFFFF, sum = 0
8899 13:58:44.912307 7, 0xFFFF, sum = 0
8900 13:58:44.912726 8, 0xFFFF, sum = 0
8901 13:58:44.916320 9, 0xFFFF, sum = 0
8902 13:58:44.916877 10, 0xFFFF, sum = 0
8903 13:58:44.919174 11, 0xFFFF, sum = 0
8904 13:58:44.919592 12, 0xFFFF, sum = 0
8905 13:58:44.922545 13, 0xFFFF, sum = 0
8906 13:58:44.922968 14, 0x0, sum = 1
8907 13:58:44.925902 15, 0x0, sum = 2
8908 13:58:44.926317 16, 0x0, sum = 3
8909 13:58:44.929289 17, 0x0, sum = 4
8910 13:58:44.929708 best_step = 15
8911 13:58:44.930033
8912 13:58:44.930338 ==
8913 13:58:44.932443 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 13:58:44.936022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 13:58:44.939518 ==
8916 13:58:44.940078 RX Vref Scan: 0
8917 13:58:44.940416
8918 13:58:44.942623 RX Vref 0 -> 0, step: 1
8919 13:58:44.943103
8920 13:58:44.946530 RX Delay 19 -> 252, step: 4
8921 13:58:44.949259 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8922 13:58:44.952868 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8923 13:58:44.956327 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8924 13:58:44.962269 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8925 13:58:44.965245 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8926 13:58:44.969123 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8927 13:58:44.971867 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8928 13:58:44.975386 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8929 13:58:44.982297 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8930 13:58:44.985107 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8931 13:58:44.988423 iDelay=195, Bit 10, Center 132 (79 ~ 186) 108
8932 13:58:44.991530 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8933 13:58:44.995018 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8934 13:58:45.001946 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8935 13:58:45.004737 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8936 13:58:45.009519 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8937 13:58:45.010138 ==
8938 13:58:45.011640 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 13:58:45.014854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 13:58:45.018148 ==
8941 13:58:45.018559 DQS Delay:
8942 13:58:45.018889 DQS0 = 0, DQS1 = 0
8943 13:58:45.021287 DQM Delay:
8944 13:58:45.021869 DQM0 = 132, DQM1 = 128
8945 13:58:45.025123 DQ Delay:
8946 13:58:45.028294 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =128
8947 13:58:45.030988 DQ4 =130, DQ5 =144, DQ6 =140, DQ7 =128
8948 13:58:45.034411 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8949 13:58:45.038182 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
8950 13:58:45.038709
8951 13:58:45.039150
8952 13:58:45.039559
8953 13:58:45.041390 [DramC_TX_OE_Calibration] TA2
8954 13:58:45.044581 Original DQ_B0 (3 6) =30, OEN = 27
8955 13:58:45.047936 Original DQ_B1 (3 6) =30, OEN = 27
8956 13:58:45.051343 24, 0x0, End_B0=24 End_B1=24
8957 13:58:45.051841 25, 0x0, End_B0=25 End_B1=25
8958 13:58:45.055122 26, 0x0, End_B0=26 End_B1=26
8959 13:58:45.057608 27, 0x0, End_B0=27 End_B1=27
8960 13:58:45.062057 28, 0x0, End_B0=28 End_B1=28
8961 13:58:45.064607 29, 0x0, End_B0=29 End_B1=29
8962 13:58:45.065072 30, 0x0, End_B0=30 End_B1=30
8963 13:58:45.067802 31, 0x4141, End_B0=30 End_B1=30
8964 13:58:45.070844 Byte0 end_step=30 best_step=27
8965 13:58:45.074228 Byte1 end_step=30 best_step=27
8966 13:58:45.077312 Byte0 TX OE(2T, 0.5T) = (3, 3)
8967 13:58:45.080891 Byte1 TX OE(2T, 0.5T) = (3, 3)
8968 13:58:45.081302
8969 13:58:45.081626
8970 13:58:45.087681 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
8971 13:58:45.090648 CH1 RK1: MR19=303, MR18=F1D
8972 13:58:45.097147 CH1_RK1: MR19=0x303, MR18=0xF1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8973 13:58:45.100777 [RxdqsGatingPostProcess] freq 1600
8974 13:58:45.103619 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8975 13:58:45.107237 best DQS0 dly(2T, 0.5T) = (1, 1)
8976 13:58:45.110176 best DQS1 dly(2T, 0.5T) = (1, 1)
8977 13:58:45.113588 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8978 13:58:45.117518 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8979 13:58:45.120271 best DQS0 dly(2T, 0.5T) = (1, 1)
8980 13:58:45.124394 best DQS1 dly(2T, 0.5T) = (1, 1)
8981 13:58:45.127269 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8982 13:58:45.130382 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8983 13:58:45.134175 Pre-setting of DQS Precalculation
8984 13:58:45.137141 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8985 13:58:45.143700 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8986 13:58:45.153509 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8987 13:58:45.154021
8988 13:58:45.154350
8989 13:58:45.157161 [Calibration Summary] 3200 Mbps
8990 13:58:45.157665 CH 0, Rank 0
8991 13:58:45.159864 SW Impedance : PASS
8992 13:58:45.160327 DUTY Scan : NO K
8993 13:58:45.163197 ZQ Calibration : PASS
8994 13:58:45.163703 Jitter Meter : NO K
8995 13:58:45.167216 CBT Training : PASS
8996 13:58:45.170166 Write leveling : PASS
8997 13:58:45.170601 RX DQS gating : PASS
8998 13:58:45.173384 RX DQ/DQS(RDDQC) : PASS
8999 13:58:45.176884 TX DQ/DQS : PASS
9000 13:58:45.177295 RX DATLAT : PASS
9001 13:58:45.180601 RX DQ/DQS(Engine): PASS
9002 13:58:45.184099 TX OE : PASS
9003 13:58:45.184508 All Pass.
9004 13:58:45.184829
9005 13:58:45.185134 CH 0, Rank 1
9006 13:58:45.186911 SW Impedance : PASS
9007 13:58:45.189668 DUTY Scan : NO K
9008 13:58:45.190171 ZQ Calibration : PASS
9009 13:58:45.193068 Jitter Meter : NO K
9010 13:58:45.196415 CBT Training : PASS
9011 13:58:45.196838 Write leveling : PASS
9012 13:58:45.199611 RX DQS gating : PASS
9013 13:58:45.203505 RX DQ/DQS(RDDQC) : PASS
9014 13:58:45.204098 TX DQ/DQS : PASS
9015 13:58:45.206629 RX DATLAT : PASS
9016 13:58:45.209379 RX DQ/DQS(Engine): PASS
9017 13:58:45.209807 TX OE : PASS
9018 13:58:45.213282 All Pass.
9019 13:58:45.213811
9020 13:58:45.214253 CH 1, Rank 0
9021 13:58:45.216469 SW Impedance : PASS
9022 13:58:45.217007 DUTY Scan : NO K
9023 13:58:45.219281 ZQ Calibration : PASS
9024 13:58:45.222408 Jitter Meter : NO K
9025 13:58:45.222836 CBT Training : PASS
9026 13:58:45.226110 Write leveling : PASS
9027 13:58:45.229100 RX DQS gating : PASS
9028 13:58:45.229527 RX DQ/DQS(RDDQC) : PASS
9029 13:58:45.232418 TX DQ/DQS : PASS
9030 13:58:45.235678 RX DATLAT : PASS
9031 13:58:45.236138 RX DQ/DQS(Engine): PASS
9032 13:58:45.239120 TX OE : PASS
9033 13:58:45.239656 All Pass.
9034 13:58:45.240042
9035 13:58:45.242765 CH 1, Rank 1
9036 13:58:45.243183 SW Impedance : PASS
9037 13:58:45.246282 DUTY Scan : NO K
9038 13:58:45.246805 ZQ Calibration : PASS
9039 13:58:45.249916 Jitter Meter : NO K
9040 13:58:45.252536 CBT Training : PASS
9041 13:58:45.253056 Write leveling : PASS
9042 13:58:45.256264 RX DQS gating : PASS
9043 13:58:45.259087 RX DQ/DQS(RDDQC) : PASS
9044 13:58:45.259608 TX DQ/DQS : PASS
9045 13:58:45.262927 RX DATLAT : PASS
9046 13:58:45.265271 RX DQ/DQS(Engine): PASS
9047 13:58:45.265700 TX OE : PASS
9048 13:58:45.268790 All Pass.
9049 13:58:45.269209
9050 13:58:45.269542 DramC Write-DBI on
9051 13:58:45.272544 PER_BANK_REFRESH: Hybrid Mode
9052 13:58:45.275282 TX_TRACKING: ON
9053 13:58:45.282274 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9054 13:58:45.292037 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9055 13:58:45.298205 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9056 13:58:45.301664 [FAST_K] Save calibration result to emmc
9057 13:58:45.304724 sync common calibartion params.
9058 13:58:45.305244 sync cbt_mode0:1, 1:1
9059 13:58:45.308329 dram_init: ddr_geometry: 2
9060 13:58:45.311703 dram_init: ddr_geometry: 2
9061 13:58:45.314916 dram_init: ddr_geometry: 2
9062 13:58:45.315341 0:dram_rank_size:100000000
9063 13:58:45.317821 1:dram_rank_size:100000000
9064 13:58:45.324823 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9065 13:58:45.325252 DFS_SHUFFLE_HW_MODE: ON
9066 13:58:45.331653 dramc_set_vcore_voltage set vcore to 725000
9067 13:58:45.332190 Read voltage for 1600, 0
9068 13:58:45.334891 Vio18 = 0
9069 13:58:45.335321 Vcore = 725000
9070 13:58:45.335749 Vdram = 0
9071 13:58:45.338197 Vddq = 0
9072 13:58:45.338620 Vmddr = 0
9073 13:58:45.341292 switch to 3200 Mbps bootup
9074 13:58:45.341818 [DramcRunTimeConfig]
9075 13:58:45.342260 PHYPLL
9076 13:58:45.344564 DPM_CONTROL_AFTERK: ON
9077 13:58:45.348018 PER_BANK_REFRESH: ON
9078 13:58:45.348547 REFRESH_OVERHEAD_REDUCTION: ON
9079 13:58:45.351207 CMD_PICG_NEW_MODE: OFF
9080 13:58:45.354647 XRTWTW_NEW_MODE: ON
9081 13:58:45.355171 XRTRTR_NEW_MODE: ON
9082 13:58:45.357214 TX_TRACKING: ON
9083 13:58:45.357640 RDSEL_TRACKING: OFF
9084 13:58:45.360958 DQS Precalculation for DVFS: ON
9085 13:58:45.361489 RX_TRACKING: OFF
9086 13:58:45.364247 HW_GATING DBG: ON
9087 13:58:45.367524 ZQCS_ENABLE_LP4: ON
9088 13:58:45.367981 RX_PICG_NEW_MODE: ON
9089 13:58:45.370765 TX_PICG_NEW_MODE: ON
9090 13:58:45.371198 ENABLE_RX_DCM_DPHY: ON
9091 13:58:45.374116 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9092 13:58:45.377805 DUMMY_READ_FOR_TRACKING: OFF
9093 13:58:45.380794 !!! SPM_CONTROL_AFTERK: OFF
9094 13:58:45.383803 !!! SPM could not control APHY
9095 13:58:45.384264 IMPEDANCE_TRACKING: ON
9096 13:58:45.387503 TEMP_SENSOR: ON
9097 13:58:45.387962 HW_SAVE_FOR_SR: OFF
9098 13:58:45.390800 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9099 13:58:45.393955 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9100 13:58:45.397305 Read ODT Tracking: ON
9101 13:58:45.400669 Refresh Rate DeBounce: ON
9102 13:58:45.401088 DFS_NO_QUEUE_FLUSH: ON
9103 13:58:45.403691 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9104 13:58:45.407561 ENABLE_DFS_RUNTIME_MRW: OFF
9105 13:58:45.410654 DDR_RESERVE_NEW_MODE: ON
9106 13:58:45.411080 MR_CBT_SWITCH_FREQ: ON
9107 13:58:45.413996 =========================
9108 13:58:45.432292 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9109 13:58:45.435266 dram_init: ddr_geometry: 2
9110 13:58:45.454342 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9111 13:58:45.457658 dram_init: dram init end (result: 0)
9112 13:58:45.463996 DRAM-K: Full calibration passed in 24398 msecs
9113 13:58:45.467053 MRC: failed to locate region type 0.
9114 13:58:45.467521 DRAM rank0 size:0x100000000,
9115 13:58:45.470672 DRAM rank1 size=0x100000000
9116 13:58:45.480665 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9117 13:58:45.487483 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9118 13:58:45.494410 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9119 13:58:45.500265 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9120 13:58:45.503488 DRAM rank0 size:0x100000000,
9121 13:58:45.507216 DRAM rank1 size=0x100000000
9122 13:58:45.507790 CBMEM:
9123 13:58:45.510451 IMD: root @ 0xfffff000 254 entries.
9124 13:58:45.513892 IMD: root @ 0xffffec00 62 entries.
9125 13:58:45.516487 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9126 13:58:45.523178 WARNING: RO_VPD is uninitialized or empty.
9127 13:58:45.526667 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9128 13:58:45.534162 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9129 13:58:45.546701 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9130 13:58:45.558115 BS: romstage times (exec / console): total (unknown) / 23930 ms
9131 13:58:45.558658
9132 13:58:45.559103
9133 13:58:45.567694 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9134 13:58:45.571350 ARM64: Exception handlers installed.
9135 13:58:45.575264 ARM64: Testing exception
9136 13:58:45.578446 ARM64: Done test exception
9137 13:58:45.579057 Enumerating buses...
9138 13:58:45.581732 Show all devs... Before device enumeration.
9139 13:58:45.584419 Root Device: enabled 1
9140 13:58:45.588603 CPU_CLUSTER: 0: enabled 1
9141 13:58:45.589093 CPU: 00: enabled 1
9142 13:58:45.591119 Compare with tree...
9143 13:58:45.591586 Root Device: enabled 1
9144 13:58:45.594481 CPU_CLUSTER: 0: enabled 1
9145 13:58:45.597850 CPU: 00: enabled 1
9146 13:58:45.598321 Root Device scanning...
9147 13:58:45.601754 scan_static_bus for Root Device
9148 13:58:45.604751 CPU_CLUSTER: 0 enabled
9149 13:58:45.607396 scan_static_bus for Root Device done
9150 13:58:45.610857 scan_bus: bus Root Device finished in 8 msecs
9151 13:58:45.611280 done
9152 13:58:45.617965 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9153 13:58:45.620715 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9154 13:58:45.627122 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9155 13:58:45.630600 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9156 13:58:45.633913 Allocating resources...
9157 13:58:45.637186 Reading resources...
9158 13:58:45.640650 Root Device read_resources bus 0 link: 0
9159 13:58:45.643588 DRAM rank0 size:0x100000000,
9160 13:58:45.644048 DRAM rank1 size=0x100000000
9161 13:58:45.650387 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9162 13:58:45.650944 CPU: 00 missing read_resources
9163 13:58:45.657259 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9164 13:58:45.660182 Root Device read_resources bus 0 link: 0 done
9165 13:58:45.664046 Done reading resources.
9166 13:58:45.666811 Show resources in subtree (Root Device)...After reading.
9167 13:58:45.669816 Root Device child on link 0 CPU_CLUSTER: 0
9168 13:58:45.673436 CPU_CLUSTER: 0 child on link 0 CPU: 00
9169 13:58:45.683572 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9170 13:58:45.684176 CPU: 00
9171 13:58:45.689389 Root Device assign_resources, bus 0 link: 0
9172 13:58:45.692878 CPU_CLUSTER: 0 missing set_resources
9173 13:58:45.696839 Root Device assign_resources, bus 0 link: 0 done
9174 13:58:45.699265 Done setting resources.
9175 13:58:45.702458 Show resources in subtree (Root Device)...After assigning values.
9176 13:58:45.706289 Root Device child on link 0 CPU_CLUSTER: 0
9177 13:58:45.712796 CPU_CLUSTER: 0 child on link 0 CPU: 00
9178 13:58:45.719094 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9179 13:58:45.722837 CPU: 00
9180 13:58:45.723425 Done allocating resources.
9181 13:58:45.729369 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9182 13:58:45.729878 Enabling resources...
9183 13:58:45.732719 done.
9184 13:58:45.735830 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9185 13:58:45.739368 Initializing devices...
9186 13:58:45.739781 Root Device init
9187 13:58:45.742354 init hardware done!
9188 13:58:45.742866 0x00000018: ctrlr->caps
9189 13:58:45.745645 52.000 MHz: ctrlr->f_max
9190 13:58:45.748959 0.400 MHz: ctrlr->f_min
9191 13:58:45.752143 0x40ff8080: ctrlr->voltages
9192 13:58:45.752616 sclk: 390625
9193 13:58:45.752977 Bus Width = 1
9194 13:58:45.755395 sclk: 390625
9195 13:58:45.755882 Bus Width = 1
9196 13:58:45.759180 Early init status = 3
9197 13:58:45.762102 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9198 13:58:45.766339 in-header: 03 fc 00 00 01 00 00 00
9199 13:58:45.769997 in-data: 00
9200 13:58:45.772973 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9201 13:58:45.779292 in-header: 03 fd 00 00 00 00 00 00
9202 13:58:45.781761 in-data:
9203 13:58:45.785550 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9204 13:58:45.790204 in-header: 03 fc 00 00 01 00 00 00
9205 13:58:45.793454 in-data: 00
9206 13:58:45.796267 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9207 13:58:45.801821 in-header: 03 fd 00 00 00 00 00 00
9208 13:58:45.805315 in-data:
9209 13:58:45.808414 [SSUSB] Setting up USB HOST controller...
9210 13:58:45.812126 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9211 13:58:45.814912 [SSUSB] phy power-on done.
9212 13:58:45.818910 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9213 13:58:45.825537 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9214 13:58:45.828049 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9215 13:58:45.834828 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9216 13:58:45.841764 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9217 13:58:45.848802 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9218 13:58:45.854849 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9219 13:58:45.861600 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9220 13:58:45.864510 SPM: binary array size = 0x9dc
9221 13:58:45.867979 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9222 13:58:45.875121 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9223 13:58:45.881397 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9224 13:58:45.887485 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9225 13:58:45.891018 configure_display: Starting display init
9226 13:58:45.925015 anx7625_power_on_init: Init interface.
9227 13:58:45.928566 anx7625_disable_pd_protocol: Disabled PD feature.
9228 13:58:45.932202 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9229 13:58:45.959765 anx7625_start_dp_work: Secure OCM version=00
9230 13:58:45.963684 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9231 13:58:45.977907 sp_tx_get_edid_block: EDID Block = 1
9232 13:58:46.080090 Extracted contents:
9233 13:58:46.083729 header: 00 ff ff ff ff ff ff 00
9234 13:58:46.086936 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9235 13:58:46.090139 version: 01 04
9236 13:58:46.093713 basic params: 95 1f 11 78 0a
9237 13:58:46.096747 chroma info: 76 90 94 55 54 90 27 21 50 54
9238 13:58:46.100011 established: 00 00 00
9239 13:58:46.106824 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9240 13:58:46.112983 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9241 13:58:46.116844 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9242 13:58:46.124175 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9243 13:58:46.129918 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9244 13:58:46.133130 extensions: 00
9245 13:58:46.133594 checksum: fb
9246 13:58:46.133959
9247 13:58:46.139995 Manufacturer: IVO Model 57d Serial Number 0
9248 13:58:46.140553 Made week 0 of 2020
9249 13:58:46.143478 EDID version: 1.4
9250 13:58:46.144085 Digital display
9251 13:58:46.146239 6 bits per primary color channel
9252 13:58:46.146937 DisplayPort interface
9253 13:58:46.149589 Maximum image size: 31 cm x 17 cm
9254 13:58:46.153258 Gamma: 220%
9255 13:58:46.153804 Check DPMS levels
9256 13:58:46.159479 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9257 13:58:46.162449 First detailed timing is preferred timing
9258 13:58:46.166115 Established timings supported:
9259 13:58:46.166664 Standard timings supported:
9260 13:58:46.169292 Detailed timings
9261 13:58:46.172381 Hex of detail: 383680a07038204018303c0035ae10000019
9262 13:58:46.179435 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9263 13:58:46.182730 0780 0798 07c8 0820 hborder 0
9264 13:58:46.185802 0438 043b 0447 0458 vborder 0
9265 13:58:46.188799 -hsync -vsync
9266 13:58:46.189269 Did detailed timing
9267 13:58:46.195519 Hex of detail: 000000000000000000000000000000000000
9268 13:58:46.199552 Manufacturer-specified data, tag 0
9269 13:58:46.202189 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9270 13:58:46.205647 ASCII string: InfoVision
9271 13:58:46.208955 Hex of detail: 000000fe00523134304e574635205248200a
9272 13:58:46.212828 ASCII string: R140NWF5 RH
9273 13:58:46.213386 Checksum
9274 13:58:46.215396 Checksum: 0xfb (valid)
9275 13:58:46.219260 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9276 13:58:46.222500 DSI data_rate: 832800000 bps
9277 13:58:46.228423 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9278 13:58:46.232064 anx7625_parse_edid: pixelclock(138800).
9279 13:58:46.234793 hactive(1920), hsync(48), hfp(24), hbp(88)
9280 13:58:46.238229 vactive(1080), vsync(12), vfp(3), vbp(17)
9281 13:58:46.241760 anx7625_dsi_config: config dsi.
9282 13:58:46.248366 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9283 13:58:46.262599 anx7625_dsi_config: success to config DSI
9284 13:58:46.265611 anx7625_dp_start: MIPI phy setup OK.
9285 13:58:46.268765 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9286 13:58:46.272541 mtk_ddp_mode_set invalid vrefresh 60
9287 13:58:46.275543 main_disp_path_setup
9288 13:58:46.276056 ovl_layer_smi_id_en
9289 13:58:46.279046 ovl_layer_smi_id_en
9290 13:58:46.279599 ccorr_config
9291 13:58:46.280025 aal_config
9292 13:58:46.282165 gamma_config
9293 13:58:46.282619 postmask_config
9294 13:58:46.285227 dither_config
9295 13:58:46.288803 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9296 13:58:46.295445 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9297 13:58:46.298721 Root Device init finished in 555 msecs
9298 13:58:46.301878 CPU_CLUSTER: 0 init
9299 13:58:46.308566 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9300 13:58:46.315508 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9301 13:58:46.316061 APU_MBOX 0x190000b0 = 0x10001
9302 13:58:46.318328 APU_MBOX 0x190001b0 = 0x10001
9303 13:58:46.321846 APU_MBOX 0x190005b0 = 0x10001
9304 13:58:46.325282 APU_MBOX 0x190006b0 = 0x10001
9305 13:58:46.331741 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9306 13:58:46.340973 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9307 13:58:46.353424 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9308 13:58:46.360238 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9309 13:58:46.372042 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9310 13:58:46.381403 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9311 13:58:46.384812 CPU_CLUSTER: 0 init finished in 81 msecs
9312 13:58:46.387690 Devices initialized
9313 13:58:46.390772 Show all devs... After init.
9314 13:58:46.391183 Root Device: enabled 1
9315 13:58:46.394787 CPU_CLUSTER: 0: enabled 1
9316 13:58:46.397813 CPU: 00: enabled 1
9317 13:58:46.400865 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9318 13:58:46.404196 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9319 13:58:46.407801 ELOG: NV offset 0x57f000 size 0x1000
9320 13:58:46.414283 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9321 13:58:46.421164 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9322 13:58:46.424016 ELOG: Event(17) added with size 13 at 2023-08-28 13:58:47 UTC
9323 13:58:46.430461 out: cmd=0x121: 03 db 21 01 00 00 00 00
9324 13:58:46.433883 in-header: 03 4b 00 00 2c 00 00 00
9325 13:58:46.443776 in-data: 14 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9326 13:58:46.450244 ELOG: Event(A1) added with size 10 at 2023-08-28 13:58:47 UTC
9327 13:58:46.456848 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9328 13:58:46.463895 ELOG: Event(A0) added with size 9 at 2023-08-28 13:58:47 UTC
9329 13:58:46.466854 elog_add_boot_reason: Logged dev mode boot
9330 13:58:46.473542 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9331 13:58:46.474223 Finalize devices...
9332 13:58:46.476847 Devices finalized
9333 13:58:46.480396 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9334 13:58:46.484379 Writing coreboot table at 0xffe64000
9335 13:58:46.486614 0. 000000000010a000-0000000000113fff: RAMSTAGE
9336 13:58:46.493227 1. 0000000040000000-00000000400fffff: RAM
9337 13:58:46.496391 2. 0000000040100000-000000004032afff: RAMSTAGE
9338 13:58:46.500389 3. 000000004032b000-00000000545fffff: RAM
9339 13:58:46.503260 4. 0000000054600000-000000005465ffff: BL31
9340 13:58:46.506732 5. 0000000054660000-00000000ffe63fff: RAM
9341 13:58:46.513171 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9342 13:58:46.516004 7. 0000000100000000-000000023fffffff: RAM
9343 13:58:46.519714 Passing 5 GPIOs to payload:
9344 13:58:46.522936 NAME | PORT | POLARITY | VALUE
9345 13:58:46.529492 EC in RW | 0x000000aa | low | undefined
9346 13:58:46.532817 EC interrupt | 0x00000005 | low | undefined
9347 13:58:46.539597 TPM interrupt | 0x000000ab | high | undefined
9348 13:58:46.542844 SD card detect | 0x00000011 | high | undefined
9349 13:58:46.546235 speaker enable | 0x00000093 | high | undefined
9350 13:58:46.550116 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9351 13:58:46.552325 in-header: 03 f9 00 00 02 00 00 00
9352 13:58:46.555952 in-data: 02 00
9353 13:58:46.559470 ADC[4]: Raw value=903694 ID=7
9354 13:58:46.562903 ADC[3]: Raw value=213546 ID=1
9355 13:58:46.563413 RAM Code: 0x71
9356 13:58:46.566338 ADC[6]: Raw value=75000 ID=0
9357 13:58:46.569054 ADC[5]: Raw value=213546 ID=1
9358 13:58:46.569475 SKU Code: 0x1
9359 13:58:46.575817 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 955a
9360 13:58:46.576361 coreboot table: 964 bytes.
9361 13:58:46.579104 IMD ROOT 0. 0xfffff000 0x00001000
9362 13:58:46.582205 IMD SMALL 1. 0xffffe000 0x00001000
9363 13:58:46.586532 RO MCACHE 2. 0xffffc000 0x00001104
9364 13:58:46.588817 CONSOLE 3. 0xfff7c000 0x00080000
9365 13:58:46.592479 FMAP 4. 0xfff7b000 0x00000452
9366 13:58:46.595569 TIME STAMP 5. 0xfff7a000 0x00000910
9367 13:58:46.599125 VBOOT WORK 6. 0xfff66000 0x00014000
9368 13:58:46.601911 RAMOOPS 7. 0xffe66000 0x00100000
9369 13:58:46.605431 COREBOOT 8. 0xffe64000 0x00002000
9370 13:58:46.608292 IMD small region:
9371 13:58:46.612037 IMD ROOT 0. 0xffffec00 0x00000400
9372 13:58:46.615180 VPD 1. 0xffffeb80 0x0000006c
9373 13:58:46.618313 MMC STATUS 2. 0xffffeb60 0x00000004
9374 13:58:46.625191 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9375 13:58:46.625623 Probing TPM: done!
9376 13:58:46.631682 Connected to device vid:did:rid of 1ae0:0028:00
9377 13:58:46.638766 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9378 13:58:46.641876 Initialized TPM device CR50 revision 0
9379 13:58:46.645188 Checking cr50 for pending updates
9380 13:58:46.650879 Reading cr50 TPM mode
9381 13:58:46.659555 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9382 13:58:46.666114 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9383 13:58:46.706315 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9384 13:58:46.709634 Checking segment from ROM address 0x40100000
9385 13:58:46.713350 Checking segment from ROM address 0x4010001c
9386 13:58:46.719635 Loading segment from ROM address 0x40100000
9387 13:58:46.720195 code (compression=0)
9388 13:58:46.729648 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9389 13:58:46.736028 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9390 13:58:46.736479 it's not compressed!
9391 13:58:46.742777 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9392 13:58:46.746121 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9393 13:58:46.767054 Loading segment from ROM address 0x4010001c
9394 13:58:46.767597 Entry Point 0x80000000
9395 13:58:46.770025 Loaded segments
9396 13:58:46.773928 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9397 13:58:46.780044 Jumping to boot code at 0x80000000(0xffe64000)
9398 13:58:46.786771 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9399 13:58:46.793143 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9400 13:58:46.801191 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9401 13:58:46.805387 Checking segment from ROM address 0x40100000
9402 13:58:46.807597 Checking segment from ROM address 0x4010001c
9403 13:58:46.814317 Loading segment from ROM address 0x40100000
9404 13:58:46.814884 code (compression=1)
9405 13:58:46.820913 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9406 13:58:46.830801 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9407 13:58:46.831370 using LZMA
9408 13:58:46.839857 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9409 13:58:46.846284 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9410 13:58:46.849558 Loading segment from ROM address 0x4010001c
9411 13:58:46.850144 Entry Point 0x54601000
9412 13:58:46.852832 Loaded segments
9413 13:58:46.856527 NOTICE: MT8192 bl31_setup
9414 13:58:46.863324 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9415 13:58:46.867088 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9416 13:58:46.869674 WARNING: region 0:
9417 13:58:46.873124 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9418 13:58:46.873688 WARNING: region 1:
9419 13:58:46.879622 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9420 13:58:46.883245 WARNING: region 2:
9421 13:58:46.886486 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9422 13:58:46.889756 WARNING: region 3:
9423 13:58:46.892923 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9424 13:58:46.897251 WARNING: region 4:
9425 13:58:46.903423 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9426 13:58:46.903887 WARNING: region 5:
9427 13:58:46.906888 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9428 13:58:46.909769 WARNING: region 6:
9429 13:58:46.912760 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9430 13:58:46.916530 WARNING: region 7:
9431 13:58:46.919192 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9432 13:58:46.926069 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9433 13:58:46.929589 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9434 13:58:46.933102 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9435 13:58:46.939615 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9436 13:58:46.942723 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9437 13:58:46.946348 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9438 13:58:46.952872 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9439 13:58:46.956085 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9440 13:58:46.962871 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9441 13:58:46.965785 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9442 13:58:46.969368 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9443 13:58:46.976008 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9444 13:58:46.979268 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9445 13:58:46.985515 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9446 13:58:46.988808 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9447 13:58:46.992633 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9448 13:58:46.999590 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9449 13:58:47.002282 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9450 13:58:47.009298 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9451 13:58:47.012637 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9452 13:58:47.015442 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9453 13:58:47.022182 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9454 13:58:47.025440 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9455 13:58:47.029625 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9456 13:58:47.035829 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9457 13:58:47.038778 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9458 13:58:47.045851 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9459 13:58:47.048468 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9460 13:58:47.052053 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9461 13:58:47.058940 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9462 13:58:47.062141 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9463 13:58:47.069092 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9464 13:58:47.072284 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9465 13:58:47.075256 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9466 13:58:47.078585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9467 13:58:47.085496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9468 13:58:47.088547 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9469 13:58:47.091592 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9470 13:58:47.095438 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9471 13:58:47.102030 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9472 13:58:47.105737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9473 13:58:47.108182 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9474 13:58:47.111973 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9475 13:58:47.118212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9476 13:58:47.122559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9477 13:58:47.125241 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9478 13:58:47.128811 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9479 13:58:47.135468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9480 13:58:47.138121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9481 13:58:47.145175 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9482 13:58:47.148359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9483 13:58:47.151962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9484 13:58:47.158395 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9485 13:58:47.162444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9486 13:58:47.168819 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9487 13:58:47.172273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9488 13:58:47.178277 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9489 13:58:47.182097 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9490 13:58:47.185557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9491 13:58:47.192024 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9492 13:58:47.195088 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9493 13:58:47.201374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9494 13:58:47.205378 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9495 13:58:47.211842 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9496 13:58:47.214861 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9497 13:58:47.222024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9498 13:58:47.224865 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9499 13:58:47.228797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9500 13:58:47.234404 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9501 13:58:47.237547 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9502 13:58:47.244615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9503 13:58:47.248134 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9504 13:58:47.254739 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9505 13:58:47.257760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9506 13:58:47.261489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9507 13:58:47.268710 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9508 13:58:47.271734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9509 13:58:47.277923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9510 13:58:47.281589 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9511 13:58:47.288304 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9512 13:58:47.291353 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9513 13:58:47.298039 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9514 13:58:47.300983 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9515 13:58:47.304498 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9516 13:58:47.311782 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9517 13:58:47.314573 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9518 13:58:47.321481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9519 13:58:47.324795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9520 13:58:47.328055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9521 13:58:47.334886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9522 13:58:47.338401 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9523 13:58:47.344991 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9524 13:58:47.348545 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9525 13:58:47.355177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9526 13:58:47.357944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9527 13:58:47.364535 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9528 13:58:47.367656 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9529 13:58:47.371138 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9530 13:58:47.375026 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9531 13:58:47.381457 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9532 13:58:47.384596 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9533 13:58:47.387727 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9534 13:58:47.394491 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9535 13:58:47.398176 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9536 13:58:47.401404 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9537 13:58:47.408220 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9538 13:58:47.411557 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9539 13:58:47.418042 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9540 13:58:47.421250 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9541 13:58:47.424741 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9542 13:58:47.431305 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9543 13:58:47.434194 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9544 13:58:47.441018 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9545 13:58:47.444579 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9546 13:58:47.447551 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9547 13:58:47.454609 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9548 13:58:47.457454 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9549 13:58:47.460888 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9550 13:58:47.467673 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9551 13:58:47.471237 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9552 13:58:47.473953 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9553 13:58:47.477371 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9554 13:58:47.483990 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9555 13:58:47.487714 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9556 13:58:47.491062 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9557 13:58:47.497708 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9558 13:58:47.500626 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9559 13:58:47.507523 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9560 13:58:47.510932 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9561 13:58:47.514155 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9562 13:58:47.520646 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9563 13:58:47.524070 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9564 13:58:47.530979 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9565 13:58:47.533838 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9566 13:58:47.536909 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9567 13:58:47.543811 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9568 13:58:47.547212 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9569 13:58:47.550314 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9570 13:58:47.557246 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9571 13:58:47.560582 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9572 13:58:47.567366 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9573 13:58:47.571329 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9574 13:58:47.574047 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9575 13:58:47.580626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9576 13:58:47.583825 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9577 13:58:47.587113 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9578 13:58:47.594121 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9579 13:58:47.597358 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9580 13:58:47.603808 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9581 13:58:47.607763 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9582 13:58:47.610403 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9583 13:58:47.617382 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9584 13:58:47.620232 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9585 13:58:47.627089 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9586 13:58:47.630296 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9587 13:58:47.633863 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9588 13:58:47.640208 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9589 13:58:47.643516 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9590 13:58:47.650751 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9591 13:58:47.653679 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9592 13:58:47.656965 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9593 13:58:47.663648 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9594 13:58:47.667037 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9595 13:58:47.673693 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9596 13:58:47.677022 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9597 13:58:47.679955 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9598 13:58:47.686867 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9599 13:58:47.690185 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9600 13:58:47.696611 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9601 13:58:47.700336 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9602 13:58:47.703135 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9603 13:58:47.709795 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9604 13:58:47.712793 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9605 13:58:47.719412 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9606 13:58:47.723831 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9607 13:58:47.726022 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9608 13:58:47.732863 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9609 13:58:47.736896 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9610 13:58:47.742772 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9611 13:58:47.746050 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9612 13:58:47.749546 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9613 13:58:47.755694 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9614 13:58:47.759337 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9615 13:58:47.765989 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9616 13:58:47.769770 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9617 13:58:47.772474 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9618 13:58:47.779394 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9619 13:58:47.782255 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9620 13:58:47.789089 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9621 13:58:47.792012 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9622 13:58:47.795458 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9623 13:58:47.802108 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9624 13:58:47.805316 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9625 13:58:47.812436 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9626 13:58:47.815745 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9627 13:58:47.822723 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9628 13:58:47.825114 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9629 13:58:47.828604 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9630 13:58:47.835354 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9631 13:58:47.838328 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9632 13:58:47.845468 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9633 13:58:47.848552 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9634 13:58:47.855586 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9635 13:58:47.858573 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9636 13:58:47.861760 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9637 13:58:47.868427 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9638 13:58:47.871547 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9639 13:58:47.878659 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9640 13:58:47.881350 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9641 13:58:47.884670 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9642 13:58:47.891502 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9643 13:58:47.894962 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9644 13:58:47.902402 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9645 13:58:47.904546 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9646 13:58:47.911104 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9647 13:58:47.914874 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9648 13:58:47.917731 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9649 13:58:47.924527 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9650 13:58:47.928007 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9651 13:58:47.934458 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9652 13:58:47.938025 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9653 13:58:47.941185 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9654 13:58:47.947368 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9655 13:58:47.950896 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9656 13:58:47.957489 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9657 13:58:47.961288 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9658 13:58:47.967695 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9659 13:58:47.971223 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9660 13:58:47.973848 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9661 13:58:47.980519 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9662 13:58:47.983647 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9663 13:58:47.987091 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9664 13:58:47.990702 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9665 13:58:47.997302 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9666 13:58:48.000496 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9667 13:58:48.003713 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9668 13:58:48.010286 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9669 13:58:48.014361 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9670 13:58:48.017567 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9671 13:58:48.023750 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9672 13:58:48.026943 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9673 13:58:48.033248 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9674 13:58:48.036364 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9675 13:58:48.039519 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9676 13:58:48.046663 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9677 13:58:48.049658 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9678 13:58:48.056173 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9679 13:58:48.059644 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9680 13:58:48.063023 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9681 13:58:48.069408 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9682 13:58:48.072883 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9683 13:58:48.079732 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9684 13:58:48.083138 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9685 13:58:48.086234 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9686 13:58:48.092929 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9687 13:58:48.095398 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9688 13:58:48.098528 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9689 13:58:48.105901 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9690 13:58:48.108617 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9691 13:58:48.115520 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9692 13:58:48.118712 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9693 13:58:48.121957 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9694 13:58:48.128950 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9695 13:58:48.132010 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9696 13:58:48.135146 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9697 13:58:48.141467 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9698 13:58:48.144697 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9699 13:58:48.151591 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9700 13:58:48.154870 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9701 13:58:48.158065 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9702 13:58:48.161264 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9703 13:58:48.168380 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9704 13:58:48.171477 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9705 13:58:48.174532 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9706 13:58:48.178008 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9707 13:58:48.184240 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9708 13:58:48.187467 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9709 13:58:48.191437 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9710 13:58:48.194450 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9711 13:58:48.201083 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9712 13:58:48.204461 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9713 13:58:48.207720 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9714 13:58:48.214681 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9715 13:58:48.217751 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9716 13:58:48.224411 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9717 13:58:48.227774 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9718 13:58:48.230633 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9719 13:58:48.237343 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9720 13:58:48.240406 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9721 13:58:48.247509 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9722 13:58:48.251115 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9723 13:58:48.254185 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9724 13:58:48.260643 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9725 13:58:48.263796 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9726 13:58:48.270915 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9727 13:58:48.274039 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9728 13:58:48.280107 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9729 13:58:48.283511 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9730 13:58:48.286809 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9731 13:58:48.293886 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9732 13:58:48.296665 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9733 13:58:48.303240 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9734 13:58:48.306309 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9735 13:58:48.312810 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9736 13:58:48.316160 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9737 13:58:48.319612 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9738 13:58:48.326076 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9739 13:58:48.329719 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9740 13:58:48.335795 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9741 13:58:48.339219 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9742 13:58:48.346033 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9743 13:58:48.349071 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9744 13:58:48.352618 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9745 13:58:48.359247 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9746 13:58:48.362676 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9747 13:58:48.368930 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9748 13:58:48.372583 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9749 13:58:48.375659 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9750 13:58:48.381846 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9751 13:58:48.385330 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9752 13:58:48.391867 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9753 13:58:48.395188 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9754 13:58:48.398553 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9755 13:58:48.405058 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9756 13:58:48.408288 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9757 13:58:48.415234 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9758 13:58:48.418888 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9759 13:58:48.424651 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9760 13:58:48.428677 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9761 13:58:48.431856 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9762 13:58:48.438157 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9763 13:58:48.441281 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9764 13:58:48.448570 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9765 13:58:48.451075 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9766 13:58:48.458264 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9767 13:58:48.461266 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9768 13:58:48.464444 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9769 13:58:48.471205 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9770 13:58:48.474695 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9771 13:58:48.480938 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9772 13:58:48.484006 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9773 13:58:48.490319 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9774 13:58:48.493925 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9775 13:58:48.497167 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9776 13:58:48.503591 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9777 13:58:48.507417 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9778 13:58:48.514327 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9779 13:58:48.516699 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9780 13:58:48.520226 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9781 13:58:48.526819 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9782 13:58:48.530149 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9783 13:58:48.536541 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9784 13:58:48.540144 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9785 13:58:48.543444 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9786 13:58:48.550616 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9787 13:58:48.553793 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9788 13:58:48.560151 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9789 13:58:48.563089 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9790 13:58:48.569803 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9791 13:58:48.573189 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9792 13:58:48.580127 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9793 13:58:48.582885 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9794 13:58:48.586062 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9795 13:58:48.592468 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9796 13:58:48.596500 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9797 13:58:48.602881 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9798 13:58:48.606551 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9799 13:58:48.612473 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9800 13:58:48.615630 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9801 13:58:48.622643 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9802 13:58:48.625522 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9803 13:58:48.628898 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9804 13:58:48.636085 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9805 13:58:48.639177 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9806 13:58:48.645208 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9807 13:58:48.649273 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9808 13:58:48.655640 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9809 13:58:48.658784 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9810 13:58:48.665442 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9811 13:58:48.668966 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9812 13:58:48.675228 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9813 13:58:48.678804 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9814 13:58:48.681861 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9815 13:58:48.688120 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9816 13:58:48.692276 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9817 13:58:48.698018 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9818 13:58:48.701491 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9819 13:58:48.708280 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9820 13:58:48.711153 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9821 13:58:48.718076 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9822 13:58:48.721310 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9823 13:58:48.727856 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9824 13:58:48.730976 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9825 13:58:48.734638 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9826 13:58:48.740727 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9827 13:58:48.744778 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9828 13:58:48.750826 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9829 13:58:48.754936 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9830 13:58:48.760423 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9831 13:58:48.764297 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9832 13:58:48.771080 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9833 13:58:48.773472 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9834 13:58:48.777183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9835 13:58:48.783581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9836 13:58:48.786992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9837 13:58:48.793895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9838 13:58:48.796825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9839 13:58:48.803754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9840 13:58:48.807322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9841 13:58:48.814060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9842 13:58:48.816819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9843 13:58:48.823655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9844 13:58:48.826630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9845 13:58:48.833291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9846 13:58:48.836442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9847 13:58:48.843100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9848 13:58:48.846290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9849 13:58:48.849628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9850 13:58:48.856891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9851 13:58:48.859535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9852 13:58:48.866259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9853 13:58:48.869492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9854 13:58:48.876034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9855 13:58:48.879497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9856 13:58:48.886409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9857 13:58:48.892721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9858 13:58:48.895756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9859 13:58:48.902269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9860 13:58:48.905761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9861 13:58:48.912287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9862 13:58:48.915787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9863 13:58:48.922035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9864 13:58:48.926360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9865 13:58:48.932137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9866 13:58:48.935800 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9867 13:58:48.938355 INFO: [APUAPC] vio 0
9868 13:58:48.941928 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9869 13:58:48.948366 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9870 13:58:48.952013 INFO: [APUAPC] D0_APC_0: 0x400510
9871 13:58:48.952524 INFO: [APUAPC] D0_APC_1: 0x0
9872 13:58:48.954787 INFO: [APUAPC] D0_APC_2: 0x1540
9873 13:58:48.958549 INFO: [APUAPC] D0_APC_3: 0x0
9874 13:58:48.961830 INFO: [APUAPC] D1_APC_0: 0xffffffff
9875 13:58:48.964646 INFO: [APUAPC] D1_APC_1: 0xffffffff
9876 13:58:48.968301 INFO: [APUAPC] D1_APC_2: 0x3fffff
9877 13:58:48.971778 INFO: [APUAPC] D1_APC_3: 0x0
9878 13:58:48.975478 INFO: [APUAPC] D2_APC_0: 0xffffffff
9879 13:58:48.978107 INFO: [APUAPC] D2_APC_1: 0xffffffff
9880 13:58:48.981255 INFO: [APUAPC] D2_APC_2: 0x3fffff
9881 13:58:48.984848 INFO: [APUAPC] D2_APC_3: 0x0
9882 13:58:48.988394 INFO: [APUAPC] D3_APC_0: 0xffffffff
9883 13:58:48.991432 INFO: [APUAPC] D3_APC_1: 0xffffffff
9884 13:58:48.994427 INFO: [APUAPC] D3_APC_2: 0x3fffff
9885 13:58:48.998217 INFO: [APUAPC] D3_APC_3: 0x0
9886 13:58:49.000894 INFO: [APUAPC] D4_APC_0: 0xffffffff
9887 13:58:49.004631 INFO: [APUAPC] D4_APC_1: 0xffffffff
9888 13:58:49.007618 INFO: [APUAPC] D4_APC_2: 0x3fffff
9889 13:58:49.011296 INFO: [APUAPC] D4_APC_3: 0x0
9890 13:58:49.014225 INFO: [APUAPC] D5_APC_0: 0xffffffff
9891 13:58:49.017728 INFO: [APUAPC] D5_APC_1: 0xffffffff
9892 13:58:49.021436 INFO: [APUAPC] D5_APC_2: 0x3fffff
9893 13:58:49.024788 INFO: [APUAPC] D5_APC_3: 0x0
9894 13:58:49.028051 INFO: [APUAPC] D6_APC_0: 0xffffffff
9895 13:58:49.031145 INFO: [APUAPC] D6_APC_1: 0xffffffff
9896 13:58:49.034132 INFO: [APUAPC] D6_APC_2: 0x3fffff
9897 13:58:49.037955 INFO: [APUAPC] D6_APC_3: 0x0
9898 13:58:49.040842 INFO: [APUAPC] D7_APC_0: 0xffffffff
9899 13:58:49.043997 INFO: [APUAPC] D7_APC_1: 0xffffffff
9900 13:58:49.047566 INFO: [APUAPC] D7_APC_2: 0x3fffff
9901 13:58:49.050869 INFO: [APUAPC] D7_APC_3: 0x0
9902 13:58:49.053986 INFO: [APUAPC] D8_APC_0: 0xffffffff
9903 13:58:49.057275 INFO: [APUAPC] D8_APC_1: 0xffffffff
9904 13:58:49.060512 INFO: [APUAPC] D8_APC_2: 0x3fffff
9905 13:58:49.064382 INFO: [APUAPC] D8_APC_3: 0x0
9906 13:58:49.067238 INFO: [APUAPC] D9_APC_0: 0xffffffff
9907 13:58:49.070637 INFO: [APUAPC] D9_APC_1: 0xffffffff
9908 13:58:49.074252 INFO: [APUAPC] D9_APC_2: 0x3fffff
9909 13:58:49.077302 INFO: [APUAPC] D9_APC_3: 0x0
9910 13:58:49.080417 INFO: [APUAPC] D10_APC_0: 0xffffffff
9911 13:58:49.083624 INFO: [APUAPC] D10_APC_1: 0xffffffff
9912 13:58:49.086937 INFO: [APUAPC] D10_APC_2: 0x3fffff
9913 13:58:49.090176 INFO: [APUAPC] D10_APC_3: 0x0
9914 13:58:49.093603 INFO: [APUAPC] D11_APC_0: 0xffffffff
9915 13:58:49.097785 INFO: [APUAPC] D11_APC_1: 0xffffffff
9916 13:58:49.100040 INFO: [APUAPC] D11_APC_2: 0x3fffff
9917 13:58:49.103590 INFO: [APUAPC] D11_APC_3: 0x0
9918 13:58:49.106902 INFO: [APUAPC] D12_APC_0: 0xffffffff
9919 13:58:49.110258 INFO: [APUAPC] D12_APC_1: 0xffffffff
9920 13:58:49.113594 INFO: [APUAPC] D12_APC_2: 0x3fffff
9921 13:58:49.116850 INFO: [APUAPC] D12_APC_3: 0x0
9922 13:58:49.119641 INFO: [APUAPC] D13_APC_0: 0xffffffff
9923 13:58:49.123329 INFO: [APUAPC] D13_APC_1: 0xffffffff
9924 13:58:49.126729 INFO: [APUAPC] D13_APC_2: 0x3fffff
9925 13:58:49.129611 INFO: [APUAPC] D13_APC_3: 0x0
9926 13:58:49.133226 INFO: [APUAPC] D14_APC_0: 0xffffffff
9927 13:58:49.136679 INFO: [APUAPC] D14_APC_1: 0xffffffff
9928 13:58:49.140106 INFO: [APUAPC] D14_APC_2: 0x3fffff
9929 13:58:49.143172 INFO: [APUAPC] D14_APC_3: 0x0
9930 13:58:49.146764 INFO: [APUAPC] D15_APC_0: 0xffffffff
9931 13:58:49.149934 INFO: [APUAPC] D15_APC_1: 0xffffffff
9932 13:58:49.153194 INFO: [APUAPC] D15_APC_2: 0x3fffff
9933 13:58:49.156543 INFO: [APUAPC] D15_APC_3: 0x0
9934 13:58:49.159873 INFO: [APUAPC] APC_CON: 0x4
9935 13:58:49.163076 INFO: [NOCDAPC] D0_APC_0: 0x0
9936 13:58:49.166147 INFO: [NOCDAPC] D0_APC_1: 0x0
9937 13:58:49.166701 INFO: [NOCDAPC] D1_APC_0: 0x0
9938 13:58:49.169782 INFO: [NOCDAPC] D1_APC_1: 0xfff
9939 13:58:49.172674 INFO: [NOCDAPC] D2_APC_0: 0x0
9940 13:58:49.175798 INFO: [NOCDAPC] D2_APC_1: 0xfff
9941 13:58:49.179750 INFO: [NOCDAPC] D3_APC_0: 0x0
9942 13:58:49.182993 INFO: [NOCDAPC] D3_APC_1: 0xfff
9943 13:58:49.186077 INFO: [NOCDAPC] D4_APC_0: 0x0
9944 13:58:49.189070 INFO: [NOCDAPC] D4_APC_1: 0xfff
9945 13:58:49.192614 INFO: [NOCDAPC] D5_APC_0: 0x0
9946 13:58:49.195729 INFO: [NOCDAPC] D5_APC_1: 0xfff
9947 13:58:49.198667 INFO: [NOCDAPC] D6_APC_0: 0x0
9948 13:58:49.202892 INFO: [NOCDAPC] D6_APC_1: 0xfff
9949 13:58:49.203414 INFO: [NOCDAPC] D7_APC_0: 0x0
9950 13:58:49.205207 INFO: [NOCDAPC] D7_APC_1: 0xfff
9951 13:58:49.208599 INFO: [NOCDAPC] D8_APC_0: 0x0
9952 13:58:49.211895 INFO: [NOCDAPC] D8_APC_1: 0xfff
9953 13:58:49.215517 INFO: [NOCDAPC] D9_APC_0: 0x0
9954 13:58:49.219257 INFO: [NOCDAPC] D9_APC_1: 0xfff
9955 13:58:49.221948 INFO: [NOCDAPC] D10_APC_0: 0x0
9956 13:58:49.225004 INFO: [NOCDAPC] D10_APC_1: 0xfff
9957 13:58:49.228818 INFO: [NOCDAPC] D11_APC_0: 0x0
9958 13:58:49.232329 INFO: [NOCDAPC] D11_APC_1: 0xfff
9959 13:58:49.235589 INFO: [NOCDAPC] D12_APC_0: 0x0
9960 13:58:49.238416 INFO: [NOCDAPC] D12_APC_1: 0xfff
9961 13:58:49.242062 INFO: [NOCDAPC] D13_APC_0: 0x0
9962 13:58:49.245105 INFO: [NOCDAPC] D13_APC_1: 0xfff
9963 13:58:49.245566 INFO: [NOCDAPC] D14_APC_0: 0x0
9964 13:58:49.248831 INFO: [NOCDAPC] D14_APC_1: 0xfff
9965 13:58:49.251952 INFO: [NOCDAPC] D15_APC_0: 0x0
9966 13:58:49.255135 INFO: [NOCDAPC] D15_APC_1: 0xfff
9967 13:58:49.259149 INFO: [NOCDAPC] APC_CON: 0x4
9968 13:58:49.261691 INFO: [APUAPC] set_apusys_apc done
9969 13:58:49.265320 INFO: [DEVAPC] devapc_init done
9970 13:58:49.268078 INFO: GICv3 without legacy support detected.
9971 13:58:49.275280 INFO: ARM GICv3 driver initialized in EL3
9972 13:58:49.278231 INFO: Maximum SPI INTID supported: 639
9973 13:58:49.281581 INFO: BL31: Initializing runtime services
9974 13:58:49.288070 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9975 13:58:49.291646 INFO: SPM: enable CPC mode
9976 13:58:49.294446 INFO: mcdi ready for mcusys-off-idle and system suspend
9977 13:58:49.301174 INFO: BL31: Preparing for EL3 exit to normal world
9978 13:58:49.304401 INFO: Entry point address = 0x80000000
9979 13:58:49.304969 INFO: SPSR = 0x8
9980 13:58:49.311015
9981 13:58:49.311531
9982 13:58:49.311869
9983 13:58:49.314566 Starting depthcharge on Spherion...
9984 13:58:49.315086
9985 13:58:49.315422 Wipe memory regions:
9986 13:58:49.315733
9987 13:58:49.318318 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9988 13:58:49.318839 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9989 13:58:49.319239 Setting prompt string to ['asurada:']
9990 13:58:49.319639 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9991 13:58:49.320380 [0x00000040000000, 0x00000054600000)
9992 13:58:49.440095
9993 13:58:49.440612 [0x00000054660000, 0x00000080000000)
9994 13:58:49.700627
9995 13:58:49.701187 [0x000000821a7280, 0x000000ffe64000)
9996 13:58:50.446039
9997 13:58:50.446610 [0x00000100000000, 0x00000240000000)
9998 13:58:52.335881
9999 13:58:52.339427 Initializing XHCI USB controller at 0x11200000.
10000 13:58:53.378518
10001 13:58:53.380021 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10002 13:58:53.380480
10003 13:58:53.380844
10004 13:58:53.381181
10005 13:58:53.381984 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10007 13:58:53.483320 asurada: tftpboot 192.168.201.1 11372179/tftp-deploy-x_1saco3/kernel/image.itb 11372179/tftp-deploy-x_1saco3/kernel/cmdline
10008 13:58:53.484022 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10009 13:58:53.484513 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10010 13:58:53.489245 tftpboot 192.168.201.1 11372179/tftp-deploy-x_1saco3/kernel/image.itp-deploy-x_1saco3/kernel/cmdline
10011 13:58:53.489712
10012 13:58:53.490114 Waiting for link
10013 13:58:53.649755
10014 13:58:53.650311 R8152: Initializing
10015 13:58:53.650679
10016 13:58:53.652896 Version 6 (ocp_data = 5c30)
10017 13:58:53.653352
10018 13:58:53.656255 R8152: Done initializing
10019 13:58:53.656797
10020 13:58:53.657279 Adding net device
10021 13:58:55.634272
10022 13:58:55.634828 done.
10023 13:58:55.635196
10024 13:58:55.635538 MAC: 00:24:32:30:7c:7b
10025 13:58:55.635870
10026 13:58:55.637135 Sending DHCP discover... done.
10027 13:58:55.637589
10028 13:58:55.640496 Waiting for reply... done.
10029 13:58:55.641102
10030 13:58:55.643604 Sending DHCP request... done.
10031 13:58:55.644108
10032 13:58:55.649622 Waiting for reply... done.
10033 13:58:55.650079
10034 13:58:55.650440 My ip is 192.168.201.14
10035 13:58:55.650779
10036 13:58:55.653169 The DHCP server ip is 192.168.201.1
10037 13:58:55.653629
10038 13:58:55.659859 TFTP server IP predefined by user: 192.168.201.1
10039 13:58:55.660322
10040 13:58:55.666413 Bootfile predefined by user: 11372179/tftp-deploy-x_1saco3/kernel/image.itb
10041 13:58:55.666927
10042 13:58:55.669311 Sending tftp read request... done.
10043 13:58:55.669725
10044 13:58:55.676177 Waiting for the transfer...
10045 13:58:55.676592
10046 13:58:56.352873 00000000 ################################################################
10047 13:58:56.353389
10048 13:58:57.031865 00080000 ################################################################
10049 13:58:57.032405
10050 13:58:57.724995 00100000 ################################################################
10051 13:58:57.725499
10052 13:58:58.405901 00180000 ################################################################
10053 13:58:58.406046
10054 13:58:59.004489 00200000 ################################################################
10055 13:58:59.004659
10056 13:58:59.686270 00280000 ################################################################
10057 13:58:59.686762
10058 13:59:00.371705 00300000 ################################################################
10059 13:59:00.372237
10060 13:59:01.049579 00380000 ################################################################
10061 13:59:01.050085
10062 13:59:01.690859 00400000 ################################################################
10063 13:59:01.691007
10064 13:59:02.255028 00480000 ################################################################
10065 13:59:02.255161
10066 13:59:02.836591 00500000 ################################################################
10067 13:59:02.836727
10068 13:59:03.405125 00580000 ################################################################
10069 13:59:03.405273
10070 13:59:03.932298 00600000 ################################################################
10071 13:59:03.932433
10072 13:59:04.472302 00680000 ################################################################
10073 13:59:04.472437
10074 13:59:05.024241 00700000 ################################################################
10075 13:59:05.024379
10076 13:59:05.585128 00780000 ################################################################
10077 13:59:05.585292
10078 13:59:06.131834 00800000 ################################################################
10079 13:59:06.132139
10080 13:59:06.667803 00880000 ################################################################
10081 13:59:06.667993
10082 13:59:07.203330 00900000 ################################################################
10083 13:59:07.203471
10084 13:59:07.734543 00980000 ################################################################
10085 13:59:07.734704
10086 13:59:08.287880 00a00000 ################################################################
10087 13:59:08.288064
10088 13:59:08.830672 00a80000 ################################################################
10089 13:59:08.830805
10090 13:59:09.394666 00b00000 ################################################################
10091 13:59:09.394812
10092 13:59:09.951545 00b80000 ################################################################
10093 13:59:09.951681
10094 13:59:10.524543 00c00000 ################################################################
10095 13:59:10.524680
10096 13:59:11.101360 00c80000 ################################################################
10097 13:59:11.101490
10098 13:59:11.695669 00d00000 ################################################################
10099 13:59:11.695828
10100 13:59:12.251001 00d80000 ################################################################
10101 13:59:12.251134
10102 13:59:12.828613 00e00000 ################################################################
10103 13:59:12.828753
10104 13:59:13.369715 00e80000 ################################################################
10105 13:59:13.369853
10106 13:59:13.911186 00f00000 ################################################################
10107 13:59:13.911319
10108 13:59:14.460085 00f80000 ################################################################
10109 13:59:14.460216
10110 13:59:15.014505 01000000 ################################################################
10111 13:59:15.014643
10112 13:59:15.589759 01080000 ################################################################
10113 13:59:15.589896
10114 13:59:16.192498 01100000 ################################################################
10115 13:59:16.192634
10116 13:59:16.801520 01180000 ################################################################
10117 13:59:16.801651
10118 13:59:17.362577 01200000 ################################################################
10119 13:59:17.362707
10120 13:59:17.925949 01280000 ################################################################
10121 13:59:17.926083
10122 13:59:18.493612 01300000 ################################################################
10123 13:59:18.493742
10124 13:59:19.072282 01380000 ################################################################
10125 13:59:19.072411
10126 13:59:19.653786 01400000 ################################################################
10127 13:59:19.653920
10128 13:59:20.216318 01480000 ################################################################
10129 13:59:20.216456
10130 13:59:20.852239 01500000 ################################################################
10131 13:59:20.852384
10132 13:59:21.438289 01580000 ################################################################
10133 13:59:21.438426
10134 13:59:22.067001 01600000 ################################################################
10135 13:59:22.067150
10136 13:59:22.699515 01680000 ################################################################
10137 13:59:22.699661
10138 13:59:23.333809 01700000 ################################################################
10139 13:59:23.333957
10140 13:59:23.989010 01780000 ################################################################
10141 13:59:23.989567
10142 13:59:24.668219 01800000 ################################################################
10143 13:59:24.668344
10144 13:59:25.278522 01880000 ################################################################
10145 13:59:25.278653
10146 13:59:25.860287 01900000 ################################################################
10147 13:59:25.860424
10148 13:59:26.517470 01980000 ################################################################
10149 13:59:26.517614
10150 13:59:27.155206 01a00000 ################################################################
10151 13:59:27.155357
10152 13:59:27.806047 01a80000 ################################################################
10153 13:59:27.806600
10154 13:59:28.487848 01b00000 ################################################################
10155 13:59:28.488468
10156 13:59:29.167700 01b80000 ################################################################
10157 13:59:29.168281
10158 13:59:29.855092 01c00000 ################################################################
10159 13:59:29.855647
10160 13:59:30.543179 01c80000 ################################################################
10161 13:59:30.543714
10162 13:59:31.226067 01d00000 ################################################################
10163 13:59:31.226601
10164 13:59:31.888863 01d80000 ################################################################
10165 13:59:31.888994
10166 13:59:32.541435 01e00000 ################################################################
10167 13:59:32.541949
10168 13:59:33.217201 01e80000 ################################################################
10169 13:59:33.217349
10170 13:59:33.886775 01f00000 ################################################################
10171 13:59:33.887290
10172 13:59:34.570964 01f80000 ################################################################
10173 13:59:34.571475
10174 13:59:35.262711 02000000 ################################################################
10175 13:59:35.263217
10176 13:59:35.946336 02080000 ################################################################
10177 13:59:35.947037
10178 13:59:36.629337 02100000 ################################################################
10179 13:59:36.629840
10180 13:59:37.321511 02180000 ################################################################
10181 13:59:37.322030
10182 13:59:38.004966 02200000 ################################################################
10183 13:59:38.005470
10184 13:59:38.686984 02280000 ################################################################
10185 13:59:38.687490
10186 13:59:39.360466 02300000 ################################################################
10187 13:59:39.360969
10188 13:59:40.053879 02380000 ################################################################
10189 13:59:40.054385
10190 13:59:40.742023 02400000 ################################################################
10191 13:59:40.742529
10192 13:59:41.422429 02480000 ################################################################
10193 13:59:41.422573
10194 13:59:42.054057 02500000 ################################################################
10195 13:59:42.054558
10196 13:59:42.683769 02580000 ################################################################
10197 13:59:42.684247
10198 13:59:43.315127 02600000 ################################################################
10199 13:59:43.315680
10200 13:59:43.911857 02680000 ################################################################
10201 13:59:43.912057
10202 13:59:44.509398 02700000 ################################################################
10203 13:59:44.509561
10204 13:59:45.150994 02780000 ################################################################
10205 13:59:45.151567
10206 13:59:45.837401 02800000 ################################################################
10207 13:59:45.837911
10208 13:59:46.513725 02880000 ################################################################
10209 13:59:46.514233
10210 13:59:47.204377 02900000 ################################################################
10211 13:59:47.204889
10212 13:59:47.888948 02980000 ################################################################
10213 13:59:47.889517
10214 13:59:48.560216 02a00000 ################################################################
10215 13:59:48.560790
10216 13:59:49.232026 02a80000 ################################################################
10217 13:59:49.232171
10218 13:59:49.854595 02b00000 ################################################################
10219 13:59:49.854742
10220 13:59:50.497877 02b80000 ################################################################
10221 13:59:50.498022
10222 13:59:51.118120 02c00000 ################################################################
10223 13:59:51.118274
10224 13:59:51.738522 02c80000 ################################################################
10225 13:59:51.739010
10226 13:59:52.409057 02d00000 ################################################################
10227 13:59:52.409202
10228 13:59:52.983662 02d80000 ################################################################
10229 13:59:52.983797
10230 13:59:53.537917 02e00000 ################################################################
10231 13:59:53.538071
10232 13:59:54.107498 02e80000 ################################################################
10233 13:59:54.107651
10234 13:59:54.701483 02f00000 ################################################################
10235 13:59:54.701637
10236 13:59:55.268925 02f80000 ################################################################
10237 13:59:55.269071
10238 13:59:55.830435 03000000 ################################################################
10239 13:59:55.830613
10240 13:59:56.407844 03080000 ################################################################
10241 13:59:56.408007
10242 13:59:56.984624 03100000 ################################################################
10243 13:59:56.984772
10244 13:59:57.581541 03180000 ################################################################
10245 13:59:57.581695
10246 13:59:58.172394 03200000 ################################################################
10247 13:59:58.172543
10248 13:59:58.742285 03280000 ################################################################
10249 13:59:58.742430
10250 13:59:59.314565 03300000 ################################################################
10251 13:59:59.314721
10252 13:59:59.873390 03380000 ################################################################
10253 13:59:59.873590
10254 14:00:00.427226 03400000 ################################################################
10255 14:00:00.427421
10256 14:00:00.998117 03480000 ################################################################
10257 14:00:00.998313
10258 14:00:01.559362 03500000 ################################################################
10259 14:00:01.559513
10260 14:00:02.114017 03580000 ################################################################
10261 14:00:02.114170
10262 14:00:02.663327 03600000 ################################################################
10263 14:00:02.663480
10264 14:00:03.227884 03680000 ################################################################
10265 14:00:03.228070
10266 14:00:03.770591 03700000 ################################################################
10267 14:00:03.770745
10268 14:00:04.188751 03780000 ################################################## done.
10269 14:00:04.188908
10270 14:00:04.192041 The bootfile was 58597930 bytes long.
10271 14:00:04.192128
10272 14:00:04.195260 Sending tftp read request... done.
10273 14:00:04.195346
10274 14:00:04.198308 Waiting for the transfer...
10275 14:00:04.198401
10276 14:00:04.198465 00000000 # done.
10277 14:00:04.198528
10278 14:00:04.208327 Command line loaded dynamically from TFTP file: 11372179/tftp-deploy-x_1saco3/kernel/cmdline
10279 14:00:04.208457
10280 14:00:04.221373 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10281 14:00:04.221514
10282 14:00:04.221587 Loading FIT.
10283 14:00:04.221650
10284 14:00:04.224491 Image ramdisk-1 has 47508781 bytes.
10285 14:00:04.224592
10286 14:00:04.228191 Image fdt-1 has 47278 bytes.
10287 14:00:04.228281
10288 14:00:04.231171 Image kernel-1 has 11039834 bytes.
10289 14:00:04.231260
10290 14:00:04.238024 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10291 14:00:04.240623
10292 14:00:04.257352 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10293 14:00:04.257503
10294 14:00:04.260579 Choosing best match conf-1 for compat google,spherion-rev2.
10295 14:00:04.266713
10296 14:00:04.271010 Connected to device vid:did:rid of 1ae0:0028:00
10297 14:00:04.278306
10298 14:00:04.281213 tpm_get_response: command 0x17b, return code 0x0
10299 14:00:04.281308
10300 14:00:04.287685 ec_init: CrosEC protocol v3 supported (256, 248)
10301 14:00:04.287790
10302 14:00:04.291368 tpm_cleanup: add release locality here.
10303 14:00:04.291454
10304 14:00:04.294557 Shutting down all USB controllers.
10305 14:00:04.294670
10306 14:00:04.298051 Removing current net device
10307 14:00:04.298135
10308 14:00:04.301145 Exiting depthcharge with code 4 at timestamp: 104213784
10309 14:00:04.301229
10310 14:00:04.304392 LZMA decompressing kernel-1 to 0x821a6718
10311 14:00:04.307708
10312 14:00:04.311019 LZMA decompressing kernel-1 to 0x40000000
10313 14:00:05.698393
10314 14:00:05.698548 jumping to kernel
10315 14:00:05.698984 end: 2.2.4 bootloader-commands (duration 00:01:16) [common]
10316 14:00:05.699084 start: 2.2.5 auto-login-action (timeout 00:03:09) [common]
10317 14:00:05.699161 Setting prompt string to ['Linux version [0-9]']
10318 14:00:05.699230 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10319 14:00:05.699318 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10320 14:00:05.781075
10321 14:00:05.784104 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10322 14:00:05.787503 start: 2.2.5.1 login-action (timeout 00:03:09) [common]
10323 14:00:05.787594 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10324 14:00:05.787665 Setting prompt string to []
10325 14:00:05.787744 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10326 14:00:05.787818 Using line separator: #'\n'#
10327 14:00:05.787876 No login prompt set.
10328 14:00:05.787993 Parsing kernel messages
10329 14:00:05.788049 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10330 14:00:05.788149 [login-action] Waiting for messages, (timeout 00:03:09)
10331 14:00:05.807646 [ 0.000000] Linux version 6.1.46-cip4-rt2 (KernelCI@build-j25372-arm64-gcc-10-defconfig-arm64-chromebook-2wz78) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 28 13:41:26 UTC 2023
10332 14:00:05.810554 [ 0.000000] random: crng init done
10333 14:00:05.817213 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10334 14:00:05.820458 [ 0.000000] efi: UEFI not found.
10335 14:00:05.826621 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10336 14:00:05.836686 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10337 14:00:05.846483 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10338 14:00:05.853121 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10339 14:00:05.859580 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10340 14:00:05.866269 [ 0.000000] printk: bootconsole [mtk8250] enabled
10341 14:00:05.873102 [ 0.000000] NUMA: No NUMA configuration found
10342 14:00:05.879402 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10343 14:00:05.886367 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10344 14:00:05.886455 [ 0.000000] Zone ranges:
10345 14:00:05.893534 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10346 14:00:05.895767 [ 0.000000] DMA32 empty
10347 14:00:05.903120 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10348 14:00:05.906188 [ 0.000000] Movable zone start for each node
10349 14:00:05.909028 [ 0.000000] Early memory node ranges
10350 14:00:05.915730 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10351 14:00:05.922565 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10352 14:00:05.929187 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10353 14:00:05.935524 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10354 14:00:05.942181 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10355 14:00:05.948334 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10356 14:00:06.005113 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10357 14:00:06.011723 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10358 14:00:06.018432 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10359 14:00:06.021430 [ 0.000000] psci: probing for conduit method from DT.
10360 14:00:06.028473 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10361 14:00:06.031502 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10362 14:00:06.038345 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10363 14:00:06.041814 [ 0.000000] psci: SMC Calling Convention v1.2
10364 14:00:06.048396 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10365 14:00:06.051479 [ 0.000000] Detected VIPT I-cache on CPU0
10366 14:00:06.057954 [ 0.000000] CPU features: detected: GIC system register CPU interface
10367 14:00:06.064661 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10368 14:00:06.071341 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10369 14:00:06.077786 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10370 14:00:06.088259 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10371 14:00:06.094160 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10372 14:00:06.097686 [ 0.000000] alternatives: applying boot alternatives
10373 14:00:06.103897 [ 0.000000] Fallback order for Node 0: 0
10374 14:00:06.110741 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10375 14:00:06.114232 [ 0.000000] Policy zone: Normal
10376 14:00:06.127398 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10377 14:00:06.136893 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10378 14:00:06.149739 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10379 14:00:06.159963 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10380 14:00:06.166050 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10381 14:00:06.169376 <6>[ 0.000000] software IO TLB: area num 8.
10382 14:00:06.227426 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10383 14:00:06.376376 <6>[ 0.000000] Memory: 7923096K/8385536K available (17984K kernel code, 4100K rwdata, 17468K rodata, 8384K init, 615K bss, 429672K reserved, 32768K cma-reserved)
10384 14:00:06.383670 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10385 14:00:06.389558 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10386 14:00:06.393102 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10387 14:00:06.399586 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10388 14:00:06.405823 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10389 14:00:06.409135 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10390 14:00:06.419181 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10391 14:00:06.425811 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10392 14:00:06.432373 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10393 14:00:06.438834 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10394 14:00:06.443076 <6>[ 0.000000] GICv3: 608 SPIs implemented
10395 14:00:06.445753 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10396 14:00:06.451873 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10397 14:00:06.455758 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10398 14:00:06.462113 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10399 14:00:06.475328 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10400 14:00:06.488510 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10401 14:00:06.494944 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10402 14:00:06.502697 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10403 14:00:06.516512 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10404 14:00:06.522604 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10405 14:00:06.529695 <6>[ 0.009181] Console: colour dummy device 80x25
10406 14:00:06.539794 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10407 14:00:06.545867 <6>[ 0.024342] pid_max: default: 32768 minimum: 301
10408 14:00:06.549466 <6>[ 0.029214] LSM: Security Framework initializing
10409 14:00:06.556374 <6>[ 0.034154] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10410 14:00:06.565634 <6>[ 0.041968] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10411 14:00:06.575758 <6>[ 0.051385] cblist_init_generic: Setting adjustable number of callback queues.
10412 14:00:06.579340 <6>[ 0.058829] cblist_init_generic: Setting shift to 3 and lim to 1.
10413 14:00:06.588932 <6>[ 0.065207] cblist_init_generic: Setting adjustable number of callback queues.
10414 14:00:06.595889 <6>[ 0.072633] cblist_init_generic: Setting shift to 3 and lim to 1.
10415 14:00:06.599153 <6>[ 0.079072] rcu: Hierarchical SRCU implementation.
10416 14:00:06.605483 <6>[ 0.079074] rcu: Max phase no-delay instances is 1000.
10417 14:00:06.611796 <6>[ 0.079099] printk: bootconsole [mtk8250] printing thread started
10418 14:00:06.618531 <6>[ 0.097423] EFI services will not be available.
10419 14:00:06.622179 <6>[ 0.097621] smp: Bringing up secondary CPUs ...
10420 14:00:06.628508 <6>[ 0.097933] Detected VIPT I-cache on CPU1
10421 14:00:06.635165 <6>[ 0.098002] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10422 14:00:06.642331 <6>[ 0.098034] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10423 14:00:06.650966 <6>[ 0.125912] Detected VIPT I-cache on CPU2
10424 14:00:06.657537 <6>[ 0.125962] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10425 14:00:06.667919 <6>[ 0.125979] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10426 14:00:06.670592 <6>[ 0.126241] Detected VIPT I-cache on CPU3
10427 14:00:06.677374 <6>[ 0.126287] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10428 14:00:06.684248 <6>[ 0.126301] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10429 14:00:06.690741 <6>[ 0.126609] CPU features: detected: Spectre-v4
10430 14:00:06.694337 <6>[ 0.126616] CPU features: detected: Spectre-BHB
10431 14:00:06.697289 <6>[ 0.126621] Detected PIPT I-cache on CPU4
10432 14:00:06.704115 <6>[ 0.126681] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10433 14:00:06.711008 <6>[ 0.126697] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10434 14:00:06.717014 <6>[ 0.126992] Detected PIPT I-cache on CPU5
10435 14:00:06.723799 <6>[ 0.127055] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10436 14:00:06.730026 <6>[ 0.127072] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10437 14:00:06.733288 <6>[ 0.127346] Detected PIPT I-cache on CPU6
10438 14:00:06.743026 <6>[ 0.127410] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10439 14:00:06.749671 <6>[ 0.127427] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10440 14:00:06.753020 <6>[ 0.127715] Detected PIPT I-cache on CPU7
10441 14:00:06.760196 <6>[ 0.127779] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10442 14:00:06.767118 <6>[ 0.127795] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10443 14:00:06.772918 <6>[ 0.127842] smp: Brought up 1 node, 8 CPUs
10444 14:00:06.775784 <6>[ 0.127846] SMP: Total of 8 processors activated.
10445 14:00:06.782866 <6>[ 0.127849] CPU features: detected: 32-bit EL0 Support
10446 14:00:06.788948 <6>[ 0.127851] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10447 14:00:06.796272 <6>[ 0.127854] CPU features: detected: Common not Private translations
10448 14:00:06.802106 <6>[ 0.127855] CPU features: detected: CRC32 instructions
10449 14:00:06.808798 <6>[ 0.127858] CPU features: detected: RCpc load-acquire (LDAPR)
10450 14:00:06.815558 <6>[ 0.127860] CPU features: detected: LSE atomic instructions
10451 14:00:06.818810 <6>[ 0.127861] CPU features: detected: Privileged Access Never
10452 14:00:06.825055 <6>[ 0.127863] CPU features: detected: RAS Extension Support
10453 14:00:06.831817 <6>[ 0.127865] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10454 14:00:06.835146 <6>[ 0.127934] CPU: All CPU(s) started at EL2
10455 14:00:06.842333 <6>[ 0.127935] alternatives: applying system-wide alternatives
10456 14:00:06.845161 <6>[ 0.140961] devtmpfs: initialized
10457 14:00:06.871557 ���hash table entries: 512 (order 0, 4096 bytes)
10458 14:00:06.874654 <6>[ 0.355495] printk: console [ttyS0] enabled
10459 14:00:06.881139 <6>[ 0.355498] printk: bootconsole [mtk8250] disabled
10460 14:00:06.884758 <6>[ 0.355498] printk: console [ttyS0] printing thread started
10461 14:00:06.891429 <6>[ 0.355512] printk: bootconsole [mtk8250] printing thread stopped
10462 14:00:06.898165 <6>[ 0.360884] SuperH (H)SCI(F) driver initialized
10463 14:00:06.900990 <6>[ 0.361376] msm_serial: driver initialized
10464 14:00:06.911235 <6>[ 0.365939] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10465 14:00:06.917895 <6>[ 0.365967] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10466 14:00:06.928509 <6>[ 0.365997] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10467 14:00:06.939558 <6>[ 0.366026] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10468 14:00:06.948308 <6>[ 0.366047] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10469 14:00:06.969452 <6>[ 0.366075] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10470 14:00:06.970019 <6>[ 0.366103] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10471 14:00:06.975839 <6>[ 0.366204] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10472 14:00:06.984330 <6>[ 0.366234] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10473 14:00:06.988336 <6>[ 0.374630] loop: module loaded
10474 14:00:06.992100 <6>[ 0.377043] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10475 14:00:06.995066 <4>[ 0.393903] mtk-pmic-keys: Failed to locate of_node [id: -1]
10476 14:00:06.998891 <6>[ 0.394710] megasas: 07.719.03.00-rc1
10477 14:00:07.002493 <6>[ 0.404665] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10478 14:00:07.008707 <6>[ 0.412722] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10479 14:00:07.015464 <6>[ 0.424607] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10480 14:00:07.028728 <6>[ 0.477529] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10481 14:00:08.777505 <6>[ 2.256193] Freeing initrd memory: 46392K
10482 14:00:08.785588 <6>[ 2.262162] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10483 14:00:08.791793 <6>[ 2.266965] tun: Universal TUN/TAP device driver, 1.6
10484 14:00:08.795426 <6>[ 2.267722] thunder_xcv, ver 1.0
10485 14:00:08.798491 <6>[ 2.267739] thunder_bgx, ver 1.0
10486 14:00:08.802052 <6>[ 2.267754] nicpf, ver 1.0
10487 14:00:08.808836 <6>[ 2.268797] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10488 14:00:08.815672 <6>[ 2.268800] hns3: Copyright (c) 2017 Huawei Corporation.
10489 14:00:08.818493 <6>[ 2.268825] hclge is initializing
10490 14:00:08.822016 <6>[ 2.268839] e1000: Intel(R) PRO/1000 Network Driver
10491 14:00:08.830378 <6>[ 2.268842] e1000: Copyright (c) 1999-2006 Intel Corporation.
10492 14:00:08.836554 <6>[ 2.268859] e1000e: Intel(R) PRO/1000 Network Driver
10493 14:00:08.840589 <6>[ 2.268860] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10494 14:00:08.846589 <6>[ 2.268882] igb: Intel(R) Gigabit Ethernet Network Driver
10495 14:00:08.853422 <6>[ 2.268884] igb: Copyright (c) 2007-2014 Intel Corporation.
10496 14:00:08.860663 <6>[ 2.268898] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10497 14:00:08.864040 <6>[ 2.268899] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10498 14:00:08.870870 <6>[ 2.269191] sky2: driver version 1.30
10499 14:00:08.874338 <6>[ 2.270274] VFIO - User Level meta-driver version: 0.3
10500 14:00:08.880377 <6>[ 2.273074] usbcore: registered new interface driver usb-storage
10501 14:00:08.886936 <6>[ 2.273255] usbcore: registered new device driver onboard-usb-hub
10502 14:00:08.893826 <6>[ 2.276014] mt6397-rtc mt6359-rtc: registered as rtc0
10503 14:00:08.900340 <6>[ 2.276163] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-28T14:00:09 UTC (1693231209)
10504 14:00:08.906854 <6>[ 2.276776] i2c_dev: i2c /dev entries driver
10505 14:00:08.913986 <6>[ 2.283918] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10506 14:00:08.916812 <6>[ 2.298899] cpu cpu0: EM: created perf domain
10507 14:00:08.923643 <6>[ 2.299126] cpu cpu4: EM: created perf domain
10508 14:00:08.930130 <6>[ 2.303529] sdhci: Secure Digital Host Controller Interface driver
10509 14:00:08.933519 <6>[ 2.303530] sdhci: Copyright(c) Pierre Ossman
10510 14:00:08.940161 <6>[ 2.303892] Synopsys Designware Multimedia Card Interface Driver
10511 14:00:08.946744 <6>[ 2.304281] sdhci-pltfm: SDHCI platform and OF driver helper
10512 14:00:08.953369 <6>[ 2.308557] ledtrig-cpu: registered to indicate activity on CPUs
10513 14:00:08.957214 <6>[ 2.309166] mmc0: CQHCI version 5.10
10514 14:00:08.963529 <6>[ 2.309231] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10515 14:00:08.970043 <6>[ 2.309534] usbcore: registered new interface driver usbhid
10516 14:00:08.973252 <6>[ 2.309535] usbhid: USB HID core driver
10517 14:00:08.979784 <6>[ 2.309661] spi_master spi0: will run message pump with realtime priority
10518 14:00:08.992985 <6>[ 2.340074] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10519 14:00:09.006208 <6>[ 2.342029] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10520 14:00:09.012606 <6>[ 2.342981] cros-ec-spi spi0.0: Chrome EC device registered
10521 14:00:09.022417 <6>[ 2.355751] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10522 14:00:09.026144 <6>[ 2.356698] NET: Registered PF_PACKET protocol family
10523 14:00:09.032641 <6>[ 2.356763] 9pnet: Installing 9P2000 support
10524 14:00:09.035855 <5>[ 2.356796] Key type dns_resolver registered
10525 14:00:09.039378 <6>[ 2.357060] registered taskstats version 1
10526 14:00:09.045587 <5>[ 2.357073] Loading compiled-in X.509 certificates
10527 14:00:09.055819 <4>[ 2.372297] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10528 14:00:09.065486 <4>[ 2.372439] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10529 14:00:09.072075 <3>[ 2.372455] debugfs: File 'uA_load' in directory '/' already present!
10530 14:00:09.078677 <3>[ 2.372463] debugfs: File 'min_uV' in directory '/' already present!
10531 14:00:09.085261 <3>[ 2.372465] debugfs: File 'max_uV' in directory '/' already present!
10532 14:00:09.092296 <3>[ 2.372468] debugfs: File 'constraint_flags' in directory '/' already present!
10533 14:00:09.101679 <3>[ 2.374363] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10534 14:00:09.108511 <6>[ 2.381015] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10535 14:00:09.111833 <6>[ 2.381862] xhci-mtk 11200000.usb: xHCI Host Controller
10536 14:00:09.122495 <6>[ 2.381900] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10537 14:00:09.131863 <6>[ 2.382156] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10538 14:00:09.134891 <6>[ 2.382224] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10539 14:00:09.142296 <6>[ 2.382409] xhci-mtk 11200000.usb: xHCI Host Controller
10540 14:00:09.148375 <6>[ 2.382429] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10541 14:00:09.157851 <6>[ 2.382443] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10542 14:00:09.161499 <6>[ 2.383212] hub 1-0:1.0: USB hub found
10543 14:00:09.164316 <6>[ 2.383251] hub 1-0:1.0: 1 port detected
10544 14:00:09.174431 <6>[ 2.383688] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10545 14:00:09.178100 <6>[ 2.384339] hub 2-0:1.0: USB hub found
10546 14:00:09.180843 <6>[ 2.384366] hub 2-0:1.0: 1 port detected
10547 14:00:09.187806 <6>[ 2.390299] mtk-msdc 11f70000.mmc: Got CD GPIO
10548 14:00:09.190729 <6>[ 2.403454] mmc0: Command Queue Engine enabled
10549 14:00:09.197378 <6>[ 2.403466] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10550 14:00:09.200705 <6>[ 2.403907] mmcblk0: mmc0:0001 DA4128 116 GiB
10551 14:00:09.208434 <6>[ 2.407137] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10552 14:00:09.213842 <6>[ 2.408534] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10553 14:00:09.217130 <6>[ 2.409132] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10554 14:00:09.227623 <6>[ 2.409582] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10555 14:00:09.233787 <6>[ 2.409594] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10556 14:00:09.243833 <4>[ 2.409721] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10557 14:00:09.250603 <6>[ 2.409946] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10558 14:00:09.256940 <6>[ 2.410215] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10559 14:00:09.266812 <6>[ 2.410216] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10560 14:00:09.273374 <6>[ 2.410327] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10561 14:00:09.279951 <6>[ 2.410338] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10562 14:00:09.289842 <6>[ 2.410339] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10563 14:00:09.299970 <6>[ 2.410342] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10564 14:00:09.306851 <6>[ 2.411953] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10565 14:00:09.316294 <6>[ 2.411966] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10566 14:00:09.323104 <6>[ 2.411970] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10567 14:00:09.332960 <6>[ 2.411973] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10568 14:00:09.339566 <6>[ 2.411976] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10569 14:00:09.349440 <6>[ 2.411979] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10570 14:00:09.356128 <6>[ 2.411982] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10571 14:00:09.365798 <6>[ 2.411985] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10572 14:00:09.372464 <6>[ 2.411988] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10573 14:00:09.382153 <6>[ 2.411994] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10574 14:00:09.389045 <6>[ 2.411998] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10575 14:00:09.398651 <6>[ 2.412001] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10576 14:00:09.405315 <6>[ 2.412004] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10577 14:00:09.415770 <6>[ 2.412007] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10578 14:00:09.422211 <6>[ 2.412010] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10579 14:00:09.428862 <6>[ 2.412667] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10580 14:00:09.435527 <6>[ 2.413699] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10581 14:00:09.442047 <6>[ 2.414241] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10582 14:00:09.448125 <6>[ 2.414712] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10583 14:00:09.454906 <6>[ 2.415064] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10584 14:00:09.464588 <6>[ 2.415234] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10585 14:00:09.474781 <6>[ 2.415249] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10586 14:00:09.484827 <6>[ 2.415253] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10587 14:00:09.495763 <6>[ 2.415258] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10588 14:00:09.501506 <6>[ 2.415263] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10589 14:00:09.511426 <6>[ 2.415267] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10590 14:00:09.521214 <6>[ 2.415271] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10591 14:00:09.531192 <6>[ 2.415275] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10592 14:00:09.541765 <6>[ 2.415278] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10593 14:00:09.550456 <6>[ 2.415283] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10594 14:00:09.560740 <6>[ 2.415286] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10595 14:00:09.567227 <6>[ 2.416022] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10596 14:00:09.574843 <6>[ 2.805443] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10597 14:00:09.580256 <6>[ 2.957681] hub 1-1:1.0: USB hub found
10598 14:00:09.583423 <6>[ 2.958060] hub 1-1:1.0: 4 ports detected
10599 14:00:09.608458 <6>[ 3.081735] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10600 14:00:09.630015 <6>[ 3.107695] hub 2-1:1.0: USB hub found
10601 14:00:09.632854 <6>[ 3.108182] hub 2-1:1.0: 3 ports detected
10602 14:00:09.796479 <6>[ 3.269676] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10603 14:00:09.921706 <6>[ 3.397433] hub 1-1.4:1.0: USB hub found
10604 14:00:09.924512 <6>[ 3.397886] hub 1-1.4:1.0: 2 ports detected
10605 14:00:10.000884 <6>[ 3.473753] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10606 14:00:10.212584 <6>[ 3.685649] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10607 14:00:10.396794 <6>[ 3.869692] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10608 14:00:21.241153 <6>[ 14.722630] ALSA device list:
10609 14:00:21.247530 <6>[ 14.722651] No soundcards found.
10610 14:00:21.250707 <6>[ 14.727041] Freeing unused kernel memory: 8384K
10611 14:00:21.254650 <6>[ 14.727136] Run /init as init process
10612 14:00:21.276497 <6>[ 14.756082] NET: Registered PF_INET6 protocol family
10613 14:00:21.279260 <6>[ 14.757457] Segment Routing with IPv6
10614 14:00:21.285732 <6>[ 14.757468] In-situ OAM (IOAM) with IPv6
10615 14:00:21.289588
10616 14:00:21.316698 Welcome to [1mDebian GNU/Linux 11 (bullseye)<30>[ 14.773618] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10617 14:00:21.316787 [0m!
10618 14:00:21.316853
10619 14:00:21.322535 <30>[ 14.774179] systemd[1]: Detected architecture arm64.
10620 14:00:21.329036 <30>[ 14.808133] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10621 14:00:21.487261 <30>[ 14.964501] systemd[1]: Queued start job for default target Graphical Interface.
10622 14:00:21.516970 [[0;32m OK [0m] Created slic<30>[ 14.994600] systemd[1]: Created slice system-getty.slice.
10623 14:00:21.521139 e [0;1;39msystem-getty.slice[0m.
10624 14:00:21.541449 [[0;32m OK [0m] Created slic<30>[ 15.019189] systemd[1]: Created slice system-modprobe.slice.
10625 14:00:21.544296 e [0;1;39msystem-modprobe.slice[0m.
10626 14:00:21.568327 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.042380] systemd[1]: Created slice system-serial\x2dgetty.slice.
10627 14:00:21.570686 m-serial\x2dgetty.slice[0m.
10628 14:00:21.589514 [[0;32m OK [0m] Created slic<30>[ 15.067345] systemd[1]: Created slice User and Session Slice.
10629 14:00:21.592700 e [0;1;39mUser and Session Slice[0m.
10630 14:00:21.616029 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 15.090412] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10631 14:00:21.618919 ssword …ts to Console Directory Watch[0m.
10632 14:00:21.643565 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 15.118397] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10633 14:00:21.646799 sword R…uests to Wall Directory Watch[0m.
10634 14:00:21.674866 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 15.146158] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10635 14:00:21.684975 l Encrypted Volu<30>[ 15.146417] systemd[1]: Reached target Local Encrypted Volumes.
10636 14:00:21.685064 mes[0m.
10637 14:00:21.704233 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 15.182226] systemd[1]: Reached target Paths.
10638 14:00:21.704319 s[0m.
10639 14:00:21.727055 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 15.201637] systemd[1]: Reached target Remote File Systems.
10640 14:00:21.727140 te File Systems[0m.
10641 14:00:21.744048 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 15.221616] systemd[1]: Reached target Slices.
10642 14:00:21.744131 es[0m.
10643 14:00:21.763677 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 15.241645] systemd[1]: Reached target Swap.
10644 14:00:21.763763 [0m.
10645 14:00:21.787338 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 15.262131] systemd[1]: Listening on initctl Compatibility Named Pipe.
10646 14:00:21.790420 l Compatibility Named Pipe[0m.
10647 14:00:21.811391 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 15.286482] systemd[1]: Listening on Journal Audit Socket.
10648 14:00:21.811503 l Audit Socket[0m.
10649 14:00:21.832808 [[0;32m OK [0m] Listening on<30>[ 15.310806] systemd[1]: Listening on Journal Socket (/dev/log).
10650 14:00:21.836026 [0;1;39mJournal Socket (/dev/log)[0m.
10651 14:00:21.857112 [[0;32m OK [0m] Listening on<30>[ 15.334845] systemd[1]: Listening on Journal Socket.
10652 14:00:21.859852 [0;1;39mJournal Socket[0m.
10653 14:00:21.879417 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 15.354349] systemd[1]: Listening on Network Service Netlink Socket.
10654 14:00:21.882979 k Service Netlink Socket[0m.
10655 14:00:21.902967 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 15.378201] systemd[1]: Listening on udev Control Socket.
10656 14:00:21.903054 ontrol Socket[0m.
10657 14:00:21.925567 [[0;32m OK [0m] Listening on<30>[ 15.402703] systemd[1]: Listening on udev Kernel Socket.
10658 14:00:21.928219 [0;1;39mudev Kernel Socket[0m.
10659 14:00:21.987127 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.461873] systemd[1]: Mounting Huge Pages File System...
10660 14:00:21.987214 m[0m...
10661 14:00:22.011304 Mounting [0;1;39mPOSIX Message Queue F<30>[ 15.485754] systemd[1]: Mounting POSIX Message Queue File System...
10662 14:00:22.011390 ile System[0m...
10663 14:00:22.039145 Mounting [0;1;39mKernel Debug File Sys<30>[ 15.513641] systemd[1]: Mounting Kernel Debug File System...
10664 14:00:22.039229 tem[0m...
10665 14:00:22.061910 Startin<30>[ 15.533815] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10666 14:00:22.067936 <30>[ 15.536265] systemd[1]: Starting Create list of static device nodes for the current kernel...
10667 14:00:22.074895 g [0;1;39mCreate list of st…odes for the current kernel[0m...
10668 14:00:22.099520 Starting [0;1;39mLoad Kernel Module co<30>[ 15.574120] systemd[1]: Starting Load Kernel Module configfs...
10669 14:00:22.099605 nfigfs[0m...
10670 14:00:22.118703 Startin<30>[ 15.596344] systemd[1]: Starting Load Kernel Module drm...
10671 14:00:22.121480 g [0;1;39mLoad Kernel Module drm[0m...
10672 14:00:22.143253 <30>[ 15.617773] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10673 14:00:22.168303 Starting [0;1;39mJournal Service[0m..<30>[ 15.646047] systemd[1]: Starting Journal Service...
10674 14:00:22.168386 .
10675 14:00:22.190971 Startin<30>[ 15.668682] systemd[1]: Starting Load Kernel Modules...
10676 14:00:22.193645 g [0;1;39mLoad Kernel Modules[0m...
10677 14:00:22.213935 Startin<30>[ 15.691986] systemd[1]: Starting Remount Root and Kernel File Systems...
10678 14:00:22.220335 g [0;1;39mRemount Root and Kernel File Systems[0m...
10679 14:00:22.243564 Starting [0;1;39mColdplug All udev Dev<30>[ 15.717541] systemd[1]: Starting Coldplug All udev Devices...
10680 14:00:22.243646 ices[0m...
10681 14:00:22.261325 [[0;32m OK [0m] Started [0;<30>[ 15.739689] systemd[1]: Started Journal Service.
10682 14:00:22.264806 1;39mJournal Service[0m.
10683 14:00:22.277915 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10684 14:00:22.293850 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10685 14:00:22.309639 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10686 14:00:22.330459 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10687 14:00:22.346797 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10688 14:00:22.365822 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10689 14:00:22.381012 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10690 14:00:22.400882 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10691 14:00:22.416413 See 'systemctl status systemd-remount-fs.service' for details.
10692 14:00:22.472136 Mounting [0;1;39mKernel Configuration File System[0m...
10693 14:00:22.492750 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10694 14:00:22.507194 <46>[ 15.985032] systemd-journald[193]: Received client request to flush runtime journal.
10695 14:00:22.516139 Starting [0;1;39mLoad/Save Random Seed[0m...
10696 14:00:22.536857 Starting [0;1;39mApply Kernel Variables[0m...
10697 14:00:22.556405 Starting [0;1;39mCreate System Users[0m...
10698 14:00:22.577443 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10699 14:00:22.593300 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10700 14:00:22.613965 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10701 14:00:22.625766 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10702 14:00:22.641982 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10703 14:00:22.658269 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10704 14:00:22.713936 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10705 14:00:22.737608 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10706 14:00:22.752535 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10707 14:00:22.768132 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10708 14:00:22.809036 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10709 14:00:22.835863 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10710 14:00:22.854628 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10711 14:00:22.864328 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10712 14:00:22.926471 Starting [0;1;39mNetwork Service[0m...
10713 14:00:22.955687 Starting [0;1;39mNetwork Time Synchronization[0m...
10714 14:00:22.980318 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10715 14:00:23.015323 <6>[ 16.492657] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10716 14:00:23.022496 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10717 14:00:23.039635 [[0;32m OK [<6>[ 16.516864] remoteproc remoteproc0: scp is available
10718 14:00:23.046850 0m] Started [0;<6>[ 16.517196] remoteproc remoteproc0: powering up scp
10719 14:00:23.056531 1;39mNetwork Tim<6>[ 16.517210] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10720 14:00:23.065824 e Synchronizatio<6>[ 16.517289] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10721 14:00:23.065906 n[0m.
10722 14:00:23.076469 <6>[ 16.553085] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10723 14:00:23.082601 <6>[ 16.553135] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10724 14:00:23.092636 <6>[ 16.553149] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10725 14:00:23.102179 [[0;32m OK [0m] Found device<3>[ 16.579756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 14:00:23.111966 [0;1;39m/dev/t<3>[ 16.579776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 14:00:23.112047 tyS0[0m.
10728 14:00:23.122145 <3>[ 16.579781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 14:00:23.128692 <4>[ 16.584648] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10730 14:00:23.135322 <4>[ 16.598052] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10731 14:00:23.145134 <3>[ 16.598241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 14:00:23.151873 <3>[ 16.598264] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 14:00:23.161925 <3>[ 16.598269] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 14:00:23.168585 <3>[ 16.598279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 14:00:23.178357 [[0;32m OK [0m] Created slic<3>[ 16.598287] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 14:00:23.188357 <3>[ 16.601696] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 14:00:23.194864 <3>[ 16.613531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 14:00:23.204474 e [0;1;39msyste<3>[ 16.613570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 14:00:23.214781 <3>[ 16.613581] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 14:00:23.221260 <3>[ 16.640397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 14:00:23.227710 <3>[ 16.640422] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 14:00:23.237731 <3>[ 16.640425] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 14:00:23.244287 <3>[ 16.640432] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 14:00:23.254451 <3>[ 16.640436] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 14:00:23.260873 <6>[ 16.645883] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10746 14:00:23.271224 m-systemd\x2dbac<6>[ 16.645896] remoteproc remoteproc0: remote processor scp is now up
10747 14:00:23.278015 <6>[ 16.645897] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10748 14:00:23.284646 klight.slice[0m<3>[ 16.676238] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 14:00:23.288200 .
10750 14:00:23.295103 <6>[ 16.681429] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10751 14:00:23.298086 <6>[ 16.681445] pci_bus 0000:00: root bus resource [bus 00-ff]
10752 14:00:23.309077 <6>[ 16.681452] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10753 14:00:23.322667 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.<6>[ 16.681458] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10754 14:00:23.322752
10755 14:00:23.329507 <6>[ 16.681496] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10756 14:00:23.335834 <6>[ 16.681518] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10757 14:00:23.342030 <6>[ 16.681600] pci 0000:00:00.0: supports D1 D2
10758 14:00:23.348875 <6>[ 16.681604] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10759 14:00:23.355808 [[0;32m OK [<6>[ 16.682601] mc: Linux media interface: v0.10
10760 14:00:23.365187 0m] Reached targ<6>[ 16.684506] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10761 14:00:23.371983 <6>[ 16.684596] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10762 14:00:23.378308 <6>[ 16.684621] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10763 14:00:23.388530 et [0;1;39mSyst<6>[ 16.684638] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10764 14:00:23.395685 em Time Synchron<6>[ 16.684653] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10765 14:00:23.398950 <6>[ 16.684757] pci 0000:01:00.0: supports D1 D2
10766 14:00:23.403436 ized[0m.
10767 14:00:23.410286 <6>[ 16.684759] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10768 14:00:23.417236 <6>[ 16.695559] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10769 14:00:23.423733 <6>[ 16.695617] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10770 14:00:23.430950 <6>[ 16.695624] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10771 14:00:23.440376 <6>[ 16.695644] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10772 14:00:23.447100 <6>[ 16.695660] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10773 14:00:23.457266 <6>[ 16.695676] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10774 14:00:23.460625 <6>[ 16.695692] pci 0000:00:00.0: PCI bridge to [bus 01]
10775 14:00:23.470369 <6>[ 16.695702] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10776 14:00:23.473411 <6>[ 16.698072] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10777 14:00:23.480449 <6>[ 16.704643] usbcore: registered new interface driver r8152
10778 14:00:23.487737 <6>[ 16.707711] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10779 14:00:23.494642 <6>[ 16.714475] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10780 14:00:23.501493 <6>[ 16.715756] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10781 14:00:23.511238 <6>[ 16.716509] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10782 14:00:23.517619 <4>[ 16.738546] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10783 14:00:23.524519 <4>[ 16.738546] Fallback method does not support PEC.
10784 14:00:23.528114 <6>[ 16.741170] videodev: Linux video capture interface: v2.00
10785 14:00:23.538274 <3>[ 16.762773] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10786 14:00:23.549685 <6>[ 16.782132] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10787 14:00:23.556204 <6>[ 16.783973] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10788 14:00:23.562280 <6>[ 16.796912] usbcore: registered new interface driver cdc_ether
10789 14:00:23.572812 <3>[ 16.802780] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10790 14:00:23.579863 <3>[ 16.803661] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10791 14:00:23.586449 <6>[ 16.808459] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10792 14:00:23.593561 <6>[ 16.817055] Bluetooth: Core ver 2.22
10793 14:00:23.596437 <6>[ 16.817196] NET: Registered PF_BLUETOOTH protocol family
10794 14:00:23.603034 <6>[ 16.817199] Bluetooth: HCI device and connection manager initialized
10795 14:00:23.609854 <6>[ 16.817234] Bluetooth: HCI socket layer initialized
10796 14:00:23.614229 <6>[ 16.817250] Bluetooth: L2CAP socket layer initialized
10797 14:00:23.620496 <6>[ 16.817274] Bluetooth: SCO socket layer initialized
10798 14:00:23.627250 <6>[ 16.829762] usbcore: registered new interface driver r8153_ecm
10799 14:00:23.634440 <5>[ 16.832498] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10800 14:00:23.640791 <4>[ 16.836683] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10801 14:00:23.651144 <4>[ 16.836696] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10802 14:00:23.658207 <6>[ 16.837999] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10803 14:00:23.668016 <6>[ 16.840466] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10804 14:00:23.675121 <5>[ 16.853079] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10805 14:00:23.681851 <4>[ 16.853165] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10806 14:00:23.688480 <6>[ 16.853173] cfg80211: failed to load regulatory.db
10807 14:00:23.694985 <6>[ 16.875171] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10808 14:00:23.708139 <6>[ 16.876351] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10809 14:00:23.711271 <6>[ 16.876646] usbcore: registered new interface driver uvcvideo
10810 14:00:23.718252 <6>[ 16.883093] r8152 2-1.3:1.0 eth0: v1.12.13
10811 14:00:23.721563 <6>[ 16.887503] usbcore: registered new interface driver btusb
10812 14:00:23.735041 <4>[ 16.888628] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10813 14:00:23.741331 <3>[ 16.888662] Bluetooth: hci0: Failed to load firmware file (-2)
10814 14:00:23.751204 Starting [0;1;39mLoad/Save Screen …o<3>[ 16.888667] Bluetooth: hci0: Failed to set up firmware (-2)
10815 14:00:23.761363 f leds:white:kbd<4>[ 16.888680] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10816 14:00:23.767371 <6>[ 16.889882] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10817 14:00:23.777650 <3>[ 16.898647] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10818 14:00:23.784043 <6>[ 16.898680] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10819 14:00:23.790672 <3>[ 16.916108] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10820 14:00:23.800998 <6>[ 16.952890] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10821 14:00:23.804234 <6>[ 16.952982] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10822 14:00:23.810350 <6>[ 16.969497] mt7921e 0000:01:00.0: ASIC revision: 79610010
10823 14:00:23.820460 <3>[ 16.976687] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10824 14:00:23.826857 <3>[ 16.977547] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10825 14:00:23.836725 <3>[ 17.023771] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10826 14:00:23.844048 <3>[ 17.024660] power_supply sbs-5-000b: driver failed to report `charge_full_design' property: -6
10827 14:00:23.853426 <3>[ 17.033530] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10828 14:00:23.866480 <4>[ 17.068239] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10829 14:00:23.876732 <4>[ 17.179153] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10830 14:00:23.886480 <4>[ 17.287294] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10831 14:00:23.889753 _backlight[0m...
10832 14:00:23.914059 Starting [0;1;39mNetwork Name Resolution[0m...
10833 14:00:23.926902 <4>[ 17.400712] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10834 14:00:23.938725 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10835 14:00:23.960826 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10836 14:00:24.026719 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10837 14:00:24.038736 <4>[ 17.511614] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10838 14:00:24.146347 <4>[ 17.619345] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10839 14:00:24.166360 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10840 14:00:24.180001 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10841 14:00:24.199280 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10842 14:00:24.212323 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10843 14:00:24.231583 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10844 14:00:24.254462 <4>[ 17.727982] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10845 14:00:24.261115 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10846 14:00:24.275800 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10847 14:00:24.296346 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10848 14:00:24.312446 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10849 14:00:24.327699 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10850 14:00:24.362370 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkil<4>[ 17.835776] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10851 14:00:24.362500 l Watch[0m.
10852 14:00:24.397009 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10853 14:00:24.432570 Starting [0;1;39mUser Login Management[0m...
10854 14:00:24.470744 Starting [0;1;39mPermit User Sessions<4>[ 17.945193] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10855 14:00:24.470832 [0m...
10856 14:00:24.496607 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10857 14:00:24.549077 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10858 14:00:24.588087 [[0;32m OK [0m] Started [0;<4>[ 18.060080] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10859 14:00:24.591231 1;39mSerial Getty on ttyS0[0m.
10860 14:00:24.609042 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10861 14:00:24.648585 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10862 14:00:24.665256 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10863 14:00:24.682904 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10864 14:00:24.689649 <3>[ 18.166248] mt7921e 0000:01:00.0: hardware init failed
10865 14:00:24.689729
10866 14:00:24.706052 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10867 14:00:24.720045 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10868 14:00:24.772250 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10869 14:00:24.800933 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10870 14:00:24.856236
10871 14:00:24.856333
10872 14:00:24.859340 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10873 14:00:24.859414
10874 14:00:24.862799 debian-bullseye-arm64 login: root (automatic login)
10875 14:00:24.862882
10876 14:00:24.862949
10877 14:00:24.879910 Linux debian-bullseye-arm64 6.1.46-cip4-rt2 #1 SMP PREEMPT Mon Aug 28 13:41:26 UTC 2023 aarch64
10878 14:00:24.880010
10879 14:00:24.886999 The programs included with the Debian GNU/Linux system are free software;
10880 14:00:24.893591 the exact distribution terms for each program are described in the
10881 14:00:24.896853 individual files in /usr/share/doc/*/copyright.
10882 14:00:24.896933
10883 14:00:24.903233 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10884 14:00:24.906284 permitted by applicable law.
10885 14:00:24.906610 Matched prompt #10: / #
10887 14:00:24.906811 Setting prompt string to ['/ #']
10888 14:00:24.906900 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10890 14:00:24.907086 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10891 14:00:24.907170 start: 2.2.6 expect-shell-connection (timeout 00:02:50) [common]
10892 14:00:24.907239 Setting prompt string to ['/ #']
10893 14:00:24.907298 Forcing a shell prompt, looking for ['/ #']
10895 14:00:24.957508 / #
10896 14:00:24.957611 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10897 14:00:24.957685 Waiting using forced prompt support (timeout 00:02:30)
10898 14:00:24.962372
10899 14:00:24.962643 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10900 14:00:24.962740 start: 2.2.7 export-device-env (timeout 00:02:50) [common]
10901 14:00:24.962833 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10902 14:00:24.962918 end: 2.2 depthcharge-retry (duration 00:02:10) [common]
10903 14:00:24.963000 end: 2 depthcharge-action (duration 00:02:10) [common]
10904 14:00:24.963086 start: 3 lava-test-retry (timeout 00:05:00) [common]
10905 14:00:24.963170 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10906 14:00:24.963239 Using namespace: common
10908 14:00:25.063567 / # #
10909 14:00:25.063702 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10910 14:00:25.071040 #<6>[ 18.546436] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307c7b: link becomes ready
10911 14:00:25.071123
10912 14:00:25.077453 <6>[ 18.547008] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10913 14:00:25.077717 Using /lava-11372179
10915 14:00:25.178020 / # export SHELL=/bin/sh
10916 14:00:25.182917 export SHELL=/bin/sh
10918 14:00:25.283438 / # . /lava-11372179/environment
10919 14:00:25.289110 . /lava-11372179/environment
10921 14:00:25.389636 / # /lava-11372179/bin/lava-test-runner /lava-11372179/0
10922 14:00:25.389751 Test shell timeout: 10s (minimum of the action and connection timeout)
10923 14:00:25.395050 /lava-11372179/bin/lava-test-runner /lava-11372179/0
10924 14:00:25.415851 + export TESTRUN_ID=0_cros-ec
10925 14:00:25.425855 + cd /lava-11372179/0/tests/0_cro<8>[ 18.903297] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11372179_1.5.2.3.1>
10926 14:00:25.425944 s-ec
10927 14:00:25.426205 Received signal: <STARTRUN> 0_cros-ec 11372179_1.5.2.3.1
10928 14:00:25.426283 Starting test lava.0_cros-ec (11372179_1.5.2.3.1)
10929 14:00:25.426389 Skipping test definition patterns.
10930 14:00:25.428966 + cat uuid
10931 14:00:25.429050 + UUID=11372179_1.5.2.3.1
10932 14:00:25.429137 + set +x
10933 14:00:25.435320 + python3 -m cros.runners.lava_runner -v
10934 14:00:25.812268 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
10935 14:00:25.822115 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
10936 14:00:25.822197
10937 14:00:25.828954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
10938 14:00:25.829210 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10940 14:00:25.835256 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
10941 14:00:25.842437 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
10942 14:00:25.842517
10943 14:00:25.852527 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8
10944 14:00:25.852618 Bad test result: ski<8
10945 14:00:25.855218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8>[ 19.336397] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11372179_1.5.2.3.1>
10946 14:00:25.855469 Received signal: <ENDRUN> 0_cros-ec 11372179_1.5.2.3.1
10947 14:00:25.855547 Ending use of test pattern.
10948 14:00:25.855609 Ending test lava.0_cros-ec (11372179_1.5.2.3.1), duration 0.43
10950 14:00:25.858422 p>
10951 14:00:25.862307 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
10952 14:00:25.868538 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
10953 14:00:25.868622
10954 14:00:25.875565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
10955 14:00:25.875814 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
10957 14:00:25.881611 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10958 14:00:25.887869 Checks the standard ABI for the main Embedded Controller. ... ok
10959 14:00:25.887967
10960 14:00:25.891487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
10961 14:00:25.891738 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
10963 14:00:25.897985 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
10964 14:00:25.904473 Checks the main Embedded controller character device. ... ok
10965 14:00:25.904555
10966 14:00:25.908543 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
10968 14:00:25.911437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
10969 14:00:25.914777 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10970 14:00:25.921306 Checks basic comunication with the main Embedded controller. ... ok
10971 14:00:25.921386
10972 14:00:25.927606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
10973 14:00:25.927889 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
10975 14:00:25.931279 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10976 14:00:25.941275 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
10977 14:00:25.941356
10978 14:00:25.944554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
10979 14:00:25.944806 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
10981 14:00:25.950919 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10982 14:00:25.957561 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
10983 14:00:25.960524
10984 14:00:25.964587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
10985 14:00:25.964837 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
10987 14:00:25.971130 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
10988 14:00:25.977247 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
10989 14:00:25.977328
10990 14:00:25.983766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
10991 14:00:25.984017 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
10993 14:00:25.987415 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10994 14:00:25.997193 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
10995 14:00:25.997275
10996 14:00:26.000030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
10997 14:00:26.000326 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
10999 14:00:26.006744 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11000 14:00:26.016705 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11001 14:00:26.016788
11002 14:00:26.020201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11003 14:00:26.020454 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11005 14:00:26.027082 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11006 14:00:26.034553 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11007 14:00:26.034680
11008 14:00:26.040020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11009 14:00:26.040344 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11011 14:00:26.046960 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11012 14:00:26.053303 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11013 14:00:26.053387
11014 14:00:26.059816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11015 14:00:26.060070 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11017 14:00:26.066154 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11018 14:00:26.073350 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11019 14:00:26.073431
11020 14:00:26.079286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11021 14:00:26.079538 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11023 14:00:26.086172 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11024 14:00:26.092950 Check the cros battery ABI. ... skipped 'No BAT found'
11025 14:00:26.093032
11026 14:00:26.099501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11027 14:00:26.099756 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11029 14:00:26.106236 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11030 14:00:26.112555 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11031 14:00:26.112633
11032 14:00:26.119239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11033 14:00:26.119514 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11035 14:00:26.122854 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11036 14:00:26.132083 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11037 14:00:26.132168
11038 14:00:26.135733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11039 14:00:26.136020 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11041 14:00:26.142010 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11042 14:00:26.148709 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11043 14:00:26.148792
11044 14:00:26.155238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11045 14:00:26.155321
11046 14:00:26.155580 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11048 14:00:26.161633 ----------------------------------------------------------------------
11049 14:00:26.165786 Ran 18 tests in 0.007s
11050 14:00:26.165870
11051 14:00:26.165954 OK (skipped=15)
11052 14:00:26.168331 + set +x
11053 14:00:26.168416 <LAVA_TEST_RUNNER EXIT>
11054 14:00:26.168692 ok: lava_test_shell seems to have completed
11055 14:00:26.168904 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11056 14:00:26.169013 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11057 14:00:26.169112 end: 3 lava-test-retry (duration 00:00:01) [common]
11058 14:00:26.169216 start: 4 finalize (timeout 00:07:27) [common]
11059 14:00:26.169348 start: 4.1 power-off (timeout 00:00:30) [common]
11060 14:00:26.169634 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11061 14:00:26.239417 >> Command sent successfully.
11062 14:00:26.241854 Returned 0 in 0 seconds
11063 14:00:26.342229 end: 4.1 power-off (duration 00:00:00) [common]
11065 14:00:26.342560 start: 4.2 read-feedback (timeout 00:07:26) [common]
11066 14:00:26.342827 Listened to connection for namespace 'common' for up to 1s
11067 14:00:27.343780 Finalising connection for namespace 'common'
11068 14:00:27.343980 Disconnecting from shell: Finalise
11069 14:00:27.344083 / #
11070 14:00:27.444423 end: 4.2 read-feedback (duration 00:00:01) [common]
11071 14:00:27.444585 end: 4 finalize (duration 00:00:01) [common]
11072 14:00:27.444719 Cleaning after the job
11073 14:00:27.444839 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/ramdisk
11074 14:00:27.451335 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/kernel
11075 14:00:27.459709 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/dtb
11076 14:00:27.459889 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372179/tftp-deploy-x_1saco3/modules
11077 14:00:27.467078 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11372179
11078 14:00:27.582584 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11372179
11079 14:00:27.582764 Job finished correctly