Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 40
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 61
1 13:57:41.315172 lava-dispatcher, installed at version: 2023.06
2 13:57:41.315416 start: 0 validate
3 13:57:41.315572 Start time: 2023-08-28 13:57:41.315559+00:00 (UTC)
4 13:57:41.315720 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:57:41.315877 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:57:41.585879 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:57:41.586764 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:57:41.857833 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:57:41.858643 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:58:06.606136 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:58:06.606871 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.46-cip4-rt2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:58:07.135731 validate duration: 25.82
14 13:58:07.137038 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:58:07.137835 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:58:07.138376 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:58:07.139112 Not decompressing ramdisk as can be used compressed.
18 13:58:07.139596 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 13:58:07.139979 saving as /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/ramdisk/rootfs.cpio.gz
20 13:58:07.140348 total size: 26246609 (25 MB)
21 13:58:10.488311 progress 0 % (0 MB)
22 13:58:10.498753 progress 5 % (1 MB)
23 13:58:10.505939 progress 10 % (2 MB)
24 13:58:10.513033 progress 15 % (3 MB)
25 13:58:10.520201 progress 20 % (5 MB)
26 13:58:10.527131 progress 25 % (6 MB)
27 13:58:10.533881 progress 30 % (7 MB)
28 13:58:10.540644 progress 35 % (8 MB)
29 13:58:10.547428 progress 40 % (10 MB)
30 13:58:10.554231 progress 45 % (11 MB)
31 13:58:10.560968 progress 50 % (12 MB)
32 13:58:10.567750 progress 55 % (13 MB)
33 13:58:10.574453 progress 60 % (15 MB)
34 13:58:10.581237 progress 65 % (16 MB)
35 13:58:10.588111 progress 70 % (17 MB)
36 13:58:10.594873 progress 75 % (18 MB)
37 13:58:10.601694 progress 80 % (20 MB)
38 13:58:10.608558 progress 85 % (21 MB)
39 13:58:10.615304 progress 90 % (22 MB)
40 13:58:10.622150 progress 95 % (23 MB)
41 13:58:10.628875 progress 100 % (25 MB)
42 13:58:10.629130 25 MB downloaded in 3.49 s (7.17 MB/s)
43 13:58:10.629285 end: 1.1.1 http-download (duration 00:00:03) [common]
45 13:58:10.629525 end: 1.1 download-retry (duration 00:00:03) [common]
46 13:58:10.629643 start: 1.2 download-retry (timeout 00:09:57) [common]
47 13:58:10.629726 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 13:58:10.629862 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:58:10.629970 saving as /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/kernel/Image
50 13:58:10.630046 total size: 49222144 (46 MB)
51 13:58:10.630107 No compression specified
52 13:58:10.631283 progress 0 % (0 MB)
53 13:58:10.644088 progress 5 % (2 MB)
54 13:58:10.656781 progress 10 % (4 MB)
55 13:58:10.669673 progress 15 % (7 MB)
56 13:58:10.682466 progress 20 % (9 MB)
57 13:58:10.695437 progress 25 % (11 MB)
58 13:58:10.708209 progress 30 % (14 MB)
59 13:58:10.721165 progress 35 % (16 MB)
60 13:58:10.734134 progress 40 % (18 MB)
61 13:58:10.747089 progress 45 % (21 MB)
62 13:58:10.760040 progress 50 % (23 MB)
63 13:58:10.772845 progress 55 % (25 MB)
64 13:58:10.785622 progress 60 % (28 MB)
65 13:58:10.798475 progress 65 % (30 MB)
66 13:58:10.811263 progress 70 % (32 MB)
67 13:58:10.824262 progress 75 % (35 MB)
68 13:58:10.837130 progress 80 % (37 MB)
69 13:58:10.850162 progress 85 % (39 MB)
70 13:58:10.862825 progress 90 % (42 MB)
71 13:58:10.875546 progress 95 % (44 MB)
72 13:58:10.888193 progress 100 % (46 MB)
73 13:58:10.888355 46 MB downloaded in 0.26 s (181.73 MB/s)
74 13:58:10.888512 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:58:10.888749 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:58:10.888837 start: 1.3 download-retry (timeout 00:09:56) [common]
78 13:58:10.888929 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 13:58:10.889071 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:58:10.889141 saving as /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/dtb/mt8192-asurada-spherion-r0.dtb
81 13:58:10.889202 total size: 47278 (0 MB)
82 13:58:10.889262 No compression specified
83 13:58:10.890414 progress 69 % (0 MB)
84 13:58:10.890700 progress 100 % (0 MB)
85 13:58:10.890864 0 MB downloaded in 0.00 s (27.16 MB/s)
86 13:58:10.890988 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:58:10.891209 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:58:10.891294 start: 1.4 download-retry (timeout 00:09:56) [common]
90 13:58:10.891377 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 13:58:10.891491 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.46-cip4-rt2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:58:10.891559 saving as /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/modules/modules.tar
93 13:58:10.891619 total size: 8615960 (8 MB)
94 13:58:10.891680 Using unxz to decompress xz
95 13:58:10.895932 progress 0 % (0 MB)
96 13:58:10.917293 progress 5 % (0 MB)
97 13:58:10.939732 progress 10 % (0 MB)
98 13:58:10.965839 progress 15 % (1 MB)
99 13:58:10.991245 progress 20 % (1 MB)
100 13:58:11.016548 progress 25 % (2 MB)
101 13:58:11.043125 progress 30 % (2 MB)
102 13:58:11.069876 progress 35 % (2 MB)
103 13:58:11.094699 progress 40 % (3 MB)
104 13:58:11.118563 progress 45 % (3 MB)
105 13:58:11.145087 progress 50 % (4 MB)
106 13:58:11.170414 progress 55 % (4 MB)
107 13:58:11.195001 progress 60 % (4 MB)
108 13:58:11.217488 progress 65 % (5 MB)
109 13:58:11.244746 progress 70 % (5 MB)
110 13:58:11.268798 progress 75 % (6 MB)
111 13:58:11.295108 progress 80 % (6 MB)
112 13:58:11.325525 progress 85 % (7 MB)
113 13:58:11.352058 progress 90 % (7 MB)
114 13:58:11.376224 progress 95 % (7 MB)
115 13:58:11.399509 progress 100 % (8 MB)
116 13:58:11.405759 8 MB downloaded in 0.51 s (15.98 MB/s)
117 13:58:11.406003 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:58:11.406260 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:58:11.406355 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 13:58:11.406452 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 13:58:11.406535 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:58:11.406634 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 13:58:11.406865 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af
125 13:58:11.407003 makedir: /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin
126 13:58:11.407111 makedir: /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/tests
127 13:58:11.407211 makedir: /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/results
128 13:58:11.407330 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-add-keys
129 13:58:11.407483 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-add-sources
130 13:58:11.407621 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-background-process-start
131 13:58:11.407761 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-background-process-stop
132 13:58:11.407892 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-common-functions
133 13:58:11.408024 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-echo-ipv4
134 13:58:11.408155 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-install-packages
135 13:58:11.408284 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-installed-packages
136 13:58:11.408412 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-os-build
137 13:58:11.408540 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-probe-channel
138 13:58:11.408668 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-probe-ip
139 13:58:11.408796 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-target-ip
140 13:58:11.408923 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-target-mac
141 13:58:11.409051 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-target-storage
142 13:58:11.409185 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-test-case
143 13:58:11.409314 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-test-event
144 13:58:11.409442 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-test-feedback
145 13:58:11.409570 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-test-raise
146 13:58:11.409702 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-test-reference
147 13:58:11.409832 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-test-runner
148 13:58:11.409959 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-test-set
149 13:58:11.410091 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-test-shell
150 13:58:11.410222 Updating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-install-packages (oe)
151 13:58:11.410382 Updating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/bin/lava-installed-packages (oe)
152 13:58:11.410509 Creating /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/environment
153 13:58:11.410616 LAVA metadata
154 13:58:11.410693 - LAVA_JOB_ID=11372172
155 13:58:11.410758 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:58:11.410860 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 13:58:11.410927 skipped lava-vland-overlay
158 13:58:11.411002 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:58:11.411086 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 13:58:11.411150 skipped lava-multinode-overlay
161 13:58:11.411222 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:58:11.411305 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 13:58:11.411381 Loading test definitions
164 13:58:11.411470 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 13:58:11.411543 Using /lava-11372172 at stage 0
166 13:58:11.411865 uuid=11372172_1.5.2.3.1 testdef=None
167 13:58:11.411953 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:58:11.412040 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 13:58:11.412565 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:58:11.412781 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 13:58:11.413408 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:58:11.413638 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 13:58:11.414237 runner path: /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11372172_1.5.2.3.1
176 13:58:11.414395 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:58:11.414603 Creating lava-test-runner.conf files
179 13:58:11.414668 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11372172/lava-overlay-n85dv1af/lava-11372172/0 for stage 0
180 13:58:11.414760 - 0_v4l2-compliance-mtk-vcodec-enc
181 13:58:11.414857 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:58:11.414947 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
183 13:58:11.421735 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:58:11.421845 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
185 13:58:11.421932 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:58:11.422019 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:58:11.422105 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
188 13:58:12.140794 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:58:12.141196 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
190 13:58:12.141323 extracting modules file /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11372172/extract-overlay-ramdisk-lkgsa6fl/ramdisk
191 13:58:12.389140 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:58:12.389411 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
193 13:58:12.389522 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11372172/compress-overlay-g0niv064/overlay-1.5.2.4.tar.gz to ramdisk
194 13:58:12.389597 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11372172/compress-overlay-g0niv064/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11372172/extract-overlay-ramdisk-lkgsa6fl/ramdisk
195 13:58:12.396399 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:58:12.396511 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
197 13:58:12.396604 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:58:12.396694 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
199 13:58:12.396774 Building ramdisk /var/lib/lava/dispatcher/tmp/11372172/extract-overlay-ramdisk-lkgsa6fl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11372172/extract-overlay-ramdisk-lkgsa6fl/ramdisk
200 13:58:13.016711 >> 228254 blocks
201 13:58:16.893799 rename /var/lib/lava/dispatcher/tmp/11372172/extract-overlay-ramdisk-lkgsa6fl/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/ramdisk/ramdisk.cpio.gz
202 13:58:16.894255 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 13:58:16.894383 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 13:58:16.894488 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 13:58:16.894627 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/kernel/Image'
206 13:58:29.411286 Returned 0 in 12 seconds
207 13:58:29.512405 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/kernel/image.itb
208 13:58:30.142615 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:58:30.143084 output: Created: Mon Aug 28 14:58:30 2023
210 13:58:30.143167 output: Image 0 (kernel-1)
211 13:58:30.143233 output: Description:
212 13:58:30.143296 output: Created: Mon Aug 28 14:58:30 2023
213 13:58:30.143361 output: Type: Kernel Image
214 13:58:30.143422 output: Compression: lzma compressed
215 13:58:30.143480 output: Data Size: 11039834 Bytes = 10781.09 KiB = 10.53 MiB
216 13:58:30.143540 output: Architecture: AArch64
217 13:58:30.143597 output: OS: Linux
218 13:58:30.143651 output: Load Address: 0x00000000
219 13:58:30.143705 output: Entry Point: 0x00000000
220 13:58:30.143757 output: Hash algo: crc32
221 13:58:30.143809 output: Hash value: 946c5cd4
222 13:58:30.143861 output: Image 1 (fdt-1)
223 13:58:30.143913 output: Description: mt8192-asurada-spherion-r0
224 13:58:30.143965 output: Created: Mon Aug 28 14:58:30 2023
225 13:58:30.144017 output: Type: Flat Device Tree
226 13:58:30.144069 output: Compression: uncompressed
227 13:58:30.144121 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:58:30.144173 output: Architecture: AArch64
229 13:58:30.144225 output: Hash algo: crc32
230 13:58:30.144276 output: Hash value: cc4352de
231 13:58:30.144327 output: Image 2 (ramdisk-1)
232 13:58:30.144379 output: Description: unavailable
233 13:58:30.144431 output: Created: Mon Aug 28 14:58:30 2023
234 13:58:30.144483 output: Type: RAMDisk Image
235 13:58:30.144535 output: Compression: Unknown Compression
236 13:58:30.144587 output: Data Size: 39351776 Bytes = 38429.47 KiB = 37.53 MiB
237 13:58:30.144639 output: Architecture: AArch64
238 13:58:30.144690 output: OS: Linux
239 13:58:30.144742 output: Load Address: unavailable
240 13:58:30.144793 output: Entry Point: unavailable
241 13:58:30.144845 output: Hash algo: crc32
242 13:58:30.144897 output: Hash value: 1d739b33
243 13:58:30.144948 output: Default Configuration: 'conf-1'
244 13:58:30.145041 output: Configuration 0 (conf-1)
245 13:58:30.145094 output: Description: mt8192-asurada-spherion-r0
246 13:58:30.145146 output: Kernel: kernel-1
247 13:58:30.145198 output: Init Ramdisk: ramdisk-1
248 13:58:30.145249 output: FDT: fdt-1
249 13:58:30.145300 output: Loadables: kernel-1
250 13:58:30.145352 output:
251 13:58:30.145547 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 13:58:30.145643 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 13:58:30.145746 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 13:58:30.145855 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 13:58:30.145944 No LXC device requested
256 13:58:30.146022 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:58:30.146109 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 13:58:30.146205 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:58:30.146287 Checking files for TFTP limit of 4294967296 bytes.
260 13:58:30.146882 end: 1 tftp-deploy (duration 00:00:23) [common]
261 13:58:30.146985 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:58:30.147073 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:58:30.147193 substitutions:
264 13:58:30.147259 - {DTB}: 11372172/tftp-deploy-mxyag6t_/dtb/mt8192-asurada-spherion-r0.dtb
265 13:58:30.147326 - {INITRD}: 11372172/tftp-deploy-mxyag6t_/ramdisk/ramdisk.cpio.gz
266 13:58:30.147384 - {KERNEL}: 11372172/tftp-deploy-mxyag6t_/kernel/Image
267 13:58:30.147440 - {LAVA_MAC}: None
268 13:58:30.147495 - {PRESEED_CONFIG}: None
269 13:58:30.147550 - {PRESEED_LOCAL}: None
270 13:58:30.147603 - {RAMDISK}: 11372172/tftp-deploy-mxyag6t_/ramdisk/ramdisk.cpio.gz
271 13:58:30.147657 - {ROOT_PART}: None
272 13:58:30.147711 - {ROOT}: None
273 13:58:30.147764 - {SERVER_IP}: 192.168.201.1
274 13:58:30.147817 - {TEE}: None
275 13:58:30.147870 Parsed boot commands:
276 13:58:30.147922 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:58:30.148102 Parsed boot commands: tftpboot 192.168.201.1 11372172/tftp-deploy-mxyag6t_/kernel/image.itb 11372172/tftp-deploy-mxyag6t_/kernel/cmdline
278 13:58:30.148190 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:58:30.148275 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:58:30.148369 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:58:30.148451 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:58:30.148520 Not connected, no need to disconnect.
283 13:58:30.148592 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:58:30.148669 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:58:30.148736 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 13:58:30.152822 Setting prompt string to ['lava-test: # ']
287 13:58:30.153176 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:58:30.153284 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:58:30.153402 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:58:30.153519 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:58:30.153759 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 13:58:35.302253 >> Command sent successfully.
293 13:58:35.308408 Returned 0 in 5 seconds
294 13:58:35.409106 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:58:35.410698 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:58:35.411259 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:58:35.411737 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:58:35.412126 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:58:35.412512 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:58:35.413841 [Enter `^Ec?' for help]
302 13:58:35.578931
303 13:58:35.579421
304 13:58:35.579760 F0: 102B 0000
305 13:58:35.580080
306 13:58:35.580382 F3: 1001 0000 [0200]
307 13:58:35.580680
308 13:58:35.582901 F3: 1001 0000
309 13:58:35.583326
310 13:58:35.583661 F7: 102D 0000
311 13:58:35.583977
312 13:58:35.586645 F1: 0000 0000
313 13:58:35.587102
314 13:58:35.587497 V0: 0000 0000 [0001]
315 13:58:35.587824
316 13:58:35.588128 00: 0007 8000
317 13:58:35.588434
318 13:58:35.589552 01: 0000 0000
319 13:58:35.589983
320 13:58:35.590320 BP: 0C00 0209 [0000]
321 13:58:35.590681
322 13:58:35.593658 G0: 1182 0000
323 13:58:35.594085
324 13:58:35.594423 EC: 0000 0021 [4000]
325 13:58:35.594891
326 13:58:35.597532 S7: 0000 0000 [0000]
327 13:58:35.597955
328 13:58:35.598320 CC: 0000 0000 [0001]
329 13:58:35.598834
330 13:58:35.600691 T0: 0000 0040 [010F]
331 13:58:35.601154
332 13:58:35.601493 Jump to BL
333 13:58:35.601808
334 13:58:35.626357
335 13:58:35.626831
336 13:58:35.627170
337 13:58:35.632568 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 13:58:35.635812 ARM64: Exception handlers installed.
339 13:58:35.639965 ARM64: Testing exception
340 13:58:35.643114 ARM64: Done test exception
341 13:58:35.649726 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 13:58:35.660938 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 13:58:35.667903 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 13:58:35.678979 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 13:58:35.685075 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 13:58:35.692108 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 13:58:35.702222 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 13:58:35.708979 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 13:58:35.728191 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 13:58:35.731698 WDT: Last reset was cold boot
351 13:58:35.734922 SPI1(PAD0) initialized at 2873684 Hz
352 13:58:35.738160 SPI5(PAD0) initialized at 992727 Hz
353 13:58:35.741637 VBOOT: Loading verstage.
354 13:58:35.748458 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 13:58:35.751277 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 13:58:35.754745 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 13:58:35.757812 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 13:58:35.766010 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 13:58:35.772330 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 13:58:35.783132 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 13:58:35.783361
362 13:58:35.783541
363 13:58:35.793736 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 13:58:35.796565 ARM64: Exception handlers installed.
365 13:58:35.800854 ARM64: Testing exception
366 13:58:35.800936 ARM64: Done test exception
367 13:58:35.807380 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 13:58:35.809643 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 13:58:35.823906 Probing TPM: . done!
370 13:58:35.823989 TPM ready after 0 ms
371 13:58:35.831218 Connected to device vid:did:rid of 1ae0:0028:00
372 13:58:35.840959 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 13:58:35.878916 Initialized TPM device CR50 revision 0
374 13:58:35.891531 tlcl_send_startup: Startup return code is 0
375 13:58:35.891922 TPM: setup succeeded
376 13:58:35.902949 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 13:58:35.911278 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:58:35.921670 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 13:58:35.930334 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 13:58:35.933828 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 13:58:35.936512 in-header: 03 07 00 00 08 00 00 00
382 13:58:35.939842 in-data: aa e4 47 04 13 02 00 00
383 13:58:35.943551 Chrome EC: UHEPI supported
384 13:58:35.950317 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 13:58:35.954421 in-header: 03 ad 00 00 08 00 00 00
386 13:58:35.957192 in-data: 00 20 20 08 00 00 00 00
387 13:58:35.957639 Phase 1
388 13:58:35.960280 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 13:58:35.966987 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 13:58:35.973902 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 13:58:35.976950 Recovery requested (1009000e)
392 13:58:35.983778 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:58:35.989430 tlcl_extend: response is 0
394 13:58:35.997528 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:58:36.002664 tlcl_extend: response is 0
396 13:58:36.009320 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:58:36.029626 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 13:58:36.036550 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:58:36.036981
400 13:58:36.037326
401 13:58:36.047604 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:58:36.051373 ARM64: Exception handlers installed.
403 13:58:36.051849 ARM64: Testing exception
404 13:58:36.054233 ARM64: Done test exception
405 13:58:36.075613 pmic_efuse_setting: Set efuses in 11 msecs
406 13:58:36.079156 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:58:36.082670 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:58:36.089927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:58:36.093909 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:58:36.099504 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:58:36.102898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:58:36.110278 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:58:36.113692 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:58:36.119845 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:58:36.123239 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:58:36.126495 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:58:36.134124 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:58:36.136258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:58:36.139923 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:58:36.147766 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:58:36.153730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:58:36.160352 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:58:36.163533 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:58:36.169753 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:58:36.176563 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:58:36.183564 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:58:36.186424 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:58:36.193774 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:58:36.197621 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:58:36.205467 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:58:36.209578 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:58:36.215252 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:58:36.218961 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:58:36.225213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:58:36.228758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:58:36.235946 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:58:36.239861 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:58:36.243103 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:58:36.249761 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:58:36.253947 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:58:36.260184 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:58:36.263602 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:58:36.270257 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:58:36.273744 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:58:36.280634 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:58:36.283709 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:58:36.288055 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:58:36.290693 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:58:36.297788 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:58:36.301125 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:58:36.304403 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:58:36.311380 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:58:36.314927 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:58:36.318175 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:58:36.321325 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:58:36.328072 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:58:36.331109 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:58:36.338111 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 13:58:36.347975 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:58:36.351022 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:58:36.361321 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:58:36.367982 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:58:36.371015 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:58:36.377987 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:58:36.381650 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:58:36.388103 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1d
467 13:58:36.394774 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:58:36.398428 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 13:58:36.404526 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:58:36.412998 [RTC]rtc_get_frequency_meter,154: input=15, output=834
471 13:58:36.422504 [RTC]rtc_get_frequency_meter,154: input=7, output=709
472 13:58:36.431594 [RTC]rtc_get_frequency_meter,154: input=11, output=772
473 13:58:36.441250 [RTC]rtc_get_frequency_meter,154: input=13, output=804
474 13:58:36.450925 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 13:58:36.460040 [RTC]rtc_get_frequency_meter,154: input=12, output=788
476 13:58:36.469478 [RTC]rtc_get_frequency_meter,154: input=13, output=805
477 13:58:36.472913 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 13:58:36.480143 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 13:58:36.483791 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 13:58:36.486759 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 13:58:36.493328 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 13:58:36.496696 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 13:58:36.500263 ADC[4]: Raw value=903031 ID=7
484 13:58:36.500732 ADC[3]: Raw value=213652 ID=1
485 13:58:36.503080 RAM Code: 0x71
486 13:58:36.507183 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 13:58:36.513502 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 13:58:36.520024 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 13:58:36.526537 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 13:58:36.529895 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 13:58:36.533752 in-header: 03 07 00 00 08 00 00 00
492 13:58:36.536538 in-data: aa e4 47 04 13 02 00 00
493 13:58:36.540036 Chrome EC: UHEPI supported
494 13:58:36.546732 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 13:58:36.549789 in-header: 03 dd 00 00 08 00 00 00
496 13:58:36.553980 in-data: 90 20 60 08 00 00 00 00
497 13:58:36.556712 MRC: failed to locate region type 0.
498 13:58:36.562848 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 13:58:36.566069 DRAM-K: Running full calibration
500 13:58:36.572927 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 13:58:36.573527 header.status = 0x0
502 13:58:36.576335 header.version = 0x6 (expected: 0x6)
503 13:58:36.579416 header.size = 0xd00 (expected: 0xd00)
504 13:58:36.583313 header.flags = 0x0
505 13:58:36.589830 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 13:58:36.606747 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 13:58:36.613607 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 13:58:36.616595 dram_init: ddr_geometry: 2
509 13:58:36.620209 [EMI] MDL number = 2
510 13:58:36.620777 [EMI] Get MDL freq = 0
511 13:58:36.623288 dram_init: ddr_type: 0
512 13:58:36.623854 is_discrete_lpddr4: 1
513 13:58:36.626513 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 13:58:36.627114
515 13:58:36.627486
516 13:58:36.630183 [Bian_co] ETT version 0.0.0.1
517 13:58:36.636238 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 13:58:36.636711
519 13:58:36.640070 dramc_set_vcore_voltage set vcore to 650000
520 13:58:36.643410 Read voltage for 800, 4
521 13:58:36.643879 Vio18 = 0
522 13:58:36.644254 Vcore = 650000
523 13:58:36.646942 Vdram = 0
524 13:58:36.647498 Vddq = 0
525 13:58:36.647872 Vmddr = 0
526 13:58:36.649718 dram_init: config_dvfs: 1
527 13:58:36.652955 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 13:58:36.659687 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 13:58:36.663006 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 13:58:36.666513 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 13:58:36.669506 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 13:58:36.676219 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 13:58:36.676691 MEM_TYPE=3, freq_sel=18
534 13:58:36.679387 sv_algorithm_assistance_LP4_1600
535 13:58:36.682749 ============ PULL DRAM RESETB DOWN ============
536 13:58:36.689593 ========== PULL DRAM RESETB DOWN end =========
537 13:58:36.692975 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 13:58:36.696099 ===================================
539 13:58:36.699914 LPDDR4 DRAM CONFIGURATION
540 13:58:36.702802 ===================================
541 13:58:36.703272 EX_ROW_EN[0] = 0x0
542 13:58:36.706158 EX_ROW_EN[1] = 0x0
543 13:58:36.706667 LP4Y_EN = 0x0
544 13:58:36.709777 WORK_FSP = 0x0
545 13:58:36.710395 WL = 0x2
546 13:58:36.712755 RL = 0x2
547 13:58:36.713315 BL = 0x2
548 13:58:36.715867 RPST = 0x0
549 13:58:36.716337 RD_PRE = 0x0
550 13:58:36.719658 WR_PRE = 0x1
551 13:58:36.720180 WR_PST = 0x0
552 13:58:36.723217 DBI_WR = 0x0
553 13:58:36.726199 DBI_RD = 0x0
554 13:58:36.726769 OTF = 0x1
555 13:58:36.729390 ===================================
556 13:58:36.732733 ===================================
557 13:58:36.733304 ANA top config
558 13:58:36.736178 ===================================
559 13:58:36.739519 DLL_ASYNC_EN = 0
560 13:58:36.743185 ALL_SLAVE_EN = 1
561 13:58:36.745739 NEW_RANK_MODE = 1
562 13:58:36.749426 DLL_IDLE_MODE = 1
563 13:58:36.749947 LP45_APHY_COMB_EN = 1
564 13:58:36.752934 TX_ODT_DIS = 1
565 13:58:36.756627 NEW_8X_MODE = 1
566 13:58:36.759394 ===================================
567 13:58:36.762634 ===================================
568 13:58:36.766103 data_rate = 1600
569 13:58:36.769301 CKR = 1
570 13:58:36.769874 DQ_P2S_RATIO = 8
571 13:58:36.773153 ===================================
572 13:58:36.776001 CA_P2S_RATIO = 8
573 13:58:36.779230 DQ_CA_OPEN = 0
574 13:58:36.782536 DQ_SEMI_OPEN = 0
575 13:58:36.786061 CA_SEMI_OPEN = 0
576 13:58:36.789295 CA_FULL_RATE = 0
577 13:58:36.789817 DQ_CKDIV4_EN = 1
578 13:58:36.792182 CA_CKDIV4_EN = 1
579 13:58:36.795987 CA_PREDIV_EN = 0
580 13:58:36.799151 PH8_DLY = 0
581 13:58:36.802740 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 13:58:36.805904 DQ_AAMCK_DIV = 4
583 13:58:36.806419 CA_AAMCK_DIV = 4
584 13:58:36.809108 CA_ADMCK_DIV = 4
585 13:58:36.812257 DQ_TRACK_CA_EN = 0
586 13:58:36.815527 CA_PICK = 800
587 13:58:36.819746 CA_MCKIO = 800
588 13:58:36.822696 MCKIO_SEMI = 0
589 13:58:36.825588 PLL_FREQ = 3068
590 13:58:36.826052 DQ_UI_PI_RATIO = 32
591 13:58:36.828723 CA_UI_PI_RATIO = 0
592 13:58:36.832079 ===================================
593 13:58:36.835611 ===================================
594 13:58:36.839077 memory_type:LPDDR4
595 13:58:36.842423 GP_NUM : 10
596 13:58:36.843041 SRAM_EN : 1
597 13:58:36.846227 MD32_EN : 0
598 13:58:36.849421 ===================================
599 13:58:36.849979 [ANA_INIT] >>>>>>>>>>>>>>
600 13:58:36.852648 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 13:58:36.855656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 13:58:36.858763 ===================================
603 13:58:36.862236 data_rate = 1600,PCW = 0X7600
604 13:58:36.865755 ===================================
605 13:58:36.868704 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 13:58:36.875493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:58:36.882690 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 13:58:36.885658 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 13:58:36.889301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:58:36.892373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 13:58:36.895344 [ANA_INIT] flow start
612 13:58:36.895845 [ANA_INIT] PLL >>>>>>>>
613 13:58:36.898478 [ANA_INIT] PLL <<<<<<<<
614 13:58:36.902157 [ANA_INIT] MIDPI >>>>>>>>
615 13:58:36.902777 [ANA_INIT] MIDPI <<<<<<<<
616 13:58:36.905505 [ANA_INIT] DLL >>>>>>>>
617 13:58:36.908388 [ANA_INIT] flow end
618 13:58:36.912193 ============ LP4 DIFF to SE enter ============
619 13:58:36.914814 ============ LP4 DIFF to SE exit ============
620 13:58:36.918763 [ANA_INIT] <<<<<<<<<<<<<
621 13:58:36.921965 [Flow] Enable top DCM control >>>>>
622 13:58:36.925510 [Flow] Enable top DCM control <<<<<
623 13:58:36.928868 Enable DLL master slave shuffle
624 13:58:36.931720 ==============================================================
625 13:58:36.934951 Gating Mode config
626 13:58:36.941620 ==============================================================
627 13:58:36.942182 Config description:
628 13:58:36.951710 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 13:58:36.958123 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 13:58:36.961656 SELPH_MODE 0: By rank 1: By Phase
631 13:58:36.968760 ==============================================================
632 13:58:36.971495 GAT_TRACK_EN = 1
633 13:58:36.975603 RX_GATING_MODE = 2
634 13:58:36.978763 RX_GATING_TRACK_MODE = 2
635 13:58:36.981806 SELPH_MODE = 1
636 13:58:36.984790 PICG_EARLY_EN = 1
637 13:58:36.988308 VALID_LAT_VALUE = 1
638 13:58:36.991697 ==============================================================
639 13:58:36.994821 Enter into Gating configuration >>>>
640 13:58:36.998733 Exit from Gating configuration <<<<
641 13:58:37.001769 Enter into DVFS_PRE_config >>>>>
642 13:58:37.015037 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 13:58:37.017729 Exit from DVFS_PRE_config <<<<<
644 13:58:37.018198 Enter into PICG configuration >>>>
645 13:58:37.021138 Exit from PICG configuration <<<<
646 13:58:37.024586 [RX_INPUT] configuration >>>>>
647 13:58:37.028385 [RX_INPUT] configuration <<<<<
648 13:58:37.034698 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 13:58:37.038493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 13:58:37.045645 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 13:58:37.053230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 13:58:37.057069 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 13:58:37.064053 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 13:58:37.067359 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 13:58:37.071311 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 13:58:37.075344 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 13:58:37.079113 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 13:58:37.082349 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 13:58:37.090000 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 13:58:37.092948 ===================================
661 13:58:37.093589 LPDDR4 DRAM CONFIGURATION
662 13:58:37.097121 ===================================
663 13:58:37.099558 EX_ROW_EN[0] = 0x0
664 13:58:37.099982 EX_ROW_EN[1] = 0x0
665 13:58:37.103913 LP4Y_EN = 0x0
666 13:58:37.104735 WORK_FSP = 0x0
667 13:58:37.107167 WL = 0x2
668 13:58:37.107736 RL = 0x2
669 13:58:37.110405 BL = 0x2
670 13:58:37.110884 RPST = 0x0
671 13:58:37.114201 RD_PRE = 0x0
672 13:58:37.114660 WR_PRE = 0x1
673 13:58:37.118348 WR_PST = 0x0
674 13:58:37.118902 DBI_WR = 0x0
675 13:58:37.121624 DBI_RD = 0x0
676 13:58:37.122046 OTF = 0x1
677 13:58:37.125329 ===================================
678 13:58:37.129245 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 13:58:37.132648 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 13:58:37.136268 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 13:58:37.139875 ===================================
682 13:58:37.143172 LPDDR4 DRAM CONFIGURATION
683 13:58:37.146430 ===================================
684 13:58:37.150769 EX_ROW_EN[0] = 0x10
685 13:58:37.151191 EX_ROW_EN[1] = 0x0
686 13:58:37.153831 LP4Y_EN = 0x0
687 13:58:37.154252 WORK_FSP = 0x0
688 13:58:37.157598 WL = 0x2
689 13:58:37.158144 RL = 0x2
690 13:58:37.161580 BL = 0x2
691 13:58:37.162002 RPST = 0x0
692 13:58:37.162341 RD_PRE = 0x0
693 13:58:37.164870 WR_PRE = 0x1
694 13:58:37.165289 WR_PST = 0x0
695 13:58:37.168697 DBI_WR = 0x0
696 13:58:37.169114 DBI_RD = 0x0
697 13:58:37.172327 OTF = 0x1
698 13:58:37.175876 ===================================
699 13:58:37.179301 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 13:58:37.185020 nWR fixed to 40
701 13:58:37.188706 [ModeRegInit_LP4] CH0 RK0
702 13:58:37.189254 [ModeRegInit_LP4] CH0 RK1
703 13:58:37.191905 [ModeRegInit_LP4] CH1 RK0
704 13:58:37.195443 [ModeRegInit_LP4] CH1 RK1
705 13:58:37.195891 match AC timing 13
706 13:58:37.199759 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 13:58:37.202584 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 13:58:37.209604 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 13:58:37.212693 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 13:58:37.219280 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 13:58:37.219787 [EMI DOE] emi_dcm 0
712 13:58:37.222545 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 13:58:37.226765 ==
714 13:58:37.227281 Dram Type= 6, Freq= 0, CH_0, rank 0
715 13:58:37.233365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 13:58:37.234007 ==
717 13:58:37.236073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 13:58:37.243373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 13:58:37.252819 [CA 0] Center 37 (6~68) winsize 63
720 13:58:37.255774 [CA 1] Center 36 (6~67) winsize 62
721 13:58:37.258809 [CA 2] Center 34 (4~65) winsize 62
722 13:58:37.262243 [CA 3] Center 34 (4~65) winsize 62
723 13:58:37.266450 [CA 4] Center 33 (3~64) winsize 62
724 13:58:37.270004 [CA 5] Center 33 (3~64) winsize 62
725 13:58:37.270488
726 13:58:37.273181 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 13:58:37.273646
728 13:58:37.276434 [CATrainingPosCal] consider 1 rank data
729 13:58:37.280430 u2DelayCellTimex100 = 270/100 ps
730 13:58:37.283633 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 13:58:37.286855 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
732 13:58:37.289955 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 13:58:37.293255 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 13:58:37.296658 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 13:58:37.303587 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 13:58:37.304056
737 13:58:37.306827 CA PerBit enable=1, Macro0, CA PI delay=33
738 13:58:37.307294
739 13:58:37.310484 [CBTSetCACLKResult] CA Dly = 33
740 13:58:37.311099 CS Dly: 6 (0~37)
741 13:58:37.311474 ==
742 13:58:37.312941 Dram Type= 6, Freq= 0, CH_0, rank 1
743 13:58:37.316652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 13:58:37.319910 ==
745 13:58:37.323147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 13:58:37.329841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 13:58:37.338488 [CA 0] Center 37 (7~68) winsize 62
748 13:58:37.342251 [CA 1] Center 37 (7~67) winsize 61
749 13:58:37.345694 [CA 2] Center 34 (4~65) winsize 62
750 13:58:37.348820 [CA 3] Center 34 (4~65) winsize 62
751 13:58:37.352256 [CA 4] Center 33 (3~64) winsize 62
752 13:58:37.354941 [CA 5] Center 33 (2~64) winsize 63
753 13:58:37.355412
754 13:58:37.358548 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 13:58:37.359231
756 13:58:37.362062 [CATrainingPosCal] consider 2 rank data
757 13:58:37.365099 u2DelayCellTimex100 = 270/100 ps
758 13:58:37.369226 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 13:58:37.371758 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
760 13:58:37.379080 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 13:58:37.382384 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 13:58:37.385569 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 13:58:37.389093 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 13:58:37.389578
765 13:58:37.392971 CA PerBit enable=1, Macro0, CA PI delay=33
766 13:58:37.393558
767 13:58:37.396705 [CBTSetCACLKResult] CA Dly = 33
768 13:58:37.397275 CS Dly: 6 (0~38)
769 13:58:37.397759
770 13:58:37.400019 ----->DramcWriteLeveling(PI) begin...
771 13:58:37.400514 ==
772 13:58:37.403986 Dram Type= 6, Freq= 0, CH_0, rank 0
773 13:58:37.407234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 13:58:37.407885 ==
775 13:58:37.411006 Write leveling (Byte 0): 30 => 30
776 13:58:37.414390 Write leveling (Byte 1): 30 => 30
777 13:58:37.417578 DramcWriteLeveling(PI) end<-----
778 13:58:37.418052
779 13:58:37.418534 ==
780 13:58:37.421422 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:58:37.424325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:58:37.424902 ==
783 13:58:37.428048 [Gating] SW mode calibration
784 13:58:37.434996 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 13:58:37.440921 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 13:58:37.444314 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:58:37.447733 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 13:58:37.454400 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 13:58:37.457810 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 13:58:37.460684 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:58:37.467567 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:58:37.470862 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:58:37.474261 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:58:37.480663 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:58:37.484509 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:58:37.487251 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:58:37.493897 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:58:37.496906 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:58:37.500104 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:58:37.507129 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:58:37.509963 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:58:37.513349 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:58:37.520343 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:58:37.523295 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 13:58:37.526907 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:58:37.533610 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:58:37.537012 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:58:37.540026 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:58:37.546916 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:58:37.550204 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:58:37.553478 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:58:37.560008 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
813 13:58:37.563044 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
814 13:58:37.566976 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:58:37.572809 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:58:37.576465 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:58:37.579706 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:58:37.586174 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 13:58:37.589691 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
820 13:58:37.593363 0 10 8 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (1 1)
821 13:58:37.599352 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:58:37.602479 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:58:37.606044 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:58:37.612716 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:58:37.616406 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:58:37.619169 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:58:37.625772 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:58:37.629873 0 11 8 | B1->B0 | 2626 3737 | 1 1 | (0 0) (0 0)
829 13:58:37.632336 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
830 13:58:37.638815 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:58:37.642136 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:58:37.646230 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:58:37.652247 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:58:37.655810 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:58:37.659123 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 13:58:37.666285 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 13:58:37.668863 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 13:58:37.671933 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:58:37.678841 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:58:37.682004 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:58:37.685628 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:58:37.689066 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:58:37.695541 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:58:37.698981 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:58:37.702718 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:58:37.706534 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:58:37.713776 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:58:37.717270 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:58:37.721468 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:58:37.724370 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:58:37.728247 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 13:58:37.735557 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 13:58:37.736089 Total UI for P1: 0, mck2ui 16
854 13:58:37.739906 best dqsien dly found for B0: ( 0, 14, 4)
855 13:58:37.743299 Total UI for P1: 0, mck2ui 16
856 13:58:37.746765 best dqsien dly found for B1: ( 0, 14, 6)
857 13:58:37.750325 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
858 13:58:37.754235 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
859 13:58:37.754849
860 13:58:37.758024 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
861 13:58:37.761269 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 13:58:37.764919 [Gating] SW calibration Done
863 13:58:37.765530 ==
864 13:58:37.768481 Dram Type= 6, Freq= 0, CH_0, rank 0
865 13:58:37.771783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 13:58:37.772246 ==
867 13:58:37.775442 RX Vref Scan: 0
868 13:58:37.775902
869 13:58:37.776305 RX Vref 0 -> 0, step: 1
870 13:58:37.776652
871 13:58:37.779170 RX Delay -130 -> 252, step: 16
872 13:58:37.782043 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 13:58:37.788664 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 13:58:37.792150 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 13:58:37.795661 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 13:58:37.798757 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 13:58:37.802180 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
878 13:58:37.809066 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 13:58:37.811895 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
880 13:58:37.815604 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
881 13:58:37.819330 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
882 13:58:37.823110 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 13:58:37.826552 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
884 13:58:37.830775 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
885 13:58:37.833776 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
886 13:58:37.841145 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 13:58:37.844539 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
888 13:58:37.845057 ==
889 13:58:37.847514 Dram Type= 6, Freq= 0, CH_0, rank 0
890 13:58:37.850979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 13:58:37.851527 ==
892 13:58:37.851869 DQS Delay:
893 13:58:37.854030 DQS0 = 0, DQS1 = 0
894 13:58:37.854444 DQM Delay:
895 13:58:37.857368 DQM0 = 86, DQM1 = 71
896 13:58:37.857785 DQ Delay:
897 13:58:37.860665 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 13:58:37.863986 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
899 13:58:37.867144 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
900 13:58:37.870948 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
901 13:58:37.871465
902 13:58:37.871796
903 13:58:37.872102 ==
904 13:58:37.874302 Dram Type= 6, Freq= 0, CH_0, rank 0
905 13:58:37.877717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 13:58:37.881158 ==
907 13:58:37.881687
908 13:58:37.882026
909 13:58:37.882336 TX Vref Scan disable
910 13:58:37.884274 == TX Byte 0 ==
911 13:58:37.887635 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
912 13:58:37.891609 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
913 13:58:37.894239 == TX Byte 1 ==
914 13:58:37.897391 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 13:58:37.901520 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 13:58:37.904365 ==
917 13:58:37.904880 Dram Type= 6, Freq= 0, CH_0, rank 0
918 13:58:37.911169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 13:58:37.911732 ==
920 13:58:37.922661 TX Vref=22, minBit 1, minWin=27, winSum=442
921 13:58:37.925905 TX Vref=24, minBit 4, minWin=27, winSum=441
922 13:58:37.929224 TX Vref=26, minBit 8, minWin=27, winSum=444
923 13:58:37.933004 TX Vref=28, minBit 9, minWin=27, winSum=446
924 13:58:37.935746 TX Vref=30, minBit 11, minWin=26, winSum=444
925 13:58:37.942057 TX Vref=32, minBit 4, minWin=27, winSum=442
926 13:58:37.945682 [TxChooseVref] Worse bit 9, Min win 27, Win sum 446, Final Vref 28
927 13:58:37.946354
928 13:58:37.949542 Final TX Range 1 Vref 28
929 13:58:37.950257
930 13:58:37.950957 ==
931 13:58:37.952139 Dram Type= 6, Freq= 0, CH_0, rank 0
932 13:58:37.956044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 13:58:37.956746 ==
934 13:58:37.958834
935 13:58:37.959257
936 13:58:37.959621 TX Vref Scan disable
937 13:58:37.962185 == TX Byte 0 ==
938 13:58:37.966493 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
939 13:58:37.971883 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
940 13:58:37.972475 == TX Byte 1 ==
941 13:58:37.975660 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
942 13:58:37.982373 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
943 13:58:37.982909
944 13:58:37.983266 [DATLAT]
945 13:58:37.983580 Freq=800, CH0 RK0
946 13:58:37.983883
947 13:58:37.985420 DATLAT Default: 0xa
948 13:58:37.985988 0, 0xFFFF, sum = 0
949 13:58:37.989517 1, 0xFFFF, sum = 0
950 13:58:37.989948 2, 0xFFFF, sum = 0
951 13:58:37.992302 3, 0xFFFF, sum = 0
952 13:58:37.995526 4, 0xFFFF, sum = 0
953 13:58:37.995958 5, 0xFFFF, sum = 0
954 13:58:37.998964 6, 0xFFFF, sum = 0
955 13:58:37.999395 7, 0xFFFF, sum = 0
956 13:58:38.002020 8, 0xFFFF, sum = 0
957 13:58:38.002447 9, 0x0, sum = 1
958 13:58:38.005316 10, 0x0, sum = 2
959 13:58:38.005747 11, 0x0, sum = 3
960 13:58:38.006087 12, 0x0, sum = 4
961 13:58:38.008914 best_step = 10
962 13:58:38.009339
963 13:58:38.009670 ==
964 13:58:38.012301 Dram Type= 6, Freq= 0, CH_0, rank 0
965 13:58:38.015611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 13:58:38.016040 ==
967 13:58:38.018679 RX Vref Scan: 1
968 13:58:38.019103
969 13:58:38.021961 Set Vref Range= 32 -> 127
970 13:58:38.022466
971 13:58:38.022863 RX Vref 32 -> 127, step: 1
972 13:58:38.023188
973 13:58:38.025846 RX Delay -111 -> 252, step: 8
974 13:58:38.026269
975 13:58:38.029355 Set Vref, RX VrefLevel [Byte0]: 32
976 13:58:38.032012 [Byte1]: 32
977 13:58:38.035249
978 13:58:38.038359 Set Vref, RX VrefLevel [Byte0]: 33
979 13:58:38.038813 [Byte1]: 33
980 13:58:38.042879
981 13:58:38.043302 Set Vref, RX VrefLevel [Byte0]: 34
982 13:58:38.045983 [Byte1]: 34
983 13:58:38.050853
984 13:58:38.051273 Set Vref, RX VrefLevel [Byte0]: 35
985 13:58:38.053757 [Byte1]: 35
986 13:58:38.058213
987 13:58:38.058678 Set Vref, RX VrefLevel [Byte0]: 36
988 13:58:38.061392 [Byte1]: 36
989 13:58:38.066104
990 13:58:38.066528 Set Vref, RX VrefLevel [Byte0]: 37
991 13:58:38.069185 [Byte1]: 37
992 13:58:38.073441
993 13:58:38.073883 Set Vref, RX VrefLevel [Byte0]: 38
994 13:58:38.076972 [Byte1]: 38
995 13:58:38.080862
996 13:58:38.081243 Set Vref, RX VrefLevel [Byte0]: 39
997 13:58:38.084618 [Byte1]: 39
998 13:58:38.088371
999 13:58:38.088763 Set Vref, RX VrefLevel [Byte0]: 40
1000 13:58:38.092466 [Byte1]: 40
1001 13:58:38.096497
1002 13:58:38.096892 Set Vref, RX VrefLevel [Byte0]: 41
1003 13:58:38.099625 [Byte1]: 41
1004 13:58:38.103995
1005 13:58:38.104432 Set Vref, RX VrefLevel [Byte0]: 42
1006 13:58:38.107489 [Byte1]: 42
1007 13:58:38.112048
1008 13:58:38.112553 Set Vref, RX VrefLevel [Byte0]: 43
1009 13:58:38.114928 [Byte1]: 43
1010 13:58:38.119698
1011 13:58:38.120141 Set Vref, RX VrefLevel [Byte0]: 44
1012 13:58:38.123005 [Byte1]: 44
1013 13:58:38.127081
1014 13:58:38.127525 Set Vref, RX VrefLevel [Byte0]: 45
1015 13:58:38.130836 [Byte1]: 45
1016 13:58:38.134660
1017 13:58:38.135115 Set Vref, RX VrefLevel [Byte0]: 46
1018 13:58:38.138101 [Byte1]: 46
1019 13:58:38.141957
1020 13:58:38.142381 Set Vref, RX VrefLevel [Byte0]: 47
1021 13:58:38.145327 [Byte1]: 47
1022 13:58:38.150017
1023 13:58:38.150439 Set Vref, RX VrefLevel [Byte0]: 48
1024 13:58:38.153239 [Byte1]: 48
1025 13:58:38.158230
1026 13:58:38.158694 Set Vref, RX VrefLevel [Byte0]: 49
1027 13:58:38.161139 [Byte1]: 49
1028 13:58:38.165080
1029 13:58:38.165546 Set Vref, RX VrefLevel [Byte0]: 50
1030 13:58:38.169518 [Byte1]: 50
1031 13:58:38.172989
1032 13:58:38.173400 Set Vref, RX VrefLevel [Byte0]: 51
1033 13:58:38.176002 [Byte1]: 51
1034 13:58:38.181047
1035 13:58:38.181566 Set Vref, RX VrefLevel [Byte0]: 52
1036 13:58:38.184349 [Byte1]: 52
1037 13:58:38.188919
1038 13:58:38.189329 Set Vref, RX VrefLevel [Byte0]: 53
1039 13:58:38.192087 [Byte1]: 53
1040 13:58:38.195616
1041 13:58:38.196088 Set Vref, RX VrefLevel [Byte0]: 54
1042 13:58:38.199328 [Byte1]: 54
1043 13:58:38.203431
1044 13:58:38.203870 Set Vref, RX VrefLevel [Byte0]: 55
1045 13:58:38.206981 [Byte1]: 55
1046 13:58:38.211208
1047 13:58:38.211618 Set Vref, RX VrefLevel [Byte0]: 56
1048 13:58:38.214891 [Byte1]: 56
1049 13:58:38.219747
1050 13:58:38.220362 Set Vref, RX VrefLevel [Byte0]: 57
1051 13:58:38.222185 [Byte1]: 57
1052 13:58:38.226976
1053 13:58:38.227387 Set Vref, RX VrefLevel [Byte0]: 58
1054 13:58:38.229945 [Byte1]: 58
1055 13:58:38.233930
1056 13:58:38.234359 Set Vref, RX VrefLevel [Byte0]: 59
1057 13:58:38.237253 [Byte1]: 59
1058 13:58:38.242432
1059 13:58:38.242928 Set Vref, RX VrefLevel [Byte0]: 60
1060 13:58:38.245373 [Byte1]: 60
1061 13:58:38.248864
1062 13:58:38.252468 Set Vref, RX VrefLevel [Byte0]: 61
1063 13:58:38.253057 [Byte1]: 61
1064 13:58:38.257013
1065 13:58:38.257422 Set Vref, RX VrefLevel [Byte0]: 62
1066 13:58:38.260466 [Byte1]: 62
1067 13:58:38.264587
1068 13:58:38.265000 Set Vref, RX VrefLevel [Byte0]: 63
1069 13:58:38.267909 [Byte1]: 63
1070 13:58:38.272906
1071 13:58:38.273465 Set Vref, RX VrefLevel [Byte0]: 64
1072 13:58:38.275687 [Byte1]: 64
1073 13:58:38.280031
1074 13:58:38.280467 Set Vref, RX VrefLevel [Byte0]: 65
1075 13:58:38.283682 [Byte1]: 65
1076 13:58:38.287694
1077 13:58:38.288105 Set Vref, RX VrefLevel [Byte0]: 66
1078 13:58:38.290985 [Byte1]: 66
1079 13:58:38.295609
1080 13:58:38.295688 Set Vref, RX VrefLevel [Byte0]: 67
1081 13:58:38.298490 [Byte1]: 67
1082 13:58:38.302448
1083 13:58:38.302555 Set Vref, RX VrefLevel [Byte0]: 68
1084 13:58:38.306155 [Byte1]: 68
1085 13:58:38.310263
1086 13:58:38.310344 Set Vref, RX VrefLevel [Byte0]: 69
1087 13:58:38.313612 [Byte1]: 69
1088 13:58:38.317406
1089 13:58:38.317486 Set Vref, RX VrefLevel [Byte0]: 70
1090 13:58:38.321622 [Byte1]: 70
1091 13:58:38.325829
1092 13:58:38.325910 Set Vref, RX VrefLevel [Byte0]: 71
1093 13:58:38.329276 [Byte1]: 71
1094 13:58:38.333384
1095 13:58:38.333465 Set Vref, RX VrefLevel [Byte0]: 72
1096 13:58:38.337301 [Byte1]: 72
1097 13:58:38.340947
1098 13:58:38.341028 Set Vref, RX VrefLevel [Byte0]: 73
1099 13:58:38.344598 [Byte1]: 73
1100 13:58:38.348671
1101 13:58:38.348776 Set Vref, RX VrefLevel [Byte0]: 74
1102 13:58:38.351835 [Byte1]: 74
1103 13:58:38.356339
1104 13:58:38.356419 Set Vref, RX VrefLevel [Byte0]: 75
1105 13:58:38.359508 [Byte1]: 75
1106 13:58:38.363671
1107 13:58:38.363787 Set Vref, RX VrefLevel [Byte0]: 76
1108 13:58:38.367103 [Byte1]: 76
1109 13:58:38.371321
1110 13:58:38.371401 Set Vref, RX VrefLevel [Byte0]: 77
1111 13:58:38.374286 [Byte1]: 77
1112 13:58:38.379179
1113 13:58:38.379259 Set Vref, RX VrefLevel [Byte0]: 78
1114 13:58:38.382167 [Byte1]: 78
1115 13:58:38.386565
1116 13:58:38.386686 Set Vref, RX VrefLevel [Byte0]: 79
1117 13:58:38.389582 [Byte1]: 79
1118 13:58:38.393940
1119 13:58:38.394020 Set Vref, RX VrefLevel [Byte0]: 80
1120 13:58:38.397466 [Byte1]: 80
1121 13:58:38.402252
1122 13:58:38.402333 Set Vref, RX VrefLevel [Byte0]: 81
1123 13:58:38.405229 [Byte1]: 81
1124 13:58:38.409515
1125 13:58:38.409595 Set Vref, RX VrefLevel [Byte0]: 82
1126 13:58:38.413344 [Byte1]: 82
1127 13:58:38.417617
1128 13:58:38.417697 Set Vref, RX VrefLevel [Byte0]: 83
1129 13:58:38.420890 [Byte1]: 83
1130 13:58:38.425582
1131 13:58:38.425662 Final RX Vref Byte 0 = 65 to rank0
1132 13:58:38.428847 Final RX Vref Byte 1 = 57 to rank0
1133 13:58:38.432195 Final RX Vref Byte 0 = 65 to rank1
1134 13:58:38.435949 Final RX Vref Byte 1 = 57 to rank1==
1135 13:58:38.440398 Dram Type= 6, Freq= 0, CH_0, rank 0
1136 13:58:38.443680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 13:58:38.443761 ==
1138 13:58:38.443826 DQS Delay:
1139 13:58:38.447326 DQS0 = 0, DQS1 = 0
1140 13:58:38.447406 DQM Delay:
1141 13:58:38.450915 DQM0 = 87, DQM1 = 75
1142 13:58:38.450995 DQ Delay:
1143 13:58:38.454865 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1144 13:58:38.454945 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1145 13:58:38.458398 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1146 13:58:38.462160 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1147 13:58:38.462259
1148 13:58:38.462329
1149 13:58:38.472642 [DQSOSCAuto] RK0, (LSB)MR18= 0x4627, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1150 13:58:38.472724 CH0 RK0: MR19=606, MR18=4627
1151 13:58:38.480167 CH0_RK0: MR19=0x606, MR18=0x4627, DQSOSC=392, MR23=63, INC=96, DEC=64
1152 13:58:38.480248
1153 13:58:38.484063 ----->DramcWriteLeveling(PI) begin...
1154 13:58:38.484145 ==
1155 13:58:38.487843 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 13:58:38.491344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 13:58:38.491425 ==
1158 13:58:38.495715 Write leveling (Byte 0): 33 => 33
1159 13:58:38.499177 Write leveling (Byte 1): 33 => 33
1160 13:58:38.543104 DramcWriteLeveling(PI) end<-----
1161 13:58:38.543198
1162 13:58:38.543262 ==
1163 13:58:38.543322 Dram Type= 6, Freq= 0, CH_0, rank 1
1164 13:58:38.543563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1165 13:58:38.543629 ==
1166 13:58:38.543930 [Gating] SW mode calibration
1167 13:58:38.544250 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1168 13:58:38.544820 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1169 13:58:38.545573 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1170 13:58:38.545654 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1171 13:58:38.545897 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1172 13:58:38.546964 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:58:38.587153 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:58:38.587420 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:58:38.587488 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:58:38.588125 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:58:38.588386 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:58:38.588468 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:58:38.588532 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:58:38.588949 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:58:38.589308 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:58:38.589899 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:58:38.631100 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:58:38.631196 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:58:38.631444 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:58:38.631814 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:58:38.632074 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1188 13:58:38.632323 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:58:38.632387 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:58:38.632785 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:58:38.633371 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:58:38.633631 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:58:38.663950 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 13:58:38.664034 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 13:58:38.664694 0 9 8 | B1->B0 | 2424 3030 | 0 1 | (0 0) (0 0)
1196 13:58:38.664955 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1197 13:58:38.665735 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 13:58:38.665997 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 13:58:38.666068 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 13:58:38.666454 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 13:58:38.669823 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 13:58:38.672928 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1203 13:58:38.679441 0 10 8 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 0)
1204 13:58:38.682952 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1205 13:58:38.686330 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 13:58:38.692789 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 13:58:38.695409 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 13:58:38.699063 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 13:58:38.702149 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 13:58:38.709159 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1211 13:58:38.712387 0 11 8 | B1->B0 | 3030 3d3d | 0 0 | (0 0) (0 0)
1212 13:58:38.715542 0 11 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
1213 13:58:38.722284 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 13:58:38.725613 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 13:58:38.728633 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 13:58:38.735683 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 13:58:38.738799 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 13:58:38.742311 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 13:58:38.749036 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1220 13:58:38.752270 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 13:58:38.755150 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 13:58:38.762025 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 13:58:38.765679 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 13:58:38.768993 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 13:58:38.775891 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 13:58:38.778644 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 13:58:38.782365 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 13:58:38.789175 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 13:58:38.792374 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 13:58:38.795286 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 13:58:38.802043 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 13:58:38.805257 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 13:58:38.808558 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 13:58:38.815258 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 13:58:38.818424 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1236 13:58:38.821730 Total UI for P1: 0, mck2ui 16
1237 13:58:38.825065 best dqsien dly found for B0: ( 0, 14, 6)
1238 13:58:38.828689 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1239 13:58:38.831920 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 13:58:38.835270 Total UI for P1: 0, mck2ui 16
1241 13:58:38.838459 best dqsien dly found for B1: ( 0, 14, 10)
1242 13:58:38.841791 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1243 13:58:38.848470 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1244 13:58:38.848551
1245 13:58:38.851656 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1246 13:58:38.855935 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1247 13:58:38.859249 [Gating] SW calibration Done
1248 13:58:38.859333 ==
1249 13:58:38.861734 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 13:58:38.865014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1251 13:58:38.865095 ==
1252 13:58:38.865158 RX Vref Scan: 0
1253 13:58:38.868155
1254 13:58:38.868235 RX Vref 0 -> 0, step: 1
1255 13:58:38.868298
1256 13:58:38.872129 RX Delay -130 -> 252, step: 16
1257 13:58:38.875061 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1258 13:58:38.878244 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1259 13:58:38.885021 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1260 13:58:38.888739 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1261 13:58:38.891551 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1262 13:58:38.895090 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1263 13:58:38.898646 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1264 13:58:38.904816 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1265 13:58:38.908163 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1266 13:58:38.911586 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1267 13:58:38.915082 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1268 13:58:38.921414 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1269 13:58:38.925047 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1270 13:58:38.928335 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1271 13:58:38.931503 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1272 13:58:38.934496 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1273 13:58:38.938307 ==
1274 13:58:38.938390 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 13:58:38.944846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 13:58:38.944930 ==
1277 13:58:38.945014 DQS Delay:
1278 13:58:38.948191 DQS0 = 0, DQS1 = 0
1279 13:58:38.948273 DQM Delay:
1280 13:58:38.951591 DQM0 = 85, DQM1 = 75
1281 13:58:38.951674 DQ Delay:
1282 13:58:38.954847 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1283 13:58:38.958246 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1284 13:58:38.961244 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1285 13:58:38.964844 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =77
1286 13:58:38.964928
1287 13:58:38.965012
1288 13:58:38.965092 ==
1289 13:58:38.967861 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 13:58:38.971512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 13:58:38.971596 ==
1292 13:58:38.971680
1293 13:58:38.971774
1294 13:58:38.974796 TX Vref Scan disable
1295 13:58:38.978556 == TX Byte 0 ==
1296 13:58:38.981292 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1297 13:58:38.984577 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1298 13:58:38.988248 == TX Byte 1 ==
1299 13:58:38.991170 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1300 13:58:38.994958 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1301 13:58:38.995038 ==
1302 13:58:38.998438 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 13:58:39.000987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 13:58:39.004747 ==
1305 13:58:39.015503 TX Vref=22, minBit 12, minWin=27, winSum=448
1306 13:58:39.018766 TX Vref=24, minBit 12, minWin=27, winSum=447
1307 13:58:39.022251 TX Vref=26, minBit 0, minWin=28, winSum=448
1308 13:58:39.025516 TX Vref=28, minBit 12, minWin=27, winSum=449
1309 13:58:39.032321 TX Vref=30, minBit 9, minWin=27, winSum=450
1310 13:58:39.035403 TX Vref=32, minBit 9, minWin=27, winSum=443
1311 13:58:39.038787 [TxChooseVref] Worse bit 0, Min win 28, Win sum 448, Final Vref 26
1312 13:58:39.038867
1313 13:58:39.042305 Final TX Range 1 Vref 26
1314 13:58:39.042385
1315 13:58:39.042447 ==
1316 13:58:39.045408 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 13:58:39.052031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 13:58:39.052111 ==
1319 13:58:39.052174
1320 13:58:39.052233
1321 13:58:39.052290 TX Vref Scan disable
1322 13:58:39.055555 == TX Byte 0 ==
1323 13:58:39.059350 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1324 13:58:39.065572 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1325 13:58:39.065651 == TX Byte 1 ==
1326 13:58:39.068745 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1327 13:58:39.075416 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1328 13:58:39.075495
1329 13:58:39.075558 [DATLAT]
1330 13:58:39.075617 Freq=800, CH0 RK1
1331 13:58:39.075675
1332 13:58:39.078720 DATLAT Default: 0xa
1333 13:58:39.082624 0, 0xFFFF, sum = 0
1334 13:58:39.082719 1, 0xFFFF, sum = 0
1335 13:58:39.085426 2, 0xFFFF, sum = 0
1336 13:58:39.085507 3, 0xFFFF, sum = 0
1337 13:58:39.088462 4, 0xFFFF, sum = 0
1338 13:58:39.088543 5, 0xFFFF, sum = 0
1339 13:58:39.092175 6, 0xFFFF, sum = 0
1340 13:58:39.092257 7, 0xFFFF, sum = 0
1341 13:58:39.095010 8, 0xFFFF, sum = 0
1342 13:58:39.095091 9, 0x0, sum = 1
1343 13:58:39.098434 10, 0x0, sum = 2
1344 13:58:39.098514 11, 0x0, sum = 3
1345 13:58:39.102340 12, 0x0, sum = 4
1346 13:58:39.102421 best_step = 10
1347 13:58:39.102484
1348 13:58:39.102542 ==
1349 13:58:39.105048 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 13:58:39.108710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 13:58:39.108791 ==
1352 13:58:39.111917 RX Vref Scan: 0
1353 13:58:39.111996
1354 13:58:39.115210 RX Vref 0 -> 0, step: 1
1355 13:58:39.115289
1356 13:58:39.115353 RX Delay -111 -> 252, step: 8
1357 13:58:39.122744 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1358 13:58:39.125811 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1359 13:58:39.129119 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1360 13:58:39.132764 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1361 13:58:39.135847 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1362 13:58:39.143018 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1363 13:58:39.145756 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1364 13:58:39.149578 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1365 13:58:39.152426 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1366 13:58:39.155625 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1367 13:58:39.162729 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1368 13:58:39.165697 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1369 13:58:39.169012 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1370 13:58:39.172763 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1371 13:58:39.175634 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1372 13:58:39.182411 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1373 13:58:39.182496 ==
1374 13:58:39.185765 Dram Type= 6, Freq= 0, CH_0, rank 1
1375 13:58:39.189027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 13:58:39.189112 ==
1377 13:58:39.189197 DQS Delay:
1378 13:58:39.192373 DQS0 = 0, DQS1 = 0
1379 13:58:39.192456 DQM Delay:
1380 13:58:39.196285 DQM0 = 86, DQM1 = 77
1381 13:58:39.196368 DQ Delay:
1382 13:58:39.199132 DQ0 =88, DQ1 =92, DQ2 =80, DQ3 =84
1383 13:58:39.202537 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1384 13:58:39.205439 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1385 13:58:39.209055 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1386 13:58:39.209138
1387 13:58:39.209222
1388 13:58:39.219136 [DQSOSCAuto] RK1, (LSB)MR18= 0x480e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
1389 13:58:39.219220 CH0 RK1: MR19=606, MR18=480E
1390 13:58:39.225803 CH0_RK1: MR19=0x606, MR18=0x480E, DQSOSC=391, MR23=63, INC=96, DEC=64
1391 13:58:39.228737 [RxdqsGatingPostProcess] freq 800
1392 13:58:39.236026 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1393 13:58:39.238854 Pre-setting of DQS Precalculation
1394 13:58:39.242049 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1395 13:58:39.242128 ==
1396 13:58:39.245508 Dram Type= 6, Freq= 0, CH_1, rank 0
1397 13:58:39.249316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 13:58:39.251944 ==
1399 13:58:39.255390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1400 13:58:39.262069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1401 13:58:39.270516 [CA 0] Center 36 (6~67) winsize 62
1402 13:58:39.274137 [CA 1] Center 36 (6~67) winsize 62
1403 13:58:39.277509 [CA 2] Center 34 (4~65) winsize 62
1404 13:58:39.280905 [CA 3] Center 34 (3~65) winsize 63
1405 13:58:39.284309 [CA 4] Center 34 (4~65) winsize 62
1406 13:58:39.287294 [CA 5] Center 34 (3~65) winsize 63
1407 13:58:39.287365
1408 13:58:39.290675 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1409 13:58:39.290745
1410 13:58:39.294034 [CATrainingPosCal] consider 1 rank data
1411 13:58:39.297801 u2DelayCellTimex100 = 270/100 ps
1412 13:58:39.301052 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1413 13:58:39.304115 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1414 13:58:39.310583 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1415 13:58:39.313929 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1416 13:58:39.317333 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1417 13:58:39.320870 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1418 13:58:39.320951
1419 13:58:39.323895 CA PerBit enable=1, Macro0, CA PI delay=34
1420 13:58:39.323977
1421 13:58:39.327501 [CBTSetCACLKResult] CA Dly = 34
1422 13:58:39.327582 CS Dly: 5 (0~36)
1423 13:58:39.330617 ==
1424 13:58:39.334264 Dram Type= 6, Freq= 0, CH_1, rank 1
1425 13:58:39.337242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 13:58:39.337324 ==
1427 13:58:39.340781 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1428 13:58:39.346975 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1429 13:58:39.357007 [CA 0] Center 36 (6~67) winsize 62
1430 13:58:39.360280 [CA 1] Center 36 (6~67) winsize 62
1431 13:58:39.363402 [CA 2] Center 34 (4~65) winsize 62
1432 13:58:39.366852 [CA 3] Center 34 (3~65) winsize 63
1433 13:58:39.370398 [CA 4] Center 34 (4~65) winsize 62
1434 13:58:39.373741 [CA 5] Center 34 (4~65) winsize 62
1435 13:58:39.373822
1436 13:58:39.377063 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1437 13:58:39.377144
1438 13:58:39.380399 [CATrainingPosCal] consider 2 rank data
1439 13:58:39.383634 u2DelayCellTimex100 = 270/100 ps
1440 13:58:39.386485 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1441 13:58:39.393316 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1442 13:58:39.396489 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1443 13:58:39.399957 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1444 13:58:39.403338 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1445 13:58:39.407191 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1446 13:58:39.407272
1447 13:58:39.409968 CA PerBit enable=1, Macro0, CA PI delay=34
1448 13:58:39.410050
1449 13:58:39.413447 [CBTSetCACLKResult] CA Dly = 34
1450 13:58:39.413528 CS Dly: 6 (0~38)
1451 13:58:39.413593
1452 13:58:39.416662 ----->DramcWriteLeveling(PI) begin...
1453 13:58:39.419915 ==
1454 13:58:39.423778 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 13:58:39.426483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 13:58:39.426615 ==
1457 13:58:39.430012 Write leveling (Byte 0): 27 => 27
1458 13:58:39.433574 Write leveling (Byte 1): 30 => 30
1459 13:58:39.436583 DramcWriteLeveling(PI) end<-----
1460 13:58:39.436680
1461 13:58:39.436745 ==
1462 13:58:39.439839 Dram Type= 6, Freq= 0, CH_1, rank 0
1463 13:58:39.443150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1464 13:58:39.443232 ==
1465 13:58:39.446821 [Gating] SW mode calibration
1466 13:58:39.453044 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1467 13:58:39.459797 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1468 13:58:39.463032 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1469 13:58:39.466807 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1470 13:58:39.473109 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:58:39.476510 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:58:39.479992 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:58:39.486257 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:58:39.489489 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:58:39.492979 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:58:39.496146 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:58:39.502825 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:58:39.506497 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 13:58:39.509840 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 13:58:39.516630 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:58:39.519380 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:58:39.522875 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 13:58:39.529506 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:58:39.532778 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:58:39.536372 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1486 13:58:39.542878 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1487 13:58:39.546264 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:58:39.549287 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:58:39.556699 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:58:39.559278 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:58:39.562951 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:58:39.569316 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 13:58:39.572671 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 13:58:39.575789 0 9 8 | B1->B0 | 2a2a 3232 | 1 0 | (1 1) (0 0)
1495 13:58:39.582718 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 13:58:39.586196 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 13:58:39.589235 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 13:58:39.596283 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 13:58:39.599688 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 13:58:39.602846 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1501 13:58:39.609429 0 10 4 | B1->B0 | 3232 3232 | 0 1 | (0 0) (1 0)
1502 13:58:39.612593 0 10 8 | B1->B0 | 2727 2424 | 0 0 | (1 1) (0 0)
1503 13:58:39.615928 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 13:58:39.622314 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 13:58:39.626053 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 13:58:39.629368 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 13:58:39.632501 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 13:58:39.639318 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 13:58:39.642803 0 11 4 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0)
1510 13:58:39.646262 0 11 8 | B1->B0 | 3a3a 3b3b | 0 1 | (0 0) (0 0)
1511 13:58:39.652645 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 13:58:39.655674 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 13:58:39.658902 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 13:58:39.665716 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 13:58:39.669040 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 13:58:39.672616 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 13:58:39.679022 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1518 13:58:39.682356 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 13:58:39.685719 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 13:58:39.692276 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 13:58:39.696925 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 13:58:39.698972 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 13:58:39.706090 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 13:58:39.708985 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 13:58:39.712420 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 13:58:39.719047 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 13:58:39.722694 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 13:58:39.725472 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 13:58:39.732294 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 13:58:39.735858 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 13:58:39.739222 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 13:58:39.745498 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 13:58:39.749144 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1534 13:58:39.752002 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1535 13:58:39.755443 Total UI for P1: 0, mck2ui 16
1536 13:58:39.758802 best dqsien dly found for B0: ( 0, 14, 4)
1537 13:58:39.761831 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 13:58:39.765413 Total UI for P1: 0, mck2ui 16
1539 13:58:39.768926 best dqsien dly found for B1: ( 0, 14, 8)
1540 13:58:39.771987 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1541 13:58:39.778907 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1542 13:58:39.779005
1543 13:58:39.782027 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1544 13:58:39.785361 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1545 13:58:39.788425 [Gating] SW calibration Done
1546 13:58:39.788508 ==
1547 13:58:39.791904 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 13:58:39.795536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1549 13:58:39.795619 ==
1550 13:58:39.795683 RX Vref Scan: 0
1551 13:58:39.798484
1552 13:58:39.798598 RX Vref 0 -> 0, step: 1
1553 13:58:39.798692
1554 13:58:39.801983 RX Delay -130 -> 252, step: 16
1555 13:58:39.805272 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1556 13:58:39.808842 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1557 13:58:39.815213 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1558 13:58:39.818461 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1559 13:58:39.821782 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1560 13:58:39.825283 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1561 13:58:39.831469 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1562 13:58:39.835102 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1563 13:58:39.838748 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1564 13:58:39.841845 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1565 13:58:39.845227 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1566 13:58:39.851557 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1567 13:58:39.855028 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1568 13:58:39.858145 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1569 13:58:39.861416 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1570 13:58:39.864849 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1571 13:58:39.868315 ==
1572 13:58:39.868397 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 13:58:39.874651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 13:58:39.874733 ==
1575 13:58:39.874799 DQS Delay:
1576 13:58:39.878454 DQS0 = 0, DQS1 = 0
1577 13:58:39.878535 DQM Delay:
1578 13:58:39.881275 DQM0 = 89, DQM1 = 79
1579 13:58:39.881381 DQ Delay:
1580 13:58:39.885166 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1581 13:58:39.887929 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1582 13:58:39.891166 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1583 13:58:39.895016 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1584 13:58:39.895087
1585 13:58:39.895147
1586 13:58:39.895204 ==
1587 13:58:39.898750 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 13:58:39.901450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 13:58:39.901554 ==
1590 13:58:39.901648
1591 13:58:39.901714
1592 13:58:39.904634 TX Vref Scan disable
1593 13:58:39.908026 == TX Byte 0 ==
1594 13:58:39.911341 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1595 13:58:39.914578 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1596 13:58:39.917911 == TX Byte 1 ==
1597 13:58:39.921256 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1598 13:58:39.924621 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1599 13:58:39.924717 ==
1600 13:58:39.927974 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 13:58:39.934972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 13:58:39.935054 ==
1603 13:58:39.945973 TX Vref=22, minBit 10, minWin=26, winSum=443
1604 13:58:39.949202 TX Vref=24, minBit 15, minWin=26, winSum=444
1605 13:58:39.952140 TX Vref=26, minBit 8, minWin=27, winSum=449
1606 13:58:39.956144 TX Vref=28, minBit 1, minWin=28, winSum=453
1607 13:58:39.958901 TX Vref=30, minBit 9, minWin=27, winSum=451
1608 13:58:39.965705 TX Vref=32, minBit 9, minWin=27, winSum=449
1609 13:58:39.968903 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 28
1610 13:58:39.968985
1611 13:58:39.972181 Final TX Range 1 Vref 28
1612 13:58:39.972262
1613 13:58:39.972326 ==
1614 13:58:39.975376 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 13:58:39.978988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 13:58:39.982363 ==
1617 13:58:39.982444
1618 13:58:39.982508
1619 13:58:39.982570 TX Vref Scan disable
1620 13:58:39.985985 == TX Byte 0 ==
1621 13:58:39.989431 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1622 13:58:39.995899 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1623 13:58:39.996001 == TX Byte 1 ==
1624 13:58:39.999318 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1625 13:58:40.005941 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1626 13:58:40.006018
1627 13:58:40.006081 [DATLAT]
1628 13:58:40.006156 Freq=800, CH1 RK0
1629 13:58:40.006243
1630 13:58:40.009560 DATLAT Default: 0xa
1631 13:58:40.009654 0, 0xFFFF, sum = 0
1632 13:58:40.012628 1, 0xFFFF, sum = 0
1633 13:58:40.012712 2, 0xFFFF, sum = 0
1634 13:58:40.015952 3, 0xFFFF, sum = 0
1635 13:58:40.019046 4, 0xFFFF, sum = 0
1636 13:58:40.019129 5, 0xFFFF, sum = 0
1637 13:58:40.022293 6, 0xFFFF, sum = 0
1638 13:58:40.022375 7, 0xFFFF, sum = 0
1639 13:58:40.025891 8, 0xFFFF, sum = 0
1640 13:58:40.025973 9, 0x0, sum = 1
1641 13:58:40.029076 10, 0x0, sum = 2
1642 13:58:40.029159 11, 0x0, sum = 3
1643 13:58:40.029225 12, 0x0, sum = 4
1644 13:58:40.032517 best_step = 10
1645 13:58:40.032598
1646 13:58:40.032663 ==
1647 13:58:40.036410 Dram Type= 6, Freq= 0, CH_1, rank 0
1648 13:58:40.040035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1649 13:58:40.040117 ==
1650 13:58:40.042803 RX Vref Scan: 1
1651 13:58:40.042884
1652 13:58:40.045676 Set Vref Range= 32 -> 127
1653 13:58:40.045757
1654 13:58:40.045821 RX Vref 32 -> 127, step: 1
1655 13:58:40.045882
1656 13:58:40.049007 RX Delay -95 -> 252, step: 8
1657 13:58:40.049089
1658 13:58:40.052532 Set Vref, RX VrefLevel [Byte0]: 32
1659 13:58:40.055596 [Byte1]: 32
1660 13:58:40.055678
1661 13:58:40.059265 Set Vref, RX VrefLevel [Byte0]: 33
1662 13:58:40.062239 [Byte1]: 33
1663 13:58:40.066340
1664 13:58:40.066421 Set Vref, RX VrefLevel [Byte0]: 34
1665 13:58:40.069473 [Byte1]: 34
1666 13:58:40.073786
1667 13:58:40.073868 Set Vref, RX VrefLevel [Byte0]: 35
1668 13:58:40.077338 [Byte1]: 35
1669 13:58:40.081857
1670 13:58:40.081939 Set Vref, RX VrefLevel [Byte0]: 36
1671 13:58:40.084959 [Byte1]: 36
1672 13:58:40.089047
1673 13:58:40.089128 Set Vref, RX VrefLevel [Byte0]: 37
1674 13:58:40.092295 [Byte1]: 37
1675 13:58:40.096697
1676 13:58:40.096778 Set Vref, RX VrefLevel [Byte0]: 38
1677 13:58:40.099885 [Byte1]: 38
1678 13:58:40.104535
1679 13:58:40.104616 Set Vref, RX VrefLevel [Byte0]: 39
1680 13:58:40.107566 [Byte1]: 39
1681 13:58:40.111844
1682 13:58:40.111925 Set Vref, RX VrefLevel [Byte0]: 40
1683 13:58:40.115621 [Byte1]: 40
1684 13:58:40.119938
1685 13:58:40.120019 Set Vref, RX VrefLevel [Byte0]: 41
1686 13:58:40.122870 [Byte1]: 41
1687 13:58:40.127187
1688 13:58:40.127268 Set Vref, RX VrefLevel [Byte0]: 42
1689 13:58:40.130447 [Byte1]: 42
1690 13:58:40.134567
1691 13:58:40.134686 Set Vref, RX VrefLevel [Byte0]: 43
1692 13:58:40.137820 [Byte1]: 43
1693 13:58:40.143054
1694 13:58:40.143133 Set Vref, RX VrefLevel [Byte0]: 44
1695 13:58:40.145768 [Byte1]: 44
1696 13:58:40.150085
1697 13:58:40.150160 Set Vref, RX VrefLevel [Byte0]: 45
1698 13:58:40.153528 [Byte1]: 45
1699 13:58:40.157582
1700 13:58:40.157680 Set Vref, RX VrefLevel [Byte0]: 46
1701 13:58:40.161058 [Byte1]: 46
1702 13:58:40.165224
1703 13:58:40.165327 Set Vref, RX VrefLevel [Byte0]: 47
1704 13:58:40.168540 [Byte1]: 47
1705 13:58:40.172851
1706 13:58:40.172950 Set Vref, RX VrefLevel [Byte0]: 48
1707 13:58:40.175946 [Byte1]: 48
1708 13:58:40.180132
1709 13:58:40.180213 Set Vref, RX VrefLevel [Byte0]: 49
1710 13:58:40.183641 [Byte1]: 49
1711 13:58:40.187967
1712 13:58:40.188048 Set Vref, RX VrefLevel [Byte0]: 50
1713 13:58:40.191386 [Byte1]: 50
1714 13:58:40.195724
1715 13:58:40.195806 Set Vref, RX VrefLevel [Byte0]: 51
1716 13:58:40.198730 [Byte1]: 51
1717 13:58:40.203149
1718 13:58:40.203231 Set Vref, RX VrefLevel [Byte0]: 52
1719 13:58:40.206533 [Byte1]: 52
1720 13:58:40.210481
1721 13:58:40.210578 Set Vref, RX VrefLevel [Byte0]: 53
1722 13:58:40.214499 [Byte1]: 53
1723 13:58:40.218810
1724 13:58:40.218892 Set Vref, RX VrefLevel [Byte0]: 54
1725 13:58:40.221626 [Byte1]: 54
1726 13:58:40.226118
1727 13:58:40.226199 Set Vref, RX VrefLevel [Byte0]: 55
1728 13:58:40.229158 [Byte1]: 55
1729 13:58:40.233630
1730 13:58:40.233711 Set Vref, RX VrefLevel [Byte0]: 56
1731 13:58:40.237012 [Byte1]: 56
1732 13:58:40.241040
1733 13:58:40.241121 Set Vref, RX VrefLevel [Byte0]: 57
1734 13:58:40.244237 [Byte1]: 57
1735 13:58:40.248581
1736 13:58:40.248662 Set Vref, RX VrefLevel [Byte0]: 58
1737 13:58:40.252029 [Byte1]: 58
1738 13:58:40.256538
1739 13:58:40.256620 Set Vref, RX VrefLevel [Byte0]: 59
1740 13:58:40.259772 [Byte1]: 59
1741 13:58:40.263911
1742 13:58:40.263991 Set Vref, RX VrefLevel [Byte0]: 60
1743 13:58:40.267173 [Byte1]: 60
1744 13:58:40.271456
1745 13:58:40.271537 Set Vref, RX VrefLevel [Byte0]: 61
1746 13:58:40.274661 [Byte1]: 61
1747 13:58:40.279275
1748 13:58:40.279356 Set Vref, RX VrefLevel [Byte0]: 62
1749 13:58:40.282459 [Byte1]: 62
1750 13:58:40.286539
1751 13:58:40.286638 Set Vref, RX VrefLevel [Byte0]: 63
1752 13:58:40.290025 [Byte1]: 63
1753 13:58:40.294395
1754 13:58:40.294496 Set Vref, RX VrefLevel [Byte0]: 64
1755 13:58:40.297939 [Byte1]: 64
1756 13:58:40.301811
1757 13:58:40.301908 Set Vref, RX VrefLevel [Byte0]: 65
1758 13:58:40.305084 [Byte1]: 65
1759 13:58:40.309711
1760 13:58:40.309807 Set Vref, RX VrefLevel [Byte0]: 66
1761 13:58:40.312566 [Byte1]: 66
1762 13:58:40.316895
1763 13:58:40.316996 Set Vref, RX VrefLevel [Byte0]: 67
1764 13:58:40.320260 [Byte1]: 67
1765 13:58:40.324585
1766 13:58:40.324682 Set Vref, RX VrefLevel [Byte0]: 68
1767 13:58:40.327793 [Byte1]: 68
1768 13:58:40.332054
1769 13:58:40.332127 Set Vref, RX VrefLevel [Byte0]: 69
1770 13:58:40.335810 [Byte1]: 69
1771 13:58:40.339951
1772 13:58:40.340027 Set Vref, RX VrefLevel [Byte0]: 70
1773 13:58:40.343585 [Byte1]: 70
1774 13:58:40.347619
1775 13:58:40.347694 Set Vref, RX VrefLevel [Byte0]: 71
1776 13:58:40.351442 [Byte1]: 71
1777 13:58:40.355439
1778 13:58:40.355511 Set Vref, RX VrefLevel [Byte0]: 72
1779 13:58:40.358178 [Byte1]: 72
1780 13:58:40.363020
1781 13:58:40.363119 Set Vref, RX VrefLevel [Byte0]: 73
1782 13:58:40.365761 [Byte1]: 73
1783 13:58:40.370118
1784 13:58:40.370190 Set Vref, RX VrefLevel [Byte0]: 74
1785 13:58:40.373551 [Byte1]: 74
1786 13:58:40.377941
1787 13:58:40.378012 Set Vref, RX VrefLevel [Byte0]: 75
1788 13:58:40.380895 [Byte1]: 75
1789 13:58:40.385191
1790 13:58:40.385276 Set Vref, RX VrefLevel [Byte0]: 76
1791 13:58:40.388643 [Byte1]: 76
1792 13:58:40.392946
1793 13:58:40.393044 Set Vref, RX VrefLevel [Byte0]: 77
1794 13:58:40.396186 [Byte1]: 77
1795 13:58:40.400463
1796 13:58:40.400560 Set Vref, RX VrefLevel [Byte0]: 78
1797 13:58:40.403845 [Byte1]: 78
1798 13:58:40.408402
1799 13:58:40.408497 Final RX Vref Byte 0 = 57 to rank0
1800 13:58:40.411901 Final RX Vref Byte 1 = 65 to rank0
1801 13:58:40.414761 Final RX Vref Byte 0 = 57 to rank1
1802 13:58:40.418406 Final RX Vref Byte 1 = 65 to rank1==
1803 13:58:40.421499 Dram Type= 6, Freq= 0, CH_1, rank 0
1804 13:58:40.428087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 13:58:40.428162 ==
1806 13:58:40.428224 DQS Delay:
1807 13:58:40.428282 DQS0 = 0, DQS1 = 0
1808 13:58:40.431958 DQM Delay:
1809 13:58:40.432024 DQM0 = 87, DQM1 = 79
1810 13:58:40.434847 DQ Delay:
1811 13:58:40.438844 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1812 13:58:40.441392 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1813 13:58:40.444589 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1814 13:58:40.447700 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =92
1815 13:58:40.447772
1816 13:58:40.447833
1817 13:58:40.455430 [DQSOSCAuto] RK0, (LSB)MR18= 0x311d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1818 13:58:40.457937 CH1 RK0: MR19=606, MR18=311D
1819 13:58:40.464538 CH1_RK0: MR19=0x606, MR18=0x311D, DQSOSC=397, MR23=63, INC=93, DEC=62
1820 13:58:40.464611
1821 13:58:40.468204 ----->DramcWriteLeveling(PI) begin...
1822 13:58:40.468299 ==
1823 13:58:40.471072 Dram Type= 6, Freq= 0, CH_1, rank 1
1824 13:58:40.474451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1825 13:58:40.474547 ==
1826 13:58:40.477665 Write leveling (Byte 0): 28 => 28
1827 13:58:40.481456 Write leveling (Byte 1): 29 => 29
1828 13:58:40.484879 DramcWriteLeveling(PI) end<-----
1829 13:58:40.484945
1830 13:58:40.485002 ==
1831 13:58:40.487797 Dram Type= 6, Freq= 0, CH_1, rank 1
1832 13:58:40.490983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1833 13:58:40.491050 ==
1834 13:58:40.494106 [Gating] SW mode calibration
1835 13:58:40.500857 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1836 13:58:40.508657 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1837 13:58:40.511059 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1838 13:58:40.517725 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1839 13:58:40.521056 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1840 13:58:40.524344 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:58:40.530845 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:58:40.534141 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:58:40.537821 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 13:58:40.544109 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:58:40.547352 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:58:40.550562 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:58:40.553919 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:58:40.560584 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 13:58:40.563991 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 13:58:40.567246 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 13:58:40.573985 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 13:58:40.577167 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 13:58:40.580481 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:58:40.587303 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1855 13:58:40.590890 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 13:58:40.593798 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 13:58:40.600627 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 13:58:40.603924 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 13:58:40.607855 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 13:58:40.614068 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 13:58:40.617261 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 13:58:40.620571 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 13:58:40.627303 0 9 8 | B1->B0 | 2f2f 2b2b | 0 1 | (0 0) (0 0)
1864 13:58:40.630578 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 13:58:40.633881 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 13:58:40.640462 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 13:58:40.644213 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 13:58:40.646963 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 13:58:40.653968 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 13:58:40.657626 0 10 4 | B1->B0 | 3232 3434 | 0 1 | (1 0) (1 0)
1871 13:58:40.660699 0 10 8 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (0 0)
1872 13:58:40.667270 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 13:58:40.670158 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 13:58:40.673483 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 13:58:40.680890 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 13:58:40.683877 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 13:58:40.686704 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 13:58:40.693812 0 11 4 | B1->B0 | 2f2e 2323 | 1 0 | (0 0) (0 0)
1879 13:58:40.696997 0 11 8 | B1->B0 | 4545 3838 | 0 0 | (0 0) (0 0)
1880 13:58:40.699944 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 13:58:40.703442 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 13:58:40.710202 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 13:58:40.713843 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 13:58:40.716697 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 13:58:40.723414 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 13:58:40.726809 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 13:58:40.730240 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 13:58:40.736809 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 13:58:40.740029 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 13:58:40.743253 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 13:58:40.750134 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 13:58:40.753616 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 13:58:40.756703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 13:58:40.763223 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 13:58:40.766387 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 13:58:40.769890 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 13:58:40.776575 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 13:58:40.779721 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 13:58:40.783069 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 13:58:40.790055 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 13:58:40.792836 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 13:58:40.796187 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1903 13:58:40.802979 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1904 13:58:40.803061 Total UI for P1: 0, mck2ui 16
1905 13:58:40.809324 best dqsien dly found for B1: ( 0, 14, 4)
1906 13:58:40.813076 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 13:58:40.816633 Total UI for P1: 0, mck2ui 16
1908 13:58:40.819418 best dqsien dly found for B0: ( 0, 14, 8)
1909 13:58:40.822800 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1910 13:58:40.826484 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1911 13:58:40.826615
1912 13:58:40.829418 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1913 13:58:40.832721 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1914 13:58:40.836242 [Gating] SW calibration Done
1915 13:58:40.836324 ==
1916 13:58:40.839730 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 13:58:40.842817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 13:58:40.842899 ==
1919 13:58:40.845819 RX Vref Scan: 0
1920 13:58:40.845900
1921 13:58:40.849187 RX Vref 0 -> 0, step: 1
1922 13:58:40.849268
1923 13:58:40.849331 RX Delay -130 -> 252, step: 16
1924 13:58:40.856280 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1925 13:58:40.859173 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1926 13:58:40.862485 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1927 13:58:40.865912 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1928 13:58:40.870037 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1929 13:58:40.876314 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1930 13:58:40.879331 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1931 13:58:40.882619 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1932 13:58:40.885659 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1933 13:58:40.892341 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1934 13:58:40.896239 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1935 13:58:40.899731 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1936 13:58:40.902310 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1937 13:58:40.905702 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1938 13:58:40.912426 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1939 13:58:40.916013 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1940 13:58:40.916110 ==
1941 13:58:40.918875 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 13:58:40.922225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 13:58:40.922306 ==
1944 13:58:40.925534 DQS Delay:
1945 13:58:40.925615 DQS0 = 0, DQS1 = 0
1946 13:58:40.925680 DQM Delay:
1947 13:58:40.929421 DQM0 = 86, DQM1 = 78
1948 13:58:40.929502 DQ Delay:
1949 13:58:40.932263 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1950 13:58:40.935845 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1951 13:58:40.939240 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1952 13:58:40.942118 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1953 13:58:40.942201
1954 13:58:40.942265
1955 13:58:40.942325 ==
1956 13:58:40.945776 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 13:58:40.952280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 13:58:40.952363 ==
1959 13:58:40.952428
1960 13:58:40.952487
1961 13:58:40.952545 TX Vref Scan disable
1962 13:58:40.956144 == TX Byte 0 ==
1963 13:58:40.958983 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1964 13:58:40.965639 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1965 13:58:40.965721 == TX Byte 1 ==
1966 13:58:40.968899 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1967 13:58:40.972855 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1968 13:58:40.975598 ==
1969 13:58:40.979209 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 13:58:40.982724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 13:58:40.982806 ==
1972 13:58:40.994928 TX Vref=22, minBit 1, minWin=27, winSum=445
1973 13:58:40.998163 TX Vref=24, minBit 8, minWin=27, winSum=450
1974 13:58:41.001513 TX Vref=26, minBit 1, minWin=27, winSum=451
1975 13:58:41.005174 TX Vref=28, minBit 13, minWin=27, winSum=452
1976 13:58:41.008382 TX Vref=30, minBit 15, minWin=27, winSum=451
1977 13:58:41.015172 TX Vref=32, minBit 8, minWin=27, winSum=446
1978 13:58:41.018385 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 28
1979 13:58:41.018493
1980 13:58:41.021308 Final TX Range 1 Vref 28
1981 13:58:41.021390
1982 13:58:41.021453 ==
1983 13:58:41.025067 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 13:58:41.027834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 13:58:41.031160 ==
1986 13:58:41.031241
1987 13:58:41.031304
1988 13:58:41.031363 TX Vref Scan disable
1989 13:58:41.035480 == TX Byte 0 ==
1990 13:58:41.038608 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1991 13:58:41.041958 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1992 13:58:41.045273 == TX Byte 1 ==
1993 13:58:41.049305 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1994 13:58:41.051963 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1995 13:58:41.055169
1996 13:58:41.055246 [DATLAT]
1997 13:58:41.055308 Freq=800, CH1 RK1
1998 13:58:41.055367
1999 13:58:41.058639 DATLAT Default: 0xa
2000 13:58:41.058711 0, 0xFFFF, sum = 0
2001 13:58:41.061592 1, 0xFFFF, sum = 0
2002 13:58:41.061690 2, 0xFFFF, sum = 0
2003 13:58:41.065141 3, 0xFFFF, sum = 0
2004 13:58:41.065215 4, 0xFFFF, sum = 0
2005 13:58:41.068374 5, 0xFFFF, sum = 0
2006 13:58:41.071609 6, 0xFFFF, sum = 0
2007 13:58:41.071710 7, 0xFFFF, sum = 0
2008 13:58:41.075239 8, 0xFFFF, sum = 0
2009 13:58:41.075313 9, 0x0, sum = 1
2010 13:58:41.075374 10, 0x0, sum = 2
2011 13:58:41.078109 11, 0x0, sum = 3
2012 13:58:41.078201 12, 0x0, sum = 4
2013 13:58:41.081601 best_step = 10
2014 13:58:41.081699
2015 13:58:41.081788 ==
2016 13:58:41.084878 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 13:58:41.088376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 13:58:41.088478 ==
2019 13:58:41.091714 RX Vref Scan: 0
2020 13:58:41.091780
2021 13:58:41.091839 RX Vref 0 -> 0, step: 1
2022 13:58:41.094903
2023 13:58:41.094974 RX Delay -95 -> 252, step: 8
2024 13:58:41.102464 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2025 13:58:41.105053 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2026 13:58:41.108566 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2027 13:58:41.111958 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2028 13:58:41.115544 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2029 13:58:41.122048 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2030 13:58:41.125223 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2031 13:58:41.128632 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2032 13:58:41.131929 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2033 13:58:41.135509 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2034 13:58:41.141651 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2035 13:58:41.145425 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2036 13:58:41.148323 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2037 13:58:41.151772 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2038 13:58:41.158547 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2039 13:58:41.162181 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2040 13:58:41.162249 ==
2041 13:58:41.164788 Dram Type= 6, Freq= 0, CH_1, rank 1
2042 13:58:41.168335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2043 13:58:41.168418 ==
2044 13:58:41.168518 DQS Delay:
2045 13:58:41.171714 DQS0 = 0, DQS1 = 0
2046 13:58:41.171807 DQM Delay:
2047 13:58:41.175359 DQM0 = 87, DQM1 = 78
2048 13:58:41.175428 DQ Delay:
2049 13:58:41.178555 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2050 13:58:41.181557 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2051 13:58:41.184876 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2052 13:58:41.188615 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2053 13:58:41.188714
2054 13:58:41.188803
2055 13:58:41.198484 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2056 13:58:41.198587 CH1 RK1: MR19=606, MR18=1F17
2057 13:58:41.204645 CH1_RK1: MR19=0x606, MR18=0x1F17, DQSOSC=402, MR23=63, INC=91, DEC=60
2058 13:58:41.208224 [RxdqsGatingPostProcess] freq 800
2059 13:58:41.214543 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2060 13:58:41.217864 Pre-setting of DQS Precalculation
2061 13:58:41.221472 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2062 13:58:41.228110 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2063 13:58:41.237760 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2064 13:58:41.237846
2065 13:58:41.237910
2066 13:58:41.241048 [Calibration Summary] 1600 Mbps
2067 13:58:41.241131 CH 0, Rank 0
2068 13:58:41.245235 SW Impedance : PASS
2069 13:58:41.245316 DUTY Scan : NO K
2070 13:58:41.248191 ZQ Calibration : PASS
2071 13:58:41.248273 Jitter Meter : NO K
2072 13:58:41.251327 CBT Training : PASS
2073 13:58:41.254387 Write leveling : PASS
2074 13:58:41.254486 RX DQS gating : PASS
2075 13:58:41.257964 RX DQ/DQS(RDDQC) : PASS
2076 13:58:41.261652 TX DQ/DQS : PASS
2077 13:58:41.261736 RX DATLAT : PASS
2078 13:58:41.264601 RX DQ/DQS(Engine): PASS
2079 13:58:41.267970 TX OE : NO K
2080 13:58:41.268051 All Pass.
2081 13:58:41.268115
2082 13:58:41.268174 CH 0, Rank 1
2083 13:58:41.271387 SW Impedance : PASS
2084 13:58:41.274542 DUTY Scan : NO K
2085 13:58:41.274646 ZQ Calibration : PASS
2086 13:58:41.277873 Jitter Meter : NO K
2087 13:58:41.281112 CBT Training : PASS
2088 13:58:41.281193 Write leveling : PASS
2089 13:58:41.284520 RX DQS gating : PASS
2090 13:58:41.287842 RX DQ/DQS(RDDQC) : PASS
2091 13:58:41.287924 TX DQ/DQS : PASS
2092 13:58:41.291352 RX DATLAT : PASS
2093 13:58:41.291434 RX DQ/DQS(Engine): PASS
2094 13:58:41.294426 TX OE : NO K
2095 13:58:41.294507 All Pass.
2096 13:58:41.294571
2097 13:58:41.298018 CH 1, Rank 0
2098 13:58:41.298099 SW Impedance : PASS
2099 13:58:41.301149 DUTY Scan : NO K
2100 13:58:41.304331 ZQ Calibration : PASS
2101 13:58:41.304412 Jitter Meter : NO K
2102 13:58:41.307628 CBT Training : PASS
2103 13:58:41.311285 Write leveling : PASS
2104 13:58:41.311366 RX DQS gating : PASS
2105 13:58:41.314813 RX DQ/DQS(RDDQC) : PASS
2106 13:58:41.317639 TX DQ/DQS : PASS
2107 13:58:41.317721 RX DATLAT : PASS
2108 13:58:41.321149 RX DQ/DQS(Engine): PASS
2109 13:58:41.324627 TX OE : NO K
2110 13:58:41.324708 All Pass.
2111 13:58:41.324773
2112 13:58:41.324833 CH 1, Rank 1
2113 13:58:41.327745 SW Impedance : PASS
2114 13:58:41.331062 DUTY Scan : NO K
2115 13:58:41.331144 ZQ Calibration : PASS
2116 13:58:41.334214 Jitter Meter : NO K
2117 13:58:41.337735 CBT Training : PASS
2118 13:58:41.337816 Write leveling : PASS
2119 13:58:41.341565 RX DQS gating : PASS
2120 13:58:41.344487 RX DQ/DQS(RDDQC) : PASS
2121 13:58:41.344568 TX DQ/DQS : PASS
2122 13:58:41.347730 RX DATLAT : PASS
2123 13:58:41.347811 RX DQ/DQS(Engine): PASS
2124 13:58:41.350711 TX OE : NO K
2125 13:58:41.350792 All Pass.
2126 13:58:41.350856
2127 13:58:41.354357 DramC Write-DBI off
2128 13:58:41.357595 PER_BANK_REFRESH: Hybrid Mode
2129 13:58:41.357685 TX_TRACKING: ON
2130 13:58:41.360990 [GetDramInforAfterCalByMRR] Vendor 6.
2131 13:58:41.363916 [GetDramInforAfterCalByMRR] Revision 606.
2132 13:58:41.370597 [GetDramInforAfterCalByMRR] Revision 2 0.
2133 13:58:41.370712 MR0 0x3b3b
2134 13:58:41.370803 MR8 0x5151
2135 13:58:41.373916 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2136 13:58:41.373985
2137 13:58:41.377408 MR0 0x3b3b
2138 13:58:41.377481 MR8 0x5151
2139 13:58:41.380412 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2140 13:58:41.380483
2141 13:58:41.390556 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2142 13:58:41.394167 [FAST_K] Save calibration result to emmc
2143 13:58:41.397049 [FAST_K] Save calibration result to emmc
2144 13:58:41.400499 dram_init: config_dvfs: 1
2145 13:58:41.404599 dramc_set_vcore_voltage set vcore to 662500
2146 13:58:41.407013 Read voltage for 1200, 2
2147 13:58:41.407089 Vio18 = 0
2148 13:58:41.407151 Vcore = 662500
2149 13:58:41.410559 Vdram = 0
2150 13:58:41.410663 Vddq = 0
2151 13:58:41.410724 Vmddr = 0
2152 13:58:41.418000 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2153 13:58:41.420396 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2154 13:58:41.423881 MEM_TYPE=3, freq_sel=15
2155 13:58:41.426932 sv_algorithm_assistance_LP4_1600
2156 13:58:41.430578 ============ PULL DRAM RESETB DOWN ============
2157 13:58:41.433654 ========== PULL DRAM RESETB DOWN end =========
2158 13:58:41.440242 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2159 13:58:41.443835 ===================================
2160 13:58:41.443908 LPDDR4 DRAM CONFIGURATION
2161 13:58:41.447158 ===================================
2162 13:58:41.450292 EX_ROW_EN[0] = 0x0
2163 13:58:41.453464 EX_ROW_EN[1] = 0x0
2164 13:58:41.453539 LP4Y_EN = 0x0
2165 13:58:41.457300 WORK_FSP = 0x0
2166 13:58:41.457370 WL = 0x4
2167 13:58:41.460268 RL = 0x4
2168 13:58:41.460335 BL = 0x2
2169 13:58:41.463544 RPST = 0x0
2170 13:58:41.463620 RD_PRE = 0x0
2171 13:58:41.467165 WR_PRE = 0x1
2172 13:58:41.467238 WR_PST = 0x0
2173 13:58:41.470394 DBI_WR = 0x0
2174 13:58:41.470492 DBI_RD = 0x0
2175 13:58:41.473872 OTF = 0x1
2176 13:58:41.476870 ===================================
2177 13:58:41.480617 ===================================
2178 13:58:41.480714 ANA top config
2179 13:58:41.483628 ===================================
2180 13:58:41.486770 DLL_ASYNC_EN = 0
2181 13:58:41.490244 ALL_SLAVE_EN = 0
2182 13:58:41.490314 NEW_RANK_MODE = 1
2183 13:58:41.493448 DLL_IDLE_MODE = 1
2184 13:58:41.497210 LP45_APHY_COMB_EN = 1
2185 13:58:41.500211 TX_ODT_DIS = 1
2186 13:58:41.503367 NEW_8X_MODE = 1
2187 13:58:41.506532 ===================================
2188 13:58:41.510104 ===================================
2189 13:58:41.510202 data_rate = 2400
2190 13:58:41.513229 CKR = 1
2191 13:58:41.516586 DQ_P2S_RATIO = 8
2192 13:58:41.519975 ===================================
2193 13:58:41.523251 CA_P2S_RATIO = 8
2194 13:58:41.526804 DQ_CA_OPEN = 0
2195 13:58:41.529823 DQ_SEMI_OPEN = 0
2196 13:58:41.529894 CA_SEMI_OPEN = 0
2197 13:58:41.533682 CA_FULL_RATE = 0
2198 13:58:41.536721 DQ_CKDIV4_EN = 0
2199 13:58:41.540239 CA_CKDIV4_EN = 0
2200 13:58:41.542954 CA_PREDIV_EN = 0
2201 13:58:41.546513 PH8_DLY = 17
2202 13:58:41.546645 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2203 13:58:41.549753 DQ_AAMCK_DIV = 4
2204 13:58:41.553303 CA_AAMCK_DIV = 4
2205 13:58:41.556770 CA_ADMCK_DIV = 4
2206 13:58:41.559929 DQ_TRACK_CA_EN = 0
2207 13:58:41.563124 CA_PICK = 1200
2208 13:58:41.566263 CA_MCKIO = 1200
2209 13:58:41.566365 MCKIO_SEMI = 0
2210 13:58:41.569685 PLL_FREQ = 2366
2211 13:58:41.572953 DQ_UI_PI_RATIO = 32
2212 13:58:41.576386 CA_UI_PI_RATIO = 0
2213 13:58:41.579664 ===================================
2214 13:58:41.582956 ===================================
2215 13:58:41.586395 memory_type:LPDDR4
2216 13:58:41.586490 GP_NUM : 10
2217 13:58:41.589820 SRAM_EN : 1
2218 13:58:41.593214 MD32_EN : 0
2219 13:58:41.596381 ===================================
2220 13:58:41.596458 [ANA_INIT] >>>>>>>>>>>>>>
2221 13:58:41.599921 <<<<<< [CONFIGURE PHASE]: ANA_TX
2222 13:58:41.603278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2223 13:58:41.606472 ===================================
2224 13:58:41.609807 data_rate = 2400,PCW = 0X5b00
2225 13:58:41.613083 ===================================
2226 13:58:41.616517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2227 13:58:41.623290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2228 13:58:41.626448 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2229 13:58:41.633452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2230 13:58:41.636435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2231 13:58:41.639640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2232 13:58:41.639738 [ANA_INIT] flow start
2233 13:58:41.644135 [ANA_INIT] PLL >>>>>>>>
2234 13:58:41.646745 [ANA_INIT] PLL <<<<<<<<
2235 13:58:41.646819 [ANA_INIT] MIDPI >>>>>>>>
2236 13:58:41.650215 [ANA_INIT] MIDPI <<<<<<<<
2237 13:58:41.652978 [ANA_INIT] DLL >>>>>>>>
2238 13:58:41.653047 [ANA_INIT] DLL <<<<<<<<
2239 13:58:41.656272 [ANA_INIT] flow end
2240 13:58:41.659661 ============ LP4 DIFF to SE enter ============
2241 13:58:41.666194 ============ LP4 DIFF to SE exit ============
2242 13:58:41.666294 [ANA_INIT] <<<<<<<<<<<<<
2243 13:58:41.669403 [Flow] Enable top DCM control >>>>>
2244 13:58:41.673157 [Flow] Enable top DCM control <<<<<
2245 13:58:41.676099 Enable DLL master slave shuffle
2246 13:58:41.683492 ==============================================================
2247 13:58:41.683565 Gating Mode config
2248 13:58:41.689820 ==============================================================
2249 13:58:41.693187 Config description:
2250 13:58:41.699951 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2251 13:58:41.706156 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2252 13:58:41.713597 SELPH_MODE 0: By rank 1: By Phase
2253 13:58:41.720127 ==============================================================
2254 13:58:41.720226 GAT_TRACK_EN = 1
2255 13:58:41.722717 RX_GATING_MODE = 2
2256 13:58:41.726188 RX_GATING_TRACK_MODE = 2
2257 13:58:41.729893 SELPH_MODE = 1
2258 13:58:41.732796 PICG_EARLY_EN = 1
2259 13:58:41.736111 VALID_LAT_VALUE = 1
2260 13:58:41.742407 ==============================================================
2261 13:58:41.745689 Enter into Gating configuration >>>>
2262 13:58:41.749427 Exit from Gating configuration <<<<
2263 13:58:41.752376 Enter into DVFS_PRE_config >>>>>
2264 13:58:41.762848 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2265 13:58:41.765879 Exit from DVFS_PRE_config <<<<<
2266 13:58:41.769007 Enter into PICG configuration >>>>
2267 13:58:41.772830 Exit from PICG configuration <<<<
2268 13:58:41.775660 [RX_INPUT] configuration >>>>>
2269 13:58:41.779080 [RX_INPUT] configuration <<<<<
2270 13:58:41.782030 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2271 13:58:41.788761 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2272 13:58:41.795831 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2273 13:58:41.798920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2274 13:58:41.805259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2275 13:58:41.812204 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2276 13:58:41.815133 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2277 13:58:41.821940 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2278 13:58:41.824980 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2279 13:58:41.829029 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2280 13:58:41.832171 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2281 13:58:41.838476 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 13:58:41.841459 ===================================
2283 13:58:41.841567 LPDDR4 DRAM CONFIGURATION
2284 13:58:41.844775 ===================================
2285 13:58:41.848341 EX_ROW_EN[0] = 0x0
2286 13:58:41.851575 EX_ROW_EN[1] = 0x0
2287 13:58:41.851659 LP4Y_EN = 0x0
2288 13:58:41.854861 WORK_FSP = 0x0
2289 13:58:41.854934 WL = 0x4
2290 13:58:41.858216 RL = 0x4
2291 13:58:41.858293 BL = 0x2
2292 13:58:41.861276 RPST = 0x0
2293 13:58:41.861346 RD_PRE = 0x0
2294 13:58:41.864772 WR_PRE = 0x1
2295 13:58:41.864873 WR_PST = 0x0
2296 13:58:41.868664 DBI_WR = 0x0
2297 13:58:41.868734 DBI_RD = 0x0
2298 13:58:41.871486 OTF = 0x1
2299 13:58:41.874870 ===================================
2300 13:58:41.878242 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2301 13:58:41.881475 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2302 13:58:41.888241 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2303 13:58:41.891124 ===================================
2304 13:58:41.891231 LPDDR4 DRAM CONFIGURATION
2305 13:58:41.894803 ===================================
2306 13:58:41.897773 EX_ROW_EN[0] = 0x10
2307 13:58:41.901182 EX_ROW_EN[1] = 0x0
2308 13:58:41.901275 LP4Y_EN = 0x0
2309 13:58:41.904806 WORK_FSP = 0x0
2310 13:58:41.904885 WL = 0x4
2311 13:58:41.907741 RL = 0x4
2312 13:58:41.907820 BL = 0x2
2313 13:58:41.911038 RPST = 0x0
2314 13:58:41.911117 RD_PRE = 0x0
2315 13:58:41.914300 WR_PRE = 0x1
2316 13:58:41.914370 WR_PST = 0x0
2317 13:58:41.918001 DBI_WR = 0x0
2318 13:58:41.918080 DBI_RD = 0x0
2319 13:58:41.920843 OTF = 0x1
2320 13:58:41.924228 ===================================
2321 13:58:41.930861 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2322 13:58:41.930941 ==
2323 13:58:41.934549 Dram Type= 6, Freq= 0, CH_0, rank 0
2324 13:58:41.937378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2325 13:58:41.937458 ==
2326 13:58:41.940712 [Duty_Offset_Calibration]
2327 13:58:41.940792 B0:1 B1:-1 CA:0
2328 13:58:41.940855
2329 13:58:41.943779 [DutyScan_Calibration_Flow] k_type=0
2330 13:58:41.954878
2331 13:58:41.954957 ==CLK 0==
2332 13:58:41.958184 Final CLK duty delay cell = 0
2333 13:58:41.961298 [0] MAX Duty = 5125%(X100), DQS PI = 24
2334 13:58:41.964973 [0] MIN Duty = 4907%(X100), DQS PI = 8
2335 13:58:41.965112 [0] AVG Duty = 5016%(X100)
2336 13:58:41.965183
2337 13:58:41.969387 CH0 CLK Duty spec in!! Max-Min= 218%
2338 13:58:41.975328 [DutyScan_Calibration_Flow] ====Done====
2339 13:58:41.975408
2340 13:58:41.977859 [DutyScan_Calibration_Flow] k_type=1
2341 13:58:41.992405
2342 13:58:41.992484 ==DQS 0 ==
2343 13:58:41.995693 Final DQS duty delay cell = -4
2344 13:58:41.999129 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2345 13:58:42.002649 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2346 13:58:42.005894 [-4] AVG Duty = 4968%(X100)
2347 13:58:42.005974
2348 13:58:42.006038 ==DQS 1 ==
2349 13:58:42.009025 Final DQS duty delay cell = -4
2350 13:58:42.012470 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2351 13:58:42.015922 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2352 13:58:42.019131 [-4] AVG Duty = 4938%(X100)
2353 13:58:42.019211
2354 13:58:42.022305 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2355 13:58:42.022387
2356 13:58:42.025731 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2357 13:58:42.029295 [DutyScan_Calibration_Flow] ====Done====
2358 13:58:42.029375
2359 13:58:42.032313 [DutyScan_Calibration_Flow] k_type=3
2360 13:58:42.050716
2361 13:58:42.050797 ==DQM 0 ==
2362 13:58:42.054289 Final DQM duty delay cell = 0
2363 13:58:42.056988 [0] MAX Duty = 5062%(X100), DQS PI = 18
2364 13:58:42.060531 [0] MIN Duty = 4875%(X100), DQS PI = 8
2365 13:58:42.060612 [0] AVG Duty = 4968%(X100)
2366 13:58:42.063893
2367 13:58:42.063973 ==DQM 1 ==
2368 13:58:42.067008 Final DQM duty delay cell = 4
2369 13:58:42.070281 [4] MAX Duty = 5187%(X100), DQS PI = 14
2370 13:58:42.073637 [4] MIN Duty = 5000%(X100), DQS PI = 24
2371 13:58:42.077191 [4] AVG Duty = 5093%(X100)
2372 13:58:42.077271
2373 13:58:42.080515 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2374 13:58:42.080595
2375 13:58:42.083397 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2376 13:58:42.087300 [DutyScan_Calibration_Flow] ====Done====
2377 13:58:42.087380
2378 13:58:42.090284 [DutyScan_Calibration_Flow] k_type=2
2379 13:58:42.105445
2380 13:58:42.105524 ==DQ 0 ==
2381 13:58:42.108658 Final DQ duty delay cell = -4
2382 13:58:42.112119 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2383 13:58:42.115564 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2384 13:58:42.118900 [-4] AVG Duty = 4969%(X100)
2385 13:58:42.118999
2386 13:58:42.119096 ==DQ 1 ==
2387 13:58:42.121957 Final DQ duty delay cell = -4
2388 13:58:42.125056 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2389 13:58:42.128423 [-4] MIN Duty = 4876%(X100), DQS PI = 40
2390 13:58:42.131995 [-4] AVG Duty = 4938%(X100)
2391 13:58:42.132066
2392 13:58:42.135111 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2393 13:58:42.135184
2394 13:58:42.138781 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2395 13:58:42.142492 [DutyScan_Calibration_Flow] ====Done====
2396 13:58:42.142598 ==
2397 13:58:42.145054 Dram Type= 6, Freq= 0, CH_1, rank 0
2398 13:58:42.148723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2399 13:58:42.148794 ==
2400 13:58:42.151759 [Duty_Offset_Calibration]
2401 13:58:42.151833 B0:-1 B1:1 CA:1
2402 13:58:42.151895
2403 13:58:42.155035 [DutyScan_Calibration_Flow] k_type=0
2404 13:58:42.166408
2405 13:58:42.166489 ==CLK 0==
2406 13:58:42.169353 Final CLK duty delay cell = 0
2407 13:58:42.172456 [0] MAX Duty = 5156%(X100), DQS PI = 6
2408 13:58:42.175772 [0] MIN Duty = 5000%(X100), DQS PI = 28
2409 13:58:42.179371 [0] AVG Duty = 5078%(X100)
2410 13:58:42.179475
2411 13:58:42.182519 CH1 CLK Duty spec in!! Max-Min= 156%
2412 13:58:42.185919 [DutyScan_Calibration_Flow] ====Done====
2413 13:58:42.185994
2414 13:58:42.189046 [DutyScan_Calibration_Flow] k_type=1
2415 13:58:42.205493
2416 13:58:42.205604 ==DQS 0 ==
2417 13:58:42.208736 Final DQS duty delay cell = 0
2418 13:58:42.211954 [0] MAX Duty = 5156%(X100), DQS PI = 48
2419 13:58:42.215312 [0] MIN Duty = 4907%(X100), DQS PI = 38
2420 13:58:42.218469 [0] AVG Duty = 5031%(X100)
2421 13:58:42.218540
2422 13:58:42.218648 ==DQS 1 ==
2423 13:58:42.221706 Final DQS duty delay cell = 0
2424 13:58:42.225084 [0] MAX Duty = 5094%(X100), DQS PI = 44
2425 13:58:42.228759 [0] MIN Duty = 4969%(X100), DQS PI = 28
2426 13:58:42.232118 [0] AVG Duty = 5031%(X100)
2427 13:58:42.232191
2428 13:58:42.235082 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2429 13:58:42.235156
2430 13:58:42.238430 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2431 13:58:42.241583 [DutyScan_Calibration_Flow] ====Done====
2432 13:58:42.241681
2433 13:58:42.244801 [DutyScan_Calibration_Flow] k_type=3
2434 13:58:42.261138
2435 13:58:42.261230 ==DQM 0 ==
2436 13:58:42.264780 Final DQM duty delay cell = -4
2437 13:58:42.267475 [-4] MAX Duty = 5062%(X100), DQS PI = 0
2438 13:58:42.270482 [-4] MIN Duty = 4876%(X100), DQS PI = 38
2439 13:58:42.274493 [-4] AVG Duty = 4969%(X100)
2440 13:58:42.274598
2441 13:58:42.274677 ==DQM 1 ==
2442 13:58:42.277373 Final DQM duty delay cell = 0
2443 13:58:42.280724 [0] MAX Duty = 5187%(X100), DQS PI = 36
2444 13:58:42.283707 [0] MIN Duty = 4969%(X100), DQS PI = 2
2445 13:58:42.287503 [0] AVG Duty = 5078%(X100)
2446 13:58:42.287580
2447 13:58:42.290918 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2448 13:58:42.290997
2449 13:58:42.294003 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2450 13:58:42.297405 [DutyScan_Calibration_Flow] ====Done====
2451 13:58:42.297478
2452 13:58:42.300796 [DutyScan_Calibration_Flow] k_type=2
2453 13:58:42.317892
2454 13:58:42.317979 ==DQ 0 ==
2455 13:58:42.321446 Final DQ duty delay cell = 0
2456 13:58:42.324410 [0] MAX Duty = 5156%(X100), DQS PI = 62
2457 13:58:42.327863 [0] MIN Duty = 4907%(X100), DQS PI = 38
2458 13:58:42.327938 [0] AVG Duty = 5031%(X100)
2459 13:58:42.331188
2460 13:58:42.331269 ==DQ 1 ==
2461 13:58:42.334300 Final DQ duty delay cell = 0
2462 13:58:42.338067 [0] MAX Duty = 5124%(X100), DQS PI = 42
2463 13:58:42.341137 [0] MIN Duty = 4969%(X100), DQS PI = 2
2464 13:58:42.341209 [0] AVG Duty = 5046%(X100)
2465 13:58:42.341270
2466 13:58:42.344662 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2467 13:58:42.348359
2468 13:58:42.350690 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2469 13:58:42.354494 [DutyScan_Calibration_Flow] ====Done====
2470 13:58:42.357432 nWR fixed to 30
2471 13:58:42.357507 [ModeRegInit_LP4] CH0 RK0
2472 13:58:42.360974 [ModeRegInit_LP4] CH0 RK1
2473 13:58:42.364294 [ModeRegInit_LP4] CH1 RK0
2474 13:58:42.367654 [ModeRegInit_LP4] CH1 RK1
2475 13:58:42.367726 match AC timing 7
2476 13:58:42.370746 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2477 13:58:42.377358 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2478 13:58:42.380586 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2479 13:58:42.387658 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2480 13:58:42.390721 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2481 13:58:42.390787 ==
2482 13:58:42.393843 Dram Type= 6, Freq= 0, CH_0, rank 0
2483 13:58:42.397755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 13:58:42.397822 ==
2485 13:58:42.404045 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 13:58:42.410665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2487 13:58:42.417450 [CA 0] Center 39 (9~70) winsize 62
2488 13:58:42.420992 [CA 1] Center 39 (9~69) winsize 61
2489 13:58:42.424350 [CA 2] Center 35 (5~66) winsize 62
2490 13:58:42.427836 [CA 3] Center 35 (4~66) winsize 63
2491 13:58:42.430938 [CA 4] Center 33 (4~63) winsize 60
2492 13:58:42.434046 [CA 5] Center 33 (3~63) winsize 61
2493 13:58:42.434117
2494 13:58:42.437520 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2495 13:58:42.437590
2496 13:58:42.440715 [CATrainingPosCal] consider 1 rank data
2497 13:58:42.444203 u2DelayCellTimex100 = 270/100 ps
2498 13:58:42.447328 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2499 13:58:42.454379 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2500 13:58:42.457364 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2501 13:58:42.461328 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2502 13:58:42.464208 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2503 13:58:42.467167 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2504 13:58:42.467242
2505 13:58:42.470572 CA PerBit enable=1, Macro0, CA PI delay=33
2506 13:58:42.470678
2507 13:58:42.473946 [CBTSetCACLKResult] CA Dly = 33
2508 13:58:42.474010 CS Dly: 8 (0~39)
2509 13:58:42.477518 ==
2510 13:58:42.480540 Dram Type= 6, Freq= 0, CH_0, rank 1
2511 13:58:42.483911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 13:58:42.483977 ==
2513 13:58:42.487637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 13:58:42.494036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2515 13:58:42.503880 [CA 0] Center 39 (9~70) winsize 62
2516 13:58:42.507286 [CA 1] Center 39 (9~70) winsize 62
2517 13:58:42.509812 [CA 2] Center 35 (5~66) winsize 62
2518 13:58:42.513358 [CA 3] Center 34 (4~65) winsize 62
2519 13:58:42.516906 [CA 4] Center 33 (3~64) winsize 62
2520 13:58:42.519872 [CA 5] Center 33 (3~63) winsize 61
2521 13:58:42.519943
2522 13:58:42.523518 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2523 13:58:42.523587
2524 13:58:42.526912 [CATrainingPosCal] consider 2 rank data
2525 13:58:42.530203 u2DelayCellTimex100 = 270/100 ps
2526 13:58:42.533803 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2527 13:58:42.539816 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2528 13:58:42.543368 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2529 13:58:42.546535 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2530 13:58:42.550207 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2531 13:58:42.553222 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2532 13:58:42.553295
2533 13:58:42.556216 CA PerBit enable=1, Macro0, CA PI delay=33
2534 13:58:42.556283
2535 13:58:42.559782 [CBTSetCACLKResult] CA Dly = 33
2536 13:58:42.559860 CS Dly: 9 (0~41)
2537 13:58:42.563073
2538 13:58:42.566729 ----->DramcWriteLeveling(PI) begin...
2539 13:58:42.566801 ==
2540 13:58:42.570099 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 13:58:42.573224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 13:58:42.573292 ==
2543 13:58:42.576411 Write leveling (Byte 0): 33 => 33
2544 13:58:42.580426 Write leveling (Byte 1): 29 => 29
2545 13:58:42.583159 DramcWriteLeveling(PI) end<-----
2546 13:58:42.583228
2547 13:58:42.583285 ==
2548 13:58:42.586276 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 13:58:42.589828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 13:58:42.589902 ==
2551 13:58:42.593010 [Gating] SW mode calibration
2552 13:58:42.599565 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2553 13:58:42.606533 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2554 13:58:42.609356 0 15 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
2555 13:58:42.613014 0 15 4 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
2556 13:58:42.619280 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2557 13:58:42.622511 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2558 13:58:42.626093 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2559 13:58:42.632779 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 13:58:42.636018 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2561 13:58:42.639357 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
2562 13:58:42.645910 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
2563 13:58:42.649228 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 13:58:42.652580 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 13:58:42.659113 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 13:58:42.662589 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 13:58:42.665978 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 13:58:42.669248 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 13:58:42.675928 1 0 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
2570 13:58:42.679415 1 1 0 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
2571 13:58:42.682503 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2572 13:58:42.689750 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 13:58:42.692879 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 13:58:42.695872 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 13:58:42.702740 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 13:58:42.705866 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 13:58:42.710024 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2578 13:58:42.715950 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2579 13:58:42.719545 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 13:58:42.722875 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 13:58:42.729495 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 13:58:42.732567 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 13:58:42.736008 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 13:58:42.742443 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 13:58:42.745780 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 13:58:42.749372 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 13:58:42.755373 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 13:58:42.758806 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 13:58:42.762175 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 13:58:42.769109 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 13:58:42.772431 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 13:58:42.775452 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 13:58:42.781919 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2594 13:58:42.785612 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2595 13:58:42.788599 Total UI for P1: 0, mck2ui 16
2596 13:58:42.791963 best dqsien dly found for B0: ( 1, 3, 28)
2597 13:58:42.795647 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2598 13:58:42.802108 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 13:58:42.802567 Total UI for P1: 0, mck2ui 16
2600 13:58:42.808493 best dqsien dly found for B1: ( 1, 4, 2)
2601 13:58:42.812276 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2602 13:58:42.815777 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2603 13:58:42.816210
2604 13:58:42.818881 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2605 13:58:42.821814 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2606 13:58:42.825188 [Gating] SW calibration Done
2607 13:58:42.825722 ==
2608 13:58:42.828663 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 13:58:42.832079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 13:58:42.832509 ==
2611 13:58:42.835105 RX Vref Scan: 0
2612 13:58:42.835625
2613 13:58:42.836143 RX Vref 0 -> 0, step: 1
2614 13:58:42.836470
2615 13:58:42.838690 RX Delay -40 -> 252, step: 8
2616 13:58:42.841909 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2617 13:58:42.848870 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2618 13:58:42.851762 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2619 13:58:42.855953 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2620 13:58:42.858693 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2621 13:58:42.862117 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2622 13:58:42.868519 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2623 13:58:42.871582 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2624 13:58:42.874983 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2625 13:58:42.878294 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2626 13:58:42.881942 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2627 13:58:42.888709 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2628 13:58:42.892189 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2629 13:58:42.895233 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2630 13:58:42.898198 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2631 13:58:42.901830 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2632 13:58:42.902258 ==
2633 13:58:42.905006 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 13:58:42.912312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 13:58:42.912767 ==
2636 13:58:42.913131 DQS Delay:
2637 13:58:42.915370 DQS0 = 0, DQS1 = 0
2638 13:58:42.915830 DQM Delay:
2639 13:58:42.918709 DQM0 = 119, DQM1 = 106
2640 13:58:42.919169 DQ Delay:
2641 13:58:42.921621 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2642 13:58:42.925065 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2643 13:58:42.928191 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2644 13:58:42.931425 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2645 13:58:42.931857
2646 13:58:42.932182
2647 13:58:42.932500 ==
2648 13:58:42.934849 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 13:58:42.941825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 13:58:42.942251 ==
2651 13:58:42.942622
2652 13:58:42.943124
2653 13:58:42.943454 TX Vref Scan disable
2654 13:58:42.945110 == TX Byte 0 ==
2655 13:58:42.948858 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2656 13:58:42.951640 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2657 13:58:42.954779 == TX Byte 1 ==
2658 13:58:42.958414 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2659 13:58:42.964877 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2660 13:58:42.965297 ==
2661 13:58:42.968085 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 13:58:42.971534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 13:58:42.971973 ==
2664 13:58:42.983056 TX Vref=22, minBit 7, minWin=25, winSum=414
2665 13:58:42.985812 TX Vref=24, minBit 1, minWin=25, winSum=423
2666 13:58:42.989737 TX Vref=26, minBit 8, minWin=26, winSum=431
2667 13:58:42.992642 TX Vref=28, minBit 10, minWin=26, winSum=435
2668 13:58:42.996131 TX Vref=30, minBit 5, minWin=26, winSum=434
2669 13:58:43.002572 TX Vref=32, minBit 10, minWin=25, winSum=430
2670 13:58:43.005925 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
2671 13:58:43.006360
2672 13:58:43.009321 Final TX Range 1 Vref 28
2673 13:58:43.009756
2674 13:58:43.010195 ==
2675 13:58:43.012695 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 13:58:43.015612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 13:58:43.019390 ==
2678 13:58:43.019863
2679 13:58:43.020361
2680 13:58:43.020699 TX Vref Scan disable
2681 13:58:43.023110 == TX Byte 0 ==
2682 13:58:43.025866 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2683 13:58:43.032561 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2684 13:58:43.032982 == TX Byte 1 ==
2685 13:58:43.035972 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2686 13:58:43.042734 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2687 13:58:43.043304
2688 13:58:43.043646 [DATLAT]
2689 13:58:43.043973 Freq=1200, CH0 RK0
2690 13:58:43.044274
2691 13:58:43.046345 DATLAT Default: 0xd
2692 13:58:43.046808 0, 0xFFFF, sum = 0
2693 13:58:43.049067 1, 0xFFFF, sum = 0
2694 13:58:43.052778 2, 0xFFFF, sum = 0
2695 13:58:43.053203 3, 0xFFFF, sum = 0
2696 13:58:43.056223 4, 0xFFFF, sum = 0
2697 13:58:43.056646 5, 0xFFFF, sum = 0
2698 13:58:43.059174 6, 0xFFFF, sum = 0
2699 13:58:43.059599 7, 0xFFFF, sum = 0
2700 13:58:43.062530 8, 0xFFFF, sum = 0
2701 13:58:43.063015 9, 0xFFFF, sum = 0
2702 13:58:43.066352 10, 0xFFFF, sum = 0
2703 13:58:43.066941 11, 0xFFFF, sum = 0
2704 13:58:43.069139 12, 0x0, sum = 1
2705 13:58:43.069566 13, 0x0, sum = 2
2706 13:58:43.072583 14, 0x0, sum = 3
2707 13:58:43.073023 15, 0x0, sum = 4
2708 13:58:43.073378 best_step = 13
2709 13:58:43.076395
2710 13:58:43.076771 ==
2711 13:58:43.079266 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 13:58:43.083218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 13:58:43.083598 ==
2714 13:58:43.083959 RX Vref Scan: 1
2715 13:58:43.084263
2716 13:58:43.085994 Set Vref Range= 32 -> 127
2717 13:58:43.086358
2718 13:58:43.089249 RX Vref 32 -> 127, step: 1
2719 13:58:43.089653
2720 13:58:43.092497 RX Delay -21 -> 252, step: 4
2721 13:58:43.092930
2722 13:58:43.095929 Set Vref, RX VrefLevel [Byte0]: 32
2723 13:58:43.099106 [Byte1]: 32
2724 13:58:43.099541
2725 13:58:43.102490 Set Vref, RX VrefLevel [Byte0]: 33
2726 13:58:43.106051 [Byte1]: 33
2727 13:58:43.109140
2728 13:58:43.109679 Set Vref, RX VrefLevel [Byte0]: 34
2729 13:58:43.112888 [Byte1]: 34
2730 13:58:43.117560
2731 13:58:43.117991 Set Vref, RX VrefLevel [Byte0]: 35
2732 13:58:43.120412 [Byte1]: 35
2733 13:58:43.125402
2734 13:58:43.125832 Set Vref, RX VrefLevel [Byte0]: 36
2735 13:58:43.128400 [Byte1]: 36
2736 13:58:43.133080
2737 13:58:43.133511 Set Vref, RX VrefLevel [Byte0]: 37
2738 13:58:43.136272 [Byte1]: 37
2739 13:58:43.141061
2740 13:58:43.141545 Set Vref, RX VrefLevel [Byte0]: 38
2741 13:58:43.144487 [Byte1]: 38
2742 13:58:43.148857
2743 13:58:43.149292 Set Vref, RX VrefLevel [Byte0]: 39
2744 13:58:43.152762 [Byte1]: 39
2745 13:58:43.157893
2746 13:58:43.158325 Set Vref, RX VrefLevel [Byte0]: 40
2747 13:58:43.163121 [Byte1]: 40
2748 13:58:43.163554
2749 13:58:43.166891 Set Vref, RX VrefLevel [Byte0]: 41
2750 13:58:43.169832 [Byte1]: 41
2751 13:58:43.170245
2752 13:58:43.173819 Set Vref, RX VrefLevel [Byte0]: 42
2753 13:58:43.176863 [Byte1]: 42
2754 13:58:43.180509
2755 13:58:43.180920 Set Vref, RX VrefLevel [Byte0]: 43
2756 13:58:43.183886 [Byte1]: 43
2757 13:58:43.188236
2758 13:58:43.188649 Set Vref, RX VrefLevel [Byte0]: 44
2759 13:58:43.191662 [Byte1]: 44
2760 13:58:43.196252
2761 13:58:43.196665 Set Vref, RX VrefLevel [Byte0]: 45
2762 13:58:43.200277 [Byte1]: 45
2763 13:58:43.204232
2764 13:58:43.204654 Set Vref, RX VrefLevel [Byte0]: 46
2765 13:58:43.207856 [Byte1]: 46
2766 13:58:43.212128
2767 13:58:43.212542 Set Vref, RX VrefLevel [Byte0]: 47
2768 13:58:43.215256 [Byte1]: 47
2769 13:58:43.220500
2770 13:58:43.220911 Set Vref, RX VrefLevel [Byte0]: 48
2771 13:58:43.223408 [Byte1]: 48
2772 13:58:43.228732
2773 13:58:43.229146 Set Vref, RX VrefLevel [Byte0]: 49
2774 13:58:43.231113 [Byte1]: 49
2775 13:58:43.236631
2776 13:58:43.237042 Set Vref, RX VrefLevel [Byte0]: 50
2777 13:58:43.239461 [Byte1]: 50
2778 13:58:43.244618
2779 13:58:43.245029 Set Vref, RX VrefLevel [Byte0]: 51
2780 13:58:43.247041 [Byte1]: 51
2781 13:58:43.252051
2782 13:58:43.252463 Set Vref, RX VrefLevel [Byte0]: 52
2783 13:58:43.255494 [Byte1]: 52
2784 13:58:43.260032
2785 13:58:43.260446 Set Vref, RX VrefLevel [Byte0]: 53
2786 13:58:43.263211 [Byte1]: 53
2787 13:58:43.267398
2788 13:58:43.267942 Set Vref, RX VrefLevel [Byte0]: 54
2789 13:58:43.271308 [Byte1]: 54
2790 13:58:43.275745
2791 13:58:43.276162 Set Vref, RX VrefLevel [Byte0]: 55
2792 13:58:43.279338 [Byte1]: 55
2793 13:58:43.283885
2794 13:58:43.284295 Set Vref, RX VrefLevel [Byte0]: 56
2795 13:58:43.287151 [Byte1]: 56
2796 13:58:43.291370
2797 13:58:43.291784 Set Vref, RX VrefLevel [Byte0]: 57
2798 13:58:43.294891 [Byte1]: 57
2799 13:58:43.299423
2800 13:58:43.299834 Set Vref, RX VrefLevel [Byte0]: 58
2801 13:58:43.302876 [Byte1]: 58
2802 13:58:43.307422
2803 13:58:43.307833 Set Vref, RX VrefLevel [Byte0]: 59
2804 13:58:43.310722 [Byte1]: 59
2805 13:58:43.315369
2806 13:58:43.315763 Set Vref, RX VrefLevel [Byte0]: 60
2807 13:58:43.318782 [Byte1]: 60
2808 13:58:43.322915
2809 13:58:43.323324 Set Vref, RX VrefLevel [Byte0]: 61
2810 13:58:43.326276 [Byte1]: 61
2811 13:58:43.331240
2812 13:58:43.331903 Set Vref, RX VrefLevel [Byte0]: 62
2813 13:58:43.334162 [Byte1]: 62
2814 13:58:43.339419
2815 13:58:43.339856 Set Vref, RX VrefLevel [Byte0]: 63
2816 13:58:43.342532 [Byte1]: 63
2817 13:58:43.347217
2818 13:58:43.347701 Set Vref, RX VrefLevel [Byte0]: 64
2819 13:58:43.350377 [Byte1]: 64
2820 13:58:43.354988
2821 13:58:43.355527 Set Vref, RX VrefLevel [Byte0]: 65
2822 13:58:43.361604 [Byte1]: 65
2823 13:58:43.362038
2824 13:58:43.365228 Set Vref, RX VrefLevel [Byte0]: 66
2825 13:58:43.368284 [Byte1]: 66
2826 13:58:43.368715
2827 13:58:43.371882 Set Vref, RX VrefLevel [Byte0]: 67
2828 13:58:43.374757 [Byte1]: 67
2829 13:58:43.378762
2830 13:58:43.379180 Set Vref, RX VrefLevel [Byte0]: 68
2831 13:58:43.382022 [Byte1]: 68
2832 13:58:43.386531
2833 13:58:43.387002 Set Vref, RX VrefLevel [Byte0]: 69
2834 13:58:43.389762 [Byte1]: 69
2835 13:58:43.394454
2836 13:58:43.394924 Set Vref, RX VrefLevel [Byte0]: 70
2837 13:58:43.397980 [Byte1]: 70
2838 13:58:43.402486
2839 13:58:43.402914 Set Vref, RX VrefLevel [Byte0]: 71
2840 13:58:43.406371 [Byte1]: 71
2841 13:58:43.410546
2842 13:58:43.411200 Set Vref, RX VrefLevel [Byte0]: 72
2843 13:58:43.414052 [Byte1]: 72
2844 13:58:43.418269
2845 13:58:43.418752 Set Vref, RX VrefLevel [Byte0]: 73
2846 13:58:43.421874 [Byte1]: 73
2847 13:58:43.426368
2848 13:58:43.426887 Set Vref, RX VrefLevel [Byte0]: 74
2849 13:58:43.429655 [Byte1]: 74
2850 13:58:43.434023
2851 13:58:43.434442 Set Vref, RX VrefLevel [Byte0]: 75
2852 13:58:43.437799 [Byte1]: 75
2853 13:58:43.441941
2854 13:58:43.442357 Final RX Vref Byte 0 = 63 to rank0
2855 13:58:43.445292 Final RX Vref Byte 1 = 55 to rank0
2856 13:58:43.449480 Final RX Vref Byte 0 = 63 to rank1
2857 13:58:43.452046 Final RX Vref Byte 1 = 55 to rank1==
2858 13:58:43.455583 Dram Type= 6, Freq= 0, CH_0, rank 0
2859 13:58:43.462234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2860 13:58:43.462697 ==
2861 13:58:43.463039 DQS Delay:
2862 13:58:43.463351 DQS0 = 0, DQS1 = 0
2863 13:58:43.465320 DQM Delay:
2864 13:58:43.465739 DQM0 = 119, DQM1 = 108
2865 13:58:43.468715 DQ Delay:
2866 13:58:43.471906 DQ0 =116, DQ1 =118, DQ2 =116, DQ3 =118
2867 13:58:43.475045 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =126
2868 13:58:43.478580 DQ8 =98, DQ9 =96, DQ10 =110, DQ11 =102
2869 13:58:43.481993 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =116
2870 13:58:43.482543
2871 13:58:43.483015
2872 13:58:43.491860 [DQSOSCAuto] RK0, (LSB)MR18= 0x1400, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 402 ps
2873 13:58:43.492441 CH0 RK0: MR19=404, MR18=1400
2874 13:58:43.498242 CH0_RK0: MR19=0x404, MR18=0x1400, DQSOSC=402, MR23=63, INC=40, DEC=27
2875 13:58:43.498857
2876 13:58:43.501963 ----->DramcWriteLeveling(PI) begin...
2877 13:58:43.502550 ==
2878 13:58:43.505037 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 13:58:43.511867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 13:58:43.512495 ==
2881 13:58:43.514785 Write leveling (Byte 0): 33 => 33
2882 13:58:43.515301 Write leveling (Byte 1): 29 => 29
2883 13:58:43.518460 DramcWriteLeveling(PI) end<-----
2884 13:58:43.519024
2885 13:58:43.521673 ==
2886 13:58:43.522259 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 13:58:43.528222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 13:58:43.528861 ==
2889 13:58:43.531705 [Gating] SW mode calibration
2890 13:58:43.538361 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2891 13:58:43.541096 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2892 13:58:43.548175 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2893 13:58:43.551336 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2894 13:58:43.554901 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 13:58:43.561820 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 13:58:43.564403 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 13:58:43.568527 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 13:58:43.574537 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 13:58:43.577657 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2900 13:58:43.580830 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
2901 13:58:43.587834 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 13:58:43.590877 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 13:58:43.594578 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 13:58:43.600930 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 13:58:43.604488 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 13:58:43.607298 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 13:58:43.613859 1 0 28 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
2908 13:58:43.617000 1 1 0 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
2909 13:58:43.620801 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 13:58:43.627607 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 13:58:43.630224 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 13:58:43.633642 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 13:58:43.640497 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 13:58:43.643723 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2915 13:58:43.647240 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2916 13:58:43.650527 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2917 13:58:43.657415 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 13:58:43.660487 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 13:58:43.663739 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 13:58:43.670183 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 13:58:43.673789 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 13:58:43.676976 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 13:58:43.683665 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 13:58:43.686970 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 13:58:43.690460 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 13:58:43.696891 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 13:58:43.700225 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 13:58:43.703504 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 13:58:43.710149 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 13:58:43.713436 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 13:58:43.717094 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2932 13:58:43.723658 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 13:58:43.723739 Total UI for P1: 0, mck2ui 16
2934 13:58:43.730128 best dqsien dly found for B0: ( 1, 3, 28)
2935 13:58:43.730218 Total UI for P1: 0, mck2ui 16
2936 13:58:43.736684 best dqsien dly found for B1: ( 1, 3, 30)
2937 13:58:43.740205 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2938 13:58:43.743521 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2939 13:58:43.743603
2940 13:58:43.746596 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2941 13:58:43.750232 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2942 13:58:43.754113 [Gating] SW calibration Done
2943 13:58:43.754194 ==
2944 13:58:43.756962 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 13:58:43.759931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 13:58:43.760007 ==
2947 13:58:43.763327 RX Vref Scan: 0
2948 13:58:43.763408
2949 13:58:43.763469 RX Vref 0 -> 0, step: 1
2950 13:58:43.763528
2951 13:58:43.766704 RX Delay -40 -> 252, step: 8
2952 13:58:43.769509 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2953 13:58:43.776237 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2954 13:58:43.780797 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2955 13:58:43.783122 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2956 13:58:43.786533 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2957 13:58:43.789952 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2958 13:58:43.796292 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2959 13:58:43.800019 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2960 13:58:43.802959 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2961 13:58:43.806371 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2962 13:58:43.809852 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2963 13:58:43.816387 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2964 13:58:43.819804 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2965 13:58:43.823566 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2966 13:58:43.826377 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2967 13:58:43.829879 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2968 13:58:43.833193 ==
2969 13:58:43.833272 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 13:58:43.839493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 13:58:43.839574 ==
2972 13:58:43.839637 DQS Delay:
2973 13:58:43.842895 DQS0 = 0, DQS1 = 0
2974 13:58:43.842974 DQM Delay:
2975 13:58:43.846449 DQM0 = 117, DQM1 = 108
2976 13:58:43.846529 DQ Delay:
2977 13:58:43.849920 DQ0 =115, DQ1 =123, DQ2 =111, DQ3 =115
2978 13:58:43.852622 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2979 13:58:43.856359 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2980 13:58:43.859286 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2981 13:58:43.859366
2982 13:58:43.859430
2983 13:58:43.859489 ==
2984 13:58:43.862927 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 13:58:43.869149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 13:58:43.869226 ==
2987 13:58:43.869295
2988 13:58:43.869354
2989 13:58:43.869410 TX Vref Scan disable
2990 13:58:43.873043 == TX Byte 0 ==
2991 13:58:43.876807 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2992 13:58:43.882844 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2993 13:58:43.882920 == TX Byte 1 ==
2994 13:58:43.886184 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2995 13:58:43.892689 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2996 13:58:43.892764 ==
2997 13:58:43.896151 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 13:58:43.899295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 13:58:43.899367 ==
3000 13:58:43.910977 TX Vref=22, minBit 13, minWin=25, winSum=420
3001 13:58:43.914227 TX Vref=24, minBit 13, minWin=25, winSum=420
3002 13:58:43.917610 TX Vref=26, minBit 1, minWin=26, winSum=429
3003 13:58:43.920745 TX Vref=28, minBit 12, minWin=26, winSum=431
3004 13:58:43.927889 TX Vref=30, minBit 13, minWin=26, winSum=434
3005 13:58:43.931057 TX Vref=32, minBit 13, minWin=25, winSum=433
3006 13:58:43.934214 [TxChooseVref] Worse bit 13, Min win 26, Win sum 434, Final Vref 30
3007 13:58:43.937818
3008 13:58:43.937892 Final TX Range 1 Vref 30
3009 13:58:43.937954
3010 13:58:43.938013 ==
3011 13:58:43.940646 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 13:58:43.947652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 13:58:43.947729 ==
3014 13:58:43.947799
3015 13:58:43.947859
3016 13:58:43.947916 TX Vref Scan disable
3017 13:58:43.951590 == TX Byte 0 ==
3018 13:58:43.954535 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3019 13:58:43.961420 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3020 13:58:43.961500 == TX Byte 1 ==
3021 13:58:43.964706 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3022 13:58:43.971550 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3023 13:58:43.971646
3024 13:58:43.971711 [DATLAT]
3025 13:58:43.971770 Freq=1200, CH0 RK1
3026 13:58:43.971828
3027 13:58:43.974962 DATLAT Default: 0xd
3028 13:58:43.975042 0, 0xFFFF, sum = 0
3029 13:58:43.977929 1, 0xFFFF, sum = 0
3030 13:58:43.981888 2, 0xFFFF, sum = 0
3031 13:58:43.981982 3, 0xFFFF, sum = 0
3032 13:58:43.984609 4, 0xFFFF, sum = 0
3033 13:58:43.984691 5, 0xFFFF, sum = 0
3034 13:58:43.987891 6, 0xFFFF, sum = 0
3035 13:58:43.987972 7, 0xFFFF, sum = 0
3036 13:58:43.991108 8, 0xFFFF, sum = 0
3037 13:58:43.991189 9, 0xFFFF, sum = 0
3038 13:58:43.994383 10, 0xFFFF, sum = 0
3039 13:58:43.994490 11, 0xFFFF, sum = 0
3040 13:58:43.998028 12, 0x0, sum = 1
3041 13:58:43.998109 13, 0x0, sum = 2
3042 13:58:44.001081 14, 0x0, sum = 3
3043 13:58:44.001162 15, 0x0, sum = 4
3044 13:58:44.004405 best_step = 13
3045 13:58:44.004485
3046 13:58:44.004547 ==
3047 13:58:44.007595 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 13:58:44.011179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 13:58:44.011259 ==
3050 13:58:44.011321 RX Vref Scan: 0
3051 13:58:44.011380
3052 13:58:44.014807 RX Vref 0 -> 0, step: 1
3053 13:58:44.014887
3054 13:58:44.017771 RX Delay -21 -> 252, step: 4
3055 13:58:44.021216 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3056 13:58:44.027995 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3057 13:58:44.031075 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3058 13:58:44.034496 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3059 13:58:44.038215 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3060 13:58:44.041143 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3061 13:58:44.047925 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3062 13:58:44.050770 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3063 13:58:44.054318 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3064 13:58:44.057520 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3065 13:58:44.061170 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3066 13:58:44.067416 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3067 13:58:44.070929 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3068 13:58:44.074002 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3069 13:58:44.077285 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3070 13:58:44.084109 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3071 13:58:44.084188 ==
3072 13:58:44.087293 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 13:58:44.090728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 13:58:44.090808 ==
3075 13:58:44.090871 DQS Delay:
3076 13:58:44.094042 DQS0 = 0, DQS1 = 0
3077 13:58:44.094121 DQM Delay:
3078 13:58:44.097650 DQM0 = 115, DQM1 = 108
3079 13:58:44.097729 DQ Delay:
3080 13:58:44.100668 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =112
3081 13:58:44.104290 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =122
3082 13:58:44.107383 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100
3083 13:58:44.110695 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =116
3084 13:58:44.110774
3085 13:58:44.110836
3086 13:58:44.120909 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 403 ps
3087 13:58:44.124031 CH0 RK1: MR19=403, MR18=10EA
3088 13:58:44.127487 CH0_RK1: MR19=0x403, MR18=0x10EA, DQSOSC=403, MR23=63, INC=40, DEC=26
3089 13:58:44.130839 [RxdqsGatingPostProcess] freq 1200
3090 13:58:44.137093 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3091 13:58:44.140611 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 13:58:44.144066 best DQS1 dly(2T, 0.5T) = (0, 12)
3093 13:58:44.147065 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 13:58:44.150804 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3095 13:58:44.153577 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 13:58:44.157111 best DQS1 dly(2T, 0.5T) = (0, 11)
3097 13:58:44.160797 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 13:58:44.163675 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3099 13:58:44.163755 Pre-setting of DQS Precalculation
3100 13:58:44.170861 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3101 13:58:44.170941 ==
3102 13:58:44.174227 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 13:58:44.177276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 13:58:44.177356 ==
3105 13:58:44.183973 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 13:58:44.190540 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3107 13:58:44.197884 [CA 0] Center 37 (7~67) winsize 61
3108 13:58:44.201146 [CA 1] Center 37 (7~68) winsize 62
3109 13:58:44.204305 [CA 2] Center 34 (4~64) winsize 61
3110 13:58:44.207994 [CA 3] Center 33 (3~64) winsize 62
3111 13:58:44.211014 [CA 4] Center 34 (4~64) winsize 61
3112 13:58:44.214318 [CA 5] Center 33 (3~64) winsize 62
3113 13:58:44.214419
3114 13:58:44.217755 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3115 13:58:44.217826
3116 13:58:44.221469 [CATrainingPosCal] consider 1 rank data
3117 13:58:44.224843 u2DelayCellTimex100 = 270/100 ps
3118 13:58:44.227748 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3119 13:58:44.231132 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 13:58:44.238040 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3121 13:58:44.241327 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3122 13:58:44.244483 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 13:58:44.248278 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3124 13:58:44.248358
3125 13:58:44.250963 CA PerBit enable=1, Macro0, CA PI delay=33
3126 13:58:44.251043
3127 13:58:44.254288 [CBTSetCACLKResult] CA Dly = 33
3128 13:58:44.254368 CS Dly: 6 (0~37)
3129 13:58:44.254431 ==
3130 13:58:44.257786 Dram Type= 6, Freq= 0, CH_1, rank 1
3131 13:58:44.264471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 13:58:44.264551 ==
3133 13:58:44.267681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 13:58:44.273996 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3135 13:58:44.283051 [CA 0] Center 37 (7~68) winsize 62
3136 13:58:44.286491 [CA 1] Center 38 (8~68) winsize 61
3137 13:58:44.290093 [CA 2] Center 34 (4~65) winsize 62
3138 13:58:44.293097 [CA 3] Center 33 (3~64) winsize 62
3139 13:58:44.296509 [CA 4] Center 34 (3~65) winsize 63
3140 13:58:44.299864 [CA 5] Center 33 (3~64) winsize 62
3141 13:58:44.299944
3142 13:58:44.303048 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3143 13:58:44.303127
3144 13:58:44.306564 [CATrainingPosCal] consider 2 rank data
3145 13:58:44.309701 u2DelayCellTimex100 = 270/100 ps
3146 13:58:44.313051 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3147 13:58:44.319970 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3148 13:58:44.322978 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3149 13:58:44.326314 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3150 13:58:44.329664 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 13:58:44.332782 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3152 13:58:44.332862
3153 13:58:44.336457 CA PerBit enable=1, Macro0, CA PI delay=33
3154 13:58:44.336536
3155 13:58:44.340141 [CBTSetCACLKResult] CA Dly = 33
3156 13:58:44.340220 CS Dly: 7 (0~40)
3157 13:58:44.343333
3158 13:58:44.346215 ----->DramcWriteLeveling(PI) begin...
3159 13:58:44.346297 ==
3160 13:58:44.349565 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 13:58:44.352783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 13:58:44.352857 ==
3163 13:58:44.356284 Write leveling (Byte 0): 23 => 23
3164 13:58:44.359495 Write leveling (Byte 1): 28 => 28
3165 13:58:44.362672 DramcWriteLeveling(PI) end<-----
3166 13:58:44.362753
3167 13:58:44.362816 ==
3168 13:58:44.366208 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 13:58:44.369622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 13:58:44.369729 ==
3171 13:58:44.373227 [Gating] SW mode calibration
3172 13:58:44.379525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3173 13:58:44.386131 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3174 13:58:44.389702 0 15 0 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
3175 13:58:44.392871 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 13:58:44.399313 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 13:58:44.402788 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 13:58:44.405947 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 13:58:44.412978 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 13:58:44.415950 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
3181 13:58:44.418924 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (1 0)
3182 13:58:44.425663 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 13:58:44.429313 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 13:58:44.432837 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 13:58:44.439093 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 13:58:44.442834 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 13:58:44.445723 1 0 20 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
3188 13:58:44.452503 1 0 24 | B1->B0 | 2727 3c3c | 1 0 | (0 0) (1 1)
3189 13:58:44.455662 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3190 13:58:44.458656 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 13:58:44.465643 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 13:58:44.469154 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 13:58:44.471905 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 13:58:44.478483 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 13:58:44.481757 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 13:58:44.485276 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3197 13:58:44.491790 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3198 13:58:44.495193 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 13:58:44.498692 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 13:58:44.501731 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 13:58:44.508352 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 13:58:44.512321 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 13:58:44.514970 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 13:58:44.521923 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 13:58:44.525164 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 13:58:44.528478 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 13:58:44.535560 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 13:58:44.538107 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 13:58:44.541466 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 13:58:44.548455 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 13:58:44.551540 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 13:58:44.554991 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3213 13:58:44.561625 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3214 13:58:44.565056 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 13:58:44.568378 Total UI for P1: 0, mck2ui 16
3216 13:58:44.571814 best dqsien dly found for B0: ( 1, 3, 26)
3217 13:58:44.574729 Total UI for P1: 0, mck2ui 16
3218 13:58:44.578333 best dqsien dly found for B1: ( 1, 3, 26)
3219 13:58:44.581219 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3220 13:58:44.584570 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3221 13:58:44.584651
3222 13:58:44.588339 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3223 13:58:44.591429 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3224 13:58:44.594791 [Gating] SW calibration Done
3225 13:58:44.594872 ==
3226 13:58:44.598012 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 13:58:44.605223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 13:58:44.605303 ==
3229 13:58:44.605367 RX Vref Scan: 0
3230 13:58:44.605426
3231 13:58:44.607679 RX Vref 0 -> 0, step: 1
3232 13:58:44.607760
3233 13:58:44.611105 RX Delay -40 -> 252, step: 8
3234 13:58:44.614877 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3235 13:58:44.617751 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3236 13:58:44.620961 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3237 13:58:44.624624 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3238 13:58:44.631523 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3239 13:58:44.634599 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3240 13:58:44.637551 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3241 13:58:44.641471 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3242 13:58:44.644494 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3243 13:58:44.650977 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3244 13:58:44.654070 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3245 13:58:44.657660 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3246 13:58:44.661317 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3247 13:58:44.665140 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3248 13:58:44.671364 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3249 13:58:44.674853 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3250 13:58:44.674927 ==
3251 13:58:44.677635 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 13:58:44.681117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 13:58:44.681187 ==
3254 13:58:44.684714 DQS Delay:
3255 13:58:44.684790 DQS0 = 0, DQS1 = 0
3256 13:58:44.684850 DQM Delay:
3257 13:58:44.687382 DQM0 = 118, DQM1 = 110
3258 13:58:44.687448 DQ Delay:
3259 13:58:44.691238 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3260 13:58:44.694419 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3261 13:58:44.697346 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3262 13:58:44.704312 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3263 13:58:44.704389
3264 13:58:44.704450
3265 13:58:44.704507 ==
3266 13:58:44.707512 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 13:58:44.710525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 13:58:44.710623 ==
3269 13:58:44.710686
3270 13:58:44.710750
3271 13:58:44.714233 TX Vref Scan disable
3272 13:58:44.714306 == TX Byte 0 ==
3273 13:58:44.720460 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3274 13:58:44.724470 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3275 13:58:44.724541 == TX Byte 1 ==
3276 13:58:44.730706 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3277 13:58:44.734041 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3278 13:58:44.734119 ==
3279 13:58:44.737605 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 13:58:44.741250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 13:58:44.741319 ==
3282 13:58:44.753616 TX Vref=22, minBit 11, minWin=24, winSum=414
3283 13:58:44.756873 TX Vref=24, minBit 0, minWin=26, winSum=424
3284 13:58:44.760342 TX Vref=26, minBit 0, minWin=26, winSum=426
3285 13:58:44.763973 TX Vref=28, minBit 10, minWin=25, winSum=427
3286 13:58:44.766737 TX Vref=30, minBit 9, minWin=25, winSum=425
3287 13:58:44.774189 TX Vref=32, minBit 9, minWin=25, winSum=421
3288 13:58:44.776740 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
3289 13:58:44.776822
3290 13:58:44.779967 Final TX Range 1 Vref 26
3291 13:58:44.780048
3292 13:58:44.780111 ==
3293 13:58:44.783457 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 13:58:44.787221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 13:58:44.789915 ==
3296 13:58:44.789993
3297 13:58:44.790055
3298 13:58:44.790112 TX Vref Scan disable
3299 13:58:44.793406 == TX Byte 0 ==
3300 13:58:44.796809 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3301 13:58:44.799788 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3302 13:58:44.803511 == TX Byte 1 ==
3303 13:58:44.807054 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3304 13:58:44.810300 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3305 13:58:44.813413
3306 13:58:44.813505 [DATLAT]
3307 13:58:44.813568 Freq=1200, CH1 RK0
3308 13:58:44.813662
3309 13:58:44.816824 DATLAT Default: 0xd
3310 13:58:44.816902 0, 0xFFFF, sum = 0
3311 13:58:44.820218 1, 0xFFFF, sum = 0
3312 13:58:44.820300 2, 0xFFFF, sum = 0
3313 13:58:44.823133 3, 0xFFFF, sum = 0
3314 13:58:44.826672 4, 0xFFFF, sum = 0
3315 13:58:44.826753 5, 0xFFFF, sum = 0
3316 13:58:44.829750 6, 0xFFFF, sum = 0
3317 13:58:44.829820 7, 0xFFFF, sum = 0
3318 13:58:44.833155 8, 0xFFFF, sum = 0
3319 13:58:44.833235 9, 0xFFFF, sum = 0
3320 13:58:44.836505 10, 0xFFFF, sum = 0
3321 13:58:44.836585 11, 0xFFFF, sum = 0
3322 13:58:44.839958 12, 0x0, sum = 1
3323 13:58:44.840057 13, 0x0, sum = 2
3324 13:58:44.842927 14, 0x0, sum = 3
3325 13:58:44.843007 15, 0x0, sum = 4
3326 13:58:44.846538 best_step = 13
3327 13:58:44.846667
3328 13:58:44.846730 ==
3329 13:58:44.850200 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 13:58:44.853318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 13:58:44.853398 ==
3332 13:58:44.853460 RX Vref Scan: 1
3333 13:58:44.853517
3334 13:58:44.856973 Set Vref Range= 32 -> 127
3335 13:58:44.857052
3336 13:58:44.859847 RX Vref 32 -> 127, step: 1
3337 13:58:44.859925
3338 13:58:44.863109 RX Delay -21 -> 252, step: 4
3339 13:58:44.863188
3340 13:58:44.866504 Set Vref, RX VrefLevel [Byte0]: 32
3341 13:58:44.869734 [Byte1]: 32
3342 13:58:44.869813
3343 13:58:44.873206 Set Vref, RX VrefLevel [Byte0]: 33
3344 13:58:44.876964 [Byte1]: 33
3345 13:58:44.879998
3346 13:58:44.880086 Set Vref, RX VrefLevel [Byte0]: 34
3347 13:58:44.883410 [Byte1]: 34
3348 13:58:44.887949
3349 13:58:44.888028 Set Vref, RX VrefLevel [Byte0]: 35
3350 13:58:44.890952 [Byte1]: 35
3351 13:58:44.895807
3352 13:58:44.895884 Set Vref, RX VrefLevel [Byte0]: 36
3353 13:58:44.898900 [Byte1]: 36
3354 13:58:44.903669
3355 13:58:44.903747 Set Vref, RX VrefLevel [Byte0]: 37
3356 13:58:44.907431 [Byte1]: 37
3357 13:58:44.911771
3358 13:58:44.911849 Set Vref, RX VrefLevel [Byte0]: 38
3359 13:58:44.915222 [Byte1]: 38
3360 13:58:44.919571
3361 13:58:44.919650 Set Vref, RX VrefLevel [Byte0]: 39
3362 13:58:44.922554 [Byte1]: 39
3363 13:58:44.927424
3364 13:58:44.927502 Set Vref, RX VrefLevel [Byte0]: 40
3365 13:58:44.930709 [Byte1]: 40
3366 13:58:44.935163
3367 13:58:44.935242 Set Vref, RX VrefLevel [Byte0]: 41
3368 13:58:44.938556 [Byte1]: 41
3369 13:58:44.943394
3370 13:58:44.943473 Set Vref, RX VrefLevel [Byte0]: 42
3371 13:58:44.946427 [Byte1]: 42
3372 13:58:44.951250
3373 13:58:44.951328 Set Vref, RX VrefLevel [Byte0]: 43
3374 13:58:44.954193 [Byte1]: 43
3375 13:58:44.959200
3376 13:58:44.959279 Set Vref, RX VrefLevel [Byte0]: 44
3377 13:58:44.962626 [Byte1]: 44
3378 13:58:44.966941
3379 13:58:44.967020 Set Vref, RX VrefLevel [Byte0]: 45
3380 13:58:44.970380 [Byte1]: 45
3381 13:58:44.975259
3382 13:58:44.975349 Set Vref, RX VrefLevel [Byte0]: 46
3383 13:58:44.979118 [Byte1]: 46
3384 13:58:44.982739
3385 13:58:44.982820 Set Vref, RX VrefLevel [Byte0]: 47
3386 13:58:44.985880 [Byte1]: 47
3387 13:58:44.990518
3388 13:58:44.990604 Set Vref, RX VrefLevel [Byte0]: 48
3389 13:58:44.993893 [Byte1]: 48
3390 13:58:44.998540
3391 13:58:44.998652 Set Vref, RX VrefLevel [Byte0]: 49
3392 13:58:45.001844 [Byte1]: 49
3393 13:58:45.007459
3394 13:58:45.007538 Set Vref, RX VrefLevel [Byte0]: 50
3395 13:58:45.013131 [Byte1]: 50
3396 13:58:45.013217
3397 13:58:45.016874 Set Vref, RX VrefLevel [Byte0]: 51
3398 13:58:45.019520 [Byte1]: 51
3399 13:58:45.019600
3400 13:58:45.022901 Set Vref, RX VrefLevel [Byte0]: 52
3401 13:58:45.026847 [Byte1]: 52
3402 13:58:45.030225
3403 13:58:45.030342 Set Vref, RX VrefLevel [Byte0]: 53
3404 13:58:45.034858 [Byte1]: 53
3405 13:58:45.038188
3406 13:58:45.038268 Set Vref, RX VrefLevel [Byte0]: 54
3407 13:58:45.041524 [Byte1]: 54
3408 13:58:45.046094
3409 13:58:45.046199 Set Vref, RX VrefLevel [Byte0]: 55
3410 13:58:45.049238 [Byte1]: 55
3411 13:58:45.054216
3412 13:58:45.054322 Set Vref, RX VrefLevel [Byte0]: 56
3413 13:58:45.058160 [Byte1]: 56
3414 13:58:45.061963
3415 13:58:45.062068 Set Vref, RX VrefLevel [Byte0]: 57
3416 13:58:45.065850 [Byte1]: 57
3417 13:58:45.069694
3418 13:58:45.069800 Set Vref, RX VrefLevel [Byte0]: 58
3419 13:58:45.072997 [Byte1]: 58
3420 13:58:45.078109
3421 13:58:45.078188 Set Vref, RX VrefLevel [Byte0]: 59
3422 13:58:45.081209 [Byte1]: 59
3423 13:58:45.085871
3424 13:58:45.085951 Set Vref, RX VrefLevel [Byte0]: 60
3425 13:58:45.088964 [Byte1]: 60
3426 13:58:45.093855
3427 13:58:45.093938 Set Vref, RX VrefLevel [Byte0]: 61
3428 13:58:45.096937 [Byte1]: 61
3429 13:58:45.101794
3430 13:58:45.101866 Set Vref, RX VrefLevel [Byte0]: 62
3431 13:58:45.104985 [Byte1]: 62
3432 13:58:45.109246
3433 13:58:45.109315 Set Vref, RX VrefLevel [Byte0]: 63
3434 13:58:45.112679 [Byte1]: 63
3435 13:58:45.117539
3436 13:58:45.117618 Set Vref, RX VrefLevel [Byte0]: 64
3437 13:58:45.121120 [Byte1]: 64
3438 13:58:45.125054
3439 13:58:45.125128 Set Vref, RX VrefLevel [Byte0]: 65
3440 13:58:45.128566 [Byte1]: 65
3441 13:58:45.133118
3442 13:58:45.133190 Set Vref, RX VrefLevel [Byte0]: 66
3443 13:58:45.136413 [Byte1]: 66
3444 13:58:45.141177
3445 13:58:45.141251 Set Vref, RX VrefLevel [Byte0]: 67
3446 13:58:45.144190 [Byte1]: 67
3447 13:58:45.149218
3448 13:58:45.149292 Final RX Vref Byte 0 = 48 to rank0
3449 13:58:45.152807 Final RX Vref Byte 1 = 53 to rank0
3450 13:58:45.155924 Final RX Vref Byte 0 = 48 to rank1
3451 13:58:45.158960 Final RX Vref Byte 1 = 53 to rank1==
3452 13:58:45.162392 Dram Type= 6, Freq= 0, CH_1, rank 0
3453 13:58:45.168710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 13:58:45.168784 ==
3455 13:58:45.168849 DQS Delay:
3456 13:58:45.168946 DQS0 = 0, DQS1 = 0
3457 13:58:45.172181 DQM Delay:
3458 13:58:45.172273 DQM0 = 117, DQM1 = 111
3459 13:58:45.175512 DQ Delay:
3460 13:58:45.179191 DQ0 =122, DQ1 =112, DQ2 =108, DQ3 =112
3461 13:58:45.182296 DQ4 =116, DQ5 =128, DQ6 =126, DQ7 =114
3462 13:58:45.185510 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =102
3463 13:58:45.188621 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3464 13:58:45.188701
3465 13:58:45.188764
3466 13:58:45.198974 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 406 ps
3467 13:58:45.199067 CH1 RK0: MR19=403, MR18=8FC
3468 13:58:45.205355 CH1_RK0: MR19=0x403, MR18=0x8FC, DQSOSC=406, MR23=63, INC=39, DEC=26
3469 13:58:45.205455
3470 13:58:45.208746 ----->DramcWriteLeveling(PI) begin...
3471 13:58:45.208847 ==
3472 13:58:45.211783 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 13:58:45.218696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 13:58:45.218815 ==
3475 13:58:45.221994 Write leveling (Byte 0): 24 => 24
3476 13:58:45.222109 Write leveling (Byte 1): 30 => 30
3477 13:58:45.225024 DramcWriteLeveling(PI) end<-----
3478 13:58:45.225156
3479 13:58:45.228231 ==
3480 13:58:45.231680 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 13:58:45.234861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 13:58:45.235029 ==
3483 13:58:45.238087 [Gating] SW mode calibration
3484 13:58:45.244721 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3485 13:58:45.248059 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3486 13:58:45.254540 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3487 13:58:45.258009 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 13:58:45.261317 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 13:58:45.268380 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 13:58:45.271211 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 13:58:45.274544 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 13:58:45.281361 0 15 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
3493 13:58:45.284399 0 15 28 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
3494 13:58:45.287900 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 13:58:45.294249 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 13:58:45.297845 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 13:58:45.300811 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 13:58:45.307869 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 13:58:45.310886 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 13:58:45.313885 1 0 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
3501 13:58:45.320795 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3502 13:58:45.323993 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 13:58:45.327678 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 13:58:45.333910 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 13:58:45.337152 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 13:58:45.340614 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 13:58:45.347215 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 13:58:45.350703 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3509 13:58:45.353730 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3510 13:58:45.360648 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 13:58:45.363596 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 13:58:45.367320 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 13:58:45.373588 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 13:58:45.377104 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 13:58:45.380343 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 13:58:45.386761 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 13:58:45.390053 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 13:58:45.393175 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 13:58:45.399956 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 13:58:45.403794 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 13:58:45.406727 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 13:58:45.413381 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 13:58:45.416693 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 13:58:45.419757 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3525 13:58:45.426436 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 13:58:45.427013 Total UI for P1: 0, mck2ui 16
3527 13:58:45.433498 best dqsien dly found for B0: ( 1, 3, 24)
3528 13:58:45.433921 Total UI for P1: 0, mck2ui 16
3529 13:58:45.439445 best dqsien dly found for B1: ( 1, 3, 24)
3530 13:58:45.442904 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3531 13:58:45.446233 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3532 13:58:45.446710
3533 13:58:45.449774 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3534 13:58:45.452639 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3535 13:58:45.456230 [Gating] SW calibration Done
3536 13:58:45.456648 ==
3537 13:58:45.459852 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 13:58:45.462867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 13:58:45.463294 ==
3540 13:58:45.465942 RX Vref Scan: 0
3541 13:58:45.466360
3542 13:58:45.466739 RX Vref 0 -> 0, step: 1
3543 13:58:45.469427
3544 13:58:45.469954 RX Delay -40 -> 252, step: 8
3545 13:58:45.475813 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3546 13:58:45.479146 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3547 13:58:45.482920 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3548 13:58:45.485952 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3549 13:58:45.489311 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3550 13:58:45.495727 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3551 13:58:45.499258 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3552 13:58:45.502374 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3553 13:58:45.505752 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3554 13:58:45.509004 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3555 13:58:45.515698 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3556 13:58:45.519745 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3557 13:58:45.522124 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3558 13:58:45.525571 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3559 13:58:45.528867 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3560 13:58:45.535606 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3561 13:58:45.536017 ==
3562 13:58:45.538710 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 13:58:45.542672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 13:58:45.543085 ==
3565 13:58:45.543411 DQS Delay:
3566 13:58:45.545669 DQS0 = 0, DQS1 = 0
3567 13:58:45.546096 DQM Delay:
3568 13:58:45.548765 DQM0 = 117, DQM1 = 110
3569 13:58:45.549185 DQ Delay:
3570 13:58:45.551850 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3571 13:58:45.555111 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3572 13:58:45.558410 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3573 13:58:45.561617 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3574 13:58:45.562039
3575 13:58:45.565158
3576 13:58:45.565575 ==
3577 13:58:45.568722 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 13:58:45.572305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 13:58:45.572731 ==
3580 13:58:45.573064
3581 13:58:45.573372
3582 13:58:45.575476 TX Vref Scan disable
3583 13:58:45.575895 == TX Byte 0 ==
3584 13:58:45.581331 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3585 13:58:45.584870 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3586 13:58:45.585289 == TX Byte 1 ==
3587 13:58:45.591941 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3588 13:58:45.594905 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3589 13:58:45.595329 ==
3590 13:58:45.597953 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 13:58:45.601242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 13:58:45.601666 ==
3593 13:58:45.614409 TX Vref=22, minBit 0, minWin=25, winSum=424
3594 13:58:45.617546 TX Vref=24, minBit 9, minWin=25, winSum=428
3595 13:58:45.620508 TX Vref=26, minBit 3, minWin=26, winSum=431
3596 13:58:45.623768 TX Vref=28, minBit 1, minWin=27, winSum=437
3597 13:58:45.627790 TX Vref=30, minBit 9, minWin=26, winSum=434
3598 13:58:45.635420 TX Vref=32, minBit 1, minWin=26, winSum=428
3599 13:58:45.637543 [TxChooseVref] Worse bit 1, Min win 27, Win sum 437, Final Vref 28
3600 13:58:45.638051
3601 13:58:45.640256 Final TX Range 1 Vref 28
3602 13:58:45.640745
3603 13:58:45.641192 ==
3604 13:58:45.643797 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 13:58:45.647189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 13:58:45.650719 ==
3607 13:58:45.651136
3608 13:58:45.651462
3609 13:58:45.651764 TX Vref Scan disable
3610 13:58:45.654050 == TX Byte 0 ==
3611 13:58:45.657307 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3612 13:58:45.663675 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3613 13:58:45.664098 == TX Byte 1 ==
3614 13:58:45.667221 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3615 13:58:45.673878 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3616 13:58:45.674350
3617 13:58:45.674736 [DATLAT]
3618 13:58:45.675061 Freq=1200, CH1 RK1
3619 13:58:45.675409
3620 13:58:45.676677 DATLAT Default: 0xd
3621 13:58:45.680034 0, 0xFFFF, sum = 0
3622 13:58:45.680463 1, 0xFFFF, sum = 0
3623 13:58:45.683583 2, 0xFFFF, sum = 0
3624 13:58:45.684087 3, 0xFFFF, sum = 0
3625 13:58:45.686926 4, 0xFFFF, sum = 0
3626 13:58:45.687426 5, 0xFFFF, sum = 0
3627 13:58:45.690717 6, 0xFFFF, sum = 0
3628 13:58:45.691141 7, 0xFFFF, sum = 0
3629 13:58:45.693542 8, 0xFFFF, sum = 0
3630 13:58:45.693959 9, 0xFFFF, sum = 0
3631 13:58:45.696877 10, 0xFFFF, sum = 0
3632 13:58:45.697298 11, 0xFFFF, sum = 0
3633 13:58:45.700190 12, 0x0, sum = 1
3634 13:58:45.700664 13, 0x0, sum = 2
3635 13:58:45.703314 14, 0x0, sum = 3
3636 13:58:45.703768 15, 0x0, sum = 4
3637 13:58:45.706810 best_step = 13
3638 13:58:45.707222
3639 13:58:45.707550 ==
3640 13:58:45.710192 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 13:58:45.713231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 13:58:45.713778 ==
3643 13:58:45.716570 RX Vref Scan: 0
3644 13:58:45.717082
3645 13:58:45.717545 RX Vref 0 -> 0, step: 1
3646 13:58:45.717990
3647 13:58:45.720451 RX Delay -21 -> 252, step: 4
3648 13:58:45.726669 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3649 13:58:45.730675 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3650 13:58:45.733477 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3651 13:58:45.736857 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3652 13:58:45.740064 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3653 13:58:45.746322 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3654 13:58:45.750130 iDelay=199, Bit 6, Center 132 (67 ~ 198) 132
3655 13:58:45.753350 iDelay=199, Bit 7, Center 114 (51 ~ 178) 128
3656 13:58:45.756508 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3657 13:58:45.760136 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3658 13:58:45.766025 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3659 13:58:45.769489 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3660 13:58:45.773022 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3661 13:58:45.775984 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3662 13:58:45.779861 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3663 13:58:45.786139 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3664 13:58:45.786552 ==
3665 13:58:45.789253 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 13:58:45.792698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 13:58:45.793127 ==
3668 13:58:45.793453 DQS Delay:
3669 13:58:45.796539 DQS0 = 0, DQS1 = 0
3670 13:58:45.796950 DQM Delay:
3671 13:58:45.799061 DQM0 = 117, DQM1 = 110
3672 13:58:45.799519 DQ Delay:
3673 13:58:45.803036 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3674 13:58:45.805664 DQ4 =116, DQ5 =126, DQ6 =132, DQ7 =114
3675 13:58:45.809307 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100
3676 13:58:45.815627 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3677 13:58:45.816043
3678 13:58:45.816366
3679 13:58:45.822050 [DQSOSCAuto] RK1, (LSB)MR18= 0xfaf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 412 ps
3680 13:58:45.825420 CH1 RK1: MR19=303, MR18=FAF4
3681 13:58:45.832137 CH1_RK1: MR19=0x303, MR18=0xFAF4, DQSOSC=412, MR23=63, INC=38, DEC=25
3682 13:58:45.835453 [RxdqsGatingPostProcess] freq 1200
3683 13:58:45.838704 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3684 13:58:45.842131 best DQS0 dly(2T, 0.5T) = (0, 11)
3685 13:58:45.845639 best DQS1 dly(2T, 0.5T) = (0, 11)
3686 13:58:45.848712 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3687 13:58:45.852239 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3688 13:58:45.855168 best DQS0 dly(2T, 0.5T) = (0, 11)
3689 13:58:45.858507 best DQS1 dly(2T, 0.5T) = (0, 11)
3690 13:58:45.861626 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3691 13:58:45.865814 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3692 13:58:45.868404 Pre-setting of DQS Precalculation
3693 13:58:45.871587 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3694 13:58:45.882053 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3695 13:58:45.888242 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3696 13:58:45.888656
3697 13:58:45.888982
3698 13:58:45.891392 [Calibration Summary] 2400 Mbps
3699 13:58:45.891805 CH 0, Rank 0
3700 13:58:45.894708 SW Impedance : PASS
3701 13:58:45.895123 DUTY Scan : NO K
3702 13:58:45.898776 ZQ Calibration : PASS
3703 13:58:45.902102 Jitter Meter : NO K
3704 13:58:45.902513 CBT Training : PASS
3705 13:58:45.904526 Write leveling : PASS
3706 13:58:45.908295 RX DQS gating : PASS
3707 13:58:45.908714 RX DQ/DQS(RDDQC) : PASS
3708 13:58:45.911435 TX DQ/DQS : PASS
3709 13:58:45.914494 RX DATLAT : PASS
3710 13:58:45.914972 RX DQ/DQS(Engine): PASS
3711 13:58:45.918354 TX OE : NO K
3712 13:58:45.918991 All Pass.
3713 13:58:45.919468
3714 13:58:45.921017 CH 0, Rank 1
3715 13:58:45.921421 SW Impedance : PASS
3716 13:58:45.924601 DUTY Scan : NO K
3717 13:58:45.927615 ZQ Calibration : PASS
3718 13:58:45.928066 Jitter Meter : NO K
3719 13:58:45.930914 CBT Training : PASS
3720 13:58:45.934557 Write leveling : PASS
3721 13:58:45.935011 RX DQS gating : PASS
3722 13:58:45.938156 RX DQ/DQS(RDDQC) : PASS
3723 13:58:45.941195 TX DQ/DQS : PASS
3724 13:58:45.941607 RX DATLAT : PASS
3725 13:58:45.944204 RX DQ/DQS(Engine): PASS
3726 13:58:45.947737 TX OE : NO K
3727 13:58:45.948186 All Pass.
3728 13:58:45.948740
3729 13:58:45.949195 CH 1, Rank 0
3730 13:58:45.950769 SW Impedance : PASS
3731 13:58:45.954066 DUTY Scan : NO K
3732 13:58:45.954479 ZQ Calibration : PASS
3733 13:58:45.957332 Jitter Meter : NO K
3734 13:58:45.960648 CBT Training : PASS
3735 13:58:45.961062 Write leveling : PASS
3736 13:58:45.964165 RX DQS gating : PASS
3737 13:58:45.964581 RX DQ/DQS(RDDQC) : PASS
3738 13:58:45.967097 TX DQ/DQS : PASS
3739 13:58:45.970643 RX DATLAT : PASS
3740 13:58:45.971062 RX DQ/DQS(Engine): PASS
3741 13:58:45.973976 TX OE : NO K
3742 13:58:45.974391 All Pass.
3743 13:58:45.974775
3744 13:58:45.977051 CH 1, Rank 1
3745 13:58:45.977463 SW Impedance : PASS
3746 13:58:45.980633 DUTY Scan : NO K
3747 13:58:45.983663 ZQ Calibration : PASS
3748 13:58:45.984090 Jitter Meter : NO K
3749 13:58:45.987081 CBT Training : PASS
3750 13:58:45.990538 Write leveling : PASS
3751 13:58:45.990986 RX DQS gating : PASS
3752 13:58:45.993789 RX DQ/DQS(RDDQC) : PASS
3753 13:58:45.996988 TX DQ/DQS : PASS
3754 13:58:45.997404 RX DATLAT : PASS
3755 13:58:46.000449 RX DQ/DQS(Engine): PASS
3756 13:58:46.003956 TX OE : NO K
3757 13:58:46.004371 All Pass.
3758 13:58:46.004697
3759 13:58:46.005004 DramC Write-DBI off
3760 13:58:46.007137 PER_BANK_REFRESH: Hybrid Mode
3761 13:58:46.010097 TX_TRACKING: ON
3762 13:58:46.017219 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3763 13:58:46.024535 [FAST_K] Save calibration result to emmc
3764 13:58:46.027263 dramc_set_vcore_voltage set vcore to 650000
3765 13:58:46.027679 Read voltage for 600, 5
3766 13:58:46.030209 Vio18 = 0
3767 13:58:46.030665 Vcore = 650000
3768 13:58:46.031006 Vdram = 0
3769 13:58:46.034149 Vddq = 0
3770 13:58:46.034564 Vmddr = 0
3771 13:58:46.036752 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3772 13:58:46.043118 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3773 13:58:46.046862 MEM_TYPE=3, freq_sel=19
3774 13:58:46.049800 sv_algorithm_assistance_LP4_1600
3775 13:58:46.053742 ============ PULL DRAM RESETB DOWN ============
3776 13:58:46.056501 ========== PULL DRAM RESETB DOWN end =========
3777 13:58:46.062884 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3778 13:58:46.066539 ===================================
3779 13:58:46.066998 LPDDR4 DRAM CONFIGURATION
3780 13:58:46.069713 ===================================
3781 13:58:46.072745 EX_ROW_EN[0] = 0x0
3782 13:58:46.073161 EX_ROW_EN[1] = 0x0
3783 13:58:46.076579 LP4Y_EN = 0x0
3784 13:58:46.079418 WORK_FSP = 0x0
3785 13:58:46.079829 WL = 0x2
3786 13:58:46.082505 RL = 0x2
3787 13:58:46.082967 BL = 0x2
3788 13:58:46.085885 RPST = 0x0
3789 13:58:46.086310 RD_PRE = 0x0
3790 13:58:46.089627 WR_PRE = 0x1
3791 13:58:46.090039 WR_PST = 0x0
3792 13:58:46.092517 DBI_WR = 0x0
3793 13:58:46.092929 DBI_RD = 0x0
3794 13:58:46.095906 OTF = 0x1
3795 13:58:46.099737 ===================================
3796 13:58:46.102432 ===================================
3797 13:58:46.102882 ANA top config
3798 13:58:46.105706 ===================================
3799 13:58:46.109021 DLL_ASYNC_EN = 0
3800 13:58:46.112601 ALL_SLAVE_EN = 1
3801 13:58:46.115511 NEW_RANK_MODE = 1
3802 13:58:46.115972 DLL_IDLE_MODE = 1
3803 13:58:46.118772 LP45_APHY_COMB_EN = 1
3804 13:58:46.122256 TX_ODT_DIS = 1
3805 13:58:46.125648 NEW_8X_MODE = 1
3806 13:58:46.129002 ===================================
3807 13:58:46.132047 ===================================
3808 13:58:46.135893 data_rate = 1200
3809 13:58:46.136491 CKR = 1
3810 13:58:46.139226 DQ_P2S_RATIO = 8
3811 13:58:46.142403 ===================================
3812 13:58:46.146449 CA_P2S_RATIO = 8
3813 13:58:46.148622 DQ_CA_OPEN = 0
3814 13:58:46.151790 DQ_SEMI_OPEN = 0
3815 13:58:46.155539 CA_SEMI_OPEN = 0
3816 13:58:46.155989 CA_FULL_RATE = 0
3817 13:58:46.158672 DQ_CKDIV4_EN = 1
3818 13:58:46.161969 CA_CKDIV4_EN = 1
3819 13:58:46.165183 CA_PREDIV_EN = 0
3820 13:58:46.168478 PH8_DLY = 0
3821 13:58:46.172061 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3822 13:58:46.172507 DQ_AAMCK_DIV = 4
3823 13:58:46.174710 CA_AAMCK_DIV = 4
3824 13:58:46.178384 CA_ADMCK_DIV = 4
3825 13:58:46.181579 DQ_TRACK_CA_EN = 0
3826 13:58:46.184936 CA_PICK = 600
3827 13:58:46.188307 CA_MCKIO = 600
3828 13:58:46.191737 MCKIO_SEMI = 0
3829 13:58:46.192158 PLL_FREQ = 2288
3830 13:58:46.194762 DQ_UI_PI_RATIO = 32
3831 13:58:46.198300 CA_UI_PI_RATIO = 0
3832 13:58:46.201468 ===================================
3833 13:58:46.204670 ===================================
3834 13:58:46.208419 memory_type:LPDDR4
3835 13:58:46.211903 GP_NUM : 10
3836 13:58:46.212431 SRAM_EN : 1
3837 13:58:46.214743 MD32_EN : 0
3838 13:58:46.217882 ===================================
3839 13:58:46.218323 [ANA_INIT] >>>>>>>>>>>>>>
3840 13:58:46.221209 <<<<<< [CONFIGURE PHASE]: ANA_TX
3841 13:58:46.224489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3842 13:58:46.227739 ===================================
3843 13:58:46.231226 data_rate = 1200,PCW = 0X5800
3844 13:58:46.234651 ===================================
3845 13:58:46.237581 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3846 13:58:46.244106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3847 13:58:46.251913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3848 13:58:46.254367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3849 13:58:46.257538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3850 13:58:46.260775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3851 13:58:46.264047 [ANA_INIT] flow start
3852 13:58:46.264460 [ANA_INIT] PLL >>>>>>>>
3853 13:58:46.267664 [ANA_INIT] PLL <<<<<<<<
3854 13:58:46.270999 [ANA_INIT] MIDPI >>>>>>>>
3855 13:58:46.271463 [ANA_INIT] MIDPI <<<<<<<<
3856 13:58:46.273944 [ANA_INIT] DLL >>>>>>>>
3857 13:58:46.277734 [ANA_INIT] flow end
3858 13:58:46.281263 ============ LP4 DIFF to SE enter ============
3859 13:58:46.284008 ============ LP4 DIFF to SE exit ============
3860 13:58:46.287163 [ANA_INIT] <<<<<<<<<<<<<
3861 13:58:46.290290 [Flow] Enable top DCM control >>>>>
3862 13:58:46.293865 [Flow] Enable top DCM control <<<<<
3863 13:58:46.297116 Enable DLL master slave shuffle
3864 13:58:46.300408 ==============================================================
3865 13:58:46.303583 Gating Mode config
3866 13:58:46.310219 ==============================================================
3867 13:58:46.310671 Config description:
3868 13:58:46.320183 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3869 13:58:46.326932 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3870 13:58:46.333669 SELPH_MODE 0: By rank 1: By Phase
3871 13:58:46.336886 ==============================================================
3872 13:58:46.340127 GAT_TRACK_EN = 1
3873 13:58:46.343071 RX_GATING_MODE = 2
3874 13:58:46.346838 RX_GATING_TRACK_MODE = 2
3875 13:58:46.350501 SELPH_MODE = 1
3876 13:58:46.353942 PICG_EARLY_EN = 1
3877 13:58:46.357141 VALID_LAT_VALUE = 1
3878 13:58:46.362977 ==============================================================
3879 13:58:46.366863 Enter into Gating configuration >>>>
3880 13:58:46.369677 Exit from Gating configuration <<<<
3881 13:58:46.370094 Enter into DVFS_PRE_config >>>>>
3882 13:58:46.382843 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3883 13:58:46.386260 Exit from DVFS_PRE_config <<<<<
3884 13:58:46.389280 Enter into PICG configuration >>>>
3885 13:58:46.392778 Exit from PICG configuration <<<<
3886 13:58:46.396116 [RX_INPUT] configuration >>>>>
3887 13:58:46.396557 [RX_INPUT] configuration <<<<<
3888 13:58:46.402376 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3889 13:58:46.409419 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3890 13:58:46.412304 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3891 13:58:46.419011 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3892 13:58:46.425723 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3893 13:58:46.432479 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3894 13:58:46.435254 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3895 13:58:46.439064 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3896 13:58:46.445257 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3897 13:58:46.448362 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3898 13:58:46.452734 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3899 13:58:46.458661 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3900 13:58:46.461902 ===================================
3901 13:58:46.462317 LPDDR4 DRAM CONFIGURATION
3902 13:58:46.464854 ===================================
3903 13:58:46.468280 EX_ROW_EN[0] = 0x0
3904 13:58:46.471483 EX_ROW_EN[1] = 0x0
3905 13:58:46.471897 LP4Y_EN = 0x0
3906 13:58:46.475059 WORK_FSP = 0x0
3907 13:58:46.475480 WL = 0x2
3908 13:58:46.477938 RL = 0x2
3909 13:58:46.478372 BL = 0x2
3910 13:58:46.481957 RPST = 0x0
3911 13:58:46.482397 RD_PRE = 0x0
3912 13:58:46.484890 WR_PRE = 0x1
3913 13:58:46.485457 WR_PST = 0x0
3914 13:58:46.488368 DBI_WR = 0x0
3915 13:58:46.488779 DBI_RD = 0x0
3916 13:58:46.491357 OTF = 0x1
3917 13:58:46.494768 ===================================
3918 13:58:46.498679 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3919 13:58:46.501468 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3920 13:58:46.507953 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 13:58:46.511793 ===================================
3922 13:58:46.512206 LPDDR4 DRAM CONFIGURATION
3923 13:58:46.514485 ===================================
3924 13:58:46.517575 EX_ROW_EN[0] = 0x10
3925 13:58:46.521462 EX_ROW_EN[1] = 0x0
3926 13:58:46.521924 LP4Y_EN = 0x0
3927 13:58:46.524408 WORK_FSP = 0x0
3928 13:58:46.524810 WL = 0x2
3929 13:58:46.528371 RL = 0x2
3930 13:58:46.528894 BL = 0x2
3931 13:58:46.531037 RPST = 0x0
3932 13:58:46.531448 RD_PRE = 0x0
3933 13:58:46.534078 WR_PRE = 0x1
3934 13:58:46.534523 WR_PST = 0x0
3935 13:58:46.537751 DBI_WR = 0x0
3936 13:58:46.538188 DBI_RD = 0x0
3937 13:58:46.540747 OTF = 0x1
3938 13:58:46.544163 ===================================
3939 13:58:46.550847 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3940 13:58:46.554350 nWR fixed to 30
3941 13:58:46.557857 [ModeRegInit_LP4] CH0 RK0
3942 13:58:46.558301 [ModeRegInit_LP4] CH0 RK1
3943 13:58:46.561107 [ModeRegInit_LP4] CH1 RK0
3944 13:58:46.564013 [ModeRegInit_LP4] CH1 RK1
3945 13:58:46.564602 match AC timing 17
3946 13:58:46.571037 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3947 13:58:46.574438 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3948 13:58:46.577751 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3949 13:58:46.584239 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3950 13:58:46.587085 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3951 13:58:46.587553 ==
3952 13:58:46.590753 Dram Type= 6, Freq= 0, CH_0, rank 0
3953 13:58:46.593775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 13:58:46.594220 ==
3955 13:58:46.600779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3956 13:58:46.607083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3957 13:58:46.610931 [CA 0] Center 36 (6~66) winsize 61
3958 13:58:46.613620 [CA 1] Center 36 (6~66) winsize 61
3959 13:58:46.617228 [CA 2] Center 34 (4~65) winsize 62
3960 13:58:46.620014 [CA 3] Center 34 (4~65) winsize 62
3961 13:58:46.623522 [CA 4] Center 33 (3~64) winsize 62
3962 13:58:46.626701 [CA 5] Center 33 (3~64) winsize 62
3963 13:58:46.627116
3964 13:58:46.630412 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3965 13:58:46.630875
3966 13:58:46.633272 [CATrainingPosCal] consider 1 rank data
3967 13:58:46.636701 u2DelayCellTimex100 = 270/100 ps
3968 13:58:46.640669 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3969 13:58:46.643182 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3970 13:58:46.646497 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 13:58:46.649824 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3972 13:58:46.656086 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 13:58:46.659645 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 13:58:46.660097
3975 13:58:46.663202 CA PerBit enable=1, Macro0, CA PI delay=33
3976 13:58:46.663614
3977 13:58:46.666451 [CBTSetCACLKResult] CA Dly = 33
3978 13:58:46.666916 CS Dly: 5 (0~36)
3979 13:58:46.667251 ==
3980 13:58:46.669552 Dram Type= 6, Freq= 0, CH_0, rank 1
3981 13:58:46.676328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 13:58:46.676899 ==
3983 13:58:46.679977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3984 13:58:46.686156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3985 13:58:46.689210 [CA 0] Center 36 (6~66) winsize 61
3986 13:58:46.692910 [CA 1] Center 36 (6~66) winsize 61
3987 13:58:46.696238 [CA 2] Center 34 (4~65) winsize 62
3988 13:58:46.699488 [CA 3] Center 34 (4~65) winsize 62
3989 13:58:46.702748 [CA 4] Center 33 (3~64) winsize 62
3990 13:58:46.705981 [CA 5] Center 33 (3~64) winsize 62
3991 13:58:46.706395
3992 13:58:46.709503 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3993 13:58:46.709914
3994 13:58:46.712660 [CATrainingPosCal] consider 2 rank data
3995 13:58:46.715911 u2DelayCellTimex100 = 270/100 ps
3996 13:58:46.719291 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3997 13:58:46.722405 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3998 13:58:46.729622 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3999 13:58:46.732935 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4000 13:58:46.736007 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 13:58:46.739009 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4002 13:58:46.739397
4003 13:58:46.743054 CA PerBit enable=1, Macro0, CA PI delay=33
4004 13:58:46.743617
4005 13:58:46.745497 [CBTSetCACLKResult] CA Dly = 33
4006 13:58:46.745908 CS Dly: 5 (0~37)
4007 13:58:46.746241
4008 13:58:46.749897 ----->DramcWriteLeveling(PI) begin...
4009 13:58:46.752438 ==
4010 13:58:46.755674 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 13:58:46.758830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 13:58:46.759245 ==
4013 13:58:46.762183 Write leveling (Byte 0): 31 => 31
4014 13:58:46.765715 Write leveling (Byte 1): 31 => 31
4015 13:58:46.768899 DramcWriteLeveling(PI) end<-----
4016 13:58:46.769313
4017 13:58:46.769638 ==
4018 13:58:46.772376 Dram Type= 6, Freq= 0, CH_0, rank 0
4019 13:58:46.775922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 13:58:46.776338 ==
4021 13:58:46.778572 [Gating] SW mode calibration
4022 13:58:46.785977 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4023 13:58:46.791864 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4024 13:58:46.795996 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 13:58:46.798457 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 13:58:46.805055 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 13:58:46.808682 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 13:58:46.811531 0 9 16 | B1->B0 | 3030 2828 | 0 0 | (1 1) (0 0)
4029 13:58:46.818216 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 13:58:46.822170 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 13:58:46.824898 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 13:58:46.831481 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 13:58:46.835052 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 13:58:46.837908 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 13:58:46.845230 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4036 13:58:46.848549 0 10 16 | B1->B0 | 3535 4242 | 1 0 | (0 0) (0 0)
4037 13:58:46.851630 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 13:58:46.858450 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 13:58:46.861666 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 13:58:46.864526 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 13:58:46.871285 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 13:58:46.874567 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 13:58:46.877832 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4044 13:58:46.881135 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4045 13:58:46.888105 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 13:58:46.891253 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 13:58:46.894546 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 13:58:46.900901 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 13:58:46.904651 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 13:58:46.907761 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 13:58:46.914319 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 13:58:46.917686 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 13:58:46.921826 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 13:58:46.927712 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 13:58:46.930811 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 13:58:46.934411 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 13:58:46.941113 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 13:58:46.944253 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 13:58:46.947483 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4060 13:58:46.954291 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4061 13:58:46.957353 Total UI for P1: 0, mck2ui 16
4062 13:58:46.960355 best dqsien dly found for B0: ( 0, 13, 12)
4063 13:58:46.964349 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 13:58:46.967308 Total UI for P1: 0, mck2ui 16
4065 13:58:46.970519 best dqsien dly found for B1: ( 0, 13, 16)
4066 13:58:46.973556 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4067 13:58:46.976898 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4068 13:58:46.977314
4069 13:58:46.980863 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4070 13:58:46.987018 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4071 13:58:46.987579 [Gating] SW calibration Done
4072 13:58:46.988086 ==
4073 13:58:46.990286 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 13:58:46.997321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 13:58:46.997839 ==
4076 13:58:46.998212 RX Vref Scan: 0
4077 13:58:46.998569
4078 13:58:47.000340 RX Vref 0 -> 0, step: 1
4079 13:58:47.000795
4080 13:58:47.005999 RX Delay -230 -> 252, step: 16
4081 13:58:47.006919 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4082 13:58:47.010327 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4083 13:58:47.016530 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4084 13:58:47.019975 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4085 13:58:47.023443 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4086 13:58:47.026690 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4087 13:58:47.029868 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4088 13:58:47.036653 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4089 13:58:47.040012 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4090 13:58:47.043230 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4091 13:58:47.046425 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4092 13:58:47.053951 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4093 13:58:47.056785 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4094 13:58:47.059489 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4095 13:58:47.062798 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4096 13:58:47.069889 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4097 13:58:47.070345 ==
4098 13:58:47.073285 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 13:58:47.076326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 13:58:47.076946 ==
4101 13:58:47.077517 DQS Delay:
4102 13:58:47.079567 DQS0 = 0, DQS1 = 0
4103 13:58:47.080100 DQM Delay:
4104 13:58:47.083248 DQM0 = 45, DQM1 = 34
4105 13:58:47.083827 DQ Delay:
4106 13:58:47.086482 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4107 13:58:47.089414 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =49
4108 13:58:47.092975 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4109 13:58:47.095945 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4110 13:58:47.096542
4111 13:58:47.097098
4112 13:58:47.097616 ==
4113 13:58:47.099212 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 13:58:47.102318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 13:58:47.105703 ==
4116 13:58:47.106051
4117 13:58:47.106334
4118 13:58:47.106762 TX Vref Scan disable
4119 13:58:47.108979 == TX Byte 0 ==
4120 13:58:47.112888 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4121 13:58:47.115262 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4122 13:58:47.118627 == TX Byte 1 ==
4123 13:58:47.122069 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4124 13:58:47.125312 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4125 13:58:47.128627 ==
4126 13:58:47.132253 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 13:58:47.134983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 13:58:47.135074 ==
4129 13:58:47.135156
4130 13:58:47.135231
4131 13:58:47.138578 TX Vref Scan disable
4132 13:58:47.138688 == TX Byte 0 ==
4133 13:58:47.145093 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4134 13:58:47.148169 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4135 13:58:47.151906 == TX Byte 1 ==
4136 13:58:47.154792 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4137 13:58:47.158103 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4138 13:58:47.158176
4139 13:58:47.158238 [DATLAT]
4140 13:58:47.161460 Freq=600, CH0 RK0
4141 13:58:47.161536
4142 13:58:47.161598 DATLAT Default: 0x9
4143 13:58:47.165059 0, 0xFFFF, sum = 0
4144 13:58:47.168099 1, 0xFFFF, sum = 0
4145 13:58:47.168182 2, 0xFFFF, sum = 0
4146 13:58:47.171596 3, 0xFFFF, sum = 0
4147 13:58:47.171706 4, 0xFFFF, sum = 0
4148 13:58:47.174888 5, 0xFFFF, sum = 0
4149 13:58:47.174971 6, 0xFFFF, sum = 0
4150 13:58:47.177821 7, 0xFFFF, sum = 0
4151 13:58:47.177903 8, 0x0, sum = 1
4152 13:58:47.181777 9, 0x0, sum = 2
4153 13:58:47.181859 10, 0x0, sum = 3
4154 13:58:47.181924 11, 0x0, sum = 4
4155 13:58:47.184513 best_step = 9
4156 13:58:47.184593
4157 13:58:47.184656 ==
4158 13:58:47.187698 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 13:58:47.191222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 13:58:47.191302 ==
4161 13:58:47.194666 RX Vref Scan: 1
4162 13:58:47.194746
4163 13:58:47.198031 RX Vref 0 -> 0, step: 1
4164 13:58:47.198110
4165 13:58:47.198173 RX Delay -195 -> 252, step: 8
4166 13:58:47.198234
4167 13:58:47.200928 Set Vref, RX VrefLevel [Byte0]: 63
4168 13:58:47.204147 [Byte1]: 55
4169 13:58:47.209280
4170 13:58:47.209360 Final RX Vref Byte 0 = 63 to rank0
4171 13:58:47.212384 Final RX Vref Byte 1 = 55 to rank0
4172 13:58:47.215533 Final RX Vref Byte 0 = 63 to rank1
4173 13:58:47.219112 Final RX Vref Byte 1 = 55 to rank1==
4174 13:58:47.222649 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 13:58:47.228992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 13:58:47.229072 ==
4177 13:58:47.229136 DQS Delay:
4178 13:58:47.229195 DQS0 = 0, DQS1 = 0
4179 13:58:47.232110 DQM Delay:
4180 13:58:47.232191 DQM0 = 42, DQM1 = 34
4181 13:58:47.235372 DQ Delay:
4182 13:58:47.238529 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4183 13:58:47.242197 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4184 13:58:47.245218 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4185 13:58:47.248478 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4186 13:58:47.248559
4187 13:58:47.248622
4188 13:58:47.255316 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4189 13:58:47.258902 CH0 RK0: MR19=808, MR18=6C43
4190 13:58:47.265303 CH0_RK0: MR19=0x808, MR18=0x6C43, DQSOSC=389, MR23=63, INC=173, DEC=115
4191 13:58:47.265383
4192 13:58:47.268787 ----->DramcWriteLeveling(PI) begin...
4193 13:58:47.268869 ==
4194 13:58:47.271780 Dram Type= 6, Freq= 0, CH_0, rank 1
4195 13:58:47.275108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 13:58:47.275189 ==
4197 13:58:47.278442 Write leveling (Byte 0): 36 => 36
4198 13:58:47.281617 Write leveling (Byte 1): 30 => 30
4199 13:58:47.285097 DramcWriteLeveling(PI) end<-----
4200 13:58:47.285177
4201 13:58:47.285240 ==
4202 13:58:47.288305 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 13:58:47.291347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 13:58:47.294812 ==
4205 13:58:47.294893 [Gating] SW mode calibration
4206 13:58:47.301543 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4207 13:58:47.307927 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4208 13:58:47.311578 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 13:58:47.317992 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 13:58:47.321226 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 13:58:47.324541 0 9 12 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
4212 13:58:47.331583 0 9 16 | B1->B0 | 3131 2c2c | 0 0 | (1 1) (1 1)
4213 13:58:47.334955 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 13:58:47.338160 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 13:58:47.344659 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 13:58:47.347752 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 13:58:47.350971 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 13:58:47.357974 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 13:58:47.360879 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 13:58:47.364243 0 10 16 | B1->B0 | 3737 3b3b | 0 0 | (1 1) (0 0)
4221 13:58:47.370924 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 13:58:47.374361 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 13:58:47.377518 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 13:58:47.384152 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 13:58:47.387411 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 13:58:47.390781 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 13:58:47.397153 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 13:58:47.400725 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4229 13:58:47.404755 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 13:58:47.410370 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 13:58:47.414045 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 13:58:47.417227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 13:58:47.423730 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 13:58:47.427456 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 13:58:47.430399 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 13:58:47.436750 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 13:58:47.440118 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 13:58:47.443194 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 13:58:47.449804 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 13:58:47.453358 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 13:58:47.457285 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 13:58:47.463116 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 13:58:47.466555 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 13:58:47.469632 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 13:58:47.473115 Total UI for P1: 0, mck2ui 16
4246 13:58:47.476561 best dqsien dly found for B0: ( 0, 13, 14)
4247 13:58:47.479863 Total UI for P1: 0, mck2ui 16
4248 13:58:47.483140 best dqsien dly found for B1: ( 0, 13, 14)
4249 13:58:47.486742 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4250 13:58:47.489575 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4251 13:58:47.489654
4252 13:58:47.496180 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4253 13:58:47.499622 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4254 13:58:47.499700 [Gating] SW calibration Done
4255 13:58:47.502944 ==
4256 13:58:47.506579 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 13:58:47.509366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 13:58:47.509435 ==
4259 13:58:47.509500 RX Vref Scan: 0
4260 13:58:47.509558
4261 13:58:47.512937 RX Vref 0 -> 0, step: 1
4262 13:58:47.513003
4263 13:58:47.515814 RX Delay -230 -> 252, step: 16
4264 13:58:47.519126 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4265 13:58:47.522588 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4266 13:58:47.529252 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4267 13:58:47.532451 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4268 13:58:47.536002 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4269 13:58:47.539174 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4270 13:58:47.545642 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4271 13:58:47.549366 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4272 13:58:47.552642 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4273 13:58:47.555521 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4274 13:58:47.562498 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4275 13:58:47.565779 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4276 13:58:47.569064 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4277 13:58:47.572026 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4278 13:58:47.578856 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4279 13:58:47.582035 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4280 13:58:47.582131 ==
4281 13:58:47.585807 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 13:58:47.589070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 13:58:47.589142 ==
4284 13:58:47.589203 DQS Delay:
4285 13:58:47.592274 DQS0 = 0, DQS1 = 0
4286 13:58:47.592343 DQM Delay:
4287 13:58:47.595861 DQM0 = 41, DQM1 = 34
4288 13:58:47.595930 DQ Delay:
4289 13:58:47.598525 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4290 13:58:47.601863 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4291 13:58:47.605243 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4292 13:58:47.608826 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4293 13:58:47.608894
4294 13:58:47.608982
4295 13:58:47.609066 ==
4296 13:58:47.612821 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 13:58:47.615388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 13:58:47.618648 ==
4299 13:58:47.618718
4300 13:58:47.618776
4301 13:58:47.618831 TX Vref Scan disable
4302 13:58:47.621867 == TX Byte 0 ==
4303 13:58:47.625012 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4304 13:58:47.631911 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4305 13:58:47.631984 == TX Byte 1 ==
4306 13:58:47.635702 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4307 13:58:47.641903 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4308 13:58:47.642001 ==
4309 13:58:47.645224 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 13:58:47.649116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 13:58:47.649211 ==
4312 13:58:47.649297
4313 13:58:47.649383
4314 13:58:47.651525 TX Vref Scan disable
4315 13:58:47.655164 == TX Byte 0 ==
4316 13:58:47.658913 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4317 13:58:47.662229 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4318 13:58:47.664828 == TX Byte 1 ==
4319 13:58:47.668094 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4320 13:58:47.671319 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4321 13:58:47.671418
4322 13:58:47.675307 [DATLAT]
4323 13:58:47.675402 Freq=600, CH0 RK1
4324 13:58:47.675492
4325 13:58:47.677858 DATLAT Default: 0x9
4326 13:58:47.677933 0, 0xFFFF, sum = 0
4327 13:58:47.681344 1, 0xFFFF, sum = 0
4328 13:58:47.681443 2, 0xFFFF, sum = 0
4329 13:58:47.684869 3, 0xFFFF, sum = 0
4330 13:58:47.684955 4, 0xFFFF, sum = 0
4331 13:58:47.687811 5, 0xFFFF, sum = 0
4332 13:58:47.687901 6, 0xFFFF, sum = 0
4333 13:58:47.690953 7, 0xFFFF, sum = 0
4334 13:58:47.691022 8, 0x0, sum = 1
4335 13:58:47.694588 9, 0x0, sum = 2
4336 13:58:47.694660 10, 0x0, sum = 3
4337 13:58:47.697608 11, 0x0, sum = 4
4338 13:58:47.697675 best_step = 9
4339 13:58:47.697738
4340 13:58:47.697794 ==
4341 13:58:47.700829 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 13:58:47.704679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 13:58:47.707480 ==
4344 13:58:47.707553 RX Vref Scan: 0
4345 13:58:47.707611
4346 13:58:47.711787 RX Vref 0 -> 0, step: 1
4347 13:58:47.711856
4348 13:58:47.714132 RX Delay -195 -> 252, step: 8
4349 13:58:47.717721 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4350 13:58:47.720797 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4351 13:58:47.727371 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4352 13:58:47.731097 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4353 13:58:47.734023 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4354 13:58:47.737418 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4355 13:58:47.744548 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4356 13:58:47.747370 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4357 13:58:47.750500 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4358 13:58:47.753717 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4359 13:58:47.760383 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4360 13:58:47.764186 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4361 13:58:47.767465 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4362 13:58:47.770256 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4363 13:58:47.776981 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4364 13:58:47.780124 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4365 13:58:47.780200 ==
4366 13:58:47.783517 Dram Type= 6, Freq= 0, CH_0, rank 1
4367 13:58:47.787242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 13:58:47.787337 ==
4369 13:58:47.790451 DQS Delay:
4370 13:58:47.790549 DQS0 = 0, DQS1 = 0
4371 13:58:47.790633 DQM Delay:
4372 13:58:47.793632 DQM0 = 40, DQM1 = 33
4373 13:58:47.793700 DQ Delay:
4374 13:58:47.797013 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =40
4375 13:58:47.800409 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4376 13:58:47.803948 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4377 13:58:47.806720 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4378 13:58:47.806789
4379 13:58:47.806852
4380 13:58:47.816483 [DQSOSCAuto] RK1, (LSB)MR18= 0x691b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4381 13:58:47.816557 CH0 RK1: MR19=808, MR18=691B
4382 13:58:47.822990 CH0_RK1: MR19=0x808, MR18=0x691B, DQSOSC=390, MR23=63, INC=172, DEC=114
4383 13:58:47.826742 [RxdqsGatingPostProcess] freq 600
4384 13:58:47.833326 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4385 13:58:47.837246 Pre-setting of DQS Precalculation
4386 13:58:47.840527 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4387 13:58:47.840603 ==
4388 13:58:47.843768 Dram Type= 6, Freq= 0, CH_1, rank 0
4389 13:58:47.849784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 13:58:47.849883 ==
4391 13:58:47.853001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4392 13:58:47.859298 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4393 13:58:47.863108 [CA 0] Center 35 (5~66) winsize 62
4394 13:58:47.866300 [CA 1] Center 35 (5~66) winsize 62
4395 13:58:47.869408 [CA 2] Center 34 (4~65) winsize 62
4396 13:58:47.872978 [CA 3] Center 33 (3~64) winsize 62
4397 13:58:47.876443 [CA 4] Center 33 (3~64) winsize 62
4398 13:58:47.879314 [CA 5] Center 33 (3~64) winsize 62
4399 13:58:47.879394
4400 13:58:47.882665 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4401 13:58:47.882765
4402 13:58:47.886267 [CATrainingPosCal] consider 1 rank data
4403 13:58:47.889344 u2DelayCellTimex100 = 270/100 ps
4404 13:58:47.892932 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4405 13:58:47.899635 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4406 13:58:47.902745 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4407 13:58:47.906073 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 13:58:47.909077 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 13:58:47.912090 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4410 13:58:47.912167
4411 13:58:47.915456 CA PerBit enable=1, Macro0, CA PI delay=33
4412 13:58:47.915525
4413 13:58:47.918822 [CBTSetCACLKResult] CA Dly = 33
4414 13:58:47.922741 CS Dly: 3 (0~34)
4415 13:58:47.922838 ==
4416 13:58:47.925366 Dram Type= 6, Freq= 0, CH_1, rank 1
4417 13:58:47.929021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 13:58:47.929099 ==
4419 13:58:47.935247 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4420 13:58:47.938536 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4421 13:58:47.942756 [CA 0] Center 35 (5~66) winsize 62
4422 13:58:47.946108 [CA 1] Center 36 (6~66) winsize 61
4423 13:58:47.949533 [CA 2] Center 34 (4~65) winsize 62
4424 13:58:47.953195 [CA 3] Center 33 (3~64) winsize 62
4425 13:58:47.956642 [CA 4] Center 34 (3~65) winsize 63
4426 13:58:47.959351 [CA 5] Center 33 (3~64) winsize 62
4427 13:58:47.959431
4428 13:58:47.962700 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4429 13:58:47.962781
4430 13:58:47.965767 [CATrainingPosCal] consider 2 rank data
4431 13:58:47.969204 u2DelayCellTimex100 = 270/100 ps
4432 13:58:47.972798 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4433 13:58:47.979314 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4434 13:58:47.982473 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 13:58:47.985576 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 13:58:47.989186 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4437 13:58:47.992354 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4438 13:58:47.992427
4439 13:58:47.995377 CA PerBit enable=1, Macro0, CA PI delay=33
4440 13:58:47.995447
4441 13:58:47.999116 [CBTSetCACLKResult] CA Dly = 33
4442 13:58:48.002073 CS Dly: 4 (0~37)
4443 13:58:48.002142
4444 13:58:48.005257 ----->DramcWriteLeveling(PI) begin...
4445 13:58:48.005325 ==
4446 13:58:48.008620 Dram Type= 6, Freq= 0, CH_1, rank 0
4447 13:58:48.011945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 13:58:48.012014 ==
4449 13:58:48.015727 Write leveling (Byte 0): 30 => 30
4450 13:58:48.018513 Write leveling (Byte 1): 30 => 30
4451 13:58:48.022227 DramcWriteLeveling(PI) end<-----
4452 13:58:48.022322
4453 13:58:48.022409 ==
4454 13:58:48.025287 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 13:58:48.028659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 13:58:48.028758 ==
4457 13:58:48.031967 [Gating] SW mode calibration
4458 13:58:48.038528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4459 13:58:48.045268 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4460 13:58:48.048665 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 13:58:48.051577 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4462 13:58:48.058009 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 13:58:48.061303 0 9 12 | B1->B0 | 3030 2929 | 0 0 | (0 0) (0 1)
4464 13:58:48.064980 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
4465 13:58:48.071335 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 13:58:48.075002 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 13:58:48.078340 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 13:58:48.084852 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 13:58:48.087968 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 13:58:48.094063 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4471 13:58:48.097538 0 10 12 | B1->B0 | 2b2b 3c3c | 0 0 | (1 1) (0 0)
4472 13:58:48.100812 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4473 13:58:48.104482 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 13:58:48.110845 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 13:58:48.114216 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 13:58:48.117675 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 13:58:48.124122 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 13:58:48.127213 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 13:58:48.131283 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4480 13:58:48.137144 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4481 13:58:48.140892 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 13:58:48.144050 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 13:58:48.150440 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 13:58:48.154107 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 13:58:48.157133 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 13:58:48.163887 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 13:58:48.167008 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 13:58:48.170042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 13:58:48.176633 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 13:58:48.180133 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 13:58:48.183277 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 13:58:48.189909 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 13:58:48.193466 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 13:58:48.197493 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 13:58:48.203147 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4496 13:58:48.206572 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4497 13:58:48.210011 Total UI for P1: 0, mck2ui 16
4498 13:58:48.213154 best dqsien dly found for B0: ( 0, 13, 12)
4499 13:58:48.216465 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 13:58:48.220483 Total UI for P1: 0, mck2ui 16
4501 13:58:48.223445 best dqsien dly found for B1: ( 0, 13, 14)
4502 13:58:48.226763 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4503 13:58:48.232903 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4504 13:58:48.233002
4505 13:58:48.236181 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4506 13:58:48.239624 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4507 13:58:48.243119 [Gating] SW calibration Done
4508 13:58:48.243189 ==
4509 13:58:48.246109 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 13:58:48.249850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 13:58:48.249919 ==
4512 13:58:48.253484 RX Vref Scan: 0
4513 13:58:48.253586
4514 13:58:48.253676 RX Vref 0 -> 0, step: 1
4515 13:58:48.253736
4516 13:58:48.255883 RX Delay -230 -> 252, step: 16
4517 13:58:48.259466 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4518 13:58:48.266081 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4519 13:58:48.269167 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4520 13:58:48.272876 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4521 13:58:48.275934 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4522 13:58:48.282255 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4523 13:58:48.285628 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4524 13:58:48.289061 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4525 13:58:48.292526 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4526 13:58:48.295492 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4527 13:58:48.302560 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4528 13:58:48.305684 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4529 13:58:48.309135 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4530 13:58:48.312123 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4531 13:58:48.318784 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4532 13:58:48.322145 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4533 13:58:48.322228 ==
4534 13:58:48.325274 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 13:58:48.328511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 13:58:48.328594 ==
4537 13:58:48.331769 DQS Delay:
4538 13:58:48.331872 DQS0 = 0, DQS1 = 0
4539 13:58:48.335345 DQM Delay:
4540 13:58:48.335441 DQM0 = 46, DQM1 = 34
4541 13:58:48.335529 DQ Delay:
4542 13:58:48.338220 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4543 13:58:48.341863 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4544 13:58:48.345049 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4545 13:58:48.348158 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =49
4546 13:58:48.348254
4547 13:58:48.348345
4548 13:58:48.351452 ==
4549 13:58:48.354692 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 13:58:48.358344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 13:58:48.358446 ==
4552 13:58:48.358535
4553 13:58:48.358652
4554 13:58:48.361281 TX Vref Scan disable
4555 13:58:48.361377 == TX Byte 0 ==
4556 13:58:48.368415 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4557 13:58:48.371261 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4558 13:58:48.371357 == TX Byte 1 ==
4559 13:58:48.378025 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4560 13:58:48.381587 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4561 13:58:48.381683 ==
4562 13:58:48.384668 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 13:58:48.387985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 13:58:48.388083 ==
4565 13:58:48.388174
4566 13:58:48.388259
4567 13:58:48.391222 TX Vref Scan disable
4568 13:58:48.394291 == TX Byte 0 ==
4569 13:58:48.397562 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4570 13:58:48.400856 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4571 13:58:48.404172 == TX Byte 1 ==
4572 13:58:48.407408 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4573 13:58:48.414017 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4574 13:58:48.414088
4575 13:58:48.414148 [DATLAT]
4576 13:58:48.414206 Freq=600, CH1 RK0
4577 13:58:48.414262
4578 13:58:48.417695 DATLAT Default: 0x9
4579 13:58:48.417767 0, 0xFFFF, sum = 0
4580 13:58:48.420764 1, 0xFFFF, sum = 0
4581 13:58:48.420833 2, 0xFFFF, sum = 0
4582 13:58:48.424023 3, 0xFFFF, sum = 0
4583 13:58:48.427494 4, 0xFFFF, sum = 0
4584 13:58:48.427568 5, 0xFFFF, sum = 0
4585 13:58:48.430441 6, 0xFFFF, sum = 0
4586 13:58:48.430540 7, 0xFFFF, sum = 0
4587 13:58:48.434148 8, 0x0, sum = 1
4588 13:58:48.434227 9, 0x0, sum = 2
4589 13:58:48.434317 10, 0x0, sum = 3
4590 13:58:48.436984 11, 0x0, sum = 4
4591 13:58:48.437080 best_step = 9
4592 13:58:48.437166
4593 13:58:48.437252 ==
4594 13:58:48.440555 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 13:58:48.446982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 13:58:48.447060 ==
4597 13:58:48.447122 RX Vref Scan: 1
4598 13:58:48.447181
4599 13:58:48.450530 RX Vref 0 -> 0, step: 1
4600 13:58:48.450663
4601 13:58:48.453478 RX Delay -195 -> 252, step: 8
4602 13:58:48.453552
4603 13:58:48.457516 Set Vref, RX VrefLevel [Byte0]: 48
4604 13:58:48.460078 [Byte1]: 53
4605 13:58:48.460147
4606 13:58:48.463835 Final RX Vref Byte 0 = 48 to rank0
4607 13:58:48.467032 Final RX Vref Byte 1 = 53 to rank0
4608 13:58:48.469909 Final RX Vref Byte 0 = 48 to rank1
4609 13:58:48.473402 Final RX Vref Byte 1 = 53 to rank1==
4610 13:58:48.476808 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 13:58:48.479825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 13:58:48.483392 ==
4613 13:58:48.483477 DQS Delay:
4614 13:58:48.483562 DQS0 = 0, DQS1 = 0
4615 13:58:48.486879 DQM Delay:
4616 13:58:48.486962 DQM0 = 45, DQM1 = 34
4617 13:58:48.489979 DQ Delay:
4618 13:58:48.490062 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4619 13:58:48.493189 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =40
4620 13:58:48.497127 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4621 13:58:48.499996 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =44
4622 13:58:48.502940
4623 13:58:48.503019
4624 13:58:48.509742 [DQSOSCAuto] RK0, (LSB)MR18= 0x563b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 393 ps
4625 13:58:48.513245 CH1 RK0: MR19=808, MR18=563B
4626 13:58:48.519864 CH1_RK0: MR19=0x808, MR18=0x563B, DQSOSC=393, MR23=63, INC=169, DEC=113
4627 13:58:48.519948
4628 13:58:48.523323 ----->DramcWriteLeveling(PI) begin...
4629 13:58:48.523438 ==
4630 13:58:48.526162 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 13:58:48.529516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 13:58:48.529618 ==
4633 13:58:48.532677 Write leveling (Byte 0): 31 => 31
4634 13:58:48.536098 Write leveling (Byte 1): 28 => 28
4635 13:58:48.539317 DramcWriteLeveling(PI) end<-----
4636 13:58:48.539390
4637 13:58:48.539451 ==
4638 13:58:48.542641 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 13:58:48.546672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 13:58:48.546744 ==
4641 13:58:48.549162 [Gating] SW mode calibration
4642 13:58:48.556067 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4643 13:58:48.562418 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4644 13:58:48.566018 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4645 13:58:48.569448 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 13:58:48.576349 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 13:58:48.579679 0 9 12 | B1->B0 | 2f2f 3030 | 1 1 | (1 0) (1 0)
4648 13:58:48.582875 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 13:58:48.589169 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 13:58:48.592154 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 13:58:48.595956 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 13:58:48.602278 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 13:58:48.605452 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 13:58:48.609303 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 13:58:48.615604 0 10 12 | B1->B0 | 3a3a 2d2d | 0 0 | (0 0) (0 0)
4656 13:58:48.618852 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
4657 13:58:48.622247 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 13:58:48.629161 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 13:58:48.632242 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 13:58:48.635605 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 13:58:48.641900 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 13:58:48.645324 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 13:58:48.648729 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4664 13:58:48.655454 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 13:58:48.658821 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 13:58:48.661888 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 13:58:48.668520 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 13:58:48.671720 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 13:58:48.675252 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 13:58:48.681729 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 13:58:48.684830 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 13:58:48.688700 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 13:58:48.694992 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 13:58:48.698130 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 13:58:48.701815 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 13:58:48.708533 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 13:58:48.711400 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 13:58:48.714900 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 13:58:48.721408 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 13:58:48.724518 Total UI for P1: 0, mck2ui 16
4681 13:58:48.728188 best dqsien dly found for B0: ( 0, 13, 10)
4682 13:58:48.728260 Total UI for P1: 0, mck2ui 16
4683 13:58:48.734408 best dqsien dly found for B1: ( 0, 13, 10)
4684 13:58:48.737584 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4685 13:58:48.741547 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4686 13:58:48.741644
4687 13:58:48.744453 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4688 13:58:48.747937 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4689 13:58:48.751378 [Gating] SW calibration Done
4690 13:58:48.751475 ==
4691 13:58:48.754356 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 13:58:48.757767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 13:58:48.757842 ==
4694 13:58:48.760759 RX Vref Scan: 0
4695 13:58:48.760828
4696 13:58:48.760887 RX Vref 0 -> 0, step: 1
4697 13:58:48.764220
4698 13:58:48.764300 RX Delay -230 -> 252, step: 16
4699 13:58:48.770871 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4700 13:58:48.774434 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4701 13:58:48.777972 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4702 13:58:48.780780 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4703 13:58:48.787280 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4704 13:58:48.790878 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4705 13:58:48.794199 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4706 13:58:48.797214 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4707 13:58:48.800633 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4708 13:58:48.807189 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4709 13:58:48.810620 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4710 13:58:48.813930 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4711 13:58:48.817090 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4712 13:58:48.824117 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4713 13:58:48.827200 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4714 13:58:48.830396 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4715 13:58:48.830464 ==
4716 13:58:48.834334 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 13:58:48.836949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 13:58:48.840137 ==
4719 13:58:48.840205 DQS Delay:
4720 13:58:48.840264 DQS0 = 0, DQS1 = 0
4721 13:58:48.843560 DQM Delay:
4722 13:58:48.843626 DQM0 = 41, DQM1 = 33
4723 13:58:48.846922 DQ Delay:
4724 13:58:48.850201 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4725 13:58:48.850268 DQ4 =33, DQ5 =49, DQ6 =65, DQ7 =33
4726 13:58:48.853742 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4727 13:58:48.860009 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4728 13:58:48.860106
4729 13:58:48.860198
4730 13:58:48.860284 ==
4731 13:58:48.863398 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 13:58:48.867320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 13:58:48.867390 ==
4734 13:58:48.867454
4735 13:58:48.867512
4736 13:58:48.870565 TX Vref Scan disable
4737 13:58:48.870681 == TX Byte 0 ==
4738 13:58:48.876979 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4739 13:58:48.880376 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4740 13:58:48.880488 == TX Byte 1 ==
4741 13:58:48.886506 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4742 13:58:48.890048 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4743 13:58:48.890146 ==
4744 13:58:48.893820 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 13:58:48.896763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 13:58:48.896835 ==
4747 13:58:48.896897
4748 13:58:48.896954
4749 13:58:48.899919 TX Vref Scan disable
4750 13:58:48.903143 == TX Byte 0 ==
4751 13:58:48.906390 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4752 13:58:48.913399 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4753 13:58:48.913501 == TX Byte 1 ==
4754 13:58:48.916691 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4755 13:58:48.922959 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4756 13:58:48.923031
4757 13:58:48.923091 [DATLAT]
4758 13:58:48.923150 Freq=600, CH1 RK1
4759 13:58:48.923212
4760 13:58:48.926191 DATLAT Default: 0x9
4761 13:58:48.929418 0, 0xFFFF, sum = 0
4762 13:58:48.929496 1, 0xFFFF, sum = 0
4763 13:58:48.932900 2, 0xFFFF, sum = 0
4764 13:58:48.932999 3, 0xFFFF, sum = 0
4765 13:58:48.936270 4, 0xFFFF, sum = 0
4766 13:58:48.936369 5, 0xFFFF, sum = 0
4767 13:58:48.939972 6, 0xFFFF, sum = 0
4768 13:58:48.940045 7, 0xFFFF, sum = 0
4769 13:58:48.942889 8, 0x0, sum = 1
4770 13:58:48.942989 9, 0x0, sum = 2
4771 13:58:48.945929 10, 0x0, sum = 3
4772 13:58:48.946027 11, 0x0, sum = 4
4773 13:58:48.946117 best_step = 9
4774 13:58:48.946214
4775 13:58:48.949376 ==
4776 13:58:48.953304 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 13:58:48.956249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 13:58:48.956322 ==
4779 13:58:48.956390 RX Vref Scan: 0
4780 13:58:48.956449
4781 13:58:48.959597 RX Vref 0 -> 0, step: 1
4782 13:58:48.959664
4783 13:58:48.962286 RX Delay -195 -> 252, step: 8
4784 13:58:48.969070 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4785 13:58:48.972088 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4786 13:58:48.975990 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4787 13:58:48.979588 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4788 13:58:48.985465 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4789 13:58:48.988619 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4790 13:58:48.992194 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4791 13:58:48.995379 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4792 13:58:48.998817 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4793 13:58:49.005466 iDelay=213, Bit 9, Center 20 (-139 ~ 180) 320
4794 13:58:49.008320 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4795 13:58:49.011493 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4796 13:58:49.015194 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4797 13:58:49.021762 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4798 13:58:49.025251 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4799 13:58:49.028116 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4800 13:58:49.028186 ==
4801 13:58:49.031614 Dram Type= 6, Freq= 0, CH_1, rank 1
4802 13:58:49.038444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4803 13:58:49.038541 ==
4804 13:58:49.038670 DQS Delay:
4805 13:58:49.038731 DQS0 = 0, DQS1 = 0
4806 13:58:49.041500 DQM Delay:
4807 13:58:49.041593 DQM0 = 42, DQM1 = 33
4808 13:58:49.044710 DQ Delay:
4809 13:58:49.048120 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4810 13:58:49.051484 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4811 13:58:49.054454 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4812 13:58:49.057683 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4813 13:58:49.057754
4814 13:58:49.057822
4815 13:58:49.064387 [DQSOSCAuto] RK1, (LSB)MR18= 0x3026, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4816 13:58:49.068077 CH1 RK1: MR19=808, MR18=3026
4817 13:58:49.074289 CH1_RK1: MR19=0x808, MR18=0x3026, DQSOSC=400, MR23=63, INC=163, DEC=109
4818 13:58:49.077608 [RxdqsGatingPostProcess] freq 600
4819 13:58:49.081413 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4820 13:58:49.084215 Pre-setting of DQS Precalculation
4821 13:58:49.091162 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4822 13:58:49.097405 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4823 13:58:49.104713 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4824 13:58:49.104786
4825 13:58:49.104847
4826 13:58:49.107397 [Calibration Summary] 1200 Mbps
4827 13:58:49.107474 CH 0, Rank 0
4828 13:58:49.111091 SW Impedance : PASS
4829 13:58:49.113786 DUTY Scan : NO K
4830 13:58:49.113862 ZQ Calibration : PASS
4831 13:58:49.117778 Jitter Meter : NO K
4832 13:58:49.120662 CBT Training : PASS
4833 13:58:49.120736 Write leveling : PASS
4834 13:58:49.124304 RX DQS gating : PASS
4835 13:58:49.126881 RX DQ/DQS(RDDQC) : PASS
4836 13:58:49.126951 TX DQ/DQS : PASS
4837 13:58:49.130665 RX DATLAT : PASS
4838 13:58:49.133560 RX DQ/DQS(Engine): PASS
4839 13:58:49.133630 TX OE : NO K
4840 13:58:49.136970 All Pass.
4841 13:58:49.137065
4842 13:58:49.137153 CH 0, Rank 1
4843 13:58:49.140262 SW Impedance : PASS
4844 13:58:49.140331 DUTY Scan : NO K
4845 13:58:49.143701 ZQ Calibration : PASS
4846 13:58:49.146579 Jitter Meter : NO K
4847 13:58:49.146686 CBT Training : PASS
4848 13:58:49.150170 Write leveling : PASS
4849 13:58:49.153269 RX DQS gating : PASS
4850 13:58:49.153352 RX DQ/DQS(RDDQC) : PASS
4851 13:58:49.156652 TX DQ/DQS : PASS
4852 13:58:49.160243 RX DATLAT : PASS
4853 13:58:49.160340 RX DQ/DQS(Engine): PASS
4854 13:58:49.163349 TX OE : NO K
4855 13:58:49.163431 All Pass.
4856 13:58:49.163495
4857 13:58:49.166584 CH 1, Rank 0
4858 13:58:49.166685 SW Impedance : PASS
4859 13:58:49.169999 DUTY Scan : NO K
4860 13:58:49.173781 ZQ Calibration : PASS
4861 13:58:49.173861 Jitter Meter : NO K
4862 13:58:49.176613 CBT Training : PASS
4863 13:58:49.176694 Write leveling : PASS
4864 13:58:49.180133 RX DQS gating : PASS
4865 13:58:49.183446 RX DQ/DQS(RDDQC) : PASS
4866 13:58:49.183526 TX DQ/DQS : PASS
4867 13:58:49.186479 RX DATLAT : PASS
4868 13:58:49.189937 RX DQ/DQS(Engine): PASS
4869 13:58:49.190017 TX OE : NO K
4870 13:58:49.193133 All Pass.
4871 13:58:49.193217
4872 13:58:49.193279 CH 1, Rank 1
4873 13:58:49.196221 SW Impedance : PASS
4874 13:58:49.196302 DUTY Scan : NO K
4875 13:58:49.199517 ZQ Calibration : PASS
4876 13:58:49.202610 Jitter Meter : NO K
4877 13:58:49.202706 CBT Training : PASS
4878 13:58:49.205850 Write leveling : PASS
4879 13:58:49.209120 RX DQS gating : PASS
4880 13:58:49.209200 RX DQ/DQS(RDDQC) : PASS
4881 13:58:49.212971 TX DQ/DQS : PASS
4882 13:58:49.215953 RX DATLAT : PASS
4883 13:58:49.216033 RX DQ/DQS(Engine): PASS
4884 13:58:49.219371 TX OE : NO K
4885 13:58:49.219452 All Pass.
4886 13:58:49.219516
4887 13:58:49.222383 DramC Write-DBI off
4888 13:58:49.225631 PER_BANK_REFRESH: Hybrid Mode
4889 13:58:49.225713 TX_TRACKING: ON
4890 13:58:49.235944 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4891 13:58:49.238872 [FAST_K] Save calibration result to emmc
4892 13:58:49.242414 dramc_set_vcore_voltage set vcore to 662500
4893 13:58:49.245457 Read voltage for 933, 3
4894 13:58:49.245529 Vio18 = 0
4895 13:58:49.245590 Vcore = 662500
4896 13:58:49.248929 Vdram = 0
4897 13:58:49.249010 Vddq = 0
4898 13:58:49.249073 Vmddr = 0
4899 13:58:49.255549 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4900 13:58:49.258784 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4901 13:58:49.262399 MEM_TYPE=3, freq_sel=17
4902 13:58:49.265548 sv_algorithm_assistance_LP4_1600
4903 13:58:49.268596 ============ PULL DRAM RESETB DOWN ============
4904 13:58:49.272349 ========== PULL DRAM RESETB DOWN end =========
4905 13:58:49.278574 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4906 13:58:49.282161 ===================================
4907 13:58:49.285418 LPDDR4 DRAM CONFIGURATION
4908 13:58:49.288613 ===================================
4909 13:58:49.288710 EX_ROW_EN[0] = 0x0
4910 13:58:49.291864 EX_ROW_EN[1] = 0x0
4911 13:58:49.291939 LP4Y_EN = 0x0
4912 13:58:49.295188 WORK_FSP = 0x0
4913 13:58:49.295261 WL = 0x3
4914 13:58:49.298271 RL = 0x3
4915 13:58:49.298365 BL = 0x2
4916 13:58:49.301661 RPST = 0x0
4917 13:58:49.301734 RD_PRE = 0x0
4918 13:58:49.305581 WR_PRE = 0x1
4919 13:58:49.305675 WR_PST = 0x0
4920 13:58:49.308518 DBI_WR = 0x0
4921 13:58:49.311854 DBI_RD = 0x0
4922 13:58:49.311922 OTF = 0x1
4923 13:58:49.315061 ===================================
4924 13:58:49.318318 ===================================
4925 13:58:49.318413 ANA top config
4926 13:58:49.321732 ===================================
4927 13:58:49.324968 DLL_ASYNC_EN = 0
4928 13:58:49.328392 ALL_SLAVE_EN = 1
4929 13:58:49.331547 NEW_RANK_MODE = 1
4930 13:58:49.334887 DLL_IDLE_MODE = 1
4931 13:58:49.334986 LP45_APHY_COMB_EN = 1
4932 13:58:49.338301 TX_ODT_DIS = 1
4933 13:58:49.341678 NEW_8X_MODE = 1
4934 13:58:49.344737 ===================================
4935 13:58:49.348126 ===================================
4936 13:58:49.351580 data_rate = 1866
4937 13:58:49.354760 CKR = 1
4938 13:58:49.354861 DQ_P2S_RATIO = 8
4939 13:58:49.358176 ===================================
4940 13:58:49.361420 CA_P2S_RATIO = 8
4941 13:58:49.365162 DQ_CA_OPEN = 0
4942 13:58:49.368314 DQ_SEMI_OPEN = 0
4943 13:58:49.371244 CA_SEMI_OPEN = 0
4944 13:58:49.374570 CA_FULL_RATE = 0
4945 13:58:49.374680 DQ_CKDIV4_EN = 1
4946 13:58:49.377659 CA_CKDIV4_EN = 1
4947 13:58:49.381028 CA_PREDIV_EN = 0
4948 13:58:49.384749 PH8_DLY = 0
4949 13:58:49.387950 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4950 13:58:49.391400 DQ_AAMCK_DIV = 4
4951 13:58:49.391471 CA_AAMCK_DIV = 4
4952 13:58:49.394541 CA_ADMCK_DIV = 4
4953 13:58:49.397690 DQ_TRACK_CA_EN = 0
4954 13:58:49.401358 CA_PICK = 933
4955 13:58:49.404849 CA_MCKIO = 933
4956 13:58:49.407755 MCKIO_SEMI = 0
4957 13:58:49.411303 PLL_FREQ = 3732
4958 13:58:49.411371 DQ_UI_PI_RATIO = 32
4959 13:58:49.414916 CA_UI_PI_RATIO = 0
4960 13:58:49.417491 ===================================
4961 13:58:49.420744 ===================================
4962 13:58:49.424333 memory_type:LPDDR4
4963 13:58:49.427493 GP_NUM : 10
4964 13:58:49.427563 SRAM_EN : 1
4965 13:58:49.430647 MD32_EN : 0
4966 13:58:49.433832 ===================================
4967 13:58:49.437110 [ANA_INIT] >>>>>>>>>>>>>>
4968 13:58:49.440861 <<<<<< [CONFIGURE PHASE]: ANA_TX
4969 13:58:49.444518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4970 13:58:49.447497 ===================================
4971 13:58:49.447566 data_rate = 1866,PCW = 0X8f00
4972 13:58:49.450376 ===================================
4973 13:58:49.453707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4974 13:58:49.460508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4975 13:58:49.466793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4976 13:58:49.470167 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4977 13:58:49.473614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4978 13:58:49.477339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4979 13:58:49.480259 [ANA_INIT] flow start
4980 13:58:49.483496 [ANA_INIT] PLL >>>>>>>>
4981 13:58:49.483568 [ANA_INIT] PLL <<<<<<<<
4982 13:58:49.486616 [ANA_INIT] MIDPI >>>>>>>>
4983 13:58:49.489936 [ANA_INIT] MIDPI <<<<<<<<
4984 13:58:49.490005 [ANA_INIT] DLL >>>>>>>>
4985 13:58:49.493276 [ANA_INIT] flow end
4986 13:58:49.496503 ============ LP4 DIFF to SE enter ============
4987 13:58:49.500218 ============ LP4 DIFF to SE exit ============
4988 13:58:49.503029 [ANA_INIT] <<<<<<<<<<<<<
4989 13:58:49.506861 [Flow] Enable top DCM control >>>>>
4990 13:58:49.509774 [Flow] Enable top DCM control <<<<<
4991 13:58:49.513393 Enable DLL master slave shuffle
4992 13:58:49.519461 ==============================================================
4993 13:58:49.519620 Gating Mode config
4994 13:58:49.526206 ==============================================================
4995 13:58:49.529634 Config description:
4996 13:58:49.536238 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4997 13:58:49.543070 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4998 13:58:49.549496 SELPH_MODE 0: By rank 1: By Phase
4999 13:58:49.555664 ==============================================================
5000 13:58:49.558978 GAT_TRACK_EN = 1
5001 13:58:49.559048 RX_GATING_MODE = 2
5002 13:58:49.562557 RX_GATING_TRACK_MODE = 2
5003 13:58:49.565731 SELPH_MODE = 1
5004 13:58:49.568885 PICG_EARLY_EN = 1
5005 13:58:49.572460 VALID_LAT_VALUE = 1
5006 13:58:49.578859 ==============================================================
5007 13:58:49.582694 Enter into Gating configuration >>>>
5008 13:58:49.585645 Exit from Gating configuration <<<<
5009 13:58:49.588870 Enter into DVFS_PRE_config >>>>>
5010 13:58:49.598881 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5011 13:58:49.602657 Exit from DVFS_PRE_config <<<<<
5012 13:58:49.605355 Enter into PICG configuration >>>>
5013 13:58:49.608755 Exit from PICG configuration <<<<
5014 13:58:49.612002 [RX_INPUT] configuration >>>>>
5015 13:58:49.615550 [RX_INPUT] configuration <<<<<
5016 13:58:49.618458 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5017 13:58:49.625242 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5018 13:58:49.631763 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5019 13:58:49.638866 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5020 13:58:49.641697 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5021 13:58:49.648261 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5022 13:58:49.651779 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5023 13:58:49.658359 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5024 13:58:49.661989 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5025 13:58:49.664890 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5026 13:58:49.668412 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5027 13:58:49.674920 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5028 13:58:49.677958 ===================================
5029 13:58:49.681429 LPDDR4 DRAM CONFIGURATION
5030 13:58:49.685096 ===================================
5031 13:58:49.685193 EX_ROW_EN[0] = 0x0
5032 13:58:49.687949 EX_ROW_EN[1] = 0x0
5033 13:58:49.688023 LP4Y_EN = 0x0
5034 13:58:49.691202 WORK_FSP = 0x0
5035 13:58:49.691302 WL = 0x3
5036 13:58:49.694884 RL = 0x3
5037 13:58:49.694954 BL = 0x2
5038 13:58:49.697708 RPST = 0x0
5039 13:58:49.697774 RD_PRE = 0x0
5040 13:58:49.701262 WR_PRE = 0x1
5041 13:58:49.701330 WR_PST = 0x0
5042 13:58:49.704409 DBI_WR = 0x0
5043 13:58:49.704473 DBI_RD = 0x0
5044 13:58:49.707598 OTF = 0x1
5045 13:58:49.710931 ===================================
5046 13:58:49.714272 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5047 13:58:49.717499 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5048 13:58:49.725002 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5049 13:58:49.728133 ===================================
5050 13:58:49.730610 LPDDR4 DRAM CONFIGURATION
5051 13:58:49.730730 ===================================
5052 13:58:49.734122 EX_ROW_EN[0] = 0x10
5053 13:58:49.737330 EX_ROW_EN[1] = 0x0
5054 13:58:49.737426 LP4Y_EN = 0x0
5055 13:58:49.740598 WORK_FSP = 0x0
5056 13:58:49.740695 WL = 0x3
5057 13:58:49.743853 RL = 0x3
5058 13:58:49.743938 BL = 0x2
5059 13:58:49.748648 RPST = 0x0
5060 13:58:49.748745 RD_PRE = 0x0
5061 13:58:49.750550 WR_PRE = 0x1
5062 13:58:49.750690 WR_PST = 0x0
5063 13:58:49.753869 DBI_WR = 0x0
5064 13:58:49.753976 DBI_RD = 0x0
5065 13:58:49.757545 OTF = 0x1
5066 13:58:49.760325 ===================================
5067 13:58:49.767029 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5068 13:58:49.770541 nWR fixed to 30
5069 13:58:49.774212 [ModeRegInit_LP4] CH0 RK0
5070 13:58:49.774321 [ModeRegInit_LP4] CH0 RK1
5071 13:58:49.777376 [ModeRegInit_LP4] CH1 RK0
5072 13:58:49.780752 [ModeRegInit_LP4] CH1 RK1
5073 13:58:49.780850 match AC timing 9
5074 13:58:49.786831 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5075 13:58:49.790105 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5076 13:58:49.793497 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5077 13:58:49.800189 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5078 13:58:49.803542 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5079 13:58:49.803619 ==
5080 13:58:49.807338 Dram Type= 6, Freq= 0, CH_0, rank 0
5081 13:58:49.810393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5082 13:58:49.810490 ==
5083 13:58:49.816759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5084 13:58:49.823443 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5085 13:58:49.826730 [CA 0] Center 37 (7~68) winsize 62
5086 13:58:49.830645 [CA 1] Center 37 (7~68) winsize 62
5087 13:58:49.833849 [CA 2] Center 34 (4~65) winsize 62
5088 13:58:49.837020 [CA 3] Center 35 (5~65) winsize 61
5089 13:58:49.840681 [CA 4] Center 33 (3~64) winsize 62
5090 13:58:49.843478 [CA 5] Center 33 (3~63) winsize 61
5091 13:58:49.843551
5092 13:58:49.846484 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5093 13:58:49.846586
5094 13:58:49.850182 [CATrainingPosCal] consider 1 rank data
5095 13:58:49.853426 u2DelayCellTimex100 = 270/100 ps
5096 13:58:49.856416 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5097 13:58:49.859708 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5098 13:58:49.862988 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5099 13:58:49.866457 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5100 13:58:49.872826 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5101 13:58:49.876558 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5102 13:58:49.876660
5103 13:58:49.879990 CA PerBit enable=1, Macro0, CA PI delay=33
5104 13:58:49.880063
5105 13:58:49.882743 [CBTSetCACLKResult] CA Dly = 33
5106 13:58:49.882836 CS Dly: 7 (0~38)
5107 13:58:49.882927 ==
5108 13:58:49.886072 Dram Type= 6, Freq= 0, CH_0, rank 1
5109 13:58:49.893136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 13:58:49.893213 ==
5111 13:58:49.895822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5112 13:58:49.902555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5113 13:58:49.905731 [CA 0] Center 37 (7~68) winsize 62
5114 13:58:49.909141 [CA 1] Center 37 (7~68) winsize 62
5115 13:58:49.913182 [CA 2] Center 34 (4~65) winsize 62
5116 13:58:49.915765 [CA 3] Center 34 (4~65) winsize 62
5117 13:58:49.919527 [CA 4] Center 33 (3~64) winsize 62
5118 13:58:49.922420 [CA 5] Center 32 (2~63) winsize 62
5119 13:58:49.922522
5120 13:58:49.925575 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5121 13:58:49.925669
5122 13:58:49.928948 [CATrainingPosCal] consider 2 rank data
5123 13:58:49.932340 u2DelayCellTimex100 = 270/100 ps
5124 13:58:49.935623 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5125 13:58:49.938965 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5126 13:58:49.945789 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5127 13:58:49.948763 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5128 13:58:49.952936 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5129 13:58:49.955295 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5130 13:58:49.955393
5131 13:58:49.958708 CA PerBit enable=1, Macro0, CA PI delay=33
5132 13:58:49.958805
5133 13:58:49.962367 [CBTSetCACLKResult] CA Dly = 33
5134 13:58:49.962464 CS Dly: 7 (0~39)
5135 13:58:49.965797
5136 13:58:49.968678 ----->DramcWriteLeveling(PI) begin...
5137 13:58:49.968781 ==
5138 13:58:49.972157 Dram Type= 6, Freq= 0, CH_0, rank 0
5139 13:58:49.975527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 13:58:49.975619 ==
5141 13:58:49.978768 Write leveling (Byte 0): 34 => 34
5142 13:58:49.982332 Write leveling (Byte 1): 30 => 30
5143 13:58:49.985161 DramcWriteLeveling(PI) end<-----
5144 13:58:49.985256
5145 13:58:49.985353 ==
5146 13:58:49.988645 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 13:58:49.992202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 13:58:49.992302 ==
5149 13:58:49.995417 [Gating] SW mode calibration
5150 13:58:50.001750 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5151 13:58:50.008289 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5152 13:58:50.012385 0 14 0 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
5153 13:58:50.014677 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5154 13:58:50.021159 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 13:58:50.025012 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 13:58:50.028007 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 13:58:50.034440 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 13:58:50.037802 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 13:58:50.041396 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
5160 13:58:50.047875 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
5161 13:58:50.050993 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 13:58:50.054918 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 13:58:50.061269 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 13:58:50.064944 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 13:58:50.067636 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 13:58:50.074173 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 13:58:50.077472 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
5168 13:58:50.080918 1 0 0 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
5169 13:58:50.087107 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5170 13:58:50.090507 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 13:58:50.093810 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 13:58:50.100143 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 13:58:50.104343 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 13:58:50.107125 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 13:58:50.113514 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5176 13:58:50.116845 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5177 13:58:50.120454 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 13:58:50.126783 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 13:58:50.130343 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 13:58:50.133466 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 13:58:50.140022 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 13:58:50.143431 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 13:58:50.146520 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 13:58:50.153107 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 13:58:50.156753 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 13:58:50.160140 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 13:58:50.166516 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 13:58:50.169744 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 13:58:50.172909 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 13:58:50.179703 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5191 13:58:50.182904 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5192 13:58:50.186293 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5193 13:58:50.189276 Total UI for P1: 0, mck2ui 16
5194 13:58:50.192436 best dqsien dly found for B0: ( 1, 2, 26)
5195 13:58:50.199619 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 13:58:50.199690 Total UI for P1: 0, mck2ui 16
5197 13:58:50.205786 best dqsien dly found for B1: ( 1, 3, 0)
5198 13:58:50.209417 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5199 13:58:50.212553 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5200 13:58:50.212639
5201 13:58:50.215555 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5202 13:58:50.219644 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5203 13:58:50.222559 [Gating] SW calibration Done
5204 13:58:50.222675 ==
5205 13:58:50.225597 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 13:58:50.228849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 13:58:50.228918 ==
5208 13:58:50.232664 RX Vref Scan: 0
5209 13:58:50.232757
5210 13:58:50.232844 RX Vref 0 -> 0, step: 1
5211 13:58:50.232933
5212 13:58:50.235506 RX Delay -80 -> 252, step: 8
5213 13:58:50.242022 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5214 13:58:50.245508 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5215 13:58:50.248640 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5216 13:58:50.251937 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5217 13:58:50.254961 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5218 13:58:50.258966 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5219 13:58:50.265226 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5220 13:58:50.268383 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5221 13:58:50.271718 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5222 13:58:50.274902 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5223 13:58:50.279095 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5224 13:58:50.285000 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5225 13:58:50.288273 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5226 13:58:50.292006 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5227 13:58:50.294773 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5228 13:58:50.297953 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5229 13:58:50.298021 ==
5230 13:58:50.301467 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 13:58:50.308776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 13:58:50.308845 ==
5233 13:58:50.308905 DQS Delay:
5234 13:58:50.311458 DQS0 = 0, DQS1 = 0
5235 13:58:50.311525 DQM Delay:
5236 13:58:50.314840 DQM0 = 96, DQM1 = 86
5237 13:58:50.314907 DQ Delay:
5238 13:58:50.318201 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5239 13:58:50.321102 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5240 13:58:50.325012 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5241 13:58:50.327769 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5242 13:58:50.327841
5243 13:58:50.327922
5244 13:58:50.327983 ==
5245 13:58:50.331528 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 13:58:50.334360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 13:58:50.334455 ==
5248 13:58:50.334543
5249 13:58:50.334662
5250 13:58:50.337796 TX Vref Scan disable
5251 13:58:50.340941 == TX Byte 0 ==
5252 13:58:50.344397 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5253 13:58:50.347727 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5254 13:58:50.350772 == TX Byte 1 ==
5255 13:58:50.354000 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5256 13:58:50.357400 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5257 13:58:50.357473 ==
5258 13:58:50.361065 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 13:58:50.367195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 13:58:50.367270 ==
5261 13:58:50.367332
5262 13:58:50.367395
5263 13:58:50.367482 TX Vref Scan disable
5264 13:58:50.371443 == TX Byte 0 ==
5265 13:58:50.374765 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5266 13:58:50.382038 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5267 13:58:50.382112 == TX Byte 1 ==
5268 13:58:50.384873 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5269 13:58:50.391184 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5270 13:58:50.391284
5271 13:58:50.391360 [DATLAT]
5272 13:58:50.391420 Freq=933, CH0 RK0
5273 13:58:50.391478
5274 13:58:50.394258 DATLAT Default: 0xd
5275 13:58:50.397970 0, 0xFFFF, sum = 0
5276 13:58:50.398045 1, 0xFFFF, sum = 0
5277 13:58:50.400830 2, 0xFFFF, sum = 0
5278 13:58:50.400927 3, 0xFFFF, sum = 0
5279 13:58:50.404160 4, 0xFFFF, sum = 0
5280 13:58:50.404234 5, 0xFFFF, sum = 0
5281 13:58:50.408471 6, 0xFFFF, sum = 0
5282 13:58:50.408544 7, 0xFFFF, sum = 0
5283 13:58:50.410943 8, 0xFFFF, sum = 0
5284 13:58:50.411011 9, 0xFFFF, sum = 0
5285 13:58:50.414012 10, 0x0, sum = 1
5286 13:58:50.414085 11, 0x0, sum = 2
5287 13:58:50.417525 12, 0x0, sum = 3
5288 13:58:50.417622 13, 0x0, sum = 4
5289 13:58:50.420636 best_step = 11
5290 13:58:50.420702
5291 13:58:50.420761 ==
5292 13:58:50.424190 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 13:58:50.427438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 13:58:50.427532 ==
5295 13:58:50.427620 RX Vref Scan: 1
5296 13:58:50.427704
5297 13:58:50.430541 RX Vref 0 -> 0, step: 1
5298 13:58:50.430660
5299 13:58:50.434137 RX Delay -61 -> 252, step: 4
5300 13:58:50.434200
5301 13:58:50.437152 Set Vref, RX VrefLevel [Byte0]: 63
5302 13:58:50.440859 [Byte1]: 55
5303 13:58:50.444167
5304 13:58:50.444235 Final RX Vref Byte 0 = 63 to rank0
5305 13:58:50.447465 Final RX Vref Byte 1 = 55 to rank0
5306 13:58:50.450356 Final RX Vref Byte 0 = 63 to rank1
5307 13:58:50.454192 Final RX Vref Byte 1 = 55 to rank1==
5308 13:58:50.457123 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 13:58:50.463587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 13:58:50.463661 ==
5311 13:58:50.463723 DQS Delay:
5312 13:58:50.467107 DQS0 = 0, DQS1 = 0
5313 13:58:50.467199 DQM Delay:
5314 13:58:50.467285 DQM0 = 96, DQM1 = 86
5315 13:58:50.470212 DQ Delay:
5316 13:58:50.473789 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5317 13:58:50.476957 DQ4 =96, DQ5 =86, DQ6 =108, DQ7 =106
5318 13:58:50.480324 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =82
5319 13:58:50.484026 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5320 13:58:50.484120
5321 13:58:50.484210
5322 13:58:50.489955 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5323 13:58:50.493189 CH0 RK0: MR19=505, MR18=2B11
5324 13:58:50.499837 CH0_RK0: MR19=0x505, MR18=0x2B11, DQSOSC=408, MR23=63, INC=65, DEC=43
5325 13:58:50.499916
5326 13:58:50.503232 ----->DramcWriteLeveling(PI) begin...
5327 13:58:50.503306 ==
5328 13:58:50.506498 Dram Type= 6, Freq= 0, CH_0, rank 1
5329 13:58:50.509861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 13:58:50.509937 ==
5331 13:58:50.513099 Write leveling (Byte 0): 33 => 33
5332 13:58:50.516460 Write leveling (Byte 1): 33 => 33
5333 13:58:50.519963 DramcWriteLeveling(PI) end<-----
5334 13:58:50.520037
5335 13:58:50.520100 ==
5336 13:58:50.523057 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 13:58:50.526545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 13:58:50.529647 ==
5339 13:58:50.529758 [Gating] SW mode calibration
5340 13:58:50.539685 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5341 13:58:50.542813 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5342 13:58:50.546545 0 14 0 | B1->B0 | 2c2b 3434 | 1 0 | (0 0) (0 0)
5343 13:58:50.552722 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 13:58:50.556087 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 13:58:50.559613 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 13:58:50.566316 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 13:58:50.569180 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 13:58:50.572702 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 13:58:50.579537 0 14 28 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (1 0)
5350 13:58:50.582622 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
5351 13:58:50.585518 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 13:58:50.592608 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 13:58:50.595859 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 13:58:50.598808 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 13:58:50.605242 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 13:58:50.608791 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 13:58:50.611881 0 15 28 | B1->B0 | 2727 3939 | 1 0 | (1 1) (0 0)
5358 13:58:50.618625 1 0 0 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
5359 13:58:50.621978 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 13:58:50.625122 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 13:58:50.632322 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 13:58:50.635573 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 13:58:50.638521 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 13:58:50.645189 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 13:58:50.648261 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5366 13:58:50.652340 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5367 13:58:50.658037 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 13:58:50.661618 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 13:58:50.664725 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 13:58:50.672037 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 13:58:50.674959 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 13:58:50.678010 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 13:58:50.684666 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 13:58:50.688225 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 13:58:50.692034 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 13:58:50.698477 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 13:58:50.701298 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 13:58:50.704919 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 13:58:50.711690 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 13:58:50.714970 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5381 13:58:50.717713 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5382 13:58:50.724802 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5383 13:58:50.724904 Total UI for P1: 0, mck2ui 16
5384 13:58:50.731316 best dqsien dly found for B0: ( 1, 2, 26)
5385 13:58:50.734074 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 13:58:50.737651 Total UI for P1: 0, mck2ui 16
5387 13:58:50.740825 best dqsien dly found for B1: ( 1, 3, 0)
5388 13:58:50.744501 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5389 13:58:50.747358 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5390 13:58:50.747428
5391 13:58:50.750926 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5392 13:58:50.754142 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5393 13:58:50.757304 [Gating] SW calibration Done
5394 13:58:50.757381 ==
5395 13:58:50.760726 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 13:58:50.766926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 13:58:50.767000 ==
5398 13:58:50.767082 RX Vref Scan: 0
5399 13:58:50.767143
5400 13:58:50.770879 RX Vref 0 -> 0, step: 1
5401 13:58:50.770974
5402 13:58:50.774030 RX Delay -80 -> 252, step: 8
5403 13:58:50.777074 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5404 13:58:50.780587 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5405 13:58:50.783480 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5406 13:58:50.787081 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5407 13:58:50.790277 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5408 13:58:50.796802 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5409 13:58:50.800343 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5410 13:58:50.803277 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5411 13:58:50.807232 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5412 13:58:50.810033 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5413 13:58:50.816756 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5414 13:58:50.820166 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5415 13:58:50.823150 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5416 13:58:50.826330 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5417 13:58:50.829821 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5418 13:58:50.836557 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5419 13:58:50.836656 ==
5420 13:58:50.839524 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 13:58:50.843145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 13:58:50.843230 ==
5423 13:58:50.843293 DQS Delay:
5424 13:58:50.846345 DQS0 = 0, DQS1 = 0
5425 13:58:50.846447 DQM Delay:
5426 13:58:50.849584 DQM0 = 98, DQM1 = 89
5427 13:58:50.849680 DQ Delay:
5428 13:58:50.852940 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5429 13:58:50.856113 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5430 13:58:50.859294 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5431 13:58:50.862504 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5432 13:58:50.862635
5433 13:58:50.862724
5434 13:58:50.862810 ==
5435 13:58:50.866166 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 13:58:50.869070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 13:58:50.873237 ==
5438 13:58:50.873338
5439 13:58:50.873427
5440 13:58:50.873513 TX Vref Scan disable
5441 13:58:50.875799 == TX Byte 0 ==
5442 13:58:50.879572 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5443 13:58:50.882500 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5444 13:58:50.886137 == TX Byte 1 ==
5445 13:58:50.889130 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5446 13:58:50.892339 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5447 13:58:50.895602 ==
5448 13:58:50.899348 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 13:58:50.902345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 13:58:50.902428 ==
5451 13:58:50.902491
5452 13:58:50.902550
5453 13:58:50.905623 TX Vref Scan disable
5454 13:58:50.905703 == TX Byte 0 ==
5455 13:58:50.912114 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5456 13:58:50.915675 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5457 13:58:50.915753 == TX Byte 1 ==
5458 13:58:50.922061 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5459 13:58:50.925464 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5460 13:58:50.925569
5461 13:58:50.925634 [DATLAT]
5462 13:58:50.928989 Freq=933, CH0 RK1
5463 13:58:50.929085
5464 13:58:50.929173 DATLAT Default: 0xb
5465 13:58:50.932126 0, 0xFFFF, sum = 0
5466 13:58:50.932212 1, 0xFFFF, sum = 0
5467 13:58:50.935704 2, 0xFFFF, sum = 0
5468 13:58:50.935775 3, 0xFFFF, sum = 0
5469 13:58:50.938569 4, 0xFFFF, sum = 0
5470 13:58:50.938683 5, 0xFFFF, sum = 0
5471 13:58:50.941836 6, 0xFFFF, sum = 0
5472 13:58:50.941942 7, 0xFFFF, sum = 0
5473 13:58:50.945262 8, 0xFFFF, sum = 0
5474 13:58:50.948650 9, 0xFFFF, sum = 0
5475 13:58:50.948749 10, 0x0, sum = 1
5476 13:58:50.948848 11, 0x0, sum = 2
5477 13:58:50.952102 12, 0x0, sum = 3
5478 13:58:50.952198 13, 0x0, sum = 4
5479 13:58:50.955107 best_step = 11
5480 13:58:50.955201
5481 13:58:50.955302 ==
5482 13:58:50.958182 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 13:58:50.961952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 13:58:50.962050 ==
5485 13:58:50.964890 RX Vref Scan: 0
5486 13:58:50.964985
5487 13:58:50.968264 RX Vref 0 -> 0, step: 1
5488 13:58:50.968337
5489 13:58:50.968399 RX Delay -61 -> 252, step: 4
5490 13:58:50.975764 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5491 13:58:50.979181 iDelay=203, Bit 1, Center 98 (-1 ~ 198) 200
5492 13:58:50.982815 iDelay=203, Bit 2, Center 90 (-5 ~ 186) 192
5493 13:58:50.986005 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5494 13:58:50.988873 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5495 13:58:50.995235 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5496 13:58:50.999272 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5497 13:58:51.001941 iDelay=203, Bit 7, Center 102 (7 ~ 198) 192
5498 13:58:51.005306 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5499 13:58:51.008786 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5500 13:58:51.015684 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5501 13:58:51.018586 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5502 13:58:51.021636 iDelay=203, Bit 12, Center 90 (-5 ~ 186) 192
5503 13:58:51.024972 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5504 13:58:51.028440 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5505 13:58:51.035291 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5506 13:58:51.035400 ==
5507 13:58:51.038941 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 13:58:51.041901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 13:58:51.042007 ==
5510 13:58:51.042097 DQS Delay:
5511 13:58:51.045206 DQS0 = 0, DQS1 = 0
5512 13:58:51.045301 DQM Delay:
5513 13:58:51.048192 DQM0 = 94, DQM1 = 87
5514 13:58:51.048266 DQ Delay:
5515 13:58:51.051884 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =92
5516 13:58:51.054842 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =102
5517 13:58:51.058571 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =80
5518 13:58:51.061392 DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =94
5519 13:58:51.061469
5520 13:58:51.061530
5521 13:58:51.071224 [DQSOSCAuto] RK1, (LSB)MR18= 0x29f9, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 408 ps
5522 13:58:51.071329 CH0 RK1: MR19=504, MR18=29F9
5523 13:58:51.077741 CH0_RK1: MR19=0x504, MR18=0x29F9, DQSOSC=408, MR23=63, INC=65, DEC=43
5524 13:58:51.081040 [RxdqsGatingPostProcess] freq 933
5525 13:58:51.087505 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5526 13:58:51.091278 best DQS0 dly(2T, 0.5T) = (0, 10)
5527 13:58:51.094843 best DQS1 dly(2T, 0.5T) = (0, 11)
5528 13:58:51.097829 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5529 13:58:51.101154 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5530 13:58:51.101258 best DQS0 dly(2T, 0.5T) = (0, 10)
5531 13:58:51.104395 best DQS1 dly(2T, 0.5T) = (0, 11)
5532 13:58:51.107918 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5533 13:58:51.111193 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5534 13:58:51.114324 Pre-setting of DQS Precalculation
5535 13:58:51.120869 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5536 13:58:51.120967 ==
5537 13:58:51.124176 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 13:58:51.127323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 13:58:51.127395 ==
5540 13:58:51.134425 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5541 13:58:51.140623 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5542 13:58:51.143745 [CA 0] Center 36 (6~67) winsize 62
5543 13:58:51.146995 [CA 1] Center 37 (6~68) winsize 63
5544 13:58:51.150331 [CA 2] Center 34 (4~65) winsize 62
5545 13:58:51.153763 [CA 3] Center 33 (3~64) winsize 62
5546 13:58:51.156675 [CA 4] Center 34 (4~64) winsize 61
5547 13:58:51.160608 [CA 5] Center 33 (3~64) winsize 62
5548 13:58:51.160715
5549 13:58:51.164042 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5550 13:58:51.164113
5551 13:58:51.166851 [CATrainingPosCal] consider 1 rank data
5552 13:58:51.170096 u2DelayCellTimex100 = 270/100 ps
5553 13:58:51.173417 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5554 13:58:51.176565 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5555 13:58:51.179903 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5556 13:58:51.183460 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 13:58:51.186659 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5558 13:58:51.193354 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5559 13:58:51.193459
5560 13:58:51.196214 CA PerBit enable=1, Macro0, CA PI delay=33
5561 13:58:51.196313
5562 13:58:51.200156 [CBTSetCACLKResult] CA Dly = 33
5563 13:58:51.200252 CS Dly: 6 (0~37)
5564 13:58:51.200340 ==
5565 13:58:51.202970 Dram Type= 6, Freq= 0, CH_1, rank 1
5566 13:58:51.206197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 13:58:51.209650 ==
5568 13:58:51.213112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5569 13:58:51.219615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5570 13:58:51.223177 [CA 0] Center 36 (6~67) winsize 62
5571 13:58:51.226097 [CA 1] Center 36 (6~67) winsize 62
5572 13:58:51.229431 [CA 2] Center 34 (4~65) winsize 62
5573 13:58:51.232927 [CA 3] Center 33 (3~64) winsize 62
5574 13:58:51.236100 [CA 4] Center 34 (3~65) winsize 63
5575 13:58:51.239530 [CA 5] Center 33 (3~64) winsize 62
5576 13:58:51.239602
5577 13:58:51.242749 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5578 13:58:51.242818
5579 13:58:51.246426 [CATrainingPosCal] consider 2 rank data
5580 13:58:51.249552 u2DelayCellTimex100 = 270/100 ps
5581 13:58:51.253052 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5582 13:58:51.255846 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5583 13:58:51.259816 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5584 13:58:51.265678 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5585 13:58:51.268962 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5586 13:58:51.272369 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5587 13:58:51.272465
5588 13:58:51.275810 CA PerBit enable=1, Macro0, CA PI delay=33
5589 13:58:51.275908
5590 13:58:51.278731 [CBTSetCACLKResult] CA Dly = 33
5591 13:58:51.278804 CS Dly: 7 (0~39)
5592 13:58:51.278865
5593 13:58:51.282322 ----->DramcWriteLeveling(PI) begin...
5594 13:58:51.282422 ==
5595 13:58:51.286007 Dram Type= 6, Freq= 0, CH_1, rank 0
5596 13:58:51.292241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5597 13:58:51.292341 ==
5598 13:58:51.295806 Write leveling (Byte 0): 28 => 28
5599 13:58:51.298681 Write leveling (Byte 1): 29 => 29
5600 13:58:51.301989 DramcWriteLeveling(PI) end<-----
5601 13:58:51.302060
5602 13:58:51.302120 ==
5603 13:58:51.306046 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 13:58:51.308526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 13:58:51.308596 ==
5606 13:58:51.311764 [Gating] SW mode calibration
5607 13:58:51.318980 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5608 13:58:51.325026 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5609 13:58:51.328502 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 13:58:51.331957 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 13:58:51.335163 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 13:58:51.341615 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 13:58:51.345069 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 13:58:51.351691 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 13:58:51.354749 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5616 13:58:51.357814 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (0 0)
5617 13:58:51.364628 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5618 13:58:51.367857 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 13:58:51.370994 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 13:58:51.378544 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 13:58:51.381448 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 13:58:51.384489 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 13:58:51.387768 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 13:58:51.394680 0 15 28 | B1->B0 | 3434 3737 | 1 0 | (0 0) (0 0)
5625 13:58:51.398202 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 13:58:51.401502 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 13:58:51.407542 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 13:58:51.410979 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 13:58:51.414834 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 13:58:51.420647 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 13:58:51.424322 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5632 13:58:51.427303 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5633 13:58:51.433879 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:58:51.437158 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 13:58:51.440534 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 13:58:51.447433 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 13:58:51.450396 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 13:58:51.453879 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 13:58:51.460412 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 13:58:51.464669 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 13:58:51.467030 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 13:58:51.473692 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 13:58:51.476824 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 13:58:51.480382 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 13:58:51.486581 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 13:58:51.489906 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 13:58:51.493857 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5648 13:58:51.499802 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5649 13:58:51.503614 Total UI for P1: 0, mck2ui 16
5650 13:58:51.506783 best dqsien dly found for B0: ( 1, 2, 24)
5651 13:58:51.509876 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 13:58:51.513244 Total UI for P1: 0, mck2ui 16
5653 13:58:51.516362 best dqsien dly found for B1: ( 1, 2, 26)
5654 13:58:51.519945 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5655 13:58:51.523822 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5656 13:58:51.523896
5657 13:58:51.526360 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5658 13:58:51.532939 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5659 13:58:51.533016 [Gating] SW calibration Done
5660 13:58:51.533078 ==
5661 13:58:51.535992 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 13:58:51.543284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 13:58:51.543358 ==
5664 13:58:51.543427 RX Vref Scan: 0
5665 13:58:51.543486
5666 13:58:51.546273 RX Vref 0 -> 0, step: 1
5667 13:58:51.546354
5668 13:58:51.549320 RX Delay -80 -> 252, step: 8
5669 13:58:51.552633 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5670 13:58:51.555660 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5671 13:58:51.559372 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5672 13:58:51.562684 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5673 13:58:51.568999 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5674 13:58:51.572301 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5675 13:58:51.575612 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5676 13:58:51.579114 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5677 13:58:51.582323 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5678 13:58:51.588874 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5679 13:58:51.593161 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5680 13:58:51.595832 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5681 13:58:51.598754 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5682 13:58:51.602465 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5683 13:58:51.608584 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5684 13:58:51.612556 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5685 13:58:51.612630 ==
5686 13:58:51.615282 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 13:58:51.618686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 13:58:51.618759 ==
5689 13:58:51.622154 DQS Delay:
5690 13:58:51.622252 DQS0 = 0, DQS1 = 0
5691 13:58:51.622341 DQM Delay:
5692 13:58:51.625145 DQM0 = 100, DQM1 = 89
5693 13:58:51.625241 DQ Delay:
5694 13:58:51.628684 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =95
5695 13:58:51.631965 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5696 13:58:51.635150 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5697 13:58:51.638408 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5698 13:58:51.638479
5699 13:58:51.638539
5700 13:58:51.638620 ==
5701 13:58:51.641718 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 13:58:51.648741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 13:58:51.648814 ==
5704 13:58:51.648876
5705 13:58:51.648936
5706 13:58:51.648997 TX Vref Scan disable
5707 13:58:51.651871 == TX Byte 0 ==
5708 13:58:51.655461 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5709 13:58:51.661874 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5710 13:58:51.661978 == TX Byte 1 ==
5711 13:58:51.665578 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5712 13:58:51.672838 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5713 13:58:51.672943 ==
5714 13:58:51.675023 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 13:58:51.678783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 13:58:51.678860 ==
5717 13:58:51.678924
5718 13:58:51.678983
5719 13:58:51.681838 TX Vref Scan disable
5720 13:58:51.681906 == TX Byte 0 ==
5721 13:58:51.688964 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5722 13:58:51.691675 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5723 13:58:51.691749 == TX Byte 1 ==
5724 13:58:51.699015 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5725 13:58:51.701894 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5726 13:58:51.701961
5727 13:58:51.702027 [DATLAT]
5728 13:58:51.705250 Freq=933, CH1 RK0
5729 13:58:51.705342
5730 13:58:51.705428 DATLAT Default: 0xd
5731 13:58:51.708772 0, 0xFFFF, sum = 0
5732 13:58:51.708866 1, 0xFFFF, sum = 0
5733 13:58:51.712014 2, 0xFFFF, sum = 0
5734 13:58:51.712081 3, 0xFFFF, sum = 0
5735 13:58:51.715190 4, 0xFFFF, sum = 0
5736 13:58:51.718550 5, 0xFFFF, sum = 0
5737 13:58:51.718672 6, 0xFFFF, sum = 0
5738 13:58:51.721383 7, 0xFFFF, sum = 0
5739 13:58:51.721477 8, 0xFFFF, sum = 0
5740 13:58:51.724772 9, 0xFFFF, sum = 0
5741 13:58:51.724840 10, 0x0, sum = 1
5742 13:58:51.728157 11, 0x0, sum = 2
5743 13:58:51.728226 12, 0x0, sum = 3
5744 13:58:51.731377 13, 0x0, sum = 4
5745 13:58:51.731453 best_step = 11
5746 13:58:51.731514
5747 13:58:51.731571 ==
5748 13:58:51.734826 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 13:58:51.738323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 13:58:51.738423 ==
5751 13:58:51.741477 RX Vref Scan: 1
5752 13:58:51.741570
5753 13:58:51.744603 RX Vref 0 -> 0, step: 1
5754 13:58:51.744697
5755 13:58:51.744783 RX Delay -69 -> 252, step: 4
5756 13:58:51.744870
5757 13:58:51.747942 Set Vref, RX VrefLevel [Byte0]: 48
5758 13:58:51.751583 [Byte1]: 53
5759 13:58:51.756207
5760 13:58:51.756303 Final RX Vref Byte 0 = 48 to rank0
5761 13:58:51.759334 Final RX Vref Byte 1 = 53 to rank0
5762 13:58:51.762366 Final RX Vref Byte 0 = 48 to rank1
5763 13:58:51.765724 Final RX Vref Byte 1 = 53 to rank1==
5764 13:58:51.769188 Dram Type= 6, Freq= 0, CH_1, rank 0
5765 13:58:51.776697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 13:58:51.776780 ==
5767 13:58:51.776845 DQS Delay:
5768 13:58:51.779084 DQS0 = 0, DQS1 = 0
5769 13:58:51.779156 DQM Delay:
5770 13:58:51.779216 DQM0 = 101, DQM1 = 93
5771 13:58:51.782742 DQ Delay:
5772 13:58:51.785537 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5773 13:58:51.789819 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5774 13:58:51.792235 DQ8 =80, DQ9 =84, DQ10 =96, DQ11 =86
5775 13:58:51.796049 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =104
5776 13:58:51.796121
5777 13:58:51.796182
5778 13:58:51.802952 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5779 13:58:51.805557 CH1 RK0: MR19=505, MR18=1D0D
5780 13:58:51.811870 CH1_RK0: MR19=0x505, MR18=0x1D0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5781 13:58:51.811940
5782 13:58:51.815445 ----->DramcWriteLeveling(PI) begin...
5783 13:58:51.815515 ==
5784 13:58:51.818554 Dram Type= 6, Freq= 0, CH_1, rank 1
5785 13:58:51.822468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5786 13:58:51.822561 ==
5787 13:58:51.825461 Write leveling (Byte 0): 26 => 26
5788 13:58:51.828750 Write leveling (Byte 1): 27 => 27
5789 13:58:51.831860 DramcWriteLeveling(PI) end<-----
5790 13:58:51.831936
5791 13:58:51.831998 ==
5792 13:58:51.835498 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 13:58:51.841604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 13:58:51.841703 ==
5795 13:58:51.841769 [Gating] SW mode calibration
5796 13:58:51.851564 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5797 13:58:51.854960 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5798 13:58:51.862340 0 14 0 | B1->B0 | 3434 3332 | 1 1 | (1 1) (0 0)
5799 13:58:51.865300 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 13:58:51.868203 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 13:58:51.874894 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 13:58:51.878678 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 13:58:51.881254 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 13:58:51.888337 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5805 13:58:51.891844 0 14 28 | B1->B0 | 2b2b 3030 | 1 0 | (1 0) (0 1)
5806 13:58:51.894916 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 13:58:51.901087 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 13:58:51.905696 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 13:58:51.908101 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 13:58:51.914463 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 13:58:51.917663 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 13:58:51.920652 0 15 24 | B1->B0 | 2c2c 2525 | 0 0 | (0 0) (0 0)
5813 13:58:51.927456 0 15 28 | B1->B0 | 3d3d 3939 | 0 0 | (0 0) (0 0)
5814 13:58:51.930828 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5815 13:58:51.933990 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 13:58:51.941459 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 13:58:51.944091 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 13:58:51.947486 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 13:58:51.954026 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 13:58:51.957616 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5821 13:58:51.960579 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5822 13:58:51.967207 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 13:58:51.970665 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 13:58:51.974557 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 13:58:51.977184 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 13:58:51.983587 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 13:58:51.987076 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 13:58:51.990388 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 13:58:51.997023 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 13:58:52.000292 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 13:58:52.003341 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 13:58:52.010131 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 13:58:52.013750 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 13:58:52.020003 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 13:58:52.023277 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 13:58:52.026926 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 13:58:52.033035 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 13:58:52.033119 Total UI for P1: 0, mck2ui 16
5839 13:58:52.036686 best dqsien dly found for B0: ( 1, 2, 26)
5840 13:58:52.039575 Total UI for P1: 0, mck2ui 16
5841 13:58:52.042875 best dqsien dly found for B1: ( 1, 2, 26)
5842 13:58:52.049422 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5843 13:58:52.052980 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5844 13:58:52.053078
5845 13:58:52.056057 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5846 13:58:52.059373 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5847 13:58:52.062792 [Gating] SW calibration Done
5848 13:58:52.062874 ==
5849 13:58:52.066095 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 13:58:52.069376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 13:58:52.069449 ==
5852 13:58:52.072650 RX Vref Scan: 0
5853 13:58:52.072752
5854 13:58:52.072841 RX Vref 0 -> 0, step: 1
5855 13:58:52.072938
5856 13:58:52.076124 RX Delay -80 -> 252, step: 8
5857 13:58:52.079262 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5858 13:58:52.086120 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5859 13:58:52.089376 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5860 13:58:52.092724 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5861 13:58:52.095863 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5862 13:58:52.098957 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5863 13:58:52.102207 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5864 13:58:52.109473 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5865 13:58:52.112677 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5866 13:58:52.115758 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5867 13:58:52.118950 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5868 13:58:52.122698 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5869 13:58:52.129515 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5870 13:58:52.132372 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5871 13:58:52.135601 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5872 13:58:52.138770 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5873 13:58:52.138846 ==
5874 13:58:52.141835 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 13:58:52.144994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 13:58:52.149090 ==
5877 13:58:52.149191 DQS Delay:
5878 13:58:52.149281 DQS0 = 0, DQS1 = 0
5879 13:58:52.151778 DQM Delay:
5880 13:58:52.151845 DQM0 = 100, DQM1 = 90
5881 13:58:52.155429 DQ Delay:
5882 13:58:52.158831 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5883 13:58:52.161560 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5884 13:58:52.165122 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5885 13:58:52.168563 DQ12 =103, DQ13 =99, DQ14 =95, DQ15 =103
5886 13:58:52.168635
5887 13:58:52.168696
5888 13:58:52.168753 ==
5889 13:58:52.171471 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 13:58:52.175126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 13:58:52.175206 ==
5892 13:58:52.175268
5893 13:58:52.175331
5894 13:58:52.178759 TX Vref Scan disable
5895 13:58:52.178828 == TX Byte 0 ==
5896 13:58:52.185050 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5897 13:58:52.188642 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5898 13:58:52.191593 == TX Byte 1 ==
5899 13:58:52.194949 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5900 13:58:52.198365 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5901 13:58:52.198461 ==
5902 13:58:52.201315 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 13:58:52.204542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 13:58:52.207566 ==
5905 13:58:52.207632
5906 13:58:52.207691
5907 13:58:52.207753 TX Vref Scan disable
5908 13:58:52.211446 == TX Byte 0 ==
5909 13:58:52.214870 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5910 13:58:52.218137 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5911 13:58:52.221361 == TX Byte 1 ==
5912 13:58:52.225030 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5913 13:58:52.228487 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5914 13:58:52.231539
5915 13:58:52.231632 [DATLAT]
5916 13:58:52.231727 Freq=933, CH1 RK1
5917 13:58:52.231813
5918 13:58:52.235661 DATLAT Default: 0xb
5919 13:58:52.235733 0, 0xFFFF, sum = 0
5920 13:58:52.238115 1, 0xFFFF, sum = 0
5921 13:58:52.238185 2, 0xFFFF, sum = 0
5922 13:58:52.241148 3, 0xFFFF, sum = 0
5923 13:58:52.244862 4, 0xFFFF, sum = 0
5924 13:58:52.244962 5, 0xFFFF, sum = 0
5925 13:58:52.248213 6, 0xFFFF, sum = 0
5926 13:58:52.248282 7, 0xFFFF, sum = 0
5927 13:58:52.251410 8, 0xFFFF, sum = 0
5928 13:58:52.251477 9, 0xFFFF, sum = 0
5929 13:58:52.254586 10, 0x0, sum = 1
5930 13:58:52.254683 11, 0x0, sum = 2
5931 13:58:52.257696 12, 0x0, sum = 3
5932 13:58:52.257772 13, 0x0, sum = 4
5933 13:58:52.257835 best_step = 11
5934 13:58:52.257900
5935 13:58:52.261143 ==
5936 13:58:52.264432 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 13:58:52.267766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 13:58:52.267835 ==
5939 13:58:52.267902 RX Vref Scan: 0
5940 13:58:52.267962
5941 13:58:52.271962 RX Vref 0 -> 0, step: 1
5942 13:58:52.272027
5943 13:58:52.274703 RX Delay -69 -> 252, step: 4
5944 13:58:52.281040 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5945 13:58:52.284712 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
5946 13:58:52.287687 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
5947 13:58:52.291190 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5948 13:58:52.294887 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5949 13:58:52.298003 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5950 13:58:52.304588 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5951 13:58:52.307295 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5952 13:58:52.310663 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5953 13:58:52.314050 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
5954 13:58:52.317284 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
5955 13:58:52.323893 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5956 13:58:52.327506 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5957 13:58:52.330397 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
5958 13:58:52.333836 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5959 13:58:52.337039 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5960 13:58:52.340904 ==
5961 13:58:52.343655 Dram Type= 6, Freq= 0, CH_1, rank 1
5962 13:58:52.347518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5963 13:58:52.347596 ==
5964 13:58:52.347658 DQS Delay:
5965 13:58:52.350394 DQS0 = 0, DQS1 = 0
5966 13:58:52.350485 DQM Delay:
5967 13:58:52.353746 DQM0 = 101, DQM1 = 93
5968 13:58:52.353820 DQ Delay:
5969 13:58:52.357230 DQ0 =106, DQ1 =96, DQ2 =88, DQ3 =98
5970 13:58:52.360027 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =98
5971 13:58:52.363807 DQ8 =82, DQ9 =82, DQ10 =92, DQ11 =84
5972 13:58:52.367328 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5973 13:58:52.367399
5974 13:58:52.367459
5975 13:58:52.376909 [DQSOSCAuto] RK1, (LSB)MR18= 0x802, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5976 13:58:52.377016 CH1 RK1: MR19=505, MR18=802
5977 13:58:52.383518 CH1_RK1: MR19=0x505, MR18=0x802, DQSOSC=419, MR23=63, INC=61, DEC=41
5978 13:58:52.387243 [RxdqsGatingPostProcess] freq 933
5979 13:58:52.393946 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5980 13:58:52.396765 best DQS0 dly(2T, 0.5T) = (0, 10)
5981 13:58:52.399957 best DQS1 dly(2T, 0.5T) = (0, 10)
5982 13:58:52.403811 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5983 13:58:52.406743 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5984 13:58:52.406833 best DQS0 dly(2T, 0.5T) = (0, 10)
5985 13:58:52.410487 best DQS1 dly(2T, 0.5T) = (0, 10)
5986 13:58:52.413367 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5987 13:58:52.417129 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5988 13:58:52.420510 Pre-setting of DQS Precalculation
5989 13:58:52.426433 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5990 13:58:52.433518 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5991 13:58:52.440360 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5992 13:58:52.440460
5993 13:58:52.440549
5994 13:58:52.443179 [Calibration Summary] 1866 Mbps
5995 13:58:52.443250 CH 0, Rank 0
5996 13:58:52.446168 SW Impedance : PASS
5997 13:58:52.449904 DUTY Scan : NO K
5998 13:58:52.449976 ZQ Calibration : PASS
5999 13:58:52.453008 Jitter Meter : NO K
6000 13:58:52.456171 CBT Training : PASS
6001 13:58:52.456266 Write leveling : PASS
6002 13:58:52.459474 RX DQS gating : PASS
6003 13:58:52.463199 RX DQ/DQS(RDDQC) : PASS
6004 13:58:52.463270 TX DQ/DQS : PASS
6005 13:58:52.466205 RX DATLAT : PASS
6006 13:58:52.469601 RX DQ/DQS(Engine): PASS
6007 13:58:52.469701 TX OE : NO K
6008 13:58:52.472941 All Pass.
6009 13:58:52.473013
6010 13:58:52.473073 CH 0, Rank 1
6011 13:58:52.476350 SW Impedance : PASS
6012 13:58:52.476453 DUTY Scan : NO K
6013 13:58:52.479334 ZQ Calibration : PASS
6014 13:58:52.483109 Jitter Meter : NO K
6015 13:58:52.483183 CBT Training : PASS
6016 13:58:52.486201 Write leveling : PASS
6017 13:58:52.489223 RX DQS gating : PASS
6018 13:58:52.489298 RX DQ/DQS(RDDQC) : PASS
6019 13:58:52.492326 TX DQ/DQS : PASS
6020 13:58:52.496373 RX DATLAT : PASS
6021 13:58:52.496470 RX DQ/DQS(Engine): PASS
6022 13:58:52.499166 TX OE : NO K
6023 13:58:52.499240 All Pass.
6024 13:58:52.499301
6025 13:58:52.502877 CH 1, Rank 0
6026 13:58:52.502980 SW Impedance : PASS
6027 13:58:52.505921 DUTY Scan : NO K
6028 13:58:52.506002 ZQ Calibration : PASS
6029 13:58:52.509016 Jitter Meter : NO K
6030 13:58:52.512794 CBT Training : PASS
6031 13:58:52.512866 Write leveling : PASS
6032 13:58:52.516492 RX DQS gating : PASS
6033 13:58:52.518825 RX DQ/DQS(RDDQC) : PASS
6034 13:58:52.518911 TX DQ/DQS : PASS
6035 13:58:52.522296 RX DATLAT : PASS
6036 13:58:52.525591 RX DQ/DQS(Engine): PASS
6037 13:58:52.525688 TX OE : NO K
6038 13:58:52.528993 All Pass.
6039 13:58:52.529064
6040 13:58:52.529123 CH 1, Rank 1
6041 13:58:52.532230 SW Impedance : PASS
6042 13:58:52.532327 DUTY Scan : NO K
6043 13:58:52.536417 ZQ Calibration : PASS
6044 13:58:52.538559 Jitter Meter : NO K
6045 13:58:52.538677 CBT Training : PASS
6046 13:58:52.542200 Write leveling : PASS
6047 13:58:52.545341 RX DQS gating : PASS
6048 13:58:52.545437 RX DQ/DQS(RDDQC) : PASS
6049 13:58:52.548448 TX DQ/DQS : PASS
6050 13:58:52.551950 RX DATLAT : PASS
6051 13:58:52.552019 RX DQ/DQS(Engine): PASS
6052 13:58:52.555081 TX OE : NO K
6053 13:58:52.555175 All Pass.
6054 13:58:52.555262
6055 13:58:52.558563 DramC Write-DBI off
6056 13:58:52.561645 PER_BANK_REFRESH: Hybrid Mode
6057 13:58:52.561742 TX_TRACKING: ON
6058 13:58:52.571987 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6059 13:58:52.575261 [FAST_K] Save calibration result to emmc
6060 13:58:52.578125 dramc_set_vcore_voltage set vcore to 650000
6061 13:58:52.582131 Read voltage for 400, 6
6062 13:58:52.582241 Vio18 = 0
6063 13:58:52.582333 Vcore = 650000
6064 13:58:52.584849 Vdram = 0
6065 13:58:52.584953 Vddq = 0
6066 13:58:52.585045 Vmddr = 0
6067 13:58:52.591691 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6068 13:58:52.594650 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6069 13:58:52.598109 MEM_TYPE=3, freq_sel=20
6070 13:58:52.601261 sv_algorithm_assistance_LP4_800
6071 13:58:52.604646 ============ PULL DRAM RESETB DOWN ============
6072 13:58:52.607997 ========== PULL DRAM RESETB DOWN end =========
6073 13:58:52.614774 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6074 13:58:52.618021 ===================================
6075 13:58:52.621231 LPDDR4 DRAM CONFIGURATION
6076 13:58:52.624473 ===================================
6077 13:58:52.624581 EX_ROW_EN[0] = 0x0
6078 13:58:52.627789 EX_ROW_EN[1] = 0x0
6079 13:58:52.627876 LP4Y_EN = 0x0
6080 13:58:52.631132 WORK_FSP = 0x0
6081 13:58:52.631229 WL = 0x2
6082 13:58:52.634954 RL = 0x2
6083 13:58:52.635029 BL = 0x2
6084 13:58:52.637948 RPST = 0x0
6085 13:58:52.638045 RD_PRE = 0x0
6086 13:58:52.640959 WR_PRE = 0x1
6087 13:58:52.641068 WR_PST = 0x0
6088 13:58:52.644242 DBI_WR = 0x0
6089 13:58:52.644344 DBI_RD = 0x0
6090 13:58:52.647810 OTF = 0x1
6091 13:58:52.651258 ===================================
6092 13:58:52.654164 ===================================
6093 13:58:52.654261 ANA top config
6094 13:58:52.657742 ===================================
6095 13:58:52.660631 DLL_ASYNC_EN = 0
6096 13:58:52.664406 ALL_SLAVE_EN = 1
6097 13:58:52.667338 NEW_RANK_MODE = 1
6098 13:58:52.671172 DLL_IDLE_MODE = 1
6099 13:58:52.671272 LP45_APHY_COMB_EN = 1
6100 13:58:52.673980 TX_ODT_DIS = 1
6101 13:58:52.677107 NEW_8X_MODE = 1
6102 13:58:52.680708 ===================================
6103 13:58:52.683776 ===================================
6104 13:58:52.687033 data_rate = 800
6105 13:58:52.690755 CKR = 1
6106 13:58:52.690833 DQ_P2S_RATIO = 4
6107 13:58:52.693828 ===================================
6108 13:58:52.696862 CA_P2S_RATIO = 4
6109 13:58:52.700249 DQ_CA_OPEN = 0
6110 13:58:52.703509 DQ_SEMI_OPEN = 1
6111 13:58:52.707079 CA_SEMI_OPEN = 1
6112 13:58:52.710086 CA_FULL_RATE = 0
6113 13:58:52.710154 DQ_CKDIV4_EN = 0
6114 13:58:52.713700 CA_CKDIV4_EN = 1
6115 13:58:52.716726 CA_PREDIV_EN = 0
6116 13:58:52.719916 PH8_DLY = 0
6117 13:58:52.723462 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6118 13:58:52.727791 DQ_AAMCK_DIV = 0
6119 13:58:52.730302 CA_AAMCK_DIV = 0
6120 13:58:52.730371 CA_ADMCK_DIV = 4
6121 13:58:52.733563 DQ_TRACK_CA_EN = 0
6122 13:58:52.736622 CA_PICK = 800
6123 13:58:52.739803 CA_MCKIO = 400
6124 13:58:52.743392 MCKIO_SEMI = 400
6125 13:58:52.746359 PLL_FREQ = 3016
6126 13:58:52.750133 DQ_UI_PI_RATIO = 32
6127 13:58:52.750204 CA_UI_PI_RATIO = 32
6128 13:58:52.753012 ===================================
6129 13:58:52.756151 ===================================
6130 13:58:52.759625 memory_type:LPDDR4
6131 13:58:52.763073 GP_NUM : 10
6132 13:58:52.763144 SRAM_EN : 1
6133 13:58:52.767185 MD32_EN : 0
6134 13:58:52.769651 ===================================
6135 13:58:52.773026 [ANA_INIT] >>>>>>>>>>>>>>
6136 13:58:52.776227 <<<<<< [CONFIGURE PHASE]: ANA_TX
6137 13:58:52.779453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6138 13:58:52.782984 ===================================
6139 13:58:52.783069 data_rate = 800,PCW = 0X7400
6140 13:58:52.785937 ===================================
6141 13:58:52.789381 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6142 13:58:52.796139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6143 13:58:52.809220 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 13:58:52.812859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6145 13:58:52.815921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6146 13:58:52.819308 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6147 13:58:52.822476 [ANA_INIT] flow start
6148 13:58:52.822576 [ANA_INIT] PLL >>>>>>>>
6149 13:58:52.825545 [ANA_INIT] PLL <<<<<<<<
6150 13:58:52.829290 [ANA_INIT] MIDPI >>>>>>>>
6151 13:58:52.832598 [ANA_INIT] MIDPI <<<<<<<<
6152 13:58:52.832695 [ANA_INIT] DLL >>>>>>>>
6153 13:58:52.835571 [ANA_INIT] flow end
6154 13:58:52.838996 ============ LP4 DIFF to SE enter ============
6155 13:58:52.842447 ============ LP4 DIFF to SE exit ============
6156 13:58:52.845575 [ANA_INIT] <<<<<<<<<<<<<
6157 13:58:52.849084 [Flow] Enable top DCM control >>>>>
6158 13:58:52.852404 [Flow] Enable top DCM control <<<<<
6159 13:58:52.855784 Enable DLL master slave shuffle
6160 13:58:52.861791 ==============================================================
6161 13:58:52.861867 Gating Mode config
6162 13:58:52.868478 ==============================================================
6163 13:58:52.868552 Config description:
6164 13:58:52.878526 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6165 13:58:52.885509 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6166 13:58:52.892155 SELPH_MODE 0: By rank 1: By Phase
6167 13:58:52.895228 ==============================================================
6168 13:58:52.898481 GAT_TRACK_EN = 0
6169 13:58:52.902200 RX_GATING_MODE = 2
6170 13:58:52.905192 RX_GATING_TRACK_MODE = 2
6171 13:58:52.908098 SELPH_MODE = 1
6172 13:58:52.912080 PICG_EARLY_EN = 1
6173 13:58:52.914867 VALID_LAT_VALUE = 1
6174 13:58:52.921747 ==============================================================
6175 13:58:52.924733 Enter into Gating configuration >>>>
6176 13:58:52.928468 Exit from Gating configuration <<<<
6177 13:58:52.931326 Enter into DVFS_PRE_config >>>>>
6178 13:58:52.941594 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6179 13:58:52.944741 Exit from DVFS_PRE_config <<<<<
6180 13:58:52.948651 Enter into PICG configuration >>>>
6181 13:58:52.952214 Exit from PICG configuration <<<<
6182 13:58:52.954439 [RX_INPUT] configuration >>>>>
6183 13:58:52.954537 [RX_INPUT] configuration <<<<<
6184 13:58:52.961203 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6185 13:58:52.967917 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6186 13:58:52.971111 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 13:58:52.977750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 13:58:52.984249 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6189 13:58:52.991279 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6190 13:58:52.994371 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6191 13:58:52.997531 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6192 13:58:53.004248 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6193 13:58:53.007551 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6194 13:58:53.010875 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6195 13:58:53.017409 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6196 13:58:53.020400 ===================================
6197 13:58:53.020473 LPDDR4 DRAM CONFIGURATION
6198 13:58:53.023770 ===================================
6199 13:58:53.027133 EX_ROW_EN[0] = 0x0
6200 13:58:53.030764 EX_ROW_EN[1] = 0x0
6201 13:58:53.030835 LP4Y_EN = 0x0
6202 13:58:53.033989 WORK_FSP = 0x0
6203 13:58:53.034085 WL = 0x2
6204 13:58:53.037134 RL = 0x2
6205 13:58:53.037232 BL = 0x2
6206 13:58:53.040146 RPST = 0x0
6207 13:58:53.040242 RD_PRE = 0x0
6208 13:58:53.043345 WR_PRE = 0x1
6209 13:58:53.043416 WR_PST = 0x0
6210 13:58:53.047094 DBI_WR = 0x0
6211 13:58:53.047168 DBI_RD = 0x0
6212 13:58:53.050317 OTF = 0x1
6213 13:58:53.053277 ===================================
6214 13:58:53.056765 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6215 13:58:53.060132 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6216 13:58:53.067133 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6217 13:58:53.070086 ===================================
6218 13:58:53.070187 LPDDR4 DRAM CONFIGURATION
6219 13:58:53.073696 ===================================
6220 13:58:53.076466 EX_ROW_EN[0] = 0x10
6221 13:58:53.080356 EX_ROW_EN[1] = 0x0
6222 13:58:53.080432 LP4Y_EN = 0x0
6223 13:58:53.083111 WORK_FSP = 0x0
6224 13:58:53.083182 WL = 0x2
6225 13:58:53.086217 RL = 0x2
6226 13:58:53.086290 BL = 0x2
6227 13:58:53.090462 RPST = 0x0
6228 13:58:53.090533 RD_PRE = 0x0
6229 13:58:53.092946 WR_PRE = 0x1
6230 13:58:53.093016 WR_PST = 0x0
6231 13:58:53.096329 DBI_WR = 0x0
6232 13:58:53.096404 DBI_RD = 0x0
6233 13:58:53.099890 OTF = 0x1
6234 13:58:53.103418 ===================================
6235 13:58:53.109739 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6236 13:58:53.112919 nWR fixed to 30
6237 13:58:53.112996 [ModeRegInit_LP4] CH0 RK0
6238 13:58:53.116255 [ModeRegInit_LP4] CH0 RK1
6239 13:58:53.120006 [ModeRegInit_LP4] CH1 RK0
6240 13:58:53.122903 [ModeRegInit_LP4] CH1 RK1
6241 13:58:53.122974 match AC timing 19
6242 13:58:53.129196 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6243 13:58:53.132921 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6244 13:58:53.135990 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6245 13:58:53.142667 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6246 13:58:53.146808 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6247 13:58:53.146881 ==
6248 13:58:53.149146 Dram Type= 6, Freq= 0, CH_0, rank 0
6249 13:58:53.152535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 13:58:53.152636 ==
6251 13:58:53.159066 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 13:58:53.166356 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6253 13:58:53.169413 [CA 0] Center 36 (8~64) winsize 57
6254 13:58:53.172629 [CA 1] Center 36 (8~64) winsize 57
6255 13:58:53.172702 [CA 2] Center 36 (8~64) winsize 57
6256 13:58:53.175887 [CA 3] Center 36 (8~64) winsize 57
6257 13:58:53.179425 [CA 4] Center 36 (8~64) winsize 57
6258 13:58:53.182342 [CA 5] Center 36 (8~64) winsize 57
6259 13:58:53.182423
6260 13:58:53.185853 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6261 13:58:53.188859
6262 13:58:53.192883 [CATrainingPosCal] consider 1 rank data
6263 13:58:53.192983 u2DelayCellTimex100 = 270/100 ps
6264 13:58:53.198892 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 13:58:53.202132 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 13:58:53.205596 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 13:58:53.208994 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 13:58:53.212616 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 13:58:53.215211 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 13:58:53.215283
6271 13:58:53.218540 CA PerBit enable=1, Macro0, CA PI delay=36
6272 13:58:53.218666
6273 13:58:53.221826 [CBTSetCACLKResult] CA Dly = 36
6274 13:58:53.225343 CS Dly: 1 (0~32)
6275 13:58:53.225440 ==
6276 13:58:53.228606 Dram Type= 6, Freq= 0, CH_0, rank 1
6277 13:58:53.231822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 13:58:53.231922 ==
6279 13:58:53.238522 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 13:58:53.242200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6281 13:58:53.244857 [CA 0] Center 36 (8~64) winsize 57
6282 13:58:53.248206 [CA 1] Center 36 (8~64) winsize 57
6283 13:58:53.251870 [CA 2] Center 36 (8~64) winsize 57
6284 13:58:53.255268 [CA 3] Center 36 (8~64) winsize 57
6285 13:58:53.258627 [CA 4] Center 36 (8~64) winsize 57
6286 13:58:53.261695 [CA 5] Center 36 (8~64) winsize 57
6287 13:58:53.261769
6288 13:58:53.265039 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6289 13:58:53.265111
6290 13:58:53.268058 [CATrainingPosCal] consider 2 rank data
6291 13:58:53.272242 u2DelayCellTimex100 = 270/100 ps
6292 13:58:53.275517 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 13:58:53.281185 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 13:58:53.284742 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 13:58:53.287935 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 13:58:53.292059 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 13:58:53.295007 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 13:58:53.295097
6299 13:58:53.298055 CA PerBit enable=1, Macro0, CA PI delay=36
6300 13:58:53.298142
6301 13:58:53.301372 [CBTSetCACLKResult] CA Dly = 36
6302 13:58:53.301450 CS Dly: 1 (0~32)
6303 13:58:53.305267
6304 13:58:53.307687 ----->DramcWriteLeveling(PI) begin...
6305 13:58:53.307760 ==
6306 13:58:53.311074 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 13:58:53.314186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 13:58:53.314284 ==
6309 13:58:53.317652 Write leveling (Byte 0): 40 => 8
6310 13:58:53.321468 Write leveling (Byte 1): 32 => 0
6311 13:58:53.324456 DramcWriteLeveling(PI) end<-----
6312 13:58:53.324528
6313 13:58:53.324588 ==
6314 13:58:53.327816 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 13:58:53.330744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 13:58:53.330816 ==
6317 13:58:53.334340 [Gating] SW mode calibration
6318 13:58:53.341261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6319 13:58:53.347590 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6320 13:58:53.350715 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6321 13:58:53.354425 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 13:58:53.360510 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 13:58:53.363992 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 13:58:53.367145 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 13:58:53.373506 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 13:58:53.377141 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 13:58:53.380674 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 13:58:53.387029 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 13:58:53.387104 Total UI for P1: 0, mck2ui 16
6330 13:58:53.393683 best dqsien dly found for B0: ( 0, 14, 24)
6331 13:58:53.393771 Total UI for P1: 0, mck2ui 16
6332 13:58:53.400024 best dqsien dly found for B1: ( 0, 14, 24)
6333 13:58:53.403455 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6334 13:58:53.406898 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6335 13:58:53.406978
6336 13:58:53.410247 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6337 13:58:53.413217 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 13:58:53.416402 [Gating] SW calibration Done
6339 13:58:53.416483 ==
6340 13:58:53.420544 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 13:58:53.423423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 13:58:53.423504 ==
6343 13:58:53.426312 RX Vref Scan: 0
6344 13:58:53.426392
6345 13:58:53.426455 RX Vref 0 -> 0, step: 1
6346 13:58:53.429506
6347 13:58:53.429587 RX Delay -410 -> 252, step: 16
6348 13:58:53.436194 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6349 13:58:53.439374 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6350 13:58:53.442610 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6351 13:58:53.449583 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6352 13:58:53.452519 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6353 13:58:53.456410 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6354 13:58:53.459429 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6355 13:58:53.465674 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6356 13:58:53.469574 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6357 13:58:53.472283 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6358 13:58:53.475669 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6359 13:58:53.482461 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6360 13:58:53.485891 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6361 13:58:53.488901 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6362 13:58:53.492488 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6363 13:58:53.498953 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6364 13:58:53.499026 ==
6365 13:58:53.501878 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 13:58:53.505765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 13:58:53.505835 ==
6368 13:58:53.505895 DQS Delay:
6369 13:58:53.508841 DQS0 = 43, DQS1 = 59
6370 13:58:53.508932 DQM Delay:
6371 13:58:53.512133 DQM0 = 10, DQM1 = 12
6372 13:58:53.512197 DQ Delay:
6373 13:58:53.515132 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6374 13:58:53.518736 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6375 13:58:53.522052 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6376 13:58:53.525181 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6377 13:58:53.525275
6378 13:58:53.525363
6379 13:58:53.525447 ==
6380 13:58:53.528298 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 13:58:53.531784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 13:58:53.534687 ==
6383 13:58:53.534761
6384 13:58:53.534822
6385 13:58:53.534879 TX Vref Scan disable
6386 13:58:53.538387 == TX Byte 0 ==
6387 13:58:53.542222 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 13:58:53.544621 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 13:58:53.548064 == TX Byte 1 ==
6390 13:58:53.551477 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6391 13:58:53.554413 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6392 13:58:53.554477 ==
6393 13:58:53.557844 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 13:58:53.564464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 13:58:53.564538 ==
6396 13:58:53.564600
6397 13:58:53.564658
6398 13:58:53.564717 TX Vref Scan disable
6399 13:58:53.567845 == TX Byte 0 ==
6400 13:58:53.571184 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 13:58:53.574387 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 13:58:53.577896 == TX Byte 1 ==
6403 13:58:53.580997 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6404 13:58:53.584443 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6405 13:58:53.584541
6406 13:58:53.587686 [DATLAT]
6407 13:58:53.587753 Freq=400, CH0 RK0
6408 13:58:53.587813
6409 13:58:53.590932 DATLAT Default: 0xf
6410 13:58:53.590996 0, 0xFFFF, sum = 0
6411 13:58:53.594772 1, 0xFFFF, sum = 0
6412 13:58:53.594842 2, 0xFFFF, sum = 0
6413 13:58:53.597655 3, 0xFFFF, sum = 0
6414 13:58:53.597749 4, 0xFFFF, sum = 0
6415 13:58:53.600994 5, 0xFFFF, sum = 0
6416 13:58:53.604149 6, 0xFFFF, sum = 0
6417 13:58:53.604220 7, 0xFFFF, sum = 0
6418 13:58:53.607647 8, 0xFFFF, sum = 0
6419 13:58:53.607721 9, 0xFFFF, sum = 0
6420 13:58:53.611256 10, 0xFFFF, sum = 0
6421 13:58:53.611324 11, 0xFFFF, sum = 0
6422 13:58:53.613864 12, 0xFFFF, sum = 0
6423 13:58:53.613952 13, 0x0, sum = 1
6424 13:58:53.617614 14, 0x0, sum = 2
6425 13:58:53.617696 15, 0x0, sum = 3
6426 13:58:53.620888 16, 0x0, sum = 4
6427 13:58:53.620970 best_step = 14
6428 13:58:53.621033
6429 13:58:53.621092 ==
6430 13:58:53.623898 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 13:58:53.627168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 13:58:53.630326 ==
6433 13:58:53.630406 RX Vref Scan: 1
6434 13:58:53.630469
6435 13:58:53.634475 RX Vref 0 -> 0, step: 1
6436 13:58:53.634555
6437 13:58:53.637673 RX Delay -359 -> 252, step: 8
6438 13:58:53.637753
6439 13:58:53.640395 Set Vref, RX VrefLevel [Byte0]: 63
6440 13:58:53.644108 [Byte1]: 55
6441 13:58:53.644189
6442 13:58:53.647130 Final RX Vref Byte 0 = 63 to rank0
6443 13:58:53.650267 Final RX Vref Byte 1 = 55 to rank0
6444 13:58:53.653838 Final RX Vref Byte 0 = 63 to rank1
6445 13:58:53.656983 Final RX Vref Byte 1 = 55 to rank1==
6446 13:58:53.660131 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 13:58:53.663349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 13:58:53.663430 ==
6449 13:58:53.666643 DQS Delay:
6450 13:58:53.666766 DQS0 = 48, DQS1 = 60
6451 13:58:53.670564 DQM Delay:
6452 13:58:53.670683 DQM0 = 12, DQM1 = 11
6453 13:58:53.673381 DQ Delay:
6454 13:58:53.673461 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6455 13:58:53.676559 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6456 13:58:53.680457 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6457 13:58:53.683383 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6458 13:58:53.683463
6459 13:58:53.683526
6460 13:58:53.693164 [DQSOSCAuto] RK0, (LSB)MR18= 0xc98b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 384 ps
6461 13:58:53.696516 CH0 RK0: MR19=C0C, MR18=C98B
6462 13:58:53.703199 CH0_RK0: MR19=0xC0C, MR18=0xC98B, DQSOSC=384, MR23=63, INC=400, DEC=267
6463 13:58:53.703280 ==
6464 13:58:53.706634 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 13:58:53.709656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 13:58:53.709736 ==
6467 13:58:53.712943 [Gating] SW mode calibration
6468 13:58:53.719799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6469 13:58:53.726154 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6470 13:58:53.729282 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6471 13:58:53.732893 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 13:58:53.739577 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 13:58:53.742840 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 13:58:53.746034 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 13:58:53.749260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 13:58:53.755778 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 13:58:53.759171 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 13:58:53.762514 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 13:58:53.765806 Total UI for P1: 0, mck2ui 16
6480 13:58:53.769094 best dqsien dly found for B0: ( 0, 14, 24)
6481 13:58:53.772699 Total UI for P1: 0, mck2ui 16
6482 13:58:53.775729 best dqsien dly found for B1: ( 0, 14, 24)
6483 13:58:53.779262 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6484 13:58:53.785834 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6485 13:58:53.785907
6486 13:58:53.788977 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6487 13:58:53.792451 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 13:58:53.795815 [Gating] SW calibration Done
6489 13:58:53.795895 ==
6490 13:58:53.799282 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 13:58:53.802022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 13:58:53.802091 ==
6493 13:58:53.805855 RX Vref Scan: 0
6494 13:58:53.805928
6495 13:58:53.805989 RX Vref 0 -> 0, step: 1
6496 13:58:53.806051
6497 13:58:53.808519 RX Delay -410 -> 252, step: 16
6498 13:58:53.815670 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6499 13:58:53.818451 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6500 13:58:53.822077 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6501 13:58:53.825295 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6502 13:58:53.831539 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6503 13:58:53.835318 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6504 13:58:53.838974 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6505 13:58:53.841500 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6506 13:58:53.848246 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6507 13:58:53.851638 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6508 13:58:53.854970 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6509 13:58:53.859069 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6510 13:58:53.864603 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6511 13:58:53.868537 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6512 13:58:53.871315 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6513 13:58:53.874814 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6514 13:58:53.877816 ==
6515 13:58:53.881047 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 13:58:53.884250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 13:58:53.884351 ==
6518 13:58:53.884441 DQS Delay:
6519 13:58:53.887676 DQS0 = 43, DQS1 = 59
6520 13:58:53.887769 DQM Delay:
6521 13:58:53.890968 DQM0 = 11, DQM1 = 16
6522 13:58:53.891043 DQ Delay:
6523 13:58:53.894414 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6524 13:58:53.897835 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6525 13:58:53.900946 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6526 13:58:53.903949 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6527 13:58:53.904021
6528 13:58:53.904081
6529 13:58:53.904137 ==
6530 13:58:53.907260 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 13:58:53.910585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 13:58:53.910662 ==
6533 13:58:53.910721
6534 13:58:53.910777
6535 13:58:53.914171 TX Vref Scan disable
6536 13:58:53.914263 == TX Byte 0 ==
6537 13:58:53.920839 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6538 13:58:53.923953 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6539 13:58:53.924023 == TX Byte 1 ==
6540 13:58:53.930587 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6541 13:58:53.933814 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6542 13:58:53.933886 ==
6543 13:58:53.937344 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 13:58:53.940497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 13:58:53.940595 ==
6546 13:58:53.940682
6547 13:58:53.940767
6548 13:58:53.943691 TX Vref Scan disable
6549 13:58:53.947039 == TX Byte 0 ==
6550 13:58:53.950228 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6551 13:58:53.953874 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6552 13:58:53.956723 == TX Byte 1 ==
6553 13:58:53.960892 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6554 13:58:53.963695 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6555 13:58:53.963766
6556 13:58:53.963827 [DATLAT]
6557 13:58:53.967209 Freq=400, CH0 RK1
6558 13:58:53.967277
6559 13:58:53.967336 DATLAT Default: 0xe
6560 13:58:53.969870 0, 0xFFFF, sum = 0
6561 13:58:53.973358 1, 0xFFFF, sum = 0
6562 13:58:53.973456 2, 0xFFFF, sum = 0
6563 13:58:53.976562 3, 0xFFFF, sum = 0
6564 13:58:53.976658 4, 0xFFFF, sum = 0
6565 13:58:53.980165 5, 0xFFFF, sum = 0
6566 13:58:53.980269 6, 0xFFFF, sum = 0
6567 13:58:53.983237 7, 0xFFFF, sum = 0
6568 13:58:53.983309 8, 0xFFFF, sum = 0
6569 13:58:53.986737 9, 0xFFFF, sum = 0
6570 13:58:53.986809 10, 0xFFFF, sum = 0
6571 13:58:53.989833 11, 0xFFFF, sum = 0
6572 13:58:53.989902 12, 0xFFFF, sum = 0
6573 13:58:53.993133 13, 0x0, sum = 1
6574 13:58:53.993234 14, 0x0, sum = 2
6575 13:58:53.996460 15, 0x0, sum = 3
6576 13:58:53.996556 16, 0x0, sum = 4
6577 13:58:54.000223 best_step = 14
6578 13:58:54.000292
6579 13:58:54.000353 ==
6580 13:58:54.003313 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 13:58:54.007220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 13:58:54.007290 ==
6583 13:58:54.009917 RX Vref Scan: 0
6584 13:58:54.010010
6585 13:58:54.010097 RX Vref 0 -> 0, step: 1
6586 13:58:54.010181
6587 13:58:54.013223 RX Delay -359 -> 252, step: 8
6588 13:58:54.021189 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6589 13:58:54.023850 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6590 13:58:54.027440 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6591 13:58:54.033959 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6592 13:58:54.036982 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6593 13:58:54.040584 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6594 13:58:54.043981 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6595 13:58:54.050773 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6596 13:58:54.054035 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6597 13:58:54.057365 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6598 13:58:54.060112 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6599 13:58:54.066857 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6600 13:58:54.070503 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6601 13:58:54.073772 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6602 13:58:54.077193 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6603 13:58:54.083384 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6604 13:58:54.083460 ==
6605 13:58:54.086868 Dram Type= 6, Freq= 0, CH_0, rank 1
6606 13:58:54.090174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 13:58:54.090240 ==
6608 13:58:54.090305 DQS Delay:
6609 13:58:54.093337 DQS0 = 44, DQS1 = 60
6610 13:58:54.093427 DQM Delay:
6611 13:58:54.096488 DQM0 = 7, DQM1 = 14
6612 13:58:54.096556 DQ Delay:
6613 13:58:54.100030 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6614 13:58:54.103029 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6615 13:58:54.106958 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6616 13:58:54.109882 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =20
6617 13:58:54.109947
6618 13:58:54.110005
6619 13:58:54.116472 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd47, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6620 13:58:54.119698 CH0 RK1: MR19=C0C, MR18=BD47
6621 13:58:54.125836 CH0_RK1: MR19=0xC0C, MR18=0xBD47, DQSOSC=386, MR23=63, INC=396, DEC=264
6622 13:58:54.129462 [RxdqsGatingPostProcess] freq 400
6623 13:58:54.136417 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6624 13:58:54.139242 best DQS0 dly(2T, 0.5T) = (0, 10)
6625 13:58:54.142392 best DQS1 dly(2T, 0.5T) = (0, 10)
6626 13:58:54.146189 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6627 13:58:54.149042 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6628 13:58:54.152596 best DQS0 dly(2T, 0.5T) = (0, 10)
6629 13:58:54.152677 best DQS1 dly(2T, 0.5T) = (0, 10)
6630 13:58:54.156143 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6631 13:58:54.158922 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6632 13:58:54.162332 Pre-setting of DQS Precalculation
6633 13:58:54.169262 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6634 13:58:54.169342 ==
6635 13:58:54.172233 Dram Type= 6, Freq= 0, CH_1, rank 0
6636 13:58:54.175606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 13:58:54.175687 ==
6638 13:58:54.182367 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 13:58:54.189131 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 13:58:54.192030 [CA 0] Center 36 (8~64) winsize 57
6641 13:58:54.195296 [CA 1] Center 36 (8~64) winsize 57
6642 13:58:54.199080 [CA 2] Center 36 (8~64) winsize 57
6643 13:58:54.199160 [CA 3] Center 36 (8~64) winsize 57
6644 13:58:54.201984 [CA 4] Center 36 (8~64) winsize 57
6645 13:58:54.204961 [CA 5] Center 36 (8~64) winsize 57
6646 13:58:54.205042
6647 13:58:54.211892 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 13:58:54.211972
6649 13:58:54.215238 [CATrainingPosCal] consider 1 rank data
6650 13:58:54.218666 u2DelayCellTimex100 = 270/100 ps
6651 13:58:54.221402 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 13:58:54.224829 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 13:58:54.227983 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 13:58:54.231951 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 13:58:54.234902 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 13:58:54.238527 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 13:58:54.238616
6658 13:58:54.241321 CA PerBit enable=1, Macro0, CA PI delay=36
6659 13:58:54.241402
6660 13:58:54.245499 [CBTSetCACLKResult] CA Dly = 36
6661 13:58:54.247908 CS Dly: 1 (0~32)
6662 13:58:54.247989 ==
6663 13:58:54.251266 Dram Type= 6, Freq= 0, CH_1, rank 1
6664 13:58:54.254493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 13:58:54.254575 ==
6666 13:58:54.261370 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 13:58:54.267752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6668 13:58:54.271072 [CA 0] Center 36 (8~64) winsize 57
6669 13:58:54.274367 [CA 1] Center 36 (8~64) winsize 57
6670 13:58:54.274447 [CA 2] Center 36 (8~64) winsize 57
6671 13:58:54.277507 [CA 3] Center 36 (8~64) winsize 57
6672 13:58:54.280747 [CA 4] Center 36 (8~64) winsize 57
6673 13:58:54.283966 [CA 5] Center 36 (8~64) winsize 57
6674 13:58:54.284047
6675 13:58:54.287445 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6676 13:58:54.290580
6677 13:58:54.294281 [CATrainingPosCal] consider 2 rank data
6678 13:58:54.294361 u2DelayCellTimex100 = 270/100 ps
6679 13:58:54.301269 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 13:58:54.304545 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 13:58:54.307250 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 13:58:54.310563 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 13:58:54.313887 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 13:58:54.317249 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 13:58:54.317330
6686 13:58:54.320925 CA PerBit enable=1, Macro0, CA PI delay=36
6687 13:58:54.321006
6688 13:58:54.323463 [CBTSetCACLKResult] CA Dly = 36
6689 13:58:54.326762 CS Dly: 1 (0~32)
6690 13:58:54.326841
6691 13:58:54.330295 ----->DramcWriteLeveling(PI) begin...
6692 13:58:54.330376 ==
6693 13:58:54.333743 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 13:58:54.337079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 13:58:54.337160 ==
6696 13:58:54.340287 Write leveling (Byte 0): 40 => 8
6697 13:58:54.343288 Write leveling (Byte 1): 32 => 0
6698 13:58:54.347049 DramcWriteLeveling(PI) end<-----
6699 13:58:54.347129
6700 13:58:54.347193 ==
6701 13:58:54.350246 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 13:58:54.353584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 13:58:54.353665 ==
6704 13:58:54.356646 [Gating] SW mode calibration
6705 13:58:54.363215 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6706 13:58:54.369597 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6707 13:58:54.372993 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6708 13:58:54.376680 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 13:58:54.383118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 13:58:54.386071 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 13:58:54.389946 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 13:58:54.395933 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 13:58:54.399343 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 13:58:54.406265 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 13:58:54.409239 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 13:58:54.412708 Total UI for P1: 0, mck2ui 16
6717 13:58:54.415739 best dqsien dly found for B0: ( 0, 14, 24)
6718 13:58:54.418971 Total UI for P1: 0, mck2ui 16
6719 13:58:54.422421 best dqsien dly found for B1: ( 0, 14, 24)
6720 13:58:54.425575 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6721 13:58:54.429420 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6722 13:58:54.429493
6723 13:58:54.432511 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6724 13:58:54.435491 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 13:58:54.438803 [Gating] SW calibration Done
6726 13:58:54.438884 ==
6727 13:58:54.442314 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 13:58:54.445287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 13:58:54.448656 ==
6730 13:58:54.448737 RX Vref Scan: 0
6731 13:58:54.448800
6732 13:58:54.452095 RX Vref 0 -> 0, step: 1
6733 13:58:54.452175
6734 13:58:54.455608 RX Delay -410 -> 252, step: 16
6735 13:58:54.458462 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6736 13:58:54.462062 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6737 13:58:54.465702 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6738 13:58:54.472018 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6739 13:58:54.475059 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6740 13:58:54.478190 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6741 13:58:54.481927 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6742 13:58:54.488284 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6743 13:58:54.491768 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6744 13:58:54.494784 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6745 13:58:54.501542 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6746 13:58:54.504821 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6747 13:58:54.508132 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6748 13:58:54.511220 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6749 13:58:54.518281 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6750 13:58:54.521043 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6751 13:58:54.521149 ==
6752 13:58:54.524953 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 13:58:54.527869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 13:58:54.527950 ==
6755 13:58:54.531843 DQS Delay:
6756 13:58:54.531923 DQS0 = 43, DQS1 = 51
6757 13:58:54.534264 DQM Delay:
6758 13:58:54.534343 DQM0 = 13, DQM1 = 15
6759 13:58:54.534407 DQ Delay:
6760 13:58:54.537709 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6761 13:58:54.541200 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6762 13:58:54.544116 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =0
6763 13:58:54.547584 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6764 13:58:54.547665
6765 13:58:54.547810
6766 13:58:54.547908 ==
6767 13:58:54.551030 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 13:58:54.557952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 13:58:54.558033 ==
6770 13:58:54.558097
6771 13:58:54.558156
6772 13:58:54.558212 TX Vref Scan disable
6773 13:58:54.561123 == TX Byte 0 ==
6774 13:58:54.564501 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 13:58:54.567860 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 13:58:54.571179 == TX Byte 1 ==
6777 13:58:54.574244 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6778 13:58:54.577276 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6779 13:58:54.577356 ==
6780 13:58:54.580714 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 13:58:54.587693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 13:58:54.587774 ==
6783 13:58:54.587838
6784 13:58:54.587896
6785 13:58:54.590500 TX Vref Scan disable
6786 13:58:54.590581 == TX Byte 0 ==
6787 13:58:54.593801 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 13:58:54.600956 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 13:58:54.601036 == TX Byte 1 ==
6790 13:58:54.603755 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6791 13:58:54.610364 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6792 13:58:54.610444
6793 13:58:54.610508 [DATLAT]
6794 13:58:54.610567 Freq=400, CH1 RK0
6795 13:58:54.610632
6796 13:58:54.614072 DATLAT Default: 0xf
6797 13:58:54.616812 0, 0xFFFF, sum = 0
6798 13:58:54.616894 1, 0xFFFF, sum = 0
6799 13:58:54.620301 2, 0xFFFF, sum = 0
6800 13:58:54.620382 3, 0xFFFF, sum = 0
6801 13:58:54.623402 4, 0xFFFF, sum = 0
6802 13:58:54.623483 5, 0xFFFF, sum = 0
6803 13:58:54.627319 6, 0xFFFF, sum = 0
6804 13:58:54.627401 7, 0xFFFF, sum = 0
6805 13:58:54.630215 8, 0xFFFF, sum = 0
6806 13:58:54.630295 9, 0xFFFF, sum = 0
6807 13:58:54.633304 10, 0xFFFF, sum = 0
6808 13:58:54.633385 11, 0xFFFF, sum = 0
6809 13:58:54.636927 12, 0xFFFF, sum = 0
6810 13:58:54.637008 13, 0x0, sum = 1
6811 13:58:54.640064 14, 0x0, sum = 2
6812 13:58:54.640146 15, 0x0, sum = 3
6813 13:58:54.643251 16, 0x0, sum = 4
6814 13:58:54.643332 best_step = 14
6815 13:58:54.643396
6816 13:58:54.643455 ==
6817 13:58:54.646488 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 13:58:54.653225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 13:58:54.653306 ==
6820 13:58:54.653369 RX Vref Scan: 1
6821 13:58:54.653429
6822 13:58:54.656603 RX Vref 0 -> 0, step: 1
6823 13:58:54.656683
6824 13:58:54.659687 RX Delay -343 -> 252, step: 8
6825 13:58:54.659768
6826 13:58:54.663138 Set Vref, RX VrefLevel [Byte0]: 48
6827 13:58:54.666631 [Byte1]: 53
6828 13:58:54.666711
6829 13:58:54.669594 Final RX Vref Byte 0 = 48 to rank0
6830 13:58:54.672874 Final RX Vref Byte 1 = 53 to rank0
6831 13:58:54.676530 Final RX Vref Byte 0 = 48 to rank1
6832 13:58:54.679857 Final RX Vref Byte 1 = 53 to rank1==
6833 13:58:54.682751 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 13:58:54.685923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 13:58:54.689527 ==
6836 13:58:54.689607 DQS Delay:
6837 13:58:54.689671 DQS0 = 44, DQS1 = 52
6838 13:58:54.692724 DQM Delay:
6839 13:58:54.692804 DQM0 = 9, DQM1 = 9
6840 13:58:54.696104 DQ Delay:
6841 13:58:54.696184 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6842 13:58:54.699693 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6843 13:58:54.702446 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6844 13:58:54.706096 DQ12 =20, DQ13 =12, DQ14 =16, DQ15 =16
6845 13:58:54.706177
6846 13:58:54.706240
6847 13:58:54.715900 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6848 13:58:54.719664 CH1 RK0: MR19=C0C, MR18=9C73
6849 13:58:54.726362 CH1_RK0: MR19=0xC0C, MR18=0x9C73, DQSOSC=390, MR23=63, INC=388, DEC=258
6850 13:58:54.726443 ==
6851 13:58:54.728897 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 13:58:54.732530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 13:58:54.732611 ==
6854 13:58:54.735489 [Gating] SW mode calibration
6855 13:58:54.742141 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6856 13:58:54.745589 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6857 13:58:54.752172 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6858 13:58:54.755269 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 13:58:54.758660 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 13:58:54.765398 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 13:58:54.768854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 13:58:54.772111 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 13:58:54.778355 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 13:58:54.781925 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 13:58:54.785007 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 13:58:54.788585 Total UI for P1: 0, mck2ui 16
6867 13:58:54.791706 best dqsien dly found for B0: ( 0, 14, 24)
6868 13:58:54.795193 Total UI for P1: 0, mck2ui 16
6869 13:58:54.798468 best dqsien dly found for B1: ( 0, 14, 24)
6870 13:58:54.804577 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6871 13:58:54.809327 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6872 13:58:54.809407
6873 13:58:54.811646 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6874 13:58:54.814817 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 13:58:54.818254 [Gating] SW calibration Done
6876 13:58:54.818334 ==
6877 13:58:54.821048 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 13:58:54.824764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 13:58:54.824845 ==
6880 13:58:54.827932 RX Vref Scan: 0
6881 13:58:54.828012
6882 13:58:54.828076 RX Vref 0 -> 0, step: 1
6883 13:58:54.828136
6884 13:58:54.831429 RX Delay -410 -> 252, step: 16
6885 13:58:54.838152 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6886 13:58:54.841161 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6887 13:58:54.844319 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6888 13:58:54.847646 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6889 13:58:54.854382 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6890 13:58:54.858051 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6891 13:58:54.860607 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6892 13:58:54.863916 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6893 13:58:54.871161 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6894 13:58:54.874259 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6895 13:58:54.877324 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6896 13:58:54.880729 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6897 13:58:54.887392 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6898 13:58:54.890562 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6899 13:58:54.893847 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6900 13:58:54.900285 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6901 13:58:54.900367 ==
6902 13:58:54.904231 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 13:58:54.906912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 13:58:54.906993 ==
6905 13:58:54.907057 DQS Delay:
6906 13:58:54.910151 DQS0 = 51, DQS1 = 51
6907 13:58:54.910232 DQM Delay:
6908 13:58:54.913735 DQM0 = 20, DQM1 = 14
6909 13:58:54.913816 DQ Delay:
6910 13:58:54.917126 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6911 13:58:54.920225 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6912 13:58:54.923343 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6913 13:58:54.926887 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6914 13:58:54.926967
6915 13:58:54.927030
6916 13:58:54.927089 ==
6917 13:58:54.930406 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 13:58:54.933698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 13:58:54.933779 ==
6920 13:58:54.933843
6921 13:58:54.933901
6922 13:58:54.936898 TX Vref Scan disable
6923 13:58:54.936982 == TX Byte 0 ==
6924 13:58:54.943594 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6925 13:58:54.947023 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6926 13:58:54.947107 == TX Byte 1 ==
6927 13:58:54.953915 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6928 13:58:54.956801 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6929 13:58:54.956884 ==
6930 13:58:54.960340 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 13:58:54.963279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 13:58:54.963362 ==
6933 13:58:54.963447
6934 13:58:54.963527
6935 13:58:54.966468 TX Vref Scan disable
6936 13:58:54.970330 == TX Byte 0 ==
6937 13:58:54.972973 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6938 13:58:54.976161 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6939 13:58:54.979616 == TX Byte 1 ==
6940 13:58:54.983175 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6941 13:58:54.986459 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6942 13:58:54.986539
6943 13:58:54.986615 [DATLAT]
6944 13:58:54.989646 Freq=400, CH1 RK1
6945 13:58:54.989727
6946 13:58:54.989791 DATLAT Default: 0xe
6947 13:58:54.993449 0, 0xFFFF, sum = 0
6948 13:58:54.993530 1, 0xFFFF, sum = 0
6949 13:58:54.996411 2, 0xFFFF, sum = 0
6950 13:58:55.000122 3, 0xFFFF, sum = 0
6951 13:58:55.000204 4, 0xFFFF, sum = 0
6952 13:58:55.002851 5, 0xFFFF, sum = 0
6953 13:58:55.002933 6, 0xFFFF, sum = 0
6954 13:58:55.006564 7, 0xFFFF, sum = 0
6955 13:58:55.006660 8, 0xFFFF, sum = 0
6956 13:58:55.009723 9, 0xFFFF, sum = 0
6957 13:58:55.009804 10, 0xFFFF, sum = 0
6958 13:58:55.012924 11, 0xFFFF, sum = 0
6959 13:58:55.013006 12, 0xFFFF, sum = 0
6960 13:58:55.016221 13, 0x0, sum = 1
6961 13:58:55.016306 14, 0x0, sum = 2
6962 13:58:55.019359 15, 0x0, sum = 3
6963 13:58:55.019444 16, 0x0, sum = 4
6964 13:58:55.022865 best_step = 14
6965 13:58:55.022948
6966 13:58:55.023033 ==
6967 13:58:55.026115 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 13:58:55.029478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 13:58:55.029562 ==
6970 13:58:55.032465 RX Vref Scan: 0
6971 13:58:55.032547
6972 13:58:55.032632 RX Vref 0 -> 0, step: 1
6973 13:58:55.032712
6974 13:58:55.035763 RX Delay -343 -> 252, step: 8
6975 13:58:55.043388 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6976 13:58:55.047241 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6977 13:58:55.050135 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6978 13:58:55.053572 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6979 13:58:55.060456 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6980 13:58:55.063493 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6981 13:58:55.067164 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6982 13:58:55.070421 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
6983 13:58:55.076938 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6984 13:58:55.079822 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6985 13:58:55.083199 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6986 13:58:55.089480 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6987 13:58:55.093346 iDelay=225, Bit 12, Center -32 (-279 ~ 216) 496
6988 13:58:55.096082 iDelay=225, Bit 13, Center -36 (-279 ~ 208) 488
6989 13:58:55.099649 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6990 13:58:55.107109 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
6991 13:58:55.107192 ==
6992 13:58:55.109826 Dram Type= 6, Freq= 0, CH_1, rank 1
6993 13:58:55.112940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6994 13:58:55.113024 ==
6995 13:58:55.116330 DQS Delay:
6996 13:58:55.116413 DQS0 = 48, DQS1 = 56
6997 13:58:55.116499 DQM Delay:
6998 13:58:55.119088 DQM0 = 12, DQM1 = 12
6999 13:58:55.119171 DQ Delay:
7000 13:58:55.122160 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7001 13:58:55.125487 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =12
7002 13:58:55.128860 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7003 13:58:55.132325 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =24
7004 13:58:55.132458
7005 13:58:55.132545
7006 13:58:55.142178 [DQSOSCAuto] RK1, (LSB)MR18= 0x7565, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
7007 13:58:55.142299 CH1 RK1: MR19=C0C, MR18=7565
7008 13:58:55.149037 CH1_RK1: MR19=0xC0C, MR18=0x7565, DQSOSC=395, MR23=63, INC=378, DEC=252
7009 13:58:55.151761 [RxdqsGatingPostProcess] freq 400
7010 13:58:55.158549 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7011 13:58:55.162246 best DQS0 dly(2T, 0.5T) = (0, 10)
7012 13:58:55.165093 best DQS1 dly(2T, 0.5T) = (0, 10)
7013 13:58:55.168374 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7014 13:58:55.171842 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7015 13:58:55.175301 best DQS0 dly(2T, 0.5T) = (0, 10)
7016 13:58:55.178272 best DQS1 dly(2T, 0.5T) = (0, 10)
7017 13:58:55.181297 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7018 13:58:55.184716 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7019 13:58:55.188616 Pre-setting of DQS Precalculation
7020 13:58:55.191343 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7021 13:58:55.197804 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7022 13:58:55.204772 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7023 13:58:55.204853
7024 13:58:55.204917
7025 13:58:55.208113 [Calibration Summary] 800 Mbps
7026 13:58:55.211327 CH 0, Rank 0
7027 13:58:55.211408 SW Impedance : PASS
7028 13:58:55.215159 DUTY Scan : NO K
7029 13:58:55.217888 ZQ Calibration : PASS
7030 13:58:55.217967 Jitter Meter : NO K
7031 13:58:55.221288 CBT Training : PASS
7032 13:58:55.225147 Write leveling : PASS
7033 13:58:55.225227 RX DQS gating : PASS
7034 13:58:55.227495 RX DQ/DQS(RDDQC) : PASS
7035 13:58:55.231292 TX DQ/DQS : PASS
7036 13:58:55.231374 RX DATLAT : PASS
7037 13:58:55.234309 RX DQ/DQS(Engine): PASS
7038 13:58:55.237556 TX OE : NO K
7039 13:58:55.237663 All Pass.
7040 13:58:55.237758
7041 13:58:55.237858 CH 0, Rank 1
7042 13:58:55.240720 SW Impedance : PASS
7043 13:58:55.244136 DUTY Scan : NO K
7044 13:58:55.244217 ZQ Calibration : PASS
7045 13:58:55.247954 Jitter Meter : NO K
7046 13:58:55.250782 CBT Training : PASS
7047 13:58:55.250865 Write leveling : NO K
7048 13:58:55.253868 RX DQS gating : PASS
7049 13:58:55.257071 RX DQ/DQS(RDDQC) : PASS
7050 13:58:55.257152 TX DQ/DQS : PASS
7051 13:58:55.260368 RX DATLAT : PASS
7052 13:58:55.260464 RX DQ/DQS(Engine): PASS
7053 13:58:55.264781 TX OE : NO K
7054 13:58:55.264862 All Pass.
7055 13:58:55.264926
7056 13:58:55.267222 CH 1, Rank 0
7057 13:58:55.267302 SW Impedance : PASS
7058 13:58:55.270311 DUTY Scan : NO K
7059 13:58:55.273631 ZQ Calibration : PASS
7060 13:58:55.273711 Jitter Meter : NO K
7061 13:58:55.277027 CBT Training : PASS
7062 13:58:55.280239 Write leveling : PASS
7063 13:58:55.280320 RX DQS gating : PASS
7064 13:58:55.283645 RX DQ/DQS(RDDQC) : PASS
7065 13:58:55.287306 TX DQ/DQS : PASS
7066 13:58:55.287387 RX DATLAT : PASS
7067 13:58:55.290301 RX DQ/DQS(Engine): PASS
7068 13:58:55.293537 TX OE : NO K
7069 13:58:55.293618 All Pass.
7070 13:58:55.293681
7071 13:58:55.293740 CH 1, Rank 1
7072 13:58:55.297154 SW Impedance : PASS
7073 13:58:55.300166 DUTY Scan : NO K
7074 13:58:55.300247 ZQ Calibration : PASS
7075 13:58:55.303249 Jitter Meter : NO K
7076 13:58:55.306729 CBT Training : PASS
7077 13:58:55.306824 Write leveling : NO K
7078 13:58:55.310172 RX DQS gating : PASS
7079 13:58:55.313650 RX DQ/DQS(RDDQC) : PASS
7080 13:58:55.313730 TX DQ/DQS : PASS
7081 13:58:55.317013 RX DATLAT : PASS
7082 13:58:55.320019 RX DQ/DQS(Engine): PASS
7083 13:58:55.320100 TX OE : NO K
7084 13:58:55.320165 All Pass.
7085 13:58:55.323312
7086 13:58:55.323392 DramC Write-DBI off
7087 13:58:55.326451 PER_BANK_REFRESH: Hybrid Mode
7088 13:58:55.326558 TX_TRACKING: ON
7089 13:58:55.336487 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7090 13:58:55.340086 [FAST_K] Save calibration result to emmc
7091 13:58:55.343032 dramc_set_vcore_voltage set vcore to 725000
7092 13:58:55.346491 Read voltage for 1600, 0
7093 13:58:55.346622 Vio18 = 0
7094 13:58:55.349774 Vcore = 725000
7095 13:58:55.349855 Vdram = 0
7096 13:58:55.349918 Vddq = 0
7097 13:58:55.353221 Vmddr = 0
7098 13:58:55.356453 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7099 13:58:55.362989 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7100 13:58:55.363070 MEM_TYPE=3, freq_sel=13
7101 13:58:55.366240 sv_algorithm_assistance_LP4_3733
7102 13:58:55.373018 ============ PULL DRAM RESETB DOWN ============
7103 13:58:55.376234 ========== PULL DRAM RESETB DOWN end =========
7104 13:58:55.379432 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7105 13:58:55.382587 ===================================
7106 13:58:55.385986 LPDDR4 DRAM CONFIGURATION
7107 13:58:55.389231 ===================================
7108 13:58:55.389312 EX_ROW_EN[0] = 0x0
7109 13:58:55.393289 EX_ROW_EN[1] = 0x0
7110 13:58:55.396199 LP4Y_EN = 0x0
7111 13:58:55.396280 WORK_FSP = 0x1
7112 13:58:55.399132 WL = 0x5
7113 13:58:55.399224 RL = 0x5
7114 13:58:55.402984 BL = 0x2
7115 13:58:55.403064 RPST = 0x0
7116 13:58:55.405734 RD_PRE = 0x0
7117 13:58:55.405815 WR_PRE = 0x1
7118 13:58:55.409237 WR_PST = 0x1
7119 13:58:55.409318 DBI_WR = 0x0
7120 13:58:55.412531 DBI_RD = 0x0
7121 13:58:55.412612 OTF = 0x1
7122 13:58:55.416004 ===================================
7123 13:58:55.419054 ===================================
7124 13:58:55.422518 ANA top config
7125 13:58:55.426465 ===================================
7126 13:58:55.426572 DLL_ASYNC_EN = 0
7127 13:58:55.429312 ALL_SLAVE_EN = 0
7128 13:58:55.432391 NEW_RANK_MODE = 1
7129 13:58:55.435609 DLL_IDLE_MODE = 1
7130 13:58:55.438878 LP45_APHY_COMB_EN = 1
7131 13:58:55.438959 TX_ODT_DIS = 0
7132 13:58:55.442730 NEW_8X_MODE = 1
7133 13:58:55.445701 ===================================
7134 13:58:55.448973 ===================================
7135 13:58:55.452263 data_rate = 3200
7136 13:58:55.455748 CKR = 1
7137 13:58:55.458877 DQ_P2S_RATIO = 8
7138 13:58:55.462246 ===================================
7139 13:58:55.465533 CA_P2S_RATIO = 8
7140 13:58:55.465613 DQ_CA_OPEN = 0
7141 13:58:55.468831 DQ_SEMI_OPEN = 0
7142 13:58:55.472186 CA_SEMI_OPEN = 0
7143 13:58:55.475513 CA_FULL_RATE = 0
7144 13:58:55.479349 DQ_CKDIV4_EN = 0
7145 13:58:55.479463 CA_CKDIV4_EN = 0
7146 13:58:55.482480 CA_PREDIV_EN = 0
7147 13:58:55.485298 PH8_DLY = 12
7148 13:58:55.488734 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7149 13:58:55.492218 DQ_AAMCK_DIV = 4
7150 13:58:55.495434 CA_AAMCK_DIV = 4
7151 13:58:55.498532 CA_ADMCK_DIV = 4
7152 13:58:55.498670 DQ_TRACK_CA_EN = 0
7153 13:58:55.502258 CA_PICK = 1600
7154 13:58:55.505496 CA_MCKIO = 1600
7155 13:58:55.508471 MCKIO_SEMI = 0
7156 13:58:55.511964 PLL_FREQ = 3068
7157 13:58:55.515420 DQ_UI_PI_RATIO = 32
7158 13:58:55.518468 CA_UI_PI_RATIO = 0
7159 13:58:55.521899 ===================================
7160 13:58:55.524933 ===================================
7161 13:58:55.525014 memory_type:LPDDR4
7162 13:58:55.528495 GP_NUM : 10
7163 13:58:55.531688 SRAM_EN : 1
7164 13:58:55.531769 MD32_EN : 0
7165 13:58:55.535250 ===================================
7166 13:58:55.538074 [ANA_INIT] >>>>>>>>>>>>>>
7167 13:58:55.541681 <<<<<< [CONFIGURE PHASE]: ANA_TX
7168 13:58:55.545108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7169 13:58:55.548015 ===================================
7170 13:58:55.551496 data_rate = 3200,PCW = 0X7600
7171 13:58:55.554493 ===================================
7172 13:58:55.558142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7173 13:58:55.561240 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7174 13:58:55.567901 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 13:58:55.571420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7176 13:58:55.574343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7177 13:58:55.581191 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7178 13:58:55.581272 [ANA_INIT] flow start
7179 13:58:55.584204 [ANA_INIT] PLL >>>>>>>>
7180 13:58:55.584285 [ANA_INIT] PLL <<<<<<<<
7181 13:58:55.588116 [ANA_INIT] MIDPI >>>>>>>>
7182 13:58:55.590927 [ANA_INIT] MIDPI <<<<<<<<
7183 13:58:55.594231 [ANA_INIT] DLL >>>>>>>>
7184 13:58:55.594311 [ANA_INIT] DLL <<<<<<<<
7185 13:58:55.597912 [ANA_INIT] flow end
7186 13:58:55.601180 ============ LP4 DIFF to SE enter ============
7187 13:58:55.604597 ============ LP4 DIFF to SE exit ============
7188 13:58:55.607799 [ANA_INIT] <<<<<<<<<<<<<
7189 13:58:55.610924 [Flow] Enable top DCM control >>>>>
7190 13:58:55.614068 [Flow] Enable top DCM control <<<<<
7191 13:58:55.617539 Enable DLL master slave shuffle
7192 13:58:55.624090 ==============================================================
7193 13:58:55.624172 Gating Mode config
7194 13:58:55.630827 ==============================================================
7195 13:58:55.630907 Config description:
7196 13:58:55.640548 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7197 13:58:55.647366 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7198 13:58:55.654115 SELPH_MODE 0: By rank 1: By Phase
7199 13:58:55.657336 ==============================================================
7200 13:58:55.660310 GAT_TRACK_EN = 1
7201 13:58:55.664219 RX_GATING_MODE = 2
7202 13:58:55.666967 RX_GATING_TRACK_MODE = 2
7203 13:58:55.670916 SELPH_MODE = 1
7204 13:58:55.673974 PICG_EARLY_EN = 1
7205 13:58:55.677075 VALID_LAT_VALUE = 1
7206 13:58:55.683996 ==============================================================
7207 13:58:55.687431 Enter into Gating configuration >>>>
7208 13:58:55.690981 Exit from Gating configuration <<<<
7209 13:58:55.693717 Enter into DVFS_PRE_config >>>>>
7210 13:58:55.703428 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7211 13:58:55.706476 Exit from DVFS_PRE_config <<<<<
7212 13:58:55.709618 Enter into PICG configuration >>>>
7213 13:58:55.713250 Exit from PICG configuration <<<<
7214 13:58:55.716338 [RX_INPUT] configuration >>>>>
7215 13:58:55.716418 [RX_INPUT] configuration <<<<<
7216 13:58:55.723375 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7217 13:58:55.729920 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7218 13:58:55.736520 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 13:58:55.739958 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 13:58:55.746403 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7221 13:58:55.753368 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7222 13:58:55.756442 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7223 13:58:55.762545 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7224 13:58:55.766442 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7225 13:58:55.769573 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7226 13:58:55.772565 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7227 13:58:55.779084 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7228 13:58:55.782482 ===================================
7229 13:58:55.782563 LPDDR4 DRAM CONFIGURATION
7230 13:58:55.785871 ===================================
7231 13:58:55.789293 EX_ROW_EN[0] = 0x0
7232 13:58:55.793012 EX_ROW_EN[1] = 0x0
7233 13:58:55.793092 LP4Y_EN = 0x0
7234 13:58:55.795883 WORK_FSP = 0x1
7235 13:58:55.795964 WL = 0x5
7236 13:58:55.799129 RL = 0x5
7237 13:58:55.799209 BL = 0x2
7238 13:58:55.802583 RPST = 0x0
7239 13:58:55.802671 RD_PRE = 0x0
7240 13:58:55.805712 WR_PRE = 0x1
7241 13:58:55.805803 WR_PST = 0x1
7242 13:58:55.809006 DBI_WR = 0x0
7243 13:58:55.809087 DBI_RD = 0x0
7244 13:58:55.812186 OTF = 0x1
7245 13:58:55.815477 ===================================
7246 13:58:55.819161 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7247 13:58:55.822126 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7248 13:58:55.829028 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7249 13:58:55.831998 ===================================
7250 13:58:55.832079 LPDDR4 DRAM CONFIGURATION
7251 13:58:55.835368 ===================================
7252 13:58:55.838474 EX_ROW_EN[0] = 0x10
7253 13:58:55.842111 EX_ROW_EN[1] = 0x0
7254 13:58:55.842191 LP4Y_EN = 0x0
7255 13:58:55.844940 WORK_FSP = 0x1
7256 13:58:55.845021 WL = 0x5
7257 13:58:55.848613 RL = 0x5
7258 13:58:55.848694 BL = 0x2
7259 13:58:55.851708 RPST = 0x0
7260 13:58:55.851788 RD_PRE = 0x0
7261 13:58:55.855350 WR_PRE = 0x1
7262 13:58:55.855430 WR_PST = 0x1
7263 13:58:55.858742 DBI_WR = 0x0
7264 13:58:55.858822 DBI_RD = 0x0
7265 13:58:55.861810 OTF = 0x1
7266 13:58:55.864726 ===================================
7267 13:58:55.872737 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7268 13:58:55.872818 ==
7269 13:58:55.874785 Dram Type= 6, Freq= 0, CH_0, rank 0
7270 13:58:55.878336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7271 13:58:55.878417 ==
7272 13:58:55.881771 [Duty_Offset_Calibration]
7273 13:58:55.881851 B0:1 B1:-1 CA:0
7274 13:58:55.881915
7275 13:58:55.884871 [DutyScan_Calibration_Flow] k_type=0
7276 13:58:55.895793
7277 13:58:55.895873 ==CLK 0==
7278 13:58:55.899277 Final CLK duty delay cell = 0
7279 13:58:55.902533 [0] MAX Duty = 5125%(X100), DQS PI = 20
7280 13:58:55.905724 [0] MIN Duty = 4907%(X100), DQS PI = 8
7281 13:58:55.908890 [0] AVG Duty = 5016%(X100)
7282 13:58:55.908971
7283 13:58:55.912489 CH0 CLK Duty spec in!! Max-Min= 218%
7284 13:58:55.915441 [DutyScan_Calibration_Flow] ====Done====
7285 13:58:55.915521
7286 13:58:55.918827 [DutyScan_Calibration_Flow] k_type=1
7287 13:58:55.935407
7288 13:58:55.935491 ==DQS 0 ==
7289 13:58:55.938285 Final DQS duty delay cell = -4
7290 13:58:55.942009 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7291 13:58:55.944521 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7292 13:58:55.947973 [-4] AVG Duty = 4906%(X100)
7293 13:58:55.948054
7294 13:58:55.948117 ==DQS 1 ==
7295 13:58:55.951193 Final DQS duty delay cell = 0
7296 13:58:55.954832 [0] MAX Duty = 5156%(X100), DQS PI = 0
7297 13:58:55.957766 [0] MIN Duty = 5031%(X100), DQS PI = 20
7298 13:58:55.961640 [0] AVG Duty = 5093%(X100)
7299 13:58:55.961708
7300 13:58:55.964704 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7301 13:58:55.964782
7302 13:58:55.967833 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7303 13:58:55.970979 [DutyScan_Calibration_Flow] ====Done====
7304 13:58:55.971047
7305 13:58:55.974541 [DutyScan_Calibration_Flow] k_type=3
7306 13:58:55.992485
7307 13:58:55.992563 ==DQM 0 ==
7308 13:58:55.995881 Final DQM duty delay cell = 0
7309 13:58:55.998955 [0] MAX Duty = 5124%(X100), DQS PI = 22
7310 13:58:56.002811 [0] MIN Duty = 4907%(X100), DQS PI = 8
7311 13:58:56.002882 [0] AVG Duty = 5015%(X100)
7312 13:58:56.005545
7313 13:58:56.005612 ==DQM 1 ==
7314 13:58:56.009010 Final DQM duty delay cell = 0
7315 13:58:56.012318 [0] MAX Duty = 5031%(X100), DQS PI = 30
7316 13:58:56.015351 [0] MIN Duty = 4813%(X100), DQS PI = 20
7317 13:58:56.019200 [0] AVG Duty = 4922%(X100)
7318 13:58:56.019278
7319 13:58:56.022091 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7320 13:58:56.022166
7321 13:58:56.025310 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7322 13:58:56.028565 [DutyScan_Calibration_Flow] ====Done====
7323 13:58:56.028641
7324 13:58:56.031973 [DutyScan_Calibration_Flow] k_type=2
7325 13:58:56.049052
7326 13:58:56.049128 ==DQ 0 ==
7327 13:58:56.051868 Final DQ duty delay cell = -4
7328 13:58:56.055351 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7329 13:58:56.058799 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7330 13:58:56.062149 [-4] AVG Duty = 4953%(X100)
7331 13:58:56.062231
7332 13:58:56.062294 ==DQ 1 ==
7333 13:58:56.065808 Final DQ duty delay cell = 0
7334 13:58:56.068496 [0] MAX Duty = 5125%(X100), DQS PI = 2
7335 13:58:56.071963 [0] MIN Duty = 5000%(X100), DQS PI = 36
7336 13:58:56.075132 [0] AVG Duty = 5062%(X100)
7337 13:58:56.075203
7338 13:58:56.078792 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7339 13:58:56.078868
7340 13:58:56.081791 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7341 13:58:56.085499 [DutyScan_Calibration_Flow] ====Done====
7342 13:58:56.085581 ==
7343 13:58:56.088918 Dram Type= 6, Freq= 0, CH_1, rank 0
7344 13:58:56.091757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7345 13:58:56.091828 ==
7346 13:58:56.095346 [Duty_Offset_Calibration]
7347 13:58:56.095417 B0:-1 B1:1 CA:2
7348 13:58:56.095483
7349 13:58:56.098463 [DutyScan_Calibration_Flow] k_type=0
7350 13:58:56.109654
7351 13:58:56.109728 ==CLK 0==
7352 13:58:56.112995 Final CLK duty delay cell = 0
7353 13:58:56.116420 [0] MAX Duty = 5187%(X100), DQS PI = 22
7354 13:58:56.119309 [0] MIN Duty = 4969%(X100), DQS PI = 62
7355 13:58:56.122534 [0] AVG Duty = 5078%(X100)
7356 13:58:56.122611
7357 13:58:56.125838 CH1 CLK Duty spec in!! Max-Min= 218%
7358 13:58:56.128880 [DutyScan_Calibration_Flow] ====Done====
7359 13:58:56.128950
7360 13:58:56.132456 [DutyScan_Calibration_Flow] k_type=1
7361 13:58:56.149209
7362 13:58:56.149287 ==DQS 0 ==
7363 13:58:56.152917 Final DQS duty delay cell = 0
7364 13:58:56.155508 [0] MAX Duty = 5156%(X100), DQS PI = 20
7365 13:58:56.159038 [0] MIN Duty = 4907%(X100), DQS PI = 10
7366 13:58:56.162378 [0] AVG Duty = 5031%(X100)
7367 13:58:56.162450
7368 13:58:56.162519 ==DQS 1 ==
7369 13:58:56.165664 Final DQS duty delay cell = 0
7370 13:58:56.168553 [0] MAX Duty = 5093%(X100), DQS PI = 22
7371 13:58:56.171959 [0] MIN Duty = 4969%(X100), DQS PI = 54
7372 13:58:56.175443 [0] AVG Duty = 5031%(X100)
7373 13:58:56.175522
7374 13:58:56.178548 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7375 13:58:56.178676
7376 13:58:56.182161 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7377 13:58:56.185112 [DutyScan_Calibration_Flow] ====Done====
7378 13:58:56.185212
7379 13:58:56.189010 [DutyScan_Calibration_Flow] k_type=3
7380 13:58:56.205473
7381 13:58:56.205546 ==DQM 0 ==
7382 13:58:56.208372 Final DQM duty delay cell = -4
7383 13:58:56.211616 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7384 13:58:56.214961 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7385 13:58:56.218401 [-4] AVG Duty = 4937%(X100)
7386 13:58:56.218497
7387 13:58:56.218586 ==DQM 1 ==
7388 13:58:56.222015 Final DQM duty delay cell = 0
7389 13:58:56.224901 [0] MAX Duty = 5156%(X100), DQS PI = 2
7390 13:58:56.228176 [0] MIN Duty = 4969%(X100), DQS PI = 34
7391 13:58:56.231894 [0] AVG Duty = 5062%(X100)
7392 13:58:56.231970
7393 13:58:56.234706 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7394 13:58:56.234776
7395 13:58:56.237912 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7396 13:58:56.241496 [DutyScan_Calibration_Flow] ====Done====
7397 13:58:56.241570
7398 13:58:56.244836 [DutyScan_Calibration_Flow] k_type=2
7399 13:58:56.262547
7400 13:58:56.262680 ==DQ 0 ==
7401 13:58:56.266247 Final DQ duty delay cell = 0
7402 13:58:56.269169 [0] MAX Duty = 5187%(X100), DQS PI = 32
7403 13:58:56.272626 [0] MIN Duty = 4906%(X100), DQS PI = 10
7404 13:58:56.272698 [0] AVG Duty = 5046%(X100)
7405 13:58:56.275895
7406 13:58:56.275966 ==DQ 1 ==
7407 13:58:56.279390 Final DQ duty delay cell = 0
7408 13:58:56.282295 [0] MAX Duty = 5156%(X100), DQS PI = 10
7409 13:58:56.285399 [0] MIN Duty = 4969%(X100), DQS PI = 56
7410 13:58:56.285503 [0] AVG Duty = 5062%(X100)
7411 13:58:56.289177
7412 13:58:56.292459 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7413 13:58:56.292533
7414 13:58:56.295292 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7415 13:58:56.298765 [DutyScan_Calibration_Flow] ====Done====
7416 13:58:56.302205 nWR fixed to 30
7417 13:58:56.302277 [ModeRegInit_LP4] CH0 RK0
7418 13:58:56.305393 [ModeRegInit_LP4] CH0 RK1
7419 13:58:56.308915 [ModeRegInit_LP4] CH1 RK0
7420 13:58:56.312318 [ModeRegInit_LP4] CH1 RK1
7421 13:58:56.312390 match AC timing 5
7422 13:58:56.319149 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7423 13:58:56.322541 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7424 13:58:56.325374 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7425 13:58:56.332504 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7426 13:58:56.335825 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7427 13:58:56.335905 [MiockJmeterHQA]
7428 13:58:56.335967
7429 13:58:56.339205 [DramcMiockJmeter] u1RxGatingPI = 0
7430 13:58:56.341992 0 : 4252, 4026
7431 13:58:56.342066 4 : 4363, 4138
7432 13:58:56.345215 8 : 4255, 4030
7433 13:58:56.345287 12 : 4363, 4138
7434 13:58:56.345355 16 : 4253, 4027
7435 13:58:56.348479 20 : 4252, 4027
7436 13:58:56.348550 24 : 4253, 4026
7437 13:58:56.351835 28 : 4250, 4026
7438 13:58:56.351905 32 : 4363, 4138
7439 13:58:56.355255 36 : 4253, 4026
7440 13:58:56.355331 40 : 4250, 4027
7441 13:58:56.358461 44 : 4250, 4027
7442 13:58:56.358557 48 : 4253, 4029
7443 13:58:56.358676 52 : 4250, 4027
7444 13:58:56.362188 56 : 4363, 4140
7445 13:58:56.362257 60 : 4361, 4137
7446 13:58:56.364806 64 : 4250, 4027
7447 13:58:56.364879 68 : 4250, 4026
7448 13:58:56.368614 72 : 4250, 4027
7449 13:58:56.368685 76 : 4250, 4027
7450 13:58:56.371644 80 : 4253, 4029
7451 13:58:56.371714 84 : 4360, 4138
7452 13:58:56.371773 88 : 4250, 4026
7453 13:58:56.375015 92 : 4250, 814
7454 13:58:56.375085 96 : 4361, 0
7455 13:58:56.378249 100 : 4250, 0
7456 13:58:56.378319 104 : 4250, 0
7457 13:58:56.378379 108 : 4253, 0
7458 13:58:56.381606 112 : 4250, 0
7459 13:58:56.381694 116 : 4250, 0
7460 13:58:56.384756 120 : 4252, 0
7461 13:58:56.384833 124 : 4250, 0
7462 13:58:56.384896 128 : 4250, 0
7463 13:58:56.388209 132 : 4252, 0
7464 13:58:56.388281 136 : 4361, 0
7465 13:58:56.391363 140 : 4250, 0
7466 13:58:56.391434 144 : 4360, 0
7467 13:58:56.391502 148 : 4253, 0
7468 13:58:56.394935 152 : 4250, 0
7469 13:58:56.395017 156 : 4250, 0
7470 13:58:56.397784 160 : 4250, 0
7471 13:58:56.397866 164 : 4250, 0
7472 13:58:56.397930 168 : 4250, 0
7473 13:58:56.401049 172 : 4252, 0
7474 13:58:56.401128 176 : 4252, 0
7475 13:58:56.401192 180 : 4250, 0
7476 13:58:56.404462 184 : 4363, 0
7477 13:58:56.404534 188 : 4364, 0
7478 13:58:56.407941 192 : 4250, 0
7479 13:58:56.408012 196 : 4360, 0
7480 13:58:56.408072 200 : 4250, 0
7481 13:58:56.411182 204 : 4250, 0
7482 13:58:56.411251 208 : 4250, 0
7483 13:58:56.414537 212 : 4250, 0
7484 13:58:56.414632 216 : 4252, 0
7485 13:58:56.414696 220 : 4250, 0
7486 13:58:56.417916 224 : 4253, 184
7487 13:58:56.417986 228 : 4361, 3133
7488 13:58:56.421126 232 : 4253, 4029
7489 13:58:56.421195 236 : 4250, 4027
7490 13:58:56.424271 240 : 4361, 4137
7491 13:58:56.424347 244 : 4250, 4027
7492 13:58:56.427611 248 : 4249, 4027
7493 13:58:56.427681 252 : 4252, 4029
7494 13:58:56.431080 256 : 4253, 4029
7495 13:58:56.431149 260 : 4250, 4027
7496 13:58:56.434701 264 : 4249, 4027
7497 13:58:56.434771 268 : 4360, 4137
7498 13:58:56.434829 272 : 4250, 4026
7499 13:58:56.437456 276 : 4250, 4027
7500 13:58:56.437524 280 : 4361, 4137
7501 13:58:56.441069 284 : 4250, 4027
7502 13:58:56.441148 288 : 4250, 4026
7503 13:58:56.444158 292 : 4363, 4139
7504 13:58:56.444228 296 : 4250, 4027
7505 13:58:56.447413 300 : 4249, 4027
7506 13:58:56.447483 304 : 4250, 4027
7507 13:58:56.450623 308 : 4250, 4026
7508 13:58:56.450713 312 : 4250, 4027
7509 13:58:56.453855 316 : 4250, 4027
7510 13:58:56.453931 320 : 4361, 4137
7511 13:58:56.457154 324 : 4250, 4026
7512 13:58:56.457230 328 : 4250, 4027
7513 13:58:56.460912 332 : 4360, 4138
7514 13:58:56.460988 336 : 4249, 3934
7515 13:58:56.461049 340 : 4250, 2212
7516 13:58:56.464258 344 : 4363, 11
7517 13:58:56.464338
7518 13:58:56.467378 MIOCK jitter meter ch=0
7519 13:58:56.467447
7520 13:58:56.467513 1T = (344-92) = 252 dly cells
7521 13:58:56.473802 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7522 13:58:56.473875 ==
7523 13:58:56.477082 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 13:58:56.480404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 13:58:56.483833 ==
7526 13:58:56.487206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7527 13:58:56.490425 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7528 13:58:56.496816 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7529 13:58:56.503405 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7530 13:58:56.511179 [CA 0] Center 43 (12~74) winsize 63
7531 13:58:56.514911 [CA 1] Center 42 (12~73) winsize 62
7532 13:58:56.517765 [CA 2] Center 38 (9~68) winsize 60
7533 13:58:56.521710 [CA 3] Center 38 (8~68) winsize 61
7534 13:58:56.525065 [CA 4] Center 36 (7~66) winsize 60
7535 13:58:56.527493 [CA 5] Center 35 (6~65) winsize 60
7536 13:58:56.527572
7537 13:58:56.530872 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7538 13:58:56.530942
7539 13:58:56.534112 [CATrainingPosCal] consider 1 rank data
7540 13:58:56.537472 u2DelayCellTimex100 = 258/100 ps
7541 13:58:56.540662 CA0 delay=43 (12~74),Diff = 8 PI (30 cell)
7542 13:58:56.547441 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7543 13:58:56.550788 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7544 13:58:56.553808 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7545 13:58:56.557589 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7546 13:58:56.560797 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7547 13:58:56.560867
7548 13:58:56.563796 CA PerBit enable=1, Macro0, CA PI delay=35
7549 13:58:56.563874
7550 13:58:56.567193 [CBTSetCACLKResult] CA Dly = 35
7551 13:58:56.570916 CS Dly: 12 (0~43)
7552 13:58:56.573992 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7553 13:58:56.577549 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7554 13:58:56.577619 ==
7555 13:58:56.580719 Dram Type= 6, Freq= 0, CH_0, rank 1
7556 13:58:56.587273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 13:58:56.587350 ==
7558 13:58:56.591228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 13:58:56.596946 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 13:58:56.600164 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 13:58:56.607364 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 13:58:56.614908 [CA 0] Center 43 (13~74) winsize 62
7563 13:58:56.617978 [CA 1] Center 44 (14~74) winsize 61
7564 13:58:56.621252 [CA 2] Center 38 (9~68) winsize 60
7565 13:58:56.624985 [CA 3] Center 38 (9~68) winsize 60
7566 13:58:56.627852 [CA 4] Center 36 (7~66) winsize 60
7567 13:58:56.631159 [CA 5] Center 36 (6~66) winsize 61
7568 13:58:56.631238
7569 13:58:56.634530 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7570 13:58:56.634661
7571 13:58:56.637633 [CATrainingPosCal] consider 2 rank data
7572 13:58:56.641110 u2DelayCellTimex100 = 258/100 ps
7573 13:58:56.644186 CA0 delay=43 (13~74),Diff = 8 PI (30 cell)
7574 13:58:56.651197 CA1 delay=43 (14~73),Diff = 8 PI (30 cell)
7575 13:58:56.654382 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7576 13:58:56.657688 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7577 13:58:56.661313 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7578 13:58:56.664174 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7579 13:58:56.664247
7580 13:58:56.667940 CA PerBit enable=1, Macro0, CA PI delay=35
7581 13:58:56.668011
7582 13:58:56.670841 [CBTSetCACLKResult] CA Dly = 35
7583 13:58:56.674237 CS Dly: 12 (0~43)
7584 13:58:56.677415 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 13:58:56.680942 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 13:58:56.681015
7587 13:58:56.684438 ----->DramcWriteLeveling(PI) begin...
7588 13:58:56.684514 ==
7589 13:58:56.687277 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 13:58:56.693667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 13:58:56.693749 ==
7592 13:58:56.697258 Write leveling (Byte 0): 36 => 36
7593 13:58:56.700837 Write leveling (Byte 1): 28 => 28
7594 13:58:56.700914 DramcWriteLeveling(PI) end<-----
7595 13:58:56.703601
7596 13:58:56.703670 ==
7597 13:58:56.706891 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 13:58:56.710371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 13:58:56.710442 ==
7600 13:58:56.713357 [Gating] SW mode calibration
7601 13:58:56.720277 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7602 13:58:56.727023 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7603 13:58:56.730368 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 13:58:56.733667 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 13:58:56.736670 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 13:58:56.744063 1 4 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
7607 13:58:56.746453 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7608 13:58:56.749738 1 4 20 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
7609 13:58:56.756664 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
7610 13:58:56.760186 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 13:58:56.762910 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 13:58:56.769691 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 13:58:56.773721 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 13:58:56.776011 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
7615 13:58:56.782541 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7616 13:58:56.786424 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7617 13:58:56.789479 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7618 13:58:56.796630 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 13:58:56.799127 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 13:58:56.802566 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 13:58:56.809092 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 13:58:56.812587 1 6 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7623 13:58:56.816479 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7624 13:58:56.822305 1 6 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7625 13:58:56.825464 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7626 13:58:56.829012 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 13:58:56.835602 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 13:58:56.839168 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 13:58:56.842322 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 13:58:56.849017 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 13:58:56.852325 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7632 13:58:56.856023 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7633 13:58:56.862378 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7634 13:58:56.865898 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 13:58:56.869281 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 13:58:56.876151 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 13:58:56.879501 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 13:58:56.882877 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 13:58:56.889113 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 13:58:56.892054 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 13:58:56.895941 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 13:58:56.902201 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 13:58:56.905643 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 13:58:56.908900 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 13:58:56.915540 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 13:58:56.918891 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7647 13:58:56.921662 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7648 13:58:56.925382 Total UI for P1: 0, mck2ui 16
7649 13:58:56.929152 best dqsien dly found for B0: ( 1, 9, 12)
7650 13:58:56.935314 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7651 13:58:56.938686 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7652 13:58:56.942026 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 13:58:56.945117 Total UI for P1: 0, mck2ui 16
7654 13:58:56.948731 best dqsien dly found for B1: ( 1, 9, 22)
7655 13:58:56.952129 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7656 13:58:56.955450 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7657 13:58:56.956021
7658 13:58:56.961487 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7659 13:58:56.964786 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7660 13:58:56.968499 [Gating] SW calibration Done
7661 13:58:56.969068 ==
7662 13:58:56.971344 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 13:58:56.974725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 13:58:56.975195 ==
7665 13:58:56.978203 RX Vref Scan: 0
7666 13:58:56.978707
7667 13:58:56.979082 RX Vref 0 -> 0, step: 1
7668 13:58:56.979427
7669 13:58:56.981322 RX Delay 0 -> 252, step: 8
7670 13:58:56.984999 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7671 13:58:56.988351 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7672 13:58:56.994909 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7673 13:58:56.997789 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7674 13:58:57.002003 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7675 13:58:57.005067 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7676 13:58:57.008016 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7677 13:58:57.014970 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7678 13:58:57.018339 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7679 13:58:57.021306 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7680 13:58:57.024919 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7681 13:58:57.028283 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7682 13:58:57.034814 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7683 13:58:57.037986 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7684 13:58:57.040848 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7685 13:58:57.044491 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7686 13:58:57.045063 ==
7687 13:58:57.047350 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 13:58:57.054527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 13:58:57.055142 ==
7690 13:58:57.055649 DQS Delay:
7691 13:58:57.058258 DQS0 = 0, DQS1 = 0
7692 13:58:57.058884 DQM Delay:
7693 13:58:57.060534 DQM0 = 137, DQM1 = 126
7694 13:58:57.061007 DQ Delay:
7695 13:58:57.063859 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7696 13:58:57.068033 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7697 13:58:57.070510 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7698 13:58:57.074074 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7699 13:58:57.074695
7700 13:58:57.075192
7701 13:58:57.075652 ==
7702 13:58:57.076783 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 13:58:57.083658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 13:58:57.084207 ==
7705 13:58:57.084572
7706 13:58:57.084911
7707 13:58:57.085234 TX Vref Scan disable
7708 13:58:57.087513 == TX Byte 0 ==
7709 13:58:57.090580 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7710 13:58:57.097140 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7711 13:58:57.097695 == TX Byte 1 ==
7712 13:58:57.101257 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7713 13:58:57.107090 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7714 13:58:57.107634 ==
7715 13:58:57.110450 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 13:58:57.113824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 13:58:57.114382 ==
7718 13:58:57.125838
7719 13:58:57.129461 TX Vref early break, caculate TX vref
7720 13:58:57.132467 TX Vref=16, minBit 4, minWin=22, winSum=374
7721 13:58:57.135707 TX Vref=18, minBit 1, minWin=23, winSum=381
7722 13:58:57.139563 TX Vref=20, minBit 14, minWin=23, winSum=397
7723 13:58:57.142015 TX Vref=22, minBit 7, minWin=23, winSum=398
7724 13:58:57.145241 TX Vref=24, minBit 0, minWin=25, winSum=409
7725 13:58:57.152313 TX Vref=26, minBit 2, minWin=25, winSum=417
7726 13:58:57.155013 TX Vref=28, minBit 4, minWin=25, winSum=422
7727 13:58:57.158563 TX Vref=30, minBit 0, minWin=24, winSum=412
7728 13:58:57.161729 TX Vref=32, minBit 4, minWin=23, winSum=399
7729 13:58:57.168893 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
7730 13:58:57.169443
7731 13:58:57.171584 Final TX Range 0 Vref 28
7732 13:58:57.172041
7733 13:58:57.172406 ==
7734 13:58:57.175464 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 13:58:57.178479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 13:58:57.179093 ==
7737 13:58:57.179462
7738 13:58:57.179799
7739 13:58:57.182274 TX Vref Scan disable
7740 13:58:57.188175 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7741 13:58:57.188635 == TX Byte 0 ==
7742 13:58:57.191879 u2DelayCellOfst[0]=15 cells (4 PI)
7743 13:58:57.195099 u2DelayCellOfst[1]=18 cells (5 PI)
7744 13:58:57.198389 u2DelayCellOfst[2]=15 cells (4 PI)
7745 13:58:57.201348 u2DelayCellOfst[3]=15 cells (4 PI)
7746 13:58:57.205020 u2DelayCellOfst[4]=11 cells (3 PI)
7747 13:58:57.208276 u2DelayCellOfst[5]=0 cells (0 PI)
7748 13:58:57.211737 u2DelayCellOfst[6]=22 cells (6 PI)
7749 13:58:57.215203 u2DelayCellOfst[7]=22 cells (6 PI)
7750 13:58:57.218064 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7751 13:58:57.221509 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7752 13:58:57.225409 == TX Byte 1 ==
7753 13:58:57.227600 u2DelayCellOfst[8]=0 cells (0 PI)
7754 13:58:57.228059 u2DelayCellOfst[9]=0 cells (0 PI)
7755 13:58:57.231449 u2DelayCellOfst[10]=3 cells (1 PI)
7756 13:58:57.235418 u2DelayCellOfst[11]=0 cells (0 PI)
7757 13:58:57.238056 u2DelayCellOfst[12]=11 cells (3 PI)
7758 13:58:57.241070 u2DelayCellOfst[13]=11 cells (3 PI)
7759 13:58:57.244372 u2DelayCellOfst[14]=15 cells (4 PI)
7760 13:58:57.247391 u2DelayCellOfst[15]=11 cells (3 PI)
7761 13:58:57.250860 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7762 13:58:57.258066 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7763 13:58:57.258681 DramC Write-DBI on
7764 13:58:57.259057 ==
7765 13:58:57.261276 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 13:58:57.267440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 13:58:57.267910 ==
7768 13:58:57.268270
7769 13:58:57.268606
7770 13:58:57.268950 TX Vref Scan disable
7771 13:58:57.271331 == TX Byte 0 ==
7772 13:58:57.275270 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7773 13:58:57.277837 == TX Byte 1 ==
7774 13:58:57.281345 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7775 13:58:57.284267 DramC Write-DBI off
7776 13:58:57.284725
7777 13:58:57.285087 [DATLAT]
7778 13:58:57.285422 Freq=1600, CH0 RK0
7779 13:58:57.285745
7780 13:58:57.288554 DATLAT Default: 0xf
7781 13:58:57.289106 0, 0xFFFF, sum = 0
7782 13:58:57.291305 1, 0xFFFF, sum = 0
7783 13:58:57.294653 2, 0xFFFF, sum = 0
7784 13:58:57.295226 3, 0xFFFF, sum = 0
7785 13:58:57.298215 4, 0xFFFF, sum = 0
7786 13:58:57.298830 5, 0xFFFF, sum = 0
7787 13:58:57.301125 6, 0xFFFF, sum = 0
7788 13:58:57.301587 7, 0xFFFF, sum = 0
7789 13:58:57.304404 8, 0xFFFF, sum = 0
7790 13:58:57.304868 9, 0xFFFF, sum = 0
7791 13:58:57.308076 10, 0xFFFF, sum = 0
7792 13:58:57.308639 11, 0xFFFF, sum = 0
7793 13:58:57.310858 12, 0xFFFF, sum = 0
7794 13:58:57.311350 13, 0xFFFF, sum = 0
7795 13:58:57.314062 14, 0x0, sum = 1
7796 13:58:57.314524 15, 0x0, sum = 2
7797 13:58:57.317645 16, 0x0, sum = 3
7798 13:58:57.318206 17, 0x0, sum = 4
7799 13:58:57.321134 best_step = 15
7800 13:58:57.321584
7801 13:58:57.321946 ==
7802 13:58:57.324371 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 13:58:57.327359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 13:58:57.327820 ==
7805 13:58:57.330528 RX Vref Scan: 1
7806 13:58:57.331038
7807 13:58:57.331400 Set Vref Range= 24 -> 127
7808 13:58:57.331736
7809 13:58:57.334856 RX Vref 24 -> 127, step: 1
7810 13:58:57.335308
7811 13:58:57.337756 RX Delay 11 -> 252, step: 4
7812 13:58:57.338303
7813 13:58:57.340967 Set Vref, RX VrefLevel [Byte0]: 24
7814 13:58:57.344091 [Byte1]: 24
7815 13:58:57.344549
7816 13:58:57.347429 Set Vref, RX VrefLevel [Byte0]: 25
7817 13:58:57.350551 [Byte1]: 25
7818 13:58:57.354199
7819 13:58:57.354813 Set Vref, RX VrefLevel [Byte0]: 26
7820 13:58:57.357768 [Byte1]: 26
7821 13:58:57.362238
7822 13:58:57.362844 Set Vref, RX VrefLevel [Byte0]: 27
7823 13:58:57.364869 [Byte1]: 27
7824 13:58:57.369660
7825 13:58:57.370215 Set Vref, RX VrefLevel [Byte0]: 28
7826 13:58:57.372805 [Byte1]: 28
7827 13:58:57.377098
7828 13:58:57.377685 Set Vref, RX VrefLevel [Byte0]: 29
7829 13:58:57.380436 [Byte1]: 29
7830 13:58:57.384522
7831 13:58:57.384975 Set Vref, RX VrefLevel [Byte0]: 30
7832 13:58:57.387711 [Byte1]: 30
7833 13:58:57.392307
7834 13:58:57.392758 Set Vref, RX VrefLevel [Byte0]: 31
7835 13:58:57.395762 [Byte1]: 31
7836 13:58:57.399875
7837 13:58:57.400425 Set Vref, RX VrefLevel [Byte0]: 32
7838 13:58:57.402967 [Byte1]: 32
7839 13:58:57.407987
7840 13:58:57.408537 Set Vref, RX VrefLevel [Byte0]: 33
7841 13:58:57.411732 [Byte1]: 33
7842 13:58:57.414951
7843 13:58:57.415405 Set Vref, RX VrefLevel [Byte0]: 34
7844 13:58:57.418661 [Byte1]: 34
7845 13:58:57.422937
7846 13:58:57.423496 Set Vref, RX VrefLevel [Byte0]: 35
7847 13:58:57.426010 [Byte1]: 35
7848 13:58:57.430446
7849 13:58:57.431057 Set Vref, RX VrefLevel [Byte0]: 36
7850 13:58:57.433628 [Byte1]: 36
7851 13:58:57.437727
7852 13:58:57.438213 Set Vref, RX VrefLevel [Byte0]: 37
7853 13:58:57.441579 [Byte1]: 37
7854 13:58:57.445575
7855 13:58:57.446128 Set Vref, RX VrefLevel [Byte0]: 38
7856 13:58:57.448762 [Byte1]: 38
7857 13:58:57.453330
7858 13:58:57.453883 Set Vref, RX VrefLevel [Byte0]: 39
7859 13:58:57.456534 [Byte1]: 39
7860 13:58:57.461160
7861 13:58:57.461714 Set Vref, RX VrefLevel [Byte0]: 40
7862 13:58:57.464029 [Byte1]: 40
7863 13:58:57.468876
7864 13:58:57.469567 Set Vref, RX VrefLevel [Byte0]: 41
7865 13:58:57.471872 [Byte1]: 41
7866 13:58:57.475893
7867 13:58:57.476430 Set Vref, RX VrefLevel [Byte0]: 42
7868 13:58:57.479308 [Byte1]: 42
7869 13:58:57.483615
7870 13:58:57.484313 Set Vref, RX VrefLevel [Byte0]: 43
7871 13:58:57.486905 [Byte1]: 43
7872 13:58:57.491058
7873 13:58:57.491509 Set Vref, RX VrefLevel [Byte0]: 44
7874 13:58:57.495222 [Byte1]: 44
7875 13:58:57.499538
7876 13:58:57.499990 Set Vref, RX VrefLevel [Byte0]: 45
7877 13:58:57.502866 [Byte1]: 45
7878 13:58:57.506533
7879 13:58:57.507204 Set Vref, RX VrefLevel [Byte0]: 46
7880 13:58:57.509886 [Byte1]: 46
7881 13:58:57.514755
7882 13:58:57.515308 Set Vref, RX VrefLevel [Byte0]: 47
7883 13:58:57.517568 [Byte1]: 47
7884 13:58:57.521743
7885 13:58:57.522295 Set Vref, RX VrefLevel [Byte0]: 48
7886 13:58:57.525351 [Byte1]: 48
7887 13:58:57.529019
7888 13:58:57.529471 Set Vref, RX VrefLevel [Byte0]: 49
7889 13:58:57.533244 [Byte1]: 49
7890 13:58:57.537110
7891 13:58:57.537668 Set Vref, RX VrefLevel [Byte0]: 50
7892 13:58:57.540009 [Byte1]: 50
7893 13:58:57.545264
7894 13:58:57.545815 Set Vref, RX VrefLevel [Byte0]: 51
7895 13:58:57.547948 [Byte1]: 51
7896 13:58:57.552836
7897 13:58:57.553394 Set Vref, RX VrefLevel [Byte0]: 52
7898 13:58:57.555386 [Byte1]: 52
7899 13:58:57.560253
7900 13:58:57.560804 Set Vref, RX VrefLevel [Byte0]: 53
7901 13:58:57.562928 [Byte1]: 53
7902 13:58:57.567440
7903 13:58:57.567896 Set Vref, RX VrefLevel [Byte0]: 54
7904 13:58:57.570646 [Byte1]: 54
7905 13:58:57.575057
7906 13:58:57.575507 Set Vref, RX VrefLevel [Byte0]: 55
7907 13:58:57.578109 [Byte1]: 55
7908 13:58:57.582730
7909 13:58:57.583274 Set Vref, RX VrefLevel [Byte0]: 56
7910 13:58:57.586353 [Byte1]: 56
7911 13:58:57.590263
7912 13:58:57.590911 Set Vref, RX VrefLevel [Byte0]: 57
7913 13:58:57.593896 [Byte1]: 57
7914 13:58:57.597823
7915 13:58:57.598281 Set Vref, RX VrefLevel [Byte0]: 58
7916 13:58:57.600919 [Byte1]: 58
7917 13:58:57.605418
7918 13:58:57.605975 Set Vref, RX VrefLevel [Byte0]: 59
7919 13:58:57.608658 [Byte1]: 59
7920 13:58:57.613578
7921 13:58:57.614130 Set Vref, RX VrefLevel [Byte0]: 60
7922 13:58:57.616516 [Byte1]: 60
7923 13:58:57.620894
7924 13:58:57.621448 Set Vref, RX VrefLevel [Byte0]: 61
7925 13:58:57.624390 [Byte1]: 61
7926 13:58:57.628655
7927 13:58:57.629210 Set Vref, RX VrefLevel [Byte0]: 62
7928 13:58:57.631781 [Byte1]: 62
7929 13:58:57.635799
7930 13:58:57.636352 Set Vref, RX VrefLevel [Byte0]: 63
7931 13:58:57.639402 [Byte1]: 63
7932 13:58:57.643348
7933 13:58:57.643923 Set Vref, RX VrefLevel [Byte0]: 64
7934 13:58:57.646858 [Byte1]: 64
7935 13:58:57.651150
7936 13:58:57.651702 Set Vref, RX VrefLevel [Byte0]: 65
7937 13:58:57.654785 [Byte1]: 65
7938 13:58:57.658573
7939 13:58:57.659070 Set Vref, RX VrefLevel [Byte0]: 66
7940 13:58:57.661952 [Byte1]: 66
7941 13:58:57.666375
7942 13:58:57.666902 Set Vref, RX VrefLevel [Byte0]: 67
7943 13:58:57.669592 [Byte1]: 67
7944 13:58:57.674426
7945 13:58:57.675024 Set Vref, RX VrefLevel [Byte0]: 68
7946 13:58:57.677514 [Byte1]: 68
7947 13:58:57.681699
7948 13:58:57.682254 Set Vref, RX VrefLevel [Byte0]: 69
7949 13:58:57.684630 [Byte1]: 69
7950 13:58:57.688807
7951 13:58:57.689370 Set Vref, RX VrefLevel [Byte0]: 70
7952 13:58:57.692399 [Byte1]: 70
7953 13:58:57.696650
7954 13:58:57.697201 Set Vref, RX VrefLevel [Byte0]: 71
7955 13:58:57.700097 [Byte1]: 71
7956 13:58:57.704686
7957 13:58:57.705247 Set Vref, RX VrefLevel [Byte0]: 72
7958 13:58:57.707582 [Byte1]: 72
7959 13:58:57.712617
7960 13:58:57.713176 Set Vref, RX VrefLevel [Byte0]: 73
7961 13:58:57.715306 [Byte1]: 73
7962 13:58:57.719696
7963 13:58:57.720250 Set Vref, RX VrefLevel [Byte0]: 74
7964 13:58:57.722946 [Byte1]: 74
7965 13:58:57.727364
7966 13:58:57.727918 Set Vref, RX VrefLevel [Byte0]: 75
7967 13:58:57.730456 [Byte1]: 75
7968 13:58:57.734860
7969 13:58:57.735316 Set Vref, RX VrefLevel [Byte0]: 76
7970 13:58:57.738520 [Byte1]: 76
7971 13:58:57.742457
7972 13:58:57.743117 Set Vref, RX VrefLevel [Byte0]: 77
7973 13:58:57.745943 [Byte1]: 77
7974 13:58:57.749844
7975 13:58:57.750399 Set Vref, RX VrefLevel [Byte0]: 78
7976 13:58:57.753127 [Byte1]: 78
7977 13:58:57.757728
7978 13:58:57.758280 Final RX Vref Byte 0 = 67 to rank0
7979 13:58:57.761220 Final RX Vref Byte 1 = 58 to rank0
7980 13:58:57.764038 Final RX Vref Byte 0 = 67 to rank1
7981 13:58:57.767734 Final RX Vref Byte 1 = 58 to rank1==
7982 13:58:57.770564 Dram Type= 6, Freq= 0, CH_0, rank 0
7983 13:58:57.777297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 13:58:57.777852 ==
7985 13:58:57.778213 DQS Delay:
7986 13:58:57.781415 DQS0 = 0, DQS1 = 0
7987 13:58:57.781970 DQM Delay:
7988 13:58:57.782338 DQM0 = 134, DQM1 = 123
7989 13:58:57.784114 DQ Delay:
7990 13:58:57.786854 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =134
7991 13:58:57.790442 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =144
7992 13:58:57.794080 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =118
7993 13:58:57.797029 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
7994 13:58:57.797580
7995 13:58:57.797942
7996 13:58:57.798274
7997 13:58:57.800417 [DramC_TX_OE_Calibration] TA2
7998 13:58:57.804510 Original DQ_B0 (3 6) =30, OEN = 27
7999 13:58:57.807211 Original DQ_B1 (3 6) =30, OEN = 27
8000 13:58:57.810257 24, 0x0, End_B0=24 End_B1=24
8001 13:58:57.813715 25, 0x0, End_B0=25 End_B1=25
8002 13:58:57.814278 26, 0x0, End_B0=26 End_B1=26
8003 13:58:57.817001 27, 0x0, End_B0=27 End_B1=27
8004 13:58:57.820300 28, 0x0, End_B0=28 End_B1=28
8005 13:58:57.823347 29, 0x0, End_B0=29 End_B1=29
8006 13:58:57.823814 30, 0x0, End_B0=30 End_B1=30
8007 13:58:57.827235 31, 0x4545, End_B0=30 End_B1=30
8008 13:58:57.829852 Byte0 end_step=30 best_step=27
8009 13:58:57.833722 Byte1 end_step=30 best_step=27
8010 13:58:57.836738 Byte0 TX OE(2T, 0.5T) = (3, 3)
8011 13:58:57.840203 Byte1 TX OE(2T, 0.5T) = (3, 3)
8012 13:58:57.840756
8013 13:58:57.841121
8014 13:58:57.846578 [DQSOSCAuto] RK0, (LSB)MR18= 0x2314, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8015 13:58:57.849564 CH0 RK0: MR19=303, MR18=2314
8016 13:58:57.856648 CH0_RK0: MR19=0x303, MR18=0x2314, DQSOSC=392, MR23=63, INC=24, DEC=16
8017 13:58:57.857335
8018 13:58:57.859763 ----->DramcWriteLeveling(PI) begin...
8019 13:58:57.860329 ==
8020 13:58:57.863286 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 13:58:57.866091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 13:58:57.866549 ==
8023 13:58:57.869852 Write leveling (Byte 0): 36 => 36
8024 13:58:57.873521 Write leveling (Byte 1): 29 => 29
8025 13:58:57.876326 DramcWriteLeveling(PI) end<-----
8026 13:58:57.877059
8027 13:58:57.877451 ==
8028 13:58:57.879220 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 13:58:57.885961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 13:58:57.886505 ==
8031 13:58:57.886914 [Gating] SW mode calibration
8032 13:58:57.896429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8033 13:58:57.899074 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8034 13:58:57.902574 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 13:58:57.909242 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 13:58:57.912363 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 13:58:57.916108 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8038 13:58:57.922926 1 4 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8039 13:58:57.925897 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
8040 13:58:57.929438 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 13:58:57.935591 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 13:58:57.938701 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 13:58:57.942532 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 13:58:57.948733 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8045 13:58:57.951999 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8046 13:58:57.955592 1 5 16 | B1->B0 | 3434 2828 | 0 0 | (1 0) (0 0)
8047 13:58:57.962530 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
8048 13:58:57.965599 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 13:58:57.968611 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 13:58:57.975652 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 13:58:57.978873 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 13:58:57.982135 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 13:58:57.988412 1 6 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8054 13:58:57.992122 1 6 16 | B1->B0 | 2f2f 4646 | 1 0 | (1 1) (0 0)
8055 13:58:57.995426 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 13:58:58.001774 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 13:58:58.005493 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 13:58:58.008434 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 13:58:58.014705 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 13:58:58.018468 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 13:58:58.021755 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8062 13:58:58.028524 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8063 13:58:58.031220 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8064 13:58:58.035498 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 13:58:58.041439 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 13:58:58.044852 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 13:58:58.047891 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 13:58:58.054732 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 13:58:58.058012 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 13:58:58.061311 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 13:58:58.067615 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 13:58:58.070860 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 13:58:58.074467 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 13:58:58.081260 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 13:58:58.084093 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 13:58:58.087607 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 13:58:58.094139 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8078 13:58:58.097482 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8079 13:58:58.100721 Total UI for P1: 0, mck2ui 16
8080 13:58:58.103981 best dqsien dly found for B0: ( 1, 9, 12)
8081 13:58:58.107401 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 13:58:58.110849 Total UI for P1: 0, mck2ui 16
8083 13:58:58.113805 best dqsien dly found for B1: ( 1, 9, 16)
8084 13:58:58.117625 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8085 13:58:58.120476 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8086 13:58:58.123679
8087 13:58:58.126994 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8088 13:58:58.130634 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8089 13:58:58.133330 [Gating] SW calibration Done
8090 13:58:58.133753 ==
8091 13:58:58.136971 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 13:58:58.140320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 13:58:58.140880 ==
8094 13:58:58.143740 RX Vref Scan: 0
8095 13:58:58.144198
8096 13:58:58.144558 RX Vref 0 -> 0, step: 1
8097 13:58:58.144892
8098 13:58:58.146921 RX Delay 0 -> 252, step: 8
8099 13:58:58.150155 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8100 13:58:58.153088 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8101 13:58:58.160428 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8102 13:58:58.163133 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
8103 13:58:58.166533 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8104 13:58:58.170261 iDelay=208, Bit 5, Center 123 (64 ~ 183) 120
8105 13:58:58.176743 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
8106 13:58:58.180151 iDelay=208, Bit 7, Center 147 (88 ~ 207) 120
8107 13:58:58.183225 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8108 13:58:58.185943 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8109 13:58:58.189317 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8110 13:58:58.195977 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8111 13:58:58.199218 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8112 13:58:58.202741 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8113 13:58:58.206210 iDelay=208, Bit 14, Center 143 (88 ~ 199) 112
8114 13:58:58.212766 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8115 13:58:58.213319 ==
8116 13:58:58.215907 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 13:58:58.220051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 13:58:58.220605 ==
8119 13:58:58.220968 DQS Delay:
8120 13:58:58.223508 DQS0 = 0, DQS1 = 0
8121 13:58:58.224058 DQM Delay:
8122 13:58:58.225935 DQM0 = 133, DQM1 = 130
8123 13:58:58.226486 DQ Delay:
8124 13:58:58.229171 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8125 13:58:58.232483 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
8126 13:58:58.235668 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =127
8127 13:58:58.239306 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8128 13:58:58.239860
8129 13:58:58.240288
8130 13:58:58.242325 ==
8131 13:58:58.245797 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 13:58:58.248673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 13:58:58.249353 ==
8134 13:58:58.249738
8135 13:58:58.250099
8136 13:58:58.252392 TX Vref Scan disable
8137 13:58:58.252957 == TX Byte 0 ==
8138 13:58:58.255265 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8139 13:58:58.262139 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8140 13:58:58.262938 == TX Byte 1 ==
8141 13:58:58.268748 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8142 13:58:58.272155 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8143 13:58:58.272718 ==
8144 13:58:58.275665 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 13:58:58.278361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 13:58:58.278958 ==
8147 13:58:58.292547
8148 13:58:58.296133 TX Vref early break, caculate TX vref
8149 13:58:58.298946 TX Vref=16, minBit 3, minWin=22, winSum=379
8150 13:58:58.303180 TX Vref=18, minBit 0, minWin=23, winSum=390
8151 13:58:58.305489 TX Vref=20, minBit 0, minWin=23, winSum=396
8152 13:58:58.309140 TX Vref=22, minBit 1, minWin=24, winSum=407
8153 13:58:58.311854 TX Vref=24, minBit 5, minWin=24, winSum=412
8154 13:58:58.319284 TX Vref=26, minBit 0, minWin=25, winSum=420
8155 13:58:58.322797 TX Vref=28, minBit 1, minWin=24, winSum=415
8156 13:58:58.325505 TX Vref=30, minBit 0, minWin=24, winSum=402
8157 13:58:58.329164 TX Vref=32, minBit 2, minWin=23, winSum=399
8158 13:58:58.332385 TX Vref=34, minBit 4, minWin=23, winSum=392
8159 13:58:58.338663 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
8160 13:58:58.339231
8161 13:58:58.342141 Final TX Range 0 Vref 26
8162 13:58:58.342753
8163 13:58:58.343124 ==
8164 13:58:58.345676 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 13:58:58.348755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 13:58:58.349344 ==
8167 13:58:58.349726
8168 13:58:58.350067
8169 13:58:58.351234 TX Vref Scan disable
8170 13:58:58.358135 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8171 13:58:58.358744 == TX Byte 0 ==
8172 13:58:58.361673 u2DelayCellOfst[0]=15 cells (4 PI)
8173 13:58:58.364881 u2DelayCellOfst[1]=18 cells (5 PI)
8174 13:58:58.368007 u2DelayCellOfst[2]=15 cells (4 PI)
8175 13:58:58.371418 u2DelayCellOfst[3]=15 cells (4 PI)
8176 13:58:58.374735 u2DelayCellOfst[4]=11 cells (3 PI)
8177 13:58:58.378844 u2DelayCellOfst[5]=0 cells (0 PI)
8178 13:58:58.381789 u2DelayCellOfst[6]=18 cells (5 PI)
8179 13:58:58.384830 u2DelayCellOfst[7]=22 cells (6 PI)
8180 13:58:58.388318 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8181 13:58:58.391124 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8182 13:58:58.394550 == TX Byte 1 ==
8183 13:58:58.398002 u2DelayCellOfst[8]=0 cells (0 PI)
8184 13:58:58.401350 u2DelayCellOfst[9]=3 cells (1 PI)
8185 13:58:58.401919 u2DelayCellOfst[10]=7 cells (2 PI)
8186 13:58:58.404600 u2DelayCellOfst[11]=3 cells (1 PI)
8187 13:58:58.407536 u2DelayCellOfst[12]=15 cells (4 PI)
8188 13:58:58.411208 u2DelayCellOfst[13]=15 cells (4 PI)
8189 13:58:58.414123 u2DelayCellOfst[14]=18 cells (5 PI)
8190 13:58:58.417868 u2DelayCellOfst[15]=11 cells (3 PI)
8191 13:58:58.424397 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8192 13:58:58.427498 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8193 13:58:58.428063 DramC Write-DBI on
8194 13:58:58.428429 ==
8195 13:58:58.430780 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 13:58:58.437712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 13:58:58.438286 ==
8198 13:58:58.438689
8199 13:58:58.439036
8200 13:58:58.441108 TX Vref Scan disable
8201 13:58:58.441672 == TX Byte 0 ==
8202 13:58:58.447426 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8203 13:58:58.447892 == TX Byte 1 ==
8204 13:58:58.450485 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8205 13:58:58.453668 DramC Write-DBI off
8206 13:58:58.454131
8207 13:58:58.454494 [DATLAT]
8208 13:58:58.457239 Freq=1600, CH0 RK1
8209 13:58:58.457803
8210 13:58:58.458172 DATLAT Default: 0xf
8211 13:58:58.461042 0, 0xFFFF, sum = 0
8212 13:58:58.461620 1, 0xFFFF, sum = 0
8213 13:58:58.464315 2, 0xFFFF, sum = 0
8214 13:58:58.464885 3, 0xFFFF, sum = 0
8215 13:58:58.466959 4, 0xFFFF, sum = 0
8216 13:58:58.467602 5, 0xFFFF, sum = 0
8217 13:58:58.470519 6, 0xFFFF, sum = 0
8218 13:58:58.471028 7, 0xFFFF, sum = 0
8219 13:58:58.473935 8, 0xFFFF, sum = 0
8220 13:58:58.477605 9, 0xFFFF, sum = 0
8221 13:58:58.478175 10, 0xFFFF, sum = 0
8222 13:58:58.480253 11, 0xFFFF, sum = 0
8223 13:58:58.480825 12, 0xFFFF, sum = 0
8224 13:58:58.483803 13, 0xFFFF, sum = 0
8225 13:58:58.484369 14, 0x0, sum = 1
8226 13:58:58.486716 15, 0x0, sum = 2
8227 13:58:58.487245 16, 0x0, sum = 3
8228 13:58:58.490075 17, 0x0, sum = 4
8229 13:58:58.490546 best_step = 15
8230 13:58:58.490950
8231 13:58:58.491291 ==
8232 13:58:58.493633 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 13:58:58.496740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 13:58:58.500154 ==
8235 13:58:58.500619 RX Vref Scan: 0
8236 13:58:58.500987
8237 13:58:58.503150 RX Vref 0 -> 0, step: 1
8238 13:58:58.503655
8239 13:58:58.504038 RX Delay 11 -> 252, step: 4
8240 13:58:58.510900 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8241 13:58:58.513977 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8242 13:58:58.517271 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8243 13:58:58.520733 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8244 13:58:58.523935 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8245 13:58:58.530583 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8246 13:58:58.534295 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8247 13:58:58.537524 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8248 13:58:58.540539 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8249 13:58:58.544092 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8250 13:58:58.550616 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8251 13:58:58.553742 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8252 13:58:58.557632 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8253 13:58:58.560689 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8254 13:58:58.567339 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8255 13:58:58.570271 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8256 13:58:58.570784 ==
8257 13:58:58.573896 Dram Type= 6, Freq= 0, CH_0, rank 1
8258 13:58:58.576951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 13:58:58.577520 ==
8260 13:58:58.580426 DQS Delay:
8261 13:58:58.580987 DQS0 = 0, DQS1 = 0
8262 13:58:58.581355 DQM Delay:
8263 13:58:58.583168 DQM0 = 130, DQM1 = 125
8264 13:58:58.583631 DQ Delay:
8265 13:58:58.586477 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8266 13:58:58.589848 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8267 13:58:58.596549 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8268 13:58:58.600794 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8269 13:58:58.601363
8270 13:58:58.601727
8271 13:58:58.602061
8272 13:58:58.603074 [DramC_TX_OE_Calibration] TA2
8273 13:58:58.606663 Original DQ_B0 (3 6) =30, OEN = 27
8274 13:58:58.607243 Original DQ_B1 (3 6) =30, OEN = 27
8275 13:58:58.609806 24, 0x0, End_B0=24 End_B1=24
8276 13:58:58.613136 25, 0x0, End_B0=25 End_B1=25
8277 13:58:58.616225 26, 0x0, End_B0=26 End_B1=26
8278 13:58:58.619432 27, 0x0, End_B0=27 End_B1=27
8279 13:58:58.619964 28, 0x0, End_B0=28 End_B1=28
8280 13:58:58.622757 29, 0x0, End_B0=29 End_B1=29
8281 13:58:58.626649 30, 0x0, End_B0=30 End_B1=30
8282 13:58:58.629414 31, 0x4141, End_B0=30 End_B1=30
8283 13:58:58.633406 Byte0 end_step=30 best_step=27
8284 13:58:58.636355 Byte1 end_step=30 best_step=27
8285 13:58:58.636918 Byte0 TX OE(2T, 0.5T) = (3, 3)
8286 13:58:58.639523 Byte1 TX OE(2T, 0.5T) = (3, 3)
8287 13:58:58.640085
8288 13:58:58.640452
8289 13:58:58.649378 [DQSOSCAuto] RK1, (LSB)MR18= 0x2405, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 391 ps
8290 13:58:58.652751 CH0 RK1: MR19=303, MR18=2405
8291 13:58:58.655670 CH0_RK1: MR19=0x303, MR18=0x2405, DQSOSC=391, MR23=63, INC=24, DEC=16
8292 13:58:58.659110 [RxdqsGatingPostProcess] freq 1600
8293 13:58:58.665510 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8294 13:58:58.668820 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 13:58:58.672532 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 13:58:58.676065 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 13:58:58.678847 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 13:58:58.682065 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 13:58:58.686312 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 13:58:58.689025 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 13:58:58.691874 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 13:58:58.692295 Pre-setting of DQS Precalculation
8303 13:58:58.698692 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8304 13:58:58.699226 ==
8305 13:58:58.702077 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 13:58:58.705340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 13:58:58.705862 ==
8308 13:58:58.712399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8309 13:58:58.715522 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8310 13:58:58.718881 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8311 13:58:58.725261 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8312 13:58:58.735718 [CA 0] Center 42 (13~72) winsize 60
8313 13:58:58.738973 [CA 1] Center 42 (13~72) winsize 60
8314 13:58:58.742127 [CA 2] Center 38 (9~67) winsize 59
8315 13:58:58.745193 [CA 3] Center 36 (7~66) winsize 60
8316 13:58:58.748285 [CA 4] Center 37 (8~67) winsize 60
8317 13:58:58.751778 [CA 5] Center 37 (8~67) winsize 60
8318 13:58:58.752238
8319 13:58:58.755024 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8320 13:58:58.755586
8321 13:58:58.761675 [CATrainingPosCal] consider 1 rank data
8322 13:58:58.762420 u2DelayCellTimex100 = 258/100 ps
8323 13:58:58.767950 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8324 13:58:58.771229 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8325 13:58:58.775269 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8326 13:58:58.778733 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8327 13:58:58.781395 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8328 13:58:58.784632 CA5 delay=37 (8~67),Diff = 1 PI (3 cell)
8329 13:58:58.785184
8330 13:58:58.787892 CA PerBit enable=1, Macro0, CA PI delay=36
8331 13:58:58.788357
8332 13:58:58.791274 [CBTSetCACLKResult] CA Dly = 36
8333 13:58:58.795212 CS Dly: 9 (0~40)
8334 13:58:58.797938 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8335 13:58:58.801088 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8336 13:58:58.801635 ==
8337 13:58:58.805359 Dram Type= 6, Freq= 0, CH_1, rank 1
8338 13:58:58.807938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 13:58:58.811116 ==
8340 13:58:58.814407 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8341 13:58:58.817447 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8342 13:58:58.824190 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8343 13:58:58.830826 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8344 13:58:58.838301 [CA 0] Center 42 (13~72) winsize 60
8345 13:58:58.841205 [CA 1] Center 42 (12~72) winsize 61
8346 13:58:58.845288 [CA 2] Center 37 (8~67) winsize 60
8347 13:58:58.847614 [CA 3] Center 37 (8~67) winsize 60
8348 13:58:58.851273 [CA 4] Center 37 (8~67) winsize 60
8349 13:58:58.854392 [CA 5] Center 36 (7~66) winsize 60
8350 13:58:58.854937
8351 13:58:58.858193 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8352 13:58:58.858719
8353 13:58:58.861341 [CATrainingPosCal] consider 2 rank data
8354 13:58:58.864636 u2DelayCellTimex100 = 258/100 ps
8355 13:58:58.871418 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8356 13:58:58.874253 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8357 13:58:58.877215 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8358 13:58:58.880411 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8359 13:58:58.883564 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8360 13:58:58.887149 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8361 13:58:58.887221
8362 13:58:58.890393 CA PerBit enable=1, Macro0, CA PI delay=37
8363 13:58:58.890488
8364 13:58:58.894103 [CBTSetCACLKResult] CA Dly = 37
8365 13:58:58.897158 CS Dly: 11 (0~44)
8366 13:58:58.900187 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8367 13:58:58.903549 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8368 13:58:58.903627
8369 13:58:58.906749 ----->DramcWriteLeveling(PI) begin...
8370 13:58:58.906829 ==
8371 13:58:58.910109 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 13:58:58.916972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 13:58:58.917078 ==
8374 13:58:58.920004 Write leveling (Byte 0): 22 => 22
8375 13:58:58.923259 Write leveling (Byte 1): 28 => 28
8376 13:58:58.927219 DramcWriteLeveling(PI) end<-----
8377 13:58:58.927393
8378 13:58:58.927506 ==
8379 13:58:58.930061 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 13:58:58.933134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 13:58:58.933335 ==
8382 13:58:58.936391 [Gating] SW mode calibration
8383 13:58:58.943377 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8384 13:58:58.949876 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8385 13:58:58.952492 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 13:58:58.955955 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 13:58:58.962438 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
8388 13:58:58.965684 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8389 13:58:58.968964 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 13:58:58.975673 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 13:58:58.978944 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 13:58:58.983296 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 13:58:58.989773 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 13:58:58.993262 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 13:58:58.995780 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8396 13:58:59.002468 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (1 0) (1 0)
8397 13:58:59.005841 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8398 13:58:59.009335 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 13:58:59.015755 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 13:58:59.019589 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 13:58:59.022261 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 13:58:59.029368 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 13:58:59.032345 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8404 13:58:59.035892 1 6 12 | B1->B0 | 2a2a 4444 | 0 0 | (1 1) (0 0)
8405 13:58:59.042345 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 13:58:59.045126 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 13:58:59.048213 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 13:58:59.055114 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 13:58:59.058346 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 13:58:59.061887 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 13:58:59.068131 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8412 13:58:59.071345 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8413 13:58:59.074706 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8414 13:58:59.081606 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 13:58:59.084763 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 13:58:59.087961 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 13:58:59.094707 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 13:58:59.097560 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 13:58:59.101359 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 13:58:59.108181 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 13:58:59.111269 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 13:58:59.114639 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 13:58:59.120785 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 13:58:59.124109 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 13:58:59.127677 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 13:58:59.134307 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 13:58:59.137941 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8428 13:58:59.140714 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8429 13:58:59.144210 Total UI for P1: 0, mck2ui 16
8430 13:58:59.147126 best dqsien dly found for B0: ( 1, 9, 8)
8431 13:58:59.153638 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8432 13:58:59.157209 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 13:58:59.160434 Total UI for P1: 0, mck2ui 16
8434 13:58:59.163669 best dqsien dly found for B1: ( 1, 9, 14)
8435 13:58:59.166786 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8436 13:58:59.170170 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8437 13:58:59.170616
8438 13:58:59.174138 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8439 13:58:59.177384 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8440 13:58:59.180214 [Gating] SW calibration Done
8441 13:58:59.180636 ==
8442 13:58:59.184412 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 13:58:59.187187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 13:58:59.190226 ==
8445 13:58:59.190679 RX Vref Scan: 0
8446 13:58:59.191025
8447 13:58:59.194301 RX Vref 0 -> 0, step: 1
8448 13:58:59.194957
8449 13:58:59.197389 RX Delay 0 -> 252, step: 8
8450 13:58:59.200171 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8451 13:58:59.203220 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8452 13:58:59.206953 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8453 13:58:59.209938 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8454 13:58:59.216744 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8455 13:58:59.219471 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8456 13:58:59.223274 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8457 13:58:59.226392 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8458 13:58:59.229897 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8459 13:58:59.236129 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8460 13:58:59.239547 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8461 13:58:59.242717 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8462 13:58:59.246028 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8463 13:58:59.249243 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8464 13:58:59.255706 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8465 13:58:59.259033 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8466 13:58:59.259114 ==
8467 13:58:59.262501 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 13:58:59.265627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 13:58:59.265708 ==
8470 13:58:59.268853 DQS Delay:
8471 13:58:59.268933 DQS0 = 0, DQS1 = 0
8472 13:58:59.268997 DQM Delay:
8473 13:58:59.272500 DQM0 = 137, DQM1 = 129
8474 13:58:59.272580 DQ Delay:
8475 13:58:59.275416 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8476 13:58:59.282339 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8477 13:58:59.285462 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8478 13:58:59.289181 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8479 13:58:59.289261
8480 13:58:59.289325
8481 13:58:59.289384 ==
8482 13:58:59.291989 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 13:58:59.295463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 13:58:59.295544 ==
8485 13:58:59.295609
8486 13:58:59.295668
8487 13:58:59.299301 TX Vref Scan disable
8488 13:58:59.302104 == TX Byte 0 ==
8489 13:58:59.305514 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8490 13:58:59.308930 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8491 13:58:59.312426 == TX Byte 1 ==
8492 13:58:59.315999 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8493 13:58:59.318585 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8494 13:58:59.318784 ==
8495 13:58:59.321973 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 13:58:59.325231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 13:58:59.328703 ==
8498 13:58:59.340760
8499 13:58:59.343280 TX Vref early break, caculate TX vref
8500 13:58:59.347102 TX Vref=16, minBit 0, minWin=21, winSum=372
8501 13:58:59.350549 TX Vref=18, minBit 0, minWin=23, winSum=385
8502 13:58:59.353823 TX Vref=20, minBit 0, minWin=23, winSum=391
8503 13:58:59.356548 TX Vref=22, minBit 0, minWin=23, winSum=403
8504 13:58:59.359773 TX Vref=24, minBit 2, minWin=24, winSum=408
8505 13:58:59.366433 TX Vref=26, minBit 5, minWin=24, winSum=417
8506 13:58:59.369539 TX Vref=28, minBit 0, minWin=25, winSum=417
8507 13:58:59.373041 TX Vref=30, minBit 0, minWin=23, winSum=406
8508 13:58:59.376351 TX Vref=32, minBit 1, minWin=23, winSum=402
8509 13:58:59.379489 TX Vref=34, minBit 1, minWin=22, winSum=390
8510 13:58:59.386242 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8511 13:58:59.386735
8512 13:58:59.389618 Final TX Range 0 Vref 28
8513 13:58:59.390007
8514 13:58:59.390347 ==
8515 13:58:59.393011 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 13:58:59.396350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 13:58:59.396653 ==
8518 13:58:59.396902
8519 13:58:59.397139
8520 13:58:59.399602 TX Vref Scan disable
8521 13:58:59.406213 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8522 13:58:59.406614 == TX Byte 0 ==
8523 13:58:59.409626 u2DelayCellOfst[0]=18 cells (5 PI)
8524 13:58:59.412098 u2DelayCellOfst[1]=15 cells (4 PI)
8525 13:58:59.416003 u2DelayCellOfst[2]=0 cells (0 PI)
8526 13:58:59.418842 u2DelayCellOfst[3]=7 cells (2 PI)
8527 13:58:59.422198 u2DelayCellOfst[4]=7 cells (2 PI)
8528 13:58:59.425724 u2DelayCellOfst[5]=22 cells (6 PI)
8529 13:58:59.428646 u2DelayCellOfst[6]=22 cells (6 PI)
8530 13:58:59.432072 u2DelayCellOfst[7]=7 cells (2 PI)
8531 13:58:59.435298 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8532 13:58:59.438479 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8533 13:58:59.442228 == TX Byte 1 ==
8534 13:58:59.445581 u2DelayCellOfst[8]=0 cells (0 PI)
8535 13:58:59.448319 u2DelayCellOfst[9]=3 cells (1 PI)
8536 13:58:59.451994 u2DelayCellOfst[10]=11 cells (3 PI)
8537 13:58:59.455349 u2DelayCellOfst[11]=3 cells (1 PI)
8538 13:58:59.455435 u2DelayCellOfst[12]=15 cells (4 PI)
8539 13:58:59.458542 u2DelayCellOfst[13]=18 cells (5 PI)
8540 13:58:59.461775 u2DelayCellOfst[14]=18 cells (5 PI)
8541 13:58:59.465337 u2DelayCellOfst[15]=18 cells (5 PI)
8542 13:58:59.471245 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8543 13:58:59.475148 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8544 13:58:59.478101 DramC Write-DBI on
8545 13:58:59.478255 ==
8546 13:58:59.481287 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 13:58:59.484645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 13:58:59.484794 ==
8549 13:58:59.484911
8550 13:58:59.485021
8551 13:58:59.487610 TX Vref Scan disable
8552 13:58:59.487819 == TX Byte 0 ==
8553 13:58:59.494436 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8554 13:58:59.494585 == TX Byte 1 ==
8555 13:58:59.497682 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8556 13:58:59.500801 DramC Write-DBI off
8557 13:58:59.500950
8558 13:58:59.501067 [DATLAT]
8559 13:58:59.504332 Freq=1600, CH1 RK0
8560 13:58:59.504480
8561 13:58:59.504596 DATLAT Default: 0xf
8562 13:58:59.507524 0, 0xFFFF, sum = 0
8563 13:58:59.507675 1, 0xFFFF, sum = 0
8564 13:58:59.510873 2, 0xFFFF, sum = 0
8565 13:58:59.514092 3, 0xFFFF, sum = 0
8566 13:58:59.514172 4, 0xFFFF, sum = 0
8567 13:58:59.517757 5, 0xFFFF, sum = 0
8568 13:58:59.517869 6, 0xFFFF, sum = 0
8569 13:58:59.520973 7, 0xFFFF, sum = 0
8570 13:58:59.521073 8, 0xFFFF, sum = 0
8571 13:58:59.524527 9, 0xFFFF, sum = 0
8572 13:58:59.524601 10, 0xFFFF, sum = 0
8573 13:58:59.528405 11, 0xFFFF, sum = 0
8574 13:58:59.528511 12, 0xFFFF, sum = 0
8575 13:58:59.530687 13, 0xFFFF, sum = 0
8576 13:58:59.530786 14, 0x0, sum = 1
8577 13:58:59.534124 15, 0x0, sum = 2
8578 13:58:59.534194 16, 0x0, sum = 3
8579 13:58:59.537918 17, 0x0, sum = 4
8580 13:58:59.538016 best_step = 15
8581 13:58:59.538107
8582 13:58:59.538193 ==
8583 13:58:59.540999 Dram Type= 6, Freq= 0, CH_1, rank 0
8584 13:58:59.544565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8585 13:58:59.547221 ==
8586 13:58:59.547294 RX Vref Scan: 1
8587 13:58:59.547358
8588 13:58:59.550662 Set Vref Range= 24 -> 127
8589 13:58:59.550742
8590 13:58:59.553941 RX Vref 24 -> 127, step: 1
8591 13:58:59.554032
8592 13:58:59.554097 RX Delay 11 -> 252, step: 4
8593 13:58:59.554171
8594 13:58:59.557674 Set Vref, RX VrefLevel [Byte0]: 24
8595 13:58:59.560666 [Byte1]: 24
8596 13:58:59.564984
8597 13:58:59.565064 Set Vref, RX VrefLevel [Byte0]: 25
8598 13:58:59.568169 [Byte1]: 25
8599 13:58:59.572607
8600 13:58:59.572686 Set Vref, RX VrefLevel [Byte0]: 26
8601 13:58:59.575188 [Byte1]: 26
8602 13:58:59.579896
8603 13:58:59.579997 Set Vref, RX VrefLevel [Byte0]: 27
8604 13:58:59.583071 [Byte1]: 27
8605 13:58:59.587045
8606 13:58:59.587116 Set Vref, RX VrefLevel [Byte0]: 28
8607 13:58:59.591095 [Byte1]: 28
8608 13:58:59.594685
8609 13:58:59.594757 Set Vref, RX VrefLevel [Byte0]: 29
8610 13:58:59.598600 [Byte1]: 29
8611 13:58:59.603036
8612 13:58:59.603106 Set Vref, RX VrefLevel [Byte0]: 30
8613 13:58:59.605665 [Byte1]: 30
8614 13:58:59.610202
8615 13:58:59.610282 Set Vref, RX VrefLevel [Byte0]: 31
8616 13:58:59.613459 [Byte1]: 31
8617 13:58:59.617779
8618 13:58:59.617852 Set Vref, RX VrefLevel [Byte0]: 32
8619 13:58:59.620913 [Byte1]: 32
8620 13:58:59.625548
8621 13:58:59.625651 Set Vref, RX VrefLevel [Byte0]: 33
8622 13:58:59.628389 [Byte1]: 33
8623 13:58:59.633024
8624 13:58:59.633127 Set Vref, RX VrefLevel [Byte0]: 34
8625 13:58:59.636376 [Byte1]: 34
8626 13:58:59.640661
8627 13:58:59.640760 Set Vref, RX VrefLevel [Byte0]: 35
8628 13:58:59.643866 [Byte1]: 35
8629 13:58:59.648285
8630 13:58:59.648383 Set Vref, RX VrefLevel [Byte0]: 36
8631 13:58:59.651687 [Byte1]: 36
8632 13:58:59.655825
8633 13:58:59.655929 Set Vref, RX VrefLevel [Byte0]: 37
8634 13:58:59.659112 [Byte1]: 37
8635 13:58:59.663189
8636 13:58:59.663294 Set Vref, RX VrefLevel [Byte0]: 38
8637 13:58:59.666912 [Byte1]: 38
8638 13:58:59.670808
8639 13:58:59.670906 Set Vref, RX VrefLevel [Byte0]: 39
8640 13:58:59.674064 [Byte1]: 39
8641 13:58:59.678900
8642 13:58:59.678982 Set Vref, RX VrefLevel [Byte0]: 40
8643 13:58:59.681654 [Byte1]: 40
8644 13:58:59.686356
8645 13:58:59.686461 Set Vref, RX VrefLevel [Byte0]: 41
8646 13:58:59.689376 [Byte1]: 41
8647 13:58:59.694250
8648 13:58:59.694350 Set Vref, RX VrefLevel [Byte0]: 42
8649 13:58:59.697120 [Byte1]: 42
8650 13:58:59.701635
8651 13:58:59.701736 Set Vref, RX VrefLevel [Byte0]: 43
8652 13:58:59.704518 [Byte1]: 43
8653 13:58:59.709061
8654 13:58:59.709138 Set Vref, RX VrefLevel [Byte0]: 44
8655 13:58:59.712539 [Byte1]: 44
8656 13:58:59.716748
8657 13:58:59.716823 Set Vref, RX VrefLevel [Byte0]: 45
8658 13:58:59.719852 [Byte1]: 45
8659 13:58:59.724431
8660 13:58:59.724500 Set Vref, RX VrefLevel [Byte0]: 46
8661 13:58:59.727687 [Byte1]: 46
8662 13:58:59.732001
8663 13:58:59.732068 Set Vref, RX VrefLevel [Byte0]: 47
8664 13:58:59.734952 [Byte1]: 47
8665 13:58:59.739720
8666 13:58:59.739805 Set Vref, RX VrefLevel [Byte0]: 48
8667 13:58:59.742930 [Byte1]: 48
8668 13:58:59.747444
8669 13:58:59.747613 Set Vref, RX VrefLevel [Byte0]: 49
8670 13:58:59.751022 [Byte1]: 49
8671 13:58:59.755029
8672 13:58:59.755209 Set Vref, RX VrefLevel [Byte0]: 50
8673 13:58:59.758429 [Byte1]: 50
8674 13:58:59.762622
8675 13:58:59.762769 Set Vref, RX VrefLevel [Byte0]: 51
8676 13:58:59.765780 [Byte1]: 51
8677 13:58:59.769977
8678 13:58:59.770175 Set Vref, RX VrefLevel [Byte0]: 52
8679 13:58:59.776934 [Byte1]: 52
8680 13:58:59.777104
8681 13:58:59.779547 Set Vref, RX VrefLevel [Byte0]: 53
8682 13:58:59.782901 [Byte1]: 53
8683 13:58:59.783094
8684 13:58:59.786540 Set Vref, RX VrefLevel [Byte0]: 54
8685 13:58:59.790230 [Byte1]: 54
8686 13:58:59.792829
8687 13:58:59.793016 Set Vref, RX VrefLevel [Byte0]: 55
8688 13:58:59.796392 [Byte1]: 55
8689 13:58:59.800785
8690 13:58:59.801046 Set Vref, RX VrefLevel [Byte0]: 56
8691 13:58:59.803747 [Byte1]: 56
8692 13:58:59.808269
8693 13:58:59.808469 Set Vref, RX VrefLevel [Byte0]: 57
8694 13:58:59.811939 [Byte1]: 57
8695 13:58:59.815664
8696 13:58:59.815875 Set Vref, RX VrefLevel [Byte0]: 58
8697 13:58:59.818834 [Byte1]: 58
8698 13:58:59.823392
8699 13:58:59.823595 Set Vref, RX VrefLevel [Byte0]: 59
8700 13:58:59.827440 [Byte1]: 59
8701 13:58:59.830986
8702 13:58:59.831192 Set Vref, RX VrefLevel [Byte0]: 60
8703 13:58:59.834127 [Byte1]: 60
8704 13:58:59.838580
8705 13:58:59.838818 Set Vref, RX VrefLevel [Byte0]: 61
8706 13:58:59.842437 [Byte1]: 61
8707 13:58:59.846644
8708 13:58:59.846856 Set Vref, RX VrefLevel [Byte0]: 62
8709 13:58:59.849539 [Byte1]: 62
8710 13:58:59.854248
8711 13:58:59.854464 Set Vref, RX VrefLevel [Byte0]: 63
8712 13:58:59.857382 [Byte1]: 63
8713 13:58:59.861990
8714 13:58:59.862193 Set Vref, RX VrefLevel [Byte0]: 64
8715 13:58:59.865074 [Byte1]: 64
8716 13:58:59.869210
8717 13:58:59.869545 Set Vref, RX VrefLevel [Byte0]: 65
8718 13:58:59.873177 [Byte1]: 65
8719 13:58:59.876870
8720 13:58:59.877172 Set Vref, RX VrefLevel [Byte0]: 66
8721 13:58:59.880193 [Byte1]: 66
8722 13:58:59.884908
8723 13:58:59.885422 Set Vref, RX VrefLevel [Byte0]: 67
8724 13:58:59.888200 [Byte1]: 67
8725 13:58:59.892466
8726 13:58:59.892892 Set Vref, RX VrefLevel [Byte0]: 68
8727 13:58:59.896017 [Byte1]: 68
8728 13:58:59.900007
8729 13:58:59.900571 Set Vref, RX VrefLevel [Byte0]: 69
8730 13:58:59.903280 [Byte1]: 69
8731 13:58:59.907443
8732 13:58:59.908002 Set Vref, RX VrefLevel [Byte0]: 70
8733 13:58:59.910952 [Byte1]: 70
8734 13:58:59.915590
8735 13:58:59.916159 Set Vref, RX VrefLevel [Byte0]: 71
8736 13:58:59.918561 [Byte1]: 71
8737 13:58:59.922998
8738 13:58:59.923566 Set Vref, RX VrefLevel [Byte0]: 72
8739 13:58:59.926127 [Byte1]: 72
8740 13:58:59.930314
8741 13:58:59.930942 Final RX Vref Byte 0 = 52 to rank0
8742 13:58:59.933598 Final RX Vref Byte 1 = 61 to rank0
8743 13:58:59.937240 Final RX Vref Byte 0 = 52 to rank1
8744 13:58:59.940389 Final RX Vref Byte 1 = 61 to rank1==
8745 13:58:59.944094 Dram Type= 6, Freq= 0, CH_1, rank 0
8746 13:58:59.951054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8747 13:58:59.951629 ==
8748 13:58:59.952000 DQS Delay:
8749 13:58:59.952344 DQS0 = 0, DQS1 = 0
8750 13:58:59.953670 DQM Delay:
8751 13:58:59.954130 DQM0 = 134, DQM1 = 127
8752 13:58:59.957128 DQ Delay:
8753 13:58:59.960100 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8754 13:58:59.963473 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8755 13:58:59.967195 DQ8 =114, DQ9 =114, DQ10 =130, DQ11 =118
8756 13:58:59.970908 DQ12 =136, DQ13 =134, DQ14 =138, DQ15 =138
8757 13:58:59.971511
8758 13:58:59.971880
8759 13:58:59.972221
8760 13:58:59.973197 [DramC_TX_OE_Calibration] TA2
8761 13:58:59.976864 Original DQ_B0 (3 6) =30, OEN = 27
8762 13:58:59.979919 Original DQ_B1 (3 6) =30, OEN = 27
8763 13:58:59.983210 24, 0x0, End_B0=24 End_B1=24
8764 13:58:59.983683 25, 0x0, End_B0=25 End_B1=25
8765 13:58:59.986882 26, 0x0, End_B0=26 End_B1=26
8766 13:58:59.989767 27, 0x0, End_B0=27 End_B1=27
8767 13:58:59.992936 28, 0x0, End_B0=28 End_B1=28
8768 13:58:59.996637 29, 0x0, End_B0=29 End_B1=29
8769 13:58:59.997206 30, 0x0, End_B0=30 End_B1=30
8770 13:58:59.999497 31, 0x4141, End_B0=30 End_B1=30
8771 13:59:00.003506 Byte0 end_step=30 best_step=27
8772 13:59:00.006133 Byte1 end_step=30 best_step=27
8773 13:59:00.009738 Byte0 TX OE(2T, 0.5T) = (3, 3)
8774 13:59:00.013471 Byte1 TX OE(2T, 0.5T) = (3, 3)
8775 13:59:00.014037
8776 13:59:00.014404
8777 13:59:00.019962 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d12, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
8778 13:59:00.022730 CH1 RK0: MR19=303, MR18=1D12
8779 13:59:00.029149 CH1_RK0: MR19=0x303, MR18=0x1D12, DQSOSC=395, MR23=63, INC=23, DEC=15
8780 13:59:00.029719
8781 13:59:00.032554 ----->DramcWriteLeveling(PI) begin...
8782 13:59:00.033138 ==
8783 13:59:00.035811 Dram Type= 6, Freq= 0, CH_1, rank 1
8784 13:59:00.039135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 13:59:00.039708 ==
8786 13:59:00.042434 Write leveling (Byte 0): 24 => 24
8787 13:59:00.045845 Write leveling (Byte 1): 28 => 28
8788 13:59:00.048935 DramcWriteLeveling(PI) end<-----
8789 13:59:00.049409
8790 13:59:00.049883 ==
8791 13:59:00.052464 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 13:59:00.058527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 13:59:00.059046 ==
8794 13:59:00.059523 [Gating] SW mode calibration
8795 13:59:00.069048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8796 13:59:00.072068 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8797 13:59:00.075367 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 13:59:00.082064 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 13:59:00.086056 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 13:59:00.088572 1 4 12 | B1->B0 | 3030 2322 | 1 1 | (1 1) (1 1)
8801 13:59:00.095740 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 13:59:00.098195 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 13:59:00.101782 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 13:59:00.108167 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 13:59:00.112191 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 13:59:00.115045 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 13:59:00.121467 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 13:59:00.124832 1 5 12 | B1->B0 | 3131 3333 | 0 0 | (0 1) (0 1)
8809 13:59:00.128881 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8810 13:59:00.134981 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 13:59:00.137932 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 13:59:00.141547 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 13:59:00.147802 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 13:59:00.151198 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 13:59:00.154555 1 6 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8816 13:59:00.161238 1 6 12 | B1->B0 | 4646 3333 | 0 1 | (0 0) (0 0)
8817 13:59:00.164944 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 13:59:00.168152 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 13:59:00.174478 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 13:59:00.177860 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 13:59:00.181120 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 13:59:00.187400 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 13:59:00.190843 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8824 13:59:00.194409 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8825 13:59:00.200906 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 13:59:00.203985 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 13:59:00.207199 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 13:59:00.214229 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 13:59:00.217093 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 13:59:00.220503 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 13:59:00.227104 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 13:59:00.230763 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 13:59:00.233551 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 13:59:00.240445 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 13:59:00.243637 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 13:59:00.246849 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 13:59:00.253089 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 13:59:00.256267 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 13:59:00.260030 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 13:59:00.266488 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8841 13:59:00.270127 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 13:59:00.273657 Total UI for P1: 0, mck2ui 16
8843 13:59:00.276736 best dqsien dly found for B0: ( 1, 9, 12)
8844 13:59:00.279896 Total UI for P1: 0, mck2ui 16
8845 13:59:00.282744 best dqsien dly found for B1: ( 1, 9, 12)
8846 13:59:00.286516 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8847 13:59:00.289454 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8848 13:59:00.289959
8849 13:59:00.292573 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8850 13:59:00.299480 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8851 13:59:00.300045 [Gating] SW calibration Done
8852 13:59:00.302837 ==
8853 13:59:00.303411 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 13:59:00.309705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 13:59:00.310277 ==
8856 13:59:00.310817 RX Vref Scan: 0
8857 13:59:00.311273
8858 13:59:00.312460 RX Vref 0 -> 0, step: 1
8859 13:59:00.312926
8860 13:59:00.316030 RX Delay 0 -> 252, step: 8
8861 13:59:00.319262 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8862 13:59:00.322489 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8863 13:59:00.325993 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8864 13:59:00.332712 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8865 13:59:00.335632 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8866 13:59:00.339582 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8867 13:59:00.342502 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8868 13:59:00.345862 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8869 13:59:00.352086 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8870 13:59:00.355475 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8871 13:59:00.358518 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8872 13:59:00.362396 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8873 13:59:00.368870 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8874 13:59:00.371874 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8875 13:59:00.375307 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8876 13:59:00.378313 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8877 13:59:00.378914 ==
8878 13:59:00.381834 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 13:59:00.388126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 13:59:00.388760 ==
8881 13:59:00.389220 DQS Delay:
8882 13:59:00.389819 DQS0 = 0, DQS1 = 0
8883 13:59:00.391365 DQM Delay:
8884 13:59:00.391867 DQM0 = 137, DQM1 = 129
8885 13:59:00.395169 DQ Delay:
8886 13:59:00.398159 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8887 13:59:00.401701 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8888 13:59:00.404891 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8889 13:59:00.408144 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8890 13:59:00.408443
8891 13:59:00.408680
8892 13:59:00.408900 ==
8893 13:59:00.411432 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 13:59:00.414279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 13:59:00.417681 ==
8896 13:59:00.417762
8897 13:59:00.417826
8898 13:59:00.417884 TX Vref Scan disable
8899 13:59:00.420939 == TX Byte 0 ==
8900 13:59:00.424278 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8901 13:59:00.427822 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8902 13:59:00.431007 == TX Byte 1 ==
8903 13:59:00.434235 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8904 13:59:00.437570 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8905 13:59:00.437652 ==
8906 13:59:00.441134 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 13:59:00.447493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 13:59:00.447574 ==
8909 13:59:00.459973
8910 13:59:00.463120 TX Vref early break, caculate TX vref
8911 13:59:00.466129 TX Vref=16, minBit 1, minWin=22, winSum=388
8912 13:59:00.469595 TX Vref=18, minBit 8, minWin=23, winSum=397
8913 13:59:00.473347 TX Vref=20, minBit 0, minWin=23, winSum=411
8914 13:59:00.476323 TX Vref=22, minBit 0, minWin=25, winSum=417
8915 13:59:00.479545 TX Vref=24, minBit 15, minWin=25, winSum=424
8916 13:59:00.486198 TX Vref=26, minBit 1, minWin=26, winSum=429
8917 13:59:00.489380 TX Vref=28, minBit 1, minWin=25, winSum=423
8918 13:59:00.492351 TX Vref=30, minBit 0, minWin=26, winSum=424
8919 13:59:00.495996 TX Vref=32, minBit 1, minWin=24, winSum=416
8920 13:59:00.499203 TX Vref=34, minBit 0, minWin=23, winSum=402
8921 13:59:00.505945 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 26
8922 13:59:00.506119
8923 13:59:00.509307 Final TX Range 0 Vref 26
8924 13:59:00.509483
8925 13:59:00.509571 ==
8926 13:59:00.513226 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 13:59:00.515883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 13:59:00.516030 ==
8929 13:59:00.516127
8930 13:59:00.516227
8931 13:59:00.519026 TX Vref Scan disable
8932 13:59:00.526007 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8933 13:59:00.526231 == TX Byte 0 ==
8934 13:59:00.529669 u2DelayCellOfst[0]=18 cells (5 PI)
8935 13:59:00.533330 u2DelayCellOfst[1]=15 cells (4 PI)
8936 13:59:00.535914 u2DelayCellOfst[2]=0 cells (0 PI)
8937 13:59:00.539274 u2DelayCellOfst[3]=7 cells (2 PI)
8938 13:59:00.542368 u2DelayCellOfst[4]=7 cells (2 PI)
8939 13:59:00.545855 u2DelayCellOfst[5]=22 cells (6 PI)
8940 13:59:00.548994 u2DelayCellOfst[6]=22 cells (6 PI)
8941 13:59:00.553093 u2DelayCellOfst[7]=3 cells (1 PI)
8942 13:59:00.555805 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8943 13:59:00.558924 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8944 13:59:00.562215 == TX Byte 1 ==
8945 13:59:00.565830 u2DelayCellOfst[8]=0 cells (0 PI)
8946 13:59:00.566492 u2DelayCellOfst[9]=3 cells (1 PI)
8947 13:59:00.568711 u2DelayCellOfst[10]=11 cells (3 PI)
8948 13:59:00.572197 u2DelayCellOfst[11]=3 cells (1 PI)
8949 13:59:00.575448 u2DelayCellOfst[12]=15 cells (4 PI)
8950 13:59:00.579075 u2DelayCellOfst[13]=18 cells (5 PI)
8951 13:59:00.582186 u2DelayCellOfst[14]=18 cells (5 PI)
8952 13:59:00.586039 u2DelayCellOfst[15]=18 cells (5 PI)
8953 13:59:00.592157 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8954 13:59:00.595607 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8955 13:59:00.596155 DramC Write-DBI on
8956 13:59:00.596733 ==
8957 13:59:00.598215 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 13:59:00.604981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 13:59:00.605090 ==
8960 13:59:00.605186
8961 13:59:00.605277
8962 13:59:00.605364 TX Vref Scan disable
8963 13:59:00.609829 == TX Byte 0 ==
8964 13:59:00.612181 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8965 13:59:00.615349 == TX Byte 1 ==
8966 13:59:00.618983 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8967 13:59:00.622065 DramC Write-DBI off
8968 13:59:00.622145
8969 13:59:00.622215 [DATLAT]
8970 13:59:00.622275 Freq=1600, CH1 RK1
8971 13:59:00.622333
8972 13:59:00.625542 DATLAT Default: 0xf
8973 13:59:00.628554 0, 0xFFFF, sum = 0
8974 13:59:00.628661 1, 0xFFFF, sum = 0
8975 13:59:00.632034 2, 0xFFFF, sum = 0
8976 13:59:00.632141 3, 0xFFFF, sum = 0
8977 13:59:00.635235 4, 0xFFFF, sum = 0
8978 13:59:00.635336 5, 0xFFFF, sum = 0
8979 13:59:00.638713 6, 0xFFFF, sum = 0
8980 13:59:00.638826 7, 0xFFFF, sum = 0
8981 13:59:00.641663 8, 0xFFFF, sum = 0
8982 13:59:00.641775 9, 0xFFFF, sum = 0
8983 13:59:00.645370 10, 0xFFFF, sum = 0
8984 13:59:00.645479 11, 0xFFFF, sum = 0
8985 13:59:00.648487 12, 0xFFFF, sum = 0
8986 13:59:00.648598 13, 0xFFFF, sum = 0
8987 13:59:00.652060 14, 0x0, sum = 1
8988 13:59:00.652166 15, 0x0, sum = 2
8989 13:59:00.654850 16, 0x0, sum = 3
8990 13:59:00.654961 17, 0x0, sum = 4
8991 13:59:00.658204 best_step = 15
8992 13:59:00.658308
8993 13:59:00.658400 ==
8994 13:59:00.661475 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 13:59:00.665763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 13:59:00.665870 ==
8997 13:59:00.668652 RX Vref Scan: 0
8998 13:59:00.668723
8999 13:59:00.668783 RX Vref 0 -> 0, step: 1
9000 13:59:00.668840
9001 13:59:00.671465 RX Delay 11 -> 252, step: 4
9002 13:59:00.678329 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9003 13:59:00.681258 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9004 13:59:00.684644 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9005 13:59:00.688004 iDelay=203, Bit 3, Center 132 (83 ~ 182) 100
9006 13:59:00.691542 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9007 13:59:00.697758 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9008 13:59:00.701176 iDelay=203, Bit 6, Center 148 (95 ~ 202) 108
9009 13:59:00.704671 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9010 13:59:00.708122 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9011 13:59:00.711461 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9012 13:59:00.717860 iDelay=203, Bit 10, Center 128 (71 ~ 186) 116
9013 13:59:00.721728 iDelay=203, Bit 11, Center 118 (63 ~ 174) 112
9014 13:59:00.724794 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9015 13:59:00.728045 iDelay=203, Bit 13, Center 132 (79 ~ 186) 108
9016 13:59:00.735112 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9017 13:59:00.737779 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9018 13:59:00.737910 ==
9019 13:59:00.741436 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 13:59:00.744644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 13:59:00.744862 ==
9022 13:59:00.744980 DQS Delay:
9023 13:59:00.747847 DQS0 = 0, DQS1 = 0
9024 13:59:00.748082 DQM Delay:
9025 13:59:00.751008 DQM0 = 134, DQM1 = 126
9026 13:59:00.751240 DQ Delay:
9027 13:59:00.754372 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
9028 13:59:00.757651 DQ4 =134, DQ5 =146, DQ6 =148, DQ7 =130
9029 13:59:00.761226 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =118
9030 13:59:00.764845 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =138
9031 13:59:00.767953
9032 13:59:00.768341
9033 13:59:00.768583
9034 13:59:00.768799 [DramC_TX_OE_Calibration] TA2
9035 13:59:00.771049 Original DQ_B0 (3 6) =30, OEN = 27
9036 13:59:00.774524 Original DQ_B1 (3 6) =30, OEN = 27
9037 13:59:00.777772 24, 0x0, End_B0=24 End_B1=24
9038 13:59:00.781195 25, 0x0, End_B0=25 End_B1=25
9039 13:59:00.784655 26, 0x0, End_B0=26 End_B1=26
9040 13:59:00.785050 27, 0x0, End_B0=27 End_B1=27
9041 13:59:00.788162 28, 0x0, End_B0=28 End_B1=28
9042 13:59:00.791172 29, 0x0, End_B0=29 End_B1=29
9043 13:59:00.794889 30, 0x0, End_B0=30 End_B1=30
9044 13:59:00.798263 31, 0x4545, End_B0=30 End_B1=30
9045 13:59:00.801102 Byte0 end_step=30 best_step=27
9046 13:59:00.801492 Byte1 end_step=30 best_step=27
9047 13:59:00.804720 Byte0 TX OE(2T, 0.5T) = (3, 3)
9048 13:59:00.807820 Byte1 TX OE(2T, 0.5T) = (3, 3)
9049 13:59:00.808301
9050 13:59:00.808606
9051 13:59:00.817823 [DQSOSCAuto] RK1, (LSB)MR18= 0x100c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
9052 13:59:00.818368 CH1 RK1: MR19=303, MR18=100C
9053 13:59:00.824344 CH1_RK1: MR19=0x303, MR18=0x100C, DQSOSC=401, MR23=63, INC=22, DEC=15
9054 13:59:00.827332 [RxdqsGatingPostProcess] freq 1600
9055 13:59:00.833981 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9056 13:59:00.837961 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 13:59:00.840414 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 13:59:00.844047 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 13:59:00.847291 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 13:59:00.850892 best DQS0 dly(2T, 0.5T) = (1, 1)
9061 13:59:00.851444 best DQS1 dly(2T, 0.5T) = (1, 1)
9062 13:59:00.854221 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9063 13:59:00.857231 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9064 13:59:00.860377 Pre-setting of DQS Precalculation
9065 13:59:00.867047 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9066 13:59:00.873394 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9067 13:59:00.880447 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9068 13:59:00.880996
9069 13:59:00.881380
9070 13:59:00.883817 [Calibration Summary] 3200 Mbps
9071 13:59:00.884273 CH 0, Rank 0
9072 13:59:00.886711 SW Impedance : PASS
9073 13:59:00.890264 DUTY Scan : NO K
9074 13:59:00.890758 ZQ Calibration : PASS
9075 13:59:00.893266 Jitter Meter : NO K
9076 13:59:00.896863 CBT Training : PASS
9077 13:59:00.897322 Write leveling : PASS
9078 13:59:00.900021 RX DQS gating : PASS
9079 13:59:00.903571 RX DQ/DQS(RDDQC) : PASS
9080 13:59:00.903984 TX DQ/DQS : PASS
9081 13:59:00.906964 RX DATLAT : PASS
9082 13:59:00.909958 RX DQ/DQS(Engine): PASS
9083 13:59:00.910478 TX OE : PASS
9084 13:59:00.913409 All Pass.
9085 13:59:00.913966
9086 13:59:00.914335 CH 0, Rank 1
9087 13:59:00.916740 SW Impedance : PASS
9088 13:59:00.917296 DUTY Scan : NO K
9089 13:59:00.920153 ZQ Calibration : PASS
9090 13:59:00.923941 Jitter Meter : NO K
9091 13:59:00.924506 CBT Training : PASS
9092 13:59:00.926362 Write leveling : PASS
9093 13:59:00.929635 RX DQS gating : PASS
9094 13:59:00.930198 RX DQ/DQS(RDDQC) : PASS
9095 13:59:00.933044 TX DQ/DQS : PASS
9096 13:59:00.936247 RX DATLAT : PASS
9097 13:59:00.936812 RX DQ/DQS(Engine): PASS
9098 13:59:00.939821 TX OE : PASS
9099 13:59:00.940385 All Pass.
9100 13:59:00.940751
9101 13:59:00.942757 CH 1, Rank 0
9102 13:59:00.943239 SW Impedance : PASS
9103 13:59:00.946061 DUTY Scan : NO K
9104 13:59:00.949439 ZQ Calibration : PASS
9105 13:59:00.950003 Jitter Meter : NO K
9106 13:59:00.952735 CBT Training : PASS
9107 13:59:00.955780 Write leveling : PASS
9108 13:59:00.956278 RX DQS gating : PASS
9109 13:59:00.959137 RX DQ/DQS(RDDQC) : PASS
9110 13:59:00.959594 TX DQ/DQS : PASS
9111 13:59:00.962571 RX DATLAT : PASS
9112 13:59:00.966187 RX DQ/DQS(Engine): PASS
9113 13:59:00.966817 TX OE : PASS
9114 13:59:00.969473 All Pass.
9115 13:59:00.970094
9116 13:59:00.970474 CH 1, Rank 1
9117 13:59:00.972418 SW Impedance : PASS
9118 13:59:00.972883 DUTY Scan : NO K
9119 13:59:00.975717 ZQ Calibration : PASS
9120 13:59:00.979242 Jitter Meter : NO K
9121 13:59:00.979804 CBT Training : PASS
9122 13:59:00.982299 Write leveling : PASS
9123 13:59:00.986372 RX DQS gating : PASS
9124 13:59:00.987013 RX DQ/DQS(RDDQC) : PASS
9125 13:59:00.988563 TX DQ/DQS : PASS
9126 13:59:00.992250 RX DATLAT : PASS
9127 13:59:00.992709 RX DQ/DQS(Engine): PASS
9128 13:59:00.995418 TX OE : PASS
9129 13:59:00.995879 All Pass.
9130 13:59:00.996241
9131 13:59:00.998675 DramC Write-DBI on
9132 13:59:01.002295 PER_BANK_REFRESH: Hybrid Mode
9133 13:59:01.002902 TX_TRACKING: ON
9134 13:59:01.012392 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9135 13:59:01.018677 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9136 13:59:01.025612 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9137 13:59:01.031865 [FAST_K] Save calibration result to emmc
9138 13:59:01.032589 sync common calibartion params.
9139 13:59:01.035156 sync cbt_mode0:1, 1:1
9140 13:59:01.038218 dram_init: ddr_geometry: 2
9141 13:59:01.041574 dram_init: ddr_geometry: 2
9142 13:59:01.042175 dram_init: ddr_geometry: 2
9143 13:59:01.044803 0:dram_rank_size:100000000
9144 13:59:01.048314 1:dram_rank_size:100000000
9145 13:59:01.051714 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9146 13:59:01.054354 DFS_SHUFFLE_HW_MODE: ON
9147 13:59:01.057858 dramc_set_vcore_voltage set vcore to 725000
9148 13:59:01.061182 Read voltage for 1600, 0
9149 13:59:01.061661 Vio18 = 0
9150 13:59:01.064473 Vcore = 725000
9151 13:59:01.064896 Vdram = 0
9152 13:59:01.065225 Vddq = 0
9153 13:59:01.065532 Vmddr = 0
9154 13:59:01.067630 switch to 3200 Mbps bootup
9155 13:59:01.071338 [DramcRunTimeConfig]
9156 13:59:01.071601 PHYPLL
9157 13:59:01.074672 DPM_CONTROL_AFTERK: ON
9158 13:59:01.074979 PER_BANK_REFRESH: ON
9159 13:59:01.077284 REFRESH_OVERHEAD_REDUCTION: ON
9160 13:59:01.080986 CMD_PICG_NEW_MODE: OFF
9161 13:59:01.081371 XRTWTW_NEW_MODE: ON
9162 13:59:01.084138 XRTRTR_NEW_MODE: ON
9163 13:59:01.084432 TX_TRACKING: ON
9164 13:59:01.087623 RDSEL_TRACKING: OFF
9165 13:59:01.090707 DQS Precalculation for DVFS: ON
9166 13:59:01.091013 RX_TRACKING: OFF
9167 13:59:01.093854 HW_GATING DBG: ON
9168 13:59:01.094144 ZQCS_ENABLE_LP4: ON
9169 13:59:01.097248 RX_PICG_NEW_MODE: ON
9170 13:59:01.097537 TX_PICG_NEW_MODE: ON
9171 13:59:01.100356 ENABLE_RX_DCM_DPHY: ON
9172 13:59:01.103785 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9173 13:59:01.107362 DUMMY_READ_FOR_TRACKING: OFF
9174 13:59:01.107652 !!! SPM_CONTROL_AFTERK: OFF
9175 13:59:01.110633 !!! SPM could not control APHY
9176 13:59:01.113712 IMPEDANCE_TRACKING: ON
9177 13:59:01.114177 TEMP_SENSOR: ON
9178 13:59:01.117077 HW_SAVE_FOR_SR: OFF
9179 13:59:01.119960 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9180 13:59:01.123687 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9181 13:59:01.127407 Read ODT Tracking: ON
9182 13:59:01.127708 Refresh Rate DeBounce: ON
9183 13:59:01.130128 DFS_NO_QUEUE_FLUSH: ON
9184 13:59:01.133240 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9185 13:59:01.136583 ENABLE_DFS_RUNTIME_MRW: OFF
9186 13:59:01.136943 DDR_RESERVE_NEW_MODE: ON
9187 13:59:01.139931 MR_CBT_SWITCH_FREQ: ON
9188 13:59:01.143685 =========================
9189 13:59:01.160935 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9190 13:59:01.164573 dram_init: ddr_geometry: 2
9191 13:59:01.183007 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9192 13:59:01.185616 dram_init: dram init end (result: 0)
9193 13:59:01.192338 DRAM-K: Full calibration passed in 24614 msecs
9194 13:59:01.195217 MRC: failed to locate region type 0.
9195 13:59:01.195776 DRAM rank0 size:0x100000000,
9196 13:59:01.198544 DRAM rank1 size=0x100000000
9197 13:59:01.208595 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9198 13:59:01.215526 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9199 13:59:01.221936 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9200 13:59:01.231296 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9201 13:59:01.231379 DRAM rank0 size:0x100000000,
9202 13:59:01.234867 DRAM rank1 size=0x100000000
9203 13:59:01.234948 CBMEM:
9204 13:59:01.238577 IMD: root @ 0xfffff000 254 entries.
9205 13:59:01.241576 IMD: root @ 0xffffec00 62 entries.
9206 13:59:01.244717 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9207 13:59:01.251056 WARNING: RO_VPD is uninitialized or empty.
9208 13:59:01.254183 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9209 13:59:01.262462 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9210 13:59:01.275374 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9211 13:59:01.286295 BS: romstage times (exec / console): total (unknown) / 24108 ms
9212 13:59:01.286377
9213 13:59:01.286441
9214 13:59:01.296003 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9215 13:59:01.299578 ARM64: Exception handlers installed.
9216 13:59:01.302750 ARM64: Testing exception
9217 13:59:01.306095 ARM64: Done test exception
9218 13:59:01.306172 Enumerating buses...
9219 13:59:01.309498 Show all devs... Before device enumeration.
9220 13:59:01.312739 Root Device: enabled 1
9221 13:59:01.316704 CPU_CLUSTER: 0: enabled 1
9222 13:59:01.316777 CPU: 00: enabled 1
9223 13:59:01.319446 Compare with tree...
9224 13:59:01.319519 Root Device: enabled 1
9225 13:59:01.323008 CPU_CLUSTER: 0: enabled 1
9226 13:59:01.326027 CPU: 00: enabled 1
9227 13:59:01.326099 Root Device scanning...
9228 13:59:01.329925 scan_static_bus for Root Device
9229 13:59:01.333242 CPU_CLUSTER: 0 enabled
9230 13:59:01.336194 scan_static_bus for Root Device done
9231 13:59:01.339105 scan_bus: bus Root Device finished in 8 msecs
9232 13:59:01.339182 done
9233 13:59:01.345544 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9234 13:59:01.349575 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9235 13:59:01.356049 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9236 13:59:01.359421 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9237 13:59:01.362462 Allocating resources...
9238 13:59:01.365446 Reading resources...
9239 13:59:01.369401 Root Device read_resources bus 0 link: 0
9240 13:59:01.372138 DRAM rank0 size:0x100000000,
9241 13:59:01.372234 DRAM rank1 size=0x100000000
9242 13:59:01.378550 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9243 13:59:01.378673 CPU: 00 missing read_resources
9244 13:59:01.385237 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9245 13:59:01.388660 Root Device read_resources bus 0 link: 0 done
9246 13:59:01.391727 Done reading resources.
9247 13:59:01.395818 Show resources in subtree (Root Device)...After reading.
9248 13:59:01.398560 Root Device child on link 0 CPU_CLUSTER: 0
9249 13:59:01.402764 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 13:59:01.411947 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 13:59:01.412032 CPU: 00
9252 13:59:01.414945 Root Device assign_resources, bus 0 link: 0
9253 13:59:01.418565 CPU_CLUSTER: 0 missing set_resources
9254 13:59:01.425149 Root Device assign_resources, bus 0 link: 0 done
9255 13:59:01.425240 Done setting resources.
9256 13:59:01.431497 Show resources in subtree (Root Device)...After assigning values.
9257 13:59:01.435286 Root Device child on link 0 CPU_CLUSTER: 0
9258 13:59:01.438614 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 13:59:01.448285 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 13:59:01.448403 CPU: 00
9261 13:59:01.451491 Done allocating resources.
9262 13:59:01.457819 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9263 13:59:01.457896 Enabling resources...
9264 13:59:01.457959 done.
9265 13:59:01.464672 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9266 13:59:01.468198 Initializing devices...
9267 13:59:01.468276 Root Device init
9268 13:59:01.471163 init hardware done!
9269 13:59:01.471247 0x00000018: ctrlr->caps
9270 13:59:01.474455 52.000 MHz: ctrlr->f_max
9271 13:59:01.477811 0.400 MHz: ctrlr->f_min
9272 13:59:01.477896 0x40ff8080: ctrlr->voltages
9273 13:59:01.481485 sclk: 390625
9274 13:59:01.481567 Bus Width = 1
9275 13:59:01.484263 sclk: 390625
9276 13:59:01.484346 Bus Width = 1
9277 13:59:01.488241 Early init status = 3
9278 13:59:01.490604 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9279 13:59:01.494549 in-header: 03 fc 00 00 01 00 00 00
9280 13:59:01.497322 in-data: 00
9281 13:59:01.500652 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9282 13:59:01.505244 in-header: 03 fd 00 00 00 00 00 00
9283 13:59:01.508521 in-data:
9284 13:59:01.511886 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9285 13:59:01.514832 in-header: 03 fc 00 00 01 00 00 00
9286 13:59:01.518267 in-data: 00
9287 13:59:01.521952 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9288 13:59:01.526221 in-header: 03 fd 00 00 00 00 00 00
9289 13:59:01.529559 in-data:
9290 13:59:01.532985 [SSUSB] Setting up USB HOST controller...
9291 13:59:01.535968 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9292 13:59:01.539253 [SSUSB] phy power-on done.
9293 13:59:01.543306 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9294 13:59:01.549356 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9295 13:59:01.552548 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9296 13:59:01.559221 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9297 13:59:01.565725 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9298 13:59:01.572476 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9299 13:59:01.579601 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9300 13:59:01.586309 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9301 13:59:01.589197 SPM: binary array size = 0x9dc
9302 13:59:01.592581 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9303 13:59:01.600127 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9304 13:59:01.605535 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9305 13:59:01.612129 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9306 13:59:01.615513 configure_display: Starting display init
9307 13:59:01.650003 anx7625_power_on_init: Init interface.
9308 13:59:01.653398 anx7625_disable_pd_protocol: Disabled PD feature.
9309 13:59:01.656290 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9310 13:59:01.684259 anx7625_start_dp_work: Secure OCM version=00
9311 13:59:01.687943 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9312 13:59:01.702399 sp_tx_get_edid_block: EDID Block = 1
9313 13:59:01.804865 Extracted contents:
9314 13:59:01.808682 header: 00 ff ff ff ff ff ff 00
9315 13:59:01.811950 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9316 13:59:01.815324 version: 01 04
9317 13:59:01.818362 basic params: 95 1f 11 78 0a
9318 13:59:01.822028 chroma info: 76 90 94 55 54 90 27 21 50 54
9319 13:59:01.824882 established: 00 00 00
9320 13:59:01.831568 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9321 13:59:01.835037 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9322 13:59:01.841464 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9323 13:59:01.847996 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9324 13:59:01.854820 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9325 13:59:01.858446 extensions: 00
9326 13:59:01.859098 checksum: fb
9327 13:59:01.859589
9328 13:59:01.861401 Manufacturer: IVO Model 57d Serial Number 0
9329 13:59:01.864571 Made week 0 of 2020
9330 13:59:01.867823 EDID version: 1.4
9331 13:59:01.868295 Digital display
9332 13:59:01.871573 6 bits per primary color channel
9333 13:59:01.872159 DisplayPort interface
9334 13:59:01.874157 Maximum image size: 31 cm x 17 cm
9335 13:59:01.877901 Gamma: 220%
9336 13:59:01.878472 Check DPMS levels
9337 13:59:01.880967 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9338 13:59:01.887473 First detailed timing is preferred timing
9339 13:59:01.888189 Established timings supported:
9340 13:59:01.890828 Standard timings supported:
9341 13:59:01.894336 Detailed timings
9342 13:59:01.897400 Hex of detail: 383680a07038204018303c0035ae10000019
9343 13:59:01.904470 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9344 13:59:01.907258 0780 0798 07c8 0820 hborder 0
9345 13:59:01.910412 0438 043b 0447 0458 vborder 0
9346 13:59:01.913755 -hsync -vsync
9347 13:59:01.914212 Did detailed timing
9348 13:59:01.920689 Hex of detail: 000000000000000000000000000000000000
9349 13:59:01.924157 Manufacturer-specified data, tag 0
9350 13:59:01.927366 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9351 13:59:01.930798 ASCII string: InfoVision
9352 13:59:01.934337 Hex of detail: 000000fe00523134304e574635205248200a
9353 13:59:01.937857 ASCII string: R140NWF5 RH
9354 13:59:01.938376 Checksum
9355 13:59:01.940288 Checksum: 0xfb (valid)
9356 13:59:01.943940 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9357 13:59:01.947194 DSI data_rate: 832800000 bps
9358 13:59:01.953953 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9359 13:59:01.956836 anx7625_parse_edid: pixelclock(138800).
9360 13:59:01.960558 hactive(1920), hsync(48), hfp(24), hbp(88)
9361 13:59:01.963350 vactive(1080), vsync(12), vfp(3), vbp(17)
9362 13:59:01.966870 anx7625_dsi_config: config dsi.
9363 13:59:01.973762 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9364 13:59:01.987397 anx7625_dsi_config: success to config DSI
9365 13:59:01.990649 anx7625_dp_start: MIPI phy setup OK.
9366 13:59:01.993583 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9367 13:59:01.996820 mtk_ddp_mode_set invalid vrefresh 60
9368 13:59:02.000253 main_disp_path_setup
9369 13:59:02.000732 ovl_layer_smi_id_en
9370 13:59:02.003458 ovl_layer_smi_id_en
9371 13:59:02.003924 ccorr_config
9372 13:59:02.004285 aal_config
9373 13:59:02.007140 gamma_config
9374 13:59:02.007597 postmask_config
9375 13:59:02.010313 dither_config
9376 13:59:02.013582 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9377 13:59:02.019916 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9378 13:59:02.023696 Root Device init finished in 551 msecs
9379 13:59:02.027330 CPU_CLUSTER: 0 init
9380 13:59:02.033521 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9381 13:59:02.040006 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9382 13:59:02.040561 APU_MBOX 0x190000b0 = 0x10001
9383 13:59:02.043606 APU_MBOX 0x190001b0 = 0x10001
9384 13:59:02.047210 APU_MBOX 0x190005b0 = 0x10001
9385 13:59:02.050038 APU_MBOX 0x190006b0 = 0x10001
9386 13:59:02.056968 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9387 13:59:02.066427 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9388 13:59:02.078396 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9389 13:59:02.085052 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9390 13:59:02.096785 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9391 13:59:02.105896 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9392 13:59:02.109168 CPU_CLUSTER: 0 init finished in 81 msecs
9393 13:59:02.112300 Devices initialized
9394 13:59:02.115771 Show all devs... After init.
9395 13:59:02.116328 Root Device: enabled 1
9396 13:59:02.118729 CPU_CLUSTER: 0: enabled 1
9397 13:59:02.122724 CPU: 00: enabled 1
9398 13:59:02.125679 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9399 13:59:02.129167 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9400 13:59:02.132384 ELOG: NV offset 0x57f000 size 0x1000
9401 13:59:02.139336 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9402 13:59:02.146050 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9403 13:59:02.149017 ELOG: Event(17) added with size 13 at 2023-08-28 13:59:04 UTC
9404 13:59:02.155525 out: cmd=0x121: 03 db 21 01 00 00 00 00
9405 13:59:02.158669 in-header: 03 d6 00 00 2c 00 00 00
9406 13:59:02.168476 in-data: 89 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9407 13:59:02.175533 ELOG: Event(A1) added with size 10 at 2023-08-28 13:59:04 UTC
9408 13:59:02.182132 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9409 13:59:02.188182 ELOG: Event(A0) added with size 9 at 2023-08-28 13:59:04 UTC
9410 13:59:02.191719 elog_add_boot_reason: Logged dev mode boot
9411 13:59:02.198165 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9412 13:59:02.198778 Finalize devices...
9413 13:59:02.201417 Devices finalized
9414 13:59:02.204892 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9415 13:59:02.208628 Writing coreboot table at 0xffe64000
9416 13:59:02.211438 0. 000000000010a000-0000000000113fff: RAMSTAGE
9417 13:59:02.218542 1. 0000000040000000-00000000400fffff: RAM
9418 13:59:02.221374 2. 0000000040100000-000000004032afff: RAMSTAGE
9419 13:59:02.224769 3. 000000004032b000-00000000545fffff: RAM
9420 13:59:02.228109 4. 0000000054600000-000000005465ffff: BL31
9421 13:59:02.231345 5. 0000000054660000-00000000ffe63fff: RAM
9422 13:59:02.238044 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9423 13:59:02.241329 7. 0000000100000000-000000023fffffff: RAM
9424 13:59:02.244378 Passing 5 GPIOs to payload:
9425 13:59:02.248364 NAME | PORT | POLARITY | VALUE
9426 13:59:02.254663 EC in RW | 0x000000aa | low | undefined
9427 13:59:02.257699 EC interrupt | 0x00000005 | low | undefined
9428 13:59:02.261240 TPM interrupt | 0x000000ab | high | undefined
9429 13:59:02.267909 SD card detect | 0x00000011 | high | undefined
9430 13:59:02.270843 speaker enable | 0x00000093 | high | undefined
9431 13:59:02.274404 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9432 13:59:02.277306 in-header: 03 f9 00 00 02 00 00 00
9433 13:59:02.280509 in-data: 02 00
9434 13:59:02.284078 ADC[4]: Raw value=903031 ID=7
9435 13:59:02.287128 ADC[3]: Raw value=213282 ID=1
9436 13:59:02.287588 RAM Code: 0x71
9437 13:59:02.290803 ADC[6]: Raw value=75036 ID=0
9438 13:59:02.294067 ADC[5]: Raw value=213282 ID=1
9439 13:59:02.294528 SKU Code: 0x1
9440 13:59:02.300480 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a16d
9441 13:59:02.301038 coreboot table: 964 bytes.
9442 13:59:02.303718 IMD ROOT 0. 0xfffff000 0x00001000
9443 13:59:02.307028 IMD SMALL 1. 0xffffe000 0x00001000
9444 13:59:02.310073 RO MCACHE 2. 0xffffc000 0x00001104
9445 13:59:02.313613 CONSOLE 3. 0xfff7c000 0x00080000
9446 13:59:02.317059 FMAP 4. 0xfff7b000 0x00000452
9447 13:59:02.320886 TIME STAMP 5. 0xfff7a000 0x00000910
9448 13:59:02.323627 VBOOT WORK 6. 0xfff66000 0x00014000
9449 13:59:02.326748 RAMOOPS 7. 0xffe66000 0x00100000
9450 13:59:02.330423 COREBOOT 8. 0xffe64000 0x00002000
9451 13:59:02.333330 IMD small region:
9452 13:59:02.336813 IMD ROOT 0. 0xffffec00 0x00000400
9453 13:59:02.340520 VPD 1. 0xffffeb80 0x0000006c
9454 13:59:02.343511 MMC STATUS 2. 0xffffeb60 0x00000004
9455 13:59:02.350060 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9456 13:59:02.350657 Probing TPM: done!
9457 13:59:02.356685 Connected to device vid:did:rid of 1ae0:0028:00
9458 13:59:02.363297 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9459 13:59:02.366711 Initialized TPM device CR50 revision 0
9460 13:59:02.369735 Checking cr50 for pending updates
9461 13:59:02.375663 Reading cr50 TPM mode
9462 13:59:02.384619 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9463 13:59:02.391075 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9464 13:59:02.430967 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9465 13:59:02.434341 Checking segment from ROM address 0x40100000
9466 13:59:02.437578 Checking segment from ROM address 0x4010001c
9467 13:59:02.444100 Loading segment from ROM address 0x40100000
9468 13:59:02.444642 code (compression=0)
9469 13:59:02.454139 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9470 13:59:02.460507 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9471 13:59:02.460972 it's not compressed!
9472 13:59:02.467538 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9473 13:59:02.470556 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9474 13:59:02.490965 Loading segment from ROM address 0x4010001c
9475 13:59:02.491169 Entry Point 0x80000000
9476 13:59:02.494403 Loaded segments
9477 13:59:02.497603 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9478 13:59:02.504116 Jumping to boot code at 0x80000000(0xffe64000)
9479 13:59:02.510921 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9480 13:59:02.517970 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9481 13:59:02.525953 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9482 13:59:02.529490 Checking segment from ROM address 0x40100000
9483 13:59:02.532070 Checking segment from ROM address 0x4010001c
9484 13:59:02.538875 Loading segment from ROM address 0x40100000
9485 13:59:02.539098 code (compression=1)
9486 13:59:02.545725 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9487 13:59:02.555246 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9488 13:59:02.555557 using LZMA
9489 13:59:02.565031 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9490 13:59:02.570744 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9491 13:59:02.574520 Loading segment from ROM address 0x4010001c
9492 13:59:02.575128 Entry Point 0x54601000
9493 13:59:02.577429 Loaded segments
9494 13:59:02.581002 NOTICE: MT8192 bl31_setup
9495 13:59:02.587645 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9496 13:59:02.591066 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9497 13:59:02.594272 WARNING: region 0:
9498 13:59:02.597395 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 13:59:02.597966 WARNING: region 1:
9500 13:59:02.604049 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9501 13:59:02.607539 WARNING: region 2:
9502 13:59:02.611173 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9503 13:59:02.615307 WARNING: region 3:
9504 13:59:02.618259 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9505 13:59:02.621103 WARNING: region 4:
9506 13:59:02.627801 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9507 13:59:02.628356 WARNING: region 5:
9508 13:59:02.631001 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 13:59:02.634627 WARNING: region 6:
9510 13:59:02.637828 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 13:59:02.641622 WARNING: region 7:
9512 13:59:02.644621 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 13:59:02.650580 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9514 13:59:02.654152 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9515 13:59:02.657645 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9516 13:59:02.664765 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9517 13:59:02.667683 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9518 13:59:02.671144 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9519 13:59:02.677207 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9520 13:59:02.680994 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9521 13:59:02.687238 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9522 13:59:02.690663 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9523 13:59:02.693971 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9524 13:59:02.700951 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9525 13:59:02.703744 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9526 13:59:02.707448 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9527 13:59:02.714330 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9528 13:59:02.717674 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9529 13:59:02.723843 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9530 13:59:02.727703 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9531 13:59:02.730222 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9532 13:59:02.737915 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9533 13:59:02.740421 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9534 13:59:02.747260 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9535 13:59:02.750711 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9536 13:59:02.753914 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9537 13:59:02.760475 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9538 13:59:02.763521 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9539 13:59:02.770548 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9540 13:59:02.773437 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9541 13:59:02.776664 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9542 13:59:02.783585 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9543 13:59:02.786524 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9544 13:59:02.793249 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9545 13:59:02.796487 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9546 13:59:02.800247 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9547 13:59:02.803970 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9548 13:59:02.810184 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9549 13:59:02.813267 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9550 13:59:02.816675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9551 13:59:02.819803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9552 13:59:02.827318 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9553 13:59:02.829663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9554 13:59:02.833550 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9555 13:59:02.836705 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9556 13:59:02.843257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9557 13:59:02.846287 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9558 13:59:02.849649 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9559 13:59:02.853496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9560 13:59:02.859524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9561 13:59:02.863002 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9562 13:59:02.869290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9563 13:59:02.872765 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9564 13:59:02.876155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9565 13:59:02.882739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9566 13:59:02.885821 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9567 13:59:02.892793 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9568 13:59:02.896152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9569 13:59:02.902825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9570 13:59:02.906335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9571 13:59:02.909991 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9572 13:59:02.915818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9573 13:59:02.919426 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9574 13:59:02.926034 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9575 13:59:02.929425 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9576 13:59:02.935965 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9577 13:59:02.938944 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9578 13:59:02.945578 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9579 13:59:02.948995 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9580 13:59:02.955485 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9581 13:59:02.959207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9582 13:59:02.962741 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9583 13:59:02.968980 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9584 13:59:02.972314 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9585 13:59:02.978896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9586 13:59:02.982650 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9587 13:59:02.988988 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9588 13:59:02.992455 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9589 13:59:02.995229 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9590 13:59:03.002137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9591 13:59:03.006181 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9592 13:59:03.011983 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9593 13:59:03.015600 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9594 13:59:03.021724 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9595 13:59:03.025253 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9596 13:59:03.032329 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9597 13:59:03.035285 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9598 13:59:03.038487 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9599 13:59:03.044902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9600 13:59:03.048369 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9601 13:59:03.055353 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9602 13:59:03.058147 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9603 13:59:03.065257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9604 13:59:03.068384 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9605 13:59:03.075684 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9606 13:59:03.077960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9607 13:59:03.081666 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9608 13:59:03.088166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9609 13:59:03.091420 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9610 13:59:03.094835 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9611 13:59:03.101472 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9612 13:59:03.105051 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9613 13:59:03.108157 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9614 13:59:03.114892 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9615 13:59:03.118542 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9616 13:59:03.122032 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9617 13:59:03.128264 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9618 13:59:03.131323 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9619 13:59:03.139007 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9620 13:59:03.141914 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9621 13:59:03.144943 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9622 13:59:03.151524 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9623 13:59:03.154850 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9624 13:59:03.158753 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9625 13:59:03.165135 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9626 13:59:03.168297 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9627 13:59:03.174559 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9628 13:59:03.177846 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9629 13:59:03.181647 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9630 13:59:03.188123 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9631 13:59:03.191480 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9632 13:59:03.194498 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9633 13:59:03.198242 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9634 13:59:03.204954 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9635 13:59:03.208148 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9636 13:59:03.211524 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9637 13:59:03.218217 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9638 13:59:03.221131 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9639 13:59:03.224501 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9640 13:59:03.231439 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9641 13:59:03.234952 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9642 13:59:03.241128 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9643 13:59:03.244840 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9644 13:59:03.247743 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9645 13:59:03.254862 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9646 13:59:03.258016 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9647 13:59:03.264511 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9648 13:59:03.267794 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9649 13:59:03.270967 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9650 13:59:03.277786 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9651 13:59:03.280795 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9652 13:59:03.287487 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9653 13:59:03.290715 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9654 13:59:03.294272 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9655 13:59:03.301260 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9656 13:59:03.304154 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9657 13:59:03.307140 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9658 13:59:03.313791 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9659 13:59:03.317160 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9660 13:59:03.323626 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9661 13:59:03.326840 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9662 13:59:03.334102 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9663 13:59:03.336937 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9664 13:59:03.340069 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9665 13:59:03.347069 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9666 13:59:03.350703 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9667 13:59:03.353660 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9668 13:59:03.360259 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9669 13:59:03.364067 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9670 13:59:03.370772 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9671 13:59:03.373983 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9672 13:59:03.376742 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9673 13:59:03.384031 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9674 13:59:03.386710 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9675 13:59:03.393642 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9676 13:59:03.397247 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9677 13:59:03.399748 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9678 13:59:03.406676 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9679 13:59:03.409990 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9680 13:59:03.417084 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9681 13:59:03.420228 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9682 13:59:03.423299 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9683 13:59:03.430211 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9684 13:59:03.433242 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9685 13:59:03.436814 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9686 13:59:03.443411 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9687 13:59:03.446427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9688 13:59:03.453326 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9689 13:59:03.456668 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9690 13:59:03.462533 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9691 13:59:03.465998 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9692 13:59:03.469460 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9693 13:59:03.476537 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9694 13:59:03.479625 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9695 13:59:03.486161 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9696 13:59:03.489188 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9697 13:59:03.492703 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9698 13:59:03.499096 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9699 13:59:03.502871 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9700 13:59:03.509473 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9701 13:59:03.512410 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9702 13:59:03.515513 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9703 13:59:03.522576 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9704 13:59:03.526083 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9705 13:59:03.532091 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9706 13:59:03.535554 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9707 13:59:03.538673 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9708 13:59:03.545732 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9709 13:59:03.548959 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9710 13:59:03.555446 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9711 13:59:03.558882 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9712 13:59:03.565309 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9713 13:59:03.568530 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9714 13:59:03.571612 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9715 13:59:03.578487 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9716 13:59:03.581869 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9717 13:59:03.588277 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9718 13:59:03.591673 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9719 13:59:03.598690 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9720 13:59:03.601775 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9721 13:59:03.605371 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9722 13:59:03.611855 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9723 13:59:03.614652 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9724 13:59:03.621812 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9725 13:59:03.624946 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9726 13:59:03.631375 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9727 13:59:03.634820 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9728 13:59:03.638797 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9729 13:59:03.644764 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9730 13:59:03.647961 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9731 13:59:03.654762 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9732 13:59:03.657821 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9733 13:59:03.664236 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9734 13:59:03.667952 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9735 13:59:03.672173 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9736 13:59:03.677432 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9737 13:59:03.680471 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9738 13:59:03.687258 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9739 13:59:03.690747 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9740 13:59:03.694251 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9741 13:59:03.701594 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9742 13:59:03.703912 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9743 13:59:03.707193 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9744 13:59:03.714213 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9745 13:59:03.717241 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9746 13:59:03.720489 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9747 13:59:03.724172 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9748 13:59:03.730865 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9749 13:59:03.734167 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9750 13:59:03.741419 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9751 13:59:03.743684 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9752 13:59:03.747271 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9753 13:59:03.754198 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9754 13:59:03.756693 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9755 13:59:03.760113 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9756 13:59:03.766747 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9757 13:59:03.770433 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9758 13:59:03.777225 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9759 13:59:03.780162 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9760 13:59:03.783098 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9761 13:59:03.790368 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9762 13:59:03.793594 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9763 13:59:03.796495 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9764 13:59:03.802980 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9765 13:59:03.806745 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9766 13:59:03.809468 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9767 13:59:03.816022 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9768 13:59:03.819248 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9769 13:59:03.826251 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9770 13:59:03.829778 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9771 13:59:03.833284 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9772 13:59:03.839522 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9773 13:59:03.842937 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9774 13:59:03.849826 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9775 13:59:03.852682 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9776 13:59:03.856072 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9777 13:59:03.862408 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9778 13:59:03.866126 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9779 13:59:03.869014 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9780 13:59:03.875370 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9781 13:59:03.878682 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9782 13:59:03.882085 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9783 13:59:03.886035 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9784 13:59:03.892734 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9785 13:59:03.895396 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9786 13:59:03.898869 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9787 13:59:03.902043 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9788 13:59:03.909332 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9789 13:59:03.912575 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9790 13:59:03.915750 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9791 13:59:03.918782 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9792 13:59:03.925440 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9793 13:59:03.928461 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9794 13:59:03.932518 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9795 13:59:03.938716 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9796 13:59:03.941952 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9797 13:59:03.948496 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9798 13:59:03.951923 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9799 13:59:03.955269 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9800 13:59:03.961479 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9801 13:59:03.964738 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9802 13:59:03.971455 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9803 13:59:03.974507 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9804 13:59:03.978428 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9805 13:59:03.984827 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9806 13:59:03.988100 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9807 13:59:03.994906 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9808 13:59:03.997852 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9809 13:59:04.004429 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9810 13:59:04.007427 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9811 13:59:04.011432 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9812 13:59:04.018877 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9813 13:59:04.021063 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9814 13:59:04.027919 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9815 13:59:04.030885 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9816 13:59:04.037230 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9817 13:59:04.040594 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9818 13:59:04.043756 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9819 13:59:04.050459 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9820 13:59:04.053858 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9821 13:59:04.061124 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9822 13:59:04.063895 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9823 13:59:04.070768 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9824 13:59:04.074319 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9825 13:59:04.077073 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9826 13:59:04.083458 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9827 13:59:04.087297 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9828 13:59:04.093578 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9829 13:59:04.096797 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9830 13:59:04.099702 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9831 13:59:04.106726 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9832 13:59:04.109922 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9833 13:59:04.116379 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9834 13:59:04.120284 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9835 13:59:04.124168 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9836 13:59:04.129582 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9837 13:59:04.132715 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9838 13:59:04.139511 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9839 13:59:04.142906 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9840 13:59:04.149808 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9841 13:59:04.152663 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9842 13:59:04.155662 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9843 13:59:04.163060 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9844 13:59:04.165887 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9845 13:59:04.172196 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9846 13:59:04.175499 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9847 13:59:04.182398 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9848 13:59:04.185614 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9849 13:59:04.188997 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9850 13:59:04.195422 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9851 13:59:04.198574 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9852 13:59:04.205690 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9853 13:59:04.209004 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9854 13:59:04.212381 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9855 13:59:04.219033 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9856 13:59:04.222004 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9857 13:59:04.228615 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9858 13:59:04.232078 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9859 13:59:04.235345 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9860 13:59:04.242107 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9861 13:59:04.245495 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9862 13:59:04.251498 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9863 13:59:04.255396 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9864 13:59:04.261845 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9865 13:59:04.265336 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9866 13:59:04.268127 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9867 13:59:04.274901 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9868 13:59:04.278185 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9869 13:59:04.284827 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9870 13:59:04.288105 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9871 13:59:04.294922 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9872 13:59:04.297985 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9873 13:59:04.305074 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9874 13:59:04.307792 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9875 13:59:04.310895 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9876 13:59:04.317992 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9877 13:59:04.320679 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9878 13:59:04.327447 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9879 13:59:04.331062 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9880 13:59:04.337375 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9881 13:59:04.340631 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9882 13:59:04.347548 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9883 13:59:04.350771 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9884 13:59:04.353859 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9885 13:59:04.360598 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9886 13:59:04.364018 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9887 13:59:04.370772 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9888 13:59:04.374661 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9889 13:59:04.380237 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9890 13:59:04.383319 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9891 13:59:04.387060 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9892 13:59:04.393487 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9893 13:59:04.396810 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9894 13:59:04.403419 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9895 13:59:04.407021 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9896 13:59:04.413314 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9897 13:59:04.416693 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9898 13:59:04.423777 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9899 13:59:04.426810 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9900 13:59:04.430199 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9901 13:59:04.437009 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9902 13:59:04.440406 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9903 13:59:04.446839 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9904 13:59:04.449771 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9905 13:59:04.456871 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9906 13:59:04.459884 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9907 13:59:04.466176 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9908 13:59:04.469846 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9909 13:59:04.473699 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9910 13:59:04.479404 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9911 13:59:04.482725 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9912 13:59:04.489415 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9913 13:59:04.492734 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9914 13:59:04.499396 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9915 13:59:04.502265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9916 13:59:04.505727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9917 13:59:04.512491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9918 13:59:04.515839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9919 13:59:04.522400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9920 13:59:04.525825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9921 13:59:04.532529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9922 13:59:04.536082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9923 13:59:04.542312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9924 13:59:04.546030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9925 13:59:04.552345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9926 13:59:04.555507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9927 13:59:04.562261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9928 13:59:04.565066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9929 13:59:04.571442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9930 13:59:04.575325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9931 13:59:04.581553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9932 13:59:04.584587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9933 13:59:04.591515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9934 13:59:04.595174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9935 13:59:04.601624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9936 13:59:04.604703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9937 13:59:04.611153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9938 13:59:04.614367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9939 13:59:04.620582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9940 13:59:04.624408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9941 13:59:04.631002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9942 13:59:04.633809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9943 13:59:04.640671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9944 13:59:04.643968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9945 13:59:04.650726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9946 13:59:04.653871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9947 13:59:04.660950 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9948 13:59:04.661507 INFO: [APUAPC] vio 0
9949 13:59:04.667631 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9950 13:59:04.671177 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9951 13:59:04.674372 INFO: [APUAPC] D0_APC_0: 0x400510
9952 13:59:04.678359 INFO: [APUAPC] D0_APC_1: 0x0
9953 13:59:04.680996 INFO: [APUAPC] D0_APC_2: 0x1540
9954 13:59:04.684074 INFO: [APUAPC] D0_APC_3: 0x0
9955 13:59:04.687363 INFO: [APUAPC] D1_APC_0: 0xffffffff
9956 13:59:04.691200 INFO: [APUAPC] D1_APC_1: 0xffffffff
9957 13:59:04.694139 INFO: [APUAPC] D1_APC_2: 0x3fffff
9958 13:59:04.697311 INFO: [APUAPC] D1_APC_3: 0x0
9959 13:59:04.700697 INFO: [APUAPC] D2_APC_0: 0xffffffff
9960 13:59:04.704901 INFO: [APUAPC] D2_APC_1: 0xffffffff
9961 13:59:04.707089 INFO: [APUAPC] D2_APC_2: 0x3fffff
9962 13:59:04.711150 INFO: [APUAPC] D2_APC_3: 0x0
9963 13:59:04.714195 INFO: [APUAPC] D3_APC_0: 0xffffffff
9964 13:59:04.717617 INFO: [APUAPC] D3_APC_1: 0xffffffff
9965 13:59:04.720306 INFO: [APUAPC] D3_APC_2: 0x3fffff
9966 13:59:04.723691 INFO: [APUAPC] D3_APC_3: 0x0
9967 13:59:04.727504 INFO: [APUAPC] D4_APC_0: 0xffffffff
9968 13:59:04.730377 INFO: [APUAPC] D4_APC_1: 0xffffffff
9969 13:59:04.733937 INFO: [APUAPC] D4_APC_2: 0x3fffff
9970 13:59:04.736943 INFO: [APUAPC] D4_APC_3: 0x0
9971 13:59:04.739915 INFO: [APUAPC] D5_APC_0: 0xffffffff
9972 13:59:04.743360 INFO: [APUAPC] D5_APC_1: 0xffffffff
9973 13:59:04.747096 INFO: [APUAPC] D5_APC_2: 0x3fffff
9974 13:59:04.750182 INFO: [APUAPC] D5_APC_3: 0x0
9975 13:59:04.753463 INFO: [APUAPC] D6_APC_0: 0xffffffff
9976 13:59:04.756483 INFO: [APUAPC] D6_APC_1: 0xffffffff
9977 13:59:04.760323 INFO: [APUAPC] D6_APC_2: 0x3fffff
9978 13:59:04.760914 INFO: [APUAPC] D6_APC_3: 0x0
9979 13:59:04.767138 INFO: [APUAPC] D7_APC_0: 0xffffffff
9980 13:59:04.769934 INFO: [APUAPC] D7_APC_1: 0xffffffff
9981 13:59:04.773273 INFO: [APUAPC] D7_APC_2: 0x3fffff
9982 13:59:04.773861 INFO: [APUAPC] D7_APC_3: 0x0
9983 13:59:04.777222 INFO: [APUAPC] D8_APC_0: 0xffffffff
9984 13:59:04.779639 INFO: [APUAPC] D8_APC_1: 0xffffffff
9985 13:59:04.783131 INFO: [APUAPC] D8_APC_2: 0x3fffff
9986 13:59:04.786641 INFO: [APUAPC] D8_APC_3: 0x0
9987 13:59:04.789812 INFO: [APUAPC] D9_APC_0: 0xffffffff
9988 13:59:04.792921 INFO: [APUAPC] D9_APC_1: 0xffffffff
9989 13:59:04.796077 INFO: [APUAPC] D9_APC_2: 0x3fffff
9990 13:59:04.799807 INFO: [APUAPC] D9_APC_3: 0x0
9991 13:59:04.803066 INFO: [APUAPC] D10_APC_0: 0xffffffff
9992 13:59:04.806460 INFO: [APUAPC] D10_APC_1: 0xffffffff
9993 13:59:04.809440 INFO: [APUAPC] D10_APC_2: 0x3fffff
9994 13:59:04.813028 INFO: [APUAPC] D10_APC_3: 0x0
9995 13:59:04.816307 INFO: [APUAPC] D11_APC_0: 0xffffffff
9996 13:59:04.819589 INFO: [APUAPC] D11_APC_1: 0xffffffff
9997 13:59:04.822830 INFO: [APUAPC] D11_APC_2: 0x3fffff
9998 13:59:04.826355 INFO: [APUAPC] D11_APC_3: 0x0
9999 13:59:04.829432 INFO: [APUAPC] D12_APC_0: 0xffffffff
10000 13:59:04.835905 INFO: [APUAPC] D12_APC_1: 0xffffffff
10001 13:59:04.840166 INFO: [APUAPC] D12_APC_2: 0x3fffff
10002 13:59:04.840733 INFO: [APUAPC] D12_APC_3: 0x0
10003 13:59:04.842706 INFO: [APUAPC] D13_APC_0: 0xffffffff
10004 13:59:04.849657 INFO: [APUAPC] D13_APC_1: 0xffffffff
10005 13:59:04.852417 INFO: [APUAPC] D13_APC_2: 0x3fffff
10006 13:59:04.852885 INFO: [APUAPC] D13_APC_3: 0x0
10007 13:59:04.859089 INFO: [APUAPC] D14_APC_0: 0xffffffff
10008 13:59:04.862360 INFO: [APUAPC] D14_APC_1: 0xffffffff
10009 13:59:04.865560 INFO: [APUAPC] D14_APC_2: 0x3fffff
10010 13:59:04.869030 INFO: [APUAPC] D14_APC_3: 0x0
10011 13:59:04.872504 INFO: [APUAPC] D15_APC_0: 0xffffffff
10012 13:59:04.875313 INFO: [APUAPC] D15_APC_1: 0xffffffff
10013 13:59:04.878649 INFO: [APUAPC] D15_APC_2: 0x3fffff
10014 13:59:04.882464 INFO: [APUAPC] D15_APC_3: 0x0
10015 13:59:04.883034 INFO: [APUAPC] APC_CON: 0x4
10016 13:59:04.884946 INFO: [NOCDAPC] D0_APC_0: 0x0
10017 13:59:04.889511 INFO: [NOCDAPC] D0_APC_1: 0x0
10018 13:59:04.891977 INFO: [NOCDAPC] D1_APC_0: 0x0
10019 13:59:04.895061 INFO: [NOCDAPC] D1_APC_1: 0xfff
10020 13:59:04.898499 INFO: [NOCDAPC] D2_APC_0: 0x0
10021 13:59:04.902005 INFO: [NOCDAPC] D2_APC_1: 0xfff
10022 13:59:04.905510 INFO: [NOCDAPC] D3_APC_0: 0x0
10023 13:59:04.908668 INFO: [NOCDAPC] D3_APC_1: 0xfff
10024 13:59:04.911805 INFO: [NOCDAPC] D4_APC_0: 0x0
10025 13:59:04.915033 INFO: [NOCDAPC] D4_APC_1: 0xfff
10026 13:59:04.915603 INFO: [NOCDAPC] D5_APC_0: 0x0
10027 13:59:04.918542 INFO: [NOCDAPC] D5_APC_1: 0xfff
10028 13:59:04.921563 INFO: [NOCDAPC] D6_APC_0: 0x0
10029 13:59:04.924994 INFO: [NOCDAPC] D6_APC_1: 0xfff
10030 13:59:04.928202 INFO: [NOCDAPC] D7_APC_0: 0x0
10031 13:59:04.931543 INFO: [NOCDAPC] D7_APC_1: 0xfff
10032 13:59:04.935001 INFO: [NOCDAPC] D8_APC_0: 0x0
10033 13:59:04.938235 INFO: [NOCDAPC] D8_APC_1: 0xfff
10034 13:59:04.942574 INFO: [NOCDAPC] D9_APC_0: 0x0
10035 13:59:04.944648 INFO: [NOCDAPC] D9_APC_1: 0xfff
10036 13:59:04.948079 INFO: [NOCDAPC] D10_APC_0: 0x0
10037 13:59:04.951726 INFO: [NOCDAPC] D10_APC_1: 0xfff
10038 13:59:04.952293 INFO: [NOCDAPC] D11_APC_0: 0x0
10039 13:59:04.954293 INFO: [NOCDAPC] D11_APC_1: 0xfff
10040 13:59:04.958243 INFO: [NOCDAPC] D12_APC_0: 0x0
10041 13:59:04.961114 INFO: [NOCDAPC] D12_APC_1: 0xfff
10042 13:59:04.964329 INFO: [NOCDAPC] D13_APC_0: 0x0
10043 13:59:04.967838 INFO: [NOCDAPC] D13_APC_1: 0xfff
10044 13:59:04.971386 INFO: [NOCDAPC] D14_APC_0: 0x0
10045 13:59:04.974333 INFO: [NOCDAPC] D14_APC_1: 0xfff
10046 13:59:04.977915 INFO: [NOCDAPC] D15_APC_0: 0x0
10047 13:59:04.980917 INFO: [NOCDAPC] D15_APC_1: 0xfff
10048 13:59:04.984396 INFO: [NOCDAPC] APC_CON: 0x4
10049 13:59:04.988318 INFO: [APUAPC] set_apusys_apc done
10050 13:59:04.990829 INFO: [DEVAPC] devapc_init done
10051 13:59:04.994838 INFO: GICv3 without legacy support detected.
10052 13:59:04.997514 INFO: ARM GICv3 driver initialized in EL3
10053 13:59:05.000505 INFO: Maximum SPI INTID supported: 639
10054 13:59:05.007282 INFO: BL31: Initializing runtime services
10055 13:59:05.010544 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10056 13:59:05.013916 INFO: SPM: enable CPC mode
10057 13:59:05.020849 INFO: mcdi ready for mcusys-off-idle and system suspend
10058 13:59:05.023814 INFO: BL31: Preparing for EL3 exit to normal world
10059 13:59:05.027077 INFO: Entry point address = 0x80000000
10060 13:59:05.030061 INFO: SPSR = 0x8
10061 13:59:05.035726
10062 13:59:05.036289
10063 13:59:05.036661
10064 13:59:05.038945 Starting depthcharge on Spherion...
10065 13:59:05.039410
10066 13:59:05.039782 Wipe memory regions:
10067 13:59:05.040128
10068 13:59:05.042891 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10069 13:59:05.043399 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10070 13:59:05.043799 Setting prompt string to ['asurada:']
10071 13:59:05.044208 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10072 13:59:05.044866 [0x00000040000000, 0x00000054600000)
10073 13:59:05.165725
10074 13:59:05.166288 [0x00000054660000, 0x00000080000000)
10075 13:59:05.425321
10076 13:59:05.425883 [0x000000821a7280, 0x000000ffe64000)
10077 13:59:06.170768
10078 13:59:06.171335 [0x00000100000000, 0x00000240000000)
10079 13:59:08.060500
10080 13:59:08.063252 Initializing XHCI USB controller at 0x11200000.
10081 13:59:09.044946
10082 13:59:09.045506 R8152: Initializing
10083 13:59:09.045875
10084 13:59:09.047866 Version 9 (ocp_data = 6010)
10085 13:59:09.048331
10086 13:59:09.051870 R8152: Done initializing
10087 13:59:09.052436
10088 13:59:09.052802 Adding net device
10089 13:59:09.573656
10090 13:59:09.576314 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10091 13:59:09.576884
10092 13:59:09.577251
10093 13:59:09.577594
10094 13:59:09.578488 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10096 13:59:09.680042 asurada: tftpboot 192.168.201.1 11372172/tftp-deploy-mxyag6t_/kernel/image.itb 11372172/tftp-deploy-mxyag6t_/kernel/cmdline
10097 13:59:09.680709 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10098 13:59:09.681191 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10099 13:59:09.685781 tftpboot 192.168.201.1 11372172/tftp-deploy-mxyag6t_/kernel/image.itp-deploy-mxyag6t_/kernel/cmdline
10100 13:59:09.686256
10101 13:59:09.686661 Waiting for link
10102 13:59:09.888390
10103 13:59:09.888964 done.
10104 13:59:09.889337
10105 13:59:09.889681 MAC: f4:f5:e8:50:de:0a
10106 13:59:09.890015
10107 13:59:09.891263 Sending DHCP discover... done.
10108 13:59:09.891723
10109 13:59:09.895106 Waiting for reply... done.
10110 13:59:09.895658
10111 13:59:09.897725 Sending DHCP request... done.
10112 13:59:09.898287
10113 13:59:09.898720 Waiting for reply... done.
10114 13:59:09.899082
10115 13:59:09.901456 My ip is 192.168.201.14
10116 13:59:09.902013
10117 13:59:09.904832 The DHCP server ip is 192.168.201.1
10118 13:59:09.905398
10119 13:59:09.909578 TFTP server IP predefined by user: 192.168.201.1
10120 13:59:09.910086
10121 13:59:09.914553 Bootfile predefined by user: 11372172/tftp-deploy-mxyag6t_/kernel/image.itb
10122 13:59:09.915179
10123 13:59:09.917537 Sending tftp read request... done.
10124 13:59:09.918050
10125 13:59:09.926731 Waiting for the transfer...
10126 13:59:09.927246
10127 13:59:10.197007 00000000 ################################################################
10128 13:59:10.197141
10129 13:59:10.437062 00080000 ################################################################
10130 13:59:10.437211
10131 13:59:10.666895 00100000 ################################################################
10132 13:59:10.667034
10133 13:59:10.919599 00180000 ################################################################
10134 13:59:10.919741
10135 13:59:11.150830 00200000 ################################################################
10136 13:59:11.150963
10137 13:59:11.391243 00280000 ################################################################
10138 13:59:11.391382
10139 13:59:11.636977 00300000 ################################################################
10140 13:59:11.637115
10141 13:59:11.871729 00380000 ################################################################
10142 13:59:11.871861
10143 13:59:12.125375 00400000 ################################################################
10144 13:59:12.125512
10145 13:59:12.379004 00480000 ################################################################
10146 13:59:12.379150
10147 13:59:12.619852 00500000 ################################################################
10148 13:59:12.619993
10149 13:59:12.852067 00580000 ################################################################
10150 13:59:12.852201
10151 13:59:13.103198 00600000 ################################################################
10152 13:59:13.103338
10153 13:59:13.329521 00680000 ################################################################
10154 13:59:13.329685
10155 13:59:13.599403 00700000 ################################################################
10156 13:59:13.599552
10157 13:59:13.854921 00780000 ################################################################
10158 13:59:13.855060
10159 13:59:14.107729 00800000 ################################################################
10160 13:59:14.107870
10161 13:59:14.380738 00880000 ################################################################
10162 13:59:14.380889
10163 13:59:14.641401 00900000 ################################################################
10164 13:59:14.641570
10165 13:59:14.881729 00980000 ################################################################
10166 13:59:14.881859
10167 13:59:15.112557 00a00000 ################################################################
10168 13:59:15.112702
10169 13:59:15.348986 00a80000 ################################################################
10170 13:59:15.349121
10171 13:59:15.656992 00b00000 ################################################################
10172 13:59:15.657554
10173 13:59:15.966329 00b80000 ################################################################
10174 13:59:15.966473
10175 13:59:16.243009 00c00000 ################################################################
10176 13:59:16.243156
10177 13:59:16.519841 00c80000 ################################################################
10178 13:59:16.520010
10179 13:59:16.788300 00d00000 ################################################################
10180 13:59:16.788440
10181 13:59:17.028980 00d80000 ################################################################
10182 13:59:17.029138
10183 13:59:17.272609 00e00000 ################################################################
10184 13:59:17.272756
10185 13:59:17.529309 00e80000 ################################################################
10186 13:59:17.529453
10187 13:59:17.799212 00f00000 ################################################################
10188 13:59:17.799337
10189 13:59:18.063985 00f80000 ################################################################
10190 13:59:18.064124
10191 13:59:18.315220 01000000 ################################################################
10192 13:59:18.315352
10193 13:59:18.587209 01080000 ################################################################
10194 13:59:18.587371
10195 13:59:18.847647 01100000 ################################################################
10196 13:59:18.847785
10197 13:59:19.091776 01180000 ################################################################
10198 13:59:19.091909
10199 13:59:19.318687 01200000 ################################################################
10200 13:59:19.318828
10201 13:59:19.545590 01280000 ################################################################
10202 13:59:19.545728
10203 13:59:19.772149 01300000 ################################################################
10204 13:59:19.772282
10205 13:59:20.029238 01380000 ################################################################
10206 13:59:20.029374
10207 13:59:20.301812 01400000 ################################################################
10208 13:59:20.301957
10209 13:59:20.578252 01480000 ################################################################
10210 13:59:20.578394
10211 13:59:20.849859 01500000 ################################################################
10212 13:59:20.849998
10213 13:59:21.119632 01580000 ################################################################
10214 13:59:21.119775
10215 13:59:21.392740 01600000 ################################################################
10216 13:59:21.392884
10217 13:59:21.665511 01680000 ################################################################
10218 13:59:21.665650
10219 13:59:21.920953 01700000 ################################################################
10220 13:59:21.921089
10221 13:59:22.193666 01780000 ################################################################
10222 13:59:22.193804
10223 13:59:22.465801 01800000 ################################################################
10224 13:59:22.465944
10225 13:59:22.709581 01880000 ################################################################
10226 13:59:22.709715
10227 13:59:22.936188 01900000 ################################################################
10228 13:59:22.936327
10229 13:59:23.163339 01980000 ################################################################
10230 13:59:23.163474
10231 13:59:23.420341 01a00000 ################################################################
10232 13:59:23.420476
10233 13:59:23.691930 01a80000 ################################################################
10234 13:59:23.692073
10235 13:59:23.961494 01b00000 ################################################################
10236 13:59:23.961639
10237 13:59:24.219368 01b80000 ################################################################
10238 13:59:24.219503
10239 13:59:24.476212 01c00000 ################################################################
10240 13:59:24.476354
10241 13:59:24.731470 01c80000 ################################################################
10242 13:59:24.731608
10243 13:59:25.003913 01d00000 ################################################################
10244 13:59:25.004055
10245 13:59:25.270494 01d80000 ################################################################
10246 13:59:25.270638
10247 13:59:25.535330 01e00000 ################################################################
10248 13:59:25.535470
10249 13:59:25.806964 01e80000 ################################################################
10250 13:59:25.807109
10251 13:59:26.079805 01f00000 ################################################################
10252 13:59:26.079972
10253 13:59:26.352821 01f80000 ################################################################
10254 13:59:26.352958
10255 13:59:26.628618 02000000 ################################################################
10256 13:59:26.628762
10257 13:59:26.882877 02080000 ################################################################
10258 13:59:26.883024
10259 13:59:27.110387 02100000 ################################################################
10260 13:59:27.110520
10261 13:59:27.338246 02180000 ################################################################
10262 13:59:27.338379
10263 13:59:27.594969 02200000 ################################################################
10264 13:59:27.595107
10265 13:59:27.847474 02280000 ################################################################
10266 13:59:27.847616
10267 13:59:28.101902 02300000 ################################################################
10268 13:59:28.102045
10269 13:59:28.333028 02380000 ################################################################
10270 13:59:28.333158
10271 13:59:28.560668 02400000 ################################################################
10272 13:59:28.560804
10273 13:59:28.792093 02480000 ################################################################
10274 13:59:28.792241
10275 13:59:29.052059 02500000 ################################################################
10276 13:59:29.052205
10277 13:59:29.282027 02580000 ################################################################
10278 13:59:29.282156
10279 13:59:29.511597 02600000 ################################################################
10280 13:59:29.511730
10281 13:59:29.745181 02680000 ################################################################
10282 13:59:29.745324
10283 13:59:29.985318 02700000 ################################################################
10284 13:59:29.985455
10285 13:59:30.213112 02780000 ################################################################
10286 13:59:30.213245
10287 13:59:30.467864 02800000 ################################################################
10288 13:59:30.468003
10289 13:59:30.743604 02880000 ################################################################
10290 13:59:30.743738
10291 13:59:31.005607 02900000 ################################################################
10292 13:59:31.005754
10293 13:59:31.273434 02980000 ################################################################
10294 13:59:31.273570
10295 13:59:31.536920 02a00000 ################################################################
10296 13:59:31.537076
10297 13:59:31.803813 02a80000 ################################################################
10298 13:59:31.803957
10299 13:59:32.080769 02b00000 ################################################################
10300 13:59:32.080916
10301 13:59:32.357281 02b80000 ################################################################
10302 13:59:32.357420
10303 13:59:32.634929 02c00000 ################################################################
10304 13:59:32.635066
10305 13:59:32.912791 02c80000 ################################################################
10306 13:59:32.912932
10307 13:59:33.190372 02d00000 ################################################################
10308 13:59:33.190511
10309 13:59:33.467934 02d80000 ################################################################
10310 13:59:33.468077
10311 13:59:33.744629 02e00000 ################################################################
10312 13:59:33.744769
10313 13:59:34.020910 02e80000 ################################################################
10314 13:59:34.021053
10315 13:59:34.297600 02f00000 ################################################################
10316 13:59:34.297745
10317 13:59:34.549208 02f80000 ################################################################
10318 13:59:34.549349
10319 13:59:34.603049 03000000 ############## done.
10320 13:59:34.603142
10321 13:59:34.606611 The bootfile was 50440922 bytes long.
10322 13:59:34.606692
10323 13:59:34.609911 Sending tftp read request... done.
10324 13:59:34.609996
10325 13:59:34.613661 Waiting for the transfer...
10326 13:59:34.613754
10327 13:59:34.613827 00000000 # done.
10328 13:59:34.613898
10329 13:59:34.623142 Command line loaded dynamically from TFTP file: 11372172/tftp-deploy-mxyag6t_/kernel/cmdline
10330 13:59:34.623331
10331 13:59:34.636625 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10332 13:59:34.636861
10333 13:59:34.636991 Loading FIT.
10334 13:59:34.637113
10335 13:59:34.639505 Image ramdisk-1 has 39351776 bytes.
10336 13:59:34.639660
10337 13:59:34.643147 Image fdt-1 has 47278 bytes.
10338 13:59:34.643317
10339 13:59:34.646726 Image kernel-1 has 11039834 bytes.
10340 13:59:34.647120
10341 13:59:34.657311 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10342 13:59:34.657711
10343 13:59:34.673758 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10344 13:59:34.674343
10345 13:59:34.676812 Choosing best match conf-1 for compat google,spherion-rev2.
10346 13:59:34.679898
10347 13:59:34.683337 Connected to device vid:did:rid of 1ae0:0028:00
10348 13:59:34.693891
10349 13:59:34.697347 tpm_get_response: command 0x17b, return code 0x0
10350 13:59:34.697908
10351 13:59:34.700182 ec_init: CrosEC protocol v3 supported (256, 248)
10352 13:59:34.704699
10353 13:59:34.708910 tpm_cleanup: add release locality here.
10354 13:59:34.709497
10355 13:59:34.709880 Shutting down all USB controllers.
10356 13:59:34.711116
10357 13:59:34.711519 Removing current net device
10358 13:59:34.711868
10359 13:59:34.717904 Exiting depthcharge with code 4 at timestamp: 59087981
10360 13:59:34.718462
10361 13:59:34.721171 LZMA decompressing kernel-1 to 0x821a6718
10362 13:59:34.721727
10363 13:59:34.724520 LZMA decompressing kernel-1 to 0x40000000
10364 13:59:36.113139
10365 13:59:36.113691 jumping to kernel
10366 13:59:36.115259 end: 2.2.4 bootloader-commands (duration 00:00:31) [common]
10367 13:59:36.115797 start: 2.2.5 auto-login-action (timeout 00:03:54) [common]
10368 13:59:36.116199 Setting prompt string to ['Linux version [0-9]']
10369 13:59:36.116565 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10370 13:59:36.116934 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10371 13:59:36.195945
10372 13:59:36.198779 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10373 13:59:36.203153 start: 2.2.5.1 login-action (timeout 00:03:54) [common]
10374 13:59:36.203731 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10375 13:59:36.204124 Setting prompt string to []
10376 13:59:36.204561 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10377 13:59:36.204957 Using line separator: #'\n'#
10378 13:59:36.205290 No login prompt set.
10379 13:59:36.205619 Parsing kernel messages
10380 13:59:36.205922 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10381 13:59:36.206470 [login-action] Waiting for messages, (timeout 00:03:54)
10382 13:59:36.222000 [ 0.000000] Linux version 6.1.46-cip4-rt2 (KernelCI@build-j25372-arm64-gcc-10-defconfig-arm64-chromebook-2wz78) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 28 13:41:26 UTC 2023
10383 13:59:36.225366 [ 0.000000] random: crng init done
10384 13:59:36.232037 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10385 13:59:36.235200 [ 0.000000] efi: UEFI not found.
10386 13:59:36.242383 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10387 13:59:36.249147 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10388 13:59:36.258333 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10389 13:59:36.268326 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10390 13:59:36.274721 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10391 13:59:36.281682 [ 0.000000] printk: bootconsole [mtk8250] enabled
10392 13:59:36.287833 [ 0.000000] NUMA: No NUMA configuration found
10393 13:59:36.294570 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10394 13:59:36.301449 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10395 13:59:36.302019 [ 0.000000] Zone ranges:
10396 13:59:36.307844 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10397 13:59:36.311539 [ 0.000000] DMA32 empty
10398 13:59:36.317802 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10399 13:59:36.321031 [ 0.000000] Movable zone start for each node
10400 13:59:36.323953 [ 0.000000] Early memory node ranges
10401 13:59:36.330886 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10402 13:59:36.337262 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10403 13:59:36.345030 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10404 13:59:36.350819 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10405 13:59:36.357072 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10406 13:59:36.364165 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10407 13:59:36.420403 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10408 13:59:36.427177 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10409 13:59:36.433487 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10410 13:59:36.437301 [ 0.000000] psci: probing for conduit method from DT.
10411 13:59:36.443482 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10412 13:59:36.446827 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10413 13:59:36.453917 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10414 13:59:36.456999 [ 0.000000] psci: SMC Calling Convention v1.2
10415 13:59:36.462986 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10416 13:59:36.466124 [ 0.000000] Detected VIPT I-cache on CPU0
10417 13:59:36.472907 [ 0.000000] CPU features: detected: GIC system register CPU interface
10418 13:59:36.479455 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10419 13:59:36.486113 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10420 13:59:36.493044 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10421 13:59:36.502923 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10422 13:59:36.509489 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10423 13:59:36.512560 [ 0.000000] alternatives: applying boot alternatives
10424 13:59:36.519192 [ 0.000000] Fallback order for Node 0: 0
10425 13:59:36.525759 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10426 13:59:36.529185 [ 0.000000] Policy zone: Normal
10427 13:59:36.542488 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10428 13:59:36.552415 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10429 13:59:36.565168 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10430 13:59:36.575220 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10431 13:59:36.581649 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10432 13:59:36.584562 <6>[ 0.000000] software IO TLB: area num 8.
10433 13:59:36.642095 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10434 13:59:36.792146 <6>[ 0.000000] Memory: 7931060K/8385536K available (17984K kernel code, 4100K rwdata, 17468K rodata, 8384K init, 615K bss, 421708K reserved, 32768K cma-reserved)
10435 13:59:36.798874 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10436 13:59:36.805338 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10437 13:59:36.808128 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10438 13:59:36.814777 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10439 13:59:36.821468 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10440 13:59:36.824779 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10441 13:59:36.835066 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10442 13:59:36.841190 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10443 13:59:36.847708 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10444 13:59:36.854144 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10445 13:59:36.857836 <6>[ 0.000000] GICv3: 608 SPIs implemented
10446 13:59:36.861038 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10447 13:59:36.867310 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10448 13:59:36.870848 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10449 13:59:36.877256 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10450 13:59:36.891200 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10451 13:59:36.904177 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10452 13:59:36.910415 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10453 13:59:36.918415 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10454 13:59:36.931357 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10455 13:59:36.938755 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10456 13:59:36.944858 <6>[ 0.009232] Console: colour dummy device 80x25
10457 13:59:36.954996 <6>[ 0.013958] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10458 13:59:36.960848 <6>[ 0.024465] pid_max: default: 32768 minimum: 301
10459 13:59:36.964437 <6>[ 0.029335] LSM: Security Framework initializing
10460 13:59:36.970943 <6>[ 0.034274] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10461 13:59:36.981142 <6>[ 0.042087] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10462 13:59:36.990829 <6>[ 0.051506] cblist_init_generic: Setting adjustable number of callback queues.
10463 13:59:36.997681 <6>[ 0.058991] cblist_init_generic: Setting shift to 3 and lim to 1.
10464 13:59:37.004044 <6>[ 0.065329] cblist_init_generic: Setting adjustable number of callback queues.
10465 13:59:37.011283 <6>[ 0.072756] cblist_init_generic: Setting shift to 3 and lim to 1.
10466 13:59:37.014166 <6>[ 0.079194] rcu: Hierarchical SRCU implementation.
10467 13:59:37.020515 <6>[ 0.079196] rcu: Max phase no-delay instances is 1000.
10468 13:59:37.027529 <6>[ 0.079221] printk: bootconsole [mtk8250] printing thread started
10469 13:59:37.033534 <6>[ 0.097558] EFI services will not be available.
10470 13:59:37.036995 <6>[ 0.097760] smp: Bringing up secondary CPUs ...
10471 13:59:37.043278 <6>[ 0.098065] Detected VIPT I-cache on CPU1
10472 13:59:37.050429 <6>[ 0.098133] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10473 13:59:37.056601 <6>[ 0.098166] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10474 13:59:37.066440 <6>[ 0.126019] Detected VIPT I-cache on CPU2
10475 13:59:37.076872 <6>[ 0.126069] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10476 13:59:37.082793 <6>[ 0.126086] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10477 13:59:37.086047 <6>[ 0.126345] Detected VIPT I-cache on CPU3
10478 13:59:37.092725 <6>[ 0.126391] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10479 13:59:37.099438 <6>[ 0.126404] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10480 13:59:37.106021 <6>[ 0.126714] CPU features: detected: Spectre-v4
10481 13:59:37.109566 <6>[ 0.126720] CPU features: detected: Spectre-BHB
10482 13:59:37.112266 <6>[ 0.126726] Detected PIPT I-cache on CPU4
10483 13:59:37.119049 <6>[ 0.126788] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10484 13:59:37.128912 <6>[ 0.126804] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10485 13:59:37.132463 <6>[ 0.127095] Detected PIPT I-cache on CPU5
10486 13:59:37.139028 <6>[ 0.127156] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10487 13:59:37.145192 <6>[ 0.127172] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10488 13:59:37.148432 <6>[ 0.127451] Detected PIPT I-cache on CPU6
10489 13:59:37.158772 <6>[ 0.127514] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10490 13:59:37.166144 <6>[ 0.127530] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10491 13:59:37.172444 <6>[ 0.127823] Detected PIPT I-cache on CPU7
10492 13:59:37.178411 <6>[ 0.127887] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10493 13:59:37.185306 <6>[ 0.127903] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10494 13:59:37.188801 <6>[ 0.127949] smp: Brought up 1 node, 8 CPUs
10495 13:59:37.194912 <6>[ 0.127954] SMP: Total of 8 processors activated.
10496 13:59:37.198039 <6>[ 0.127957] CPU features: detected: 32-bit EL0 Support
10497 13:59:37.207783 <6>[ 0.127959] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10498 13:59:37.214360 <6>[ 0.127961] CPU features: detected: Common not Private translations
10499 13:59:37.221294 <6>[ 0.127963] CPU features: detected: CRC32 instructions
10500 13:59:37.224061 <6>[ 0.127966] CPU features: detected: RCpc load-acquire (LDAPR)
10501 13:59:37.231228 <6>[ 0.127967] CPU features: detected: LSE atomic instructions
10502 13:59:37.237303 <6>[ 0.127969] CPU features: detected: Privileged Access Never
10503 13:59:37.244269 <6>[ 0.127970] CPU features: detected: RAS Extension Support
10504 13:59:37.251182 <6>[ 0.127973] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10505 13:59:37.253693 <6>[ 0.128041] CPU: All CPU(s) started at EL2
10506 13:59:37.261119 <6>[ 0.128043] alternatives: applying system-wide alternatives
10507 13:59:37.263855 <6>[ 0.141086] devtmpfs: initialized
10508 13:59:37.274055 <6>[ 0.147382] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10509 13:59:37.280332 <6>[ 0.147400] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10510 13:59:37.309326 �������Bzɑ����b���ª���ѕͱb����ɥjR�<6>[ 0.374253<] printk: console [ttyS0] printing thread started
10511 13:59:37.315475 6<6>[ 0.374268] printk: console [ttyS0] enabled
10512 13:59:37.322449 >[ 0.247586] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10513 13:59:37.331951 <6>[ 0.247660] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10514 13:59:37.339409 <6>[ 0.374271] printk: bootconsole [mtk8250] disabled
10515 13:59:37.345680 <6>[ 0.401345] printk: bootconsole [mtk8250] printing thread stopped
10516 13:59:37.348980 <6>[ 0.402366] SuperH (H)SCI(F) driver initialized
10517 13:59:37.355581 <6>[ 0.402840] msm_serial: driver initialized
10518 13:59:37.362407 <6>[ 0.407426] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10519 13:59:37.372273 <6>[ 0.407454] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10520 13:59:37.378904 <6>[ 0.407492] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10521 13:59:37.388647 <6>[ 0.407522] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10522 13:59:37.407155 <6>[ 0.407543] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10523 13:59:37.407753 <6>[ 0.407570] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10524 13:59:37.426768 <6>[ 0.407598] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10525 13:59:37.427904 <6>[ 0.407694] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10526 13:59:37.436723 <6>[ 0.407724] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10527 13:59:37.443858 <6>[ 0.418601] loop: module loaded
10528 13:59:37.450018 <6>[ 0.421256] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10529 13:59:37.451216 <4>[ 0.437905] mtk-pmic-keys: Failed to locate of_node [id: -1]
10530 13:59:37.452785 <6>[ 0.438640] megasas: 07.719.03.00-rc1
10531 13:59:37.456493 <6>[ 0.450860] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10532 13:59:37.462766 <6>[ 0.451061] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10533 13:59:37.469993 <6>[ 0.462654] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10534 13:59:37.479492 <6>[ 0.520796] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10535 13:59:38.759534 <6>[ 1.821528] Freeing initrd memory: 38428K
10536 13:59:38.764915 <6>[ 1.827548] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10537 13:59:38.768448 <6>[ 1.832158] tun: Universal TUN/TAP device driver, 1.6
10538 13:59:38.771609 <6>[ 1.832892] thunder_xcv, ver 1.0
10539 13:59:38.775163 <6>[ 1.832910] thunder_bgx, ver 1.0
10540 13:59:38.778088 <6>[ 1.832927] nicpf, ver 1.0
10541 13:59:38.788468 <6>[ 1.833975] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10542 13:59:38.791576 <6>[ 1.833978] hns3: Copyright (c) 2017 Huawei Corporation.
10543 13:59:38.794972 <6>[ 1.834002] hclge is initializing
10544 13:59:38.801546 <6>[ 1.834019] e1000: Intel(R) PRO/1000 Network Driver
10545 13:59:38.808360 <6>[ 1.834021] e1000: Copyright (c) 1999-2006 Intel Corporation.
10546 13:59:38.812322 <6>[ 1.834041] e1000e: Intel(R) PRO/1000 Network Driver
10547 13:59:38.819635 <6>[ 1.834043] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10548 13:59:38.822830 <6>[ 1.834060] igb: Intel(R) Gigabit Ethernet Network Driver
10549 13:59:38.829730 <6>[ 1.834062] igb: Copyright (c) 2007-2014 Intel Corporation.
10550 13:59:38.836680 <6>[ 1.834075] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10551 13:59:38.843144 <6>[ 1.834077] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10552 13:59:38.846733 <6>[ 1.834371] sky2: driver version 1.30
10553 13:59:38.853037 <6>[ 1.835439] VFIO - User Level meta-driver version: 0.3
10554 13:59:38.860288 <6>[ 1.838265] usbcore: registered new interface driver usb-storage
10555 13:59:38.867023 <6>[ 1.838444] usbcore: registered new device driver onboard-usb-hub
10556 13:59:38.869724 <6>[ 1.841183] mt6397-rtc mt6359-rtc: registered as rtc0
10557 13:59:38.879666 <6>[ 1.841335] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-28T13:59:41 UTC (1693231181)
10558 13:59:38.883383 <6>[ 1.841949] i2c_dev: i2c /dev entries driver
10559 13:59:38.893373 <6>[ 1.849058] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10560 13:59:38.895913 <6>[ 1.864047] cpu cpu0: EM: created perf domain
10561 13:59:38.899696 <6>[ 1.864261] cpu cpu4: EM: created perf domain
10562 13:59:38.906259 <6>[ 1.866174] sdhci: Secure Digital Host Controller Interface driver
10563 13:59:38.912455 <6>[ 1.866176] sdhci: Copyright(c) Pierre Ossman
10564 13:59:38.918995 <6>[ 1.866521] Synopsys Designware Multimedia Card Interface Driver
10565 13:59:38.922406 <6>[ 1.866909] sdhci-pltfm: SDHCI platform and OF driver helper
10566 13:59:38.929190 <6>[ 1.870997] ledtrig-cpu: registered to indicate activity on CPUs
10567 13:59:38.932499 <6>[ 1.871630] mmc0: CQHCI version 5.10
10568 13:59:38.942140 <6>[ 1.871666] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10569 13:59:38.946105 <6>[ 1.871978] usbcore: registered new interface driver usbhid
10570 13:59:38.952432 <6>[ 1.871981] usbhid: USB HID core driver
10571 13:59:38.959008 <6>[ 1.872155] spi_master spi0: will run message pump with realtime priority
10572 13:59:38.969267 <6>[ 1.898382] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10573 13:59:38.985821 <6>[ 1.900184] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10574 13:59:38.988839 <6>[ 1.901263] cros-ec-spi spi0.0: Chrome EC device registered
10575 13:59:38.998381 <6>[ 1.917405] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10576 13:59:39.005268 <6>[ 1.918357] NET: Registered PF_PACKET protocol family
10577 13:59:39.008601 <6>[ 1.918423] 9pnet: Installing 9P2000 support
10578 13:59:39.011681 <5>[ 1.918456] Key type dns_resolver registered
10579 13:59:39.018742 <6>[ 1.918751] registered taskstats version 1
10580 13:59:39.021583 <5>[ 1.918764] Loading compiled-in X.509 certificates
10581 13:59:39.031384 <4>[ 1.935712] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 13:59:39.044302 <4>[ 1.935888] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10583 13:59:39.051387 <3>[ 1.935900] debugfs: File 'uA_load' in directory '/' already present!
10584 13:59:39.057548 <3>[ 1.935908] debugfs: File 'min_uV' in directory '/' already present!
10585 13:59:39.064845 <3>[ 1.935912] debugfs: File 'max_uV' in directory '/' already present!
10586 13:59:39.071440 <3>[ 1.935916] debugfs: File 'constraint_flags' in directory '/' already present!
10587 13:59:39.081479 <3>[ 1.937814] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10588 13:59:39.084254 <6>[ 1.944505] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10589 13:59:39.091346 <6>[ 1.945142] xhci-mtk 11200000.usb: xHCI Host Controller
10590 13:59:39.097198 <6>[ 1.945158] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10591 13:59:39.107296 <6>[ 1.945356] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10592 13:59:39.114124 <6>[ 1.945392] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10593 13:59:39.120700 <6>[ 1.945474] xhci-mtk 11200000.usb: xHCI Host Controller
10594 13:59:39.127141 <6>[ 1.945477] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10595 13:59:39.133951 <6>[ 1.945480] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10596 13:59:39.136932 <6>[ 1.945865] hub 1-0:1.0: USB hub found
10597 13:59:39.143733 <6>[ 1.945899] hub 1-0:1.0: 1 port detected
10598 13:59:39.150656 <6>[ 1.946163] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10599 13:59:39.153909 <6>[ 1.946648] hub 2-0:1.0: USB hub found
10600 13:59:39.160225 <6>[ 1.946744] hub 2-0:1.0: 1 port detected
10601 13:59:39.164320 <6>[ 1.949773] mtk-msdc 11f70000.mmc: Got CD GPIO
10602 13:59:39.174272 <6>[ 1.957203] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10603 13:59:39.180070 <6>[ 1.957211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10604 13:59:39.190541 <4>[ 1.957303] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10605 13:59:39.196913 <6>[ 1.957796] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10606 13:59:39.203622 <6>[ 1.957797] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10607 13:59:39.213113 <6>[ 1.958036] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10608 13:59:39.219663 <6>[ 1.958059] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10609 13:59:39.229659 <6>[ 1.958061] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10610 13:59:39.236406 <6>[ 1.958065] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10611 13:59:39.245776 <6>[ 1.959208] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10612 13:59:39.252678 <6>[ 1.959223] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10613 13:59:39.262455 <6>[ 1.959226] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10614 13:59:39.269306 <6>[ 1.959229] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10615 13:59:39.279183 <6>[ 1.959232] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10616 13:59:39.286869 <6>[ 1.959235] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10617 13:59:39.295936 <6>[ 1.959239] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10618 13:59:39.305563 <6>[ 1.959242] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10619 13:59:39.312065 <6>[ 1.959244] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10620 13:59:39.321698 <6>[ 1.959248] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10621 13:59:39.328760 <6>[ 1.959250] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10622 13:59:39.339088 <6>[ 1.959253] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10623 13:59:39.345477 <6>[ 1.959257] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10624 13:59:39.355186 <6>[ 1.959261] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10625 13:59:39.361981 <6>[ 1.959264] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10626 13:59:39.368329 <6>[ 1.959574] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10627 13:59:39.374926 <6>[ 1.960239] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10628 13:59:39.381684 <6>[ 1.960469] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10629 13:59:39.388360 <6>[ 1.960700] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10630 13:59:39.395147 <6>[ 1.960937] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10631 13:59:39.404727 <6>[ 1.961106] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10632 13:59:39.415006 <6>[ 1.961120] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10633 13:59:39.424416 <6>[ 1.961124] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10634 13:59:39.432051 <6>[ 1.961129] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10635 13:59:39.440910 <6>[ 1.961133] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10636 13:59:39.450663 <6>[ 1.961137] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10637 13:59:39.461311 <6>[ 1.961141] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10638 13:59:39.470377 <6>[ 1.961145] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10639 13:59:39.477204 <6>[ 1.961148] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10640 13:59:39.490988 <6>[ 1.961154] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10641 13:59:39.500307 <6>[ 1.961157] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10642 13:59:39.507278 <6>[ 1.961789] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10643 13:59:39.513199 <6>[ 1.965826] mmc0: Command Queue Engine enabled
10644 13:59:39.520034 <6>[ 1.965839] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10645 13:59:39.523457 <6>[ 1.966273] mmcblk0: mmc0:0001 DA4128 116 GiB
10646 13:59:39.529955 <6>[ 1.969377] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10647 13:59:39.533832 <6>[ 1.970362] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10648 13:59:39.539749 <6>[ 1.970931] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10649 13:59:39.546181 <6>[ 1.971457] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10650 13:59:39.553491 <6>[ 2.327806] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10651 13:59:39.556449 <6>[ 2.355185] hub 2-1:1.0: USB hub found
10652 13:59:39.559917 <6>[ 2.355692] hub 2-1:1.0: 3 ports detected
10653 13:59:39.569301 <6>[ 2.475628] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10654 13:59:39.573134 <6>[ 2.628590] hub 1-1:1.0: USB hub found
10655 13:59:39.576029 <6>[ 2.629008] hub 1-1:1.0: 4 ports detected
10656 13:59:39.882410 <6>[ 2.939763] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10657 13:59:40.002843 <6>[ 3.065292] hub 1-1.1:1.0: USB hub found
10658 13:59:40.006546 <6>[ 3.065363] hub 1-1.1:1.0: 4 ports detected
10659 13:59:40.115190 <6>[ 3.171596] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10660 13:59:40.234466 <6>[ 3.298641] hub 1-1.4:1.0: USB hub found
10661 13:59:40.238148 <6>[ 3.298958] hub 1-1.4:1.0: 2 ports detected
10662 13:59:40.317896 <6>[ 3.375781] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10663 13:59:40.498336 <6>[ 3.555797] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10664 13:59:40.575368 <3>[ 3.635852] usb 1-1.1.4: device descriptor read/64, error -32
10665 13:59:40.763241 <3>[ 3.823854] usb 1-1.1.4: device descriptor read/64, error -32
10666 13:59:40.954004 <6>[ 4.011816] usb 1-1.1.4: new full-speed USB device number 7 using xhci-mtk
10667 13:59:41.031384 <3>[ 4.091790] usb 1-1.1.4: device descriptor read/64, error -32
10668 13:59:41.218791 <3>[ 4.279851] usb 1-1.1.4: device descriptor read/64, error -32
10669 13:59:41.326684 <6>[ 4.388060] usb 1-1.1-port4: attempt power cycle
10670 13:59:41.409989 <6>[ 4.467816] usb 1-1.4.1: new high-speed USB device number 8 using xhci-mtk
10671 13:59:41.594770 <6>[ 4.651816] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10672 13:59:41.982565 <6>[ 5.039816] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10673 13:59:41.988469 <4>[ 5.039954] usb 1-1.1.4: Device not responding to setup address.
10674 13:59:42.186644 <4>[ 5.247967] usb 1-1.1.4: Device not responding to setup address.
10675 13:59:42.394530 <3>[ 5.455809] usb 1-1.1.4: device not accepting address 10, error -71
10676 13:59:42.478218 <6>[ 5.535794] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10677 13:59:42.484159 <4>[ 5.536047] usb 1-1.1.4: Device not responding to setup address.
10678 13:59:42.682882 <4>[ 5.743929] usb 1-1.1.4: Device not responding to setup address.
10679 13:59:42.891311 <3>[ 5.951819] usb 1-1.1.4: device not accepting address 11, error -71
10680 13:59:42.896860 <3>[ 5.952147] usb 1-1.1-port4: unable to enumerate USB device
10681 13:59:51.206536 <6>[ 14.272814] ALSA device list:
10682 13:59:51.212965 <6>[ 14.272836] No soundcards found.
10683 13:59:51.216777 <6>[ 14.277270] Freeing unused kernel memory: 8384K
10684 13:59:51.219493 <6>[ 14.277436] Run /init as init process
10685 13:59:51.254008 <6>[ 14.319452] NET: Registered PF_INET6 protocol family
10686 13:59:51.256895 <6>[ 14.320638] Segment Routing with IPv6
10687 13:59:51.263839 <6>[ 14.320653] In-situ OAM (IOAM) with IPv6
10688 13:59:51.267352
10689 13:59:51.293701 Welcome to [1mDebian GNU/Linux 11 (bullseye)<30>[ 14.335990] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10690 13:59:51.294262 [0m!
10691 13:59:51.294674
10692 13:59:51.300600 <30>[ 14.336389] systemd[1]: Detected architecture arm64.
10693 13:59:51.306815 <30>[ 14.370205] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10694 13:59:51.425331 <30>[ 14.486368] systemd[1]: Queued start job for default target Graphical Interface.
10695 13:59:51.462250 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.524503] systemd[1]: Created slice system-getty.slice.
10696 13:59:51.465409 m-getty.slice[0m.
10697 13:59:51.489208 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.548357] systemd[1]: Created slice system-modprobe.slice.
10698 13:59:51.489795 m-modprobe.slice[0m.
10699 13:59:51.510906 [[0;32m OK [0m] Created slic<30>[ 14.573393] systemd[1]: Created slice system-serial\x2dgetty.slice.
10700 13:59:51.517689 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10701 13:59:51.534338 [[0;32m OK [0m] Created slic<30>[ 14.596772] systemd[1]: Created slice User and Session Slice.
10702 13:59:51.537557 e [0;1;39mUser and Session Slice[0m.
10703 13:59:51.561233 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 14.620306] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10704 13:59:51.564318 ssword …ts to Console Directory Watch[0m.
10705 13:59:51.588873 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 14.647808] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10706 13:59:51.591384 sword R…uests to Wall Directory Watch[0m.
10707 13:59:51.615974 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 14.671812] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10708 13:59:51.622867 <30>[ 14.671989] systemd[1]: Reached target Local Encrypted Volumes.
10709 13:59:51.625940 l Encrypted Volumes[0m.
10710 13:59:51.646123 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 14.708277] systemd[1]: Reached target Paths.
10711 13:59:51.646764 s[0m.
10712 13:59:51.668507 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 14.727748] systemd[1]: Reached target Remote File Systems.
10713 13:59:51.669081 te File Systems[0m.
10714 13:59:51.685208 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 14.747703] systemd[1]: Reached target Slices.
10715 13:59:51.685795 es[0m.
10716 13:59:51.705399 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 14.767747] systemd[1]: Reached target Swap.
10717 13:59:51.705988 [0m.
10718 13:59:51.729303 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 14.788199] systemd[1]: Listening on initctl Compatibility Named Pipe.
10719 13:59:51.732469 l Compatibility Named Pipe[0m.
10720 13:59:51.753514 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 14.812511] systemd[1]: Listening on Journal Audit Socket.
10721 13:59:51.754102 l Audit Socket[0m.
10722 13:59:51.774579 [[0;32m OK [0m] Listening on<30>[ 14.836850] systemd[1]: Listening on Journal Socket (/dev/log).
10723 13:59:51.777668 [0;1;39mJournal Socket (/dev/log)[0m.
10724 13:59:51.798446 [[0;32m OK [0m] Listening on<30>[ 14.860911] systemd[1]: Listening on Journal Socket.
10725 13:59:51.801285 [0;1;39mJournal Socket[0m.
10726 13:59:51.821092 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 14.880391] systemd[1]: Listening on Network Service Netlink Socket.
10727 13:59:51.823880 k Service Netlink Socket[0m.
10728 13:59:51.844748 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 14.904227] systemd[1]: Listening on udev Control Socket.
10729 13:59:51.845322 ontrol Socket[0m.
10730 13:59:51.866204 [[0;32m OK [0m] Listening on<30>[ 14.928803] systemd[1]: Listening on udev Kernel Socket.
10731 13:59:51.869494 [0;1;39mudev Kernel Socket[0m.
10732 13:59:51.928719 Mounting [0;1;39mHuge Pages File Syste<30>[ 14.987935] systemd[1]: Mounting Huge Pages File System...
10733 13:59:51.929285 m[0m...
10734 13:59:51.952474 Mounting [0;1;39mPOSIX Message Queue F<30>[ 15.011543] systemd[1]: Mounting POSIX Message Queue File System...
10735 13:59:51.953047 ile System[0m...
10736 13:59:51.980151 Mounting [0;1;39mKernel Debug File Sys<30>[ 15.039527] systemd[1]: Mounting Kernel Debug File System...
10737 13:59:51.980724 tem[0m...
10738 13:59:52.003328 Startin<30>[ 15.059964] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10739 13:59:52.012937 g [0;1;39mCreat<30>[ 15.062392] systemd[1]: Starting Create list of static device nodes for the current kernel...
10740 13:59:52.016577 e list of st…odes for the current kernel[0m...
10741 13:59:52.040221 Starting [0;1;39mLoad Kernel Module co<30>[ 15.099477] systemd[1]: Starting Load Kernel Module configfs...
10742 13:59:52.040810 nfigfs[0m...
10743 13:59:52.057423 <30>[ 15.123375] systemd[1]: Starting Load Kernel Module drm...
10744 13:59:52.064109 Starting [0;1;39mLoad Kernel Module drm[0m...
10745 13:59:52.085093 <30>[ 15.144020] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10746 13:59:52.098578 Starting [0;1;39mJournal Service[0m..<30>[ 15.160304] systemd[1]: Starting Journal Service...
10747 13:59:52.099195 .
10748 13:59:52.120142 Startin<30>[ 15.182641] systemd[1]: Starting Load Kernel Modules...
10749 13:59:52.123340 g [0;1;39mLoad Kernel Modules[0m...
10750 13:59:52.146737 Starting [0;1;39mRemou<30>[ 15.209025] systemd[1]: Starting Remount Root and Kernel File Systems...
10751 13:59:52.152990 nt Root and Kernel File Systems[0m...
10752 13:59:52.176626 Starting [0;1;39mColdplug All udev Dev<30>[ 15.236043] systemd[1]: Starting Coldplug All udev Devices...
10753 13:59:52.177200 ices[0m...
10754 13:59:52.192730 [[0;32m OK [<30>[ 15.258603] systemd[1]: Started Journal Service.
10755 13:59:52.199422 0m] Started [0;1;39mJournal Service[0m.
10756 13:59:52.218091 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10757 13:59:52.235343 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10758 13:59:52.250498 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10759 13:59:52.270736 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10760 13:59:52.287756 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10761 13:59:52.308687 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10762 13:59:52.331581 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10763 13:59:52.354373 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10764 13:59:52.369713 See 'systemctl status systemd-remount-fs.service' for details.
10765 13:59:52.415913 Mounting [0;1;39mKernel Configuration File System[0m...
10766 13:59:52.433144 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10767 13:59:52.449397 <46>[ 15.510350] systemd-journald[195]: Received client request to flush runtime journal.
10768 13:59:52.456958 Starting [0;1;39mLoad/Save Random Seed[0m...
10769 13:59:52.478523 Starting [0;1;39mApply Kernel Variables[0m...
10770 13:59:52.499256 Starting [0;1;39mCreate System Users[0m...
10771 13:59:52.517991 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10772 13:59:52.536200 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10773 13:59:52.559016 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10774 13:59:52.575391 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10775 13:59:52.591518 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10776 13:59:52.607569 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10777 13:59:52.662640 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10778 13:59:52.681855 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10779 13:59:52.694174 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10780 13:59:52.709995 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10781 13:59:52.754174 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10782 13:59:52.778895 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10783 13:59:52.798994 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10784 13:59:52.819288 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10785 13:59:52.856345 Starting [0;1;39mNetwork Service[0m...
10786 13:59:52.875434 Starting [0;1;39mNetwork Time Synchronization[0m...
10787 13:59:52.902361 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10788 13:59:52.924254 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10789 13:59:52.955547 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10790 13:59:52.980626 <6>[ 16.042570] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10791 13:59:52.990403 <6>[ 16.043347] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10792 13:59:53.001147 [[0;32m OK [0m] Found device<6>[ 16.043378] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10793 13:59:53.010717 [0;1;39m/dev/t<3>[ 16.067442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10794 13:59:53.020151 <3>[ 16.067455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 13:59:53.020726 tyS0[0m.
10796 13:59:53.027404 <3>[ 16.067459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10797 13:59:53.033849 <6>[ 16.068426] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10798 13:59:53.043512 <3>[ 16.073985] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10799 13:59:53.050944 <3>[ 16.074019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10800 13:59:53.060258 <3>[ 16.074028] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10801 13:59:53.066777 <3>[ 16.074039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10802 13:59:53.076423 <3>[ 16.074046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10803 13:59:53.082828 [[0;32m OK [0m] Finished [0<6>[ 16.075846] remoteproc remoteproc0: scp is available
10804 13:59:53.089512 ;1;39mUpdate UTM<6>[ 16.075953] remoteproc remoteproc0: powering up scp
10805 13:59:53.099766 P about System B<6>[ 16.075958] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10806 13:59:53.105996 <6>[ 16.075974] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10807 13:59:53.116454 oot/Shutdown[0m<3>[ 16.080075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 13:59:53.117029 .
10809 13:59:53.122587 <3>[ 16.115401] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10810 13:59:53.132491 <3>[ 16.115423] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10811 13:59:53.139285 <3>[ 16.115431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10812 13:59:53.146307 <6>[ 16.121957] mc: Linux media interface: v0.10
10813 13:59:53.152342 <3>[ 16.135824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10814 13:59:53.159121 <3>[ 16.135842] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10815 13:59:53.168557 <3>[ 16.135845] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10816 13:59:53.175227 <3>[ 16.135850] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10817 13:59:53.185368 <3>[ 16.135853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10818 13:59:53.192149 <6>[ 16.135854] usbcore: registered new interface driver r8152
10819 13:59:53.198708 <3>[ 16.135919] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10820 13:59:53.205235 <6>[ 16.159811] videodev: Linux video capture interface: v2.00
10821 13:59:53.212305 [[0;32m OK [<6>[ 16.164852] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10822 13:59:53.218776 <6>[ 16.164859] pci_bus 0000:00: root bus resource [bus 00-ff]
10823 13:59:53.225448 <6>[ 16.164863] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10824 13:59:53.236282 <6>[ 16.164865] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10825 13:59:53.242587 <6>[ 16.164889] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10826 13:59:53.249004 <6>[ 16.164902] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10827 13:59:53.252787 <6>[ 16.164965] pci 0000:00:00.0: supports D1 D2
10828 13:59:53.262446 0m] Created slic<6>[ 16.164966] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10829 13:59:53.268844 <6>[ 16.165881] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10830 13:59:53.276124 <6>[ 16.165968] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10831 13:59:53.286557 e [0;1;39msyste<6>[ 16.165993] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10832 13:59:53.293399 <6>[ 16.166011] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10833 13:59:53.302588 m-systemd\x2dbac<6>[ 16.166025] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10834 13:59:53.306515 klight.slice[0m<6>[ 16.166129] pci 0000:01:00.0: supports D1 D2
10835 13:59:53.312989 <6>[ 16.166131] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10836 13:59:53.320071 <6>[ 16.179665] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10837 13:59:53.320641 .
10838 13:59:53.330245 <6>[ 16.179706] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10839 13:59:53.336344 <6>[ 16.179712] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10840 13:59:53.346798 <6>[ 16.179725] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10841 13:59:53.356629 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 16.179741] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10842 13:59:53.366522 em Time Set[0m.<6>[ 16.179756] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10843 13:59:53.367157
10844 13:59:53.373163 <6>[ 16.179772] pci 0000:00:00.0: PCI bridge to [bus 01]
10845 13:59:53.379944 <6>[ 16.179780] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10846 13:59:53.387386 <6>[ 16.179943] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10847 13:59:53.394005 <6>[ 16.181167] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10848 13:59:53.402038 <6>[ 16.181394] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10849 13:59:53.408358 <6>[ 16.201500] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10850 13:59:53.414665 <6>[ 16.201500] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10851 13:59:53.421367 <6>[ 16.201518] remoteproc remoteproc0: remote processor scp is now up
10852 13:59:53.427628 <6>[ 16.203412] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10853 13:59:53.438455 [[0;32m OK [<4>[ 16.242411] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10854 13:59:53.444762 0m] Reached targ<4>[ 16.244864] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10855 13:59:53.454975 et [0;1;39mSyst<4>[ 16.276561] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10856 13:59:53.461577 <4>[ 16.276561] Fallback method does not support PEC.
10857 13:59:53.471456 em Time Synchron<6>[ 16.288234] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10858 13:59:53.472011 ized[0m.
10859 13:59:53.478725 <3>[ 16.294268] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 13:59:53.489167 <5>[ 16.322789] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10861 13:59:53.495395 <6>[ 16.325719] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10862 13:59:53.505944 <6>[ 16.327030] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10863 13:59:53.515674 <6>[ 16.333062] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10864 13:59:53.523061 <6>[ 16.333601] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10865 13:59:53.529310 <5>[ 16.335779] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10866 13:59:53.539334 <4>[ 16.335889] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10867 13:59:53.542550 <6>[ 16.335898] cfg80211: failed to load regulatory.db
10868 13:59:53.553087 <3>[ 16.349258] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 13:59:53.560366 <3>[ 16.350992] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10870 13:59:53.570172 <6>[ 16.355958] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10871 13:59:53.576514 <6>[ 16.373347] usbcore: registered new interface driver cdc_ether
10872 13:59:53.583092 <6>[ 16.385950] usbcore: registered new interface driver r8153_ecm
10873 13:59:53.589721 <4>[ 16.394857] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10874 13:59:53.600074 <4>[ 16.394875] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10875 13:59:53.603969 <6>[ 16.401154] Bluetooth: Core ver 2.22
10876 13:59:53.609780 <6>[ 16.401227] NET: Registered PF_BLUETOOTH protocol family
10877 13:59:53.617140 <6>[ 16.401229] Bluetooth: HCI device and connection manager initialized
10878 13:59:53.619773 <6>[ 16.401242] Bluetooth: HCI socket layer initialized
10879 13:59:53.626763 <6>[ 16.401245] Bluetooth: L2CAP socket layer initialized
10880 13:59:53.629532 <6>[ 16.401251] Bluetooth: SCO socket layer initialized
10881 13:59:53.640155 <6>[ 16.410901] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10882 13:59:53.646098 <3>[ 16.411337] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 13:59:53.659379 <6>[ 16.417218] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10884 13:59:53.666153 <6>[ 16.417638] usbcore: registered new interface driver uvcvideo
10885 13:59:53.668989 <6>[ 16.441749] usbcore: registered new interface driver btusb
10886 13:59:53.682282 <4>[ 16.441874] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10887 13:59:53.689382 <3>[ 16.441892] Bluetooth: hci0: Failed to load firmware file (-2)
10888 13:59:53.692275 <3>[ 16.441896] Bluetooth: hci0: Failed to set up firmware (-2)
10889 13:59:53.702819 <4>[ 16.441900] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10890 13:59:53.709080 <6>[ 16.451691] r8152 1-1.1.1:1.0 eth0: v1.12.13
10891 13:59:53.715451 <6>[ 16.453564] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10892 13:59:53.721778 <6>[ 16.461129] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10893 13:59:53.731712 Starting [0;1;39mLoad/<6>[ 16.461248] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10894 13:59:53.741925 Save Screen …o<3>[ 16.467587] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 13:59:53.748809 f leds:white:kbd<6>[ 16.467892] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10896 13:59:53.758842 <3>[ 16.468557] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10897 13:59:53.765232 <6>[ 16.479617] mt7921e 0000:01:00.0: ASIC revision: 79610010
10898 13:59:53.771812 <3>[ 16.480570] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 13:59:53.781442 <3>[ 16.506250] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 13:59:53.792213 <3>[ 16.533018] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 13:59:53.798181 <3>[ 16.553750] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 13:59:53.811503 <4>[ 16.574753] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10903 13:59:53.821489 <4>[ 16.681735] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10904 13:59:53.835108 <4>[ 16.793928] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10905 13:59:53.835682 _backlight[0m...
10906 13:59:53.851983 <4>[ 16.909633] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10907 13:59:53.878721 Starting [0;1;39mNetwork Name Resolution[0m...
10908 13:59:53.904212 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10909 13:59:53.945663 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10910 13:59:53.960005 <4>[ 17.018243] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10911 13:59:54.072126 <4>[ 17.129314] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10912 13:59:54.104305 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10913 13:59:54.117750 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10914 13:59:54.137061 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10915 13:59:54.149867 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10916 13:59:54.176521 [[0;32m OK [0m] Started [0;1;39mDiscard unu<4>[ 17.233426] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10917 13:59:54.179493 sed blocks once a week[0m.
10918 13:59:54.197222 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10919 13:59:54.210416 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10920 13:59:54.229789 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10921 13:59:54.241884 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10922 13:59:54.257576 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10923 13:59:54.284252 [[0;32m OK [0m] Listening on [0;1;39mLoad/S<4>[ 17.341939] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10924 13:59:54.287813 ave RF …itch Status /dev/rfkill Watch[0m.
10925 13:59:54.327319 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10926 13:59:54.361635 Starting [0;1;39mUser Login Management[0m...
10927 13:59:54.395972 <4>[ 17.451605] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10928 13:59:54.403118 Starting [0;1;39mPermit User Sessions[0m...
10929 13:59:54.422676 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10930 13:59:54.441968 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10931 13:59:54.462052 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10932 13:59:54.477718 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10933 13:59:54.506237 <4>[ 17.562169] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10934 13:59:54.538383 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10935 13:59:54.555593 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10936 13:59:54.569938 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10937 13:59:54.587252 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10938 13:59:54.602687 <3>[ 17.667234] mt7921e 0000:01:00.0: hardware init failed
10939 13:59:54.608775 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10940 13:59:54.662863 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10941 13:59:54.694325 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10942 13:59:54.737824
10943 13:59:54.738383
10944 13:59:54.741408 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10945 13:59:54.741961
10946 13:59:54.744379 debian-bullseye-arm64 login: root (automatic login)
10947 13:59:54.744929
10948 13:59:54.745289
10949 13:59:54.761465 Linux debian-bullseye-arm64 6.1.46-cip4-rt2 #1 SMP PREEMPT Mon Aug 28 13:41:26 UTC 2023 aarch64
10950 13:59:54.762024
10951 13:59:54.767806 The programs included with the Debian GNU/Linux system are free software;
10952 13:59:54.774867 the exact distribution terms for each program are described in the
10953 13:59:54.779092 individual files in /usr/share/doc/*/copyright.
10954 13:59:54.779551
10955 13:59:54.784668 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10956 13:59:54.787908 permitted by applicable law.
10957 13:59:54.789037 Matched prompt #10: / #
10959 13:59:54.790134 Setting prompt string to ['/ #']
10960 13:59:54.790628 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10962 13:59:54.791720 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10963 13:59:54.792193 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
10964 13:59:54.792575 Setting prompt string to ['/ #']
10965 13:59:54.792884 Forcing a shell prompt, looking for ['/ #']
10967 13:59:54.843667 / #
10968 13:59:54.844318 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10969 13:59:54.844757 Waiting using forced prompt support (timeout 00:02:30)
10970 13:59:54.850197
10971 13:59:54.851163 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10972 13:59:54.851692 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
10973 13:59:54.852198 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10974 13:59:54.852669 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
10975 13:59:54.853122 end: 2 depthcharge-action (duration 00:01:25) [common]
10976 13:59:54.853591 start: 3 lava-test-retry (timeout 00:08:12) [common]
10977 13:59:54.854047 start: 3.1 lava-test-shell (timeout 00:08:12) [common]
10978 13:59:54.854440 Using namespace: common
10980 13:59:54.955564 / # #
10981 13:59:54.956188 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10982 13:59:54.962054 #
10983 13:59:54.962978 Using /lava-11372172
10985 13:59:55.064311 / # export SHELL=/bin/sh
10986 13:59:55.065152 export SHELL=/bin/sh<6>[ 18.111570] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
10987 13:59:55.065599 <6>[ 18.112136] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10988 13:59:55.070783
10990 13:59:55.172621 / # . /lava-11372172/environment
10991 13:59:55.178670 . /lava-11372172/environment
10993 13:59:55.280528 / # /lava-11372172/bin/lava-test-runner /lava-11372172/0
10994 13:59:55.281328 Test shell timeout: 10s (minimum of the action and connection timeout)
10995 13:59:55.286831 /lava-11372172/bin/lava-test-runner /lava-11372172/0
10996 13:59:55.312555 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10997 13:59:55.319059 + cd /lava-11372172/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10998 13:59:55.319611 + cat uuid
10999 13:59:55.322144 + UUID=11372172_1.5.2.3.1
11000 13:59:55.322720 + set +x
11001 13:59:55.329074 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11372172_1.5.2.3.1>
11002 13:59:55.329941 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11372172_1.5.2.3.1
11003 13:59:55.330349 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11372172_1.5.2.3.1)
11004 13:59:55.331151 Skipping test definition patterns.
11005 13:59:55.332119 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11006 13:59:55.338578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11007 13:59:55.339099 device: /dev/video2
11008 13:59:55.339724 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11010 13:59:55.348724 <4>[ 18.409649] use of bytesused == 0 is deprecated and will be removed in the future,
11011 13:59:55.352291 <4>[ 18.409660] use the actual size instead.
11012 13:59:55.358522 <4>[ 18.411980] ------------[ cut here ]------------
11013 13:59:55.365333 v4l2-compliance <4>[ 18.411987] get_vaddr_frames() cannot follow VM_IO mapping
11014 13:59:55.378643 1.25.0-1, 64 bit<4>[ 18.412141] WARNING: CPU: 1 PID: 326 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11015 13:59:55.428006 s, 64-bit time_t<4>[ 18.412206] Modules linked in: mtk_vcodec_enc btusb mt7921e mtk_vcodec_common btintel btmtk mt7921_common btrtl mtk_vpu mt76_connac_lib btbcm uvcvideo mt76 v4l2_mem2mem videobuf2_vmalloc videobuf2_dma_contig bluetooth mac80211 r8153_ecm videobuf2_memops videobuf2_v4l2 cdc_ether libarc4 ecdh_generic cros_ec_rpmsg cfg80211 ecc crct10dif_ce elants_i2c rfkill videobuf2_common elan_i2c sbs_battery usbnet videodev mc r8152 hid_google_hammer hid_vivaldi_common mtk_scp cros_ec_chardev cros_ec_typec pcie_mediatek_gen3 mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11016 13:59:55.428594
11017 13:59:55.437456 v4l2-complianc<4>[ 18.412333] CPU: 1 PID: 326 Comm: v4l2-compliance Not tainted 6.1.46-cip4-rt2 #1
11018 13:59:55.444113 e SHA: 16e70e285<4>[ 18.412341] Hardware name: Google Spherion (rev0 - 3) (DT)
11019 13:59:55.454136 84c 2023-06-22 0<4>[ 18.412346] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11020 13:59:55.461162 <4>[ 18.412353] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11021 13:59:55.467125 <4>[ 18.412374] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11022 13:59:55.470568 <4>[ 18.412395] sp : ffff80000924b850
11023 13:59:55.477650 <4>[ 18.412398] x29: ffff80000924b850 x28: ffffad21c5275000 x27: ffffad21c5271238
11024 13:59:55.484329 <4>[ 18.412409] x26: 0000000000000000 x25: ffffad21fe62ce20 x24: ffff116c0a3fd298
11025 13:59:55.490543 <4>[ 18.412420] x23: ffff116c0c0b2c00 x22: ffff116c00e01410 x21: 0000000000000000
11026 13:59:55.500817 <4>[ 18.412431] x20: 00000000fffffff2 x19: ffff116c0e595700 x18: fffffffffffe9d18
11027 13:59:55.507075 <4>[ 18.412442] x17: 0000000000000000 x16: ffffad21fc48bbb0 x15: 0000000000000038
11028 13:59:55.513415 <4>[ 18.412453] x14: 0000320000003200 x13: 676e697070616d20 x12: 4f495f4d5620776f
11029 13:59:55.520634 <4>[ 18.412463] x11: 6c6c6f6620746f6e x10: 6e61632029287365 x9 : 776f6c6c6f662074
11030 13:59:55.527196 <4>[ 18.412474] x8 : ffffad21fef13450 x7 : ffff80000924b660 x6 : 00000000fffff230
11031 13:59:55.536818 <4>[ 18.412484] x5 : ffff116d3ef2aa18 x4 : 00000000fffff230 x3 : ffff644b406d7000
11032 13:59:55.543509 <4>[ 18.412495] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff116c0c324b00
11033 13:59:55.546740 <4>[ 18.412506] Call trace:
11034 13:59:55.549863 <4>[ 18.412510] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11035 13:59:55.556634 <4>[ 18.412531] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11036 13:59:55.563763 <4>[ 18.412546] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11037 13:59:55.570231 <4>[ 18.412565] __prepare_userptr+0x280/0x410 [videobuf2_common]
11038 13:59:55.576684 <4>[ 18.412585] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11039 13:59:55.582584 <4>[ 18.412606] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11040 13:59:55.586782 <4>[ 18.412626] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11041 13:59:55.592903 <4>[ 18.412653] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11042 13:59:55.599537 <4>[ 18.412707] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11043 13:59:55.602912 <4>[ 18.412728] v4l_prepare_buf+0x48/0x60 [videodev]
11044 13:59:55.609481 <4>[ 18.412821] __video_do_ioctl+0x184/0x3d0 [videodev]
11045 13:59:55.616044 <4>[ 18.412878] video_usercopy+0x358/0x680 [videodev]
11046 13:59:55.619080 <4>[ 18.412936] video_ioctl2+0x18/0x30 [videodev]
11047 13:59:55.622443 <4>[ 18.412993] v4l2_ioctl+0x40/0x60 [videodev]
11048 13:59:55.629435 <4>[ 18.413050] __arm64_sys_ioctl+0xa8/0xf0
11049 13:59:55.632849 <4>[ 18.413065] invoke_syscall+0x48/0x114
11050 13:59:55.636109 <4>[ 18.413078] el0_svc_common.constprop.0+0x44/0xec
11051 13:59:55.639396 <4>[ 18.413086] do_el0_svc+0x2c/0xd0
11052 13:59:55.642349 <4>[ 18.413094] el0_svc+0x2c/0x84
11053 13:59:55.648857 <4>[ 18.413103] el0t_64_sync_handler+0xb8/0xc0
11054 13:59:55.652581 <4>[ 18.413109] el0t_64_sync+0x18c/0x190
11055 13:59:55.655638 <4>[ 18.413117] ---[ end trace 0000000000000000 ]---
11056 13:59:55.659019 9:47:27
11057 13:59:55.659577
11058 13:59:55.662320 Compliance test for mtk-vcodec-enc device /dev/video2:
11059 13:59:55.662918
11060 13:59:55.665599 Driver Info:
11061 13:59:55.666150 Driver name : mtk-vcodec-enc
11062 13:59:55.672099 Card type : MT8192 video encoder
11063 13:59:55.675199 Bus info : platform:17020000.vcodec
11064 13:59:55.678663 Driver version : 6.1.46
11065 13:59:55.683554 Capabilities : 0x84204000
11066 13:59:55.697953 Video Memory-to-Memory Multiplanar
11067 13:59:55.710057 Streaming
11068 13:59:55.725973 Extended Pix Format
11069 13:59:55.736519 Device Capabilities
11070 13:59:55.746076 Device Caps : 0x04204000
11071 13:59:55.753761 Video Memory-to-Memory Multiplanar
11072 13:59:55.764524 Streaming
11073 13:59:55.776244 Extended Pix Format
11074 13:59:55.788006 Detected Stateful Encoder
11075 13:59:55.800531
11076 13:59:55.813344 Required ioctls:
11077 13:59:55.828970 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11078 13:59:55.829525 test VIDIOC_QUERYCAP: OK
11079 13:59:55.830226 Received signal: <TESTSET> START Required-ioctls
11080 13:59:55.830664 Starting test_set Required-ioctls
11081 13:59:55.853075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11082 13:59:55.853910 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11084 13:59:55.856095 test invalid ioctls: OK
11085 13:59:55.879019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11086 13:59:55.879577
11087 13:59:55.880217 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11089 13:59:55.889121 Allow for multiple opens:
11090 13:59:55.896321 <LAVA_SIGNAL_TESTSET STOP>
11091 13:59:55.897150 Received signal: <TESTSET> STOP
11092 13:59:55.897548 Closing test_set Required-ioctls
11093 13:59:55.905881 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11094 13:59:55.906758 Received signal: <TESTSET> START Allow-for-multiple-opens
11095 13:59:55.907167 Starting test_set Allow-for-multiple-opens
11096 13:59:55.909164 test second /dev/video2 open: OK
11097 13:59:55.929706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11098 13:59:55.930382 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11100 13:59:55.932948 test VIDIOC_QUERYCAP: OK
11101 13:59:55.955085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11102 13:59:55.955924 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11104 13:59:55.957950 test VIDIOC_G/S_PRIORITY: OK
11105 13:59:55.979861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11106 13:59:55.980704 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11108 13:59:55.983751 test for unlimited opens: OK
11109 13:59:56.004149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11110 13:59:56.004911
11111 13:59:56.005580 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11113 13:59:56.016604 Debug ioctls:
11114 13:59:56.025402 <LAVA_SIGNAL_TESTSET STOP>
11115 13:59:56.026231 Received signal: <TESTSET> STOP
11116 13:59:56.026660 Closing test_set Allow-for-multiple-opens
11117 13:59:56.036615 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11118 13:59:56.037438 Received signal: <TESTSET> START Debug-ioctls
11119 13:59:56.037835 Starting test_set Debug-ioctls
11120 13:59:56.039435 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11121 13:59:56.060371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11122 13:59:56.061209 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11124 13:59:56.066786 test VIDIOC_LOG_STATUS: OK (Not Supported)
11125 13:59:56.083704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11126 13:59:56.084254
11127 13:59:56.084898 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11129 13:59:56.099813 Input ioctls:
11130 13:59:56.107349 <LAVA_SIGNAL_TESTSET STOP>
11131 13:59:56.108187 Received signal: <TESTSET> STOP
11132 13:59:56.108573 Closing test_set Debug-ioctls
11133 13:59:56.117078 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11134 13:59:56.117917 Received signal: <TESTSET> START Input-ioctls
11135 13:59:56.118310 Starting test_set Input-ioctls
11136 13:59:56.119911 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11137 13:59:56.147171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11138 13:59:56.148009 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11140 13:59:56.150347 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11141 13:59:56.168374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11142 13:59:56.169218 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11144 13:59:56.175151 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11145 13:59:56.193297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11146 13:59:56.194176 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11148 13:59:56.199789 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11149 13:59:56.220352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11150 13:59:56.221199 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11152 13:59:56.223741 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11153 13:59:56.244342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11154 13:59:56.245182 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11156 13:59:56.247343 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11157 13:59:56.271465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11158 13:59:56.272303 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11160 13:59:56.274644 Inputs: 0 Audio Inputs: 0 Tuners: 0
11161 13:59:56.281465
11162 13:59:56.301887 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11163 13:59:56.324734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11164 13:59:56.325580 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11166 13:59:56.330982 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11167 13:59:56.348463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11168 13:59:56.349334 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11170 13:59:56.355024 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11171 13:59:56.373011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11172 13:59:56.373849 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11174 13:59:56.379282 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11175 13:59:56.396909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11176 13:59:56.397727 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11178 13:59:56.403398 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11179 13:59:56.427950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11180 13:59:56.428508
11181 13:59:56.429151 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11183 13:59:56.450648 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11184 13:59:56.475601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11185 13:59:56.476434 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11187 13:59:56.481977 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11188 13:59:56.504020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11189 13:59:56.504825 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11191 13:59:56.507553 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11192 13:59:56.530340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11193 13:59:56.531326 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11195 13:59:56.533257 test VIDIOC_G/S_EDID: OK (Not Supported)
11196 13:59:56.555528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11197 13:59:56.556087
11198 13:59:56.556722 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11200 13:59:56.567164 Control ioctls:
11201 13:59:56.577863 <LAVA_SIGNAL_TESTSET STOP>
11202 13:59:56.578720 Received signal: <TESTSET> STOP
11203 13:59:56.579110 Closing test_set Input-ioctls
11204 13:59:56.588211 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11205 13:59:56.589061 Received signal: <TESTSET> START Control-ioctls
11206 13:59:56.589480 Starting test_set Control-ioctls
11207 13:59:56.591425 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11208 13:59:56.616991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11209 13:59:56.617549 test VIDIOC_QUERYCTRL: OK
11210 13:59:56.618187 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11212 13:59:56.637864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11213 13:59:56.638745 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11215 13:59:56.640946 test VIDIOC_G/S_CTRL: OK
11216 13:59:56.662724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11217 13:59:56.663575 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11219 13:59:56.666317 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11220 13:59:56.688126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11221 13:59:56.689015 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11223 13:59:56.698272 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11224 13:59:56.700903 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11225 13:59:56.728108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11226 13:59:56.728951 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11228 13:59:56.732342 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11229 13:59:56.753443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11230 13:59:56.754285 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11232 13:59:56.755855 Standard Controls: 16 Private Controls: 0
11233 13:59:56.763400
11234 13:59:56.777971 Format ioctls:
11235 13:59:56.784082 <LAVA_SIGNAL_TESTSET STOP>
11236 13:59:56.784808 Received signal: <TESTSET> STOP
11237 13:59:56.785193 Closing test_set Control-ioctls
11238 13:59:56.794434 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11239 13:59:56.795338 Received signal: <TESTSET> START Format-ioctls
11240 13:59:56.795733 Starting test_set Format-ioctls
11241 13:59:56.799949 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11242 13:59:56.825524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11243 13:59:56.826368 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11245 13:59:56.828486 test VIDIOC_G/S_PARM: OK
11246 13:59:56.846776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11247 13:59:56.847617 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11249 13:59:56.849563 test VIDIOC_G_FBUF: OK (Not Supported)
11250 13:59:56.871297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11251 13:59:56.872146 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11253 13:59:56.874393 test VIDIOC_G_FMT: OK
11254 13:59:56.900124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11255 13:59:56.900997 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11257 13:59:56.903176 test VIDIOC_TRY_FMT: OK
11258 13:59:56.924591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11259 13:59:56.925429 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11261 13:59:56.934290 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11262 13:59:56.937337 test VIDIOC_S_FMT: FAIL
11263 13:59:56.967582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11264 13:59:56.968422 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11266 13:59:56.970906 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11267 13:59:56.994558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11268 13:59:56.995421 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11270 13:59:56.998098 test Cropping: OK
11271 13:59:57.020516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11272 13:59:57.021340 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11274 13:59:57.023162 test Composing: OK (Not Supported)
11275 13:59:57.051234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11276 13:59:57.052358 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11278 13:59:57.054035 test Scaling: OK (Not Supported)
11279 13:59:57.080967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11280 13:59:57.081518
11281 13:59:57.082173 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11283 13:59:57.091740 Codec ioctls:
11284 13:59:57.098552 <LAVA_SIGNAL_TESTSET STOP>
11285 13:59:57.099481 Received signal: <TESTSET> STOP
11286 13:59:57.099907 Closing test_set Format-ioctls
11287 13:59:57.107932 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11288 13:59:57.108779 Received signal: <TESTSET> START Codec-ioctls
11289 13:59:57.109210 Starting test_set Codec-ioctls
11290 13:59:57.112154 test VIDIOC_(TRY_)ENCODER_CMD: OK
11291 13:59:57.132356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11292 13:59:57.133197 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11294 13:59:57.138565 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11295 13:59:57.157544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11296 13:59:57.158383 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11298 13:59:57.164221 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11299 13:59:57.181867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11300 13:59:57.182417
11301 13:59:57.183111 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11303 13:59:57.194362 Buffer ioctls:
11304 13:59:57.200952 <LAVA_SIGNAL_TESTSET STOP>
11305 13:59:57.201783 Received signal: <TESTSET> STOP
11306 13:59:57.202170 Closing test_set Codec-ioctls
11307 13:59:57.209999 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11308 13:59:57.210847 Received signal: <TESTSET> START Buffer-ioctls
11309 13:59:57.211248 Starting test_set Buffer-ioctls
11310 13:59:57.213049 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11311 13:59:57.238551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11312 13:59:57.239162 test VIDIOC_EXPBUF: OK
11313 13:59:57.239807 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11315 13:59:57.259310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11316 13:59:57.260165 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11318 13:59:57.262358 test Requests: OK (Not Supported)
11319 13:59:57.285337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11320 13:59:57.285900
11321 13:59:57.286542 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11323 13:59:57.293784 Test input 0:
11324 13:59:57.303791
11325 13:59:57.313892 Streaming ioctls:
11326 13:59:57.320754 <LAVA_SIGNAL_TESTSET STOP>
11327 13:59:57.321591 Received signal: <TESTSET> STOP
11328 13:59:57.321978 Closing test_set Buffer-ioctls
11329 13:59:57.330695 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11330 13:59:57.331558 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11331 13:59:57.331963 Starting test_set Streaming-ioctls_Test-input-0
11332 13:59:57.333852 test read/write: OK (Not Supported)
11333 13:59:57.357175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11334 13:59:57.358038 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11336 13:59:57.363939 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11337 13:59:57.374149 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11338 13:59:57.380328 test blocking wait: FAIL
11339 13:59:57.407390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11340 13:59:57.408234 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11342 13:59:57.416812 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11343 13:59:57.420347 test MMAP (select): FAIL
11344 13:59:57.443736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11345 13:59:57.444565 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11347 13:59:57.450228 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11348 13:59:57.453886 test MMAP (epoll): FAIL
11349 13:59:57.478074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11350 13:59:57.478963 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11352 13:59:57.487864 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11353 13:59:57.494202 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11354 13:59:57.503337 test USERPTR (select): FAIL
11355 13:59:57.528222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11356 13:59:57.529074 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11358 13:59:57.534540 test DMABUF: Cannot test, specify --expbuf-device
11359 13:59:57.539626
11360 13:59:57.558905 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11361 13:59:57.562370 <LAVA_TEST_RUNNER EXIT>
11362 13:59:57.563438 ok: lava_test_shell seems to have completed
11363 13:59:57.563884 Marking unfinished test run as failed
11365 13:59:57.568872 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11366 13:59:57.569511 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11367 13:59:57.569985 end: 3 lava-test-retry (duration 00:00:03) [common]
11368 13:59:57.570471 start: 4 finalize (timeout 00:08:10) [common]
11369 13:59:57.570977 start: 4.1 power-off (timeout 00:00:30) [common]
11370 13:59:57.571806 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11371 13:59:57.656451 >> Command sent successfully.
11372 13:59:57.667000 Returned 0 in 0 seconds
11373 13:59:57.768319 end: 4.1 power-off (duration 00:00:00) [common]
11375 13:59:57.769754 start: 4.2 read-feedback (timeout 00:08:09) [common]
11376 13:59:57.771110 Listened to connection for namespace 'common' for up to 1s
11377 13:59:58.770919 Finalising connection for namespace 'common'
11378 13:59:58.771760 Disconnecting from shell: Finalise
11379 13:59:58.772250 / #
11380 13:59:58.873400 end: 4.2 read-feedback (duration 00:00:01) [common]
11381 13:59:58.874096 end: 4 finalize (duration 00:00:01) [common]
11382 13:59:58.874776 Cleaning after the job
11383 13:59:58.875423 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/ramdisk
11384 13:59:58.900801 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/kernel
11385 13:59:58.919054 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/dtb
11386 13:59:58.919367 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11372172/tftp-deploy-mxyag6t_/modules
11387 13:59:58.929550 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11372172
11388 13:59:58.998442 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11372172
11389 13:59:58.998630 Job finished correctly