Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 34
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 22
1 13:57:19.325533 lava-dispatcher, installed at version: 2023.06
2 13:57:19.325731 start: 0 validate
3 13:57:19.325873 Start time: 2023-09-21 13:57:19.325865+00:00 (UTC)
4 13:57:19.326001 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:57:19.326145 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:57:19.619312 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:57:19.620132 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:57:19.892658 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:57:19.893422 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:58:09.212732 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:58:09.213422 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:58:09.751914 validate duration: 50.43
14 13:58:09.753178 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:58:09.753728 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:58:09.754206 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:58:09.754836 Not decompressing ramdisk as can be used compressed.
18 13:58:09.755321 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 13:58:09.755693 saving as /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/ramdisk/rootfs.cpio.gz
20 13:58:09.756131 total size: 8181372 (7 MB)
21 13:58:13.676701 progress 0 % (0 MB)
22 13:58:13.688304 progress 5 % (0 MB)
23 13:58:13.699105 progress 10 % (0 MB)
24 13:58:13.708401 progress 15 % (1 MB)
25 13:58:13.714148 progress 20 % (1 MB)
26 13:58:13.718953 progress 25 % (1 MB)
27 13:58:13.722778 progress 30 % (2 MB)
28 13:58:13.726464 progress 35 % (2 MB)
29 13:58:13.729582 progress 40 % (3 MB)
30 13:58:13.732734 progress 45 % (3 MB)
31 13:58:13.735398 progress 50 % (3 MB)
32 13:58:13.738226 progress 55 % (4 MB)
33 13:58:13.740531 progress 60 % (4 MB)
34 13:58:13.743009 progress 65 % (5 MB)
35 13:58:13.745113 progress 70 % (5 MB)
36 13:58:13.747359 progress 75 % (5 MB)
37 13:58:13.749428 progress 80 % (6 MB)
38 13:58:13.751653 progress 85 % (6 MB)
39 13:58:13.753699 progress 90 % (7 MB)
40 13:58:13.755901 progress 95 % (7 MB)
41 13:58:13.757967 progress 100 % (7 MB)
42 13:58:13.758167 7 MB downloaded in 4.00 s (1.95 MB/s)
43 13:58:13.758319 end: 1.1.1 http-download (duration 00:00:04) [common]
45 13:58:13.758557 end: 1.1 download-retry (duration 00:00:04) [common]
46 13:58:13.758642 start: 1.2 download-retry (timeout 00:09:56) [common]
47 13:58:13.758725 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 13:58:13.758863 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:58:13.758930 saving as /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/kernel/Image
50 13:58:13.758990 total size: 49304064 (47 MB)
51 13:58:13.759050 No compression specified
52 13:58:14.018706 progress 0 % (0 MB)
53 13:58:14.066433 progress 5 % (2 MB)
54 13:58:14.084251 progress 10 % (4 MB)
55 13:58:14.097379 progress 15 % (7 MB)
56 13:58:14.110068 progress 20 % (9 MB)
57 13:58:14.122969 progress 25 % (11 MB)
58 13:58:14.135389 progress 30 % (14 MB)
59 13:58:14.147797 progress 35 % (16 MB)
60 13:58:14.160297 progress 40 % (18 MB)
61 13:58:14.173058 progress 45 % (21 MB)
62 13:58:14.185877 progress 50 % (23 MB)
63 13:58:14.198537 progress 55 % (25 MB)
64 13:58:14.211330 progress 60 % (28 MB)
65 13:58:14.224243 progress 65 % (30 MB)
66 13:58:14.236901 progress 70 % (32 MB)
67 13:58:14.249451 progress 75 % (35 MB)
68 13:58:14.261982 progress 80 % (37 MB)
69 13:58:14.274505 progress 85 % (39 MB)
70 13:58:14.287343 progress 90 % (42 MB)
71 13:58:14.299946 progress 95 % (44 MB)
72 13:58:14.312400 progress 100 % (47 MB)
73 13:58:14.312603 47 MB downloaded in 0.55 s (84.93 MB/s)
74 13:58:14.312750 end: 1.2.1 http-download (duration 00:00:01) [common]
76 13:58:14.312982 end: 1.2 download-retry (duration 00:00:01) [common]
77 13:58:14.313073 start: 1.3 download-retry (timeout 00:09:55) [common]
78 13:58:14.313157 start: 1.3.1 http-download (timeout 00:09:55) [common]
79 13:58:14.313377 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:58:14.313485 saving as /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/dtb/mt8192-asurada-spherion-r0.dtb
81 13:58:14.313576 total size: 47278 (0 MB)
82 13:58:14.313667 No compression specified
83 13:58:14.314825 progress 69 % (0 MB)
84 13:58:14.315095 progress 100 % (0 MB)
85 13:58:14.315249 0 MB downloaded in 0.00 s (27.00 MB/s)
86 13:58:14.315370 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:58:14.315589 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:58:14.315674 start: 1.4 download-retry (timeout 00:09:55) [common]
90 13:58:14.315796 start: 1.4.1 http-download (timeout 00:09:55) [common]
91 13:58:14.315910 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:58:14.315982 saving as /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/modules/modules.tar
93 13:58:14.316042 total size: 8629568 (8 MB)
94 13:58:14.316103 Using unxz to decompress xz
95 13:58:14.320191 progress 0 % (0 MB)
96 13:58:14.341893 progress 5 % (0 MB)
97 13:58:14.363789 progress 10 % (0 MB)
98 13:58:14.389495 progress 15 % (1 MB)
99 13:58:14.414452 progress 20 % (1 MB)
100 13:58:14.439828 progress 25 % (2 MB)
101 13:58:14.467302 progress 30 % (2 MB)
102 13:58:14.491649 progress 35 % (2 MB)
103 13:58:14.516107 progress 40 % (3 MB)
104 13:58:14.539673 progress 45 % (3 MB)
105 13:58:14.565216 progress 50 % (4 MB)
106 13:58:14.590046 progress 55 % (4 MB)
107 13:58:14.616103 progress 60 % (4 MB)
108 13:58:14.638711 progress 65 % (5 MB)
109 13:58:14.663259 progress 70 % (5 MB)
110 13:58:14.687329 progress 75 % (6 MB)
111 13:58:14.713991 progress 80 % (6 MB)
112 13:58:14.742664 progress 85 % (7 MB)
113 13:58:14.772060 progress 90 % (7 MB)
114 13:58:14.796255 progress 95 % (7 MB)
115 13:58:14.819289 progress 100 % (8 MB)
116 13:58:14.824464 8 MB downloaded in 0.51 s (16.19 MB/s)
117 13:58:14.824718 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:58:14.824984 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:58:14.825078 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 13:58:14.825175 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 13:58:14.825261 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:58:14.825348 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 13:58:14.825580 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp
125 13:58:14.825720 makedir: /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin
126 13:58:14.825829 makedir: /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/tests
127 13:58:14.825930 makedir: /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/results
128 13:58:14.826048 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-add-keys
129 13:58:14.826200 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-add-sources
130 13:58:14.826331 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-background-process-start
131 13:58:14.826463 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-background-process-stop
132 13:58:14.826590 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-common-functions
133 13:58:14.826716 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-echo-ipv4
134 13:58:14.826846 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-install-packages
135 13:58:14.826974 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-installed-packages
136 13:58:14.827100 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-os-build
137 13:58:14.827227 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-probe-channel
138 13:58:14.827354 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-probe-ip
139 13:58:14.827479 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-target-ip
140 13:58:14.827605 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-target-mac
141 13:58:14.827734 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-target-storage
142 13:58:14.827905 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-test-case
143 13:58:14.828031 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-test-event
144 13:58:14.828156 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-test-feedback
145 13:58:14.828282 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-test-raise
146 13:58:14.828409 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-test-reference
147 13:58:14.828534 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-test-runner
148 13:58:14.828659 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-test-set
149 13:58:14.828786 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-test-shell
150 13:58:14.828916 Updating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-install-packages (oe)
151 13:58:14.829071 Updating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/bin/lava-installed-packages (oe)
152 13:58:14.829198 Creating /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/environment
153 13:58:14.829301 LAVA metadata
154 13:58:14.829375 - LAVA_JOB_ID=11588086
155 13:58:14.829440 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:58:14.829545 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 13:58:14.829612 skipped lava-vland-overlay
158 13:58:14.829687 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:58:14.829769 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 13:58:14.829830 skipped lava-multinode-overlay
161 13:58:14.829905 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:58:14.829985 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 13:58:14.830065 Loading test definitions
164 13:58:14.830164 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 13:58:14.830237 Using /lava-11588086 at stage 0
166 13:58:14.830557 uuid=11588086_1.5.2.3.1 testdef=None
167 13:58:14.830646 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:58:14.830732 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 13:58:14.831276 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:58:14.831495 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 13:58:14.832217 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:58:14.832450 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 13:58:14.833085 runner path: /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/0/tests/0_dmesg test_uuid 11588086_1.5.2.3.1
176 13:58:14.833243 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:58:14.833470 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:55) [common]
179 13:58:14.833542 Using /lava-11588086 at stage 1
180 13:58:14.833848 uuid=11588086_1.5.2.3.5 testdef=None
181 13:58:14.833937 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 13:58:14.834022 start: 1.5.2.3.6 test-overlay (timeout 00:09:55) [common]
183 13:58:14.834555 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 13:58:14.834772 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:55) [common]
186 13:58:14.835943 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 13:58:14.836174 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:55) [common]
189 13:58:14.836811 runner path: /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/1/tests/1_bootrr test_uuid 11588086_1.5.2.3.5
190 13:58:14.836964 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 13:58:14.837172 Creating lava-test-runner.conf files
193 13:58:14.837237 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/0 for stage 0
194 13:58:14.837329 - 0_dmesg
195 13:58:14.837408 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11588086/lava-overlay-udbenlnp/lava-11588086/1 for stage 1
196 13:58:14.837501 - 1_bootrr
197 13:58:14.837596 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 13:58:14.837683 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
199 13:58:14.845681 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 13:58:14.845796 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
201 13:58:14.845885 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 13:58:14.845972 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 13:58:14.846058 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
204 13:58:15.092782 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 13:58:15.093175 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
206 13:58:15.093299 extracting modules file /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11588086/extract-overlay-ramdisk-7cse5xd4/ramdisk
207 13:58:15.313740 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 13:58:15.313916 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
209 13:58:15.314009 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11588086/compress-overlay-jz7e5amc/overlay-1.5.2.4.tar.gz to ramdisk
210 13:58:15.314082 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11588086/compress-overlay-jz7e5amc/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11588086/extract-overlay-ramdisk-7cse5xd4/ramdisk
211 13:58:15.322362 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 13:58:15.322472 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
213 13:58:15.322564 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 13:58:15.322650 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
215 13:58:15.322732 Building ramdisk /var/lib/lava/dispatcher/tmp/11588086/extract-overlay-ramdisk-7cse5xd4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11588086/extract-overlay-ramdisk-7cse5xd4/ramdisk
216 13:58:15.724164 >> 145268 blocks
217 13:58:17.965108 rename /var/lib/lava/dispatcher/tmp/11588086/extract-overlay-ramdisk-7cse5xd4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/ramdisk/ramdisk.cpio.gz
218 13:58:17.965559 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 13:58:17.965684 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
220 13:58:17.965789 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
221 13:58:17.965900 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/kernel/Image'
222 13:58:29.830635 Returned 0 in 11 seconds
223 13:58:29.931622 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/kernel/image.itb
224 13:58:30.343387 output: FIT description: Kernel Image image with one or more FDT blobs
225 13:58:30.343804 output: Created: Thu Sep 21 14:58:30 2023
226 13:58:30.343898 output: Image 0 (kernel-1)
227 13:58:30.343971 output: Description:
228 13:58:30.344039 output: Created: Thu Sep 21 14:58:30 2023
229 13:58:30.344102 output: Type: Kernel Image
230 13:58:30.344165 output: Compression: lzma compressed
231 13:58:30.344226 output: Data Size: 11044874 Bytes = 10786.01 KiB = 10.53 MiB
232 13:58:30.344289 output: Architecture: AArch64
233 13:58:30.344349 output: OS: Linux
234 13:58:30.344409 output: Load Address: 0x00000000
235 13:58:30.344464 output: Entry Point: 0x00000000
236 13:58:30.344518 output: Hash algo: crc32
237 13:58:30.344573 output: Hash value: a5f1a0d7
238 13:58:30.344628 output: Image 1 (fdt-1)
239 13:58:30.344683 output: Description: mt8192-asurada-spherion-r0
240 13:58:30.344738 output: Created: Thu Sep 21 14:58:30 2023
241 13:58:30.344793 output: Type: Flat Device Tree
242 13:58:30.344847 output: Compression: uncompressed
243 13:58:30.344901 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 13:58:30.344956 output: Architecture: AArch64
245 13:58:30.345010 output: Hash algo: crc32
246 13:58:30.345065 output: Hash value: cc4352de
247 13:58:30.345119 output: Image 2 (ramdisk-1)
248 13:58:30.345172 output: Description: unavailable
249 13:58:30.345226 output: Created: Thu Sep 21 14:58:30 2023
250 13:58:30.345280 output: Type: RAMDisk Image
251 13:58:30.345334 output: Compression: Unknown Compression
252 13:58:30.345387 output: Data Size: 21393819 Bytes = 20892.40 KiB = 20.40 MiB
253 13:58:30.345441 output: Architecture: AArch64
254 13:58:30.345495 output: OS: Linux
255 13:58:30.345549 output: Load Address: unavailable
256 13:58:30.345603 output: Entry Point: unavailable
257 13:58:30.345657 output: Hash algo: crc32
258 13:58:30.345710 output: Hash value: fff07421
259 13:58:30.345764 output: Default Configuration: 'conf-1'
260 13:58:30.345818 output: Configuration 0 (conf-1)
261 13:58:30.345871 output: Description: mt8192-asurada-spherion-r0
262 13:58:30.345925 output: Kernel: kernel-1
263 13:58:30.345979 output: Init Ramdisk: ramdisk-1
264 13:58:30.346032 output: FDT: fdt-1
265 13:58:30.346085 output: Loadables: kernel-1
266 13:58:30.346138 output:
267 13:58:30.346345 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
268 13:58:30.346444 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
269 13:58:30.346548 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 13:58:30.346642 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
271 13:58:30.346720 No LXC device requested
272 13:58:30.346801 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 13:58:30.346887 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
274 13:58:30.346967 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 13:58:30.347037 Checking files for TFTP limit of 4294967296 bytes.
276 13:58:30.347550 end: 1 tftp-deploy (duration 00:00:21) [common]
277 13:58:30.347652 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 13:58:30.347753 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 13:58:30.347915 substitutions:
280 13:58:30.347982 - {DTB}: 11588086/tftp-deploy-69elt4hq/dtb/mt8192-asurada-spherion-r0.dtb
281 13:58:30.348048 - {INITRD}: 11588086/tftp-deploy-69elt4hq/ramdisk/ramdisk.cpio.gz
282 13:58:30.348109 - {KERNEL}: 11588086/tftp-deploy-69elt4hq/kernel/Image
283 13:58:30.348168 - {LAVA_MAC}: None
284 13:58:30.348225 - {PRESEED_CONFIG}: None
285 13:58:30.348282 - {PRESEED_LOCAL}: None
286 13:58:30.348337 - {RAMDISK}: 11588086/tftp-deploy-69elt4hq/ramdisk/ramdisk.cpio.gz
287 13:58:30.348393 - {ROOT_PART}: None
288 13:58:30.348448 - {ROOT}: None
289 13:58:30.348503 - {SERVER_IP}: 192.168.201.1
290 13:58:30.348558 - {TEE}: None
291 13:58:30.348614 Parsed boot commands:
292 13:58:30.348668 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 13:58:30.348849 Parsed boot commands: tftpboot 192.168.201.1 11588086/tftp-deploy-69elt4hq/kernel/image.itb 11588086/tftp-deploy-69elt4hq/kernel/cmdline
294 13:58:30.348938 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 13:58:30.349026 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 13:58:30.349118 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 13:58:30.349207 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 13:58:30.349278 Not connected, no need to disconnect.
299 13:58:30.349355 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 13:58:30.349436 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 13:58:30.349502 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
302 13:58:30.353629 Setting prompt string to ['lava-test: # ']
303 13:58:30.353993 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 13:58:30.354102 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 13:58:30.354219 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 13:58:30.354530 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 13:58:30.354761 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
308 13:58:35.508904 >> Command sent successfully.
309 13:58:35.520027 Returned 0 in 5 seconds
310 13:58:35.621138 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 13:58:35.622231 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 13:58:35.622622 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 13:58:35.622957 Setting prompt string to 'Starting depthcharge on Spherion...'
315 13:58:35.623207 Changing prompt to 'Starting depthcharge on Spherion...'
316 13:58:35.623470 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 13:58:35.624507 [Enter `^Ec?' for help]
318 13:58:35.787180
319 13:58:35.787755
320 13:58:35.788181 F0: 102B 0000
321 13:58:35.788528
322 13:58:35.788893 F3: 1001 0000 [0200]
323 13:58:35.789212
324 13:58:35.789804 F3: 1001 0000
325 13:58:35.790133
326 13:58:35.790435 F7: 102D 0000
327 13:58:35.790731
328 13:58:35.791021 F1: 0000 0000
329 13:58:35.793080
330 13:58:35.793508 V0: 0000 0000 [0001]
331 13:58:35.793850
332 13:58:35.794173 00: 0007 8000
333 13:58:35.794506
334 13:58:35.796687 01: 0000 0000
335 13:58:35.797128
336 13:58:35.797470 BP: 0C00 0209 [0000]
337 13:58:35.797795
338 13:58:35.800600 G0: 1182 0000
339 13:58:35.801032
340 13:58:35.801386 EC: 0000 0021 [4000]
341 13:58:35.801712
342 13:58:35.804909 S7: 0000 0000 [0000]
343 13:58:35.805339
344 13:58:35.805682 CC: 0000 0000 [0001]
345 13:58:35.806049
346 13:58:35.807459 T0: 0000 0040 [010F]
347 13:58:35.807920
348 13:58:35.808268 Jump to BL
349 13:58:35.808606
350 13:58:35.833136
351 13:58:35.833689
352 13:58:35.834040
353 13:58:35.840321 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 13:58:35.843817 ARM64: Exception handlers installed.
355 13:58:35.847088 ARM64: Testing exception
356 13:58:35.850728 ARM64: Done test exception
357 13:58:35.858076 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 13:58:35.869373 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 13:58:35.876198 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 13:58:35.883456 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 13:58:35.890546 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 13:58:35.900463 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 13:58:35.910309 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 13:58:35.917843 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 13:58:35.935638 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 13:58:35.938929 WDT: Last reset was cold boot
367 13:58:35.942352 SPI1(PAD0) initialized at 2873684 Hz
368 13:58:35.945809 SPI5(PAD0) initialized at 992727 Hz
369 13:58:35.948878 VBOOT: Loading verstage.
370 13:58:35.955517 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 13:58:35.959284 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 13:58:35.962245 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 13:58:35.965496 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 13:58:35.973214 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 13:58:35.979800 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 13:58:35.990554 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 13:58:35.991126
378 13:58:35.991503
379 13:58:36.000842 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 13:58:36.003947 ARM64: Exception handlers installed.
381 13:58:36.007324 ARM64: Testing exception
382 13:58:36.007962 ARM64: Done test exception
383 13:58:36.014687 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 13:58:36.016854 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 13:58:36.032277 Probing TPM: . done!
386 13:58:36.032848 TPM ready after 0 ms
387 13:58:36.038359 Connected to device vid:did:rid of 1ae0:0028:00
388 13:58:36.048321 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
389 13:58:36.086448 Initialized TPM device CR50 revision 0
390 13:58:36.097704 tlcl_send_startup: Startup return code is 0
391 13:58:36.098278 TPM: setup succeeded
392 13:58:36.108565 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 13:58:36.117247 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 13:58:36.123793 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 13:58:36.136670 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 13:58:36.139649 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 13:58:36.143427 in-header: 03 07 00 00 08 00 00 00
398 13:58:36.146524 in-data: aa e4 47 04 13 02 00 00
399 13:58:36.149569 Chrome EC: UHEPI supported
400 13:58:36.156263 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 13:58:36.159502 in-header: 03 ad 00 00 08 00 00 00
402 13:58:36.162746 in-data: 00 20 20 08 00 00 00 00
403 13:58:36.163220 Phase 1
404 13:58:36.169873 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 13:58:36.172701 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 13:58:36.180139 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 13:58:36.183533 Recovery requested (1009000e)
408 13:58:36.187660 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 13:58:36.196646 tlcl_extend: response is 0
410 13:58:36.204209 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 13:58:36.209153 tlcl_extend: response is 0
412 13:58:36.216121 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 13:58:36.236443 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 13:58:36.242976 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 13:58:36.243545
416 13:58:36.244092
417 13:58:36.253761 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 13:58:36.257188 ARM64: Exception handlers installed.
419 13:58:36.257763 ARM64: Testing exception
420 13:58:36.260185 ARM64: Done test exception
421 13:58:36.281919 pmic_efuse_setting: Set efuses in 11 msecs
422 13:58:36.286075 pmwrap_interface_init: Select PMIF_VLD_RDY
423 13:58:36.289535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 13:58:36.296607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 13:58:36.299869 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 13:58:36.306596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 13:58:36.309753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 13:58:36.316576 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 13:58:36.320025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 13:58:36.323242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 13:58:36.329940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 13:58:36.332979 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 13:58:36.339557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 13:58:36.343123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 13:58:36.346212 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 13:58:36.353322 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 13:58:36.360299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 13:58:36.366824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 13:58:36.370060 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 13:58:36.376572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 13:58:36.383449 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 13:58:36.386711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 13:58:36.394012 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 13:58:36.400400 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 13:58:36.404139 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 13:58:36.411389 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 13:58:36.414849 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 13:58:36.421158 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 13:58:36.428053 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 13:58:36.431264 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 13:58:36.434972 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 13:58:36.442077 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 13:58:36.444937 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 13:58:36.451858 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 13:58:36.455367 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 13:58:36.462197 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 13:58:36.465373 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 13:58:36.471866 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 13:58:36.475285 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 13:58:36.482001 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 13:58:36.485125 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 13:58:36.489032 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 13:58:36.492998 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 13:58:36.500179 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 13:58:36.503581 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 13:58:36.507081 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 13:58:36.511276 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 13:58:36.517168 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 13:58:36.520732 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 13:58:36.523574 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 13:58:36.527775 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 13:58:36.533876 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 13:58:36.537446 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 13:58:36.543679 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 13:58:36.553769 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 13:58:36.556749 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 13:58:36.567103 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 13:58:36.573516 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 13:58:36.581021 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 13:58:36.583628 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 13:58:36.586806 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 13:58:36.594429 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x35
483 13:58:36.601383 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 13:58:36.604534 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
485 13:58:36.611291 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 13:58:36.619126 [RTC]rtc_get_frequency_meter,154: input=15, output=834
487 13:58:36.628454 [RTC]rtc_get_frequency_meter,154: input=7, output=708
488 13:58:36.637849 [RTC]rtc_get_frequency_meter,154: input=11, output=771
489 13:58:36.647703 [RTC]rtc_get_frequency_meter,154: input=13, output=803
490 13:58:36.656921 [RTC]rtc_get_frequency_meter,154: input=12, output=788
491 13:58:36.666642 [RTC]rtc_get_frequency_meter,154: input=12, output=787
492 13:58:36.676380 [RTC]rtc_get_frequency_meter,154: input=13, output=804
493 13:58:36.679851 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
494 13:58:36.687058 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
495 13:58:36.690022 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 13:58:36.693173 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 13:58:36.699897 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 13:58:36.703485 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 13:58:36.706372 ADC[4]: Raw value=903031 ID=7
500 13:58:36.706838 ADC[3]: Raw value=213282 ID=1
501 13:58:36.709706 RAM Code: 0x71
502 13:58:36.713068 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 13:58:36.719975 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 13:58:36.726422 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 13:58:36.732736 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 13:58:36.736334 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 13:58:36.739587 in-header: 03 07 00 00 08 00 00 00
508 13:58:36.743261 in-data: aa e4 47 04 13 02 00 00
509 13:58:36.745999 Chrome EC: UHEPI supported
510 13:58:36.752628 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 13:58:36.756040 in-header: 03 dd 00 00 08 00 00 00
512 13:58:36.759809 in-data: 90 20 60 08 00 00 00 00
513 13:58:36.763082 MRC: failed to locate region type 0.
514 13:58:36.769350 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 13:58:36.772920 DRAM-K: Running full calibration
516 13:58:36.779416 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 13:58:36.779929 header.status = 0x0
518 13:58:36.782773 header.version = 0x6 (expected: 0x6)
519 13:58:36.786152 header.size = 0xd00 (expected: 0xd00)
520 13:58:36.789876 header.flags = 0x0
521 13:58:36.796044 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 13:58:36.812948 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
523 13:58:36.819471 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 13:58:36.822506 dram_init: ddr_geometry: 2
525 13:58:36.826125 [EMI] MDL number = 2
526 13:58:36.826688 [EMI] Get MDL freq = 0
527 13:58:36.829743 dram_init: ddr_type: 0
528 13:58:36.830311 is_discrete_lpddr4: 1
529 13:58:36.832986 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 13:58:36.833551
531 13:58:36.836184
532 13:58:36.836746 [Bian_co] ETT version 0.0.0.1
533 13:58:36.842555 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 13:58:36.843120
535 13:58:36.846332 dramc_set_vcore_voltage set vcore to 650000
536 13:58:36.848909 Read voltage for 800, 4
537 13:58:36.849379 Vio18 = 0
538 13:58:36.849752 Vcore = 650000
539 13:58:36.852844 Vdram = 0
540 13:58:36.853310 Vddq = 0
541 13:58:36.853682 Vmddr = 0
542 13:58:36.855558 dram_init: config_dvfs: 1
543 13:58:36.860005 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 13:58:36.865971 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 13:58:36.869259 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
546 13:58:36.872423 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
547 13:58:36.876267 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
548 13:58:36.882625 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
549 13:58:36.883196 MEM_TYPE=3, freq_sel=18
550 13:58:36.885748 sv_algorithm_assistance_LP4_1600
551 13:58:36.888975 ============ PULL DRAM RESETB DOWN ============
552 13:58:36.895930 ========== PULL DRAM RESETB DOWN end =========
553 13:58:36.899081 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 13:58:36.902350 ===================================
555 13:58:36.905383 LPDDR4 DRAM CONFIGURATION
556 13:58:36.908858 ===================================
557 13:58:36.909428 EX_ROW_EN[0] = 0x0
558 13:58:36.913175 EX_ROW_EN[1] = 0x0
559 13:58:36.913738 LP4Y_EN = 0x0
560 13:58:36.915040 WORK_FSP = 0x0
561 13:58:36.918719 WL = 0x2
562 13:58:36.919285 RL = 0x2
563 13:58:36.921753 BL = 0x2
564 13:58:36.922342 RPST = 0x0
565 13:58:36.925128 RD_PRE = 0x0
566 13:58:36.925594 WR_PRE = 0x1
567 13:58:36.928687 WR_PST = 0x0
568 13:58:36.929156 DBI_WR = 0x0
569 13:58:36.932938 DBI_RD = 0x0
570 13:58:36.933464 OTF = 0x1
571 13:58:36.935521 ===================================
572 13:58:36.938722 ===================================
573 13:58:36.942190 ANA top config
574 13:58:36.946057 ===================================
575 13:58:36.946586 DLL_ASYNC_EN = 0
576 13:58:36.948411 ALL_SLAVE_EN = 1
577 13:58:36.951762 NEW_RANK_MODE = 1
578 13:58:36.955082 DLL_IDLE_MODE = 1
579 13:58:36.955509 LP45_APHY_COMB_EN = 1
580 13:58:36.958294 TX_ODT_DIS = 1
581 13:58:36.961874 NEW_8X_MODE = 1
582 13:58:36.965121 ===================================
583 13:58:36.968422 ===================================
584 13:58:36.971839 data_rate = 1600
585 13:58:36.974956 CKR = 1
586 13:58:36.975410 DQ_P2S_RATIO = 8
587 13:58:36.978155 ===================================
588 13:58:36.981745 CA_P2S_RATIO = 8
589 13:58:36.984804 DQ_CA_OPEN = 0
590 13:58:36.988162 DQ_SEMI_OPEN = 0
591 13:58:36.991844 CA_SEMI_OPEN = 0
592 13:58:36.995301 CA_FULL_RATE = 0
593 13:58:36.995893 DQ_CKDIV4_EN = 1
594 13:58:36.998446 CA_CKDIV4_EN = 1
595 13:58:37.001474 CA_PREDIV_EN = 0
596 13:58:37.005181 PH8_DLY = 0
597 13:58:37.008236 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 13:58:37.011710 DQ_AAMCK_DIV = 4
599 13:58:37.012475 CA_AAMCK_DIV = 4
600 13:58:37.015297 CA_ADMCK_DIV = 4
601 13:58:37.018530 DQ_TRACK_CA_EN = 0
602 13:58:37.021404 CA_PICK = 800
603 13:58:37.025423 CA_MCKIO = 800
604 13:58:37.028427 MCKIO_SEMI = 0
605 13:58:37.031802 PLL_FREQ = 3068
606 13:58:37.032228 DQ_UI_PI_RATIO = 32
607 13:58:37.035391 CA_UI_PI_RATIO = 0
608 13:58:37.038692 ===================================
609 13:58:37.041611 ===================================
610 13:58:37.045120 memory_type:LPDDR4
611 13:58:37.048152 GP_NUM : 10
612 13:58:37.048679 SRAM_EN : 1
613 13:58:37.051674 MD32_EN : 0
614 13:58:37.054857 ===================================
615 13:58:37.059231 [ANA_INIT] >>>>>>>>>>>>>>
616 13:58:37.059837 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 13:58:37.062033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 13:58:37.064887 ===================================
619 13:58:37.068515 data_rate = 1600,PCW = 0X7600
620 13:58:37.073448 ===================================
621 13:58:37.076099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 13:58:37.081140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 13:58:37.088470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 13:58:37.091542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 13:58:37.094802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 13:58:37.098507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 13:58:37.101117 [ANA_INIT] flow start
628 13:58:37.101556 [ANA_INIT] PLL >>>>>>>>
629 13:58:37.104344 [ANA_INIT] PLL <<<<<<<<
630 13:58:37.108043 [ANA_INIT] MIDPI >>>>>>>>
631 13:58:37.111289 [ANA_INIT] MIDPI <<<<<<<<
632 13:58:37.111867 [ANA_INIT] DLL >>>>>>>>
633 13:58:37.115106 [ANA_INIT] flow end
634 13:58:37.118169 ============ LP4 DIFF to SE enter ============
635 13:58:37.121269 ============ LP4 DIFF to SE exit ============
636 13:58:37.124267 [ANA_INIT] <<<<<<<<<<<<<
637 13:58:37.128584 [Flow] Enable top DCM control >>>>>
638 13:58:37.131319 [Flow] Enable top DCM control <<<<<
639 13:58:37.134447 Enable DLL master slave shuffle
640 13:58:37.137824 ==============================================================
641 13:58:37.141419 Gating Mode config
642 13:58:37.147772 ==============================================================
643 13:58:37.148317 Config description:
644 13:58:37.158067 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 13:58:37.164791 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 13:58:37.171083 SELPH_MODE 0: By rank 1: By Phase
647 13:58:37.174529 ==============================================================
648 13:58:37.178330 GAT_TRACK_EN = 1
649 13:58:37.181037 RX_GATING_MODE = 2
650 13:58:37.184779 RX_GATING_TRACK_MODE = 2
651 13:58:37.187775 SELPH_MODE = 1
652 13:58:37.191187 PICG_EARLY_EN = 1
653 13:58:37.194394 VALID_LAT_VALUE = 1
654 13:58:37.198629 ==============================================================
655 13:58:37.200965 Enter into Gating configuration >>>>
656 13:58:37.204143 Exit from Gating configuration <<<<
657 13:58:37.207848 Enter into DVFS_PRE_config >>>>>
658 13:58:37.220902 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 13:58:37.223861 Exit from DVFS_PRE_config <<<<<
660 13:58:37.227116 Enter into PICG configuration >>>>
661 13:58:37.227553 Exit from PICG configuration <<<<
662 13:58:37.230638 [RX_INPUT] configuration >>>>>
663 13:58:37.234152 [RX_INPUT] configuration <<<<<
664 13:58:37.240461 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 13:58:37.244559 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 13:58:37.251277 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 13:58:37.258373 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 13:58:37.266586 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 13:58:37.269490 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 13:58:37.273499 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 13:58:37.276289 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 13:58:37.283482 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 13:58:37.287380 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 13:58:37.291906 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 13:58:37.294718 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 13:58:37.298782 ===================================
677 13:58:37.302776 LPDDR4 DRAM CONFIGURATION
678 13:58:37.303371 ===================================
679 13:58:37.305407 EX_ROW_EN[0] = 0x0
680 13:58:37.309340 EX_ROW_EN[1] = 0x0
681 13:58:37.309824 LP4Y_EN = 0x0
682 13:58:37.312532 WORK_FSP = 0x0
683 13:58:37.313016 WL = 0x2
684 13:58:37.316489 RL = 0x2
685 13:58:37.317067 BL = 0x2
686 13:58:37.320087 RPST = 0x0
687 13:58:37.320559 RD_PRE = 0x0
688 13:58:37.320932 WR_PRE = 0x1
689 13:58:37.323407 WR_PST = 0x0
690 13:58:37.323933 DBI_WR = 0x0
691 13:58:37.327767 DBI_RD = 0x0
692 13:58:37.328208 OTF = 0x1
693 13:58:37.331092 ===================================
694 13:58:37.334574 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 13:58:37.338277 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 13:58:37.345385 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 13:58:37.349108 ===================================
698 13:58:37.349540 LPDDR4 DRAM CONFIGURATION
699 13:58:37.352299 ===================================
700 13:58:37.356421 EX_ROW_EN[0] = 0x10
701 13:58:37.357013 EX_ROW_EN[1] = 0x0
702 13:58:37.359776 LP4Y_EN = 0x0
703 13:58:37.360221 WORK_FSP = 0x0
704 13:58:37.364042 WL = 0x2
705 13:58:37.364592 RL = 0x2
706 13:58:37.367179 BL = 0x2
707 13:58:37.367603 RPST = 0x0
708 13:58:37.371051 RD_PRE = 0x0
709 13:58:37.371585 WR_PRE = 0x1
710 13:58:37.372087 WR_PST = 0x0
711 13:58:37.374731 DBI_WR = 0x0
712 13:58:37.375157 DBI_RD = 0x0
713 13:58:37.378893 OTF = 0x1
714 13:58:37.382038 ===================================
715 13:58:37.386650 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 13:58:37.391678 nWR fixed to 40
717 13:58:37.392244 [ModeRegInit_LP4] CH0 RK0
718 13:58:37.395441 [ModeRegInit_LP4] CH0 RK1
719 13:58:37.399557 [ModeRegInit_LP4] CH1 RK0
720 13:58:37.400136 [ModeRegInit_LP4] CH1 RK1
721 13:58:37.402601 match AC timing 13
722 13:58:37.406183 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 13:58:37.410103 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 13:58:37.416221 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 13:58:37.419611 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 13:58:37.426039 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 13:58:37.426581 [EMI DOE] emi_dcm 0
728 13:58:37.428920 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 13:58:37.429356 ==
730 13:58:37.432609 Dram Type= 6, Freq= 0, CH_0, rank 0
731 13:58:37.439962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 13:58:37.440576 ==
733 13:58:37.444456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 13:58:37.451003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 13:58:37.458616 [CA 0] Center 37 (7~68) winsize 62
736 13:58:37.462008 [CA 1] Center 37 (6~68) winsize 63
737 13:58:37.465195 [CA 2] Center 34 (4~65) winsize 62
738 13:58:37.468711 [CA 3] Center 34 (4~65) winsize 62
739 13:58:37.472469 [CA 4] Center 33 (3~64) winsize 62
740 13:58:37.475344 [CA 5] Center 33 (3~64) winsize 62
741 13:58:37.475855
742 13:58:37.479016 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 13:58:37.479513
744 13:58:37.482337 [CATrainingPosCal] consider 1 rank data
745 13:58:37.486189 u2DelayCellTimex100 = 270/100 ps
746 13:58:37.489231 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
747 13:58:37.492436 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
748 13:58:37.495465 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
749 13:58:37.502156 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
750 13:58:37.505891 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
751 13:58:37.509196 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 13:58:37.509624
753 13:58:37.511961 CA PerBit enable=1, Macro0, CA PI delay=33
754 13:58:37.512387
755 13:58:37.515866 [CBTSetCACLKResult] CA Dly = 33
756 13:58:37.516296 CS Dly: 7 (0~38)
757 13:58:37.516636 ==
758 13:58:37.518894 Dram Type= 6, Freq= 0, CH_0, rank 1
759 13:58:37.525820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 13:58:37.526335 ==
761 13:58:37.528610 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 13:58:37.535495 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 13:58:37.544549 [CA 0] Center 37 (6~68) winsize 63
764 13:58:37.547921 [CA 1] Center 37 (7~68) winsize 62
765 13:58:37.551344 [CA 2] Center 34 (4~65) winsize 62
766 13:58:37.554445 [CA 3] Center 34 (4~65) winsize 62
767 13:58:37.557752 [CA 4] Center 33 (3~64) winsize 62
768 13:58:37.561105 [CA 5] Center 33 (3~64) winsize 62
769 13:58:37.561534
770 13:58:37.564362 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 13:58:37.564789
772 13:58:37.568114 [CATrainingPosCal] consider 2 rank data
773 13:58:37.571505 u2DelayCellTimex100 = 270/100 ps
774 13:58:37.574784 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
775 13:58:37.581750 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 13:58:37.584761 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
777 13:58:37.588886 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
778 13:58:37.591961 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
779 13:58:37.595783 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 13:58:37.596271
781 13:58:37.599285 CA PerBit enable=1, Macro0, CA PI delay=33
782 13:58:37.599854
783 13:58:37.603056 [CBTSetCACLKResult] CA Dly = 33
784 13:58:37.603521 CS Dly: 7 (0~38)
785 13:58:37.604109
786 13:58:37.606733 ----->DramcWriteLeveling(PI) begin...
787 13:58:37.607306 ==
788 13:58:37.610310 Dram Type= 6, Freq= 0, CH_0, rank 0
789 13:58:37.614243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 13:58:37.614673 ==
791 13:58:37.617381 Write leveling (Byte 0): 32 => 32
792 13:58:37.620730 Write leveling (Byte 1): 28 => 28
793 13:58:37.623945 DramcWriteLeveling(PI) end<-----
794 13:58:37.624386
795 13:58:37.624723 ==
796 13:58:37.627647 Dram Type= 6, Freq= 0, CH_0, rank 0
797 13:58:37.630633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 13:58:37.631062 ==
799 13:58:37.634737 [Gating] SW mode calibration
800 13:58:37.641118 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 13:58:37.648461 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 13:58:37.650637 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 13:58:37.654067 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
804 13:58:37.661163 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 13:58:37.664201 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:58:37.667672 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:58:37.673755 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:58:37.677444 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:58:37.680412 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:58:37.687660 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:58:37.690481 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:58:37.694444 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 13:58:37.697203 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 13:58:37.703779 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 13:58:37.706952 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 13:58:37.710624 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 13:58:37.717031 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 13:58:37.721141 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 13:58:37.723777 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 13:58:37.730847 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
821 13:58:37.734144 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:58:37.737044 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:58:37.743669 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:58:37.747156 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:58:37.750801 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:58:37.757086 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:58:37.760215 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:58:37.763880 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
829 13:58:37.770304 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
830 13:58:37.773730 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 13:58:37.776893 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 13:58:37.783588 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 13:58:37.786742 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 13:58:37.790483 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 13:58:37.797089 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
836 13:58:37.800061 0 10 8 | B1->B0 | 3333 2626 | 0 0 | (0 1) (0 0)
837 13:58:37.803343 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
838 13:58:37.810832 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 13:58:37.813384 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 13:58:37.817391 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 13:58:37.820532 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 13:58:37.827844 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 13:58:37.831203 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
844 13:58:37.835061 0 11 8 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
845 13:58:37.839010 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
846 13:58:37.842598 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 13:58:37.849316 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 13:58:37.853543 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 13:58:37.856810 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 13:58:37.860838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 13:58:37.868094 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 13:58:37.871095 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
853 13:58:37.875225 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
854 13:58:37.878829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 13:58:37.884949 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 13:58:37.888472 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 13:58:37.891281 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 13:58:37.898350 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 13:58:37.901925 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 13:58:37.904700 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 13:58:37.912092 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 13:58:37.915326 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 13:58:37.918507 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 13:58:37.924792 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 13:58:37.928297 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 13:58:37.932243 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 13:58:37.936307 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 13:58:37.940014 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
869 13:58:37.943983 Total UI for P1: 0, mck2ui 16
870 13:58:37.947658 best dqsien dly found for B0: ( 0, 14, 6)
871 13:58:37.951338 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 13:58:37.954253 Total UI for P1: 0, mck2ui 16
873 13:58:37.958073 best dqsien dly found for B1: ( 0, 14, 8)
874 13:58:37.961225 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
875 13:58:37.964984 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
876 13:58:37.965506
877 13:58:37.968118 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
878 13:58:37.971058 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 13:58:37.974572 [Gating] SW calibration Done
880 13:58:37.975099 ==
881 13:58:37.978047 Dram Type= 6, Freq= 0, CH_0, rank 0
882 13:58:37.981971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 13:58:37.984699 ==
884 13:58:37.985131 RX Vref Scan: 0
885 13:58:37.985475
886 13:58:37.988296 RX Vref 0 -> 0, step: 1
887 13:58:37.988726
888 13:58:37.991707 RX Delay -130 -> 252, step: 16
889 13:58:37.995341 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
890 13:58:37.998271 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
891 13:58:38.001653 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
892 13:58:38.004972 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
893 13:58:38.008216 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
894 13:58:38.015409 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
895 13:58:38.018216 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
896 13:58:38.021850 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
897 13:58:38.024693 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
898 13:58:38.028677 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
899 13:58:38.035262 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
900 13:58:38.038751 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
901 13:58:38.041873 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
902 13:58:38.045002 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
903 13:58:38.051849 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
904 13:58:38.054765 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
905 13:58:38.055241 ==
906 13:58:38.058615 Dram Type= 6, Freq= 0, CH_0, rank 0
907 13:58:38.062111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 13:58:38.062685 ==
909 13:58:38.063063 DQS Delay:
910 13:58:38.065122 DQS0 = 0, DQS1 = 0
911 13:58:38.065595 DQM Delay:
912 13:58:38.069167 DQM0 = 85, DQM1 = 69
913 13:58:38.069739 DQ Delay:
914 13:58:38.071413 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
915 13:58:38.075260 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
916 13:58:38.078314 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
917 13:58:38.081947 DQ12 =69, DQ13 =77, DQ14 =77, DQ15 =77
918 13:58:38.082509
919 13:58:38.082885
920 13:58:38.083232 ==
921 13:58:38.085016 Dram Type= 6, Freq= 0, CH_0, rank 0
922 13:58:38.088690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 13:58:38.091426 ==
924 13:58:38.092031
925 13:58:38.092413
926 13:58:38.092763 TX Vref Scan disable
927 13:58:38.094712 == TX Byte 0 ==
928 13:58:38.098150 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
929 13:58:38.101572 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
930 13:58:38.104974 == TX Byte 1 ==
931 13:58:38.108608 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
932 13:58:38.111195 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
933 13:58:38.115146 ==
934 13:58:38.115767 Dram Type= 6, Freq= 0, CH_0, rank 0
935 13:58:38.121994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 13:58:38.122587 ==
937 13:58:38.134217 TX Vref=22, minBit 5, minWin=27, winSum=442
938 13:58:38.137136 TX Vref=24, minBit 5, minWin=27, winSum=442
939 13:58:38.140518 TX Vref=26, minBit 8, minWin=27, winSum=446
940 13:58:38.144267 TX Vref=28, minBit 14, minWin=27, winSum=448
941 13:58:38.147221 TX Vref=30, minBit 8, minWin=27, winSum=445
942 13:58:38.153972 TX Vref=32, minBit 9, minWin=26, winSum=441
943 13:58:38.157312 [TxChooseVref] Worse bit 14, Min win 27, Win sum 448, Final Vref 28
944 13:58:38.157859
945 13:58:38.161011 Final TX Range 1 Vref 28
946 13:58:38.161591
947 13:58:38.161970 ==
948 13:58:38.163910 Dram Type= 6, Freq= 0, CH_0, rank 0
949 13:58:38.167353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 13:58:38.167974 ==
951 13:58:38.170519
952 13:58:38.170987
953 13:58:38.171362 TX Vref Scan disable
954 13:58:38.174261 == TX Byte 0 ==
955 13:58:38.177851 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
956 13:58:38.184402 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
957 13:58:38.184979 == TX Byte 1 ==
958 13:58:38.187360 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
959 13:58:38.194274 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
960 13:58:38.194856
961 13:58:38.195234 [DATLAT]
962 13:58:38.195582 Freq=800, CH0 RK0
963 13:58:38.195991
964 13:58:38.196973 DATLAT Default: 0xa
965 13:58:38.197445 0, 0xFFFF, sum = 0
966 13:58:38.200481 1, 0xFFFF, sum = 0
967 13:58:38.200958 2, 0xFFFF, sum = 0
968 13:58:38.204071 3, 0xFFFF, sum = 0
969 13:58:38.207298 4, 0xFFFF, sum = 0
970 13:58:38.207921 5, 0xFFFF, sum = 0
971 13:58:38.210899 6, 0xFFFF, sum = 0
972 13:58:38.211477 7, 0xFFFF, sum = 0
973 13:58:38.213895 8, 0xFFFF, sum = 0
974 13:58:38.214479 9, 0x0, sum = 1
975 13:58:38.216800 10, 0x0, sum = 2
976 13:58:38.217280 11, 0x0, sum = 3
977 13:58:38.217663 12, 0x0, sum = 4
978 13:58:38.220593 best_step = 10
979 13:58:38.221065
980 13:58:38.221466 ==
981 13:58:38.223697 Dram Type= 6, Freq= 0, CH_0, rank 0
982 13:58:38.227343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 13:58:38.227981 ==
984 13:58:38.230923 RX Vref Scan: 1
985 13:58:38.231507
986 13:58:38.233744 Set Vref Range= 32 -> 127
987 13:58:38.234321
988 13:58:38.234703 RX Vref 32 -> 127, step: 1
989 13:58:38.235055
990 13:58:38.237072 RX Delay -111 -> 252, step: 8
991 13:58:38.237639
992 13:58:38.240604 Set Vref, RX VrefLevel [Byte0]: 32
993 13:58:38.243774 [Byte1]: 32
994 13:58:38.247571
995 13:58:38.248194 Set Vref, RX VrefLevel [Byte0]: 33
996 13:58:38.250164 [Byte1]: 33
997 13:58:38.255023
998 13:58:38.255585 Set Vref, RX VrefLevel [Byte0]: 34
999 13:58:38.258008 [Byte1]: 34
1000 13:58:38.262270
1001 13:58:38.262833 Set Vref, RX VrefLevel [Byte0]: 35
1002 13:58:38.265266 [Byte1]: 35
1003 13:58:38.269989
1004 13:58:38.270581 Set Vref, RX VrefLevel [Byte0]: 36
1005 13:58:38.273690 [Byte1]: 36
1006 13:58:38.278068
1007 13:58:38.278632 Set Vref, RX VrefLevel [Byte0]: 37
1008 13:58:38.280922 [Byte1]: 37
1009 13:58:38.285336
1010 13:58:38.285903 Set Vref, RX VrefLevel [Byte0]: 38
1011 13:58:38.288276 [Byte1]: 38
1012 13:58:38.292987
1013 13:58:38.293550 Set Vref, RX VrefLevel [Byte0]: 39
1014 13:58:38.296081 [Byte1]: 39
1015 13:58:38.300286
1016 13:58:38.300757 Set Vref, RX VrefLevel [Byte0]: 40
1017 13:58:38.303699 [Byte1]: 40
1018 13:58:38.308170
1019 13:58:38.308645 Set Vref, RX VrefLevel [Byte0]: 41
1020 13:58:38.311223 [Byte1]: 41
1021 13:58:38.316314
1022 13:58:38.316830 Set Vref, RX VrefLevel [Byte0]: 42
1023 13:58:38.319047 [Byte1]: 42
1024 13:58:38.323289
1025 13:58:38.323880 Set Vref, RX VrefLevel [Byte0]: 43
1026 13:58:38.326237 [Byte1]: 43
1027 13:58:38.331241
1028 13:58:38.331830 Set Vref, RX VrefLevel [Byte0]: 44
1029 13:58:38.334558 [Byte1]: 44
1030 13:58:38.338978
1031 13:58:38.339497 Set Vref, RX VrefLevel [Byte0]: 45
1032 13:58:38.342014 [Byte1]: 45
1033 13:58:38.346461
1034 13:58:38.347061 Set Vref, RX VrefLevel [Byte0]: 46
1035 13:58:38.349415 [Byte1]: 46
1036 13:58:38.354075
1037 13:58:38.354639 Set Vref, RX VrefLevel [Byte0]: 47
1038 13:58:38.357263 [Byte1]: 47
1039 13:58:38.361859
1040 13:58:38.362424 Set Vref, RX VrefLevel [Byte0]: 48
1041 13:58:38.364686 [Byte1]: 48
1042 13:58:38.369616
1043 13:58:38.370184 Set Vref, RX VrefLevel [Byte0]: 49
1044 13:58:38.372477 [Byte1]: 49
1045 13:58:38.376697
1046 13:58:38.377265 Set Vref, RX VrefLevel [Byte0]: 50
1047 13:58:38.380133 [Byte1]: 50
1048 13:58:38.384349
1049 13:58:38.384816 Set Vref, RX VrefLevel [Byte0]: 51
1050 13:58:38.387837 [Byte1]: 51
1051 13:58:38.392153
1052 13:58:38.392618 Set Vref, RX VrefLevel [Byte0]: 52
1053 13:58:38.395465 [Byte1]: 52
1054 13:58:38.400194
1055 13:58:38.400759 Set Vref, RX VrefLevel [Byte0]: 53
1056 13:58:38.403029 [Byte1]: 53
1057 13:58:38.407956
1058 13:58:38.408517 Set Vref, RX VrefLevel [Byte0]: 54
1059 13:58:38.411821 [Byte1]: 54
1060 13:58:38.415144
1061 13:58:38.415707 Set Vref, RX VrefLevel [Byte0]: 55
1062 13:58:38.418358 [Byte1]: 55
1063 13:58:38.422948
1064 13:58:38.423510 Set Vref, RX VrefLevel [Byte0]: 56
1065 13:58:38.425985 [Byte1]: 56
1066 13:58:38.430297
1067 13:58:38.430857 Set Vref, RX VrefLevel [Byte0]: 57
1068 13:58:38.433659 [Byte1]: 57
1069 13:58:38.437954
1070 13:58:38.438420 Set Vref, RX VrefLevel [Byte0]: 58
1071 13:58:38.441178 [Byte1]: 58
1072 13:58:38.445854
1073 13:58:38.446408 Set Vref, RX VrefLevel [Byte0]: 59
1074 13:58:38.449147 [Byte1]: 59
1075 13:58:38.453608
1076 13:58:38.454075 Set Vref, RX VrefLevel [Byte0]: 60
1077 13:58:38.456864 [Byte1]: 60
1078 13:58:38.461487
1079 13:58:38.462052 Set Vref, RX VrefLevel [Byte0]: 61
1080 13:58:38.464926 [Byte1]: 61
1081 13:58:38.468637
1082 13:58:38.469067 Set Vref, RX VrefLevel [Byte0]: 62
1083 13:58:38.472366 [Byte1]: 62
1084 13:58:38.476462
1085 13:58:38.476885 Set Vref, RX VrefLevel [Byte0]: 63
1086 13:58:38.480254 [Byte1]: 63
1087 13:58:38.484234
1088 13:58:38.484754 Set Vref, RX VrefLevel [Byte0]: 64
1089 13:58:38.487121 [Byte1]: 64
1090 13:58:38.491370
1091 13:58:38.494854 Set Vref, RX VrefLevel [Byte0]: 65
1092 13:58:38.495588 [Byte1]: 65
1093 13:58:38.499879
1094 13:58:38.500383 Set Vref, RX VrefLevel [Byte0]: 66
1095 13:58:38.502218 [Byte1]: 66
1096 13:58:38.507672
1097 13:58:38.508248 Set Vref, RX VrefLevel [Byte0]: 67
1098 13:58:38.511091 [Byte1]: 67
1099 13:58:38.514653
1100 13:58:38.515177 Set Vref, RX VrefLevel [Byte0]: 68
1101 13:58:38.518673 [Byte1]: 68
1102 13:58:38.522371
1103 13:58:38.522788 Set Vref, RX VrefLevel [Byte0]: 69
1104 13:58:38.526133 [Byte1]: 69
1105 13:58:38.530155
1106 13:58:38.531002 Set Vref, RX VrefLevel [Byte0]: 70
1107 13:58:38.533625 [Byte1]: 70
1108 13:58:38.537446
1109 13:58:38.537867 Set Vref, RX VrefLevel [Byte0]: 71
1110 13:58:38.541104 [Byte1]: 71
1111 13:58:38.544782
1112 13:58:38.548594 Set Vref, RX VrefLevel [Byte0]: 72
1113 13:58:38.549422 [Byte1]: 72
1114 13:58:38.552480
1115 13:58:38.552902 Set Vref, RX VrefLevel [Byte0]: 73
1116 13:58:38.555998 [Byte1]: 73
1117 13:58:38.560287
1118 13:58:38.560865 Set Vref, RX VrefLevel [Byte0]: 74
1119 13:58:38.563695 [Byte1]: 74
1120 13:58:38.568246
1121 13:58:38.568885 Set Vref, RX VrefLevel [Byte0]: 75
1122 13:58:38.571473 [Byte1]: 75
1123 13:58:38.575538
1124 13:58:38.576021 Set Vref, RX VrefLevel [Byte0]: 76
1125 13:58:38.579344 [Byte1]: 76
1126 13:58:38.583322
1127 13:58:38.583884 Set Vref, RX VrefLevel [Byte0]: 77
1128 13:58:38.586792 [Byte1]: 77
1129 13:58:38.591110
1130 13:58:38.591529 Set Vref, RX VrefLevel [Byte0]: 78
1131 13:58:38.594102 [Byte1]: 78
1132 13:58:38.599041
1133 13:58:38.599456 Set Vref, RX VrefLevel [Byte0]: 79
1134 13:58:38.602483 [Byte1]: 79
1135 13:58:38.607054
1136 13:58:38.607681 Set Vref, RX VrefLevel [Byte0]: 80
1137 13:58:38.609742 [Byte1]: 80
1138 13:58:38.614560
1139 13:58:38.615279 Set Vref, RX VrefLevel [Byte0]: 81
1140 13:58:38.617499 [Byte1]: 81
1141 13:58:38.622113
1142 13:58:38.622718 Final RX Vref Byte 0 = 61 to rank0
1143 13:58:38.625552 Final RX Vref Byte 1 = 61 to rank0
1144 13:58:38.628913 Final RX Vref Byte 0 = 61 to rank1
1145 13:58:38.632505 Final RX Vref Byte 1 = 61 to rank1==
1146 13:58:38.636371 Dram Type= 6, Freq= 0, CH_0, rank 0
1147 13:58:38.639903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 13:58:38.640554 ==
1149 13:58:38.643632 DQS Delay:
1150 13:58:38.644264 DQS0 = 0, DQS1 = 0
1151 13:58:38.644671 DQM Delay:
1152 13:58:38.647227 DQM0 = 87, DQM1 = 75
1153 13:58:38.647927 DQ Delay:
1154 13:58:38.650610 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1155 13:58:38.654620 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1156 13:58:38.657987 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =68
1157 13:58:38.661637 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =80
1158 13:58:38.662239
1159 13:58:38.662786
1160 13:58:38.668480 [DQSOSCAuto] RK0, (LSB)MR18= 0x4729, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1161 13:58:38.672448 CH0 RK0: MR19=606, MR18=4729
1162 13:58:38.675570 CH0_RK0: MR19=0x606, MR18=0x4729, DQSOSC=392, MR23=63, INC=96, DEC=64
1163 13:58:38.676052
1164 13:58:38.679780 ----->DramcWriteLeveling(PI) begin...
1165 13:58:38.680323 ==
1166 13:58:38.683501 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 13:58:38.687112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1168 13:58:38.687634 ==
1169 13:58:38.690925 Write leveling (Byte 0): 32 => 32
1170 13:58:38.695123 Write leveling (Byte 1): 31 => 31
1171 13:58:38.698452 DramcWriteLeveling(PI) end<-----
1172 13:58:38.698966
1173 13:58:38.699301 ==
1174 13:58:38.701940 Dram Type= 6, Freq= 0, CH_0, rank 1
1175 13:58:38.705388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 13:58:38.705818 ==
1177 13:58:38.749706 [Gating] SW mode calibration
1178 13:58:38.750295 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1179 13:58:38.750673 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1180 13:58:38.751022 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1181 13:58:38.751355 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1182 13:58:38.752009 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1183 13:58:38.752365 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:58:38.752689 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:58:38.753006 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:58:38.753320 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:58:38.793449 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:58:38.794332 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:58:38.794783 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:58:38.795146 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:58:38.795484 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:58:38.795938 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:58:38.796377 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 13:58:38.797702 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 13:58:38.798484 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 13:58:38.798874 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 13:58:38.838141 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 13:58:38.838720 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1199 13:58:38.839434 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1200 13:58:38.839851 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 13:58:38.840194 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 13:58:38.840521 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 13:58:38.840842 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 13:58:38.841217 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 13:58:38.841547 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 13:58:38.841855 0 9 8 | B1->B0 | 2525 3434 | 1 0 | (1 1) (0 0)
1207 13:58:38.882738 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1208 13:58:38.883621 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1209 13:58:38.884104 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1210 13:58:38.884467 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1211 13:58:38.884805 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1212 13:58:38.885132 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1213 13:58:38.885520 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 1)
1214 13:58:38.885848 0 10 8 | B1->B0 | 3030 2a2a | 1 1 | (1 0) (0 0)
1215 13:58:38.886165 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1216 13:58:38.886473 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 13:58:38.895704 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 13:58:38.896633 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 13:58:38.898575 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 13:58:38.902465 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 13:58:38.905694 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1222 13:58:38.909165 0 11 8 | B1->B0 | 2f2f 4141 | 0 0 | (0 0) (0 0)
1223 13:58:38.912672 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 13:58:38.919137 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 13:58:38.922452 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 13:58:38.925618 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 13:58:38.932489 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 13:58:38.935914 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 13:58:38.938666 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1230 13:58:38.945744 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1231 13:58:38.949164 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1232 13:58:38.952723 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 13:58:38.958667 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 13:58:38.961836 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 13:58:38.965336 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 13:58:38.972197 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 13:58:38.975970 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 13:58:38.978636 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 13:58:38.985193 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 13:58:38.988643 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 13:58:38.991845 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 13:58:38.998490 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 13:58:39.002138 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 13:58:39.005156 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 13:58:39.011830 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 13:58:39.015462 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1247 13:58:39.018000 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1248 13:58:39.021666 Total UI for P1: 0, mck2ui 16
1249 13:58:39.024456 best dqsien dly found for B0: ( 0, 14, 8)
1250 13:58:39.031500 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 13:58:39.032115 Total UI for P1: 0, mck2ui 16
1252 13:58:39.038232 best dqsien dly found for B1: ( 0, 14, 12)
1253 13:58:39.041356 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1254 13:58:39.044695 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1255 13:58:39.045329
1256 13:58:39.048837 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1257 13:58:39.051543 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1258 13:58:39.054650 [Gating] SW calibration Done
1259 13:58:39.055207 ==
1260 13:58:39.058359 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 13:58:39.061410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 13:58:39.061879 ==
1263 13:58:39.064243 RX Vref Scan: 0
1264 13:58:39.064705
1265 13:58:39.065078 RX Vref 0 -> 0, step: 1
1266 13:58:39.065423
1267 13:58:39.067956 RX Delay -130 -> 252, step: 16
1268 13:58:39.070891 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1269 13:58:39.078018 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1270 13:58:39.081115 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1271 13:58:39.084160 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1272 13:58:39.087581 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1273 13:58:39.091454 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1274 13:58:39.097744 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1275 13:58:39.100959 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1276 13:58:39.104205 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1277 13:58:39.108130 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1278 13:58:39.111534 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1279 13:58:39.117523 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1280 13:58:39.120821 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1281 13:58:39.123933 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1282 13:58:39.127302 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1283 13:58:39.133988 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1284 13:58:39.134533 ==
1285 13:58:39.138166 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 13:58:39.140514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 13:58:39.140984 ==
1288 13:58:39.141358 DQS Delay:
1289 13:58:39.143903 DQS0 = 0, DQS1 = 0
1290 13:58:39.144370 DQM Delay:
1291 13:58:39.147967 DQM0 = 86, DQM1 = 78
1292 13:58:39.148514 DQ Delay:
1293 13:58:39.151138 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1294 13:58:39.153845 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1295 13:58:39.157720 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =77
1296 13:58:39.160730 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1297 13:58:39.161200
1298 13:58:39.161571
1299 13:58:39.161919 ==
1300 13:58:39.163795 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 13:58:39.167078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 13:58:39.167586 ==
1303 13:58:39.167994
1304 13:58:39.170496
1305 13:58:39.170917 TX Vref Scan disable
1306 13:58:39.173681 == TX Byte 0 ==
1307 13:58:39.176737 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1308 13:58:39.179930 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1309 13:58:39.184154 == TX Byte 1 ==
1310 13:58:39.186558 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1311 13:58:39.189779 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1312 13:58:39.193015 ==
1313 13:58:39.193435 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 13:58:39.199516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 13:58:39.199990 ==
1316 13:58:39.212145 TX Vref=22, minBit 0, minWin=27, winSum=442
1317 13:58:39.215386 TX Vref=24, minBit 1, minWin=27, winSum=442
1318 13:58:39.218568 TX Vref=26, minBit 9, minWin=27, winSum=447
1319 13:58:39.222190 TX Vref=28, minBit 9, minWin=27, winSum=450
1320 13:58:39.225255 TX Vref=30, minBit 9, minWin=27, winSum=448
1321 13:58:39.231558 TX Vref=32, minBit 9, minWin=27, winSum=448
1322 13:58:39.234770 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 28
1323 13:58:39.235191
1324 13:58:39.238456 Final TX Range 1 Vref 28
1325 13:58:39.238880
1326 13:58:39.239214 ==
1327 13:58:39.241927 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 13:58:39.245804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 13:58:39.248158 ==
1330 13:58:39.248577
1331 13:58:39.248908
1332 13:58:39.249216 TX Vref Scan disable
1333 13:58:39.252406 == TX Byte 0 ==
1334 13:58:39.255025 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1335 13:58:39.261801 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1336 13:58:39.262220 == TX Byte 1 ==
1337 13:58:39.265170 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1338 13:58:39.273169 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1339 13:58:39.273680
1340 13:58:39.274012 [DATLAT]
1341 13:58:39.274321 Freq=800, CH0 RK1
1342 13:58:39.274620
1343 13:58:39.275346 DATLAT Default: 0xa
1344 13:58:39.275672 0, 0xFFFF, sum = 0
1345 13:58:39.278712 1, 0xFFFF, sum = 0
1346 13:58:39.279139 2, 0xFFFF, sum = 0
1347 13:58:39.281821 3, 0xFFFF, sum = 0
1348 13:58:39.285268 4, 0xFFFF, sum = 0
1349 13:58:39.285789 5, 0xFFFF, sum = 0
1350 13:58:39.288696 6, 0xFFFF, sum = 0
1351 13:58:39.289218 7, 0xFFFF, sum = 0
1352 13:58:39.291959 8, 0xFFFF, sum = 0
1353 13:58:39.292599 9, 0x0, sum = 1
1354 13:58:39.295670 10, 0x0, sum = 2
1355 13:58:39.296436 11, 0x0, sum = 3
1356 13:58:39.296797 12, 0x0, sum = 4
1357 13:58:39.298560 best_step = 10
1358 13:58:39.299069
1359 13:58:39.299407 ==
1360 13:58:39.301859 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 13:58:39.304802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 13:58:39.305319 ==
1363 13:58:39.308189 RX Vref Scan: 0
1364 13:58:39.308698
1365 13:58:39.309035 RX Vref 0 -> 0, step: 1
1366 13:58:39.311477
1367 13:58:39.311940 RX Delay -111 -> 252, step: 8
1368 13:58:39.318745 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1369 13:58:39.322614 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1370 13:58:39.325566 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1371 13:58:39.328591 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1372 13:58:39.332454 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1373 13:58:39.338640 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1374 13:58:39.342292 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1375 13:58:39.345744 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1376 13:58:39.349071 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1377 13:58:39.352421 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1378 13:58:39.358983 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1379 13:58:39.361640 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1380 13:58:39.365402 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1381 13:58:39.368656 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1382 13:58:39.375381 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1383 13:58:39.378273 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1384 13:58:39.378692 ==
1385 13:58:39.382160 Dram Type= 6, Freq= 0, CH_0, rank 1
1386 13:58:39.385133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1387 13:58:39.385645 ==
1388 13:58:39.385982 DQS Delay:
1389 13:58:39.388894 DQS0 = 0, DQS1 = 0
1390 13:58:39.389403 DQM Delay:
1391 13:58:39.392180 DQM0 = 85, DQM1 = 77
1392 13:58:39.392693 DQ Delay:
1393 13:58:39.395262 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1394 13:58:39.398277 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1395 13:58:39.401754 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1396 13:58:39.404988 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1397 13:58:39.405497
1398 13:58:39.405833
1399 13:58:39.415382 [DQSOSCAuto] RK1, (LSB)MR18= 0x4207, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1400 13:58:39.415946 CH0 RK1: MR19=606, MR18=4207
1401 13:58:39.421709 CH0_RK1: MR19=0x606, MR18=0x4207, DQSOSC=393, MR23=63, INC=95, DEC=63
1402 13:58:39.425411 [RxdqsGatingPostProcess] freq 800
1403 13:58:39.431782 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1404 13:58:39.435633 Pre-setting of DQS Precalculation
1405 13:58:39.438521 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1406 13:58:39.439078 ==
1407 13:58:39.441883 Dram Type= 6, Freq= 0, CH_1, rank 0
1408 13:58:39.444929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 13:58:39.448145 ==
1410 13:58:39.452249 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 13:58:39.457982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 13:58:39.467237 [CA 0] Center 36 (6~67) winsize 62
1413 13:58:39.470450 [CA 1] Center 36 (6~67) winsize 62
1414 13:58:39.473808 [CA 2] Center 34 (4~65) winsize 62
1415 13:58:39.477009 [CA 3] Center 34 (3~65) winsize 63
1416 13:58:39.480334 [CA 4] Center 34 (4~65) winsize 62
1417 13:58:39.484431 [CA 5] Center 34 (3~65) winsize 63
1418 13:58:39.484989
1419 13:58:39.486847 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1420 13:58:39.487310
1421 13:58:39.490468 [CATrainingPosCal] consider 1 rank data
1422 13:58:39.493489 u2DelayCellTimex100 = 270/100 ps
1423 13:58:39.496858 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 13:58:39.503474 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 13:58:39.507058 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 13:58:39.510191 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1427 13:58:39.513628 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 13:58:39.516451 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1429 13:58:39.516921
1430 13:58:39.520000 CA PerBit enable=1, Macro0, CA PI delay=34
1431 13:58:39.520468
1432 13:58:39.523639 [CBTSetCACLKResult] CA Dly = 34
1433 13:58:39.524242 CS Dly: 5 (0~36)
1434 13:58:39.527152 ==
1435 13:58:39.530718 Dram Type= 6, Freq= 0, CH_1, rank 1
1436 13:58:39.533135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 13:58:39.533605 ==
1438 13:58:39.537161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1439 13:58:39.543523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1440 13:58:39.553350 [CA 0] Center 36 (6~67) winsize 62
1441 13:58:39.556462 [CA 1] Center 36 (6~67) winsize 62
1442 13:58:39.559818 [CA 2] Center 34 (4~65) winsize 62
1443 13:58:39.562853 [CA 3] Center 34 (3~65) winsize 63
1444 13:58:39.566531 [CA 4] Center 34 (4~65) winsize 62
1445 13:58:39.569654 [CA 5] Center 34 (3~65) winsize 63
1446 13:58:39.570088
1447 13:58:39.572771 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1448 13:58:39.573192
1449 13:58:39.576610 [CATrainingPosCal] consider 2 rank data
1450 13:58:39.579396 u2DelayCellTimex100 = 270/100 ps
1451 13:58:39.582971 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 13:58:39.589662 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1453 13:58:39.592929 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 13:58:39.596228 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1455 13:58:39.599542 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 13:58:39.602895 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1457 13:58:39.603405
1458 13:58:39.606033 CA PerBit enable=1, Macro0, CA PI delay=34
1459 13:58:39.606544
1460 13:58:39.609779 [CBTSetCACLKResult] CA Dly = 34
1461 13:58:39.612659 CS Dly: 6 (0~38)
1462 13:58:39.613082
1463 13:58:39.616205 ----->DramcWriteLeveling(PI) begin...
1464 13:58:39.616632 ==
1465 13:58:39.619668 Dram Type= 6, Freq= 0, CH_1, rank 0
1466 13:58:39.623219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1467 13:58:39.623782 ==
1468 13:58:39.626234 Write leveling (Byte 0): 25 => 25
1469 13:58:39.629001 Write leveling (Byte 1): 30 => 30
1470 13:58:39.632639 DramcWriteLeveling(PI) end<-----
1471 13:58:39.633161
1472 13:58:39.633498 ==
1473 13:58:39.636546 Dram Type= 6, Freq= 0, CH_1, rank 0
1474 13:58:39.639454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 13:58:39.639906 ==
1476 13:58:39.643059 [Gating] SW mode calibration
1477 13:58:39.649033 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1478 13:58:39.656367 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1479 13:58:39.659055 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1480 13:58:39.661964 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1481 13:58:39.669156 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:58:39.672114 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 13:58:39.675649 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:58:39.681992 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:58:39.685312 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:58:39.688632 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:58:39.695641 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:58:39.699269 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:58:39.701812 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:58:39.708886 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:58:39.712287 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:58:39.715256 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 13:58:39.722195 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 13:58:39.725391 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 13:58:39.728885 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1496 13:58:39.735435 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1497 13:58:39.738876 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 13:58:39.742023 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 13:58:39.748569 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 13:58:39.751627 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 13:58:39.755634 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 13:58:39.761543 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 13:58:39.765046 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 13:58:39.768474 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 13:58:39.774797 0 9 8 | B1->B0 | 2e2d 2f2f | 1 0 | (1 1) (0 0)
1506 13:58:39.778162 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 13:58:39.781543 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1508 13:58:39.787952 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1509 13:58:39.791460 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1510 13:58:39.794657 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 13:58:39.798280 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1512 13:58:39.805023 0 10 4 | B1->B0 | 3232 3434 | 1 0 | (1 0) (0 1)
1513 13:58:39.807880 0 10 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
1514 13:58:39.811265 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 13:58:39.818407 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 13:58:39.821451 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 13:58:39.824269 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 13:58:39.833235 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 13:58:39.834931 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 13:58:39.837943 0 11 4 | B1->B0 | 2424 2827 | 0 1 | (0 0) (0 0)
1521 13:58:39.844671 0 11 8 | B1->B0 | 3737 3f3f | 0 0 | (1 1) (0 0)
1522 13:58:39.848435 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 13:58:39.851074 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 13:58:39.857815 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 13:58:39.860907 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 13:58:39.864328 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 13:58:39.871108 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 13:58:39.875136 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1529 13:58:39.878065 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1530 13:58:39.884555 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 13:58:39.887431 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 13:58:39.891177 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 13:58:39.897214 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 13:58:39.900924 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 13:58:39.904074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 13:58:39.911061 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 13:58:39.914372 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 13:58:39.918146 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 13:58:39.923917 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 13:58:39.927828 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 13:58:39.931049 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 13:58:39.937719 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 13:58:39.940506 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 13:58:39.943810 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1545 13:58:39.950836 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1546 13:58:39.951392 Total UI for P1: 0, mck2ui 16
1547 13:58:39.957609 best dqsien dly found for B0: ( 0, 14, 4)
1548 13:58:39.960531 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 13:58:39.964083 Total UI for P1: 0, mck2ui 16
1550 13:58:39.967576 best dqsien dly found for B1: ( 0, 14, 6)
1551 13:58:39.970868 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1552 13:58:39.973427 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1553 13:58:39.973999
1554 13:58:39.977678 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1555 13:58:39.980145 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1556 13:58:39.983352 [Gating] SW calibration Done
1557 13:58:39.983881 ==
1558 13:58:39.988101 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 13:58:39.990295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 13:58:39.990879 ==
1561 13:58:39.994112 RX Vref Scan: 0
1562 13:58:39.994669
1563 13:58:39.997725 RX Vref 0 -> 0, step: 1
1564 13:58:39.998192
1565 13:58:39.998564 RX Delay -130 -> 252, step: 16
1566 13:58:40.003864 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1567 13:58:40.007061 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1568 13:58:40.010579 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1569 13:58:40.013663 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1570 13:58:40.017091 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1571 13:58:40.023358 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1572 13:58:40.026774 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1573 13:58:40.029856 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1574 13:58:40.033615 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1575 13:58:40.036458 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1576 13:58:40.043104 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1577 13:58:40.046446 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1578 13:58:40.050121 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1579 13:58:40.052754 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1580 13:58:40.059878 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1581 13:58:40.063238 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1582 13:58:40.063826 ==
1583 13:58:40.066372 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 13:58:40.069751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 13:58:40.070311 ==
1586 13:58:40.073104 DQS Delay:
1587 13:58:40.073569 DQS0 = 0, DQS1 = 0
1588 13:58:40.074037 DQM Delay:
1589 13:58:40.076439 DQM0 = 88, DQM1 = 78
1590 13:58:40.077005 DQ Delay:
1591 13:58:40.079776 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1592 13:58:40.083068 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1593 13:58:40.086698 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1594 13:58:40.090277 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1595 13:58:40.090833
1596 13:58:40.091202
1597 13:58:40.091545 ==
1598 13:58:40.092931 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 13:58:40.099903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 13:58:40.100695 ==
1601 13:58:40.101092
1602 13:58:40.101438
1603 13:58:40.101771 TX Vref Scan disable
1604 13:58:40.103221 == TX Byte 0 ==
1605 13:58:40.106566 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1606 13:58:40.113368 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1607 13:58:40.113926 == TX Byte 1 ==
1608 13:58:40.116643 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1609 13:58:40.122936 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1610 13:58:40.123496 ==
1611 13:58:40.126213 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 13:58:40.129400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 13:58:40.129872 ==
1614 13:58:40.143141 TX Vref=22, minBit 3, minWin=26, winSum=441
1615 13:58:40.145972 TX Vref=24, minBit 8, minWin=27, winSum=446
1616 13:58:40.149385 TX Vref=26, minBit 8, minWin=27, winSum=447
1617 13:58:40.152566 TX Vref=28, minBit 8, minWin=27, winSum=447
1618 13:58:40.155956 TX Vref=30, minBit 0, minWin=27, winSum=445
1619 13:58:40.162287 TX Vref=32, minBit 9, minWin=27, winSum=444
1620 13:58:40.166101 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 26
1621 13:58:40.166752
1622 13:58:40.169808 Final TX Range 1 Vref 26
1623 13:58:40.170379
1624 13:58:40.170868 ==
1625 13:58:40.172310 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 13:58:40.175914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 13:58:40.176483 ==
1628 13:58:40.179113
1629 13:58:40.179689
1630 13:58:40.180223 TX Vref Scan disable
1631 13:58:40.182471 == TX Byte 0 ==
1632 13:58:40.186084 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1633 13:58:40.192358 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1634 13:58:40.192934 == TX Byte 1 ==
1635 13:58:40.196717 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1636 13:58:40.202481 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1637 13:58:40.203055
1638 13:58:40.203539 [DATLAT]
1639 13:58:40.204053 Freq=800, CH1 RK0
1640 13:58:40.204501
1641 13:58:40.205594 DATLAT Default: 0xa
1642 13:58:40.206068 0, 0xFFFF, sum = 0
1643 13:58:40.208692 1, 0xFFFF, sum = 0
1644 13:58:40.212491 2, 0xFFFF, sum = 0
1645 13:58:40.212971 3, 0xFFFF, sum = 0
1646 13:58:40.215246 4, 0xFFFF, sum = 0
1647 13:58:40.215753 5, 0xFFFF, sum = 0
1648 13:58:40.218450 6, 0xFFFF, sum = 0
1649 13:58:40.218886 7, 0xFFFF, sum = 0
1650 13:58:40.222016 8, 0xFFFF, sum = 0
1651 13:58:40.222545 9, 0x0, sum = 1
1652 13:58:40.225431 10, 0x0, sum = 2
1653 13:58:40.225866 11, 0x0, sum = 3
1654 13:58:40.229005 12, 0x0, sum = 4
1655 13:58:40.229439 best_step = 10
1656 13:58:40.229869
1657 13:58:40.230274 ==
1658 13:58:40.231937 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 13:58:40.234962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 13:58:40.235391 ==
1661 13:58:40.239133 RX Vref Scan: 1
1662 13:58:40.239661
1663 13:58:40.242048 Set Vref Range= 32 -> 127
1664 13:58:40.242571
1665 13:58:40.243012 RX Vref 32 -> 127, step: 1
1666 13:58:40.243418
1667 13:58:40.245414 RX Delay -95 -> 252, step: 8
1668 13:58:40.245940
1669 13:58:40.248525 Set Vref, RX VrefLevel [Byte0]: 32
1670 13:58:40.251803 [Byte1]: 32
1671 13:58:40.256070
1672 13:58:40.256595 Set Vref, RX VrefLevel [Byte0]: 33
1673 13:58:40.258273 [Byte1]: 33
1674 13:58:40.262632
1675 13:58:40.263058 Set Vref, RX VrefLevel [Byte0]: 34
1676 13:58:40.265959 [Byte1]: 34
1677 13:58:40.270611
1678 13:58:40.271147 Set Vref, RX VrefLevel [Byte0]: 35
1679 13:58:40.273771 [Byte1]: 35
1680 13:58:40.277787
1681 13:58:40.278328 Set Vref, RX VrefLevel [Byte0]: 36
1682 13:58:40.281834 [Byte1]: 36
1683 13:58:40.285738
1684 13:58:40.288591 Set Vref, RX VrefLevel [Byte0]: 37
1685 13:58:40.292898 [Byte1]: 37
1686 13:58:40.293418
1687 13:58:40.295369 Set Vref, RX VrefLevel [Byte0]: 38
1688 13:58:40.298449 [Byte1]: 38
1689 13:58:40.298876
1690 13:58:40.301838 Set Vref, RX VrefLevel [Byte0]: 39
1691 13:58:40.305914 [Byte1]: 39
1692 13:58:40.306443
1693 13:58:40.308560 Set Vref, RX VrefLevel [Byte0]: 40
1694 13:58:40.312179 [Byte1]: 40
1695 13:58:40.316118
1696 13:58:40.316643 Set Vref, RX VrefLevel [Byte0]: 41
1697 13:58:40.319394 [Byte1]: 41
1698 13:58:40.323947
1699 13:58:40.324470 Set Vref, RX VrefLevel [Byte0]: 42
1700 13:58:40.327321 [Byte1]: 42
1701 13:58:40.331341
1702 13:58:40.332067 Set Vref, RX VrefLevel [Byte0]: 43
1703 13:58:40.334191 [Byte1]: 43
1704 13:58:40.338721
1705 13:58:40.339230 Set Vref, RX VrefLevel [Byte0]: 44
1706 13:58:40.342385 [Byte1]: 44
1707 13:58:40.347146
1708 13:58:40.347655 Set Vref, RX VrefLevel [Byte0]: 45
1709 13:58:40.351045 [Byte1]: 45
1710 13:58:40.354186
1711 13:58:40.354694 Set Vref, RX VrefLevel [Byte0]: 46
1712 13:58:40.357467 [Byte1]: 46
1713 13:58:40.362279
1714 13:58:40.362787 Set Vref, RX VrefLevel [Byte0]: 47
1715 13:58:40.364674 [Byte1]: 47
1716 13:58:40.369685
1717 13:58:40.370273 Set Vref, RX VrefLevel [Byte0]: 48
1718 13:58:40.372397 [Byte1]: 48
1719 13:58:40.376887
1720 13:58:40.377449 Set Vref, RX VrefLevel [Byte0]: 49
1721 13:58:40.380013 [Byte1]: 49
1722 13:58:40.384327
1723 13:58:40.387641 Set Vref, RX VrefLevel [Byte0]: 50
1724 13:58:40.390968 [Byte1]: 50
1725 13:58:40.391533
1726 13:58:40.394121 Set Vref, RX VrefLevel [Byte0]: 51
1727 13:58:40.397971 [Byte1]: 51
1728 13:58:40.398456
1729 13:58:40.400510 Set Vref, RX VrefLevel [Byte0]: 52
1730 13:58:40.404088 [Byte1]: 52
1731 13:58:40.404549
1732 13:58:40.407501 Set Vref, RX VrefLevel [Byte0]: 53
1733 13:58:40.410825 [Byte1]: 53
1734 13:58:40.414926
1735 13:58:40.415479 Set Vref, RX VrefLevel [Byte0]: 54
1736 13:58:40.418491 [Byte1]: 54
1737 13:58:40.422425
1738 13:58:40.422982 Set Vref, RX VrefLevel [Byte0]: 55
1739 13:58:40.425841 [Byte1]: 55
1740 13:58:40.430308
1741 13:58:40.430862 Set Vref, RX VrefLevel [Byte0]: 56
1742 13:58:40.433371 [Byte1]: 56
1743 13:58:40.437505
1744 13:58:40.438152 Set Vref, RX VrefLevel [Byte0]: 57
1745 13:58:40.440849 [Byte1]: 57
1746 13:58:40.445177
1747 13:58:40.445730 Set Vref, RX VrefLevel [Byte0]: 58
1748 13:58:40.448944 [Byte1]: 58
1749 13:58:40.452569
1750 13:58:40.453030 Set Vref, RX VrefLevel [Byte0]: 59
1751 13:58:40.456551 [Byte1]: 59
1752 13:58:40.460726
1753 13:58:40.461281 Set Vref, RX VrefLevel [Byte0]: 60
1754 13:58:40.463601 [Byte1]: 60
1755 13:58:40.467906
1756 13:58:40.468486 Set Vref, RX VrefLevel [Byte0]: 61
1757 13:58:40.471422 [Byte1]: 61
1758 13:58:40.475291
1759 13:58:40.475790 Set Vref, RX VrefLevel [Byte0]: 62
1760 13:58:40.479053 [Byte1]: 62
1761 13:58:40.482894
1762 13:58:40.486424 Set Vref, RX VrefLevel [Byte0]: 63
1763 13:58:40.489681 [Byte1]: 63
1764 13:58:40.490239
1765 13:58:40.493166 Set Vref, RX VrefLevel [Byte0]: 64
1766 13:58:40.496045 [Byte1]: 64
1767 13:58:40.496604
1768 13:58:40.499516 Set Vref, RX VrefLevel [Byte0]: 65
1769 13:58:40.502636 [Byte1]: 65
1770 13:58:40.506061
1771 13:58:40.506634 Set Vref, RX VrefLevel [Byte0]: 66
1772 13:58:40.509471 [Byte1]: 66
1773 13:58:40.513524
1774 13:58:40.513983 Set Vref, RX VrefLevel [Byte0]: 67
1775 13:58:40.520674 [Byte1]: 67
1776 13:58:40.521230
1777 13:58:40.523019 Set Vref, RX VrefLevel [Byte0]: 68
1778 13:58:40.526763 [Byte1]: 68
1779 13:58:40.527321
1780 13:58:40.530120 Set Vref, RX VrefLevel [Byte0]: 69
1781 13:58:40.533465 [Byte1]: 69
1782 13:58:40.534021
1783 13:58:40.536893 Set Vref, RX VrefLevel [Byte0]: 70
1784 13:58:40.539880 [Byte1]: 70
1785 13:58:40.543838
1786 13:58:40.544391 Set Vref, RX VrefLevel [Byte0]: 71
1787 13:58:40.547553 [Byte1]: 71
1788 13:58:40.551271
1789 13:58:40.551870 Set Vref, RX VrefLevel [Byte0]: 72
1790 13:58:40.554557 [Byte1]: 72
1791 13:58:40.559410
1792 13:58:40.559991 Set Vref, RX VrefLevel [Byte0]: 73
1793 13:58:40.562338 [Byte1]: 73
1794 13:58:40.566606
1795 13:58:40.567159 Set Vref, RX VrefLevel [Byte0]: 74
1796 13:58:40.570219 [Byte1]: 74
1797 13:58:40.574151
1798 13:58:40.574608 Set Vref, RX VrefLevel [Byte0]: 75
1799 13:58:40.577346 [Byte1]: 75
1800 13:58:40.581731
1801 13:58:40.582207 Set Vref, RX VrefLevel [Byte0]: 76
1802 13:58:40.584973 [Byte1]: 76
1803 13:58:40.589929
1804 13:58:40.590497 Final RX Vref Byte 0 = 56 to rank0
1805 13:58:40.592814 Final RX Vref Byte 1 = 64 to rank0
1806 13:58:40.595634 Final RX Vref Byte 0 = 56 to rank1
1807 13:58:40.599692 Final RX Vref Byte 1 = 64 to rank1==
1808 13:58:40.602380 Dram Type= 6, Freq= 0, CH_1, rank 0
1809 13:58:40.609369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 13:58:40.609941 ==
1811 13:58:40.610415 DQS Delay:
1812 13:58:40.610979 DQS0 = 0, DQS1 = 0
1813 13:58:40.612719 DQM Delay:
1814 13:58:40.613134 DQM0 = 86, DQM1 = 79
1815 13:58:40.616156 DQ Delay:
1816 13:58:40.619280 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1817 13:58:40.622244 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1818 13:58:40.625962 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1819 13:58:40.629838 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1820 13:58:40.630253
1821 13:58:40.630580
1822 13:58:40.635937 [DQSOSCAuto] RK0, (LSB)MR18= 0x3420, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1823 13:58:40.639185 CH1 RK0: MR19=606, MR18=3420
1824 13:58:40.645807 CH1_RK0: MR19=0x606, MR18=0x3420, DQSOSC=396, MR23=63, INC=94, DEC=62
1825 13:58:40.646318
1826 13:58:40.648817 ----->DramcWriteLeveling(PI) begin...
1827 13:58:40.649378 ==
1828 13:58:40.652356 Dram Type= 6, Freq= 0, CH_1, rank 1
1829 13:58:40.655464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1830 13:58:40.656084 ==
1831 13:58:40.658844 Write leveling (Byte 0): 27 => 27
1832 13:58:40.662145 Write leveling (Byte 1): 28 => 28
1833 13:58:40.665083 DramcWriteLeveling(PI) end<-----
1834 13:58:40.665541
1835 13:58:40.665902 ==
1836 13:58:40.668717 Dram Type= 6, Freq= 0, CH_1, rank 1
1837 13:58:40.672079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1838 13:58:40.676000 ==
1839 13:58:40.676553 [Gating] SW mode calibration
1840 13:58:40.685237 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1841 13:58:40.688609 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1842 13:58:40.692462 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1843 13:58:40.698442 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1844 13:58:40.701419 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:58:40.705506 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:58:40.711799 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:58:40.715114 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:58:40.718499 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 13:58:40.726287 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 13:58:40.728072 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 13:58:40.731293 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 13:58:40.738670 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 13:58:40.741468 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:58:40.745350 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 13:58:40.751464 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 13:58:40.755145 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 13:58:40.758438 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 13:58:40.764630 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 13:58:40.768246 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1860 13:58:40.772123 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 13:58:40.775476 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 13:58:40.781964 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 13:58:40.784947 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 13:58:40.788341 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 13:58:40.795420 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 13:58:40.798675 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 13:58:40.801467 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1868 13:58:40.808466 0 9 8 | B1->B0 | 3232 2a2a | 1 0 | (1 1) (1 1)
1869 13:58:40.811611 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 13:58:40.815188 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 13:58:40.821988 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 13:58:40.825119 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 13:58:40.828210 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 13:58:40.834664 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 13:58:40.838413 0 10 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 0)
1876 13:58:40.841462 0 10 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1877 13:58:40.847985 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 13:58:40.851422 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 13:58:40.854750 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 13:58:40.861801 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 13:58:40.864664 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 13:58:40.868277 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 13:58:40.874817 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1884 13:58:40.877991 0 11 8 | B1->B0 | 4040 3838 | 0 1 | (0 0) (0 0)
1885 13:58:40.881164 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 13:58:40.888246 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 13:58:40.891444 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 13:58:40.894574 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 13:58:40.901498 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 13:58:40.904693 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 13:58:40.908199 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 13:58:40.911080 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1893 13:58:40.918211 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 13:58:40.920951 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 13:58:40.925033 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 13:58:40.930877 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 13:58:40.934523 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 13:58:40.937718 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 13:58:40.944951 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 13:58:40.947320 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 13:58:40.950921 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 13:58:40.957463 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 13:58:40.960861 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 13:58:40.963893 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 13:58:40.970674 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 13:58:40.973691 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 13:58:40.977604 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 13:58:40.984372 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1909 13:58:40.987534 Total UI for P1: 0, mck2ui 16
1910 13:58:40.990114 best dqsien dly found for B1: ( 0, 14, 6)
1911 13:58:40.993796 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 13:58:40.997111 Total UI for P1: 0, mck2ui 16
1913 13:58:41.000392 best dqsien dly found for B0: ( 0, 14, 8)
1914 13:58:41.003544 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1915 13:58:41.007172 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1916 13:58:41.007767
1917 13:58:41.010640 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1918 13:58:41.013459 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1919 13:58:41.017065 [Gating] SW calibration Done
1920 13:58:41.017618 ==
1921 13:58:41.020586 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 13:58:41.024154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 13:58:41.027183 ==
1924 13:58:41.027777 RX Vref Scan: 0
1925 13:58:41.028163
1926 13:58:41.030598 RX Vref 0 -> 0, step: 1
1927 13:58:41.031069
1928 13:58:41.033647 RX Delay -130 -> 252, step: 16
1929 13:58:41.037024 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1930 13:58:41.040247 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1931 13:58:41.044313 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1932 13:58:41.046747 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1933 13:58:41.053988 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1934 13:58:41.056815 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1935 13:58:41.060407 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1936 13:58:41.063417 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1937 13:58:41.067080 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1938 13:58:41.073209 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1939 13:58:41.076907 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1940 13:58:41.080127 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1941 13:58:41.083885 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1942 13:58:41.086860 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1943 13:58:41.093712 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1944 13:58:41.096422 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1945 13:58:41.096890 ==
1946 13:58:41.100025 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 13:58:41.103400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 13:58:41.104019 ==
1949 13:58:41.107041 DQS Delay:
1950 13:58:41.107595 DQS0 = 0, DQS1 = 0
1951 13:58:41.110017 DQM Delay:
1952 13:58:41.110567 DQM0 = 86, DQM1 = 78
1953 13:58:41.110939 DQ Delay:
1954 13:58:41.113251 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1955 13:58:41.116457 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1956 13:58:41.120335 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1957 13:58:41.123665 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1958 13:58:41.124263
1959 13:58:41.124636
1960 13:58:41.124986 ==
1961 13:58:41.126843 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 13:58:41.133133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 13:58:41.133680 ==
1964 13:58:41.134164
1965 13:58:41.134522
1966 13:58:41.134856 TX Vref Scan disable
1967 13:58:41.136855 == TX Byte 0 ==
1968 13:58:41.140240 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1969 13:58:41.146951 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1970 13:58:41.147511 == TX Byte 1 ==
1971 13:58:41.150585 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1972 13:58:41.156752 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1973 13:58:41.157374 ==
1974 13:58:41.160442 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 13:58:41.163361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 13:58:41.163915 ==
1977 13:58:41.175993 TX Vref=22, minBit 1, minWin=27, winSum=443
1978 13:58:41.179547 TX Vref=24, minBit 8, minWin=27, winSum=450
1979 13:58:41.182956 TX Vref=26, minBit 8, minWin=27, winSum=449
1980 13:58:41.186310 TX Vref=28, minBit 8, minWin=27, winSum=450
1981 13:58:41.189657 TX Vref=30, minBit 8, minWin=27, winSum=452
1982 13:58:41.196047 TX Vref=32, minBit 8, minWin=27, winSum=446
1983 13:58:41.199365 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 30
1984 13:58:41.200013
1985 13:58:41.202738 Final TX Range 1 Vref 30
1986 13:58:41.203201
1987 13:58:41.203704 ==
1988 13:58:41.206255 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 13:58:41.209912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 13:58:41.210485 ==
1991 13:58:41.212496
1992 13:58:41.212960
1993 13:58:41.213328 TX Vref Scan disable
1994 13:58:41.216129 == TX Byte 0 ==
1995 13:58:41.219570 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1996 13:58:41.226199 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1997 13:58:41.226757 == TX Byte 1 ==
1998 13:58:41.230007 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1999 13:58:41.235905 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2000 13:58:41.236462
2001 13:58:41.236835 [DATLAT]
2002 13:58:41.237183 Freq=800, CH1 RK1
2003 13:58:41.237514
2004 13:58:41.239394 DATLAT Default: 0xa
2005 13:58:41.239909 0, 0xFFFF, sum = 0
2006 13:58:41.242754 1, 0xFFFF, sum = 0
2007 13:58:41.246032 2, 0xFFFF, sum = 0
2008 13:58:41.246589 3, 0xFFFF, sum = 0
2009 13:58:41.249871 4, 0xFFFF, sum = 0
2010 13:58:41.250433 5, 0xFFFF, sum = 0
2011 13:58:41.252924 6, 0xFFFF, sum = 0
2012 13:58:41.253481 7, 0xFFFF, sum = 0
2013 13:58:41.256658 8, 0xFFFF, sum = 0
2014 13:58:41.257222 9, 0x0, sum = 1
2015 13:58:41.257607 10, 0x0, sum = 2
2016 13:58:41.259532 11, 0x0, sum = 3
2017 13:58:41.260045 12, 0x0, sum = 4
2018 13:58:41.262732 best_step = 10
2019 13:58:41.263282
2020 13:58:41.263692 ==
2021 13:58:41.265924 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 13:58:41.269296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 13:58:41.269876 ==
2024 13:58:41.272699 RX Vref Scan: 0
2025 13:58:41.273375
2026 13:58:41.273879 RX Vref 0 -> 0, step: 1
2027 13:58:41.274237
2028 13:58:41.275838 RX Delay -95 -> 252, step: 8
2029 13:58:41.283061 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2030 13:58:41.285933 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2031 13:58:41.289432 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2032 13:58:41.293031 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2033 13:58:41.295902 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2034 13:58:41.302574 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2035 13:58:41.305889 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2036 13:58:41.309175 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2037 13:58:41.312539 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2038 13:58:41.316202 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2039 13:58:41.322944 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2040 13:58:41.326102 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2041 13:58:41.329305 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2042 13:58:41.333019 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2043 13:58:41.339396 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2044 13:58:41.342354 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2045 13:58:41.342913 ==
2046 13:58:41.345809 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 13:58:41.348936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 13:58:41.349531 ==
2049 13:58:41.352365 DQS Delay:
2050 13:58:41.352922 DQS0 = 0, DQS1 = 0
2051 13:58:41.353294 DQM Delay:
2052 13:58:41.355950 DQM0 = 87, DQM1 = 78
2053 13:58:41.356509 DQ Delay:
2054 13:58:41.359098 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2055 13:58:41.362548 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2056 13:58:41.365881 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2057 13:58:41.369188 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2058 13:58:41.369782
2059 13:58:41.370161
2060 13:58:41.379411 [DQSOSCAuto] RK1, (LSB)MR18= 0x2018, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2061 13:58:41.380014 CH1 RK1: MR19=606, MR18=2018
2062 13:58:41.385591 CH1_RK1: MR19=0x606, MR18=0x2018, DQSOSC=401, MR23=63, INC=91, DEC=61
2063 13:58:41.388911 [RxdqsGatingPostProcess] freq 800
2064 13:58:41.395822 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2065 13:58:41.398879 Pre-setting of DQS Precalculation
2066 13:58:41.401969 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2067 13:58:41.409025 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2068 13:58:41.419434 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2069 13:58:41.420029
2070 13:58:41.420406
2071 13:58:41.422086 [Calibration Summary] 1600 Mbps
2072 13:58:41.422554 CH 0, Rank 0
2073 13:58:41.425602 SW Impedance : PASS
2074 13:58:41.426331 DUTY Scan : NO K
2075 13:58:41.428607 ZQ Calibration : PASS
2076 13:58:41.432189 Jitter Meter : NO K
2077 13:58:41.432654 CBT Training : PASS
2078 13:58:41.435227 Write leveling : PASS
2079 13:58:41.435691 RX DQS gating : PASS
2080 13:58:41.439177 RX DQ/DQS(RDDQC) : PASS
2081 13:58:41.441864 TX DQ/DQS : PASS
2082 13:58:41.442332 RX DATLAT : PASS
2083 13:58:41.445407 RX DQ/DQS(Engine): PASS
2084 13:58:41.448696 TX OE : NO K
2085 13:58:41.449254 All Pass.
2086 13:58:41.449624
2087 13:58:41.449966 CH 0, Rank 1
2088 13:58:41.451773 SW Impedance : PASS
2089 13:58:41.455533 DUTY Scan : NO K
2090 13:58:41.456129 ZQ Calibration : PASS
2091 13:58:41.458719 Jitter Meter : NO K
2092 13:58:41.462142 CBT Training : PASS
2093 13:58:41.462699 Write leveling : PASS
2094 13:58:41.465614 RX DQS gating : PASS
2095 13:58:41.468929 RX DQ/DQS(RDDQC) : PASS
2096 13:58:41.469485 TX DQ/DQS : PASS
2097 13:58:41.472382 RX DATLAT : PASS
2098 13:58:41.475411 RX DQ/DQS(Engine): PASS
2099 13:58:41.475910 TX OE : NO K
2100 13:58:41.476287 All Pass.
2101 13:58:41.478823
2102 13:58:41.479427 CH 1, Rank 0
2103 13:58:41.482346 SW Impedance : PASS
2104 13:58:41.482905 DUTY Scan : NO K
2105 13:58:41.485334 ZQ Calibration : PASS
2106 13:58:41.485894 Jitter Meter : NO K
2107 13:58:41.488428 CBT Training : PASS
2108 13:58:41.492195 Write leveling : PASS
2109 13:58:41.492756 RX DQS gating : PASS
2110 13:58:41.495793 RX DQ/DQS(RDDQC) : PASS
2111 13:58:41.498795 TX DQ/DQS : PASS
2112 13:58:41.499353 RX DATLAT : PASS
2113 13:58:41.501984 RX DQ/DQS(Engine): PASS
2114 13:58:41.505460 TX OE : NO K
2115 13:58:41.505927 All Pass.
2116 13:58:41.506299
2117 13:58:41.506643 CH 1, Rank 1
2118 13:58:41.508240 SW Impedance : PASS
2119 13:58:41.511814 DUTY Scan : NO K
2120 13:58:41.512371 ZQ Calibration : PASS
2121 13:58:41.515382 Jitter Meter : NO K
2122 13:58:41.518682 CBT Training : PASS
2123 13:58:41.519235 Write leveling : PASS
2124 13:58:41.521971 RX DQS gating : PASS
2125 13:58:41.524953 RX DQ/DQS(RDDQC) : PASS
2126 13:58:41.525425 TX DQ/DQS : PASS
2127 13:58:41.528507 RX DATLAT : PASS
2128 13:58:41.528973 RX DQ/DQS(Engine): PASS
2129 13:58:41.531668 TX OE : NO K
2130 13:58:41.532193 All Pass.
2131 13:58:41.532568
2132 13:58:41.535218 DramC Write-DBI off
2133 13:58:41.538439 PER_BANK_REFRESH: Hybrid Mode
2134 13:58:41.539009 TX_TRACKING: ON
2135 13:58:41.541626 [GetDramInforAfterCalByMRR] Vendor 6.
2136 13:58:41.544974 [GetDramInforAfterCalByMRR] Revision 606.
2137 13:58:41.551945 [GetDramInforAfterCalByMRR] Revision 2 0.
2138 13:58:41.552507 MR0 0x3b3b
2139 13:58:41.552882 MR8 0x5151
2140 13:58:41.555794 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2141 13:58:41.556352
2142 13:58:41.558000 MR0 0x3b3b
2143 13:58:41.558464 MR8 0x5151
2144 13:58:41.561637 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2145 13:58:41.562195
2146 13:58:41.573654 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2147 13:58:41.575002 [FAST_K] Save calibration result to emmc
2148 13:58:41.578105 [FAST_K] Save calibration result to emmc
2149 13:58:41.581574 dram_init: config_dvfs: 1
2150 13:58:41.585061 dramc_set_vcore_voltage set vcore to 662500
2151 13:58:41.588983 Read voltage for 1200, 2
2152 13:58:41.589542 Vio18 = 0
2153 13:58:41.589916 Vcore = 662500
2154 13:58:41.590262 Vdram = 0
2155 13:58:41.591462 Vddq = 0
2156 13:58:41.592025 Vmddr = 0
2157 13:58:41.598357 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2158 13:58:41.601335 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2159 13:58:41.604661 MEM_TYPE=3, freq_sel=15
2160 13:58:41.608079 sv_algorithm_assistance_LP4_1600
2161 13:58:41.611230 ============ PULL DRAM RESETB DOWN ============
2162 13:58:41.614767 ========== PULL DRAM RESETB DOWN end =========
2163 13:58:41.621349 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2164 13:58:41.625599 ===================================
2165 13:58:41.626157 LPDDR4 DRAM CONFIGURATION
2166 13:58:41.628302 ===================================
2167 13:58:41.630882 EX_ROW_EN[0] = 0x0
2168 13:58:41.634563 EX_ROW_EN[1] = 0x0
2169 13:58:41.635024 LP4Y_EN = 0x0
2170 13:58:41.637739 WORK_FSP = 0x0
2171 13:58:41.638157 WL = 0x4
2172 13:58:41.641147 RL = 0x4
2173 13:58:41.641568 BL = 0x2
2174 13:58:41.644402 RPST = 0x0
2175 13:58:41.644819 RD_PRE = 0x0
2176 13:58:41.647684 WR_PRE = 0x1
2177 13:58:41.648178 WR_PST = 0x0
2178 13:58:41.651280 DBI_WR = 0x0
2179 13:58:41.651702 DBI_RD = 0x0
2180 13:58:41.655032 OTF = 0x1
2181 13:58:41.658602 ===================================
2182 13:58:41.661764 ===================================
2183 13:58:41.662258 ANA top config
2184 13:58:41.664985 ===================================
2185 13:58:41.667751 DLL_ASYNC_EN = 0
2186 13:58:41.671645 ALL_SLAVE_EN = 0
2187 13:58:41.672202 NEW_RANK_MODE = 1
2188 13:58:41.674607 DLL_IDLE_MODE = 1
2189 13:58:41.678392 LP45_APHY_COMB_EN = 1
2190 13:58:41.681668 TX_ODT_DIS = 1
2191 13:58:41.684622 NEW_8X_MODE = 1
2192 13:58:41.687899 ===================================
2193 13:58:41.691755 ===================================
2194 13:58:41.692268 data_rate = 2400
2195 13:58:41.694628 CKR = 1
2196 13:58:41.697990 DQ_P2S_RATIO = 8
2197 13:58:41.701167 ===================================
2198 13:58:41.704299 CA_P2S_RATIO = 8
2199 13:58:41.707406 DQ_CA_OPEN = 0
2200 13:58:41.711814 DQ_SEMI_OPEN = 0
2201 13:58:41.712242 CA_SEMI_OPEN = 0
2202 13:58:41.714622 CA_FULL_RATE = 0
2203 13:58:41.717699 DQ_CKDIV4_EN = 0
2204 13:58:41.721246 CA_CKDIV4_EN = 0
2205 13:58:41.724235 CA_PREDIV_EN = 0
2206 13:58:41.727912 PH8_DLY = 17
2207 13:58:41.728462 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2208 13:58:41.731116 DQ_AAMCK_DIV = 4
2209 13:58:41.734824 CA_AAMCK_DIV = 4
2210 13:58:41.738377 CA_ADMCK_DIV = 4
2211 13:58:41.741292 DQ_TRACK_CA_EN = 0
2212 13:58:41.744116 CA_PICK = 1200
2213 13:58:41.747807 CA_MCKIO = 1200
2214 13:58:41.748361 MCKIO_SEMI = 0
2215 13:58:41.751040 PLL_FREQ = 2366
2216 13:58:41.754351 DQ_UI_PI_RATIO = 32
2217 13:58:41.757799 CA_UI_PI_RATIO = 0
2218 13:58:41.761022 ===================================
2219 13:58:41.764739 ===================================
2220 13:58:41.767843 memory_type:LPDDR4
2221 13:58:41.768302 GP_NUM : 10
2222 13:58:41.771067 SRAM_EN : 1
2223 13:58:41.774231 MD32_EN : 0
2224 13:58:41.774791 ===================================
2225 13:58:41.777312 [ANA_INIT] >>>>>>>>>>>>>>
2226 13:58:41.780699 <<<<<< [CONFIGURE PHASE]: ANA_TX
2227 13:58:41.784347 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2228 13:58:41.787311 ===================================
2229 13:58:41.791085 data_rate = 2400,PCW = 0X5b00
2230 13:58:41.794462 ===================================
2231 13:58:41.797919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2232 13:58:41.804445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2233 13:58:41.807834 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2234 13:58:41.813960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2235 13:58:41.819003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2236 13:58:41.820675 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2237 13:58:41.821142 [ANA_INIT] flow start
2238 13:58:41.824207 [ANA_INIT] PLL >>>>>>>>
2239 13:58:41.827188 [ANA_INIT] PLL <<<<<<<<
2240 13:58:41.827787 [ANA_INIT] MIDPI >>>>>>>>
2241 13:58:41.830835 [ANA_INIT] MIDPI <<<<<<<<
2242 13:58:41.834341 [ANA_INIT] DLL >>>>>>>>
2243 13:58:41.834807 [ANA_INIT] DLL <<<<<<<<
2244 13:58:41.838049 [ANA_INIT] flow end
2245 13:58:41.840557 ============ LP4 DIFF to SE enter ============
2246 13:58:41.847328 ============ LP4 DIFF to SE exit ============
2247 13:58:41.847926 [ANA_INIT] <<<<<<<<<<<<<
2248 13:58:41.850707 [Flow] Enable top DCM control >>>>>
2249 13:58:41.854011 [Flow] Enable top DCM control <<<<<
2250 13:58:41.857317 Enable DLL master slave shuffle
2251 13:58:41.864258 ==============================================================
2252 13:58:41.864813 Gating Mode config
2253 13:58:41.870319 ==============================================================
2254 13:58:41.874437 Config description:
2255 13:58:41.880601 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2256 13:58:41.887096 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2257 13:58:41.893585 SELPH_MODE 0: By rank 1: By Phase
2258 13:58:41.900542 ==============================================================
2259 13:58:41.901101 GAT_TRACK_EN = 1
2260 13:58:41.903907 RX_GATING_MODE = 2
2261 13:58:41.907258 RX_GATING_TRACK_MODE = 2
2262 13:58:41.910628 SELPH_MODE = 1
2263 13:58:41.914081 PICG_EARLY_EN = 1
2264 13:58:41.916671 VALID_LAT_VALUE = 1
2265 13:58:41.923110 ==============================================================
2266 13:58:41.927052 Enter into Gating configuration >>>>
2267 13:58:41.930321 Exit from Gating configuration <<<<
2268 13:58:41.933027 Enter into DVFS_PRE_config >>>>>
2269 13:58:41.943190 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2270 13:58:41.946614 Exit from DVFS_PRE_config <<<<<
2271 13:58:41.950241 Enter into PICG configuration >>>>
2272 13:58:41.953185 Exit from PICG configuration <<<<
2273 13:58:41.956270 [RX_INPUT] configuration >>>>>
2274 13:58:41.959842 [RX_INPUT] configuration <<<<<
2275 13:58:41.963253 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2276 13:58:41.970357 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2277 13:58:41.976447 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2278 13:58:41.983184 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2279 13:58:41.986575 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2280 13:58:41.992839 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2281 13:58:41.996615 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2282 13:58:42.002712 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2283 13:58:42.006278 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2284 13:58:42.009680 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2285 13:58:42.013353 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2286 13:58:42.019441 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 13:58:42.022941 ===================================
2288 13:58:42.023495 LPDDR4 DRAM CONFIGURATION
2289 13:58:42.025852 ===================================
2290 13:58:42.029536 EX_ROW_EN[0] = 0x0
2291 13:58:42.032261 EX_ROW_EN[1] = 0x0
2292 13:58:42.032833 LP4Y_EN = 0x0
2293 13:58:42.036255 WORK_FSP = 0x0
2294 13:58:42.036818 WL = 0x4
2295 13:58:42.039884 RL = 0x4
2296 13:58:42.040452 BL = 0x2
2297 13:58:42.042633 RPST = 0x0
2298 13:58:42.043189 RD_PRE = 0x0
2299 13:58:42.045770 WR_PRE = 0x1
2300 13:58:42.046234 WR_PST = 0x0
2301 13:58:42.049235 DBI_WR = 0x0
2302 13:58:42.049788 DBI_RD = 0x0
2303 13:58:42.053064 OTF = 0x1
2304 13:58:42.055949 ===================================
2305 13:58:42.059293 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2306 13:58:42.062503 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2307 13:58:42.068793 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2308 13:58:42.073351 ===================================
2309 13:58:42.073812 LPDDR4 DRAM CONFIGURATION
2310 13:58:42.075424 ===================================
2311 13:58:42.078979 EX_ROW_EN[0] = 0x10
2312 13:58:42.082238 EX_ROW_EN[1] = 0x0
2313 13:58:42.082653 LP4Y_EN = 0x0
2314 13:58:42.085965 WORK_FSP = 0x0
2315 13:58:42.086379 WL = 0x4
2316 13:58:42.088923 RL = 0x4
2317 13:58:42.089337 BL = 0x2
2318 13:58:42.092189 RPST = 0x0
2319 13:58:42.092603 RD_PRE = 0x0
2320 13:58:42.095657 WR_PRE = 0x1
2321 13:58:42.096210 WR_PST = 0x0
2322 13:58:42.099347 DBI_WR = 0x0
2323 13:58:42.100089 DBI_RD = 0x0
2324 13:58:42.101985 OTF = 0x1
2325 13:58:42.105693 ===================================
2326 13:58:42.112312 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2327 13:58:42.112731 ==
2328 13:58:42.116044 Dram Type= 6, Freq= 0, CH_0, rank 0
2329 13:58:42.118727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2330 13:58:42.119163 ==
2331 13:58:42.122372 [Duty_Offset_Calibration]
2332 13:58:42.122879 B0:1 B1:-1 CA:0
2333 13:58:42.123212
2334 13:58:42.125288 [DutyScan_Calibration_Flow] k_type=0
2335 13:58:42.135185
2336 13:58:42.135643 ==CLK 0==
2337 13:58:42.138559 Final CLK duty delay cell = 0
2338 13:58:42.142058 [0] MAX Duty = 5125%(X100), DQS PI = 24
2339 13:58:42.145405 [0] MIN Duty = 4907%(X100), DQS PI = 6
2340 13:58:42.149563 [0] AVG Duty = 5016%(X100)
2341 13:58:42.150111
2342 13:58:42.152060 CH0 CLK Duty spec in!! Max-Min= 218%
2343 13:58:42.155628 [DutyScan_Calibration_Flow] ====Done====
2344 13:58:42.156135
2345 13:58:42.159198 [DutyScan_Calibration_Flow] k_type=1
2346 13:58:42.174092
2347 13:58:42.174648 ==DQS 0 ==
2348 13:58:42.177756 Final DQS duty delay cell = -4
2349 13:58:42.181216 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2350 13:58:42.184300 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2351 13:58:42.187667 [-4] AVG Duty = 4968%(X100)
2352 13:58:42.188277
2353 13:58:42.188641 ==DQS 1 ==
2354 13:58:42.190835 Final DQS duty delay cell = 0
2355 13:58:42.194179 [0] MAX Duty = 5124%(X100), DQS PI = 4
2356 13:58:42.197411 [0] MIN Duty = 5000%(X100), DQS PI = 22
2357 13:58:42.200967 [0] AVG Duty = 5062%(X100)
2358 13:58:42.201520
2359 13:58:42.203941 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2360 13:58:42.204498
2361 13:58:42.207481 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2362 13:58:42.210505 [DutyScan_Calibration_Flow] ====Done====
2363 13:58:42.210966
2364 13:58:42.213680 [DutyScan_Calibration_Flow] k_type=3
2365 13:58:42.231988
2366 13:58:42.232537 ==DQM 0 ==
2367 13:58:42.234678 Final DQM duty delay cell = 0
2368 13:58:42.238607 [0] MAX Duty = 5062%(X100), DQS PI = 24
2369 13:58:42.242248 [0] MIN Duty = 4875%(X100), DQS PI = 8
2370 13:58:42.245437 [0] AVG Duty = 4968%(X100)
2371 13:58:42.245894
2372 13:58:42.246258 ==DQM 1 ==
2373 13:58:42.248943 Final DQM duty delay cell = 4
2374 13:58:42.252184 [4] MAX Duty = 5187%(X100), DQS PI = 32
2375 13:58:42.255568 [4] MIN Duty = 5000%(X100), DQS PI = 22
2376 13:58:42.256166 [4] AVG Duty = 5093%(X100)
2377 13:58:42.258978
2378 13:58:42.261872 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2379 13:58:42.262429
2380 13:58:42.264888 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2381 13:58:42.268361 [DutyScan_Calibration_Flow] ====Done====
2382 13:58:42.269090
2383 13:58:42.271814 [DutyScan_Calibration_Flow] k_type=2
2384 13:58:42.286745
2385 13:58:42.287304 ==DQ 0 ==
2386 13:58:42.289616 Final DQ duty delay cell = -4
2387 13:58:42.293773 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2388 13:58:42.296435 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2389 13:58:42.299780 [-4] AVG Duty = 4969%(X100)
2390 13:58:42.300335
2391 13:58:42.300702 ==DQ 1 ==
2392 13:58:42.303074 Final DQ duty delay cell = -4
2393 13:58:42.306600 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2394 13:58:42.309885 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2395 13:58:42.313102 [-4] AVG Duty = 4922%(X100)
2396 13:58:42.313560
2397 13:58:42.316500 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2398 13:58:42.317121
2399 13:58:42.319506 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2400 13:58:42.323587 [DutyScan_Calibration_Flow] ====Done====
2401 13:58:42.324207 ==
2402 13:58:42.326183 Dram Type= 6, Freq= 0, CH_1, rank 0
2403 13:58:42.329364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2404 13:58:42.329939 ==
2405 13:58:42.332745 [Duty_Offset_Calibration]
2406 13:58:42.335866 B0:-1 B1:1 CA:2
2407 13:58:42.336323
2408 13:58:42.339311 [DutyScan_Calibration_Flow] k_type=0
2409 13:58:42.347256
2410 13:58:42.347866 ==CLK 0==
2411 13:58:42.350558 Final CLK duty delay cell = 0
2412 13:58:42.354010 [0] MAX Duty = 5156%(X100), DQS PI = 20
2413 13:58:42.357378 [0] MIN Duty = 4969%(X100), DQS PI = 62
2414 13:58:42.357940 [0] AVG Duty = 5062%(X100)
2415 13:58:42.360672
2416 13:58:42.363983 CH1 CLK Duty spec in!! Max-Min= 187%
2417 13:58:42.366794 [DutyScan_Calibration_Flow] ====Done====
2418 13:58:42.367350
2419 13:58:42.370070 [DutyScan_Calibration_Flow] k_type=1
2420 13:58:42.386979
2421 13:58:42.387533 ==DQS 0 ==
2422 13:58:42.390228 Final DQS duty delay cell = 0
2423 13:58:42.393409 [0] MAX Duty = 5125%(X100), DQS PI = 48
2424 13:58:42.396718 [0] MIN Duty = 4907%(X100), DQS PI = 6
2425 13:58:42.397297 [0] AVG Duty = 5016%(X100)
2426 13:58:42.399812
2427 13:58:42.400380 ==DQS 1 ==
2428 13:58:42.402848 Final DQS duty delay cell = 0
2429 13:58:42.406470 [0] MAX Duty = 5094%(X100), DQS PI = 12
2430 13:58:42.409693 [0] MIN Duty = 4969%(X100), DQS PI = 58
2431 13:58:42.412964 [0] AVG Duty = 5031%(X100)
2432 13:58:42.413422
2433 13:58:42.416664 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2434 13:58:42.417259
2435 13:58:42.419946 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2436 13:58:42.423141 [DutyScan_Calibration_Flow] ====Done====
2437 13:58:42.423796
2438 13:58:42.426582 [DutyScan_Calibration_Flow] k_type=3
2439 13:58:42.442559
2440 13:58:42.443175 ==DQM 0 ==
2441 13:58:42.445462 Final DQM duty delay cell = -4
2442 13:58:42.448757 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2443 13:58:42.452628 [-4] MIN Duty = 4876%(X100), DQS PI = 4
2444 13:58:42.455862 [-4] AVG Duty = 4969%(X100)
2445 13:58:42.456418
2446 13:58:42.456791 ==DQM 1 ==
2447 13:58:42.459383 Final DQM duty delay cell = 0
2448 13:58:42.462356 [0] MAX Duty = 5187%(X100), DQS PI = 4
2449 13:58:42.465081 [0] MIN Duty = 5000%(X100), DQS PI = 28
2450 13:58:42.468823 [0] AVG Duty = 5093%(X100)
2451 13:58:42.469524
2452 13:58:42.472518 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2453 13:58:42.473073
2454 13:58:42.475364 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2455 13:58:42.478980 [DutyScan_Calibration_Flow] ====Done====
2456 13:58:42.479539
2457 13:58:42.481932 [DutyScan_Calibration_Flow] k_type=2
2458 13:58:42.499011
2459 13:58:42.499608 ==DQ 0 ==
2460 13:58:42.502165 Final DQ duty delay cell = 0
2461 13:58:42.505336 [0] MAX Duty = 5156%(X100), DQS PI = 28
2462 13:58:42.509258 [0] MIN Duty = 4907%(X100), DQS PI = 6
2463 13:58:42.509819 [0] AVG Duty = 5031%(X100)
2464 13:58:42.511830
2465 13:58:42.512293 ==DQ 1 ==
2466 13:58:42.515623 Final DQ duty delay cell = 0
2467 13:58:42.519077 [0] MAX Duty = 5124%(X100), DQS PI = 10
2468 13:58:42.522305 [0] MIN Duty = 4969%(X100), DQS PI = 0
2469 13:58:42.522862 [0] AVG Duty = 5046%(X100)
2470 13:58:42.523237
2471 13:58:42.528847 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2472 13:58:42.529404
2473 13:58:42.532584 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2474 13:58:42.535200 [DutyScan_Calibration_Flow] ====Done====
2475 13:58:42.538458 nWR fixed to 30
2476 13:58:42.539019 [ModeRegInit_LP4] CH0 RK0
2477 13:58:42.541636 [ModeRegInit_LP4] CH0 RK1
2478 13:58:42.545746 [ModeRegInit_LP4] CH1 RK0
2479 13:58:42.548185 [ModeRegInit_LP4] CH1 RK1
2480 13:58:42.548663 match AC timing 7
2481 13:58:42.555027 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2482 13:58:42.558413 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2483 13:58:42.561691 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2484 13:58:42.568440 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2485 13:58:42.572432 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2486 13:58:42.573005 ==
2487 13:58:42.575160 Dram Type= 6, Freq= 0, CH_0, rank 0
2488 13:58:42.578105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 13:58:42.578658 ==
2490 13:58:42.585232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 13:58:42.591121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2492 13:58:42.598825 [CA 0] Center 39 (9~70) winsize 62
2493 13:58:42.602056 [CA 1] Center 39 (9~69) winsize 61
2494 13:58:42.605631 [CA 2] Center 35 (5~66) winsize 62
2495 13:58:42.608817 [CA 3] Center 35 (5~66) winsize 62
2496 13:58:42.611873 [CA 4] Center 33 (4~63) winsize 60
2497 13:58:42.615444 [CA 5] Center 33 (3~63) winsize 61
2498 13:58:42.616063
2499 13:58:42.618696 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2500 13:58:42.619162
2501 13:58:42.621958 [CATrainingPosCal] consider 1 rank data
2502 13:58:42.625625 u2DelayCellTimex100 = 270/100 ps
2503 13:58:42.628597 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2504 13:58:42.635189 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2505 13:58:42.638269 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 13:58:42.641459 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2507 13:58:42.645079 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2508 13:58:42.648654 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2509 13:58:42.649210
2510 13:58:42.651514 CA PerBit enable=1, Macro0, CA PI delay=33
2511 13:58:42.652296
2512 13:58:42.655559 [CBTSetCACLKResult] CA Dly = 33
2513 13:58:42.658285 CS Dly: 8 (0~39)
2514 13:58:42.658843 ==
2515 13:58:42.661423 Dram Type= 6, Freq= 0, CH_0, rank 1
2516 13:58:42.664582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 13:58:42.665076 ==
2518 13:58:42.671207 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 13:58:42.674961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2520 13:58:42.684216 [CA 0] Center 39 (9~70) winsize 62
2521 13:58:42.687915 [CA 1] Center 39 (9~70) winsize 62
2522 13:58:42.691233 [CA 2] Center 35 (5~66) winsize 62
2523 13:58:42.694231 [CA 3] Center 34 (4~65) winsize 62
2524 13:58:42.697864 [CA 4] Center 33 (3~64) winsize 62
2525 13:58:42.701430 [CA 5] Center 33 (3~63) winsize 61
2526 13:58:42.701947
2527 13:58:42.704593 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2528 13:58:42.705015
2529 13:58:42.707712 [CATrainingPosCal] consider 2 rank data
2530 13:58:42.711691 u2DelayCellTimex100 = 270/100 ps
2531 13:58:42.714351 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2532 13:58:42.717739 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2533 13:58:42.724299 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2534 13:58:42.727651 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2535 13:58:42.731862 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2536 13:58:42.734064 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2537 13:58:42.734487
2538 13:58:42.737591 CA PerBit enable=1, Macro0, CA PI delay=33
2539 13:58:42.738135
2540 13:58:42.741034 [CBTSetCACLKResult] CA Dly = 33
2541 13:58:42.741490 CS Dly: 9 (0~41)
2542 13:58:42.741858
2543 13:58:42.744230 ----->DramcWriteLeveling(PI) begin...
2544 13:58:42.747989 ==
2545 13:58:42.751127 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 13:58:42.753833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 13:58:42.754282 ==
2548 13:58:42.757575 Write leveling (Byte 0): 34 => 34
2549 13:58:42.761043 Write leveling (Byte 1): 29 => 29
2550 13:58:42.764630 DramcWriteLeveling(PI) end<-----
2551 13:58:42.765183
2552 13:58:42.765550 ==
2553 13:58:42.767808 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 13:58:42.771195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 13:58:42.771662 ==
2556 13:58:42.774421 [Gating] SW mode calibration
2557 13:58:42.780939 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2558 13:58:42.787423 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2559 13:58:42.790980 0 15 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2560 13:58:42.794258 0 15 4 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
2561 13:58:42.800709 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 13:58:42.804306 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 13:58:42.807610 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 13:58:42.813653 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 13:58:42.817475 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2566 13:58:42.820657 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2567 13:58:42.827799 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2568 13:58:42.830355 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2569 13:58:42.833581 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 13:58:42.837389 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 13:58:42.843632 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 13:58:42.847241 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 13:58:42.850848 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 13:58:42.857307 1 0 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
2575 13:58:42.860516 1 1 0 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2576 13:58:42.863933 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
2577 13:58:42.870237 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 13:58:42.874313 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 13:58:42.876749 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 13:58:42.884118 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 13:58:42.886800 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 13:58:42.890421 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2583 13:58:42.896956 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2584 13:58:42.900452 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 13:58:42.903523 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 13:58:42.910198 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 13:58:42.913482 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 13:58:42.917125 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 13:58:42.923420 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 13:58:42.926855 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 13:58:42.929791 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 13:58:42.936330 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 13:58:42.939772 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 13:58:42.943264 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 13:58:42.949617 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 13:58:42.953115 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 13:58:42.956431 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2598 13:58:42.962792 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2599 13:58:42.966475 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2600 13:58:42.969688 Total UI for P1: 0, mck2ui 16
2601 13:58:42.972623 best dqsien dly found for B0: ( 1, 3, 26)
2602 13:58:42.976423 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2603 13:58:42.983303 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 13:58:42.984081 Total UI for P1: 0, mck2ui 16
2605 13:58:42.990105 best dqsien dly found for B1: ( 1, 4, 2)
2606 13:58:42.992577 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2607 13:58:42.996281 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2608 13:58:42.996749
2609 13:58:42.999545 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2610 13:58:43.002828 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2611 13:58:43.006163 [Gating] SW calibration Done
2612 13:58:43.006720 ==
2613 13:58:43.009474 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 13:58:43.013109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 13:58:43.013615 ==
2616 13:58:43.015960 RX Vref Scan: 0
2617 13:58:43.016420
2618 13:58:43.016784 RX Vref 0 -> 0, step: 1
2619 13:58:43.017126
2620 13:58:43.018911 RX Delay -40 -> 252, step: 8
2621 13:58:43.023408 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2622 13:58:43.029376 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2623 13:58:43.032571 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2624 13:58:43.035591 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2625 13:58:43.039047 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2626 13:58:43.042626 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2627 13:58:43.048926 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2628 13:58:43.052581 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2629 13:58:43.055799 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2630 13:58:43.059573 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2631 13:58:43.062325 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2632 13:58:43.068818 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2633 13:58:43.072245 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2634 13:58:43.075884 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2635 13:58:43.079355 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2636 13:58:43.082370 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2637 13:58:43.085622 ==
2638 13:58:43.086176 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 13:58:43.091854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 13:58:43.092410 ==
2641 13:58:43.092786 DQS Delay:
2642 13:58:43.095459 DQS0 = 0, DQS1 = 0
2643 13:58:43.095979 DQM Delay:
2644 13:58:43.099051 DQM0 = 119, DQM1 = 107
2645 13:58:43.099611 DQ Delay:
2646 13:58:43.101909 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2647 13:58:43.106442 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2648 13:58:43.108360 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2649 13:58:43.112044 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2650 13:58:43.112603
2651 13:58:43.112976
2652 13:58:43.113316 ==
2653 13:58:43.115513 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 13:58:43.122007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 13:58:43.122570 ==
2656 13:58:43.122944
2657 13:58:43.123286
2658 13:58:43.123612 TX Vref Scan disable
2659 13:58:43.125555 == TX Byte 0 ==
2660 13:58:43.129016 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2661 13:58:43.135885 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2662 13:58:43.136436 == TX Byte 1 ==
2663 13:58:43.138870 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2664 13:58:43.145703 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2665 13:58:43.146251 ==
2666 13:58:43.148346 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 13:58:43.151607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 13:58:43.152123 ==
2669 13:58:43.163461 TX Vref=22, minBit 12, minWin=25, winSum=415
2670 13:58:43.167087 TX Vref=24, minBit 1, minWin=26, winSum=424
2671 13:58:43.170306 TX Vref=26, minBit 1, minWin=26, winSum=430
2672 13:58:43.174161 TX Vref=28, minBit 1, minWin=27, winSum=435
2673 13:58:43.176976 TX Vref=30, minBit 10, minWin=26, winSum=434
2674 13:58:43.183665 TX Vref=32, minBit 4, minWin=26, winSum=429
2675 13:58:43.187461 [TxChooseVref] Worse bit 1, Min win 27, Win sum 435, Final Vref 28
2676 13:58:43.188085
2677 13:58:43.190773 Final TX Range 1 Vref 28
2678 13:58:43.191334
2679 13:58:43.191703 ==
2680 13:58:43.194179 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 13:58:43.196708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 13:58:43.197177 ==
2683 13:58:43.200399
2684 13:58:43.200954
2685 13:58:43.201326 TX Vref Scan disable
2686 13:58:43.203897 == TX Byte 0 ==
2687 13:58:43.207269 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2688 13:58:43.210200 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2689 13:58:43.213273 == TX Byte 1 ==
2690 13:58:43.216720 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2691 13:58:43.220573 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2692 13:58:43.224020
2693 13:58:43.224573 [DATLAT]
2694 13:58:43.224944 Freq=1200, CH0 RK0
2695 13:58:43.225295
2696 13:58:43.226651 DATLAT Default: 0xd
2697 13:58:43.227112 0, 0xFFFF, sum = 0
2698 13:58:43.230062 1, 0xFFFF, sum = 0
2699 13:58:43.230625 2, 0xFFFF, sum = 0
2700 13:58:43.233357 3, 0xFFFF, sum = 0
2701 13:58:43.237410 4, 0xFFFF, sum = 0
2702 13:58:43.237972 5, 0xFFFF, sum = 0
2703 13:58:43.239936 6, 0xFFFF, sum = 0
2704 13:58:43.240506 7, 0xFFFF, sum = 0
2705 13:58:43.243457 8, 0xFFFF, sum = 0
2706 13:58:43.244091 9, 0xFFFF, sum = 0
2707 13:58:43.247218 10, 0xFFFF, sum = 0
2708 13:58:43.247685 11, 0xFFFF, sum = 0
2709 13:58:43.250428 12, 0x0, sum = 1
2710 13:58:43.250992 13, 0x0, sum = 2
2711 13:58:43.253667 14, 0x0, sum = 3
2712 13:58:43.254231 15, 0x0, sum = 4
2713 13:58:43.256323 best_step = 13
2714 13:58:43.256787
2715 13:58:43.257153 ==
2716 13:58:43.260182 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 13:58:43.263109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2718 13:58:43.263668 ==
2719 13:58:43.264080 RX Vref Scan: 1
2720 13:58:43.266416
2721 13:58:43.267006 Set Vref Range= 32 -> 127
2722 13:58:43.267390
2723 13:58:43.269411 RX Vref 32 -> 127, step: 1
2724 13:58:43.269900
2725 13:58:43.273812 RX Delay -21 -> 252, step: 4
2726 13:58:43.274564
2727 13:58:43.276104 Set Vref, RX VrefLevel [Byte0]: 32
2728 13:58:43.279681 [Byte1]: 32
2729 13:58:43.280284
2730 13:58:43.283660 Set Vref, RX VrefLevel [Byte0]: 33
2731 13:58:43.286083 [Byte1]: 33
2732 13:58:43.290144
2733 13:58:43.290719 Set Vref, RX VrefLevel [Byte0]: 34
2734 13:58:43.293434 [Byte1]: 34
2735 13:58:43.297520
2736 13:58:43.297989 Set Vref, RX VrefLevel [Byte0]: 35
2737 13:58:43.300930 [Byte1]: 35
2738 13:58:43.305813
2739 13:58:43.306381 Set Vref, RX VrefLevel [Byte0]: 36
2740 13:58:43.309064 [Byte1]: 36
2741 13:58:43.313998
2742 13:58:43.314614 Set Vref, RX VrefLevel [Byte0]: 37
2743 13:58:43.316891 [Byte1]: 37
2744 13:58:43.321715
2745 13:58:43.322273 Set Vref, RX VrefLevel [Byte0]: 38
2746 13:58:43.324806 [Byte1]: 38
2747 13:58:43.329606
2748 13:58:43.330162 Set Vref, RX VrefLevel [Byte0]: 39
2749 13:58:43.333338 [Byte1]: 39
2750 13:58:43.337537
2751 13:58:43.338088 Set Vref, RX VrefLevel [Byte0]: 40
2752 13:58:43.340630 [Byte1]: 40
2753 13:58:43.345667
2754 13:58:43.346241 Set Vref, RX VrefLevel [Byte0]: 41
2755 13:58:43.349233 [Byte1]: 41
2756 13:58:43.353287
2757 13:58:43.353841 Set Vref, RX VrefLevel [Byte0]: 42
2758 13:58:43.356971 [Byte1]: 42
2759 13:58:43.361597
2760 13:58:43.362150 Set Vref, RX VrefLevel [Byte0]: 43
2761 13:58:43.364874 [Byte1]: 43
2762 13:58:43.369750
2763 13:58:43.370299 Set Vref, RX VrefLevel [Byte0]: 44
2764 13:58:43.373110 [Byte1]: 44
2765 13:58:43.377185
2766 13:58:43.377741 Set Vref, RX VrefLevel [Byte0]: 45
2767 13:58:43.380208 [Byte1]: 45
2768 13:58:43.384996
2769 13:58:43.385626 Set Vref, RX VrefLevel [Byte0]: 46
2770 13:58:43.388469 [Byte1]: 46
2771 13:58:43.393033
2772 13:58:43.393584 Set Vref, RX VrefLevel [Byte0]: 47
2773 13:58:43.396137 [Byte1]: 47
2774 13:58:43.400679
2775 13:58:43.401231 Set Vref, RX VrefLevel [Byte0]: 48
2776 13:58:43.404213 [Byte1]: 48
2777 13:58:43.408728
2778 13:58:43.409195 Set Vref, RX VrefLevel [Byte0]: 49
2779 13:58:43.412493 [Byte1]: 49
2780 13:58:43.416793
2781 13:58:43.417371 Set Vref, RX VrefLevel [Byte0]: 50
2782 13:58:43.419690 [Byte1]: 50
2783 13:58:43.425228
2784 13:58:43.425785 Set Vref, RX VrefLevel [Byte0]: 51
2785 13:58:43.427767 [Byte1]: 51
2786 13:58:43.432914
2787 13:58:43.433464 Set Vref, RX VrefLevel [Byte0]: 52
2788 13:58:43.435662 [Byte1]: 52
2789 13:58:43.440525
2790 13:58:43.441080 Set Vref, RX VrefLevel [Byte0]: 53
2791 13:58:43.444014 [Byte1]: 53
2792 13:58:43.448719
2793 13:58:43.449272 Set Vref, RX VrefLevel [Byte0]: 54
2794 13:58:43.451697 [Byte1]: 54
2795 13:58:43.456428
2796 13:58:43.456979 Set Vref, RX VrefLevel [Byte0]: 55
2797 13:58:43.460456 [Byte1]: 55
2798 13:58:43.464278
2799 13:58:43.464831 Set Vref, RX VrefLevel [Byte0]: 56
2800 13:58:43.467671 [Byte1]: 56
2801 13:58:43.472476
2802 13:58:43.472954 Set Vref, RX VrefLevel [Byte0]: 57
2803 13:58:43.475438 [Byte1]: 57
2804 13:58:43.480668
2805 13:58:43.481218 Set Vref, RX VrefLevel [Byte0]: 58
2806 13:58:43.483541 [Byte1]: 58
2807 13:58:43.487903
2808 13:58:43.488383 Set Vref, RX VrefLevel [Byte0]: 59
2809 13:58:43.491521 [Byte1]: 59
2810 13:58:43.495972
2811 13:58:43.496648 Set Vref, RX VrefLevel [Byte0]: 60
2812 13:58:43.499021 [Byte1]: 60
2813 13:58:43.503872
2814 13:58:43.504333 Set Vref, RX VrefLevel [Byte0]: 61
2815 13:58:43.507288 [Byte1]: 61
2816 13:58:43.512074
2817 13:58:43.512636 Set Vref, RX VrefLevel [Byte0]: 62
2818 13:58:43.515462 [Byte1]: 62
2819 13:58:43.521000
2820 13:58:43.521554 Set Vref, RX VrefLevel [Byte0]: 63
2821 13:58:43.526375 [Byte1]: 63
2822 13:58:43.527041
2823 13:58:43.530179 Set Vref, RX VrefLevel [Byte0]: 64
2824 13:58:43.532657 [Byte1]: 64
2825 13:58:43.533126
2826 13:58:43.536273 Set Vref, RX VrefLevel [Byte0]: 65
2827 13:58:43.540018 [Byte1]: 65
2828 13:58:43.544314
2829 13:58:43.544871 Set Vref, RX VrefLevel [Byte0]: 66
2830 13:58:43.546953 [Byte1]: 66
2831 13:58:43.551488
2832 13:58:43.552085 Set Vref, RX VrefLevel [Byte0]: 67
2833 13:58:43.555075 [Byte1]: 67
2834 13:58:43.559483
2835 13:58:43.560235 Set Vref, RX VrefLevel [Byte0]: 68
2836 13:58:43.563189 [Byte1]: 68
2837 13:58:43.567516
2838 13:58:43.568165 Set Vref, RX VrefLevel [Byte0]: 69
2839 13:58:43.570295 [Byte1]: 69
2840 13:58:43.575142
2841 13:58:43.575692 Set Vref, RX VrefLevel [Byte0]: 70
2842 13:58:43.578841 [Byte1]: 70
2843 13:58:43.583423
2844 13:58:43.584017 Set Vref, RX VrefLevel [Byte0]: 71
2845 13:58:43.587337 [Byte1]: 71
2846 13:58:43.591244
2847 13:58:43.591854 Set Vref, RX VrefLevel [Byte0]: 72
2848 13:58:43.594905 [Byte1]: 72
2849 13:58:43.598830
2850 13:58:43.599293 Set Vref, RX VrefLevel [Byte0]: 73
2851 13:58:43.603670 [Byte1]: 73
2852 13:58:43.607606
2853 13:58:43.608223 Set Vref, RX VrefLevel [Byte0]: 74
2854 13:58:43.610172 [Byte1]: 74
2855 13:58:43.615003
2856 13:58:43.615556 Set Vref, RX VrefLevel [Byte0]: 75
2857 13:58:43.618452 [Byte1]: 75
2858 13:58:43.622799
2859 13:58:43.623280 Set Vref, RX VrefLevel [Byte0]: 76
2860 13:58:43.626133 [Byte1]: 76
2861 13:58:43.630760
2862 13:58:43.631309 Set Vref, RX VrefLevel [Byte0]: 77
2863 13:58:43.633734 [Byte1]: 77
2864 13:58:43.639031
2865 13:58:43.639601 Final RX Vref Byte 0 = 60 to rank0
2866 13:58:43.641876 Final RX Vref Byte 1 = 50 to rank0
2867 13:58:43.645262 Final RX Vref Byte 0 = 60 to rank1
2868 13:58:43.648796 Final RX Vref Byte 1 = 50 to rank1==
2869 13:58:43.652357 Dram Type= 6, Freq= 0, CH_0, rank 0
2870 13:58:43.658969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 13:58:43.659525 ==
2872 13:58:43.659939 DQS Delay:
2873 13:58:43.662102 DQS0 = 0, DQS1 = 0
2874 13:58:43.662680 DQM Delay:
2875 13:58:43.663058 DQM0 = 119, DQM1 = 107
2876 13:58:43.665384 DQ Delay:
2877 13:58:43.668721 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2878 13:58:43.673394 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2879 13:58:43.675432 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100
2880 13:58:43.678967 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2881 13:58:43.679520
2882 13:58:43.679930
2883 13:58:43.688574 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2884 13:58:43.689139 CH0 RK0: MR19=403, MR18=10FC
2885 13:58:43.695472 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2886 13:58:43.696081
2887 13:58:43.698659 ----->DramcWriteLeveling(PI) begin...
2888 13:58:43.699429 ==
2889 13:58:43.702265 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 13:58:43.708199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 13:58:43.708669 ==
2892 13:58:43.711238 Write leveling (Byte 0): 32 => 32
2893 13:58:43.711816 Write leveling (Byte 1): 31 => 31
2894 13:58:43.715248 DramcWriteLeveling(PI) end<-----
2895 13:58:43.715797
2896 13:58:43.716182 ==
2897 13:58:43.717952 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 13:58:43.724614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 13:58:43.725081 ==
2900 13:58:43.727886 [Gating] SW mode calibration
2901 13:58:43.734639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2902 13:58:43.737790 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2903 13:58:43.744666 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
2904 13:58:43.747559 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2905 13:58:43.751657 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 13:58:43.758337 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 13:58:43.761549 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 13:58:43.764931 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 13:58:43.771459 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2910 13:58:43.774778 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2911 13:58:43.778541 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
2912 13:58:43.781663 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 13:58:43.788304 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 13:58:43.791340 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 13:58:43.794781 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 13:58:43.801888 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 13:58:43.804831 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 13:58:43.808113 1 0 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2919 13:58:43.814709 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2920 13:58:43.818556 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 13:58:43.821539 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 13:58:43.827814 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 13:58:43.831338 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 13:58:43.834653 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 13:58:43.840822 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 13:58:43.844217 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2927 13:58:43.847624 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 13:58:43.854130 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 13:58:43.857755 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 13:58:43.861151 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 13:58:43.867642 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 13:58:43.870950 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 13:58:43.874368 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 13:58:43.881101 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 13:58:43.884347 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 13:58:43.887868 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 13:58:43.894331 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 13:58:43.897578 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 13:58:43.900939 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 13:58:43.907474 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 13:58:43.911012 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 13:58:43.914351 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2943 13:58:43.917326 Total UI for P1: 0, mck2ui 16
2944 13:58:43.920488 best dqsien dly found for B0: ( 1, 3, 26)
2945 13:58:43.927482 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 13:58:43.928123 Total UI for P1: 0, mck2ui 16
2947 13:58:43.930664 best dqsien dly found for B1: ( 1, 3, 30)
2948 13:58:43.937477 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2949 13:58:43.940416 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2950 13:58:43.941011
2951 13:58:43.944006 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2952 13:58:43.947056 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2953 13:58:43.950934 [Gating] SW calibration Done
2954 13:58:43.951493 ==
2955 13:58:43.954153 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 13:58:43.957052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 13:58:43.957622 ==
2958 13:58:43.960352 RX Vref Scan: 0
2959 13:58:43.960809
2960 13:58:43.961177 RX Vref 0 -> 0, step: 1
2961 13:58:43.961516
2962 13:58:43.963618 RX Delay -40 -> 252, step: 8
2963 13:58:43.967104 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2964 13:58:43.973319 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2965 13:58:43.976955 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2966 13:58:43.980138 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2967 13:58:43.984019 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2968 13:58:43.986948 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2969 13:58:43.993489 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2970 13:58:43.997047 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2971 13:58:44.000100 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2972 13:58:44.004604 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2973 13:58:44.006832 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2974 13:58:44.013706 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2975 13:58:44.016756 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2976 13:58:44.020008 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2977 13:58:44.023682 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2978 13:58:44.026762 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2979 13:58:44.030420 ==
2980 13:58:44.030983 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 13:58:44.036906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 13:58:44.037456 ==
2983 13:58:44.037832 DQS Delay:
2984 13:58:44.040129 DQS0 = 0, DQS1 = 0
2985 13:58:44.040688 DQM Delay:
2986 13:58:44.043284 DQM0 = 117, DQM1 = 107
2987 13:58:44.043906 DQ Delay:
2988 13:58:44.046860 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2989 13:58:44.050210 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2990 13:58:44.053780 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2991 13:58:44.056887 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2992 13:58:44.057455
2993 13:58:44.057827
2994 13:58:44.058171 ==
2995 13:58:44.060244 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 13:58:44.063531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 13:58:44.066790 ==
2998 13:58:44.067361
2999 13:58:44.067780
3000 13:58:44.068147 TX Vref Scan disable
3001 13:58:44.070817 == TX Byte 0 ==
3002 13:58:44.073231 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3003 13:58:44.076607 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3004 13:58:44.080200 == TX Byte 1 ==
3005 13:58:44.083169 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3006 13:58:44.086480 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3007 13:58:44.090032 ==
3008 13:58:44.093159 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 13:58:44.096084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 13:58:44.096554 ==
3011 13:58:44.107830 TX Vref=22, minBit 0, minWin=26, winSum=419
3012 13:58:44.110903 TX Vref=24, minBit 5, minWin=25, winSum=425
3013 13:58:44.115572 TX Vref=26, minBit 2, minWin=26, winSum=427
3014 13:58:44.118122 TX Vref=28, minBit 1, minWin=26, winSum=433
3015 13:58:44.120715 TX Vref=30, minBit 1, minWin=27, winSum=434
3016 13:58:44.128031 TX Vref=32, minBit 2, minWin=26, winSum=431
3017 13:58:44.131139 [TxChooseVref] Worse bit 1, Min win 27, Win sum 434, Final Vref 30
3018 13:58:44.131696
3019 13:58:44.134495 Final TX Range 1 Vref 30
3020 13:58:44.135057
3021 13:58:44.135423 ==
3022 13:58:44.137381 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 13:58:44.141191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 13:58:44.141810 ==
3025 13:58:44.143769
3026 13:58:44.144232
3027 13:58:44.144598 TX Vref Scan disable
3028 13:58:44.148028 == TX Byte 0 ==
3029 13:58:44.150977 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3030 13:58:44.157624 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3031 13:58:44.158177 == TX Byte 1 ==
3032 13:58:44.161023 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3033 13:58:44.167345 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3034 13:58:44.167959
3035 13:58:44.168335 [DATLAT]
3036 13:58:44.168677 Freq=1200, CH0 RK1
3037 13:58:44.169009
3038 13:58:44.170509 DATLAT Default: 0xd
3039 13:58:44.170969 0, 0xFFFF, sum = 0
3040 13:58:44.173859 1, 0xFFFF, sum = 0
3041 13:58:44.177158 2, 0xFFFF, sum = 0
3042 13:58:44.177685 3, 0xFFFF, sum = 0
3043 13:58:44.181119 4, 0xFFFF, sum = 0
3044 13:58:44.181700 5, 0xFFFF, sum = 0
3045 13:58:44.184435 6, 0xFFFF, sum = 0
3046 13:58:44.185002 7, 0xFFFF, sum = 0
3047 13:58:44.187465 8, 0xFFFF, sum = 0
3048 13:58:44.188149 9, 0xFFFF, sum = 0
3049 13:58:44.190772 10, 0xFFFF, sum = 0
3050 13:58:44.191258 11, 0xFFFF, sum = 0
3051 13:58:44.193708 12, 0x0, sum = 1
3052 13:58:44.194185 13, 0x0, sum = 2
3053 13:58:44.197755 14, 0x0, sum = 3
3054 13:58:44.198336 15, 0x0, sum = 4
3055 13:58:44.200714 best_step = 13
3056 13:58:44.201197
3057 13:58:44.201564 ==
3058 13:58:44.203710 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 13:58:44.206823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 13:58:44.207286 ==
3061 13:58:44.207682 RX Vref Scan: 0
3062 13:58:44.208100
3063 13:58:44.210565 RX Vref 0 -> 0, step: 1
3064 13:58:44.211206
3065 13:58:44.214130 RX Delay -21 -> 252, step: 4
3066 13:58:44.220079 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3067 13:58:44.224127 iDelay=199, Bit 1, Center 120 (47 ~ 194) 148
3068 13:58:44.227628 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3069 13:58:44.230149 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3070 13:58:44.233672 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3071 13:58:44.240526 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3072 13:58:44.243699 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3073 13:58:44.247342 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3074 13:58:44.250148 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3075 13:58:44.252981 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3076 13:58:44.259990 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3077 13:58:44.263514 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3078 13:58:44.266528 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3079 13:58:44.270440 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3080 13:58:44.272903 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3081 13:58:44.280393 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3082 13:58:44.280949 ==
3083 13:58:44.283117 Dram Type= 6, Freq= 0, CH_0, rank 1
3084 13:58:44.286832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 13:58:44.287391 ==
3086 13:58:44.287814 DQS Delay:
3087 13:58:44.289379 DQS0 = 0, DQS1 = 0
3088 13:58:44.289871 DQM Delay:
3089 13:58:44.293086 DQM0 = 116, DQM1 = 107
3090 13:58:44.293644 DQ Delay:
3091 13:58:44.296654 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =114
3092 13:58:44.299315 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3093 13:58:44.302919 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3094 13:58:44.306906 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3095 13:58:44.307370
3096 13:58:44.307778
3097 13:58:44.315835 [DQSOSCAuto] RK1, (LSB)MR18= 0xee9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3098 13:58:44.319291 CH0 RK1: MR19=403, MR18=EE9
3099 13:58:44.325678 CH0_RK1: MR19=0x403, MR18=0xEE9, DQSOSC=404, MR23=63, INC=40, DEC=26
3100 13:58:44.326144 [RxdqsGatingPostProcess] freq 1200
3101 13:58:44.332608 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3102 13:58:44.336023 best DQS0 dly(2T, 0.5T) = (0, 11)
3103 13:58:44.339492 best DQS1 dly(2T, 0.5T) = (0, 12)
3104 13:58:44.342761 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3105 13:58:44.345902 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3106 13:58:44.349345 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 13:58:44.352981 best DQS1 dly(2T, 0.5T) = (0, 11)
3108 13:58:44.356468 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 13:58:44.359502 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3110 13:58:44.362991 Pre-setting of DQS Precalculation
3111 13:58:44.365759 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3112 13:58:44.366318 ==
3113 13:58:44.369259 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 13:58:44.372607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 13:58:44.373073 ==
3116 13:58:44.379126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3117 13:58:44.385400 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3118 13:58:44.393687 [CA 0] Center 37 (7~68) winsize 62
3119 13:58:44.397230 [CA 1] Center 38 (8~68) winsize 61
3120 13:58:44.400724 [CA 2] Center 34 (4~64) winsize 61
3121 13:58:44.403849 [CA 3] Center 33 (3~64) winsize 62
3122 13:58:44.407121 [CA 4] Center 34 (4~64) winsize 61
3123 13:58:44.411040 [CA 5] Center 33 (3~64) winsize 62
3124 13:58:44.411597
3125 13:58:44.413442 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3126 13:58:44.413901
3127 13:58:44.416942 [CATrainingPosCal] consider 1 rank data
3128 13:58:44.420276 u2DelayCellTimex100 = 270/100 ps
3129 13:58:44.423676 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3130 13:58:44.427052 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3131 13:58:44.434024 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 13:58:44.436695 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3133 13:58:44.440806 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 13:58:44.443709 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3135 13:58:44.444338
3136 13:58:44.447416 CA PerBit enable=1, Macro0, CA PI delay=33
3137 13:58:44.448025
3138 13:58:44.450699 [CBTSetCACLKResult] CA Dly = 33
3139 13:58:44.451163 CS Dly: 5 (0~36)
3140 13:58:44.451534 ==
3141 13:58:44.453546 Dram Type= 6, Freq= 0, CH_1, rank 1
3142 13:58:44.460362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 13:58:44.460927 ==
3144 13:58:44.463557 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3145 13:58:44.470601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3146 13:58:44.479457 [CA 0] Center 37 (7~68) winsize 62
3147 13:58:44.482168 [CA 1] Center 38 (8~68) winsize 61
3148 13:58:44.485950 [CA 2] Center 34 (4~65) winsize 62
3149 13:58:44.489075 [CA 3] Center 33 (3~64) winsize 62
3150 13:58:44.492357 [CA 4] Center 34 (4~65) winsize 62
3151 13:58:44.495801 [CA 5] Center 33 (3~64) winsize 62
3152 13:58:44.496421
3153 13:58:44.499230 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3154 13:58:44.499842
3155 13:58:44.502291 [CATrainingPosCal] consider 2 rank data
3156 13:58:44.506526 u2DelayCellTimex100 = 270/100 ps
3157 13:58:44.509240 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3158 13:58:44.515984 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3159 13:58:44.518971 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 13:58:44.522554 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3161 13:58:44.525383 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 13:58:44.529908 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3163 13:58:44.530482
3164 13:58:44.532157 CA PerBit enable=1, Macro0, CA PI delay=33
3165 13:58:44.532617
3166 13:58:44.535644 [CBTSetCACLKResult] CA Dly = 33
3167 13:58:44.536267 CS Dly: 7 (0~40)
3168 13:58:44.538864
3169 13:58:44.542212 ----->DramcWriteLeveling(PI) begin...
3170 13:58:44.542778 ==
3171 13:58:44.546036 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 13:58:44.549059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 13:58:44.549666 ==
3174 13:58:44.552626 Write leveling (Byte 0): 24 => 24
3175 13:58:44.555573 Write leveling (Byte 1): 26 => 26
3176 13:58:44.558597 DramcWriteLeveling(PI) end<-----
3177 13:58:44.559064
3178 13:58:44.559433 ==
3179 13:58:44.562651 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 13:58:44.565881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 13:58:44.566443 ==
3182 13:58:44.569031 [Gating] SW mode calibration
3183 13:58:44.575319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3184 13:58:44.582574 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3185 13:58:44.585445 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3186 13:58:44.588675 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 13:58:44.595303 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 13:58:44.598957 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 13:58:44.602230 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 13:58:44.608475 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 13:58:44.612025 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
3192 13:58:44.615437 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
3193 13:58:44.618906 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 13:58:44.625345 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 13:58:44.628630 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 13:58:44.631592 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 13:58:44.638379 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 13:58:44.641904 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 13:58:44.645558 1 0 24 | B1->B0 | 2a2a 3c3c | 0 0 | (0 0) (0 0)
3200 13:58:44.651962 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3201 13:58:44.655195 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 13:58:44.658759 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 13:58:44.665780 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 13:58:44.668149 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 13:58:44.671800 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 13:58:44.678443 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 13:58:44.682073 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3208 13:58:44.685064 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3209 13:58:44.691808 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 13:58:44.695437 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 13:58:44.698568 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 13:58:44.704881 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 13:58:44.708305 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 13:58:44.712146 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 13:58:44.719089 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 13:58:44.721530 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 13:58:44.724836 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 13:58:44.731883 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 13:58:44.734714 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 13:58:44.738189 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 13:58:44.741722 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 13:58:44.748335 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 13:58:44.751310 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3224 13:58:44.754860 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 13:58:44.761565 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 13:58:44.764582 Total UI for P1: 0, mck2ui 16
3227 13:58:44.767781 best dqsien dly found for B0: ( 1, 3, 26)
3228 13:58:44.771647 Total UI for P1: 0, mck2ui 16
3229 13:58:44.774454 best dqsien dly found for B1: ( 1, 3, 26)
3230 13:58:44.777809 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3231 13:58:44.781628 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3232 13:58:44.782094
3233 13:58:44.784791 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3234 13:58:44.787846 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3235 13:58:44.791501 [Gating] SW calibration Done
3236 13:58:44.792043 ==
3237 13:58:44.794556 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 13:58:44.797857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 13:58:44.798305 ==
3240 13:58:44.801586 RX Vref Scan: 0
3241 13:58:44.802095
3242 13:58:44.802427 RX Vref 0 -> 0, step: 1
3243 13:58:44.804817
3244 13:58:44.805232 RX Delay -40 -> 252, step: 8
3245 13:58:44.811809 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3246 13:58:44.814753 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3247 13:58:44.817936 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3248 13:58:44.820970 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3249 13:58:44.824250 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3250 13:58:44.831205 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3251 13:58:44.834201 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3252 13:58:44.837685 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3253 13:58:44.841160 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3254 13:58:44.844448 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3255 13:58:44.851119 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3256 13:58:44.854320 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3257 13:58:44.857702 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3258 13:58:44.861052 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3259 13:58:44.864607 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3260 13:58:44.870818 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3261 13:58:44.871286 ==
3262 13:58:44.874245 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 13:58:44.877350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 13:58:44.877825 ==
3265 13:58:44.878198 DQS Delay:
3266 13:58:44.881071 DQS0 = 0, DQS1 = 0
3267 13:58:44.881640 DQM Delay:
3268 13:58:44.883978 DQM0 = 117, DQM1 = 108
3269 13:58:44.884444 DQ Delay:
3270 13:58:44.887042 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3271 13:58:44.890583 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3272 13:58:44.894194 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3273 13:58:44.897100 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3274 13:58:44.897672
3275 13:58:44.898048
3276 13:58:44.900496 ==
3277 13:58:44.903674 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 13:58:44.907184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 13:58:44.907823 ==
3280 13:58:44.908303
3281 13:58:44.908664
3282 13:58:44.910257 TX Vref Scan disable
3283 13:58:44.910724 == TX Byte 0 ==
3284 13:58:44.913864 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3285 13:58:44.920447 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3286 13:58:44.921013 == TX Byte 1 ==
3287 13:58:44.927304 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3288 13:58:44.930080 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3289 13:58:44.930552 ==
3290 13:58:44.933548 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 13:58:44.937612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 13:58:44.938193 ==
3293 13:58:44.949674 TX Vref=22, minBit 9, minWin=25, winSum=418
3294 13:58:44.952273 TX Vref=24, minBit 10, minWin=25, winSum=421
3295 13:58:44.955635 TX Vref=26, minBit 9, minWin=25, winSum=427
3296 13:58:44.958893 TX Vref=28, minBit 10, minWin=25, winSum=435
3297 13:58:44.962524 TX Vref=30, minBit 9, minWin=25, winSum=431
3298 13:58:44.969043 TX Vref=32, minBit 9, minWin=25, winSum=426
3299 13:58:44.972094 [TxChooseVref] Worse bit 10, Min win 25, Win sum 435, Final Vref 28
3300 13:58:44.972559
3301 13:58:44.976011 Final TX Range 1 Vref 28
3302 13:58:44.976662
3303 13:58:44.977037 ==
3304 13:58:44.978765 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 13:58:44.983467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 13:58:44.985144 ==
3307 13:58:44.985612
3308 13:58:44.985982
3309 13:58:44.986323 TX Vref Scan disable
3310 13:58:44.988665 == TX Byte 0 ==
3311 13:58:44.992689 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3312 13:58:44.998518 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3313 13:58:44.998983 == TX Byte 1 ==
3314 13:58:45.002156 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3315 13:58:45.008629 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3316 13:58:45.009094
3317 13:58:45.009448 [DATLAT]
3318 13:58:45.009760 Freq=1200, CH1 RK0
3319 13:58:45.010065
3320 13:58:45.011838 DATLAT Default: 0xd
3321 13:58:45.015275 0, 0xFFFF, sum = 0
3322 13:58:45.015896 1, 0xFFFF, sum = 0
3323 13:58:45.018572 2, 0xFFFF, sum = 0
3324 13:58:45.019050 3, 0xFFFF, sum = 0
3325 13:58:45.022050 4, 0xFFFF, sum = 0
3326 13:58:45.022537 5, 0xFFFF, sum = 0
3327 13:58:45.025254 6, 0xFFFF, sum = 0
3328 13:58:45.025768 7, 0xFFFF, sum = 0
3329 13:58:45.028621 8, 0xFFFF, sum = 0
3330 13:58:45.029048 9, 0xFFFF, sum = 0
3331 13:58:45.032283 10, 0xFFFF, sum = 0
3332 13:58:45.032815 11, 0xFFFF, sum = 0
3333 13:58:45.035097 12, 0x0, sum = 1
3334 13:58:45.035548 13, 0x0, sum = 2
3335 13:58:45.039165 14, 0x0, sum = 3
3336 13:58:45.039590 15, 0x0, sum = 4
3337 13:58:45.042021 best_step = 13
3338 13:58:45.042438
3339 13:58:45.042771 ==
3340 13:58:45.045621 Dram Type= 6, Freq= 0, CH_1, rank 0
3341 13:58:45.048552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3342 13:58:45.048977 ==
3343 13:58:45.049315 RX Vref Scan: 1
3344 13:58:45.049694
3345 13:58:45.051708 Set Vref Range= 32 -> 127
3346 13:58:45.052160
3347 13:58:45.055246 RX Vref 32 -> 127, step: 1
3348 13:58:45.055667
3349 13:58:45.059206 RX Delay -21 -> 252, step: 4
3350 13:58:45.059628
3351 13:58:45.062161 Set Vref, RX VrefLevel [Byte0]: 32
3352 13:58:45.065196 [Byte1]: 32
3353 13:58:45.065719
3354 13:58:45.068633 Set Vref, RX VrefLevel [Byte0]: 33
3355 13:58:45.072178 [Byte1]: 33
3356 13:58:45.075255
3357 13:58:45.075796 Set Vref, RX VrefLevel [Byte0]: 34
3358 13:58:45.078640 [Byte1]: 34
3359 13:58:45.083818
3360 13:58:45.084339 Set Vref, RX VrefLevel [Byte0]: 35
3361 13:58:45.086741 [Byte1]: 35
3362 13:58:45.091346
3363 13:58:45.091937 Set Vref, RX VrefLevel [Byte0]: 36
3364 13:58:45.094758 [Byte1]: 36
3365 13:58:45.099310
3366 13:58:45.099880 Set Vref, RX VrefLevel [Byte0]: 37
3367 13:58:45.102295 [Byte1]: 37
3368 13:58:45.107173
3369 13:58:45.107693 Set Vref, RX VrefLevel [Byte0]: 38
3370 13:58:45.110377 [Byte1]: 38
3371 13:58:45.115337
3372 13:58:45.115904 Set Vref, RX VrefLevel [Byte0]: 39
3373 13:58:45.118563 [Byte1]: 39
3374 13:58:45.122810
3375 13:58:45.123292 Set Vref, RX VrefLevel [Byte0]: 40
3376 13:58:45.125928 [Byte1]: 40
3377 13:58:45.130746
3378 13:58:45.131262 Set Vref, RX VrefLevel [Byte0]: 41
3379 13:58:45.134255 [Byte1]: 41
3380 13:58:45.138937
3381 13:58:45.139377 Set Vref, RX VrefLevel [Byte0]: 42
3382 13:58:45.142651 [Byte1]: 42
3383 13:58:45.146565
3384 13:58:45.147120 Set Vref, RX VrefLevel [Byte0]: 43
3385 13:58:45.150311 [Byte1]: 43
3386 13:58:45.154703
3387 13:58:45.155349 Set Vref, RX VrefLevel [Byte0]: 44
3388 13:58:45.158464 [Byte1]: 44
3389 13:58:45.162826
3390 13:58:45.163430 Set Vref, RX VrefLevel [Byte0]: 45
3391 13:58:45.166047 [Byte1]: 45
3392 13:58:45.170428
3393 13:58:45.170979 Set Vref, RX VrefLevel [Byte0]: 46
3394 13:58:45.174425 [Byte1]: 46
3395 13:58:45.178342
3396 13:58:45.178800 Set Vref, RX VrefLevel [Byte0]: 47
3397 13:58:45.181796 [Byte1]: 47
3398 13:58:45.186774
3399 13:58:45.187358 Set Vref, RX VrefLevel [Byte0]: 48
3400 13:58:45.189524 [Byte1]: 48
3401 13:58:45.194317
3402 13:58:45.194874 Set Vref, RX VrefLevel [Byte0]: 49
3403 13:58:45.197454 [Byte1]: 49
3404 13:58:45.202352
3405 13:58:45.202909 Set Vref, RX VrefLevel [Byte0]: 50
3406 13:58:45.205631 [Byte1]: 50
3407 13:58:45.210078
3408 13:58:45.210632 Set Vref, RX VrefLevel [Byte0]: 51
3409 13:58:45.213390 [Byte1]: 51
3410 13:58:45.218384
3411 13:58:45.218938 Set Vref, RX VrefLevel [Byte0]: 52
3412 13:58:45.221073 [Byte1]: 52
3413 13:58:45.226118
3414 13:58:45.226749 Set Vref, RX VrefLevel [Byte0]: 53
3415 13:58:45.228887 [Byte1]: 53
3416 13:58:45.233917
3417 13:58:45.234530 Set Vref, RX VrefLevel [Byte0]: 54
3418 13:58:45.236801 [Byte1]: 54
3419 13:58:45.241665
3420 13:58:45.242232 Set Vref, RX VrefLevel [Byte0]: 55
3421 13:58:45.244745 [Byte1]: 55
3422 13:58:45.249199
3423 13:58:45.249666 Set Vref, RX VrefLevel [Byte0]: 56
3424 13:58:45.252583 [Byte1]: 56
3425 13:58:45.257541
3426 13:58:45.258120 Set Vref, RX VrefLevel [Byte0]: 57
3427 13:58:45.260622 [Byte1]: 57
3428 13:58:45.265175
3429 13:58:45.265641 Set Vref, RX VrefLevel [Byte0]: 58
3430 13:58:45.269317 [Byte1]: 58
3431 13:58:45.273006
3432 13:58:45.273477 Set Vref, RX VrefLevel [Byte0]: 59
3433 13:58:45.276392 [Byte1]: 59
3434 13:58:45.281612
3435 13:58:45.282178 Set Vref, RX VrefLevel [Byte0]: 60
3436 13:58:45.284612 [Byte1]: 60
3437 13:58:45.289175
3438 13:58:45.289741 Set Vref, RX VrefLevel [Byte0]: 61
3439 13:58:45.292596 [Byte1]: 61
3440 13:58:45.296925
3441 13:58:45.297682 Set Vref, RX VrefLevel [Byte0]: 62
3442 13:58:45.300741 [Byte1]: 62
3443 13:58:45.305339
3444 13:58:45.305905 Set Vref, RX VrefLevel [Byte0]: 63
3445 13:58:45.308115 [Byte1]: 63
3446 13:58:45.312899
3447 13:58:45.313471 Set Vref, RX VrefLevel [Byte0]: 64
3448 13:58:45.316322 [Byte1]: 64
3449 13:58:45.320724
3450 13:58:45.321292 Set Vref, RX VrefLevel [Byte0]: 65
3451 13:58:45.324213 [Byte1]: 65
3452 13:58:45.329020
3453 13:58:45.329482 Set Vref, RX VrefLevel [Byte0]: 66
3454 13:58:45.331810 [Byte1]: 66
3455 13:58:45.336691
3456 13:58:45.337159 Set Vref, RX VrefLevel [Byte0]: 67
3457 13:58:45.343084 [Byte1]: 67
3458 13:58:45.343588
3459 13:58:45.346918 Set Vref, RX VrefLevel [Byte0]: 68
3460 13:58:45.349356 [Byte1]: 68
3461 13:58:45.349779
3462 13:58:45.352739 Final RX Vref Byte 0 = 47 to rank0
3463 13:58:45.356406 Final RX Vref Byte 1 = 60 to rank0
3464 13:58:45.359277 Final RX Vref Byte 0 = 47 to rank1
3465 13:58:45.362366 Final RX Vref Byte 1 = 60 to rank1==
3466 13:58:45.365982 Dram Type= 6, Freq= 0, CH_1, rank 0
3467 13:58:45.368963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 13:58:45.372277 ==
3469 13:58:45.372460 DQS Delay:
3470 13:58:45.372606 DQS0 = 0, DQS1 = 0
3471 13:58:45.375649 DQM Delay:
3472 13:58:45.375820 DQM0 = 116, DQM1 = 112
3473 13:58:45.378781 DQ Delay:
3474 13:58:45.382203 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3475 13:58:45.385476 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =114
3476 13:58:45.388799 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =100
3477 13:58:45.392333 DQ12 =118, DQ13 =120, DQ14 =122, DQ15 =120
3478 13:58:45.392438
3479 13:58:45.392520
3480 13:58:45.399199 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3481 13:58:45.402286 CH1 RK0: MR19=403, MR18=5F8
3482 13:58:45.408518 CH1_RK0: MR19=0x403, MR18=0x5F8, DQSOSC=408, MR23=63, INC=39, DEC=26
3483 13:58:45.408701
3484 13:58:45.412195 ----->DramcWriteLeveling(PI) begin...
3485 13:58:45.412358 ==
3486 13:58:45.415645 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 13:58:45.419288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 13:58:45.422005 ==
3489 13:58:45.422194 Write leveling (Byte 0): 25 => 25
3490 13:58:45.425523 Write leveling (Byte 1): 29 => 29
3491 13:58:45.428508 DramcWriteLeveling(PI) end<-----
3492 13:58:45.428718
3493 13:58:45.428836 ==
3494 13:58:45.432145 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 13:58:45.438536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 13:58:45.438774 ==
3497 13:58:45.438913 [Gating] SW mode calibration
3498 13:58:45.448193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3499 13:58:45.452143 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3500 13:58:45.459319 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3501 13:58:45.462044 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 13:58:45.465663 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 13:58:45.471840 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 13:58:45.475703 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 13:58:45.478489 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 13:58:45.485139 0 15 24 | B1->B0 | 2f2f 3434 | 0 1 | (1 0) (1 0)
3507 13:58:45.489046 0 15 28 | B1->B0 | 2424 2828 | 0 0 | (1 0) (0 1)
3508 13:58:45.491888 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 13:58:45.495257 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 13:58:45.501700 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 13:58:45.505256 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 13:58:45.511624 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 13:58:45.514922 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3514 13:58:45.518013 1 0 24 | B1->B0 | 3838 2424 | 1 0 | (0 0) (0 0)
3515 13:58:45.521388 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3516 13:58:45.528286 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 13:58:45.531213 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 13:58:45.534567 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 13:58:45.541573 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 13:58:45.544464 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 13:58:45.548172 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 13:58:45.555075 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3523 13:58:45.558557 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3524 13:58:45.561475 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 13:58:45.567800 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 13:58:45.570649 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 13:58:45.574618 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 13:58:45.580718 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 13:58:45.584756 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 13:58:45.588046 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 13:58:45.594526 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 13:58:45.597690 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 13:58:45.601147 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 13:58:45.607686 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 13:58:45.611677 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 13:58:45.613685 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 13:58:45.620325 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3538 13:58:45.624017 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3539 13:58:45.627266 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3540 13:58:45.630304 Total UI for P1: 0, mck2ui 16
3541 13:58:45.633511 best dqsien dly found for B1: ( 1, 3, 22)
3542 13:58:45.640620 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 13:58:45.643900 Total UI for P1: 0, mck2ui 16
3544 13:58:45.647633 best dqsien dly found for B0: ( 1, 3, 26)
3545 13:58:45.650269 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3546 13:58:45.653817 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3547 13:58:45.654387
3548 13:58:45.657117 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3549 13:58:45.660286 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3550 13:58:45.664457 [Gating] SW calibration Done
3551 13:58:45.665026 ==
3552 13:58:45.666828 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 13:58:45.670252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 13:58:45.670726 ==
3555 13:58:45.673523 RX Vref Scan: 0
3556 13:58:45.674092
3557 13:58:45.674463 RX Vref 0 -> 0, step: 1
3558 13:58:45.676675
3559 13:58:45.677143 RX Delay -40 -> 252, step: 8
3560 13:58:45.684426 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3561 13:58:45.686602 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3562 13:58:45.690690 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3563 13:58:45.693394 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3564 13:58:45.696729 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3565 13:58:45.703560 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3566 13:58:45.706706 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3567 13:58:45.710252 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3568 13:58:45.712932 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3569 13:58:45.717435 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3570 13:58:45.722810 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3571 13:58:45.726225 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3572 13:58:45.729333 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3573 13:58:45.732690 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3574 13:58:45.736062 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3575 13:58:45.742835 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3576 13:58:45.743418 ==
3577 13:58:45.746212 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 13:58:45.748929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 13:58:45.749400 ==
3580 13:58:45.749846 DQS Delay:
3581 13:58:45.752397 DQS0 = 0, DQS1 = 0
3582 13:58:45.753040 DQM Delay:
3583 13:58:45.755910 DQM0 = 116, DQM1 = 110
3584 13:58:45.756498 DQ Delay:
3585 13:58:45.759229 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3586 13:58:45.762927 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3587 13:58:45.765803 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3588 13:58:45.769194 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3589 13:58:45.772227
3590 13:58:45.772790
3591 13:58:45.773161 ==
3592 13:58:45.775716 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 13:58:45.779159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 13:58:45.779627 ==
3595 13:58:45.780043
3596 13:58:45.780390
3597 13:58:45.782600 TX Vref Scan disable
3598 13:58:45.783066 == TX Byte 0 ==
3599 13:58:45.788853 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3600 13:58:45.792258 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3601 13:58:45.792731 == TX Byte 1 ==
3602 13:58:45.799089 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3603 13:58:45.802078 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3604 13:58:45.802551 ==
3605 13:58:45.805330 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 13:58:45.808311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 13:58:45.808741 ==
3608 13:58:45.821754 TX Vref=22, minBit 8, minWin=25, winSum=425
3609 13:58:45.824333 TX Vref=24, minBit 8, minWin=25, winSum=426
3610 13:58:45.828086 TX Vref=26, minBit 8, minWin=25, winSum=431
3611 13:58:45.831414 TX Vref=28, minBit 8, minWin=25, winSum=431
3612 13:58:45.835094 TX Vref=30, minBit 8, minWin=26, winSum=432
3613 13:58:45.841516 TX Vref=32, minBit 9, minWin=25, winSum=429
3614 13:58:45.844505 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
3615 13:58:45.844961
3616 13:58:45.847771 Final TX Range 1 Vref 30
3617 13:58:45.848208
3618 13:58:45.848544 ==
3619 13:58:45.851524 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 13:58:45.854516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 13:58:45.855046 ==
3622 13:58:45.858163
3623 13:58:45.858688
3624 13:58:45.859049 TX Vref Scan disable
3625 13:58:45.861425 == TX Byte 0 ==
3626 13:58:45.864450 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3627 13:58:45.870756 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3628 13:58:45.871270 == TX Byte 1 ==
3629 13:58:45.873943 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3630 13:58:45.880986 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3631 13:58:45.881659
3632 13:58:45.882107 [DATLAT]
3633 13:58:45.882437 Freq=1200, CH1 RK1
3634 13:58:45.882751
3635 13:58:45.883919 DATLAT Default: 0xd
3636 13:58:45.887842 0, 0xFFFF, sum = 0
3637 13:58:45.888378 1, 0xFFFF, sum = 0
3638 13:58:45.890732 2, 0xFFFF, sum = 0
3639 13:58:45.891163 3, 0xFFFF, sum = 0
3640 13:58:45.894201 4, 0xFFFF, sum = 0
3641 13:58:45.894756 5, 0xFFFF, sum = 0
3642 13:58:45.897394 6, 0xFFFF, sum = 0
3643 13:58:45.897926 7, 0xFFFF, sum = 0
3644 13:58:45.900589 8, 0xFFFF, sum = 0
3645 13:58:45.901022 9, 0xFFFF, sum = 0
3646 13:58:45.904290 10, 0xFFFF, sum = 0
3647 13:58:45.904721 11, 0xFFFF, sum = 0
3648 13:58:45.907657 12, 0x0, sum = 1
3649 13:58:45.908239 13, 0x0, sum = 2
3650 13:58:45.910361 14, 0x0, sum = 3
3651 13:58:45.910791 15, 0x0, sum = 4
3652 13:58:45.914107 best_step = 13
3653 13:58:45.914637
3654 13:58:45.914981 ==
3655 13:58:45.917376 Dram Type= 6, Freq= 0, CH_1, rank 1
3656 13:58:45.921068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3657 13:58:45.921594 ==
3658 13:58:45.923623 RX Vref Scan: 0
3659 13:58:45.924090
3660 13:58:45.924435 RX Vref 0 -> 0, step: 1
3661 13:58:45.924751
3662 13:58:45.927084 RX Delay -21 -> 252, step: 4
3663 13:58:45.934013 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3664 13:58:45.937342 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3665 13:58:45.940545 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3666 13:58:45.943505 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3667 13:58:45.946804 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3668 13:58:45.953915 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3669 13:58:45.956713 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3670 13:58:45.960185 iDelay=199, Bit 7, Center 114 (51 ~ 178) 128
3671 13:58:45.963186 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3672 13:58:45.966994 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3673 13:58:45.973415 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3674 13:58:45.976315 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3675 13:58:45.979787 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3676 13:58:45.982829 iDelay=199, Bit 13, Center 118 (55 ~ 182) 128
3677 13:58:45.990043 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3678 13:58:45.993956 iDelay=199, Bit 15, Center 122 (55 ~ 190) 136
3679 13:58:45.994509 ==
3680 13:58:45.996111 Dram Type= 6, Freq= 0, CH_1, rank 1
3681 13:58:45.999785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3682 13:58:46.000396 ==
3683 13:58:46.003188 DQS Delay:
3684 13:58:46.003649 DQS0 = 0, DQS1 = 0
3685 13:58:46.004075 DQM Delay:
3686 13:58:46.006593 DQM0 = 116, DQM1 = 111
3687 13:58:46.007164 DQ Delay:
3688 13:58:46.009972 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3689 13:58:46.013100 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =114
3690 13:58:46.016000 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =102
3691 13:58:46.022894 DQ12 =120, DQ13 =118, DQ14 =120, DQ15 =122
3692 13:58:46.023452
3693 13:58:46.023878
3694 13:58:46.029805 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7f2, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
3695 13:58:46.032785 CH1 RK1: MR19=303, MR18=F7F2
3696 13:58:46.039504 CH1_RK1: MR19=0x303, MR18=0xF7F2, DQSOSC=413, MR23=63, INC=38, DEC=25
3697 13:58:46.042817 [RxdqsGatingPostProcess] freq 1200
3698 13:58:46.045995 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3699 13:58:46.049209 best DQS0 dly(2T, 0.5T) = (0, 11)
3700 13:58:46.052385 best DQS1 dly(2T, 0.5T) = (0, 11)
3701 13:58:46.056115 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3702 13:58:46.060361 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3703 13:58:46.062006 best DQS0 dly(2T, 0.5T) = (0, 11)
3704 13:58:46.065550 best DQS1 dly(2T, 0.5T) = (0, 11)
3705 13:58:46.068753 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3706 13:58:46.071976 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3707 13:58:46.075436 Pre-setting of DQS Precalculation
3708 13:58:46.082619 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3709 13:58:46.088983 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3710 13:58:46.095664 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3711 13:58:46.096261
3712 13:58:46.096630
3713 13:58:46.098580 [Calibration Summary] 2400 Mbps
3714 13:58:46.099040 CH 0, Rank 0
3715 13:58:46.102261 SW Impedance : PASS
3716 13:58:46.105702 DUTY Scan : NO K
3717 13:58:46.106263 ZQ Calibration : PASS
3718 13:58:46.108723 Jitter Meter : NO K
3719 13:58:46.109188 CBT Training : PASS
3720 13:58:46.111666 Write leveling : PASS
3721 13:58:46.115191 RX DQS gating : PASS
3722 13:58:46.115714 RX DQ/DQS(RDDQC) : PASS
3723 13:58:46.119171 TX DQ/DQS : PASS
3724 13:58:46.121879 RX DATLAT : PASS
3725 13:58:46.122344 RX DQ/DQS(Engine): PASS
3726 13:58:46.125518 TX OE : NO K
3727 13:58:46.125978 All Pass.
3728 13:58:46.126339
3729 13:58:46.128389 CH 0, Rank 1
3730 13:58:46.128847 SW Impedance : PASS
3731 13:58:46.131803 DUTY Scan : NO K
3732 13:58:46.135372 ZQ Calibration : PASS
3733 13:58:46.135980 Jitter Meter : NO K
3734 13:58:46.139057 CBT Training : PASS
3735 13:58:46.141399 Write leveling : PASS
3736 13:58:46.141859 RX DQS gating : PASS
3737 13:58:46.145635 RX DQ/DQS(RDDQC) : PASS
3738 13:58:46.148027 TX DQ/DQS : PASS
3739 13:58:46.148514 RX DATLAT : PASS
3740 13:58:46.151829 RX DQ/DQS(Engine): PASS
3741 13:58:46.155175 TX OE : NO K
3742 13:58:46.155780 All Pass.
3743 13:58:46.156164
3744 13:58:46.156501 CH 1, Rank 0
3745 13:58:46.158743 SW Impedance : PASS
3746 13:58:46.161405 DUTY Scan : NO K
3747 13:58:46.161869 ZQ Calibration : PASS
3748 13:58:46.165050 Jitter Meter : NO K
3749 13:58:46.167959 CBT Training : PASS
3750 13:58:46.168520 Write leveling : PASS
3751 13:58:46.171658 RX DQS gating : PASS
3752 13:58:46.174783 RX DQ/DQS(RDDQC) : PASS
3753 13:58:46.175345 TX DQ/DQS : PASS
3754 13:58:46.177698 RX DATLAT : PASS
3755 13:58:46.178161 RX DQ/DQS(Engine): PASS
3756 13:58:46.181571 TX OE : NO K
3757 13:58:46.182137 All Pass.
3758 13:58:46.182509
3759 13:58:46.184876 CH 1, Rank 1
3760 13:58:46.187858 SW Impedance : PASS
3761 13:58:46.188415 DUTY Scan : NO K
3762 13:58:46.191075 ZQ Calibration : PASS
3763 13:58:46.191628 Jitter Meter : NO K
3764 13:58:46.194343 CBT Training : PASS
3765 13:58:46.197823 Write leveling : PASS
3766 13:58:46.198386 RX DQS gating : PASS
3767 13:58:46.200899 RX DQ/DQS(RDDQC) : PASS
3768 13:58:46.204689 TX DQ/DQS : PASS
3769 13:58:46.205152 RX DATLAT : PASS
3770 13:58:46.207512 RX DQ/DQS(Engine): PASS
3771 13:58:46.211064 TX OE : NO K
3772 13:58:46.211619 All Pass.
3773 13:58:46.212049
3774 13:58:46.214423 DramC Write-DBI off
3775 13:58:46.214978 PER_BANK_REFRESH: Hybrid Mode
3776 13:58:46.217676 TX_TRACKING: ON
3777 13:58:46.227407 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3778 13:58:46.230338 [FAST_K] Save calibration result to emmc
3779 13:58:46.233635 dramc_set_vcore_voltage set vcore to 650000
3780 13:58:46.234096 Read voltage for 600, 5
3781 13:58:46.237055 Vio18 = 0
3782 13:58:46.237512 Vcore = 650000
3783 13:58:46.237879 Vdram = 0
3784 13:58:46.240538 Vddq = 0
3785 13:58:46.241075 Vmddr = 0
3786 13:58:46.247165 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3787 13:58:46.250910 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3788 13:58:46.253447 MEM_TYPE=3, freq_sel=19
3789 13:58:46.257568 sv_algorithm_assistance_LP4_1600
3790 13:58:46.260745 ============ PULL DRAM RESETB DOWN ============
3791 13:58:46.263675 ========== PULL DRAM RESETB DOWN end =========
3792 13:58:46.270195 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3793 13:58:46.273483 ===================================
3794 13:58:46.274040 LPDDR4 DRAM CONFIGURATION
3795 13:58:46.276814 ===================================
3796 13:58:46.280453 EX_ROW_EN[0] = 0x0
3797 13:58:46.283671 EX_ROW_EN[1] = 0x0
3798 13:58:46.284273 LP4Y_EN = 0x0
3799 13:58:46.286891 WORK_FSP = 0x0
3800 13:58:46.287350 WL = 0x2
3801 13:58:46.290374 RL = 0x2
3802 13:58:46.290932 BL = 0x2
3803 13:58:46.293605 RPST = 0x0
3804 13:58:46.294172 RD_PRE = 0x0
3805 13:58:46.296419 WR_PRE = 0x1
3806 13:58:46.296980 WR_PST = 0x0
3807 13:58:46.300322 DBI_WR = 0x0
3808 13:58:46.300877 DBI_RD = 0x0
3809 13:58:46.302915 OTF = 0x1
3810 13:58:46.306695 ===================================
3811 13:58:46.309991 ===================================
3812 13:58:46.310553 ANA top config
3813 13:58:46.313023 ===================================
3814 13:58:46.316308 DLL_ASYNC_EN = 0
3815 13:58:46.320198 ALL_SLAVE_EN = 1
3816 13:58:46.323554 NEW_RANK_MODE = 1
3817 13:58:46.324173 DLL_IDLE_MODE = 1
3818 13:58:46.326717 LP45_APHY_COMB_EN = 1
3819 13:58:46.329608 TX_ODT_DIS = 1
3820 13:58:46.332938 NEW_8X_MODE = 1
3821 13:58:46.335963 ===================================
3822 13:58:46.339631 ===================================
3823 13:58:46.342672 data_rate = 1200
3824 13:58:46.343147 CKR = 1
3825 13:58:46.345970 DQ_P2S_RATIO = 8
3826 13:58:46.349758 ===================================
3827 13:58:46.352614 CA_P2S_RATIO = 8
3828 13:58:46.355628 DQ_CA_OPEN = 0
3829 13:58:46.359412 DQ_SEMI_OPEN = 0
3830 13:58:46.362611 CA_SEMI_OPEN = 0
3831 13:58:46.363168 CA_FULL_RATE = 0
3832 13:58:46.366588 DQ_CKDIV4_EN = 1
3833 13:58:46.369082 CA_CKDIV4_EN = 1
3834 13:58:46.372342 CA_PREDIV_EN = 0
3835 13:58:46.375427 PH8_DLY = 0
3836 13:58:46.378643 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3837 13:58:46.382690 DQ_AAMCK_DIV = 4
3838 13:58:46.383247 CA_AAMCK_DIV = 4
3839 13:58:46.386075 CA_ADMCK_DIV = 4
3840 13:58:46.388445 DQ_TRACK_CA_EN = 0
3841 13:58:46.392295 CA_PICK = 600
3842 13:58:46.395623 CA_MCKIO = 600
3843 13:58:46.398677 MCKIO_SEMI = 0
3844 13:58:46.402105 PLL_FREQ = 2288
3845 13:58:46.402574 DQ_UI_PI_RATIO = 32
3846 13:58:46.405265 CA_UI_PI_RATIO = 0
3847 13:58:46.408408 ===================================
3848 13:58:46.411690 ===================================
3849 13:58:46.415482 memory_type:LPDDR4
3850 13:58:46.418686 GP_NUM : 10
3851 13:58:46.419168 SRAM_EN : 1
3852 13:58:46.421819 MD32_EN : 0
3853 13:58:46.424974 ===================================
3854 13:58:46.428183 [ANA_INIT] >>>>>>>>>>>>>>
3855 13:58:46.428645 <<<<<< [CONFIGURE PHASE]: ANA_TX
3856 13:58:46.432270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3857 13:58:46.434828 ===================================
3858 13:58:46.438487 data_rate = 1200,PCW = 0X5800
3859 13:58:46.441519 ===================================
3860 13:58:46.446297 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3861 13:58:46.451430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3862 13:58:46.457956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 13:58:46.461518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3864 13:58:46.464677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3865 13:58:46.467711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3866 13:58:46.471619 [ANA_INIT] flow start
3867 13:58:46.472246 [ANA_INIT] PLL >>>>>>>>
3868 13:58:46.474755 [ANA_INIT] PLL <<<<<<<<
3869 13:58:46.478057 [ANA_INIT] MIDPI >>>>>>>>
3870 13:58:46.481535 [ANA_INIT] MIDPI <<<<<<<<
3871 13:58:46.482002 [ANA_INIT] DLL >>>>>>>>
3872 13:58:46.484417 [ANA_INIT] flow end
3873 13:58:46.488220 ============ LP4 DIFF to SE enter ============
3874 13:58:46.491665 ============ LP4 DIFF to SE exit ============
3875 13:58:46.494430 [ANA_INIT] <<<<<<<<<<<<<
3876 13:58:46.497635 [Flow] Enable top DCM control >>>>>
3877 13:58:46.501030 [Flow] Enable top DCM control <<<<<
3878 13:58:46.504287 Enable DLL master slave shuffle
3879 13:58:46.511370 ==============================================================
3880 13:58:46.512138 Gating Mode config
3881 13:58:46.517615 ==============================================================
3882 13:58:46.518188 Config description:
3883 13:58:46.527831 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3884 13:58:46.533604 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3885 13:58:46.540395 SELPH_MODE 0: By rank 1: By Phase
3886 13:58:46.544373 ==============================================================
3887 13:58:46.546989 GAT_TRACK_EN = 1
3888 13:58:46.551090 RX_GATING_MODE = 2
3889 13:58:46.553991 RX_GATING_TRACK_MODE = 2
3890 13:58:46.556739 SELPH_MODE = 1
3891 13:58:46.560121 PICG_EARLY_EN = 1
3892 13:58:46.563336 VALID_LAT_VALUE = 1
3893 13:58:46.570584 ==============================================================
3894 13:58:46.573877 Enter into Gating configuration >>>>
3895 13:58:46.577297 Exit from Gating configuration <<<<
3896 13:58:46.579988 Enter into DVFS_PRE_config >>>>>
3897 13:58:46.590386 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3898 13:58:46.593293 Exit from DVFS_PRE_config <<<<<
3899 13:58:46.596451 Enter into PICG configuration >>>>
3900 13:58:46.600661 Exit from PICG configuration <<<<
3901 13:58:46.603641 [RX_INPUT] configuration >>>>>
3902 13:58:46.604251 [RX_INPUT] configuration <<<<<
3903 13:58:46.610156 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3904 13:58:46.617097 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3905 13:58:46.623089 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 13:58:46.626226 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 13:58:46.632562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 13:58:46.639520 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 13:58:46.642455 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3910 13:58:46.649796 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3911 13:58:46.652684 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3912 13:58:46.656259 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3913 13:58:46.659642 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3914 13:58:46.666346 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3915 13:58:46.669052 ===================================
3916 13:58:46.669613 LPDDR4 DRAM CONFIGURATION
3917 13:58:46.672388 ===================================
3918 13:58:46.676157 EX_ROW_EN[0] = 0x0
3919 13:58:46.679615 EX_ROW_EN[1] = 0x0
3920 13:58:46.680436 LP4Y_EN = 0x0
3921 13:58:46.682294 WORK_FSP = 0x0
3922 13:58:46.682852 WL = 0x2
3923 13:58:46.685486 RL = 0x2
3924 13:58:46.686045 BL = 0x2
3925 13:58:46.689527 RPST = 0x0
3926 13:58:46.690089 RD_PRE = 0x0
3927 13:58:46.692262 WR_PRE = 0x1
3928 13:58:46.692729 WR_PST = 0x0
3929 13:58:46.696447 DBI_WR = 0x0
3930 13:58:46.697113 DBI_RD = 0x0
3931 13:58:46.698697 OTF = 0x1
3932 13:58:46.702316 ===================================
3933 13:58:46.704990 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3934 13:58:46.708336 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3935 13:58:46.715453 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3936 13:58:46.718538 ===================================
3937 13:58:46.719096 LPDDR4 DRAM CONFIGURATION
3938 13:58:46.722114 ===================================
3939 13:58:46.725744 EX_ROW_EN[0] = 0x10
3940 13:58:46.727965 EX_ROW_EN[1] = 0x0
3941 13:58:46.728431 LP4Y_EN = 0x0
3942 13:58:46.731484 WORK_FSP = 0x0
3943 13:58:46.731986 WL = 0x2
3944 13:58:46.735481 RL = 0x2
3945 13:58:46.736154 BL = 0x2
3946 13:58:46.738438 RPST = 0x0
3947 13:58:46.738906 RD_PRE = 0x0
3948 13:58:46.741641 WR_PRE = 0x1
3949 13:58:46.742266 WR_PST = 0x0
3950 13:58:46.744870 DBI_WR = 0x0
3951 13:58:46.745439 DBI_RD = 0x0
3952 13:58:46.748316 OTF = 0x1
3953 13:58:46.751344 ===================================
3954 13:58:46.758945 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3955 13:58:46.761442 nWR fixed to 30
3956 13:58:46.764814 [ModeRegInit_LP4] CH0 RK0
3957 13:58:46.765383 [ModeRegInit_LP4] CH0 RK1
3958 13:58:46.768042 [ModeRegInit_LP4] CH1 RK0
3959 13:58:46.771342 [ModeRegInit_LP4] CH1 RK1
3960 13:58:46.771978 match AC timing 17
3961 13:58:46.777762 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3962 13:58:46.781072 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3963 13:58:46.784307 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3964 13:58:46.791413 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3965 13:58:46.794661 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3966 13:58:46.795231 ==
3967 13:58:46.797646 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 13:58:46.800900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 13:58:46.801472 ==
3970 13:58:46.807460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3971 13:58:46.813860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3972 13:58:46.817194 [CA 0] Center 36 (6~66) winsize 61
3973 13:58:46.820564 [CA 1] Center 36 (6~66) winsize 61
3974 13:58:46.824057 [CA 2] Center 34 (4~65) winsize 62
3975 13:58:46.827100 [CA 3] Center 34 (4~65) winsize 62
3976 13:58:46.830483 [CA 4] Center 33 (3~64) winsize 62
3977 13:58:46.833912 [CA 5] Center 33 (2~64) winsize 63
3978 13:58:46.834333
3979 13:58:46.837296 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3980 13:58:46.837718
3981 13:58:46.840907 [CATrainingPosCal] consider 1 rank data
3982 13:58:46.843827 u2DelayCellTimex100 = 270/100 ps
3983 13:58:46.847256 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3984 13:58:46.850894 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3985 13:58:46.853911 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3986 13:58:46.856808 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3987 13:58:46.863699 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3988 13:58:46.867015 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3989 13:58:46.867581
3990 13:58:46.870855 CA PerBit enable=1, Macro0, CA PI delay=33
3991 13:58:46.871421
3992 13:58:46.873707 [CBTSetCACLKResult] CA Dly = 33
3993 13:58:46.874266 CS Dly: 4 (0~35)
3994 13:58:46.874641 ==
3995 13:58:46.876988 Dram Type= 6, Freq= 0, CH_0, rank 1
3996 13:58:46.884303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 13:58:46.884869 ==
3998 13:58:46.887052 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3999 13:58:46.893731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4000 13:58:46.897094 [CA 0] Center 36 (6~66) winsize 61
4001 13:58:46.900009 [CA 1] Center 36 (6~66) winsize 61
4002 13:58:46.902927 [CA 2] Center 34 (3~65) winsize 63
4003 13:58:46.906665 [CA 3] Center 33 (3~64) winsize 62
4004 13:58:46.909730 [CA 4] Center 33 (2~64) winsize 63
4005 13:58:46.913317 [CA 5] Center 33 (2~64) winsize 63
4006 13:58:46.913885
4007 13:58:46.916100 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4008 13:58:46.916622
4009 13:58:46.919884 [CATrainingPosCal] consider 2 rank data
4010 13:58:46.923377 u2DelayCellTimex100 = 270/100 ps
4011 13:58:46.926403 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4012 13:58:46.932964 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4013 13:58:46.936416 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4014 13:58:46.939529 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4015 13:58:46.942729 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4016 13:58:46.946259 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4017 13:58:46.946823
4018 13:58:46.949513 CA PerBit enable=1, Macro0, CA PI delay=33
4019 13:58:46.950085
4020 13:58:46.952721 [CBTSetCACLKResult] CA Dly = 33
4021 13:58:46.956604 CS Dly: 5 (0~37)
4022 13:58:46.957164
4023 13:58:46.959777 ----->DramcWriteLeveling(PI) begin...
4024 13:58:46.960360 ==
4025 13:58:46.963391 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 13:58:46.966025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 13:58:46.966585 ==
4028 13:58:46.969336 Write leveling (Byte 0): 33 => 33
4029 13:58:46.972537 Write leveling (Byte 1): 28 => 28
4030 13:58:46.976241 DramcWriteLeveling(PI) end<-----
4031 13:58:46.976801
4032 13:58:46.977245 ==
4033 13:58:46.979275 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 13:58:46.982539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 13:58:46.983010 ==
4036 13:58:46.986479 [Gating] SW mode calibration
4037 13:58:46.992907 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4038 13:58:46.999638 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4039 13:58:47.002242 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 13:58:47.005614 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 13:58:47.012544 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 13:58:47.015872 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4043 13:58:47.019241 0 9 16 | B1->B0 | 2e2e 2828 | 1 0 | (1 0) (0 0)
4044 13:58:47.025352 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 13:58:47.028943 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 13:58:47.032110 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 13:58:47.038452 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 13:58:47.042417 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 13:58:47.045477 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 13:58:47.051933 0 10 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4051 13:58:47.055403 0 10 16 | B1->B0 | 3434 4141 | 1 1 | (0 0) (0 0)
4052 13:58:47.058868 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 13:58:47.065471 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 13:58:47.068546 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 13:58:47.071879 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 13:58:47.078632 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 13:58:47.081628 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 13:58:47.085030 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 13:58:47.091649 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 13:58:47.094896 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 13:58:47.098455 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 13:58:47.104752 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 13:58:47.108561 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 13:58:47.111615 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 13:58:47.118135 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 13:58:47.121578 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 13:58:47.124703 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 13:58:47.131209 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 13:58:47.134764 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 13:58:47.137702 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 13:58:47.144112 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 13:58:47.147571 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 13:58:47.150764 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4074 13:58:47.157421 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4075 13:58:47.160614 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4076 13:58:47.163965 Total UI for P1: 0, mck2ui 16
4077 13:58:47.167388 best dqsien dly found for B0: ( 0, 13, 10)
4078 13:58:47.170724 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 13:58:47.173967 Total UI for P1: 0, mck2ui 16
4080 13:58:47.177336 best dqsien dly found for B1: ( 0, 13, 16)
4081 13:58:47.180855 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4082 13:58:47.183600 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4083 13:58:47.184090
4084 13:58:47.190577 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4085 13:58:47.193994 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4086 13:58:47.197955 [Gating] SW calibration Done
4087 13:58:47.198540 ==
4088 13:58:47.200471 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 13:58:47.204469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 13:58:47.205033 ==
4091 13:58:47.205404 RX Vref Scan: 0
4092 13:58:47.205749
4093 13:58:47.207427 RX Vref 0 -> 0, step: 1
4094 13:58:47.208044
4095 13:58:47.210926 RX Delay -230 -> 252, step: 16
4096 13:58:47.214685 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4097 13:58:47.217038 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4098 13:58:47.223617 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4099 13:58:47.227892 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4100 13:58:47.230656 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4101 13:58:47.234355 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4102 13:58:47.241137 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4103 13:58:47.242958 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4104 13:58:47.246762 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4105 13:58:47.250113 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4106 13:58:47.256861 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4107 13:58:47.259716 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4108 13:58:47.263083 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4109 13:58:47.266591 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4110 13:58:47.273159 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4111 13:58:47.276358 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4112 13:58:47.276917 ==
4113 13:58:47.280548 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 13:58:47.282717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 13:58:47.283181 ==
4116 13:58:47.286725 DQS Delay:
4117 13:58:47.287357 DQS0 = 0, DQS1 = 0
4118 13:58:47.287769 DQM Delay:
4119 13:58:47.289738 DQM0 = 41, DQM1 = 32
4120 13:58:47.290299 DQ Delay:
4121 13:58:47.292841 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4122 13:58:47.296431 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4123 13:58:47.299462 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4124 13:58:47.303254 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4125 13:58:47.303868
4126 13:58:47.304251
4127 13:58:47.304597 ==
4128 13:58:47.305747 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 13:58:47.312606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 13:58:47.313170 ==
4131 13:58:47.313540
4132 13:58:47.313883
4133 13:58:47.314211 TX Vref Scan disable
4134 13:58:47.316229 == TX Byte 0 ==
4135 13:58:47.319448 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4136 13:58:47.326318 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4137 13:58:47.326879 == TX Byte 1 ==
4138 13:58:47.330108 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4139 13:58:47.337048 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4140 13:58:47.337609 ==
4141 13:58:47.339408 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 13:58:47.343374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 13:58:47.343978 ==
4144 13:58:47.344362
4145 13:58:47.344707
4146 13:58:47.346940 TX Vref Scan disable
4147 13:58:47.349902 == TX Byte 0 ==
4148 13:58:47.352616 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4149 13:58:47.356377 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4150 13:58:47.359501 == TX Byte 1 ==
4151 13:58:47.363201 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4152 13:58:47.365895 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4153 13:58:47.366451
4154 13:58:47.366821 [DATLAT]
4155 13:58:47.369135 Freq=600, CH0 RK0
4156 13:58:47.369698
4157 13:58:47.372456 DATLAT Default: 0x9
4158 13:58:47.373012 0, 0xFFFF, sum = 0
4159 13:58:47.376175 1, 0xFFFF, sum = 0
4160 13:58:47.376753 2, 0xFFFF, sum = 0
4161 13:58:47.379985 3, 0xFFFF, sum = 0
4162 13:58:47.380548 4, 0xFFFF, sum = 0
4163 13:58:47.382729 5, 0xFFFF, sum = 0
4164 13:58:47.383202 6, 0xFFFF, sum = 0
4165 13:58:47.385407 7, 0xFFFF, sum = 0
4166 13:58:47.385872 8, 0x0, sum = 1
4167 13:58:47.389113 9, 0x0, sum = 2
4168 13:58:47.389676 10, 0x0, sum = 3
4169 13:58:47.392155 11, 0x0, sum = 4
4170 13:58:47.392719 best_step = 9
4171 13:58:47.393085
4172 13:58:47.393422 ==
4173 13:58:47.395669 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 13:58:47.399036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 13:58:47.399623 ==
4176 13:58:47.402369 RX Vref Scan: 1
4177 13:58:47.402921
4178 13:58:47.406086 RX Vref 0 -> 0, step: 1
4179 13:58:47.406644
4180 13:58:47.407015 RX Delay -179 -> 252, step: 8
4181 13:58:47.409135
4182 13:58:47.409594 Set Vref, RX VrefLevel [Byte0]: 60
4183 13:58:47.412021 [Byte1]: 50
4184 13:58:47.417295
4185 13:58:47.417852 Final RX Vref Byte 0 = 60 to rank0
4186 13:58:47.419695 Final RX Vref Byte 1 = 50 to rank0
4187 13:58:47.423558 Final RX Vref Byte 0 = 60 to rank1
4188 13:58:47.426555 Final RX Vref Byte 1 = 50 to rank1==
4189 13:58:47.430797 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 13:58:47.436684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 13:58:47.437255 ==
4192 13:58:47.437625 DQS Delay:
4193 13:58:47.439707 DQS0 = 0, DQS1 = 0
4194 13:58:47.440216 DQM Delay:
4195 13:58:47.440591 DQM0 = 43, DQM1 = 32
4196 13:58:47.442810 DQ Delay:
4197 13:58:47.446530 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4198 13:58:47.450057 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4199 13:58:47.452505 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4200 13:58:47.456481 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4201 13:58:47.457117
4202 13:58:47.457488
4203 13:58:47.463571 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 389 ps
4204 13:58:47.465833 CH0 RK0: MR19=808, MR18=6C44
4205 13:58:47.472447 CH0_RK0: MR19=0x808, MR18=0x6C44, DQSOSC=389, MR23=63, INC=173, DEC=115
4206 13:58:47.473015
4207 13:58:47.476112 ----->DramcWriteLeveling(PI) begin...
4208 13:58:47.476679 ==
4209 13:58:47.479427 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 13:58:47.482216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 13:58:47.482784 ==
4212 13:58:47.485662 Write leveling (Byte 0): 33 => 33
4213 13:58:47.488947 Write leveling (Byte 1): 32 => 32
4214 13:58:47.492382 DramcWriteLeveling(PI) end<-----
4215 13:58:47.492843
4216 13:58:47.493206 ==
4217 13:58:47.495914 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 13:58:47.502326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 13:58:47.502888 ==
4220 13:58:47.503265 [Gating] SW mode calibration
4221 13:58:47.511888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4222 13:58:47.515642 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4223 13:58:47.521916 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 13:58:47.525470 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 13:58:47.528515 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 13:58:47.535224 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4227 13:58:47.538734 0 9 16 | B1->B0 | 2d2d 2626 | 1 0 | (0 0) (0 0)
4228 13:58:47.541873 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 13:58:47.545427 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 13:58:47.551936 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 13:58:47.555063 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 13:58:47.558444 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 13:58:47.565028 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 13:58:47.568785 0 10 12 | B1->B0 | 2727 2525 | 1 0 | (0 0) (0 0)
4235 13:58:47.571554 0 10 16 | B1->B0 | 4343 4141 | 0 0 | (0 0) (0 0)
4236 13:58:47.577934 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 13:58:47.581469 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 13:58:47.585477 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 13:58:47.591416 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 13:58:47.594683 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 13:58:47.597894 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 13:58:47.604675 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4243 13:58:47.607874 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 13:58:47.610963 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 13:58:47.617611 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 13:58:47.621213 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 13:58:47.624152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 13:58:47.631015 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 13:58:47.634658 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 13:58:47.638047 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 13:58:47.644247 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 13:58:47.647581 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 13:58:47.650873 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 13:58:47.657277 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 13:58:47.661318 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 13:58:47.663983 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 13:58:47.670654 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 13:58:47.673835 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4259 13:58:47.677215 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 13:58:47.680199 Total UI for P1: 0, mck2ui 16
4261 13:58:47.683465 best dqsien dly found for B0: ( 0, 13, 12)
4262 13:58:47.686857 Total UI for P1: 0, mck2ui 16
4263 13:58:47.690308 best dqsien dly found for B1: ( 0, 13, 12)
4264 13:58:47.693971 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4265 13:58:47.699961 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4266 13:58:47.700423
4267 13:58:47.703785 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4268 13:58:47.707158 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4269 13:58:47.710555 [Gating] SW calibration Done
4270 13:58:47.711117 ==
4271 13:58:47.713662 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 13:58:47.716837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 13:58:47.717400 ==
4274 13:58:47.719650 RX Vref Scan: 0
4275 13:58:47.720159
4276 13:58:47.720525 RX Vref 0 -> 0, step: 1
4277 13:58:47.720867
4278 13:58:47.723566 RX Delay -230 -> 252, step: 16
4279 13:58:47.726523 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4280 13:58:47.732887 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4281 13:58:47.736611 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4282 13:58:47.739991 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4283 13:58:47.743156 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4284 13:58:47.749712 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4285 13:58:47.752853 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4286 13:58:47.755908 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4287 13:58:47.759802 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4288 13:58:47.766031 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4289 13:58:47.770470 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4290 13:58:47.772494 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4291 13:58:47.776044 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4292 13:58:47.782958 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4293 13:58:47.786334 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4294 13:58:47.789415 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4295 13:58:47.789972 ==
4296 13:58:47.792468 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 13:58:47.795556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 13:58:47.796057 ==
4299 13:58:47.799233 DQS Delay:
4300 13:58:47.799689 DQS0 = 0, DQS1 = 0
4301 13:58:47.802472 DQM Delay:
4302 13:58:47.803031 DQM0 = 42, DQM1 = 36
4303 13:58:47.803395 DQ Delay:
4304 13:58:47.805395 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =41
4305 13:58:47.809238 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4306 13:58:47.812382 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4307 13:58:47.815669 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4308 13:58:47.816287
4309 13:58:47.818681
4310 13:58:47.819139 ==
4311 13:58:47.822570 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 13:58:47.825225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 13:58:47.825912 ==
4314 13:58:47.826306
4315 13:58:47.826650
4316 13:58:47.829049 TX Vref Scan disable
4317 13:58:47.829524 == TX Byte 0 ==
4318 13:58:47.835049 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4319 13:58:47.838459 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4320 13:58:47.838877 == TX Byte 1 ==
4321 13:58:47.844739 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4322 13:58:47.849067 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4323 13:58:47.849457 ==
4324 13:58:47.851703 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 13:58:47.854843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 13:58:47.855192 ==
4327 13:58:47.855536
4328 13:58:47.855898
4329 13:58:47.858269 TX Vref Scan disable
4330 13:58:47.861501 == TX Byte 0 ==
4331 13:58:47.864671 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4332 13:58:47.868111 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4333 13:58:47.871367 == TX Byte 1 ==
4334 13:58:47.875595 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4335 13:58:47.878056 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4336 13:58:47.878350
4337 13:58:47.881740 [DATLAT]
4338 13:58:47.882031 Freq=600, CH0 RK1
4339 13:58:47.882265
4340 13:58:47.885201 DATLAT Default: 0x9
4341 13:58:47.885491 0, 0xFFFF, sum = 0
4342 13:58:47.887818 1, 0xFFFF, sum = 0
4343 13:58:47.888116 2, 0xFFFF, sum = 0
4344 13:58:47.891672 3, 0xFFFF, sum = 0
4345 13:58:47.892228 4, 0xFFFF, sum = 0
4346 13:58:47.894839 5, 0xFFFF, sum = 0
4347 13:58:47.898123 6, 0xFFFF, sum = 0
4348 13:58:47.898642 7, 0xFFFF, sum = 0
4349 13:58:47.898987 8, 0x0, sum = 1
4350 13:58:47.901455 9, 0x0, sum = 2
4351 13:58:47.901972 10, 0x0, sum = 3
4352 13:58:47.904654 11, 0x0, sum = 4
4353 13:58:47.905195 best_step = 9
4354 13:58:47.905549
4355 13:58:47.905858 ==
4356 13:58:47.908279 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 13:58:47.914655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 13:58:47.915167 ==
4359 13:58:47.915502 RX Vref Scan: 0
4360 13:58:47.915868
4361 13:58:47.918273 RX Vref 0 -> 0, step: 1
4362 13:58:47.918785
4363 13:58:47.921561 RX Delay -179 -> 252, step: 8
4364 13:58:47.924448 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4365 13:58:47.931343 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4366 13:58:47.934531 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4367 13:58:47.937803 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4368 13:58:47.941224 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4369 13:58:47.948143 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4370 13:58:47.951023 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4371 13:58:47.954933 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4372 13:58:47.957653 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4373 13:58:47.961241 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4374 13:58:47.967633 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4375 13:58:47.971567 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4376 13:58:47.974251 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4377 13:58:47.977809 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4378 13:58:47.984123 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4379 13:58:47.987471 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4380 13:58:47.988177 ==
4381 13:58:47.990864 Dram Type= 6, Freq= 0, CH_0, rank 1
4382 13:58:47.994231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 13:58:47.994835 ==
4384 13:58:47.997323 DQS Delay:
4385 13:58:47.997788 DQS0 = 0, DQS1 = 0
4386 13:58:47.998156 DQM Delay:
4387 13:58:48.000475 DQM0 = 42, DQM1 = 37
4388 13:58:48.000933 DQ Delay:
4389 13:58:48.004308 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4390 13:58:48.007169 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4391 13:58:48.010308 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4392 13:58:48.013576 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4393 13:58:48.014035
4394 13:58:48.014400
4395 13:58:48.023614 [DQSOSCAuto] RK1, (LSB)MR18= 0x6415, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4396 13:58:48.027483 CH0 RK1: MR19=808, MR18=6415
4397 13:58:48.030226 CH0_RK1: MR19=0x808, MR18=0x6415, DQSOSC=391, MR23=63, INC=171, DEC=114
4398 13:58:48.033869 [RxdqsGatingPostProcess] freq 600
4399 13:58:48.040375 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4400 13:58:48.043583 Pre-setting of DQS Precalculation
4401 13:58:48.047281 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4402 13:58:48.050453 ==
4403 13:58:48.051012 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 13:58:48.056856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 13:58:48.057421 ==
4406 13:58:48.060010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4407 13:58:48.066767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4408 13:58:48.070472 [CA 0] Center 35 (5~66) winsize 62
4409 13:58:48.073902 [CA 1] Center 36 (6~66) winsize 61
4410 13:58:48.077232 [CA 2] Center 34 (4~65) winsize 62
4411 13:58:48.080258 [CA 3] Center 33 (3~64) winsize 62
4412 13:58:48.083774 [CA 4] Center 34 (4~64) winsize 61
4413 13:58:48.087281 [CA 5] Center 33 (3~64) winsize 62
4414 13:58:48.087900
4415 13:58:48.090603 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4416 13:58:48.091156
4417 13:58:48.093793 [CATrainingPosCal] consider 1 rank data
4418 13:58:48.096513 u2DelayCellTimex100 = 270/100 ps
4419 13:58:48.100384 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4420 13:58:48.107026 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4421 13:58:48.109804 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4422 13:58:48.113326 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4423 13:58:48.116482 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4424 13:58:48.119821 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4425 13:58:48.120382
4426 13:58:48.122875 CA PerBit enable=1, Macro0, CA PI delay=33
4427 13:58:48.123338
4428 13:58:48.126283 [CBTSetCACLKResult] CA Dly = 33
4429 13:58:48.129794 CS Dly: 4 (0~35)
4430 13:58:48.130255 ==
4431 13:58:48.132937 Dram Type= 6, Freq= 0, CH_1, rank 1
4432 13:58:48.136463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 13:58:48.137025 ==
4434 13:58:48.142690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4435 13:58:48.145901 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4436 13:58:48.150904 [CA 0] Center 35 (5~66) winsize 62
4437 13:58:48.154090 [CA 1] Center 36 (6~66) winsize 61
4438 13:58:48.156865 [CA 2] Center 34 (4~65) winsize 62
4439 13:58:48.160153 [CA 3] Center 34 (4~65) winsize 62
4440 13:58:48.163684 [CA 4] Center 34 (4~65) winsize 62
4441 13:58:48.167078 [CA 5] Center 34 (3~65) winsize 63
4442 13:58:48.167632
4443 13:58:48.170312 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4444 13:58:48.170866
4445 13:58:48.173610 [CATrainingPosCal] consider 2 rank data
4446 13:58:48.176638 u2DelayCellTimex100 = 270/100 ps
4447 13:58:48.179841 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4448 13:58:48.186798 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4449 13:58:48.190342 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4450 13:58:48.193290 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4451 13:58:48.196620 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4452 13:58:48.200281 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4453 13:58:48.200845
4454 13:58:48.203322 CA PerBit enable=1, Macro0, CA PI delay=33
4455 13:58:48.203909
4456 13:58:48.207122 [CBTSetCACLKResult] CA Dly = 33
4457 13:58:48.210056 CS Dly: 5 (0~37)
4458 13:58:48.210517
4459 13:58:48.213031 ----->DramcWriteLeveling(PI) begin...
4460 13:58:48.213596 ==
4461 13:58:48.216123 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 13:58:48.220824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 13:58:48.221419 ==
4464 13:58:48.223253 Write leveling (Byte 0): 28 => 28
4465 13:58:48.226509 Write leveling (Byte 1): 30 => 30
4466 13:58:48.229732 DramcWriteLeveling(PI) end<-----
4467 13:58:48.230298
4468 13:58:48.230668 ==
4469 13:58:48.233331 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 13:58:48.236511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 13:58:48.236976 ==
4472 13:58:48.239874 [Gating] SW mode calibration
4473 13:58:48.245974 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4474 13:58:48.252594 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4475 13:58:48.256517 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4476 13:58:48.259366 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4477 13:58:48.266407 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 13:58:48.269474 0 9 12 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
4479 13:58:48.272714 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
4480 13:58:48.279530 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 13:58:48.282552 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 13:58:48.285750 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 13:58:48.292742 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 13:58:48.295949 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 13:58:48.299781 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4486 13:58:48.306514 0 10 12 | B1->B0 | 2929 4040 | 0 0 | (0 0) (0 0)
4487 13:58:48.308804 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 13:58:48.312103 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 13:58:48.318216 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 13:58:48.321723 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 13:58:48.325078 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 13:58:48.331479 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 13:58:48.335661 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 13:58:48.338480 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4495 13:58:48.345610 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 13:58:48.348323 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 13:58:48.351383 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 13:58:48.357987 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 13:58:48.361525 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 13:58:48.365113 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 13:58:48.371636 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 13:58:48.375141 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 13:58:48.377855 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 13:58:48.385114 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 13:58:48.387611 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 13:58:48.391266 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 13:58:48.397561 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 13:58:48.400607 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 13:58:48.404299 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 13:58:48.410702 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4511 13:58:48.414468 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 13:58:48.417560 Total UI for P1: 0, mck2ui 16
4513 13:58:48.420641 best dqsien dly found for B0: ( 0, 13, 12)
4514 13:58:48.423768 Total UI for P1: 0, mck2ui 16
4515 13:58:48.427292 best dqsien dly found for B1: ( 0, 13, 12)
4516 13:58:48.430332 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4517 13:58:48.434230 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4518 13:58:48.434799
4519 13:58:48.437670 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4520 13:58:48.443562 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4521 13:58:48.444294 [Gating] SW calibration Done
4522 13:58:48.444840 ==
4523 13:58:48.446766 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 13:58:48.453790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 13:58:48.454256 ==
4526 13:58:48.454729 RX Vref Scan: 0
4527 13:58:48.455087
4528 13:58:48.456996 RX Vref 0 -> 0, step: 1
4529 13:58:48.457457
4530 13:58:48.460053 RX Delay -230 -> 252, step: 16
4531 13:58:48.463425 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4532 13:58:48.466976 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4533 13:58:48.473540 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4534 13:58:48.477179 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4535 13:58:48.480278 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4536 13:58:48.483823 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4537 13:58:48.486629 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4538 13:58:48.493100 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4539 13:58:48.496589 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4540 13:58:48.499903 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4541 13:58:48.503026 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4542 13:58:48.509652 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4543 13:58:48.512772 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4544 13:58:48.516138 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4545 13:58:48.519624 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4546 13:58:48.526240 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4547 13:58:48.526796 ==
4548 13:58:48.529248 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 13:58:48.533155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 13:58:48.533718 ==
4551 13:58:48.534087 DQS Delay:
4552 13:58:48.536323 DQS0 = 0, DQS1 = 0
4553 13:58:48.536784 DQM Delay:
4554 13:58:48.539495 DQM0 = 46, DQM1 = 39
4555 13:58:48.540101 DQ Delay:
4556 13:58:48.542656 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4557 13:58:48.546064 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4558 13:58:48.549383 DQ8 =17, DQ9 =33, DQ10 =41, DQ11 =25
4559 13:58:48.552451 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4560 13:58:48.553099
4561 13:58:48.553497
4562 13:58:48.553838 ==
4563 13:58:48.555985 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 13:58:48.558751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 13:58:48.562577 ==
4566 13:58:48.563153
4567 13:58:48.563525
4568 13:58:48.563925 TX Vref Scan disable
4569 13:58:48.565676 == TX Byte 0 ==
4570 13:58:48.568748 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4571 13:58:48.572222 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4572 13:58:48.575943 == TX Byte 1 ==
4573 13:58:48.579209 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4574 13:58:48.582337 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4575 13:58:48.585533 ==
4576 13:58:48.588779 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 13:58:48.592725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 13:58:48.593281 ==
4579 13:58:48.593654
4580 13:58:48.593997
4581 13:58:48.595235 TX Vref Scan disable
4582 13:58:48.598662 == TX Byte 0 ==
4583 13:58:48.602545 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4584 13:58:48.605174 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4585 13:58:48.609271 == TX Byte 1 ==
4586 13:58:48.612361 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4587 13:58:48.615073 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4588 13:58:48.615536
4589 13:58:48.615960 [DATLAT]
4590 13:58:48.618761 Freq=600, CH1 RK0
4591 13:58:48.619317
4592 13:58:48.619682 DATLAT Default: 0x9
4593 13:58:48.622971 0, 0xFFFF, sum = 0
4594 13:58:48.625573 1, 0xFFFF, sum = 0
4595 13:58:48.626040 2, 0xFFFF, sum = 0
4596 13:58:48.628495 3, 0xFFFF, sum = 0
4597 13:58:48.628962 4, 0xFFFF, sum = 0
4598 13:58:48.631639 5, 0xFFFF, sum = 0
4599 13:58:48.632095 6, 0xFFFF, sum = 0
4600 13:58:48.635529 7, 0xFFFF, sum = 0
4601 13:58:48.636100 8, 0x0, sum = 1
4602 13:58:48.638646 9, 0x0, sum = 2
4603 13:58:48.639169 10, 0x0, sum = 3
4604 13:58:48.639510 11, 0x0, sum = 4
4605 13:58:48.641940 best_step = 9
4606 13:58:48.642454
4607 13:58:48.642789 ==
4608 13:58:48.645028 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 13:58:48.648472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 13:58:48.648911 ==
4611 13:58:48.652153 RX Vref Scan: 1
4612 13:58:48.652571
4613 13:58:48.652904 RX Vref 0 -> 0, step: 1
4614 13:58:48.654935
4615 13:58:48.655352 RX Delay -195 -> 252, step: 8
4616 13:58:48.655691
4617 13:58:48.658303 Set Vref, RX VrefLevel [Byte0]: 47
4618 13:58:48.661381 [Byte1]: 60
4619 13:58:48.666431
4620 13:58:48.666846 Final RX Vref Byte 0 = 47 to rank0
4621 13:58:48.669299 Final RX Vref Byte 1 = 60 to rank0
4622 13:58:48.672582 Final RX Vref Byte 0 = 47 to rank1
4623 13:58:48.675823 Final RX Vref Byte 1 = 60 to rank1==
4624 13:58:48.679070 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 13:58:48.685667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 13:58:48.686173 ==
4627 13:58:48.686514 DQS Delay:
4628 13:58:48.688914 DQS0 = 0, DQS1 = 0
4629 13:58:48.689330 DQM Delay:
4630 13:58:48.689663 DQM0 = 48, DQM1 = 37
4631 13:58:48.692590 DQ Delay:
4632 13:58:48.695967 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4633 13:58:48.699542 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4634 13:58:48.702425 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4635 13:58:48.705844 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =48
4636 13:58:48.706365
4637 13:58:48.706702
4638 13:58:48.712569 [DQSOSCAuto] RK0, (LSB)MR18= 0x5439, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
4639 13:58:48.715637 CH1 RK0: MR19=808, MR18=5439
4640 13:58:48.722388 CH1_RK0: MR19=0x808, MR18=0x5439, DQSOSC=393, MR23=63, INC=169, DEC=113
4641 13:58:48.722893
4642 13:58:48.725672 ----->DramcWriteLeveling(PI) begin...
4643 13:58:48.726194 ==
4644 13:58:48.729292 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 13:58:48.731863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 13:58:48.732286 ==
4647 13:58:48.735307 Write leveling (Byte 0): 29 => 29
4648 13:58:48.739381 Write leveling (Byte 1): 31 => 31
4649 13:58:48.742586 DramcWriteLeveling(PI) end<-----
4650 13:58:48.743099
4651 13:58:48.743431 ==
4652 13:58:48.744982 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 13:58:48.748551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 13:58:48.752249 ==
4655 13:58:48.752768 [Gating] SW mode calibration
4656 13:58:48.762290 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4657 13:58:48.765043 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4658 13:58:48.768623 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4659 13:58:48.775101 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4660 13:58:48.778202 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4661 13:58:48.783707 0 9 12 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (0 0)
4662 13:58:48.788703 0 9 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4663 13:58:48.791702 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 13:58:48.794860 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 13:58:48.801392 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 13:58:48.804806 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 13:58:48.808277 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 13:58:48.814575 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 13:58:48.817638 0 10 12 | B1->B0 | 3333 3131 | 1 1 | (0 0) (0 0)
4670 13:58:48.821375 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4671 13:58:48.828217 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 13:58:48.831374 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 13:58:48.834767 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 13:58:48.841108 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 13:58:48.844737 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 13:58:48.848278 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 13:58:48.854337 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4678 13:58:48.857803 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4679 13:58:48.860645 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 13:58:48.867980 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 13:58:48.871077 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 13:58:48.874071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 13:58:48.880897 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 13:58:48.884180 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 13:58:48.887233 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 13:58:48.895107 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 13:58:48.897265 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 13:58:48.900234 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 13:58:48.907076 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 13:58:48.910138 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 13:58:48.913302 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 13:58:48.919860 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4693 13:58:48.923145 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4694 13:58:48.926544 Total UI for P1: 0, mck2ui 16
4695 13:58:48.929782 best dqsien dly found for B1: ( 0, 13, 8)
4696 13:58:48.934055 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 13:58:48.936690 Total UI for P1: 0, mck2ui 16
4698 13:58:48.939582 best dqsien dly found for B0: ( 0, 13, 14)
4699 13:58:48.942970 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4700 13:58:48.946373 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4701 13:58:48.949902
4702 13:58:48.952760 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4703 13:58:48.956609 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4704 13:58:48.959848 [Gating] SW calibration Done
4705 13:58:48.960268 ==
4706 13:58:48.962834 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 13:58:48.967037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 13:58:48.967565 ==
4709 13:58:48.967947 RX Vref Scan: 0
4710 13:58:48.969881
4711 13:58:48.970443 RX Vref 0 -> 0, step: 1
4712 13:58:48.970817
4713 13:58:48.973220 RX Delay -230 -> 252, step: 16
4714 13:58:48.976205 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4715 13:58:48.983205 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4716 13:58:48.985967 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4717 13:58:48.989627 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4718 13:58:48.992662 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4719 13:58:48.999295 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4720 13:58:49.002562 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4721 13:58:49.005751 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4722 13:58:49.008997 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4723 13:58:49.012524 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4724 13:58:49.018351 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4725 13:58:49.022000 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4726 13:58:49.025410 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4727 13:58:49.029849 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4728 13:58:49.034767 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4729 13:58:49.038226 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4730 13:58:49.038699 ==
4731 13:58:49.041447 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 13:58:49.044395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 13:58:49.044865 ==
4734 13:58:49.048032 DQS Delay:
4735 13:58:49.048510 DQS0 = 0, DQS1 = 0
4736 13:58:49.051594 DQM Delay:
4737 13:58:49.052088 DQM0 = 42, DQM1 = 37
4738 13:58:49.052459 DQ Delay:
4739 13:58:49.055274 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4740 13:58:49.057988 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4741 13:58:49.060936 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4742 13:58:49.064396 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4743 13:58:49.064865
4744 13:58:49.067866
4745 13:58:49.068432 ==
4746 13:58:49.071257 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 13:58:49.074384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 13:58:49.074954 ==
4749 13:58:49.075333
4750 13:58:49.075681
4751 13:58:49.078104 TX Vref Scan disable
4752 13:58:49.078667 == TX Byte 0 ==
4753 13:58:49.084851 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4754 13:58:49.087931 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4755 13:58:49.088503 == TX Byte 1 ==
4756 13:58:49.094911 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4757 13:58:49.097658 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4758 13:58:49.098234 ==
4759 13:58:49.101530 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 13:58:49.103932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 13:58:49.104408 ==
4762 13:58:49.104783
4763 13:58:49.105129
4764 13:58:49.107832 TX Vref Scan disable
4765 13:58:49.111092 == TX Byte 0 ==
4766 13:58:49.114682 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4767 13:58:49.117490 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4768 13:58:49.121211 == TX Byte 1 ==
4769 13:58:49.123886 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4770 13:58:49.127668 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4771 13:58:49.131258
4772 13:58:49.131765 [DATLAT]
4773 13:58:49.132154 Freq=600, CH1 RK1
4774 13:58:49.132509
4775 13:58:49.133758 DATLAT Default: 0x9
4776 13:58:49.134226 0, 0xFFFF, sum = 0
4777 13:58:49.137351 1, 0xFFFF, sum = 0
4778 13:58:49.137935 2, 0xFFFF, sum = 0
4779 13:58:49.140525 3, 0xFFFF, sum = 0
4780 13:58:49.141000 4, 0xFFFF, sum = 0
4781 13:58:49.144284 5, 0xFFFF, sum = 0
4782 13:58:49.147200 6, 0xFFFF, sum = 0
4783 13:58:49.147672 7, 0xFFFF, sum = 0
4784 13:58:49.148093 8, 0x0, sum = 1
4785 13:58:49.150170 9, 0x0, sum = 2
4786 13:58:49.150643 10, 0x0, sum = 3
4787 13:58:49.153795 11, 0x0, sum = 4
4788 13:58:49.154370 best_step = 9
4789 13:58:49.154744
4790 13:58:49.155092 ==
4791 13:58:49.157515 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 13:58:49.164035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 13:58:49.164606 ==
4794 13:58:49.165018 RX Vref Scan: 0
4795 13:58:49.165416
4796 13:58:49.166853 RX Vref 0 -> 0, step: 1
4797 13:58:49.167456
4798 13:58:49.170362 RX Delay -195 -> 252, step: 8
4799 13:58:49.173672 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4800 13:58:49.180511 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4801 13:58:49.184107 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4802 13:58:49.186619 iDelay=213, Bit 3, Center 44 (-99 ~ 188) 288
4803 13:58:49.190527 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4804 13:58:49.193735 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4805 13:58:49.200324 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4806 13:58:49.203218 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4807 13:58:49.206836 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4808 13:58:49.210512 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4809 13:58:49.216626 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4810 13:58:49.219799 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4811 13:58:49.223001 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4812 13:58:49.226433 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4813 13:58:49.233284 iDelay=213, Bit 14, Center 44 (-115 ~ 204) 320
4814 13:58:49.235917 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4815 13:58:49.236387 ==
4816 13:58:49.239387 Dram Type= 6, Freq= 0, CH_1, rank 1
4817 13:58:49.242812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4818 13:58:49.243387 ==
4819 13:58:49.246358 DQS Delay:
4820 13:58:49.247000 DQS0 = 0, DQS1 = 0
4821 13:58:49.249525 DQM Delay:
4822 13:58:49.249992 DQM0 = 45, DQM1 = 36
4823 13:58:49.250363 DQ Delay:
4824 13:58:49.252651 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4825 13:58:49.256244 DQ4 =44, DQ5 =52, DQ6 =56, DQ7 =44
4826 13:58:49.259329 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4827 13:58:49.262825 DQ12 =44, DQ13 =48, DQ14 =44, DQ15 =48
4828 13:58:49.263394
4829 13:58:49.263822
4830 13:58:49.272352 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4831 13:58:49.276168 CH1 RK1: MR19=808, MR18=2E23
4832 13:58:49.282375 CH1_RK1: MR19=0x808, MR18=0x2E23, DQSOSC=401, MR23=63, INC=163, DEC=108
4833 13:58:49.282932 [RxdqsGatingPostProcess] freq 600
4834 13:58:49.289084 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4835 13:58:49.292695 Pre-setting of DQS Precalculation
4836 13:58:49.295714 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4837 13:58:49.305848 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4838 13:58:49.312644 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4839 13:58:49.313216
4840 13:58:49.313593
4841 13:58:49.315594 [Calibration Summary] 1200 Mbps
4842 13:58:49.316215 CH 0, Rank 0
4843 13:58:49.318866 SW Impedance : PASS
4844 13:58:49.319441 DUTY Scan : NO K
4845 13:58:49.322736 ZQ Calibration : PASS
4846 13:58:49.325523 Jitter Meter : NO K
4847 13:58:49.326104 CBT Training : PASS
4848 13:58:49.328851 Write leveling : PASS
4849 13:58:49.331772 RX DQS gating : PASS
4850 13:58:49.332242 RX DQ/DQS(RDDQC) : PASS
4851 13:58:49.335240 TX DQ/DQS : PASS
4852 13:58:49.338270 RX DATLAT : PASS
4853 13:58:49.338739 RX DQ/DQS(Engine): PASS
4854 13:58:49.342458 TX OE : NO K
4855 13:58:49.343028 All Pass.
4856 13:58:49.343404
4857 13:58:49.344875 CH 0, Rank 1
4858 13:58:49.345342 SW Impedance : PASS
4859 13:58:49.348327 DUTY Scan : NO K
4860 13:58:49.352001 ZQ Calibration : PASS
4861 13:58:49.352472 Jitter Meter : NO K
4862 13:58:49.354958 CBT Training : PASS
4863 13:58:49.358543 Write leveling : PASS
4864 13:58:49.359129 RX DQS gating : PASS
4865 13:58:49.362023 RX DQ/DQS(RDDQC) : PASS
4866 13:58:49.364877 TX DQ/DQS : PASS
4867 13:58:49.365349 RX DATLAT : PASS
4868 13:58:49.369164 RX DQ/DQS(Engine): PASS
4869 13:58:49.369728 TX OE : NO K
4870 13:58:49.371376 All Pass.
4871 13:58:49.371934
4872 13:58:49.372366 CH 1, Rank 0
4873 13:58:49.375251 SW Impedance : PASS
4874 13:58:49.379229 DUTY Scan : NO K
4875 13:58:49.379844 ZQ Calibration : PASS
4876 13:58:49.381609 Jitter Meter : NO K
4877 13:58:49.382091 CBT Training : PASS
4878 13:58:49.385097 Write leveling : PASS
4879 13:58:49.389380 RX DQS gating : PASS
4880 13:58:49.389949 RX DQ/DQS(RDDQC) : PASS
4881 13:58:49.391570 TX DQ/DQS : PASS
4882 13:58:49.395101 RX DATLAT : PASS
4883 13:58:49.395672 RX DQ/DQS(Engine): PASS
4884 13:58:49.398393 TX OE : NO K
4885 13:58:49.398968 All Pass.
4886 13:58:49.399344
4887 13:58:49.401549 CH 1, Rank 1
4888 13:58:49.402117 SW Impedance : PASS
4889 13:58:49.404991 DUTY Scan : NO K
4890 13:58:49.407931 ZQ Calibration : PASS
4891 13:58:49.408401 Jitter Meter : NO K
4892 13:58:49.411583 CBT Training : PASS
4893 13:58:49.414855 Write leveling : PASS
4894 13:58:49.415418 RX DQS gating : PASS
4895 13:58:49.417836 RX DQ/DQS(RDDQC) : PASS
4896 13:58:49.421525 TX DQ/DQS : PASS
4897 13:58:49.422094 RX DATLAT : PASS
4898 13:58:49.424363 RX DQ/DQS(Engine): PASS
4899 13:58:49.427931 TX OE : NO K
4900 13:58:49.428500 All Pass.
4901 13:58:49.428877
4902 13:58:49.429223 DramC Write-DBI off
4903 13:58:49.431028 PER_BANK_REFRESH: Hybrid Mode
4904 13:58:49.434307 TX_TRACKING: ON
4905 13:58:49.440631 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4906 13:58:49.447033 [FAST_K] Save calibration result to emmc
4907 13:58:49.450884 dramc_set_vcore_voltage set vcore to 662500
4908 13:58:49.451510 Read voltage for 933, 3
4909 13:58:49.453883 Vio18 = 0
4910 13:58:49.454350 Vcore = 662500
4911 13:58:49.454722 Vdram = 0
4912 13:58:49.457679 Vddq = 0
4913 13:58:49.458145 Vmddr = 0
4914 13:58:49.460467 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4915 13:58:49.467204 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4916 13:58:49.470752 MEM_TYPE=3, freq_sel=17
4917 13:58:49.473504 sv_algorithm_assistance_LP4_1600
4918 13:58:49.476775 ============ PULL DRAM RESETB DOWN ============
4919 13:58:49.480129 ========== PULL DRAM RESETB DOWN end =========
4920 13:58:49.486888 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4921 13:58:49.490426 ===================================
4922 13:58:49.490992 LPDDR4 DRAM CONFIGURATION
4923 13:58:49.493757 ===================================
4924 13:58:49.496849 EX_ROW_EN[0] = 0x0
4925 13:58:49.497417 EX_ROW_EN[1] = 0x0
4926 13:58:49.500351 LP4Y_EN = 0x0
4927 13:58:49.500909 WORK_FSP = 0x0
4928 13:58:49.503847 WL = 0x3
4929 13:58:49.507670 RL = 0x3
4930 13:58:49.508290 BL = 0x2
4931 13:58:49.510306 RPST = 0x0
4932 13:58:49.510867 RD_PRE = 0x0
4933 13:58:49.513184 WR_PRE = 0x1
4934 13:58:49.513651 WR_PST = 0x0
4935 13:58:49.516941 DBI_WR = 0x0
4936 13:58:49.517501 DBI_RD = 0x0
4937 13:58:49.520100 OTF = 0x1
4938 13:58:49.523674 ===================================
4939 13:58:49.526681 ===================================
4940 13:58:49.527112 ANA top config
4941 13:58:49.530226 ===================================
4942 13:58:49.533401 DLL_ASYNC_EN = 0
4943 13:58:49.536363 ALL_SLAVE_EN = 1
4944 13:58:49.536933 NEW_RANK_MODE = 1
4945 13:58:49.540142 DLL_IDLE_MODE = 1
4946 13:58:49.543529 LP45_APHY_COMB_EN = 1
4947 13:58:49.546537 TX_ODT_DIS = 1
4948 13:58:49.550080 NEW_8X_MODE = 1
4949 13:58:49.552840 ===================================
4950 13:58:49.556490 ===================================
4951 13:58:49.557062 data_rate = 1866
4952 13:58:49.559715 CKR = 1
4953 13:58:49.563145 DQ_P2S_RATIO = 8
4954 13:58:49.566328 ===================================
4955 13:58:49.569552 CA_P2S_RATIO = 8
4956 13:58:49.572838 DQ_CA_OPEN = 0
4957 13:58:49.575923 DQ_SEMI_OPEN = 0
4958 13:58:49.579286 CA_SEMI_OPEN = 0
4959 13:58:49.579789 CA_FULL_RATE = 0
4960 13:58:49.582448 DQ_CKDIV4_EN = 1
4961 13:58:49.586296 CA_CKDIV4_EN = 1
4962 13:58:49.589456 CA_PREDIV_EN = 0
4963 13:58:49.592933 PH8_DLY = 0
4964 13:58:49.595583 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4965 13:58:49.596086 DQ_AAMCK_DIV = 4
4966 13:58:49.599065 CA_AAMCK_DIV = 4
4967 13:58:49.602441 CA_ADMCK_DIV = 4
4968 13:58:49.605716 DQ_TRACK_CA_EN = 0
4969 13:58:49.609129 CA_PICK = 933
4970 13:58:49.612724 CA_MCKIO = 933
4971 13:58:49.613293 MCKIO_SEMI = 0
4972 13:58:49.616379 PLL_FREQ = 3732
4973 13:58:49.619371 DQ_UI_PI_RATIO = 32
4974 13:58:49.622070 CA_UI_PI_RATIO = 0
4975 13:58:49.625508 ===================================
4976 13:58:49.629036 ===================================
4977 13:58:49.632621 memory_type:LPDDR4
4978 13:58:49.633187 GP_NUM : 10
4979 13:58:49.635575 SRAM_EN : 1
4980 13:58:49.638672 MD32_EN : 0
4981 13:58:49.642483 ===================================
4982 13:58:49.643050 [ANA_INIT] >>>>>>>>>>>>>>
4983 13:58:49.645560 <<<<<< [CONFIGURE PHASE]: ANA_TX
4984 13:58:49.648466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4985 13:58:49.652069 ===================================
4986 13:58:49.655512 data_rate = 1866,PCW = 0X8f00
4987 13:58:49.659072 ===================================
4988 13:58:49.661925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4989 13:58:49.668335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4990 13:58:49.672336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4991 13:58:49.678836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4992 13:58:49.682022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4993 13:58:49.685064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4994 13:58:49.688046 [ANA_INIT] flow start
4995 13:58:49.688555 [ANA_INIT] PLL >>>>>>>>
4996 13:58:49.691548 [ANA_INIT] PLL <<<<<<<<
4997 13:58:49.694704 [ANA_INIT] MIDPI >>>>>>>>
4998 13:58:49.695169 [ANA_INIT] MIDPI <<<<<<<<
4999 13:58:49.698769 [ANA_INIT] DLL >>>>>>>>
5000 13:58:49.701301 [ANA_INIT] flow end
5001 13:58:49.704724 ============ LP4 DIFF to SE enter ============
5002 13:58:49.708106 ============ LP4 DIFF to SE exit ============
5003 13:58:49.711207 [ANA_INIT] <<<<<<<<<<<<<
5004 13:58:49.714860 [Flow] Enable top DCM control >>>>>
5005 13:58:49.717901 [Flow] Enable top DCM control <<<<<
5006 13:58:49.721103 Enable DLL master slave shuffle
5007 13:58:49.724354 ==============================================================
5008 13:58:49.727853 Gating Mode config
5009 13:58:49.734863 ==============================================================
5010 13:58:49.735420 Config description:
5011 13:58:49.744203 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5012 13:58:49.751127 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5013 13:58:49.757440 SELPH_MODE 0: By rank 1: By Phase
5014 13:58:49.761086 ==============================================================
5015 13:58:49.764377 GAT_TRACK_EN = 1
5016 13:58:49.767810 RX_GATING_MODE = 2
5017 13:58:49.771211 RX_GATING_TRACK_MODE = 2
5018 13:58:49.774474 SELPH_MODE = 1
5019 13:58:49.777946 PICG_EARLY_EN = 1
5020 13:58:49.780978 VALID_LAT_VALUE = 1
5021 13:58:49.783936 ==============================================================
5022 13:58:49.787774 Enter into Gating configuration >>>>
5023 13:58:49.790520 Exit from Gating configuration <<<<
5024 13:58:49.794051 Enter into DVFS_PRE_config >>>>>
5025 13:58:49.807164 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5026 13:58:49.810953 Exit from DVFS_PRE_config <<<<<
5027 13:58:49.813783 Enter into PICG configuration >>>>
5028 13:58:49.817344 Exit from PICG configuration <<<<
5029 13:58:49.817911 [RX_INPUT] configuration >>>>>
5030 13:58:49.820368 [RX_INPUT] configuration <<<<<
5031 13:58:49.827280 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5032 13:58:49.830307 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5033 13:58:49.836689 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5034 13:58:49.843519 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5035 13:58:49.850019 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5036 13:58:49.856565 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5037 13:58:49.859849 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5038 13:58:49.863228 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5039 13:58:49.869966 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5040 13:58:49.873433 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5041 13:58:49.876706 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5042 13:58:49.883163 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5043 13:58:49.886482 ===================================
5044 13:58:49.887048 LPDDR4 DRAM CONFIGURATION
5045 13:58:49.889569 ===================================
5046 13:58:49.893436 EX_ROW_EN[0] = 0x0
5047 13:58:49.894000 EX_ROW_EN[1] = 0x0
5048 13:58:49.896514 LP4Y_EN = 0x0
5049 13:58:49.897077 WORK_FSP = 0x0
5050 13:58:49.899959 WL = 0x3
5051 13:58:49.900530 RL = 0x3
5052 13:58:49.903203 BL = 0x2
5053 13:58:49.906202 RPST = 0x0
5054 13:58:49.906764 RD_PRE = 0x0
5055 13:58:49.909860 WR_PRE = 0x1
5056 13:58:49.910420 WR_PST = 0x0
5057 13:58:49.912901 DBI_WR = 0x0
5058 13:58:49.913465 DBI_RD = 0x0
5059 13:58:49.916104 OTF = 0x1
5060 13:58:49.920286 ===================================
5061 13:58:49.922618 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5062 13:58:49.926653 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5063 13:58:49.929388 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5064 13:58:49.932795 ===================================
5065 13:58:49.935857 LPDDR4 DRAM CONFIGURATION
5066 13:58:49.939519 ===================================
5067 13:58:49.943076 EX_ROW_EN[0] = 0x10
5068 13:58:49.943645 EX_ROW_EN[1] = 0x0
5069 13:58:49.946193 LP4Y_EN = 0x0
5070 13:58:49.946657 WORK_FSP = 0x0
5071 13:58:49.949238 WL = 0x3
5072 13:58:49.949700 RL = 0x3
5073 13:58:49.952471 BL = 0x2
5074 13:58:49.952938 RPST = 0x0
5075 13:58:49.955572 RD_PRE = 0x0
5076 13:58:49.959060 WR_PRE = 0x1
5077 13:58:49.959622 WR_PST = 0x0
5078 13:58:49.962285 DBI_WR = 0x0
5079 13:58:49.962847 DBI_RD = 0x0
5080 13:58:49.965876 OTF = 0x1
5081 13:58:49.968783 ===================================
5082 13:58:49.972097 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5083 13:58:49.977756 nWR fixed to 30
5084 13:58:49.981056 [ModeRegInit_LP4] CH0 RK0
5085 13:58:49.981610 [ModeRegInit_LP4] CH0 RK1
5086 13:58:49.985205 [ModeRegInit_LP4] CH1 RK0
5087 13:58:49.987795 [ModeRegInit_LP4] CH1 RK1
5088 13:58:49.988263 match AC timing 9
5089 13:58:49.994320 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5090 13:58:49.997992 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5091 13:58:50.001089 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5092 13:58:50.007486 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5093 13:58:50.010868 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5094 13:58:50.011427 ==
5095 13:58:50.014107 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 13:58:50.017750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 13:58:50.018313 ==
5098 13:58:50.024513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5099 13:58:50.030462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5100 13:58:50.033425 [CA 0] Center 37 (7~68) winsize 62
5101 13:58:50.036854 [CA 1] Center 37 (7~68) winsize 62
5102 13:58:50.040191 [CA 2] Center 34 (4~65) winsize 62
5103 13:58:50.043504 [CA 3] Center 35 (5~65) winsize 61
5104 13:58:50.047237 [CA 4] Center 33 (3~64) winsize 62
5105 13:58:50.050245 [CA 5] Center 33 (3~64) winsize 62
5106 13:58:50.050798
5107 13:58:50.054595 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5108 13:58:50.055188
5109 13:58:50.057139 [CATrainingPosCal] consider 1 rank data
5110 13:58:50.060201 u2DelayCellTimex100 = 270/100 ps
5111 13:58:50.063205 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5112 13:58:50.066671 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5113 13:58:50.070071 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5114 13:58:50.073418 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5115 13:58:50.079932 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5116 13:58:50.083162 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5117 13:58:50.083819
5118 13:58:50.086431 CA PerBit enable=1, Macro0, CA PI delay=33
5119 13:58:50.086899
5120 13:58:50.089883 [CBTSetCACLKResult] CA Dly = 33
5121 13:58:50.090351 CS Dly: 7 (0~38)
5122 13:58:50.090726 ==
5123 13:58:50.093512 Dram Type= 6, Freq= 0, CH_0, rank 1
5124 13:58:50.099621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 13:58:50.100236 ==
5126 13:58:50.103249 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5127 13:58:50.109947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5128 13:58:50.112673 [CA 0] Center 37 (7~68) winsize 62
5129 13:58:50.116047 [CA 1] Center 37 (7~68) winsize 62
5130 13:58:50.119390 [CA 2] Center 34 (4~65) winsize 62
5131 13:58:50.122755 [CA 3] Center 34 (4~65) winsize 62
5132 13:58:50.126168 [CA 4] Center 33 (3~64) winsize 62
5133 13:58:50.130015 [CA 5] Center 32 (2~63) winsize 62
5134 13:58:50.130572
5135 13:58:50.133342 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5136 13:58:50.133898
5137 13:58:50.135773 [CATrainingPosCal] consider 2 rank data
5138 13:58:50.139174 u2DelayCellTimex100 = 270/100 ps
5139 13:58:50.142467 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5140 13:58:50.148850 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5141 13:58:50.152192 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5142 13:58:50.155609 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5143 13:58:50.158947 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5144 13:58:50.162321 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5145 13:58:50.162786
5146 13:58:50.165871 CA PerBit enable=1, Macro0, CA PI delay=33
5147 13:58:50.166429
5148 13:58:50.168652 [CBTSetCACLKResult] CA Dly = 33
5149 13:58:50.172712 CS Dly: 7 (0~39)
5150 13:58:50.173267
5151 13:58:50.175960 ----->DramcWriteLeveling(PI) begin...
5152 13:58:50.176518 ==
5153 13:58:50.179318 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 13:58:50.182198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 13:58:50.182759 ==
5156 13:58:50.185970 Write leveling (Byte 0): 31 => 31
5157 13:58:50.188438 Write leveling (Byte 1): 29 => 29
5158 13:58:50.191825 DramcWriteLeveling(PI) end<-----
5159 13:58:50.192288
5160 13:58:50.192660 ==
5161 13:58:50.196224 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 13:58:50.198667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 13:58:50.199133 ==
5164 13:58:50.201789 [Gating] SW mode calibration
5165 13:58:50.208671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5166 13:58:50.215082 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5167 13:58:50.218445 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5168 13:58:50.221936 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5169 13:58:50.228045 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 13:58:50.232140 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 13:58:50.235153 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 13:58:50.241293 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 13:58:50.244815 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 13:58:50.248058 0 14 28 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (1 0)
5175 13:58:50.254884 0 15 0 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (1 0)
5176 13:58:50.257929 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 13:58:50.264057 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 13:58:50.267853 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 13:58:50.271460 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 13:58:50.277613 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 13:58:50.280924 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 13:58:50.284335 0 15 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5183 13:58:50.287841 1 0 0 | B1->B0 | 3939 4242 | 0 0 | (0 0) (1 1)
5184 13:58:50.294285 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 13:58:50.297210 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 13:58:50.300840 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 13:58:50.307506 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 13:58:50.311151 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 13:58:50.314405 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 13:58:50.320989 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5191 13:58:50.324101 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5192 13:58:50.327416 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5193 13:58:50.333788 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 13:58:50.336710 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 13:58:50.340272 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 13:58:50.346957 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 13:58:50.349715 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 13:58:50.356610 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 13:58:50.360383 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 13:58:50.363988 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 13:58:50.369536 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 13:58:50.373470 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 13:58:50.376587 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 13:58:50.383190 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 13:58:50.386536 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 13:58:50.389707 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5207 13:58:50.396502 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5208 13:58:50.397057 Total UI for P1: 0, mck2ui 16
5209 13:58:50.399487 best dqsien dly found for B0: ( 1, 2, 28)
5210 13:58:50.406156 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 13:58:50.409420 Total UI for P1: 0, mck2ui 16
5212 13:58:50.412999 best dqsien dly found for B1: ( 1, 2, 30)
5213 13:58:50.415771 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5214 13:58:50.419311 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5215 13:58:50.419913
5216 13:58:50.422771 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5217 13:58:50.425895 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5218 13:58:50.429031 [Gating] SW calibration Done
5219 13:58:50.429591 ==
5220 13:58:50.432751 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 13:58:50.435927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 13:58:50.436492 ==
5223 13:58:50.439688 RX Vref Scan: 0
5224 13:58:50.440284
5225 13:58:50.442421 RX Vref 0 -> 0, step: 1
5226 13:58:50.443042
5227 13:58:50.443424 RX Delay -80 -> 252, step: 8
5228 13:58:50.449057 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5229 13:58:50.452452 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5230 13:58:50.455848 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5231 13:58:50.459083 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5232 13:58:50.462123 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5233 13:58:50.465594 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5234 13:58:50.472216 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5235 13:58:50.475421 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5236 13:58:50.478892 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5237 13:58:50.481687 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5238 13:58:50.484959 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5239 13:58:50.492369 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5240 13:58:50.495173 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5241 13:58:50.498123 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5242 13:58:50.501885 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5243 13:58:50.504780 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5244 13:58:50.508704 ==
5245 13:58:50.511587 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 13:58:50.515348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 13:58:50.515659 ==
5248 13:58:50.515878 DQS Delay:
5249 13:58:50.518789 DQS0 = 0, DQS1 = 0
5250 13:58:50.519152 DQM Delay:
5251 13:58:50.521734 DQM0 = 97, DQM1 = 85
5252 13:58:50.522195 DQ Delay:
5253 13:58:50.525202 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5254 13:58:50.528377 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5255 13:58:50.531781 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5256 13:58:50.535123 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5257 13:58:50.535588
5258 13:58:50.535994
5259 13:58:50.536339 ==
5260 13:58:50.538657 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 13:58:50.541856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 13:58:50.542327 ==
5263 13:58:50.542697
5264 13:58:50.545455
5265 13:58:50.546010 TX Vref Scan disable
5266 13:58:50.548134 == TX Byte 0 ==
5267 13:58:50.551455 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5268 13:58:50.554804 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5269 13:58:50.557881 == TX Byte 1 ==
5270 13:58:50.561659 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5271 13:58:50.564507 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5272 13:58:50.564973 ==
5273 13:58:50.568374 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 13:58:50.574530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 13:58:50.575087 ==
5276 13:58:50.575455
5277 13:58:50.575852
5278 13:58:50.576212 TX Vref Scan disable
5279 13:58:50.578864 == TX Byte 0 ==
5280 13:58:50.581993 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5281 13:58:50.588725 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5282 13:58:50.589283 == TX Byte 1 ==
5283 13:58:50.592147 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5284 13:58:50.598786 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5285 13:58:50.599343
5286 13:58:50.599713 [DATLAT]
5287 13:58:50.600143 Freq=933, CH0 RK0
5288 13:58:50.600485
5289 13:58:50.601581 DATLAT Default: 0xd
5290 13:58:50.602047 0, 0xFFFF, sum = 0
5291 13:58:50.605223 1, 0xFFFF, sum = 0
5292 13:58:50.608518 2, 0xFFFF, sum = 0
5293 13:58:50.609084 3, 0xFFFF, sum = 0
5294 13:58:50.612112 4, 0xFFFF, sum = 0
5295 13:58:50.612693 5, 0xFFFF, sum = 0
5296 13:58:50.615386 6, 0xFFFF, sum = 0
5297 13:58:50.616008 7, 0xFFFF, sum = 0
5298 13:58:50.618525 8, 0xFFFF, sum = 0
5299 13:58:50.618993 9, 0xFFFF, sum = 0
5300 13:58:50.621666 10, 0x0, sum = 1
5301 13:58:50.622231 11, 0x0, sum = 2
5302 13:58:50.624941 12, 0x0, sum = 3
5303 13:58:50.625504 13, 0x0, sum = 4
5304 13:58:50.625886 best_step = 11
5305 13:58:50.628017
5306 13:58:50.628480 ==
5307 13:58:50.632065 Dram Type= 6, Freq= 0, CH_0, rank 0
5308 13:58:50.635551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 13:58:50.636052 ==
5310 13:58:50.636422 RX Vref Scan: 1
5311 13:58:50.636766
5312 13:58:50.637892 RX Vref 0 -> 0, step: 1
5313 13:58:50.638352
5314 13:58:50.641675 RX Delay -69 -> 252, step: 4
5315 13:58:50.642136
5316 13:58:50.645299 Set Vref, RX VrefLevel [Byte0]: 60
5317 13:58:50.648421 [Byte1]: 50
5318 13:58:50.651387
5319 13:58:50.651839 Final RX Vref Byte 0 = 60 to rank0
5320 13:58:50.654878 Final RX Vref Byte 1 = 50 to rank0
5321 13:58:50.657904 Final RX Vref Byte 0 = 60 to rank1
5322 13:58:50.661476 Final RX Vref Byte 1 = 50 to rank1==
5323 13:58:50.664368 Dram Type= 6, Freq= 0, CH_0, rank 0
5324 13:58:50.671030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 13:58:50.671419 ==
5326 13:58:50.671656 DQS Delay:
5327 13:58:50.671951 DQS0 = 0, DQS1 = 0
5328 13:58:50.674301 DQM Delay:
5329 13:58:50.674595 DQM0 = 97, DQM1 = 85
5330 13:58:50.677890 DQ Delay:
5331 13:58:50.680949 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5332 13:58:50.684544 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5333 13:58:50.687548 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5334 13:58:50.690901 DQ12 =92, DQ13 =86, DQ14 =96, DQ15 =94
5335 13:58:50.691340
5336 13:58:50.691702
5337 13:58:50.697282 [DQSOSCAuto] RK0, (LSB)MR18= 0x3017, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 406 ps
5338 13:58:50.700713 CH0 RK0: MR19=505, MR18=3017
5339 13:58:50.707753 CH0_RK0: MR19=0x505, MR18=0x3017, DQSOSC=406, MR23=63, INC=65, DEC=43
5340 13:58:50.708330
5341 13:58:50.711138 ----->DramcWriteLeveling(PI) begin...
5342 13:58:50.711697 ==
5343 13:58:50.714162 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 13:58:50.717365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 13:58:50.717832 ==
5346 13:58:50.720724 Write leveling (Byte 0): 34 => 34
5347 13:58:50.723819 Write leveling (Byte 1): 31 => 31
5348 13:58:50.726978 DramcWriteLeveling(PI) end<-----
5349 13:58:50.727528
5350 13:58:50.727954 ==
5351 13:58:50.730334 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 13:58:50.733944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 13:58:50.737816 ==
5354 13:58:50.738279 [Gating] SW mode calibration
5355 13:58:50.746767 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5356 13:58:50.750061 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5357 13:58:50.754304 0 14 0 | B1->B0 | 2c2c 3333 | 0 1 | (0 0) (1 1)
5358 13:58:50.760274 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 13:58:50.763826 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 13:58:50.767008 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 13:58:50.773421 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 13:58:50.776518 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 13:58:50.779992 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 13:58:50.786425 0 14 28 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
5365 13:58:50.789725 0 15 0 | B1->B0 | 2d2d 2828 | 0 0 | (0 0) (0 0)
5366 13:58:50.793099 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 13:58:50.799668 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 13:58:50.802968 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 13:58:50.806482 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 13:58:50.812923 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 13:58:50.816683 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 13:58:50.819166 0 15 28 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
5373 13:58:50.826380 1 0 0 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
5374 13:58:50.829008 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 13:58:50.832362 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 13:58:50.839221 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 13:58:50.842391 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 13:58:50.845837 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 13:58:50.852518 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 13:58:50.856293 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5381 13:58:50.859565 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 13:58:50.866249 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 13:58:50.869856 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 13:58:50.872119 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 13:58:50.878465 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 13:58:50.882982 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 13:58:50.885412 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 13:58:50.892073 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 13:58:50.896394 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 13:58:50.898861 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 13:58:50.905357 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 13:58:50.908784 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 13:58:50.912106 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 13:58:50.919098 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 13:58:50.921892 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 13:58:50.925219 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5397 13:58:50.931985 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 13:58:50.935313 Total UI for P1: 0, mck2ui 16
5399 13:58:50.938739 best dqsien dly found for B0: ( 1, 2, 28)
5400 13:58:50.939294 Total UI for P1: 0, mck2ui 16
5401 13:58:50.944858 best dqsien dly found for B1: ( 1, 2, 28)
5402 13:58:50.948496 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5403 13:58:50.951254 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5404 13:58:50.951752
5405 13:58:50.955032 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5406 13:58:50.958242 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5407 13:58:50.961470 [Gating] SW calibration Done
5408 13:58:50.962182 ==
5409 13:58:50.964746 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 13:58:50.967876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 13:58:50.968377 ==
5412 13:58:50.971690 RX Vref Scan: 0
5413 13:58:50.972215
5414 13:58:50.972741 RX Vref 0 -> 0, step: 1
5415 13:58:50.973234
5416 13:58:50.975103 RX Delay -80 -> 252, step: 8
5417 13:58:50.977938 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5418 13:58:50.984624 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5419 13:58:50.987921 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5420 13:58:50.991212 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5421 13:58:50.994947 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5422 13:58:50.997952 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5423 13:58:51.002408 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5424 13:58:51.007824 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5425 13:58:51.011534 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5426 13:58:51.014449 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5427 13:58:51.018228 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5428 13:58:51.020800 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5429 13:58:51.027968 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5430 13:58:51.031157 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5431 13:58:51.034601 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5432 13:58:51.038411 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5433 13:58:51.038969 ==
5434 13:58:51.041071 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 13:58:51.047505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 13:58:51.048104 ==
5437 13:58:51.048484 DQS Delay:
5438 13:58:51.048831 DQS0 = 0, DQS1 = 0
5439 13:58:51.051107 DQM Delay:
5440 13:58:51.051568 DQM0 = 97, DQM1 = 87
5441 13:58:51.054873 DQ Delay:
5442 13:58:51.057489 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5443 13:58:51.061101 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5444 13:58:51.063604 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5445 13:58:51.067021 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5446 13:58:51.067574
5447 13:58:51.068006
5448 13:58:51.068355 ==
5449 13:58:51.070582 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 13:58:51.073972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 13:58:51.074531 ==
5452 13:58:51.074905
5453 13:58:51.075246
5454 13:58:51.077041 TX Vref Scan disable
5455 13:58:51.077599 == TX Byte 0 ==
5456 13:58:51.083767 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5457 13:58:51.086758 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5458 13:58:51.090224 == TX Byte 1 ==
5459 13:58:51.093729 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5460 13:58:51.097579 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5461 13:58:51.098136 ==
5462 13:58:51.099976 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 13:58:51.103437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 13:58:51.106853 ==
5465 13:58:51.107408
5466 13:58:51.107812
5467 13:58:51.108160 TX Vref Scan disable
5468 13:58:51.110139 == TX Byte 0 ==
5469 13:58:51.113128 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5470 13:58:51.120431 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5471 13:58:51.120997 == TX Byte 1 ==
5472 13:58:51.124220 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5473 13:58:51.129968 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5474 13:58:51.130526
5475 13:58:51.130895 [DATLAT]
5476 13:58:51.131240 Freq=933, CH0 RK1
5477 13:58:51.131573
5478 13:58:51.133365 DATLAT Default: 0xb
5479 13:58:51.133822 0, 0xFFFF, sum = 0
5480 13:58:51.136733 1, 0xFFFF, sum = 0
5481 13:58:51.139968 2, 0xFFFF, sum = 0
5482 13:58:51.140531 3, 0xFFFF, sum = 0
5483 13:58:51.143435 4, 0xFFFF, sum = 0
5484 13:58:51.144063 5, 0xFFFF, sum = 0
5485 13:58:51.146787 6, 0xFFFF, sum = 0
5486 13:58:51.147351 7, 0xFFFF, sum = 0
5487 13:58:51.151116 8, 0xFFFF, sum = 0
5488 13:58:51.151676 9, 0xFFFF, sum = 0
5489 13:58:51.153008 10, 0x0, sum = 1
5490 13:58:51.153476 11, 0x0, sum = 2
5491 13:58:51.156435 12, 0x0, sum = 3
5492 13:58:51.156901 13, 0x0, sum = 4
5493 13:58:51.157274 best_step = 11
5494 13:58:51.159867
5495 13:58:51.160447 ==
5496 13:58:51.163155 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 13:58:51.167060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 13:58:51.167625 ==
5499 13:58:51.168095 RX Vref Scan: 0
5500 13:58:51.168447
5501 13:58:51.169406 RX Vref 0 -> 0, step: 1
5502 13:58:51.169866
5503 13:58:51.172962 RX Delay -61 -> 252, step: 4
5504 13:58:51.179772 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5505 13:58:51.182812 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5506 13:58:51.185637 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5507 13:58:51.189493 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5508 13:58:51.192938 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5509 13:58:51.196493 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5510 13:58:51.202494 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5511 13:58:51.206371 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5512 13:58:51.209538 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5513 13:58:51.212183 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5514 13:58:51.216242 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5515 13:58:51.222583 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5516 13:58:51.226386 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5517 13:58:51.228753 iDelay=203, Bit 13, Center 92 (-5 ~ 190) 196
5518 13:58:51.232461 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5519 13:58:51.235847 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5520 13:58:51.239354 ==
5521 13:58:51.242665 Dram Type= 6, Freq= 0, CH_0, rank 1
5522 13:58:51.245705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 13:58:51.246266 ==
5524 13:58:51.246633 DQS Delay:
5525 13:58:51.248952 DQS0 = 0, DQS1 = 0
5526 13:58:51.249505 DQM Delay:
5527 13:58:51.252204 DQM0 = 95, DQM1 = 86
5528 13:58:51.252663 DQ Delay:
5529 13:58:51.255678 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5530 13:58:51.259326 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5531 13:58:51.262230 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5532 13:58:51.265587 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5533 13:58:51.266051
5534 13:58:51.266416
5535 13:58:51.272078 [DQSOSCAuto] RK1, (LSB)MR18= 0x2dfd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 407 ps
5536 13:58:51.275553 CH0 RK1: MR19=504, MR18=2DFD
5537 13:58:51.281743 CH0_RK1: MR19=0x504, MR18=0x2DFD, DQSOSC=407, MR23=63, INC=65, DEC=43
5538 13:58:51.285241 [RxdqsGatingPostProcess] freq 933
5539 13:58:51.292323 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5540 13:58:51.295413 best DQS0 dly(2T, 0.5T) = (0, 10)
5541 13:58:51.296016 best DQS1 dly(2T, 0.5T) = (0, 10)
5542 13:58:51.298724 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5543 13:58:51.302155 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5544 13:58:51.305576 best DQS0 dly(2T, 0.5T) = (0, 10)
5545 13:58:51.308721 best DQS1 dly(2T, 0.5T) = (0, 10)
5546 13:58:51.312062 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5547 13:58:51.315105 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5548 13:58:51.318917 Pre-setting of DQS Precalculation
5549 13:58:51.324774 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5550 13:58:51.325271 ==
5551 13:58:51.328002 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 13:58:51.332201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 13:58:51.332777 ==
5554 13:58:51.338204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5555 13:58:51.341296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5556 13:58:51.345528 [CA 0] Center 37 (7~67) winsize 61
5557 13:58:51.348918 [CA 1] Center 37 (6~68) winsize 63
5558 13:58:51.352113 [CA 2] Center 34 (4~65) winsize 62
5559 13:58:51.355894 [CA 3] Center 33 (3~64) winsize 62
5560 13:58:51.359234 [CA 4] Center 34 (4~65) winsize 62
5561 13:58:51.362627 [CA 5] Center 33 (3~64) winsize 62
5562 13:58:51.363091
5563 13:58:51.365690 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5564 13:58:51.366154
5565 13:58:51.368709 [CATrainingPosCal] consider 1 rank data
5566 13:58:51.372389 u2DelayCellTimex100 = 270/100 ps
5567 13:58:51.375590 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5568 13:58:51.382039 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5569 13:58:51.385306 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5570 13:58:51.388690 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5571 13:58:51.391771 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5572 13:58:51.394988 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5573 13:58:51.395503
5574 13:58:51.398511 CA PerBit enable=1, Macro0, CA PI delay=33
5575 13:58:51.399029
5576 13:58:51.402208 [CBTSetCACLKResult] CA Dly = 33
5577 13:58:51.404999 CS Dly: 6 (0~37)
5578 13:58:51.405511 ==
5579 13:58:51.408764 Dram Type= 6, Freq= 0, CH_1, rank 1
5580 13:58:51.411907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 13:58:51.412423 ==
5582 13:58:51.418235 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5583 13:58:51.421467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5584 13:58:51.425984 [CA 0] Center 37 (7~67) winsize 61
5585 13:58:51.429250 [CA 1] Center 37 (7~68) winsize 62
5586 13:58:51.432584 [CA 2] Center 34 (4~65) winsize 62
5587 13:58:51.435346 [CA 3] Center 34 (3~65) winsize 63
5588 13:58:51.438725 [CA 4] Center 34 (4~65) winsize 62
5589 13:58:51.441766 [CA 5] Center 33 (3~64) winsize 62
5590 13:58:51.442318
5591 13:58:51.445659 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5592 13:58:51.446145
5593 13:58:51.448261 [CATrainingPosCal] consider 2 rank data
5594 13:58:51.451531 u2DelayCellTimex100 = 270/100 ps
5595 13:58:51.458215 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5596 13:58:51.461752 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5597 13:58:51.464797 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5598 13:58:51.468280 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5599 13:58:51.471658 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5600 13:58:51.475095 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5601 13:58:51.475620
5602 13:58:51.478216 CA PerBit enable=1, Macro0, CA PI delay=33
5603 13:58:51.478637
5604 13:58:51.481232 [CBTSetCACLKResult] CA Dly = 33
5605 13:58:51.485385 CS Dly: 7 (0~39)
5606 13:58:51.485902
5607 13:58:51.487939 ----->DramcWriteLeveling(PI) begin...
5608 13:58:51.488373 ==
5609 13:58:51.491236 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 13:58:51.494403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 13:58:51.494823 ==
5612 13:58:51.497789 Write leveling (Byte 0): 25 => 25
5613 13:58:51.501877 Write leveling (Byte 1): 27 => 27
5614 13:58:51.504414 DramcWriteLeveling(PI) end<-----
5615 13:58:51.504837
5616 13:58:51.505171 ==
5617 13:58:51.507661 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 13:58:51.510783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 13:58:51.511303 ==
5620 13:58:51.514851 [Gating] SW mode calibration
5621 13:58:51.521066 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5622 13:58:51.528630 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5623 13:58:51.531237 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 13:58:51.537878 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 13:58:51.541370 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 13:58:51.543707 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 13:58:51.550494 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 13:58:51.553608 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5629 13:58:51.557773 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5630 13:58:51.563529 0 14 28 | B1->B0 | 2c2c 2525 | 1 1 | (1 0) (1 0)
5631 13:58:51.567161 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 13:58:51.570167 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 13:58:51.576569 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 13:58:51.580336 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 13:58:51.583827 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 13:58:51.590245 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 13:58:51.593459 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5638 13:58:51.597233 0 15 28 | B1->B0 | 3232 3636 | 0 0 | (0 0) (0 0)
5639 13:58:51.604081 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 13:58:51.606963 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 13:58:51.610300 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 13:58:51.617145 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 13:58:51.619791 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 13:58:51.623609 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5645 13:58:51.629877 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5646 13:58:51.633328 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 13:58:51.636956 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5648 13:58:51.643333 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 13:58:51.646348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 13:58:51.649509 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 13:58:51.656306 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 13:58:51.659355 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 13:58:51.662696 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 13:58:51.669363 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 13:58:51.672674 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 13:58:51.676034 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 13:58:51.679578 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 13:58:51.685876 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 13:58:51.688848 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 13:58:51.695789 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 13:58:51.699125 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5662 13:58:51.702235 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5663 13:58:51.708934 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 13:58:51.709501 Total UI for P1: 0, mck2ui 16
5665 13:58:51.712332 best dqsien dly found for B0: ( 1, 2, 26)
5666 13:58:51.716350 Total UI for P1: 0, mck2ui 16
5667 13:58:51.718862 best dqsien dly found for B1: ( 1, 2, 26)
5668 13:58:51.722418 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5669 13:58:51.728564 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5670 13:58:51.729128
5671 13:58:51.732072 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5672 13:58:51.735686 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5673 13:58:51.738529 [Gating] SW calibration Done
5674 13:58:51.739093 ==
5675 13:58:51.741761 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 13:58:51.746028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 13:58:51.746598 ==
5678 13:58:51.748497 RX Vref Scan: 0
5679 13:58:51.748959
5680 13:58:51.749329 RX Vref 0 -> 0, step: 1
5681 13:58:51.749677
5682 13:58:51.751331 RX Delay -80 -> 252, step: 8
5683 13:58:51.755577 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5684 13:58:51.761810 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5685 13:58:51.765265 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5686 13:58:51.767945 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5687 13:58:51.771234 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5688 13:58:51.775271 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5689 13:58:51.778153 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5690 13:58:51.784703 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5691 13:58:51.787801 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5692 13:58:51.791351 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5693 13:58:51.794747 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5694 13:58:51.797930 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5695 13:58:51.804342 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5696 13:58:51.807544 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5697 13:58:51.811376 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5698 13:58:51.814277 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5699 13:58:51.814838 ==
5700 13:58:51.817749 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 13:58:51.820958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 13:58:51.825346 ==
5703 13:58:51.825871 DQS Delay:
5704 13:58:51.826211 DQS0 = 0, DQS1 = 0
5705 13:58:51.827876 DQM Delay:
5706 13:58:51.828400 DQM0 = 102, DQM1 = 92
5707 13:58:51.830978 DQ Delay:
5708 13:58:51.831494 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5709 13:58:51.835313 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5710 13:58:51.837976 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =83
5711 13:58:51.844461 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5712 13:58:51.845011
5713 13:58:51.845353
5714 13:58:51.845665 ==
5715 13:58:51.847247 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 13:58:51.850899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 13:58:51.851324 ==
5718 13:58:51.851662
5719 13:58:51.852174
5720 13:58:51.854354 TX Vref Scan disable
5721 13:58:51.854871 == TX Byte 0 ==
5722 13:58:51.860934 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5723 13:58:51.864985 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5724 13:58:51.865528 == TX Byte 1 ==
5725 13:58:51.871177 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5726 13:58:51.873732 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5727 13:58:51.874150 ==
5728 13:58:51.877297 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 13:58:51.880512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 13:58:51.880954 ==
5731 13:58:51.881285
5732 13:58:51.881591
5733 13:58:51.883902 TX Vref Scan disable
5734 13:58:51.888183 == TX Byte 0 ==
5735 13:58:51.890419 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5736 13:58:51.893693 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5737 13:58:51.897602 == TX Byte 1 ==
5738 13:58:51.901288 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5739 13:58:51.903945 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5740 13:58:51.904520
5741 13:58:51.907624 [DATLAT]
5742 13:58:51.908256 Freq=933, CH1 RK0
5743 13:58:51.908746
5744 13:58:51.910650 DATLAT Default: 0xd
5745 13:58:51.911124 0, 0xFFFF, sum = 0
5746 13:58:51.913770 1, 0xFFFF, sum = 0
5747 13:58:51.914255 2, 0xFFFF, sum = 0
5748 13:58:51.917139 3, 0xFFFF, sum = 0
5749 13:58:51.917622 4, 0xFFFF, sum = 0
5750 13:58:51.920460 5, 0xFFFF, sum = 0
5751 13:58:51.923969 6, 0xFFFF, sum = 0
5752 13:58:51.924567 7, 0xFFFF, sum = 0
5753 13:58:51.926760 8, 0xFFFF, sum = 0
5754 13:58:51.927338 9, 0xFFFF, sum = 0
5755 13:58:51.930011 10, 0x0, sum = 1
5756 13:58:51.930575 11, 0x0, sum = 2
5757 13:58:51.931152 12, 0x0, sum = 3
5758 13:58:51.933894 13, 0x0, sum = 4
5759 13:58:51.934464 best_step = 11
5760 13:58:51.934839
5761 13:58:51.936525 ==
5762 13:58:51.940199 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 13:58:51.943508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 13:58:51.944114 ==
5765 13:58:51.944495 RX Vref Scan: 1
5766 13:58:51.944843
5767 13:58:51.946496 RX Vref 0 -> 0, step: 1
5768 13:58:51.946957
5769 13:58:51.949748 RX Delay -61 -> 252, step: 4
5770 13:58:51.950214
5771 13:58:51.953539 Set Vref, RX VrefLevel [Byte0]: 47
5772 13:58:51.956606 [Byte1]: 60
5773 13:58:51.957132
5774 13:58:51.959848 Final RX Vref Byte 0 = 47 to rank0
5775 13:58:51.963077 Final RX Vref Byte 1 = 60 to rank0
5776 13:58:51.966408 Final RX Vref Byte 0 = 47 to rank1
5777 13:58:51.969636 Final RX Vref Byte 1 = 60 to rank1==
5778 13:58:51.973888 Dram Type= 6, Freq= 0, CH_1, rank 0
5779 13:58:51.976159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 13:58:51.979874 ==
5781 13:58:51.980446 DQS Delay:
5782 13:58:51.980793 DQS0 = 0, DQS1 = 0
5783 13:58:51.982751 DQM Delay:
5784 13:58:51.983173 DQM0 = 101, DQM1 = 94
5785 13:58:51.986258 DQ Delay:
5786 13:58:51.989558 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5787 13:58:51.992882 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5788 13:58:51.996325 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =86
5789 13:58:51.999888 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5790 13:58:52.000416
5791 13:58:52.000896
5792 13:58:52.006674 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5793 13:58:52.009852 CH1 RK0: MR19=505, MR18=1D0D
5794 13:58:52.016156 CH1_RK0: MR19=0x505, MR18=0x1D0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5795 13:58:52.016736
5796 13:58:52.019292 ----->DramcWriteLeveling(PI) begin...
5797 13:58:52.019821 ==
5798 13:58:52.022930 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 13:58:52.026592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 13:58:52.027209 ==
5801 13:58:52.029387 Write leveling (Byte 0): 27 => 27
5802 13:58:52.032317 Write leveling (Byte 1): 29 => 29
5803 13:58:52.035962 DramcWriteLeveling(PI) end<-----
5804 13:58:52.036547
5805 13:58:52.037071 ==
5806 13:58:52.039433 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 13:58:52.042768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 13:58:52.045676 ==
5809 13:58:52.046146 [Gating] SW mode calibration
5810 13:58:52.055891 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5811 13:58:52.059115 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5812 13:58:52.063886 0 14 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5813 13:58:52.068722 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 13:58:52.072285 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 13:58:52.075658 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 13:58:52.082481 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 13:58:52.085557 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 13:58:52.089503 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
5819 13:58:52.095360 0 14 28 | B1->B0 | 2727 3131 | 0 1 | (0 0) (1 0)
5820 13:58:52.098716 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5821 13:58:52.101903 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 13:58:52.108270 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 13:58:52.112067 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 13:58:52.115659 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 13:58:52.122365 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 13:58:52.125631 0 15 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5827 13:58:52.128685 0 15 28 | B1->B0 | 4242 2f2f | 0 0 | (0 0) (0 0)
5828 13:58:52.134844 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5829 13:58:52.138044 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 13:58:52.141753 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 13:58:52.147808 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 13:58:52.151338 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 13:58:52.154643 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 13:58:52.161218 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5835 13:58:52.164468 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5836 13:58:52.167455 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 13:58:52.174509 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 13:58:52.177798 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 13:58:52.181213 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 13:58:52.187509 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 13:58:52.190937 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 13:58:52.193955 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 13:58:52.201081 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 13:58:52.204070 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 13:58:52.207667 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 13:58:52.214075 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 13:58:52.217393 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 13:58:52.220393 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 13:58:52.227138 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 13:58:52.230604 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5851 13:58:52.233600 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5852 13:58:52.237041 Total UI for P1: 0, mck2ui 16
5853 13:58:52.240001 best dqsien dly found for B1: ( 1, 2, 24)
5854 13:58:52.246949 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 13:58:52.247523 Total UI for P1: 0, mck2ui 16
5856 13:58:52.253407 best dqsien dly found for B0: ( 1, 2, 26)
5857 13:58:52.257206 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5858 13:58:52.260200 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5859 13:58:52.260687
5860 13:58:52.263221 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5861 13:58:52.266431 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5862 13:58:52.270030 [Gating] SW calibration Done
5863 13:58:52.270499 ==
5864 13:58:52.273266 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 13:58:52.277105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 13:58:52.277676 ==
5867 13:58:52.280323 RX Vref Scan: 0
5868 13:58:52.280792
5869 13:58:52.281169 RX Vref 0 -> 0, step: 1
5870 13:58:52.283007
5871 13:58:52.283472 RX Delay -80 -> 252, step: 8
5872 13:58:52.290309 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5873 13:58:52.293050 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5874 13:58:52.296261 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5875 13:58:52.299487 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5876 13:58:52.303078 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5877 13:58:52.306995 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5878 13:58:52.312961 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5879 13:58:52.316282 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5880 13:58:52.320135 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5881 13:58:52.322711 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5882 13:58:52.326594 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5883 13:58:52.333040 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5884 13:58:52.336384 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5885 13:58:52.339465 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5886 13:58:52.342875 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5887 13:58:52.346218 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5888 13:58:52.346784 ==
5889 13:58:52.349238 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 13:58:52.355953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 13:58:52.356526 ==
5892 13:58:52.356951 DQS Delay:
5893 13:58:52.358833 DQS0 = 0, DQS1 = 0
5894 13:58:52.359306 DQM Delay:
5895 13:58:52.359683 DQM0 = 99, DQM1 = 91
5896 13:58:52.362427 DQ Delay:
5897 13:58:52.365860 DQ0 =107, DQ1 =91, DQ2 =91, DQ3 =99
5898 13:58:52.369364 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5899 13:58:52.372246 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5900 13:58:52.375421 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5901 13:58:52.375998
5902 13:58:52.376497
5903 13:58:52.376846 ==
5904 13:58:52.379160 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 13:58:52.382210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 13:58:52.382639 ==
5907 13:58:52.382984
5908 13:58:52.383299
5909 13:58:52.385833 TX Vref Scan disable
5910 13:58:52.388752 == TX Byte 0 ==
5911 13:58:52.392283 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5912 13:58:52.395569 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5913 13:58:52.398842 == TX Byte 1 ==
5914 13:58:52.402413 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5915 13:58:52.405624 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5916 13:58:52.406253 ==
5917 13:58:52.408601 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 13:58:52.412447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 13:58:52.415380 ==
5920 13:58:52.415933
5921 13:58:52.416274
5922 13:58:52.416587 TX Vref Scan disable
5923 13:58:52.419788 == TX Byte 0 ==
5924 13:58:52.422350 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5925 13:58:52.428444 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5926 13:58:52.428963 == TX Byte 1 ==
5927 13:58:52.431838 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5928 13:58:52.438592 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5929 13:58:52.439312
5930 13:58:52.439800 [DATLAT]
5931 13:58:52.440172 Freq=933, CH1 RK1
5932 13:58:52.440520
5933 13:58:52.441768 DATLAT Default: 0xb
5934 13:58:52.442232 0, 0xFFFF, sum = 0
5935 13:58:52.445521 1, 0xFFFF, sum = 0
5936 13:58:52.448450 2, 0xFFFF, sum = 0
5937 13:58:52.448925 3, 0xFFFF, sum = 0
5938 13:58:52.452088 4, 0xFFFF, sum = 0
5939 13:58:52.452631 5, 0xFFFF, sum = 0
5940 13:58:52.454908 6, 0xFFFF, sum = 0
5941 13:58:52.455370 7, 0xFFFF, sum = 0
5942 13:58:52.458278 8, 0xFFFF, sum = 0
5943 13:58:52.458705 9, 0xFFFF, sum = 0
5944 13:58:52.461987 10, 0x0, sum = 1
5945 13:58:52.462414 11, 0x0, sum = 2
5946 13:58:52.465444 12, 0x0, sum = 3
5947 13:58:52.465872 13, 0x0, sum = 4
5948 13:58:52.466217 best_step = 11
5949 13:58:52.467995
5950 13:58:52.468417 ==
5951 13:58:52.471864 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 13:58:52.475016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 13:58:52.475442 ==
5954 13:58:52.475839 RX Vref Scan: 0
5955 13:58:52.476241
5956 13:58:52.478779 RX Vref 0 -> 0, step: 1
5957 13:58:52.479298
5958 13:58:52.481990 RX Delay -61 -> 252, step: 4
5959 13:58:52.488601 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5960 13:58:52.491575 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
5961 13:58:52.495267 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5962 13:58:52.498484 iDelay=207, Bit 3, Center 100 (19 ~ 182) 164
5963 13:58:52.501651 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5964 13:58:52.504710 iDelay=207, Bit 5, Center 112 (27 ~ 198) 172
5965 13:58:52.511261 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5966 13:58:52.514824 iDelay=207, Bit 7, Center 98 (11 ~ 186) 176
5967 13:58:52.518339 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5968 13:58:52.521259 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5969 13:58:52.524543 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5970 13:58:52.531171 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5971 13:58:52.535272 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5972 13:58:52.537635 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
5973 13:58:52.540807 iDelay=207, Bit 14, Center 106 (19 ~ 194) 176
5974 13:58:52.548268 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5975 13:58:52.548852 ==
5976 13:58:52.550654 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 13:58:52.554101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 13:58:52.554570 ==
5979 13:58:52.555080 DQS Delay:
5980 13:58:52.557647 DQS0 = 0, DQS1 = 0
5981 13:58:52.558215 DQM Delay:
5982 13:58:52.561163 DQM0 = 102, DQM1 = 94
5983 13:58:52.561728 DQ Delay:
5984 13:58:52.564469 DQ0 =106, DQ1 =96, DQ2 =90, DQ3 =100
5985 13:58:52.567344 DQ4 =100, DQ5 =112, DQ6 =114, DQ7 =98
5986 13:58:52.570555 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
5987 13:58:52.574478 DQ12 =102, DQ13 =102, DQ14 =106, DQ15 =102
5988 13:58:52.575047
5989 13:58:52.575424
5990 13:58:52.583523 [DQSOSCAuto] RK1, (LSB)MR18= 0xa04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
5991 13:58:52.584132 CH1 RK1: MR19=505, MR18=A04
5992 13:58:52.590652 CH1_RK1: MR19=0x505, MR18=0xA04, DQSOSC=418, MR23=63, INC=62, DEC=41
5993 13:58:52.593572 [RxdqsGatingPostProcess] freq 933
5994 13:58:52.600358 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5995 13:58:52.603825 best DQS0 dly(2T, 0.5T) = (0, 10)
5996 13:58:52.607189 best DQS1 dly(2T, 0.5T) = (0, 10)
5997 13:58:52.610378 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5998 13:58:52.613504 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5999 13:58:52.616761 best DQS0 dly(2T, 0.5T) = (0, 10)
6000 13:58:52.619964 best DQS1 dly(2T, 0.5T) = (0, 10)
6001 13:58:52.623338 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6002 13:58:52.627111 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6003 13:58:52.627767 Pre-setting of DQS Precalculation
6004 13:58:52.633278 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6005 13:58:52.640222 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6006 13:58:52.646461 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6007 13:58:52.647072
6008 13:58:52.647454
6009 13:58:52.649535 [Calibration Summary] 1866 Mbps
6010 13:58:52.653512 CH 0, Rank 0
6011 13:58:52.654109 SW Impedance : PASS
6012 13:58:52.656684 DUTY Scan : NO K
6013 13:58:52.659965 ZQ Calibration : PASS
6014 13:58:52.660528 Jitter Meter : NO K
6015 13:58:52.663317 CBT Training : PASS
6016 13:58:52.666260 Write leveling : PASS
6017 13:58:52.666725 RX DQS gating : PASS
6018 13:58:52.669664 RX DQ/DQS(RDDQC) : PASS
6019 13:58:52.670160 TX DQ/DQS : PASS
6020 13:58:52.672976 RX DATLAT : PASS
6021 13:58:52.676656 RX DQ/DQS(Engine): PASS
6022 13:58:52.677364 TX OE : NO K
6023 13:58:52.679552 All Pass.
6024 13:58:52.680062
6025 13:58:52.680436 CH 0, Rank 1
6026 13:58:52.683014 SW Impedance : PASS
6027 13:58:52.683577 DUTY Scan : NO K
6028 13:58:52.686379 ZQ Calibration : PASS
6029 13:58:52.689418 Jitter Meter : NO K
6030 13:58:52.689933 CBT Training : PASS
6031 13:58:52.693410 Write leveling : PASS
6032 13:58:52.696267 RX DQS gating : PASS
6033 13:58:52.696689 RX DQ/DQS(RDDQC) : PASS
6034 13:58:52.699339 TX DQ/DQS : PASS
6035 13:58:52.702632 RX DATLAT : PASS
6036 13:58:52.703128 RX DQ/DQS(Engine): PASS
6037 13:58:52.706329 TX OE : NO K
6038 13:58:52.706851 All Pass.
6039 13:58:52.707214
6040 13:58:52.709361 CH 1, Rank 0
6041 13:58:52.709782 SW Impedance : PASS
6042 13:58:52.712959 DUTY Scan : NO K
6043 13:58:52.715889 ZQ Calibration : PASS
6044 13:58:52.716311 Jitter Meter : NO K
6045 13:58:52.719961 CBT Training : PASS
6046 13:58:52.723093 Write leveling : PASS
6047 13:58:52.723619 RX DQS gating : PASS
6048 13:58:52.726124 RX DQ/DQS(RDDQC) : PASS
6049 13:58:52.729148 TX DQ/DQS : PASS
6050 13:58:52.729670 RX DATLAT : PASS
6051 13:58:52.732622 RX DQ/DQS(Engine): PASS
6052 13:58:52.733044 TX OE : NO K
6053 13:58:52.735983 All Pass.
6054 13:58:52.736497
6055 13:58:52.736837 CH 1, Rank 1
6056 13:58:52.738813 SW Impedance : PASS
6057 13:58:52.743153 DUTY Scan : NO K
6058 13:58:52.743573 ZQ Calibration : PASS
6059 13:58:52.745605 Jitter Meter : NO K
6060 13:58:52.746024 CBT Training : PASS
6061 13:58:52.748890 Write leveling : PASS
6062 13:58:52.751931 RX DQS gating : PASS
6063 13:58:52.752353 RX DQ/DQS(RDDQC) : PASS
6064 13:58:52.755551 TX DQ/DQS : PASS
6065 13:58:52.759167 RX DATLAT : PASS
6066 13:58:52.759685 RX DQ/DQS(Engine): PASS
6067 13:58:52.762179 TX OE : NO K
6068 13:58:52.762604 All Pass.
6069 13:58:52.762942
6070 13:58:52.765925 DramC Write-DBI off
6071 13:58:52.768900 PER_BANK_REFRESH: Hybrid Mode
6072 13:58:52.769325 TX_TRACKING: ON
6073 13:58:52.779233 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6074 13:58:52.782174 [FAST_K] Save calibration result to emmc
6075 13:58:52.785467 dramc_set_vcore_voltage set vcore to 650000
6076 13:58:52.788664 Read voltage for 400, 6
6077 13:58:52.789178 Vio18 = 0
6078 13:58:52.789521 Vcore = 650000
6079 13:58:52.792095 Vdram = 0
6080 13:58:52.792636 Vddq = 0
6081 13:58:52.792979 Vmddr = 0
6082 13:58:52.798762 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6083 13:58:52.802597 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6084 13:58:52.805401 MEM_TYPE=3, freq_sel=20
6085 13:58:52.808651 sv_algorithm_assistance_LP4_800
6086 13:58:52.812252 ============ PULL DRAM RESETB DOWN ============
6087 13:58:52.815084 ========== PULL DRAM RESETB DOWN end =========
6088 13:58:52.822241 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6089 13:58:52.824952 ===================================
6090 13:58:52.828050 LPDDR4 DRAM CONFIGURATION
6091 13:58:52.832698 ===================================
6092 13:58:52.833217 EX_ROW_EN[0] = 0x0
6093 13:58:52.834663 EX_ROW_EN[1] = 0x0
6094 13:58:52.835142 LP4Y_EN = 0x0
6095 13:58:52.838969 WORK_FSP = 0x0
6096 13:58:52.839527 WL = 0x2
6097 13:58:52.841297 RL = 0x2
6098 13:58:52.841919 BL = 0x2
6099 13:58:52.845143 RPST = 0x0
6100 13:58:52.845670 RD_PRE = 0x0
6101 13:58:52.847952 WR_PRE = 0x1
6102 13:58:52.851345 WR_PST = 0x0
6103 13:58:52.852089 DBI_WR = 0x0
6104 13:58:52.854666 DBI_RD = 0x0
6105 13:58:52.855131 OTF = 0x1
6106 13:58:52.858191 ===================================
6107 13:58:52.861744 ===================================
6108 13:58:52.862317 ANA top config
6109 13:58:52.864868 ===================================
6110 13:58:52.868028 DLL_ASYNC_EN = 0
6111 13:58:52.871116 ALL_SLAVE_EN = 1
6112 13:58:52.874822 NEW_RANK_MODE = 1
6113 13:58:52.877899 DLL_IDLE_MODE = 1
6114 13:58:52.878468 LP45_APHY_COMB_EN = 1
6115 13:58:52.881350 TX_ODT_DIS = 1
6116 13:58:52.884488 NEW_8X_MODE = 1
6117 13:58:52.887518 ===================================
6118 13:58:52.890829 ===================================
6119 13:58:52.894472 data_rate = 800
6120 13:58:52.897414 CKR = 1
6121 13:58:52.901239 DQ_P2S_RATIO = 4
6122 13:58:52.904200 ===================================
6123 13:58:52.904781 CA_P2S_RATIO = 4
6124 13:58:52.907720 DQ_CA_OPEN = 0
6125 13:58:52.910995 DQ_SEMI_OPEN = 1
6126 13:58:52.914406 CA_SEMI_OPEN = 1
6127 13:58:52.917478 CA_FULL_RATE = 0
6128 13:58:52.920709 DQ_CKDIV4_EN = 0
6129 13:58:52.921224 CA_CKDIV4_EN = 1
6130 13:58:52.923678 CA_PREDIV_EN = 0
6131 13:58:52.927209 PH8_DLY = 0
6132 13:58:52.931128 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6133 13:58:52.933748 DQ_AAMCK_DIV = 0
6134 13:58:52.937992 CA_AAMCK_DIV = 0
6135 13:58:52.938564 CA_ADMCK_DIV = 4
6136 13:58:52.940204 DQ_TRACK_CA_EN = 0
6137 13:58:52.943795 CA_PICK = 800
6138 13:58:52.947928 CA_MCKIO = 400
6139 13:58:52.950531 MCKIO_SEMI = 400
6140 13:58:52.954074 PLL_FREQ = 3016
6141 13:58:52.957334 DQ_UI_PI_RATIO = 32
6142 13:58:52.960503 CA_UI_PI_RATIO = 32
6143 13:58:52.963704 ===================================
6144 13:58:52.966754 ===================================
6145 13:58:52.967228 memory_type:LPDDR4
6146 13:58:52.970423 GP_NUM : 10
6147 13:58:52.973292 SRAM_EN : 1
6148 13:58:52.973754 MD32_EN : 0
6149 13:58:52.976451 ===================================
6150 13:58:52.980724 [ANA_INIT] >>>>>>>>>>>>>>
6151 13:58:52.983614 <<<<<< [CONFIGURE PHASE]: ANA_TX
6152 13:58:52.986357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6153 13:58:52.989794 ===================================
6154 13:58:52.993211 data_rate = 800,PCW = 0X7400
6155 13:58:52.996694 ===================================
6156 13:58:53.000299 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6157 13:58:53.003416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 13:58:53.016107 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 13:58:53.019897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6160 13:58:53.022979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6161 13:58:53.025756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6162 13:58:53.029220 [ANA_INIT] flow start
6163 13:58:53.032426 [ANA_INIT] PLL >>>>>>>>
6164 13:58:53.032893 [ANA_INIT] PLL <<<<<<<<
6165 13:58:53.035944 [ANA_INIT] MIDPI >>>>>>>>
6166 13:58:53.039922 [ANA_INIT] MIDPI <<<<<<<<
6167 13:58:53.040489 [ANA_INIT] DLL >>>>>>>>
6168 13:58:53.042867 [ANA_INIT] flow end
6169 13:58:53.045892 ============ LP4 DIFF to SE enter ============
6170 13:58:53.049275 ============ LP4 DIFF to SE exit ============
6171 13:58:53.052276 [ANA_INIT] <<<<<<<<<<<<<
6172 13:58:53.055682 [Flow] Enable top DCM control >>>>>
6173 13:58:53.059072 [Flow] Enable top DCM control <<<<<
6174 13:58:53.062742 Enable DLL master slave shuffle
6175 13:58:53.068835 ==============================================================
6176 13:58:53.069393 Gating Mode config
6177 13:58:53.075508 ==============================================================
6178 13:58:53.078870 Config description:
6179 13:58:53.085476 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6180 13:58:53.092339 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6181 13:58:53.098836 SELPH_MODE 0: By rank 1: By Phase
6182 13:58:53.105439 ==============================================================
6183 13:58:53.106005 GAT_TRACK_EN = 0
6184 13:58:53.108543 RX_GATING_MODE = 2
6185 13:58:53.112250 RX_GATING_TRACK_MODE = 2
6186 13:58:53.115236 SELPH_MODE = 1
6187 13:58:53.118733 PICG_EARLY_EN = 1
6188 13:58:53.122059 VALID_LAT_VALUE = 1
6189 13:58:53.128632 ==============================================================
6190 13:58:53.131516 Enter into Gating configuration >>>>
6191 13:58:53.134901 Exit from Gating configuration <<<<
6192 13:58:53.138614 Enter into DVFS_PRE_config >>>>>
6193 13:58:53.148340 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6194 13:58:53.151687 Exit from DVFS_PRE_config <<<<<
6195 13:58:53.154943 Enter into PICG configuration >>>>
6196 13:58:53.158452 Exit from PICG configuration <<<<
6197 13:58:53.161951 [RX_INPUT] configuration >>>>>
6198 13:58:53.164700 [RX_INPUT] configuration <<<<<
6199 13:58:53.167890 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6200 13:58:53.174276 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6201 13:58:53.181917 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 13:58:53.188007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 13:58:53.191178 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 13:58:53.197658 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 13:58:53.201376 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6206 13:58:53.207847 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6207 13:58:53.211318 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6208 13:58:53.214449 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6209 13:58:53.218316 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6210 13:58:53.224188 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 13:58:53.227705 ===================================
6212 13:58:53.228307 LPDDR4 DRAM CONFIGURATION
6213 13:58:53.231278 ===================================
6214 13:58:53.234194 EX_ROW_EN[0] = 0x0
6215 13:58:53.237204 EX_ROW_EN[1] = 0x0
6216 13:58:53.237761 LP4Y_EN = 0x0
6217 13:58:53.241358 WORK_FSP = 0x0
6218 13:58:53.241916 WL = 0x2
6219 13:58:53.243801 RL = 0x2
6220 13:58:53.244268 BL = 0x2
6221 13:58:53.247315 RPST = 0x0
6222 13:58:53.247926 RD_PRE = 0x0
6223 13:58:53.250465 WR_PRE = 0x1
6224 13:58:53.251103 WR_PST = 0x0
6225 13:58:53.253532 DBI_WR = 0x0
6226 13:58:53.253997 DBI_RD = 0x0
6227 13:58:53.257044 OTF = 0x1
6228 13:58:53.260353 ===================================
6229 13:58:53.264754 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6230 13:58:53.266781 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6231 13:58:53.273515 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6232 13:58:53.276507 ===================================
6233 13:58:53.279880 LPDDR4 DRAM CONFIGURATION
6234 13:58:53.280347 ===================================
6235 13:58:53.283238 EX_ROW_EN[0] = 0x10
6236 13:58:53.286730 EX_ROW_EN[1] = 0x0
6237 13:58:53.287308 LP4Y_EN = 0x0
6238 13:58:53.290323 WORK_FSP = 0x0
6239 13:58:53.290919 WL = 0x2
6240 13:58:53.293146 RL = 0x2
6241 13:58:53.293611 BL = 0x2
6242 13:58:53.296811 RPST = 0x0
6243 13:58:53.297484 RD_PRE = 0x0
6244 13:58:53.300724 WR_PRE = 0x1
6245 13:58:53.301291 WR_PST = 0x0
6246 13:58:53.304439 DBI_WR = 0x0
6247 13:58:53.305006 DBI_RD = 0x0
6248 13:58:53.306402 OTF = 0x1
6249 13:58:53.309676 ===================================
6250 13:58:53.316979 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6251 13:58:53.319885 nWR fixed to 30
6252 13:58:53.323860 [ModeRegInit_LP4] CH0 RK0
6253 13:58:53.324424 [ModeRegInit_LP4] CH0 RK1
6254 13:58:53.327622 [ModeRegInit_LP4] CH1 RK0
6255 13:58:53.329841 [ModeRegInit_LP4] CH1 RK1
6256 13:58:53.330400 match AC timing 19
6257 13:58:53.336673 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6258 13:58:53.339909 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6259 13:58:53.342793 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6260 13:58:53.349509 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6261 13:58:53.352727 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6262 13:58:53.353298 ==
6263 13:58:53.356042 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 13:58:53.359806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 13:58:53.360375 ==
6266 13:58:53.366117 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 13:58:53.372413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6268 13:58:53.375709 [CA 0] Center 36 (8~64) winsize 57
6269 13:58:53.379123 [CA 1] Center 36 (8~64) winsize 57
6270 13:58:53.382498 [CA 2] Center 36 (8~64) winsize 57
6271 13:58:53.386258 [CA 3] Center 36 (8~64) winsize 57
6272 13:58:53.389313 [CA 4] Center 36 (8~64) winsize 57
6273 13:58:53.389872 [CA 5] Center 36 (8~64) winsize 57
6274 13:58:53.392255
6275 13:58:53.395710 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6276 13:58:53.396226
6277 13:58:53.398808 [CATrainingPosCal] consider 1 rank data
6278 13:58:53.402064 u2DelayCellTimex100 = 270/100 ps
6279 13:58:53.405826 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 13:58:53.408654 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 13:58:53.412094 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 13:58:53.415282 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 13:58:53.419036 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 13:58:53.422541 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 13:58:53.423096
6286 13:58:53.425581 CA PerBit enable=1, Macro0, CA PI delay=36
6287 13:58:53.429189
6288 13:58:53.429739 [CBTSetCACLKResult] CA Dly = 36
6289 13:58:53.432419 CS Dly: 1 (0~32)
6290 13:58:53.432978 ==
6291 13:58:53.435875 Dram Type= 6, Freq= 0, CH_0, rank 1
6292 13:58:53.439003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 13:58:53.439565 ==
6294 13:58:53.445244 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6295 13:58:53.452157 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6296 13:58:53.455052 [CA 0] Center 36 (8~64) winsize 57
6297 13:58:53.458195 [CA 1] Center 36 (8~64) winsize 57
6298 13:58:53.462663 [CA 2] Center 36 (8~64) winsize 57
6299 13:58:53.463235 [CA 3] Center 36 (8~64) winsize 57
6300 13:58:53.465519 [CA 4] Center 36 (8~64) winsize 57
6301 13:58:53.468410 [CA 5] Center 36 (8~64) winsize 57
6302 13:58:53.468875
6303 13:58:53.474764 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6304 13:58:53.475399
6305 13:58:53.477993 [CATrainingPosCal] consider 2 rank data
6306 13:58:53.481625 u2DelayCellTimex100 = 270/100 ps
6307 13:58:53.484496 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 13:58:53.488122 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 13:58:53.491340 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 13:58:53.494741 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 13:58:53.497747 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 13:58:53.501256 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 13:58:53.501674
6314 13:58:53.505070 CA PerBit enable=1, Macro0, CA PI delay=36
6315 13:58:53.505487
6316 13:58:53.507774 [CBTSetCACLKResult] CA Dly = 36
6317 13:58:53.511377 CS Dly: 1 (0~32)
6318 13:58:53.511833
6319 13:58:53.514431 ----->DramcWriteLeveling(PI) begin...
6320 13:58:53.514857 ==
6321 13:58:53.518331 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 13:58:53.521452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 13:58:53.521969 ==
6324 13:58:53.524346 Write leveling (Byte 0): 40 => 8
6325 13:58:53.527673 Write leveling (Byte 1): 32 => 0
6326 13:58:53.531067 DramcWriteLeveling(PI) end<-----
6327 13:58:53.531583
6328 13:58:53.531985 ==
6329 13:58:53.534503 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 13:58:53.538129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 13:58:53.538654 ==
6332 13:58:53.540913 [Gating] SW mode calibration
6333 13:58:53.547752 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6334 13:58:53.554066 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6335 13:58:53.557122 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 13:58:53.563957 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 13:58:53.567501 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 13:58:53.571042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 13:58:53.577320 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 13:58:53.580143 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 13:58:53.583988 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 13:58:53.591306 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 13:58:53.593415 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 13:58:53.596692 Total UI for P1: 0, mck2ui 16
6345 13:58:53.600186 best dqsien dly found for B0: ( 0, 14, 24)
6346 13:58:53.603323 Total UI for P1: 0, mck2ui 16
6347 13:58:53.607262 best dqsien dly found for B1: ( 0, 14, 24)
6348 13:58:53.610623 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6349 13:58:53.613085 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6350 13:58:53.613551
6351 13:58:53.616880 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 13:58:53.620311 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 13:58:53.623125 [Gating] SW calibration Done
6354 13:58:53.623587 ==
6355 13:58:53.627118 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 13:58:53.630688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 13:58:53.631252 ==
6358 13:58:53.633556 RX Vref Scan: 0
6359 13:58:53.634165
6360 13:58:53.637455 RX Vref 0 -> 0, step: 1
6361 13:58:53.637916
6362 13:58:53.639956 RX Delay -410 -> 252, step: 16
6363 13:58:53.643820 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6364 13:58:53.646395 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6365 13:58:53.649621 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6366 13:58:53.657265 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6367 13:58:53.660062 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6368 13:58:53.663284 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6369 13:58:53.666727 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6370 13:58:53.672954 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6371 13:58:53.676322 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6372 13:58:53.680204 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6373 13:58:53.683839 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6374 13:58:53.689518 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6375 13:58:53.693123 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6376 13:58:53.696262 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6377 13:58:53.702727 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6378 13:58:53.707054 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6379 13:58:53.707616 ==
6380 13:58:53.709236 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 13:58:53.712541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 13:58:53.713104 ==
6383 13:58:53.715986 DQS Delay:
6384 13:58:53.716531 DQS0 = 43, DQS1 = 59
6385 13:58:53.716909 DQM Delay:
6386 13:58:53.719537 DQM0 = 9, DQM1 = 12
6387 13:58:53.720138 DQ Delay:
6388 13:58:53.722515 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6389 13:58:53.726257 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6390 13:58:53.729220 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6391 13:58:53.732351 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6392 13:58:53.732815
6393 13:58:53.733183
6394 13:58:53.733524 ==
6395 13:58:53.736253 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 13:58:53.739209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 13:58:53.739810 ==
6398 13:58:53.743090
6399 13:58:53.743640
6400 13:58:53.744072 TX Vref Scan disable
6401 13:58:53.745477 == TX Byte 0 ==
6402 13:58:53.749452 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 13:58:53.752501 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 13:58:53.755828 == TX Byte 1 ==
6405 13:58:53.758687 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6406 13:58:53.762173 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6407 13:58:53.762806 ==
6408 13:58:53.765281 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 13:58:53.772069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 13:58:53.772541 ==
6411 13:58:53.772912
6412 13:58:53.773362
6413 13:58:53.773704 TX Vref Scan disable
6414 13:58:53.775790 == TX Byte 0 ==
6415 13:58:53.779076 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 13:58:53.782397 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 13:58:53.785291 == TX Byte 1 ==
6418 13:58:53.788824 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6419 13:58:53.792168 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6420 13:58:53.792723
6421 13:58:53.795421 [DATLAT]
6422 13:58:53.796038 Freq=400, CH0 RK0
6423 13:58:53.796424
6424 13:58:53.798434 DATLAT Default: 0xf
6425 13:58:53.798955 0, 0xFFFF, sum = 0
6426 13:58:53.802106 1, 0xFFFF, sum = 0
6427 13:58:53.802666 2, 0xFFFF, sum = 0
6428 13:58:53.804924 3, 0xFFFF, sum = 0
6429 13:58:53.805414 4, 0xFFFF, sum = 0
6430 13:58:53.807971 5, 0xFFFF, sum = 0
6431 13:58:53.808449 6, 0xFFFF, sum = 0
6432 13:58:53.812352 7, 0xFFFF, sum = 0
6433 13:58:53.814818 8, 0xFFFF, sum = 0
6434 13:58:53.815302 9, 0xFFFF, sum = 0
6435 13:58:53.818299 10, 0xFFFF, sum = 0
6436 13:58:53.818871 11, 0xFFFF, sum = 0
6437 13:58:53.821867 12, 0xFFFF, sum = 0
6438 13:58:53.822430 13, 0x0, sum = 1
6439 13:58:53.825030 14, 0x0, sum = 2
6440 13:58:53.825620 15, 0x0, sum = 3
6441 13:58:53.828180 16, 0x0, sum = 4
6442 13:58:53.828760 best_step = 14
6443 13:58:53.829137
6444 13:58:53.829489 ==
6445 13:58:53.831843 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 13:58:53.834995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 13:58:53.835552 ==
6448 13:58:53.838072 RX Vref Scan: 1
6449 13:58:53.838624
6450 13:58:53.841594 RX Vref 0 -> 0, step: 1
6451 13:58:53.842150
6452 13:58:53.842529 RX Delay -359 -> 252, step: 8
6453 13:58:53.844458
6454 13:58:53.844921 Set Vref, RX VrefLevel [Byte0]: 60
6455 13:58:53.847910 [Byte1]: 50
6456 13:58:53.853809
6457 13:58:53.854363 Final RX Vref Byte 0 = 60 to rank0
6458 13:58:53.856830 Final RX Vref Byte 1 = 50 to rank0
6459 13:58:53.860535 Final RX Vref Byte 0 = 60 to rank1
6460 13:58:53.864446 Final RX Vref Byte 1 = 50 to rank1==
6461 13:58:53.866983 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 13:58:53.873436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 13:58:53.873909 ==
6464 13:58:53.874283 DQS Delay:
6465 13:58:53.876559 DQS0 = 48, DQS1 = 60
6466 13:58:53.877119 DQM Delay:
6467 13:58:53.877686 DQM0 = 11, DQM1 = 12
6468 13:58:53.879756 DQ Delay:
6469 13:58:53.883598 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6470 13:58:53.887336 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6471 13:58:53.889872 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6472 13:58:53.893644 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6473 13:58:53.894209
6474 13:58:53.894580
6475 13:58:53.899441 [DQSOSCAuto] RK0, (LSB)MR18= 0xc082, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6476 13:58:53.903559 CH0 RK0: MR19=C0C, MR18=C082
6477 13:58:53.910379 CH0_RK0: MR19=0xC0C, MR18=0xC082, DQSOSC=386, MR23=63, INC=396, DEC=264
6478 13:58:53.910950 ==
6479 13:58:53.912933 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 13:58:53.916366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 13:58:53.917015 ==
6482 13:58:53.919567 [Gating] SW mode calibration
6483 13:58:53.926629 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 13:58:53.932610 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6485 13:58:53.936454 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 13:58:53.939147 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 13:58:53.946090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 13:58:53.948890 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 13:58:53.952313 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 13:58:53.959380 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 13:58:53.962836 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 13:58:53.965651 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 13:58:53.972726 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 13:58:53.975411 Total UI for P1: 0, mck2ui 16
6495 13:58:53.978967 best dqsien dly found for B0: ( 0, 14, 24)
6496 13:58:53.982658 Total UI for P1: 0, mck2ui 16
6497 13:58:53.985995 best dqsien dly found for B1: ( 0, 14, 24)
6498 13:58:53.988668 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6499 13:58:53.991940 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6500 13:58:53.992407
6501 13:58:53.995455 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 13:58:53.998720 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 13:58:54.002069 [Gating] SW calibration Done
6504 13:58:54.002625 ==
6505 13:58:54.005564 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 13:58:54.008213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 13:58:54.008683 ==
6508 13:58:54.011705 RX Vref Scan: 0
6509 13:58:54.012305
6510 13:58:54.016135 RX Vref 0 -> 0, step: 1
6511 13:58:54.016690
6512 13:58:54.017069 RX Delay -410 -> 252, step: 16
6513 13:58:54.022114 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6514 13:58:54.025298 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6515 13:58:54.028711 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6516 13:58:54.035559 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6517 13:58:54.038509 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6518 13:58:54.041712 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6519 13:58:54.044912 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6520 13:58:54.051292 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6521 13:58:54.054516 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6522 13:58:54.057833 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6523 13:58:54.061310 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6524 13:58:54.068039 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6525 13:58:54.071125 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6526 13:58:54.074640 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6527 13:58:54.077682 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6528 13:58:54.084482 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6529 13:58:54.085028 ==
6530 13:58:54.087791 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 13:58:54.091410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 13:58:54.092023 ==
6533 13:58:54.092406 DQS Delay:
6534 13:58:54.094667 DQS0 = 43, DQS1 = 59
6535 13:58:54.095130 DQM Delay:
6536 13:58:54.098641 DQM0 = 11, DQM1 = 16
6537 13:58:54.099462 DQ Delay:
6538 13:58:54.100684 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6539 13:58:54.104005 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6540 13:58:54.107808 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6541 13:58:54.111224 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6542 13:58:54.111835
6543 13:58:54.112221
6544 13:58:54.112566 ==
6545 13:58:54.113937 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 13:58:54.117280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 13:58:54.117749 ==
6548 13:58:54.121616
6549 13:58:54.122206
6550 13:58:54.122580 TX Vref Scan disable
6551 13:58:54.123708 == TX Byte 0 ==
6552 13:58:54.127581 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6553 13:58:54.131070 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6554 13:58:54.133873 == TX Byte 1 ==
6555 13:58:54.137443 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6556 13:58:54.140325 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6557 13:58:54.140885 ==
6558 13:58:54.144458 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 13:58:54.147072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 13:58:54.150070 ==
6561 13:58:54.150530
6562 13:58:54.150912
6563 13:58:54.151256 TX Vref Scan disable
6564 13:58:54.154557 == TX Byte 0 ==
6565 13:58:54.157363 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6566 13:58:54.160247 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6567 13:58:54.163642 == TX Byte 1 ==
6568 13:58:54.166779 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6569 13:58:54.169821 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6570 13:58:54.170388
6571 13:58:54.173505 [DATLAT]
6572 13:58:54.173994 Freq=400, CH0 RK1
6573 13:58:54.174344
6574 13:58:54.176389 DATLAT Default: 0xe
6575 13:58:54.176810 0, 0xFFFF, sum = 0
6576 13:58:54.180104 1, 0xFFFF, sum = 0
6577 13:58:54.180530 2, 0xFFFF, sum = 0
6578 13:58:54.183494 3, 0xFFFF, sum = 0
6579 13:58:54.184065 4, 0xFFFF, sum = 0
6580 13:58:54.188084 5, 0xFFFF, sum = 0
6581 13:58:54.188604 6, 0xFFFF, sum = 0
6582 13:58:54.189953 7, 0xFFFF, sum = 0
6583 13:58:54.190377 8, 0xFFFF, sum = 0
6584 13:58:54.193095 9, 0xFFFF, sum = 0
6585 13:58:54.193522 10, 0xFFFF, sum = 0
6586 13:58:54.197067 11, 0xFFFF, sum = 0
6587 13:58:54.199697 12, 0xFFFF, sum = 0
6588 13:58:54.200204 13, 0x0, sum = 1
6589 13:58:54.200547 14, 0x0, sum = 2
6590 13:58:54.203376 15, 0x0, sum = 3
6591 13:58:54.204049 16, 0x0, sum = 4
6592 13:58:54.206301 best_step = 14
6593 13:58:54.206805
6594 13:58:54.207145 ==
6595 13:58:54.209537 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 13:58:54.213428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 13:58:54.213963 ==
6598 13:58:54.216367 RX Vref Scan: 0
6599 13:58:54.216788
6600 13:58:54.217121 RX Vref 0 -> 0, step: 1
6601 13:58:54.217438
6602 13:58:54.220007 RX Delay -359 -> 252, step: 8
6603 13:58:54.228099 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6604 13:58:54.231929 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6605 13:58:54.234580 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6606 13:58:54.241171 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6607 13:58:54.244901 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6608 13:58:54.247549 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6609 13:58:54.250824 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6610 13:58:54.258366 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6611 13:58:54.260820 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6612 13:58:54.264438 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6613 13:58:54.267898 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6614 13:58:54.274502 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6615 13:58:54.277161 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6616 13:58:54.280934 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6617 13:58:54.283955 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6618 13:58:54.290396 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6619 13:58:54.290957 ==
6620 13:58:54.293928 Dram Type= 6, Freq= 0, CH_0, rank 1
6621 13:58:54.296928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 13:58:54.297487 ==
6623 13:58:54.300958 DQS Delay:
6624 13:58:54.301421 DQS0 = 44, DQS1 = 60
6625 13:58:54.301791 DQM Delay:
6626 13:58:54.303787 DQM0 = 8, DQM1 = 14
6627 13:58:54.304347 DQ Delay:
6628 13:58:54.306897 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6629 13:58:54.310492 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6630 13:58:54.313942 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6631 13:58:54.316614 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6632 13:58:54.317084
6633 13:58:54.317452
6634 13:58:54.326695 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe47, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6635 13:58:54.327265 CH0 RK1: MR19=C0C, MR18=BE47
6636 13:58:54.333334 CH0_RK1: MR19=0xC0C, MR18=0xBE47, DQSOSC=386, MR23=63, INC=396, DEC=264
6637 13:58:54.337049 [RxdqsGatingPostProcess] freq 400
6638 13:58:54.343707 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6639 13:58:54.346995 best DQS0 dly(2T, 0.5T) = (0, 10)
6640 13:58:54.350343 best DQS1 dly(2T, 0.5T) = (0, 10)
6641 13:58:54.352719 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6642 13:58:54.356653 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6643 13:58:54.359400 best DQS0 dly(2T, 0.5T) = (0, 10)
6644 13:58:54.363057 best DQS1 dly(2T, 0.5T) = (0, 10)
6645 13:58:54.363620 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6646 13:58:54.366270 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6647 13:58:54.369876 Pre-setting of DQS Precalculation
6648 13:58:54.376284 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6649 13:58:54.376755 ==
6650 13:58:54.379425 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 13:58:54.383415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 13:58:54.384048 ==
6653 13:58:54.389300 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 13:58:54.396166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6655 13:58:54.399649 [CA 0] Center 36 (8~64) winsize 57
6656 13:58:54.403374 [CA 1] Center 36 (8~64) winsize 57
6657 13:58:54.406097 [CA 2] Center 36 (8~64) winsize 57
6658 13:58:54.406664 [CA 3] Center 36 (8~64) winsize 57
6659 13:58:54.409823 [CA 4] Center 36 (8~64) winsize 57
6660 13:58:54.412386 [CA 5] Center 36 (8~64) winsize 57
6661 13:58:54.412849
6662 13:58:54.419152 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6663 13:58:54.419718
6664 13:58:54.423000 [CATrainingPosCal] consider 1 rank data
6665 13:58:54.425896 u2DelayCellTimex100 = 270/100 ps
6666 13:58:54.429796 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 13:58:54.433522 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 13:58:54.435783 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 13:58:54.440044 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 13:58:54.442464 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 13:58:54.445843 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 13:58:54.446407
6673 13:58:54.448764 CA PerBit enable=1, Macro0, CA PI delay=36
6674 13:58:54.449251
6675 13:58:54.452464 [CBTSetCACLKResult] CA Dly = 36
6676 13:58:54.456198 CS Dly: 1 (0~32)
6677 13:58:54.456764 ==
6678 13:58:54.458858 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 13:58:54.462126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 13:58:54.462687 ==
6681 13:58:54.468631 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6682 13:58:54.475838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6683 13:58:54.476397 [CA 0] Center 36 (8~64) winsize 57
6684 13:58:54.478369 [CA 1] Center 36 (8~64) winsize 57
6685 13:58:54.482403 [CA 2] Center 36 (8~64) winsize 57
6686 13:58:54.486142 [CA 3] Center 36 (8~64) winsize 57
6687 13:58:54.488690 [CA 4] Center 36 (8~64) winsize 57
6688 13:58:54.492329 [CA 5] Center 36 (8~64) winsize 57
6689 13:58:54.492892
6690 13:58:54.495286 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6691 13:58:54.495905
6692 13:58:54.498669 [CATrainingPosCal] consider 2 rank data
6693 13:58:54.502109 u2DelayCellTimex100 = 270/100 ps
6694 13:58:54.505358 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 13:58:54.512270 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 13:58:54.515022 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 13:58:54.518224 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 13:58:54.522232 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 13:58:54.524731 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 13:58:54.525199
6701 13:58:54.528145 CA PerBit enable=1, Macro0, CA PI delay=36
6702 13:58:54.528702
6703 13:58:54.531530 [CBTSetCACLKResult] CA Dly = 36
6704 13:58:54.534655 CS Dly: 1 (0~32)
6705 13:58:54.535212
6706 13:58:54.538525 ----->DramcWriteLeveling(PI) begin...
6707 13:58:54.539091 ==
6708 13:58:54.542035 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 13:58:54.544464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 13:58:54.544933 ==
6711 13:58:54.548039 Write leveling (Byte 0): 40 => 8
6712 13:58:54.551635 Write leveling (Byte 1): 40 => 8
6713 13:58:54.554633 DramcWriteLeveling(PI) end<-----
6714 13:58:54.555188
6715 13:58:54.555557 ==
6716 13:58:54.557864 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 13:58:54.561226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 13:58:54.561781 ==
6719 13:58:54.564869 [Gating] SW mode calibration
6720 13:58:54.571070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6721 13:58:54.577754 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6722 13:58:54.580852 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 13:58:54.584815 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 13:58:54.591084 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 13:58:54.594269 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 13:58:54.597377 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 13:58:54.604635 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 13:58:54.607490 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 13:58:54.610947 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 13:58:54.617884 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 13:58:54.618442 Total UI for P1: 0, mck2ui 16
6732 13:58:54.624161 best dqsien dly found for B0: ( 0, 14, 24)
6733 13:58:54.624720 Total UI for P1: 0, mck2ui 16
6734 13:58:54.630622 best dqsien dly found for B1: ( 0, 14, 24)
6735 13:58:54.634656 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6736 13:58:54.637307 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6737 13:58:54.637869
6738 13:58:54.640550 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 13:58:54.644158 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 13:58:54.647894 [Gating] SW calibration Done
6741 13:58:54.648447 ==
6742 13:58:54.650930 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 13:58:54.653627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 13:58:54.654097 ==
6745 13:58:54.656913 RX Vref Scan: 0
6746 13:58:54.657378
6747 13:58:54.657749 RX Vref 0 -> 0, step: 1
6748 13:58:54.659891
6749 13:58:54.660348 RX Delay -410 -> 252, step: 16
6750 13:58:54.667140 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6751 13:58:54.669772 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6752 13:58:54.673362 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6753 13:58:54.679801 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6754 13:58:54.683271 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6755 13:58:54.686721 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6756 13:58:54.689534 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6757 13:58:54.696399 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6758 13:58:54.700640 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6759 13:58:54.703584 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6760 13:58:54.706567 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6761 13:58:54.712663 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6762 13:58:54.716039 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6763 13:58:54.719242 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6764 13:58:54.722641 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6765 13:58:54.729790 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6766 13:58:54.730351 ==
6767 13:58:54.732482 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 13:58:54.736738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 13:58:54.737303 ==
6770 13:58:54.737671 DQS Delay:
6771 13:58:54.739101 DQS0 = 43, DQS1 = 51
6772 13:58:54.739569 DQM Delay:
6773 13:58:54.742437 DQM0 = 12, DQM1 = 14
6774 13:58:54.742994 DQ Delay:
6775 13:58:54.746020 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6776 13:58:54.749652 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6777 13:58:54.752345 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6778 13:58:54.755928 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6779 13:58:54.756391
6780 13:58:54.756760
6781 13:58:54.757103 ==
6782 13:58:54.759147 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 13:58:54.761956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 13:58:54.762375 ==
6785 13:58:54.762739
6786 13:58:54.765345
6787 13:58:54.765807 TX Vref Scan disable
6788 13:58:54.769504 == TX Byte 0 ==
6789 13:58:54.772071 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 13:58:54.775564 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 13:58:54.778743 == TX Byte 1 ==
6792 13:58:54.782095 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 13:58:54.785532 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 13:58:54.786091 ==
6795 13:58:54.788614 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 13:58:54.792468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 13:58:54.795476 ==
6798 13:58:54.795995
6799 13:58:54.796368
6800 13:58:54.796713 TX Vref Scan disable
6801 13:58:54.798359 == TX Byte 0 ==
6802 13:58:54.801816 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 13:58:54.805803 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 13:58:54.808259 == TX Byte 1 ==
6805 13:58:54.811958 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 13:58:54.815025 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 13:58:54.815582
6808 13:58:54.818358 [DATLAT]
6809 13:58:54.818914 Freq=400, CH1 RK0
6810 13:58:54.819299
6811 13:58:54.821563 DATLAT Default: 0xf
6812 13:58:54.822124 0, 0xFFFF, sum = 0
6813 13:58:54.824686 1, 0xFFFF, sum = 0
6814 13:58:54.825254 2, 0xFFFF, sum = 0
6815 13:58:54.828520 3, 0xFFFF, sum = 0
6816 13:58:54.829089 4, 0xFFFF, sum = 0
6817 13:58:54.831424 5, 0xFFFF, sum = 0
6818 13:58:54.832034 6, 0xFFFF, sum = 0
6819 13:58:54.834833 7, 0xFFFF, sum = 0
6820 13:58:54.835396 8, 0xFFFF, sum = 0
6821 13:58:54.838155 9, 0xFFFF, sum = 0
6822 13:58:54.838710 10, 0xFFFF, sum = 0
6823 13:58:54.841642 11, 0xFFFF, sum = 0
6824 13:58:54.844647 12, 0xFFFF, sum = 0
6825 13:58:54.845214 13, 0x0, sum = 1
6826 13:58:54.848373 14, 0x0, sum = 2
6827 13:58:54.848950 15, 0x0, sum = 3
6828 13:58:54.849330 16, 0x0, sum = 4
6829 13:58:54.851226 best_step = 14
6830 13:58:54.851808
6831 13:58:54.852186 ==
6832 13:58:54.854449 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 13:58:54.857890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 13:58:54.858437 ==
6835 13:58:54.861157 RX Vref Scan: 1
6836 13:58:54.861621
6837 13:58:54.864483 RX Vref 0 -> 0, step: 1
6838 13:58:54.864958
6839 13:58:54.865328 RX Delay -343 -> 252, step: 8
6840 13:58:54.865674
6841 13:58:54.867507 Set Vref, RX VrefLevel [Byte0]: 47
6842 13:58:54.871209 [Byte1]: 60
6843 13:58:54.876486
6844 13:58:54.877003 Final RX Vref Byte 0 = 47 to rank0
6845 13:58:54.879972 Final RX Vref Byte 1 = 60 to rank0
6846 13:58:54.882692 Final RX Vref Byte 0 = 47 to rank1
6847 13:58:54.886272 Final RX Vref Byte 1 = 60 to rank1==
6848 13:58:54.889573 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 13:58:54.896109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 13:58:54.896534 ==
6851 13:58:54.896868 DQS Delay:
6852 13:58:54.899381 DQS0 = 44, DQS1 = 56
6853 13:58:54.899947 DQM Delay:
6854 13:58:54.900291 DQM0 = 8, DQM1 = 11
6855 13:58:54.902558 DQ Delay:
6856 13:58:54.906051 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6857 13:58:54.906578 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6858 13:58:54.909358 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6859 13:58:54.912832 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6860 13:58:54.913499
6861 13:58:54.913851
6862 13:58:54.922815 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6863 13:58:54.926083 CH1 RK0: MR19=C0C, MR18=9D72
6864 13:58:54.932907 CH1_RK0: MR19=0xC0C, MR18=0x9D72, DQSOSC=390, MR23=63, INC=388, DEC=258
6865 13:58:54.933470 ==
6866 13:58:54.936337 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 13:58:54.938965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 13:58:54.939527 ==
6869 13:58:54.942556 [Gating] SW mode calibration
6870 13:58:54.948689 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6871 13:58:54.955386 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6872 13:58:54.958933 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 13:58:54.962415 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 13:58:54.968316 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 13:58:54.972251 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 13:58:54.974750 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 13:58:54.982350 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 13:58:54.984901 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 13:58:54.989405 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 13:58:54.995169 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 13:58:54.995634 Total UI for P1: 0, mck2ui 16
6882 13:58:55.001481 best dqsien dly found for B0: ( 0, 14, 24)
6883 13:58:55.002128 Total UI for P1: 0, mck2ui 16
6884 13:58:55.008259 best dqsien dly found for B1: ( 0, 14, 24)
6885 13:58:55.011899 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6886 13:58:55.015353 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6887 13:58:55.015978
6888 13:58:55.018092 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 13:58:55.021375 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 13:58:55.024507 [Gating] SW calibration Done
6891 13:58:55.024966 ==
6892 13:58:55.028478 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 13:58:55.031180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 13:58:55.031771 ==
6895 13:58:55.034931 RX Vref Scan: 0
6896 13:58:55.035488
6897 13:58:55.035905 RX Vref 0 -> 0, step: 1
6898 13:58:55.037852
6899 13:58:55.038406 RX Delay -410 -> 252, step: 16
6900 13:58:55.044221 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6901 13:58:55.047599 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6902 13:58:55.051012 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6903 13:58:55.054034 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6904 13:58:55.060782 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6905 13:58:55.064228 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6906 13:58:55.067380 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6907 13:58:55.070832 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6908 13:58:55.077375 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6909 13:58:55.080502 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6910 13:58:55.084078 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6911 13:58:55.090446 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6912 13:58:55.094016 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6913 13:58:55.097007 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6914 13:58:55.100456 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6915 13:58:55.107423 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6916 13:58:55.108040 ==
6917 13:58:55.110460 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 13:58:55.113714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 13:58:55.114275 ==
6920 13:58:55.114644 DQS Delay:
6921 13:58:55.117161 DQS0 = 51, DQS1 = 51
6922 13:58:55.117831 DQM Delay:
6923 13:58:55.120202 DQM0 = 18, DQM1 = 15
6924 13:58:55.120775 DQ Delay:
6925 13:58:55.123710 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6926 13:58:55.126857 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6927 13:58:55.130779 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6928 13:58:55.133671 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6929 13:58:55.134239
6930 13:58:55.134611
6931 13:58:55.134949 ==
6932 13:58:55.137070 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 13:58:55.139834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 13:58:55.143116 ==
6935 13:58:55.143577
6936 13:58:55.144060
6937 13:58:55.144413 TX Vref Scan disable
6938 13:58:55.146815 == TX Byte 0 ==
6939 13:58:55.149813 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6940 13:58:55.152693 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6941 13:58:55.156260 == TX Byte 1 ==
6942 13:58:55.159422 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6943 13:58:55.162677 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6944 13:58:55.163153 ==
6945 13:58:55.166408 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 13:58:55.172764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 13:58:55.173322 ==
6948 13:58:55.173704
6949 13:58:55.174044
6950 13:58:55.174371 TX Vref Scan disable
6951 13:58:55.176041 == TX Byte 0 ==
6952 13:58:55.179183 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6953 13:58:55.182577 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6954 13:58:55.185965 == TX Byte 1 ==
6955 13:58:55.190130 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6956 13:58:55.192374 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6957 13:58:55.192830
6958 13:58:55.196263 [DATLAT]
6959 13:58:55.196722 Freq=400, CH1 RK1
6960 13:58:55.197091
6961 13:58:55.199134 DATLAT Default: 0xe
6962 13:58:55.199692 0, 0xFFFF, sum = 0
6963 13:58:55.202541 1, 0xFFFF, sum = 0
6964 13:58:55.203053 2, 0xFFFF, sum = 0
6965 13:58:55.206131 3, 0xFFFF, sum = 0
6966 13:58:55.206694 4, 0xFFFF, sum = 0
6967 13:58:55.209607 5, 0xFFFF, sum = 0
6968 13:58:55.210174 6, 0xFFFF, sum = 0
6969 13:58:55.212103 7, 0xFFFF, sum = 0
6970 13:58:55.212525 8, 0xFFFF, sum = 0
6971 13:58:55.215673 9, 0xFFFF, sum = 0
6972 13:58:55.216244 10, 0xFFFF, sum = 0
6973 13:58:55.219482 11, 0xFFFF, sum = 0
6974 13:58:55.222488 12, 0xFFFF, sum = 0
6975 13:58:55.223012 13, 0x0, sum = 1
6976 13:58:55.225746 14, 0x0, sum = 2
6977 13:58:55.226307 15, 0x0, sum = 3
6978 13:58:55.226658 16, 0x0, sum = 4
6979 13:58:55.228379 best_step = 14
6980 13:58:55.228796
6981 13:58:55.229130 ==
6982 13:58:55.232142 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 13:58:55.235764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 13:58:55.236283 ==
6985 13:58:55.239145 RX Vref Scan: 0
6986 13:58:55.239659
6987 13:58:55.241963 RX Vref 0 -> 0, step: 1
6988 13:58:55.242396
6989 13:58:55.242736 RX Delay -343 -> 252, step: 8
6990 13:58:55.250705 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6991 13:58:55.254265 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6992 13:58:55.256945 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6993 13:58:55.260464 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6994 13:58:55.267252 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6995 13:58:55.270643 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6996 13:58:55.273655 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6997 13:58:55.276876 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6998 13:58:55.283790 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
6999 13:58:55.287711 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7000 13:58:55.290473 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7001 13:58:55.296755 iDelay=225, Bit 11, Center -52 (-303 ~ 200) 504
7002 13:58:55.300249 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
7003 13:58:55.303318 iDelay=225, Bit 13, Center -36 (-287 ~ 216) 504
7004 13:58:55.306642 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7005 13:58:55.313637 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7006 13:58:55.314158 ==
7007 13:58:55.316578 Dram Type= 6, Freq= 0, CH_1, rank 1
7008 13:58:55.319897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7009 13:58:55.320413 ==
7010 13:58:55.320754 DQS Delay:
7011 13:58:55.323867 DQS0 = 48, DQS1 = 60
7012 13:58:55.324378 DQM Delay:
7013 13:58:55.326243 DQM0 = 12, DQM1 = 14
7014 13:58:55.326656 DQ Delay:
7015 13:58:55.329595 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7016 13:58:55.333159 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7017 13:58:55.336450 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7018 13:58:55.339663 DQ12 =20, DQ13 =24, DQ14 =20, DQ15 =24
7019 13:58:55.340232
7020 13:58:55.340567
7021 13:58:55.347134 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 395 ps
7022 13:58:55.349993 CH1 RK1: MR19=C0C, MR18=6E5D
7023 13:58:55.356387 CH1_RK1: MR19=0xC0C, MR18=0x6E5D, DQSOSC=395, MR23=63, INC=378, DEC=252
7024 13:58:55.359643 [RxdqsGatingPostProcess] freq 400
7025 13:58:55.366623 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7026 13:58:55.369309 best DQS0 dly(2T, 0.5T) = (0, 10)
7027 13:58:55.373186 best DQS1 dly(2T, 0.5T) = (0, 10)
7028 13:58:55.375555 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7029 13:58:55.379480 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7030 13:58:55.382519 best DQS0 dly(2T, 0.5T) = (0, 10)
7031 13:58:55.383037 best DQS1 dly(2T, 0.5T) = (0, 10)
7032 13:58:55.385565 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7033 13:58:55.389625 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7034 13:58:55.392486 Pre-setting of DQS Precalculation
7035 13:58:55.399051 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7036 13:58:55.406097 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7037 13:58:55.412710 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7038 13:58:55.413226
7039 13:58:55.413558
7040 13:58:55.415774 [Calibration Summary] 800 Mbps
7041 13:58:55.418827 CH 0, Rank 0
7042 13:58:55.419339 SW Impedance : PASS
7043 13:58:55.422199 DUTY Scan : NO K
7044 13:58:55.422715 ZQ Calibration : PASS
7045 13:58:55.425958 Jitter Meter : NO K
7046 13:58:55.428903 CBT Training : PASS
7047 13:58:55.429415 Write leveling : PASS
7048 13:58:55.432437 RX DQS gating : PASS
7049 13:58:55.435393 RX DQ/DQS(RDDQC) : PASS
7050 13:58:55.435952 TX DQ/DQS : PASS
7051 13:58:55.439348 RX DATLAT : PASS
7052 13:58:55.442231 RX DQ/DQS(Engine): PASS
7053 13:58:55.442646 TX OE : NO K
7054 13:58:55.444913 All Pass.
7055 13:58:55.445327
7056 13:58:55.445785 CH 0, Rank 1
7057 13:58:55.448603 SW Impedance : PASS
7058 13:58:55.449019 DUTY Scan : NO K
7059 13:58:55.451623 ZQ Calibration : PASS
7060 13:58:55.454997 Jitter Meter : NO K
7061 13:58:55.455511 CBT Training : PASS
7062 13:58:55.458844 Write leveling : NO K
7063 13:58:55.461595 RX DQS gating : PASS
7064 13:58:55.462014 RX DQ/DQS(RDDQC) : PASS
7065 13:58:55.464683 TX DQ/DQS : PASS
7066 13:58:55.468313 RX DATLAT : PASS
7067 13:58:55.468847 RX DQ/DQS(Engine): PASS
7068 13:58:55.471587 TX OE : NO K
7069 13:58:55.472194 All Pass.
7070 13:58:55.472529
7071 13:58:55.474698 CH 1, Rank 0
7072 13:58:55.475113 SW Impedance : PASS
7073 13:58:55.477777 DUTY Scan : NO K
7074 13:58:55.481755 ZQ Calibration : PASS
7075 13:58:55.482213 Jitter Meter : NO K
7076 13:58:55.484981 CBT Training : PASS
7077 13:58:55.488354 Write leveling : PASS
7078 13:58:55.488884 RX DQS gating : PASS
7079 13:58:55.491292 RX DQ/DQS(RDDQC) : PASS
7080 13:58:55.491857 TX DQ/DQS : PASS
7081 13:58:55.494802 RX DATLAT : PASS
7082 13:58:55.497984 RX DQ/DQS(Engine): PASS
7083 13:58:55.498496 TX OE : NO K
7084 13:58:55.501620 All Pass.
7085 13:58:55.502144
7086 13:58:55.502482 CH 1, Rank 1
7087 13:58:55.505197 SW Impedance : PASS
7088 13:58:55.505712 DUTY Scan : NO K
7089 13:58:55.507519 ZQ Calibration : PASS
7090 13:58:55.511831 Jitter Meter : NO K
7091 13:58:55.512365 CBT Training : PASS
7092 13:58:55.514591 Write leveling : NO K
7093 13:58:55.517771 RX DQS gating : PASS
7094 13:58:55.518306 RX DQ/DQS(RDDQC) : PASS
7095 13:58:55.520933 TX DQ/DQS : PASS
7096 13:58:55.524560 RX DATLAT : PASS
7097 13:58:55.525070 RX DQ/DQS(Engine): PASS
7098 13:58:55.527710 TX OE : NO K
7099 13:58:55.528265 All Pass.
7100 13:58:55.528604
7101 13:58:55.531288 DramC Write-DBI off
7102 13:58:55.534089 PER_BANK_REFRESH: Hybrid Mode
7103 13:58:55.534600 TX_TRACKING: ON
7104 13:58:55.543967 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7105 13:58:55.547508 [FAST_K] Save calibration result to emmc
7106 13:58:55.550576 dramc_set_vcore_voltage set vcore to 725000
7107 13:58:55.554208 Read voltage for 1600, 0
7108 13:58:55.554803 Vio18 = 0
7109 13:58:55.555177 Vcore = 725000
7110 13:58:55.557212 Vdram = 0
7111 13:58:55.557679 Vddq = 0
7112 13:58:55.558047 Vmddr = 0
7113 13:58:55.564043 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7114 13:58:55.567062 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7115 13:58:55.570899 MEM_TYPE=3, freq_sel=13
7116 13:58:55.574054 sv_algorithm_assistance_LP4_3733
7117 13:58:55.577213 ============ PULL DRAM RESETB DOWN ============
7118 13:58:55.583851 ========== PULL DRAM RESETB DOWN end =========
7119 13:58:55.586821 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7120 13:58:55.591010 ===================================
7121 13:58:55.594018 LPDDR4 DRAM CONFIGURATION
7122 13:58:55.596918 ===================================
7123 13:58:55.597383 EX_ROW_EN[0] = 0x0
7124 13:58:55.600136 EX_ROW_EN[1] = 0x0
7125 13:58:55.600598 LP4Y_EN = 0x0
7126 13:58:55.603863 WORK_FSP = 0x1
7127 13:58:55.604332 WL = 0x5
7128 13:58:55.606758 RL = 0x5
7129 13:58:55.607220 BL = 0x2
7130 13:58:55.610008 RPST = 0x0
7131 13:58:55.610609 RD_PRE = 0x0
7132 13:58:55.613492 WR_PRE = 0x1
7133 13:58:55.616617 WR_PST = 0x1
7134 13:58:55.617085 DBI_WR = 0x0
7135 13:58:55.620790 DBI_RD = 0x0
7136 13:58:55.621377 OTF = 0x1
7137 13:58:55.623800 ===================================
7138 13:58:55.626551 ===================================
7139 13:58:55.630026 ANA top config
7140 13:58:55.633438 ===================================
7141 13:58:55.634008 DLL_ASYNC_EN = 0
7142 13:58:55.636655 ALL_SLAVE_EN = 0
7143 13:58:55.640406 NEW_RANK_MODE = 1
7144 13:58:55.643167 DLL_IDLE_MODE = 1
7145 13:58:55.643795 LP45_APHY_COMB_EN = 1
7146 13:58:55.646728 TX_ODT_DIS = 0
7147 13:58:55.649899 NEW_8X_MODE = 1
7148 13:58:55.653624 ===================================
7149 13:58:55.656221 ===================================
7150 13:58:55.659516 data_rate = 3200
7151 13:58:55.663235 CKR = 1
7152 13:58:55.666451 DQ_P2S_RATIO = 8
7153 13:58:55.669314 ===================================
7154 13:58:55.669976 CA_P2S_RATIO = 8
7155 13:58:55.672508 DQ_CA_OPEN = 0
7156 13:58:55.675761 DQ_SEMI_OPEN = 0
7157 13:58:55.679580 CA_SEMI_OPEN = 0
7158 13:58:55.683445 CA_FULL_RATE = 0
7159 13:58:55.685748 DQ_CKDIV4_EN = 0
7160 13:58:55.686217 CA_CKDIV4_EN = 0
7161 13:58:55.689204 CA_PREDIV_EN = 0
7162 13:58:55.692259 PH8_DLY = 12
7163 13:58:55.696166 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7164 13:58:55.699066 DQ_AAMCK_DIV = 4
7165 13:58:55.702671 CA_AAMCK_DIV = 4
7166 13:58:55.703235 CA_ADMCK_DIV = 4
7167 13:58:55.705860 DQ_TRACK_CA_EN = 0
7168 13:58:55.708856 CA_PICK = 1600
7169 13:58:55.712229 CA_MCKIO = 1600
7170 13:58:55.716162 MCKIO_SEMI = 0
7171 13:58:55.719388 PLL_FREQ = 3068
7172 13:58:55.722214 DQ_UI_PI_RATIO = 32
7173 13:58:55.725446 CA_UI_PI_RATIO = 0
7174 13:58:55.729058 ===================================
7175 13:58:55.732514 ===================================
7176 13:58:55.733079 memory_type:LPDDR4
7177 13:58:55.735559 GP_NUM : 10
7178 13:58:55.738649 SRAM_EN : 1
7179 13:58:55.739209 MD32_EN : 0
7180 13:58:55.741612 ===================================
7181 13:58:55.745522 [ANA_INIT] >>>>>>>>>>>>>>
7182 13:58:55.748501 <<<<<< [CONFIGURE PHASE]: ANA_TX
7183 13:58:55.752129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7184 13:58:55.755182 ===================================
7185 13:58:55.758754 data_rate = 3200,PCW = 0X7600
7186 13:58:55.761800 ===================================
7187 13:58:55.764903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7188 13:58:55.768149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 13:58:55.775576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 13:58:55.778468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7191 13:58:55.781372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7192 13:58:55.788014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7193 13:58:55.788489 [ANA_INIT] flow start
7194 13:58:55.791532 [ANA_INIT] PLL >>>>>>>>
7195 13:58:55.794608 [ANA_INIT] PLL <<<<<<<<
7196 13:58:55.795164 [ANA_INIT] MIDPI >>>>>>>>
7197 13:58:55.797930 [ANA_INIT] MIDPI <<<<<<<<
7198 13:58:55.801823 [ANA_INIT] DLL >>>>>>>>
7199 13:58:55.802381 [ANA_INIT] DLL <<<<<<<<
7200 13:58:55.804323 [ANA_INIT] flow end
7201 13:58:55.807965 ============ LP4 DIFF to SE enter ============
7202 13:58:55.811155 ============ LP4 DIFF to SE exit ============
7203 13:58:55.814428 [ANA_INIT] <<<<<<<<<<<<<
7204 13:58:55.817890 [Flow] Enable top DCM control >>>>>
7205 13:58:55.821618 [Flow] Enable top DCM control <<<<<
7206 13:58:55.824398 Enable DLL master slave shuffle
7207 13:58:55.831766 ==============================================================
7208 13:58:55.832331 Gating Mode config
7209 13:58:55.837503 ==============================================================
7210 13:58:55.841024 Config description:
7211 13:58:55.848300 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7212 13:58:55.854275 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7213 13:58:55.860533 SELPH_MODE 0: By rank 1: By Phase
7214 13:58:55.867173 ==============================================================
7215 13:58:55.867787 GAT_TRACK_EN = 1
7216 13:58:55.870785 RX_GATING_MODE = 2
7217 13:58:55.874146 RX_GATING_TRACK_MODE = 2
7218 13:58:55.876735 SELPH_MODE = 1
7219 13:58:55.880744 PICG_EARLY_EN = 1
7220 13:58:55.884020 VALID_LAT_VALUE = 1
7221 13:58:55.890353 ==============================================================
7222 13:58:55.894453 Enter into Gating configuration >>>>
7223 13:58:55.897392 Exit from Gating configuration <<<<
7224 13:58:55.900197 Enter into DVFS_PRE_config >>>>>
7225 13:58:55.910686 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7226 13:58:55.913457 Exit from DVFS_PRE_config <<<<<
7227 13:58:55.916652 Enter into PICG configuration >>>>
7228 13:58:55.920082 Exit from PICG configuration <<<<
7229 13:58:55.923603 [RX_INPUT] configuration >>>>>
7230 13:58:55.927023 [RX_INPUT] configuration <<<<<
7231 13:58:55.930777 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7232 13:58:55.936407 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7233 13:58:55.942974 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 13:58:55.949951 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 13:58:55.953965 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 13:58:55.959399 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 13:58:55.962642 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7238 13:58:55.969579 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7239 13:58:55.972952 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7240 13:58:55.976090 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7241 13:58:55.979077 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7242 13:58:55.986049 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 13:58:55.988982 ===================================
7244 13:58:55.992242 LPDDR4 DRAM CONFIGURATION
7245 13:58:55.996082 ===================================
7246 13:58:55.996685 EX_ROW_EN[0] = 0x0
7247 13:58:55.998874 EX_ROW_EN[1] = 0x0
7248 13:58:55.999348 LP4Y_EN = 0x0
7249 13:58:56.002771 WORK_FSP = 0x1
7250 13:58:56.003329 WL = 0x5
7251 13:58:56.005369 RL = 0x5
7252 13:58:56.005838 BL = 0x2
7253 13:58:56.008940 RPST = 0x0
7254 13:58:56.009499 RD_PRE = 0x0
7255 13:58:56.012557 WR_PRE = 0x1
7256 13:58:56.013026 WR_PST = 0x1
7257 13:58:56.016016 DBI_WR = 0x0
7258 13:58:56.016475 DBI_RD = 0x0
7259 13:58:56.019293 OTF = 0x1
7260 13:58:56.022247 ===================================
7261 13:58:56.025376 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7262 13:58:56.029031 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7263 13:58:56.035236 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7264 13:58:56.039175 ===================================
7265 13:58:56.042253 LPDDR4 DRAM CONFIGURATION
7266 13:58:56.042810 ===================================
7267 13:58:56.045345 EX_ROW_EN[0] = 0x10
7268 13:58:56.048411 EX_ROW_EN[1] = 0x0
7269 13:58:56.048873 LP4Y_EN = 0x0
7270 13:58:56.051953 WORK_FSP = 0x1
7271 13:58:56.052426 WL = 0x5
7272 13:58:56.055503 RL = 0x5
7273 13:58:56.056125 BL = 0x2
7274 13:58:56.058386 RPST = 0x0
7275 13:58:56.059010 RD_PRE = 0x0
7276 13:58:56.061513 WR_PRE = 0x1
7277 13:58:56.062132 WR_PST = 0x1
7278 13:58:56.064943 DBI_WR = 0x0
7279 13:58:56.065410 DBI_RD = 0x0
7280 13:58:56.068576 OTF = 0x1
7281 13:58:56.072023 ===================================
7282 13:58:56.078125 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7283 13:58:56.078678 ==
7284 13:58:56.081549 Dram Type= 6, Freq= 0, CH_0, rank 0
7285 13:58:56.084538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7286 13:58:56.085030 ==
7287 13:58:56.087959 [Duty_Offset_Calibration]
7288 13:58:56.088428 B0:1 B1:-1 CA:0
7289 13:58:56.091894
7290 13:58:56.094518 [DutyScan_Calibration_Flow] k_type=0
7291 13:58:56.102691
7292 13:58:56.103242 ==CLK 0==
7293 13:58:56.106009 Final CLK duty delay cell = 0
7294 13:58:56.109454 [0] MAX Duty = 5125%(X100), DQS PI = 20
7295 13:58:56.113091 [0] MIN Duty = 4907%(X100), DQS PI = 4
7296 13:58:56.116025 [0] AVG Duty = 5016%(X100)
7297 13:58:56.116499
7298 13:58:56.119331 CH0 CLK Duty spec in!! Max-Min= 218%
7299 13:58:56.122920 [DutyScan_Calibration_Flow] ====Done====
7300 13:58:56.123483
7301 13:58:56.125967 [DutyScan_Calibration_Flow] k_type=1
7302 13:58:56.142251
7303 13:58:56.142804 ==DQS 0 ==
7304 13:58:56.145084 Final DQS duty delay cell = -4
7305 13:58:56.148803 [-4] MAX Duty = 5000%(X100), DQS PI = 36
7306 13:58:56.151706 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7307 13:58:56.155281 [-4] AVG Duty = 4922%(X100)
7308 13:58:56.156108
7309 13:58:56.156749 ==DQS 1 ==
7310 13:58:56.158754 Final DQS duty delay cell = 0
7311 13:58:56.161521 [0] MAX Duty = 5156%(X100), DQS PI = 0
7312 13:58:56.165620 [0] MIN Duty = 5031%(X100), DQS PI = 18
7313 13:58:56.168233 [0] AVG Duty = 5093%(X100)
7314 13:58:56.168698
7315 13:58:56.171651 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7316 13:58:56.172167
7317 13:58:56.174737 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7318 13:58:56.179208 [DutyScan_Calibration_Flow] ====Done====
7319 13:58:56.179632
7320 13:58:56.181662 [DutyScan_Calibration_Flow] k_type=3
7321 13:58:56.199502
7322 13:58:56.200036 ==DQM 0 ==
7323 13:58:56.202632 Final DQM duty delay cell = 0
7324 13:58:56.205706 [0] MAX Duty = 5124%(X100), DQS PI = 20
7325 13:58:56.209740 [0] MIN Duty = 4907%(X100), DQS PI = 10
7326 13:58:56.212589 [0] AVG Duty = 5015%(X100)
7327 13:58:56.213046
7328 13:58:56.213406 ==DQM 1 ==
7329 13:58:56.215888 Final DQM duty delay cell = 0
7330 13:58:56.219021 [0] MAX Duty = 5031%(X100), DQS PI = 54
7331 13:58:56.222516 [0] MIN Duty = 4813%(X100), DQS PI = 20
7332 13:58:56.225560 [0] AVG Duty = 4922%(X100)
7333 13:58:56.226018
7334 13:58:56.229297 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7335 13:58:56.229824
7336 13:58:56.233111 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7337 13:58:56.236304 [DutyScan_Calibration_Flow] ====Done====
7338 13:58:56.236856
7339 13:58:56.240182 [DutyScan_Calibration_Flow] k_type=2
7340 13:58:56.256336
7341 13:58:56.256891 ==DQ 0 ==
7342 13:58:56.259064 Final DQ duty delay cell = -4
7343 13:58:56.262420 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7344 13:58:56.265800 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7345 13:58:56.268947 [-4] AVG Duty = 4953%(X100)
7346 13:58:56.269500
7347 13:58:56.269867 ==DQ 1 ==
7348 13:58:56.272128 Final DQ duty delay cell = 0
7349 13:58:56.276219 [0] MAX Duty = 5125%(X100), DQS PI = 2
7350 13:58:56.278643 [0] MIN Duty = 5000%(X100), DQS PI = 36
7351 13:58:56.282347 [0] AVG Duty = 5062%(X100)
7352 13:58:56.282811
7353 13:58:56.285756 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7354 13:58:56.286213
7355 13:58:56.288693 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7356 13:58:56.292123 [DutyScan_Calibration_Flow] ====Done====
7357 13:58:56.292596 ==
7358 13:58:56.295536 Dram Type= 6, Freq= 0, CH_1, rank 0
7359 13:58:56.298687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7360 13:58:56.299148 ==
7361 13:58:56.302314 [Duty_Offset_Calibration]
7362 13:58:56.302883 B0:-1 B1:1 CA:2
7363 13:58:56.303253
7364 13:58:56.305089 [DutyScan_Calibration_Flow] k_type=0
7365 13:58:56.316472
7366 13:58:56.316989 ==CLK 0==
7367 13:58:56.319955 Final CLK duty delay cell = 0
7368 13:58:56.323401 [0] MAX Duty = 5187%(X100), DQS PI = 24
7369 13:58:56.326601 [0] MIN Duty = 4969%(X100), DQS PI = 62
7370 13:58:56.329507 [0] AVG Duty = 5078%(X100)
7371 13:58:56.330070
7372 13:58:56.333349 CH1 CLK Duty spec in!! Max-Min= 218%
7373 13:58:56.336322 [DutyScan_Calibration_Flow] ====Done====
7374 13:58:56.336785
7375 13:58:56.339887 [DutyScan_Calibration_Flow] k_type=1
7376 13:58:56.356319
7377 13:58:56.356880 ==DQS 0 ==
7378 13:58:56.359614 Final DQS duty delay cell = 0
7379 13:58:56.362752 [0] MAX Duty = 5125%(X100), DQS PI = 20
7380 13:58:56.366316 [0] MIN Duty = 4907%(X100), DQS PI = 10
7381 13:58:56.369206 [0] AVG Duty = 5016%(X100)
7382 13:58:56.369765
7383 13:58:56.370133 ==DQS 1 ==
7384 13:58:56.372933 Final DQS duty delay cell = 0
7385 13:58:56.375874 [0] MAX Duty = 5093%(X100), DQS PI = 24
7386 13:58:56.379474 [0] MIN Duty = 4969%(X100), DQS PI = 56
7387 13:58:56.382518 [0] AVG Duty = 5031%(X100)
7388 13:58:56.383074
7389 13:58:56.385947 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7390 13:58:56.386411
7391 13:58:56.389054 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7392 13:58:56.392270 [DutyScan_Calibration_Flow] ====Done====
7393 13:58:56.392729
7394 13:58:56.395819 [DutyScan_Calibration_Flow] k_type=3
7395 13:58:56.413137
7396 13:58:56.413683 ==DQM 0 ==
7397 13:58:56.416886 Final DQM duty delay cell = 0
7398 13:58:56.419479 [0] MAX Duty = 5218%(X100), DQS PI = 18
7399 13:58:56.423008 [0] MIN Duty = 5031%(X100), DQS PI = 8
7400 13:58:56.426882 [0] AVG Duty = 5124%(X100)
7401 13:58:56.427441
7402 13:58:56.427869 ==DQM 1 ==
7403 13:58:56.430009 Final DQM duty delay cell = 0
7404 13:58:56.432803 [0] MAX Duty = 5125%(X100), DQS PI = 0
7405 13:58:56.435993 [0] MIN Duty = 4969%(X100), DQS PI = 28
7406 13:58:56.439427 [0] AVG Duty = 5047%(X100)
7407 13:58:56.440026
7408 13:58:56.443003 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7409 13:58:56.443556
7410 13:58:56.446018 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7411 13:58:56.449692 [DutyScan_Calibration_Flow] ====Done====
7412 13:58:56.450247
7413 13:58:56.452634 [DutyScan_Calibration_Flow] k_type=2
7414 13:58:56.470020
7415 13:58:56.470579 ==DQ 0 ==
7416 13:58:56.473482 Final DQ duty delay cell = 0
7417 13:58:56.476481 [0] MAX Duty = 5156%(X100), DQS PI = 30
7418 13:58:56.480022 [0] MIN Duty = 4906%(X100), DQS PI = 10
7419 13:58:56.483067 [0] AVG Duty = 5031%(X100)
7420 13:58:56.483625
7421 13:58:56.484021 ==DQ 1 ==
7422 13:58:56.486306 Final DQ duty delay cell = 0
7423 13:58:56.489540 [0] MAX Duty = 5156%(X100), DQS PI = 8
7424 13:58:56.492719 [0] MIN Duty = 4938%(X100), DQS PI = 58
7425 13:58:56.493189 [0] AVG Duty = 5047%(X100)
7426 13:58:56.496155
7427 13:58:56.499521 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7428 13:58:56.500046
7429 13:58:56.502545 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7430 13:58:56.505755 [DutyScan_Calibration_Flow] ====Done====
7431 13:58:56.509500 nWR fixed to 30
7432 13:58:56.512541 [ModeRegInit_LP4] CH0 RK0
7433 13:58:56.513114 [ModeRegInit_LP4] CH0 RK1
7434 13:58:56.515943 [ModeRegInit_LP4] CH1 RK0
7435 13:58:56.519110 [ModeRegInit_LP4] CH1 RK1
7436 13:58:56.519688 match AC timing 5
7437 13:58:56.525602 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7438 13:58:56.529042 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7439 13:58:56.532399 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7440 13:58:56.538970 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7441 13:58:56.542274 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7442 13:58:56.542849 [MiockJmeterHQA]
7443 13:58:56.543340
7444 13:58:56.546094 [DramcMiockJmeter] u1RxGatingPI = 0
7445 13:58:56.549298 0 : 4252, 4027
7446 13:58:56.549883 4 : 4252, 4027
7447 13:58:56.552925 8 : 4255, 4029
7448 13:58:56.553505 12 : 4258, 4029
7449 13:58:56.555299 16 : 4252, 4027
7450 13:58:56.555841 20 : 4363, 4137
7451 13:58:56.556339 24 : 4252, 4026
7452 13:58:56.558735 28 : 4363, 4137
7453 13:58:56.559389 32 : 4257, 4029
7454 13:58:56.562367 36 : 4257, 4029
7455 13:58:56.562857 40 : 4253, 4027
7456 13:58:56.565280 44 : 4252, 4027
7457 13:58:56.565772 48 : 4363, 4137
7458 13:58:56.569124 52 : 4252, 4027
7459 13:58:56.569705 56 : 4363, 4137
7460 13:58:56.570204 60 : 4365, 4140
7461 13:58:56.571782 64 : 4252, 4030
7462 13:58:56.572281 68 : 4252, 4029
7463 13:58:56.575425 72 : 4361, 4137
7464 13:58:56.576057 76 : 4250, 4027
7465 13:58:56.578174 80 : 4363, 4140
7466 13:58:56.578665 84 : 4255, 4029
7467 13:58:56.582021 88 : 4250, 4026
7468 13:58:56.582599 92 : 4250, 924
7469 13:58:56.583101 96 : 4366, 0
7470 13:58:56.585366 100 : 4249, 0
7471 13:58:56.585857 104 : 4252, 0
7472 13:58:56.586362 108 : 4252, 0
7473 13:58:56.588404 112 : 4252, 0
7474 13:58:56.588895 116 : 4363, 0
7475 13:58:56.592096 120 : 4252, 0
7476 13:58:56.592553 124 : 4250, 0
7477 13:58:56.593006 128 : 4257, 0
7478 13:58:56.595297 132 : 4361, 0
7479 13:58:56.595822 136 : 4250, 0
7480 13:58:56.598956 140 : 4254, 0
7481 13:58:56.599533 144 : 4250, 0
7482 13:58:56.600083 148 : 4363, 0
7483 13:58:56.601471 152 : 4250, 0
7484 13:58:56.601963 156 : 4250, 0
7485 13:58:56.605376 160 : 4250, 0
7486 13:58:56.605863 164 : 4253, 0
7487 13:58:56.606480 168 : 4363, 0
7488 13:58:56.608865 172 : 4250, 0
7489 13:58:56.609402 176 : 4250, 0
7490 13:58:56.611606 180 : 4254, 0
7491 13:58:56.612093 184 : 4363, 0
7492 13:58:56.612549 188 : 4250, 0
7493 13:58:56.615177 192 : 4254, 0
7494 13:58:56.615711 196 : 4253, 0
7495 13:58:56.616218 200 : 4360, 0
7496 13:58:56.618256 204 : 4250, 0
7497 13:58:56.618790 208 : 4250, 0
7498 13:58:56.621618 212 : 4250, 0
7499 13:58:56.622167 216 : 4253, 0
7500 13:58:56.622621 220 : 4360, 0
7501 13:58:56.624729 224 : 4250, 165
7502 13:58:56.625173 228 : 4249, 3475
7503 13:58:56.628204 232 : 4250, 4027
7504 13:58:56.628652 236 : 4250, 4026
7505 13:58:56.631914 240 : 4250, 4027
7506 13:58:56.632451 244 : 4360, 4138
7507 13:58:56.635095 248 : 4250, 4026
7508 13:58:56.635659 252 : 4360, 4137
7509 13:58:56.638008 256 : 4361, 4137
7510 13:58:56.638452 260 : 4361, 4137
7511 13:58:56.641742 264 : 4250, 4026
7512 13:58:56.642274 268 : 4363, 4140
7513 13:58:56.644568 272 : 4252, 4029
7514 13:58:56.645012 276 : 4250, 4027
7515 13:58:56.645465 280 : 4252, 4030
7516 13:58:56.648239 284 : 4252, 4029
7517 13:58:56.648681 288 : 4252, 4029
7518 13:58:56.651592 292 : 4250, 4027
7519 13:58:56.652170 296 : 4363, 4140
7520 13:58:56.654480 300 : 4250, 4026
7521 13:58:56.654927 304 : 4360, 4137
7522 13:58:56.658059 308 : 4363, 4140
7523 13:58:56.658595 312 : 4361, 4137
7524 13:58:56.661177 316 : 4250, 4027
7525 13:58:56.661623 320 : 4363, 4139
7526 13:58:56.664228 324 : 4252, 4030
7527 13:58:56.664769 328 : 4250, 4027
7528 13:58:56.667879 332 : 4249, 4027
7529 13:58:56.668427 336 : 4252, 3849
7530 13:58:56.671353 340 : 4252, 1964
7531 13:58:56.672136
7532 13:58:56.672533 MIOCK jitter meter ch=0
7533 13:58:56.672859
7534 13:58:56.675103 1T = (340-92) = 248 dly cells
7535 13:58:56.680710 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7536 13:58:56.681139 ==
7537 13:58:56.684179 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 13:58:56.687320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 13:58:56.687777 ==
7540 13:58:56.693841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7541 13:58:56.697518 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7542 13:58:56.700343 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7543 13:58:56.707278 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7544 13:58:56.717619 [CA 0] Center 43 (13~74) winsize 62
7545 13:58:56.720411 [CA 1] Center 43 (13~74) winsize 62
7546 13:58:56.723570 [CA 2] Center 39 (10~68) winsize 59
7547 13:58:56.727581 [CA 3] Center 39 (9~69) winsize 61
7548 13:58:56.731200 [CA 4] Center 37 (8~66) winsize 59
7549 13:58:56.733465 [CA 5] Center 36 (7~66) winsize 60
7550 13:58:56.733936
7551 13:58:56.736574 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7552 13:58:56.737042
7553 13:58:56.743270 [CATrainingPosCal] consider 1 rank data
7554 13:58:56.743882 u2DelayCellTimex100 = 262/100 ps
7555 13:58:56.750514 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7556 13:58:56.753475 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7557 13:58:56.756923 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7558 13:58:56.760121 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7559 13:58:56.763124 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7560 13:58:56.766457 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7561 13:58:56.766921
7562 13:58:56.770334 CA PerBit enable=1, Macro0, CA PI delay=36
7563 13:58:56.770892
7564 13:58:56.772900 [CBTSetCACLKResult] CA Dly = 36
7565 13:58:56.776596 CS Dly: 12 (0~43)
7566 13:58:56.779847 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7567 13:58:56.783380 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7568 13:58:56.784006 ==
7569 13:58:56.786577 Dram Type= 6, Freq= 0, CH_0, rank 1
7570 13:58:56.792702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 13:58:56.793266 ==
7572 13:58:56.796569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7573 13:58:56.802935 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7574 13:58:56.806210 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7575 13:58:56.813338 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7576 13:58:56.820824 [CA 0] Center 43 (13~74) winsize 62
7577 13:58:56.824096 [CA 1] Center 44 (14~74) winsize 61
7578 13:58:56.827247 [CA 2] Center 38 (9~68) winsize 60
7579 13:58:56.830915 [CA 3] Center 38 (9~68) winsize 60
7580 13:58:56.833286 [CA 4] Center 36 (7~66) winsize 60
7581 13:58:56.836887 [CA 5] Center 36 (6~66) winsize 61
7582 13:58:56.837458
7583 13:58:56.840672 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7584 13:58:56.841247
7585 13:58:56.846949 [CATrainingPosCal] consider 2 rank data
7586 13:58:56.847526 u2DelayCellTimex100 = 262/100 ps
7587 13:58:56.853790 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7588 13:58:56.856666 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7589 13:58:56.860119 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7590 13:58:56.863085 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7591 13:58:56.866806 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7592 13:58:56.870081 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7593 13:58:56.870652
7594 13:58:56.873170 CA PerBit enable=1, Macro0, CA PI delay=36
7595 13:58:56.873653
7596 13:58:56.876692 [CBTSetCACLKResult] CA Dly = 36
7597 13:58:56.880026 CS Dly: 12 (0~44)
7598 13:58:56.883343 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7599 13:58:56.887206 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7600 13:58:56.887840
7601 13:58:56.889818 ----->DramcWriteLeveling(PI) begin...
7602 13:58:56.890396 ==
7603 13:58:56.893076 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 13:58:56.899713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 13:58:56.900325 ==
7606 13:58:56.903042 Write leveling (Byte 0): 36 => 36
7607 13:58:56.906471 Write leveling (Byte 1): 27 => 27
7608 13:58:56.909344 DramcWriteLeveling(PI) end<-----
7609 13:58:56.909947
7610 13:58:56.910472 ==
7611 13:58:56.912566 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 13:58:56.915866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 13:58:56.916263 ==
7614 13:58:56.919871 [Gating] SW mode calibration
7615 13:58:56.925869 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7616 13:58:56.932554 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7617 13:58:56.936549 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 13:58:56.939129 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 13:58:56.945640 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 13:58:56.949343 1 4 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7621 13:58:56.952646 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7622 13:58:56.958749 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7623 13:58:56.962053 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
7624 13:58:56.965106 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 13:58:56.972405 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 13:58:56.975161 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 13:58:56.979087 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7628 13:58:56.985384 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
7629 13:58:56.988547 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7630 13:58:56.992226 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
7631 13:58:56.998124 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7632 13:58:57.002104 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 13:58:57.005147 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 13:58:57.011228 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 13:58:57.015493 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 13:58:57.018241 1 6 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
7637 13:58:57.024737 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7638 13:58:57.028033 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7639 13:58:57.031009 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7640 13:58:57.037919 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 13:58:57.040778 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 13:58:57.044893 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 13:58:57.051582 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 13:58:57.055176 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7645 13:58:57.057800 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7646 13:58:57.065091 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7647 13:58:57.067625 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7648 13:58:57.070764 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 13:58:57.077404 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 13:58:57.081281 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 13:58:57.084676 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 13:58:57.090779 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 13:58:57.093789 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 13:58:57.097665 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 13:58:57.104093 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 13:58:57.107991 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 13:58:57.110504 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 13:58:57.117184 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 13:58:57.120173 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7660 13:58:57.123893 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7661 13:58:57.130849 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7662 13:58:57.131407 Total UI for P1: 0, mck2ui 16
7663 13:58:57.136916 best dqsien dly found for B0: ( 1, 9, 10)
7664 13:58:57.140186 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7665 13:58:57.143459 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7666 13:58:57.150326 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 13:58:57.150885 Total UI for P1: 0, mck2ui 16
7668 13:58:57.153975 best dqsien dly found for B1: ( 1, 9, 20)
7669 13:58:57.159931 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7670 13:58:57.163139 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7671 13:58:57.163601
7672 13:58:57.166591 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7673 13:58:57.170254 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7674 13:58:57.173429 [Gating] SW calibration Done
7675 13:58:57.173989 ==
7676 13:58:57.176322 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 13:58:57.179996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 13:58:57.180552 ==
7679 13:58:57.183229 RX Vref Scan: 0
7680 13:58:57.183809
7681 13:58:57.184179 RX Vref 0 -> 0, step: 1
7682 13:58:57.184519
7683 13:58:57.186146 RX Delay 0 -> 252, step: 8
7684 13:58:57.190078 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7685 13:58:57.196473 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7686 13:58:57.199364 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7687 13:58:57.203908 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7688 13:58:57.206742 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7689 13:58:57.210155 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7690 13:58:57.216447 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7691 13:58:57.220146 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7692 13:58:57.223013 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7693 13:58:57.226104 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7694 13:58:57.229151 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7695 13:58:57.236112 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7696 13:58:57.239635 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7697 13:58:57.242468 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7698 13:58:57.245951 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7699 13:58:57.252563 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7700 13:58:57.253127 ==
7701 13:58:57.255940 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 13:58:57.259270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 13:58:57.259906 ==
7704 13:58:57.260288 DQS Delay:
7705 13:58:57.262445 DQS0 = 0, DQS1 = 0
7706 13:58:57.262903 DQM Delay:
7707 13:58:57.266374 DQM0 = 136, DQM1 = 126
7708 13:58:57.266935 DQ Delay:
7709 13:58:57.268715 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7710 13:58:57.271981 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7711 13:58:57.275822 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7712 13:58:57.279049 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7713 13:58:57.279624
7714 13:58:57.280041
7715 13:58:57.282402 ==
7716 13:58:57.285893 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 13:58:57.288856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 13:58:57.289418 ==
7719 13:58:57.289787
7720 13:58:57.290124
7721 13:58:57.292050 TX Vref Scan disable
7722 13:58:57.292627 == TX Byte 0 ==
7723 13:58:57.298816 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7724 13:58:57.302015 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7725 13:58:57.302578 == TX Byte 1 ==
7726 13:58:57.308940 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7727 13:58:57.311595 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7728 13:58:57.312109 ==
7729 13:58:57.315379 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 13:58:57.317900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 13:58:57.318362 ==
7732 13:58:57.332532
7733 13:58:57.336408 TX Vref early break, caculate TX vref
7734 13:58:57.339020 TX Vref=16, minBit 4, minWin=22, winSum=371
7735 13:58:57.342336 TX Vref=18, minBit 1, minWin=23, winSum=379
7736 13:58:57.345666 TX Vref=20, minBit 1, minWin=24, winSum=392
7737 13:58:57.348540 TX Vref=22, minBit 3, minWin=24, winSum=401
7738 13:58:57.352592 TX Vref=24, minBit 3, minWin=24, winSum=404
7739 13:58:57.358820 TX Vref=26, minBit 0, minWin=25, winSum=416
7740 13:58:57.361878 TX Vref=28, minBit 0, minWin=25, winSum=415
7741 13:58:57.365598 TX Vref=30, minBit 0, minWin=24, winSum=411
7742 13:58:57.368351 TX Vref=32, minBit 0, minWin=24, winSum=403
7743 13:58:57.371921 TX Vref=34, minBit 4, minWin=23, winSum=385
7744 13:58:57.378415 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
7745 13:58:57.378979
7746 13:58:57.381927 Final TX Range 0 Vref 26
7747 13:58:57.382402
7748 13:58:57.382767 ==
7749 13:58:57.384941 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 13:58:57.389625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 13:58:57.390216 ==
7752 13:58:57.390592
7753 13:58:57.390931
7754 13:58:57.392070 TX Vref Scan disable
7755 13:58:57.398208 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7756 13:58:57.398677 == TX Byte 0 ==
7757 13:58:57.401731 u2DelayCellOfst[0]=14 cells (4 PI)
7758 13:58:57.405355 u2DelayCellOfst[1]=18 cells (5 PI)
7759 13:58:57.408055 u2DelayCellOfst[2]=14 cells (4 PI)
7760 13:58:57.411608 u2DelayCellOfst[3]=14 cells (4 PI)
7761 13:58:57.415951 u2DelayCellOfst[4]=11 cells (3 PI)
7762 13:58:57.417912 u2DelayCellOfst[5]=0 cells (0 PI)
7763 13:58:57.421466 u2DelayCellOfst[6]=18 cells (5 PI)
7764 13:58:57.424539 u2DelayCellOfst[7]=22 cells (6 PI)
7765 13:58:57.427957 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7766 13:58:57.431457 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7767 13:58:57.434281 == TX Byte 1 ==
7768 13:58:57.437720 u2DelayCellOfst[8]=0 cells (0 PI)
7769 13:58:57.440793 u2DelayCellOfst[9]=0 cells (0 PI)
7770 13:58:57.444681 u2DelayCellOfst[10]=3 cells (1 PI)
7771 13:58:57.447850 u2DelayCellOfst[11]=0 cells (0 PI)
7772 13:58:57.450783 u2DelayCellOfst[12]=11 cells (3 PI)
7773 13:58:57.454249 u2DelayCellOfst[13]=11 cells (3 PI)
7774 13:58:57.454815 u2DelayCellOfst[14]=11 cells (3 PI)
7775 13:58:57.457694 u2DelayCellOfst[15]=7 cells (2 PI)
7776 13:58:57.464460 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7777 13:58:57.467657 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7778 13:58:57.470619 DramC Write-DBI on
7779 13:58:57.471189 ==
7780 13:58:57.474015 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 13:58:57.477398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 13:58:57.477870 ==
7783 13:58:57.478242
7784 13:58:57.478587
7785 13:58:57.480789 TX Vref Scan disable
7786 13:58:57.481271 == TX Byte 0 ==
7787 13:58:57.487075 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7788 13:58:57.487629 == TX Byte 1 ==
7789 13:58:57.490179 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7790 13:58:57.493751 DramC Write-DBI off
7791 13:58:57.494305
7792 13:58:57.494676 [DATLAT]
7793 13:58:57.496829 Freq=1600, CH0 RK0
7794 13:58:57.497296
7795 13:58:57.497667 DATLAT Default: 0xf
7796 13:58:57.500658 0, 0xFFFF, sum = 0
7797 13:58:57.501129 1, 0xFFFF, sum = 0
7798 13:58:57.503470 2, 0xFFFF, sum = 0
7799 13:58:57.506531 3, 0xFFFF, sum = 0
7800 13:58:57.506998 4, 0xFFFF, sum = 0
7801 13:58:57.510530 5, 0xFFFF, sum = 0
7802 13:58:57.511034 6, 0xFFFF, sum = 0
7803 13:58:57.513400 7, 0xFFFF, sum = 0
7804 13:58:57.513970 8, 0xFFFF, sum = 0
7805 13:58:57.516625 9, 0xFFFF, sum = 0
7806 13:58:57.517098 10, 0xFFFF, sum = 0
7807 13:58:57.520360 11, 0xFFFF, sum = 0
7808 13:58:57.520939 12, 0xFFFF, sum = 0
7809 13:58:57.523527 13, 0xFFFF, sum = 0
7810 13:58:57.524180 14, 0x0, sum = 1
7811 13:58:57.526786 15, 0x0, sum = 2
7812 13:58:57.527369 16, 0x0, sum = 3
7813 13:58:57.530532 17, 0x0, sum = 4
7814 13:58:57.531125 best_step = 15
7815 13:58:57.531495
7816 13:58:57.531920 ==
7817 13:58:57.533151 Dram Type= 6, Freq= 0, CH_0, rank 0
7818 13:58:57.539968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7819 13:58:57.540536 ==
7820 13:58:57.540917 RX Vref Scan: 1
7821 13:58:57.541263
7822 13:58:57.543430 Set Vref Range= 24 -> 127
7823 13:58:57.544047
7824 13:58:57.546682 RX Vref 24 -> 127, step: 1
7825 13:58:57.547251
7826 13:58:57.547621 RX Delay 19 -> 252, step: 4
7827 13:58:57.548020
7828 13:58:57.549972 Set Vref, RX VrefLevel [Byte0]: 24
7829 13:58:57.553440 [Byte1]: 24
7830 13:58:57.557435
7831 13:58:57.558002 Set Vref, RX VrefLevel [Byte0]: 25
7832 13:58:57.560872 [Byte1]: 25
7833 13:58:57.564439
7834 13:58:57.564907 Set Vref, RX VrefLevel [Byte0]: 26
7835 13:58:57.568341 [Byte1]: 26
7836 13:58:57.572250
7837 13:58:57.572817 Set Vref, RX VrefLevel [Byte0]: 27
7838 13:58:57.575967 [Byte1]: 27
7839 13:58:57.579972
7840 13:58:57.580551 Set Vref, RX VrefLevel [Byte0]: 28
7841 13:58:57.583395 [Byte1]: 28
7842 13:58:57.587690
7843 13:58:57.588322 Set Vref, RX VrefLevel [Byte0]: 29
7844 13:58:57.590922 [Byte1]: 29
7845 13:58:57.595241
7846 13:58:57.595900 Set Vref, RX VrefLevel [Byte0]: 30
7847 13:58:57.598404 [Byte1]: 30
7848 13:58:57.602887
7849 13:58:57.603471 Set Vref, RX VrefLevel [Byte0]: 31
7850 13:58:57.606088 [Byte1]: 31
7851 13:58:57.610140
7852 13:58:57.610603 Set Vref, RX VrefLevel [Byte0]: 32
7853 13:58:57.613274 [Byte1]: 32
7854 13:58:57.618032
7855 13:58:57.618594 Set Vref, RX VrefLevel [Byte0]: 33
7856 13:58:57.620903 [Byte1]: 33
7857 13:58:57.625236
7858 13:58:57.625741 Set Vref, RX VrefLevel [Byte0]: 34
7859 13:58:57.628978 [Byte1]: 34
7860 13:58:57.633049
7861 13:58:57.633618 Set Vref, RX VrefLevel [Byte0]: 35
7862 13:58:57.635847 [Byte1]: 35
7863 13:58:57.640659
7864 13:58:57.641227 Set Vref, RX VrefLevel [Byte0]: 36
7865 13:58:57.644124 [Byte1]: 36
7866 13:58:57.648039
7867 13:58:57.648504 Set Vref, RX VrefLevel [Byte0]: 37
7868 13:58:57.651384 [Byte1]: 37
7869 13:58:57.655759
7870 13:58:57.659298 Set Vref, RX VrefLevel [Byte0]: 38
7871 13:58:57.662287 [Byte1]: 38
7872 13:58:57.662849
7873 13:58:57.664926 Set Vref, RX VrefLevel [Byte0]: 39
7874 13:58:57.668748 [Byte1]: 39
7875 13:58:57.669318
7876 13:58:57.671919 Set Vref, RX VrefLevel [Byte0]: 40
7877 13:58:57.675159 [Byte1]: 40
7878 13:58:57.675712
7879 13:58:57.678399 Set Vref, RX VrefLevel [Byte0]: 41
7880 13:58:57.681771 [Byte1]: 41
7881 13:58:57.685901
7882 13:58:57.686461 Set Vref, RX VrefLevel [Byte0]: 42
7883 13:58:57.692457 [Byte1]: 42
7884 13:58:57.693017
7885 13:58:57.696068 Set Vref, RX VrefLevel [Byte0]: 43
7886 13:58:57.699184 [Byte1]: 43
7887 13:58:57.699803
7888 13:58:57.702249 Set Vref, RX VrefLevel [Byte0]: 44
7889 13:58:57.705373 [Byte1]: 44
7890 13:58:57.705932
7891 13:58:57.708841 Set Vref, RX VrefLevel [Byte0]: 45
7892 13:58:57.712111 [Byte1]: 45
7893 13:58:57.716331
7894 13:58:57.716895 Set Vref, RX VrefLevel [Byte0]: 46
7895 13:58:57.719527 [Byte1]: 46
7896 13:58:57.723936
7897 13:58:57.724498 Set Vref, RX VrefLevel [Byte0]: 47
7898 13:58:57.726920 [Byte1]: 47
7899 13:58:57.731581
7900 13:58:57.732198 Set Vref, RX VrefLevel [Byte0]: 48
7901 13:58:57.734923 [Byte1]: 48
7902 13:58:57.739209
7903 13:58:57.739809 Set Vref, RX VrefLevel [Byte0]: 49
7904 13:58:57.742174 [Byte1]: 49
7905 13:58:57.746768
7906 13:58:57.747319 Set Vref, RX VrefLevel [Byte0]: 50
7907 13:58:57.750153 [Byte1]: 50
7908 13:58:57.753969
7909 13:58:57.754518 Set Vref, RX VrefLevel [Byte0]: 51
7910 13:58:57.757662 [Byte1]: 51
7911 13:58:57.762108
7912 13:58:57.762663 Set Vref, RX VrefLevel [Byte0]: 52
7913 13:58:57.764758 [Byte1]: 52
7914 13:58:57.769328
7915 13:58:57.769883 Set Vref, RX VrefLevel [Byte0]: 53
7916 13:58:57.772289 [Byte1]: 53
7917 13:58:57.776709
7918 13:58:57.777173 Set Vref, RX VrefLevel [Byte0]: 54
7919 13:58:57.780310 [Byte1]: 54
7920 13:58:57.784183
7921 13:58:57.784642 Set Vref, RX VrefLevel [Byte0]: 55
7922 13:58:57.787703 [Byte1]: 55
7923 13:58:57.792833
7924 13:58:57.793387 Set Vref, RX VrefLevel [Byte0]: 56
7925 13:58:57.795533 [Byte1]: 56
7926 13:58:57.799971
7927 13:58:57.800436 Set Vref, RX VrefLevel [Byte0]: 57
7928 13:58:57.803081 [Byte1]: 57
7929 13:58:57.807228
7930 13:58:57.807842 Set Vref, RX VrefLevel [Byte0]: 58
7931 13:58:57.810229 [Byte1]: 58
7932 13:58:57.815208
7933 13:58:57.815635 Set Vref, RX VrefLevel [Byte0]: 59
7934 13:58:57.817586 [Byte1]: 59
7935 13:58:57.822452
7936 13:58:57.822990 Set Vref, RX VrefLevel [Byte0]: 60
7937 13:58:57.825576 [Byte1]: 60
7938 13:58:57.829798
7939 13:58:57.830364 Set Vref, RX VrefLevel [Byte0]: 61
7940 13:58:57.833434 [Byte1]: 61
7941 13:58:57.837412
7942 13:58:57.837975 Set Vref, RX VrefLevel [Byte0]: 62
7943 13:58:57.841312 [Byte1]: 62
7944 13:58:57.845018
7945 13:58:57.845579 Set Vref, RX VrefLevel [Byte0]: 63
7946 13:58:57.847837 [Byte1]: 63
7947 13:58:57.852414
7948 13:58:57.852991 Set Vref, RX VrefLevel [Byte0]: 64
7949 13:58:57.855613 [Byte1]: 64
7950 13:58:57.860306
7951 13:58:57.860872 Set Vref, RX VrefLevel [Byte0]: 65
7952 13:58:57.863250 [Byte1]: 65
7953 13:58:57.867519
7954 13:58:57.868128 Set Vref, RX VrefLevel [Byte0]: 66
7955 13:58:57.870782 [Byte1]: 66
7956 13:58:57.875795
7957 13:58:57.876360 Set Vref, RX VrefLevel [Byte0]: 67
7958 13:58:57.878755 [Byte1]: 67
7959 13:58:57.882831
7960 13:58:57.883310 Set Vref, RX VrefLevel [Byte0]: 68
7961 13:58:57.885810 [Byte1]: 68
7962 13:58:57.890674
7963 13:58:57.891238 Set Vref, RX VrefLevel [Byte0]: 69
7964 13:58:57.894266 [Byte1]: 69
7965 13:58:57.897713
7966 13:58:57.898202 Set Vref, RX VrefLevel [Byte0]: 70
7967 13:58:57.901171 [Byte1]: 70
7968 13:58:57.905980
7969 13:58:57.906550 Set Vref, RX VrefLevel [Byte0]: 71
7970 13:58:57.908510 [Byte1]: 71
7971 13:58:57.913458
7972 13:58:57.914034 Set Vref, RX VrefLevel [Byte0]: 72
7973 13:58:57.916281 [Byte1]: 72
7974 13:58:57.920603
7975 13:58:57.921171 Set Vref, RX VrefLevel [Byte0]: 73
7976 13:58:57.923702 [Byte1]: 73
7977 13:58:57.928247
7978 13:58:57.928812 Set Vref, RX VrefLevel [Byte0]: 74
7979 13:58:57.931972 [Byte1]: 74
7980 13:58:57.935676
7981 13:58:57.936308 Set Vref, RX VrefLevel [Byte0]: 75
7982 13:58:57.939221 [Byte1]: 75
7983 13:58:57.943685
7984 13:58:57.944303 Set Vref, RX VrefLevel [Byte0]: 76
7985 13:58:57.946673 [Byte1]: 76
7986 13:58:57.950697
7987 13:58:57.951420 Set Vref, RX VrefLevel [Byte0]: 77
7988 13:58:57.953845 [Byte1]: 77
7989 13:58:57.958669
7990 13:58:57.959222 Set Vref, RX VrefLevel [Byte0]: 78
7991 13:58:57.961727 [Byte1]: 78
7992 13:58:57.966423
7993 13:58:57.966951 Set Vref, RX VrefLevel [Byte0]: 79
7994 13:58:57.969472 [Byte1]: 79
7995 13:58:57.974649
7996 13:58:57.975167 Set Vref, RX VrefLevel [Byte0]: 80
7997 13:58:57.976944 [Byte1]: 80
7998 13:58:57.980983
7999 13:58:57.981424 Final RX Vref Byte 0 = 68 to rank0
8000 13:58:57.984296 Final RX Vref Byte 1 = 58 to rank0
8001 13:58:57.988177 Final RX Vref Byte 0 = 68 to rank1
8002 13:58:57.990843 Final RX Vref Byte 1 = 58 to rank1==
8003 13:58:57.994057 Dram Type= 6, Freq= 0, CH_0, rank 0
8004 13:58:58.000733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8005 13:58:58.001166 ==
8006 13:58:58.001607 DQS Delay:
8007 13:58:58.004283 DQS0 = 0, DQS1 = 0
8008 13:58:58.004854 DQM Delay:
8009 13:58:58.005270 DQM0 = 134, DQM1 = 122
8010 13:58:58.007530 DQ Delay:
8011 13:58:58.010778 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =134
8012 13:58:58.014310 DQ4 =134, DQ5 =122, DQ6 =142, DQ7 =142
8013 13:58:58.017840 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =116
8014 13:58:58.020968 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
8015 13:58:58.021478
8016 13:58:58.021812
8017 13:58:58.022118
8018 13:58:58.024591 [DramC_TX_OE_Calibration] TA2
8019 13:58:58.027481 Original DQ_B0 (3 6) =30, OEN = 27
8020 13:58:58.030834 Original DQ_B1 (3 6) =30, OEN = 27
8021 13:58:58.034361 24, 0x0, End_B0=24 End_B1=24
8022 13:58:58.037187 25, 0x0, End_B0=25 End_B1=25
8023 13:58:58.037617 26, 0x0, End_B0=26 End_B1=26
8024 13:58:58.040695 27, 0x0, End_B0=27 End_B1=27
8025 13:58:58.044321 28, 0x0, End_B0=28 End_B1=28
8026 13:58:58.047078 29, 0x0, End_B0=29 End_B1=29
8027 13:58:58.047504 30, 0x0, End_B0=30 End_B1=30
8028 13:58:58.050121 31, 0x5151, End_B0=30 End_B1=30
8029 13:58:58.054095 Byte0 end_step=30 best_step=27
8030 13:58:58.056644 Byte1 end_step=30 best_step=27
8031 13:58:58.060061 Byte0 TX OE(2T, 0.5T) = (3, 3)
8032 13:58:58.063496 Byte1 TX OE(2T, 0.5T) = (3, 3)
8033 13:58:58.064093
8034 13:58:58.064447
8035 13:58:58.070325 [DQSOSCAuto] RK0, (LSB)MR18= 0x2416, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
8036 13:58:58.073153 CH0 RK0: MR19=303, MR18=2416
8037 13:58:58.079866 CH0_RK0: MR19=0x303, MR18=0x2416, DQSOSC=391, MR23=63, INC=24, DEC=16
8038 13:58:58.080305
8039 13:58:58.083106 ----->DramcWriteLeveling(PI) begin...
8040 13:58:58.083587 ==
8041 13:58:58.086579 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 13:58:58.089687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 13:58:58.090146 ==
8044 13:58:58.093048 Write leveling (Byte 0): 36 => 36
8045 13:58:58.096190 Write leveling (Byte 1): 29 => 29
8046 13:58:58.099989 DramcWriteLeveling(PI) end<-----
8047 13:58:58.100423
8048 13:58:58.100859 ==
8049 13:58:58.103418 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 13:58:58.106486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 13:58:58.109754 ==
8052 13:58:58.110187 [Gating] SW mode calibration
8053 13:58:58.119615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8054 13:58:58.122729 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8055 13:58:58.126482 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 13:58:58.133549 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 13:58:58.136362 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 13:58:58.139338 1 4 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8059 13:58:58.146450 1 4 16 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8060 13:58:58.149460 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8061 13:58:58.152708 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 13:58:58.159608 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 13:58:58.163071 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 13:58:58.165710 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 13:58:58.173109 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 13:58:58.175953 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8067 13:58:58.178912 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
8068 13:58:58.185696 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
8069 13:58:58.189897 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 13:58:58.192780 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 13:58:58.199014 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 13:58:58.202355 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 13:58:58.205872 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 13:58:58.212763 1 6 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
8075 13:58:58.216249 1 6 16 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
8076 13:58:58.218626 1 6 20 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8077 13:58:58.225759 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 13:58:58.228690 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 13:58:58.232256 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 13:58:58.239378 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 13:58:58.242286 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 13:58:58.245238 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8083 13:58:58.251902 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8084 13:58:58.255080 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8085 13:58:58.258300 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 13:58:58.264877 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 13:58:58.268054 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 13:58:58.271886 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 13:58:58.278637 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 13:58:58.281669 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 13:58:58.284470 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 13:58:58.291357 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 13:58:58.294742 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 13:58:58.298454 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 13:58:58.304372 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 13:58:58.307848 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 13:58:58.311121 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 13:58:58.317873 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8099 13:58:58.321059 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8100 13:58:58.324359 Total UI for P1: 0, mck2ui 16
8101 13:58:58.327692 best dqsien dly found for B0: ( 1, 9, 12)
8102 13:58:58.330793 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8103 13:58:58.337809 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 13:58:58.338437 Total UI for P1: 0, mck2ui 16
8105 13:58:58.344175 best dqsien dly found for B1: ( 1, 9, 18)
8106 13:58:58.347417 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8107 13:58:58.350828 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8108 13:58:58.351387
8109 13:58:58.354142 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8110 13:58:58.357202 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8111 13:58:58.360821 [Gating] SW calibration Done
8112 13:58:58.361396 ==
8113 13:58:58.363945 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 13:58:58.367885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 13:58:58.368449 ==
8116 13:58:58.370525 RX Vref Scan: 0
8117 13:58:58.371221
8118 13:58:58.371667 RX Vref 0 -> 0, step: 1
8119 13:58:58.373600
8120 13:58:58.374062 RX Delay 0 -> 252, step: 8
8121 13:58:58.380568 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8122 13:58:58.383637 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8123 13:58:58.387299 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8124 13:58:58.390188 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8125 13:58:58.393408 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8126 13:58:58.397196 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8127 13:58:58.403900 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8128 13:58:58.407251 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8129 13:58:58.410793 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8130 13:58:58.413741 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8131 13:58:58.416599 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8132 13:58:58.424447 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8133 13:58:58.426998 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8134 13:58:58.430196 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8135 13:58:58.433950 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8136 13:58:58.440055 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8137 13:58:58.440612 ==
8138 13:58:58.443510 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 13:58:58.446789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 13:58:58.447358 ==
8141 13:58:58.447761 DQS Delay:
8142 13:58:58.449939 DQS0 = 0, DQS1 = 0
8143 13:58:58.450399 DQM Delay:
8144 13:58:58.453227 DQM0 = 133, DQM1 = 128
8145 13:58:58.453692 DQ Delay:
8146 13:58:58.456826 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8147 13:58:58.460023 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8148 13:58:58.463341 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8149 13:58:58.466322 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8150 13:58:58.466788
8151 13:58:58.469718
8152 13:58:58.470179 ==
8153 13:58:58.473024 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 13:58:58.476477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 13:58:58.476943 ==
8156 13:58:58.477312
8157 13:58:58.477767
8158 13:58:58.479484 TX Vref Scan disable
8159 13:58:58.480000 == TX Byte 0 ==
8160 13:58:58.487081 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8161 13:58:58.489865 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8162 13:58:58.490420 == TX Byte 1 ==
8163 13:58:58.495793 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8164 13:58:58.499307 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8165 13:58:58.499902 ==
8166 13:58:58.502581 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 13:58:58.506572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 13:58:58.507137 ==
8169 13:58:58.520202
8170 13:58:58.523566 TX Vref early break, caculate TX vref
8171 13:58:58.527365 TX Vref=16, minBit 5, minWin=22, winSum=380
8172 13:58:58.530154 TX Vref=18, minBit 0, minWin=23, winSum=385
8173 13:58:58.534042 TX Vref=20, minBit 0, minWin=23, winSum=399
8174 13:58:58.536726 TX Vref=22, minBit 1, minWin=23, winSum=404
8175 13:58:58.540100 TX Vref=24, minBit 1, minWin=24, winSum=415
8176 13:58:58.546750 TX Vref=26, minBit 1, minWin=24, winSum=420
8177 13:58:58.549957 TX Vref=28, minBit 1, minWin=24, winSum=415
8178 13:58:58.553421 TX Vref=30, minBit 0, minWin=24, winSum=409
8179 13:58:58.556322 TX Vref=32, minBit 0, minWin=24, winSum=399
8180 13:58:58.560112 TX Vref=34, minBit 1, minWin=23, winSum=389
8181 13:58:58.566324 [TxChooseVref] Worse bit 1, Min win 24, Win sum 420, Final Vref 26
8182 13:58:58.566869
8183 13:58:58.569860 Final TX Range 0 Vref 26
8184 13:58:58.570327
8185 13:58:58.570695 ==
8186 13:58:58.573141 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 13:58:58.576292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 13:58:58.576762 ==
8189 13:58:58.577134
8190 13:58:58.577471
8191 13:58:58.579595 TX Vref Scan disable
8192 13:58:58.585804 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8193 13:58:58.586346 == TX Byte 0 ==
8194 13:58:58.589502 u2DelayCellOfst[0]=11 cells (3 PI)
8195 13:58:58.592632 u2DelayCellOfst[1]=14 cells (4 PI)
8196 13:58:58.596331 u2DelayCellOfst[2]=11 cells (3 PI)
8197 13:58:58.599464 u2DelayCellOfst[3]=11 cells (3 PI)
8198 13:58:58.602497 u2DelayCellOfst[4]=7 cells (2 PI)
8199 13:58:58.605740 u2DelayCellOfst[5]=0 cells (0 PI)
8200 13:58:58.609607 u2DelayCellOfst[6]=14 cells (4 PI)
8201 13:58:58.612329 u2DelayCellOfst[7]=18 cells (5 PI)
8202 13:58:58.615984 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8203 13:58:58.619894 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8204 13:58:58.622512 == TX Byte 1 ==
8205 13:58:58.625947 u2DelayCellOfst[8]=0 cells (0 PI)
8206 13:58:58.629526 u2DelayCellOfst[9]=3 cells (1 PI)
8207 13:58:58.633261 u2DelayCellOfst[10]=7 cells (2 PI)
8208 13:58:58.633819 u2DelayCellOfst[11]=3 cells (1 PI)
8209 13:58:58.635678 u2DelayCellOfst[12]=14 cells (4 PI)
8210 13:58:58.639108 u2DelayCellOfst[13]=14 cells (4 PI)
8211 13:58:58.642565 u2DelayCellOfst[14]=18 cells (5 PI)
8212 13:58:58.645755 u2DelayCellOfst[15]=11 cells (3 PI)
8213 13:58:58.652343 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8214 13:58:58.655549 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8215 13:58:58.656348 DramC Write-DBI on
8216 13:58:58.659232 ==
8217 13:58:58.659850 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 13:58:58.665017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 13:58:58.665566 ==
8220 13:58:58.665933
8221 13:58:58.666471
8222 13:58:58.668459 TX Vref Scan disable
8223 13:58:58.668919 == TX Byte 0 ==
8224 13:58:58.675048 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8225 13:58:58.675635 == TX Byte 1 ==
8226 13:58:58.678275 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8227 13:58:58.681738 DramC Write-DBI off
8228 13:58:58.682303
8229 13:58:58.682793 [DATLAT]
8230 13:58:58.684488 Freq=1600, CH0 RK1
8231 13:58:58.684924
8232 13:58:58.685385 DATLAT Default: 0xf
8233 13:58:58.688506 0, 0xFFFF, sum = 0
8234 13:58:58.688993 1, 0xFFFF, sum = 0
8235 13:58:58.691248 2, 0xFFFF, sum = 0
8236 13:58:58.691854 3, 0xFFFF, sum = 0
8237 13:58:58.695455 4, 0xFFFF, sum = 0
8238 13:58:58.698288 5, 0xFFFF, sum = 0
8239 13:58:58.698772 6, 0xFFFF, sum = 0
8240 13:58:58.701664 7, 0xFFFF, sum = 0
8241 13:58:58.702153 8, 0xFFFF, sum = 0
8242 13:58:58.704386 9, 0xFFFF, sum = 0
8243 13:58:58.704871 10, 0xFFFF, sum = 0
8244 13:58:58.708336 11, 0xFFFF, sum = 0
8245 13:58:58.708906 12, 0xFFFF, sum = 0
8246 13:58:58.711049 13, 0xFFFF, sum = 0
8247 13:58:58.711536 14, 0x0, sum = 1
8248 13:58:58.714588 15, 0x0, sum = 2
8249 13:58:58.715025 16, 0x0, sum = 3
8250 13:58:58.717479 17, 0x0, sum = 4
8251 13:58:58.717916 best_step = 15
8252 13:58:58.718352
8253 13:58:58.718766 ==
8254 13:58:58.721098 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 13:58:58.724658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 13:58:58.727783 ==
8257 13:58:58.728316 RX Vref Scan: 0
8258 13:58:58.728761
8259 13:58:58.731543 RX Vref 0 -> 0, step: 1
8260 13:58:58.732020
8261 13:58:58.733871 RX Delay 11 -> 252, step: 4
8262 13:58:58.738080 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8263 13:58:58.741106 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8264 13:58:58.744250 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8265 13:58:58.750792 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8266 13:58:58.753749 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8267 13:58:58.757655 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8268 13:58:58.760936 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8269 13:58:58.764141 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8270 13:58:58.770732 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8271 13:58:58.774082 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8272 13:58:58.777231 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8273 13:58:58.780667 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8274 13:58:58.783402 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8275 13:58:58.790299 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8276 13:58:58.793379 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8277 13:58:58.797131 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8278 13:58:58.797761 ==
8279 13:58:58.800160 Dram Type= 6, Freq= 0, CH_0, rank 1
8280 13:58:58.806834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 13:58:58.807270 ==
8282 13:58:58.807601 DQS Delay:
8283 13:58:58.807970 DQS0 = 0, DQS1 = 0
8284 13:58:58.810041 DQM Delay:
8285 13:58:58.810455 DQM0 = 129, DQM1 = 125
8286 13:58:58.813339 DQ Delay:
8287 13:58:58.816993 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =128
8288 13:58:58.819787 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =140
8289 13:58:58.823181 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8290 13:58:58.826798 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8291 13:58:58.827321
8292 13:58:58.827795
8293 13:58:58.828217
8294 13:58:58.829977 [DramC_TX_OE_Calibration] TA2
8295 13:58:58.833390 Original DQ_B0 (3 6) =30, OEN = 27
8296 13:58:58.836714 Original DQ_B1 (3 6) =30, OEN = 27
8297 13:58:58.839814 24, 0x0, End_B0=24 End_B1=24
8298 13:58:58.840347 25, 0x0, End_B0=25 End_B1=25
8299 13:58:58.843089 26, 0x0, End_B0=26 End_B1=26
8300 13:58:58.846876 27, 0x0, End_B0=27 End_B1=27
8301 13:58:58.850084 28, 0x0, End_B0=28 End_B1=28
8302 13:58:58.853070 29, 0x0, End_B0=29 End_B1=29
8303 13:58:58.853602 30, 0x0, End_B0=30 End_B1=30
8304 13:58:58.856559 31, 0x4545, End_B0=30 End_B1=30
8305 13:58:58.859664 Byte0 end_step=30 best_step=27
8306 13:58:58.862905 Byte1 end_step=30 best_step=27
8307 13:58:58.866420 Byte0 TX OE(2T, 0.5T) = (3, 3)
8308 13:58:58.869270 Byte1 TX OE(2T, 0.5T) = (3, 3)
8309 13:58:58.869815
8310 13:58:58.870285
8311 13:58:58.876325 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8312 13:58:58.879100 CH0 RK1: MR19=303, MR18=2104
8313 13:58:58.885713 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8314 13:58:58.888809 [RxdqsGatingPostProcess] freq 1600
8315 13:58:58.892015 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8316 13:58:58.895820 best DQS0 dly(2T, 0.5T) = (1, 1)
8317 13:58:58.899002 best DQS1 dly(2T, 0.5T) = (1, 1)
8318 13:58:58.902246 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8319 13:58:58.905531 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8320 13:58:58.908798 best DQS0 dly(2T, 0.5T) = (1, 1)
8321 13:58:58.912201 best DQS1 dly(2T, 0.5T) = (1, 1)
8322 13:58:58.915932 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8323 13:58:58.918885 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8324 13:58:58.922160 Pre-setting of DQS Precalculation
8325 13:58:58.925154 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8326 13:58:58.925575 ==
8327 13:58:58.928659 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 13:58:58.934991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 13:58:58.935470 ==
8330 13:58:58.938746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8331 13:58:58.945295 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8332 13:58:58.948752 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8333 13:58:58.955308 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8334 13:58:58.962956 [CA 0] Center 41 (11~71) winsize 61
8335 13:58:58.966990 [CA 1] Center 42 (13~72) winsize 60
8336 13:58:58.969591 [CA 2] Center 37 (8~66) winsize 59
8337 13:58:58.973740 [CA 3] Center 35 (6~65) winsize 60
8338 13:58:58.976050 [CA 4] Center 36 (7~66) winsize 60
8339 13:58:58.979285 [CA 5] Center 36 (7~66) winsize 60
8340 13:58:58.979795
8341 13:58:58.983902 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8342 13:58:58.984465
8343 13:58:58.990149 [CATrainingPosCal] consider 1 rank data
8344 13:58:58.990705 u2DelayCellTimex100 = 262/100 ps
8345 13:58:58.995912 CA0 delay=41 (11~71),Diff = 6 PI (22 cell)
8346 13:58:58.999156 CA1 delay=42 (13~72),Diff = 7 PI (26 cell)
8347 13:58:59.003057 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8348 13:58:59.005870 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8349 13:58:59.008866 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8350 13:58:59.011935 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8351 13:58:59.012402
8352 13:58:59.015571 CA PerBit enable=1, Macro0, CA PI delay=35
8353 13:58:59.016079
8354 13:58:59.019042 [CBTSetCACLKResult] CA Dly = 35
8355 13:58:59.022210 CS Dly: 9 (0~40)
8356 13:58:59.025419 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8357 13:58:59.028475 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8358 13:58:59.028935 ==
8359 13:58:59.031787 Dram Type= 6, Freq= 0, CH_1, rank 1
8360 13:58:59.038635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 13:58:59.039184 ==
8362 13:58:59.042125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8363 13:58:59.048758 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8364 13:58:59.051681 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8365 13:58:59.058857 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8366 13:58:59.066382 [CA 0] Center 42 (14~71) winsize 58
8367 13:58:59.069340 [CA 1] Center 43 (13~73) winsize 61
8368 13:58:59.073071 [CA 2] Center 37 (8~67) winsize 60
8369 13:58:59.075667 [CA 3] Center 37 (8~67) winsize 60
8370 13:58:59.079689 [CA 4] Center 38 (9~67) winsize 59
8371 13:58:59.082795 [CA 5] Center 37 (8~67) winsize 60
8372 13:58:59.083344
8373 13:58:59.085792 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8374 13:58:59.086253
8375 13:58:59.089358 [CATrainingPosCal] consider 2 rank data
8376 13:58:59.092737 u2DelayCellTimex100 = 262/100 ps
8377 13:58:59.095830 CA0 delay=42 (14~71),Diff = 6 PI (22 cell)
8378 13:58:59.102496 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8379 13:58:59.105615 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8380 13:58:59.109012 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8381 13:58:59.112333 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8382 13:58:59.115312 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8383 13:58:59.115861
8384 13:58:59.119269 CA PerBit enable=1, Macro0, CA PI delay=36
8385 13:58:59.119773
8386 13:58:59.122185 [CBTSetCACLKResult] CA Dly = 36
8387 13:58:59.125032 CS Dly: 10 (0~43)
8388 13:58:59.128539 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8389 13:58:59.131644 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8390 13:58:59.132107
8391 13:58:59.135272 ----->DramcWriteLeveling(PI) begin...
8392 13:58:59.135698 ==
8393 13:58:59.138366 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 13:58:59.145279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 13:58:59.145894 ==
8396 13:58:59.148691 Write leveling (Byte 0): 24 => 24
8397 13:58:59.152011 Write leveling (Byte 1): 27 => 27
8398 13:58:59.152522 DramcWriteLeveling(PI) end<-----
8399 13:58:59.155316
8400 13:58:59.155756 ==
8401 13:58:59.158929 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 13:58:59.161811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 13:58:59.162275 ==
8404 13:58:59.164882 [Gating] SW mode calibration
8405 13:58:59.171932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8406 13:58:59.178449 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8407 13:58:59.181326 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 13:58:59.184718 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 13:58:59.191058 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8410 13:58:59.194995 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8411 13:58:59.197965 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 13:58:59.204868 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 13:58:59.207856 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 13:58:59.211022 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 13:58:59.217643 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 13:58:59.221034 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 13:58:59.224120 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8418 13:58:59.230779 1 5 12 | B1->B0 | 3030 2626 | 0 0 | (0 1) (1 0)
8419 13:58:59.234699 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 13:58:59.237196 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 13:58:59.243972 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 13:58:59.246835 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 13:58:59.250606 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 13:58:59.257325 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 13:58:59.260728 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8426 13:58:59.263296 1 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8427 13:58:59.270591 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 13:58:59.273770 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 13:58:59.276726 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 13:58:59.283111 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 13:58:59.286301 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 13:58:59.289950 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 13:58:59.296857 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 13:58:59.299921 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8435 13:58:59.303297 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8436 13:58:59.309334 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 13:58:59.312913 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 13:58:59.315989 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 13:58:59.323013 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 13:58:59.326450 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 13:58:59.329612 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 13:58:59.336473 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 13:58:59.338935 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 13:58:59.342982 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 13:58:59.349002 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 13:58:59.352724 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 13:58:59.355977 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 13:58:59.362690 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 13:58:59.365444 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8450 13:58:59.369022 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8451 13:58:59.375567 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 13:58:59.376174 Total UI for P1: 0, mck2ui 16
8453 13:58:59.381516 best dqsien dly found for B0: ( 1, 9, 10)
8454 13:58:59.381978 Total UI for P1: 0, mck2ui 16
8455 13:58:59.388483 best dqsien dly found for B1: ( 1, 9, 12)
8456 13:58:59.392468 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8457 13:58:59.394933 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8458 13:58:59.395354
8459 13:58:59.398525 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8460 13:58:59.401805 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8461 13:58:59.404964 [Gating] SW calibration Done
8462 13:58:59.405382 ==
8463 13:58:59.408376 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 13:58:59.411838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 13:58:59.412354 ==
8466 13:58:59.414803 RX Vref Scan: 0
8467 13:58:59.415217
8468 13:58:59.415547 RX Vref 0 -> 0, step: 1
8469 13:58:59.418353
8470 13:58:59.418863 RX Delay 0 -> 252, step: 8
8471 13:58:59.421426 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8472 13:58:59.428224 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8473 13:58:59.431611 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8474 13:58:59.434644 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8475 13:58:59.438797 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8476 13:58:59.441276 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8477 13:58:59.448002 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8478 13:58:59.451318 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8479 13:58:59.455048 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8480 13:58:59.457861 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8481 13:58:59.461406 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8482 13:58:59.467460 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8483 13:58:59.471254 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8484 13:58:59.474654 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8485 13:58:59.477633 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8486 13:58:59.484062 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8487 13:58:59.484618 ==
8488 13:58:59.487570 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 13:58:59.490644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 13:58:59.491199 ==
8491 13:58:59.491568 DQS Delay:
8492 13:58:59.493966 DQS0 = 0, DQS1 = 0
8493 13:58:59.494547 DQM Delay:
8494 13:58:59.497584 DQM0 = 137, DQM1 = 128
8495 13:58:59.498155 DQ Delay:
8496 13:58:59.500625 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8497 13:58:59.503934 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8498 13:58:59.506791 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8499 13:58:59.513375 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8500 13:58:59.513932
8501 13:58:59.514300
8502 13:58:59.514726 ==
8503 13:58:59.516733 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 13:58:59.520215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 13:58:59.520912 ==
8506 13:58:59.521294
8507 13:58:59.521640
8508 13:58:59.523272 TX Vref Scan disable
8509 13:58:59.523774 == TX Byte 0 ==
8510 13:58:59.530072 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8511 13:58:59.533122 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8512 13:58:59.533539 == TX Byte 1 ==
8513 13:58:59.539787 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8514 13:58:59.543262 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8515 13:58:59.543837 ==
8516 13:58:59.547051 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 13:58:59.550031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 13:58:59.550546 ==
8519 13:58:59.564135
8520 13:58:59.567345 TX Vref early break, caculate TX vref
8521 13:58:59.570530 TX Vref=16, minBit 0, minWin=23, winSum=381
8522 13:58:59.573578 TX Vref=18, minBit 0, minWin=22, winSum=387
8523 13:58:59.576597 TX Vref=20, minBit 0, minWin=23, winSum=396
8524 13:58:59.580542 TX Vref=22, minBit 0, minWin=24, winSum=406
8525 13:58:59.583519 TX Vref=24, minBit 5, minWin=24, winSum=415
8526 13:58:59.590198 TX Vref=26, minBit 5, minWin=25, winSum=420
8527 13:58:59.593547 TX Vref=28, minBit 0, minWin=25, winSum=420
8528 13:58:59.596429 TX Vref=30, minBit 1, minWin=24, winSum=412
8529 13:58:59.599822 TX Vref=32, minBit 0, minWin=23, winSum=400
8530 13:58:59.603396 TX Vref=34, minBit 0, minWin=22, winSum=395
8531 13:58:59.609554 [TxChooseVref] Worse bit 5, Min win 25, Win sum 420, Final Vref 26
8532 13:58:59.610016
8533 13:58:59.613024 Final TX Range 0 Vref 26
8534 13:58:59.613596
8535 13:58:59.613963 ==
8536 13:58:59.616369 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 13:58:59.620037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 13:58:59.620581 ==
8539 13:58:59.620927
8540 13:58:59.621239
8541 13:58:59.623301 TX Vref Scan disable
8542 13:58:59.629698 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8543 13:58:59.630212 == TX Byte 0 ==
8544 13:58:59.632732 u2DelayCellOfst[0]=14 cells (4 PI)
8545 13:58:59.636274 u2DelayCellOfst[1]=11 cells (3 PI)
8546 13:58:59.639140 u2DelayCellOfst[2]=0 cells (0 PI)
8547 13:58:59.642885 u2DelayCellOfst[3]=3 cells (1 PI)
8548 13:58:59.647344 u2DelayCellOfst[4]=7 cells (2 PI)
8549 13:58:59.649004 u2DelayCellOfst[5]=18 cells (5 PI)
8550 13:58:59.652361 u2DelayCellOfst[6]=22 cells (6 PI)
8551 13:58:59.656342 u2DelayCellOfst[7]=3 cells (1 PI)
8552 13:58:59.659668 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8553 13:58:59.662511 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8554 13:58:59.665673 == TX Byte 1 ==
8555 13:58:59.668431 u2DelayCellOfst[8]=0 cells (0 PI)
8556 13:58:59.672168 u2DelayCellOfst[9]=3 cells (1 PI)
8557 13:58:59.675558 u2DelayCellOfst[10]=11 cells (3 PI)
8558 13:58:59.678619 u2DelayCellOfst[11]=3 cells (1 PI)
8559 13:58:59.682045 u2DelayCellOfst[12]=14 cells (4 PI)
8560 13:58:59.682464 u2DelayCellOfst[13]=18 cells (5 PI)
8561 13:58:59.685207 u2DelayCellOfst[14]=18 cells (5 PI)
8562 13:58:59.688381 u2DelayCellOfst[15]=18 cells (5 PI)
8563 13:58:59.696463 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8564 13:58:59.698401 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8565 13:58:59.698913 DramC Write-DBI on
8566 13:58:59.701853 ==
8567 13:58:59.705221 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 13:58:59.708481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 13:58:59.708900 ==
8570 13:58:59.709288
8571 13:58:59.709600
8572 13:58:59.711501 TX Vref Scan disable
8573 13:58:59.712064 == TX Byte 0 ==
8574 13:58:59.718493 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8575 13:58:59.719012 == TX Byte 1 ==
8576 13:58:59.722232 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8577 13:58:59.725755 DramC Write-DBI off
8578 13:58:59.726309
8579 13:58:59.726649 [DATLAT]
8580 13:58:59.728334 Freq=1600, CH1 RK0
8581 13:58:59.728752
8582 13:58:59.729083 DATLAT Default: 0xf
8583 13:58:59.731609 0, 0xFFFF, sum = 0
8584 13:58:59.732201 1, 0xFFFF, sum = 0
8585 13:58:59.735147 2, 0xFFFF, sum = 0
8586 13:58:59.735672 3, 0xFFFF, sum = 0
8587 13:58:59.738053 4, 0xFFFF, sum = 0
8588 13:58:59.738578 5, 0xFFFF, sum = 0
8589 13:58:59.741529 6, 0xFFFF, sum = 0
8590 13:58:59.744859 7, 0xFFFF, sum = 0
8591 13:58:59.745430 8, 0xFFFF, sum = 0
8592 13:58:59.747902 9, 0xFFFF, sum = 0
8593 13:58:59.748478 10, 0xFFFF, sum = 0
8594 13:58:59.751866 11, 0xFFFF, sum = 0
8595 13:58:59.752446 12, 0xFFFF, sum = 0
8596 13:58:59.754564 13, 0xFFFF, sum = 0
8597 13:58:59.755035 14, 0x0, sum = 1
8598 13:58:59.757970 15, 0x0, sum = 2
8599 13:58:59.758519 16, 0x0, sum = 3
8600 13:58:59.762108 17, 0x0, sum = 4
8601 13:58:59.762633 best_step = 15
8602 13:58:59.762969
8603 13:58:59.763276 ==
8604 13:58:59.764310 Dram Type= 6, Freq= 0, CH_1, rank 0
8605 13:58:59.767676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8606 13:58:59.771628 ==
8607 13:58:59.772197 RX Vref Scan: 1
8608 13:58:59.772537
8609 13:58:59.774612 Set Vref Range= 24 -> 127
8610 13:58:59.775135
8611 13:58:59.778079 RX Vref 24 -> 127, step: 1
8612 13:58:59.778600
8613 13:58:59.778936 RX Delay 11 -> 252, step: 4
8614 13:58:59.779250
8615 13:58:59.781036 Set Vref, RX VrefLevel [Byte0]: 24
8616 13:58:59.784611 [Byte1]: 24
8617 13:58:59.788302
8618 13:58:59.788817 Set Vref, RX VrefLevel [Byte0]: 25
8619 13:58:59.791577 [Byte1]: 25
8620 13:58:59.796197
8621 13:58:59.796717 Set Vref, RX VrefLevel [Byte0]: 26
8622 13:58:59.799063 [Byte1]: 26
8623 13:58:59.803645
8624 13:58:59.804249 Set Vref, RX VrefLevel [Byte0]: 27
8625 13:58:59.806847 [Byte1]: 27
8626 13:58:59.810651
8627 13:58:59.811074 Set Vref, RX VrefLevel [Byte0]: 28
8628 13:58:59.814668 [Byte1]: 28
8629 13:58:59.818637
8630 13:58:59.819155 Set Vref, RX VrefLevel [Byte0]: 29
8631 13:58:59.822478 [Byte1]: 29
8632 13:58:59.826698
8633 13:58:59.827249 Set Vref, RX VrefLevel [Byte0]: 30
8634 13:58:59.830079 [Byte1]: 30
8635 13:58:59.834686
8636 13:58:59.835209 Set Vref, RX VrefLevel [Byte0]: 31
8637 13:58:59.837019 [Byte1]: 31
8638 13:58:59.841418
8639 13:58:59.841939 Set Vref, RX VrefLevel [Byte0]: 32
8640 13:58:59.844773 [Byte1]: 32
8641 13:58:59.849537
8642 13:58:59.850055 Set Vref, RX VrefLevel [Byte0]: 33
8643 13:58:59.852287 [Byte1]: 33
8644 13:58:59.856939
8645 13:58:59.857453 Set Vref, RX VrefLevel [Byte0]: 34
8646 13:58:59.860090 [Byte1]: 34
8647 13:58:59.864439
8648 13:58:59.864957 Set Vref, RX VrefLevel [Byte0]: 35
8649 13:58:59.868116 [Byte1]: 35
8650 13:58:59.872077
8651 13:58:59.872616 Set Vref, RX VrefLevel [Byte0]: 36
8652 13:58:59.875103 [Byte1]: 36
8653 13:58:59.879754
8654 13:58:59.880277 Set Vref, RX VrefLevel [Byte0]: 37
8655 13:58:59.883361 [Byte1]: 37
8656 13:58:59.886893
8657 13:58:59.887316 Set Vref, RX VrefLevel [Byte0]: 38
8658 13:58:59.890221 [Byte1]: 38
8659 13:58:59.894509
8660 13:58:59.895027 Set Vref, RX VrefLevel [Byte0]: 39
8661 13:58:59.897905 [Byte1]: 39
8662 13:58:59.902839
8663 13:58:59.903358 Set Vref, RX VrefLevel [Byte0]: 40
8664 13:58:59.905662 [Byte1]: 40
8665 13:58:59.910243
8666 13:58:59.910679 Set Vref, RX VrefLevel [Byte0]: 41
8667 13:58:59.913012 [Byte1]: 41
8668 13:58:59.917917
8669 13:58:59.918439 Set Vref, RX VrefLevel [Byte0]: 42
8670 13:58:59.920720 [Byte1]: 42
8671 13:58:59.925255
8672 13:58:59.925821 Set Vref, RX VrefLevel [Byte0]: 43
8673 13:58:59.928229 [Byte1]: 43
8674 13:58:59.933022
8675 13:58:59.933544 Set Vref, RX VrefLevel [Byte0]: 44
8676 13:58:59.935753 [Byte1]: 44
8677 13:58:59.940222
8678 13:58:59.940746 Set Vref, RX VrefLevel [Byte0]: 45
8679 13:58:59.944133 [Byte1]: 45
8680 13:58:59.948193
8681 13:58:59.948719 Set Vref, RX VrefLevel [Byte0]: 46
8682 13:58:59.951497 [Byte1]: 46
8683 13:58:59.956085
8684 13:58:59.956651 Set Vref, RX VrefLevel [Byte0]: 47
8685 13:58:59.958999 [Byte1]: 47
8686 13:58:59.964244
8687 13:58:59.964834 Set Vref, RX VrefLevel [Byte0]: 48
8688 13:58:59.969384 [Byte1]: 48
8689 13:58:59.969807
8690 13:58:59.973181 Set Vref, RX VrefLevel [Byte0]: 49
8691 13:58:59.976250 [Byte1]: 49
8692 13:58:59.976894
8693 13:58:59.980187 Set Vref, RX VrefLevel [Byte0]: 50
8694 13:58:59.982865 [Byte1]: 50
8695 13:58:59.985971
8696 13:58:59.986498 Set Vref, RX VrefLevel [Byte0]: 51
8697 13:58:59.989591 [Byte1]: 51
8698 13:58:59.994296
8699 13:58:59.994915 Set Vref, RX VrefLevel [Byte0]: 52
8700 13:58:59.996898 [Byte1]: 52
8701 13:59:00.001656
8702 13:59:00.002177 Set Vref, RX VrefLevel [Byte0]: 53
8703 13:59:00.004635 [Byte1]: 53
8704 13:59:00.008643
8705 13:59:00.009069 Set Vref, RX VrefLevel [Byte0]: 54
8706 13:59:00.011869 [Byte1]: 54
8707 13:59:00.017056
8708 13:59:00.017582 Set Vref, RX VrefLevel [Byte0]: 55
8709 13:59:00.020245 [Byte1]: 55
8710 13:59:00.024496
8711 13:59:00.024915 Set Vref, RX VrefLevel [Byte0]: 56
8712 13:59:00.027701 [Byte1]: 56
8713 13:59:00.032038
8714 13:59:00.032560 Set Vref, RX VrefLevel [Byte0]: 57
8715 13:59:00.035039 [Byte1]: 57
8716 13:59:00.039583
8717 13:59:00.040168 Set Vref, RX VrefLevel [Byte0]: 58
8718 13:59:00.042560 [Byte1]: 58
8719 13:59:00.046915
8720 13:59:00.047436 Set Vref, RX VrefLevel [Byte0]: 59
8721 13:59:00.050195 [Byte1]: 59
8722 13:59:00.054562
8723 13:59:00.055100 Set Vref, RX VrefLevel [Byte0]: 60
8724 13:59:00.057940 [Byte1]: 60
8725 13:59:00.062113
8726 13:59:00.062629 Set Vref, RX VrefLevel [Byte0]: 61
8727 13:59:00.069384 [Byte1]: 61
8728 13:59:00.069908
8729 13:59:00.071999 Set Vref, RX VrefLevel [Byte0]: 62
8730 13:59:00.075589 [Byte1]: 62
8731 13:59:00.076169
8732 13:59:00.078672 Set Vref, RX VrefLevel [Byte0]: 63
8733 13:59:00.081862 [Byte1]: 63
8734 13:59:00.085681
8735 13:59:00.086303 Set Vref, RX VrefLevel [Byte0]: 64
8736 13:59:00.088066 [Byte1]: 64
8737 13:59:00.092631
8738 13:59:00.093155 Set Vref, RX VrefLevel [Byte0]: 65
8739 13:59:00.095979 [Byte1]: 65
8740 13:59:00.100300
8741 13:59:00.100764 Set Vref, RX VrefLevel [Byte0]: 66
8742 13:59:00.103962 [Byte1]: 66
8743 13:59:00.107786
8744 13:59:00.108303 Set Vref, RX VrefLevel [Byte0]: 67
8745 13:59:00.111349 [Byte1]: 67
8746 13:59:00.115287
8747 13:59:00.115707 Set Vref, RX VrefLevel [Byte0]: 68
8748 13:59:00.118637 [Byte1]: 68
8749 13:59:00.123370
8750 13:59:00.123946 Set Vref, RX VrefLevel [Byte0]: 69
8751 13:59:00.126294 [Byte1]: 69
8752 13:59:00.130860
8753 13:59:00.131382 Set Vref, RX VrefLevel [Byte0]: 70
8754 13:59:00.133881 [Byte1]: 70
8755 13:59:00.137963
8756 13:59:00.138407 Set Vref, RX VrefLevel [Byte0]: 71
8757 13:59:00.141784 [Byte1]: 71
8758 13:59:00.146268
8759 13:59:00.146789 Set Vref, RX VrefLevel [Byte0]: 72
8760 13:59:00.148918 [Byte1]: 72
8761 13:59:00.153797
8762 13:59:00.154320 Set Vref, RX VrefLevel [Byte0]: 73
8763 13:59:00.156447 [Byte1]: 73
8764 13:59:00.161449
8765 13:59:00.161988 Final RX Vref Byte 0 = 53 to rank0
8766 13:59:00.164287 Final RX Vref Byte 1 = 61 to rank0
8767 13:59:00.168294 Final RX Vref Byte 0 = 53 to rank1
8768 13:59:00.170988 Final RX Vref Byte 1 = 61 to rank1==
8769 13:59:00.174967 Dram Type= 6, Freq= 0, CH_1, rank 0
8770 13:59:00.181648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 13:59:00.182179 ==
8772 13:59:00.182521 DQS Delay:
8773 13:59:00.182834 DQS0 = 0, DQS1 = 0
8774 13:59:00.184136 DQM Delay:
8775 13:59:00.184562 DQM0 = 133, DQM1 = 127
8776 13:59:00.187630 DQ Delay:
8777 13:59:00.190946 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8778 13:59:00.194303 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8779 13:59:00.197288 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8780 13:59:00.200656 DQ12 =136, DQ13 =134, DQ14 =136, DQ15 =138
8781 13:59:00.201080
8782 13:59:00.201415
8783 13:59:00.201728
8784 13:59:00.203941 [DramC_TX_OE_Calibration] TA2
8785 13:59:00.207268 Original DQ_B0 (3 6) =30, OEN = 27
8786 13:59:00.210618 Original DQ_B1 (3 6) =30, OEN = 27
8787 13:59:00.213763 24, 0x0, End_B0=24 End_B1=24
8788 13:59:00.214198 25, 0x0, End_B0=25 End_B1=25
8789 13:59:00.217174 26, 0x0, End_B0=26 End_B1=26
8790 13:59:00.220992 27, 0x0, End_B0=27 End_B1=27
8791 13:59:00.224612 28, 0x0, End_B0=28 End_B1=28
8792 13:59:00.227163 29, 0x0, End_B0=29 End_B1=29
8793 13:59:00.227780 30, 0x0, End_B0=30 End_B1=30
8794 13:59:00.230459 31, 0x4141, End_B0=30 End_B1=30
8795 13:59:00.234005 Byte0 end_step=30 best_step=27
8796 13:59:00.236876 Byte1 end_step=30 best_step=27
8797 13:59:00.240082 Byte0 TX OE(2T, 0.5T) = (3, 3)
8798 13:59:00.243625 Byte1 TX OE(2T, 0.5T) = (3, 3)
8799 13:59:00.244201
8800 13:59:00.244541
8801 13:59:00.250392 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8802 13:59:00.253564 CH1 RK0: MR19=303, MR18=1B11
8803 13:59:00.260279 CH1_RK0: MR19=0x303, MR18=0x1B11, DQSOSC=396, MR23=63, INC=23, DEC=15
8804 13:59:00.260797
8805 13:59:00.263414 ----->DramcWriteLeveling(PI) begin...
8806 13:59:00.263987 ==
8807 13:59:00.266565 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 13:59:00.269923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 13:59:00.270353 ==
8810 13:59:00.273143 Write leveling (Byte 0): 24 => 24
8811 13:59:00.277377 Write leveling (Byte 1): 26 => 26
8812 13:59:00.279813 DramcWriteLeveling(PI) end<-----
8813 13:59:00.280339
8814 13:59:00.280678 ==
8815 13:59:00.283419 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 13:59:00.289310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 13:59:00.289741 ==
8818 13:59:00.290080 [Gating] SW mode calibration
8819 13:59:00.299602 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8820 13:59:00.302990 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8821 13:59:00.306022 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 13:59:00.312816 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 13:59:00.315653 1 4 8 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
8824 13:59:00.322857 1 4 12 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
8825 13:59:00.325666 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 13:59:00.328787 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 13:59:00.335864 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 13:59:00.338835 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 13:59:00.342360 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 13:59:00.348874 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 13:59:00.352093 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8832 13:59:00.354977 1 5 12 | B1->B0 | 2626 3434 | 0 1 | (0 1) (1 0)
8833 13:59:00.362176 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 13:59:00.365469 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 13:59:00.368579 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 13:59:00.375596 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 13:59:00.378663 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 13:59:00.382141 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 13:59:00.388284 1 6 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8840 13:59:00.391449 1 6 12 | B1->B0 | 4444 2323 | 1 0 | (0 0) (0 0)
8841 13:59:00.395013 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 13:59:00.401740 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 13:59:00.405105 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 13:59:00.408251 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 13:59:00.414653 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 13:59:00.417801 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 13:59:00.420900 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8848 13:59:00.428042 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8849 13:59:00.431476 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8850 13:59:00.434527 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 13:59:00.441383 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 13:59:00.444682 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 13:59:00.448079 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 13:59:00.450767 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 13:59:00.457462 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 13:59:00.460496 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 13:59:00.464396 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 13:59:00.470779 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 13:59:00.474228 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 13:59:00.477445 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 13:59:00.484428 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 13:59:00.487201 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 13:59:00.491804 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8864 13:59:00.497128 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8865 13:59:00.500434 Total UI for P1: 0, mck2ui 16
8866 13:59:00.504012 best dqsien dly found for B1: ( 1, 9, 8)
8867 13:59:00.507287 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8868 13:59:00.510614 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 13:59:00.513821 Total UI for P1: 0, mck2ui 16
8870 13:59:00.516952 best dqsien dly found for B0: ( 1, 9, 14)
8871 13:59:00.523449 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8872 13:59:00.526851 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8873 13:59:00.527376
8874 13:59:00.530195 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8875 13:59:00.533405 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8876 13:59:00.537119 [Gating] SW calibration Done
8877 13:59:00.537647 ==
8878 13:59:00.539651 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 13:59:00.543601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 13:59:00.544185 ==
8881 13:59:00.546656 RX Vref Scan: 0
8882 13:59:00.547176
8883 13:59:00.547515 RX Vref 0 -> 0, step: 1
8884 13:59:00.547892
8885 13:59:00.549686 RX Delay 0 -> 252, step: 8
8886 13:59:00.552990 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8887 13:59:00.559703 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8888 13:59:00.563385 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8889 13:59:00.566208 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8890 13:59:00.569816 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8891 13:59:00.572901 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8892 13:59:00.579273 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8893 13:59:00.582673 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8894 13:59:00.585992 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8895 13:59:00.588940 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8896 13:59:00.592881 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8897 13:59:00.600431 iDelay=208, Bit 11, Center 119 (56 ~ 183) 128
8898 13:59:00.602190 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8899 13:59:00.605756 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8900 13:59:00.609238 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8901 13:59:00.615344 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8902 13:59:00.615945 ==
8903 13:59:00.618553 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 13:59:00.622229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 13:59:00.622759 ==
8906 13:59:00.623098 DQS Delay:
8907 13:59:00.625529 DQS0 = 0, DQS1 = 0
8908 13:59:00.625954 DQM Delay:
8909 13:59:00.628666 DQM0 = 136, DQM1 = 129
8910 13:59:00.629227 DQ Delay:
8911 13:59:00.632297 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8912 13:59:00.635888 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8913 13:59:00.639639 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8914 13:59:00.642473 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8915 13:59:00.643083
8916 13:59:00.643431
8917 13:59:00.645396 ==
8918 13:59:00.648660 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 13:59:00.651883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 13:59:00.652404 ==
8921 13:59:00.652747
8922 13:59:00.653065
8923 13:59:00.655155 TX Vref Scan disable
8924 13:59:00.655683 == TX Byte 0 ==
8925 13:59:00.661899 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8926 13:59:00.665232 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8927 13:59:00.665765 == TX Byte 1 ==
8928 13:59:00.671550 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8929 13:59:00.674914 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8930 13:59:00.675444 ==
8931 13:59:00.678173 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 13:59:00.681688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 13:59:00.682219 ==
8934 13:59:00.695096
8935 13:59:00.698159 TX Vref early break, caculate TX vref
8936 13:59:00.701877 TX Vref=16, minBit 0, minWin=23, winSum=387
8937 13:59:00.704602 TX Vref=18, minBit 1, minWin=23, winSum=395
8938 13:59:00.708087 TX Vref=20, minBit 1, minWin=23, winSum=405
8939 13:59:00.711392 TX Vref=22, minBit 6, minWin=24, winSum=407
8940 13:59:00.714669 TX Vref=24, minBit 1, minWin=25, winSum=419
8941 13:59:00.721402 TX Vref=26, minBit 5, minWin=25, winSum=426
8942 13:59:00.724668 TX Vref=28, minBit 0, minWin=25, winSum=426
8943 13:59:00.727759 TX Vref=30, minBit 0, minWin=25, winSum=421
8944 13:59:00.731516 TX Vref=32, minBit 0, minWin=24, winSum=411
8945 13:59:00.734833 TX Vref=34, minBit 0, minWin=23, winSum=399
8946 13:59:00.741172 [TxChooseVref] Worse bit 5, Min win 25, Win sum 426, Final Vref 26
8947 13:59:00.741692
8948 13:59:00.744258 Final TX Range 0 Vref 26
8949 13:59:00.744712
8950 13:59:00.745044 ==
8951 13:59:00.748353 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 13:59:00.750936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 13:59:00.751356 ==
8954 13:59:00.751688
8955 13:59:00.752049
8956 13:59:00.754324 TX Vref Scan disable
8957 13:59:00.760913 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8958 13:59:00.761495 == TX Byte 0 ==
8959 13:59:00.763997 u2DelayCellOfst[0]=18 cells (5 PI)
8960 13:59:00.767948 u2DelayCellOfst[1]=11 cells (3 PI)
8961 13:59:00.770680 u2DelayCellOfst[2]=0 cells (0 PI)
8962 13:59:00.774512 u2DelayCellOfst[3]=7 cells (2 PI)
8963 13:59:00.778031 u2DelayCellOfst[4]=7 cells (2 PI)
8964 13:59:00.780678 u2DelayCellOfst[5]=18 cells (5 PI)
8965 13:59:00.784112 u2DelayCellOfst[6]=18 cells (5 PI)
8966 13:59:00.787439 u2DelayCellOfst[7]=3 cells (1 PI)
8967 13:59:00.791328 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8968 13:59:00.793800 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8969 13:59:00.797558 == TX Byte 1 ==
8970 13:59:00.800709 u2DelayCellOfst[8]=0 cells (0 PI)
8971 13:59:00.801237 u2DelayCellOfst[9]=7 cells (2 PI)
8972 13:59:00.804014 u2DelayCellOfst[10]=11 cells (3 PI)
8973 13:59:00.807230 u2DelayCellOfst[11]=3 cells (1 PI)
8974 13:59:00.810401 u2DelayCellOfst[12]=14 cells (4 PI)
8975 13:59:00.814121 u2DelayCellOfst[13]=18 cells (5 PI)
8976 13:59:00.817505 u2DelayCellOfst[14]=18 cells (5 PI)
8977 13:59:00.820136 u2DelayCellOfst[15]=18 cells (5 PI)
8978 13:59:00.823445 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8979 13:59:00.830400 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8980 13:59:00.830966 DramC Write-DBI on
8981 13:59:00.831385 ==
8982 13:59:00.833812 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 13:59:00.840245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 13:59:00.840804 ==
8985 13:59:00.841313
8986 13:59:00.841815
8987 13:59:00.842170 TX Vref Scan disable
8988 13:59:00.844066 == TX Byte 0 ==
8989 13:59:00.847700 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8990 13:59:00.850567 == TX Byte 1 ==
8991 13:59:00.854714 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8992 13:59:00.857391 DramC Write-DBI off
8993 13:59:00.857824
8994 13:59:00.858163 [DATLAT]
8995 13:59:00.858477 Freq=1600, CH1 RK1
8996 13:59:00.858781
8997 13:59:00.860620 DATLAT Default: 0xf
8998 13:59:00.861045 0, 0xFFFF, sum = 0
8999 13:59:00.865014 1, 0xFFFF, sum = 0
9000 13:59:00.867565 2, 0xFFFF, sum = 0
9001 13:59:00.868166 3, 0xFFFF, sum = 0
9002 13:59:00.871126 4, 0xFFFF, sum = 0
9003 13:59:00.871775 5, 0xFFFF, sum = 0
9004 13:59:00.874137 6, 0xFFFF, sum = 0
9005 13:59:00.874668 7, 0xFFFF, sum = 0
9006 13:59:00.877632 8, 0xFFFF, sum = 0
9007 13:59:00.878164 9, 0xFFFF, sum = 0
9008 13:59:00.880645 10, 0xFFFF, sum = 0
9009 13:59:00.881173 11, 0xFFFF, sum = 0
9010 13:59:00.884425 12, 0xFFFF, sum = 0
9011 13:59:00.884960 13, 0xFFFF, sum = 0
9012 13:59:00.887303 14, 0x0, sum = 1
9013 13:59:00.887877 15, 0x0, sum = 2
9014 13:59:00.890243 16, 0x0, sum = 3
9015 13:59:00.890672 17, 0x0, sum = 4
9016 13:59:00.893614 best_step = 15
9017 13:59:00.894139
9018 13:59:00.894481 ==
9019 13:59:00.896583 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 13:59:00.899900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 13:59:00.900426 ==
9022 13:59:00.903500 RX Vref Scan: 0
9023 13:59:00.904079
9024 13:59:00.904427 RX Vref 0 -> 0, step: 1
9025 13:59:00.904745
9026 13:59:00.906593 RX Delay 11 -> 252, step: 4
9027 13:59:00.913444 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9028 13:59:00.916383 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9029 13:59:00.919641 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9030 13:59:00.923218 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9031 13:59:00.926754 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9032 13:59:00.933155 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9033 13:59:00.936238 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9034 13:59:00.939926 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9035 13:59:00.943884 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9036 13:59:00.947318 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9037 13:59:00.953128 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9038 13:59:00.956254 iDelay=203, Bit 11, Center 118 (63 ~ 174) 112
9039 13:59:00.960324 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9040 13:59:00.963654 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9041 13:59:00.969608 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9042 13:59:00.972460 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9043 13:59:00.972931 ==
9044 13:59:00.976126 Dram Type= 6, Freq= 0, CH_1, rank 1
9045 13:59:00.979427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9046 13:59:00.980061 ==
9047 13:59:00.982653 DQS Delay:
9048 13:59:00.983216 DQS0 = 0, DQS1 = 0
9049 13:59:00.983592 DQM Delay:
9050 13:59:00.986602 DQM0 = 134, DQM1 = 127
9051 13:59:00.987168 DQ Delay:
9052 13:59:00.990047 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9053 13:59:00.992511 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9054 13:59:00.996102 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =118
9055 13:59:01.003294 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9056 13:59:01.003893
9057 13:59:01.004269
9058 13:59:01.004618
9059 13:59:01.005994 [DramC_TX_OE_Calibration] TA2
9060 13:59:01.006461 Original DQ_B0 (3 6) =30, OEN = 27
9061 13:59:01.009904 Original DQ_B1 (3 6) =30, OEN = 27
9062 13:59:01.012330 24, 0x0, End_B0=24 End_B1=24
9063 13:59:01.015547 25, 0x0, End_B0=25 End_B1=25
9064 13:59:01.018865 26, 0x0, End_B0=26 End_B1=26
9065 13:59:01.022800 27, 0x0, End_B0=27 End_B1=27
9066 13:59:01.023331 28, 0x0, End_B0=28 End_B1=28
9067 13:59:01.025731 29, 0x0, End_B0=29 End_B1=29
9068 13:59:01.029066 30, 0x0, End_B0=30 End_B1=30
9069 13:59:01.032178 31, 0x4141, End_B0=30 End_B1=30
9070 13:59:01.035202 Byte0 end_step=30 best_step=27
9071 13:59:01.035632 Byte1 end_step=30 best_step=27
9072 13:59:01.039311 Byte0 TX OE(2T, 0.5T) = (3, 3)
9073 13:59:01.042300 Byte1 TX OE(2T, 0.5T) = (3, 3)
9074 13:59:01.042856
9075 13:59:01.043372
9076 13:59:01.052186 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9077 13:59:01.052731 CH1 RK1: MR19=303, MR18=E0B
9078 13:59:01.058638 CH1_RK1: MR19=0x303, MR18=0xE0B, DQSOSC=402, MR23=63, INC=22, DEC=15
9079 13:59:01.062042 [RxdqsGatingPostProcess] freq 1600
9080 13:59:01.068351 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9081 13:59:01.071820 best DQS0 dly(2T, 0.5T) = (1, 1)
9082 13:59:01.075652 best DQS1 dly(2T, 0.5T) = (1, 1)
9083 13:59:01.078604 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9084 13:59:01.082558 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9085 13:59:01.085106 best DQS0 dly(2T, 0.5T) = (1, 1)
9086 13:59:01.085531 best DQS1 dly(2T, 0.5T) = (1, 1)
9087 13:59:01.088142 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9088 13:59:01.091793 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9089 13:59:01.095086 Pre-setting of DQS Precalculation
9090 13:59:01.101324 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9091 13:59:01.108494 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9092 13:59:01.114979 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9093 13:59:01.115534
9094 13:59:01.115944
9095 13:59:01.117736 [Calibration Summary] 3200 Mbps
9096 13:59:01.121716 CH 0, Rank 0
9097 13:59:01.122241 SW Impedance : PASS
9098 13:59:01.124873 DUTY Scan : NO K
9099 13:59:01.125297 ZQ Calibration : PASS
9100 13:59:01.127517 Jitter Meter : NO K
9101 13:59:01.131902 CBT Training : PASS
9102 13:59:01.132427 Write leveling : PASS
9103 13:59:01.134449 RX DQS gating : PASS
9104 13:59:01.138407 RX DQ/DQS(RDDQC) : PASS
9105 13:59:01.138935 TX DQ/DQS : PASS
9106 13:59:01.141228 RX DATLAT : PASS
9107 13:59:01.144567 RX DQ/DQS(Engine): PASS
9108 13:59:01.144995 TX OE : PASS
9109 13:59:01.147852 All Pass.
9110 13:59:01.148381
9111 13:59:01.148720 CH 0, Rank 1
9112 13:59:01.150832 SW Impedance : PASS
9113 13:59:01.151255 DUTY Scan : NO K
9114 13:59:01.154184 ZQ Calibration : PASS
9115 13:59:01.157585 Jitter Meter : NO K
9116 13:59:01.158008 CBT Training : PASS
9117 13:59:01.161743 Write leveling : PASS
9118 13:59:01.164422 RX DQS gating : PASS
9119 13:59:01.164951 RX DQ/DQS(RDDQC) : PASS
9120 13:59:01.167351 TX DQ/DQS : PASS
9121 13:59:01.170742 RX DATLAT : PASS
9122 13:59:01.171281 RX DQ/DQS(Engine): PASS
9123 13:59:01.174461 TX OE : PASS
9124 13:59:01.174993 All Pass.
9125 13:59:01.175335
9126 13:59:01.177353 CH 1, Rank 0
9127 13:59:01.177879 SW Impedance : PASS
9128 13:59:01.181541 DUTY Scan : NO K
9129 13:59:01.184621 ZQ Calibration : PASS
9130 13:59:01.185051 Jitter Meter : NO K
9131 13:59:01.187409 CBT Training : PASS
9132 13:59:01.188036 Write leveling : PASS
9133 13:59:01.190378 RX DQS gating : PASS
9134 13:59:01.194134 RX DQ/DQS(RDDQC) : PASS
9135 13:59:01.194663 TX DQ/DQS : PASS
9136 13:59:01.197302 RX DATLAT : PASS
9137 13:59:01.200612 RX DQ/DQS(Engine): PASS
9138 13:59:01.201027 TX OE : PASS
9139 13:59:01.203847 All Pass.
9140 13:59:01.204264
9141 13:59:01.204595 CH 1, Rank 1
9142 13:59:01.206979 SW Impedance : PASS
9143 13:59:01.207392 DUTY Scan : NO K
9144 13:59:01.211060 ZQ Calibration : PASS
9145 13:59:01.213658 Jitter Meter : NO K
9146 13:59:01.214180 CBT Training : PASS
9147 13:59:01.216861 Write leveling : PASS
9148 13:59:01.220559 RX DQS gating : PASS
9149 13:59:01.220985 RX DQ/DQS(RDDQC) : PASS
9150 13:59:01.223757 TX DQ/DQS : PASS
9151 13:59:01.227057 RX DATLAT : PASS
9152 13:59:01.227582 RX DQ/DQS(Engine): PASS
9153 13:59:01.229943 TX OE : PASS
9154 13:59:01.230371 All Pass.
9155 13:59:01.230708
9156 13:59:01.234362 DramC Write-DBI on
9157 13:59:01.236575 PER_BANK_REFRESH: Hybrid Mode
9158 13:59:01.237000 TX_TRACKING: ON
9159 13:59:01.246729 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9160 13:59:01.253706 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9161 13:59:01.260180 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9162 13:59:01.263055 [FAST_K] Save calibration result to emmc
9163 13:59:01.266867 sync common calibartion params.
9164 13:59:01.270246 sync cbt_mode0:1, 1:1
9165 13:59:01.272879 dram_init: ddr_geometry: 2
9166 13:59:01.273306 dram_init: ddr_geometry: 2
9167 13:59:01.277024 dram_init: ddr_geometry: 2
9168 13:59:01.280150 0:dram_rank_size:100000000
9169 13:59:01.283470 1:dram_rank_size:100000000
9170 13:59:01.286471 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9171 13:59:01.289785 DFS_SHUFFLE_HW_MODE: ON
9172 13:59:01.293602 dramc_set_vcore_voltage set vcore to 725000
9173 13:59:01.296474 Read voltage for 1600, 0
9174 13:59:01.296999 Vio18 = 0
9175 13:59:01.297339 Vcore = 725000
9176 13:59:01.299651 Vdram = 0
9177 13:59:01.300172 Vddq = 0
9178 13:59:01.300689 Vmddr = 0
9179 13:59:01.303346 switch to 3200 Mbps bootup
9180 13:59:01.306188 [DramcRunTimeConfig]
9181 13:59:01.306608 PHYPLL
9182 13:59:01.306945 DPM_CONTROL_AFTERK: ON
9183 13:59:01.309475 PER_BANK_REFRESH: ON
9184 13:59:01.312664 REFRESH_OVERHEAD_REDUCTION: ON
9185 13:59:01.313088 CMD_PICG_NEW_MODE: OFF
9186 13:59:01.316157 XRTWTW_NEW_MODE: ON
9187 13:59:01.319324 XRTRTR_NEW_MODE: ON
9188 13:59:01.319991 TX_TRACKING: ON
9189 13:59:01.322960 RDSEL_TRACKING: OFF
9190 13:59:01.323480 DQS Precalculation for DVFS: ON
9191 13:59:01.326114 RX_TRACKING: OFF
9192 13:59:01.326632 HW_GATING DBG: ON
9193 13:59:01.329976 ZQCS_ENABLE_LP4: ON
9194 13:59:01.330498 RX_PICG_NEW_MODE: ON
9195 13:59:01.332831 TX_PICG_NEW_MODE: ON
9196 13:59:01.336283 ENABLE_RX_DCM_DPHY: ON
9197 13:59:01.339430 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9198 13:59:01.339997 DUMMY_READ_FOR_TRACKING: OFF
9199 13:59:01.342451 !!! SPM_CONTROL_AFTERK: OFF
9200 13:59:01.345852 !!! SPM could not control APHY
9201 13:59:01.349749 IMPEDANCE_TRACKING: ON
9202 13:59:01.350273 TEMP_SENSOR: ON
9203 13:59:01.352295 HW_SAVE_FOR_SR: OFF
9204 13:59:01.352722 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9205 13:59:01.359041 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9206 13:59:01.359555 Read ODT Tracking: ON
9207 13:59:01.362916 Refresh Rate DeBounce: ON
9208 13:59:01.365939 DFS_NO_QUEUE_FLUSH: ON
9209 13:59:01.368984 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9210 13:59:01.369508 ENABLE_DFS_RUNTIME_MRW: OFF
9211 13:59:01.372155 DDR_RESERVE_NEW_MODE: ON
9212 13:59:01.376645 MR_CBT_SWITCH_FREQ: ON
9213 13:59:01.377370 =========================
9214 13:59:01.395689 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9215 13:59:01.398507 dram_init: ddr_geometry: 2
9216 13:59:01.416832 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9217 13:59:01.420257 dram_init: dram init end (result: 0)
9218 13:59:01.426843 DRAM-K: Full calibration passed in 24642 msecs
9219 13:59:01.430028 MRC: failed to locate region type 0.
9220 13:59:01.430499 DRAM rank0 size:0x100000000,
9221 13:59:01.434309 DRAM rank1 size=0x100000000
9222 13:59:01.443360 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9223 13:59:01.450464 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9224 13:59:01.456978 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9225 13:59:01.463229 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9226 13:59:01.467045 DRAM rank0 size:0x100000000,
9227 13:59:01.470716 DRAM rank1 size=0x100000000
9228 13:59:01.471292 CBMEM:
9229 13:59:01.473207 IMD: root @ 0xfffff000 254 entries.
9230 13:59:01.476905 IMD: root @ 0xffffec00 62 entries.
9231 13:59:01.480120 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9232 13:59:01.486569 WARNING: RO_VPD is uninitialized or empty.
9233 13:59:01.490242 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9234 13:59:01.496934 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9235 13:59:01.509572 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9236 13:59:01.521450 BS: romstage times (exec / console): total (unknown) / 24133 ms
9237 13:59:01.521998
9238 13:59:01.522366
9239 13:59:01.531228 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9240 13:59:01.534475 ARM64: Exception handlers installed.
9241 13:59:01.537833 ARM64: Testing exception
9242 13:59:01.541178 ARM64: Done test exception
9243 13:59:01.541736 Enumerating buses...
9244 13:59:01.545435 Show all devs... Before device enumeration.
9245 13:59:01.547536 Root Device: enabled 1
9246 13:59:01.551009 CPU_CLUSTER: 0: enabled 1
9247 13:59:01.551562 CPU: 00: enabled 1
9248 13:59:01.554209 Compare with tree...
9249 13:59:01.554767 Root Device: enabled 1
9250 13:59:01.557730 CPU_CLUSTER: 0: enabled 1
9251 13:59:01.560699 CPU: 00: enabled 1
9252 13:59:01.561257 Root Device scanning...
9253 13:59:01.564976 scan_static_bus for Root Device
9254 13:59:01.567609 CPU_CLUSTER: 0 enabled
9255 13:59:01.571083 scan_static_bus for Root Device done
9256 13:59:01.574188 scan_bus: bus Root Device finished in 8 msecs
9257 13:59:01.574744 done
9258 13:59:01.581322 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9259 13:59:01.583424 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9260 13:59:01.590657 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9261 13:59:01.596752 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9262 13:59:01.597253 Allocating resources...
9263 13:59:01.599913 Reading resources...
9264 13:59:01.603479 Root Device read_resources bus 0 link: 0
9265 13:59:01.606795 DRAM rank0 size:0x100000000,
9266 13:59:01.607349 DRAM rank1 size=0x100000000
9267 13:59:01.613356 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9268 13:59:01.613911 CPU: 00 missing read_resources
9269 13:59:01.620646 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9270 13:59:01.624320 Root Device read_resources bus 0 link: 0 done
9271 13:59:01.626947 Done reading resources.
9272 13:59:01.630028 Show resources in subtree (Root Device)...After reading.
9273 13:59:01.633175 Root Device child on link 0 CPU_CLUSTER: 0
9274 13:59:01.636361 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 13:59:01.646866 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 13:59:01.647445 CPU: 00
9277 13:59:01.653772 Root Device assign_resources, bus 0 link: 0
9278 13:59:01.656133 CPU_CLUSTER: 0 missing set_resources
9279 13:59:01.659532 Root Device assign_resources, bus 0 link: 0 done
9280 13:59:01.662776 Done setting resources.
9281 13:59:01.666108 Show resources in subtree (Root Device)...After assigning values.
9282 13:59:01.669748 Root Device child on link 0 CPU_CLUSTER: 0
9283 13:59:01.675897 CPU_CLUSTER: 0 child on link 0 CPU: 00
9284 13:59:01.682703 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9285 13:59:01.686108 CPU: 00
9286 13:59:01.686663 Done allocating resources.
9287 13:59:01.692186 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9288 13:59:01.692957 Enabling resources...
9289 13:59:01.695650 done.
9290 13:59:01.699150 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9291 13:59:01.702597 Initializing devices...
9292 13:59:01.703068 Root Device init
9293 13:59:01.705333 init hardware done!
9294 13:59:01.705800 0x00000018: ctrlr->caps
9295 13:59:01.708894 52.000 MHz: ctrlr->f_max
9296 13:59:01.712057 0.400 MHz: ctrlr->f_min
9297 13:59:01.715599 0x40ff8080: ctrlr->voltages
9298 13:59:01.716308 sclk: 390625
9299 13:59:01.716692 Bus Width = 1
9300 13:59:01.718698 sclk: 390625
9301 13:59:01.719164 Bus Width = 1
9302 13:59:01.721918 Early init status = 3
9303 13:59:01.725985 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9304 13:59:01.728496 in-header: 03 fc 00 00 01 00 00 00
9305 13:59:01.732410 in-data: 00
9306 13:59:01.734984 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9307 13:59:01.741458 in-header: 03 fd 00 00 00 00 00 00
9308 13:59:01.743837 in-data:
9309 13:59:01.746873 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9310 13:59:01.751417 in-header: 03 fc 00 00 01 00 00 00
9311 13:59:01.754551 in-data: 00
9312 13:59:01.758243 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9313 13:59:01.763139 in-header: 03 fd 00 00 00 00 00 00
9314 13:59:01.766870 in-data:
9315 13:59:01.770287 [SSUSB] Setting up USB HOST controller...
9316 13:59:01.773747 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9317 13:59:01.777376 [SSUSB] phy power-on done.
9318 13:59:01.779992 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9319 13:59:01.786668 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9320 13:59:01.790476 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9321 13:59:01.796407 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9322 13:59:01.802952 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9323 13:59:01.809760 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9324 13:59:01.816523 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9325 13:59:01.822920 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9326 13:59:01.826002 SPM: binary array size = 0x9dc
9327 13:59:01.829395 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9328 13:59:01.836287 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9329 13:59:01.842725 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9330 13:59:01.849273 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9331 13:59:01.852653 configure_display: Starting display init
9332 13:59:01.887060 anx7625_power_on_init: Init interface.
9333 13:59:01.890062 anx7625_disable_pd_protocol: Disabled PD feature.
9334 13:59:01.893180 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9335 13:59:01.921140 anx7625_start_dp_work: Secure OCM version=00
9336 13:59:01.924321 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9337 13:59:01.939634 sp_tx_get_edid_block: EDID Block = 1
9338 13:59:02.042176 Extracted contents:
9339 13:59:02.045878 header: 00 ff ff ff ff ff ff 00
9340 13:59:02.049021 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9341 13:59:02.051388 version: 01 04
9342 13:59:02.055239 basic params: 95 1f 11 78 0a
9343 13:59:02.058254 chroma info: 76 90 94 55 54 90 27 21 50 54
9344 13:59:02.061634 established: 00 00 00
9345 13:59:02.068331 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9346 13:59:02.071593 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9347 13:59:02.078198 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9348 13:59:02.084727 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9349 13:59:02.091003 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9350 13:59:02.094556 extensions: 00
9351 13:59:02.095212 checksum: fb
9352 13:59:02.095597
9353 13:59:02.097509 Manufacturer: IVO Model 57d Serial Number 0
9354 13:59:02.101249 Made week 0 of 2020
9355 13:59:02.104758 EDID version: 1.4
9356 13:59:02.105227 Digital display
9357 13:59:02.107974 6 bits per primary color channel
9358 13:59:02.108482 DisplayPort interface
9359 13:59:02.111250 Maximum image size: 31 cm x 17 cm
9360 13:59:02.114444 Gamma: 220%
9361 13:59:02.115004 Check DPMS levels
9362 13:59:02.120741 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9363 13:59:02.124260 First detailed timing is preferred timing
9364 13:59:02.124726 Established timings supported:
9365 13:59:02.127330 Standard timings supported:
9366 13:59:02.130974 Detailed timings
9367 13:59:02.134300 Hex of detail: 383680a07038204018303c0035ae10000019
9368 13:59:02.141204 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9369 13:59:02.144151 0780 0798 07c8 0820 hborder 0
9370 13:59:02.147240 0438 043b 0447 0458 vborder 0
9371 13:59:02.150800 -hsync -vsync
9372 13:59:02.151357 Did detailed timing
9373 13:59:02.157446 Hex of detail: 000000000000000000000000000000000000
9374 13:59:02.160154 Manufacturer-specified data, tag 0
9375 13:59:02.163915 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9376 13:59:02.167233 ASCII string: InfoVision
9377 13:59:02.170798 Hex of detail: 000000fe00523134304e574635205248200a
9378 13:59:02.173811 ASCII string: R140NWF5 RH
9379 13:59:02.174284 Checksum
9380 13:59:02.176889 Checksum: 0xfb (valid)
9381 13:59:02.180439 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9382 13:59:02.183757 DSI data_rate: 832800000 bps
9383 13:59:02.190375 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9384 13:59:02.193155 anx7625_parse_edid: pixelclock(138800).
9385 13:59:02.196973 hactive(1920), hsync(48), hfp(24), hbp(88)
9386 13:59:02.200382 vactive(1080), vsync(12), vfp(3), vbp(17)
9387 13:59:02.203432 anx7625_dsi_config: config dsi.
9388 13:59:02.210106 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9389 13:59:02.223651 anx7625_dsi_config: success to config DSI
9390 13:59:02.226910 anx7625_dp_start: MIPI phy setup OK.
9391 13:59:02.230385 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9392 13:59:02.233543 mtk_ddp_mode_set invalid vrefresh 60
9393 13:59:02.236882 main_disp_path_setup
9394 13:59:02.237456 ovl_layer_smi_id_en
9395 13:59:02.240314 ovl_layer_smi_id_en
9396 13:59:02.240773 ccorr_config
9397 13:59:02.241135 aal_config
9398 13:59:02.243331 gamma_config
9399 13:59:02.243780 postmask_config
9400 13:59:02.247504 dither_config
9401 13:59:02.250169 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9402 13:59:02.256881 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9403 13:59:02.259860 Root Device init finished in 553 msecs
9404 13:59:02.263482 CPU_CLUSTER: 0 init
9405 13:59:02.270263 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9406 13:59:02.276294 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9407 13:59:02.276713 APU_MBOX 0x190000b0 = 0x10001
9408 13:59:02.280464 APU_MBOX 0x190001b0 = 0x10001
9409 13:59:02.283823 APU_MBOX 0x190005b0 = 0x10001
9410 13:59:02.286665 APU_MBOX 0x190006b0 = 0x10001
9411 13:59:02.292633 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9412 13:59:02.303280 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9413 13:59:02.315401 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9414 13:59:02.322348 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9415 13:59:02.333426 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9416 13:59:02.342630 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9417 13:59:02.345892 CPU_CLUSTER: 0 init finished in 81 msecs
9418 13:59:02.349931 Devices initialized
9419 13:59:02.352442 Show all devs... After init.
9420 13:59:02.353002 Root Device: enabled 1
9421 13:59:02.355893 CPU_CLUSTER: 0: enabled 1
9422 13:59:02.358776 CPU: 00: enabled 1
9423 13:59:02.362231 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9424 13:59:02.365455 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9425 13:59:02.368920 ELOG: NV offset 0x57f000 size 0x1000
9426 13:59:02.376057 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9427 13:59:02.382452 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9428 13:59:02.386329 ELOG: Event(17) added with size 13 at 2023-09-21 13:59:04 UTC
9429 13:59:02.392640 out: cmd=0x121: 03 db 21 01 00 00 00 00
9430 13:59:02.395138 in-header: 03 b4 00 00 2c 00 00 00
9431 13:59:02.408853 in-data: ab 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9432 13:59:02.415978 ELOG: Event(A1) added with size 10 at 2023-09-21 13:59:04 UTC
9433 13:59:02.421921 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9434 13:59:02.424895 ELOG: Event(A0) added with size 9 at 2023-09-21 13:59:04 UTC
9435 13:59:02.428353 elog_add_boot_reason: Logged dev mode boot
9436 13:59:02.435276 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9437 13:59:02.438444 Finalize devices...
9438 13:59:02.439023 Devices finalized
9439 13:59:02.444922 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9440 13:59:02.448278 Writing coreboot table at 0xffe64000
9441 13:59:02.451907 0. 000000000010a000-0000000000113fff: RAMSTAGE
9442 13:59:02.455002 1. 0000000040000000-00000000400fffff: RAM
9443 13:59:02.458316 2. 0000000040100000-000000004032afff: RAMSTAGE
9444 13:59:02.461642 3. 000000004032b000-00000000545fffff: RAM
9445 13:59:02.468062 4. 0000000054600000-000000005465ffff: BL31
9446 13:59:02.471155 5. 0000000054660000-00000000ffe63fff: RAM
9447 13:59:02.474694 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9448 13:59:02.478333 7. 0000000100000000-000000023fffffff: RAM
9449 13:59:02.482381 Passing 5 GPIOs to payload:
9450 13:59:02.488306 NAME | PORT | POLARITY | VALUE
9451 13:59:02.491441 EC in RW | 0x000000aa | low | undefined
9452 13:59:02.494719 EC interrupt | 0x00000005 | low | undefined
9453 13:59:02.500800 TPM interrupt | 0x000000ab | high | undefined
9454 13:59:02.504554 SD card detect | 0x00000011 | high | undefined
9455 13:59:02.511057 speaker enable | 0x00000093 | high | undefined
9456 13:59:02.514393 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9457 13:59:02.517396 in-header: 03 f9 00 00 02 00 00 00
9458 13:59:02.517953 in-data: 02 00
9459 13:59:02.521519 ADC[4]: Raw value=901552 ID=7
9460 13:59:02.524377 ADC[3]: Raw value=214021 ID=1
9461 13:59:02.527493 RAM Code: 0x71
9462 13:59:02.528130 ADC[6]: Raw value=75036 ID=0
9463 13:59:02.531247 ADC[5]: Raw value=213652 ID=1
9464 13:59:02.533763 SKU Code: 0x1
9465 13:59:02.537105 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a16d
9466 13:59:02.540264 coreboot table: 964 bytes.
9467 13:59:02.543893 IMD ROOT 0. 0xfffff000 0x00001000
9468 13:59:02.548234 IMD SMALL 1. 0xffffe000 0x00001000
9469 13:59:02.550420 RO MCACHE 2. 0xffffc000 0x00001104
9470 13:59:02.553762 CONSOLE 3. 0xfff7c000 0x00080000
9471 13:59:02.557163 FMAP 4. 0xfff7b000 0x00000452
9472 13:59:02.560273 TIME STAMP 5. 0xfff7a000 0x00000910
9473 13:59:02.563841 VBOOT WORK 6. 0xfff66000 0x00014000
9474 13:59:02.567367 RAMOOPS 7. 0xffe66000 0x00100000
9475 13:59:02.571411 COREBOOT 8. 0xffe64000 0x00002000
9476 13:59:02.572034 IMD small region:
9477 13:59:02.573467 IMD ROOT 0. 0xffffec00 0x00000400
9478 13:59:02.580340 VPD 1. 0xffffeb80 0x0000006c
9479 13:59:02.584597 MMC STATUS 2. 0xffffeb60 0x00000004
9480 13:59:02.586909 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9481 13:59:02.590316 Probing TPM: done!
9482 13:59:02.593724 Connected to device vid:did:rid of 1ae0:0028:00
9483 13:59:02.603995 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9484 13:59:02.606816 Initialized TPM device CR50 revision 0
9485 13:59:02.611162 Checking cr50 for pending updates
9486 13:59:02.614600 Reading cr50 TPM mode
9487 13:59:02.623288 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9488 13:59:02.629835 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9489 13:59:02.669851 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9490 13:59:02.673430 Checking segment from ROM address 0x40100000
9491 13:59:02.679414 Checking segment from ROM address 0x4010001c
9492 13:59:02.683191 Loading segment from ROM address 0x40100000
9493 13:59:02.683780 code (compression=0)
9494 13:59:02.692793 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9495 13:59:02.699379 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9496 13:59:02.699982 it's not compressed!
9497 13:59:02.706114 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9498 13:59:02.712654 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9499 13:59:02.730635 Loading segment from ROM address 0x4010001c
9500 13:59:02.731235 Entry Point 0x80000000
9501 13:59:02.733627 Loaded segments
9502 13:59:02.737124 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9503 13:59:02.743491 Jumping to boot code at 0x80000000(0xffe64000)
9504 13:59:02.750077 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9505 13:59:02.756328 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9506 13:59:02.765347 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9507 13:59:02.768242 Checking segment from ROM address 0x40100000
9508 13:59:02.771672 Checking segment from ROM address 0x4010001c
9509 13:59:02.778565 Loading segment from ROM address 0x40100000
9510 13:59:02.779124 code (compression=1)
9511 13:59:02.784984 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9512 13:59:02.795178 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9513 13:59:02.795795 using LZMA
9514 13:59:02.803074 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9515 13:59:02.809912 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9516 13:59:02.813698 Loading segment from ROM address 0x4010001c
9517 13:59:02.814257 Entry Point 0x54601000
9518 13:59:02.816035 Loaded segments
9519 13:59:02.819519 NOTICE: MT8192 bl31_setup
9520 13:59:02.826877 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9521 13:59:02.830242 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9522 13:59:02.833903 WARNING: region 0:
9523 13:59:02.836259 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 13:59:02.836734 WARNING: region 1:
9525 13:59:02.842849 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9526 13:59:02.847024 WARNING: region 2:
9527 13:59:02.849798 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9528 13:59:02.852836 WARNING: region 3:
9529 13:59:02.856202 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9530 13:59:02.859745 WARNING: region 4:
9531 13:59:02.866404 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9532 13:59:02.866976 WARNING: region 5:
9533 13:59:02.869972 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9534 13:59:02.873422 WARNING: region 6:
9535 13:59:02.876624 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 13:59:02.879810 WARNING: region 7:
9537 13:59:02.883055 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 13:59:02.889637 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9539 13:59:02.892667 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9540 13:59:02.896045 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9541 13:59:02.903130 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9542 13:59:02.906130 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9543 13:59:02.912648 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9544 13:59:02.915847 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9545 13:59:02.919330 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9546 13:59:02.926203 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9547 13:59:02.929322 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9548 13:59:02.935837 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9549 13:59:02.939215 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9550 13:59:02.942432 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9551 13:59:02.948872 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9552 13:59:02.952119 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9553 13:59:02.955654 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9554 13:59:02.961901 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9555 13:59:02.965025 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9556 13:59:02.972198 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9557 13:59:02.975435 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9558 13:59:02.978891 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9559 13:59:02.985668 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9560 13:59:02.988905 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9561 13:59:02.992309 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9562 13:59:02.998805 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9563 13:59:03.002043 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9564 13:59:03.009036 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9565 13:59:03.012196 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9566 13:59:03.015407 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9567 13:59:03.022098 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9568 13:59:03.025774 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9569 13:59:03.032628 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9570 13:59:03.035432 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9571 13:59:03.038608 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9572 13:59:03.042079 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9573 13:59:03.049182 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9574 13:59:03.052431 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9575 13:59:03.054889 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9576 13:59:03.058802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9577 13:59:03.065392 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9578 13:59:03.068138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9579 13:59:03.071808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9580 13:59:03.075577 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9581 13:59:03.082176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9582 13:59:03.085251 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9583 13:59:03.088718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9584 13:59:03.095278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9585 13:59:03.098472 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9586 13:59:03.101326 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9587 13:59:03.108257 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9588 13:59:03.111864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9589 13:59:03.115117 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9590 13:59:03.121785 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9591 13:59:03.124872 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9592 13:59:03.132461 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9593 13:59:03.135314 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9594 13:59:03.141972 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9595 13:59:03.144954 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9596 13:59:03.149160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9597 13:59:03.154926 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9598 13:59:03.158890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9599 13:59:03.165038 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9600 13:59:03.168137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9601 13:59:03.174976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9602 13:59:03.178214 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9603 13:59:03.185200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9604 13:59:03.188146 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9605 13:59:03.191451 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9606 13:59:03.198115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9607 13:59:03.201579 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9608 13:59:03.207999 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9609 13:59:03.211393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9610 13:59:03.218440 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9611 13:59:03.221670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9612 13:59:03.227720 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9613 13:59:03.231396 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9614 13:59:03.234414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9615 13:59:03.241025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9616 13:59:03.244503 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9617 13:59:03.251827 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9618 13:59:03.254226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9619 13:59:03.260928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9620 13:59:03.264269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9621 13:59:03.270966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9622 13:59:03.274135 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9623 13:59:03.277822 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9624 13:59:03.284215 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9625 13:59:03.287213 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9626 13:59:03.293831 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9627 13:59:03.297113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9628 13:59:03.303833 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9629 13:59:03.307971 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9630 13:59:03.310621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9631 13:59:03.318076 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9632 13:59:03.320339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9633 13:59:03.327530 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9634 13:59:03.330779 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9635 13:59:03.334897 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9636 13:59:03.340678 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9637 13:59:03.343986 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9638 13:59:03.347183 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9639 13:59:03.350314 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9640 13:59:03.357126 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9641 13:59:03.360429 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9642 13:59:03.367144 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9643 13:59:03.370736 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9644 13:59:03.373519 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9645 13:59:03.380449 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9646 13:59:03.384109 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9647 13:59:03.390597 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9648 13:59:03.393838 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9649 13:59:03.396694 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9650 13:59:03.403289 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9651 13:59:03.406550 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9652 13:59:03.413401 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9653 13:59:03.416563 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9654 13:59:03.420183 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9655 13:59:03.426701 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9656 13:59:03.429857 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9657 13:59:03.433204 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9658 13:59:03.440279 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9659 13:59:03.443763 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9660 13:59:03.446548 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9661 13:59:03.450092 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9662 13:59:03.456715 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9663 13:59:03.459351 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9664 13:59:03.466968 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9665 13:59:03.469960 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9666 13:59:03.473273 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9667 13:59:03.479797 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9668 13:59:03.482799 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9669 13:59:03.486481 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9670 13:59:03.492681 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9671 13:59:03.496293 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9672 13:59:03.502917 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9673 13:59:03.505855 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9674 13:59:03.509046 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9675 13:59:03.515831 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9676 13:59:03.519276 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9677 13:59:03.525832 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9678 13:59:03.529145 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9679 13:59:03.532373 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9680 13:59:03.539026 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9681 13:59:03.542191 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9682 13:59:03.549242 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9683 13:59:03.552403 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9684 13:59:03.555876 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9685 13:59:03.562390 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9686 13:59:03.566080 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9687 13:59:03.572323 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9688 13:59:03.575984 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9689 13:59:03.579086 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9690 13:59:03.585595 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9691 13:59:03.589860 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9692 13:59:03.595539 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9693 13:59:03.598702 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9694 13:59:03.602469 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9695 13:59:03.608581 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9696 13:59:03.612974 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9697 13:59:03.615203 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9698 13:59:03.622222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9699 13:59:03.624989 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9700 13:59:03.631589 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9701 13:59:03.635078 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9702 13:59:03.642144 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9703 13:59:03.645413 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9704 13:59:03.649313 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9705 13:59:03.655198 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9706 13:59:03.658702 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9707 13:59:03.662599 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9708 13:59:03.668612 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9709 13:59:03.671908 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9710 13:59:03.678669 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9711 13:59:03.681895 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9712 13:59:03.685357 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9713 13:59:03.691584 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9714 13:59:03.694796 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9715 13:59:03.701375 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9716 13:59:03.704831 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9717 13:59:03.708345 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9718 13:59:03.715331 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9719 13:59:03.718213 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9720 13:59:03.724689 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9721 13:59:03.727706 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9722 13:59:03.730677 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9723 13:59:03.737621 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9724 13:59:03.741504 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9725 13:59:03.747490 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9726 13:59:03.750860 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9727 13:59:03.754569 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9728 13:59:03.760971 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9729 13:59:03.764055 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9730 13:59:03.770983 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9731 13:59:03.773962 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9732 13:59:03.780722 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9733 13:59:03.783991 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9734 13:59:03.787303 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9735 13:59:03.794130 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9736 13:59:03.797480 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9737 13:59:03.804232 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9738 13:59:03.807310 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9739 13:59:03.813749 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9740 13:59:03.817898 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9741 13:59:03.820425 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9742 13:59:03.826898 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9743 13:59:03.829868 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9744 13:59:03.836733 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9745 13:59:03.840271 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9746 13:59:03.846848 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9747 13:59:03.849796 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9748 13:59:03.853059 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9749 13:59:03.859579 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9750 13:59:03.862748 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9751 13:59:03.869452 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9752 13:59:03.873326 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9753 13:59:03.879492 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9754 13:59:03.883180 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9755 13:59:03.886033 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9756 13:59:03.892710 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9757 13:59:03.895874 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9758 13:59:03.902772 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9759 13:59:03.905998 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9760 13:59:03.912583 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9761 13:59:03.915921 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9762 13:59:03.919664 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9763 13:59:03.925734 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9764 13:59:03.929090 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9765 13:59:03.935604 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9766 13:59:03.938921 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9767 13:59:03.942536 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9768 13:59:03.945674 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9769 13:59:03.951771 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9770 13:59:03.955424 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9771 13:59:03.958789 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9772 13:59:03.965064 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9773 13:59:03.968435 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9774 13:59:03.971775 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9775 13:59:03.978419 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9776 13:59:03.981668 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9777 13:59:03.985809 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9778 13:59:03.991618 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9779 13:59:03.995380 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9780 13:59:04.001939 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9781 13:59:04.004965 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9782 13:59:04.008038 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9783 13:59:04.014795 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9784 13:59:04.017992 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9785 13:59:04.025931 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9786 13:59:04.028343 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9787 13:59:04.031815 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9788 13:59:04.038077 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9789 13:59:04.041384 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9790 13:59:04.044477 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9791 13:59:04.051865 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9792 13:59:04.054476 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9793 13:59:04.058461 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9794 13:59:04.064424 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9795 13:59:04.067664 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9796 13:59:04.074133 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9797 13:59:04.077808 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9798 13:59:04.080686 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9799 13:59:04.087682 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9800 13:59:04.090955 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9801 13:59:04.094358 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9802 13:59:04.101126 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9803 13:59:04.104417 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9804 13:59:04.110974 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9805 13:59:04.113953 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9806 13:59:04.117309 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9807 13:59:04.121076 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9808 13:59:04.127222 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9809 13:59:04.130677 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9810 13:59:04.134236 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9811 13:59:04.136961 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9812 13:59:04.143872 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9813 13:59:04.147180 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9814 13:59:04.150182 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9815 13:59:04.154131 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9816 13:59:04.160300 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9817 13:59:04.163439 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9818 13:59:04.167475 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9819 13:59:04.173449 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9820 13:59:04.176758 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9821 13:59:04.179693 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9822 13:59:04.187080 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9823 13:59:04.190085 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9824 13:59:04.197385 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9825 13:59:04.199479 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9826 13:59:04.206280 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9827 13:59:04.209302 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9828 13:59:04.212606 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9829 13:59:04.219274 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9830 13:59:04.223010 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9831 13:59:04.230399 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9832 13:59:04.233037 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9833 13:59:04.236160 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9834 13:59:04.243012 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9835 13:59:04.246181 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9836 13:59:04.252510 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9837 13:59:04.255817 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9838 13:59:04.259361 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9839 13:59:04.265790 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9840 13:59:04.269554 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9841 13:59:04.275541 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9842 13:59:04.278600 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9843 13:59:04.285980 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9844 13:59:04.289105 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9845 13:59:04.292832 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9846 13:59:04.298595 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9847 13:59:04.301997 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9848 13:59:04.308490 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9849 13:59:04.311824 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9850 13:59:04.318204 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9851 13:59:04.321671 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9852 13:59:04.325704 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9853 13:59:04.331478 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9854 13:59:04.334342 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9855 13:59:04.341633 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9856 13:59:04.344388 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9857 13:59:04.351046 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9858 13:59:04.354324 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9859 13:59:04.358786 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9860 13:59:04.364348 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9861 13:59:04.367848 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9862 13:59:04.374215 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9863 13:59:04.377469 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9864 13:59:04.384690 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9865 13:59:04.387272 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9866 13:59:04.390511 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9867 13:59:04.397482 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9868 13:59:04.400156 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9869 13:59:04.407235 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9870 13:59:04.410373 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9871 13:59:04.413836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9872 13:59:04.419872 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9873 13:59:04.423850 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9874 13:59:04.430270 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9875 13:59:04.433381 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9876 13:59:04.436982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9877 13:59:04.443688 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9878 13:59:04.447057 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9879 13:59:04.453217 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9880 13:59:04.456142 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9881 13:59:04.462894 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9882 13:59:04.466024 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9883 13:59:04.469674 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9884 13:59:04.476736 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9885 13:59:04.479618 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9886 13:59:04.486159 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9887 13:59:04.489784 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9888 13:59:04.496595 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9889 13:59:04.499596 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9890 13:59:04.502726 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9891 13:59:04.509430 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9892 13:59:04.512477 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9893 13:59:04.519544 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9894 13:59:04.522917 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9895 13:59:04.529336 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9896 13:59:04.532742 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9897 13:59:04.539606 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9898 13:59:04.541772 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9899 13:59:04.545277 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9900 13:59:04.552120 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9901 13:59:04.555595 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9902 13:59:04.561779 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9903 13:59:04.564955 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9904 13:59:04.572030 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9905 13:59:04.574906 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9906 13:59:04.582161 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9907 13:59:04.585010 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9908 13:59:04.588309 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9909 13:59:04.595516 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9910 13:59:04.598942 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9911 13:59:04.605052 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9912 13:59:04.608161 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9913 13:59:04.614896 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9914 13:59:04.618141 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9915 13:59:04.621486 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9916 13:59:04.627520 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9917 13:59:04.630871 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9918 13:59:04.637770 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9919 13:59:04.640935 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9920 13:59:04.648341 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9921 13:59:04.650750 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9922 13:59:04.657816 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9923 13:59:04.660535 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9924 13:59:04.663995 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9925 13:59:04.670807 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9926 13:59:04.674116 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9927 13:59:04.680379 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9928 13:59:04.684121 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9929 13:59:04.690691 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9930 13:59:04.693743 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9931 13:59:04.700861 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9932 13:59:04.703884 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9933 13:59:04.709972 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9934 13:59:04.713689 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9935 13:59:04.716494 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9936 13:59:04.723010 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9937 13:59:04.726838 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9938 13:59:04.733955 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9939 13:59:04.736430 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9940 13:59:04.739660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9941 13:59:04.746139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9942 13:59:04.749482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9943 13:59:04.756745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9944 13:59:04.759948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9945 13:59:04.766208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9946 13:59:04.770133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9947 13:59:04.776678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9948 13:59:04.779517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9949 13:59:04.786173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9950 13:59:04.789302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9951 13:59:04.796266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9952 13:59:04.799501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9953 13:59:04.806301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9954 13:59:04.809228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9955 13:59:04.815673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9956 13:59:04.818565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9957 13:59:04.825623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9958 13:59:04.828748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9959 13:59:04.835866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9960 13:59:04.838767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9961 13:59:04.844950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9962 13:59:04.848473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9963 13:59:04.855259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9964 13:59:04.858671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9965 13:59:04.864977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9966 13:59:04.868113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9967 13:59:04.875112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9968 13:59:04.878227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9969 13:59:04.884592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9970 13:59:04.888367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9971 13:59:04.895095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9972 13:59:04.898330 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9973 13:59:04.901198 INFO: [APUAPC] vio 0
9974 13:59:04.905217 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9975 13:59:04.911485 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9976 13:59:04.914851 INFO: [APUAPC] D0_APC_0: 0x400510
9977 13:59:04.917639 INFO: [APUAPC] D0_APC_1: 0x0
9978 13:59:04.918113 INFO: [APUAPC] D0_APC_2: 0x1540
9979 13:59:04.921456 INFO: [APUAPC] D0_APC_3: 0x0
9980 13:59:04.924462 INFO: [APUAPC] D1_APC_0: 0xffffffff
9981 13:59:04.927524 INFO: [APUAPC] D1_APC_1: 0xffffffff
9982 13:59:04.930916 INFO: [APUAPC] D1_APC_2: 0x3fffff
9983 13:59:04.934333 INFO: [APUAPC] D1_APC_3: 0x0
9984 13:59:04.937557 INFO: [APUAPC] D2_APC_0: 0xffffffff
9985 13:59:04.940556 INFO: [APUAPC] D2_APC_1: 0xffffffff
9986 13:59:04.944438 INFO: [APUAPC] D2_APC_2: 0x3fffff
9987 13:59:04.947439 INFO: [APUAPC] D2_APC_3: 0x0
9988 13:59:04.951395 INFO: [APUAPC] D3_APC_0: 0xffffffff
9989 13:59:04.954395 INFO: [APUAPC] D3_APC_1: 0xffffffff
9990 13:59:04.957477 INFO: [APUAPC] D3_APC_2: 0x3fffff
9991 13:59:04.960723 INFO: [APUAPC] D3_APC_3: 0x0
9992 13:59:04.964015 INFO: [APUAPC] D4_APC_0: 0xffffffff
9993 13:59:04.967246 INFO: [APUAPC] D4_APC_1: 0xffffffff
9994 13:59:04.971330 INFO: [APUAPC] D4_APC_2: 0x3fffff
9995 13:59:04.974029 INFO: [APUAPC] D4_APC_3: 0x0
9996 13:59:04.977283 INFO: [APUAPC] D5_APC_0: 0xffffffff
9997 13:59:04.980244 INFO: [APUAPC] D5_APC_1: 0xffffffff
9998 13:59:04.983819 INFO: [APUAPC] D5_APC_2: 0x3fffff
9999 13:59:04.987190 INFO: [APUAPC] D5_APC_3: 0x0
10000 13:59:04.990282 INFO: [APUAPC] D6_APC_0: 0xffffffff
10001 13:59:04.994138 INFO: [APUAPC] D6_APC_1: 0xffffffff
10002 13:59:04.996553 INFO: [APUAPC] D6_APC_2: 0x3fffff
10003 13:59:05.000356 INFO: [APUAPC] D6_APC_3: 0x0
10004 13:59:05.003241 INFO: [APUAPC] D7_APC_0: 0xffffffff
10005 13:59:05.006985 INFO: [APUAPC] D7_APC_1: 0xffffffff
10006 13:59:05.010697 INFO: [APUAPC] D7_APC_2: 0x3fffff
10007 13:59:05.013077 INFO: [APUAPC] D7_APC_3: 0x0
10008 13:59:05.016821 INFO: [APUAPC] D8_APC_0: 0xffffffff
10009 13:59:05.019969 INFO: [APUAPC] D8_APC_1: 0xffffffff
10010 13:59:05.023523 INFO: [APUAPC] D8_APC_2: 0x3fffff
10011 13:59:05.026874 INFO: [APUAPC] D8_APC_3: 0x0
10012 13:59:05.030247 INFO: [APUAPC] D9_APC_0: 0xffffffff
10013 13:59:05.033089 INFO: [APUAPC] D9_APC_1: 0xffffffff
10014 13:59:05.036490 INFO: [APUAPC] D9_APC_2: 0x3fffff
10015 13:59:05.039580 INFO: [APUAPC] D9_APC_3: 0x0
10016 13:59:05.043112 INFO: [APUAPC] D10_APC_0: 0xffffffff
10017 13:59:05.046217 INFO: [APUAPC] D10_APC_1: 0xffffffff
10018 13:59:05.049928 INFO: [APUAPC] D10_APC_2: 0x3fffff
10019 13:59:05.052577 INFO: [APUAPC] D10_APC_3: 0x0
10020 13:59:05.056386 INFO: [APUAPC] D11_APC_0: 0xffffffff
10021 13:59:05.059448 INFO: [APUAPC] D11_APC_1: 0xffffffff
10022 13:59:05.062460 INFO: [APUAPC] D11_APC_2: 0x3fffff
10023 13:59:05.066403 INFO: [APUAPC] D11_APC_3: 0x0
10024 13:59:05.069382 INFO: [APUAPC] D12_APC_0: 0xffffffff
10025 13:59:05.072547 INFO: [APUAPC] D12_APC_1: 0xffffffff
10026 13:59:05.076177 INFO: [APUAPC] D12_APC_2: 0x3fffff
10027 13:59:05.079364 INFO: [APUAPC] D12_APC_3: 0x0
10028 13:59:05.082609 INFO: [APUAPC] D13_APC_0: 0xffffffff
10029 13:59:05.085823 INFO: [APUAPC] D13_APC_1: 0xffffffff
10030 13:59:05.089082 INFO: [APUAPC] D13_APC_2: 0x3fffff
10031 13:59:05.092337 INFO: [APUAPC] D13_APC_3: 0x0
10032 13:59:05.095840 INFO: [APUAPC] D14_APC_0: 0xffffffff
10033 13:59:05.099003 INFO: [APUAPC] D14_APC_1: 0xffffffff
10034 13:59:05.102133 INFO: [APUAPC] D14_APC_2: 0x3fffff
10035 13:59:05.105664 INFO: [APUAPC] D14_APC_3: 0x0
10036 13:59:05.108700 INFO: [APUAPC] D15_APC_0: 0xffffffff
10037 13:59:05.112359 INFO: [APUAPC] D15_APC_1: 0xffffffff
10038 13:59:05.116138 INFO: [APUAPC] D15_APC_2: 0x3fffff
10039 13:59:05.118570 INFO: [APUAPC] D15_APC_3: 0x0
10040 13:59:05.122473 INFO: [APUAPC] APC_CON: 0x4
10041 13:59:05.125244 INFO: [NOCDAPC] D0_APC_0: 0x0
10042 13:59:05.128690 INFO: [NOCDAPC] D0_APC_1: 0x0
10043 13:59:05.132430 INFO: [NOCDAPC] D1_APC_0: 0x0
10044 13:59:05.135007 INFO: [NOCDAPC] D1_APC_1: 0xfff
10045 13:59:05.138140 INFO: [NOCDAPC] D2_APC_0: 0x0
10046 13:59:05.142021 INFO: [NOCDAPC] D2_APC_1: 0xfff
10047 13:59:05.142582 INFO: [NOCDAPC] D3_APC_0: 0x0
10048 13:59:05.144475 INFO: [NOCDAPC] D3_APC_1: 0xfff
10049 13:59:05.148577 INFO: [NOCDAPC] D4_APC_0: 0x0
10050 13:59:05.151706 INFO: [NOCDAPC] D4_APC_1: 0xfff
10051 13:59:05.155150 INFO: [NOCDAPC] D5_APC_0: 0x0
10052 13:59:05.157816 INFO: [NOCDAPC] D5_APC_1: 0xfff
10053 13:59:05.161271 INFO: [NOCDAPC] D6_APC_0: 0x0
10054 13:59:05.164661 INFO: [NOCDAPC] D6_APC_1: 0xfff
10055 13:59:05.167649 INFO: [NOCDAPC] D7_APC_0: 0x0
10056 13:59:05.171658 INFO: [NOCDAPC] D7_APC_1: 0xfff
10057 13:59:05.174486 INFO: [NOCDAPC] D8_APC_0: 0x0
10058 13:59:05.178160 INFO: [NOCDAPC] D8_APC_1: 0xfff
10059 13:59:05.178750 INFO: [NOCDAPC] D9_APC_0: 0x0
10060 13:59:05.181358 INFO: [NOCDAPC] D9_APC_1: 0xfff
10061 13:59:05.184344 INFO: [NOCDAPC] D10_APC_0: 0x0
10062 13:59:05.187900 INFO: [NOCDAPC] D10_APC_1: 0xfff
10063 13:59:05.191181 INFO: [NOCDAPC] D11_APC_0: 0x0
10064 13:59:05.194695 INFO: [NOCDAPC] D11_APC_1: 0xfff
10065 13:59:05.197427 INFO: [NOCDAPC] D12_APC_0: 0x0
10066 13:59:05.201183 INFO: [NOCDAPC] D12_APC_1: 0xfff
10067 13:59:05.204588 INFO: [NOCDAPC] D13_APC_0: 0x0
10068 13:59:05.207591 INFO: [NOCDAPC] D13_APC_1: 0xfff
10069 13:59:05.210546 INFO: [NOCDAPC] D14_APC_0: 0x0
10070 13:59:05.214416 INFO: [NOCDAPC] D14_APC_1: 0xfff
10071 13:59:05.217040 INFO: [NOCDAPC] D15_APC_0: 0x0
10072 13:59:05.220462 INFO: [NOCDAPC] D15_APC_1: 0xfff
10073 13:59:05.223832 INFO: [NOCDAPC] APC_CON: 0x4
10074 13:59:05.227114 INFO: [APUAPC] set_apusys_apc done
10075 13:59:05.230744 INFO: [DEVAPC] devapc_init done
10076 13:59:05.233635 INFO: GICv3 without legacy support detected.
10077 13:59:05.237566 INFO: ARM GICv3 driver initialized in EL3
10078 13:59:05.240080 INFO: Maximum SPI INTID supported: 639
10079 13:59:05.243764 INFO: BL31: Initializing runtime services
10080 13:59:05.250683 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10081 13:59:05.253976 INFO: SPM: enable CPC mode
10082 13:59:05.260417 INFO: mcdi ready for mcusys-off-idle and system suspend
10083 13:59:05.263555 INFO: BL31: Preparing for EL3 exit to normal world
10084 13:59:05.266581 INFO: Entry point address = 0x80000000
10085 13:59:05.270030 INFO: SPSR = 0x8
10086 13:59:05.274746
10087 13:59:05.275302
10088 13:59:05.275675
10089 13:59:05.277852 Starting depthcharge on Spherion...
10090 13:59:05.278339
10091 13:59:05.278718 Wipe memory regions:
10092 13:59:05.279070
10093 13:59:05.281955 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10094 13:59:05.282529 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10095 13:59:05.282974 Setting prompt string to ['asurada:']
10096 13:59:05.283373 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10097 13:59:05.284073 [0x00000040000000, 0x00000054600000)
10098 13:59:05.403447
10099 13:59:05.404128 [0x00000054660000, 0x00000080000000)
10100 13:59:05.664012
10101 13:59:05.664562 [0x000000821a7280, 0x000000ffe64000)
10102 13:59:06.408590
10103 13:59:06.409279 [0x00000100000000, 0x00000240000000)
10104 13:59:08.297975
10105 13:59:08.301550 Initializing XHCI USB controller at 0x11200000.
10106 13:59:09.283010
10107 13:59:09.283563 R8152: Initializing
10108 13:59:09.283978
10109 13:59:09.286616 Version 9 (ocp_data = 6010)
10110 13:59:09.287208
10111 13:59:09.289850 R8152: Done initializing
10112 13:59:09.290449
10113 13:59:09.291059 Adding net device
10114 13:59:09.811609
10115 13:59:09.814548 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10116 13:59:09.815009
10117 13:59:09.815369
10118 13:59:09.815710
10119 13:59:09.816581 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10121 13:59:09.918176 asurada: tftpboot 192.168.201.1 11588086/tftp-deploy-69elt4hq/kernel/image.itb 11588086/tftp-deploy-69elt4hq/kernel/cmdline
10122 13:59:09.918833 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10123 13:59:09.919307 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10124 13:59:09.924171 tftpboot 192.168.201.1 11588086/tftp-deploy-69elt4hq/kernel/image.ittp-deploy-69elt4hq/kernel/cmdline
10125 13:59:09.924732
10126 13:59:09.925107 Waiting for link
10127 13:59:10.126573
10128 13:59:10.127251 done.
10129 13:59:10.127638
10130 13:59:10.128067 MAC: f4:f5:e8:50:de:0a
10131 13:59:10.128409
10132 13:59:10.129351 Sending DHCP discover... done.
10133 13:59:10.129817
10134 13:59:10.132922 Waiting for reply... done.
10135 13:59:10.133380
10136 13:59:10.136281 Sending DHCP request... done.
10137 13:59:10.136741
10138 13:59:10.141129 Waiting for reply... done.
10139 13:59:10.141681
10140 13:59:10.142054 My ip is 192.168.201.14
10141 13:59:10.142393
10142 13:59:10.144360 The DHCP server ip is 192.168.201.1
10143 13:59:10.144827
10144 13:59:10.151353 TFTP server IP predefined by user: 192.168.201.1
10145 13:59:10.151980
10146 13:59:10.157865 Bootfile predefined by user: 11588086/tftp-deploy-69elt4hq/kernel/image.itb
10147 13:59:10.158421
10148 13:59:10.160980 Sending tftp read request... done.
10149 13:59:10.161442
10150 13:59:10.167428 Waiting for the transfer...
10151 13:59:10.167968
10152 13:59:10.431344 00000000 ################################################################
10153 13:59:10.431494
10154 13:59:10.682019 00080000 ################################################################
10155 13:59:10.682168
10156 13:59:10.940785 00100000 ################################################################
10157 13:59:10.940927
10158 13:59:11.192845 00180000 ################################################################
10159 13:59:11.192987
10160 13:59:11.437196 00200000 ################################################################
10161 13:59:11.437337
10162 13:59:11.702503 00280000 ################################################################
10163 13:59:11.702649
10164 13:59:11.965282 00300000 ################################################################
10165 13:59:11.965435
10166 13:59:12.220216 00380000 ################################################################
10167 13:59:12.220389
10168 13:59:12.476437 00400000 ################################################################
10169 13:59:12.476580
10170 13:59:12.731051 00480000 ################################################################
10171 13:59:12.731200
10172 13:59:12.971292 00500000 ################################################################
10173 13:59:12.971442
10174 13:59:13.242248 00580000 ################################################################
10175 13:59:13.242388
10176 13:59:13.504121 00600000 ################################################################
10177 13:59:13.504261
10178 13:59:13.741053 00680000 ################################################################
10179 13:59:13.741200
10180 13:59:13.968384 00700000 ################################################################
10181 13:59:13.968526
10182 13:59:14.195007 00780000 ################################################################
10183 13:59:14.195145
10184 13:59:14.432838 00800000 ################################################################
10185 13:59:14.432969
10186 13:59:14.691538 00880000 ################################################################
10187 13:59:14.691680
10188 13:59:14.919185 00900000 ################################################################
10189 13:59:14.919333
10190 13:59:15.167569 00980000 ################################################################
10191 13:59:15.167754
10192 13:59:15.407582 00a00000 ################################################################
10193 13:59:15.407720
10194 13:59:15.640822 00a80000 ################################################################
10195 13:59:15.640958
10196 13:59:15.876939 00b00000 ################################################################
10197 13:59:15.877090
10198 13:59:16.136831 00b80000 ################################################################
10199 13:59:16.136969
10200 13:59:16.398335 00c00000 ################################################################
10201 13:59:16.398470
10202 13:59:16.642065 00c80000 ################################################################
10203 13:59:16.642205
10204 13:59:16.878009 00d00000 ################################################################
10205 13:59:16.878145
10206 13:59:17.117224 00d80000 ################################################################
10207 13:59:17.117360
10208 13:59:17.380189 00e00000 ################################################################
10209 13:59:17.380330
10210 13:59:17.649130 00e80000 ################################################################
10211 13:59:17.649268
10212 13:59:17.899368 00f00000 ################################################################
10213 13:59:17.899507
10214 13:59:18.135053 00f80000 ################################################################
10215 13:59:18.135185
10216 13:59:18.381967 01000000 ################################################################
10217 13:59:18.382107
10218 13:59:18.653879 01080000 ################################################################
10219 13:59:18.654015
10220 13:59:18.911911 01100000 ################################################################
10221 13:59:18.912055
10222 13:59:19.153827 01180000 ################################################################
10223 13:59:19.153967
10224 13:59:19.384791 01200000 ################################################################
10225 13:59:19.384927
10226 13:59:19.644071 01280000 ################################################################
10227 13:59:19.644206
10228 13:59:19.895940 01300000 ################################################################
10229 13:59:19.896078
10230 13:59:20.136781 01380000 ################################################################
10231 13:59:20.136915
10232 13:59:20.377465 01400000 ################################################################
10233 13:59:20.377603
10234 13:59:20.647576 01480000 ################################################################
10235 13:59:20.647717
10236 13:59:20.883919 01500000 ################################################################
10237 13:59:20.884069
10238 13:59:21.139615 01580000 ################################################################
10239 13:59:21.139804
10240 13:59:21.397778 01600000 ################################################################
10241 13:59:21.397917
10242 13:59:21.637712 01680000 ################################################################
10243 13:59:21.637849
10244 13:59:21.868191 01700000 ################################################################
10245 13:59:21.868324
10246 13:59:22.115244 01780000 ################################################################
10247 13:59:22.115387
10248 13:59:22.360660 01800000 ################################################################
10249 13:59:22.360820
10250 13:59:22.611435 01880000 ################################################################
10251 13:59:22.611575
10252 13:59:22.844107 01900000 ################################################################
10253 13:59:22.844242
10254 13:59:23.087579 01980000 ################################################################
10255 13:59:23.087795
10256 13:59:23.353941 01a00000 ################################################################
10257 13:59:23.354081
10258 13:59:23.603249 01a80000 ################################################################
10259 13:59:23.603389
10260 13:59:23.831581 01b00000 ################################################################
10261 13:59:23.831714
10262 13:59:24.090358 01b80000 ################################################################
10263 13:59:24.090505
10264 13:59:24.332677 01c00000 ################################################################
10265 13:59:24.332815
10266 13:59:24.564196 01c80000 ################################################################
10267 13:59:24.564333
10268 13:59:24.797190 01d00000 ################################################################
10269 13:59:24.797343
10270 13:59:25.027055 01d80000 ################################################################
10271 13:59:25.027186
10272 13:59:25.280103 01e00000 ################################################################
10273 13:59:25.280246
10274 13:59:25.538234 01e80000 ############################################################## done.
10275 13:59:25.538375
10276 13:59:25.541825 The bootfile was 32488006 bytes long.
10277 13:59:25.541914
10278 13:59:25.544599 Sending tftp read request... done.
10279 13:59:25.544732
10280 13:59:25.544867 Waiting for the transfer...
10281 13:59:25.544943
10282 13:59:25.547846 00000000 # done.
10283 13:59:25.547942
10284 13:59:25.554838 Command line loaded dynamically from TFTP file: 11588086/tftp-deploy-69elt4hq/kernel/cmdline
10285 13:59:25.555028
10286 13:59:25.568365 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10287 13:59:25.568596
10288 13:59:25.571191 Loading FIT.
10289 13:59:25.571424
10290 13:59:25.574405 Image ramdisk-1 has 21393819 bytes.
10291 13:59:25.574587
10292 13:59:25.578163 Image fdt-1 has 47278 bytes.
10293 13:59:25.578464
10294 13:59:25.578637 Image kernel-1 has 11044874 bytes.
10295 13:59:25.581152
10296 13:59:25.587714 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10297 13:59:25.588072
10298 13:59:25.608185 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10299 13:59:25.608769
10300 13:59:25.611486 Choosing best match conf-1 for compat google,spherion-rev2.
10301 13:59:25.616098
10302 13:59:25.619682 Connected to device vid:did:rid of 1ae0:0028:00
10303 13:59:25.627670
10304 13:59:25.631075 tpm_get_response: command 0x17b, return code 0x0
10305 13:59:25.631632
10306 13:59:25.634142 ec_init: CrosEC protocol v3 supported (256, 248)
10307 13:59:25.638538
10308 13:59:25.642166 tpm_cleanup: add release locality here.
10309 13:59:25.642725
10310 13:59:25.643090 Shutting down all USB controllers.
10311 13:59:25.645054
10312 13:59:25.645514 Removing current net device
10313 13:59:25.645886
10314 13:59:25.652194 Exiting depthcharge with code 4 at timestamp: 49815614
10315 13:59:25.652753
10316 13:59:25.656233 LZMA decompressing kernel-1 to 0x821a6718
10317 13:59:25.656791
10318 13:59:25.658529 LZMA decompressing kernel-1 to 0x40000000
10319 13:59:27.046733
10320 13:59:27.047290 jumping to kernel
10321 13:59:27.048751 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10322 13:59:27.049291 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10323 13:59:27.049701 Setting prompt string to ['Linux version [0-9]']
10324 13:59:27.050092 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10325 13:59:27.050547 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10326 13:59:27.128101
10327 13:59:27.131477 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10328 13:59:27.135112 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10329 13:59:27.135692 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10330 13:59:27.136158 Setting prompt string to []
10331 13:59:27.136595 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10332 13:59:27.137000 Using line separator: #'\n'#
10333 13:59:27.137368 No login prompt set.
10334 13:59:27.137870 Parsing kernel messages
10335 13:59:27.138200 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10336 13:59:27.138752 [login-action] Waiting for messages, (timeout 00:04:03)
10337 13:59:27.154984 [ 0.000000] Linux version 6.1.54-cip6-rt3 (KernelCI@build-j53691-arm64-gcc-10-defconfig-arm64-chromebook-2d8w4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Sep 21 13:44:36 UTC 2023
10338 13:59:27.158429 [ 0.000000] random: crng init done
10339 13:59:27.164331 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10340 13:59:27.167708 [ 0.000000] efi: UEFI not found.
10341 13:59:27.174906 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10342 13:59:27.184020 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10343 13:59:27.193754 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10344 13:59:27.200195 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10345 13:59:27.206846 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10346 13:59:27.213850 [ 0.000000] printk: bootconsole [mtk8250] enabled
10347 13:59:27.220660 [ 0.000000] NUMA: No NUMA configuration found
10348 13:59:27.226906 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10349 13:59:27.234113 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10350 13:59:27.234432 [ 0.000000] Zone ranges:
10351 13:59:27.240129 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10352 13:59:27.243232 [ 0.000000] DMA32 empty
10353 13:59:27.250325 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10354 13:59:27.253782 [ 0.000000] Movable zone start for each node
10355 13:59:27.256308 [ 0.000000] Early memory node ranges
10356 13:59:27.263878 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10357 13:59:27.269814 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10358 13:59:27.276618 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10359 13:59:27.283124 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10360 13:59:27.289796 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10361 13:59:27.296124 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10362 13:59:27.353036 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10363 13:59:27.359927 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10364 13:59:27.365947 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10365 13:59:27.369443 [ 0.000000] psci: probing for conduit method from DT.
10366 13:59:27.376117 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10367 13:59:27.379284 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10368 13:59:27.385827 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10369 13:59:27.389117 [ 0.000000] psci: SMC Calling Convention v1.2
10370 13:59:27.396119 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10371 13:59:27.399602 [ 0.000000] Detected VIPT I-cache on CPU0
10372 13:59:27.406204 [ 0.000000] CPU features: detected: GIC system register CPU interface
10373 13:59:27.412505 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10374 13:59:27.419157 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10375 13:59:27.426133 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10376 13:59:27.433094 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10377 13:59:27.442020 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10378 13:59:27.445291 [ 0.000000] alternatives: applying boot alternatives
10379 13:59:27.452211 [ 0.000000] Fallback order for Node 0: 0
10380 13:59:27.458602 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10381 13:59:27.461998 [ 0.000000] Policy zone: Normal
10382 13:59:27.474974 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10383 13:59:27.484931 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10384 13:59:27.495963 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10385 13:59:27.506009 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10386 13:59:27.512314 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10387 13:59:27.516240 <6>[ 0.000000] software IO TLB: area num 8.
10388 13:59:27.572632 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10389 13:59:27.721860 <6>[ 0.000000] Memory: 7948536K/8385536K available (17984K kernel code, 4116K rwdata, 17472K rodata, 8448K init, 615K bss, 404232K reserved, 32768K cma-reserved)
10390 13:59:27.728224 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10391 13:59:27.735063 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10392 13:59:27.738298 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10393 13:59:27.745248 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10394 13:59:27.751495 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10395 13:59:27.754381 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10396 13:59:27.764706 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10397 13:59:27.771036 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10398 13:59:27.777938 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10399 13:59:27.784415 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10400 13:59:27.787445 <6>[ 0.000000] GICv3: 608 SPIs implemented
10401 13:59:27.790862 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10402 13:59:27.797840 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10403 13:59:27.801396 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10404 13:59:27.807885 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10405 13:59:27.820737 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10406 13:59:27.834230 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10407 13:59:27.840554 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10408 13:59:27.848467 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10409 13:59:27.862498 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10410 13:59:27.868428 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10411 13:59:27.875057 <6>[ 0.009238] Console: colour dummy device 80x25
10412 13:59:27.884592 <6>[ 0.013963] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10413 13:59:27.891377 <6>[ 0.024406] pid_max: default: 32768 minimum: 301
10414 13:59:27.894494 <6>[ 0.029279] LSM: Security Framework initializing
10415 13:59:27.901168 <6>[ 0.034218] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10416 13:59:27.910931 <6>[ 0.042032] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10417 13:59:27.921041 <6>[ 0.051435] cblist_init_generic: Setting adjustable number of callback queues.
10418 13:59:27.927519 <6>[ 0.058877] cblist_init_generic: Setting shift to 3 and lim to 1.
10419 13:59:27.934343 <6>[ 0.065216] cblist_init_generic: Setting adjustable number of callback queues.
10420 13:59:27.940811 <6>[ 0.072690] cblist_init_generic: Setting shift to 3 and lim to 1.
10421 13:59:27.944145 <6>[ 0.079117] rcu: Hierarchical SRCU implementation.
10422 13:59:27.951524 <6>[ 0.079119] rcu: Max phase no-delay instances is 1000.
10423 13:59:27.957272 <6>[ 0.079142] printk: bootconsole [mtk8250] printing thread started
10424 13:59:27.964293 <6>[ 0.097427] EFI services will not be available.
10425 13:59:27.966975 <6>[ 0.097627] smp: Bringing up secondary CPUs ...
10426 13:59:27.973915 <6>[ 0.097937] Detected VIPT I-cache on CPU1
10427 13:59:27.980691 <6>[ 0.098007] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10428 13:59:27.986756 <6>[ 0.098040] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10429 13:59:27.996414 <6>[ 0.125941] Detected VIPT I-cache on CPU2
10430 13:59:28.003221 <6>[ 0.125992] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10431 13:59:28.012796 <6>[ 0.126009] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10432 13:59:28.016696 <6>[ 0.126264] Detected VIPT I-cache on CPU3
10433 13:59:28.023420 <6>[ 0.126309] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10434 13:59:28.029713 <6>[ 0.126323] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10435 13:59:28.032705 <6>[ 0.126635] CPU features: detected: Spectre-v4
10436 13:59:28.039487 <6>[ 0.126642] CPU features: detected: Spectre-BHB
10437 13:59:28.043111 <6>[ 0.126647] Detected PIPT I-cache on CPU4
10438 13:59:28.049701 <6>[ 0.126705] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10439 13:59:28.056417 <6>[ 0.126722] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10440 13:59:28.062645 <6>[ 0.127012] Detected PIPT I-cache on CPU5
10441 13:59:28.069343 <6>[ 0.127072] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10442 13:59:28.076204 <6>[ 0.127089] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10443 13:59:28.079223 <6>[ 0.127364] Detected PIPT I-cache on CPU6
10444 13:59:28.089308 <6>[ 0.127425] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10445 13:59:28.096004 <6>[ 0.127442] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10446 13:59:28.099220 <6>[ 0.127733] Detected PIPT I-cache on CPU7
10447 13:59:28.105335 <6>[ 0.127797] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10448 13:59:28.111879 <6>[ 0.127813] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10449 13:59:28.115214 <6>[ 0.127859] smp: Brought up 1 node, 8 CPUs
10450 13:59:28.121952 <6>[ 0.127864] SMP: Total of 8 processors activated.
10451 13:59:28.129139 <6>[ 0.127867] CPU features: detected: 32-bit EL0 Support
10452 13:59:28.135469 <6>[ 0.127869] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10453 13:59:28.141966 <6>[ 0.127871] CPU features: detected: Common not Private translations
10454 13:59:28.148528 <6>[ 0.127873] CPU features: detected: CRC32 instructions
10455 13:59:28.155060 <6>[ 0.127875] CPU features: detected: RCpc load-acquire (LDAPR)
10456 13:59:28.158203 <6>[ 0.127877] CPU features: detected: LSE atomic instructions
10457 13:59:28.164351 <6>[ 0.127879] CPU features: detected: Privileged Access Never
10458 13:59:28.170942 <6>[ 0.127880] CPU features: detected: RAS Extension Support
10459 13:59:28.178482 <6>[ 0.127883] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10460 13:59:28.181371 <6>[ 0.127951] CPU: All CPU(s) started at EL2
10461 13:59:28.187801 <6>[ 0.127952] alternatives: applying system-wide alternatives
10462 13:59:28.191105 <6>[ 0.141026] devtmpfs: initialized
10463 13:59:28.201077 <6>[ 0.147226] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10464 13:59:28.229898 �%���ѕɕ���}%9Q��ɽѽ����2�����5S�<6>[ 0.36429<2] printk: console [ttyS0] printing thread started
10465 13:59:28.236449 6>[ <6>[ 0.364333] printk: console [ttyS0] enabled
10466 13:59:28.242963 0.228673] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10467 13:59:28.251211 <6>[ 0.364339] printk: bootconsole [mtk8250] disabled
10468 13:59:28.258071 <6>[ 0.382406] printk: bootconsole [mtk8250] printing thread stopped
10469 13:59:28.261153 <6>[ 0.383706] SuperH (H)SCI(F) driver initialized
10470 13:59:28.267795 <6>[ 0.384188] msm_serial: driver initialized
10471 13:59:28.274285 <6>[ 0.388825] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10472 13:59:28.284172 <6>[ 0.388854] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10473 13:59:28.295786 <6>[ 0.388883] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10474 13:59:28.300758 <6>[ 0.388912] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10475 13:59:28.311111 <6>[ 0.388933] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10476 13:59:28.319475 <6>[ 0.388960] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10477 13:59:28.339787 <6>[ 0.388988] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10478 13:59:28.340386 <6>[ 0.389098] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10479 13:59:28.348149 <6>[ 0.389127] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10480 13:59:28.348745 <6>[ 0.400312] loop: module loaded
10481 13:59:28.356403 <6>[ 0.402937] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10482 13:59:28.361423 <4>[ 0.420010] mtk-pmic-keys: Failed to locate of_node [id: -1]
10483 13:59:28.364407 <6>[ 0.421018] megasas: 07.719.03.00-rc1
10484 13:59:28.371117 <6>[ 0.432896] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10485 13:59:28.374621 <6>[ 0.433020] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10486 13:59:28.381172 <6>[ 0.444970] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10487 13:59:28.394404 <6>[ 0.505225] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10488 13:59:29.031320 <6>[ 1.162601] Freeing initrd memory: 20888K
10489 13:59:29.042895 <6>[ 1.174116] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10490 13:59:29.049117 <6>[ 1.178784] tun: Universal TUN/TAP device driver, 1.6
10491 13:59:29.052752 <6>[ 1.179538] thunder_xcv, ver 1.0
10492 13:59:29.056212 <6>[ 1.179555] thunder_bgx, ver 1.0
10493 13:59:29.059261 <6>[ 1.179584] nicpf, ver 1.0
10494 13:59:29.066074 <6>[ 1.180631] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10495 13:59:29.072683 <6>[ 1.180634] hns3: Copyright (c) 2017 Huawei Corporation.
10496 13:59:29.075678 <6>[ 1.180663] hclge is initializing
10497 13:59:29.082651 <6>[ 1.180678] e1000: Intel(R) PRO/1000 Network Driver
10498 13:59:29.086812 <6>[ 1.180680] e1000: Copyright (c) 1999-2006 Intel Corporation.
10499 13:59:29.093130 <6>[ 1.180698] e1000e: Intel(R) PRO/1000 Network Driver
10500 13:59:29.100249 <6>[ 1.180700] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10501 13:59:29.104331 <6>[ 1.180715] igb: Intel(R) Gigabit Ethernet Network Driver
10502 13:59:29.110610 <6>[ 1.180716] igb: Copyright (c) 2007-2014 Intel Corporation.
10503 13:59:29.117015 <6>[ 1.180730] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10504 13:59:29.124388 <6>[ 1.180732] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10505 13:59:29.127930 <6>[ 1.181029] sky2: driver version 1.30
10506 13:59:29.131091 <6>[ 1.182121] VFIO - User Level meta-driver version: 0.3
10507 13:59:29.137979 <6>[ 1.184974] usbcore: registered new interface driver usb-storage
10508 13:59:29.144578 <6>[ 1.185153] usbcore: registered new device driver onboard-usb-hub
10509 13:59:29.151505 <6>[ 1.187910] mt6397-rtc mt6359-rtc: registered as rtc0
10510 13:59:29.157646 <6>[ 1.188065] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-21T13:59:31 UTC (1695304771)
10511 13:59:29.164517 <6>[ 1.188687] i2c_dev: i2c /dev entries driver
10512 13:59:29.171174 <6>[ 1.195960] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10513 13:59:29.177495 <6>[ 1.210943] cpu cpu0: EM: created perf domain
10514 13:59:29.181646 <6>[ 1.211266] cpu cpu4: EM: created perf domain
10515 13:59:29.187826 <6>[ 1.215723] sdhci: Secure Digital Host Controller Interface driver
10516 13:59:29.191095 <6>[ 1.215724] sdhci: Copyright(c) Pierre Ossman
10517 13:59:29.197349 <6>[ 1.216079] Synopsys Designware Multimedia Card Interface Driver
10518 13:59:29.203825 <6>[ 1.216469] sdhci-pltfm: SDHCI platform and OF driver helper
10519 13:59:29.210723 <6>[ 1.220687] ledtrig-cpu: registered to indicate activity on CPUs
10520 13:59:29.214047 <6>[ 1.221365] mmc0: CQHCI version 5.10
10521 13:59:29.220632 <6>[ 1.221446] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10522 13:59:29.227175 <6>[ 1.221746] usbcore: registered new interface driver usbhid
10523 13:59:29.230597 <6>[ 1.221748] usbhid: USB HID core driver
10524 13:59:29.237419 <6>[ 1.221856] spi_master spi0: will run message pump with realtime priority
10525 13:59:29.251357 <6>[ 1.257018] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10526 13:59:29.264373 <6>[ 1.259298] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10527 13:59:29.269970 <6>[ 1.260303] cros-ec-spi spi0.0: Chrome EC device registered
10528 13:59:29.280377 <6>[ 1.281657] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10529 13:59:29.283274 <6>[ 1.284262] NET: Registered PF_PACKET protocol family
10530 13:59:29.290220 <6>[ 1.284363] 9pnet: Installing 9P2000 support
10531 13:59:29.293609 <5>[ 1.284406] Key type dns_resolver registered
10532 13:59:29.297300 <6>[ 1.284801] registered taskstats version 1
10533 13:59:29.303585 <5>[ 1.284823] Loading compiled-in X.509 certificates
10534 13:59:29.313203 <4>[ 1.300559] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10535 13:59:29.323097 <4>[ 1.300734] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10536 13:59:29.330030 <3>[ 1.300745] debugfs: File 'uA_load' in directory '/' already present!
10537 13:59:29.336563 <3>[ 1.300752] debugfs: File 'min_uV' in directory '/' already present!
10538 13:59:29.343994 <3>[ 1.300755] debugfs: File 'max_uV' in directory '/' already present!
10539 13:59:29.350106 <3>[ 1.300758] debugfs: File 'constraint_flags' in directory '/' already present!
10540 13:59:29.360118 <3>[ 1.302827] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10541 13:59:29.366540 <6>[ 1.309551] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10542 13:59:29.369727 <6>[ 1.310080] xhci-mtk 11200000.usb: xHCI Host Controller
10543 13:59:29.379467 <6>[ 1.310095] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10544 13:59:29.389356 <6>[ 1.310287] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10545 13:59:29.393139 <6>[ 1.310327] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10546 13:59:29.399320 <6>[ 1.310403] xhci-mtk 11200000.usb: xHCI Host Controller
10547 13:59:29.406038 <6>[ 1.310406] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10548 13:59:29.415714 <6>[ 1.310409] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10549 13:59:29.418898 <6>[ 1.311056] hub 1-0:1.0: USB hub found
10550 13:59:29.422516 <6>[ 1.311067] hub 1-0:1.0: 1 port detected
10551 13:59:29.432203 <6>[ 1.311161] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10552 13:59:29.436125 <6>[ 1.311286] hub 2-0:1.0: USB hub found
10553 13:59:29.439177 <6>[ 1.311292] hub 2-0:1.0: 1 port detected
10554 13:59:29.442850 <6>[ 1.314135] mtk-msdc 11f70000.mmc: Got CD GPIO
10555 13:59:29.448707 <6>[ 1.315599] mmc0: Command Queue Engine enabled
10556 13:59:29.455424 <6>[ 1.315613] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10557 13:59:29.459246 <6>[ 1.316579] mmcblk0: mmc0:0001 DA4128 116 GiB
10558 13:59:29.465828 <6>[ 1.321072] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10559 13:59:29.472401 <6>[ 1.323159] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10560 13:59:29.478790 <6>[ 1.323485] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10561 13:59:29.485279 <6>[ 1.323493] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10562 13:59:29.495121 <4>[ 1.323575] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10563 13:59:29.501565 <6>[ 1.324023] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10564 13:59:29.508304 <6>[ 1.324071] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10565 13:59:29.518614 <6>[ 1.324073] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10566 13:59:29.524437 <6>[ 1.324247] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10567 13:59:29.531874 <6>[ 1.324255] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10568 13:59:29.541378 <6>[ 1.324259] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10569 13:59:29.551246 <6>[ 1.324261] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10570 13:59:29.557531 <6>[ 1.325032] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10571 13:59:29.564117 <6>[ 1.325711] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10572 13:59:29.574489 <6>[ 1.325725] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10573 13:59:29.580735 <6>[ 1.325729] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10574 13:59:29.591342 <6>[ 1.325733] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10575 13:59:29.597621 <6>[ 1.325736] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10576 13:59:29.607642 <6>[ 1.325739] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10577 13:59:29.614334 <6>[ 1.325743] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10578 13:59:29.623842 <6>[ 1.325746] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10579 13:59:29.630561 <6>[ 1.325749] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10580 13:59:29.640242 <6>[ 1.325752] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10581 13:59:29.646913 <6>[ 1.325756] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10582 13:59:29.656564 <6>[ 1.325759] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10583 13:59:29.663205 <6>[ 1.325762] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10584 13:59:29.673232 <6>[ 1.325766] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10585 13:59:29.680144 <6>[ 1.325769] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10586 13:59:29.686474 <6>[ 1.326143] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10587 13:59:29.694160 <6>[ 1.326759] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10588 13:59:29.699484 <6>[ 1.326992] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10589 13:59:29.706298 <6>[ 1.327223] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10590 13:59:29.712482 <6>[ 1.327462] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10591 13:59:29.722938 <6>[ 1.327627] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10592 13:59:29.732372 <6>[ 1.327636] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10593 13:59:29.742557 <6>[ 1.327638] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10594 13:59:29.752255 <6>[ 1.327642] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10595 13:59:29.759277 <6>[ 1.327650] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10596 13:59:29.769120 <6>[ 1.327654] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10597 13:59:29.778933 <6>[ 1.327659] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10598 13:59:29.789164 <6>[ 1.327663] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10599 13:59:29.798761 <6>[ 1.327664] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10600 13:59:29.808518 <6>[ 1.327668] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10601 13:59:29.818302 <6>[ 1.327670] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10602 13:59:29.825474 <6>[ 1.328029] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10603 13:59:29.831674 <6>[ 1.701925] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10604 13:59:29.838457 <6>[ 1.728355] hub 2-1:1.0: USB hub found
10605 13:59:29.841230 <6>[ 1.728662] hub 2-1:1.0: 3 ports detected
10606 13:59:29.847999 <6>[ 1.857693] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10607 13:59:29.879081 <6>[ 2.010488] hub 1-1:1.0: USB hub found
10608 13:59:29.882228 <6>[ 2.010912] hub 1-1:1.0: 4 ports detected
10609 13:59:30.194290 <6>[ 2.321791] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10610 13:59:30.314886 <6>[ 2.448041] hub 1-1.1:1.0: USB hub found
10611 13:59:30.318007 <6>[ 2.448185] hub 1-1.1:1.0: 4 ports detected
10612 13:59:30.426462 <6>[ 2.553871] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10613 13:59:30.550897 <6>[ 2.681433] hub 1-1.4:1.0: USB hub found
10614 13:59:30.554373 <6>[ 2.681893] hub 1-1.4:1.0: 2 ports detected
10615 13:59:30.630208 <6>[ 2.757739] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10616 13:59:30.814698 <6>[ 2.941780] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10617 13:59:30.891079 <3>[ 3.021994] usb 1-1.1.4: device descriptor read/64, error -32
10618 13:59:31.079190 <3>[ 3.209990] usb 1-1.1.4: device descriptor read/64, error -32
10619 13:59:31.270463 <6>[ 3.397539] usb 1-1.1.4: new full-speed USB device number 7 using xhci-mtk
10620 13:59:31.347041 <3>[ 3.477905] usb 1-1.1.4: device descriptor read/64, error -32
10621 13:59:31.535478 <3>[ 3.665967] usb 1-1.1.4: device descriptor read/64, error -32
10622 13:59:31.642929 <6>[ 3.774297] usb 1-1.1-port4: attempt power cycle
10623 13:59:31.726375 <6>[ 3.853842] usb 1-1.4.1: new high-speed USB device number 8 using xhci-mtk
10624 13:59:31.910823 <6>[ 4.037791] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10625 13:59:32.298232 <6>[ 4.425547] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10626 13:59:32.304930 <4>[ 4.425751] usb 1-1.1.4: Device not responding to setup address.
10627 13:59:32.502827 <4>[ 4.634081] usb 1-1.1.4: Device not responding to setup address.
10628 13:59:32.710792 <3>[ 4.841779] usb 1-1.1.4: device not accepting address 10, error -71
10629 13:59:32.794459 <6>[ 4.921802] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10630 13:59:32.800396 <4>[ 4.922073] usb 1-1.1.4: Device not responding to setup address.
10631 13:59:32.999174 <4>[ 5.130088] usb 1-1.1.4: Device not responding to setup address.
10632 13:59:33.206966 <3>[ 5.337778] usb 1-1.1.4: device not accepting address 11, error -71
10633 13:59:33.213536 <3>[ 5.338349] usb 1-1.1-port4: unable to enumerate USB device
10634 13:59:41.498632 <6>[ 13.634864] ALSA device list:
10635 13:59:41.505588 <6>[ 13.634888] No soundcards found.
10636 13:59:41.508518 <6>[ 13.639453] Freeing unused kernel memory: 8448K
10637 13:59:41.511695 <6>[ 13.639630] Run /init as init process
10638 13:59:41.528121 Starting syslogd: OK
10639 13:59:41.532440 Starting klogd: OK
10640 13:59:41.541997 Running sysctl: OK
10641 13:59:41.554318 Populating /dev using udev: <30>[ 13.686010] udevd[200]: starting version 3.2.9
10642 13:59:41.561158 <27>[ 13.687503] udevd[200]: specified user 'tss' unknown
10643 13:59:41.564112 <27>[ 13.687520] udevd[200]: specified group 'tss' unknown
10644 13:59:41.570521 <30>[ 13.688358] udevd[201]: starting eudev-3.2.9
10645 13:59:41.573678 <27>[ 13.705494] udevd[201]: specified user 'tss' unknown
10646 13:59:41.580224 <27>[ 13.705572] udevd[201]: specified group 'tss' unknown
10647 13:59:41.697222 <6>[ 13.828919] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10648 13:59:41.700133 <6>[ 13.837431] remoteproc remoteproc0: scp is available
10649 13:59:41.706939 <6>[ 13.841771] remoteproc remoteproc0: powering up scp
10650 13:59:41.717095 <6>[ 13.841786] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10651 13:59:41.720439 <6>[ 13.841830] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10652 13:59:41.729950 <6>[ 13.845429] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10653 13:59:41.736827 <6>[ 13.845830] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10654 13:59:41.746532 <6>[ 13.845839] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10655 13:59:41.753349 <6>[ 13.881012] usbcore: registered new interface driver r8152
10656 13:59:41.759711 <3>[ 13.888350] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 13:59:41.769912 <3>[ 13.888414] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 13:59:41.776095 <3>[ 13.888422] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 13:59:41.786194 <3>[ 13.889995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 13:59:41.792638 <3>[ 13.890020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 13:59:41.799892 <3>[ 13.890024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 13:59:41.810512 <3>[ 13.890029] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 13:59:41.820938 <3>[ 13.890033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 13:59:41.828035 <6>[ 13.893585] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10665 13:59:41.834603 <6>[ 13.893859] usbcore: registered new interface driver cdc_ether
10666 13:59:41.841459 <3>[ 13.898240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 13:59:41.851040 <3>[ 13.898398] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10668 13:59:41.857946 <3>[ 13.898408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 13:59:41.867976 <3>[ 13.898418] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10670 13:59:41.874715 <3>[ 13.898499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 13:59:41.884149 <3>[ 13.898507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 13:59:41.891367 <3>[ 13.898513] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10673 13:59:41.900928 <3>[ 13.898522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10674 13:59:41.907959 <3>[ 13.898529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10675 13:59:41.917335 <3>[ 13.898570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10676 13:59:41.920532 <6>[ 13.906200] mc: Linux media interface: v0.10
10677 13:59:41.927536 <6>[ 13.917064] usbcore: registered new interface driver r8153_ecm
10678 13:59:41.934449 <4>[ 13.922903] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10679 13:59:41.940730 <4>[ 13.922903] Fallback method does not support PEC.
10680 13:59:41.946942 <6>[ 13.930468] videodev: Linux video capture interface: v2.00
10681 13:59:41.950407 <6>[ 13.934648] Bluetooth: Core ver 2.22
10682 13:59:41.953910 <6>[ 13.934743] NET: Registered PF_BLUETOOTH protocol family
10683 13:59:41.960181 <6>[ 13.934744] Bluetooth: HCI device and connection manager initialized
10684 13:59:41.966729 <6>[ 13.934771] Bluetooth: HCI socket layer initialized
10685 13:59:41.973450 <6>[ 13.934777] Bluetooth: L2CAP socket layer initialized
10686 13:59:41.977165 <6>[ 13.934786] Bluetooth: SCO socket layer initialized
10687 13:59:41.983952 <4>[ 13.935360] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10688 13:59:41.993051 <4>[ 13.935513] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10689 13:59:41.999999 <3>[ 13.943106] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10690 13:59:42.006633 <6>[ 13.967230] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10691 13:59:42.013544 <6>[ 13.967293] pci_bus 0000:00: root bus resource [bus 00-ff]
10692 13:59:42.019966 <6>[ 13.967323] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10693 13:59:42.030128 <6>[ 13.967339] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10694 13:59:42.036503 <6>[ 13.967510] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10695 13:59:42.042586 <6>[ 13.967542] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10696 13:59:42.049474 <6>[ 13.967574] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10697 13:59:42.055957 <6>[ 13.967680] pci 0000:00:00.0: supports D1 D2
10698 13:59:42.062707 <6>[ 13.967683] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10699 13:59:42.069810 <6>[ 13.969365] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10700 13:59:42.075683 <6>[ 13.969382] remoteproc remoteproc0: remote processor scp is now up
10701 13:59:42.085663 <6>[ 13.969783] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10702 13:59:42.092221 <6>[ 13.970077] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10703 13:59:42.099130 <6>[ 13.970080] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10704 13:59:42.105417 <6>[ 13.970114] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10705 13:59:42.116591 <6>[ 13.970139] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10706 13:59:42.122245 <6>[ 13.970159] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10707 13:59:42.125684 <6>[ 13.970288] pci 0000:01:00.0: supports D1 D2
10708 13:59:42.131890 <6>[ 13.970291] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10709 13:59:42.141979 <3>[ 13.970495] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10710 13:59:42.148636 <6>[ 13.981631] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10711 13:59:42.155216 <6>[ 13.981677] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10712 13:59:42.164882 <6>[ 13.981684] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10713 13:59:42.171380 <6>[ 13.981698] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10714 13:59:42.181417 <6>[ 13.981714] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10715 13:59:42.188055 <6>[ 13.981730] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10716 13:59:42.194402 <6>[ 13.981747] pci 0000:00:00.0: PCI bridge to [bus 01]
10717 13:59:42.201141 <6>[ 13.981771] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10718 13:59:42.208028 <6>[ 13.982060] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10719 13:59:42.214180 <6>[ 13.993766] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10720 13:59:42.221267 <6>[ 13.994145] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10721 13:59:42.227423 <6>[ 14.040809] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10722 13:59:42.240857 <6>[ 14.045885] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10723 13:59:42.248095 <6>[ 14.046142] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10724 13:59:42.257620 <6>[ 14.058638] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10725 13:59:42.263952 <6>[ 14.061070] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10726 13:59:42.273870 <5>[ 14.063334] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10727 13:59:42.280239 <4>[ 14.072403] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10728 13:59:42.290452 <4>[ 14.072413] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10729 13:59:42.296961 <5>[ 14.088661] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10730 13:59:42.306812 <4>[ 14.088715] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10731 13:59:42.310216 <6>[ 14.088721] cfg80211: failed to load regulatory.db
10732 13:59:42.316563 <6>[ 14.098666] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10733 13:59:42.323977 <6>[ 14.098673] usbcore: registered new interface driver btusb
10734 13:59:42.334271 <4>[ 14.099700] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10735 13:59:42.340424 <3>[ 14.099742] Bluetooth: hci0: Failed to load firmware file (-2)
10736 13:59:42.346397 <3>[ 14.099757] Bluetooth: hci0: Failed to set up firmware (-2)
10737 13:59:42.356342 <4>[ 14.099770] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10738 13:59:42.370624 <6>[ 14.101055] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10739 13:59:42.376642 <6>[ 14.101316] usbcore: registered new interface driver uvcvideo
10740 13:59:42.382670 <6>[ 14.119208] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10741 13:59:42.386186 <6>[ 14.121633] r8152 1-1.1.1:1.0 eth0: v1.12.13
10742 13:59:42.392531 <6>[ 14.180583] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10743 13:59:42.399777 <6>[ 14.180682] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10744 13:59:42.405718 <6>[ 14.197570] mt7921e 0000:01:00.0: ASIC revision: 79610010
10745 13:59:42.415965 <4>[ 14.296418] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10746 13:59:42.429384 <4>[ 14.403299] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10747 13:59:42.438996 <4>[ 14.510946] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10748 13:59:42.447609 done
10749 13:59:42.459695 Saving random seed: OK
10750 13:59:42.488322 Starting network: <4>[ 14.616727] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10751 13:59:42.488918 OK
10752 13:59:42.538005 Starting dropbear sshd: <6>[ 14.670841] NET: Registered PF_INET6 protocol family
10753 13:59:42.541079 <6>[ 14.672010] Segment Routing with IPv6
10754 13:59:42.544359 <6>[ 14.672022] In-situ OAM (IOAM) with IPv6
10755 13:59:42.547333 OK
10756 13:59:42.557716 /bin/sh: can't access tty; job control turned off
10757 13:59:42.558901 Matched prompt #10: / #
10759 13:59:42.560383 Setting prompt string to ['/ #']
10760 13:59:42.560868 end: 2.2.5.1 login-action (duration 00:00:15) [common]
10762 13:59:42.561976 end: 2.2.5 auto-login-action (duration 00:00:16) [common]
10763 13:59:42.562463 start: 2.2.6 expect-shell-connection (timeout 00:03:48) [common]
10764 13:59:42.562864 Setting prompt string to ['/ #']
10765 13:59:42.563200 Forcing a shell prompt, looking for ['/ #']
10767 13:59:42.614251 / #
10768 13:59:42.614906 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10769 13:59:42.615331 Waiting using forced prompt support (timeout 00:02:30)
10770 13:59:42.615880 <4>[ 14.724234] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 13:59:42.620976
10772 13:59:42.621946 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10773 13:59:42.622471 start: 2.2.7 export-device-env (timeout 00:03:48) [common]
10774 13:59:42.622994 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10775 13:59:42.623482 end: 2.2 depthcharge-retry (duration 00:01:12) [common]
10776 13:59:42.624050 end: 2 depthcharge-action (duration 00:01:12) [common]
10777 13:59:42.624519 start: 3 lava-test-retry (timeout 00:01:00) [common]
10778 13:59:42.624991 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10779 13:59:42.625396 Using namespace: common
10781 13:59:42.726681 / # #
10782 13:59:42.727324 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10783 13:59:42.727971 #<4>[ 14.832216] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 13:59:42.733594
10785 13:59:42.734475 Using /lava-11588086
10787 13:59:42.835671 / # export SHELL=/bin/sh
10788 13:59:42.836440 export SHELL=/bin/sh<4>[ 14.940476] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10789 13:59:42.842679
10791 13:59:42.944523 / # . /lava-11588086/environment
10792 13:59:42.945305 . /lava-11588086/environment<4>[ 15.048663] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 13:59:42.951020
10795 13:59:43.052920 / # /lava-11588086/bin/lava-test-runner /lava-11588086/0
10796 13:59:43.053543 Test shell timeout: 10s (minimum of the action and connection timeout)
10797 13:59:43.055181 /lava-11588086/bin/lava-test-runner /lava-11588086/0<4>[ 15.156587] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10798 13:59:43.059830
10799 13:59:43.100221 + export 'TESTRUN_ID=0_dmesg'
10800 13:59:43.100778 +<8>[ 15.220980] <LAVA_SIGNAL_STARTRUN 0_dmesg 11588086_1.5.2.3.1>
10801 13:59:43.101156 cd /lava-11588086/0/tests/0_dmesg
10802 13:59:43.101495 + cat uuid
10803 13:59:43.102119 Received signal: <STARTRUN> 0_dmesg 11588086_1.5.2.3.1
10804 13:59:43.102503 Starting test lava.0_dmesg (11588086_1.5.2.3.1)
10805 13:59:43.102937 Skipping test definition patterns.
10806 13:59:43.103462 + UUID=11588086_1.5.2.3.1
10807 13:59:43.103876 + set<8>[ 15.231922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10808 13:59:43.104218 +x
10809 13:59:43.104808 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10811 13:59:43.112960 + KERNELCI_<8>[ 15.242634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10812 13:59:43.113822 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10814 13:59:43.115489 LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10815 13:59:43.124461 + set +x
10816 13:59:43.135157 <LAVA_TEST_RUNNE<8>[ 15.262112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10817 13:59:43.136061 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10819 13:59:43.141372 <8>[ 15.263845] <LAVA_SIGNAL_ENDRUN 0_dmesg 11588086_1.5.2.3.1>
10820 13:59:43.142224 Received signal: <ENDRUN> 0_dmesg 11588086_1.5.2.3.1
10821 13:59:43.142679 Ending use of test pattern.
10822 13:59:43.143038 Ending test lava.0_dmesg (11588086_1.5.2.3.1), duration 0.04
10824 13:59:43.150907 <4>[ 15.265173] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10825 13:59:43.151483 R EXIT>
10826 13:59:43.233713 / # <3>[ 15.366117] mt7921e 0000:01:00.0: hardware init failed
10827 14:00:11.894864 <6>[ 44.034136] vpu: disabling
10828 14:00:11.898332 <6>[ 44.034271] vproc2: disabling
10829 14:00:11.901513 <6>[ 44.034330] vproc1: disabling
10830 14:00:11.904833 <6>[ 44.034390] vaud18: disabling
10831 14:00:11.911311 <6>[ 44.034663] vsram_others: disabling
10832 14:00:11.911838 <6>[ 44.034861] va09: disabling
10833 14:00:11.915083 <6>[ 44.034944] vsram_md: disabling
10834 14:00:11.917941 <6>[ 44.035086] Vgpu: disabling
10836 14:00:42.626039 end: 3.1 lava-test-shell (duration 00:01:00) [common]
10838 14:00:42.627070 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10840 14:00:42.627956 end: 3 lava-test-retry (duration 00:01:00) [common]
10842 14:00:42.629145 Cleaning after the job
10843 14:00:42.629639 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/ramdisk
10844 14:00:42.633161 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/kernel
10845 14:00:42.645925 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/dtb
10846 14:00:42.646097 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588086/tftp-deploy-69elt4hq/modules
10847 14:00:42.653346 start: 5.1 power-off (timeout 00:00:30) [common]
10848 14:00:42.653510 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
10849 14:00:42.733692 >> Command sent successfully.
10850 14:00:42.739020 Returned 0 in 0 seconds
10851 14:00:42.840088 end: 5.1 power-off (duration 00:00:00) [common]
10853 14:00:42.841642 start: 5.2 read-feedback (timeout 00:10:00) [common]
10854 14:00:42.842962 Listened to connection for namespace 'common' for up to 1s
10855 14:00:43.843562 Finalising connection for namespace 'common'
10856 14:00:43.844303 Disconnecting from shell: Finalise
10857 14:00:43.945419 end: 5.2 read-feedback (duration 00:00:01) [common]
10858 14:00:43.946063 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11588086
10859 14:00:44.041578 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11588086
10860 14:00:44.041779 TestError: A test failed to run, look at the error message.