Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 37
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 24
1 13:57:29.299090 lava-dispatcher, installed at version: 2023.06
2 13:57:29.299318 start: 0 validate
3 13:57:29.299519 Start time: 2023-09-21 13:57:29.299512+00:00 (UTC)
4 13:57:29.299663 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:57:29.299808 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 13:57:29.567175 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:57:29.567629 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:58:22.353819 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:58:22.354548 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:58:22.625943 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:58:22.626622 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:58:23.156461 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:58:23.157151 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:58:25.666296 validate duration: 56.37
16 13:58:25.666555 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:58:25.666654 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:58:25.666737 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:58:25.666864 Not decompressing ramdisk as can be used compressed.
20 13:58:25.666949 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 13:58:25.667011 saving as /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/ramdisk/initrd.cpio.gz
22 13:58:25.667077 total size: 4665412 (4 MB)
23 13:58:25.932958 progress 0 % (0 MB)
24 13:58:25.934481 progress 5 % (0 MB)
25 13:58:25.935776 progress 10 % (0 MB)
26 13:58:25.937033 progress 15 % (0 MB)
27 13:58:25.938298 progress 20 % (0 MB)
28 13:58:25.939543 progress 25 % (1 MB)
29 13:58:25.940787 progress 30 % (1 MB)
30 13:58:25.942021 progress 35 % (1 MB)
31 13:58:25.943246 progress 40 % (1 MB)
32 13:58:25.944646 progress 45 % (2 MB)
33 13:58:25.945910 progress 50 % (2 MB)
34 13:58:25.947137 progress 55 % (2 MB)
35 13:58:25.948366 progress 60 % (2 MB)
36 13:58:25.949590 progress 65 % (2 MB)
37 13:58:25.950812 progress 70 % (3 MB)
38 13:58:25.952081 progress 75 % (3 MB)
39 13:58:25.953311 progress 80 % (3 MB)
40 13:58:25.954703 progress 85 % (3 MB)
41 13:58:25.955972 progress 90 % (4 MB)
42 13:58:25.957198 progress 95 % (4 MB)
43 13:58:25.958454 progress 100 % (4 MB)
44 13:58:25.958609 4 MB downloaded in 0.29 s (15.26 MB/s)
45 13:58:25.958761 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:58:25.958999 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:58:25.959085 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:58:25.959169 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:58:25.959305 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:58:25.959376 saving as /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/kernel/Image
52 13:58:25.959483 total size: 49304064 (47 MB)
53 13:58:25.959544 No compression specified
54 13:58:25.960657 progress 0 % (0 MB)
55 13:58:25.973433 progress 5 % (2 MB)
56 13:58:25.986278 progress 10 % (4 MB)
57 13:58:25.999346 progress 15 % (7 MB)
58 13:58:26.012397 progress 20 % (9 MB)
59 13:58:26.025581 progress 25 % (11 MB)
60 13:58:26.038292 progress 30 % (14 MB)
61 13:58:26.050953 progress 35 % (16 MB)
62 13:58:26.063738 progress 40 % (18 MB)
63 13:58:26.076595 progress 45 % (21 MB)
64 13:58:26.089342 progress 50 % (23 MB)
65 13:58:26.102423 progress 55 % (25 MB)
66 13:58:26.116130 progress 60 % (28 MB)
67 13:58:26.130175 progress 65 % (30 MB)
68 13:58:26.143988 progress 70 % (32 MB)
69 13:58:26.158044 progress 75 % (35 MB)
70 13:58:26.171855 progress 80 % (37 MB)
71 13:58:26.185747 progress 85 % (39 MB)
72 13:58:26.199800 progress 90 % (42 MB)
73 13:58:26.213408 progress 95 % (44 MB)
74 13:58:26.226957 progress 100 % (47 MB)
75 13:58:26.227210 47 MB downloaded in 0.27 s (175.63 MB/s)
76 13:58:26.227368 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:58:26.227768 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:58:26.227876 start: 1.3 download-retry (timeout 00:09:59) [common]
80 13:58:26.227967 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 13:58:26.228115 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:58:26.228186 saving as /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/dtb/mt8192-asurada-spherion-r0.dtb
83 13:58:26.228248 total size: 47278 (0 MB)
84 13:58:26.228311 No compression specified
85 13:58:26.229461 progress 69 % (0 MB)
86 13:58:26.229746 progress 100 % (0 MB)
87 13:58:26.229971 0 MB downloaded in 0.00 s (26.21 MB/s)
88 13:58:26.230095 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:58:26.230324 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:58:26.230409 start: 1.4 download-retry (timeout 00:09:59) [common]
92 13:58:26.230490 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 13:58:26.230604 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 13:58:26.230671 saving as /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/nfsrootfs/full.rootfs.tar
95 13:58:26.230731 total size: 125290964 (119 MB)
96 13:58:26.230792 Using unxz to decompress xz
97 13:58:26.234931 progress 0 % (0 MB)
98 13:58:26.560223 progress 5 % (6 MB)
99 13:58:26.891861 progress 10 % (11 MB)
100 13:58:27.226487 progress 15 % (17 MB)
101 13:58:27.412681 progress 20 % (23 MB)
102 13:58:27.591840 progress 25 % (29 MB)
103 13:58:27.941510 progress 30 % (35 MB)
104 13:58:28.302212 progress 35 % (41 MB)
105 13:58:28.706172 progress 40 % (47 MB)
106 13:58:29.091943 progress 45 % (53 MB)
107 13:58:29.489641 progress 50 % (59 MB)
108 13:58:29.847248 progress 55 % (65 MB)
109 13:58:30.219664 progress 60 % (71 MB)
110 13:58:30.569328 progress 65 % (77 MB)
111 13:58:30.938565 progress 70 % (83 MB)
112 13:58:31.331815 progress 75 % (89 MB)
113 13:58:31.749547 progress 80 % (95 MB)
114 13:58:32.165152 progress 85 % (101 MB)
115 13:58:32.408143 progress 90 % (107 MB)
116 13:58:32.746510 progress 95 % (113 MB)
117 13:58:33.121554 progress 100 % (119 MB)
118 13:58:33.127320 119 MB downloaded in 6.90 s (17.33 MB/s)
119 13:58:33.127688 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:58:33.127957 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:58:33.128046 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:58:33.128133 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:58:33.128270 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:58:33.128341 saving as /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/modules/modules.tar
126 13:58:33.128401 total size: 8629568 (8 MB)
127 13:58:33.128482 Using unxz to decompress xz
128 13:58:33.397608 progress 0 % (0 MB)
129 13:58:33.419476 progress 5 % (0 MB)
130 13:58:33.441605 progress 10 % (0 MB)
131 13:58:33.467678 progress 15 % (1 MB)
132 13:58:33.493381 progress 20 % (1 MB)
133 13:58:33.519301 progress 25 % (2 MB)
134 13:58:33.547703 progress 30 % (2 MB)
135 13:58:33.572672 progress 35 % (2 MB)
136 13:58:33.598069 progress 40 % (3 MB)
137 13:58:33.622547 progress 45 % (3 MB)
138 13:58:33.649121 progress 50 % (4 MB)
139 13:58:33.675265 progress 55 % (4 MB)
140 13:58:33.702274 progress 60 % (4 MB)
141 13:58:33.726785 progress 65 % (5 MB)
142 13:58:33.753314 progress 70 % (5 MB)
143 13:58:33.779357 progress 75 % (6 MB)
144 13:58:33.807706 progress 80 % (6 MB)
145 13:58:33.838539 progress 85 % (7 MB)
146 13:58:33.869604 progress 90 % (7 MB)
147 13:58:33.895423 progress 95 % (7 MB)
148 13:58:33.920635 progress 100 % (8 MB)
149 13:58:33.926097 8 MB downloaded in 0.80 s (10.32 MB/s)
150 13:58:33.926480 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:58:33.926884 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:58:33.927020 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 13:58:33.927159 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 13:58:36.109671 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11588090/extract-nfsrootfs-oq143gd7
156 13:58:36.109875 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 13:58:36.109974 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 13:58:36.110137 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn
159 13:58:36.110270 makedir: /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin
160 13:58:36.110377 makedir: /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/tests
161 13:58:36.110477 makedir: /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/results
162 13:58:36.110577 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-add-keys
163 13:58:36.110721 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-add-sources
164 13:58:36.110853 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-background-process-start
165 13:58:36.110983 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-background-process-stop
166 13:58:36.111114 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-common-functions
167 13:58:36.111241 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-echo-ipv4
168 13:58:36.111367 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-install-packages
169 13:58:36.111744 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-installed-packages
170 13:58:36.111872 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-os-build
171 13:58:36.112001 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-probe-channel
172 13:58:36.112127 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-probe-ip
173 13:58:36.112253 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-target-ip
174 13:58:36.112379 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-target-mac
175 13:58:36.112503 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-target-storage
176 13:58:36.112631 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-test-case
177 13:58:36.112757 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-test-event
178 13:58:36.112881 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-test-feedback
179 13:58:36.113005 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-test-raise
180 13:58:36.113129 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-test-reference
181 13:58:36.113253 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-test-runner
182 13:58:36.113377 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-test-set
183 13:58:36.113503 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-test-shell
184 13:58:36.113631 Updating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-install-packages (oe)
185 13:58:36.113787 Updating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/bin/lava-installed-packages (oe)
186 13:58:36.113912 Creating /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/environment
187 13:58:36.114009 LAVA metadata
188 13:58:36.114081 - LAVA_JOB_ID=11588090
189 13:58:36.114143 - LAVA_DISPATCHER_IP=192.168.201.1
190 13:58:36.114246 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 13:58:36.114313 skipped lava-vland-overlay
192 13:58:36.114387 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 13:58:36.114467 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 13:58:36.114527 skipped lava-multinode-overlay
195 13:58:36.114600 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 13:58:36.114680 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 13:58:36.114754 Loading test definitions
198 13:58:36.114842 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 13:58:36.114913 Using /lava-11588090 at stage 0
200 13:58:36.115249 uuid=11588090_1.6.2.3.1 testdef=None
201 13:58:36.115340 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 13:58:36.115456 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 13:58:36.115981 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 13:58:36.116200 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 13:58:36.116832 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 13:58:36.117060 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 13:58:36.117678 runner path: /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/0/tests/0_dmesg test_uuid 11588090_1.6.2.3.1
210 13:58:36.117835 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 13:58:36.118059 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 13:58:36.118132 Using /lava-11588090 at stage 1
214 13:58:36.118434 uuid=11588090_1.6.2.3.5 testdef=None
215 13:58:36.118523 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 13:58:36.118608 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 13:58:36.119075 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 13:58:36.119289 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 13:58:36.119936 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 13:58:36.120163 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 13:58:36.120787 runner path: /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/1/tests/1_bootrr test_uuid 11588090_1.6.2.3.5
224 13:58:36.120941 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 13:58:36.121144 Creating lava-test-runner.conf files
227 13:58:36.121209 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/0 for stage 0
228 13:58:36.121300 - 0_dmesg
229 13:58:36.121380 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11588090/lava-overlay-uz0r6dgn/lava-11588090/1 for stage 1
230 13:58:36.121472 - 1_bootrr
231 13:58:36.121567 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 13:58:36.121653 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 13:58:36.129139 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 13:58:36.129285 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 13:58:36.129376 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 13:58:36.129465 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 13:58:36.129550 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 13:58:36.250959 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 13:58:36.251356 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 13:58:36.251517 extracting modules file /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11588090/extract-nfsrootfs-oq143gd7
241 13:58:36.477400 extracting modules file /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11588090/extract-overlay-ramdisk-3ku4y11t/ramdisk
242 13:58:36.708846 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 13:58:36.709043 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 13:58:36.709141 [common] Applying overlay to NFS
245 13:58:36.709216 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11588090/compress-overlay-1_6osrow/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11588090/extract-nfsrootfs-oq143gd7
246 13:58:36.717646 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 13:58:36.717792 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 13:58:36.717884 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 13:58:36.717970 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 13:58:36.718055 Building ramdisk /var/lib/lava/dispatcher/tmp/11588090/extract-overlay-ramdisk-3ku4y11t/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11588090/extract-overlay-ramdisk-3ku4y11t/ramdisk
251 13:58:37.021462 >> 119356 blocks
252 13:58:38.993314 rename /var/lib/lava/dispatcher/tmp/11588090/extract-overlay-ramdisk-3ku4y11t/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/ramdisk/ramdisk.cpio.gz
253 13:58:38.993781 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 13:58:38.993904 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 13:58:38.994010 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 13:58:38.994123 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/kernel/Image'
257 13:58:52.121382 Returned 0 in 13 seconds
258 13:58:52.222220 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/kernel/image.itb
259 13:58:52.592360 output: FIT description: Kernel Image image with one or more FDT blobs
260 13:58:52.592748 output: Created: Thu Sep 21 14:58:52 2023
261 13:58:52.592823 output: Image 0 (kernel-1)
262 13:58:52.592890 output: Description:
263 13:58:52.592954 output: Created: Thu Sep 21 14:58:52 2023
264 13:58:52.593017 output: Type: Kernel Image
265 13:58:52.593078 output: Compression: lzma compressed
266 13:58:52.593140 output: Data Size: 11044874 Bytes = 10786.01 KiB = 10.53 MiB
267 13:58:52.593201 output: Architecture: AArch64
268 13:58:52.593261 output: OS: Linux
269 13:58:52.593317 output: Load Address: 0x00000000
270 13:58:52.593371 output: Entry Point: 0x00000000
271 13:58:52.593423 output: Hash algo: crc32
272 13:58:52.593476 output: Hash value: a5f1a0d7
273 13:58:52.593529 output: Image 1 (fdt-1)
274 13:58:52.593582 output: Description: mt8192-asurada-spherion-r0
275 13:58:52.593634 output: Created: Thu Sep 21 14:58:52 2023
276 13:58:52.593688 output: Type: Flat Device Tree
277 13:58:52.593740 output: Compression: uncompressed
278 13:58:52.593793 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 13:58:52.593845 output: Architecture: AArch64
280 13:58:52.593898 output: Hash algo: crc32
281 13:58:52.593951 output: Hash value: cc4352de
282 13:58:52.594003 output: Image 2 (ramdisk-1)
283 13:58:52.594055 output: Description: unavailable
284 13:58:52.594106 output: Created: Thu Sep 21 14:58:52 2023
285 13:58:52.594160 output: Type: RAMDisk Image
286 13:58:52.594212 output: Compression: Unknown Compression
287 13:58:52.594265 output: Data Size: 17788363 Bytes = 17371.45 KiB = 16.96 MiB
288 13:58:52.594318 output: Architecture: AArch64
289 13:58:52.594371 output: OS: Linux
290 13:58:52.594423 output: Load Address: unavailable
291 13:58:52.594476 output: Entry Point: unavailable
292 13:58:52.594529 output: Hash algo: crc32
293 13:58:52.594581 output: Hash value: 8fbc098e
294 13:58:52.594633 output: Default Configuration: 'conf-1'
295 13:58:52.594685 output: Configuration 0 (conf-1)
296 13:58:52.594737 output: Description: mt8192-asurada-spherion-r0
297 13:58:52.594790 output: Kernel: kernel-1
298 13:58:52.594842 output: Init Ramdisk: ramdisk-1
299 13:58:52.594894 output: FDT: fdt-1
300 13:58:52.594946 output: Loadables: kernel-1
301 13:58:52.594998 output:
302 13:58:52.595214 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
303 13:58:52.595314 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
304 13:58:52.595429 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
305 13:58:52.595533 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
306 13:58:52.595618 No LXC device requested
307 13:58:52.595698 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 13:58:52.595783 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
309 13:58:52.595863 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 13:58:52.595933 Checking files for TFTP limit of 4294967296 bytes.
311 13:58:52.596441 end: 1 tftp-deploy (duration 00:00:27) [common]
312 13:58:52.596547 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 13:58:52.596643 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 13:58:52.596771 substitutions:
315 13:58:52.596838 - {DTB}: 11588090/tftp-deploy-mrsx7v69/dtb/mt8192-asurada-spherion-r0.dtb
316 13:58:52.596905 - {INITRD}: 11588090/tftp-deploy-mrsx7v69/ramdisk/ramdisk.cpio.gz
317 13:58:52.596964 - {KERNEL}: 11588090/tftp-deploy-mrsx7v69/kernel/Image
318 13:58:52.597021 - {LAVA_MAC}: None
319 13:58:52.597078 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11588090/extract-nfsrootfs-oq143gd7
320 13:58:52.597135 - {NFS_SERVER_IP}: 192.168.201.1
321 13:58:52.597189 - {PRESEED_CONFIG}: None
322 13:58:52.597243 - {PRESEED_LOCAL}: None
323 13:58:52.597298 - {RAMDISK}: 11588090/tftp-deploy-mrsx7v69/ramdisk/ramdisk.cpio.gz
324 13:58:52.597352 - {ROOT_PART}: None
325 13:58:52.597406 - {ROOT}: None
326 13:58:52.597460 - {SERVER_IP}: 192.168.201.1
327 13:58:52.597514 - {TEE}: None
328 13:58:52.597568 Parsed boot commands:
329 13:58:52.597621 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 13:58:52.597807 Parsed boot commands: tftpboot 192.168.201.1 11588090/tftp-deploy-mrsx7v69/kernel/image.itb 11588090/tftp-deploy-mrsx7v69/kernel/cmdline
331 13:58:52.597895 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 13:58:52.597983 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 13:58:52.598082 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 13:58:52.598169 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 13:58:52.598241 Not connected, no need to disconnect.
336 13:58:52.598315 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 13:58:52.598399 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 13:58:52.598465 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
339 13:58:52.602390 Setting prompt string to ['lava-test: # ']
340 13:58:52.602767 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 13:58:52.602878 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 13:58:52.602978 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 13:58:52.603069 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 13:58:52.603315 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
345 13:58:57.745189 >> Command sent successfully.
346 13:58:57.756654 Returned 0 in 5 seconds
347 13:58:57.857973 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 13:58:57.859432 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 13:58:57.859977 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 13:58:57.860452 Setting prompt string to 'Starting depthcharge on Spherion...'
352 13:58:57.860817 Changing prompt to 'Starting depthcharge on Spherion...'
353 13:58:57.861181 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 13:58:57.862433 [Enter `^Ec?' for help]
355 13:58:58.023032
356 13:58:58.023631
357 13:58:58.023999 F0: 102B 0000
358 13:58:58.024319
359 13:58:58.024624 F3: 1001 0000 [0200]
360 13:58:58.024928
361 13:58:58.026529 F3: 1001 0000
362 13:58:58.026959
363 13:58:58.027300 F7: 102D 0000
364 13:58:58.027698
365 13:58:58.028013 F1: 0000 0000
366 13:58:58.028316
367 13:58:58.030666 V0: 0000 0000 [0001]
368 13:58:58.031259
369 13:58:58.031701 00: 0007 8000
370 13:58:58.032128
371 13:58:58.033753 01: 0000 0000
372 13:58:58.034391
373 13:58:58.034815 BP: 0C00 0209 [0000]
374 13:58:58.035185
375 13:58:58.037699 G0: 1182 0000
376 13:58:58.038358
377 13:58:58.038916 EC: 0000 0021 [4000]
378 13:58:58.039334
379 13:58:58.041358 S7: 0000 0000 [0000]
380 13:58:58.041878
381 13:58:58.042396 CC: 0000 0000 [0001]
382 13:58:58.042809
383 13:58:58.044673 T0: 0000 0040 [010F]
384 13:58:58.045138
385 13:58:58.045491 Jump to BL
386 13:58:58.045808
387 13:58:58.069856
388 13:58:58.070420
389 13:58:58.070899
390 13:58:58.076921 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 13:58:58.080577 ARM64: Exception handlers installed.
392 13:58:58.084425 ARM64: Testing exception
393 13:58:58.088026 ARM64: Done test exception
394 13:58:58.095243 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 13:58:58.102459 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 13:58:58.109929 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 13:58:58.120666 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 13:58:58.127632 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 13:58:58.137115 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 13:58:58.147741 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 13:58:58.154432 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 13:58:58.172520 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 13:58:58.175704 WDT: Last reset was cold boot
404 13:58:58.179861 SPI1(PAD0) initialized at 2873684 Hz
405 13:58:58.182501 SPI5(PAD0) initialized at 992727 Hz
406 13:58:58.185840 VBOOT: Loading verstage.
407 13:58:58.192608 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 13:58:58.195945 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 13:58:58.199536 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 13:58:58.202933 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 13:58:58.210556 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 13:58:58.216515 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 13:58:58.227189 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 13:58:58.227722
415 13:58:58.228103
416 13:58:58.237316 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 13:58:58.240861 ARM64: Exception handlers installed.
418 13:58:58.243845 ARM64: Testing exception
419 13:58:58.244274 ARM64: Done test exception
420 13:58:58.250807 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 13:58:58.254299 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 13:58:58.268671 Probing TPM: . done!
423 13:58:58.269107 TPM ready after 0 ms
424 13:58:58.275206 Connected to device vid:did:rid of 1ae0:0028:00
425 13:58:58.282015 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 13:58:58.322993 Initialized TPM device CR50 revision 0
427 13:58:58.335061 tlcl_send_startup: Startup return code is 0
428 13:58:58.335555 TPM: setup succeeded
429 13:58:58.345880 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 13:58:58.354320 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 13:58:58.367296 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 13:58:58.375436 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 13:58:58.378339 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 13:58:58.382123 in-header: 03 07 00 00 08 00 00 00
435 13:58:58.385898 in-data: aa e4 47 04 13 02 00 00
436 13:58:58.389562 Chrome EC: UHEPI supported
437 13:58:58.396587 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 13:58:58.400005 in-header: 03 9d 00 00 08 00 00 00
439 13:58:58.404192 in-data: 10 20 20 08 00 00 00 00
440 13:58:58.404621 Phase 1
441 13:58:58.407454 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 13:58:58.414884 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 13:58:58.422287 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 13:58:58.422721 Recovery requested (1009000e)
445 13:58:58.431026 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 13:58:58.436751 tlcl_extend: response is 0
447 13:58:58.444909 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 13:58:58.450093 tlcl_extend: response is 0
449 13:58:58.456565 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 13:58:58.478095 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 13:58:58.484883 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 13:58:58.485362
453 13:58:58.485741
454 13:58:58.492575 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 13:58:58.496246 ARM64: Exception handlers installed.
456 13:58:58.499880 ARM64: Testing exception
457 13:58:58.502979 ARM64: Done test exception
458 13:58:58.523484 pmic_efuse_setting: Set efuses in 11 msecs
459 13:58:58.526933 pmwrap_interface_init: Select PMIF_VLD_RDY
460 13:58:58.531254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 13:58:58.538385 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 13:58:58.541929 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 13:58:58.545509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 13:58:58.552846 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 13:58:58.555950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 13:58:58.559519 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 13:58:58.566991 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 13:58:58.570355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 13:58:58.573609 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 13:58:58.580379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 13:58:58.583941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 13:58:58.586809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 13:58:58.594136 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 13:58:58.601110 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 13:58:58.607485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 13:58:58.610838 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 13:58:58.617536 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 13:58:58.625338 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 13:58:58.628979 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 13:58:58.636222 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 13:58:58.640192 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 13:58:58.647203 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 13:58:58.650260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 13:58:58.657636 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 13:58:58.661085 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 13:58:58.667228 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 13:58:58.670540 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 13:58:58.677650 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 13:58:58.681646 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 13:58:58.688633 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 13:58:58.692605 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 13:58:58.696331 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 13:58:58.703563 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 13:58:58.707131 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 13:58:58.710890 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 13:58:58.718336 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 13:58:58.721424 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 13:58:58.724842 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 13:58:58.731848 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 13:58:58.734399 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 13:58:58.737962 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 13:58:58.744233 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 13:58:58.747784 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 13:58:58.751471 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 13:58:58.757833 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 13:58:58.760925 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 13:58:58.764341 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 13:58:58.771102 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 13:58:58.774069 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 13:58:58.777756 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 13:58:58.784056 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 13:58:58.794000 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 13:58:58.797198 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 13:58:58.807802 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 13:58:58.813878 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 13:58:58.820695 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 13:58:58.823825 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 13:58:58.826974 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 13:58:58.835154 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x39
520 13:58:58.842015 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 13:58:58.845054 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 13:58:58.848756 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 13:58:58.860031 [RTC]rtc_get_frequency_meter,154: input=15, output=795
524 13:58:58.863299 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
525 13:58:58.869994 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
526 13:58:58.873887 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
527 13:58:58.876884 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
528 13:58:58.880388 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
529 13:58:58.883678 ADC[4]: Raw value=899630 ID=7
530 13:58:58.887069 ADC[3]: Raw value=213440 ID=1
531 13:58:58.887694 RAM Code: 0x71
532 13:58:58.893429 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
533 13:58:58.896726 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
534 13:58:58.907043 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
535 13:58:58.913830 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
536 13:58:58.917207 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
537 13:58:58.920371 in-header: 03 07 00 00 08 00 00 00
538 13:58:58.923956 in-data: aa e4 47 04 13 02 00 00
539 13:58:58.924559 Chrome EC: UHEPI supported
540 13:58:58.930187 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
541 13:58:58.934678 in-header: 03 95 00 00 08 00 00 00
542 13:58:58.938362 in-data: 18 20 20 08 00 00 00 00
543 13:58:58.941783 MRC: failed to locate region type 0.
544 13:58:58.949022 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
545 13:58:58.953464 DRAM-K: Running full calibration
546 13:58:58.956804 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
547 13:58:58.959624 header.status = 0x0
548 13:58:58.963022 header.version = 0x6 (expected: 0x6)
549 13:58:58.967055 header.size = 0xd00 (expected: 0xd00)
550 13:58:58.967528 header.flags = 0x0
551 13:58:58.973818 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
552 13:58:58.991729 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
553 13:58:58.998706 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
554 13:58:59.001595 dram_init: ddr_geometry: 2
555 13:58:59.005559 [EMI] MDL number = 2
556 13:58:59.005984 [EMI] Get MDL freq = 0
557 13:58:59.008438 dram_init: ddr_type: 0
558 13:58:59.008862 is_discrete_lpddr4: 1
559 13:58:59.012110 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
560 13:58:59.012534
561 13:58:59.012868
562 13:58:59.015852 [Bian_co] ETT version 0.0.0.1
563 13:58:59.021868 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
564 13:58:59.022293
565 13:58:59.025797 dramc_set_vcore_voltage set vcore to 650000
566 13:58:59.026239 Read voltage for 800, 4
567 13:58:59.029692 Vio18 = 0
568 13:58:59.030162 Vcore = 650000
569 13:58:59.030510 Vdram = 0
570 13:58:59.030826 Vddq = 0
571 13:58:59.033155 Vmddr = 0
572 13:58:59.033577 dram_init: config_dvfs: 1
573 13:58:59.040160 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
574 13:58:59.043898 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
575 13:58:59.047560 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
576 13:58:59.051312 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
577 13:58:59.055679 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
578 13:58:59.058973 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
579 13:58:59.062479 MEM_TYPE=3, freq_sel=18
580 13:58:59.065654 sv_algorithm_assistance_LP4_1600
581 13:58:59.069764 ============ PULL DRAM RESETB DOWN ============
582 13:58:59.073522 ========== PULL DRAM RESETB DOWN end =========
583 13:58:59.076964 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
584 13:58:59.081291 ===================================
585 13:58:59.084943 LPDDR4 DRAM CONFIGURATION
586 13:58:59.088184 ===================================
587 13:58:59.088628 EX_ROW_EN[0] = 0x0
588 13:58:59.091919 EX_ROW_EN[1] = 0x0
589 13:58:59.092223 LP4Y_EN = 0x0
590 13:58:59.095658 WORK_FSP = 0x0
591 13:58:59.096010 WL = 0x2
592 13:58:59.099749 RL = 0x2
593 13:58:59.100022 BL = 0x2
594 13:58:59.100230 RPST = 0x0
595 13:58:59.102891 RD_PRE = 0x0
596 13:58:59.103217 WR_PRE = 0x1
597 13:58:59.106555 WR_PST = 0x0
598 13:58:59.106895 DBI_WR = 0x0
599 13:58:59.110283 DBI_RD = 0x0
600 13:58:59.110601 OTF = 0x1
601 13:58:59.114016 ===================================
602 13:58:59.117078 ===================================
603 13:58:59.120386 ANA top config
604 13:58:59.124115 ===================================
605 13:58:59.124380 DLL_ASYNC_EN = 0
606 13:58:59.127334 ALL_SLAVE_EN = 1
607 13:58:59.130738 NEW_RANK_MODE = 1
608 13:58:59.134093 DLL_IDLE_MODE = 1
609 13:58:59.134322 LP45_APHY_COMB_EN = 1
610 13:58:59.136984 TX_ODT_DIS = 1
611 13:58:59.140328 NEW_8X_MODE = 1
612 13:58:59.143860 ===================================
613 13:58:59.147264 ===================================
614 13:58:59.150642 data_rate = 1600
615 13:58:59.154299 CKR = 1
616 13:58:59.157250 DQ_P2S_RATIO = 8
617 13:58:59.160332 ===================================
618 13:58:59.160562 CA_P2S_RATIO = 8
619 13:58:59.163729 DQ_CA_OPEN = 0
620 13:58:59.167371 DQ_SEMI_OPEN = 0
621 13:58:59.170793 CA_SEMI_OPEN = 0
622 13:58:59.174234 CA_FULL_RATE = 0
623 13:58:59.177110 DQ_CKDIV4_EN = 1
624 13:58:59.177185 CA_CKDIV4_EN = 1
625 13:58:59.180566 CA_PREDIV_EN = 0
626 13:58:59.183480 PH8_DLY = 0
627 13:58:59.186846 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
628 13:58:59.190156 DQ_AAMCK_DIV = 4
629 13:58:59.190258 CA_AAMCK_DIV = 4
630 13:58:59.193328 CA_ADMCK_DIV = 4
631 13:58:59.196660 DQ_TRACK_CA_EN = 0
632 13:58:59.200028 CA_PICK = 800
633 13:58:59.203236 CA_MCKIO = 800
634 13:58:59.206888 MCKIO_SEMI = 0
635 13:58:59.210268 PLL_FREQ = 3068
636 13:58:59.210346 DQ_UI_PI_RATIO = 32
637 13:58:59.213696 CA_UI_PI_RATIO = 0
638 13:58:59.216767 ===================================
639 13:58:59.220828 ===================================
640 13:58:59.223685 memory_type:LPDDR4
641 13:58:59.227023 GP_NUM : 10
642 13:58:59.227091 SRAM_EN : 1
643 13:58:59.230330 MD32_EN : 0
644 13:58:59.234047 ===================================
645 13:58:59.234118 [ANA_INIT] >>>>>>>>>>>>>>
646 13:58:59.236880 <<<<<< [CONFIGURE PHASE]: ANA_TX
647 13:58:59.240322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
648 13:58:59.243642 ===================================
649 13:58:59.246767 data_rate = 1600,PCW = 0X7600
650 13:58:59.250556 ===================================
651 13:58:59.254015 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
652 13:58:59.260740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
653 13:58:59.264287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
654 13:58:59.270547 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
655 13:58:59.273743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
656 13:58:59.277566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
657 13:58:59.277678 [ANA_INIT] flow start
658 13:58:59.281788 [ANA_INIT] PLL >>>>>>>>
659 13:58:59.285209 [ANA_INIT] PLL <<<<<<<<
660 13:58:59.285288 [ANA_INIT] MIDPI >>>>>>>>
661 13:58:59.288593 [ANA_INIT] MIDPI <<<<<<<<
662 13:58:59.292325 [ANA_INIT] DLL >>>>>>>>
663 13:58:59.292407 [ANA_INIT] flow end
664 13:58:59.296254 ============ LP4 DIFF to SE enter ============
665 13:58:59.299610 ============ LP4 DIFF to SE exit ============
666 13:58:59.303647 [ANA_INIT] <<<<<<<<<<<<<
667 13:58:59.307371 [Flow] Enable top DCM control >>>>>
668 13:58:59.310597 [Flow] Enable top DCM control <<<<<
669 13:58:59.314109 Enable DLL master slave shuffle
670 13:58:59.317524 ==============================================================
671 13:58:59.321136 Gating Mode config
672 13:58:59.324715 ==============================================================
673 13:58:59.327560 Config description:
674 13:58:59.337642 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
675 13:58:59.344107 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
676 13:58:59.347609 SELPH_MODE 0: By rank 1: By Phase
677 13:58:59.354664 ==============================================================
678 13:58:59.358183 GAT_TRACK_EN = 1
679 13:58:59.362114 RX_GATING_MODE = 2
680 13:58:59.362208 RX_GATING_TRACK_MODE = 2
681 13:58:59.365380 SELPH_MODE = 1
682 13:58:59.368905 PICG_EARLY_EN = 1
683 13:58:59.372576 VALID_LAT_VALUE = 1
684 13:58:59.376241 ==============================================================
685 13:58:59.379884 Enter into Gating configuration >>>>
686 13:58:59.383830 Exit from Gating configuration <<<<
687 13:58:59.388096 Enter into DVFS_PRE_config >>>>>
688 13:58:59.398401 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
689 13:58:59.402105 Exit from DVFS_PRE_config <<<<<
690 13:58:59.405700 Enter into PICG configuration >>>>
691 13:58:59.408704 Exit from PICG configuration <<<<
692 13:58:59.408784 [RX_INPUT] configuration >>>>>
693 13:58:59.412788 [RX_INPUT] configuration <<<<<
694 13:58:59.420036 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
695 13:58:59.424048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
696 13:58:59.431163 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
697 13:58:59.435323 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
698 13:58:59.442233 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
699 13:58:59.450251 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
700 13:58:59.453601 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
701 13:58:59.457763 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
702 13:58:59.461625 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
703 13:58:59.465051 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
704 13:58:59.468491 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
705 13:58:59.472332 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
706 13:58:59.475715 ===================================
707 13:58:59.479745 LPDDR4 DRAM CONFIGURATION
708 13:58:59.483949 ===================================
709 13:58:59.484074 EX_ROW_EN[0] = 0x0
710 13:58:59.487337 EX_ROW_EN[1] = 0x0
711 13:58:59.487464 LP4Y_EN = 0x0
712 13:58:59.491181 WORK_FSP = 0x0
713 13:58:59.491254 WL = 0x2
714 13:58:59.495091 RL = 0x2
715 13:58:59.495198 BL = 0x2
716 13:58:59.498690 RPST = 0x0
717 13:58:59.498790 RD_PRE = 0x0
718 13:58:59.498881 WR_PRE = 0x1
719 13:58:59.502577 WR_PST = 0x0
720 13:58:59.502650 DBI_WR = 0x0
721 13:58:59.506503 DBI_RD = 0x0
722 13:58:59.506602 OTF = 0x1
723 13:58:59.509906 ===================================
724 13:58:59.513754 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
725 13:58:59.517479 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
726 13:58:59.524236 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 13:58:59.527689 ===================================
728 13:58:59.527779 LPDDR4 DRAM CONFIGURATION
729 13:58:59.531678 ===================================
730 13:58:59.535523 EX_ROW_EN[0] = 0x10
731 13:58:59.535602 EX_ROW_EN[1] = 0x0
732 13:58:59.539395 LP4Y_EN = 0x0
733 13:58:59.539525 WORK_FSP = 0x0
734 13:58:59.542581 WL = 0x2
735 13:58:59.542686 RL = 0x2
736 13:58:59.542778 BL = 0x2
737 13:58:59.546118 RPST = 0x0
738 13:58:59.546214 RD_PRE = 0x0
739 13:58:59.550395 WR_PRE = 0x1
740 13:58:59.550482 WR_PST = 0x0
741 13:58:59.553870 DBI_WR = 0x0
742 13:58:59.553957 DBI_RD = 0x0
743 13:58:59.557703 OTF = 0x1
744 13:58:59.561581 ===================================
745 13:58:59.565138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
746 13:58:59.570119 nWR fixed to 40
747 13:58:59.570227 [ModeRegInit_LP4] CH0 RK0
748 13:58:59.573963 [ModeRegInit_LP4] CH0 RK1
749 13:58:59.577738 [ModeRegInit_LP4] CH1 RK0
750 13:58:59.577846 [ModeRegInit_LP4] CH1 RK1
751 13:58:59.581292 match AC timing 13
752 13:58:59.585204 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
753 13:58:59.588790 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
754 13:58:59.592861 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
755 13:58:59.599796 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
756 13:58:59.604032 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
757 13:58:59.604122 [EMI DOE] emi_dcm 0
758 13:58:59.607484 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
759 13:58:59.611201 ==
760 13:58:59.611281 Dram Type= 6, Freq= 0, CH_0, rank 0
761 13:58:59.615441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
762 13:58:59.619027 ==
763 13:58:59.622463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
764 13:58:59.629738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
765 13:58:59.637858 [CA 0] Center 38 (7~69) winsize 63
766 13:58:59.641589 [CA 1] Center 37 (7~68) winsize 62
767 13:58:59.645193 [CA 2] Center 35 (5~66) winsize 62
768 13:58:59.649173 [CA 3] Center 35 (5~66) winsize 62
769 13:58:59.652613 [CA 4] Center 34 (4~65) winsize 62
770 13:58:59.652688 [CA 5] Center 34 (4~65) winsize 62
771 13:58:59.656123
772 13:58:59.659742 [CmdBusTrainingLP45] Vref(ca) range 1: 34
773 13:58:59.659820
774 13:58:59.663184 [CATrainingPosCal] consider 1 rank data
775 13:58:59.666576 u2DelayCellTimex100 = 270/100 ps
776 13:58:59.669723 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
777 13:58:59.673192 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
778 13:58:59.676080 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
779 13:58:59.679445 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
780 13:58:59.683044 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
781 13:58:59.686013 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
782 13:58:59.686122
783 13:58:59.689390 CA PerBit enable=1, Macro0, CA PI delay=34
784 13:58:59.689492
785 13:58:59.692761 [CBTSetCACLKResult] CA Dly = 34
786 13:58:59.696541 CS Dly: 6 (0~37)
787 13:58:59.696614 ==
788 13:58:59.699682 Dram Type= 6, Freq= 0, CH_0, rank 1
789 13:58:59.702785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 13:58:59.702887 ==
791 13:58:59.709586 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
792 13:58:59.712617 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
793 13:58:59.723543 [CA 0] Center 38 (7~69) winsize 63
794 13:58:59.726717 [CA 1] Center 37 (7~68) winsize 62
795 13:58:59.730358 [CA 2] Center 35 (5~66) winsize 62
796 13:58:59.733328 [CA 3] Center 35 (5~66) winsize 62
797 13:58:59.736749 [CA 4] Center 34 (4~65) winsize 62
798 13:58:59.740396 [CA 5] Center 34 (4~65) winsize 62
799 13:58:59.740473
800 13:58:59.743670 [CmdBusTrainingLP45] Vref(ca) range 1: 32
801 13:58:59.743750
802 13:58:59.746846 [CATrainingPosCal] consider 2 rank data
803 13:58:59.750383 u2DelayCellTimex100 = 270/100 ps
804 13:58:59.753548 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
805 13:58:59.756909 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
806 13:58:59.763323 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
807 13:58:59.766947 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
808 13:58:59.770341 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
809 13:58:59.773375 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
810 13:58:59.773456
811 13:58:59.776752 CA PerBit enable=1, Macro0, CA PI delay=34
812 13:58:59.776822
813 13:58:59.779890 [CBTSetCACLKResult] CA Dly = 34
814 13:58:59.779965 CS Dly: 6 (0~38)
815 13:58:59.783651
816 13:58:59.786463 ----->DramcWriteLeveling(PI) begin...
817 13:58:59.786538 ==
818 13:58:59.789767 Dram Type= 6, Freq= 0, CH_0, rank 0
819 13:58:59.793102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
820 13:58:59.793175 ==
821 13:58:59.796774 Write leveling (Byte 0): 33 => 33
822 13:58:59.799911 Write leveling (Byte 1): 28 => 28
823 13:58:59.803284 DramcWriteLeveling(PI) end<-----
824 13:58:59.803393
825 13:58:59.803481 ==
826 13:58:59.806616 Dram Type= 6, Freq= 0, CH_0, rank 0
827 13:58:59.810328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
828 13:58:59.810445 ==
829 13:58:59.813092 [Gating] SW mode calibration
830 13:58:59.819730 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
831 13:58:59.826715 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
832 13:58:59.829790 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
833 13:58:59.832958 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
834 13:58:59.836987 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
835 13:58:59.843336 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
836 13:58:59.846459 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 13:58:59.850208 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 13:58:59.856490 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 13:58:59.859993 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 13:58:59.864017 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 13:58:59.867556 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 13:58:59.874955 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 13:58:59.878590 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 13:58:59.881374 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 13:58:59.884987 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 13:58:59.891983 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 13:58:59.895314 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 13:58:59.899037 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 13:58:59.905711 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 13:58:59.908659 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
851 13:58:59.912201 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
852 13:58:59.915685 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 13:58:59.921974 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 13:58:59.925473 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 13:58:59.929233 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:58:59.935490 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:58:59.938569 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:58:59.942310 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
859 13:58:59.949344 0 9 12 | B1->B0 | 2525 3433 | 0 1 | (0 0) (0 0)
860 13:58:59.951966 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
861 13:58:59.955220 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
862 13:58:59.962112 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
863 13:58:59.965780 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
864 13:58:59.969155 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 13:58:59.975374 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
866 13:58:59.978777 0 10 8 | B1->B0 | 3232 3030 | 1 0 | (1 1) (1 0)
867 13:58:59.982159 0 10 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
868 13:58:59.988686 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 13:58:59.992289 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 13:58:59.995348 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 13:59:00.002047 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 13:59:00.005592 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 13:59:00.009065 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 13:59:00.015743 0 11 8 | B1->B0 | 2525 2c2c | 0 1 | (0 0) (0 0)
875 13:59:00.019515 0 11 12 | B1->B0 | 3535 4141 | 1 0 | (0 0) (1 1)
876 13:59:00.022372 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
877 13:59:00.025499 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
878 13:59:00.031966 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
879 13:59:00.035345 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
880 13:59:00.038732 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 13:59:00.045579 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
882 13:59:00.048914 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
883 13:59:00.052343 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
884 13:59:00.058683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 13:59:00.062039 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 13:59:00.065654 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 13:59:00.072417 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 13:59:00.075552 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 13:59:00.079169 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 13:59:00.085545 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 13:59:00.089174 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 13:59:00.092155 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 13:59:00.098968 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 13:59:00.102101 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 13:59:00.105426 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 13:59:00.112160 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 13:59:00.115612 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 13:59:00.119103 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
899 13:59:00.122267 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
900 13:59:00.125654 Total UI for P1: 0, mck2ui 16
901 13:59:00.129413 best dqsien dly found for B0: ( 0, 14, 8)
902 13:59:00.135848 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 13:59:00.138934 Total UI for P1: 0, mck2ui 16
904 13:59:00.142638 best dqsien dly found for B1: ( 0, 14, 12)
905 13:59:00.145488 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
906 13:59:00.148810 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
907 13:59:00.148894
908 13:59:00.152241 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
909 13:59:00.155667 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
910 13:59:00.159207 [Gating] SW calibration Done
911 13:59:00.159291 ==
912 13:59:00.162373 Dram Type= 6, Freq= 0, CH_0, rank 0
913 13:59:00.166153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 13:59:00.166237 ==
915 13:59:00.168787 RX Vref Scan: 0
916 13:59:00.168870
917 13:59:00.168937 RX Vref 0 -> 0, step: 1
918 13:59:00.168999
919 13:59:00.172150 RX Delay -130 -> 252, step: 16
920 13:59:00.176108 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
921 13:59:00.182512 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
922 13:59:00.186108 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
923 13:59:00.188926 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
924 13:59:00.192224 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
925 13:59:00.195842 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
926 13:59:00.202754 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
927 13:59:00.205713 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
928 13:59:00.209229 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
929 13:59:00.212556 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
930 13:59:00.215724 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
931 13:59:00.222314 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
932 13:59:00.225521 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
933 13:59:00.229587 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
934 13:59:00.232418 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
935 13:59:00.235707 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
936 13:59:00.239202 ==
937 13:59:00.242294 Dram Type= 6, Freq= 0, CH_0, rank 0
938 13:59:00.245791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
939 13:59:00.245875 ==
940 13:59:00.245941 DQS Delay:
941 13:59:00.249312 DQS0 = 0, DQS1 = 0
942 13:59:00.249397 DQM Delay:
943 13:59:00.252876 DQM0 = 83, DQM1 = 70
944 13:59:00.252959 DQ Delay:
945 13:59:00.256261 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
946 13:59:00.259023 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
947 13:59:00.263129 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
948 13:59:00.265863 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
949 13:59:00.265947
950 13:59:00.266013
951 13:59:00.266112 ==
952 13:59:00.269412 Dram Type= 6, Freq= 0, CH_0, rank 0
953 13:59:00.273478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 13:59:00.273562 ==
955 13:59:00.273628
956 13:59:00.273689
957 13:59:00.276954 TX Vref Scan disable
958 13:59:00.277037 == TX Byte 0 ==
959 13:59:00.283563 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
960 13:59:00.286592 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
961 13:59:00.286675 == TX Byte 1 ==
962 13:59:00.293537 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
963 13:59:00.296828 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
964 13:59:00.296912 ==
965 13:59:00.299882 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:59:00.303357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 13:59:00.303463 ==
968 13:59:00.317353 TX Vref=22, minBit 1, minWin=27, winSum=438
969 13:59:00.320761 TX Vref=24, minBit 4, minWin=27, winSum=443
970 13:59:00.324152 TX Vref=26, minBit 5, minWin=27, winSum=446
971 13:59:00.327308 TX Vref=28, minBit 5, minWin=27, winSum=445
972 13:59:00.330631 TX Vref=30, minBit 5, minWin=27, winSum=445
973 13:59:00.334056 TX Vref=32, minBit 2, minWin=27, winSum=444
974 13:59:00.340751 [TxChooseVref] Worse bit 5, Min win 27, Win sum 446, Final Vref 26
975 13:59:00.340857
976 13:59:00.344073 Final TX Range 1 Vref 26
977 13:59:00.344190
978 13:59:00.344285 ==
979 13:59:00.347209 Dram Type= 6, Freq= 0, CH_0, rank 0
980 13:59:00.350606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 13:59:00.350689 ==
982 13:59:00.350756
983 13:59:00.350845
984 13:59:00.353916 TX Vref Scan disable
985 13:59:00.357378 == TX Byte 0 ==
986 13:59:00.360520 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
987 13:59:00.364167 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
988 13:59:00.367076 == TX Byte 1 ==
989 13:59:00.370714 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
990 13:59:00.374180 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
991 13:59:00.377457
992 13:59:00.377540 [DATLAT]
993 13:59:00.377641 Freq=800, CH0 RK0
994 13:59:00.377704
995 13:59:00.380616 DATLAT Default: 0xa
996 13:59:00.380699 0, 0xFFFF, sum = 0
997 13:59:00.383826 1, 0xFFFF, sum = 0
998 13:59:00.383914 2, 0xFFFF, sum = 0
999 13:59:00.387496 3, 0xFFFF, sum = 0
1000 13:59:00.387581 4, 0xFFFF, sum = 0
1001 13:59:00.390767 5, 0xFFFF, sum = 0
1002 13:59:00.394226 6, 0xFFFF, sum = 0
1003 13:59:00.394311 7, 0xFFFF, sum = 0
1004 13:59:00.397376 8, 0xFFFF, sum = 0
1005 13:59:00.397460 9, 0x0, sum = 1
1006 13:59:00.397528 10, 0x0, sum = 2
1007 13:59:00.400744 11, 0x0, sum = 3
1008 13:59:00.400828 12, 0x0, sum = 4
1009 13:59:00.404209 best_step = 10
1010 13:59:00.404294
1011 13:59:00.404361 ==
1012 13:59:00.407520 Dram Type= 6, Freq= 0, CH_0, rank 0
1013 13:59:00.410682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1014 13:59:00.410765 ==
1015 13:59:00.414125 RX Vref Scan: 1
1016 13:59:00.414208
1017 13:59:00.414275 Set Vref Range= 32 -> 127
1018 13:59:00.414338
1019 13:59:00.417682 RX Vref 32 -> 127, step: 1
1020 13:59:00.417766
1021 13:59:00.420844 RX Delay -111 -> 252, step: 8
1022 13:59:00.420927
1023 13:59:00.423916 Set Vref, RX VrefLevel [Byte0]: 32
1024 13:59:00.427243 [Byte1]: 32
1025 13:59:00.427332
1026 13:59:00.430583 Set Vref, RX VrefLevel [Byte0]: 33
1027 13:59:00.433896 [Byte1]: 33
1028 13:59:00.437734
1029 13:59:00.437815 Set Vref, RX VrefLevel [Byte0]: 34
1030 13:59:00.441095 [Byte1]: 34
1031 13:59:00.445626
1032 13:59:00.445708 Set Vref, RX VrefLevel [Byte0]: 35
1033 13:59:00.449079 [Byte1]: 35
1034 13:59:00.453117
1035 13:59:00.453199 Set Vref, RX VrefLevel [Byte0]: 36
1036 13:59:00.456541 [Byte1]: 36
1037 13:59:00.460864
1038 13:59:00.460946 Set Vref, RX VrefLevel [Byte0]: 37
1039 13:59:00.464579 [Byte1]: 37
1040 13:59:00.468506
1041 13:59:00.468588 Set Vref, RX VrefLevel [Byte0]: 38
1042 13:59:00.471609 [Byte1]: 38
1043 13:59:00.475801
1044 13:59:00.479649 Set Vref, RX VrefLevel [Byte0]: 39
1045 13:59:00.479732 [Byte1]: 39
1046 13:59:00.483827
1047 13:59:00.483908 Set Vref, RX VrefLevel [Byte0]: 40
1048 13:59:00.486980 [Byte1]: 40
1049 13:59:00.491330
1050 13:59:00.491448 Set Vref, RX VrefLevel [Byte0]: 41
1051 13:59:00.494820 [Byte1]: 41
1052 13:59:00.499004
1053 13:59:00.499085 Set Vref, RX VrefLevel [Byte0]: 42
1054 13:59:00.502227 [Byte1]: 42
1055 13:59:00.506502
1056 13:59:00.506584 Set Vref, RX VrefLevel [Byte0]: 43
1057 13:59:00.509782 [Byte1]: 43
1058 13:59:00.514250
1059 13:59:00.514331 Set Vref, RX VrefLevel [Byte0]: 44
1060 13:59:00.517808 [Byte1]: 44
1061 13:59:00.522326
1062 13:59:00.522407 Set Vref, RX VrefLevel [Byte0]: 45
1063 13:59:00.525453 [Byte1]: 45
1064 13:59:00.529976
1065 13:59:00.530057 Set Vref, RX VrefLevel [Byte0]: 46
1066 13:59:00.533287 [Byte1]: 46
1067 13:59:00.537759
1068 13:59:00.537841 Set Vref, RX VrefLevel [Byte0]: 47
1069 13:59:00.541050 [Byte1]: 47
1070 13:59:00.545119
1071 13:59:00.545201 Set Vref, RX VrefLevel [Byte0]: 48
1072 13:59:00.548245 [Byte1]: 48
1073 13:59:00.552675
1074 13:59:00.552757 Set Vref, RX VrefLevel [Byte0]: 49
1075 13:59:00.556054 [Byte1]: 49
1076 13:59:00.560117
1077 13:59:00.560198 Set Vref, RX VrefLevel [Byte0]: 50
1078 13:59:00.563352 [Byte1]: 50
1079 13:59:00.567611
1080 13:59:00.567693 Set Vref, RX VrefLevel [Byte0]: 51
1081 13:59:00.570902 [Byte1]: 51
1082 13:59:00.575322
1083 13:59:00.575444 Set Vref, RX VrefLevel [Byte0]: 52
1084 13:59:00.579046 [Byte1]: 52
1085 13:59:00.583122
1086 13:59:00.583204 Set Vref, RX VrefLevel [Byte0]: 53
1087 13:59:00.586677 [Byte1]: 53
1088 13:59:00.590822
1089 13:59:00.590904 Set Vref, RX VrefLevel [Byte0]: 54
1090 13:59:00.594151 [Byte1]: 54
1091 13:59:00.598886
1092 13:59:00.598968 Set Vref, RX VrefLevel [Byte0]: 55
1093 13:59:00.601742 [Byte1]: 55
1094 13:59:00.605986
1095 13:59:00.606070 Set Vref, RX VrefLevel [Byte0]: 56
1096 13:59:00.609109 [Byte1]: 56
1097 13:59:00.613548
1098 13:59:00.613638 Set Vref, RX VrefLevel [Byte0]: 57
1099 13:59:00.617147 [Byte1]: 57
1100 13:59:00.621288
1101 13:59:00.621363 Set Vref, RX VrefLevel [Byte0]: 58
1102 13:59:00.624373 [Byte1]: 58
1103 13:59:00.628976
1104 13:59:00.629052 Set Vref, RX VrefLevel [Byte0]: 59
1105 13:59:00.632563 [Byte1]: 59
1106 13:59:00.636380
1107 13:59:00.636463 Set Vref, RX VrefLevel [Byte0]: 60
1108 13:59:00.640013 [Byte1]: 60
1109 13:59:00.644470
1110 13:59:00.644574 Set Vref, RX VrefLevel [Byte0]: 61
1111 13:59:00.647715 [Byte1]: 61
1112 13:59:00.651863
1113 13:59:00.651948 Set Vref, RX VrefLevel [Byte0]: 62
1114 13:59:00.655366 [Byte1]: 62
1115 13:59:00.659323
1116 13:59:00.659440 Set Vref, RX VrefLevel [Byte0]: 63
1117 13:59:00.663177 [Byte1]: 63
1118 13:59:00.667133
1119 13:59:00.667208 Set Vref, RX VrefLevel [Byte0]: 64
1120 13:59:00.670568 [Byte1]: 64
1121 13:59:00.674658
1122 13:59:00.674740 Set Vref, RX VrefLevel [Byte0]: 65
1123 13:59:00.678324 [Byte1]: 65
1124 13:59:00.682579
1125 13:59:00.682661 Set Vref, RX VrefLevel [Byte0]: 66
1126 13:59:00.685710 [Byte1]: 66
1127 13:59:00.689886
1128 13:59:00.689968 Set Vref, RX VrefLevel [Byte0]: 67
1129 13:59:00.693282 [Byte1]: 67
1130 13:59:00.697712
1131 13:59:00.697793 Set Vref, RX VrefLevel [Byte0]: 68
1132 13:59:00.701063 [Byte1]: 68
1133 13:59:00.705406
1134 13:59:00.705483 Set Vref, RX VrefLevel [Byte0]: 69
1135 13:59:00.708828 [Byte1]: 69
1136 13:59:00.713184
1137 13:59:00.713268 Set Vref, RX VrefLevel [Byte0]: 70
1138 13:59:00.716187 [Byte1]: 70
1139 13:59:00.720966
1140 13:59:00.721043 Set Vref, RX VrefLevel [Byte0]: 71
1141 13:59:00.724464 [Byte1]: 71
1142 13:59:00.728527
1143 13:59:00.728602 Set Vref, RX VrefLevel [Byte0]: 72
1144 13:59:00.731704 [Byte1]: 72
1145 13:59:00.736150
1146 13:59:00.736224 Set Vref, RX VrefLevel [Byte0]: 73
1147 13:59:00.739115 [Byte1]: 73
1148 13:59:00.743981
1149 13:59:00.744057 Set Vref, RX VrefLevel [Byte0]: 74
1150 13:59:00.746880 [Byte1]: 74
1151 13:59:00.751480
1152 13:59:00.751561 Set Vref, RX VrefLevel [Byte0]: 75
1153 13:59:00.754614 [Byte1]: 75
1154 13:59:00.759045
1155 13:59:00.759123 Set Vref, RX VrefLevel [Byte0]: 76
1156 13:59:00.762154 [Byte1]: 76
1157 13:59:00.766402
1158 13:59:00.766477 Set Vref, RX VrefLevel [Byte0]: 77
1159 13:59:00.769852 [Byte1]: 77
1160 13:59:00.774421
1161 13:59:00.774501 Set Vref, RX VrefLevel [Byte0]: 78
1162 13:59:00.777318 [Byte1]: 78
1163 13:59:00.782092
1164 13:59:00.782174 Set Vref, RX VrefLevel [Byte0]: 79
1165 13:59:00.785177 [Byte1]: 79
1166 13:59:00.789460
1167 13:59:00.789542 Final RX Vref Byte 0 = 60 to rank0
1168 13:59:00.792803 Final RX Vref Byte 1 = 55 to rank0
1169 13:59:00.796470 Final RX Vref Byte 0 = 60 to rank1
1170 13:59:00.799261 Final RX Vref Byte 1 = 55 to rank1==
1171 13:59:00.802652 Dram Type= 6, Freq= 0, CH_0, rank 0
1172 13:59:00.809427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1173 13:59:00.809511 ==
1174 13:59:00.809577 DQS Delay:
1175 13:59:00.809637 DQS0 = 0, DQS1 = 0
1176 13:59:00.812883 DQM Delay:
1177 13:59:00.812965 DQM0 = 82, DQM1 = 67
1178 13:59:00.816193 DQ Delay:
1179 13:59:00.819528 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1180 13:59:00.822951 DQ4 =84, DQ5 =68, DQ6 =88, DQ7 =92
1181 13:59:00.823033 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1182 13:59:00.829385 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1183 13:59:00.829467
1184 13:59:00.829532
1185 13:59:00.835891 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1186 13:59:00.839604 CH0 RK0: MR19=606, MR18=2A2A
1187 13:59:00.846142 CH0_RK0: MR19=0x606, MR18=0x2A2A, DQSOSC=399, MR23=63, INC=92, DEC=61
1188 13:59:00.846226
1189 13:59:00.849338 ----->DramcWriteLeveling(PI) begin...
1190 13:59:00.849411 ==
1191 13:59:00.853180 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 13:59:00.856327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 13:59:00.856408 ==
1194 13:59:00.859442 Write leveling (Byte 0): 30 => 30
1195 13:59:00.862837 Write leveling (Byte 1): 29 => 29
1196 13:59:00.866453 DramcWriteLeveling(PI) end<-----
1197 13:59:00.866527
1198 13:59:00.866590 ==
1199 13:59:00.869144 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 13:59:00.872687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 13:59:00.872763 ==
1202 13:59:00.876062 [Gating] SW mode calibration
1203 13:59:00.882924 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1204 13:59:00.889267 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1205 13:59:00.892694 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1206 13:59:00.896040 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1207 13:59:00.902900 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1208 13:59:00.906212 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1209 13:59:00.909490 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 13:59:00.916041 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 13:59:00.919483 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 13:59:00.922605 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 13:59:00.929468 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 13:59:00.932877 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 13:59:00.936074 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 13:59:00.942617 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 13:59:00.945889 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 13:59:00.949540 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 13:59:00.993349 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 13:59:00.993638 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 13:59:00.993731 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 13:59:00.994399 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1223 13:59:00.994478 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1224 13:59:00.995039 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:59:00.995755 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 13:59:00.996020 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 13:59:00.996093 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 13:59:00.996156 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 13:59:01.037311 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 13:59:01.037829 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 13:59:01.038092 0 9 8 | B1->B0 | 2424 2929 | 0 0 | (0 0) (1 1)
1232 13:59:01.038162 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1233 13:59:01.038801 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 13:59:01.039064 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 13:59:01.039314 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 13:59:01.039567 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 13:59:01.039636 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 13:59:01.039707 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
1239 13:59:01.059254 0 10 8 | B1->B0 | 3131 2929 | 1 0 | (1 0) (0 0)
1240 13:59:01.059558 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1241 13:59:01.059634 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 13:59:01.059699 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 13:59:01.060395 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 13:59:01.062941 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 13:59:01.069477 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 13:59:01.073071 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
1247 13:59:01.076332 0 11 8 | B1->B0 | 2828 3939 | 1 1 | (0 0) (0 0)
1248 13:59:01.083077 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1249 13:59:01.086577 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 13:59:01.089762 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 13:59:01.096402 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 13:59:01.100122 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 13:59:01.103826 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 13:59:01.107192 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 13:59:01.114423 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1256 13:59:01.117927 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 13:59:01.121145 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 13:59:01.124733 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 13:59:01.131460 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 13:59:01.135042 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 13:59:01.138315 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 13:59:01.141885 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 13:59:01.148106 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 13:59:01.152137 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 13:59:01.155225 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 13:59:01.161461 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 13:59:01.164770 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 13:59:01.168031 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 13:59:01.174854 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 13:59:01.178263 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1271 13:59:01.182030 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1272 13:59:01.185113 Total UI for P1: 0, mck2ui 16
1273 13:59:01.188739 best dqsien dly found for B0: ( 0, 14, 4)
1274 13:59:01.194750 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1275 13:59:01.197946 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 13:59:01.201588 Total UI for P1: 0, mck2ui 16
1277 13:59:01.204889 best dqsien dly found for B1: ( 0, 14, 10)
1278 13:59:01.208595 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1279 13:59:01.211490 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1280 13:59:01.211572
1281 13:59:01.215326 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1282 13:59:01.218204 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1283 13:59:01.221346 [Gating] SW calibration Done
1284 13:59:01.221428 ==
1285 13:59:01.225017 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 13:59:01.228334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 13:59:01.231814 ==
1288 13:59:01.231896 RX Vref Scan: 0
1289 13:59:01.231961
1290 13:59:01.234888 RX Vref 0 -> 0, step: 1
1291 13:59:01.234971
1292 13:59:01.238027 RX Delay -130 -> 252, step: 16
1293 13:59:01.241245 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1294 13:59:01.244733 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1295 13:59:01.247948 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1296 13:59:01.251516 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1297 13:59:01.258487 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1298 13:59:01.261404 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1299 13:59:01.264800 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1300 13:59:01.268371 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1301 13:59:01.271347 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1302 13:59:01.274896 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1303 13:59:01.281628 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1304 13:59:01.284894 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1305 13:59:01.287848 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1306 13:59:01.291482 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1307 13:59:01.298220 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1308 13:59:01.301366 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1309 13:59:01.301441 ==
1310 13:59:01.304714 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 13:59:01.307888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 13:59:01.307962 ==
1313 13:59:01.311281 DQS Delay:
1314 13:59:01.311359 DQS0 = 0, DQS1 = 0
1315 13:59:01.311472 DQM Delay:
1316 13:59:01.314663 DQM0 = 79, DQM1 = 71
1317 13:59:01.314733 DQ Delay:
1318 13:59:01.318122 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1319 13:59:01.321429 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =85
1320 13:59:01.324542 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1321 13:59:01.327979 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
1322 13:59:01.328051
1323 13:59:01.328112
1324 13:59:01.328178 ==
1325 13:59:01.331236 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 13:59:01.334862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 13:59:01.338375 ==
1328 13:59:01.338445
1329 13:59:01.338507
1330 13:59:01.338572 TX Vref Scan disable
1331 13:59:01.341336 == TX Byte 0 ==
1332 13:59:01.344795 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1333 13:59:01.348145 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1334 13:59:01.351161 == TX Byte 1 ==
1335 13:59:01.354687 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1336 13:59:01.357906 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1337 13:59:01.361131 ==
1338 13:59:01.364595 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 13:59:01.368157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 13:59:01.368234 ==
1341 13:59:01.380300 TX Vref=22, minBit 1, minWin=27, winSum=435
1342 13:59:01.383363 TX Vref=24, minBit 1, minWin=26, winSum=434
1343 13:59:01.386751 TX Vref=26, minBit 1, minWin=27, winSum=441
1344 13:59:01.390095 TX Vref=28, minBit 1, minWin=27, winSum=445
1345 13:59:01.393494 TX Vref=30, minBit 1, minWin=27, winSum=443
1346 13:59:01.396947 TX Vref=32, minBit 1, minWin=27, winSum=443
1347 13:59:01.403456 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 28
1348 13:59:01.403544
1349 13:59:01.406583 Final TX Range 1 Vref 28
1350 13:59:01.406657
1351 13:59:01.406726 ==
1352 13:59:01.410252 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 13:59:01.413443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 13:59:01.413519 ==
1355 13:59:01.413597
1356 13:59:01.417089
1357 13:59:01.417167 TX Vref Scan disable
1358 13:59:01.420521 == TX Byte 0 ==
1359 13:59:01.423454 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1360 13:59:01.426705 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1361 13:59:01.430271 == TX Byte 1 ==
1362 13:59:01.433756 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1363 13:59:01.436940 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1364 13:59:01.440156
1365 13:59:01.440307 [DATLAT]
1366 13:59:01.440408 Freq=800, CH0 RK1
1367 13:59:01.440498
1368 13:59:01.443413 DATLAT Default: 0xa
1369 13:59:01.443509 0, 0xFFFF, sum = 0
1370 13:59:01.446993 1, 0xFFFF, sum = 0
1371 13:59:01.447081 2, 0xFFFF, sum = 0
1372 13:59:01.450036 3, 0xFFFF, sum = 0
1373 13:59:01.450115 4, 0xFFFF, sum = 0
1374 13:59:01.453644 5, 0xFFFF, sum = 0
1375 13:59:01.453728 6, 0xFFFF, sum = 0
1376 13:59:01.456828 7, 0xFFFF, sum = 0
1377 13:59:01.459924 8, 0xFFFF, sum = 0
1378 13:59:01.460010 9, 0x0, sum = 1
1379 13:59:01.460110 10, 0x0, sum = 2
1380 13:59:01.463058 11, 0x0, sum = 3
1381 13:59:01.463134 12, 0x0, sum = 4
1382 13:59:01.466475 best_step = 10
1383 13:59:01.466551
1384 13:59:01.466613 ==
1385 13:59:01.469933 Dram Type= 6, Freq= 0, CH_0, rank 1
1386 13:59:01.473231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1387 13:59:01.473307 ==
1388 13:59:01.476776 RX Vref Scan: 0
1389 13:59:01.476854
1390 13:59:01.476925 RX Vref 0 -> 0, step: 1
1391 13:59:01.476988
1392 13:59:01.479712 RX Delay -111 -> 252, step: 8
1393 13:59:01.486636 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1394 13:59:01.490152 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1395 13:59:01.493488 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1396 13:59:01.497136 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1397 13:59:01.500034 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1398 13:59:01.506748 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1399 13:59:01.509980 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1400 13:59:01.514030 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1401 13:59:01.516930 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1402 13:59:01.520092 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1403 13:59:01.527016 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1404 13:59:01.530363 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1405 13:59:01.533736 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1406 13:59:01.536695 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1407 13:59:01.540293 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1408 13:59:01.546878 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1409 13:59:01.546956 ==
1410 13:59:01.550145 Dram Type= 6, Freq= 0, CH_0, rank 1
1411 13:59:01.553447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 13:59:01.553529 ==
1413 13:59:01.553596 DQS Delay:
1414 13:59:01.557060 DQS0 = 0, DQS1 = 0
1415 13:59:01.557161 DQM Delay:
1416 13:59:01.560465 DQM0 = 79, DQM1 = 69
1417 13:59:01.560540 DQ Delay:
1418 13:59:01.563292 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1419 13:59:01.567228 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1420 13:59:01.570256 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1421 13:59:01.573452 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1422 13:59:01.573527
1423 13:59:01.573625
1424 13:59:01.580048 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1425 13:59:01.583951 CH0 RK1: MR19=606, MR18=4A25
1426 13:59:01.590122 CH0_RK1: MR19=0x606, MR18=0x4A25, DQSOSC=391, MR23=63, INC=96, DEC=64
1427 13:59:01.593475 [RxdqsGatingPostProcess] freq 800
1428 13:59:01.599941 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1429 13:59:01.603246 Pre-setting of DQS Precalculation
1430 13:59:01.606574 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1431 13:59:01.606651 ==
1432 13:59:01.610467 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 13:59:01.613560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 13:59:01.613643 ==
1435 13:59:01.619978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1436 13:59:01.626615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1437 13:59:01.635268 [CA 0] Center 36 (6~66) winsize 61
1438 13:59:01.638958 [CA 1] Center 36 (6~67) winsize 62
1439 13:59:01.641845 [CA 2] Center 34 (4~64) winsize 61
1440 13:59:01.645188 [CA 3] Center 34 (4~64) winsize 61
1441 13:59:01.648500 [CA 4] Center 34 (4~64) winsize 61
1442 13:59:01.652129 [CA 5] Center 33 (3~64) winsize 62
1443 13:59:01.652228
1444 13:59:01.655548 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1445 13:59:01.655630
1446 13:59:01.658489 [CATrainingPosCal] consider 1 rank data
1447 13:59:01.661931 u2DelayCellTimex100 = 270/100 ps
1448 13:59:01.665584 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1449 13:59:01.668494 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1450 13:59:01.675234 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1451 13:59:01.678699 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1452 13:59:01.681784 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1453 13:59:01.685387 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1454 13:59:01.685470
1455 13:59:01.688797 CA PerBit enable=1, Macro0, CA PI delay=33
1456 13:59:01.688880
1457 13:59:01.691665 [CBTSetCACLKResult] CA Dly = 33
1458 13:59:01.691771 CS Dly: 5 (0~36)
1459 13:59:01.691861 ==
1460 13:59:01.695311 Dram Type= 6, Freq= 0, CH_1, rank 1
1461 13:59:01.702079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 13:59:01.702162 ==
1463 13:59:01.705271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1464 13:59:01.711929 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1465 13:59:01.721128 [CA 0] Center 36 (6~67) winsize 62
1466 13:59:01.724402 [CA 1] Center 36 (6~67) winsize 62
1467 13:59:01.727683 [CA 2] Center 34 (4~65) winsize 62
1468 13:59:01.731148 [CA 3] Center 33 (3~64) winsize 62
1469 13:59:01.734347 [CA 4] Center 34 (4~65) winsize 62
1470 13:59:01.737772 [CA 5] Center 33 (3~64) winsize 62
1471 13:59:01.737873
1472 13:59:01.741271 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1473 13:59:01.741370
1474 13:59:01.744688 [CATrainingPosCal] consider 2 rank data
1475 13:59:01.747948 u2DelayCellTimex100 = 270/100 ps
1476 13:59:01.751576 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1477 13:59:01.754598 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1478 13:59:01.761448 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1479 13:59:01.765506 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1480 13:59:01.765588 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1481 13:59:01.768942 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1482 13:59:01.772745
1483 13:59:01.776751 CA PerBit enable=1, Macro0, CA PI delay=33
1484 13:59:01.776834
1485 13:59:01.776899 [CBTSetCACLKResult] CA Dly = 33
1486 13:59:01.780013 CS Dly: 6 (0~38)
1487 13:59:01.780117
1488 13:59:01.783660 ----->DramcWriteLeveling(PI) begin...
1489 13:59:01.783761 ==
1490 13:59:01.787634 Dram Type= 6, Freq= 0, CH_1, rank 0
1491 13:59:01.790898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1492 13:59:01.791006 ==
1493 13:59:01.794822 Write leveling (Byte 0): 28 => 28
1494 13:59:01.798460 Write leveling (Byte 1): 29 => 29
1495 13:59:01.798566 DramcWriteLeveling(PI) end<-----
1496 13:59:01.798657
1497 13:59:01.798744 ==
1498 13:59:01.801894 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 13:59:01.808593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1500 13:59:01.808675 ==
1501 13:59:01.811974 [Gating] SW mode calibration
1502 13:59:01.818710 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1503 13:59:01.821741 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1504 13:59:01.829129 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1505 13:59:01.831665 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1506 13:59:01.834854 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1507 13:59:01.841722 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 13:59:01.844994 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 13:59:01.848330 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 13:59:01.851990 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 13:59:01.858856 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 13:59:01.861814 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 13:59:01.865364 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 13:59:01.871964 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 13:59:01.875421 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 13:59:01.878924 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 13:59:01.885165 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 13:59:01.888585 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 13:59:01.891905 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 13:59:01.898312 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 13:59:01.901461 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1522 13:59:01.905156 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1523 13:59:01.912120 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 13:59:01.915212 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 13:59:01.918434 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 13:59:01.924951 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 13:59:01.928060 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 13:59:01.931460 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 13:59:01.938104 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 13:59:01.941510 0 9 8 | B1->B0 | 2f2f 2a2a | 1 0 | (1 1) (0 0)
1531 13:59:01.945080 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 13:59:01.951689 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 13:59:01.954521 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 13:59:01.958294 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 13:59:01.965013 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 13:59:01.968201 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 13:59:01.971859 0 10 4 | B1->B0 | 3333 3333 | 1 1 | (0 0) (0 0)
1538 13:59:01.974596 0 10 8 | B1->B0 | 2828 2a2a | 0 0 | (0 0) (0 0)
1539 13:59:01.981476 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1540 13:59:01.984498 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 13:59:01.987993 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 13:59:01.994543 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 13:59:01.998035 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 13:59:02.001261 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 13:59:02.007879 0 11 4 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
1546 13:59:02.011580 0 11 8 | B1->B0 | 3c3c 3f3f | 0 1 | (0 0) (0 0)
1547 13:59:02.014563 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 13:59:02.021580 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 13:59:02.024841 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 13:59:02.028239 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 13:59:02.034705 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 13:59:02.037834 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 13:59:02.041518 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 13:59:02.047840 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 13:59:02.051608 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 13:59:02.054909 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 13:59:02.061260 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 13:59:02.064601 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 13:59:02.067989 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 13:59:02.074559 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 13:59:02.078338 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 13:59:02.081403 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 13:59:02.084609 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 13:59:02.091344 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 13:59:02.094539 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 13:59:02.097777 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 13:59:02.105123 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 13:59:02.108222 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 13:59:02.111133 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 13:59:02.118121 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1571 13:59:02.121128 Total UI for P1: 0, mck2ui 16
1572 13:59:02.124389 best dqsien dly found for B1: ( 0, 14, 6)
1573 13:59:02.128100 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 13:59:02.131584 Total UI for P1: 0, mck2ui 16
1575 13:59:02.134563 best dqsien dly found for B0: ( 0, 14, 8)
1576 13:59:02.137941 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1577 13:59:02.141581 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1578 13:59:02.141658
1579 13:59:02.144902 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1580 13:59:02.148203 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1581 13:59:02.151510 [Gating] SW calibration Done
1582 13:59:02.151585 ==
1583 13:59:02.154409 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 13:59:02.158051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 13:59:02.158129 ==
1586 13:59:02.161404 RX Vref Scan: 0
1587 13:59:02.161486
1588 13:59:02.164932 RX Vref 0 -> 0, step: 1
1589 13:59:02.165011
1590 13:59:02.165073 RX Delay -130 -> 252, step: 16
1591 13:59:02.171117 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1592 13:59:02.174532 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1593 13:59:02.178023 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1594 13:59:02.181150 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1595 13:59:02.184703 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1596 13:59:02.191521 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1597 13:59:02.194431 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1598 13:59:02.198065 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1599 13:59:02.201253 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1600 13:59:02.204565 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1601 13:59:02.211266 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1602 13:59:02.215184 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1603 13:59:02.218012 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1604 13:59:02.221883 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1605 13:59:02.224833 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1606 13:59:02.231322 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1607 13:59:02.231445 ==
1608 13:59:02.234626 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 13:59:02.238251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 13:59:02.238329 ==
1611 13:59:02.238401 DQS Delay:
1612 13:59:02.241606 DQS0 = 0, DQS1 = 0
1613 13:59:02.241682 DQM Delay:
1614 13:59:02.244799 DQM0 = 81, DQM1 = 73
1615 13:59:02.244880 DQ Delay:
1616 13:59:02.248045 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1617 13:59:02.251342 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1618 13:59:02.254691 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1619 13:59:02.257971 DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77
1620 13:59:02.258049
1621 13:59:02.258122
1622 13:59:02.258182 ==
1623 13:59:02.261331 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 13:59:02.264549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 13:59:02.264629 ==
1626 13:59:02.264692
1627 13:59:02.267851
1628 13:59:02.267924 TX Vref Scan disable
1629 13:59:02.271248 == TX Byte 0 ==
1630 13:59:02.274725 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1631 13:59:02.278132 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1632 13:59:02.281681 == TX Byte 1 ==
1633 13:59:02.284845 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1634 13:59:02.288049 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1635 13:59:02.288130 ==
1636 13:59:02.291494 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 13:59:02.298363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 13:59:02.298476 ==
1639 13:59:02.309708 TX Vref=22, minBit 8, minWin=27, winSum=444
1640 13:59:02.313198 TX Vref=24, minBit 8, minWin=27, winSum=447
1641 13:59:02.316441 TX Vref=26, minBit 8, minWin=27, winSum=452
1642 13:59:02.319594 TX Vref=28, minBit 11, minWin=27, winSum=456
1643 13:59:02.322784 TX Vref=30, minBit 9, minWin=27, winSum=457
1644 13:59:02.329513 TX Vref=32, minBit 9, minWin=27, winSum=455
1645 13:59:02.332770 [TxChooseVref] Worse bit 9, Min win 27, Win sum 457, Final Vref 30
1646 13:59:02.332852
1647 13:59:02.336736 Final TX Range 1 Vref 30
1648 13:59:02.336826
1649 13:59:02.336889 ==
1650 13:59:02.339311 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 13:59:02.343612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 13:59:02.343687 ==
1653 13:59:02.343750
1654 13:59:02.343808
1655 13:59:02.346648 TX Vref Scan disable
1656 13:59:02.350516 == TX Byte 0 ==
1657 13:59:02.353711 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1658 13:59:02.357252 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1659 13:59:02.360530 == TX Byte 1 ==
1660 13:59:02.363943 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1661 13:59:02.367147 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1662 13:59:02.367261
1663 13:59:02.370265 [DATLAT]
1664 13:59:02.370337 Freq=800, CH1 RK0
1665 13:59:02.370398
1666 13:59:02.373604 DATLAT Default: 0xa
1667 13:59:02.373678 0, 0xFFFF, sum = 0
1668 13:59:02.376830 1, 0xFFFF, sum = 0
1669 13:59:02.376904 2, 0xFFFF, sum = 0
1670 13:59:02.380038 3, 0xFFFF, sum = 0
1671 13:59:02.380113 4, 0xFFFF, sum = 0
1672 13:59:02.383724 5, 0xFFFF, sum = 0
1673 13:59:02.383800 6, 0xFFFF, sum = 0
1674 13:59:02.387242 7, 0xFFFF, sum = 0
1675 13:59:02.387316 8, 0xFFFF, sum = 0
1676 13:59:02.390453 9, 0x0, sum = 1
1677 13:59:02.390531 10, 0x0, sum = 2
1678 13:59:02.393814 11, 0x0, sum = 3
1679 13:59:02.393889 12, 0x0, sum = 4
1680 13:59:02.396863 best_step = 10
1681 13:59:02.396937
1682 13:59:02.397007 ==
1683 13:59:02.400075 Dram Type= 6, Freq= 0, CH_1, rank 0
1684 13:59:02.404051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1685 13:59:02.404134 ==
1686 13:59:02.404197 RX Vref Scan: 1
1687 13:59:02.406686
1688 13:59:02.406758 Set Vref Range= 32 -> 127
1689 13:59:02.406819
1690 13:59:02.410586 RX Vref 32 -> 127, step: 1
1691 13:59:02.410660
1692 13:59:02.413595 RX Delay -111 -> 252, step: 8
1693 13:59:02.413667
1694 13:59:02.416961 Set Vref, RX VrefLevel [Byte0]: 32
1695 13:59:02.420463 [Byte1]: 32
1696 13:59:02.420538
1697 13:59:02.423501 Set Vref, RX VrefLevel [Byte0]: 33
1698 13:59:02.427057 [Byte1]: 33
1699 13:59:02.427132
1700 13:59:02.430539 Set Vref, RX VrefLevel [Byte0]: 34
1701 13:59:02.433686 [Byte1]: 34
1702 13:59:02.437689
1703 13:59:02.437764 Set Vref, RX VrefLevel [Byte0]: 35
1704 13:59:02.441288 [Byte1]: 35
1705 13:59:02.445372
1706 13:59:02.445451 Set Vref, RX VrefLevel [Byte0]: 36
1707 13:59:02.449046 [Byte1]: 36
1708 13:59:02.452993
1709 13:59:02.453068 Set Vref, RX VrefLevel [Byte0]: 37
1710 13:59:02.456647 [Byte1]: 37
1711 13:59:02.460630
1712 13:59:02.460705 Set Vref, RX VrefLevel [Byte0]: 38
1713 13:59:02.464143 [Byte1]: 38
1714 13:59:02.468687
1715 13:59:02.468764 Set Vref, RX VrefLevel [Byte0]: 39
1716 13:59:02.472079 [Byte1]: 39
1717 13:59:02.476258
1718 13:59:02.476340 Set Vref, RX VrefLevel [Byte0]: 40
1719 13:59:02.479354 [Byte1]: 40
1720 13:59:02.483346
1721 13:59:02.483468 Set Vref, RX VrefLevel [Byte0]: 41
1722 13:59:02.487075 [Byte1]: 41
1723 13:59:02.491010
1724 13:59:02.491084 Set Vref, RX VrefLevel [Byte0]: 42
1725 13:59:02.494558 [Byte1]: 42
1726 13:59:02.499255
1727 13:59:02.499329 Set Vref, RX VrefLevel [Byte0]: 43
1728 13:59:02.501920 [Byte1]: 43
1729 13:59:02.506386
1730 13:59:02.506467 Set Vref, RX VrefLevel [Byte0]: 44
1731 13:59:02.509874 [Byte1]: 44
1732 13:59:02.514467
1733 13:59:02.514542 Set Vref, RX VrefLevel [Byte0]: 45
1734 13:59:02.517537 [Byte1]: 45
1735 13:59:02.522204
1736 13:59:02.522279 Set Vref, RX VrefLevel [Byte0]: 46
1737 13:59:02.524980 [Byte1]: 46
1738 13:59:02.529389
1739 13:59:02.529470 Set Vref, RX VrefLevel [Byte0]: 47
1740 13:59:02.533057 [Byte1]: 47
1741 13:59:02.536946
1742 13:59:02.537027 Set Vref, RX VrefLevel [Byte0]: 48
1743 13:59:02.540819 [Byte1]: 48
1744 13:59:02.544748
1745 13:59:02.544823 Set Vref, RX VrefLevel [Byte0]: 49
1746 13:59:02.548140 [Byte1]: 49
1747 13:59:02.552245
1748 13:59:02.552319 Set Vref, RX VrefLevel [Byte0]: 50
1749 13:59:02.555562 [Byte1]: 50
1750 13:59:02.559991
1751 13:59:02.560066 Set Vref, RX VrefLevel [Byte0]: 51
1752 13:59:02.563421 [Byte1]: 51
1753 13:59:02.568036
1754 13:59:02.568110 Set Vref, RX VrefLevel [Byte0]: 52
1755 13:59:02.570862 [Byte1]: 52
1756 13:59:02.575269
1757 13:59:02.575343 Set Vref, RX VrefLevel [Byte0]: 53
1758 13:59:02.578626 [Byte1]: 53
1759 13:59:02.583024
1760 13:59:02.583101 Set Vref, RX VrefLevel [Byte0]: 54
1761 13:59:02.586565 [Byte1]: 54
1762 13:59:02.591165
1763 13:59:02.591242 Set Vref, RX VrefLevel [Byte0]: 55
1764 13:59:02.593946 [Byte1]: 55
1765 13:59:02.598655
1766 13:59:02.598728 Set Vref, RX VrefLevel [Byte0]: 56
1767 13:59:02.601570 [Byte1]: 56
1768 13:59:02.606084
1769 13:59:02.606162 Set Vref, RX VrefLevel [Byte0]: 57
1770 13:59:02.609355 [Byte1]: 57
1771 13:59:02.614039
1772 13:59:02.614119 Set Vref, RX VrefLevel [Byte0]: 58
1773 13:59:02.617061 [Byte1]: 58
1774 13:59:02.621519
1775 13:59:02.621600 Set Vref, RX VrefLevel [Byte0]: 59
1776 13:59:02.624590 [Byte1]: 59
1777 13:59:02.629189
1778 13:59:02.629267 Set Vref, RX VrefLevel [Byte0]: 60
1779 13:59:02.632042 [Byte1]: 60
1780 13:59:02.636559
1781 13:59:02.636640 Set Vref, RX VrefLevel [Byte0]: 61
1782 13:59:02.639763 [Byte1]: 61
1783 13:59:02.644275
1784 13:59:02.644356 Set Vref, RX VrefLevel [Byte0]: 62
1785 13:59:02.647245 [Byte1]: 62
1786 13:59:02.652324
1787 13:59:02.652407 Set Vref, RX VrefLevel [Byte0]: 63
1788 13:59:02.654988 [Byte1]: 63
1789 13:59:02.659273
1790 13:59:02.659354 Set Vref, RX VrefLevel [Byte0]: 64
1791 13:59:02.662698 [Byte1]: 64
1792 13:59:02.667476
1793 13:59:02.667552 Set Vref, RX VrefLevel [Byte0]: 65
1794 13:59:02.670679 [Byte1]: 65
1795 13:59:02.674622
1796 13:59:02.674696 Set Vref, RX VrefLevel [Byte0]: 66
1797 13:59:02.678499 [Byte1]: 66
1798 13:59:02.682694
1799 13:59:02.682775 Set Vref, RX VrefLevel [Byte0]: 67
1800 13:59:02.685536 [Byte1]: 67
1801 13:59:02.689968
1802 13:59:02.690065 Set Vref, RX VrefLevel [Byte0]: 68
1803 13:59:02.693134 [Byte1]: 68
1804 13:59:02.697584
1805 13:59:02.697659 Set Vref, RX VrefLevel [Byte0]: 69
1806 13:59:02.700920 [Byte1]: 69
1807 13:59:02.705205
1808 13:59:02.705280 Set Vref, RX VrefLevel [Byte0]: 70
1809 13:59:02.708768 [Byte1]: 70
1810 13:59:02.713285
1811 13:59:02.713368 Set Vref, RX VrefLevel [Byte0]: 71
1812 13:59:02.716044 [Byte1]: 71
1813 13:59:02.720597
1814 13:59:02.720672 Set Vref, RX VrefLevel [Byte0]: 72
1815 13:59:02.723742 [Byte1]: 72
1816 13:59:02.728220
1817 13:59:02.728302 Set Vref, RX VrefLevel [Byte0]: 73
1818 13:59:02.731390 [Byte1]: 73
1819 13:59:02.736042
1820 13:59:02.736117 Set Vref, RX VrefLevel [Byte0]: 74
1821 13:59:02.739464 [Byte1]: 74
1822 13:59:02.743473
1823 13:59:02.743556 Set Vref, RX VrefLevel [Byte0]: 75
1824 13:59:02.747170 [Byte1]: 75
1825 13:59:02.751227
1826 13:59:02.751308 Set Vref, RX VrefLevel [Byte0]: 76
1827 13:59:02.754401 [Byte1]: 76
1828 13:59:02.758702
1829 13:59:02.758810 Final RX Vref Byte 0 = 54 to rank0
1830 13:59:02.762723 Final RX Vref Byte 1 = 54 to rank0
1831 13:59:02.765669 Final RX Vref Byte 0 = 54 to rank1
1832 13:59:02.769019 Final RX Vref Byte 1 = 54 to rank1==
1833 13:59:02.772527 Dram Type= 6, Freq= 0, CH_1, rank 0
1834 13:59:02.779264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 13:59:02.779348 ==
1836 13:59:02.779432 DQS Delay:
1837 13:59:02.779522 DQS0 = 0, DQS1 = 0
1838 13:59:02.782631 DQM Delay:
1839 13:59:02.782727 DQM0 = 80, DQM1 = 71
1840 13:59:02.786045 DQ Delay:
1841 13:59:02.789041 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1842 13:59:02.789124 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1843 13:59:02.792355 DQ8 =64, DQ9 =64, DQ10 =72, DQ11 =64
1844 13:59:02.795699 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1845 13:59:02.799579
1846 13:59:02.799660
1847 13:59:02.805442 [DQSOSCAuto] RK0, (LSB)MR18= 0x131d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1848 13:59:02.808998 CH1 RK0: MR19=606, MR18=131D
1849 13:59:02.815798 CH1_RK0: MR19=0x606, MR18=0x131D, DQSOSC=402, MR23=63, INC=91, DEC=60
1850 13:59:02.815881
1851 13:59:02.818748 ----->DramcWriteLeveling(PI) begin...
1852 13:59:02.818832 ==
1853 13:59:02.822187 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 13:59:02.825903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 13:59:02.825986 ==
1856 13:59:02.829239 Write leveling (Byte 0): 26 => 26
1857 13:59:02.832082 Write leveling (Byte 1): 31 => 31
1858 13:59:02.835719 DramcWriteLeveling(PI) end<-----
1859 13:59:02.835801
1860 13:59:02.835865 ==
1861 13:59:02.839066 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 13:59:02.842522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 13:59:02.842599 ==
1864 13:59:02.845872 [Gating] SW mode calibration
1865 13:59:02.852409 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1866 13:59:02.858923 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1867 13:59:02.862431 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1868 13:59:02.866010 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1869 13:59:02.872942 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1870 13:59:02.875582 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 13:59:02.878890 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 13:59:02.885642 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 13:59:02.889216 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 13:59:02.892650 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 13:59:02.895991 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 13:59:02.902940 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 13:59:02.906018 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 13:59:02.908889 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 13:59:02.916100 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 13:59:02.919100 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 13:59:02.922526 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 13:59:02.929017 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 13:59:02.932404 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 13:59:02.935810 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1885 13:59:02.942791 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1886 13:59:02.946126 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 13:59:02.949090 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 13:59:02.955953 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 13:59:02.959291 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 13:59:02.962836 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 13:59:02.969193 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 13:59:02.972412 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
1893 13:59:02.975805 0 9 8 | B1->B0 | 2f2f 3535 | 1 0 | (1 1) (0 0)
1894 13:59:02.982518 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 13:59:02.986138 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 13:59:02.989679 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 13:59:02.992264 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 13:59:02.999792 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 13:59:03.002560 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1900 13:59:03.005810 0 10 4 | B1->B0 | 3030 2b2b | 0 0 | (0 1) (1 1)
1901 13:59:03.012693 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1902 13:59:03.015826 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 13:59:03.018951 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 13:59:03.025751 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 13:59:03.029160 0 10 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1906 13:59:03.032521 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 13:59:03.039025 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 13:59:03.042706 0 11 4 | B1->B0 | 2f2f 3939 | 0 0 | (0 0) (0 0)
1909 13:59:03.045608 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 13:59:03.052356 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 13:59:03.055824 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 13:59:03.058912 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 13:59:03.066231 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 13:59:03.069335 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 13:59:03.072290 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 13:59:03.079278 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1917 13:59:03.082647 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1918 13:59:03.085708 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 13:59:03.089473 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 13:59:03.095785 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 13:59:03.099083 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 13:59:03.103080 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 13:59:03.109067 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 13:59:03.112484 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 13:59:03.116110 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 13:59:03.122578 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 13:59:03.125938 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 13:59:03.129179 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 13:59:03.135750 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 13:59:03.139375 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 13:59:03.143138 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 13:59:03.149339 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1933 13:59:03.152700 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1934 13:59:03.156174 Total UI for P1: 0, mck2ui 16
1935 13:59:03.159324 best dqsien dly found for B0: ( 0, 14, 4)
1936 13:59:03.162878 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 13:59:03.166118 Total UI for P1: 0, mck2ui 16
1938 13:59:03.169283 best dqsien dly found for B1: ( 0, 14, 6)
1939 13:59:03.172775 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1940 13:59:03.176107 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1941 13:59:03.176183
1942 13:59:03.179200 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1943 13:59:03.182567 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1944 13:59:03.186023 [Gating] SW calibration Done
1945 13:59:03.186098 ==
1946 13:59:03.189441 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 13:59:03.192882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 13:59:03.195874 ==
1949 13:59:03.195949 RX Vref Scan: 0
1950 13:59:03.196013
1951 13:59:03.199379 RX Vref 0 -> 0, step: 1
1952 13:59:03.199493
1953 13:59:03.202679 RX Delay -130 -> 252, step: 16
1954 13:59:03.206186 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1955 13:59:03.209285 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1956 13:59:03.212831 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1957 13:59:03.216155 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1958 13:59:03.222861 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1959 13:59:03.226296 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1960 13:59:03.229197 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1961 13:59:03.232618 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1962 13:59:03.236501 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1963 13:59:03.243064 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1964 13:59:03.245878 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1965 13:59:03.249313 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1966 13:59:03.252473 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1967 13:59:03.255939 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1968 13:59:03.262273 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1969 13:59:03.265821 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1970 13:59:03.265903 ==
1971 13:59:03.269451 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 13:59:03.272048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 13:59:03.272125 ==
1974 13:59:03.275871 DQS Delay:
1975 13:59:03.275947 DQS0 = 0, DQS1 = 0
1976 13:59:03.276018 DQM Delay:
1977 13:59:03.279177 DQM0 = 79, DQM1 = 73
1978 13:59:03.279251 DQ Delay:
1979 13:59:03.282469 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1980 13:59:03.285590 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1981 13:59:03.289244 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1982 13:59:03.292642 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1983 13:59:03.292725
1984 13:59:03.292788
1985 13:59:03.292847 ==
1986 13:59:03.296040 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 13:59:03.302353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 13:59:03.302432 ==
1989 13:59:03.302505
1990 13:59:03.302565
1991 13:59:03.302654 TX Vref Scan disable
1992 13:59:03.305926 == TX Byte 0 ==
1993 13:59:03.309127 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1994 13:59:03.315985 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1995 13:59:03.316064 == TX Byte 1 ==
1996 13:59:03.319477 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1997 13:59:03.325972 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1998 13:59:03.326060 ==
1999 13:59:03.329477 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 13:59:03.332585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 13:59:03.332668 ==
2002 13:59:03.345680 TX Vref=22, minBit 9, minWin=27, winSum=450
2003 13:59:03.348746 TX Vref=24, minBit 3, minWin=28, winSum=456
2004 13:59:03.352036 TX Vref=26, minBit 0, minWin=28, winSum=456
2005 13:59:03.355671 TX Vref=28, minBit 3, minWin=28, winSum=458
2006 13:59:03.359052 TX Vref=30, minBit 3, minWin=28, winSum=462
2007 13:59:03.362223 TX Vref=32, minBit 2, minWin=28, winSum=457
2008 13:59:03.368911 [TxChooseVref] Worse bit 3, Min win 28, Win sum 462, Final Vref 30
2009 13:59:03.368994
2010 13:59:03.372204 Final TX Range 1 Vref 30
2011 13:59:03.372287
2012 13:59:03.372352 ==
2013 13:59:03.375464 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 13:59:03.379062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 13:59:03.379146 ==
2016 13:59:03.379211
2017 13:59:03.382106
2018 13:59:03.382188 TX Vref Scan disable
2019 13:59:03.385501 == TX Byte 0 ==
2020 13:59:03.388990 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2021 13:59:03.395276 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2022 13:59:03.395359 == TX Byte 1 ==
2023 13:59:03.398674 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2024 13:59:03.405425 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2025 13:59:03.405507
2026 13:59:03.405571 [DATLAT]
2027 13:59:03.405630 Freq=800, CH1 RK1
2028 13:59:03.405689
2029 13:59:03.408790 DATLAT Default: 0xa
2030 13:59:03.408872 0, 0xFFFF, sum = 0
2031 13:59:03.412583 1, 0xFFFF, sum = 0
2032 13:59:03.412681 2, 0xFFFF, sum = 0
2033 13:59:03.415622 3, 0xFFFF, sum = 0
2034 13:59:03.415705 4, 0xFFFF, sum = 0
2035 13:59:03.419179 5, 0xFFFF, sum = 0
2036 13:59:03.419262 6, 0xFFFF, sum = 0
2037 13:59:03.422416 7, 0xFFFF, sum = 0
2038 13:59:03.425725 8, 0xFFFF, sum = 0
2039 13:59:03.425809 9, 0x0, sum = 1
2040 13:59:03.425875 10, 0x0, sum = 2
2041 13:59:03.429029 11, 0x0, sum = 3
2042 13:59:03.429112 12, 0x0, sum = 4
2043 13:59:03.432165 best_step = 10
2044 13:59:03.432247
2045 13:59:03.432311 ==
2046 13:59:03.435651 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 13:59:03.439190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 13:59:03.439273 ==
2049 13:59:03.442096 RX Vref Scan: 0
2050 13:59:03.442179
2051 13:59:03.442243 RX Vref 0 -> 0, step: 1
2052 13:59:03.442303
2053 13:59:03.445558 RX Delay -111 -> 252, step: 8
2054 13:59:03.452270 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2055 13:59:03.455582 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2056 13:59:03.459312 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2057 13:59:03.462420 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2058 13:59:03.465770 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2059 13:59:03.472042 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2060 13:59:03.475688 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2061 13:59:03.479063 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2062 13:59:03.482070 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2063 13:59:03.485609 iDelay=209, Bit 9, Center 60 (-63 ~ 184) 248
2064 13:59:03.492613 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2065 13:59:03.495617 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2066 13:59:03.498922 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2067 13:59:03.502446 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2068 13:59:03.506128 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2069 13:59:03.512551 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2070 13:59:03.512634 ==
2071 13:59:03.515643 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 13:59:03.518954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 13:59:03.519037 ==
2074 13:59:03.519127 DQS Delay:
2075 13:59:03.522501 DQS0 = 0, DQS1 = 0
2076 13:59:03.522582 DQM Delay:
2077 13:59:03.525956 DQM0 = 77, DQM1 = 72
2078 13:59:03.526038 DQ Delay:
2079 13:59:03.529085 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2080 13:59:03.532544 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2081 13:59:03.535688 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64
2082 13:59:03.538719 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76
2083 13:59:03.538801
2084 13:59:03.538866
2085 13:59:03.548965 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2086 13:59:03.549048 CH1 RK1: MR19=606, MR18=2139
2087 13:59:03.555382 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2088 13:59:03.559168 [RxdqsGatingPostProcess] freq 800
2089 13:59:03.565369 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 13:59:03.568991 Pre-setting of DQS Precalculation
2091 13:59:03.572117 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 13:59:03.579180 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 13:59:03.585769 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 13:59:03.585851
2095 13:59:03.588646
2096 13:59:03.588724 [Calibration Summary] 1600 Mbps
2097 13:59:03.592581 CH 0, Rank 0
2098 13:59:03.592652 SW Impedance : PASS
2099 13:59:03.595458 DUTY Scan : NO K
2100 13:59:03.598834 ZQ Calibration : PASS
2101 13:59:03.598904 Jitter Meter : NO K
2102 13:59:03.602136 CBT Training : PASS
2103 13:59:03.605535 Write leveling : PASS
2104 13:59:03.605609 RX DQS gating : PASS
2105 13:59:03.608906 RX DQ/DQS(RDDQC) : PASS
2106 13:59:03.612209 TX DQ/DQS : PASS
2107 13:59:03.612283 RX DATLAT : PASS
2108 13:59:03.615703 RX DQ/DQS(Engine): PASS
2109 13:59:03.615786 TX OE : NO K
2110 13:59:03.618848 All Pass.
2111 13:59:03.618918
2112 13:59:03.618995 CH 0, Rank 1
2113 13:59:03.622325 SW Impedance : PASS
2114 13:59:03.622398 DUTY Scan : NO K
2115 13:59:03.625508 ZQ Calibration : PASS
2116 13:59:03.628686 Jitter Meter : NO K
2117 13:59:03.628774 CBT Training : PASS
2118 13:59:03.632425 Write leveling : PASS
2119 13:59:03.635311 RX DQS gating : PASS
2120 13:59:03.635390 RX DQ/DQS(RDDQC) : PASS
2121 13:59:03.638873 TX DQ/DQS : PASS
2122 13:59:03.642412 RX DATLAT : PASS
2123 13:59:03.642485 RX DQ/DQS(Engine): PASS
2124 13:59:03.645859 TX OE : NO K
2125 13:59:03.645933 All Pass.
2126 13:59:03.645995
2127 13:59:03.648554 CH 1, Rank 0
2128 13:59:03.648626 SW Impedance : PASS
2129 13:59:03.652127 DUTY Scan : NO K
2130 13:59:03.655648 ZQ Calibration : PASS
2131 13:59:03.655722 Jitter Meter : NO K
2132 13:59:03.659007 CBT Training : PASS
2133 13:59:03.661997 Write leveling : PASS
2134 13:59:03.662075 RX DQS gating : PASS
2135 13:59:03.665644 RX DQ/DQS(RDDQC) : PASS
2136 13:59:03.665730 TX DQ/DQS : PASS
2137 13:59:03.668647 RX DATLAT : PASS
2138 13:59:03.671904 RX DQ/DQS(Engine): PASS
2139 13:59:03.671980 TX OE : NO K
2140 13:59:03.675570 All Pass.
2141 13:59:03.675644
2142 13:59:03.675705 CH 1, Rank 1
2143 13:59:03.678804 SW Impedance : PASS
2144 13:59:03.678882 DUTY Scan : NO K
2145 13:59:03.682361 ZQ Calibration : PASS
2146 13:59:03.685434 Jitter Meter : NO K
2147 13:59:03.685506 CBT Training : PASS
2148 13:59:03.688784 Write leveling : PASS
2149 13:59:03.692229 RX DQS gating : PASS
2150 13:59:03.692306 RX DQ/DQS(RDDQC) : PASS
2151 13:59:03.695576 TX DQ/DQS : PASS
2152 13:59:03.698938 RX DATLAT : PASS
2153 13:59:03.699021 RX DQ/DQS(Engine): PASS
2154 13:59:03.701985 TX OE : NO K
2155 13:59:03.702067 All Pass.
2156 13:59:03.702132
2157 13:59:03.705220 DramC Write-DBI off
2158 13:59:03.709058 PER_BANK_REFRESH: Hybrid Mode
2159 13:59:03.709142 TX_TRACKING: ON
2160 13:59:03.712368 [GetDramInforAfterCalByMRR] Vendor 6.
2161 13:59:03.715368 [GetDramInforAfterCalByMRR] Revision 606.
2162 13:59:03.719010 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 13:59:03.722008 MR0 0x3b3b
2164 13:59:03.722107 MR8 0x5151
2165 13:59:03.725285 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 13:59:03.725368
2167 13:59:03.725431 MR0 0x3b3b
2168 13:59:03.728746 MR8 0x5151
2169 13:59:03.731955 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 13:59:03.732038
2171 13:59:03.739009 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 13:59:03.745641 [FAST_K] Save calibration result to emmc
2173 13:59:03.748673 [FAST_K] Save calibration result to emmc
2174 13:59:03.748756 dram_init: config_dvfs: 1
2175 13:59:03.755374 dramc_set_vcore_voltage set vcore to 662500
2176 13:59:03.755480 Read voltage for 1200, 2
2177 13:59:03.755545 Vio18 = 0
2178 13:59:03.758984 Vcore = 662500
2179 13:59:03.759066 Vdram = 0
2180 13:59:03.759132 Vddq = 0
2181 13:59:03.761899 Vmddr = 0
2182 13:59:03.765739 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 13:59:03.772186 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 13:59:03.772268 MEM_TYPE=3, freq_sel=15
2185 13:59:03.775558 sv_algorithm_assistance_LP4_1600
2186 13:59:03.781972 ============ PULL DRAM RESETB DOWN ============
2187 13:59:03.785222 ========== PULL DRAM RESETB DOWN end =========
2188 13:59:03.788505 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 13:59:03.791858 ===================================
2190 13:59:03.795142 LPDDR4 DRAM CONFIGURATION
2191 13:59:03.798672 ===================================
2192 13:59:03.802032 EX_ROW_EN[0] = 0x0
2193 13:59:03.802127 EX_ROW_EN[1] = 0x0
2194 13:59:03.805325 LP4Y_EN = 0x0
2195 13:59:03.805397 WORK_FSP = 0x0
2196 13:59:03.808875 WL = 0x4
2197 13:59:03.808949 RL = 0x4
2198 13:59:03.812164 BL = 0x2
2199 13:59:03.812259 RPST = 0x0
2200 13:59:03.815380 RD_PRE = 0x0
2201 13:59:03.815483 WR_PRE = 0x1
2202 13:59:03.819058 WR_PST = 0x0
2203 13:59:03.819134 DBI_WR = 0x0
2204 13:59:03.822060 DBI_RD = 0x0
2205 13:59:03.822133 OTF = 0x1
2206 13:59:03.825603 ===================================
2207 13:59:03.828645 ===================================
2208 13:59:03.832052 ANA top config
2209 13:59:03.835234 ===================================
2210 13:59:03.835338 DLL_ASYNC_EN = 0
2211 13:59:03.838681 ALL_SLAVE_EN = 0
2212 13:59:03.842187 NEW_RANK_MODE = 1
2213 13:59:03.845857 DLL_IDLE_MODE = 1
2214 13:59:03.848683 LP45_APHY_COMB_EN = 1
2215 13:59:03.848765 TX_ODT_DIS = 1
2216 13:59:03.852128 NEW_8X_MODE = 1
2217 13:59:03.855655 ===================================
2218 13:59:03.858761 ===================================
2219 13:59:03.862412 data_rate = 2400
2220 13:59:03.865513 CKR = 1
2221 13:59:03.868880 DQ_P2S_RATIO = 8
2222 13:59:03.872264 ===================================
2223 13:59:03.872345 CA_P2S_RATIO = 8
2224 13:59:03.875566 DQ_CA_OPEN = 0
2225 13:59:03.879250 DQ_SEMI_OPEN = 0
2226 13:59:03.882286 CA_SEMI_OPEN = 0
2227 13:59:03.885375 CA_FULL_RATE = 0
2228 13:59:03.889430 DQ_CKDIV4_EN = 0
2229 13:59:03.889507 CA_CKDIV4_EN = 0
2230 13:59:03.892054 CA_PREDIV_EN = 0
2231 13:59:03.895793 PH8_DLY = 17
2232 13:59:03.899022 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 13:59:03.902103 DQ_AAMCK_DIV = 4
2234 13:59:03.905488 CA_AAMCK_DIV = 4
2235 13:59:03.905569 CA_ADMCK_DIV = 4
2236 13:59:03.908579 DQ_TRACK_CA_EN = 0
2237 13:59:03.912091 CA_PICK = 1200
2238 13:59:03.915481 CA_MCKIO = 1200
2239 13:59:03.919043 MCKIO_SEMI = 0
2240 13:59:03.921953 PLL_FREQ = 2366
2241 13:59:03.925675 DQ_UI_PI_RATIO = 32
2242 13:59:03.925753 CA_UI_PI_RATIO = 0
2243 13:59:03.929039 ===================================
2244 13:59:03.932591 ===================================
2245 13:59:03.935172 memory_type:LPDDR4
2246 13:59:03.938846 GP_NUM : 10
2247 13:59:03.938927 SRAM_EN : 1
2248 13:59:03.942096 MD32_EN : 0
2249 13:59:03.945258 ===================================
2250 13:59:03.948586 [ANA_INIT] >>>>>>>>>>>>>>
2251 13:59:03.951948 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 13:59:03.955554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 13:59:03.958953 ===================================
2254 13:59:03.959040 data_rate = 2400,PCW = 0X5b00
2255 13:59:03.962158 ===================================
2256 13:59:03.965480 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 13:59:03.972087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 13:59:03.978980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 13:59:03.982057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 13:59:03.985452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 13:59:03.989061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 13:59:03.992414 [ANA_INIT] flow start
2263 13:59:03.992488 [ANA_INIT] PLL >>>>>>>>
2264 13:59:03.995531 [ANA_INIT] PLL <<<<<<<<
2265 13:59:03.999172 [ANA_INIT] MIDPI >>>>>>>>
2266 13:59:03.999254 [ANA_INIT] MIDPI <<<<<<<<
2267 13:59:04.002612 [ANA_INIT] DLL >>>>>>>>
2268 13:59:04.006044 [ANA_INIT] DLL <<<<<<<<
2269 13:59:04.006117 [ANA_INIT] flow end
2270 13:59:04.012034 ============ LP4 DIFF to SE enter ============
2271 13:59:04.015401 ============ LP4 DIFF to SE exit ============
2272 13:59:04.019042 [ANA_INIT] <<<<<<<<<<<<<
2273 13:59:04.022345 [Flow] Enable top DCM control >>>>>
2274 13:59:04.025373 [Flow] Enable top DCM control <<<<<
2275 13:59:04.025462 Enable DLL master slave shuffle
2276 13:59:04.031979 ==============================================================
2277 13:59:04.035337 Gating Mode config
2278 13:59:04.038687 ==============================================================
2279 13:59:04.042268 Config description:
2280 13:59:04.052070 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 13:59:04.058617 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 13:59:04.061955 SELPH_MODE 0: By rank 1: By Phase
2283 13:59:04.069004 ==============================================================
2284 13:59:04.072063 GAT_TRACK_EN = 1
2285 13:59:04.075726 RX_GATING_MODE = 2
2286 13:59:04.079307 RX_GATING_TRACK_MODE = 2
2287 13:59:04.079380 SELPH_MODE = 1
2288 13:59:04.082175 PICG_EARLY_EN = 1
2289 13:59:04.085311 VALID_LAT_VALUE = 1
2290 13:59:04.091925 ==============================================================
2291 13:59:04.095715 Enter into Gating configuration >>>>
2292 13:59:04.098572 Exit from Gating configuration <<<<
2293 13:59:04.102126 Enter into DVFS_PRE_config >>>>>
2294 13:59:04.112106 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 13:59:04.115538 Exit from DVFS_PRE_config <<<<<
2296 13:59:04.119148 Enter into PICG configuration >>>>
2297 13:59:04.122052 Exit from PICG configuration <<<<
2298 13:59:04.125946 [RX_INPUT] configuration >>>>>
2299 13:59:04.128641 [RX_INPUT] configuration <<<<<
2300 13:59:04.131897 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 13:59:04.138604 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 13:59:04.145299 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 13:59:04.152043 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 13:59:04.155745 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 13:59:04.162072 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 13:59:04.165551 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 13:59:04.171825 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 13:59:04.175420 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 13:59:04.178852 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 13:59:04.182293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 13:59:04.188741 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 13:59:04.191911 ===================================
2313 13:59:04.191995 LPDDR4 DRAM CONFIGURATION
2314 13:59:04.195324 ===================================
2315 13:59:04.198601 EX_ROW_EN[0] = 0x0
2316 13:59:04.202461 EX_ROW_EN[1] = 0x0
2317 13:59:04.202544 LP4Y_EN = 0x0
2318 13:59:04.205882 WORK_FSP = 0x0
2319 13:59:04.205971 WL = 0x4
2320 13:59:04.209016 RL = 0x4
2321 13:59:04.209103 BL = 0x2
2322 13:59:04.212236 RPST = 0x0
2323 13:59:04.212346 RD_PRE = 0x0
2324 13:59:04.215673 WR_PRE = 0x1
2325 13:59:04.215756 WR_PST = 0x0
2326 13:59:04.218864 DBI_WR = 0x0
2327 13:59:04.218948 DBI_RD = 0x0
2328 13:59:04.222463 OTF = 0x1
2329 13:59:04.225362 ===================================
2330 13:59:04.228674 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 13:59:04.232264 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 13:59:04.238540 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 13:59:04.242150 ===================================
2334 13:59:04.242235 LPDDR4 DRAM CONFIGURATION
2335 13:59:04.245161 ===================================
2336 13:59:04.248376 EX_ROW_EN[0] = 0x10
2337 13:59:04.251728 EX_ROW_EN[1] = 0x0
2338 13:59:04.251811 LP4Y_EN = 0x0
2339 13:59:04.255211 WORK_FSP = 0x0
2340 13:59:04.255295 WL = 0x4
2341 13:59:04.258550 RL = 0x4
2342 13:59:04.258633 BL = 0x2
2343 13:59:04.261965 RPST = 0x0
2344 13:59:04.262048 RD_PRE = 0x0
2345 13:59:04.265470 WR_PRE = 0x1
2346 13:59:04.265580 WR_PST = 0x0
2347 13:59:04.268480 DBI_WR = 0x0
2348 13:59:04.268576 DBI_RD = 0x0
2349 13:59:04.271842 OTF = 0x1
2350 13:59:04.275136 ===================================
2351 13:59:04.282080 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 13:59:04.282160 ==
2353 13:59:04.285529 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 13:59:04.288535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 13:59:04.288616 ==
2356 13:59:04.292201 [Duty_Offset_Calibration]
2357 13:59:04.292281 B0:2 B1:0 CA:3
2358 13:59:04.292344
2359 13:59:04.295016 [DutyScan_Calibration_Flow] k_type=0
2360 13:59:04.304715
2361 13:59:04.304798 ==CLK 0==
2362 13:59:04.308231 Final CLK duty delay cell = 0
2363 13:59:04.312139 [0] MAX Duty = 5031%(X100), DQS PI = 12
2364 13:59:04.315115 [0] MIN Duty = 4906%(X100), DQS PI = 8
2365 13:59:04.315197 [0] AVG Duty = 4968%(X100)
2366 13:59:04.315261
2367 13:59:04.318370 CH0 CLK Duty spec in!! Max-Min= 125%
2368 13:59:04.325357 [DutyScan_Calibration_Flow] ====Done====
2369 13:59:04.325508
2370 13:59:04.328215 [DutyScan_Calibration_Flow] k_type=1
2371 13:59:04.343356
2372 13:59:04.343479 ==DQS 0 ==
2373 13:59:04.346963 Final DQS duty delay cell = 0
2374 13:59:04.350359 [0] MAX Duty = 5093%(X100), DQS PI = 12
2375 13:59:04.353214 [0] MIN Duty = 4907%(X100), DQS PI = 2
2376 13:59:04.353296 [0] AVG Duty = 5000%(X100)
2377 13:59:04.356996
2378 13:59:04.357097 ==DQS 1 ==
2379 13:59:04.360216 Final DQS duty delay cell = -4
2380 13:59:04.363531 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2381 13:59:04.366677 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2382 13:59:04.370675 [-4] AVG Duty = 4953%(X100)
2383 13:59:04.370756
2384 13:59:04.373631 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2385 13:59:04.373713
2386 13:59:04.377200 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2387 13:59:04.380657 [DutyScan_Calibration_Flow] ====Done====
2388 13:59:04.380787
2389 13:59:04.383311 [DutyScan_Calibration_Flow] k_type=3
2390 13:59:04.400544
2391 13:59:04.400646 ==DQM 0 ==
2392 13:59:04.403992 Final DQM duty delay cell = 0
2393 13:59:04.407156 [0] MAX Duty = 5124%(X100), DQS PI = 28
2394 13:59:04.410750 [0] MIN Duty = 4876%(X100), DQS PI = 48
2395 13:59:04.413869 [0] AVG Duty = 5000%(X100)
2396 13:59:04.413951
2397 13:59:04.414015 ==DQM 1 ==
2398 13:59:04.417187 Final DQM duty delay cell = 4
2399 13:59:04.421205 [4] MAX Duty = 5124%(X100), DQS PI = 50
2400 13:59:04.423894 [4] MIN Duty = 5000%(X100), DQS PI = 14
2401 13:59:04.427685 [4] AVG Duty = 5062%(X100)
2402 13:59:04.427767
2403 13:59:04.430640 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2404 13:59:04.430736
2405 13:59:04.434027 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2406 13:59:04.437663 [DutyScan_Calibration_Flow] ====Done====
2407 13:59:04.437742
2408 13:59:04.440651 [DutyScan_Calibration_Flow] k_type=2
2409 13:59:04.455611
2410 13:59:04.455714 ==DQ 0 ==
2411 13:59:04.458942 Final DQ duty delay cell = -4
2412 13:59:04.462167 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2413 13:59:04.465633 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2414 13:59:04.469063 [-4] AVG Duty = 4969%(X100)
2415 13:59:04.469135
2416 13:59:04.469196 ==DQ 1 ==
2417 13:59:04.472245 Final DQ duty delay cell = -4
2418 13:59:04.475710 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2419 13:59:04.479271 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2420 13:59:04.482404 [-4] AVG Duty = 4938%(X100)
2421 13:59:04.482476
2422 13:59:04.485711 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2423 13:59:04.485795
2424 13:59:04.489246 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2425 13:59:04.492173 [DutyScan_Calibration_Flow] ====Done====
2426 13:59:04.492298 ==
2427 13:59:04.496010 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 13:59:04.499073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 13:59:04.499156 ==
2430 13:59:04.502306 [Duty_Offset_Calibration]
2431 13:59:04.502388 B0:1 B1:-2 CA:0
2432 13:59:04.502453
2433 13:59:04.505924 [DutyScan_Calibration_Flow] k_type=0
2434 13:59:04.516300
2435 13:59:04.516409 ==CLK 0==
2436 13:59:04.519754 Final CLK duty delay cell = 0
2437 13:59:04.522983 [0] MAX Duty = 5031%(X100), DQS PI = 50
2438 13:59:04.526600 [0] MIN Duty = 4844%(X100), DQS PI = 26
2439 13:59:04.526683 [0] AVG Duty = 4937%(X100)
2440 13:59:04.526748
2441 13:59:04.529643 CH1 CLK Duty spec in!! Max-Min= 187%
2442 13:59:04.536307 [DutyScan_Calibration_Flow] ====Done====
2443 13:59:04.536390
2444 13:59:04.539845 [DutyScan_Calibration_Flow] k_type=1
2445 13:59:04.554533
2446 13:59:04.554618 ==DQS 0 ==
2447 13:59:04.558095 Final DQS duty delay cell = -4
2448 13:59:04.561611 [-4] MAX Duty = 5031%(X100), DQS PI = 56
2449 13:59:04.564853 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2450 13:59:04.568403 [-4] AVG Duty = 4969%(X100)
2451 13:59:04.568485
2452 13:59:04.568550 ==DQS 1 ==
2453 13:59:04.571515 Final DQS duty delay cell = 0
2454 13:59:04.575145 [0] MAX Duty = 5093%(X100), DQS PI = 32
2455 13:59:04.578020 [0] MIN Duty = 4875%(X100), DQS PI = 10
2456 13:59:04.581613 [0] AVG Duty = 4984%(X100)
2457 13:59:04.581695
2458 13:59:04.584437 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2459 13:59:04.584520
2460 13:59:04.588436 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2461 13:59:04.591408 [DutyScan_Calibration_Flow] ====Done====
2462 13:59:04.591531
2463 13:59:04.594373 [DutyScan_Calibration_Flow] k_type=3
2464 13:59:04.612344
2465 13:59:04.612427 ==DQM 0 ==
2466 13:59:04.616003 Final DQM duty delay cell = 4
2467 13:59:04.618836 [4] MAX Duty = 5156%(X100), DQS PI = 54
2468 13:59:04.622332 [4] MIN Duty = 5031%(X100), DQS PI = 20
2469 13:59:04.625745 [4] AVG Duty = 5093%(X100)
2470 13:59:04.625827
2471 13:59:04.625893 ==DQM 1 ==
2472 13:59:04.628818 Final DQM duty delay cell = 0
2473 13:59:04.632232 [0] MAX Duty = 5031%(X100), DQS PI = 4
2474 13:59:04.635720 [0] MIN Duty = 4907%(X100), DQS PI = 32
2475 13:59:04.639003 [0] AVG Duty = 4969%(X100)
2476 13:59:04.639125
2477 13:59:04.641899 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2478 13:59:04.642009
2479 13:59:04.645304 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2480 13:59:04.649249 [DutyScan_Calibration_Flow] ====Done====
2481 13:59:04.649354
2482 13:59:04.652176 [DutyScan_Calibration_Flow] k_type=2
2483 13:59:04.668805
2484 13:59:04.668887 ==DQ 0 ==
2485 13:59:04.671848 Final DQ duty delay cell = 0
2486 13:59:04.675194 [0] MAX Duty = 5062%(X100), DQS PI = 0
2487 13:59:04.678408 [0] MIN Duty = 4938%(X100), DQS PI = 22
2488 13:59:04.678485 [0] AVG Duty = 5000%(X100)
2489 13:59:04.678551
2490 13:59:04.682051 ==DQ 1 ==
2491 13:59:04.685305 Final DQ duty delay cell = 0
2492 13:59:04.688706 [0] MAX Duty = 5125%(X100), DQS PI = 14
2493 13:59:04.692000 [0] MIN Duty = 4969%(X100), DQS PI = 58
2494 13:59:04.692084 [0] AVG Duty = 5047%(X100)
2495 13:59:04.692149
2496 13:59:04.698293 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2497 13:59:04.698376
2498 13:59:04.702002 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2499 13:59:04.705232 [DutyScan_Calibration_Flow] ====Done====
2500 13:59:04.708657 nWR fixed to 30
2501 13:59:04.708740 [ModeRegInit_LP4] CH0 RK0
2502 13:59:04.712137 [ModeRegInit_LP4] CH0 RK1
2503 13:59:04.715133 [ModeRegInit_LP4] CH1 RK0
2504 13:59:04.715233 [ModeRegInit_LP4] CH1 RK1
2505 13:59:04.718470 match AC timing 7
2506 13:59:04.721705 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 13:59:04.728334 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 13:59:04.731546 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 13:59:04.734954 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 13:59:04.741917 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 13:59:04.742014 ==
2512 13:59:04.744964 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 13:59:04.748470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 13:59:04.748554 ==
2515 13:59:04.754912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 13:59:04.761533 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 13:59:04.768447 [CA 0] Center 40 (10~71) winsize 62
2518 13:59:04.772024 [CA 1] Center 39 (9~70) winsize 62
2519 13:59:04.775630 [CA 2] Center 36 (6~66) winsize 61
2520 13:59:04.778776 [CA 3] Center 35 (5~66) winsize 62
2521 13:59:04.782018 [CA 4] Center 34 (4~65) winsize 62
2522 13:59:04.785365 [CA 5] Center 33 (3~64) winsize 62
2523 13:59:04.785470
2524 13:59:04.788558 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2525 13:59:04.788657
2526 13:59:04.791896 [CATrainingPosCal] consider 1 rank data
2527 13:59:04.795242 u2DelayCellTimex100 = 270/100 ps
2528 13:59:04.798816 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2529 13:59:04.805340 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2530 13:59:04.808637 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2531 13:59:04.811889 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2532 13:59:04.815320 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2533 13:59:04.818604 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2534 13:59:04.818688
2535 13:59:04.822059 CA PerBit enable=1, Macro0, CA PI delay=33
2536 13:59:04.822141
2537 13:59:04.825631 [CBTSetCACLKResult] CA Dly = 33
2538 13:59:04.825736 CS Dly: 7 (0~38)
2539 13:59:04.828551 ==
2540 13:59:04.828634 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 13:59:04.835569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 13:59:04.835652 ==
2543 13:59:04.838922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 13:59:04.845176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2545 13:59:04.854960 [CA 0] Center 40 (10~70) winsize 61
2546 13:59:04.858406 [CA 1] Center 39 (9~70) winsize 62
2547 13:59:04.861804 [CA 2] Center 35 (5~66) winsize 62
2548 13:59:04.864623 [CA 3] Center 35 (5~66) winsize 62
2549 13:59:04.868305 [CA 4] Center 34 (4~65) winsize 62
2550 13:59:04.871240 [CA 5] Center 33 (3~64) winsize 62
2551 13:59:04.871373
2552 13:59:04.874707 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2553 13:59:04.874820
2554 13:59:04.877937 [CATrainingPosCal] consider 2 rank data
2555 13:59:04.881666 u2DelayCellTimex100 = 270/100 ps
2556 13:59:04.885085 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2557 13:59:04.891555 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2558 13:59:04.895010 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2559 13:59:04.898321 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2560 13:59:04.901243 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2561 13:59:04.905351 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2562 13:59:04.905436
2563 13:59:04.908398 CA PerBit enable=1, Macro0, CA PI delay=33
2564 13:59:04.908474
2565 13:59:04.911358 [CBTSetCACLKResult] CA Dly = 33
2566 13:59:04.911458 CS Dly: 8 (0~40)
2567 13:59:04.914480
2568 13:59:04.918067 ----->DramcWriteLeveling(PI) begin...
2569 13:59:04.918237 ==
2570 13:59:04.921296 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 13:59:04.924865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 13:59:04.924954 ==
2573 13:59:04.928180 Write leveling (Byte 0): 31 => 31
2574 13:59:04.931655 Write leveling (Byte 1): 29 => 29
2575 13:59:04.934586 DramcWriteLeveling(PI) end<-----
2576 13:59:04.934674
2577 13:59:04.934790 ==
2578 13:59:04.938011 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 13:59:04.941355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 13:59:04.941487 ==
2581 13:59:04.944456 [Gating] SW mode calibration
2582 13:59:04.951927 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 13:59:04.958054 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 13:59:04.961755 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 13:59:04.964949 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2586 13:59:04.968457 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 13:59:04.974885 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 13:59:04.977872 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 13:59:04.981384 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 13:59:04.988077 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 13:59:04.991590 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2592 13:59:04.994707 1 0 0 | B1->B0 | 3232 2727 | 1 0 | (1 0) (1 0)
2593 13:59:05.001632 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2594 13:59:05.004978 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 13:59:05.008470 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 13:59:05.014677 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 13:59:05.018022 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 13:59:05.021374 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 13:59:05.028460 1 0 28 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
2600 13:59:05.031403 1 1 0 | B1->B0 | 2929 3838 | 0 1 | (0 0) (0 0)
2601 13:59:05.034492 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2602 13:59:05.041259 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 13:59:05.044509 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 13:59:05.047939 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 13:59:05.054707 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 13:59:05.058324 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 13:59:05.061128 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 13:59:05.065063 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2609 13:59:05.071202 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2610 13:59:05.074942 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 13:59:05.077816 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 13:59:05.084686 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 13:59:05.087904 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 13:59:05.091585 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 13:59:05.098135 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 13:59:05.101343 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 13:59:05.104811 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 13:59:05.111403 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 13:59:05.114554 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 13:59:05.117985 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 13:59:05.124776 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 13:59:05.128211 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 13:59:05.131375 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 13:59:05.137938 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2625 13:59:05.141123 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2626 13:59:05.144474 Total UI for P1: 0, mck2ui 16
2627 13:59:05.148455 best dqsien dly found for B0: ( 1, 3, 30)
2628 13:59:05.151456 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 13:59:05.154679 Total UI for P1: 0, mck2ui 16
2630 13:59:05.158073 best dqsien dly found for B1: ( 1, 4, 2)
2631 13:59:05.161224 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2632 13:59:05.164802 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2633 13:59:05.164909
2634 13:59:05.168033 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2635 13:59:05.171330 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2636 13:59:05.174899 [Gating] SW calibration Done
2637 13:59:05.175013 ==
2638 13:59:05.178171 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 13:59:05.184772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 13:59:05.184888 ==
2641 13:59:05.184987 RX Vref Scan: 0
2642 13:59:05.185078
2643 13:59:05.188151 RX Vref 0 -> 0, step: 1
2644 13:59:05.188252
2645 13:59:05.191247 RX Delay -40 -> 252, step: 8
2646 13:59:05.194971 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2647 13:59:05.198073 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2648 13:59:05.201326 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2649 13:59:05.204647 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2650 13:59:05.211179 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2651 13:59:05.215016 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2652 13:59:05.218130 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2653 13:59:05.221653 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2654 13:59:05.224763 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2655 13:59:05.227914 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2656 13:59:05.234621 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2657 13:59:05.238207 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2658 13:59:05.241613 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2659 13:59:05.244839 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2660 13:59:05.248598 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2661 13:59:05.255065 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2662 13:59:05.255208 ==
2663 13:59:05.258622 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 13:59:05.261655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 13:59:05.261757 ==
2666 13:59:05.261853 DQS Delay:
2667 13:59:05.264644 DQS0 = 0, DQS1 = 0
2668 13:59:05.264733 DQM Delay:
2669 13:59:05.268007 DQM0 = 112, DQM1 = 103
2670 13:59:05.268098 DQ Delay:
2671 13:59:05.271630 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2672 13:59:05.274819 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2673 13:59:05.278323 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2674 13:59:05.281761 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2675 13:59:05.281880
2676 13:59:05.281984
2677 13:59:05.284945 ==
2678 13:59:05.285067 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 13:59:05.291375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 13:59:05.291560 ==
2681 13:59:05.291665
2682 13:59:05.291755
2683 13:59:05.295028 TX Vref Scan disable
2684 13:59:05.295161 == TX Byte 0 ==
2685 13:59:05.298162 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2686 13:59:05.305030 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2687 13:59:05.305210 == TX Byte 1 ==
2688 13:59:05.308042 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2689 13:59:05.314996 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2690 13:59:05.315183 ==
2691 13:59:05.317946 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 13:59:05.321624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 13:59:05.321738 ==
2694 13:59:05.333424 TX Vref=22, minBit 4, minWin=25, winSum=416
2695 13:59:05.336557 TX Vref=24, minBit 1, minWin=26, winSum=425
2696 13:59:05.340065 TX Vref=26, minBit 4, minWin=26, winSum=429
2697 13:59:05.343436 TX Vref=28, minBit 4, minWin=26, winSum=436
2698 13:59:05.346660 TX Vref=30, minBit 10, minWin=25, winSum=433
2699 13:59:05.350111 TX Vref=32, minBit 3, minWin=26, winSum=430
2700 13:59:05.356749 [TxChooseVref] Worse bit 4, Min win 26, Win sum 436, Final Vref 28
2701 13:59:05.356861
2702 13:59:05.360248 Final TX Range 1 Vref 28
2703 13:59:05.360354
2704 13:59:05.360452 ==
2705 13:59:05.363326 Dram Type= 6, Freq= 0, CH_0, rank 0
2706 13:59:05.366796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2707 13:59:05.366900 ==
2708 13:59:05.370313
2709 13:59:05.370417
2710 13:59:05.370513 TX Vref Scan disable
2711 13:59:05.373821 == TX Byte 0 ==
2712 13:59:05.377021 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2713 13:59:05.380116 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2714 13:59:05.383464 == TX Byte 1 ==
2715 13:59:05.386518 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2716 13:59:05.390051 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2717 13:59:05.390154
2718 13:59:05.393996 [DATLAT]
2719 13:59:05.394103 Freq=1200, CH0 RK0
2720 13:59:05.394200
2721 13:59:05.396817 DATLAT Default: 0xd
2722 13:59:05.396892 0, 0xFFFF, sum = 0
2723 13:59:05.400450 1, 0xFFFF, sum = 0
2724 13:59:05.400558 2, 0xFFFF, sum = 0
2725 13:59:05.403372 3, 0xFFFF, sum = 0
2726 13:59:05.403489 4, 0xFFFF, sum = 0
2727 13:59:05.406810 5, 0xFFFF, sum = 0
2728 13:59:05.406915 6, 0xFFFF, sum = 0
2729 13:59:05.409857 7, 0xFFFF, sum = 0
2730 13:59:05.409962 8, 0xFFFF, sum = 0
2731 13:59:05.413934 9, 0xFFFF, sum = 0
2732 13:59:05.416612 10, 0xFFFF, sum = 0
2733 13:59:05.416720 11, 0xFFFF, sum = 0
2734 13:59:05.420075 12, 0x0, sum = 1
2735 13:59:05.420179 13, 0x0, sum = 2
2736 13:59:05.420276 14, 0x0, sum = 3
2737 13:59:05.423521 15, 0x0, sum = 4
2738 13:59:05.423601 best_step = 13
2739 13:59:05.423665
2740 13:59:05.426915 ==
2741 13:59:05.427020 Dram Type= 6, Freq= 0, CH_0, rank 0
2742 13:59:05.433463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2743 13:59:05.433563 ==
2744 13:59:05.433632 RX Vref Scan: 1
2745 13:59:05.433721
2746 13:59:05.436695 Set Vref Range= 32 -> 127
2747 13:59:05.436772
2748 13:59:05.440317 RX Vref 32 -> 127, step: 1
2749 13:59:05.440392
2750 13:59:05.443960 RX Delay -37 -> 252, step: 4
2751 13:59:05.444076
2752 13:59:05.446744 Set Vref, RX VrefLevel [Byte0]: 32
2753 13:59:05.450119 [Byte1]: 32
2754 13:59:05.450224
2755 13:59:05.453448 Set Vref, RX VrefLevel [Byte0]: 33
2756 13:59:05.456481 [Byte1]: 33
2757 13:59:05.456586
2758 13:59:05.459936 Set Vref, RX VrefLevel [Byte0]: 34
2759 13:59:05.463237 [Byte1]: 34
2760 13:59:05.467881
2761 13:59:05.467958 Set Vref, RX VrefLevel [Byte0]: 35
2762 13:59:05.471201 [Byte1]: 35
2763 13:59:05.475803
2764 13:59:05.475903 Set Vref, RX VrefLevel [Byte0]: 36
2765 13:59:05.479256 [Byte1]: 36
2766 13:59:05.483673
2767 13:59:05.483777 Set Vref, RX VrefLevel [Byte0]: 37
2768 13:59:05.486876 [Byte1]: 37
2769 13:59:05.491766
2770 13:59:05.491870 Set Vref, RX VrefLevel [Byte0]: 38
2771 13:59:05.495541 [Byte1]: 38
2772 13:59:05.499604
2773 13:59:05.499680 Set Vref, RX VrefLevel [Byte0]: 39
2774 13:59:05.503211 [Byte1]: 39
2775 13:59:05.507627
2776 13:59:05.507714 Set Vref, RX VrefLevel [Byte0]: 40
2777 13:59:05.510880 [Byte1]: 40
2778 13:59:05.516044
2779 13:59:05.516122 Set Vref, RX VrefLevel [Byte0]: 41
2780 13:59:05.519054 [Byte1]: 41
2781 13:59:05.523628
2782 13:59:05.523728 Set Vref, RX VrefLevel [Byte0]: 42
2783 13:59:05.527091 [Byte1]: 42
2784 13:59:05.531827
2785 13:59:05.531909 Set Vref, RX VrefLevel [Byte0]: 43
2786 13:59:05.535303 [Byte1]: 43
2787 13:59:05.540001
2788 13:59:05.540100 Set Vref, RX VrefLevel [Byte0]: 44
2789 13:59:05.543440 [Byte1]: 44
2790 13:59:05.548096
2791 13:59:05.548198 Set Vref, RX VrefLevel [Byte0]: 45
2792 13:59:05.551392 [Byte1]: 45
2793 13:59:05.555684
2794 13:59:05.555786 Set Vref, RX VrefLevel [Byte0]: 46
2795 13:59:05.559781 [Byte1]: 46
2796 13:59:05.563938
2797 13:59:05.564038 Set Vref, RX VrefLevel [Byte0]: 47
2798 13:59:05.567094 [Byte1]: 47
2799 13:59:05.571767
2800 13:59:05.571869 Set Vref, RX VrefLevel [Byte0]: 48
2801 13:59:05.575070 [Byte1]: 48
2802 13:59:05.579640
2803 13:59:05.579715 Set Vref, RX VrefLevel [Byte0]: 49
2804 13:59:05.583272 [Byte1]: 49
2805 13:59:05.587760
2806 13:59:05.587839 Set Vref, RX VrefLevel [Byte0]: 50
2807 13:59:05.591181 [Byte1]: 50
2808 13:59:05.595663
2809 13:59:05.595736 Set Vref, RX VrefLevel [Byte0]: 51
2810 13:59:05.599132 [Byte1]: 51
2811 13:59:05.603781
2812 13:59:05.603862 Set Vref, RX VrefLevel [Byte0]: 52
2813 13:59:05.606982 [Byte1]: 52
2814 13:59:05.611804
2815 13:59:05.611908 Set Vref, RX VrefLevel [Byte0]: 53
2816 13:59:05.615292 [Byte1]: 53
2817 13:59:05.619920
2818 13:59:05.619996 Set Vref, RX VrefLevel [Byte0]: 54
2819 13:59:05.623023 [Byte1]: 54
2820 13:59:05.627890
2821 13:59:05.627994 Set Vref, RX VrefLevel [Byte0]: 55
2822 13:59:05.631161 [Byte1]: 55
2823 13:59:05.636092
2824 13:59:05.636205 Set Vref, RX VrefLevel [Byte0]: 56
2825 13:59:05.639460 [Byte1]: 56
2826 13:59:05.644145
2827 13:59:05.644243 Set Vref, RX VrefLevel [Byte0]: 57
2828 13:59:05.646902 [Byte1]: 57
2829 13:59:05.651859
2830 13:59:05.651968 Set Vref, RX VrefLevel [Byte0]: 58
2831 13:59:05.655372 [Byte1]: 58
2832 13:59:05.659932
2833 13:59:05.660035 Set Vref, RX VrefLevel [Byte0]: 59
2834 13:59:05.662985 [Byte1]: 59
2835 13:59:05.667688
2836 13:59:05.667761 Set Vref, RX VrefLevel [Byte0]: 60
2837 13:59:05.671317 [Byte1]: 60
2838 13:59:05.676239
2839 13:59:05.676340 Set Vref, RX VrefLevel [Byte0]: 61
2840 13:59:05.679094 [Byte1]: 61
2841 13:59:05.683700
2842 13:59:05.683804 Set Vref, RX VrefLevel [Byte0]: 62
2843 13:59:05.686922 [Byte1]: 62
2844 13:59:05.691808
2845 13:59:05.691904 Set Vref, RX VrefLevel [Byte0]: 63
2846 13:59:05.695069 [Byte1]: 63
2847 13:59:05.699800
2848 13:59:05.699895 Set Vref, RX VrefLevel [Byte0]: 64
2849 13:59:05.703500 [Byte1]: 64
2850 13:59:05.707732
2851 13:59:05.707804 Set Vref, RX VrefLevel [Byte0]: 65
2852 13:59:05.711256 [Byte1]: 65
2853 13:59:05.715813
2854 13:59:05.715886 Set Vref, RX VrefLevel [Byte0]: 66
2855 13:59:05.719018 [Byte1]: 66
2856 13:59:05.724174
2857 13:59:05.724249 Set Vref, RX VrefLevel [Byte0]: 67
2858 13:59:05.727002 [Byte1]: 67
2859 13:59:05.731631
2860 13:59:05.731738 Set Vref, RX VrefLevel [Byte0]: 68
2861 13:59:05.735137 [Byte1]: 68
2862 13:59:05.739696
2863 13:59:05.739798 Set Vref, RX VrefLevel [Byte0]: 69
2864 13:59:05.743050 [Byte1]: 69
2865 13:59:05.747675
2866 13:59:05.747783 Set Vref, RX VrefLevel [Byte0]: 70
2867 13:59:05.751279 [Byte1]: 70
2868 13:59:05.755664
2869 13:59:05.755770 Set Vref, RX VrefLevel [Byte0]: 71
2870 13:59:05.758972 [Byte1]: 71
2871 13:59:05.763879
2872 13:59:05.763985 Set Vref, RX VrefLevel [Byte0]: 72
2873 13:59:05.767278 [Byte1]: 72
2874 13:59:05.772045
2875 13:59:05.772121 Set Vref, RX VrefLevel [Byte0]: 73
2876 13:59:05.774968 [Byte1]: 73
2877 13:59:05.779977
2878 13:59:05.780080 Set Vref, RX VrefLevel [Byte0]: 74
2879 13:59:05.783081 [Byte1]: 74
2880 13:59:05.787962
2881 13:59:05.788039 Final RX Vref Byte 0 = 60 to rank0
2882 13:59:05.791076 Final RX Vref Byte 1 = 52 to rank0
2883 13:59:05.794365 Final RX Vref Byte 0 = 60 to rank1
2884 13:59:05.798034 Final RX Vref Byte 1 = 52 to rank1==
2885 13:59:05.800979 Dram Type= 6, Freq= 0, CH_0, rank 0
2886 13:59:05.808086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 13:59:05.808196 ==
2888 13:59:05.808288 DQS Delay:
2889 13:59:05.808386 DQS0 = 0, DQS1 = 0
2890 13:59:05.811230 DQM Delay:
2891 13:59:05.811333 DQM0 = 112, DQM1 = 101
2892 13:59:05.814522 DQ Delay:
2893 13:59:05.817943 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2894 13:59:05.821098 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =122
2895 13:59:05.824363 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2896 13:59:05.827964 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2897 13:59:05.828040
2898 13:59:05.828108
2899 13:59:05.834589 [DQSOSCAuto] RK0, (LSB)MR18= 0xffff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2900 13:59:05.837791 CH0 RK0: MR19=303, MR18=FFFF
2901 13:59:05.844809 CH0_RK0: MR19=0x303, MR18=0xFFFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2902 13:59:05.844911
2903 13:59:05.847650 ----->DramcWriteLeveling(PI) begin...
2904 13:59:05.847759 ==
2905 13:59:05.851117 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 13:59:05.854214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 13:59:05.857616 ==
2908 13:59:05.857697 Write leveling (Byte 0): 32 => 32
2909 13:59:05.860900 Write leveling (Byte 1): 32 => 32
2910 13:59:05.864301 DramcWriteLeveling(PI) end<-----
2911 13:59:05.864382
2912 13:59:05.864492 ==
2913 13:59:05.867709 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 13:59:05.874649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 13:59:05.874739 ==
2916 13:59:05.874804 [Gating] SW mode calibration
2917 13:59:05.884263 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2918 13:59:05.887869 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2919 13:59:05.891022 0 15 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2920 13:59:05.897542 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 13:59:05.901277 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 13:59:05.904269 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 13:59:05.911134 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 13:59:05.914108 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 13:59:05.917516 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2926 13:59:05.924241 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2927 13:59:05.927382 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
2928 13:59:05.931091 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 13:59:05.937465 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 13:59:05.940661 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 13:59:05.943973 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 13:59:05.951006 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 13:59:05.954238 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2934 13:59:05.957656 1 0 28 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
2935 13:59:05.963933 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2936 13:59:05.967638 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 13:59:05.971075 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 13:59:05.977530 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 13:59:05.980954 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 13:59:05.984364 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 13:59:05.991152 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 13:59:05.994482 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2943 13:59:05.997458 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2944 13:59:06.000898 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 13:59:06.007546 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 13:59:06.011028 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 13:59:06.014488 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 13:59:06.020542 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 13:59:06.024497 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 13:59:06.027405 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 13:59:06.034249 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 13:59:06.037467 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 13:59:06.040797 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 13:59:06.047418 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 13:59:06.051138 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 13:59:06.054021 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 13:59:06.060793 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 13:59:06.063877 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2959 13:59:06.067588 Total UI for P1: 0, mck2ui 16
2960 13:59:06.070734 best dqsien dly found for B0: ( 1, 3, 26)
2961 13:59:06.074283 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2962 13:59:06.080990 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 13:59:06.081144 Total UI for P1: 0, mck2ui 16
2964 13:59:06.084107 best dqsien dly found for B1: ( 1, 4, 0)
2965 13:59:06.091105 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2966 13:59:06.094155 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2967 13:59:06.094259
2968 13:59:06.097337 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2969 13:59:06.100806 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2970 13:59:06.104329 [Gating] SW calibration Done
2971 13:59:06.104434 ==
2972 13:59:06.107479 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 13:59:06.110904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 13:59:06.111015 ==
2975 13:59:06.111110 RX Vref Scan: 0
2976 13:59:06.114273
2977 13:59:06.114365 RX Vref 0 -> 0, step: 1
2978 13:59:06.114468
2979 13:59:06.117666 RX Delay -40 -> 252, step: 8
2980 13:59:06.120819 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2981 13:59:06.124213 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2982 13:59:06.130997 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2983 13:59:06.134167 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2984 13:59:06.137931 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2985 13:59:06.140897 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2986 13:59:06.143919 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2987 13:59:06.150488 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2988 13:59:06.153863 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2989 13:59:06.157275 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2990 13:59:06.160594 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2991 13:59:06.163923 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2992 13:59:06.171070 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2993 13:59:06.173838 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2994 13:59:06.177201 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2995 13:59:06.180878 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2996 13:59:06.180980 ==
2997 13:59:06.183833 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 13:59:06.187235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 13:59:06.190803 ==
3000 13:59:06.190905 DQS Delay:
3001 13:59:06.190996 DQS0 = 0, DQS1 = 0
3002 13:59:06.193878 DQM Delay:
3003 13:59:06.193952 DQM0 = 112, DQM1 = 101
3004 13:59:06.197291 DQ Delay:
3005 13:59:06.200597 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3006 13:59:06.204492 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
3007 13:59:06.207811 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3008 13:59:06.211154 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
3009 13:59:06.211251
3010 13:59:06.211343
3011 13:59:06.211464 ==
3012 13:59:06.214560 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 13:59:06.217700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 13:59:06.217775 ==
3015 13:59:06.217857
3016 13:59:06.217956
3017 13:59:06.221157 TX Vref Scan disable
3018 13:59:06.224637 == TX Byte 0 ==
3019 13:59:06.228166 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3020 13:59:06.231086 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3021 13:59:06.234414 == TX Byte 1 ==
3022 13:59:06.237701 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3023 13:59:06.241017 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3024 13:59:06.241103 ==
3025 13:59:06.244563 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 13:59:06.247902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 13:59:06.248001 ==
3028 13:59:06.260762 TX Vref=22, minBit 5, minWin=25, winSum=427
3029 13:59:06.263879 TX Vref=24, minBit 1, minWin=26, winSum=433
3030 13:59:06.267442 TX Vref=26, minBit 1, minWin=26, winSum=436
3031 13:59:06.270455 TX Vref=28, minBit 13, minWin=26, winSum=440
3032 13:59:06.274230 TX Vref=30, minBit 1, minWin=27, winSum=441
3033 13:59:06.280374 TX Vref=32, minBit 13, minWin=26, winSum=437
3034 13:59:06.284118 [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 30
3035 13:59:06.284220
3036 13:59:06.287140 Final TX Range 1 Vref 30
3037 13:59:06.287238
3038 13:59:06.287327 ==
3039 13:59:06.290966 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 13:59:06.293670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 13:59:06.297070 ==
3042 13:59:06.297144
3043 13:59:06.297213
3044 13:59:06.297303 TX Vref Scan disable
3045 13:59:06.300660 == TX Byte 0 ==
3046 13:59:06.304021 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3047 13:59:06.307255 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3048 13:59:06.310419 == TX Byte 1 ==
3049 13:59:06.313685 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3050 13:59:06.317033 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3051 13:59:06.320626
3052 13:59:06.320700 [DATLAT]
3053 13:59:06.320773 Freq=1200, CH0 RK1
3054 13:59:06.320839
3055 13:59:06.324147 DATLAT Default: 0xd
3056 13:59:06.324249 0, 0xFFFF, sum = 0
3057 13:59:06.327588 1, 0xFFFF, sum = 0
3058 13:59:06.327661 2, 0xFFFF, sum = 0
3059 13:59:06.330937 3, 0xFFFF, sum = 0
3060 13:59:06.331046 4, 0xFFFF, sum = 0
3061 13:59:06.333737 5, 0xFFFF, sum = 0
3062 13:59:06.337111 6, 0xFFFF, sum = 0
3063 13:59:06.337218 7, 0xFFFF, sum = 0
3064 13:59:06.340408 8, 0xFFFF, sum = 0
3065 13:59:06.340508 9, 0xFFFF, sum = 0
3066 13:59:06.343984 10, 0xFFFF, sum = 0
3067 13:59:06.344079 11, 0xFFFF, sum = 0
3068 13:59:06.347278 12, 0x0, sum = 1
3069 13:59:06.347390 13, 0x0, sum = 2
3070 13:59:06.350852 14, 0x0, sum = 3
3071 13:59:06.350954 15, 0x0, sum = 4
3072 13:59:06.351046 best_step = 13
3073 13:59:06.354179
3074 13:59:06.354275 ==
3075 13:59:06.357322 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 13:59:06.360846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 13:59:06.360948 ==
3078 13:59:06.361037 RX Vref Scan: 0
3079 13:59:06.361131
3080 13:59:06.363624 RX Vref 0 -> 0, step: 1
3081 13:59:06.363695
3082 13:59:06.367333 RX Delay -37 -> 252, step: 4
3083 13:59:06.370220 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3084 13:59:06.377350 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3085 13:59:06.380702 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3086 13:59:06.384008 iDelay=195, Bit 3, Center 110 (39 ~ 182) 144
3087 13:59:06.387019 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3088 13:59:06.390684 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3089 13:59:06.397500 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3090 13:59:06.400780 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3091 13:59:06.404285 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3092 13:59:06.407143 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3093 13:59:06.410572 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3094 13:59:06.414046 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3095 13:59:06.420704 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3096 13:59:06.423649 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3097 13:59:06.426976 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3098 13:59:06.430470 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3099 13:59:06.430546 ==
3100 13:59:06.433770 Dram Type= 6, Freq= 0, CH_0, rank 1
3101 13:59:06.444108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 13:59:06.444191 ==
3103 13:59:06.444257 DQS Delay:
3104 13:59:06.444504 DQS0 = 0, DQS1 = 0
3105 13:59:06.444598 DQM Delay:
3106 13:59:06.444689 DQM0 = 111, DQM1 = 101
3107 13:59:06.447192 DQ Delay:
3108 13:59:06.450648 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =110
3109 13:59:06.454297 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =120
3110 13:59:06.457499 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =92
3111 13:59:06.460730 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3112 13:59:06.460826
3113 13:59:06.460919
3114 13:59:06.467781 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3115 13:59:06.470408 CH0 RK1: MR19=403, MR18=13FB
3116 13:59:06.477293 CH0_RK1: MR19=0x403, MR18=0x13FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3117 13:59:06.480573 [RxdqsGatingPostProcess] freq 1200
3118 13:59:06.487551 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3119 13:59:06.490641 best DQS0 dly(2T, 0.5T) = (0, 11)
3120 13:59:06.490741 best DQS1 dly(2T, 0.5T) = (0, 12)
3121 13:59:06.493814 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3122 13:59:06.497366 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3123 13:59:06.500806 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 13:59:06.503987 best DQS1 dly(2T, 0.5T) = (0, 12)
3125 13:59:06.507058 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 13:59:06.510915 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3127 13:59:06.514344 Pre-setting of DQS Precalculation
3128 13:59:06.520650 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3129 13:59:06.520735 ==
3130 13:59:06.524045 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 13:59:06.527320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 13:59:06.527461 ==
3133 13:59:06.533832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 13:59:06.537640 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3135 13:59:06.546997 [CA 0] Center 37 (8~67) winsize 60
3136 13:59:06.550022 [CA 1] Center 37 (7~68) winsize 62
3137 13:59:06.553922 [CA 2] Center 34 (5~64) winsize 60
3138 13:59:06.556886 [CA 3] Center 34 (4~64) winsize 61
3139 13:59:06.559894 [CA 4] Center 34 (4~64) winsize 61
3140 13:59:06.563244 [CA 5] Center 33 (3~63) winsize 61
3141 13:59:06.563346
3142 13:59:06.566763 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3143 13:59:06.566865
3144 13:59:06.570399 [CATrainingPosCal] consider 1 rank data
3145 13:59:06.573178 u2DelayCellTimex100 = 270/100 ps
3146 13:59:06.576815 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3147 13:59:06.580242 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 13:59:06.587105 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3149 13:59:06.590454 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 13:59:06.593743 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 13:59:06.596551 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3152 13:59:06.596629
3153 13:59:06.600198 CA PerBit enable=1, Macro0, CA PI delay=33
3154 13:59:06.600272
3155 13:59:06.603632 [CBTSetCACLKResult] CA Dly = 33
3156 13:59:06.603730 CS Dly: 6 (0~37)
3157 13:59:06.603817 ==
3158 13:59:06.606917 Dram Type= 6, Freq= 0, CH_1, rank 1
3159 13:59:06.613750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 13:59:06.613855 ==
3161 13:59:06.616705 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3162 13:59:06.623559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3163 13:59:06.632022 [CA 0] Center 38 (8~68) winsize 61
3164 13:59:06.635526 [CA 1] Center 37 (7~68) winsize 62
3165 13:59:06.639031 [CA 2] Center 35 (5~65) winsize 61
3166 13:59:06.642707 [CA 3] Center 33 (3~64) winsize 62
3167 13:59:06.645739 [CA 4] Center 34 (4~65) winsize 62
3168 13:59:06.649282 [CA 5] Center 33 (3~64) winsize 62
3169 13:59:06.649356
3170 13:59:06.652473 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3171 13:59:06.652552
3172 13:59:06.655474 [CATrainingPosCal] consider 2 rank data
3173 13:59:06.658884 u2DelayCellTimex100 = 270/100 ps
3174 13:59:06.662531 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3175 13:59:06.665513 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3176 13:59:06.672464 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3177 13:59:06.675591 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3178 13:59:06.678952 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3179 13:59:06.682499 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3180 13:59:06.682568
3181 13:59:06.685789 CA PerBit enable=1, Macro0, CA PI delay=33
3182 13:59:06.685856
3183 13:59:06.688895 [CBTSetCACLKResult] CA Dly = 33
3184 13:59:06.688968 CS Dly: 7 (0~40)
3185 13:59:06.689027
3186 13:59:06.692385 ----->DramcWriteLeveling(PI) begin...
3187 13:59:06.695540 ==
3188 13:59:06.695617 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 13:59:06.702059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 13:59:06.702135 ==
3191 13:59:06.706158 Write leveling (Byte 0): 25 => 25
3192 13:59:06.708780 Write leveling (Byte 1): 28 => 28
3193 13:59:06.712733 DramcWriteLeveling(PI) end<-----
3194 13:59:06.712841
3195 13:59:06.712932 ==
3196 13:59:06.715505 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 13:59:06.719042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 13:59:06.719115 ==
3199 13:59:06.722290 [Gating] SW mode calibration
3200 13:59:06.729270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3201 13:59:06.732597 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3202 13:59:06.739269 0 15 0 | B1->B0 | 2828 2a2a | 0 0 | (0 0) (0 0)
3203 13:59:06.742324 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 13:59:06.745713 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 13:59:06.752479 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 13:59:06.755959 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 13:59:06.759271 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 13:59:06.766031 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 13:59:06.768993 0 15 28 | B1->B0 | 2d2d 3232 | 0 1 | (0 0) (1 0)
3210 13:59:06.772656 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 13:59:06.779314 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 13:59:06.782739 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 13:59:06.786173 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 13:59:06.792998 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 13:59:06.795972 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 13:59:06.799215 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3217 13:59:06.802605 1 0 28 | B1->B0 | 3838 2a2a | 0 1 | (0 0) (0 0)
3218 13:59:06.809561 1 1 0 | B1->B0 | 4444 4444 | 0 1 | (0 0) (0 0)
3219 13:59:06.812393 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 13:59:06.816023 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 13:59:06.822769 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 13:59:06.825824 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 13:59:06.829245 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 13:59:06.835919 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 13:59:06.839066 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3226 13:59:06.843178 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3227 13:59:06.849218 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 13:59:06.852580 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 13:59:06.856110 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 13:59:06.862742 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 13:59:06.866093 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 13:59:06.869352 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 13:59:06.875876 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 13:59:06.879245 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 13:59:06.883000 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 13:59:06.889362 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 13:59:06.892592 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 13:59:06.895720 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 13:59:06.899600 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 13:59:06.905945 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 13:59:06.909315 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3242 13:59:06.912808 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3243 13:59:06.915972 Total UI for P1: 0, mck2ui 16
3244 13:59:06.919298 best dqsien dly found for B0: ( 1, 3, 28)
3245 13:59:06.925870 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 13:59:06.929244 Total UI for P1: 0, mck2ui 16
3247 13:59:06.932327 best dqsien dly found for B1: ( 1, 3, 30)
3248 13:59:06.935812 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3249 13:59:06.939158 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3250 13:59:06.939254
3251 13:59:06.942592 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3252 13:59:06.945728 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3253 13:59:06.948898 [Gating] SW calibration Done
3254 13:59:06.948995 ==
3255 13:59:06.952646 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 13:59:06.955854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 13:59:06.955926 ==
3258 13:59:06.959303 RX Vref Scan: 0
3259 13:59:06.959428
3260 13:59:06.959519 RX Vref 0 -> 0, step: 1
3261 13:59:06.959608
3262 13:59:06.962695 RX Delay -40 -> 252, step: 8
3263 13:59:06.966291 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3264 13:59:06.972317 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3265 13:59:06.975545 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3266 13:59:06.979189 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3267 13:59:06.982694 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3268 13:59:06.985899 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3269 13:59:06.992381 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3270 13:59:06.996108 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3271 13:59:06.998981 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3272 13:59:07.002806 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3273 13:59:07.005944 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3274 13:59:07.012338 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3275 13:59:07.015773 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3276 13:59:07.019547 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3277 13:59:07.022262 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3278 13:59:07.025531 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3279 13:59:07.029002 ==
3280 13:59:07.032335 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 13:59:07.035743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 13:59:07.035816 ==
3283 13:59:07.035886 DQS Delay:
3284 13:59:07.039150 DQS0 = 0, DQS1 = 0
3285 13:59:07.039216 DQM Delay:
3286 13:59:07.041987 DQM0 = 115, DQM1 = 107
3287 13:59:07.042053 DQ Delay:
3288 13:59:07.045406 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3289 13:59:07.049137 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3290 13:59:07.052586 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3291 13:59:07.055620 DQ12 =115, DQ13 =119, DQ14 =111, DQ15 =111
3292 13:59:07.055688
3293 13:59:07.055747
3294 13:59:07.055821 ==
3295 13:59:07.058859 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 13:59:07.065567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 13:59:07.065641 ==
3298 13:59:07.065703
3299 13:59:07.065766
3300 13:59:07.065825 TX Vref Scan disable
3301 13:59:07.068818 == TX Byte 0 ==
3302 13:59:07.072193 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3303 13:59:07.078856 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3304 13:59:07.078967 == TX Byte 1 ==
3305 13:59:07.082283 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3306 13:59:07.089157 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3307 13:59:07.089264 ==
3308 13:59:07.092344 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 13:59:07.095343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 13:59:07.095474 ==
3311 13:59:07.106707 TX Vref=22, minBit 1, minWin=24, winSum=404
3312 13:59:07.110142 TX Vref=24, minBit 11, minWin=24, winSum=410
3313 13:59:07.113812 TX Vref=26, minBit 1, minWin=25, winSum=418
3314 13:59:07.117087 TX Vref=28, minBit 1, minWin=25, winSum=418
3315 13:59:07.120115 TX Vref=30, minBit 7, minWin=25, winSum=421
3316 13:59:07.123751 TX Vref=32, minBit 3, minWin=24, winSum=415
3317 13:59:07.130539 [TxChooseVref] Worse bit 7, Min win 25, Win sum 421, Final Vref 30
3318 13:59:07.130617
3319 13:59:07.133896 Final TX Range 1 Vref 30
3320 13:59:07.133972
3321 13:59:07.134033 ==
3322 13:59:07.136818 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 13:59:07.140311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 13:59:07.140386 ==
3325 13:59:07.140448
3326 13:59:07.144212
3327 13:59:07.144282 TX Vref Scan disable
3328 13:59:07.146993 == TX Byte 0 ==
3329 13:59:07.150100 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3330 13:59:07.153788 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3331 13:59:07.157186 == TX Byte 1 ==
3332 13:59:07.160402 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3333 13:59:07.163781 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3334 13:59:07.163857
3335 13:59:07.167128 [DATLAT]
3336 13:59:07.167203 Freq=1200, CH1 RK0
3337 13:59:07.167290
3338 13:59:07.170266 DATLAT Default: 0xd
3339 13:59:07.170340 0, 0xFFFF, sum = 0
3340 13:59:07.173590 1, 0xFFFF, sum = 0
3341 13:59:07.173674 2, 0xFFFF, sum = 0
3342 13:59:07.177048 3, 0xFFFF, sum = 0
3343 13:59:07.177124 4, 0xFFFF, sum = 0
3344 13:59:07.180491 5, 0xFFFF, sum = 0
3345 13:59:07.180566 6, 0xFFFF, sum = 0
3346 13:59:07.183684 7, 0xFFFF, sum = 0
3347 13:59:07.183792 8, 0xFFFF, sum = 0
3348 13:59:07.187021 9, 0xFFFF, sum = 0
3349 13:59:07.190122 10, 0xFFFF, sum = 0
3350 13:59:07.190204 11, 0xFFFF, sum = 0
3351 13:59:07.193572 12, 0x0, sum = 1
3352 13:59:07.193662 13, 0x0, sum = 2
3353 13:59:07.193728 14, 0x0, sum = 3
3354 13:59:07.196919 15, 0x0, sum = 4
3355 13:59:07.197010 best_step = 13
3356 13:59:07.197076
3357 13:59:07.200321 ==
3358 13:59:07.200398 Dram Type= 6, Freq= 0, CH_1, rank 0
3359 13:59:07.206761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3360 13:59:07.206838 ==
3361 13:59:07.206901 RX Vref Scan: 1
3362 13:59:07.206961
3363 13:59:07.210502 Set Vref Range= 32 -> 127
3364 13:59:07.210574
3365 13:59:07.213832 RX Vref 32 -> 127, step: 1
3366 13:59:07.213910
3367 13:59:07.217269 RX Delay -21 -> 252, step: 4
3368 13:59:07.217340
3369 13:59:07.220104 Set Vref, RX VrefLevel [Byte0]: 32
3370 13:59:07.223867 [Byte1]: 32
3371 13:59:07.223941
3372 13:59:07.227274 Set Vref, RX VrefLevel [Byte0]: 33
3373 13:59:07.230338 [Byte1]: 33
3374 13:59:07.230412
3375 13:59:07.233480 Set Vref, RX VrefLevel [Byte0]: 34
3376 13:59:07.236930 [Byte1]: 34
3377 13:59:07.240709
3378 13:59:07.240781 Set Vref, RX VrefLevel [Byte0]: 35
3379 13:59:07.244203 [Byte1]: 35
3380 13:59:07.248928
3381 13:59:07.249010 Set Vref, RX VrefLevel [Byte0]: 36
3382 13:59:07.252280 [Byte1]: 36
3383 13:59:07.256851
3384 13:59:07.256932 Set Vref, RX VrefLevel [Byte0]: 37
3385 13:59:07.260056 [Byte1]: 37
3386 13:59:07.264976
3387 13:59:07.265068 Set Vref, RX VrefLevel [Byte0]: 38
3388 13:59:07.267911 [Byte1]: 38
3389 13:59:07.272719
3390 13:59:07.272807 Set Vref, RX VrefLevel [Byte0]: 39
3391 13:59:07.276246 [Byte1]: 39
3392 13:59:07.280682
3393 13:59:07.280763 Set Vref, RX VrefLevel [Byte0]: 40
3394 13:59:07.283835 [Byte1]: 40
3395 13:59:07.288949
3396 13:59:07.289030 Set Vref, RX VrefLevel [Byte0]: 41
3397 13:59:07.291757 [Byte1]: 41
3398 13:59:07.297001
3399 13:59:07.297081 Set Vref, RX VrefLevel [Byte0]: 42
3400 13:59:07.299992 [Byte1]: 42
3401 13:59:07.304504
3402 13:59:07.304585 Set Vref, RX VrefLevel [Byte0]: 43
3403 13:59:07.307795 [Byte1]: 43
3404 13:59:07.312484
3405 13:59:07.312565 Set Vref, RX VrefLevel [Byte0]: 44
3406 13:59:07.315478 [Byte1]: 44
3407 13:59:07.320255
3408 13:59:07.320336 Set Vref, RX VrefLevel [Byte0]: 45
3409 13:59:07.323970 [Byte1]: 45
3410 13:59:07.328003
3411 13:59:07.328085 Set Vref, RX VrefLevel [Byte0]: 46
3412 13:59:07.331344 [Byte1]: 46
3413 13:59:07.335957
3414 13:59:07.336038 Set Vref, RX VrefLevel [Byte0]: 47
3415 13:59:07.339644 [Byte1]: 47
3416 13:59:07.344263
3417 13:59:07.344344 Set Vref, RX VrefLevel [Byte0]: 48
3418 13:59:07.347513 [Byte1]: 48
3419 13:59:07.351718
3420 13:59:07.351800 Set Vref, RX VrefLevel [Byte0]: 49
3421 13:59:07.355778 [Byte1]: 49
3422 13:59:07.359980
3423 13:59:07.360061 Set Vref, RX VrefLevel [Byte0]: 50
3424 13:59:07.362959 [Byte1]: 50
3425 13:59:07.367796
3426 13:59:07.367876 Set Vref, RX VrefLevel [Byte0]: 51
3427 13:59:07.371245 [Byte1]: 51
3428 13:59:07.375834
3429 13:59:07.375916 Set Vref, RX VrefLevel [Byte0]: 52
3430 13:59:07.379187 [Byte1]: 52
3431 13:59:07.383921
3432 13:59:07.384003 Set Vref, RX VrefLevel [Byte0]: 53
3433 13:59:07.386877 [Byte1]: 53
3434 13:59:07.391586
3435 13:59:07.391668 Set Vref, RX VrefLevel [Byte0]: 54
3436 13:59:07.395179 [Byte1]: 54
3437 13:59:07.399176
3438 13:59:07.399287 Set Vref, RX VrefLevel [Byte0]: 55
3439 13:59:07.402600 [Byte1]: 55
3440 13:59:07.407500
3441 13:59:07.407582 Set Vref, RX VrefLevel [Byte0]: 56
3442 13:59:07.410616 [Byte1]: 56
3443 13:59:07.415077
3444 13:59:07.415159 Set Vref, RX VrefLevel [Byte0]: 57
3445 13:59:07.418619 [Byte1]: 57
3446 13:59:07.423068
3447 13:59:07.423150 Set Vref, RX VrefLevel [Byte0]: 58
3448 13:59:07.426747 [Byte1]: 58
3449 13:59:07.431144
3450 13:59:07.431226 Set Vref, RX VrefLevel [Byte0]: 59
3451 13:59:07.434508 [Byte1]: 59
3452 13:59:07.439028
3453 13:59:07.439109 Set Vref, RX VrefLevel [Byte0]: 60
3454 13:59:07.442377 [Byte1]: 60
3455 13:59:07.447249
3456 13:59:07.447330 Set Vref, RX VrefLevel [Byte0]: 61
3457 13:59:07.450668 [Byte1]: 61
3458 13:59:07.454756
3459 13:59:07.454838 Set Vref, RX VrefLevel [Byte0]: 62
3460 13:59:07.458174 [Byte1]: 62
3461 13:59:07.462819
3462 13:59:07.462900 Set Vref, RX VrefLevel [Byte0]: 63
3463 13:59:07.465957 [Byte1]: 63
3464 13:59:07.470572
3465 13:59:07.470654 Set Vref, RX VrefLevel [Byte0]: 64
3466 13:59:07.474010 [Byte1]: 64
3467 13:59:07.478586
3468 13:59:07.478668 Set Vref, RX VrefLevel [Byte0]: 65
3469 13:59:07.482180 [Byte1]: 65
3470 13:59:07.486382
3471 13:59:07.486464 Set Vref, RX VrefLevel [Byte0]: 66
3472 13:59:07.489916 [Byte1]: 66
3473 13:59:07.494728
3474 13:59:07.494809 Set Vref, RX VrefLevel [Byte0]: 67
3475 13:59:07.497929 [Byte1]: 67
3476 13:59:07.502241
3477 13:59:07.502325 Final RX Vref Byte 0 = 56 to rank0
3478 13:59:07.505838 Final RX Vref Byte 1 = 49 to rank0
3479 13:59:07.509030 Final RX Vref Byte 0 = 56 to rank1
3480 13:59:07.512208 Final RX Vref Byte 1 = 49 to rank1==
3481 13:59:07.515960 Dram Type= 6, Freq= 0, CH_1, rank 0
3482 13:59:07.522741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3483 13:59:07.522824 ==
3484 13:59:07.522889 DQS Delay:
3485 13:59:07.522950 DQS0 = 0, DQS1 = 0
3486 13:59:07.526130 DQM Delay:
3487 13:59:07.526212 DQM0 = 115, DQM1 = 106
3488 13:59:07.528885 DQ Delay:
3489 13:59:07.532146 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3490 13:59:07.535400 DQ4 =112, DQ5 =122, DQ6 =128, DQ7 =114
3491 13:59:07.539229 DQ8 =94, DQ9 =100, DQ10 =104, DQ11 =100
3492 13:59:07.542321 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =112
3493 13:59:07.542404
3494 13:59:07.542468
3495 13:59:07.552168 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3496 13:59:07.552252 CH1 RK0: MR19=303, MR18=F0F8
3497 13:59:07.559045 CH1_RK0: MR19=0x303, MR18=0xF0F8, DQSOSC=413, MR23=63, INC=38, DEC=25
3498 13:59:07.559127
3499 13:59:07.562051 ----->DramcWriteLeveling(PI) begin...
3500 13:59:07.562136 ==
3501 13:59:07.565760 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 13:59:07.572053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 13:59:07.572136 ==
3504 13:59:07.572200 Write leveling (Byte 0): 23 => 23
3505 13:59:07.575563 Write leveling (Byte 1): 27 => 27
3506 13:59:07.578942 DramcWriteLeveling(PI) end<-----
3507 13:59:07.579023
3508 13:59:07.579088 ==
3509 13:59:07.582544 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 13:59:07.589358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 13:59:07.589444 ==
3512 13:59:07.592261 [Gating] SW mode calibration
3513 13:59:07.599212 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3514 13:59:07.602135 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3515 13:59:07.608798 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3516 13:59:07.612398 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 13:59:07.615573 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 13:59:07.622465 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 13:59:07.625373 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 13:59:07.628897 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 13:59:07.632284 0 15 24 | B1->B0 | 3333 2828 | 1 0 | (1 0) (1 0)
3522 13:59:07.639249 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3523 13:59:07.642238 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 13:59:07.645266 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 13:59:07.652422 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 13:59:07.655288 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 13:59:07.658710 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 13:59:07.665314 1 0 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3529 13:59:07.668643 1 0 24 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
3530 13:59:07.671987 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3531 13:59:07.678404 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 13:59:07.681997 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 13:59:07.685155 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 13:59:07.692032 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 13:59:07.695536 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 13:59:07.698386 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3537 13:59:07.705107 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3538 13:59:07.708514 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3539 13:59:07.711696 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 13:59:07.718687 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 13:59:07.721610 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 13:59:07.724992 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 13:59:07.731665 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 13:59:07.734875 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 13:59:07.738241 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 13:59:07.744789 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 13:59:07.747994 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 13:59:07.751183 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 13:59:07.758204 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 13:59:07.761118 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 13:59:07.764414 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 13:59:07.771609 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 13:59:07.774407 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3554 13:59:07.777925 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3555 13:59:07.781048 Total UI for P1: 0, mck2ui 16
3556 13:59:07.784768 best dqsien dly found for B0: ( 1, 3, 24)
3557 13:59:07.788212 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 13:59:07.791339 Total UI for P1: 0, mck2ui 16
3559 13:59:07.794767 best dqsien dly found for B1: ( 1, 3, 26)
3560 13:59:07.798280 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3561 13:59:07.804410 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3562 13:59:07.804487
3563 13:59:07.807690 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3564 13:59:07.810913 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3565 13:59:07.814735 [Gating] SW calibration Done
3566 13:59:07.814811 ==
3567 13:59:07.817829 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 13:59:07.820857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 13:59:07.820936 ==
3570 13:59:07.824163 RX Vref Scan: 0
3571 13:59:07.824237
3572 13:59:07.824303 RX Vref 0 -> 0, step: 1
3573 13:59:07.824362
3574 13:59:07.827560 RX Delay -40 -> 252, step: 8
3575 13:59:07.830706 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3576 13:59:07.837558 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3577 13:59:07.840938 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3578 13:59:07.844088 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3579 13:59:07.847269 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3580 13:59:07.850725 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3581 13:59:07.857322 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3582 13:59:07.861030 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3583 13:59:07.863820 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3584 13:59:07.867368 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3585 13:59:07.870784 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3586 13:59:07.873814 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3587 13:59:07.880923 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3588 13:59:07.884103 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3589 13:59:07.887108 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3590 13:59:07.890702 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3591 13:59:07.890783 ==
3592 13:59:07.893826 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 13:59:07.900552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 13:59:07.900634 ==
3595 13:59:07.900698 DQS Delay:
3596 13:59:07.903709 DQS0 = 0, DQS1 = 0
3597 13:59:07.903790 DQM Delay:
3598 13:59:07.907239 DQM0 = 111, DQM1 = 107
3599 13:59:07.907320 DQ Delay:
3600 13:59:07.910733 DQ0 =115, DQ1 =111, DQ2 =99, DQ3 =111
3601 13:59:07.914136 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3602 13:59:07.916967 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3603 13:59:07.920172 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =111
3604 13:59:07.920246
3605 13:59:07.920307
3606 13:59:07.920368 ==
3607 13:59:07.924015 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 13:59:07.927019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 13:59:07.930646 ==
3610 13:59:07.930727
3611 13:59:07.930792
3612 13:59:07.930852 TX Vref Scan disable
3613 13:59:07.933493 == TX Byte 0 ==
3614 13:59:07.936684 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3615 13:59:07.940410 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3616 13:59:07.943717 == TX Byte 1 ==
3617 13:59:07.947067 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3618 13:59:07.949986 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3619 13:59:07.953396 ==
3620 13:59:07.956555 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 13:59:07.959886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 13:59:07.959972 ==
3623 13:59:07.971647 TX Vref=22, minBit 0, minWin=25, winSum=414
3624 13:59:07.974798 TX Vref=24, minBit 0, minWin=25, winSum=415
3625 13:59:07.977776 TX Vref=26, minBit 3, minWin=25, winSum=423
3626 13:59:07.981262 TX Vref=28, minBit 0, minWin=25, winSum=422
3627 13:59:07.984607 TX Vref=30, minBit 1, minWin=25, winSum=423
3628 13:59:07.991128 TX Vref=32, minBit 1, minWin=25, winSum=419
3629 13:59:07.994850 [TxChooseVref] Worse bit 3, Min win 25, Win sum 423, Final Vref 26
3630 13:59:07.994936
3631 13:59:07.998022 Final TX Range 1 Vref 26
3632 13:59:07.998104
3633 13:59:07.998168 ==
3634 13:59:08.001099 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 13:59:08.004755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 13:59:08.004837 ==
3637 13:59:08.008246
3638 13:59:08.008326
3639 13:59:08.008390 TX Vref Scan disable
3640 13:59:08.011514 == TX Byte 0 ==
3641 13:59:08.014595 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3642 13:59:08.020985 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3643 13:59:08.021067 == TX Byte 1 ==
3644 13:59:08.024298 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3645 13:59:08.031145 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3646 13:59:08.031240
3647 13:59:08.031333 [DATLAT]
3648 13:59:08.031454 Freq=1200, CH1 RK1
3649 13:59:08.031515
3650 13:59:08.034084 DATLAT Default: 0xd
3651 13:59:08.037456 0, 0xFFFF, sum = 0
3652 13:59:08.037539 1, 0xFFFF, sum = 0
3653 13:59:08.040897 2, 0xFFFF, sum = 0
3654 13:59:08.040980 3, 0xFFFF, sum = 0
3655 13:59:08.044241 4, 0xFFFF, sum = 0
3656 13:59:08.044324 5, 0xFFFF, sum = 0
3657 13:59:08.047343 6, 0xFFFF, sum = 0
3658 13:59:08.047459 7, 0xFFFF, sum = 0
3659 13:59:08.050621 8, 0xFFFF, sum = 0
3660 13:59:08.050724 9, 0xFFFF, sum = 0
3661 13:59:08.054021 10, 0xFFFF, sum = 0
3662 13:59:08.054105 11, 0xFFFF, sum = 0
3663 13:59:08.057493 12, 0x0, sum = 1
3664 13:59:08.057575 13, 0x0, sum = 2
3665 13:59:08.060986 14, 0x0, sum = 3
3666 13:59:08.061068 15, 0x0, sum = 4
3667 13:59:08.063909 best_step = 13
3668 13:59:08.064057
3669 13:59:08.064125 ==
3670 13:59:08.067462 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 13:59:08.070473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 13:59:08.070571 ==
3673 13:59:08.070674 RX Vref Scan: 0
3674 13:59:08.074048
3675 13:59:08.074157 RX Vref 0 -> 0, step: 1
3676 13:59:08.074249
3677 13:59:08.077868 RX Delay -21 -> 252, step: 4
3678 13:59:08.083830 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3679 13:59:08.086966 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3680 13:59:08.090676 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3681 13:59:08.093795 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3682 13:59:08.097199 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3683 13:59:08.103799 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3684 13:59:08.107249 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3685 13:59:08.110698 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3686 13:59:08.113505 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3687 13:59:08.116884 iDelay=195, Bit 9, Center 104 (39 ~ 170) 132
3688 13:59:08.123752 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3689 13:59:08.126650 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3690 13:59:08.130231 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3691 13:59:08.133381 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3692 13:59:08.137032 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3693 13:59:08.143626 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3694 13:59:08.143702 ==
3695 13:59:08.146569 Dram Type= 6, Freq= 0, CH_1, rank 1
3696 13:59:08.149826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3697 13:59:08.149928 ==
3698 13:59:08.150018 DQS Delay:
3699 13:59:08.153339 DQS0 = 0, DQS1 = 0
3700 13:59:08.153413 DQM Delay:
3701 13:59:08.156498 DQM0 = 111, DQM1 = 111
3702 13:59:08.156569 DQ Delay:
3703 13:59:08.160074 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =108
3704 13:59:08.163087 DQ4 =108, DQ5 =120, DQ6 =124, DQ7 =110
3705 13:59:08.166365 DQ8 =98, DQ9 =104, DQ10 =110, DQ11 =104
3706 13:59:08.170335 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3707 13:59:08.173280
3708 13:59:08.173384
3709 13:59:08.179973 [DQSOSCAuto] RK1, (LSB)MR18= 0xfd0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3710 13:59:08.182911 CH1 RK1: MR19=304, MR18=FD0C
3711 13:59:08.189518 CH1_RK1: MR19=0x304, MR18=0xFD0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3712 13:59:08.193079 [RxdqsGatingPostProcess] freq 1200
3713 13:59:08.196265 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3714 13:59:08.199915 best DQS0 dly(2T, 0.5T) = (0, 11)
3715 13:59:08.202941 best DQS1 dly(2T, 0.5T) = (0, 11)
3716 13:59:08.206431 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3717 13:59:08.210088 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3718 13:59:08.212869 best DQS0 dly(2T, 0.5T) = (0, 11)
3719 13:59:08.216348 best DQS1 dly(2T, 0.5T) = (0, 11)
3720 13:59:08.219908 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3721 13:59:08.222762 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3722 13:59:08.226201 Pre-setting of DQS Precalculation
3723 13:59:08.229684 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3724 13:59:08.239213 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3725 13:59:08.245855 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3726 13:59:08.245957
3727 13:59:08.246051
3728 13:59:08.249231 [Calibration Summary] 2400 Mbps
3729 13:59:08.249333 CH 0, Rank 0
3730 13:59:08.252652 SW Impedance : PASS
3731 13:59:08.252745 DUTY Scan : NO K
3732 13:59:08.255873 ZQ Calibration : PASS
3733 13:59:08.259334 Jitter Meter : NO K
3734 13:59:08.259445 CBT Training : PASS
3735 13:59:08.262231 Write leveling : PASS
3736 13:59:08.265694 RX DQS gating : PASS
3737 13:59:08.265796 RX DQ/DQS(RDDQC) : PASS
3738 13:59:08.269183 TX DQ/DQS : PASS
3739 13:59:08.269286 RX DATLAT : PASS
3740 13:59:08.272528 RX DQ/DQS(Engine): PASS
3741 13:59:08.276219 TX OE : NO K
3742 13:59:08.276294 All Pass.
3743 13:59:08.276357
3744 13:59:08.276428 CH 0, Rank 1
3745 13:59:08.279338 SW Impedance : PASS
3746 13:59:08.282771 DUTY Scan : NO K
3747 13:59:08.282873 ZQ Calibration : PASS
3748 13:59:08.286164 Jitter Meter : NO K
3749 13:59:08.289134 CBT Training : PASS
3750 13:59:08.289236 Write leveling : PASS
3751 13:59:08.292453 RX DQS gating : PASS
3752 13:59:08.296166 RX DQ/DQS(RDDQC) : PASS
3753 13:59:08.296271 TX DQ/DQS : PASS
3754 13:59:08.299533 RX DATLAT : PASS
3755 13:59:08.302076 RX DQ/DQS(Engine): PASS
3756 13:59:08.302176 TX OE : NO K
3757 13:59:08.305329 All Pass.
3758 13:59:08.305426
3759 13:59:08.305521 CH 1, Rank 0
3760 13:59:08.308976 SW Impedance : PASS
3761 13:59:08.309081 DUTY Scan : NO K
3762 13:59:08.312277 ZQ Calibration : PASS
3763 13:59:08.315811 Jitter Meter : NO K
3764 13:59:08.315889 CBT Training : PASS
3765 13:59:08.319011 Write leveling : PASS
3766 13:59:08.322395 RX DQS gating : PASS
3767 13:59:08.322469 RX DQ/DQS(RDDQC) : PASS
3768 13:59:08.325961 TX DQ/DQS : PASS
3769 13:59:08.326061 RX DATLAT : PASS
3770 13:59:08.328799 RX DQ/DQS(Engine): PASS
3771 13:59:08.332173 TX OE : NO K
3772 13:59:08.332273 All Pass.
3773 13:59:08.332363
3774 13:59:08.332452 CH 1, Rank 1
3775 13:59:08.335422 SW Impedance : PASS
3776 13:59:08.338762 DUTY Scan : NO K
3777 13:59:08.338867 ZQ Calibration : PASS
3778 13:59:08.342118 Jitter Meter : NO K
3779 13:59:08.345892 CBT Training : PASS
3780 13:59:08.345990 Write leveling : PASS
3781 13:59:08.348546 RX DQS gating : PASS
3782 13:59:08.351889 RX DQ/DQS(RDDQC) : PASS
3783 13:59:08.351963 TX DQ/DQS : PASS
3784 13:59:08.355721 RX DATLAT : PASS
3785 13:59:08.358568 RX DQ/DQS(Engine): PASS
3786 13:59:08.358670 TX OE : NO K
3787 13:59:08.362337 All Pass.
3788 13:59:08.362436
3789 13:59:08.362526 DramC Write-DBI off
3790 13:59:08.365598 PER_BANK_REFRESH: Hybrid Mode
3791 13:59:08.365696 TX_TRACKING: ON
3792 13:59:08.375359 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3793 13:59:08.378372 [FAST_K] Save calibration result to emmc
3794 13:59:08.382308 dramc_set_vcore_voltage set vcore to 650000
3795 13:59:08.385315 Read voltage for 600, 5
3796 13:59:08.385396 Vio18 = 0
3797 13:59:08.388423 Vcore = 650000
3798 13:59:08.388497 Vdram = 0
3799 13:59:08.388565 Vddq = 0
3800 13:59:08.391701 Vmddr = 0
3801 13:59:08.395525 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3802 13:59:08.401722 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3803 13:59:08.401829 MEM_TYPE=3, freq_sel=19
3804 13:59:08.405243 sv_algorithm_assistance_LP4_1600
3805 13:59:08.411745 ============ PULL DRAM RESETB DOWN ============
3806 13:59:08.414843 ========== PULL DRAM RESETB DOWN end =========
3807 13:59:08.418528 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3808 13:59:08.421914 ===================================
3809 13:59:08.425118 LPDDR4 DRAM CONFIGURATION
3810 13:59:08.428078 ===================================
3811 13:59:08.428179 EX_ROW_EN[0] = 0x0
3812 13:59:08.431367 EX_ROW_EN[1] = 0x0
3813 13:59:08.434736 LP4Y_EN = 0x0
3814 13:59:08.434812 WORK_FSP = 0x0
3815 13:59:08.438168 WL = 0x2
3816 13:59:08.438269 RL = 0x2
3817 13:59:08.441512 BL = 0x2
3818 13:59:08.441611 RPST = 0x0
3819 13:59:08.444644 RD_PRE = 0x0
3820 13:59:08.444756 WR_PRE = 0x1
3821 13:59:08.448000 WR_PST = 0x0
3822 13:59:08.448100 DBI_WR = 0x0
3823 13:59:08.451475 DBI_RD = 0x0
3824 13:59:08.451548 OTF = 0x1
3825 13:59:08.454738 ===================================
3826 13:59:08.458347 ===================================
3827 13:59:08.461189 ANA top config
3828 13:59:08.464831 ===================================
3829 13:59:08.464933 DLL_ASYNC_EN = 0
3830 13:59:08.467819 ALL_SLAVE_EN = 1
3831 13:59:08.471300 NEW_RANK_MODE = 1
3832 13:59:08.474329 DLL_IDLE_MODE = 1
3833 13:59:08.477777 LP45_APHY_COMB_EN = 1
3834 13:59:08.477859 TX_ODT_DIS = 1
3835 13:59:08.481428 NEW_8X_MODE = 1
3836 13:59:08.484321 ===================================
3837 13:59:08.488201 ===================================
3838 13:59:08.491654 data_rate = 1200
3839 13:59:08.494175 CKR = 1
3840 13:59:08.497654 DQ_P2S_RATIO = 8
3841 13:59:08.501134 ===================================
3842 13:59:08.504301 CA_P2S_RATIO = 8
3843 13:59:08.504404 DQ_CA_OPEN = 0
3844 13:59:08.507630 DQ_SEMI_OPEN = 0
3845 13:59:08.510779 CA_SEMI_OPEN = 0
3846 13:59:08.514282 CA_FULL_RATE = 0
3847 13:59:08.517624 DQ_CKDIV4_EN = 1
3848 13:59:08.517730 CA_CKDIV4_EN = 1
3849 13:59:08.521179 CA_PREDIV_EN = 0
3850 13:59:08.524801 PH8_DLY = 0
3851 13:59:08.527513 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3852 13:59:08.530982 DQ_AAMCK_DIV = 4
3853 13:59:08.534703 CA_AAMCK_DIV = 4
3854 13:59:08.534810 CA_ADMCK_DIV = 4
3855 13:59:08.537356 DQ_TRACK_CA_EN = 0
3856 13:59:08.540737 CA_PICK = 600
3857 13:59:08.544197 CA_MCKIO = 600
3858 13:59:08.547380 MCKIO_SEMI = 0
3859 13:59:08.550479 PLL_FREQ = 2288
3860 13:59:08.554479 DQ_UI_PI_RATIO = 32
3861 13:59:08.557968 CA_UI_PI_RATIO = 0
3862 13:59:08.560605 ===================================
3863 13:59:08.564331 ===================================
3864 13:59:08.564442 memory_type:LPDDR4
3865 13:59:08.567660 GP_NUM : 10
3866 13:59:08.567741 SRAM_EN : 1
3867 13:59:08.570416 MD32_EN : 0
3868 13:59:08.573980 ===================================
3869 13:59:08.577274 [ANA_INIT] >>>>>>>>>>>>>>
3870 13:59:08.580484 <<<<<< [CONFIGURE PHASE]: ANA_TX
3871 13:59:08.583978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3872 13:59:08.587158 ===================================
3873 13:59:08.590443 data_rate = 1200,PCW = 0X5800
3874 13:59:08.594089 ===================================
3875 13:59:08.596832 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3876 13:59:08.600210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3877 13:59:08.607110 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3878 13:59:08.610262 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3879 13:59:08.613657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3880 13:59:08.616789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3881 13:59:08.620159 [ANA_INIT] flow start
3882 13:59:08.623527 [ANA_INIT] PLL >>>>>>>>
3883 13:59:08.623632 [ANA_INIT] PLL <<<<<<<<
3884 13:59:08.627081 [ANA_INIT] MIDPI >>>>>>>>
3885 13:59:08.629941 [ANA_INIT] MIDPI <<<<<<<<
3886 13:59:08.630021 [ANA_INIT] DLL >>>>>>>>
3887 13:59:08.633651 [ANA_INIT] flow end
3888 13:59:08.636997 ============ LP4 DIFF to SE enter ============
3889 13:59:08.643760 ============ LP4 DIFF to SE exit ============
3890 13:59:08.643841 [ANA_INIT] <<<<<<<<<<<<<
3891 13:59:08.646960 [Flow] Enable top DCM control >>>>>
3892 13:59:08.649958 [Flow] Enable top DCM control <<<<<
3893 13:59:08.653560 Enable DLL master slave shuffle
3894 13:59:08.659755 ==============================================================
3895 13:59:08.659833 Gating Mode config
3896 13:59:08.666496 ==============================================================
3897 13:59:08.669674 Config description:
3898 13:59:08.676375 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3899 13:59:08.683173 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3900 13:59:08.690119 SELPH_MODE 0: By rank 1: By Phase
3901 13:59:08.696653 ==============================================================
3902 13:59:08.696760 GAT_TRACK_EN = 1
3903 13:59:08.699824 RX_GATING_MODE = 2
3904 13:59:08.703134 RX_GATING_TRACK_MODE = 2
3905 13:59:08.706260 SELPH_MODE = 1
3906 13:59:08.709943 PICG_EARLY_EN = 1
3907 13:59:08.713106 VALID_LAT_VALUE = 1
3908 13:59:08.719956 ==============================================================
3909 13:59:08.723219 Enter into Gating configuration >>>>
3910 13:59:08.726049 Exit from Gating configuration <<<<
3911 13:59:08.729565 Enter into DVFS_PRE_config >>>>>
3912 13:59:08.739465 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3913 13:59:08.742870 Exit from DVFS_PRE_config <<<<<
3914 13:59:08.746284 Enter into PICG configuration >>>>
3915 13:59:08.749467 Exit from PICG configuration <<<<
3916 13:59:08.752762 [RX_INPUT] configuration >>>>>
3917 13:59:08.755897 [RX_INPUT] configuration <<<<<
3918 13:59:08.759503 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3919 13:59:08.766011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3920 13:59:08.772772 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3921 13:59:08.775743 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3922 13:59:08.782593 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3923 13:59:08.789017 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3924 13:59:08.792672 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3925 13:59:08.795915 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3926 13:59:08.802540 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3927 13:59:08.805609 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3928 13:59:08.809056 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3929 13:59:08.815486 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3930 13:59:08.819313 ===================================
3931 13:59:08.819455 LPDDR4 DRAM CONFIGURATION
3932 13:59:08.822690 ===================================
3933 13:59:08.825714 EX_ROW_EN[0] = 0x0
3934 13:59:08.829029 EX_ROW_EN[1] = 0x0
3935 13:59:08.829142 LP4Y_EN = 0x0
3936 13:59:08.832539 WORK_FSP = 0x0
3937 13:59:08.832647 WL = 0x2
3938 13:59:08.835821 RL = 0x2
3939 13:59:08.835902 BL = 0x2
3940 13:59:08.838785 RPST = 0x0
3941 13:59:08.838868 RD_PRE = 0x0
3942 13:59:08.842258 WR_PRE = 0x1
3943 13:59:08.842339 WR_PST = 0x0
3944 13:59:08.845650 DBI_WR = 0x0
3945 13:59:08.845731 DBI_RD = 0x0
3946 13:59:08.848943 OTF = 0x1
3947 13:59:08.852580 ===================================
3948 13:59:08.855406 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3949 13:59:08.859268 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3950 13:59:08.865409 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3951 13:59:08.868909 ===================================
3952 13:59:08.868994 LPDDR4 DRAM CONFIGURATION
3953 13:59:08.872334 ===================================
3954 13:59:08.875645 EX_ROW_EN[0] = 0x10
3955 13:59:08.878604 EX_ROW_EN[1] = 0x0
3956 13:59:08.878677 LP4Y_EN = 0x0
3957 13:59:08.882673 WORK_FSP = 0x0
3958 13:59:08.882775 WL = 0x2
3959 13:59:08.885313 RL = 0x2
3960 13:59:08.885413 BL = 0x2
3961 13:59:08.888744 RPST = 0x0
3962 13:59:08.888842 RD_PRE = 0x0
3963 13:59:08.892280 WR_PRE = 0x1
3964 13:59:08.892365 WR_PST = 0x0
3965 13:59:08.895357 DBI_WR = 0x0
3966 13:59:08.895481 DBI_RD = 0x0
3967 13:59:08.898469 OTF = 0x1
3968 13:59:08.902215 ===================================
3969 13:59:08.908486 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3970 13:59:08.911886 nWR fixed to 30
3971 13:59:08.911969 [ModeRegInit_LP4] CH0 RK0
3972 13:59:08.915095 [ModeRegInit_LP4] CH0 RK1
3973 13:59:08.918586 [ModeRegInit_LP4] CH1 RK0
3974 13:59:08.921644 [ModeRegInit_LP4] CH1 RK1
3975 13:59:08.921744 match AC timing 17
3976 13:59:08.925372 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3977 13:59:08.931410 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3978 13:59:08.934918 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3979 13:59:08.941910 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3980 13:59:08.945076 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3981 13:59:08.945178 ==
3982 13:59:08.948210 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 13:59:08.951339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 13:59:08.951462 ==
3985 13:59:08.958260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3986 13:59:08.964985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3987 13:59:08.967894 [CA 0] Center 37 (7~67) winsize 61
3988 13:59:08.971559 [CA 1] Center 36 (6~67) winsize 62
3989 13:59:08.975031 [CA 2] Center 35 (5~65) winsize 61
3990 13:59:08.978387 [CA 3] Center 35 (5~65) winsize 61
3991 13:59:08.981256 [CA 4] Center 34 (4~64) winsize 61
3992 13:59:08.984520 [CA 5] Center 33 (3~64) winsize 62
3993 13:59:08.984590
3994 13:59:08.987975 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3995 13:59:08.988070
3996 13:59:08.991487 [CATrainingPosCal] consider 1 rank data
3997 13:59:08.994966 u2DelayCellTimex100 = 270/100 ps
3998 13:59:08.998049 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3999 13:59:09.001552 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4000 13:59:09.004485 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4001 13:59:09.007774 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
4002 13:59:09.011099 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4003 13:59:09.014655 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4004 13:59:09.014751
4005 13:59:09.021233 CA PerBit enable=1, Macro0, CA PI delay=33
4006 13:59:09.021308
4007 13:59:09.021370 [CBTSetCACLKResult] CA Dly = 33
4008 13:59:09.024716 CS Dly: 7 (0~38)
4009 13:59:09.024786 ==
4010 13:59:09.027945 Dram Type= 6, Freq= 0, CH_0, rank 1
4011 13:59:09.030996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 13:59:09.031092 ==
4013 13:59:09.037667 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4014 13:59:09.044663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4015 13:59:09.048088 [CA 0] Center 37 (7~67) winsize 61
4016 13:59:09.050933 [CA 1] Center 37 (7~67) winsize 61
4017 13:59:09.054796 [CA 2] Center 35 (5~65) winsize 61
4018 13:59:09.057588 [CA 3] Center 35 (5~65) winsize 61
4019 13:59:09.060829 [CA 4] Center 34 (4~65) winsize 62
4020 13:59:09.064328 [CA 5] Center 33 (3~64) winsize 62
4021 13:59:09.064431
4022 13:59:09.067348 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4023 13:59:09.067463
4024 13:59:09.070830 [CATrainingPosCal] consider 2 rank data
4025 13:59:09.074541 u2DelayCellTimex100 = 270/100 ps
4026 13:59:09.077820 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
4027 13:59:09.080950 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
4028 13:59:09.084537 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4029 13:59:09.087373 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
4030 13:59:09.094354 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4031 13:59:09.097247 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4032 13:59:09.097354
4033 13:59:09.100612 CA PerBit enable=1, Macro0, CA PI delay=33
4034 13:59:09.100711
4035 13:59:09.103989 [CBTSetCACLKResult] CA Dly = 33
4036 13:59:09.104066 CS Dly: 6 (0~37)
4037 13:59:09.104157
4038 13:59:09.107665 ----->DramcWriteLeveling(PI) begin...
4039 13:59:09.107800 ==
4040 13:59:09.111011 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 13:59:09.117587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 13:59:09.117688 ==
4043 13:59:09.120940 Write leveling (Byte 0): 32 => 32
4044 13:59:09.121039 Write leveling (Byte 1): 31 => 31
4045 13:59:09.123928 DramcWriteLeveling(PI) end<-----
4046 13:59:09.124026
4047 13:59:09.124096 ==
4048 13:59:09.127309 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 13:59:09.133876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 13:59:09.133952 ==
4051 13:59:09.137258 [Gating] SW mode calibration
4052 13:59:09.144197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4053 13:59:09.147255 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4054 13:59:09.154258 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4055 13:59:09.157323 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 13:59:09.160361 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 13:59:09.167150 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4058 13:59:09.170912 0 9 16 | B1->B0 | 3232 2b2b | 0 1 | (0 1) (1 0)
4059 13:59:09.174118 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 13:59:09.180656 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 13:59:09.183674 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 13:59:09.186694 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 13:59:09.193373 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 13:59:09.196779 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 13:59:09.200181 0 10 12 | B1->B0 | 2727 2f2f | 0 1 | (0 0) (0 0)
4066 13:59:09.206608 0 10 16 | B1->B0 | 3232 3a3a | 1 0 | (0 0) (0 0)
4067 13:59:09.210595 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 13:59:09.213253 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 13:59:09.219911 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 13:59:09.223858 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 13:59:09.226400 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 13:59:09.233698 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 13:59:09.236488 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4074 13:59:09.239767 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4075 13:59:09.246811 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 13:59:09.250135 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 13:59:09.253058 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 13:59:09.256716 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 13:59:09.263221 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 13:59:09.266150 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 13:59:09.270025 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 13:59:09.276330 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 13:59:09.279585 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 13:59:09.282781 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 13:59:09.290021 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 13:59:09.292885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 13:59:09.296373 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 13:59:09.303173 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 13:59:09.306076 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4090 13:59:09.309704 Total UI for P1: 0, mck2ui 16
4091 13:59:09.312523 best dqsien dly found for B0: ( 0, 13, 10)
4092 13:59:09.315999 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 13:59:09.319295 Total UI for P1: 0, mck2ui 16
4094 13:59:09.322953 best dqsien dly found for B1: ( 0, 13, 14)
4095 13:59:09.325880 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4096 13:59:09.329357 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4097 13:59:09.332667
4098 13:59:09.336058 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4099 13:59:09.339026 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4100 13:59:09.342306 [Gating] SW calibration Done
4101 13:59:09.342409 ==
4102 13:59:09.345734 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 13:59:09.349157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 13:59:09.349261 ==
4105 13:59:09.352417 RX Vref Scan: 0
4106 13:59:09.352498
4107 13:59:09.352561 RX Vref 0 -> 0, step: 1
4108 13:59:09.352635
4109 13:59:09.355906 RX Delay -230 -> 252, step: 16
4110 13:59:09.359059 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4111 13:59:09.366032 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4112 13:59:09.368757 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4113 13:59:09.372226 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4114 13:59:09.375746 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4115 13:59:09.379249 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4116 13:59:09.385176 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4117 13:59:09.388542 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4118 13:59:09.391970 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4119 13:59:09.395250 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4120 13:59:09.401751 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4121 13:59:09.405032 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4122 13:59:09.409087 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4123 13:59:09.412256 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4124 13:59:09.418363 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4125 13:59:09.421759 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4126 13:59:09.421842 ==
4127 13:59:09.425297 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 13:59:09.428621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 13:59:09.428708 ==
4130 13:59:09.431722 DQS Delay:
4131 13:59:09.431824 DQS0 = 0, DQS1 = 0
4132 13:59:09.431912 DQM Delay:
4133 13:59:09.435157 DQM0 = 37, DQM1 = 29
4134 13:59:09.435258 DQ Delay:
4135 13:59:09.438278 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4136 13:59:09.441532 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4137 13:59:09.445170 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =25
4138 13:59:09.448180 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4139 13:59:09.448259
4140 13:59:09.448329
4141 13:59:09.451442 ==
4142 13:59:09.451524 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 13:59:09.457692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 13:59:09.457799 ==
4145 13:59:09.457893
4146 13:59:09.457983
4147 13:59:09.460947 TX Vref Scan disable
4148 13:59:09.461046 == TX Byte 0 ==
4149 13:59:09.464680 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4150 13:59:09.471016 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4151 13:59:09.471122 == TX Byte 1 ==
4152 13:59:09.477527 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4153 13:59:09.481357 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4154 13:59:09.481461 ==
4155 13:59:09.484672 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 13:59:09.487528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 13:59:09.487609 ==
4158 13:59:09.487678
4159 13:59:09.487770
4160 13:59:09.490801 TX Vref Scan disable
4161 13:59:09.494167 == TX Byte 0 ==
4162 13:59:09.497739 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4163 13:59:09.500648 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4164 13:59:09.504367 == TX Byte 1 ==
4165 13:59:09.507490 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4166 13:59:09.510690 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4167 13:59:09.510795
4168 13:59:09.514475 [DATLAT]
4169 13:59:09.514580 Freq=600, CH0 RK0
4170 13:59:09.514675
4171 13:59:09.517187 DATLAT Default: 0x9
4172 13:59:09.517291 0, 0xFFFF, sum = 0
4173 13:59:09.520591 1, 0xFFFF, sum = 0
4174 13:59:09.520673 2, 0xFFFF, sum = 0
4175 13:59:09.524364 3, 0xFFFF, sum = 0
4176 13:59:09.524472 4, 0xFFFF, sum = 0
4177 13:59:09.527475 5, 0xFFFF, sum = 0
4178 13:59:09.527553 6, 0xFFFF, sum = 0
4179 13:59:09.530376 7, 0xFFFF, sum = 0
4180 13:59:09.530488 8, 0x0, sum = 1
4181 13:59:09.533781 9, 0x0, sum = 2
4182 13:59:09.533887 10, 0x0, sum = 3
4183 13:59:09.537024 11, 0x0, sum = 4
4184 13:59:09.537132 best_step = 9
4185 13:59:09.537223
4186 13:59:09.537314 ==
4187 13:59:09.541025 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 13:59:09.547221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 13:59:09.547342 ==
4190 13:59:09.547464 RX Vref Scan: 1
4191 13:59:09.547557
4192 13:59:09.550294 RX Vref 0 -> 0, step: 1
4193 13:59:09.550393
4194 13:59:09.553896 RX Delay -195 -> 252, step: 8
4195 13:59:09.554000
4196 13:59:09.557048 Set Vref, RX VrefLevel [Byte0]: 60
4197 13:59:09.560302 [Byte1]: 52
4198 13:59:09.560402
4199 13:59:09.563502 Final RX Vref Byte 0 = 60 to rank0
4200 13:59:09.566755 Final RX Vref Byte 1 = 52 to rank0
4201 13:59:09.570550 Final RX Vref Byte 0 = 60 to rank1
4202 13:59:09.573868 Final RX Vref Byte 1 = 52 to rank1==
4203 13:59:09.577266 Dram Type= 6, Freq= 0, CH_0, rank 0
4204 13:59:09.580153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 13:59:09.580256 ==
4206 13:59:09.583639 DQS Delay:
4207 13:59:09.583750 DQS0 = 0, DQS1 = 0
4208 13:59:09.583845 DQM Delay:
4209 13:59:09.586846 DQM0 = 35, DQM1 = 29
4210 13:59:09.586946 DQ Delay:
4211 13:59:09.590263 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4212 13:59:09.593314 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =48
4213 13:59:09.596828 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4214 13:59:09.600235 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4215 13:59:09.600319
4216 13:59:09.600418
4217 13:59:09.610205 [DQSOSCAuto] RK0, (LSB)MR18= 0x4241, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4218 13:59:09.613353 CH0 RK0: MR19=808, MR18=4241
4219 13:59:09.616822 CH0_RK0: MR19=0x808, MR18=0x4241, DQSOSC=397, MR23=63, INC=166, DEC=110
4220 13:59:09.616925
4221 13:59:09.620158 ----->DramcWriteLeveling(PI) begin...
4222 13:59:09.623359 ==
4223 13:59:09.626600 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 13:59:09.629812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 13:59:09.629894 ==
4226 13:59:09.633076 Write leveling (Byte 0): 33 => 33
4227 13:59:09.636828 Write leveling (Byte 1): 30 => 30
4228 13:59:09.639833 DramcWriteLeveling(PI) end<-----
4229 13:59:09.639943
4230 13:59:09.640039 ==
4231 13:59:09.643280 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 13:59:09.646328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 13:59:09.646436 ==
4234 13:59:09.649946 [Gating] SW mode calibration
4235 13:59:09.656890 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4236 13:59:09.663216 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4237 13:59:09.666249 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4238 13:59:09.669386 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4239 13:59:09.676272 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 13:59:09.679645 0 9 12 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
4241 13:59:09.682830 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
4242 13:59:09.689581 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 13:59:09.692571 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 13:59:09.696006 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 13:59:09.703018 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 13:59:09.705735 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 13:59:09.709419 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 13:59:09.715727 0 10 12 | B1->B0 | 2a2a 3332 | 0 1 | (0 0) (0 0)
4249 13:59:09.719647 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4250 13:59:09.722352 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 13:59:09.728990 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 13:59:09.732623 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 13:59:09.735571 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 13:59:09.742519 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 13:59:09.745621 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 13:59:09.749240 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 13:59:09.756205 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 13:59:09.759139 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 13:59:09.762129 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 13:59:09.765495 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 13:59:09.772118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 13:59:09.776119 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 13:59:09.778912 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 13:59:09.785771 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 13:59:09.788717 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 13:59:09.792340 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 13:59:09.798551 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 13:59:09.801859 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 13:59:09.805196 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 13:59:09.811731 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 13:59:09.815269 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 13:59:09.819033 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 13:59:09.825241 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 13:59:09.828570 Total UI for P1: 0, mck2ui 16
4275 13:59:09.831977 best dqsien dly found for B0: ( 0, 13, 14)
4276 13:59:09.832075 Total UI for P1: 0, mck2ui 16
4277 13:59:09.838549 best dqsien dly found for B1: ( 0, 13, 14)
4278 13:59:09.842232 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4279 13:59:09.845236 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4280 13:59:09.845341
4281 13:59:09.848266 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4282 13:59:09.851730 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4283 13:59:09.855088 [Gating] SW calibration Done
4284 13:59:09.855192 ==
4285 13:59:09.858483 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 13:59:09.861798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 13:59:09.861878 ==
4288 13:59:09.865141 RX Vref Scan: 0
4289 13:59:09.865240
4290 13:59:09.865331 RX Vref 0 -> 0, step: 1
4291 13:59:09.865421
4292 13:59:09.868821 RX Delay -230 -> 252, step: 16
4293 13:59:09.874894 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4294 13:59:09.878166 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4295 13:59:09.881629 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4296 13:59:09.885139 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4297 13:59:09.891322 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4298 13:59:09.894855 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4299 13:59:09.898417 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4300 13:59:09.901502 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4301 13:59:09.904947 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4302 13:59:09.911656 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4303 13:59:09.914767 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4304 13:59:09.918332 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4305 13:59:09.921279 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4306 13:59:09.928000 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4307 13:59:09.931014 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4308 13:59:09.934623 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4309 13:59:09.934722 ==
4310 13:59:09.937632 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 13:59:09.941284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 13:59:09.944523 ==
4313 13:59:09.944626 DQS Delay:
4314 13:59:09.944717 DQS0 = 0, DQS1 = 0
4315 13:59:09.947534 DQM Delay:
4316 13:59:09.947634 DQM0 = 35, DQM1 = 28
4317 13:59:09.951188 DQ Delay:
4318 13:59:09.951293 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4319 13:59:09.954282 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4320 13:59:09.957613 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4321 13:59:09.961025 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4322 13:59:09.964477
4323 13:59:09.964553
4324 13:59:09.964623 ==
4325 13:59:09.967538 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 13:59:09.970847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 13:59:09.970948 ==
4328 13:59:09.971038
4329 13:59:09.971126
4330 13:59:09.974709 TX Vref Scan disable
4331 13:59:09.974817 == TX Byte 0 ==
4332 13:59:09.981555 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4333 13:59:09.984370 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4334 13:59:09.984473 == TX Byte 1 ==
4335 13:59:09.990667 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4336 13:59:09.994073 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4337 13:59:09.994175 ==
4338 13:59:09.997355 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 13:59:10.000804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 13:59:10.000911 ==
4341 13:59:10.001005
4342 13:59:10.001104
4343 13:59:10.004183 TX Vref Scan disable
4344 13:59:10.007829 == TX Byte 0 ==
4345 13:59:10.010709 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4346 13:59:10.014084 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4347 13:59:10.017275 == TX Byte 1 ==
4348 13:59:10.020534 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4349 13:59:10.023862 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4350 13:59:10.027179
4351 13:59:10.027256 [DATLAT]
4352 13:59:10.027319 Freq=600, CH0 RK1
4353 13:59:10.027379
4354 13:59:10.031104 DATLAT Default: 0x9
4355 13:59:10.031205 0, 0xFFFF, sum = 0
4356 13:59:10.034566 1, 0xFFFF, sum = 0
4357 13:59:10.034674 2, 0xFFFF, sum = 0
4358 13:59:10.037465 3, 0xFFFF, sum = 0
4359 13:59:10.037540 4, 0xFFFF, sum = 0
4360 13:59:10.040774 5, 0xFFFF, sum = 0
4361 13:59:10.043929 6, 0xFFFF, sum = 0
4362 13:59:10.044044 7, 0xFFFF, sum = 0
4363 13:59:10.044143 8, 0x0, sum = 1
4364 13:59:10.047342 9, 0x0, sum = 2
4365 13:59:10.047471 10, 0x0, sum = 3
4366 13:59:10.050512 11, 0x0, sum = 4
4367 13:59:10.050623 best_step = 9
4368 13:59:10.050712
4369 13:59:10.050799 ==
4370 13:59:10.054004 Dram Type= 6, Freq= 0, CH_0, rank 1
4371 13:59:10.060670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 13:59:10.060778 ==
4373 13:59:10.060872 RX Vref Scan: 0
4374 13:59:10.060962
4375 13:59:10.063805 RX Vref 0 -> 0, step: 1
4376 13:59:10.063877
4377 13:59:10.067096 RX Delay -195 -> 252, step: 8
4378 13:59:10.070566 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4379 13:59:10.077209 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4380 13:59:10.080656 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4381 13:59:10.084007 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4382 13:59:10.087169 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4383 13:59:10.093804 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4384 13:59:10.096758 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4385 13:59:10.100211 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4386 13:59:10.103738 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4387 13:59:10.107051 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4388 13:59:10.113474 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4389 13:59:10.116603 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4390 13:59:10.120046 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4391 13:59:10.123369 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4392 13:59:10.129969 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4393 13:59:10.133205 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4394 13:59:10.133280 ==
4395 13:59:10.136801 Dram Type= 6, Freq= 0, CH_0, rank 1
4396 13:59:10.139933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 13:59:10.140025 ==
4398 13:59:10.143224 DQS Delay:
4399 13:59:10.143324 DQS0 = 0, DQS1 = 0
4400 13:59:10.143452 DQM Delay:
4401 13:59:10.146551 DQM0 = 34, DQM1 = 28
4402 13:59:10.146651 DQ Delay:
4403 13:59:10.150027 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4404 13:59:10.153044 DQ4 =36, DQ5 =20, DQ6 =44, DQ7 =44
4405 13:59:10.156561 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4406 13:59:10.159651 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4407 13:59:10.159743
4408 13:59:10.159807
4409 13:59:10.169832 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4410 13:59:10.173130 CH0 RK1: MR19=808, MR18=6A38
4411 13:59:10.176934 CH0_RK1: MR19=0x808, MR18=0x6A38, DQSOSC=389, MR23=63, INC=173, DEC=115
4412 13:59:10.179961 [RxdqsGatingPostProcess] freq 600
4413 13:59:10.186378 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4414 13:59:10.189951 Pre-setting of DQS Precalculation
4415 13:59:10.193026 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4416 13:59:10.193128 ==
4417 13:59:10.196283 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 13:59:10.202827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 13:59:10.202935 ==
4420 13:59:10.206183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4421 13:59:10.212775 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4422 13:59:10.216100 [CA 0] Center 36 (6~66) winsize 61
4423 13:59:10.219630 [CA 1] Center 36 (6~66) winsize 61
4424 13:59:10.223119 [CA 2] Center 34 (4~65) winsize 62
4425 13:59:10.226029 [CA 3] Center 34 (4~65) winsize 62
4426 13:59:10.229647 [CA 4] Center 34 (4~65) winsize 62
4427 13:59:10.232951 [CA 5] Center 33 (3~64) winsize 62
4428 13:59:10.233025
4429 13:59:10.236570 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4430 13:59:10.236668
4431 13:59:10.239523 [CATrainingPosCal] consider 1 rank data
4432 13:59:10.242684 u2DelayCellTimex100 = 270/100 ps
4433 13:59:10.246387 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4434 13:59:10.252861 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4435 13:59:10.255992 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 13:59:10.259526 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4437 13:59:10.262981 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4438 13:59:10.266545 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4439 13:59:10.266625
4440 13:59:10.269849 CA PerBit enable=1, Macro0, CA PI delay=33
4441 13:59:10.269949
4442 13:59:10.272689 [CBTSetCACLKResult] CA Dly = 33
4443 13:59:10.272786 CS Dly: 6 (0~37)
4444 13:59:10.276186 ==
4445 13:59:10.279108 Dram Type= 6, Freq= 0, CH_1, rank 1
4446 13:59:10.282766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 13:59:10.282867 ==
4448 13:59:10.286288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4449 13:59:10.292394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4450 13:59:10.296391 [CA 0] Center 36 (6~66) winsize 61
4451 13:59:10.299986 [CA 1] Center 36 (6~66) winsize 61
4452 13:59:10.303083 [CA 2] Center 34 (4~65) winsize 62
4453 13:59:10.306978 [CA 3] Center 34 (3~65) winsize 63
4454 13:59:10.309794 [CA 4] Center 34 (4~65) winsize 62
4455 13:59:10.313455 [CA 5] Center 33 (3~64) winsize 62
4456 13:59:10.313548
4457 13:59:10.316585 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4458 13:59:10.316674
4459 13:59:10.319829 [CATrainingPosCal] consider 2 rank data
4460 13:59:10.323168 u2DelayCellTimex100 = 270/100 ps
4461 13:59:10.326251 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4462 13:59:10.329716 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4463 13:59:10.336343 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4464 13:59:10.339836 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4465 13:59:10.343274 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4466 13:59:10.346102 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4467 13:59:10.346210
4468 13:59:10.349743 CA PerBit enable=1, Macro0, CA PI delay=33
4469 13:59:10.349843
4470 13:59:10.353426 [CBTSetCACLKResult] CA Dly = 33
4471 13:59:10.353528 CS Dly: 6 (0~38)
4472 13:59:10.353628
4473 13:59:10.359489 ----->DramcWriteLeveling(PI) begin...
4474 13:59:10.359579 ==
4475 13:59:10.362647 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 13:59:10.366188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 13:59:10.366293 ==
4478 13:59:10.369431 Write leveling (Byte 0): 29 => 29
4479 13:59:10.373027 Write leveling (Byte 1): 29 => 29
4480 13:59:10.375950 DramcWriteLeveling(PI) end<-----
4481 13:59:10.376050
4482 13:59:10.376140 ==
4483 13:59:10.379546 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 13:59:10.382473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 13:59:10.382576 ==
4486 13:59:10.385737 [Gating] SW mode calibration
4487 13:59:10.392344 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4488 13:59:10.399001 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4489 13:59:10.402718 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4490 13:59:10.405571 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4491 13:59:10.412198 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4492 13:59:10.415635 0 9 12 | B1->B0 | 3030 3030 | 1 1 | (0 0) (0 1)
4493 13:59:10.419120 0 9 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4494 13:59:10.425780 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 13:59:10.428760 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 13:59:10.432922 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 13:59:10.438602 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 13:59:10.442494 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 13:59:10.445274 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 13:59:10.451893 0 10 12 | B1->B0 | 2f2f 3131 | 1 0 | (0 0) (0 0)
4501 13:59:10.455104 0 10 16 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
4502 13:59:10.458608 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 13:59:10.465598 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 13:59:10.469020 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 13:59:10.471812 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 13:59:10.478320 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 13:59:10.481532 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 13:59:10.484843 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4509 13:59:10.491701 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4510 13:59:10.495157 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 13:59:10.498207 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 13:59:10.504650 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 13:59:10.508175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 13:59:10.511316 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 13:59:10.517911 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 13:59:10.521670 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 13:59:10.524544 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 13:59:10.531380 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 13:59:10.534432 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 13:59:10.537891 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 13:59:10.544519 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 13:59:10.547740 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 13:59:10.551264 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 13:59:10.557478 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4525 13:59:10.557589 Total UI for P1: 0, mck2ui 16
4526 13:59:10.560767 best dqsien dly found for B0: ( 0, 13, 10)
4527 13:59:10.567684 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4528 13:59:10.570590 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 13:59:10.574252 Total UI for P1: 0, mck2ui 16
4530 13:59:10.577512 best dqsien dly found for B1: ( 0, 13, 14)
4531 13:59:10.580634 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4532 13:59:10.583872 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4533 13:59:10.583979
4534 13:59:10.587336 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4535 13:59:10.594250 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4536 13:59:10.594377 [Gating] SW calibration Done
4537 13:59:10.594479 ==
4538 13:59:10.597096 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 13:59:10.603658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 13:59:10.603775 ==
4541 13:59:10.603875 RX Vref Scan: 0
4542 13:59:10.603974
4543 13:59:10.607225 RX Vref 0 -> 0, step: 1
4544 13:59:10.607334
4545 13:59:10.610398 RX Delay -230 -> 252, step: 16
4546 13:59:10.613555 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4547 13:59:10.617172 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4548 13:59:10.623354 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4549 13:59:10.626874 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4550 13:59:10.630052 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4551 13:59:10.633683 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4552 13:59:10.640482 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4553 13:59:10.643659 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4554 13:59:10.647232 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4555 13:59:10.650139 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4556 13:59:10.653174 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4557 13:59:10.660349 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4558 13:59:10.663767 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4559 13:59:10.666603 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4560 13:59:10.669977 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4561 13:59:10.676822 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4562 13:59:10.676931 ==
4563 13:59:10.679731 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 13:59:10.683307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 13:59:10.683426 ==
4566 13:59:10.683522 DQS Delay:
4567 13:59:10.686915 DQS0 = 0, DQS1 = 0
4568 13:59:10.687018 DQM Delay:
4569 13:59:10.690376 DQM0 = 38, DQM1 = 28
4570 13:59:10.690484 DQ Delay:
4571 13:59:10.693225 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4572 13:59:10.696848 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4573 13:59:10.699812 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4574 13:59:10.703258 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4575 13:59:10.703373
4576 13:59:10.703472
4577 13:59:10.703537 ==
4578 13:59:10.706682 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 13:59:10.709651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 13:59:10.709765 ==
4581 13:59:10.713198
4582 13:59:10.713304
4583 13:59:10.713410 TX Vref Scan disable
4584 13:59:10.716704 == TX Byte 0 ==
4585 13:59:10.719882 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4586 13:59:10.723156 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4587 13:59:10.726331 == TX Byte 1 ==
4588 13:59:10.729872 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4589 13:59:10.732926 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4590 13:59:10.733022 ==
4591 13:59:10.736622 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 13:59:10.743065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 13:59:10.743177 ==
4594 13:59:10.743270
4595 13:59:10.743360
4596 13:59:10.746042 TX Vref Scan disable
4597 13:59:10.746144 == TX Byte 0 ==
4598 13:59:10.752899 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4599 13:59:10.756251 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4600 13:59:10.756354 == TX Byte 1 ==
4601 13:59:10.763118 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4602 13:59:10.766729 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4603 13:59:10.766807
4604 13:59:10.766893 [DATLAT]
4605 13:59:10.769744 Freq=600, CH1 RK0
4606 13:59:10.769845
4607 13:59:10.769939 DATLAT Default: 0x9
4608 13:59:10.773067 0, 0xFFFF, sum = 0
4609 13:59:10.773267 1, 0xFFFF, sum = 0
4610 13:59:10.776236 2, 0xFFFF, sum = 0
4611 13:59:10.776392 3, 0xFFFF, sum = 0
4612 13:59:10.779312 4, 0xFFFF, sum = 0
4613 13:59:10.779456 5, 0xFFFF, sum = 0
4614 13:59:10.782590 6, 0xFFFF, sum = 0
4615 13:59:10.785963 7, 0xFFFF, sum = 0
4616 13:59:10.786063 8, 0x0, sum = 1
4617 13:59:10.786162 9, 0x0, sum = 2
4618 13:59:10.789438 10, 0x0, sum = 3
4619 13:59:10.789517 11, 0x0, sum = 4
4620 13:59:10.792636 best_step = 9
4621 13:59:10.792730
4622 13:59:10.792823 ==
4623 13:59:10.796319 Dram Type= 6, Freq= 0, CH_1, rank 0
4624 13:59:10.799554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 13:59:10.799678 ==
4626 13:59:10.802984 RX Vref Scan: 1
4627 13:59:10.803114
4628 13:59:10.803235 RX Vref 0 -> 0, step: 1
4629 13:59:10.803324
4630 13:59:10.806354 RX Delay -195 -> 252, step: 8
4631 13:59:10.806481
4632 13:59:10.809242 Set Vref, RX VrefLevel [Byte0]: 56
4633 13:59:10.812510 [Byte1]: 49
4634 13:59:10.816926
4635 13:59:10.817078 Final RX Vref Byte 0 = 56 to rank0
4636 13:59:10.819851 Final RX Vref Byte 1 = 49 to rank0
4637 13:59:10.823632 Final RX Vref Byte 0 = 56 to rank1
4638 13:59:10.826367 Final RX Vref Byte 1 = 49 to rank1==
4639 13:59:10.830162 Dram Type= 6, Freq= 0, CH_1, rank 0
4640 13:59:10.836436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 13:59:10.836547 ==
4642 13:59:10.836645 DQS Delay:
4643 13:59:10.836748 DQS0 = 0, DQS1 = 0
4644 13:59:10.839973 DQM Delay:
4645 13:59:10.840076 DQM0 = 39, DQM1 = 28
4646 13:59:10.842853 DQ Delay:
4647 13:59:10.846285 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4648 13:59:10.849906 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4649 13:59:10.853001 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4650 13:59:10.856169 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4651 13:59:10.856272
4652 13:59:10.856369
4653 13:59:10.863335 [DQSOSCAuto] RK0, (LSB)MR18= 0x2836, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
4654 13:59:10.866541 CH1 RK0: MR19=808, MR18=2836
4655 13:59:10.872984 CH1_RK0: MR19=0x808, MR18=0x2836, DQSOSC=399, MR23=63, INC=164, DEC=109
4656 13:59:10.873094
4657 13:59:10.876382 ----->DramcWriteLeveling(PI) begin...
4658 13:59:10.876496 ==
4659 13:59:10.879469 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 13:59:10.882811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 13:59:10.882925 ==
4662 13:59:10.885985 Write leveling (Byte 0): 31 => 31
4663 13:59:10.889994 Write leveling (Byte 1): 31 => 31
4664 13:59:10.892655 DramcWriteLeveling(PI) end<-----
4665 13:59:10.892762
4666 13:59:10.892857 ==
4667 13:59:10.895871 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 13:59:10.899308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 13:59:10.899426 ==
4670 13:59:10.903032 [Gating] SW mode calibration
4671 13:59:10.909134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4672 13:59:10.915945 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4673 13:59:10.918980 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4674 13:59:10.926336 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4675 13:59:10.929517 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4676 13:59:10.932254 0 9 12 | B1->B0 | 3030 2e2e | 1 0 | (1 0) (0 0)
4677 13:59:10.939238 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4678 13:59:10.942554 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 13:59:10.945583 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 13:59:10.952478 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 13:59:10.955570 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 13:59:10.959210 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 13:59:10.965533 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4684 13:59:10.968814 0 10 12 | B1->B0 | 302f 3e3e | 1 0 | (0 0) (0 0)
4685 13:59:10.972529 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4686 13:59:10.975860 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 13:59:10.982150 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 13:59:10.985624 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 13:59:10.989051 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 13:59:10.995885 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 13:59:10.999268 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 13:59:11.002027 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4693 13:59:11.008745 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 13:59:11.012210 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 13:59:11.015606 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 13:59:11.021850 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 13:59:11.025555 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 13:59:11.028902 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 13:59:11.035124 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 13:59:11.038495 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 13:59:11.041946 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 13:59:11.048334 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 13:59:11.051808 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 13:59:11.054856 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 13:59:11.061879 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 13:59:11.064861 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 13:59:11.068362 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 13:59:11.075445 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4709 13:59:11.078213 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4710 13:59:11.081988 Total UI for P1: 0, mck2ui 16
4711 13:59:11.085377 best dqsien dly found for B0: ( 0, 13, 12)
4712 13:59:11.088279 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 13:59:11.091856 Total UI for P1: 0, mck2ui 16
4714 13:59:11.095330 best dqsien dly found for B1: ( 0, 13, 16)
4715 13:59:11.098281 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4716 13:59:11.101419 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4717 13:59:11.101536
4718 13:59:11.108312 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4719 13:59:11.111415 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4720 13:59:11.111536 [Gating] SW calibration Done
4721 13:59:11.114715 ==
4722 13:59:11.118581 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 13:59:11.121217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 13:59:11.121340 ==
4725 13:59:11.121412 RX Vref Scan: 0
4726 13:59:11.121509
4727 13:59:11.124851 RX Vref 0 -> 0, step: 1
4728 13:59:11.124964
4729 13:59:11.128197 RX Delay -230 -> 252, step: 16
4730 13:59:11.131655 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4731 13:59:11.134836 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4732 13:59:11.141204 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4733 13:59:11.144867 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4734 13:59:11.147842 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4735 13:59:11.151098 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4736 13:59:11.157588 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4737 13:59:11.161305 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4738 13:59:11.164422 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4739 13:59:11.167878 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4740 13:59:11.171267 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4741 13:59:11.178271 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4742 13:59:11.180901 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4743 13:59:11.184274 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4744 13:59:11.187598 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4745 13:59:11.194489 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4746 13:59:11.194606 ==
4747 13:59:11.197654 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 13:59:11.200875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 13:59:11.200968 ==
4750 13:59:11.201048 DQS Delay:
4751 13:59:11.204424 DQS0 = 0, DQS1 = 0
4752 13:59:11.204514 DQM Delay:
4753 13:59:11.207918 DQM0 = 35, DQM1 = 29
4754 13:59:11.208006 DQ Delay:
4755 13:59:11.211134 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4756 13:59:11.214204 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4757 13:59:11.217654 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4758 13:59:11.221174 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4759 13:59:11.221287
4760 13:59:11.221379
4761 13:59:11.221475 ==
4762 13:59:11.224867 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 13:59:11.227655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 13:59:11.227742 ==
4765 13:59:11.231329
4766 13:59:11.231466
4767 13:59:11.231531 TX Vref Scan disable
4768 13:59:11.234694 == TX Byte 0 ==
4769 13:59:11.237483 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4770 13:59:11.241171 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4771 13:59:11.244119 == TX Byte 1 ==
4772 13:59:11.247953 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4773 13:59:11.251267 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4774 13:59:11.254360 ==
4775 13:59:11.254465 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 13:59:11.260656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 13:59:11.260763 ==
4778 13:59:11.260863
4779 13:59:11.260959
4780 13:59:11.264185 TX Vref Scan disable
4781 13:59:11.264266 == TX Byte 0 ==
4782 13:59:11.270882 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4783 13:59:11.274402 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4784 13:59:11.274507 == TX Byte 1 ==
4785 13:59:11.280912 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4786 13:59:11.283788 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4787 13:59:11.283880
4788 13:59:11.283959 [DATLAT]
4789 13:59:11.287145 Freq=600, CH1 RK1
4790 13:59:11.287251
4791 13:59:11.287350 DATLAT Default: 0x9
4792 13:59:11.290516 0, 0xFFFF, sum = 0
4793 13:59:11.290597 1, 0xFFFF, sum = 0
4794 13:59:11.293799 2, 0xFFFF, sum = 0
4795 13:59:11.293879 3, 0xFFFF, sum = 0
4796 13:59:11.297096 4, 0xFFFF, sum = 0
4797 13:59:11.300471 5, 0xFFFF, sum = 0
4798 13:59:11.300549 6, 0xFFFF, sum = 0
4799 13:59:11.304068 7, 0xFFFF, sum = 0
4800 13:59:11.304143 8, 0x0, sum = 1
4801 13:59:11.304217 9, 0x0, sum = 2
4802 13:59:11.307143 10, 0x0, sum = 3
4803 13:59:11.307242 11, 0x0, sum = 4
4804 13:59:11.310499 best_step = 9
4805 13:59:11.310575
4806 13:59:11.310637 ==
4807 13:59:11.313994 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 13:59:11.317011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 13:59:11.317085 ==
4810 13:59:11.320263 RX Vref Scan: 0
4811 13:59:11.320362
4812 13:59:11.320460 RX Vref 0 -> 0, step: 1
4813 13:59:11.320549
4814 13:59:11.323731 RX Delay -195 -> 252, step: 8
4815 13:59:11.331065 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4816 13:59:11.334513 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4817 13:59:11.337564 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4818 13:59:11.341014 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4819 13:59:11.347531 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4820 13:59:11.351675 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4821 13:59:11.354507 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4822 13:59:11.357419 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4823 13:59:11.364041 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4824 13:59:11.367713 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4825 13:59:11.370863 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4826 13:59:11.374326 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4827 13:59:11.377360 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4828 13:59:11.384170 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4829 13:59:11.387235 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4830 13:59:11.390325 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4831 13:59:11.390433 ==
4832 13:59:11.393763 Dram Type= 6, Freq= 0, CH_1, rank 1
4833 13:59:11.400723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4834 13:59:11.400803 ==
4835 13:59:11.400887 DQS Delay:
4836 13:59:11.400956 DQS0 = 0, DQS1 = 0
4837 13:59:11.403879 DQM Delay:
4838 13:59:11.403964 DQM0 = 35, DQM1 = 29
4839 13:59:11.407037 DQ Delay:
4840 13:59:11.410619 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4841 13:59:11.413658 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4842 13:59:11.416932 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =20
4843 13:59:11.420314 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4844 13:59:11.420414
4845 13:59:11.420504
4846 13:59:11.427206 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4847 13:59:11.430813 CH1 RK1: MR19=808, MR18=3D5E
4848 13:59:11.437274 CH1_RK1: MR19=0x808, MR18=0x3D5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4849 13:59:11.440125 [RxdqsGatingPostProcess] freq 600
4850 13:59:11.444172 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4851 13:59:11.446730 Pre-setting of DQS Precalculation
4852 13:59:11.453267 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4853 13:59:11.460235 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4854 13:59:11.467061 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4855 13:59:11.467168
4856 13:59:11.467260
4857 13:59:11.469977 [Calibration Summary] 1200 Mbps
4858 13:59:11.470077 CH 0, Rank 0
4859 13:59:11.473625 SW Impedance : PASS
4860 13:59:11.476919 DUTY Scan : NO K
4861 13:59:11.477021 ZQ Calibration : PASS
4862 13:59:11.480030 Jitter Meter : NO K
4863 13:59:11.483211 CBT Training : PASS
4864 13:59:11.483310 Write leveling : PASS
4865 13:59:11.486547 RX DQS gating : PASS
4866 13:59:11.490008 RX DQ/DQS(RDDQC) : PASS
4867 13:59:11.490090 TX DQ/DQS : PASS
4868 13:59:11.493328 RX DATLAT : PASS
4869 13:59:11.493408 RX DQ/DQS(Engine): PASS
4870 13:59:11.496955 TX OE : NO K
4871 13:59:11.497036 All Pass.
4872 13:59:11.497100
4873 13:59:11.499974 CH 0, Rank 1
4874 13:59:11.500058 SW Impedance : PASS
4875 13:59:11.503237 DUTY Scan : NO K
4876 13:59:11.506846 ZQ Calibration : PASS
4877 13:59:11.506952 Jitter Meter : NO K
4878 13:59:11.509895 CBT Training : PASS
4879 13:59:11.513319 Write leveling : PASS
4880 13:59:11.513406 RX DQS gating : PASS
4881 13:59:11.516431 RX DQ/DQS(RDDQC) : PASS
4882 13:59:11.520161 TX DQ/DQS : PASS
4883 13:59:11.520252 RX DATLAT : PASS
4884 13:59:11.523081 RX DQ/DQS(Engine): PASS
4885 13:59:11.526460 TX OE : NO K
4886 13:59:11.526561 All Pass.
4887 13:59:11.526662
4888 13:59:11.526753 CH 1, Rank 0
4889 13:59:11.529993 SW Impedance : PASS
4890 13:59:11.533174 DUTY Scan : NO K
4891 13:59:11.533275 ZQ Calibration : PASS
4892 13:59:11.536819 Jitter Meter : NO K
4893 13:59:11.540029 CBT Training : PASS
4894 13:59:11.540106 Write leveling : PASS
4895 13:59:11.543419 RX DQS gating : PASS
4896 13:59:11.543511 RX DQ/DQS(RDDQC) : PASS
4897 13:59:11.546889 TX DQ/DQS : PASS
4898 13:59:11.549880 RX DATLAT : PASS
4899 13:59:11.549991 RX DQ/DQS(Engine): PASS
4900 13:59:11.552975 TX OE : NO K
4901 13:59:11.553075 All Pass.
4902 13:59:11.553167
4903 13:59:11.556433 CH 1, Rank 1
4904 13:59:11.556541 SW Impedance : PASS
4905 13:59:11.560079 DUTY Scan : NO K
4906 13:59:11.562993 ZQ Calibration : PASS
4907 13:59:11.563096 Jitter Meter : NO K
4908 13:59:11.566222 CBT Training : PASS
4909 13:59:11.569666 Write leveling : PASS
4910 13:59:11.569768 RX DQS gating : PASS
4911 13:59:11.572799 RX DQ/DQS(RDDQC) : PASS
4912 13:59:11.576674 TX DQ/DQS : PASS
4913 13:59:11.576777 RX DATLAT : PASS
4914 13:59:11.580077 RX DQ/DQS(Engine): PASS
4915 13:59:11.583682 TX OE : NO K
4916 13:59:11.583785 All Pass.
4917 13:59:11.583885
4918 13:59:11.583974 DramC Write-DBI off
4919 13:59:11.586045 PER_BANK_REFRESH: Hybrid Mode
4920 13:59:11.589772 TX_TRACKING: ON
4921 13:59:11.596212 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4922 13:59:11.599532 [FAST_K] Save calibration result to emmc
4923 13:59:11.606085 dramc_set_vcore_voltage set vcore to 662500
4924 13:59:11.606192 Read voltage for 933, 3
4925 13:59:11.609858 Vio18 = 0
4926 13:59:11.609934 Vcore = 662500
4927 13:59:11.610014 Vdram = 0
4928 13:59:11.612668 Vddq = 0
4929 13:59:11.612774 Vmddr = 0
4930 13:59:11.616518 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4931 13:59:11.622899 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4932 13:59:11.625981 MEM_TYPE=3, freq_sel=17
4933 13:59:11.629235 sv_algorithm_assistance_LP4_1600
4934 13:59:11.632790 ============ PULL DRAM RESETB DOWN ============
4935 13:59:11.636039 ========== PULL DRAM RESETB DOWN end =========
4936 13:59:11.639751 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4937 13:59:11.642594 ===================================
4938 13:59:11.646112 LPDDR4 DRAM CONFIGURATION
4939 13:59:11.649242 ===================================
4940 13:59:11.652460 EX_ROW_EN[0] = 0x0
4941 13:59:11.652558 EX_ROW_EN[1] = 0x0
4942 13:59:11.655967 LP4Y_EN = 0x0
4943 13:59:11.656045 WORK_FSP = 0x0
4944 13:59:11.659656 WL = 0x3
4945 13:59:11.659725 RL = 0x3
4946 13:59:11.662706 BL = 0x2
4947 13:59:11.662805 RPST = 0x0
4948 13:59:11.666167 RD_PRE = 0x0
4949 13:59:11.666265 WR_PRE = 0x1
4950 13:59:11.669686 WR_PST = 0x0
4951 13:59:11.672576 DBI_WR = 0x0
4952 13:59:11.672673 DBI_RD = 0x0
4953 13:59:11.675755 OTF = 0x1
4954 13:59:11.679285 ===================================
4955 13:59:11.682454 ===================================
4956 13:59:11.682553 ANA top config
4957 13:59:11.686050 ===================================
4958 13:59:11.689164 DLL_ASYNC_EN = 0
4959 13:59:11.689264 ALL_SLAVE_EN = 1
4960 13:59:11.692332 NEW_RANK_MODE = 1
4961 13:59:11.695769 DLL_IDLE_MODE = 1
4962 13:59:11.699161 LP45_APHY_COMB_EN = 1
4963 13:59:11.702309 TX_ODT_DIS = 1
4964 13:59:11.702415 NEW_8X_MODE = 1
4965 13:59:11.706161 ===================================
4966 13:59:11.709109 ===================================
4967 13:59:11.712450 data_rate = 1866
4968 13:59:11.715574 CKR = 1
4969 13:59:11.718957 DQ_P2S_RATIO = 8
4970 13:59:11.722447 ===================================
4971 13:59:11.725670 CA_P2S_RATIO = 8
4972 13:59:11.729553 DQ_CA_OPEN = 0
4973 13:59:11.729657 DQ_SEMI_OPEN = 0
4974 13:59:11.732142 CA_SEMI_OPEN = 0
4975 13:59:11.735293 CA_FULL_RATE = 0
4976 13:59:11.738625 DQ_CKDIV4_EN = 1
4977 13:59:11.741884 CA_CKDIV4_EN = 1
4978 13:59:11.745623 CA_PREDIV_EN = 0
4979 13:59:11.745730 PH8_DLY = 0
4980 13:59:11.748783 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4981 13:59:11.752136 DQ_AAMCK_DIV = 4
4982 13:59:11.755327 CA_AAMCK_DIV = 4
4983 13:59:11.758839 CA_ADMCK_DIV = 4
4984 13:59:11.762014 DQ_TRACK_CA_EN = 0
4985 13:59:11.762117 CA_PICK = 933
4986 13:59:11.765621 CA_MCKIO = 933
4987 13:59:11.768918 MCKIO_SEMI = 0
4988 13:59:11.772379 PLL_FREQ = 3732
4989 13:59:11.775208 DQ_UI_PI_RATIO = 32
4990 13:59:11.778635 CA_UI_PI_RATIO = 0
4991 13:59:11.782203 ===================================
4992 13:59:11.785644 ===================================
4993 13:59:11.785753 memory_type:LPDDR4
4994 13:59:11.789066 GP_NUM : 10
4995 13:59:11.791804 SRAM_EN : 1
4996 13:59:11.791879 MD32_EN : 0
4997 13:59:11.795582 ===================================
4998 13:59:11.798778 [ANA_INIT] >>>>>>>>>>>>>>
4999 13:59:11.802315 <<<<<< [CONFIGURE PHASE]: ANA_TX
5000 13:59:11.805554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5001 13:59:11.808634 ===================================
5002 13:59:11.811894 data_rate = 1866,PCW = 0X8f00
5003 13:59:11.815303 ===================================
5004 13:59:11.818229 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5005 13:59:11.821932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5006 13:59:11.828742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5007 13:59:11.831706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5008 13:59:11.834947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5009 13:59:11.841909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5010 13:59:11.842012 [ANA_INIT] flow start
5011 13:59:11.845448 [ANA_INIT] PLL >>>>>>>>
5012 13:59:11.845547 [ANA_INIT] PLL <<<<<<<<
5013 13:59:11.848537 [ANA_INIT] MIDPI >>>>>>>>
5014 13:59:11.851818 [ANA_INIT] MIDPI <<<<<<<<
5015 13:59:11.854952 [ANA_INIT] DLL >>>>>>>>
5016 13:59:11.855054 [ANA_INIT] flow end
5017 13:59:11.858221 ============ LP4 DIFF to SE enter ============
5018 13:59:11.865094 ============ LP4 DIFF to SE exit ============
5019 13:59:11.865200 [ANA_INIT] <<<<<<<<<<<<<
5020 13:59:11.868193 [Flow] Enable top DCM control >>>>>
5021 13:59:11.871688 [Flow] Enable top DCM control <<<<<
5022 13:59:11.874814 Enable DLL master slave shuffle
5023 13:59:11.881717 ==============================================================
5024 13:59:11.881820 Gating Mode config
5025 13:59:11.888206 ==============================================================
5026 13:59:11.891735 Config description:
5027 13:59:11.901927 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5028 13:59:11.907990 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5029 13:59:11.911486 SELPH_MODE 0: By rank 1: By Phase
5030 13:59:11.918263 ==============================================================
5031 13:59:11.921168 GAT_TRACK_EN = 1
5032 13:59:11.924659 RX_GATING_MODE = 2
5033 13:59:11.924762 RX_GATING_TRACK_MODE = 2
5034 13:59:11.927638 SELPH_MODE = 1
5035 13:59:11.931213 PICG_EARLY_EN = 1
5036 13:59:11.934722 VALID_LAT_VALUE = 1
5037 13:59:11.941441 ==============================================================
5038 13:59:11.944264 Enter into Gating configuration >>>>
5039 13:59:11.947639 Exit from Gating configuration <<<<
5040 13:59:11.950905 Enter into DVFS_PRE_config >>>>>
5041 13:59:11.960901 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5042 13:59:11.964553 Exit from DVFS_PRE_config <<<<<
5043 13:59:11.967454 Enter into PICG configuration >>>>
5044 13:59:11.970582 Exit from PICG configuration <<<<
5045 13:59:11.974539 [RX_INPUT] configuration >>>>>
5046 13:59:11.977383 [RX_INPUT] configuration <<<<<
5047 13:59:11.980831 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5048 13:59:11.987473 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5049 13:59:11.994301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5050 13:59:12.000575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5051 13:59:12.004188 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5052 13:59:12.010656 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5053 13:59:12.013855 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5054 13:59:12.020815 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5055 13:59:12.023750 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5056 13:59:12.027117 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5057 13:59:12.030338 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5058 13:59:12.036881 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5059 13:59:12.040506 ===================================
5060 13:59:12.043695 LPDDR4 DRAM CONFIGURATION
5061 13:59:12.047682 ===================================
5062 13:59:12.047773 EX_ROW_EN[0] = 0x0
5063 13:59:12.050478 EX_ROW_EN[1] = 0x0
5064 13:59:12.050556 LP4Y_EN = 0x0
5065 13:59:12.053681 WORK_FSP = 0x0
5066 13:59:12.053776 WL = 0x3
5067 13:59:12.057177 RL = 0x3
5068 13:59:12.057273 BL = 0x2
5069 13:59:12.060166 RPST = 0x0
5070 13:59:12.060240 RD_PRE = 0x0
5071 13:59:12.063705 WR_PRE = 0x1
5072 13:59:12.063803 WR_PST = 0x0
5073 13:59:12.066855 DBI_WR = 0x0
5074 13:59:12.066951 DBI_RD = 0x0
5075 13:59:12.070156 OTF = 0x1
5076 13:59:12.074033 ===================================
5077 13:59:12.077132 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5078 13:59:12.080117 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5079 13:59:12.087058 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5080 13:59:12.090274 ===================================
5081 13:59:12.090376 LPDDR4 DRAM CONFIGURATION
5082 13:59:12.093710 ===================================
5083 13:59:12.097330 EX_ROW_EN[0] = 0x10
5084 13:59:12.100191 EX_ROW_EN[1] = 0x0
5085 13:59:12.100291 LP4Y_EN = 0x0
5086 13:59:12.103289 WORK_FSP = 0x0
5087 13:59:12.103441 WL = 0x3
5088 13:59:12.106806 RL = 0x3
5089 13:59:12.106915 BL = 0x2
5090 13:59:12.110145 RPST = 0x0
5091 13:59:12.110244 RD_PRE = 0x0
5092 13:59:12.113353 WR_PRE = 0x1
5093 13:59:12.113464 WR_PST = 0x0
5094 13:59:12.116931 DBI_WR = 0x0
5095 13:59:12.117031 DBI_RD = 0x0
5096 13:59:12.120422 OTF = 0x1
5097 13:59:12.123659 ===================================
5098 13:59:12.130020 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5099 13:59:12.133112 nWR fixed to 30
5100 13:59:12.136581 [ModeRegInit_LP4] CH0 RK0
5101 13:59:12.136659 [ModeRegInit_LP4] CH0 RK1
5102 13:59:12.140208 [ModeRegInit_LP4] CH1 RK0
5103 13:59:12.143255 [ModeRegInit_LP4] CH1 RK1
5104 13:59:12.143371 match AC timing 9
5105 13:59:12.149687 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5106 13:59:12.153135 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5107 13:59:12.156476 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5108 13:59:12.163280 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5109 13:59:12.166270 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5110 13:59:12.166348 ==
5111 13:59:12.169814 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 13:59:12.173642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 13:59:12.173717 ==
5114 13:59:12.179703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5115 13:59:12.186564 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5116 13:59:12.189573 [CA 0] Center 38 (8~69) winsize 62
5117 13:59:12.192805 [CA 1] Center 38 (8~69) winsize 62
5118 13:59:12.196255 [CA 2] Center 35 (5~65) winsize 61
5119 13:59:12.199324 [CA 3] Center 35 (5~65) winsize 61
5120 13:59:12.202731 [CA 4] Center 34 (3~65) winsize 63
5121 13:59:12.206676 [CA 5] Center 33 (3~64) winsize 62
5122 13:59:12.206778
5123 13:59:12.209770 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5124 13:59:12.209871
5125 13:59:12.212844 [CATrainingPosCal] consider 1 rank data
5126 13:59:12.216378 u2DelayCellTimex100 = 270/100 ps
5127 13:59:12.219659 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5128 13:59:12.222661 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5129 13:59:12.226192 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5130 13:59:12.229634 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5131 13:59:12.232911 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5132 13:59:12.236359 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5133 13:59:12.236431
5134 13:59:12.242910 CA PerBit enable=1, Macro0, CA PI delay=33
5135 13:59:12.242985
5136 13:59:12.246236 [CBTSetCACLKResult] CA Dly = 33
5137 13:59:12.246311 CS Dly: 6 (0~37)
5138 13:59:12.246373 ==
5139 13:59:12.249706 Dram Type= 6, Freq= 0, CH_0, rank 1
5140 13:59:12.252958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 13:59:12.253030 ==
5142 13:59:12.259346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5143 13:59:12.266246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5144 13:59:12.269724 [CA 0] Center 38 (8~69) winsize 62
5145 13:59:12.273131 [CA 1] Center 38 (8~69) winsize 62
5146 13:59:12.275974 [CA 2] Center 35 (5~66) winsize 62
5147 13:59:12.279240 [CA 3] Center 35 (5~66) winsize 62
5148 13:59:12.282942 [CA 4] Center 33 (3~64) winsize 62
5149 13:59:12.286545 [CA 5] Center 33 (3~64) winsize 62
5150 13:59:12.286624
5151 13:59:12.289527 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5152 13:59:12.289606
5153 13:59:12.292985 [CATrainingPosCal] consider 2 rank data
5154 13:59:12.296122 u2DelayCellTimex100 = 270/100 ps
5155 13:59:12.299525 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5156 13:59:12.302696 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5157 13:59:12.305893 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5158 13:59:12.309426 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5159 13:59:12.312531 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5160 13:59:12.319599 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5161 13:59:12.319681
5162 13:59:12.322381 CA PerBit enable=1, Macro0, CA PI delay=33
5163 13:59:12.322454
5164 13:59:12.325833 [CBTSetCACLKResult] CA Dly = 33
5165 13:59:12.325947 CS Dly: 7 (0~39)
5166 13:59:12.326009
5167 13:59:12.329705 ----->DramcWriteLeveling(PI) begin...
5168 13:59:12.329812 ==
5169 13:59:12.332639 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 13:59:12.335693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 13:59:12.339645 ==
5172 13:59:12.342564 Write leveling (Byte 0): 30 => 30
5173 13:59:12.342634 Write leveling (Byte 1): 30 => 30
5174 13:59:12.345851 DramcWriteLeveling(PI) end<-----
5175 13:59:12.345919
5176 13:59:12.345978 ==
5177 13:59:12.349016 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 13:59:12.355770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 13:59:12.355845 ==
5180 13:59:12.359105 [Gating] SW mode calibration
5181 13:59:12.366186 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5182 13:59:12.368818 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5183 13:59:12.375533 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5184 13:59:12.378853 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5185 13:59:12.382378 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 13:59:12.389066 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 13:59:12.391946 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 13:59:12.395408 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 13:59:12.402239 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 13:59:12.405392 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
5191 13:59:12.408716 0 15 0 | B1->B0 | 3131 2929 | 1 0 | (0 0) (1 0)
5192 13:59:12.415218 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5193 13:59:12.418600 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 13:59:12.421990 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 13:59:12.428820 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 13:59:12.431972 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 13:59:12.435328 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 13:59:12.441926 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5199 13:59:12.445503 1 0 0 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
5200 13:59:12.448669 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5201 13:59:12.452235 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 13:59:12.458823 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 13:59:12.461764 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 13:59:12.464916 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 13:59:12.471612 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 13:59:12.475587 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 13:59:12.478172 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5208 13:59:12.485017 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5209 13:59:12.488411 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 13:59:12.491354 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 13:59:12.498618 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 13:59:12.501545 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 13:59:12.505311 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 13:59:12.511806 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 13:59:12.515021 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 13:59:12.518247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 13:59:12.525000 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 13:59:12.528198 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 13:59:12.531896 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 13:59:12.537896 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 13:59:12.541856 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 13:59:12.544958 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5223 13:59:12.551107 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5224 13:59:12.554487 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 13:59:12.557865 Total UI for P1: 0, mck2ui 16
5226 13:59:12.561328 best dqsien dly found for B0: ( 1, 2, 30)
5227 13:59:12.565051 Total UI for P1: 0, mck2ui 16
5228 13:59:12.568428 best dqsien dly found for B1: ( 1, 3, 2)
5229 13:59:12.571476 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5230 13:59:12.574368 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5231 13:59:12.574446
5232 13:59:12.578040 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5233 13:59:12.581457 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5234 13:59:12.584421 [Gating] SW calibration Done
5235 13:59:12.584493 ==
5236 13:59:12.587856 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 13:59:12.591331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 13:59:12.591468 ==
5239 13:59:12.594406 RX Vref Scan: 0
5240 13:59:12.594477
5241 13:59:12.597507 RX Vref 0 -> 0, step: 1
5242 13:59:12.597585
5243 13:59:12.597655 RX Delay -80 -> 252, step: 8
5244 13:59:12.604616 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5245 13:59:12.607651 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5246 13:59:12.611527 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5247 13:59:12.614143 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5248 13:59:12.617599 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5249 13:59:12.624077 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5250 13:59:12.627543 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5251 13:59:12.630615 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5252 13:59:12.633784 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5253 13:59:12.637424 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5254 13:59:12.644171 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5255 13:59:12.647419 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5256 13:59:12.650502 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5257 13:59:12.653885 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5258 13:59:12.657407 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5259 13:59:12.664296 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5260 13:59:12.664379 ==
5261 13:59:12.667352 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 13:59:12.670779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 13:59:12.670862 ==
5264 13:59:12.670926 DQS Delay:
5265 13:59:12.674014 DQS0 = 0, DQS1 = 0
5266 13:59:12.674095 DQM Delay:
5267 13:59:12.677065 DQM0 = 94, DQM1 = 83
5268 13:59:12.677146 DQ Delay:
5269 13:59:12.680427 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5270 13:59:12.683813 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =111
5271 13:59:12.686990 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5272 13:59:12.690402 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5273 13:59:12.690484
5274 13:59:12.690550
5275 13:59:12.690627 ==
5276 13:59:12.693634 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 13:59:12.697099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 13:59:12.697181 ==
5279 13:59:12.700250
5280 13:59:12.700330
5281 13:59:12.700395 TX Vref Scan disable
5282 13:59:12.703570 == TX Byte 0 ==
5283 13:59:12.706929 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5284 13:59:12.710563 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5285 13:59:12.713364 == TX Byte 1 ==
5286 13:59:12.716591 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5287 13:59:12.720223 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5288 13:59:12.720305 ==
5289 13:59:12.723773 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 13:59:12.729914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 13:59:12.729996 ==
5292 13:59:12.730060
5293 13:59:12.730120
5294 13:59:12.733483 TX Vref Scan disable
5295 13:59:12.733565 == TX Byte 0 ==
5296 13:59:12.740218 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5297 13:59:12.743559 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5298 13:59:12.743641 == TX Byte 1 ==
5299 13:59:12.749799 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5300 13:59:12.753618 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5301 13:59:12.753700
5302 13:59:12.753764 [DATLAT]
5303 13:59:12.756757 Freq=933, CH0 RK0
5304 13:59:12.756838
5305 13:59:12.756902 DATLAT Default: 0xd
5306 13:59:12.759621 0, 0xFFFF, sum = 0
5307 13:59:12.759703 1, 0xFFFF, sum = 0
5308 13:59:12.763537 2, 0xFFFF, sum = 0
5309 13:59:12.763620 3, 0xFFFF, sum = 0
5310 13:59:12.766553 4, 0xFFFF, sum = 0
5311 13:59:12.766653 5, 0xFFFF, sum = 0
5312 13:59:12.770113 6, 0xFFFF, sum = 0
5313 13:59:12.770195 7, 0xFFFF, sum = 0
5314 13:59:12.773398 8, 0xFFFF, sum = 0
5315 13:59:12.773481 9, 0xFFFF, sum = 0
5316 13:59:12.776462 10, 0x0, sum = 1
5317 13:59:12.776549 11, 0x0, sum = 2
5318 13:59:12.779704 12, 0x0, sum = 3
5319 13:59:12.779786 13, 0x0, sum = 4
5320 13:59:12.783298 best_step = 11
5321 13:59:12.783441
5322 13:59:12.783507 ==
5323 13:59:12.786772 Dram Type= 6, Freq= 0, CH_0, rank 0
5324 13:59:12.790002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 13:59:12.790124 ==
5326 13:59:12.792956 RX Vref Scan: 1
5327 13:59:12.793038
5328 13:59:12.793102 RX Vref 0 -> 0, step: 1
5329 13:59:12.793162
5330 13:59:12.796334 RX Delay -69 -> 252, step: 4
5331 13:59:12.796415
5332 13:59:12.799671 Set Vref, RX VrefLevel [Byte0]: 60
5333 13:59:12.803269 [Byte1]: 52
5334 13:59:12.807282
5335 13:59:12.807411 Final RX Vref Byte 0 = 60 to rank0
5336 13:59:12.810497 Final RX Vref Byte 1 = 52 to rank0
5337 13:59:12.813542 Final RX Vref Byte 0 = 60 to rank1
5338 13:59:12.816705 Final RX Vref Byte 1 = 52 to rank1==
5339 13:59:12.820293 Dram Type= 6, Freq= 0, CH_0, rank 0
5340 13:59:12.826758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 13:59:12.826842 ==
5342 13:59:12.826908 DQS Delay:
5343 13:59:12.830073 DQS0 = 0, DQS1 = 0
5344 13:59:12.830155 DQM Delay:
5345 13:59:12.830219 DQM0 = 95, DQM1 = 83
5346 13:59:12.833351 DQ Delay:
5347 13:59:12.836605 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5348 13:59:12.840145 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5349 13:59:12.843172 DQ8 =76, DQ9 =70, DQ10 =82, DQ11 =78
5350 13:59:12.846649 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5351 13:59:12.846730
5352 13:59:12.846794
5353 13:59:12.853305 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5354 13:59:12.856471 CH0 RK0: MR19=505, MR18=1717
5355 13:59:12.863180 CH0_RK0: MR19=0x505, MR18=0x1717, DQSOSC=414, MR23=63, INC=63, DEC=42
5356 13:59:12.863262
5357 13:59:12.866576 ----->DramcWriteLeveling(PI) begin...
5358 13:59:12.866658 ==
5359 13:59:12.869673 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 13:59:12.873428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 13:59:12.873513 ==
5362 13:59:12.876508 Write leveling (Byte 0): 31 => 31
5363 13:59:12.879615 Write leveling (Byte 1): 31 => 31
5364 13:59:12.883510 DramcWriteLeveling(PI) end<-----
5365 13:59:12.883606
5366 13:59:12.883670 ==
5367 13:59:12.886241 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 13:59:12.890137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 13:59:12.890218 ==
5370 13:59:12.892892 [Gating] SW mode calibration
5371 13:59:12.899698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5372 13:59:12.906088 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5373 13:59:12.909519 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5374 13:59:12.916571 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 13:59:12.919825 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 13:59:12.923482 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 13:59:12.929610 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 13:59:12.932895 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 13:59:12.936412 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 13:59:12.943197 0 14 28 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 0)
5381 13:59:12.946394 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
5382 13:59:12.949791 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 13:59:12.956569 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 13:59:12.959781 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 13:59:12.962603 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 13:59:12.966000 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 13:59:12.972705 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 13:59:12.976133 0 15 28 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)
5389 13:59:12.979284 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5390 13:59:12.985854 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 13:59:12.989212 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 13:59:12.992807 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 13:59:12.999238 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 13:59:13.002692 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 13:59:13.005921 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5396 13:59:13.012651 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5397 13:59:13.016109 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5398 13:59:13.018729 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5399 13:59:13.025789 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 13:59:13.029030 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 13:59:13.032112 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 13:59:13.038612 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 13:59:13.042325 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 13:59:13.045553 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 13:59:13.052014 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 13:59:13.055692 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 13:59:13.058861 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 13:59:13.065746 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 13:59:13.068608 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 13:59:13.071906 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 13:59:13.078517 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 13:59:13.081834 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5413 13:59:13.085098 Total UI for P1: 0, mck2ui 16
5414 13:59:13.088564 best dqsien dly found for B0: ( 1, 2, 26)
5415 13:59:13.091622 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5416 13:59:13.098444 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5417 13:59:13.101964 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 13:59:13.105136 Total UI for P1: 0, mck2ui 16
5419 13:59:13.108547 best dqsien dly found for B1: ( 1, 3, 0)
5420 13:59:13.111804 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5421 13:59:13.115213 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5422 13:59:13.115288
5423 13:59:13.118004 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5424 13:59:13.121444 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5425 13:59:13.124639 [Gating] SW calibration Done
5426 13:59:13.124713 ==
5427 13:59:13.128003 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 13:59:13.131620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 13:59:13.134755 ==
5430 13:59:13.134833 RX Vref Scan: 0
5431 13:59:13.134895
5432 13:59:13.138467 RX Vref 0 -> 0, step: 1
5433 13:59:13.138544
5434 13:59:13.141368 RX Delay -80 -> 252, step: 8
5435 13:59:13.144820 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5436 13:59:13.147931 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5437 13:59:13.151853 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5438 13:59:13.154668 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5439 13:59:13.158159 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5440 13:59:13.165034 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5441 13:59:13.168107 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5442 13:59:13.171493 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5443 13:59:13.174481 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5444 13:59:13.177868 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5445 13:59:13.184697 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5446 13:59:13.187953 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5447 13:59:13.191283 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5448 13:59:13.194579 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5449 13:59:13.198248 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5450 13:59:13.204716 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5451 13:59:13.204815 ==
5452 13:59:13.207497 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 13:59:13.210884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 13:59:13.210963 ==
5455 13:59:13.211041 DQS Delay:
5456 13:59:13.214379 DQS0 = 0, DQS1 = 0
5457 13:59:13.214453 DQM Delay:
5458 13:59:13.217705 DQM0 = 91, DQM1 = 83
5459 13:59:13.217783 DQ Delay:
5460 13:59:13.221018 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5461 13:59:13.224260 DQ4 =91, DQ5 =75, DQ6 =99, DQ7 =103
5462 13:59:13.227831 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5463 13:59:13.231328 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5464 13:59:13.231424
5465 13:59:13.231517
5466 13:59:13.231607 ==
5467 13:59:13.234618 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 13:59:13.237557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 13:59:13.237629 ==
5470 13:59:13.237689
5471 13:59:13.241442
5472 13:59:13.241511 TX Vref Scan disable
5473 13:59:13.244361 == TX Byte 0 ==
5474 13:59:13.247605 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5475 13:59:13.251138 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5476 13:59:13.254741 == TX Byte 1 ==
5477 13:59:13.257813 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5478 13:59:13.261299 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5479 13:59:13.261398 ==
5480 13:59:13.264252 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 13:59:13.270687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 13:59:13.270787 ==
5483 13:59:13.270884
5484 13:59:13.270960
5485 13:59:13.271051 TX Vref Scan disable
5486 13:59:13.274845 == TX Byte 0 ==
5487 13:59:13.278054 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5488 13:59:13.281398 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5489 13:59:13.284647 == TX Byte 1 ==
5490 13:59:13.288363 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5491 13:59:13.294998 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5492 13:59:13.295098
5493 13:59:13.295194 [DATLAT]
5494 13:59:13.295255 Freq=933, CH0 RK1
5495 13:59:13.295314
5496 13:59:13.297947 DATLAT Default: 0xb
5497 13:59:13.298045 0, 0xFFFF, sum = 0
5498 13:59:13.301307 1, 0xFFFF, sum = 0
5499 13:59:13.301423 2, 0xFFFF, sum = 0
5500 13:59:13.304781 3, 0xFFFF, sum = 0
5501 13:59:13.307957 4, 0xFFFF, sum = 0
5502 13:59:13.308071 5, 0xFFFF, sum = 0
5503 13:59:13.311623 6, 0xFFFF, sum = 0
5504 13:59:13.311708 7, 0xFFFF, sum = 0
5505 13:59:13.314458 8, 0xFFFF, sum = 0
5506 13:59:13.314542 9, 0xFFFF, sum = 0
5507 13:59:13.318187 10, 0x0, sum = 1
5508 13:59:13.318288 11, 0x0, sum = 2
5509 13:59:13.321324 12, 0x0, sum = 3
5510 13:59:13.321406 13, 0x0, sum = 4
5511 13:59:13.321489 best_step = 11
5512 13:59:13.324387
5513 13:59:13.324468 ==
5514 13:59:13.327912 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 13:59:13.331289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 13:59:13.331420 ==
5517 13:59:13.331538 RX Vref Scan: 0
5518 13:59:13.331599
5519 13:59:13.334360 RX Vref 0 -> 0, step: 1
5520 13:59:13.334441
5521 13:59:13.338155 RX Delay -77 -> 252, step: 4
5522 13:59:13.341191 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5523 13:59:13.347917 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5524 13:59:13.351563 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5525 13:59:13.354373 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5526 13:59:13.358000 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5527 13:59:13.360901 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5528 13:59:13.367899 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5529 13:59:13.370941 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5530 13:59:13.374280 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5531 13:59:13.377508 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5532 13:59:13.380659 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5533 13:59:13.387152 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5534 13:59:13.390645 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5535 13:59:13.393945 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5536 13:59:13.397159 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5537 13:59:13.400365 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5538 13:59:13.400449 ==
5539 13:59:13.403993 Dram Type= 6, Freq= 0, CH_0, rank 1
5540 13:59:13.410328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 13:59:13.410415 ==
5542 13:59:13.410482 DQS Delay:
5543 13:59:13.413581 DQS0 = 0, DQS1 = 0
5544 13:59:13.413666 DQM Delay:
5545 13:59:13.416987 DQM0 = 92, DQM1 = 85
5546 13:59:13.417069 DQ Delay:
5547 13:59:13.420396 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5548 13:59:13.424124 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =102
5549 13:59:13.426778 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =78
5550 13:59:13.430496 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5551 13:59:13.430578
5552 13:59:13.430643
5553 13:59:13.436820 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5554 13:59:13.440455 CH0 RK1: MR19=505, MR18=2F11
5555 13:59:13.446669 CH0_RK1: MR19=0x505, MR18=0x2F11, DQSOSC=407, MR23=63, INC=65, DEC=43
5556 13:59:13.450125 [RxdqsGatingPostProcess] freq 933
5557 13:59:13.456798 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5558 13:59:13.456881 best DQS0 dly(2T, 0.5T) = (0, 10)
5559 13:59:13.460035 best DQS1 dly(2T, 0.5T) = (0, 11)
5560 13:59:13.463566 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5561 13:59:13.466928 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5562 13:59:13.470130 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 13:59:13.473228 best DQS1 dly(2T, 0.5T) = (0, 11)
5564 13:59:13.476900 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 13:59:13.480297 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5566 13:59:13.483440 Pre-setting of DQS Precalculation
5567 13:59:13.486606 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5568 13:59:13.490269 ==
5569 13:59:13.493364 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 13:59:13.496667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 13:59:13.496742 ==
5572 13:59:13.503284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5573 13:59:13.506491 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5574 13:59:13.510512 [CA 0] Center 37 (7~67) winsize 61
5575 13:59:13.513726 [CA 1] Center 37 (7~67) winsize 61
5576 13:59:13.516983 [CA 2] Center 34 (5~64) winsize 60
5577 13:59:13.520502 [CA 3] Center 34 (4~64) winsize 61
5578 13:59:13.523816 [CA 4] Center 34 (5~64) winsize 60
5579 13:59:13.526892 [CA 5] Center 34 (4~64) winsize 61
5580 13:59:13.526965
5581 13:59:13.530607 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5582 13:59:13.530688
5583 13:59:13.534088 [CATrainingPosCal] consider 1 rank data
5584 13:59:13.537277 u2DelayCellTimex100 = 270/100 ps
5585 13:59:13.540297 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5586 13:59:13.546896 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5587 13:59:13.550707 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5588 13:59:13.554019 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5589 13:59:13.557453 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5590 13:59:13.560236 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5591 13:59:13.560359
5592 13:59:13.564188 CA PerBit enable=1, Macro0, CA PI delay=34
5593 13:59:13.564308
5594 13:59:13.566837 [CBTSetCACLKResult] CA Dly = 34
5595 13:59:13.566970 CS Dly: 6 (0~37)
5596 13:59:13.570339 ==
5597 13:59:13.573672 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 13:59:13.577216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 13:59:13.577396 ==
5600 13:59:13.580423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 13:59:13.587122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5602 13:59:13.590778 [CA 0] Center 37 (7~67) winsize 61
5603 13:59:13.594226 [CA 1] Center 37 (7~68) winsize 62
5604 13:59:13.597540 [CA 2] Center 34 (5~64) winsize 60
5605 13:59:13.600743 [CA 3] Center 34 (4~64) winsize 61
5606 13:59:13.604276 [CA 4] Center 34 (5~64) winsize 60
5607 13:59:13.607158 [CA 5] Center 33 (3~64) winsize 62
5608 13:59:13.607596
5609 13:59:13.610736 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5610 13:59:13.611168
5611 13:59:13.613951 [CATrainingPosCal] consider 2 rank data
5612 13:59:13.617171 u2DelayCellTimex100 = 270/100 ps
5613 13:59:13.620664 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5614 13:59:13.627649 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5615 13:59:13.630776 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5616 13:59:13.634123 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5617 13:59:13.637439 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5618 13:59:13.640522 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5619 13:59:13.640987
5620 13:59:13.644010 CA PerBit enable=1, Macro0, CA PI delay=34
5621 13:59:13.644472
5622 13:59:13.647720 [CBTSetCACLKResult] CA Dly = 34
5623 13:59:13.648186 CS Dly: 7 (0~39)
5624 13:59:13.648551
5625 13:59:13.650542 ----->DramcWriteLeveling(PI) begin...
5626 13:59:13.653866 ==
5627 13:59:13.657233 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 13:59:13.660670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 13:59:13.661181 ==
5630 13:59:13.663729 Write leveling (Byte 0): 27 => 27
5631 13:59:13.667512 Write leveling (Byte 1): 31 => 31
5632 13:59:13.670632 DramcWriteLeveling(PI) end<-----
5633 13:59:13.671208
5634 13:59:13.671811 ==
5635 13:59:13.674147 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 13:59:13.677038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 13:59:13.677495 ==
5638 13:59:13.680440 [Gating] SW mode calibration
5639 13:59:13.686743 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5640 13:59:13.693427 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5641 13:59:13.696694 0 14 0 | B1->B0 | 3232 3131 | 1 1 | (1 1) (1 1)
5642 13:59:13.700408 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 13:59:13.707379 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 13:59:13.710126 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 13:59:13.713555 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 13:59:13.720057 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 13:59:13.723175 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 13:59:13.727067 0 14 28 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
5649 13:59:13.733702 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5650 13:59:13.736501 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 13:59:13.739940 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 13:59:13.746420 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 13:59:13.749809 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 13:59:13.753181 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 13:59:13.760252 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 13:59:13.763751 0 15 28 | B1->B0 | 3030 2f2f | 0 1 | (0 0) (0 0)
5657 13:59:13.766227 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5658 13:59:13.773391 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 13:59:13.776657 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 13:59:13.779716 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 13:59:13.783103 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 13:59:13.789847 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 13:59:13.793165 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5664 13:59:13.796376 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5665 13:59:13.803131 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5666 13:59:13.806204 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 13:59:13.810232 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 13:59:13.816118 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 13:59:13.819655 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 13:59:13.823138 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 13:59:13.829457 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 13:59:13.832733 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 13:59:13.836054 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 13:59:13.843361 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 13:59:13.846813 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 13:59:13.849923 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 13:59:13.856155 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 13:59:13.859832 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 13:59:13.862742 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 13:59:13.869782 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5681 13:59:13.872393 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 13:59:13.875956 Total UI for P1: 0, mck2ui 16
5683 13:59:13.879449 best dqsien dly found for B0: ( 1, 2, 28)
5684 13:59:13.882622 Total UI for P1: 0, mck2ui 16
5685 13:59:13.886181 best dqsien dly found for B1: ( 1, 2, 28)
5686 13:59:13.889217 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5687 13:59:13.892496 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5688 13:59:13.892983
5689 13:59:13.895985 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5690 13:59:13.899493 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5691 13:59:13.903006 [Gating] SW calibration Done
5692 13:59:13.903462 ==
5693 13:59:13.905800 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 13:59:13.909129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 13:59:13.912536 ==
5696 13:59:13.912984 RX Vref Scan: 0
5697 13:59:13.913344
5698 13:59:13.915649 RX Vref 0 -> 0, step: 1
5699 13:59:13.916091
5700 13:59:13.919300 RX Delay -80 -> 252, step: 8
5701 13:59:13.922079 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5702 13:59:13.925511 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5703 13:59:13.928703 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5704 13:59:13.932250 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5705 13:59:13.935422 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5706 13:59:13.941689 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5707 13:59:13.945153 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5708 13:59:13.948878 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5709 13:59:13.951844 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5710 13:59:13.955158 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5711 13:59:13.961978 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5712 13:59:13.964896 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5713 13:59:13.968610 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5714 13:59:13.972144 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5715 13:59:13.975011 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5716 13:59:13.981884 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5717 13:59:13.982305 ==
5718 13:59:13.984793 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 13:59:13.988195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 13:59:13.988619 ==
5721 13:59:13.988949 DQS Delay:
5722 13:59:13.991854 DQS0 = 0, DQS1 = 0
5723 13:59:13.992274 DQM Delay:
5724 13:59:13.995137 DQM0 = 94, DQM1 = 86
5725 13:59:13.995595 DQ Delay:
5726 13:59:13.997998 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5727 13:59:14.001805 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5728 13:59:14.004910 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5729 13:59:14.007956 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5730 13:59:14.008529
5731 13:59:14.008883
5732 13:59:14.009197 ==
5733 13:59:14.011593 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 13:59:14.014539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 13:59:14.018037 ==
5736 13:59:14.018485
5737 13:59:14.018836
5738 13:59:14.019153 TX Vref Scan disable
5739 13:59:14.021485 == TX Byte 0 ==
5740 13:59:14.024836 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5741 13:59:14.027918 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5742 13:59:14.031372 == TX Byte 1 ==
5743 13:59:14.034556 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5744 13:59:14.037830 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5745 13:59:14.041335 ==
5746 13:59:14.045013 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 13:59:14.047684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 13:59:14.048130 ==
5749 13:59:14.048467
5750 13:59:14.048798
5751 13:59:14.050924 TX Vref Scan disable
5752 13:59:14.051370 == TX Byte 0 ==
5753 13:59:14.057430 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5754 13:59:14.061072 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5755 13:59:14.061512 == TX Byte 1 ==
5756 13:59:14.067818 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5757 13:59:14.070978 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5758 13:59:14.071498
5759 13:59:14.071848 [DATLAT]
5760 13:59:14.074126 Freq=933, CH1 RK0
5761 13:59:14.074621
5762 13:59:14.074977 DATLAT Default: 0xd
5763 13:59:14.077773 0, 0xFFFF, sum = 0
5764 13:59:14.078227 1, 0xFFFF, sum = 0
5765 13:59:14.080835 2, 0xFFFF, sum = 0
5766 13:59:14.081288 3, 0xFFFF, sum = 0
5767 13:59:14.083969 4, 0xFFFF, sum = 0
5768 13:59:14.087595 5, 0xFFFF, sum = 0
5769 13:59:14.088048 6, 0xFFFF, sum = 0
5770 13:59:14.091164 7, 0xFFFF, sum = 0
5771 13:59:14.091766 8, 0xFFFF, sum = 0
5772 13:59:14.094588 9, 0xFFFF, sum = 0
5773 13:59:14.095202 10, 0x0, sum = 1
5774 13:59:14.097289 11, 0x0, sum = 2
5775 13:59:14.097721 12, 0x0, sum = 3
5776 13:59:14.098081 13, 0x0, sum = 4
5777 13:59:14.100433 best_step = 11
5778 13:59:14.100878
5779 13:59:14.101213 ==
5780 13:59:14.104396 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 13:59:14.107343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 13:59:14.107869 ==
5783 13:59:14.110486 RX Vref Scan: 1
5784 13:59:14.110930
5785 13:59:14.113797 RX Vref 0 -> 0, step: 1
5786 13:59:14.114179
5787 13:59:14.114517 RX Delay -61 -> 252, step: 4
5788 13:59:14.114838
5789 13:59:14.117154 Set Vref, RX VrefLevel [Byte0]: 56
5790 13:59:14.120320 [Byte1]: 49
5791 13:59:14.124786
5792 13:59:14.125207 Final RX Vref Byte 0 = 56 to rank0
5793 13:59:14.128486 Final RX Vref Byte 1 = 49 to rank0
5794 13:59:14.131835 Final RX Vref Byte 0 = 56 to rank1
5795 13:59:14.135587 Final RX Vref Byte 1 = 49 to rank1==
5796 13:59:14.138066 Dram Type= 6, Freq= 0, CH_1, rank 0
5797 13:59:14.145006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 13:59:14.145462 ==
5799 13:59:14.145804 DQS Delay:
5800 13:59:14.148001 DQS0 = 0, DQS1 = 0
5801 13:59:14.148445 DQM Delay:
5802 13:59:14.148782 DQM0 = 96, DQM1 = 88
5803 13:59:14.151768 DQ Delay:
5804 13:59:14.155106 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =92
5805 13:59:14.158239 DQ4 =94, DQ5 =104, DQ6 =108, DQ7 =92
5806 13:59:14.161411 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =80
5807 13:59:14.164644 DQ12 =96, DQ13 =94, DQ14 =92, DQ15 =96
5808 13:59:14.165092
5809 13:59:14.165452
5810 13:59:14.171530 [DQSOSCAuto] RK0, (LSB)MR18= 0x60e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5811 13:59:14.174434 CH1 RK0: MR19=505, MR18=60E
5812 13:59:14.181380 CH1_RK0: MR19=0x505, MR18=0x60E, DQSOSC=417, MR23=63, INC=62, DEC=41
5813 13:59:14.181807
5814 13:59:14.185152 ----->DramcWriteLeveling(PI) begin...
5815 13:59:14.185684 ==
5816 13:59:14.187843 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 13:59:14.190904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 13:59:14.191329 ==
5819 13:59:14.194550 Write leveling (Byte 0): 28 => 28
5820 13:59:14.197739 Write leveling (Byte 1): 26 => 26
5821 13:59:14.201102 DramcWriteLeveling(PI) end<-----
5822 13:59:14.201584
5823 13:59:14.202103 ==
5824 13:59:14.204161 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 13:59:14.207457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 13:59:14.207889 ==
5827 13:59:14.210819 [Gating] SW mode calibration
5828 13:59:14.217844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5829 13:59:14.224207 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5830 13:59:14.227930 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 13:59:14.234461 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 13:59:14.237556 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 13:59:14.241182 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 13:59:14.247315 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 13:59:14.251221 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 13:59:14.254331 0 14 24 | B1->B0 | 3232 2e2e | 1 0 | (1 1) (1 0)
5837 13:59:14.260906 0 14 28 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
5838 13:59:14.264685 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5839 13:59:14.267715 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 13:59:14.270766 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 13:59:14.277683 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 13:59:14.280757 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 13:59:14.284133 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 13:59:14.290600 0 15 24 | B1->B0 | 2a2a 3535 | 0 1 | (0 0) (0 0)
5845 13:59:14.293660 0 15 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5846 13:59:14.297181 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 13:59:14.304228 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 13:59:14.306962 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 13:59:14.310639 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 13:59:14.317437 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 13:59:14.320453 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 13:59:14.323508 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5853 13:59:14.330519 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5854 13:59:14.333346 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 13:59:14.337056 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 13:59:14.343860 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 13:59:14.347140 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 13:59:14.350385 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 13:59:14.356764 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 13:59:14.360290 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 13:59:14.363186 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 13:59:14.370094 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 13:59:14.373586 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 13:59:14.376555 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 13:59:14.383546 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 13:59:14.386869 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 13:59:14.389895 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 13:59:14.396561 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5869 13:59:14.400444 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 13:59:14.403613 Total UI for P1: 0, mck2ui 16
5871 13:59:14.406884 best dqsien dly found for B0: ( 1, 2, 24)
5872 13:59:14.409485 Total UI for P1: 0, mck2ui 16
5873 13:59:14.413035 best dqsien dly found for B1: ( 1, 2, 26)
5874 13:59:14.416444 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5875 13:59:14.419776 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5876 13:59:14.420289
5877 13:59:14.423356 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5878 13:59:14.426333 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5879 13:59:14.429619 [Gating] SW calibration Done
5880 13:59:14.430221 ==
5881 13:59:14.433048 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 13:59:14.436436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 13:59:14.439495 ==
5884 13:59:14.440000 RX Vref Scan: 0
5885 13:59:14.440407
5886 13:59:14.442688 RX Vref 0 -> 0, step: 1
5887 13:59:14.443257
5888 13:59:14.446066 RX Delay -80 -> 252, step: 8
5889 13:59:14.449388 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5890 13:59:14.453295 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5891 13:59:14.456215 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5892 13:59:14.459329 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5893 13:59:14.463181 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5894 13:59:14.469449 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5895 13:59:14.472435 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5896 13:59:14.476138 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5897 13:59:14.479167 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5898 13:59:14.482383 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5899 13:59:14.488960 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5900 13:59:14.492506 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5901 13:59:14.495588 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5902 13:59:14.499240 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5903 13:59:14.502311 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5904 13:59:14.505808 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5905 13:59:14.508877 ==
5906 13:59:14.512428 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 13:59:14.515664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 13:59:14.516162 ==
5909 13:59:14.516597 DQS Delay:
5910 13:59:14.519035 DQS0 = 0, DQS1 = 0
5911 13:59:14.519592 DQM Delay:
5912 13:59:14.522179 DQM0 = 95, DQM1 = 88
5913 13:59:14.522696 DQ Delay:
5914 13:59:14.525421 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5915 13:59:14.528997 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5916 13:59:14.532342 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5917 13:59:14.535936 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5918 13:59:14.536430
5919 13:59:14.536798
5920 13:59:14.537171 ==
5921 13:59:14.538978 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 13:59:14.542163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 13:59:14.542675 ==
5924 13:59:14.543302
5925 13:59:14.543768
5926 13:59:14.545950 TX Vref Scan disable
5927 13:59:14.548928 == TX Byte 0 ==
5928 13:59:14.551933 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5929 13:59:14.555745 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5930 13:59:14.559201 == TX Byte 1 ==
5931 13:59:14.561848 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5932 13:59:14.565531 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5933 13:59:14.566030 ==
5934 13:59:14.568554 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 13:59:14.575759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 13:59:14.576256 ==
5937 13:59:14.576657
5938 13:59:14.577027
5939 13:59:14.577392 TX Vref Scan disable
5940 13:59:14.579548 == TX Byte 0 ==
5941 13:59:14.583067 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5942 13:59:14.589263 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5943 13:59:14.589754 == TX Byte 1 ==
5944 13:59:14.592569 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5945 13:59:14.599005 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5946 13:59:14.599540
5947 13:59:14.599910 [DATLAT]
5948 13:59:14.600230 Freq=933, CH1 RK1
5949 13:59:14.600564
5950 13:59:14.602184 DATLAT Default: 0xb
5951 13:59:14.605627 0, 0xFFFF, sum = 0
5952 13:59:14.606085 1, 0xFFFF, sum = 0
5953 13:59:14.609359 2, 0xFFFF, sum = 0
5954 13:59:14.609908 3, 0xFFFF, sum = 0
5955 13:59:14.612186 4, 0xFFFF, sum = 0
5956 13:59:14.612641 5, 0xFFFF, sum = 0
5957 13:59:14.615925 6, 0xFFFF, sum = 0
5958 13:59:14.616383 7, 0xFFFF, sum = 0
5959 13:59:14.618986 8, 0xFFFF, sum = 0
5960 13:59:14.619578 9, 0xFFFF, sum = 0
5961 13:59:14.622552 10, 0x0, sum = 1
5962 13:59:14.622977 11, 0x0, sum = 2
5963 13:59:14.626011 12, 0x0, sum = 3
5964 13:59:14.626466 13, 0x0, sum = 4
5965 13:59:14.626843 best_step = 11
5966 13:59:14.628743
5967 13:59:14.629187 ==
5968 13:59:14.632363 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 13:59:14.635287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 13:59:14.635846 ==
5971 13:59:14.636213 RX Vref Scan: 0
5972 13:59:14.636581
5973 13:59:14.638491 RX Vref 0 -> 0, step: 1
5974 13:59:14.638946
5975 13:59:14.642318 RX Delay -61 -> 252, step: 4
5976 13:59:14.648773 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5977 13:59:14.651613 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5978 13:59:14.655165 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5979 13:59:14.658638 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5980 13:59:14.661675 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5981 13:59:14.664976 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5982 13:59:14.671593 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5983 13:59:14.674972 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5984 13:59:14.678243 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5985 13:59:14.681797 iDelay=203, Bit 9, Center 78 (-17 ~ 174) 192
5986 13:59:14.684783 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5987 13:59:14.691442 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5988 13:59:14.694964 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5989 13:59:14.698539 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5990 13:59:14.701336 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5991 13:59:14.705184 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5992 13:59:14.705695 ==
5993 13:59:14.708262 Dram Type= 6, Freq= 0, CH_1, rank 1
5994 13:59:14.714652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5995 13:59:14.715103 ==
5996 13:59:14.715519 DQS Delay:
5997 13:59:14.717725 DQS0 = 0, DQS1 = 0
5998 13:59:14.718207 DQM Delay:
5999 13:59:14.721096 DQM0 = 92, DQM1 = 89
6000 13:59:14.721578 DQ Delay:
6001 13:59:14.724801 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =90
6002 13:59:14.728169 DQ4 =88, DQ5 =102, DQ6 =104, DQ7 =90
6003 13:59:14.731172 DQ8 =76, DQ9 =78, DQ10 =92, DQ11 =82
6004 13:59:14.734431 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =94
6005 13:59:14.734883
6006 13:59:14.735346
6007 13:59:14.740875 [DQSOSCAuto] RK1, (LSB)MR18= 0x1124, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
6008 13:59:14.744131 CH1 RK1: MR19=505, MR18=1124
6009 13:59:14.751312 CH1_RK1: MR19=0x505, MR18=0x1124, DQSOSC=410, MR23=63, INC=64, DEC=42
6010 13:59:14.754346 [RxdqsGatingPostProcess] freq 933
6011 13:59:14.761064 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6012 13:59:14.761555 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 13:59:14.764329 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 13:59:14.767866 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 13:59:14.770853 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 13:59:14.774234 best DQS0 dly(2T, 0.5T) = (0, 10)
6017 13:59:14.777412 best DQS1 dly(2T, 0.5T) = (0, 10)
6018 13:59:14.780834 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6019 13:59:14.784282 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6020 13:59:14.787572 Pre-setting of DQS Precalculation
6021 13:59:14.791029 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6022 13:59:14.800809 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6023 13:59:14.807777 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6024 13:59:14.808416
6025 13:59:14.808920
6026 13:59:14.811230 [Calibration Summary] 1866 Mbps
6027 13:59:14.811726 CH 0, Rank 0
6028 13:59:14.813909 SW Impedance : PASS
6029 13:59:14.814356 DUTY Scan : NO K
6030 13:59:14.817669 ZQ Calibration : PASS
6031 13:59:14.821182 Jitter Meter : NO K
6032 13:59:14.821639 CBT Training : PASS
6033 13:59:14.824637 Write leveling : PASS
6034 13:59:14.827330 RX DQS gating : PASS
6035 13:59:14.827826 RX DQ/DQS(RDDQC) : PASS
6036 13:59:14.830516 TX DQ/DQS : PASS
6037 13:59:14.834316 RX DATLAT : PASS
6038 13:59:14.834777 RX DQ/DQS(Engine): PASS
6039 13:59:14.836884 TX OE : NO K
6040 13:59:14.837454 All Pass.
6041 13:59:14.837894
6042 13:59:14.840844 CH 0, Rank 1
6043 13:59:14.841309 SW Impedance : PASS
6044 13:59:14.844134 DUTY Scan : NO K
6045 13:59:14.847086 ZQ Calibration : PASS
6046 13:59:14.847559 Jitter Meter : NO K
6047 13:59:14.850316 CBT Training : PASS
6048 13:59:14.853653 Write leveling : PASS
6049 13:59:14.854082 RX DQS gating : PASS
6050 13:59:14.857227 RX DQ/DQS(RDDQC) : PASS
6051 13:59:14.860213 TX DQ/DQS : PASS
6052 13:59:14.860644 RX DATLAT : PASS
6053 13:59:14.864107 RX DQ/DQS(Engine): PASS
6054 13:59:14.864537 TX OE : NO K
6055 13:59:14.867103 All Pass.
6056 13:59:14.867572
6057 13:59:14.868008 CH 1, Rank 0
6058 13:59:14.870212 SW Impedance : PASS
6059 13:59:14.870650 DUTY Scan : NO K
6060 13:59:14.873573 ZQ Calibration : PASS
6061 13:59:14.877312 Jitter Meter : NO K
6062 13:59:14.877740 CBT Training : PASS
6063 13:59:14.880315 Write leveling : PASS
6064 13:59:14.883446 RX DQS gating : PASS
6065 13:59:14.883877 RX DQ/DQS(RDDQC) : PASS
6066 13:59:14.886656 TX DQ/DQS : PASS
6067 13:59:14.890046 RX DATLAT : PASS
6068 13:59:14.890537 RX DQ/DQS(Engine): PASS
6069 13:59:14.893347 TX OE : NO K
6070 13:59:14.893779 All Pass.
6071 13:59:14.894217
6072 13:59:14.896924 CH 1, Rank 1
6073 13:59:14.897374 SW Impedance : PASS
6074 13:59:14.900227 DUTY Scan : NO K
6075 13:59:14.903340 ZQ Calibration : PASS
6076 13:59:14.903875 Jitter Meter : NO K
6077 13:59:14.906971 CBT Training : PASS
6078 13:59:14.910334 Write leveling : PASS
6079 13:59:14.910977 RX DQS gating : PASS
6080 13:59:14.913598 RX DQ/DQS(RDDQC) : PASS
6081 13:59:14.916918 TX DQ/DQS : PASS
6082 13:59:14.917370 RX DATLAT : PASS
6083 13:59:14.919978 RX DQ/DQS(Engine): PASS
6084 13:59:14.923484 TX OE : NO K
6085 13:59:14.923961 All Pass.
6086 13:59:14.924325
6087 13:59:14.924643 DramC Write-DBI off
6088 13:59:14.926822 PER_BANK_REFRESH: Hybrid Mode
6089 13:59:14.930112 TX_TRACKING: ON
6090 13:59:14.936522 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6091 13:59:14.940280 [FAST_K] Save calibration result to emmc
6092 13:59:14.946425 dramc_set_vcore_voltage set vcore to 650000
6093 13:59:14.946843 Read voltage for 400, 6
6094 13:59:14.949671 Vio18 = 0
6095 13:59:14.950089 Vcore = 650000
6096 13:59:14.950456 Vdram = 0
6097 13:59:14.953259 Vddq = 0
6098 13:59:14.953717 Vmddr = 0
6099 13:59:14.956619 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6100 13:59:14.962867 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6101 13:59:14.966309 MEM_TYPE=3, freq_sel=20
6102 13:59:14.969962 sv_algorithm_assistance_LP4_800
6103 13:59:14.972997 ============ PULL DRAM RESETB DOWN ============
6104 13:59:14.976252 ========== PULL DRAM RESETB DOWN end =========
6105 13:59:14.979522 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6106 13:59:14.982847 ===================================
6107 13:59:14.986092 LPDDR4 DRAM CONFIGURATION
6108 13:59:14.989640 ===================================
6109 13:59:14.992692 EX_ROW_EN[0] = 0x0
6110 13:59:14.993131 EX_ROW_EN[1] = 0x0
6111 13:59:14.995936 LP4Y_EN = 0x0
6112 13:59:14.996356 WORK_FSP = 0x0
6113 13:59:14.999241 WL = 0x2
6114 13:59:14.999732 RL = 0x2
6115 13:59:15.002798 BL = 0x2
6116 13:59:15.003224 RPST = 0x0
6117 13:59:15.005819 RD_PRE = 0x0
6118 13:59:15.006250 WR_PRE = 0x1
6119 13:59:15.009283 WR_PST = 0x0
6120 13:59:15.009714 DBI_WR = 0x0
6121 13:59:15.012606 DBI_RD = 0x0
6122 13:59:15.015931 OTF = 0x1
6123 13:59:15.019170 ===================================
6124 13:59:15.019666 ===================================
6125 13:59:15.022892 ANA top config
6126 13:59:15.026185 ===================================
6127 13:59:15.029795 DLL_ASYNC_EN = 0
6128 13:59:15.030226 ALL_SLAVE_EN = 1
6129 13:59:15.032588 NEW_RANK_MODE = 1
6130 13:59:15.035821 DLL_IDLE_MODE = 1
6131 13:59:15.039449 LP45_APHY_COMB_EN = 1
6132 13:59:15.042767 TX_ODT_DIS = 1
6133 13:59:15.043198 NEW_8X_MODE = 1
6134 13:59:15.045728 ===================================
6135 13:59:15.049381 ===================================
6136 13:59:15.052673 data_rate = 800
6137 13:59:15.055730 CKR = 1
6138 13:59:15.059525 DQ_P2S_RATIO = 4
6139 13:59:15.062408 ===================================
6140 13:59:15.065686 CA_P2S_RATIO = 4
6141 13:59:15.069321 DQ_CA_OPEN = 0
6142 13:59:15.069743 DQ_SEMI_OPEN = 1
6143 13:59:15.072209 CA_SEMI_OPEN = 1
6144 13:59:15.075326 CA_FULL_RATE = 0
6145 13:59:15.079497 DQ_CKDIV4_EN = 0
6146 13:59:15.082538 CA_CKDIV4_EN = 1
6147 13:59:15.086057 CA_PREDIV_EN = 0
6148 13:59:15.086475 PH8_DLY = 0
6149 13:59:15.089066 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6150 13:59:15.092339 DQ_AAMCK_DIV = 0
6151 13:59:15.095674 CA_AAMCK_DIV = 0
6152 13:59:15.099171 CA_ADMCK_DIV = 4
6153 13:59:15.099643 DQ_TRACK_CA_EN = 0
6154 13:59:15.102237 CA_PICK = 800
6155 13:59:15.105461 CA_MCKIO = 400
6156 13:59:15.108842 MCKIO_SEMI = 400
6157 13:59:15.112769 PLL_FREQ = 3016
6158 13:59:15.115437 DQ_UI_PI_RATIO = 32
6159 13:59:15.118868 CA_UI_PI_RATIO = 32
6160 13:59:15.122113 ===================================
6161 13:59:15.125633 ===================================
6162 13:59:15.126067 memory_type:LPDDR4
6163 13:59:15.128706 GP_NUM : 10
6164 13:59:15.131712 SRAM_EN : 1
6165 13:59:15.131792 MD32_EN : 0
6166 13:59:15.135204 ===================================
6167 13:59:15.138828 [ANA_INIT] >>>>>>>>>>>>>>
6168 13:59:15.141590 <<<<<< [CONFIGURE PHASE]: ANA_TX
6169 13:59:15.144977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6170 13:59:15.148340 ===================================
6171 13:59:15.151636 data_rate = 800,PCW = 0X7400
6172 13:59:15.155257 ===================================
6173 13:59:15.158677 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6174 13:59:15.162008 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6175 13:59:15.174988 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6176 13:59:15.178228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6177 13:59:15.181768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6178 13:59:15.184972 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6179 13:59:15.188504 [ANA_INIT] flow start
6180 13:59:15.191328 [ANA_INIT] PLL >>>>>>>>
6181 13:59:15.191444 [ANA_INIT] PLL <<<<<<<<
6182 13:59:15.194824 [ANA_INIT] MIDPI >>>>>>>>
6183 13:59:15.198116 [ANA_INIT] MIDPI <<<<<<<<
6184 13:59:15.198196 [ANA_INIT] DLL >>>>>>>>
6185 13:59:15.201550 [ANA_INIT] flow end
6186 13:59:15.204835 ============ LP4 DIFF to SE enter ============
6187 13:59:15.208086 ============ LP4 DIFF to SE exit ============
6188 13:59:15.211637 [ANA_INIT] <<<<<<<<<<<<<
6189 13:59:15.214833 [Flow] Enable top DCM control >>>>>
6190 13:59:15.218440 [Flow] Enable top DCM control <<<<<
6191 13:59:15.221846 Enable DLL master slave shuffle
6192 13:59:15.228118 ==============================================================
6193 13:59:15.228200 Gating Mode config
6194 13:59:15.234551 ==============================================================
6195 13:59:15.234633 Config description:
6196 13:59:15.244766 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6197 13:59:15.251335 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6198 13:59:15.258097 SELPH_MODE 0: By rank 1: By Phase
6199 13:59:15.261263 ==============================================================
6200 13:59:15.264582 GAT_TRACK_EN = 0
6201 13:59:15.268195 RX_GATING_MODE = 2
6202 13:59:15.271340 RX_GATING_TRACK_MODE = 2
6203 13:59:15.274449 SELPH_MODE = 1
6204 13:59:15.277641 PICG_EARLY_EN = 1
6205 13:59:15.281665 VALID_LAT_VALUE = 1
6206 13:59:15.287782 ==============================================================
6207 13:59:15.291250 Enter into Gating configuration >>>>
6208 13:59:15.294490 Exit from Gating configuration <<<<
6209 13:59:15.297914 Enter into DVFS_PRE_config >>>>>
6210 13:59:15.308093 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6211 13:59:15.310825 Exit from DVFS_PRE_config <<<<<
6212 13:59:15.314277 Enter into PICG configuration >>>>
6213 13:59:15.317305 Exit from PICG configuration <<<<
6214 13:59:15.320566 [RX_INPUT] configuration >>>>>
6215 13:59:15.320647 [RX_INPUT] configuration <<<<<
6216 13:59:15.327192 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6217 13:59:15.334438 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6218 13:59:15.337439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6219 13:59:15.343960 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6220 13:59:15.350845 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6221 13:59:15.357526 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6222 13:59:15.360572 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6223 13:59:15.363697 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6224 13:59:15.370639 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6225 13:59:15.374160 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6226 13:59:15.377371 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6227 13:59:15.383863 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6228 13:59:15.386980 ===================================
6229 13:59:15.387061 LPDDR4 DRAM CONFIGURATION
6230 13:59:15.390752 ===================================
6231 13:59:15.394004 EX_ROW_EN[0] = 0x0
6232 13:59:15.394085 EX_ROW_EN[1] = 0x0
6233 13:59:15.397610 LP4Y_EN = 0x0
6234 13:59:15.400493 WORK_FSP = 0x0
6235 13:59:15.400574 WL = 0x2
6236 13:59:15.403614 RL = 0x2
6237 13:59:15.403694 BL = 0x2
6238 13:59:15.407064 RPST = 0x0
6239 13:59:15.407145 RD_PRE = 0x0
6240 13:59:15.410495 WR_PRE = 0x1
6241 13:59:15.410580 WR_PST = 0x0
6242 13:59:15.414119 DBI_WR = 0x0
6243 13:59:15.414199 DBI_RD = 0x0
6244 13:59:15.416873 OTF = 0x1
6245 13:59:15.420123 ===================================
6246 13:59:15.423776 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6247 13:59:15.426881 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6248 13:59:15.433681 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6249 13:59:15.436825 ===================================
6250 13:59:15.436906 LPDDR4 DRAM CONFIGURATION
6251 13:59:15.440019 ===================================
6252 13:59:15.443513 EX_ROW_EN[0] = 0x10
6253 13:59:15.443593 EX_ROW_EN[1] = 0x0
6254 13:59:15.446944 LP4Y_EN = 0x0
6255 13:59:15.447024 WORK_FSP = 0x0
6256 13:59:15.450391 WL = 0x2
6257 13:59:15.453444 RL = 0x2
6258 13:59:15.453525 BL = 0x2
6259 13:59:15.456875 RPST = 0x0
6260 13:59:15.456983 RD_PRE = 0x0
6261 13:59:15.459799 WR_PRE = 0x1
6262 13:59:15.459883 WR_PST = 0x0
6263 13:59:15.463261 DBI_WR = 0x0
6264 13:59:15.463344 DBI_RD = 0x0
6265 13:59:15.466781 OTF = 0x1
6266 13:59:15.469989 ===================================
6267 13:59:15.476668 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6268 13:59:15.480108 nWR fixed to 30
6269 13:59:15.480191 [ModeRegInit_LP4] CH0 RK0
6270 13:59:15.483114 [ModeRegInit_LP4] CH0 RK1
6271 13:59:15.487000 [ModeRegInit_LP4] CH1 RK0
6272 13:59:15.487075 [ModeRegInit_LP4] CH1 RK1
6273 13:59:15.489679 match AC timing 19
6274 13:59:15.493313 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6275 13:59:15.496836 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6276 13:59:15.503243 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6277 13:59:15.506208 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6278 13:59:15.512929 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6279 13:59:15.513011 ==
6280 13:59:15.516447 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 13:59:15.519635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 13:59:15.519713 ==
6283 13:59:15.526205 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6284 13:59:15.529814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6285 13:59:15.533060 [CA 0] Center 36 (8~64) winsize 57
6286 13:59:15.536027 [CA 1] Center 36 (8~64) winsize 57
6287 13:59:15.539333 [CA 2] Center 36 (8~64) winsize 57
6288 13:59:15.542646 [CA 3] Center 36 (8~64) winsize 57
6289 13:59:15.545900 [CA 4] Center 36 (8~64) winsize 57
6290 13:59:15.549804 [CA 5] Center 36 (8~64) winsize 57
6291 13:59:15.549877
6292 13:59:15.552889 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6293 13:59:15.552964
6294 13:59:15.556270 [CATrainingPosCal] consider 1 rank data
6295 13:59:15.559337 u2DelayCellTimex100 = 270/100 ps
6296 13:59:15.562862 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 13:59:15.565892 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 13:59:15.573120 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 13:59:15.575731 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 13:59:15.579373 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 13:59:15.582441 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 13:59:15.582514
6303 13:59:15.585687 CA PerBit enable=1, Macro0, CA PI delay=36
6304 13:59:15.585786
6305 13:59:15.588903 [CBTSetCACLKResult] CA Dly = 36
6306 13:59:15.588996 CS Dly: 1 (0~32)
6307 13:59:15.592408 ==
6308 13:59:15.595959 Dram Type= 6, Freq= 0, CH_0, rank 1
6309 13:59:15.599364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 13:59:15.599476 ==
6311 13:59:15.602378 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6312 13:59:15.609197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6313 13:59:15.612146 [CA 0] Center 36 (8~64) winsize 57
6314 13:59:15.615487 [CA 1] Center 36 (8~64) winsize 57
6315 13:59:15.618939 [CA 2] Center 36 (8~64) winsize 57
6316 13:59:15.621928 [CA 3] Center 36 (8~64) winsize 57
6317 13:59:15.625313 [CA 4] Center 36 (8~64) winsize 57
6318 13:59:15.629130 [CA 5] Center 36 (8~64) winsize 57
6319 13:59:15.629211
6320 13:59:15.632254 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6321 13:59:15.632334
6322 13:59:15.635350 [CATrainingPosCal] consider 2 rank data
6323 13:59:15.639038 u2DelayCellTimex100 = 270/100 ps
6324 13:59:15.642317 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 13:59:15.645483 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 13:59:15.648597 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 13:59:15.652383 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 13:59:15.658932 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 13:59:15.661948 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 13:59:15.662022
6331 13:59:15.665264 CA PerBit enable=1, Macro0, CA PI delay=36
6332 13:59:15.665335
6333 13:59:15.668568 [CBTSetCACLKResult] CA Dly = 36
6334 13:59:15.668695 CS Dly: 1 (0~32)
6335 13:59:15.668775
6336 13:59:15.672279 ----->DramcWriteLeveling(PI) begin...
6337 13:59:15.672356 ==
6338 13:59:15.675217 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 13:59:15.682190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 13:59:15.682294 ==
6341 13:59:15.684927 Write leveling (Byte 0): 40 => 8
6342 13:59:15.685001 Write leveling (Byte 1): 40 => 8
6343 13:59:15.688517 DramcWriteLeveling(PI) end<-----
6344 13:59:15.688617
6345 13:59:15.691805 ==
6346 13:59:15.694678 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 13:59:15.698306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 13:59:15.698379 ==
6349 13:59:15.701569 [Gating] SW mode calibration
6350 13:59:15.707893 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6351 13:59:15.711274 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6352 13:59:15.717822 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6353 13:59:15.721283 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6354 13:59:15.724893 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6355 13:59:15.731070 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 13:59:15.734423 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 13:59:15.737765 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 13:59:15.744147 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 13:59:15.747649 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 13:59:15.751246 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 13:59:15.754066 Total UI for P1: 0, mck2ui 16
6362 13:59:15.757587 best dqsien dly found for B0: ( 0, 14, 24)
6363 13:59:15.760669 Total UI for P1: 0, mck2ui 16
6364 13:59:15.764130 best dqsien dly found for B1: ( 0, 14, 24)
6365 13:59:15.767541 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6366 13:59:15.770434 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6367 13:59:15.773738
6368 13:59:15.777623 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6369 13:59:15.781018 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6370 13:59:15.783933 [Gating] SW calibration Done
6371 13:59:15.784006 ==
6372 13:59:15.787590 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 13:59:15.790388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 13:59:15.790488 ==
6375 13:59:15.794148 RX Vref Scan: 0
6376 13:59:15.794253
6377 13:59:15.794344 RX Vref 0 -> 0, step: 1
6378 13:59:15.794430
6379 13:59:15.797679 RX Delay -410 -> 252, step: 16
6380 13:59:15.800559 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6381 13:59:15.807645 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6382 13:59:15.810610 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6383 13:59:15.813868 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6384 13:59:15.817318 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6385 13:59:15.823936 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6386 13:59:15.827061 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6387 13:59:15.830537 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6388 13:59:15.834001 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6389 13:59:15.840718 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6390 13:59:15.844328 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6391 13:59:15.847489 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6392 13:59:15.850448 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6393 13:59:15.857010 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6394 13:59:15.860021 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6395 13:59:15.863689 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6396 13:59:15.863778 ==
6397 13:59:15.866720 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 13:59:15.873362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 13:59:15.873440 ==
6400 13:59:15.873503 DQS Delay:
6401 13:59:15.876964 DQS0 = 59, DQS1 = 59
6402 13:59:15.877041 DQM Delay:
6403 13:59:15.877104 DQM0 = 18, DQM1 = 10
6404 13:59:15.880491 DQ Delay:
6405 13:59:15.883679 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6406 13:59:15.886741 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6407 13:59:15.886813 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6408 13:59:15.893233 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6409 13:59:15.893309
6410 13:59:15.893372
6411 13:59:15.893430 ==
6412 13:59:15.896636 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 13:59:15.899751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 13:59:15.899825 ==
6415 13:59:15.899886
6416 13:59:15.899943
6417 13:59:15.903110 TX Vref Scan disable
6418 13:59:15.903186 == TX Byte 0 ==
6419 13:59:15.906752 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6420 13:59:15.913239 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6421 13:59:15.913314 == TX Byte 1 ==
6422 13:59:15.916573 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6423 13:59:15.923268 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6424 13:59:15.923349 ==
6425 13:59:15.926504 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 13:59:15.929603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 13:59:15.929684 ==
6428 13:59:15.929748
6429 13:59:15.929808
6430 13:59:15.932982 TX Vref Scan disable
6431 13:59:15.933144 == TX Byte 0 ==
6432 13:59:15.939795 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6433 13:59:15.943072 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6434 13:59:15.943145 == TX Byte 1 ==
6435 13:59:15.949456 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6436 13:59:15.953450 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6437 13:59:15.953523
6438 13:59:15.953584 [DATLAT]
6439 13:59:15.956697 Freq=400, CH0 RK0
6440 13:59:15.956774
6441 13:59:15.956833 DATLAT Default: 0xf
6442 13:59:15.959520 0, 0xFFFF, sum = 0
6443 13:59:15.959594 1, 0xFFFF, sum = 0
6444 13:59:15.962846 2, 0xFFFF, sum = 0
6445 13:59:15.962920 3, 0xFFFF, sum = 0
6446 13:59:15.966247 4, 0xFFFF, sum = 0
6447 13:59:15.966319 5, 0xFFFF, sum = 0
6448 13:59:15.969560 6, 0xFFFF, sum = 0
6449 13:59:15.969657 7, 0xFFFF, sum = 0
6450 13:59:15.972801 8, 0xFFFF, sum = 0
6451 13:59:15.972902 9, 0xFFFF, sum = 0
6452 13:59:15.976025 10, 0xFFFF, sum = 0
6453 13:59:15.976101 11, 0xFFFF, sum = 0
6454 13:59:15.979495 12, 0xFFFF, sum = 0
6455 13:59:15.979567 13, 0x0, sum = 1
6456 13:59:15.983032 14, 0x0, sum = 2
6457 13:59:15.983103 15, 0x0, sum = 3
6458 13:59:15.985885 16, 0x0, sum = 4
6459 13:59:15.985958 best_step = 14
6460 13:59:15.986018
6461 13:59:15.986076 ==
6462 13:59:15.989644 Dram Type= 6, Freq= 0, CH_0, rank 0
6463 13:59:15.996000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 13:59:15.996079 ==
6465 13:59:15.996143 RX Vref Scan: 1
6466 13:59:15.996203
6467 13:59:15.999426 RX Vref 0 -> 0, step: 1
6468 13:59:15.999533
6469 13:59:16.002681 RX Delay -359 -> 252, step: 8
6470 13:59:16.002752
6471 13:59:16.006367 Set Vref, RX VrefLevel [Byte0]: 60
6472 13:59:16.009488 [Byte1]: 52
6473 13:59:16.012846
6474 13:59:16.012919 Final RX Vref Byte 0 = 60 to rank0
6475 13:59:16.015721 Final RX Vref Byte 1 = 52 to rank0
6476 13:59:16.019272 Final RX Vref Byte 0 = 60 to rank1
6477 13:59:16.022597 Final RX Vref Byte 1 = 52 to rank1==
6478 13:59:16.025767 Dram Type= 6, Freq= 0, CH_0, rank 0
6479 13:59:16.032526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 13:59:16.032606 ==
6481 13:59:16.032698 DQS Delay:
6482 13:59:16.035924 DQS0 = 60, DQS1 = 68
6483 13:59:16.036019 DQM Delay:
6484 13:59:16.036106 DQM0 = 14, DQM1 = 13
6485 13:59:16.039189 DQ Delay:
6486 13:59:16.042602 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6487 13:59:16.042711 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6488 13:59:16.045722 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6489 13:59:16.049192 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6490 13:59:16.049264
6491 13:59:16.052414
6492 13:59:16.059505 [DQSOSCAuto] RK0, (LSB)MR18= 0x8282, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6493 13:59:16.062453 CH0 RK0: MR19=C0C, MR18=8282
6494 13:59:16.069137 CH0_RK0: MR19=0xC0C, MR18=0x8282, DQSOSC=393, MR23=63, INC=382, DEC=254
6495 13:59:16.069211 ==
6496 13:59:16.072490 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 13:59:16.075937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 13:59:16.076012 ==
6499 13:59:16.078823 [Gating] SW mode calibration
6500 13:59:16.085402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6501 13:59:16.092109 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6502 13:59:16.095318 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6503 13:59:16.098700 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6504 13:59:16.105270 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6505 13:59:16.108626 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 13:59:16.111843 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 13:59:16.118496 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 13:59:16.122156 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 13:59:16.125627 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 13:59:16.131978 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 13:59:16.132069 Total UI for P1: 0, mck2ui 16
6512 13:59:16.138193 best dqsien dly found for B0: ( 0, 14, 24)
6513 13:59:16.138274 Total UI for P1: 0, mck2ui 16
6514 13:59:16.142072 best dqsien dly found for B1: ( 0, 14, 24)
6515 13:59:16.148445 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6516 13:59:16.151728 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6517 13:59:16.151829
6518 13:59:16.154820 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6519 13:59:16.158151 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6520 13:59:16.161569 [Gating] SW calibration Done
6521 13:59:16.161679 ==
6522 13:59:16.165191 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 13:59:16.168438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 13:59:16.168539 ==
6525 13:59:16.171557 RX Vref Scan: 0
6526 13:59:16.171677
6527 13:59:16.171738 RX Vref 0 -> 0, step: 1
6528 13:59:16.171796
6529 13:59:16.174744 RX Delay -410 -> 252, step: 16
6530 13:59:16.181220 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6531 13:59:16.184844 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6532 13:59:16.188222 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6533 13:59:16.191459 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6534 13:59:16.197926 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6535 13:59:16.201446 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6536 13:59:16.204540 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6537 13:59:16.208057 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6538 13:59:16.214176 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6539 13:59:16.217755 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6540 13:59:16.220950 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6541 13:59:16.224249 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6542 13:59:16.231274 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6543 13:59:16.234209 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6544 13:59:16.237829 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6545 13:59:16.241223 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6546 13:59:16.244138 ==
6547 13:59:16.247956 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 13:59:16.250860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 13:59:16.250960 ==
6550 13:59:16.251051 DQS Delay:
6551 13:59:16.254090 DQS0 = 59, DQS1 = 59
6552 13:59:16.254190 DQM Delay:
6553 13:59:16.258093 DQM0 = 16, DQM1 = 10
6554 13:59:16.258193 DQ Delay:
6555 13:59:16.260688 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6556 13:59:16.264403 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6557 13:59:16.267369 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6558 13:59:16.271028 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6559 13:59:16.271116
6560 13:59:16.271182
6561 13:59:16.271242 ==
6562 13:59:16.274025 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 13:59:16.277358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 13:59:16.277437 ==
6565 13:59:16.277506
6566 13:59:16.277567
6567 13:59:16.280608 TX Vref Scan disable
6568 13:59:16.280680 == TX Byte 0 ==
6569 13:59:16.287350 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6570 13:59:16.290438 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6571 13:59:16.290519 == TX Byte 1 ==
6572 13:59:16.297756 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6573 13:59:16.300718 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6574 13:59:16.300796 ==
6575 13:59:16.303767 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 13:59:16.307390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 13:59:16.307464 ==
6578 13:59:16.307533
6579 13:59:16.307593
6580 13:59:16.311195 TX Vref Scan disable
6581 13:59:16.311271 == TX Byte 0 ==
6582 13:59:16.317251 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6583 13:59:16.320988 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6584 13:59:16.321092 == TX Byte 1 ==
6585 13:59:16.327199 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6586 13:59:16.330638 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6587 13:59:16.330731
6588 13:59:16.330797 [DATLAT]
6589 13:59:16.334072 Freq=400, CH0 RK1
6590 13:59:16.334156
6591 13:59:16.334223 DATLAT Default: 0xe
6592 13:59:16.337088 0, 0xFFFF, sum = 0
6593 13:59:16.337174 1, 0xFFFF, sum = 0
6594 13:59:16.340517 2, 0xFFFF, sum = 0
6595 13:59:16.340611 3, 0xFFFF, sum = 0
6596 13:59:16.344110 4, 0xFFFF, sum = 0
6597 13:59:16.344195 5, 0xFFFF, sum = 0
6598 13:59:16.347202 6, 0xFFFF, sum = 0
6599 13:59:16.347314 7, 0xFFFF, sum = 0
6600 13:59:16.350609 8, 0xFFFF, sum = 0
6601 13:59:16.353702 9, 0xFFFF, sum = 0
6602 13:59:16.353807 10, 0xFFFF, sum = 0
6603 13:59:16.357317 11, 0xFFFF, sum = 0
6604 13:59:16.357422 12, 0xFFFF, sum = 0
6605 13:59:16.360940 13, 0x0, sum = 1
6606 13:59:16.361016 14, 0x0, sum = 2
6607 13:59:16.363922 15, 0x0, sum = 3
6608 13:59:16.363996 16, 0x0, sum = 4
6609 13:59:16.364058 best_step = 14
6610 13:59:16.364117
6611 13:59:16.367185 ==
6612 13:59:16.370359 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 13:59:16.373673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 13:59:16.373752 ==
6615 13:59:16.373818 RX Vref Scan: 0
6616 13:59:16.373879
6617 13:59:16.376933 RX Vref 0 -> 0, step: 1
6618 13:59:16.377014
6619 13:59:16.380250 RX Delay -359 -> 252, step: 8
6620 13:59:16.387466 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6621 13:59:16.391001 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6622 13:59:16.393881 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6623 13:59:16.397159 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6624 13:59:16.404288 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6625 13:59:16.407395 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6626 13:59:16.410936 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6627 13:59:16.413909 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6628 13:59:16.420678 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6629 13:59:16.424237 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6630 13:59:16.427152 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6631 13:59:16.433997 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6632 13:59:16.437003 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6633 13:59:16.440494 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6634 13:59:16.443874 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6635 13:59:16.450512 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6636 13:59:16.450592 ==
6637 13:59:16.454146 Dram Type= 6, Freq= 0, CH_0, rank 1
6638 13:59:16.457134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 13:59:16.457219 ==
6640 13:59:16.457314 DQS Delay:
6641 13:59:16.460467 DQS0 = 60, DQS1 = 72
6642 13:59:16.460549 DQM Delay:
6643 13:59:16.463615 DQM0 = 11, DQM1 = 17
6644 13:59:16.463696 DQ Delay:
6645 13:59:16.466957 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6646 13:59:16.470603 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6647 13:59:16.474191 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6648 13:59:16.477001 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =24
6649 13:59:16.477083
6650 13:59:16.477147
6651 13:59:16.484012 [DQSOSCAuto] RK1, (LSB)MR18= 0xca7e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6652 13:59:16.487126 CH0 RK1: MR19=C0C, MR18=CA7E
6653 13:59:16.493702 CH0_RK1: MR19=0xC0C, MR18=0xCA7E, DQSOSC=384, MR23=63, INC=400, DEC=267
6654 13:59:16.497177 [RxdqsGatingPostProcess] freq 400
6655 13:59:16.503470 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6656 13:59:16.503548 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 13:59:16.507129 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 13:59:16.510158 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 13:59:16.513352 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 13:59:16.516967 best DQS0 dly(2T, 0.5T) = (0, 10)
6661 13:59:16.520700 best DQS1 dly(2T, 0.5T) = (0, 10)
6662 13:59:16.523810 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6663 13:59:16.526660 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6664 13:59:16.530189 Pre-setting of DQS Precalculation
6665 13:59:16.536898 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6666 13:59:16.536977 ==
6667 13:59:16.540313 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 13:59:16.543578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 13:59:16.543657 ==
6670 13:59:16.549979 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6671 13:59:16.553435 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6672 13:59:16.556542 [CA 0] Center 36 (8~64) winsize 57
6673 13:59:16.560348 [CA 1] Center 36 (8~64) winsize 57
6674 13:59:16.563268 [CA 2] Center 36 (8~64) winsize 57
6675 13:59:16.566769 [CA 3] Center 36 (8~64) winsize 57
6676 13:59:16.570261 [CA 4] Center 36 (8~64) winsize 57
6677 13:59:16.573548 [CA 5] Center 36 (8~64) winsize 57
6678 13:59:16.573680
6679 13:59:16.576885 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6680 13:59:16.577036
6681 13:59:16.579996 [CATrainingPosCal] consider 1 rank data
6682 13:59:16.583086 u2DelayCellTimex100 = 270/100 ps
6683 13:59:16.586661 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 13:59:16.590047 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 13:59:16.593358 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 13:59:16.599954 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 13:59:16.603350 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 13:59:16.606587 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 13:59:16.607175
6690 13:59:16.609899 CA PerBit enable=1, Macro0, CA PI delay=36
6691 13:59:16.610386
6692 13:59:16.613518 [CBTSetCACLKResult] CA Dly = 36
6693 13:59:16.614034 CS Dly: 1 (0~32)
6694 13:59:16.614430 ==
6695 13:59:16.616972 Dram Type= 6, Freq= 0, CH_1, rank 1
6696 13:59:16.623089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 13:59:16.623640 ==
6698 13:59:16.626458 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6699 13:59:16.633337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6700 13:59:16.636397 [CA 0] Center 36 (8~64) winsize 57
6701 13:59:16.639771 [CA 1] Center 36 (8~64) winsize 57
6702 13:59:16.643158 [CA 2] Center 36 (8~64) winsize 57
6703 13:59:16.646797 [CA 3] Center 36 (8~64) winsize 57
6704 13:59:16.650006 [CA 4] Center 36 (8~64) winsize 57
6705 13:59:16.653564 [CA 5] Center 36 (8~64) winsize 57
6706 13:59:16.654023
6707 13:59:16.656742 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6708 13:59:16.657252
6709 13:59:16.659581 [CATrainingPosCal] consider 2 rank data
6710 13:59:16.663174 u2DelayCellTimex100 = 270/100 ps
6711 13:59:16.666405 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 13:59:16.670030 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 13:59:16.672936 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 13:59:16.676344 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 13:59:16.679169 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 13:59:16.686139 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 13:59:16.686625
6718 13:59:16.689036 CA PerBit enable=1, Macro0, CA PI delay=36
6719 13:59:16.689674
6720 13:59:16.692858 [CBTSetCACLKResult] CA Dly = 36
6721 13:59:16.693362 CS Dly: 1 (0~32)
6722 13:59:16.693758
6723 13:59:16.696037 ----->DramcWriteLeveling(PI) begin...
6724 13:59:16.696636 ==
6725 13:59:16.699435 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 13:59:16.702876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 13:59:16.706082 ==
6728 13:59:16.706567 Write leveling (Byte 0): 40 => 8
6729 13:59:16.709640 Write leveling (Byte 1): 40 => 8
6730 13:59:16.712514 DramcWriteLeveling(PI) end<-----
6731 13:59:16.713136
6732 13:59:16.713675 ==
6733 13:59:16.715998 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 13:59:16.722863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 13:59:16.723368 ==
6736 13:59:16.723833 [Gating] SW mode calibration
6737 13:59:16.732809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6738 13:59:16.735926 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6739 13:59:16.742359 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6740 13:59:16.745832 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6741 13:59:16.749181 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6742 13:59:16.752722 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 13:59:16.759252 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 13:59:16.762611 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 13:59:16.765605 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 13:59:16.772322 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 13:59:16.775689 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 13:59:16.779266 Total UI for P1: 0, mck2ui 16
6749 13:59:16.782672 best dqsien dly found for B0: ( 0, 14, 24)
6750 13:59:16.785964 Total UI for P1: 0, mck2ui 16
6751 13:59:16.789271 best dqsien dly found for B1: ( 0, 14, 24)
6752 13:59:16.792281 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6753 13:59:16.795820 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6754 13:59:16.796264
6755 13:59:16.799287 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6756 13:59:16.805782 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6757 13:59:16.806456 [Gating] SW calibration Done
6758 13:59:16.807095 ==
6759 13:59:16.808648 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 13:59:16.815872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 13:59:16.816444 ==
6762 13:59:16.816934 RX Vref Scan: 0
6763 13:59:16.817412
6764 13:59:16.819092 RX Vref 0 -> 0, step: 1
6765 13:59:16.819643
6766 13:59:16.822113 RX Delay -410 -> 252, step: 16
6767 13:59:16.825464 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6768 13:59:16.828987 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6769 13:59:16.835921 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6770 13:59:16.838803 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6771 13:59:16.842097 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6772 13:59:16.845818 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6773 13:59:16.852077 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6774 13:59:16.855609 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6775 13:59:16.859027 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6776 13:59:16.861835 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6777 13:59:16.868680 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6778 13:59:16.871888 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6779 13:59:16.875235 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6780 13:59:16.878489 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6781 13:59:16.885249 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6782 13:59:16.888715 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6783 13:59:16.889189 ==
6784 13:59:16.891855 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 13:59:16.895148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 13:59:16.895693 ==
6787 13:59:16.898269 DQS Delay:
6788 13:59:16.898832 DQS0 = 51, DQS1 = 59
6789 13:59:16.901830 DQM Delay:
6790 13:59:16.902284 DQM0 = 13, DQM1 = 12
6791 13:59:16.902641 DQ Delay:
6792 13:59:16.904926 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6793 13:59:16.908330 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6794 13:59:16.911639 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6795 13:59:16.915339 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6796 13:59:16.915836
6797 13:59:16.916209
6798 13:59:16.916571 ==
6799 13:59:16.918313 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 13:59:16.921703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 13:59:16.924809 ==
6802 13:59:16.925109
6803 13:59:16.925310
6804 13:59:16.925488 TX Vref Scan disable
6805 13:59:16.928153 == TX Byte 0 ==
6806 13:59:16.931276 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 13:59:16.934766 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 13:59:16.937919 == TX Byte 1 ==
6809 13:59:16.941417 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6810 13:59:16.944319 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6811 13:59:16.944428 ==
6812 13:59:16.947555 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 13:59:16.954649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 13:59:16.954755 ==
6815 13:59:16.954854
6816 13:59:16.954943
6817 13:59:16.955022 TX Vref Scan disable
6818 13:59:16.957836 == TX Byte 0 ==
6819 13:59:16.961178 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6820 13:59:16.964458 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6821 13:59:16.967648 == TX Byte 1 ==
6822 13:59:16.971218 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6823 13:59:16.974163 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6824 13:59:16.974242
6825 13:59:16.977481 [DATLAT]
6826 13:59:16.977590 Freq=400, CH1 RK0
6827 13:59:16.977691
6828 13:59:16.980867 DATLAT Default: 0xf
6829 13:59:16.980952 0, 0xFFFF, sum = 0
6830 13:59:16.984189 1, 0xFFFF, sum = 0
6831 13:59:16.984304 2, 0xFFFF, sum = 0
6832 13:59:16.987893 3, 0xFFFF, sum = 0
6833 13:59:16.988006 4, 0xFFFF, sum = 0
6834 13:59:16.991017 5, 0xFFFF, sum = 0
6835 13:59:16.991133 6, 0xFFFF, sum = 0
6836 13:59:16.994147 7, 0xFFFF, sum = 0
6837 13:59:16.994228 8, 0xFFFF, sum = 0
6838 13:59:16.997491 9, 0xFFFF, sum = 0
6839 13:59:16.997597 10, 0xFFFF, sum = 0
6840 13:59:17.000789 11, 0xFFFF, sum = 0
6841 13:59:17.003980 12, 0xFFFF, sum = 0
6842 13:59:17.004059 13, 0x0, sum = 1
6843 13:59:17.004130 14, 0x0, sum = 2
6844 13:59:17.007212 15, 0x0, sum = 3
6845 13:59:17.007317 16, 0x0, sum = 4
6846 13:59:17.011060 best_step = 14
6847 13:59:17.011175
6848 13:59:17.011275 ==
6849 13:59:17.014360 Dram Type= 6, Freq= 0, CH_1, rank 0
6850 13:59:17.017195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 13:59:17.017307 ==
6852 13:59:17.020884 RX Vref Scan: 1
6853 13:59:17.020987
6854 13:59:17.021089 RX Vref 0 -> 0, step: 1
6855 13:59:17.021185
6856 13:59:17.024192 RX Delay -359 -> 252, step: 8
6857 13:59:17.024302
6858 13:59:17.027055 Set Vref, RX VrefLevel [Byte0]: 56
6859 13:59:17.030610 [Byte1]: 49
6860 13:59:17.035831
6861 13:59:17.035907 Final RX Vref Byte 0 = 56 to rank0
6862 13:59:17.038910 Final RX Vref Byte 1 = 49 to rank0
6863 13:59:17.042417 Final RX Vref Byte 0 = 56 to rank1
6864 13:59:17.045892 Final RX Vref Byte 1 = 49 to rank1==
6865 13:59:17.049040 Dram Type= 6, Freq= 0, CH_1, rank 0
6866 13:59:17.055382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 13:59:17.055501 ==
6868 13:59:17.055564 DQS Delay:
6869 13:59:17.058836 DQS0 = 56, DQS1 = 64
6870 13:59:17.058907 DQM Delay:
6871 13:59:17.058967 DQM0 = 13, DQM1 = 11
6872 13:59:17.062387 DQ Delay:
6873 13:59:17.065438 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6874 13:59:17.068707 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6875 13:59:17.068775 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6876 13:59:17.072166 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6877 13:59:17.075307
6878 13:59:17.075378
6879 13:59:17.082446 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6880 13:59:17.085571 CH1 RK0: MR19=C0C, MR18=5E71
6881 13:59:17.092545 CH1_RK0: MR19=0xC0C, MR18=0x5E71, DQSOSC=395, MR23=63, INC=378, DEC=252
6882 13:59:17.092622 ==
6883 13:59:17.095885 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 13:59:17.098928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 13:59:17.099009 ==
6886 13:59:17.101916 [Gating] SW mode calibration
6887 13:59:17.108520 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6888 13:59:17.115727 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6889 13:59:17.118616 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6890 13:59:17.122156 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6891 13:59:17.128229 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6892 13:59:17.131357 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 13:59:17.134927 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 13:59:17.141273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 13:59:17.145028 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 13:59:17.147756 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 13:59:17.155130 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 13:59:17.155250 Total UI for P1: 0, mck2ui 16
6899 13:59:17.161522 best dqsien dly found for B0: ( 0, 14, 24)
6900 13:59:17.161627 Total UI for P1: 0, mck2ui 16
6901 13:59:17.167672 best dqsien dly found for B1: ( 0, 14, 24)
6902 13:59:17.171237 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6903 13:59:17.174576 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6904 13:59:17.174650
6905 13:59:17.177617 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6906 13:59:17.181055 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6907 13:59:17.184384 [Gating] SW calibration Done
6908 13:59:17.184496 ==
6909 13:59:17.187947 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 13:59:17.191138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 13:59:17.191216 ==
6912 13:59:17.194711 RX Vref Scan: 0
6913 13:59:17.194787
6914 13:59:17.194886 RX Vref 0 -> 0, step: 1
6915 13:59:17.194950
6916 13:59:17.197667 RX Delay -410 -> 252, step: 16
6917 13:59:17.204347 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6918 13:59:17.207413 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6919 13:59:17.211160 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6920 13:59:17.214375 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6921 13:59:17.220755 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6922 13:59:17.224634 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6923 13:59:17.227811 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6924 13:59:17.230966 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6925 13:59:17.237346 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6926 13:59:17.240939 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6927 13:59:17.244343 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6928 13:59:17.247398 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6929 13:59:17.254502 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6930 13:59:17.257687 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6931 13:59:17.260981 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6932 13:59:17.264942 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6933 13:59:17.265027 ==
6934 13:59:17.267568 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 13:59:17.274544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 13:59:17.274653 ==
6937 13:59:17.274760 DQS Delay:
6938 13:59:17.277410 DQS0 = 59, DQS1 = 59
6939 13:59:17.277493 DQM Delay:
6940 13:59:17.280882 DQM0 = 19, DQM1 = 12
6941 13:59:17.280959 DQ Delay:
6942 13:59:17.283965 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6943 13:59:17.287339 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6944 13:59:17.291049 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6945 13:59:17.294456 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6946 13:59:17.294560
6947 13:59:17.294643
6948 13:59:17.294725 ==
6949 13:59:17.297325 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 13:59:17.300686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 13:59:17.300770 ==
6952 13:59:17.300853
6953 13:59:17.300932
6954 13:59:17.303849 TX Vref Scan disable
6955 13:59:17.303926 == TX Byte 0 ==
6956 13:59:17.310445 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6957 13:59:17.314195 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6958 13:59:17.314276 == TX Byte 1 ==
6959 13:59:17.320752 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6960 13:59:17.324093 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6961 13:59:17.324175 ==
6962 13:59:17.327198 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 13:59:17.330508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 13:59:17.330588 ==
6965 13:59:17.330671
6966 13:59:17.330770
6967 13:59:17.334044 TX Vref Scan disable
6968 13:59:17.334144 == TX Byte 0 ==
6969 13:59:17.340699 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6970 13:59:17.343774 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6971 13:59:17.343852 == TX Byte 1 ==
6972 13:59:17.350752 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6973 13:59:17.353762 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6974 13:59:17.353839
6975 13:59:17.353922 [DATLAT]
6976 13:59:17.357210 Freq=400, CH1 RK1
6977 13:59:17.357285
6978 13:59:17.357370 DATLAT Default: 0xe
6979 13:59:17.360248 0, 0xFFFF, sum = 0
6980 13:59:17.360349 1, 0xFFFF, sum = 0
6981 13:59:17.363576 2, 0xFFFF, sum = 0
6982 13:59:17.363661 3, 0xFFFF, sum = 0
6983 13:59:17.367162 4, 0xFFFF, sum = 0
6984 13:59:17.367264 5, 0xFFFF, sum = 0
6985 13:59:17.370478 6, 0xFFFF, sum = 0
6986 13:59:17.370588 7, 0xFFFF, sum = 0
6987 13:59:17.373431 8, 0xFFFF, sum = 0
6988 13:59:17.373523 9, 0xFFFF, sum = 0
6989 13:59:17.377166 10, 0xFFFF, sum = 0
6990 13:59:17.380177 11, 0xFFFF, sum = 0
6991 13:59:17.380262 12, 0xFFFF, sum = 0
6992 13:59:17.383348 13, 0x0, sum = 1
6993 13:59:17.383451 14, 0x0, sum = 2
6994 13:59:17.386885 15, 0x0, sum = 3
6995 13:59:17.386998 16, 0x0, sum = 4
6996 13:59:17.387084 best_step = 14
6997 13:59:17.387164
6998 13:59:17.390114 ==
6999 13:59:17.393449 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 13:59:17.397200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 13:59:17.397285 ==
7002 13:59:17.397376 RX Vref Scan: 0
7003 13:59:17.397456
7004 13:59:17.400391 RX Vref 0 -> 0, step: 1
7005 13:59:17.400479
7006 13:59:17.403341 RX Delay -359 -> 252, step: 8
7007 13:59:17.410534 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7008 13:59:17.413724 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7009 13:59:17.416804 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7010 13:59:17.420287 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7011 13:59:17.427010 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7012 13:59:17.430599 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7013 13:59:17.433545 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7014 13:59:17.437011 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7015 13:59:17.443612 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7016 13:59:17.446796 iDelay=217, Bit 9, Center -60 (-319 ~ 200) 520
7017 13:59:17.450517 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7018 13:59:17.453937 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7019 13:59:17.460149 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7020 13:59:17.463903 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7021 13:59:17.466964 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7022 13:59:17.473419 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7023 13:59:17.473507 ==
7024 13:59:17.476769 Dram Type= 6, Freq= 0, CH_1, rank 1
7025 13:59:17.480545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7026 13:59:17.480623 ==
7027 13:59:17.480706 DQS Delay:
7028 13:59:17.483569 DQS0 = 60, DQS1 = 64
7029 13:59:17.483645 DQM Delay:
7030 13:59:17.487041 DQM0 = 12, DQM1 = 11
7031 13:59:17.487125 DQ Delay:
7032 13:59:17.490079 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7033 13:59:17.493525 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7034 13:59:17.496915 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7035 13:59:17.499988 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7036 13:59:17.500065
7037 13:59:17.500145
7038 13:59:17.506986 [DQSOSCAuto] RK1, (LSB)MR18= 0x82b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
7039 13:59:17.510365 CH1 RK1: MR19=C0C, MR18=82B3
7040 13:59:17.516674 CH1_RK1: MR19=0xC0C, MR18=0x82B3, DQSOSC=387, MR23=63, INC=394, DEC=262
7041 13:59:17.520230 [RxdqsGatingPostProcess] freq 400
7042 13:59:17.526494 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7043 13:59:17.526599 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 13:59:17.530502 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 13:59:17.533173 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 13:59:17.536702 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 13:59:17.539950 best DQS0 dly(2T, 0.5T) = (0, 10)
7048 13:59:17.543361 best DQS1 dly(2T, 0.5T) = (0, 10)
7049 13:59:17.547072 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7050 13:59:17.549819 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7051 13:59:17.553368 Pre-setting of DQS Precalculation
7052 13:59:17.556513 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7053 13:59:17.566656 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7054 13:59:17.573134 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7055 13:59:17.573238
7056 13:59:17.573340
7057 13:59:17.576600 [Calibration Summary] 800 Mbps
7058 13:59:17.576677 CH 0, Rank 0
7059 13:59:17.579839 SW Impedance : PASS
7060 13:59:17.579923 DUTY Scan : NO K
7061 13:59:17.583285 ZQ Calibration : PASS
7062 13:59:17.586665 Jitter Meter : NO K
7063 13:59:17.586743 CBT Training : PASS
7064 13:59:17.589694 Write leveling : PASS
7065 13:59:17.593216 RX DQS gating : PASS
7066 13:59:17.593315 RX DQ/DQS(RDDQC) : PASS
7067 13:59:17.596208 TX DQ/DQS : PASS
7068 13:59:17.599661 RX DATLAT : PASS
7069 13:59:17.599737 RX DQ/DQS(Engine): PASS
7070 13:59:17.602622 TX OE : NO K
7071 13:59:17.602697 All Pass.
7072 13:59:17.602777
7073 13:59:17.606314 CH 0, Rank 1
7074 13:59:17.606389 SW Impedance : PASS
7075 13:59:17.609403 DUTY Scan : NO K
7076 13:59:17.612682 ZQ Calibration : PASS
7077 13:59:17.612761 Jitter Meter : NO K
7078 13:59:17.616060 CBT Training : PASS
7079 13:59:17.619257 Write leveling : NO K
7080 13:59:17.619357 RX DQS gating : PASS
7081 13:59:17.622907 RX DQ/DQS(RDDQC) : PASS
7082 13:59:17.626417 TX DQ/DQS : PASS
7083 13:59:17.626493 RX DATLAT : PASS
7084 13:59:17.630045 RX DQ/DQS(Engine): PASS
7085 13:59:17.630128 TX OE : NO K
7086 13:59:17.633253 All Pass.
7087 13:59:17.633331
7088 13:59:17.633412 CH 1, Rank 0
7089 13:59:17.636089 SW Impedance : PASS
7090 13:59:17.636164 DUTY Scan : NO K
7091 13:59:17.639512 ZQ Calibration : PASS
7092 13:59:17.643007 Jitter Meter : NO K
7093 13:59:17.643110 CBT Training : PASS
7094 13:59:17.645979 Write leveling : PASS
7095 13:59:17.649699 RX DQS gating : PASS
7096 13:59:17.649852 RX DQ/DQS(RDDQC) : PASS
7097 13:59:17.652705 TX DQ/DQS : PASS
7098 13:59:17.656086 RX DATLAT : PASS
7099 13:59:17.656186 RX DQ/DQS(Engine): PASS
7100 13:59:17.659567 TX OE : NO K
7101 13:59:17.659668 All Pass.
7102 13:59:17.659767
7103 13:59:17.662489 CH 1, Rank 1
7104 13:59:17.662595 SW Impedance : PASS
7105 13:59:17.665866 DUTY Scan : NO K
7106 13:59:17.669240 ZQ Calibration : PASS
7107 13:59:17.669316 Jitter Meter : NO K
7108 13:59:17.672487 CBT Training : PASS
7109 13:59:17.675894 Write leveling : NO K
7110 13:59:17.675974 RX DQS gating : PASS
7111 13:59:17.679300 RX DQ/DQS(RDDQC) : PASS
7112 13:59:17.682756 TX DQ/DQS : PASS
7113 13:59:17.682836 RX DATLAT : PASS
7114 13:59:17.686283 RX DQ/DQS(Engine): PASS
7115 13:59:17.686360 TX OE : NO K
7116 13:59:17.689646 All Pass.
7117 13:59:17.689723
7118 13:59:17.689804 DramC Write-DBI off
7119 13:59:17.692540 PER_BANK_REFRESH: Hybrid Mode
7120 13:59:17.696116 TX_TRACKING: ON
7121 13:59:17.702302 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7122 13:59:17.705610 [FAST_K] Save calibration result to emmc
7123 13:59:17.712623 dramc_set_vcore_voltage set vcore to 725000
7124 13:59:17.712706 Read voltage for 1600, 0
7125 13:59:17.712789 Vio18 = 0
7126 13:59:17.715741 Vcore = 725000
7127 13:59:17.715829 Vdram = 0
7128 13:59:17.715925 Vddq = 0
7129 13:59:17.719314 Vmddr = 0
7130 13:59:17.722302 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7131 13:59:17.729152 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7132 13:59:17.732446 MEM_TYPE=3, freq_sel=13
7133 13:59:17.732553 sv_algorithm_assistance_LP4_3733
7134 13:59:17.739069 ============ PULL DRAM RESETB DOWN ============
7135 13:59:17.742385 ========== PULL DRAM RESETB DOWN end =========
7136 13:59:17.745730 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7137 13:59:17.748978 ===================================
7138 13:59:17.752028 LPDDR4 DRAM CONFIGURATION
7139 13:59:17.755585 ===================================
7140 13:59:17.758969 EX_ROW_EN[0] = 0x0
7141 13:59:17.759078 EX_ROW_EN[1] = 0x0
7142 13:59:17.762483 LP4Y_EN = 0x0
7143 13:59:17.762594 WORK_FSP = 0x1
7144 13:59:17.765298 WL = 0x5
7145 13:59:17.765405 RL = 0x5
7146 13:59:17.768800 BL = 0x2
7147 13:59:17.768905 RPST = 0x0
7148 13:59:17.772134 RD_PRE = 0x0
7149 13:59:17.772215 WR_PRE = 0x1
7150 13:59:17.775176 WR_PST = 0x1
7151 13:59:17.775282 DBI_WR = 0x0
7152 13:59:17.778671 DBI_RD = 0x0
7153 13:59:17.782086 OTF = 0x1
7154 13:59:17.782199 ===================================
7155 13:59:17.785524 ===================================
7156 13:59:17.788504 ANA top config
7157 13:59:17.792027 ===================================
7158 13:59:17.795211 DLL_ASYNC_EN = 0
7159 13:59:17.795319 ALL_SLAVE_EN = 0
7160 13:59:17.798996 NEW_RANK_MODE = 1
7161 13:59:17.802268 DLL_IDLE_MODE = 1
7162 13:59:17.805636 LP45_APHY_COMB_EN = 1
7163 13:59:17.808337 TX_ODT_DIS = 0
7164 13:59:17.808419 NEW_8X_MODE = 1
7165 13:59:17.811499 ===================================
7166 13:59:17.815205 ===================================
7167 13:59:17.818306 data_rate = 3200
7168 13:59:17.821804 CKR = 1
7169 13:59:17.825068 DQ_P2S_RATIO = 8
7170 13:59:17.828345 ===================================
7171 13:59:17.831403 CA_P2S_RATIO = 8
7172 13:59:17.834900 DQ_CA_OPEN = 0
7173 13:59:17.834984 DQ_SEMI_OPEN = 0
7174 13:59:17.838818 CA_SEMI_OPEN = 0
7175 13:59:17.841567 CA_FULL_RATE = 0
7176 13:59:17.845021 DQ_CKDIV4_EN = 0
7177 13:59:17.848416 CA_CKDIV4_EN = 0
7178 13:59:17.851454 CA_PREDIV_EN = 0
7179 13:59:17.851539 PH8_DLY = 12
7180 13:59:17.854737 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7181 13:59:17.858360 DQ_AAMCK_DIV = 4
7182 13:59:17.861801 CA_AAMCK_DIV = 4
7183 13:59:17.864952 CA_ADMCK_DIV = 4
7184 13:59:17.868407 DQ_TRACK_CA_EN = 0
7185 13:59:17.868531 CA_PICK = 1600
7186 13:59:17.871709 CA_MCKIO = 1600
7187 13:59:17.874680 MCKIO_SEMI = 0
7188 13:59:17.878310 PLL_FREQ = 3068
7189 13:59:17.881290 DQ_UI_PI_RATIO = 32
7190 13:59:17.884550 CA_UI_PI_RATIO = 0
7191 13:59:17.888300 ===================================
7192 13:59:17.891351 ===================================
7193 13:59:17.891482 memory_type:LPDDR4
7194 13:59:17.894569 GP_NUM : 10
7195 13:59:17.897880 SRAM_EN : 1
7196 13:59:17.897984 MD32_EN : 0
7197 13:59:17.901367 ===================================
7198 13:59:17.904588 [ANA_INIT] >>>>>>>>>>>>>>
7199 13:59:17.907866 <<<<<< [CONFIGURE PHASE]: ANA_TX
7200 13:59:17.911081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7201 13:59:17.914676 ===================================
7202 13:59:17.917879 data_rate = 3200,PCW = 0X7600
7203 13:59:17.921309 ===================================
7204 13:59:17.924916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7205 13:59:17.928152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7206 13:59:17.934491 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7207 13:59:17.937893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7208 13:59:17.944797 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7209 13:59:17.947770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7210 13:59:17.947865 [ANA_INIT] flow start
7211 13:59:17.951616 [ANA_INIT] PLL >>>>>>>>
7212 13:59:17.954546 [ANA_INIT] PLL <<<<<<<<
7213 13:59:17.954619 [ANA_INIT] MIDPI >>>>>>>>
7214 13:59:17.957680 [ANA_INIT] MIDPI <<<<<<<<
7215 13:59:17.961146 [ANA_INIT] DLL >>>>>>>>
7216 13:59:17.961248 [ANA_INIT] DLL <<<<<<<<
7217 13:59:17.964412 [ANA_INIT] flow end
7218 13:59:17.967766 ============ LP4 DIFF to SE enter ============
7219 13:59:17.971163 ============ LP4 DIFF to SE exit ============
7220 13:59:17.974383 [ANA_INIT] <<<<<<<<<<<<<
7221 13:59:17.977944 [Flow] Enable top DCM control >>>>>
7222 13:59:17.981620 [Flow] Enable top DCM control <<<<<
7223 13:59:17.984410 Enable DLL master slave shuffle
7224 13:59:17.991502 ==============================================================
7225 13:59:17.991612 Gating Mode config
7226 13:59:17.997917 ==============================================================
7227 13:59:17.998037 Config description:
7228 13:59:18.007829 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7229 13:59:18.014466 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7230 13:59:18.021112 SELPH_MODE 0: By rank 1: By Phase
7231 13:59:18.024113 ==============================================================
7232 13:59:18.027886 GAT_TRACK_EN = 1
7233 13:59:18.031115 RX_GATING_MODE = 2
7234 13:59:18.034142 RX_GATING_TRACK_MODE = 2
7235 13:59:18.037764 SELPH_MODE = 1
7236 13:59:18.040815 PICG_EARLY_EN = 1
7237 13:59:18.044256 VALID_LAT_VALUE = 1
7238 13:59:18.050561 ==============================================================
7239 13:59:18.054297 Enter into Gating configuration >>>>
7240 13:59:18.057266 Exit from Gating configuration <<<<
7241 13:59:18.057366 Enter into DVFS_PRE_config >>>>>
7242 13:59:18.070702 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7243 13:59:18.074239 Exit from DVFS_PRE_config <<<<<
7244 13:59:18.077193 Enter into PICG configuration >>>>
7245 13:59:18.080458 Exit from PICG configuration <<<<
7246 13:59:18.080594 [RX_INPUT] configuration >>>>>
7247 13:59:18.084075 [RX_INPUT] configuration <<<<<
7248 13:59:18.090613 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7249 13:59:18.094366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7250 13:59:18.100728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7251 13:59:18.107361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7252 13:59:18.113641 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7253 13:59:18.120412 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7254 13:59:18.123680 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7255 13:59:18.127600 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7256 13:59:18.134464 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7257 13:59:18.137759 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7258 13:59:18.140965 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7259 13:59:18.143931 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7260 13:59:18.147952 ===================================
7261 13:59:18.150703 LPDDR4 DRAM CONFIGURATION
7262 13:59:18.154558 ===================================
7263 13:59:18.157876 EX_ROW_EN[0] = 0x0
7264 13:59:18.158437 EX_ROW_EN[1] = 0x0
7265 13:59:18.160800 LP4Y_EN = 0x0
7266 13:59:18.161262 WORK_FSP = 0x1
7267 13:59:18.164077 WL = 0x5
7268 13:59:18.164563 RL = 0x5
7269 13:59:18.167275 BL = 0x2
7270 13:59:18.167828 RPST = 0x0
7271 13:59:18.170615 RD_PRE = 0x0
7272 13:59:18.171084 WR_PRE = 0x1
7273 13:59:18.173764 WR_PST = 0x1
7274 13:59:18.177259 DBI_WR = 0x0
7275 13:59:18.177726 DBI_RD = 0x0
7276 13:59:18.181099 OTF = 0x1
7277 13:59:18.183981 ===================================
7278 13:59:18.187263 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7279 13:59:18.190651 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7280 13:59:18.193983 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7281 13:59:18.197198 ===================================
7282 13:59:18.200648 LPDDR4 DRAM CONFIGURATION
7283 13:59:18.204364 ===================================
7284 13:59:18.207200 EX_ROW_EN[0] = 0x10
7285 13:59:18.207713 EX_ROW_EN[1] = 0x0
7286 13:59:18.210875 LP4Y_EN = 0x0
7287 13:59:18.211447 WORK_FSP = 0x1
7288 13:59:18.214193 WL = 0x5
7289 13:59:18.214660 RL = 0x5
7290 13:59:18.217588 BL = 0x2
7291 13:59:18.218174 RPST = 0x0
7292 13:59:18.220854 RD_PRE = 0x0
7293 13:59:18.221320 WR_PRE = 0x1
7294 13:59:18.223618 WR_PST = 0x1
7295 13:59:18.224083 DBI_WR = 0x0
7296 13:59:18.227261 DBI_RD = 0x0
7297 13:59:18.227810 OTF = 0x1
7298 13:59:18.230818 ===================================
7299 13:59:18.237271 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7300 13:59:18.237832 ==
7301 13:59:18.240594 Dram Type= 6, Freq= 0, CH_0, rank 0
7302 13:59:18.247124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7303 13:59:18.247745 ==
7304 13:59:18.248124 [Duty_Offset_Calibration]
7305 13:59:18.250373 B0:2 B1:0 CA:3
7306 13:59:18.250943
7307 13:59:18.253797 [DutyScan_Calibration_Flow] k_type=0
7308 13:59:18.263642
7309 13:59:18.264201 ==CLK 0==
7310 13:59:18.266661 Final CLK duty delay cell = 0
7311 13:59:18.270718 [0] MAX Duty = 5031%(X100), DQS PI = 12
7312 13:59:18.273121 [0] MIN Duty = 4907%(X100), DQS PI = 6
7313 13:59:18.273599 [0] AVG Duty = 4969%(X100)
7314 13:59:18.276537
7315 13:59:18.277000 CH0 CLK Duty spec in!! Max-Min= 124%
7316 13:59:18.283020 [DutyScan_Calibration_Flow] ====Done====
7317 13:59:18.283633
7318 13:59:18.286072 [DutyScan_Calibration_Flow] k_type=1
7319 13:59:18.302941
7320 13:59:18.303553 ==DQS 0 ==
7321 13:59:18.306587 Final DQS duty delay cell = 0
7322 13:59:18.309739 [0] MAX Duty = 5125%(X100), DQS PI = 30
7323 13:59:18.313107 [0] MIN Duty = 4875%(X100), DQS PI = 52
7324 13:59:18.316086 [0] AVG Duty = 5000%(X100)
7325 13:59:18.316602
7326 13:59:18.316967 ==DQS 1 ==
7327 13:59:18.319772 Final DQS duty delay cell = 0
7328 13:59:18.322788 [0] MAX Duty = 5156%(X100), DQS PI = 32
7329 13:59:18.326537 [0] MIN Duty = 5031%(X100), DQS PI = 14
7330 13:59:18.329549 [0] AVG Duty = 5093%(X100)
7331 13:59:18.330046
7332 13:59:18.333704 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7333 13:59:18.334271
7334 13:59:18.336127 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7335 13:59:18.339262 [DutyScan_Calibration_Flow] ====Done====
7336 13:59:18.339814
7337 13:59:18.343311 [DutyScan_Calibration_Flow] k_type=3
7338 13:59:18.361186
7339 13:59:18.361745 ==DQM 0 ==
7340 13:59:18.364565 Final DQM duty delay cell = 0
7341 13:59:18.368173 [0] MAX Duty = 5156%(X100), DQS PI = 28
7342 13:59:18.371539 [0] MIN Duty = 4875%(X100), DQS PI = 0
7343 13:59:18.372109 [0] AVG Duty = 5015%(X100)
7344 13:59:18.374301
7345 13:59:18.374763 ==DQM 1 ==
7346 13:59:18.377811 Final DQM duty delay cell = 4
7347 13:59:18.381035 [4] MAX Duty = 5156%(X100), DQS PI = 0
7348 13:59:18.384358 [4] MIN Duty = 5031%(X100), DQS PI = 12
7349 13:59:18.387792 [4] AVG Duty = 5093%(X100)
7350 13:59:18.388252
7351 13:59:18.390776 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7352 13:59:18.391264
7353 13:59:18.393941 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7354 13:59:18.397514 [DutyScan_Calibration_Flow] ====Done====
7355 13:59:18.397974
7356 13:59:18.401006 [DutyScan_Calibration_Flow] k_type=2
7357 13:59:18.417306
7358 13:59:18.417858 ==DQ 0 ==
7359 13:59:18.420494 Final DQ duty delay cell = -4
7360 13:59:18.423987 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7361 13:59:18.427263 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7362 13:59:18.430339 [-4] AVG Duty = 4938%(X100)
7363 13:59:18.430875
7364 13:59:18.431286 ==DQ 1 ==
7365 13:59:18.433867 Final DQ duty delay cell = 0
7366 13:59:18.436947 [0] MAX Duty = 5156%(X100), DQS PI = 58
7367 13:59:18.440623 [0] MIN Duty = 5000%(X100), DQS PI = 16
7368 13:59:18.443990 [0] AVG Duty = 5078%(X100)
7369 13:59:18.444449
7370 13:59:18.447088 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7371 13:59:18.447585
7372 13:59:18.450845 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7373 13:59:18.454209 [DutyScan_Calibration_Flow] ====Done====
7374 13:59:18.454759 ==
7375 13:59:18.457370 Dram Type= 6, Freq= 0, CH_1, rank 0
7376 13:59:18.461047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7377 13:59:18.461603 ==
7378 13:59:18.464126 [Duty_Offset_Calibration]
7379 13:59:18.464584 B0:1 B1:-2 CA:0
7380 13:59:18.464946
7381 13:59:18.467178 [DutyScan_Calibration_Flow] k_type=0
7382 13:59:18.477964
7383 13:59:18.478524 ==CLK 0==
7384 13:59:18.481746 Final CLK duty delay cell = 0
7385 13:59:18.484805 [0] MAX Duty = 5062%(X100), DQS PI = 20
7386 13:59:18.488402 [0] MIN Duty = 4813%(X100), DQS PI = 60
7387 13:59:18.491662 [0] AVG Duty = 4937%(X100)
7388 13:59:18.492218
7389 13:59:18.494643 CH1 CLK Duty spec in!! Max-Min= 249%
7390 13:59:18.498214 [DutyScan_Calibration_Flow] ====Done====
7391 13:59:18.498773
7392 13:59:18.500943 [DutyScan_Calibration_Flow] k_type=1
7393 13:59:18.517556
7394 13:59:18.518108 ==DQS 0 ==
7395 13:59:18.520089 Final DQS duty delay cell = -4
7396 13:59:18.523684 [-4] MAX Duty = 4969%(X100), DQS PI = 26
7397 13:59:18.527344 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7398 13:59:18.530333 [-4] AVG Duty = 4906%(X100)
7399 13:59:18.530879
7400 13:59:18.531257 ==DQS 1 ==
7401 13:59:18.534083 Final DQS duty delay cell = 0
7402 13:59:18.536904 [0] MAX Duty = 5093%(X100), DQS PI = 60
7403 13:59:18.539890 [0] MIN Duty = 4844%(X100), DQS PI = 24
7404 13:59:18.543539 [0] AVG Duty = 4968%(X100)
7405 13:59:18.544122
7406 13:59:18.546548 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7407 13:59:18.547102
7408 13:59:18.550248 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7409 13:59:18.553488 [DutyScan_Calibration_Flow] ====Done====
7410 13:59:18.554060
7411 13:59:18.556660 [DutyScan_Calibration_Flow] k_type=3
7412 13:59:18.574046
7413 13:59:18.574607 ==DQM 0 ==
7414 13:59:18.577283 Final DQM duty delay cell = 0
7415 13:59:18.581069 [0] MAX Duty = 5031%(X100), DQS PI = 24
7416 13:59:18.584346 [0] MIN Duty = 4813%(X100), DQS PI = 56
7417 13:59:18.588112 [0] AVG Duty = 4922%(X100)
7418 13:59:18.588676
7419 13:59:18.589043 ==DQM 1 ==
7420 13:59:18.590644 Final DQM duty delay cell = 0
7421 13:59:18.594415 [0] MAX Duty = 5062%(X100), DQS PI = 34
7422 13:59:18.597084 [0] MIN Duty = 4875%(X100), DQS PI = 26
7423 13:59:18.601001 [0] AVG Duty = 4968%(X100)
7424 13:59:18.601558
7425 13:59:18.604020 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7426 13:59:18.604550
7427 13:59:18.607046 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7428 13:59:18.610608 [DutyScan_Calibration_Flow] ====Done====
7429 13:59:18.611186
7430 13:59:18.614040 [DutyScan_Calibration_Flow] k_type=2
7431 13:59:18.631050
7432 13:59:18.631661 ==DQ 0 ==
7433 13:59:18.634500 Final DQ duty delay cell = 0
7434 13:59:18.637891 [0] MAX Duty = 5093%(X100), DQS PI = 22
7435 13:59:18.641233 [0] MIN Duty = 4907%(X100), DQS PI = 62
7436 13:59:18.641781 [0] AVG Duty = 5000%(X100)
7437 13:59:18.644680
7438 13:59:18.645141 ==DQ 1 ==
7439 13:59:18.647649 Final DQ duty delay cell = 0
7440 13:59:18.651238 [0] MAX Duty = 5125%(X100), DQS PI = 34
7441 13:59:18.654146 [0] MIN Duty = 4969%(X100), DQS PI = 24
7442 13:59:18.654703 [0] AVG Duty = 5047%(X100)
7443 13:59:18.657588
7444 13:59:18.658146 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7445 13:59:18.661041
7446 13:59:18.664242 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7447 13:59:18.667472 [DutyScan_Calibration_Flow] ====Done====
7448 13:59:18.671081 nWR fixed to 30
7449 13:59:18.671790 [ModeRegInit_LP4] CH0 RK0
7450 13:59:18.674090 [ModeRegInit_LP4] CH0 RK1
7451 13:59:18.677691 [ModeRegInit_LP4] CH1 RK0
7452 13:59:18.680975 [ModeRegInit_LP4] CH1 RK1
7453 13:59:18.681431 match AC timing 5
7454 13:59:18.684393 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7455 13:59:18.691011 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7456 13:59:18.694465 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7457 13:59:18.701027 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7458 13:59:18.704337 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7459 13:59:18.704919 [MiockJmeterHQA]
7460 13:59:18.705288
7461 13:59:18.707593 [DramcMiockJmeter] u1RxGatingPI = 0
7462 13:59:18.710716 0 : 4252, 4027
7463 13:59:18.711231 4 : 4253, 4027
7464 13:59:18.711733 8 : 4252, 4027
7465 13:59:18.714261 12 : 4257, 4030
7466 13:59:18.714824 16 : 4257, 4029
7467 13:59:18.717439 20 : 4257, 4029
7468 13:59:18.717903 24 : 4253, 4026
7469 13:59:18.720633 28 : 4252, 4027
7470 13:59:18.721150 32 : 4252, 4027
7471 13:59:18.723796 36 : 4255, 4029
7472 13:59:18.724264 40 : 4252, 4027
7473 13:59:18.724636 44 : 4363, 4137
7474 13:59:18.727499 48 : 4363, 4137
7475 13:59:18.728072 52 : 4252, 4027
7476 13:59:18.730555 56 : 4253, 4026
7477 13:59:18.731021 60 : 4252, 4027
7478 13:59:18.733727 64 : 4252, 4030
7479 13:59:18.734200 68 : 4255, 4029
7480 13:59:18.737311 72 : 4360, 4137
7481 13:59:18.737886 76 : 4250, 4026
7482 13:59:18.738259 80 : 4250, 4027
7483 13:59:18.740767 84 : 4250, 4027
7484 13:59:18.741238 88 : 4253, 4029
7485 13:59:18.744203 92 : 4249, 4027
7486 13:59:18.744673 96 : 4360, 4137
7487 13:59:18.747423 100 : 4360, 4138
7488 13:59:18.748003 104 : 4250, 3867
7489 13:59:18.750670 108 : 4249, 6
7490 13:59:18.751250 112 : 4250, 0
7491 13:59:18.751808 116 : 4250, 0
7492 13:59:18.753767 120 : 4250, 0
7493 13:59:18.754234 124 : 4250, 0
7494 13:59:18.757135 128 : 4253, 0
7495 13:59:18.757724 132 : 4360, 0
7496 13:59:18.758105 136 : 4250, 0
7497 13:59:18.760193 140 : 4250, 0
7498 13:59:18.760659 144 : 4250, 0
7499 13:59:18.761027 148 : 4360, 0
7500 13:59:18.763585 152 : 4250, 0
7501 13:59:18.764054 156 : 4253, 0
7502 13:59:18.767065 160 : 4253, 0
7503 13:59:18.767577 164 : 4361, 0
7504 13:59:18.767954 168 : 4250, 0
7505 13:59:18.770566 172 : 4252, 0
7506 13:59:18.771135 176 : 4250, 0
7507 13:59:18.774395 180 : 4250, 0
7508 13:59:18.775013 184 : 4362, 0
7509 13:59:18.775454 188 : 4252, 0
7510 13:59:18.777059 192 : 4250, 0
7511 13:59:18.777547 196 : 4250, 0
7512 13:59:18.780551 200 : 4363, 0
7513 13:59:18.781017 204 : 4250, 0
7514 13:59:18.781492 208 : 4250, 0
7515 13:59:18.783579 212 : 4250, 0
7516 13:59:18.784163 216 : 4361, 0
7517 13:59:18.784540 220 : 4250, 0
7518 13:59:18.786761 224 : 4250, 0
7519 13:59:18.787226 228 : 4250, 0
7520 13:59:18.790784 232 : 4250, 0
7521 13:59:18.791351 236 : 4363, 880
7522 13:59:18.793782 240 : 4361, 4137
7523 13:59:18.794351 244 : 4250, 4027
7524 13:59:18.794720 248 : 4250, 4027
7525 13:59:18.797865 252 : 4250, 4026
7526 13:59:18.798457 256 : 4253, 4029
7527 13:59:18.800081 260 : 4250, 4027
7528 13:59:18.800549 264 : 4249, 4027
7529 13:59:18.803454 268 : 4360, 4137
7530 13:59:18.803926 272 : 4250, 4027
7531 13:59:18.807248 276 : 4250, 4027
7532 13:59:18.807862 280 : 4360, 4138
7533 13:59:18.810345 284 : 4250, 4027
7534 13:59:18.810811 288 : 4250, 4026
7535 13:59:18.813728 292 : 4363, 4140
7536 13:59:18.814302 296 : 4250, 4027
7537 13:59:18.816869 300 : 4249, 4027
7538 13:59:18.817339 304 : 4253, 4026
7539 13:59:18.817706 308 : 4253, 4029
7540 13:59:18.819904 312 : 4250, 4027
7541 13:59:18.820371 316 : 4249, 4027
7542 13:59:18.823896 320 : 4360, 4137
7543 13:59:18.824362 324 : 4250, 4026
7544 13:59:18.826761 328 : 4250, 4027
7545 13:59:18.827228 332 : 4360, 4138
7546 13:59:18.830366 336 : 4249, 4027
7547 13:59:18.830928 340 : 4250, 4026
7548 13:59:18.833575 344 : 4363, 4140
7549 13:59:18.834143 348 : 4250, 4027
7550 13:59:18.836459 352 : 4249, 4022
7551 13:59:18.836925 356 : 4250, 3032
7552 13:59:18.839868 360 : 4253, 18
7553 13:59:18.840418
7554 13:59:18.840789 MIOCK jitter meter ch=0
7555 13:59:18.841132
7556 13:59:18.843446 1T = (360-108) = 252 dly cells
7557 13:59:18.849745 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7558 13:59:18.850305 ==
7559 13:59:18.853427 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 13:59:18.856289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 13:59:18.856764 ==
7562 13:59:18.862823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7563 13:59:18.866579 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7564 13:59:18.869778 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7565 13:59:18.876168 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7566 13:59:18.886497 [CA 0] Center 43 (13~74) winsize 62
7567 13:59:18.889417 [CA 1] Center 43 (13~74) winsize 62
7568 13:59:18.892455 [CA 2] Center 39 (10~68) winsize 59
7569 13:59:18.896039 [CA 3] Center 39 (10~68) winsize 59
7570 13:59:18.899093 [CA 4] Center 36 (7~66) winsize 60
7571 13:59:18.902629 [CA 5] Center 36 (7~66) winsize 60
7572 13:59:18.903142
7573 13:59:18.906251 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7574 13:59:18.906854
7575 13:59:18.909559 [CATrainingPosCal] consider 1 rank data
7576 13:59:18.912810 u2DelayCellTimex100 = 258/100 ps
7577 13:59:18.916124 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7578 13:59:18.923002 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7579 13:59:18.925693 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7580 13:59:18.929162 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7581 13:59:18.932475 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7582 13:59:18.935821 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7583 13:59:18.936284
7584 13:59:18.939230 CA PerBit enable=1, Macro0, CA PI delay=36
7585 13:59:18.939726
7586 13:59:18.942231 [CBTSetCACLKResult] CA Dly = 36
7587 13:59:18.945455 CS Dly: 11 (0~42)
7588 13:59:18.949226 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7589 13:59:18.952258 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7590 13:59:18.952723 ==
7591 13:59:18.955783 Dram Type= 6, Freq= 0, CH_0, rank 1
7592 13:59:18.962232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 13:59:18.962841 ==
7594 13:59:18.965820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7595 13:59:18.969117 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7596 13:59:18.975616 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7597 13:59:18.982241 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7598 13:59:18.989961 [CA 0] Center 44 (14~75) winsize 62
7599 13:59:18.993092 [CA 1] Center 43 (13~74) winsize 62
7600 13:59:18.996687 [CA 2] Center 39 (10~69) winsize 60
7601 13:59:19.000070 [CA 3] Center 39 (10~69) winsize 60
7602 13:59:19.002998 [CA 4] Center 37 (8~67) winsize 60
7603 13:59:19.007074 [CA 5] Center 37 (7~67) winsize 61
7604 13:59:19.007766
7605 13:59:19.009903 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7606 13:59:19.010460
7607 13:59:19.016603 [CATrainingPosCal] consider 2 rank data
7608 13:59:19.017164 u2DelayCellTimex100 = 258/100 ps
7609 13:59:19.023074 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7610 13:59:19.026551 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7611 13:59:19.030071 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7612 13:59:19.032826 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7613 13:59:19.036424 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7614 13:59:19.040227 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7615 13:59:19.040793
7616 13:59:19.043534 CA PerBit enable=1, Macro0, CA PI delay=36
7617 13:59:19.044094
7618 13:59:19.046552 [CBTSetCACLKResult] CA Dly = 36
7619 13:59:19.050171 CS Dly: 11 (0~43)
7620 13:59:19.052855 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7621 13:59:19.056441 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7622 13:59:19.057040
7623 13:59:19.059871 ----->DramcWriteLeveling(PI) begin...
7624 13:59:19.060435 ==
7625 13:59:19.062702 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 13:59:19.069941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 13:59:19.070571 ==
7628 13:59:19.072747 Write leveling (Byte 0): 35 => 35
7629 13:59:19.076146 Write leveling (Byte 1): 29 => 29
7630 13:59:19.076607 DramcWriteLeveling(PI) end<-----
7631 13:59:19.079664
7632 13:59:19.080343 ==
7633 13:59:19.082601 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 13:59:19.086512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 13:59:19.087079 ==
7636 13:59:19.089746 [Gating] SW mode calibration
7637 13:59:19.096111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7638 13:59:19.099465 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7639 13:59:19.106152 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 13:59:19.109741 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 13:59:19.112274 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 13:59:19.119359 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 13:59:19.122905 1 4 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7644 13:59:19.126375 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
7645 13:59:19.132187 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 13:59:19.135881 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7647 13:59:19.139281 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7648 13:59:19.145803 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7649 13:59:19.148828 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7650 13:59:19.152285 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7651 13:59:19.159263 1 5 16 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
7652 13:59:19.162190 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7653 13:59:19.165596 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7654 13:59:19.172588 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7655 13:59:19.175735 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 13:59:19.179164 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 13:59:19.185271 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 13:59:19.188574 1 6 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7659 13:59:19.192685 1 6 16 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7660 13:59:19.198954 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7661 13:59:19.201979 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 13:59:19.205586 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 13:59:19.212412 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 13:59:19.215055 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 13:59:19.218932 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 13:59:19.225218 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7667 13:59:19.228632 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7668 13:59:19.231729 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7669 13:59:19.238622 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7670 13:59:19.242042 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 13:59:19.245374 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 13:59:19.251622 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 13:59:19.254883 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 13:59:19.258197 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 13:59:19.265038 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 13:59:19.268840 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 13:59:19.271324 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 13:59:19.274610 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 13:59:19.281459 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 13:59:19.285144 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 13:59:19.288157 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 13:59:19.295192 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7683 13:59:19.298572 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7684 13:59:19.301814 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7685 13:59:19.305035 Total UI for P1: 0, mck2ui 16
7686 13:59:19.308326 best dqsien dly found for B0: ( 1, 9, 14)
7687 13:59:19.314563 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7688 13:59:19.318176 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 13:59:19.321516 Total UI for P1: 0, mck2ui 16
7690 13:59:19.324525 best dqsien dly found for B1: ( 1, 9, 22)
7691 13:59:19.328011 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7692 13:59:19.330965 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7693 13:59:19.331476
7694 13:59:19.334655 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7695 13:59:19.341260 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7696 13:59:19.341834 [Gating] SW calibration Done
7697 13:59:19.342212 ==
7698 13:59:19.344647 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 13:59:19.350973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 13:59:19.351494 ==
7701 13:59:19.351877 RX Vref Scan: 0
7702 13:59:19.352221
7703 13:59:19.354222 RX Vref 0 -> 0, step: 1
7704 13:59:19.354688
7705 13:59:19.357826 RX Delay 0 -> 252, step: 8
7706 13:59:19.361419 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7707 13:59:19.364266 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7708 13:59:19.367479 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7709 13:59:19.374360 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7710 13:59:19.377250 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7711 13:59:19.380411 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7712 13:59:19.384147 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7713 13:59:19.387429 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7714 13:59:19.394212 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7715 13:59:19.397449 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7716 13:59:19.400595 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7717 13:59:19.403933 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7718 13:59:19.407107 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7719 13:59:19.413582 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7720 13:59:19.417525 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7721 13:59:19.420364 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7722 13:59:19.420836 ==
7723 13:59:19.423707 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 13:59:19.427249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 13:59:19.427859 ==
7726 13:59:19.430889 DQS Delay:
7727 13:59:19.431505 DQS0 = 0, DQS1 = 0
7728 13:59:19.433809 DQM Delay:
7729 13:59:19.434274 DQM0 = 128, DQM1 = 124
7730 13:59:19.437129 DQ Delay:
7731 13:59:19.440775 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7732 13:59:19.443559 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7733 13:59:19.447013 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7734 13:59:19.450422 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7735 13:59:19.450987
7736 13:59:19.451354
7737 13:59:19.451767 ==
7738 13:59:19.454293 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 13:59:19.457391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 13:59:19.457959 ==
7741 13:59:19.458332
7742 13:59:19.458675
7743 13:59:19.460768 TX Vref Scan disable
7744 13:59:19.464007 == TX Byte 0 ==
7745 13:59:19.466939 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7746 13:59:19.470263 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7747 13:59:19.473700 == TX Byte 1 ==
7748 13:59:19.477092 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7749 13:59:19.480296 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7750 13:59:19.480869 ==
7751 13:59:19.484051 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 13:59:19.487128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 13:59:19.490289 ==
7754 13:59:19.502613
7755 13:59:19.505694 TX Vref early break, caculate TX vref
7756 13:59:19.508870 TX Vref=16, minBit 11, minWin=21, winSum=363
7757 13:59:19.512205 TX Vref=18, minBit 8, minWin=22, winSum=369
7758 13:59:19.515504 TX Vref=20, minBit 8, minWin=22, winSum=377
7759 13:59:19.519096 TX Vref=22, minBit 8, minWin=23, winSum=387
7760 13:59:19.521931 TX Vref=24, minBit 4, minWin=24, winSum=401
7761 13:59:19.528912 TX Vref=26, minBit 4, minWin=24, winSum=408
7762 13:59:19.532053 TX Vref=28, minBit 2, minWin=25, winSum=409
7763 13:59:19.535510 TX Vref=30, minBit 8, minWin=24, winSum=408
7764 13:59:19.538967 TX Vref=32, minBit 11, minWin=23, winSum=392
7765 13:59:19.542385 TX Vref=34, minBit 8, minWin=23, winSum=385
7766 13:59:19.548623 [TxChooseVref] Worse bit 2, Min win 25, Win sum 409, Final Vref 28
7767 13:59:19.549187
7768 13:59:19.551999 Final TX Range 0 Vref 28
7769 13:59:19.552486
7770 13:59:19.552854 ==
7771 13:59:19.555717 Dram Type= 6, Freq= 0, CH_0, rank 0
7772 13:59:19.558999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7773 13:59:19.559597 ==
7774 13:59:19.559969
7775 13:59:19.560307
7776 13:59:19.562134 TX Vref Scan disable
7777 13:59:19.569093 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7778 13:59:19.569656 == TX Byte 0 ==
7779 13:59:19.572201 u2DelayCellOfst[0]=15 cells (4 PI)
7780 13:59:19.575453 u2DelayCellOfst[1]=18 cells (5 PI)
7781 13:59:19.578468 u2DelayCellOfst[2]=15 cells (4 PI)
7782 13:59:19.582244 u2DelayCellOfst[3]=15 cells (4 PI)
7783 13:59:19.585504 u2DelayCellOfst[4]=11 cells (3 PI)
7784 13:59:19.588673 u2DelayCellOfst[5]=0 cells (0 PI)
7785 13:59:19.592070 u2DelayCellOfst[6]=22 cells (6 PI)
7786 13:59:19.596007 u2DelayCellOfst[7]=18 cells (5 PI)
7787 13:59:19.598587 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7788 13:59:19.602150 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7789 13:59:19.605261 == TX Byte 1 ==
7790 13:59:19.605819 u2DelayCellOfst[8]=0 cells (0 PI)
7791 13:59:19.608626 u2DelayCellOfst[9]=3 cells (1 PI)
7792 13:59:19.612039 u2DelayCellOfst[10]=7 cells (2 PI)
7793 13:59:19.614980 u2DelayCellOfst[11]=7 cells (2 PI)
7794 13:59:19.618799 u2DelayCellOfst[12]=15 cells (4 PI)
7795 13:59:19.622050 u2DelayCellOfst[13]=15 cells (4 PI)
7796 13:59:19.624928 u2DelayCellOfst[14]=15 cells (4 PI)
7797 13:59:19.628338 u2DelayCellOfst[15]=11 cells (3 PI)
7798 13:59:19.631952 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7799 13:59:19.638236 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7800 13:59:19.638699 DramC Write-DBI on
7801 13:59:19.639063 ==
7802 13:59:19.642037 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 13:59:19.644825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 13:59:19.648210 ==
7805 13:59:19.648673
7806 13:59:19.649038
7807 13:59:19.649377 TX Vref Scan disable
7808 13:59:19.651635 == TX Byte 0 ==
7809 13:59:19.655164 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7810 13:59:19.658781 == TX Byte 1 ==
7811 13:59:19.662013 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7812 13:59:19.665422 DramC Write-DBI off
7813 13:59:19.665905
7814 13:59:19.666338 [DATLAT]
7815 13:59:19.666688 Freq=1600, CH0 RK0
7816 13:59:19.667017
7817 13:59:19.668560 DATLAT Default: 0xf
7818 13:59:19.669016 0, 0xFFFF, sum = 0
7819 13:59:19.672520 1, 0xFFFF, sum = 0
7820 13:59:19.675091 2, 0xFFFF, sum = 0
7821 13:59:19.675587 3, 0xFFFF, sum = 0
7822 13:59:19.678570 4, 0xFFFF, sum = 0
7823 13:59:19.679036 5, 0xFFFF, sum = 0
7824 13:59:19.682204 6, 0xFFFF, sum = 0
7825 13:59:19.682770 7, 0xFFFF, sum = 0
7826 13:59:19.685251 8, 0xFFFF, sum = 0
7827 13:59:19.685718 9, 0xFFFF, sum = 0
7828 13:59:19.688854 10, 0xFFFF, sum = 0
7829 13:59:19.689423 11, 0xFFFF, sum = 0
7830 13:59:19.692049 12, 0xFFFF, sum = 0
7831 13:59:19.692516 13, 0xFFFF, sum = 0
7832 13:59:19.695755 14, 0x0, sum = 1
7833 13:59:19.696319 15, 0x0, sum = 2
7834 13:59:19.698588 16, 0x0, sum = 3
7835 13:59:19.699154 17, 0x0, sum = 4
7836 13:59:19.702210 best_step = 15
7837 13:59:19.702781
7838 13:59:19.703146 ==
7839 13:59:19.705256 Dram Type= 6, Freq= 0, CH_0, rank 0
7840 13:59:19.708647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7841 13:59:19.709211 ==
7842 13:59:19.709579 RX Vref Scan: 1
7843 13:59:19.711842
7844 13:59:19.712304 Set Vref Range= 24 -> 127
7845 13:59:19.712671
7846 13:59:19.715289 RX Vref 24 -> 127, step: 1
7847 13:59:19.715799
7848 13:59:19.718402 RX Delay 11 -> 252, step: 4
7849 13:59:19.718957
7850 13:59:19.722399 Set Vref, RX VrefLevel [Byte0]: 24
7851 13:59:19.725044 [Byte1]: 24
7852 13:59:19.725606
7853 13:59:19.728749 Set Vref, RX VrefLevel [Byte0]: 25
7854 13:59:19.731780 [Byte1]: 25
7855 13:59:19.732335
7856 13:59:19.734896 Set Vref, RX VrefLevel [Byte0]: 26
7857 13:59:19.738419 [Byte1]: 26
7858 13:59:19.743005
7859 13:59:19.743615 Set Vref, RX VrefLevel [Byte0]: 27
7860 13:59:19.745718 [Byte1]: 27
7861 13:59:19.749953
7862 13:59:19.750507 Set Vref, RX VrefLevel [Byte0]: 28
7863 13:59:19.753212 [Byte1]: 28
7864 13:59:19.757487
7865 13:59:19.758044 Set Vref, RX VrefLevel [Byte0]: 29
7866 13:59:19.761227 [Byte1]: 29
7867 13:59:19.765072
7868 13:59:19.765549 Set Vref, RX VrefLevel [Byte0]: 30
7869 13:59:19.768669 [Byte1]: 30
7870 13:59:19.772960
7871 13:59:19.773517 Set Vref, RX VrefLevel [Byte0]: 31
7872 13:59:19.776086 [Byte1]: 31
7873 13:59:19.780192
7874 13:59:19.780657 Set Vref, RX VrefLevel [Byte0]: 32
7875 13:59:19.783705 [Byte1]: 32
7876 13:59:19.787880
7877 13:59:19.788335 Set Vref, RX VrefLevel [Byte0]: 33
7878 13:59:19.791867 [Byte1]: 33
7879 13:59:19.795855
7880 13:59:19.796412 Set Vref, RX VrefLevel [Byte0]: 34
7881 13:59:19.798947 [Byte1]: 34
7882 13:59:19.803482
7883 13:59:19.804035 Set Vref, RX VrefLevel [Byte0]: 35
7884 13:59:19.806454 [Byte1]: 35
7885 13:59:19.810816
7886 13:59:19.811375 Set Vref, RX VrefLevel [Byte0]: 36
7887 13:59:19.813949 [Byte1]: 36
7888 13:59:19.818457
7889 13:59:19.819011 Set Vref, RX VrefLevel [Byte0]: 37
7890 13:59:19.821874 [Byte1]: 37
7891 13:59:19.826040
7892 13:59:19.826622 Set Vref, RX VrefLevel [Byte0]: 38
7893 13:59:19.829429 [Byte1]: 38
7894 13:59:19.833663
7895 13:59:19.834226 Set Vref, RX VrefLevel [Byte0]: 39
7896 13:59:19.836807 [Byte1]: 39
7897 13:59:19.841796
7898 13:59:19.842353 Set Vref, RX VrefLevel [Byte0]: 40
7899 13:59:19.844688 [Byte1]: 40
7900 13:59:19.849015
7901 13:59:19.849574 Set Vref, RX VrefLevel [Byte0]: 41
7902 13:59:19.852630 [Byte1]: 41
7903 13:59:19.856221
7904 13:59:19.856683 Set Vref, RX VrefLevel [Byte0]: 42
7905 13:59:19.859687 [Byte1]: 42
7906 13:59:19.864138
7907 13:59:19.864693 Set Vref, RX VrefLevel [Byte0]: 43
7908 13:59:19.867488 [Byte1]: 43
7909 13:59:19.871942
7910 13:59:19.872405 Set Vref, RX VrefLevel [Byte0]: 44
7911 13:59:19.875162 [Byte1]: 44
7912 13:59:19.879272
7913 13:59:19.879813 Set Vref, RX VrefLevel [Byte0]: 45
7914 13:59:19.882249 [Byte1]: 45
7915 13:59:19.886876
7916 13:59:19.887458 Set Vref, RX VrefLevel [Byte0]: 46
7917 13:59:19.889965 [Byte1]: 46
7918 13:59:19.894965
7919 13:59:19.895542 Set Vref, RX VrefLevel [Byte0]: 47
7920 13:59:19.897739 [Byte1]: 47
7921 13:59:19.902058
7922 13:59:19.902519 Set Vref, RX VrefLevel [Byte0]: 48
7923 13:59:19.905178 [Byte1]: 48
7924 13:59:19.909733
7925 13:59:19.910199 Set Vref, RX VrefLevel [Byte0]: 49
7926 13:59:19.913147 [Byte1]: 49
7927 13:59:19.917379
7928 13:59:19.917840 Set Vref, RX VrefLevel [Byte0]: 50
7929 13:59:19.920929 [Byte1]: 50
7930 13:59:19.925283
7931 13:59:19.925745 Set Vref, RX VrefLevel [Byte0]: 51
7932 13:59:19.928635 [Byte1]: 51
7933 13:59:19.932792
7934 13:59:19.933349 Set Vref, RX VrefLevel [Byte0]: 52
7935 13:59:19.936016 [Byte1]: 52
7936 13:59:19.940073
7937 13:59:19.940628 Set Vref, RX VrefLevel [Byte0]: 53
7938 13:59:19.943320 [Byte1]: 53
7939 13:59:19.948122
7940 13:59:19.948840 Set Vref, RX VrefLevel [Byte0]: 54
7941 13:59:19.951484 [Byte1]: 54
7942 13:59:19.955223
7943 13:59:19.955738 Set Vref, RX VrefLevel [Byte0]: 55
7944 13:59:19.958923 [Byte1]: 55
7945 13:59:19.963189
7946 13:59:19.963800 Set Vref, RX VrefLevel [Byte0]: 56
7947 13:59:19.966620 [Byte1]: 56
7948 13:59:19.970855
7949 13:59:19.971465 Set Vref, RX VrefLevel [Byte0]: 57
7950 13:59:19.973926 [Byte1]: 57
7951 13:59:19.978173
7952 13:59:19.978636 Set Vref, RX VrefLevel [Byte0]: 58
7953 13:59:19.981505 [Byte1]: 58
7954 13:59:19.986306
7955 13:59:19.986874 Set Vref, RX VrefLevel [Byte0]: 59
7956 13:59:19.989304 [Byte1]: 59
7957 13:59:19.993906
7958 13:59:19.994495 Set Vref, RX VrefLevel [Byte0]: 60
7959 13:59:19.996977 [Byte1]: 60
7960 13:59:20.000790
7961 13:59:20.001247 Set Vref, RX VrefLevel [Byte0]: 61
7962 13:59:20.004267 [Byte1]: 61
7963 13:59:20.008902
7964 13:59:20.009472 Set Vref, RX VrefLevel [Byte0]: 62
7965 13:59:20.012088 [Byte1]: 62
7966 13:59:20.016238
7967 13:59:20.016750 Set Vref, RX VrefLevel [Byte0]: 63
7968 13:59:20.019775 [Byte1]: 63
7969 13:59:20.024075
7970 13:59:20.024632 Set Vref, RX VrefLevel [Byte0]: 64
7971 13:59:20.027198 [Byte1]: 64
7972 13:59:20.031756
7973 13:59:20.032215 Set Vref, RX VrefLevel [Byte0]: 65
7974 13:59:20.035275 [Byte1]: 65
7975 13:59:20.039514
7976 13:59:20.039977 Set Vref, RX VrefLevel [Byte0]: 66
7977 13:59:20.042534 [Byte1]: 66
7978 13:59:20.046809
7979 13:59:20.047368 Set Vref, RX VrefLevel [Byte0]: 67
7980 13:59:20.050768 [Byte1]: 67
7981 13:59:20.054760
7982 13:59:20.055319 Set Vref, RX VrefLevel [Byte0]: 68
7983 13:59:20.058089 [Byte1]: 68
7984 13:59:20.062029
7985 13:59:20.062589 Set Vref, RX VrefLevel [Byte0]: 69
7986 13:59:20.065157 [Byte1]: 69
7987 13:59:20.069937
7988 13:59:20.070491 Set Vref, RX VrefLevel [Byte0]: 70
7989 13:59:20.073040 [Byte1]: 70
7990 13:59:20.076943
7991 13:59:20.077403 Set Vref, RX VrefLevel [Byte0]: 71
7992 13:59:20.080613 [Byte1]: 71
7993 13:59:20.085537
7994 13:59:20.086100 Set Vref, RX VrefLevel [Byte0]: 72
7995 13:59:20.088771 [Byte1]: 72
7996 13:59:20.092409
7997 13:59:20.092963 Set Vref, RX VrefLevel [Byte0]: 73
7998 13:59:20.095890 [Byte1]: 73
7999 13:59:20.100405
8000 13:59:20.100959 Set Vref, RX VrefLevel [Byte0]: 74
8001 13:59:20.103807 [Byte1]: 74
8002 13:59:20.108043
8003 13:59:20.108599 Set Vref, RX VrefLevel [Byte0]: 75
8004 13:59:20.111531 [Byte1]: 75
8005 13:59:20.115499
8006 13:59:20.115964 Set Vref, RX VrefLevel [Byte0]: 76
8007 13:59:20.118874 [Byte1]: 76
8008 13:59:20.122977
8009 13:59:20.123636 Final RX Vref Byte 0 = 65 to rank0
8010 13:59:20.126312 Final RX Vref Byte 1 = 60 to rank0
8011 13:59:20.129483 Final RX Vref Byte 0 = 65 to rank1
8012 13:59:20.132802 Final RX Vref Byte 1 = 60 to rank1==
8013 13:59:20.136019 Dram Type= 6, Freq= 0, CH_0, rank 0
8014 13:59:20.142765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 13:59:20.143328 ==
8016 13:59:20.143849 DQS Delay:
8017 13:59:20.146267 DQS0 = 0, DQS1 = 0
8018 13:59:20.146722 DQM Delay:
8019 13:59:20.147082 DQM0 = 126, DQM1 = 120
8020 13:59:20.149320 DQ Delay:
8021 13:59:20.152926 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8022 13:59:20.156288 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8023 13:59:20.158915 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8024 13:59:20.162698 DQ12 =124, DQ13 =124, DQ14 =132, DQ15 =128
8025 13:59:20.163258
8026 13:59:20.163746
8027 13:59:20.164090
8028 13:59:20.165905 [DramC_TX_OE_Calibration] TA2
8029 13:59:20.169461 Original DQ_B0 (3 6) =30, OEN = 27
8030 13:59:20.172229 Original DQ_B1 (3 6) =30, OEN = 27
8031 13:59:20.176324 24, 0x0, End_B0=24 End_B1=24
8032 13:59:20.176891 25, 0x0, End_B0=25 End_B1=25
8033 13:59:20.179522 26, 0x0, End_B0=26 End_B1=26
8034 13:59:20.182743 27, 0x0, End_B0=27 End_B1=27
8035 13:59:20.185962 28, 0x0, End_B0=28 End_B1=28
8036 13:59:20.189243 29, 0x0, End_B0=29 End_B1=29
8037 13:59:20.189810 30, 0x0, End_B0=30 End_B1=30
8038 13:59:20.192687 31, 0x4545, End_B0=30 End_B1=30
8039 13:59:20.195609 Byte0 end_step=30 best_step=27
8040 13:59:20.199079 Byte1 end_step=30 best_step=27
8041 13:59:20.202546 Byte0 TX OE(2T, 0.5T) = (3, 3)
8042 13:59:20.206186 Byte1 TX OE(2T, 0.5T) = (3, 3)
8043 13:59:20.206754
8044 13:59:20.207125
8045 13:59:20.212290 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
8046 13:59:20.216000 CH0 RK0: MR19=303, MR18=1111
8047 13:59:20.222296 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=22, DEC=15
8048 13:59:20.222844
8049 13:59:20.225793 ----->DramcWriteLeveling(PI) begin...
8050 13:59:20.226376 ==
8051 13:59:20.228700 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 13:59:20.232633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 13:59:20.233116 ==
8054 13:59:20.235261 Write leveling (Byte 0): 35 => 35
8055 13:59:20.238589 Write leveling (Byte 1): 27 => 27
8056 13:59:20.241842 DramcWriteLeveling(PI) end<-----
8057 13:59:20.242384
8058 13:59:20.242872 ==
8059 13:59:20.245799 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 13:59:20.248713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 13:59:20.249186 ==
8062 13:59:20.251832 [Gating] SW mode calibration
8063 13:59:20.258716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8064 13:59:20.265183 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8065 13:59:20.268255 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 13:59:20.275074 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 13:59:20.278592 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 13:59:20.281725 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
8069 13:59:20.288168 1 4 16 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8070 13:59:20.291649 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 13:59:20.295033 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 13:59:20.301294 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 13:59:20.304720 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 13:59:20.308196 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 13:59:20.311380 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8076 13:59:20.317950 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8077 13:59:20.321381 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8078 13:59:20.324745 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8079 13:59:20.331116 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 13:59:20.334979 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 13:59:20.338338 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 13:59:20.344825 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 13:59:20.348221 1 6 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8084 13:59:20.351113 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8085 13:59:20.358012 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8086 13:59:20.361351 1 6 20 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8087 13:59:20.364495 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 13:59:20.371168 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 13:59:20.374110 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 13:59:20.378094 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 13:59:20.384577 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 13:59:20.387466 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8093 13:59:20.390806 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8094 13:59:20.397246 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8095 13:59:20.400946 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 13:59:20.403922 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 13:59:20.410668 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 13:59:20.413886 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 13:59:20.417278 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 13:59:20.423953 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 13:59:20.427090 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 13:59:20.430442 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 13:59:20.437119 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 13:59:20.440277 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 13:59:20.443692 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 13:59:20.450635 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8107 13:59:20.453522 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8108 13:59:20.457073 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8109 13:59:20.463751 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8110 13:59:20.463829 Total UI for P1: 0, mck2ui 16
8111 13:59:20.470733 best dqsien dly found for B0: ( 1, 9, 8)
8112 13:59:20.473674 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8113 13:59:20.476935 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8114 13:59:20.480380 Total UI for P1: 0, mck2ui 16
8115 13:59:20.483484 best dqsien dly found for B1: ( 1, 9, 18)
8116 13:59:20.486398 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8117 13:59:20.489820 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8118 13:59:20.489979
8119 13:59:20.493689 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8120 13:59:20.500001 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8121 13:59:20.500189 [Gating] SW calibration Done
8122 13:59:20.503234 ==
8123 13:59:20.503486 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 13:59:20.509697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 13:59:20.510075 ==
8126 13:59:20.510414 RX Vref Scan: 0
8127 13:59:20.510725
8128 13:59:20.513422 RX Vref 0 -> 0, step: 1
8129 13:59:20.513829
8130 13:59:20.516286 RX Delay 0 -> 252, step: 8
8131 13:59:20.520890 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8132 13:59:20.523195 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8133 13:59:20.526838 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8134 13:59:20.533181 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8135 13:59:20.536847 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8136 13:59:20.540037 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8137 13:59:20.543219 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8138 13:59:20.546870 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8139 13:59:20.553068 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8140 13:59:20.556416 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8141 13:59:20.559824 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8142 13:59:20.564240 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8143 13:59:20.567020 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8144 13:59:20.573053 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8145 13:59:20.576576 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8146 13:59:20.579236 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8147 13:59:20.579908 ==
8148 13:59:20.582577 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 13:59:20.589281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 13:59:20.589911 ==
8151 13:59:20.590484 DQS Delay:
8152 13:59:20.591032 DQS0 = 0, DQS1 = 0
8153 13:59:20.592823 DQM Delay:
8154 13:59:20.593301 DQM0 = 127, DQM1 = 121
8155 13:59:20.595856 DQ Delay:
8156 13:59:20.599244 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8157 13:59:20.602995 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8158 13:59:20.606045 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8159 13:59:20.609466 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8160 13:59:20.609959
8161 13:59:20.610322
8162 13:59:20.610687 ==
8163 13:59:20.612404 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 13:59:20.615695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 13:59:20.619769 ==
8166 13:59:20.620256
8167 13:59:20.620624
8168 13:59:20.621183 TX Vref Scan disable
8169 13:59:20.622385 == TX Byte 0 ==
8170 13:59:20.626008 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8171 13:59:20.629635 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8172 13:59:20.632313 == TX Byte 1 ==
8173 13:59:20.636094 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8174 13:59:20.639308 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8175 13:59:20.642332 ==
8176 13:59:20.642754 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 13:59:20.648835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 13:59:20.649265 ==
8179 13:59:20.663068
8180 13:59:20.666327 TX Vref early break, caculate TX vref
8181 13:59:20.669373 TX Vref=16, minBit 8, minWin=21, winSum=369
8182 13:59:20.672820 TX Vref=18, minBit 9, minWin=21, winSum=373
8183 13:59:20.676601 TX Vref=20, minBit 9, minWin=22, winSum=380
8184 13:59:20.679281 TX Vref=22, minBit 11, minWin=23, winSum=394
8185 13:59:20.683092 TX Vref=24, minBit 0, minWin=24, winSum=399
8186 13:59:20.689352 TX Vref=26, minBit 8, minWin=24, winSum=407
8187 13:59:20.693105 TX Vref=28, minBit 8, minWin=24, winSum=410
8188 13:59:20.696217 TX Vref=30, minBit 8, minWin=24, winSum=406
8189 13:59:20.699425 TX Vref=32, minBit 8, minWin=22, winSum=397
8190 13:59:20.702963 TX Vref=34, minBit 8, minWin=22, winSum=390
8191 13:59:20.706236 TX Vref=36, minBit 8, minWin=22, winSum=381
8192 13:59:20.712553 [TxChooseVref] Worse bit 8, Min win 24, Win sum 410, Final Vref 28
8193 13:59:20.712864
8194 13:59:20.715919 Final TX Range 0 Vref 28
8195 13:59:20.716152
8196 13:59:20.716394 ==
8197 13:59:20.719564 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 13:59:20.722678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 13:59:20.722866 ==
8200 13:59:20.723056
8201 13:59:20.726182
8202 13:59:20.726337 TX Vref Scan disable
8203 13:59:20.732366 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8204 13:59:20.732524 == TX Byte 0 ==
8205 13:59:20.735585 u2DelayCellOfst[0]=15 cells (4 PI)
8206 13:59:20.739231 u2DelayCellOfst[1]=18 cells (5 PI)
8207 13:59:20.742043 u2DelayCellOfst[2]=11 cells (3 PI)
8208 13:59:20.745742 u2DelayCellOfst[3]=15 cells (4 PI)
8209 13:59:20.748766 u2DelayCellOfst[4]=7 cells (2 PI)
8210 13:59:20.752508 u2DelayCellOfst[5]=0 cells (0 PI)
8211 13:59:20.755605 u2DelayCellOfst[6]=18 cells (5 PI)
8212 13:59:20.758566 u2DelayCellOfst[7]=18 cells (5 PI)
8213 13:59:20.762331 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8214 13:59:20.765489 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8215 13:59:20.768837 == TX Byte 1 ==
8216 13:59:20.772043 u2DelayCellOfst[8]=0 cells (0 PI)
8217 13:59:20.775889 u2DelayCellOfst[9]=0 cells (0 PI)
8218 13:59:20.778827 u2DelayCellOfst[10]=11 cells (3 PI)
8219 13:59:20.782494 u2DelayCellOfst[11]=3 cells (1 PI)
8220 13:59:20.782656 u2DelayCellOfst[12]=15 cells (4 PI)
8221 13:59:20.785701 u2DelayCellOfst[13]=11 cells (3 PI)
8222 13:59:20.789038 u2DelayCellOfst[14]=15 cells (4 PI)
8223 13:59:20.792703 u2DelayCellOfst[15]=11 cells (3 PI)
8224 13:59:20.798688 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8225 13:59:20.802520 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8226 13:59:20.802709 DramC Write-DBI on
8227 13:59:20.805578 ==
8228 13:59:20.805727 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 13:59:20.812601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 13:59:20.812817 ==
8231 13:59:20.812936
8232 13:59:20.813040
8233 13:59:20.815570 TX Vref Scan disable
8234 13:59:20.815719 == TX Byte 0 ==
8235 13:59:20.821881 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8236 13:59:20.822115 == TX Byte 1 ==
8237 13:59:20.825807 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8238 13:59:20.828515 DramC Write-DBI off
8239 13:59:20.828794
8240 13:59:20.828967 [DATLAT]
8241 13:59:20.831918 Freq=1600, CH0 RK1
8242 13:59:20.832122
8243 13:59:20.832281 DATLAT Default: 0xf
8244 13:59:20.835493 0, 0xFFFF, sum = 0
8245 13:59:20.835740 1, 0xFFFF, sum = 0
8246 13:59:20.838609 2, 0xFFFF, sum = 0
8247 13:59:20.838895 3, 0xFFFF, sum = 0
8248 13:59:20.841774 4, 0xFFFF, sum = 0
8249 13:59:20.842075 5, 0xFFFF, sum = 0
8250 13:59:20.845281 6, 0xFFFF, sum = 0
8251 13:59:20.845844 7, 0xFFFF, sum = 0
8252 13:59:20.848584 8, 0xFFFF, sum = 0
8253 13:59:20.851889 9, 0xFFFF, sum = 0
8254 13:59:20.852360 10, 0xFFFF, sum = 0
8255 13:59:20.854999 11, 0xFFFF, sum = 0
8256 13:59:20.855501 12, 0xFFFF, sum = 0
8257 13:59:20.859119 13, 0xCFFF, sum = 0
8258 13:59:20.859743 14, 0x0, sum = 1
8259 13:59:20.862059 15, 0x0, sum = 2
8260 13:59:20.862625 16, 0x0, sum = 3
8261 13:59:20.865320 17, 0x0, sum = 4
8262 13:59:20.865886 best_step = 15
8263 13:59:20.866253
8264 13:59:20.866591 ==
8265 13:59:20.868434 Dram Type= 6, Freq= 0, CH_0, rank 1
8266 13:59:20.871920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8267 13:59:20.872390 ==
8268 13:59:20.875469 RX Vref Scan: 0
8269 13:59:20.875955
8270 13:59:20.878148 RX Vref 0 -> 0, step: 1
8271 13:59:20.878610
8272 13:59:20.878971 RX Delay 3 -> 252, step: 4
8273 13:59:20.885416 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
8274 13:59:20.888989 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8275 13:59:20.892178 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8276 13:59:20.895270 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8277 13:59:20.899439 iDelay=195, Bit 4, Center 124 (71 ~ 178) 108
8278 13:59:20.905816 iDelay=195, Bit 5, Center 112 (59 ~ 166) 108
8279 13:59:20.908849 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8280 13:59:20.912152 iDelay=195, Bit 7, Center 136 (79 ~ 194) 116
8281 13:59:20.915261 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8282 13:59:20.918697 iDelay=195, Bit 9, Center 104 (47 ~ 162) 116
8283 13:59:20.925261 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
8284 13:59:20.928939 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8285 13:59:20.932082 iDelay=195, Bit 12, Center 124 (67 ~ 182) 116
8286 13:59:20.935822 iDelay=195, Bit 13, Center 122 (67 ~ 178) 112
8287 13:59:20.942276 iDelay=195, Bit 14, Center 128 (71 ~ 186) 116
8288 13:59:20.945682 iDelay=195, Bit 15, Center 124 (67 ~ 182) 116
8289 13:59:20.946376 ==
8290 13:59:20.948506 Dram Type= 6, Freq= 0, CH_0, rank 1
8291 13:59:20.952078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 13:59:20.952442 ==
8293 13:59:20.952709 DQS Delay:
8294 13:59:20.955344 DQS0 = 0, DQS1 = 0
8295 13:59:20.955931 DQM Delay:
8296 13:59:20.958274 DQM0 = 124, DQM1 = 117
8297 13:59:20.958646 DQ Delay:
8298 13:59:20.961830 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8299 13:59:20.964895 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =136
8300 13:59:20.968310 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8301 13:59:20.974885 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8302 13:59:20.975169
8303 13:59:20.975360
8304 13:59:20.975643
8305 13:59:20.978322 [DramC_TX_OE_Calibration] TA2
8306 13:59:20.978611 Original DQ_B0 (3 6) =30, OEN = 27
8307 13:59:20.981120 Original DQ_B1 (3 6) =30, OEN = 27
8308 13:59:20.984678 24, 0x0, End_B0=24 End_B1=24
8309 13:59:20.987957 25, 0x0, End_B0=25 End_B1=25
8310 13:59:20.991440 26, 0x0, End_B0=26 End_B1=26
8311 13:59:20.995039 27, 0x0, End_B0=27 End_B1=27
8312 13:59:20.995233 28, 0x0, End_B0=28 End_B1=28
8313 13:59:20.997898 29, 0x0, End_B0=29 End_B1=29
8314 13:59:21.001132 30, 0x0, End_B0=30 End_B1=30
8315 13:59:21.004630 31, 0x4141, End_B0=30 End_B1=30
8316 13:59:21.007549 Byte0 end_step=30 best_step=27
8317 13:59:21.007743 Byte1 end_step=30 best_step=27
8318 13:59:21.011213 Byte0 TX OE(2T, 0.5T) = (3, 3)
8319 13:59:21.014339 Byte1 TX OE(2T, 0.5T) = (3, 3)
8320 13:59:21.014528
8321 13:59:21.014677
8322 13:59:21.025595 [DQSOSCAuto] RK1, (LSB)MR18= 0x2210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8323 13:59:21.025788 CH0 RK1: MR19=303, MR18=2210
8324 13:59:21.030757 CH0_RK1: MR19=0x303, MR18=0x2210, DQSOSC=392, MR23=63, INC=24, DEC=16
8325 13:59:21.033982 [RxdqsGatingPostProcess] freq 1600
8326 13:59:21.040943 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8327 13:59:21.044312 best DQS0 dly(2T, 0.5T) = (1, 1)
8328 13:59:21.047741 best DQS1 dly(2T, 0.5T) = (1, 1)
8329 13:59:21.050805 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8330 13:59:21.053933 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8331 13:59:21.054125 best DQS0 dly(2T, 0.5T) = (1, 1)
8332 13:59:21.057470 best DQS1 dly(2T, 0.5T) = (1, 1)
8333 13:59:21.060789 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8334 13:59:21.064312 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8335 13:59:21.067611 Pre-setting of DQS Precalculation
8336 13:59:21.074229 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8337 13:59:21.074652 ==
8338 13:59:21.077487 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 13:59:21.081195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 13:59:21.081555 ==
8341 13:59:21.088009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8342 13:59:21.091433 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8343 13:59:21.094157 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8344 13:59:21.100918 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8345 13:59:21.109673 [CA 0] Center 41 (12~71) winsize 60
8346 13:59:21.112797 [CA 1] Center 42 (12~72) winsize 61
8347 13:59:21.116550 [CA 2] Center 38 (9~67) winsize 59
8348 13:59:21.119865 [CA 3] Center 37 (8~66) winsize 59
8349 13:59:21.123366 [CA 4] Center 37 (8~67) winsize 60
8350 13:59:21.126080 [CA 5] Center 36 (7~66) winsize 60
8351 13:59:21.126391
8352 13:59:21.129579 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8353 13:59:21.129920
8354 13:59:21.133119 [CATrainingPosCal] consider 1 rank data
8355 13:59:21.135944 u2DelayCellTimex100 = 258/100 ps
8356 13:59:21.139051 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8357 13:59:21.145814 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8358 13:59:21.149244 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8359 13:59:21.152642 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8360 13:59:21.155783 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8361 13:59:21.158990 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8362 13:59:21.159092
8363 13:59:21.162394 CA PerBit enable=1, Macro0, CA PI delay=36
8364 13:59:21.162494
8365 13:59:21.166057 [CBTSetCACLKResult] CA Dly = 36
8366 13:59:21.169428 CS Dly: 10 (0~41)
8367 13:59:21.172753 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8368 13:59:21.175701 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8369 13:59:21.175786 ==
8370 13:59:21.179107 Dram Type= 6, Freq= 0, CH_1, rank 1
8371 13:59:21.182181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8372 13:59:21.185681 ==
8373 13:59:21.189050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8374 13:59:21.192347 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8375 13:59:21.199108 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8376 13:59:21.205320 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8377 13:59:21.212817 [CA 0] Center 42 (13~71) winsize 59
8378 13:59:21.216186 [CA 1] Center 42 (12~72) winsize 61
8379 13:59:21.219668 [CA 2] Center 37 (8~67) winsize 60
8380 13:59:21.222986 [CA 3] Center 36 (7~66) winsize 60
8381 13:59:21.226388 [CA 4] Center 37 (7~67) winsize 61
8382 13:59:21.229585 [CA 5] Center 36 (6~66) winsize 61
8383 13:59:21.229924
8384 13:59:21.232652 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8385 13:59:21.233072
8386 13:59:21.235923 [CATrainingPosCal] consider 2 rank data
8387 13:59:21.239352 u2DelayCellTimex100 = 258/100 ps
8388 13:59:21.242690 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8389 13:59:21.249127 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8390 13:59:21.252315 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8391 13:59:21.255513 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8392 13:59:21.258868 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8393 13:59:21.262171 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8394 13:59:21.262251
8395 13:59:21.265209 CA PerBit enable=1, Macro0, CA PI delay=36
8396 13:59:21.265290
8397 13:59:21.268508 [CBTSetCACLKResult] CA Dly = 36
8398 13:59:21.272149 CS Dly: 11 (0~43)
8399 13:59:21.275247 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8400 13:59:21.278727 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8401 13:59:21.278812
8402 13:59:21.282595 ----->DramcWriteLeveling(PI) begin...
8403 13:59:21.282683 ==
8404 13:59:21.285474 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 13:59:21.291825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 13:59:21.291919 ==
8407 13:59:21.295023 Write leveling (Byte 0): 25 => 25
8408 13:59:21.298523 Write leveling (Byte 1): 29 => 29
8409 13:59:21.298645 DramcWriteLeveling(PI) end<-----
8410 13:59:21.298755
8411 13:59:21.302282 ==
8412 13:59:21.305367 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 13:59:21.308183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 13:59:21.308293 ==
8415 13:59:21.311550 [Gating] SW mode calibration
8416 13:59:21.318481 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8417 13:59:21.321923 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8418 13:59:21.328141 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 13:59:21.331812 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 13:59:21.334767 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 13:59:21.341602 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 13:59:21.344992 1 4 16 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
8423 13:59:21.348384 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 13:59:21.355813 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 13:59:21.358500 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 13:59:21.361542 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 13:59:21.368367 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 13:59:21.371598 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 13:59:21.374678 1 5 12 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 0)
8430 13:59:21.381070 1 5 16 | B1->B0 | 2424 2525 | 0 0 | (0 0) (1 0)
8431 13:59:21.385063 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8432 13:59:21.387726 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 13:59:21.394895 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 13:59:21.398155 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 13:59:21.401193 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 13:59:21.408485 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 13:59:21.411656 1 6 12 | B1->B0 | 2a2a 2929 | 0 0 | (0 0) (0 0)
8438 13:59:21.414308 1 6 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8439 13:59:21.420731 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 13:59:21.424171 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 13:59:21.427355 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 13:59:21.434601 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 13:59:21.437293 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 13:59:21.441770 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 13:59:21.447542 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8446 13:59:21.450477 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8447 13:59:21.453744 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8448 13:59:21.460757 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 13:59:21.464061 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 13:59:21.467283 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 13:59:21.473821 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 13:59:21.477348 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 13:59:21.480436 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 13:59:21.487132 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 13:59:21.490599 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 13:59:21.493731 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 13:59:21.500582 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 13:59:21.503366 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 13:59:21.507264 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 13:59:21.513385 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 13:59:21.516877 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8462 13:59:21.520304 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8463 13:59:21.526791 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 13:59:21.527180 Total UI for P1: 0, mck2ui 16
8465 13:59:21.533212 best dqsien dly found for B0: ( 1, 9, 14)
8466 13:59:21.533511 Total UI for P1: 0, mck2ui 16
8467 13:59:21.536582 best dqsien dly found for B1: ( 1, 9, 14)
8468 13:59:21.543255 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8469 13:59:21.546976 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8470 13:59:21.547270
8471 13:59:21.549790 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8472 13:59:21.553171 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8473 13:59:21.556695 [Gating] SW calibration Done
8474 13:59:21.557068 ==
8475 13:59:21.559595 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 13:59:21.562997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 13:59:21.563399 ==
8478 13:59:21.566506 RX Vref Scan: 0
8479 13:59:21.566798
8480 13:59:21.567028 RX Vref 0 -> 0, step: 1
8481 13:59:21.567425
8482 13:59:21.569944 RX Delay 0 -> 252, step: 8
8483 13:59:21.573079 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8484 13:59:21.579651 iDelay=208, Bit 1, Center 123 (64 ~ 183) 120
8485 13:59:21.583153 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8486 13:59:21.586010 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8487 13:59:21.589806 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8488 13:59:21.592768 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8489 13:59:21.599642 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8490 13:59:21.602961 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8491 13:59:21.605888 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8492 13:59:21.609378 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8493 13:59:21.612856 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8494 13:59:21.619500 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8495 13:59:21.623331 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8496 13:59:21.626303 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8497 13:59:21.629746 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8498 13:59:21.632711 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8499 13:59:21.636255 ==
8500 13:59:21.639380 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 13:59:21.643013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 13:59:21.643523 ==
8503 13:59:21.643902 DQS Delay:
8504 13:59:21.646427 DQS0 = 0, DQS1 = 0
8505 13:59:21.646974 DQM Delay:
8506 13:59:21.649479 DQM0 = 132, DQM1 = 126
8507 13:59:21.649894 DQ Delay:
8508 13:59:21.652602 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8509 13:59:21.656328 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8510 13:59:21.659280 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8511 13:59:21.662663 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8512 13:59:21.663099
8513 13:59:21.663472
8514 13:59:21.663790 ==
8515 13:59:21.665899 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 13:59:21.672884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 13:59:21.673307 ==
8518 13:59:21.673634
8519 13:59:21.673940
8520 13:59:21.674236 TX Vref Scan disable
8521 13:59:21.676245 == TX Byte 0 ==
8522 13:59:21.679928 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8523 13:59:21.686303 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8524 13:59:21.686727 == TX Byte 1 ==
8525 13:59:21.689666 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8526 13:59:21.696125 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8527 13:59:21.696547 ==
8528 13:59:21.699293 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 13:59:21.702484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 13:59:21.702905 ==
8531 13:59:21.715039
8532 13:59:21.718508 TX Vref early break, caculate TX vref
8533 13:59:21.721651 TX Vref=16, minBit 11, minWin=20, winSum=361
8534 13:59:21.725183 TX Vref=18, minBit 8, minWin=21, winSum=366
8535 13:59:21.728583 TX Vref=20, minBit 11, minWin=22, winSum=379
8536 13:59:21.731564 TX Vref=22, minBit 8, minWin=23, winSum=390
8537 13:59:21.738542 TX Vref=24, minBit 5, minWin=24, winSum=397
8538 13:59:21.741437 TX Vref=26, minBit 5, minWin=24, winSum=409
8539 13:59:21.744883 TX Vref=28, minBit 0, minWin=25, winSum=414
8540 13:59:21.748151 TX Vref=30, minBit 0, minWin=24, winSum=407
8541 13:59:21.751932 TX Vref=32, minBit 0, minWin=24, winSum=399
8542 13:59:21.754868 TX Vref=34, minBit 0, minWin=23, winSum=390
8543 13:59:21.761540 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
8544 13:59:21.762061
8545 13:59:21.764598 Final TX Range 0 Vref 28
8546 13:59:21.765115
8547 13:59:21.765501 ==
8548 13:59:21.767714 Dram Type= 6, Freq= 0, CH_1, rank 0
8549 13:59:21.771095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8550 13:59:21.771543 ==
8551 13:59:21.771944
8552 13:59:21.772262
8553 13:59:21.774781 TX Vref Scan disable
8554 13:59:21.781284 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8555 13:59:21.781701 == TX Byte 0 ==
8556 13:59:21.784738 u2DelayCellOfst[0]=22 cells (6 PI)
8557 13:59:21.787875 u2DelayCellOfst[1]=15 cells (4 PI)
8558 13:59:21.791066 u2DelayCellOfst[2]=0 cells (0 PI)
8559 13:59:21.794466 u2DelayCellOfst[3]=11 cells (3 PI)
8560 13:59:21.797615 u2DelayCellOfst[4]=11 cells (3 PI)
8561 13:59:21.801043 u2DelayCellOfst[5]=26 cells (7 PI)
8562 13:59:21.804475 u2DelayCellOfst[6]=22 cells (6 PI)
8563 13:59:21.807872 u2DelayCellOfst[7]=7 cells (2 PI)
8564 13:59:21.810888 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8565 13:59:21.814213 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8566 13:59:21.818028 == TX Byte 1 ==
8567 13:59:21.821291 u2DelayCellOfst[8]=0 cells (0 PI)
8568 13:59:21.821811 u2DelayCellOfst[9]=7 cells (2 PI)
8569 13:59:21.824253 u2DelayCellOfst[10]=11 cells (3 PI)
8570 13:59:21.827732 u2DelayCellOfst[11]=7 cells (2 PI)
8571 13:59:21.830975 u2DelayCellOfst[12]=15 cells (4 PI)
8572 13:59:21.834256 u2DelayCellOfst[13]=18 cells (5 PI)
8573 13:59:21.837722 u2DelayCellOfst[14]=18 cells (5 PI)
8574 13:59:21.841204 u2DelayCellOfst[15]=18 cells (5 PI)
8575 13:59:21.847579 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8576 13:59:21.850792 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8577 13:59:21.851236 DramC Write-DBI on
8578 13:59:21.851603 ==
8579 13:59:21.854287 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 13:59:21.860549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 13:59:21.860987 ==
8582 13:59:21.861319
8583 13:59:21.861625
8584 13:59:21.861919 TX Vref Scan disable
8585 13:59:21.865127 == TX Byte 0 ==
8586 13:59:21.868165 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8587 13:59:21.871454 == TX Byte 1 ==
8588 13:59:21.874915 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8589 13:59:21.878278 DramC Write-DBI off
8590 13:59:21.878718
8591 13:59:21.879077 [DATLAT]
8592 13:59:21.879510 Freq=1600, CH1 RK0
8593 13:59:21.879865
8594 13:59:21.881357 DATLAT Default: 0xf
8595 13:59:21.881798 0, 0xFFFF, sum = 0
8596 13:59:21.884432 1, 0xFFFF, sum = 0
8597 13:59:21.885033 2, 0xFFFF, sum = 0
8598 13:59:21.887976 3, 0xFFFF, sum = 0
8599 13:59:21.891206 4, 0xFFFF, sum = 0
8600 13:59:21.891773 5, 0xFFFF, sum = 0
8601 13:59:21.895007 6, 0xFFFF, sum = 0
8602 13:59:21.895499 7, 0xFFFF, sum = 0
8603 13:59:21.898362 8, 0xFFFF, sum = 0
8604 13:59:21.898829 9, 0xFFFF, sum = 0
8605 13:59:21.901104 10, 0xFFFF, sum = 0
8606 13:59:21.901515 11, 0xFFFF, sum = 0
8607 13:59:21.904604 12, 0xFFFF, sum = 0
8608 13:59:21.905128 13, 0x8FFF, sum = 0
8609 13:59:21.908210 14, 0x0, sum = 1
8610 13:59:21.908658 15, 0x0, sum = 2
8611 13:59:21.911316 16, 0x0, sum = 3
8612 13:59:21.911795 17, 0x0, sum = 4
8613 13:59:21.914502 best_step = 15
8614 13:59:21.915002
8615 13:59:21.915537 ==
8616 13:59:21.918333 Dram Type= 6, Freq= 0, CH_1, rank 0
8617 13:59:21.921367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8618 13:59:21.921784 ==
8619 13:59:21.922114 RX Vref Scan: 1
8620 13:59:21.924358
8621 13:59:21.924785 Set Vref Range= 24 -> 127
8622 13:59:21.925115
8623 13:59:21.928365 RX Vref 24 -> 127, step: 1
8624 13:59:21.928777
8625 13:59:21.931061 RX Delay 11 -> 252, step: 4
8626 13:59:21.931520
8627 13:59:21.934421 Set Vref, RX VrefLevel [Byte0]: 24
8628 13:59:21.938218 [Byte1]: 24
8629 13:59:21.938650
8630 13:59:21.941110 Set Vref, RX VrefLevel [Byte0]: 25
8631 13:59:21.944884 [Byte1]: 25
8632 13:59:21.945312
8633 13:59:21.947882 Set Vref, RX VrefLevel [Byte0]: 26
8634 13:59:21.951032 [Byte1]: 26
8635 13:59:21.954975
8636 13:59:21.955438 Set Vref, RX VrefLevel [Byte0]: 27
8637 13:59:21.958757 [Byte1]: 27
8638 13:59:21.962573
8639 13:59:21.963017 Set Vref, RX VrefLevel [Byte0]: 28
8640 13:59:21.966127 [Byte1]: 28
8641 13:59:21.970381
8642 13:59:21.970834 Set Vref, RX VrefLevel [Byte0]: 29
8643 13:59:21.973985 [Byte1]: 29
8644 13:59:21.977729
8645 13:59:21.978148 Set Vref, RX VrefLevel [Byte0]: 30
8646 13:59:21.981037 [Byte1]: 30
8647 13:59:21.985616
8648 13:59:21.986058 Set Vref, RX VrefLevel [Byte0]: 31
8649 13:59:21.989193 [Byte1]: 31
8650 13:59:21.993182
8651 13:59:21.993615 Set Vref, RX VrefLevel [Byte0]: 32
8652 13:59:21.996336 [Byte1]: 32
8653 13:59:22.000705
8654 13:59:22.001122 Set Vref, RX VrefLevel [Byte0]: 33
8655 13:59:22.004193 [Byte1]: 33
8656 13:59:22.008378
8657 13:59:22.008796 Set Vref, RX VrefLevel [Byte0]: 34
8658 13:59:22.011551 [Byte1]: 34
8659 13:59:22.016459
8660 13:59:22.016879 Set Vref, RX VrefLevel [Byte0]: 35
8661 13:59:22.019905 [Byte1]: 35
8662 13:59:22.023833
8663 13:59:22.024314 Set Vref, RX VrefLevel [Byte0]: 36
8664 13:59:22.027061 [Byte1]: 36
8665 13:59:22.031249
8666 13:59:22.031712 Set Vref, RX VrefLevel [Byte0]: 37
8667 13:59:22.034889 [Byte1]: 37
8668 13:59:22.038842
8669 13:59:22.039259 Set Vref, RX VrefLevel [Byte0]: 38
8670 13:59:22.042071 [Byte1]: 38
8671 13:59:22.046759
8672 13:59:22.047175 Set Vref, RX VrefLevel [Byte0]: 39
8673 13:59:22.049966 [Byte1]: 39
8674 13:59:22.054010
8675 13:59:22.054427 Set Vref, RX VrefLevel [Byte0]: 40
8676 13:59:22.057340 [Byte1]: 40
8677 13:59:22.062187
8678 13:59:22.062606 Set Vref, RX VrefLevel [Byte0]: 41
8679 13:59:22.065025 [Byte1]: 41
8680 13:59:22.069391
8681 13:59:22.069805 Set Vref, RX VrefLevel [Byte0]: 42
8682 13:59:22.072637 [Byte1]: 42
8683 13:59:22.077373
8684 13:59:22.077784 Set Vref, RX VrefLevel [Byte0]: 43
8685 13:59:22.080254 [Byte1]: 43
8686 13:59:22.085058
8687 13:59:22.085490 Set Vref, RX VrefLevel [Byte0]: 44
8688 13:59:22.087673 [Byte1]: 44
8689 13:59:22.091994
8690 13:59:22.092418 Set Vref, RX VrefLevel [Byte0]: 45
8691 13:59:22.095441 [Byte1]: 45
8692 13:59:22.099656
8693 13:59:22.100081 Set Vref, RX VrefLevel [Byte0]: 46
8694 13:59:22.103290 [Byte1]: 46
8695 13:59:22.107619
8696 13:59:22.108039 Set Vref, RX VrefLevel [Byte0]: 47
8697 13:59:22.110442 [Byte1]: 47
8698 13:59:22.114806
8699 13:59:22.115228 Set Vref, RX VrefLevel [Byte0]: 48
8700 13:59:22.118436 [Byte1]: 48
8701 13:59:22.122928
8702 13:59:22.123493 Set Vref, RX VrefLevel [Byte0]: 49
8703 13:59:22.126012 [Byte1]: 49
8704 13:59:22.129978
8705 13:59:22.130489 Set Vref, RX VrefLevel [Byte0]: 50
8706 13:59:22.133423 [Byte1]: 50
8707 13:59:22.137924
8708 13:59:22.138349 Set Vref, RX VrefLevel [Byte0]: 51
8709 13:59:22.140852 [Byte1]: 51
8710 13:59:22.145349
8711 13:59:22.145785 Set Vref, RX VrefLevel [Byte0]: 52
8712 13:59:22.148836 [Byte1]: 52
8713 13:59:22.153035
8714 13:59:22.153459 Set Vref, RX VrefLevel [Byte0]: 53
8715 13:59:22.156568 [Byte1]: 53
8716 13:59:22.160595
8717 13:59:22.161076 Set Vref, RX VrefLevel [Byte0]: 54
8718 13:59:22.164113 [Byte1]: 54
8719 13:59:22.168046
8720 13:59:22.168553 Set Vref, RX VrefLevel [Byte0]: 55
8721 13:59:22.171505 [Byte1]: 55
8722 13:59:22.176241
8723 13:59:22.176663 Set Vref, RX VrefLevel [Byte0]: 56
8724 13:59:22.179062 [Byte1]: 56
8725 13:59:22.183797
8726 13:59:22.184217 Set Vref, RX VrefLevel [Byte0]: 57
8727 13:59:22.186657 [Byte1]: 57
8728 13:59:22.191357
8729 13:59:22.191821 Set Vref, RX VrefLevel [Byte0]: 58
8730 13:59:22.194597 [Byte1]: 58
8731 13:59:22.198598
8732 13:59:22.199020 Set Vref, RX VrefLevel [Byte0]: 59
8733 13:59:22.202520 [Byte1]: 59
8734 13:59:22.206331
8735 13:59:22.206753 Set Vref, RX VrefLevel [Byte0]: 60
8736 13:59:22.209608 [Byte1]: 60
8737 13:59:22.213793
8738 13:59:22.214215 Set Vref, RX VrefLevel [Byte0]: 61
8739 13:59:22.217353 [Byte1]: 61
8740 13:59:22.221455
8741 13:59:22.221878 Set Vref, RX VrefLevel [Byte0]: 62
8742 13:59:22.225081 [Byte1]: 62
8743 13:59:22.229061
8744 13:59:22.229480 Set Vref, RX VrefLevel [Byte0]: 63
8745 13:59:22.232739 [Byte1]: 63
8746 13:59:22.236685
8747 13:59:22.237127 Set Vref, RX VrefLevel [Byte0]: 64
8748 13:59:22.240172 [Byte1]: 64
8749 13:59:22.244358
8750 13:59:22.244783 Set Vref, RX VrefLevel [Byte0]: 65
8751 13:59:22.248029 [Byte1]: 65
8752 13:59:22.251920
8753 13:59:22.252346 Set Vref, RX VrefLevel [Byte0]: 66
8754 13:59:22.255353 [Byte1]: 66
8755 13:59:22.259469
8756 13:59:22.259976 Set Vref, RX VrefLevel [Byte0]: 67
8757 13:59:22.262964 [Byte1]: 67
8758 13:59:22.267455
8759 13:59:22.267998 Set Vref, RX VrefLevel [Byte0]: 68
8760 13:59:22.270884 [Byte1]: 68
8761 13:59:22.274816
8762 13:59:22.275249 Set Vref, RX VrefLevel [Byte0]: 69
8763 13:59:22.278359 [Byte1]: 69
8764 13:59:22.282687
8765 13:59:22.283162 Set Vref, RX VrefLevel [Byte0]: 70
8766 13:59:22.285823 [Byte1]: 70
8767 13:59:22.290128
8768 13:59:22.290570 Set Vref, RX VrefLevel [Byte0]: 71
8769 13:59:22.293322 [Byte1]: 71
8770 13:59:22.297828
8771 13:59:22.298250 Final RX Vref Byte 0 = 59 to rank0
8772 13:59:22.300876 Final RX Vref Byte 1 = 54 to rank0
8773 13:59:22.304938 Final RX Vref Byte 0 = 59 to rank1
8774 13:59:22.307457 Final RX Vref Byte 1 = 54 to rank1==
8775 13:59:22.311033 Dram Type= 6, Freq= 0, CH_1, rank 0
8776 13:59:22.317561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 13:59:22.317988 ==
8778 13:59:22.318327 DQS Delay:
8779 13:59:22.320659 DQS0 = 0, DQS1 = 0
8780 13:59:22.321081 DQM Delay:
8781 13:59:22.321415 DQM0 = 130, DQM1 = 123
8782 13:59:22.324446 DQ Delay:
8783 13:59:22.327881 DQ0 =138, DQ1 =126, DQ2 =118, DQ3 =126
8784 13:59:22.330742 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =126
8785 13:59:22.334607 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8786 13:59:22.337335 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8787 13:59:22.337766
8788 13:59:22.338100
8789 13:59:22.338411
8790 13:59:22.340496 [DramC_TX_OE_Calibration] TA2
8791 13:59:22.344087 Original DQ_B0 (3 6) =30, OEN = 27
8792 13:59:22.347179 Original DQ_B1 (3 6) =30, OEN = 27
8793 13:59:22.350466 24, 0x0, End_B0=24 End_B1=24
8794 13:59:22.350939 25, 0x0, End_B0=25 End_B1=25
8795 13:59:22.353828 26, 0x0, End_B0=26 End_B1=26
8796 13:59:22.357707 27, 0x0, End_B0=27 End_B1=27
8797 13:59:22.361024 28, 0x0, End_B0=28 End_B1=28
8798 13:59:22.363845 29, 0x0, End_B0=29 End_B1=29
8799 13:59:22.364275 30, 0x0, End_B0=30 End_B1=30
8800 13:59:22.367244 31, 0x4141, End_B0=30 End_B1=30
8801 13:59:22.370946 Byte0 end_step=30 best_step=27
8802 13:59:22.373721 Byte1 end_step=30 best_step=27
8803 13:59:22.377312 Byte0 TX OE(2T, 0.5T) = (3, 3)
8804 13:59:22.380480 Byte1 TX OE(2T, 0.5T) = (3, 3)
8805 13:59:22.380902
8806 13:59:22.381280
8807 13:59:22.387318 [DQSOSCAuto] RK0, (LSB)MR18= 0x70c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8808 13:59:22.390593 CH1 RK0: MR19=303, MR18=70C
8809 13:59:22.397336 CH1_RK0: MR19=0x303, MR18=0x70C, DQSOSC=403, MR23=63, INC=22, DEC=15
8810 13:59:22.397762
8811 13:59:22.400693 ----->DramcWriteLeveling(PI) begin...
8812 13:59:22.401257 ==
8813 13:59:22.403838 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 13:59:22.407481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 13:59:22.407903 ==
8816 13:59:22.410655 Write leveling (Byte 0): 22 => 22
8817 13:59:22.414050 Write leveling (Byte 1): 28 => 28
8818 13:59:22.417109 DramcWriteLeveling(PI) end<-----
8819 13:59:22.417527
8820 13:59:22.417857 ==
8821 13:59:22.420520 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 13:59:22.423869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 13:59:22.424292 ==
8824 13:59:22.427448 [Gating] SW mode calibration
8825 13:59:22.433935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8826 13:59:22.440764 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8827 13:59:22.443736 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 13:59:22.447019 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 13:59:22.453558 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8830 13:59:22.457000 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8831 13:59:22.460184 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 13:59:22.467310 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 13:59:22.470095 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 13:59:22.473319 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 13:59:22.479882 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 13:59:22.483344 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8837 13:59:22.486994 1 5 8 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
8838 13:59:22.493264 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8839 13:59:22.496958 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8840 13:59:22.500295 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 13:59:22.506693 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 13:59:22.509979 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 13:59:22.513177 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 13:59:22.519943 1 6 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8845 13:59:22.523468 1 6 8 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
8846 13:59:22.526849 1 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8847 13:59:22.533517 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 13:59:22.536451 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 13:59:22.539624 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 13:59:22.546280 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 13:59:22.549868 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 13:59:22.553446 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 13:59:22.559837 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8854 13:59:22.562666 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8855 13:59:22.566022 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 13:59:22.572953 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 13:59:22.576428 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 13:59:22.579322 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 13:59:22.586007 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 13:59:22.589706 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 13:59:22.592766 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 13:59:22.599075 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 13:59:22.602737 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 13:59:22.605897 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 13:59:22.612675 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 13:59:22.616363 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 13:59:22.618985 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 13:59:22.625903 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 13:59:22.629325 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8870 13:59:22.632269 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8871 13:59:22.635517 Total UI for P1: 0, mck2ui 16
8872 13:59:22.639525 best dqsien dly found for B0: ( 1, 9, 8)
8873 13:59:22.642292 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 13:59:22.645744 Total UI for P1: 0, mck2ui 16
8875 13:59:22.648914 best dqsien dly found for B1: ( 1, 9, 10)
8876 13:59:22.652115 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8877 13:59:22.655489 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8878 13:59:22.658951
8879 13:59:22.662223 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8880 13:59:22.665585 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8881 13:59:22.668675 [Gating] SW calibration Done
8882 13:59:22.669094 ==
8883 13:59:22.672185 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 13:59:22.675783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 13:59:22.676203 ==
8886 13:59:22.676581 RX Vref Scan: 0
8887 13:59:22.678627
8888 13:59:22.679040 RX Vref 0 -> 0, step: 1
8889 13:59:22.679370
8890 13:59:22.682212 RX Delay 0 -> 252, step: 8
8891 13:59:22.685072 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8892 13:59:22.688490 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8893 13:59:22.695327 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8894 13:59:22.698490 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8895 13:59:22.702087 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8896 13:59:22.705205 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8897 13:59:22.708621 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8898 13:59:22.715835 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8899 13:59:22.718450 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8900 13:59:22.721481 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8901 13:59:22.724773 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8902 13:59:22.728111 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8903 13:59:22.735320 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8904 13:59:22.738347 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8905 13:59:22.741771 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8906 13:59:22.744691 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8907 13:59:22.745150 ==
8908 13:59:22.748053 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 13:59:22.754954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 13:59:22.755383 ==
8911 13:59:22.755758 DQS Delay:
8912 13:59:22.758412 DQS0 = 0, DQS1 = 0
8913 13:59:22.758831 DQM Delay:
8914 13:59:22.761547 DQM0 = 133, DQM1 = 129
8915 13:59:22.761969 DQ Delay:
8916 13:59:22.764923 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131
8917 13:59:22.767927 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8918 13:59:22.771504 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8919 13:59:22.774765 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8920 13:59:22.775187
8921 13:59:22.775573
8922 13:59:22.775893 ==
8923 13:59:22.777976 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 13:59:22.784577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 13:59:22.785001 ==
8926 13:59:22.785334
8927 13:59:22.785641
8928 13:59:22.785938 TX Vref Scan disable
8929 13:59:22.787921 == TX Byte 0 ==
8930 13:59:22.791270 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8931 13:59:22.798230 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8932 13:59:22.798727 == TX Byte 1 ==
8933 13:59:22.801148 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8934 13:59:22.808197 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8935 13:59:22.808708 ==
8936 13:59:22.811643 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 13:59:22.815072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 13:59:22.815538 ==
8939 13:59:22.827106
8940 13:59:22.830650 TX Vref early break, caculate TX vref
8941 13:59:22.833680 TX Vref=16, minBit 0, minWin=21, winSum=372
8942 13:59:22.837268 TX Vref=18, minBit 6, minWin=22, winSum=381
8943 13:59:22.840744 TX Vref=20, minBit 0, minWin=22, winSum=390
8944 13:59:22.843909 TX Vref=22, minBit 0, minWin=23, winSum=403
8945 13:59:22.847343 TX Vref=24, minBit 0, minWin=23, winSum=405
8946 13:59:22.853571 TX Vref=26, minBit 6, minWin=24, winSum=418
8947 13:59:22.857006 TX Vref=28, minBit 0, minWin=24, winSum=421
8948 13:59:22.860530 TX Vref=30, minBit 1, minWin=24, winSum=415
8949 13:59:22.864091 TX Vref=32, minBit 1, minWin=23, winSum=409
8950 13:59:22.866784 TX Vref=34, minBit 0, minWin=22, winSum=397
8951 13:59:22.873727 [TxChooseVref] Worse bit 0, Min win 24, Win sum 421, Final Vref 28
8952 13:59:22.874259
8953 13:59:22.876877 Final TX Range 0 Vref 28
8954 13:59:22.877339
8955 13:59:22.877674 ==
8956 13:59:22.880381 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 13:59:22.883534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 13:59:22.883961 ==
8959 13:59:22.884295
8960 13:59:22.884606
8961 13:59:22.886928 TX Vref Scan disable
8962 13:59:22.893568 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8963 13:59:22.894008 == TX Byte 0 ==
8964 13:59:22.896934 u2DelayCellOfst[0]=15 cells (4 PI)
8965 13:59:22.900278 u2DelayCellOfst[1]=15 cells (4 PI)
8966 13:59:22.903656 u2DelayCellOfst[2]=0 cells (0 PI)
8967 13:59:22.906531 u2DelayCellOfst[3]=3 cells (1 PI)
8968 13:59:22.909838 u2DelayCellOfst[4]=7 cells (2 PI)
8969 13:59:22.913552 u2DelayCellOfst[5]=22 cells (6 PI)
8970 13:59:22.916695 u2DelayCellOfst[6]=22 cells (6 PI)
8971 13:59:22.920265 u2DelayCellOfst[7]=7 cells (2 PI)
8972 13:59:22.923920 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8973 13:59:22.926957 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8974 13:59:22.930080 == TX Byte 1 ==
8975 13:59:22.930576 u2DelayCellOfst[8]=0 cells (0 PI)
8976 13:59:22.933314 u2DelayCellOfst[9]=7 cells (2 PI)
8977 13:59:22.937219 u2DelayCellOfst[10]=15 cells (4 PI)
8978 13:59:22.939756 u2DelayCellOfst[11]=3 cells (1 PI)
8979 13:59:22.943113 u2DelayCellOfst[12]=18 cells (5 PI)
8980 13:59:22.946282 u2DelayCellOfst[13]=18 cells (5 PI)
8981 13:59:22.949778 u2DelayCellOfst[14]=22 cells (6 PI)
8982 13:59:22.953202 u2DelayCellOfst[15]=18 cells (5 PI)
8983 13:59:22.955979 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8984 13:59:22.962860 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8985 13:59:22.963278 DramC Write-DBI on
8986 13:59:22.963669 ==
8987 13:59:22.966418 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 13:59:22.972596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 13:59:22.973027 ==
8990 13:59:22.973355
8991 13:59:22.973655
8992 13:59:22.973946 TX Vref Scan disable
8993 13:59:22.977062 == TX Byte 0 ==
8994 13:59:22.979978 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8995 13:59:22.983066 == TX Byte 1 ==
8996 13:59:22.986490 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8997 13:59:22.989750 DramC Write-DBI off
8998 13:59:22.990201
8999 13:59:22.990534 [DATLAT]
9000 13:59:22.990882 Freq=1600, CH1 RK1
9001 13:59:22.991365
9002 13:59:22.993496 DATLAT Default: 0xf
9003 13:59:22.994062 0, 0xFFFF, sum = 0
9004 13:59:22.996622 1, 0xFFFF, sum = 0
9005 13:59:22.999804 2, 0xFFFF, sum = 0
9006 13:59:23.000500 3, 0xFFFF, sum = 0
9007 13:59:23.002864 4, 0xFFFF, sum = 0
9008 13:59:23.003519 5, 0xFFFF, sum = 0
9009 13:59:23.006709 6, 0xFFFF, sum = 0
9010 13:59:23.007129 7, 0xFFFF, sum = 0
9011 13:59:23.009713 8, 0xFFFF, sum = 0
9012 13:59:23.010133 9, 0xFFFF, sum = 0
9013 13:59:23.013153 10, 0xFFFF, sum = 0
9014 13:59:23.013654 11, 0xFFFF, sum = 0
9015 13:59:23.016476 12, 0xFFFF, sum = 0
9016 13:59:23.016911 13, 0x8FFF, sum = 0
9017 13:59:23.020064 14, 0x0, sum = 1
9018 13:59:23.020576 15, 0x0, sum = 2
9019 13:59:23.022952 16, 0x0, sum = 3
9020 13:59:23.023381 17, 0x0, sum = 4
9021 13:59:23.026374 best_step = 15
9022 13:59:23.026787
9023 13:59:23.027111 ==
9024 13:59:23.029756 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 13:59:23.033154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 13:59:23.033701 ==
9027 13:59:23.036428 RX Vref Scan: 0
9028 13:59:23.036843
9029 13:59:23.037166 RX Vref 0 -> 0, step: 1
9030 13:59:23.037469
9031 13:59:23.039936 RX Delay 11 -> 252, step: 4
9032 13:59:23.042857 iDelay=195, Bit 0, Center 136 (83 ~ 190) 108
9033 13:59:23.049684 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9034 13:59:23.052635 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9035 13:59:23.056256 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9036 13:59:23.059379 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9037 13:59:23.062465 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9038 13:59:23.069198 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9039 13:59:23.073133 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
9040 13:59:23.075808 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9041 13:59:23.079271 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9042 13:59:23.082579 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9043 13:59:23.089471 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9044 13:59:23.092298 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9045 13:59:23.095718 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9046 13:59:23.098801 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9047 13:59:23.105504 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9048 13:59:23.105696 ==
9049 13:59:23.108720 Dram Type= 6, Freq= 0, CH_1, rank 1
9050 13:59:23.112547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9051 13:59:23.112790 ==
9052 13:59:23.112997 DQS Delay:
9053 13:59:23.115820 DQS0 = 0, DQS1 = 0
9054 13:59:23.115998 DQM Delay:
9055 13:59:23.118981 DQM0 = 129, DQM1 = 126
9056 13:59:23.119160 DQ Delay:
9057 13:59:23.122142 DQ0 =136, DQ1 =128, DQ2 =116, DQ3 =126
9058 13:59:23.125310 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =126
9059 13:59:23.129142 DQ8 =114, DQ9 =114, DQ10 =128, DQ11 =120
9060 13:59:23.131754 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
9061 13:59:23.131933
9062 13:59:23.135279
9063 13:59:23.135502
9064 13:59:23.135645 [DramC_TX_OE_Calibration] TA2
9065 13:59:23.138862 Original DQ_B0 (3 6) =30, OEN = 27
9066 13:59:23.141985 Original DQ_B1 (3 6) =30, OEN = 27
9067 13:59:23.145448 24, 0x0, End_B0=24 End_B1=24
9068 13:59:23.148934 25, 0x0, End_B0=25 End_B1=25
9069 13:59:23.151974 26, 0x0, End_B0=26 End_B1=26
9070 13:59:23.152156 27, 0x0, End_B0=27 End_B1=27
9071 13:59:23.155591 28, 0x0, End_B0=28 End_B1=28
9072 13:59:23.158380 29, 0x0, End_B0=29 End_B1=29
9073 13:59:23.162073 30, 0x0, End_B0=30 End_B1=30
9074 13:59:23.165173 31, 0x4141, End_B0=30 End_B1=30
9075 13:59:23.165355 Byte0 end_step=30 best_step=27
9076 13:59:23.168331 Byte1 end_step=30 best_step=27
9077 13:59:23.171878 Byte0 TX OE(2T, 0.5T) = (3, 3)
9078 13:59:23.175105 Byte1 TX OE(2T, 0.5T) = (3, 3)
9079 13:59:23.175285
9080 13:59:23.175447
9081 13:59:23.181576 [DQSOSCAuto] RK1, (LSB)MR18= 0x121e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9082 13:59:23.185179 CH1 RK1: MR19=303, MR18=121E
9083 13:59:23.191326 CH1_RK1: MR19=0x303, MR18=0x121E, DQSOSC=394, MR23=63, INC=23, DEC=15
9084 13:59:23.195712 [RxdqsGatingPostProcess] freq 1600
9085 13:59:23.201864 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9086 13:59:23.205020 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 13:59:23.208098 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 13:59:23.211463 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 13:59:23.211971 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 13:59:23.214815 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 13:59:23.218387 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 13:59:23.221827 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 13:59:23.225155 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 13:59:23.228114 Pre-setting of DQS Precalculation
9095 13:59:23.235209 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9096 13:59:23.241533 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9097 13:59:23.247954 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 13:59:23.248376
9099 13:59:23.248709
9100 13:59:23.251464 [Calibration Summary] 3200 Mbps
9101 13:59:23.251893 CH 0, Rank 0
9102 13:59:23.254733 SW Impedance : PASS
9103 13:59:23.258431 DUTY Scan : NO K
9104 13:59:23.258851 ZQ Calibration : PASS
9105 13:59:23.261684 Jitter Meter : NO K
9106 13:59:23.264686 CBT Training : PASS
9107 13:59:23.265104 Write leveling : PASS
9108 13:59:23.268130 RX DQS gating : PASS
9109 13:59:23.268551 RX DQ/DQS(RDDQC) : PASS
9110 13:59:23.271443 TX DQ/DQS : PASS
9111 13:59:23.274531 RX DATLAT : PASS
9112 13:59:23.274950 RX DQ/DQS(Engine): PASS
9113 13:59:23.278020 TX OE : PASS
9114 13:59:23.278440 All Pass.
9115 13:59:23.278772
9116 13:59:23.281183 CH 0, Rank 1
9117 13:59:23.281603 SW Impedance : PASS
9118 13:59:23.284392 DUTY Scan : NO K
9119 13:59:23.288430 ZQ Calibration : PASS
9120 13:59:23.288811 Jitter Meter : NO K
9121 13:59:23.291492 CBT Training : PASS
9122 13:59:23.294567 Write leveling : PASS
9123 13:59:23.295102 RX DQS gating : PASS
9124 13:59:23.297714 RX DQ/DQS(RDDQC) : PASS
9125 13:59:23.301052 TX DQ/DQS : PASS
9126 13:59:23.301475 RX DATLAT : PASS
9127 13:59:23.304340 RX DQ/DQS(Engine): PASS
9128 13:59:23.307664 TX OE : PASS
9129 13:59:23.308086 All Pass.
9130 13:59:23.308418
9131 13:59:23.308727 CH 1, Rank 0
9132 13:59:23.311084 SW Impedance : PASS
9133 13:59:23.314288 DUTY Scan : NO K
9134 13:59:23.314705 ZQ Calibration : PASS
9135 13:59:23.317628 Jitter Meter : NO K
9136 13:59:23.320823 CBT Training : PASS
9137 13:59:23.321365 Write leveling : PASS
9138 13:59:23.324135 RX DQS gating : PASS
9139 13:59:23.324581 RX DQ/DQS(RDDQC) : PASS
9140 13:59:23.327790 TX DQ/DQS : PASS
9141 13:59:23.330881 RX DATLAT : PASS
9142 13:59:23.331456 RX DQ/DQS(Engine): PASS
9143 13:59:23.334400 TX OE : PASS
9144 13:59:23.334933 All Pass.
9145 13:59:23.335444
9146 13:59:23.337424 CH 1, Rank 1
9147 13:59:23.337818 SW Impedance : PASS
9148 13:59:23.340960 DUTY Scan : NO K
9149 13:59:23.344009 ZQ Calibration : PASS
9150 13:59:23.344461 Jitter Meter : NO K
9151 13:59:23.347796 CBT Training : PASS
9152 13:59:23.351098 Write leveling : PASS
9153 13:59:23.351539 RX DQS gating : PASS
9154 13:59:23.354014 RX DQ/DQS(RDDQC) : PASS
9155 13:59:23.357568 TX DQ/DQS : PASS
9156 13:59:23.358104 RX DATLAT : PASS
9157 13:59:23.360617 RX DQ/DQS(Engine): PASS
9158 13:59:23.363999 TX OE : PASS
9159 13:59:23.364423 All Pass.
9160 13:59:23.364759
9161 13:59:23.365073 DramC Write-DBI on
9162 13:59:23.367302 PER_BANK_REFRESH: Hybrid Mode
9163 13:59:23.370886 TX_TRACKING: ON
9164 13:59:23.377286 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9165 13:59:23.387261 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9166 13:59:23.394079 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9167 13:59:23.397377 [FAST_K] Save calibration result to emmc
9168 13:59:23.400296 sync common calibartion params.
9169 13:59:23.403873 sync cbt_mode0:1, 1:1
9170 13:59:23.404385 dram_init: ddr_geometry: 2
9171 13:59:23.407479 dram_init: ddr_geometry: 2
9172 13:59:23.410385 dram_init: ddr_geometry: 2
9173 13:59:23.410805 0:dram_rank_size:100000000
9174 13:59:23.413726 1:dram_rank_size:100000000
9175 13:59:23.420545 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9176 13:59:23.423534 DFS_SHUFFLE_HW_MODE: ON
9177 13:59:23.427511 dramc_set_vcore_voltage set vcore to 725000
9178 13:59:23.428087 Read voltage for 1600, 0
9179 13:59:23.430850 Vio18 = 0
9180 13:59:23.431437 Vcore = 725000
9181 13:59:23.431929 Vdram = 0
9182 13:59:23.434048 Vddq = 0
9183 13:59:23.434593 Vmddr = 0
9184 13:59:23.437498 switch to 3200 Mbps bootup
9185 13:59:23.438037 [DramcRunTimeConfig]
9186 13:59:23.438505 PHYPLL
9187 13:59:23.440382 DPM_CONTROL_AFTERK: ON
9188 13:59:23.443751 PER_BANK_REFRESH: ON
9189 13:59:23.444261 REFRESH_OVERHEAD_REDUCTION: ON
9190 13:59:23.446804 CMD_PICG_NEW_MODE: OFF
9191 13:59:23.450363 XRTWTW_NEW_MODE: ON
9192 13:59:23.450924 XRTRTR_NEW_MODE: ON
9193 13:59:23.453748 TX_TRACKING: ON
9194 13:59:23.454298 RDSEL_TRACKING: OFF
9195 13:59:23.457414 DQS Precalculation for DVFS: ON
9196 13:59:23.457829 RX_TRACKING: OFF
9197 13:59:23.460049 HW_GATING DBG: ON
9198 13:59:23.460435 ZQCS_ENABLE_LP4: ON
9199 13:59:23.463494 RX_PICG_NEW_MODE: ON
9200 13:59:23.466597 TX_PICG_NEW_MODE: ON
9201 13:59:23.466988 ENABLE_RX_DCM_DPHY: ON
9202 13:59:23.469974 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9203 13:59:23.473522 DUMMY_READ_FOR_TRACKING: OFF
9204 13:59:23.476630 !!! SPM_CONTROL_AFTERK: OFF
9205 13:59:23.480201 !!! SPM could not control APHY
9206 13:59:23.480497 IMPEDANCE_TRACKING: ON
9207 13:59:23.483501 TEMP_SENSOR: ON
9208 13:59:23.483830 HW_SAVE_FOR_SR: OFF
9209 13:59:23.486935 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9210 13:59:23.489747 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9211 13:59:23.493346 Read ODT Tracking: ON
9212 13:59:23.493640 Refresh Rate DeBounce: ON
9213 13:59:23.496599 DFS_NO_QUEUE_FLUSH: ON
9214 13:59:23.500052 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9215 13:59:23.503105 ENABLE_DFS_RUNTIME_MRW: OFF
9216 13:59:23.503517 DDR_RESERVE_NEW_MODE: ON
9217 13:59:23.506562 MR_CBT_SWITCH_FREQ: ON
9218 13:59:23.509945 =========================
9219 13:59:23.528048 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9220 13:59:23.531523 dram_init: ddr_geometry: 2
9221 13:59:23.549494 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9222 13:59:23.552699 dram_init: dram init end (result: 0)
9223 13:59:23.559710 DRAM-K: Full calibration passed in 24596 msecs
9224 13:59:23.562904 MRC: failed to locate region type 0.
9225 13:59:23.563265 DRAM rank0 size:0x100000000,
9226 13:59:23.566124 DRAM rank1 size=0x100000000
9227 13:59:23.575865 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9228 13:59:23.582586 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9229 13:59:23.589041 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9230 13:59:23.595811 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9231 13:59:23.599298 DRAM rank0 size:0x100000000,
9232 13:59:23.602399 DRAM rank1 size=0x100000000
9233 13:59:23.602691 CBMEM:
9234 13:59:23.605667 IMD: root @ 0xfffff000 254 entries.
9235 13:59:23.609518 IMD: root @ 0xffffec00 62 entries.
9236 13:59:23.612433 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9237 13:59:23.615912 WARNING: RO_VPD is uninitialized or empty.
9238 13:59:23.622272 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9239 13:59:23.629717 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9240 13:59:23.642196 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9241 13:59:23.653556 BS: romstage times (exec / console): total (unknown) / 24057 ms
9242 13:59:23.653867
9243 13:59:23.654112
9244 13:59:23.663601 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9245 13:59:23.666937 ARM64: Exception handlers installed.
9246 13:59:23.670401 ARM64: Testing exception
9247 13:59:23.673480 ARM64: Done test exception
9248 13:59:23.673809 Enumerating buses...
9249 13:59:23.677015 Show all devs... Before device enumeration.
9250 13:59:23.680424 Root Device: enabled 1
9251 13:59:23.683903 CPU_CLUSTER: 0: enabled 1
9252 13:59:23.684336 CPU: 00: enabled 1
9253 13:59:23.686792 Compare with tree...
9254 13:59:23.687245 Root Device: enabled 1
9255 13:59:23.690213 CPU_CLUSTER: 0: enabled 1
9256 13:59:23.693750 CPU: 00: enabled 1
9257 13:59:23.694131 Root Device scanning...
9258 13:59:23.696696 scan_static_bus for Root Device
9259 13:59:23.699957 CPU_CLUSTER: 0 enabled
9260 13:59:23.703616 scan_static_bus for Root Device done
9261 13:59:23.707176 scan_bus: bus Root Device finished in 8 msecs
9262 13:59:23.707631 done
9263 13:59:23.713471 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9264 13:59:23.716920 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9265 13:59:23.723485 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9266 13:59:23.726544 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9267 13:59:23.730170 Allocating resources...
9268 13:59:23.733614 Reading resources...
9269 13:59:23.737436 Root Device read_resources bus 0 link: 0
9270 13:59:23.737988 DRAM rank0 size:0x100000000,
9271 13:59:23.740008 DRAM rank1 size=0x100000000
9272 13:59:23.743639 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9273 13:59:23.746591 CPU: 00 missing read_resources
9274 13:59:23.750052 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9275 13:59:23.756568 Root Device read_resources bus 0 link: 0 done
9276 13:59:23.756975 Done reading resources.
9277 13:59:23.763086 Show resources in subtree (Root Device)...After reading.
9278 13:59:23.766776 Root Device child on link 0 CPU_CLUSTER: 0
9279 13:59:23.770301 CPU_CLUSTER: 0 child on link 0 CPU: 00
9280 13:59:23.780181 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9281 13:59:23.780571 CPU: 00
9282 13:59:23.783336 Root Device assign_resources, bus 0 link: 0
9283 13:59:23.786685 CPU_CLUSTER: 0 missing set_resources
9284 13:59:23.793148 Root Device assign_resources, bus 0 link: 0 done
9285 13:59:23.793543 Done setting resources.
9286 13:59:23.800382 Show resources in subtree (Root Device)...After assigning values.
9287 13:59:23.802945 Root Device child on link 0 CPU_CLUSTER: 0
9288 13:59:23.806310 CPU_CLUSTER: 0 child on link 0 CPU: 00
9289 13:59:23.816683 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9290 13:59:23.817073 CPU: 00
9291 13:59:23.819654 Done allocating resources.
9292 13:59:23.823217 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9293 13:59:23.826585 Enabling resources...
9294 13:59:23.826972 done.
9295 13:59:23.832925 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9296 13:59:23.833322 Initializing devices...
9297 13:59:23.836545 Root Device init
9298 13:59:23.836928 init hardware done!
9299 13:59:23.839594 0x00000018: ctrlr->caps
9300 13:59:23.843491 52.000 MHz: ctrlr->f_max
9301 13:59:23.843885 0.400 MHz: ctrlr->f_min
9302 13:59:23.846397 0x40ff8080: ctrlr->voltages
9303 13:59:23.846901 sclk: 390625
9304 13:59:23.849881 Bus Width = 1
9305 13:59:23.850287 sclk: 390625
9306 13:59:23.853255 Bus Width = 1
9307 13:59:23.853636 Early init status = 3
9308 13:59:23.859371 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9309 13:59:23.862826 in-header: 03 fc 00 00 01 00 00 00
9310 13:59:23.863299 in-data: 00
9311 13:59:23.869388 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9312 13:59:23.873503 in-header: 03 fd 00 00 00 00 00 00
9313 13:59:23.876636 in-data:
9314 13:59:23.879979 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9315 13:59:23.884302 in-header: 03 fc 00 00 01 00 00 00
9316 13:59:23.887351 in-data: 00
9317 13:59:23.890941 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9318 13:59:23.896666 in-header: 03 fd 00 00 00 00 00 00
9319 13:59:23.899700 in-data:
9320 13:59:23.903292 [SSUSB] Setting up USB HOST controller...
9321 13:59:23.906158 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9322 13:59:23.910134 [SSUSB] phy power-on done.
9323 13:59:23.913036 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9324 13:59:23.919676 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9325 13:59:23.922990 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9326 13:59:23.929421 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9327 13:59:23.936321 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9328 13:59:23.942650 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9329 13:59:23.949509 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9330 13:59:23.955965 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9331 13:59:23.959297 SPM: binary array size = 0x9dc
9332 13:59:23.962752 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9333 13:59:23.969413 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9334 13:59:23.975904 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9335 13:59:23.982712 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9336 13:59:23.986042 configure_display: Starting display init
9337 13:59:24.019426 anx7625_power_on_init: Init interface.
9338 13:59:24.022766 anx7625_disable_pd_protocol: Disabled PD feature.
9339 13:59:24.026196 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9340 13:59:24.054123 anx7625_start_dp_work: Secure OCM version=00
9341 13:59:24.057391 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9342 13:59:24.071925 sp_tx_get_edid_block: EDID Block = 1
9343 13:59:24.174581 Extracted contents:
9344 13:59:24.177995 header: 00 ff ff ff ff ff ff 00
9345 13:59:24.181232 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9346 13:59:24.184857 version: 01 04
9347 13:59:24.187821 basic params: 95 1f 11 78 0a
9348 13:59:24.191101 chroma info: 76 90 94 55 54 90 27 21 50 54
9349 13:59:24.194706 established: 00 00 00
9350 13:59:24.201120 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9351 13:59:24.204511 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9352 13:59:24.210868 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 13:59:24.217988 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9354 13:59:24.224188 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9355 13:59:24.227533 extensions: 00
9356 13:59:24.227964 checksum: fb
9357 13:59:24.228295
9358 13:59:24.230965 Manufacturer: IVO Model 57d Serial Number 0
9359 13:59:24.234099 Made week 0 of 2020
9360 13:59:24.234603 EDID version: 1.4
9361 13:59:24.237516 Digital display
9362 13:59:24.240963 6 bits per primary color channel
9363 13:59:24.241537 DisplayPort interface
9364 13:59:24.244041 Maximum image size: 31 cm x 17 cm
9365 13:59:24.247382 Gamma: 220%
9366 13:59:24.247968 Check DPMS levels
9367 13:59:24.251081 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9368 13:59:24.257081 First detailed timing is preferred timing
9369 13:59:24.257650 Established timings supported:
9370 13:59:24.260961 Standard timings supported:
9371 13:59:24.263718 Detailed timings
9372 13:59:24.267450 Hex of detail: 383680a07038204018303c0035ae10000019
9373 13:59:24.273935 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9374 13:59:24.277677 0780 0798 07c8 0820 hborder 0
9375 13:59:24.280333 0438 043b 0447 0458 vborder 0
9376 13:59:24.284068 -hsync -vsync
9377 13:59:24.284484 Did detailed timing
9378 13:59:24.290417 Hex of detail: 000000000000000000000000000000000000
9379 13:59:24.294023 Manufacturer-specified data, tag 0
9380 13:59:24.297337 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9381 13:59:24.300210 ASCII string: InfoVision
9382 13:59:24.303867 Hex of detail: 000000fe00523134304e574635205248200a
9383 13:59:24.307657 ASCII string: R140NWF5 RH
9384 13:59:24.308067 Checksum
9385 13:59:24.310077 Checksum: 0xfb (valid)
9386 13:59:24.313530 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9387 13:59:24.317128 DSI data_rate: 832800000 bps
9388 13:59:24.323358 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9389 13:59:24.326904 anx7625_parse_edid: pixelclock(138800).
9390 13:59:24.330551 hactive(1920), hsync(48), hfp(24), hbp(88)
9391 13:59:24.333686 vactive(1080), vsync(12), vfp(3), vbp(17)
9392 13:59:24.336667 anx7625_dsi_config: config dsi.
9393 13:59:24.343058 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9394 13:59:24.356666 anx7625_dsi_config: success to config DSI
9395 13:59:24.360535 anx7625_dp_start: MIPI phy setup OK.
9396 13:59:24.363224 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9397 13:59:24.366976 mtk_ddp_mode_set invalid vrefresh 60
9398 13:59:24.370146 main_disp_path_setup
9399 13:59:24.370370 ovl_layer_smi_id_en
9400 13:59:24.373370 ovl_layer_smi_id_en
9401 13:59:24.373593 ccorr_config
9402 13:59:24.373781 aal_config
9403 13:59:24.376548 gamma_config
9404 13:59:24.376765 postmask_config
9405 13:59:24.379648 dither_config
9406 13:59:24.383411 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9407 13:59:24.389843 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9408 13:59:24.393221 Root Device init finished in 554 msecs
9409 13:59:24.393405 CPU_CLUSTER: 0 init
9410 13:59:24.402837 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9411 13:59:24.406549 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9412 13:59:24.409725 APU_MBOX 0x190000b0 = 0x10001
9413 13:59:24.413293 APU_MBOX 0x190001b0 = 0x10001
9414 13:59:24.416589 APU_MBOX 0x190005b0 = 0x10001
9415 13:59:24.419643 APU_MBOX 0x190006b0 = 0x10001
9416 13:59:24.422791 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9417 13:59:24.435732 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9418 13:59:24.448403 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9419 13:59:24.455124 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9420 13:59:24.466496 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9421 13:59:24.475611 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9422 13:59:24.478818 CPU_CLUSTER: 0 init finished in 81 msecs
9423 13:59:24.482352 Devices initialized
9424 13:59:24.485658 Show all devs... After init.
9425 13:59:24.486127 Root Device: enabled 1
9426 13:59:24.489029 CPU_CLUSTER: 0: enabled 1
9427 13:59:24.492436 CPU: 00: enabled 1
9428 13:59:24.495680 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9429 13:59:24.498811 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9430 13:59:24.502182 ELOG: NV offset 0x57f000 size 0x1000
9431 13:59:24.508861 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9432 13:59:24.515222 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9433 13:59:24.519115 ELOG: Event(17) added with size 13 at 2023-09-21 13:59:27 UTC
9434 13:59:24.521978 out: cmd=0x121: 03 db 21 01 00 00 00 00
9435 13:59:24.525947 in-header: 03 43 00 00 2c 00 00 00
9436 13:59:24.539344 in-data: 1b 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9437 13:59:24.545838 ELOG: Event(A1) added with size 10 at 2023-09-21 13:59:27 UTC
9438 13:59:24.552356 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9439 13:59:24.559299 ELOG: Event(A0) added with size 9 at 2023-09-21 13:59:27 UTC
9440 13:59:24.562667 elog_add_boot_reason: Logged dev mode boot
9441 13:59:24.565723 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9442 13:59:24.569272 Finalize devices...
9443 13:59:24.569747 Devices finalized
9444 13:59:24.575962 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9445 13:59:24.579272 Writing coreboot table at 0xffe64000
9446 13:59:24.582301 0. 000000000010a000-0000000000113fff: RAMSTAGE
9447 13:59:24.585431 1. 0000000040000000-00000000400fffff: RAM
9448 13:59:24.588736 2. 0000000040100000-000000004032afff: RAMSTAGE
9449 13:59:24.595516 3. 000000004032b000-00000000545fffff: RAM
9450 13:59:24.599250 4. 0000000054600000-000000005465ffff: BL31
9451 13:59:24.602650 5. 0000000054660000-00000000ffe63fff: RAM
9452 13:59:24.605970 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9453 13:59:24.612353 7. 0000000100000000-000000023fffffff: RAM
9454 13:59:24.612911 Passing 5 GPIOs to payload:
9455 13:59:24.618610 NAME | PORT | POLARITY | VALUE
9456 13:59:24.622073 EC in RW | 0x000000aa | low | undefined
9457 13:59:24.628977 EC interrupt | 0x00000005 | low | undefined
9458 13:59:24.631997 TPM interrupt | 0x000000ab | high | undefined
9459 13:59:24.635495 SD card detect | 0x00000011 | high | undefined
9460 13:59:24.642118 speaker enable | 0x00000093 | high | undefined
9461 13:59:24.645428 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9462 13:59:24.648994 in-header: 03 f9 00 00 02 00 00 00
9463 13:59:24.649461 in-data: 02 00
9464 13:59:24.651723 ADC[4]: Raw value=895191 ID=7
9465 13:59:24.655370 ADC[3]: Raw value=213070 ID=1
9466 13:59:24.655935 RAM Code: 0x71
9467 13:59:24.658685 ADC[6]: Raw value=74722 ID=0
9468 13:59:24.662050 ADC[5]: Raw value=211960 ID=1
9469 13:59:24.662516 SKU Code: 0x1
9470 13:59:24.669043 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 360f
9471 13:59:24.671892 coreboot table: 964 bytes.
9472 13:59:24.675087 IMD ROOT 0. 0xfffff000 0x00001000
9473 13:59:24.678429 IMD SMALL 1. 0xffffe000 0x00001000
9474 13:59:24.681617 RO MCACHE 2. 0xffffc000 0x00001104
9475 13:59:24.685294 CONSOLE 3. 0xfff7c000 0x00080000
9476 13:59:24.688549 FMAP 4. 0xfff7b000 0x00000452
9477 13:59:24.691729 TIME STAMP 5. 0xfff7a000 0x00000910
9478 13:59:24.695209 VBOOT WORK 6. 0xfff66000 0x00014000
9479 13:59:24.698308 RAMOOPS 7. 0xffe66000 0x00100000
9480 13:59:24.701806 COREBOOT 8. 0xffe64000 0x00002000
9481 13:59:24.702364 IMD small region:
9482 13:59:24.705025 IMD ROOT 0. 0xffffec00 0x00000400
9483 13:59:24.708363 VPD 1. 0xffffeb80 0x0000006c
9484 13:59:24.711173 MMC STATUS 2. 0xffffeb60 0x00000004
9485 13:59:24.718095 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9486 13:59:24.721483 Probing TPM: done!
9487 13:59:24.724798 Connected to device vid:did:rid of 1ae0:0028:00
9488 13:59:24.734795 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9489 13:59:24.738029 Initialized TPM device CR50 revision 0
9490 13:59:24.742545 Checking cr50 for pending updates
9491 13:59:24.745894 Reading cr50 TPM mode
9492 13:59:24.753715 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9493 13:59:24.760427 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9494 13:59:24.800909 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9495 13:59:24.803682 Checking segment from ROM address 0x40100000
9496 13:59:24.807253 Checking segment from ROM address 0x4010001c
9497 13:59:24.813680 Loading segment from ROM address 0x40100000
9498 13:59:24.814192 code (compression=0)
9499 13:59:24.823889 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9500 13:59:24.830392 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9501 13:59:24.830814 it's not compressed!
9502 13:59:24.836961 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9503 13:59:24.843584 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9504 13:59:24.860984 Loading segment from ROM address 0x4010001c
9505 13:59:24.861434 Entry Point 0x80000000
9506 13:59:24.864362 Loaded segments
9507 13:59:24.867867 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9508 13:59:24.874310 Jumping to boot code at 0x80000000(0xffe64000)
9509 13:59:24.880657 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9510 13:59:24.887477 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9511 13:59:24.895342 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9512 13:59:24.898827 Checking segment from ROM address 0x40100000
9513 13:59:24.901893 Checking segment from ROM address 0x4010001c
9514 13:59:24.908630 Loading segment from ROM address 0x40100000
9515 13:59:24.909057 code (compression=1)
9516 13:59:24.915528 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9517 13:59:24.925688 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9518 13:59:24.926190 using LZMA
9519 13:59:24.933688 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9520 13:59:24.940250 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9521 13:59:24.943966 Loading segment from ROM address 0x4010001c
9522 13:59:24.944388 Entry Point 0x54601000
9523 13:59:24.947486 Loaded segments
9524 13:59:24.950734 NOTICE: MT8192 bl31_setup
9525 13:59:24.957438 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9526 13:59:24.960613 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9527 13:59:24.964002 WARNING: region 0:
9528 13:59:24.967490 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 13:59:24.967922 WARNING: region 1:
9530 13:59:24.973969 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9531 13:59:24.977455 WARNING: region 2:
9532 13:59:24.980727 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9533 13:59:24.984013 WARNING: region 3:
9534 13:59:24.987166 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 13:59:24.990926 WARNING: region 4:
9536 13:59:24.997739 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 13:59:24.998256 WARNING: region 5:
9538 13:59:25.001009 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 13:59:25.004198 WARNING: region 6:
9540 13:59:25.007796 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 13:59:25.008455 WARNING: region 7:
9542 13:59:25.014326 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 13:59:25.020805 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9544 13:59:25.024186 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9545 13:59:25.027720 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9546 13:59:25.034012 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9547 13:59:25.037464 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9548 13:59:25.041020 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9549 13:59:25.047715 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9550 13:59:25.051035 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9551 13:59:25.057793 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9552 13:59:25.060569 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9553 13:59:25.064015 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9554 13:59:25.071002 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9555 13:59:25.074002 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9556 13:59:25.077665 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9557 13:59:25.084895 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9558 13:59:25.087983 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9559 13:59:25.091154 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9560 13:59:25.097638 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9561 13:59:25.100833 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9562 13:59:25.104102 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9563 13:59:25.110766 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9564 13:59:25.113876 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9565 13:59:25.121037 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9566 13:59:25.124187 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9567 13:59:25.130742 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9568 13:59:25.134083 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9569 13:59:25.137619 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9570 13:59:25.144408 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9571 13:59:25.147430 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9572 13:59:25.150904 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9573 13:59:25.157484 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9574 13:59:25.160859 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9575 13:59:25.164579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9576 13:59:25.170743 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9577 13:59:25.174062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9578 13:59:25.177775 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9579 13:59:25.181057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9580 13:59:25.187499 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9581 13:59:25.190922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9582 13:59:25.194473 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9583 13:59:25.197279 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9584 13:59:25.203998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9585 13:59:25.207603 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9586 13:59:25.210873 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9587 13:59:25.214458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9588 13:59:25.221283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9589 13:59:25.224390 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9590 13:59:25.227934 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9591 13:59:25.234555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9592 13:59:25.237359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9593 13:59:25.244042 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9594 13:59:25.247644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9595 13:59:25.250840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9596 13:59:25.257247 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9597 13:59:25.260532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9598 13:59:25.267180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9599 13:59:25.271215 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9600 13:59:25.273851 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9601 13:59:25.281121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9602 13:59:25.284043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9603 13:59:25.290779 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9604 13:59:25.294359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9605 13:59:25.300711 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9606 13:59:25.304245 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9607 13:59:25.310648 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9608 13:59:25.314140 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9609 13:59:25.317468 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9610 13:59:25.324402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9611 13:59:25.327447 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9612 13:59:25.334360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9613 13:59:25.337723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9614 13:59:25.344296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9615 13:59:25.347505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9616 13:59:25.351095 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9617 13:59:25.357871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9618 13:59:25.360960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9619 13:59:25.367345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9620 13:59:25.370859 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9621 13:59:25.377868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9622 13:59:25.380466 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9623 13:59:25.387118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9624 13:59:25.391063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9625 13:59:25.394499 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9626 13:59:25.401230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9627 13:59:25.403959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9628 13:59:25.410502 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9629 13:59:25.413785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9630 13:59:25.417599 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9631 13:59:25.423840 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9632 13:59:25.427416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9633 13:59:25.434202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9634 13:59:25.437384 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9635 13:59:25.443600 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9636 13:59:25.447417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9637 13:59:25.453796 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9638 13:59:25.457157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9639 13:59:25.460787 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9640 13:59:25.467031 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9641 13:59:25.470567 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9642 13:59:25.474172 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9643 13:59:25.476911 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9644 13:59:25.484188 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9645 13:59:25.487449 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9646 13:59:25.493790 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9647 13:59:25.497337 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9648 13:59:25.500776 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9649 13:59:25.507071 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9650 13:59:25.510325 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9651 13:59:25.513871 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9652 13:59:25.520827 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9653 13:59:25.524200 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9654 13:59:25.530926 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9655 13:59:25.534080 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9656 13:59:25.537470 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9657 13:59:25.544019 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9658 13:59:25.547501 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9659 13:59:25.550989 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9660 13:59:25.557477 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9661 13:59:25.561225 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9662 13:59:25.564286 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9663 13:59:25.567867 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9664 13:59:25.574323 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9665 13:59:25.577207 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9666 13:59:25.580668 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9667 13:59:25.587172 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9668 13:59:25.590452 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9669 13:59:25.594063 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9670 13:59:25.600860 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9671 13:59:25.603982 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9672 13:59:25.610658 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9673 13:59:25.614082 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9674 13:59:25.617325 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9675 13:59:25.624165 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9676 13:59:25.627170 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9677 13:59:25.633992 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9678 13:59:25.637214 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9679 13:59:25.640980 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9680 13:59:25.647619 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9681 13:59:25.650630 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9682 13:59:25.653746 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9683 13:59:25.660699 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9684 13:59:25.664114 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9685 13:59:25.670870 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9686 13:59:25.673829 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9687 13:59:25.677177 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9688 13:59:25.684287 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9689 13:59:25.687775 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9690 13:59:25.693891 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9691 13:59:25.697351 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9692 13:59:25.700722 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9693 13:59:25.707449 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9694 13:59:25.710715 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9695 13:59:25.714180 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9696 13:59:25.720475 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9697 13:59:25.724110 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9698 13:59:25.730584 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9699 13:59:25.733882 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9700 13:59:25.737201 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9701 13:59:25.744129 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9702 13:59:25.747097 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9703 13:59:25.754345 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9704 13:59:25.757095 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9705 13:59:25.761012 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9706 13:59:25.767292 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9707 13:59:25.770370 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9708 13:59:25.773709 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9709 13:59:25.780263 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9710 13:59:25.783765 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9711 13:59:25.790819 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9712 13:59:25.793602 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9713 13:59:25.800175 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9714 13:59:25.803660 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9715 13:59:25.806825 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9716 13:59:25.813333 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9717 13:59:25.816543 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9718 13:59:25.820199 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9719 13:59:25.827076 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9720 13:59:25.829745 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9721 13:59:25.836583 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9722 13:59:25.839921 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9723 13:59:25.843457 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9724 13:59:25.849855 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9725 13:59:25.853065 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9726 13:59:25.860181 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9727 13:59:25.862977 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9728 13:59:25.866312 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9729 13:59:25.872976 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9730 13:59:25.876362 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9731 13:59:25.883233 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9732 13:59:25.886350 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9733 13:59:25.889851 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9734 13:59:25.896414 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9735 13:59:25.899962 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9736 13:59:25.906187 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9737 13:59:25.909792 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9738 13:59:25.916391 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9739 13:59:25.919523 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9740 13:59:25.922540 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9741 13:59:25.929527 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9742 13:59:25.932893 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9743 13:59:25.939181 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9744 13:59:25.942747 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9745 13:59:25.946132 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9746 13:59:25.952398 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9747 13:59:25.955671 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9748 13:59:25.962594 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9749 13:59:25.966110 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9750 13:59:25.972883 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9751 13:59:25.975861 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9752 13:59:25.979108 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9753 13:59:25.985787 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9754 13:59:25.989294 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9755 13:59:25.995549 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9756 13:59:25.998645 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9757 13:59:26.005575 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9758 13:59:26.008547 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9759 13:59:26.012219 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9760 13:59:26.018962 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9761 13:59:26.021880 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9762 13:59:26.028798 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9763 13:59:26.032332 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9764 13:59:26.038661 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9765 13:59:26.042230 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9766 13:59:26.044932 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9767 13:59:26.051837 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9768 13:59:26.055161 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9769 13:59:26.061997 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9770 13:59:26.064877 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9771 13:59:26.068554 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9772 13:59:26.075287 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9773 13:59:26.078664 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9774 13:59:26.081786 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9775 13:59:26.085149 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9776 13:59:26.088450 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9777 13:59:26.095481 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9778 13:59:26.098273 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9779 13:59:26.104959 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9780 13:59:26.108444 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9781 13:59:26.111362 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9782 13:59:26.117947 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9783 13:59:26.121477 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9784 13:59:26.127951 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9785 13:59:26.131825 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9786 13:59:26.134760 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9787 13:59:26.141235 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9788 13:59:26.144543 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9789 13:59:26.148056 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9790 13:59:26.154397 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9791 13:59:26.157912 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9792 13:59:26.161445 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9793 13:59:26.167675 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9794 13:59:26.171159 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9795 13:59:26.178197 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9796 13:59:26.181482 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9797 13:59:26.184377 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9798 13:59:26.191281 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9799 13:59:26.194398 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9800 13:59:26.197544 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9801 13:59:26.204457 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9802 13:59:26.207658 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9803 13:59:26.211028 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9804 13:59:26.217538 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9805 13:59:26.221219 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9806 13:59:26.224204 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9807 13:59:26.231222 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9808 13:59:26.234406 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9809 13:59:26.241091 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9810 13:59:26.244678 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9811 13:59:26.247641 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9812 13:59:26.254532 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9813 13:59:26.257556 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9814 13:59:26.261368 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9815 13:59:26.264230 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9816 13:59:26.267491 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9817 13:59:26.273936 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9818 13:59:26.277313 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9819 13:59:26.280554 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9820 13:59:26.284045 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9821 13:59:26.290549 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9822 13:59:26.293570 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9823 13:59:26.297015 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9824 13:59:26.303826 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9825 13:59:26.307286 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9826 13:59:26.310322 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9827 13:59:26.317186 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9828 13:59:26.320555 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9829 13:59:26.327261 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9830 13:59:26.330222 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9831 13:59:26.337197 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9832 13:59:26.340258 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9833 13:59:26.343554 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9834 13:59:26.350342 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9835 13:59:26.353733 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9836 13:59:26.360524 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9837 13:59:26.363663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9838 13:59:26.367197 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9839 13:59:26.373592 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9840 13:59:26.376984 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9841 13:59:26.383094 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9842 13:59:26.386484 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9843 13:59:26.390033 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9844 13:59:26.396271 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9845 13:59:26.399569 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9846 13:59:26.406588 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9847 13:59:26.410072 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9848 13:59:26.412930 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9849 13:59:26.419524 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9850 13:59:26.423063 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9851 13:59:26.429577 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9852 13:59:26.433001 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9853 13:59:26.439751 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9854 13:59:26.443277 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9855 13:59:26.446623 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9856 13:59:26.452966 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9857 13:59:26.456131 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9858 13:59:26.462689 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9859 13:59:26.465927 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9860 13:59:26.469347 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9861 13:59:26.476372 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9862 13:59:26.479620 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9863 13:59:26.486012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9864 13:59:26.489526 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9865 13:59:26.492880 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9866 13:59:26.499901 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9867 13:59:26.502985 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9868 13:59:26.509334 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9869 13:59:26.512670 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9870 13:59:26.519545 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9871 13:59:26.522807 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9872 13:59:26.525827 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9873 13:59:26.532506 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9874 13:59:26.535856 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9875 13:59:26.542472 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9876 13:59:26.545663 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9877 13:59:26.549149 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9878 13:59:26.555891 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9879 13:59:26.559029 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9880 13:59:26.562924 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9881 13:59:26.569510 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9882 13:59:26.572406 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9883 13:59:26.579224 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9884 13:59:26.582432 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9885 13:59:26.588970 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9886 13:59:26.592061 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9887 13:59:26.598988 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9888 13:59:26.602012 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9889 13:59:26.605520 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9890 13:59:26.611975 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9891 13:59:26.615416 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9892 13:59:26.622396 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9893 13:59:26.624977 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9894 13:59:26.628738 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9895 13:59:26.635426 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9896 13:59:26.638544 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9897 13:59:26.645164 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9898 13:59:26.648462 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9899 13:59:26.651713 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9900 13:59:26.658325 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9901 13:59:26.661576 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9902 13:59:26.668268 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9903 13:59:26.672267 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9904 13:59:26.678970 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9905 13:59:26.681607 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9906 13:59:26.688085 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9907 13:59:26.691459 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9908 13:59:26.695061 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9909 13:59:26.701664 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9910 13:59:26.704642 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9911 13:59:26.711954 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9912 13:59:26.714504 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9913 13:59:26.721332 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9914 13:59:26.724709 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9915 13:59:26.730999 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9916 13:59:26.734579 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9917 13:59:26.737893 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9918 13:59:26.744419 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9919 13:59:26.747690 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9920 13:59:26.754171 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9921 13:59:26.757539 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9922 13:59:26.764376 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9923 13:59:26.767494 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9924 13:59:26.771156 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9925 13:59:26.777355 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9926 13:59:26.781003 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9927 13:59:26.787654 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9928 13:59:26.791074 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9929 13:59:26.797944 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9930 13:59:26.801369 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9931 13:59:26.804489 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9932 13:59:26.811420 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9933 13:59:26.814651 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9934 13:59:26.820918 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9935 13:59:26.824110 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9936 13:59:26.827769 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9937 13:59:26.834647 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9938 13:59:26.837683 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9939 13:59:26.844388 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9940 13:59:26.847939 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9941 13:59:26.854155 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9942 13:59:26.857713 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9943 13:59:26.864415 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9944 13:59:26.867621 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9945 13:59:26.870781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9946 13:59:26.877320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9947 13:59:26.880574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9948 13:59:26.887213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9949 13:59:26.890538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9950 13:59:26.897215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9951 13:59:26.900486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9952 13:59:26.907025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9953 13:59:26.910970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9954 13:59:26.917031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9955 13:59:26.920724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9956 13:59:26.927196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9957 13:59:26.930349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9958 13:59:26.937300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9959 13:59:26.940877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9960 13:59:26.947138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9961 13:59:26.950922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9962 13:59:26.953742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9963 13:59:26.960307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9964 13:59:26.963823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9965 13:59:26.970168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9966 13:59:26.973765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9967 13:59:26.980560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9968 13:59:26.983332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9969 13:59:26.990066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9970 13:59:26.993465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9971 13:59:27.000213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9972 13:59:27.003700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9973 13:59:27.010199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9974 13:59:27.013167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9975 13:59:27.020011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9976 13:59:27.023535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9977 13:59:27.029812 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9978 13:59:27.030218 INFO: [APUAPC] vio 0
9979 13:59:27.037198 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9980 13:59:27.040669 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9981 13:59:27.043972 INFO: [APUAPC] D0_APC_0: 0x400510
9982 13:59:27.047523 INFO: [APUAPC] D0_APC_1: 0x0
9983 13:59:27.050503 INFO: [APUAPC] D0_APC_2: 0x1540
9984 13:59:27.053537 INFO: [APUAPC] D0_APC_3: 0x0
9985 13:59:27.056869 INFO: [APUAPC] D1_APC_0: 0xffffffff
9986 13:59:27.060418 INFO: [APUAPC] D1_APC_1: 0xffffffff
9987 13:59:27.063825 INFO: [APUAPC] D1_APC_2: 0x3fffff
9988 13:59:27.067220 INFO: [APUAPC] D1_APC_3: 0x0
9989 13:59:27.070662 INFO: [APUAPC] D2_APC_0: 0xffffffff
9990 13:59:27.073422 INFO: [APUAPC] D2_APC_1: 0xffffffff
9991 13:59:27.076813 INFO: [APUAPC] D2_APC_2: 0x3fffff
9992 13:59:27.080354 INFO: [APUAPC] D2_APC_3: 0x0
9993 13:59:27.083900 INFO: [APUAPC] D3_APC_0: 0xffffffff
9994 13:59:27.087282 INFO: [APUAPC] D3_APC_1: 0xffffffff
9995 13:59:27.090073 INFO: [APUAPC] D3_APC_2: 0x3fffff
9996 13:59:27.093428 INFO: [APUAPC] D3_APC_3: 0x0
9997 13:59:27.097236 INFO: [APUAPC] D4_APC_0: 0xffffffff
9998 13:59:27.100411 INFO: [APUAPC] D4_APC_1: 0xffffffff
9999 13:59:27.103910 INFO: [APUAPC] D4_APC_2: 0x3fffff
10000 13:59:27.104280 INFO: [APUAPC] D4_APC_3: 0x0
10001 13:59:27.106701 INFO: [APUAPC] D5_APC_0: 0xffffffff
10002 13:59:27.110058 INFO: [APUAPC] D5_APC_1: 0xffffffff
10003 13:59:27.113503 INFO: [APUAPC] D5_APC_2: 0x3fffff
10004 13:59:27.116975 INFO: [APUAPC] D5_APC_3: 0x0
10005 13:59:27.120353 INFO: [APUAPC] D6_APC_0: 0xffffffff
10006 13:59:27.123481 INFO: [APUAPC] D6_APC_1: 0xffffffff
10007 13:59:27.127100 INFO: [APUAPC] D6_APC_2: 0x3fffff
10008 13:59:27.130198 INFO: [APUAPC] D6_APC_3: 0x0
10009 13:59:27.133544 INFO: [APUAPC] D7_APC_0: 0xffffffff
10010 13:59:27.137111 INFO: [APUAPC] D7_APC_1: 0xffffffff
10011 13:59:27.139864 INFO: [APUAPC] D7_APC_2: 0x3fffff
10012 13:59:27.143651 INFO: [APUAPC] D7_APC_3: 0x0
10013 13:59:27.146996 INFO: [APUAPC] D8_APC_0: 0xffffffff
10014 13:59:27.150627 INFO: [APUAPC] D8_APC_1: 0xffffffff
10015 13:59:27.153740 INFO: [APUAPC] D8_APC_2: 0x3fffff
10016 13:59:27.156505 INFO: [APUAPC] D8_APC_3: 0x0
10017 13:59:27.160091 INFO: [APUAPC] D9_APC_0: 0xffffffff
10018 13:59:27.163494 INFO: [APUAPC] D9_APC_1: 0xffffffff
10019 13:59:27.166883 INFO: [APUAPC] D9_APC_2: 0x3fffff
10020 13:59:27.169981 INFO: [APUAPC] D9_APC_3: 0x0
10021 13:59:27.173379 INFO: [APUAPC] D10_APC_0: 0xffffffff
10022 13:59:27.176385 INFO: [APUAPC] D10_APC_1: 0xffffffff
10023 13:59:27.180476 INFO: [APUAPC] D10_APC_2: 0x3fffff
10024 13:59:27.183116 INFO: [APUAPC] D10_APC_3: 0x0
10025 13:59:27.186613 INFO: [APUAPC] D11_APC_0: 0xffffffff
10026 13:59:27.190055 INFO: [APUAPC] D11_APC_1: 0xffffffff
10027 13:59:27.193129 INFO: [APUAPC] D11_APC_2: 0x3fffff
10028 13:59:27.196449 INFO: [APUAPC] D11_APC_3: 0x0
10029 13:59:27.200128 INFO: [APUAPC] D12_APC_0: 0xffffffff
10030 13:59:27.203193 INFO: [APUAPC] D12_APC_1: 0xffffffff
10031 13:59:27.206335 INFO: [APUAPC] D12_APC_2: 0x3fffff
10032 13:59:27.209740 INFO: [APUAPC] D12_APC_3: 0x0
10033 13:59:27.212974 INFO: [APUAPC] D13_APC_0: 0xffffffff
10034 13:59:27.216529 INFO: [APUAPC] D13_APC_1: 0xffffffff
10035 13:59:27.220282 INFO: [APUAPC] D13_APC_2: 0x3fffff
10036 13:59:27.223540 INFO: [APUAPC] D13_APC_3: 0x0
10037 13:59:27.227091 INFO: [APUAPC] D14_APC_0: 0xffffffff
10038 13:59:27.229662 INFO: [APUAPC] D14_APC_1: 0xffffffff
10039 13:59:27.233742 INFO: [APUAPC] D14_APC_2: 0x3fffff
10040 13:59:27.236295 INFO: [APUAPC] D14_APC_3: 0x0
10041 13:59:27.239656 INFO: [APUAPC] D15_APC_0: 0xffffffff
10042 13:59:27.243065 INFO: [APUAPC] D15_APC_1: 0xffffffff
10043 13:59:27.246598 INFO: [APUAPC] D15_APC_2: 0x3fffff
10044 13:59:27.250082 INFO: [APUAPC] D15_APC_3: 0x0
10045 13:59:27.253486 INFO: [APUAPC] APC_CON: 0x4
10046 13:59:27.256427 INFO: [NOCDAPC] D0_APC_0: 0x0
10047 13:59:27.259510 INFO: [NOCDAPC] D0_APC_1: 0x0
10048 13:59:27.262709 INFO: [NOCDAPC] D1_APC_0: 0x0
10049 13:59:27.266429 INFO: [NOCDAPC] D1_APC_1: 0xfff
10050 13:59:27.266782 INFO: [NOCDAPC] D2_APC_0: 0x0
10051 13:59:27.269391 INFO: [NOCDAPC] D2_APC_1: 0xfff
10052 13:59:27.272696 INFO: [NOCDAPC] D3_APC_0: 0x0
10053 13:59:27.276364 INFO: [NOCDAPC] D3_APC_1: 0xfff
10054 13:59:27.279163 INFO: [NOCDAPC] D4_APC_0: 0x0
10055 13:59:27.283120 INFO: [NOCDAPC] D4_APC_1: 0xfff
10056 13:59:27.285790 INFO: [NOCDAPC] D5_APC_0: 0x0
10057 13:59:27.289319 INFO: [NOCDAPC] D5_APC_1: 0xfff
10058 13:59:27.292695 INFO: [NOCDAPC] D6_APC_0: 0x0
10059 13:59:27.296062 INFO: [NOCDAPC] D6_APC_1: 0xfff
10060 13:59:27.299179 INFO: [NOCDAPC] D7_APC_0: 0x0
10061 13:59:27.302842 INFO: [NOCDAPC] D7_APC_1: 0xfff
10062 13:59:27.303301 INFO: [NOCDAPC] D8_APC_0: 0x0
10063 13:59:27.306254 INFO: [NOCDAPC] D8_APC_1: 0xfff
10064 13:59:27.309384 INFO: [NOCDAPC] D9_APC_0: 0x0
10065 13:59:27.312457 INFO: [NOCDAPC] D9_APC_1: 0xfff
10066 13:59:27.316312 INFO: [NOCDAPC] D10_APC_0: 0x0
10067 13:59:27.319162 INFO: [NOCDAPC] D10_APC_1: 0xfff
10068 13:59:27.322563 INFO: [NOCDAPC] D11_APC_0: 0x0
10069 13:59:27.326231 INFO: [NOCDAPC] D11_APC_1: 0xfff
10070 13:59:27.328903 INFO: [NOCDAPC] D12_APC_0: 0x0
10071 13:59:27.332517 INFO: [NOCDAPC] D12_APC_1: 0xfff
10072 13:59:27.335698 INFO: [NOCDAPC] D13_APC_0: 0x0
10073 13:59:27.339097 INFO: [NOCDAPC] D13_APC_1: 0xfff
10074 13:59:27.342564 INFO: [NOCDAPC] D14_APC_0: 0x0
10075 13:59:27.342951 INFO: [NOCDAPC] D14_APC_1: 0xfff
10076 13:59:27.345860 INFO: [NOCDAPC] D15_APC_0: 0x0
10077 13:59:27.349005 INFO: [NOCDAPC] D15_APC_1: 0xfff
10078 13:59:27.352541 INFO: [NOCDAPC] APC_CON: 0x4
10079 13:59:27.356249 INFO: [APUAPC] set_apusys_apc done
10080 13:59:27.359437 INFO: [DEVAPC] devapc_init done
10081 13:59:27.362371 INFO: GICv3 without legacy support detected.
10082 13:59:27.369184 INFO: ARM GICv3 driver initialized in EL3
10083 13:59:27.372386 INFO: Maximum SPI INTID supported: 639
10084 13:59:27.375674 INFO: BL31: Initializing runtime services
10085 13:59:27.382570 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10086 13:59:27.385550 INFO: SPM: enable CPC mode
10087 13:59:27.389110 INFO: mcdi ready for mcusys-off-idle and system suspend
10088 13:59:27.392648 INFO: BL31: Preparing for EL3 exit to normal world
10089 13:59:27.398620 INFO: Entry point address = 0x80000000
10090 13:59:27.398980 INFO: SPSR = 0x8
10091 13:59:27.404943
10092 13:59:27.405297
10093 13:59:27.405580
10094 13:59:27.408707 Starting depthcharge on Spherion...
10095 13:59:27.409063
10096 13:59:27.409344 Wipe memory regions:
10097 13:59:27.409607
10098 13:59:27.411804 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10099 13:59:27.412238 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10100 13:59:27.413528 Setting prompt string to ['asurada:']
10101 13:59:27.413871 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10102 13:59:27.414504 [0x00000040000000, 0x00000054600000)
10103 13:59:27.534151
10104 13:59:27.534602 [0x00000054660000, 0x00000080000000)
10105 13:59:27.795009
10106 13:59:27.795569 [0x000000821a7280, 0x000000ffe64000)
10107 13:59:28.539981
10108 13:59:28.540488 [0x00000100000000, 0x00000240000000)
10109 13:59:30.430290
10110 13:59:30.433023 Initializing XHCI USB controller at 0x11200000.
10111 13:59:31.471354
10112 13:59:31.474328 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10113 13:59:31.474638
10114 13:59:31.474951
10115 13:59:31.475245
10116 13:59:31.475949 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 13:59:31.576920 asurada: tftpboot 192.168.201.1 11588090/tftp-deploy-mrsx7v69/kernel/image.itb 11588090/tftp-deploy-mrsx7v69/kernel/cmdline
10119 13:59:31.577375 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 13:59:31.577718 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10121 13:59:31.582272 tftpboot 192.168.201.1 11588090/tftp-deploy-mrsx7v69/kernel/image.itp-deploy-mrsx7v69/kernel/cmdline
10122 13:59:31.582720
10123 13:59:31.583065 Waiting for link
10124 13:59:31.742588
10125 13:59:31.743069 R8152: Initializing
10126 13:59:31.743483
10127 13:59:31.746085 Version 6 (ocp_data = 5c30)
10128 13:59:31.746450
10129 13:59:31.749021 R8152: Done initializing
10130 13:59:31.749432
10131 13:59:31.749809 Adding net device
10132 13:59:33.676764
10133 13:59:33.677234 done.
10134 13:59:33.677545
10135 13:59:33.677892 MAC: 00:24:32:30:78:ff
10136 13:59:33.678211
10137 13:59:33.679645 Sending DHCP discover... done.
10138 13:59:33.680045
10139 13:59:33.683498 Waiting for reply... done.
10140 13:59:33.683916
10141 13:59:33.686504 Sending DHCP request... done.
10142 13:59:33.686927
10143 13:59:33.692635 Waiting for reply... done.
10144 13:59:33.693015
10145 13:59:33.693317 My ip is 192.168.201.21
10146 13:59:33.693676
10147 13:59:33.695942 The DHCP server ip is 192.168.201.1
10148 13:59:33.696217
10149 13:59:33.702107 TFTP server IP predefined by user: 192.168.201.1
10150 13:59:33.702384
10151 13:59:33.708693 Bootfile predefined by user: 11588090/tftp-deploy-mrsx7v69/kernel/image.itb
10152 13:59:33.708970
10153 13:59:33.709185 Sending tftp read request... done.
10154 13:59:33.711627
10155 13:59:33.717437 Waiting for the transfer...
10156 13:59:33.717826
10157 13:59:34.366589 00000000 ################################################################
10158 13:59:34.366883
10159 13:59:34.994880 00080000 ################################################################
10160 13:59:34.995066
10161 13:59:35.589963 00100000 ################################################################
10162 13:59:35.590117
10163 13:59:36.156449 00180000 ################################################################
10164 13:59:36.156600
10165 13:59:36.740014 00200000 ################################################################
10166 13:59:36.740195
10167 13:59:37.340941 00280000 ################################################################
10168 13:59:37.341104
10169 13:59:37.942885 00300000 ################################################################
10170 13:59:37.943140
10171 13:59:38.584370 00380000 ################################################################
10172 13:59:38.584503
10173 13:59:39.152459 00400000 ################################################################
10174 13:59:39.152613
10175 13:59:39.742829 00480000 ################################################################
10176 13:59:39.743012
10177 13:59:40.383265 00500000 ################################################################
10178 13:59:40.383878
10179 13:59:40.962022 00580000 ################################################################
10180 13:59:40.962161
10181 13:59:41.541600 00600000 ################################################################
10182 13:59:41.541754
10183 13:59:42.116970 00680000 ################################################################
10184 13:59:42.117103
10185 13:59:42.730280 00700000 ################################################################
10186 13:59:42.730808
10187 13:59:43.382818 00780000 ################################################################
10188 13:59:43.382968
10189 13:59:44.035743 00800000 ################################################################
10190 13:59:44.035886
10191 13:59:44.611380 00880000 ################################################################
10192 13:59:44.611548
10193 13:59:45.188043 00900000 ################################################################
10194 13:59:45.188196
10195 13:59:45.788748 00980000 ################################################################
10196 13:59:45.788889
10197 13:59:46.407791 00a00000 ################################################################
10198 13:59:46.408351
10199 13:59:47.048119 00a80000 ################################################################
10200 13:59:47.048262
10201 13:59:47.704650 00b00000 ################################################################
10202 13:59:47.704785
10203 13:59:48.351112 00b80000 ################################################################
10204 13:59:48.351264
10205 13:59:48.947276 00c00000 ################################################################
10206 13:59:48.947882
10207 13:59:49.564086 00c80000 ################################################################
10208 13:59:49.564630
10209 13:59:50.283051 00d00000 ################################################################
10210 13:59:50.283196
10211 13:59:50.968951 00d80000 ################################################################
10212 13:59:50.969531
10213 13:59:51.648096 00e00000 ################################################################
10214 13:59:51.648687
10215 13:59:52.242042 00e80000 ################################################################
10216 13:59:52.242215
10217 13:59:52.817972 00f00000 ################################################################
10218 13:59:52.818116
10219 13:59:53.459035 00f80000 ################################################################
10220 13:59:53.459735
10221 13:59:54.098281 01000000 ################################################################
10222 13:59:54.098429
10223 13:59:54.725053 01080000 ################################################################
10224 13:59:54.725576
10225 13:59:55.414250 01100000 ################################################################
10226 13:59:55.414382
10227 13:59:56.011834 01180000 ################################################################
10228 13:59:56.011969
10229 13:59:56.697652 01200000 ################################################################
10230 13:59:56.698222
10231 13:59:57.420481 01280000 ################################################################
10232 13:59:57.420706
10233 13:59:58.036418 01300000 ################################################################
10234 13:59:58.036705
10235 13:59:58.760438 01380000 ################################################################
10236 13:59:58.761017
10237 13:59:59.494280 01400000 ################################################################
10238 13:59:59.494955
10239 14:00:00.213256 01480000 ################################################################
10240 14:00:00.213864
10241 14:00:00.935323 01500000 ################################################################
10242 14:00:00.935964
10243 14:00:01.668498 01580000 ################################################################
10244 14:00:01.669070
10245 14:00:02.397064 01600000 ################################################################
10246 14:00:02.397671
10247 14:00:03.129852 01680000 ################################################################
10248 14:00:03.130462
10249 14:00:03.853698 01700000 ################################################################
10250 14:00:03.854307
10251 14:00:04.578719 01780000 ################################################################
10252 14:00:04.579337
10253 14:00:05.300598 01800000 ################################################################
10254 14:00:05.301171
10255 14:00:06.009702 01880000 ################################################################
10256 14:00:06.010164
10257 14:00:06.743520 01900000 ################################################################
10258 14:00:06.744088
10259 14:00:07.481069 01980000 ################################################################
10260 14:00:07.481604
10261 14:00:08.208011 01a00000 ################################################################
10262 14:00:08.208587
10263 14:00:08.939502 01a80000 ################################################################
10264 14:00:08.940076
10265 14:00:09.665251 01b00000 ################################################################
10266 14:00:09.665825
10267 14:00:09.729915 01b80000 ###### done.
10268 14:00:09.730484
10269 14:00:09.733024 The bootfile was 28882550 bytes long.
10270 14:00:09.733493
10271 14:00:09.736028 Sending tftp read request... done.
10272 14:00:09.736494
10273 14:00:09.740322 Waiting for the transfer...
10274 14:00:09.740943
10275 14:00:09.741327 00000000 # done.
10276 14:00:09.741684
10277 14:00:09.747566 Command line loaded dynamically from TFTP file: 11588090/tftp-deploy-mrsx7v69/kernel/cmdline
10278 14:00:09.748034
10279 14:00:09.770407 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11588090/extract-nfsrootfs-oq143gd7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10280 14:00:09.770992
10281 14:00:09.771368 Loading FIT.
10282 14:00:09.771784
10283 14:00:09.773630 Image ramdisk-1 has 17788363 bytes.
10284 14:00:09.774093
10285 14:00:09.776683 Image fdt-1 has 47278 bytes.
10286 14:00:09.777165
10287 14:00:09.780271 Image kernel-1 has 11044874 bytes.
10288 14:00:09.780761
10289 14:00:09.790342 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10290 14:00:09.790927
10291 14:00:09.806916 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10292 14:00:09.807584
10293 14:00:09.813388 Choosing best match conf-1 for compat google,spherion-rev2.
10294 14:00:09.813972
10295 14:00:09.820700 Connected to device vid:did:rid of 1ae0:0028:00
10296 14:00:09.827651
10297 14:00:09.831102 tpm_get_response: command 0x17b, return code 0x0
10298 14:00:09.831724
10299 14:00:09.834812 ec_init: CrosEC protocol v3 supported (256, 248)
10300 14:00:09.838138
10301 14:00:09.841618 tpm_cleanup: add release locality here.
10302 14:00:09.842206
10303 14:00:09.842580 Shutting down all USB controllers.
10304 14:00:09.845456
10305 14:00:09.845913 Removing current net device
10306 14:00:09.846277
10307 14:00:09.851890 Exiting depthcharge with code 4 at timestamp: 71778194
10308 14:00:09.852439
10309 14:00:09.855046 LZMA decompressing kernel-1 to 0x821a6718
10310 14:00:09.855666
10311 14:00:09.858400 LZMA decompressing kernel-1 to 0x40000000
10312 14:00:11.246765
10313 14:00:11.247496 jumping to kernel
10314 14:00:11.248955 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10315 14:00:11.249487 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10316 14:00:11.249911 Setting prompt string to ['Linux version [0-9]']
10317 14:00:11.250288 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10318 14:00:11.250666 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10319 14:00:11.328382
10320 14:00:11.331872 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10321 14:00:11.335744 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10322 14:00:11.336313 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10323 14:00:11.336960 Setting prompt string to []
10324 14:00:11.337416 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10325 14:00:11.337812 Using line separator: #'\n'#
10326 14:00:11.338150 No login prompt set.
10327 14:00:11.338481 Parsing kernel messages
10328 14:00:11.338788 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10329 14:00:11.339340 [login-action] Waiting for messages, (timeout 00:03:41)
10330 14:00:11.354917 [ 0.000000] Linux version 6.1.54-cip6-rt3 (KernelCI@build-j53691-arm64-gcc-10-defconfig-arm64-chromebook-2d8w4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Sep 21 13:44:36 UTC 2023
10331 14:00:11.358717 [ 0.000000] random: crng init done
10332 14:00:11.364879 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10333 14:00:11.368681 [ 0.000000] efi: UEFI not found.
10334 14:00:11.374987 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10335 14:00:11.381895 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10336 14:00:11.391493 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10337 14:00:11.401313 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10338 14:00:11.408571 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10339 14:00:11.414720 [ 0.000000] printk: bootconsole [mtk8250] enabled
10340 14:00:11.421094 [ 0.000000] NUMA: No NUMA configuration found
10341 14:00:11.428352 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10342 14:00:11.431377 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10343 14:00:11.434976 [ 0.000000] Zone ranges:
10344 14:00:11.441209 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10345 14:00:11.444567 [ 0.000000] DMA32 empty
10346 14:00:11.450810 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10347 14:00:11.454663 [ 0.000000] Movable zone start for each node
10348 14:00:11.458158 [ 0.000000] Early memory node ranges
10349 14:00:11.464559 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10350 14:00:11.470971 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10351 14:00:11.478161 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10352 14:00:11.484353 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10353 14:00:11.487807 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10354 14:00:11.497359 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10355 14:00:11.552955 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10356 14:00:11.560518 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10357 14:00:11.566640 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10358 14:00:11.569838 [ 0.000000] psci: probing for conduit method from DT.
10359 14:00:11.576348 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10360 14:00:11.579660 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10361 14:00:11.586425 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10362 14:00:11.589152 [ 0.000000] psci: SMC Calling Convention v1.2
10363 14:00:11.596100 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10364 14:00:11.599724 [ 0.000000] Detected VIPT I-cache on CPU0
10365 14:00:11.606134 [ 0.000000] CPU features: detected: GIC system register CPU interface
10366 14:00:11.613144 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10367 14:00:11.619556 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10368 14:00:11.626047 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10369 14:00:11.635700 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10370 14:00:11.642539 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10371 14:00:11.645550 [ 0.000000] alternatives: applying boot alternatives
10372 14:00:11.652723 [ 0.000000] Fallback order for Node 0: 0
10373 14:00:11.659183 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10374 14:00:11.662305 [ 0.000000] Policy zone: Normal
10375 14:00:11.685827 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11588090/extract-nfsrootfs-oq143gd7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10376 14:00:11.695508 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10377 14:00:11.706021 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10378 14:00:11.715846 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10379 14:00:11.722662 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10380 14:00:11.725875 <6>[ 0.000000] software IO TLB: area num 8.
10381 14:00:11.782217 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10382 14:00:11.931819 <6>[ 0.000000] Memory: 7952052K/8385536K available (17984K kernel code, 4116K rwdata, 17472K rodata, 8448K init, 615K bss, 400716K reserved, 32768K cma-reserved)
10383 14:00:11.938092 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10384 14:00:11.945062 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10385 14:00:11.948284 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10386 14:00:11.954700 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10387 14:00:11.961139 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10388 14:00:11.964186 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10389 14:00:11.974714 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10390 14:00:11.981388 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10391 14:00:11.988112 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10392 14:00:11.994617 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10393 14:00:11.997687 <6>[ 0.000000] GICv3: 608 SPIs implemented
10394 14:00:12.000923 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10395 14:00:12.007860 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10396 14:00:12.011027 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10397 14:00:12.017477 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10398 14:00:12.031221 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10399 14:00:12.040899 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10400 14:00:12.050464 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10401 14:00:12.058154 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10402 14:00:12.071205 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10403 14:00:12.078351 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10404 14:00:12.084759 <6>[ 0.009185] Console: colour dummy device 80x25
10405 14:00:12.094644 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10406 14:00:12.100930 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10407 14:00:12.104712 <6>[ 0.029220] LSM: Security Framework initializing
10408 14:00:12.111003 <6>[ 0.034160] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 14:00:12.121025 <6>[ 0.041974] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10410 14:00:12.127460 <6>[ 0.051382] cblist_init_generic: Setting adjustable number of callback queues.
10411 14:00:12.134006 <6>[ 0.058824] cblist_init_generic: Setting shift to 3 and lim to 1.
10412 14:00:12.144172 <6>[ 0.065162] cblist_init_generic: Setting adjustable number of callback queues.
10413 14:00:12.150824 <6>[ 0.072589] cblist_init_generic: Setting shift to 3 and lim to 1.
10414 14:00:12.154145 <6>[ 0.079065] rcu: Hierarchical SRCU implementation.
10415 14:00:12.160889 <6>[ 0.079067] rcu: Max phase no-delay instances is 1000.
10416 14:00:12.167345 <6>[ 0.079092] printk: bootconsole [mtk8250] printing thread started
10417 14:00:12.173785 <6>[ 0.097408] EFI services will not be available.
10418 14:00:12.177256 <6>[ 0.097606] smp: Bringing up secondary CPUs ...
10419 14:00:12.180709 <6>[ 0.097913] Detected VIPT I-cache on CPU1
10420 14:00:12.190204 <6>[ 0.097981] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10421 14:00:12.196926 <6>[ 0.098013] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10422 14:00:12.206535 <6>[ 0.125897] Detected VIPT I-cache on CPU2
10423 14:00:12.215806 <6>[ 0.125946] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10424 14:00:12.223035 <6>[ 0.125962] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10425 14:00:12.226166 <6>[ 0.126221] Detected VIPT I-cache on CPU3
10426 14:00:12.232622 <6>[ 0.126267] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10427 14:00:12.239458 <6>[ 0.126281] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10428 14:00:12.242490 <6>[ 0.126592] CPU features: detected: Spectre-v4
10429 14:00:12.248963 <6>[ 0.126598] CPU features: detected: Spectre-BHB
10430 14:00:12.252325 <6>[ 0.126603] Detected PIPT I-cache on CPU4
10431 14:00:12.259539 <6>[ 0.126660] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10432 14:00:12.265449 <6>[ 0.126678] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10433 14:00:12.272094 <6>[ 0.126968] Detected PIPT I-cache on CPU5
10434 14:00:12.278863 <6>[ 0.127028] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10435 14:00:12.285828 <6>[ 0.127045] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10436 14:00:12.288783 <6>[ 0.127321] Detected PIPT I-cache on CPU6
10437 14:00:12.295637 <6>[ 0.127387] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10438 14:00:12.302227 <6>[ 0.127405] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10439 14:00:12.309038 <6>[ 0.127696] Detected PIPT I-cache on CPU7
10440 14:00:12.315565 <6>[ 0.127760] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10441 14:00:12.321924 <6>[ 0.127776] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10442 14:00:12.325233 <6>[ 0.127821] smp: Brought up 1 node, 8 CPUs
10443 14:00:12.331849 <6>[ 0.127826] SMP: Total of 8 processors activated.
10444 14:00:12.335171 <6>[ 0.127828] CPU features: detected: 32-bit EL0 Support
10445 14:00:12.345025 <6>[ 0.127830] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10446 14:00:12.351674 <6>[ 0.127833] CPU features: detected: Common not Private translations
10447 14:00:12.358253 <6>[ 0.127835] CPU features: detected: CRC32 instructions
10448 14:00:12.364714 <6>[ 0.127837] CPU features: detected: RCpc load-acquire (LDAPR)
10449 14:00:12.368127 <6>[ 0.127839] CPU features: detected: LSE atomic instructions
10450 14:00:12.374706 <6>[ 0.127840] CPU features: detected: Privileged Access Never
10451 14:00:12.381592 <6>[ 0.127842] CPU features: detected: RAS Extension Support
10452 14:00:12.387649 <6>[ 0.127845] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10453 14:00:12.391440 <6>[ 0.127913] CPU: All CPU(s) started at EL2
10454 14:00:12.398135 <6>[ 0.127915] alternatives: applying system-wide alternatives
10455 14:00:12.400935 <6>[ 0.140964] devtmpfs: initialized
10456 14:00:12.432826 �A�͡�������*��ɥ������Bzɑ�Ɂ�b��ʲ�ѕͥjR�<6>[ 0.355405] printk:< console [ttyS0] printing thread started
10457 14:00:12.435894 6<6>[ 0.355435] printk: console [ttyS0] enabled
10458 14:00:12.439982 >[ 0.225658] pnp: PnP ACPI: disabled
10459 14:00:12.446244 <6>[ 0.355439] printk: bootconsole [mtk8250] disabled
10460 14:00:12.449569 <6>[ 0.369426] printk: bootconsole [mtk8250] printing thread stopped
10461 14:00:12.456184 <6>[ 0.375426] SuperH (H)SCI(F) driver initialized
10462 14:00:12.460027 <6>[ 0.375909] msm_serial: driver initialized
10463 14:00:12.469183 <6>[ 0.380520] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10464 14:00:12.476351 <6>[ 0.380550] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10465 14:00:12.485679 <6>[ 0.380579] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10466 14:00:12.497630 <6>[ 0.380608] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10467 14:00:12.511491 <6>[ 0.380629] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10468 14:00:12.512594 <6>[ 0.380656] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10469 14:00:12.520095 <6>[ 0.380684] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10470 14:00:12.535350 <6>[ 0.380789] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10471 14:00:12.540504 <6>[ 0.380818] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10472 14:00:12.547288 <6>[ 0.389158] loop: module loaded
10473 14:00:12.550006 <6>[ 0.391509] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10474 14:00:12.555116 <4>[ 0.408263] mtk-pmic-keys: Failed to locate of_node [id: -1]
10475 14:00:12.558770 <6>[ 0.409122] megasas: 07.719.03.00-rc1
10476 14:00:12.561761 <6>[ 0.416919] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10477 14:00:12.568371 <6>[ 0.420813] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10478 14:00:12.575148 <6>[ 0.432689] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10479 14:00:12.584851 <6>[ 0.486302] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10480 14:00:13.036632 <6>[ 0.958534] Freeing initrd memory: 17368K
10481 14:00:13.043825 <6>[ 0.964344] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10482 14:00:13.046488 <6>[ 0.969022] tun: Universal TUN/TAP device driver, 1.6
10483 14:00:13.049749 <6>[ 0.969789] thunder_xcv, ver 1.0
10484 14:00:13.053161 <6>[ 0.969806] thunder_bgx, ver 1.0
10485 14:00:13.056160 <6>[ 0.969819] nicpf, ver 1.0
10486 14:00:13.063284 <6>[ 0.970865] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10487 14:00:13.069587 <6>[ 0.970868] hns3: Copyright (c) 2017 Huawei Corporation.
10488 14:00:13.073284 <6>[ 0.970892] hclge is initializing
10489 14:00:13.079678 <6>[ 0.970905] e1000: Intel(R) PRO/1000 Network Driver
10490 14:00:13.083471 <6>[ 0.970907] e1000: Copyright (c) 1999-2006 Intel Corporation.
10491 14:00:13.090621 <6>[ 0.970926] e1000e: Intel(R) PRO/1000 Network Driver
10492 14:00:13.098065 <6>[ 0.970928] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10493 14:00:13.101080 <6>[ 0.970943] igb: Intel(R) Gigabit Ethernet Network Driver
10494 14:00:13.108332 <6>[ 0.970945] igb: Copyright (c) 2007-2014 Intel Corporation.
10495 14:00:13.114820 <6>[ 0.970958] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10496 14:00:13.121232 <6>[ 0.970960] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10497 14:00:13.124737 <6>[ 0.971257] sky2: driver version 1.30
10498 14:00:13.131463 <6>[ 0.972333] VFIO - User Level meta-driver version: 0.3
10499 14:00:13.134855 <6>[ 0.975212] usbcore: registered new interface driver usb-storage
10500 14:00:13.141252 <6>[ 0.975394] usbcore: registered new device driver onboard-usb-hub
10501 14:00:13.147762 <6>[ 0.978118] mt6397-rtc mt6359-rtc: registered as rtc0
10502 14:00:13.157783 <6>[ 0.978269] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-21T14:00:16 UTC (1695304816)
10503 14:00:13.160886 <6>[ 0.978885] i2c_dev: i2c /dev entries driver
10504 14:00:13.167458 <6>[ 0.985998] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10505 14:00:13.174110 <6>[ 1.000989] cpu cpu0: EM: created perf domain
10506 14:00:13.177771 <6>[ 1.001293] cpu cpu4: EM: created perf domain
10507 14:00:13.183875 <6>[ 1.003900] sdhci: Secure Digital Host Controller Interface driver
10508 14:00:13.190451 <6>[ 1.003902] sdhci: Copyright(c) Pierre Ossman
10509 14:00:13.194069 <6>[ 1.004262] Synopsys Designware Multimedia Card Interface Driver
10510 14:00:13.200408 <6>[ 1.004647] sdhci-pltfm: SDHCI platform and OF driver helper
10511 14:00:13.207218 <6>[ 1.008909] ledtrig-cpu: registered to indicate activity on CPUs
10512 14:00:13.210684 <6>[ 1.009509] mmc0: CQHCI version 5.10
10513 14:00:13.217182 <6>[ 1.009578] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10514 14:00:13.223785 <6>[ 1.009828] usbcore: registered new interface driver usbhid
10515 14:00:13.227636 <6>[ 1.009830] usbhid: USB HID core driver
10516 14:00:13.234062 <6>[ 1.009912] spi_master spi0: will run message pump with realtime priority
10517 14:00:13.247372 <6>[ 1.038768] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10518 14:00:13.260504 <6>[ 1.040581] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10519 14:00:13.266996 <6>[ 1.043302] cros-ec-spi spi0.0: Chrome EC device registered
10520 14:00:13.277248 <6>[ 1.055149] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10521 14:00:13.280154 <6>[ 1.056124] NET: Registered PF_PACKET protocol family
10522 14:00:13.286960 <6>[ 1.056209] 9pnet: Installing 9P2000 support
10523 14:00:13.290526 <5>[ 1.056245] Key type dns_resolver registered
10524 14:00:13.293852 <6>[ 1.056622] registered taskstats version 1
10525 14:00:13.300042 <5>[ 1.056637] Loading compiled-in X.509 certificates
10526 14:00:13.310667 <4>[ 1.072847] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10527 14:00:13.320232 <4>[ 1.073099] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10528 14:00:13.326495 <3>[ 1.073117] debugfs: File 'uA_load' in directory '/' already present!
10529 14:00:13.333382 <3>[ 1.073127] debugfs: File 'min_uV' in directory '/' already present!
10530 14:00:13.340029 <3>[ 1.073132] debugfs: File 'max_uV' in directory '/' already present!
10531 14:00:13.349559 <3>[ 1.073136] debugfs: File 'constraint_flags' in directory '/' already present!
10532 14:00:13.356044 <3>[ 1.075609] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10533 14:00:13.363128 <6>[ 1.083319] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10534 14:00:13.369741 <6>[ 1.083955] xhci-mtk 11200000.usb: xHCI Host Controller
10535 14:00:13.377103 <6>[ 1.083972] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10536 14:00:13.386240 <6>[ 1.084199] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10537 14:00:13.392613 <6>[ 1.084249] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10538 14:00:13.396255 <6>[ 1.084339] xhci-mtk 11200000.usb: xHCI Host Controller
10539 14:00:13.406376 <6>[ 1.084346] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10540 14:00:13.413127 <6>[ 1.084355] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10541 14:00:13.416210 <6>[ 1.084726] hub 1-0:1.0: USB hub found
10542 14:00:13.419936 <6>[ 1.084742] hub 1-0:1.0: 1 port detected
10543 14:00:13.429740 <6>[ 1.084912] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10544 14:00:13.432795 <6>[ 1.085131] hub 2-0:1.0: USB hub found
10545 14:00:13.435796 <6>[ 1.085143] hub 2-0:1.0: 1 port detected
10546 14:00:13.442635 <6>[ 1.088290] mtk-msdc 11f70000.mmc: Got CD GPIO
10547 14:00:13.449344 <6>[ 1.102198] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10548 14:00:13.455826 <6>[ 1.102207] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10549 14:00:13.466421 <4>[ 1.102369] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10550 14:00:13.476079 <6>[ 1.103005] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10551 14:00:13.482339 <6>[ 1.103008] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10552 14:00:13.489867 <6>[ 1.103132] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10553 14:00:13.498885 <6>[ 1.103142] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10554 14:00:13.505919 <6>[ 1.103147] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10555 14:00:13.515569 <6>[ 1.103156] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10556 14:00:13.518775 <6>[ 1.103865] mmc0: Command Queue Engine enabled
10557 14:00:13.525883 <6>[ 1.103879] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10558 14:00:13.532767 <6>[ 1.104617] mmcblk0: mmc0:0001 DA4128 116 GiB
10559 14:00:13.539042 <6>[ 1.104837] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10560 14:00:13.549094 <6>[ 1.104858] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10561 14:00:13.555644 <6>[ 1.104864] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10562 14:00:13.565765 <6>[ 1.104871] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10563 14:00:13.572333 <6>[ 1.104878] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10564 14:00:13.581960 <6>[ 1.104884] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10565 14:00:13.588668 <6>[ 1.104890] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10566 14:00:13.598645 <6>[ 1.104897] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10567 14:00:13.604778 <6>[ 1.104903] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10568 14:00:13.615033 <6>[ 1.104910] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10569 14:00:13.621789 <6>[ 1.104916] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10570 14:00:13.631562 <6>[ 1.104922] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10571 14:00:13.638055 <6>[ 1.104928] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10572 14:00:13.648355 <6>[ 1.104935] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10573 14:00:13.654252 <6>[ 1.104941] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10574 14:00:13.661295 <6>[ 1.105558] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10575 14:00:13.667916 <6>[ 1.106501] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10576 14:00:13.674365 <6>[ 1.107068] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10577 14:00:13.681386 <6>[ 1.107689] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10578 14:00:13.687533 <6>[ 1.108329] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10579 14:00:13.697669 <6>[ 1.108506] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10580 14:00:13.707904 <6>[ 1.108519] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10581 14:00:13.717460 <6>[ 1.108524] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10582 14:00:13.727085 <6>[ 1.108531] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10583 14:00:13.734334 <6>[ 1.108540] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10584 14:00:13.743953 <6>[ 1.108548] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10585 14:00:13.753547 <6>[ 1.108554] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10586 14:00:13.764043 <6>[ 1.108561] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10587 14:00:13.773992 <6>[ 1.108565] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10588 14:00:13.783276 <6>[ 1.108572] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10589 14:00:13.793175 <6>[ 1.108577] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10590 14:00:13.800032 <6>[ 1.109244] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10591 14:00:13.806760 <6>[ 1.109245] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10592 14:00:13.813610 <6>[ 1.111468] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10593 14:00:13.816259 <6>[ 1.112140] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10594 14:00:13.822956 <6>[ 1.112710] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10595 14:00:13.829969 <6>[ 1.124773] Trying to probe devices needed for running init ...
10596 14:00:13.835908 <6>[ 1.513564] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10597 14:00:13.839473 <6>[ 1.670146] hub 1-1:1.0: USB hub found
10598 14:00:13.845748 <6>[ 1.670522] hub 1-1:1.0: 4 ports detected
10599 14:00:13.876011 <6>[ 1.793755] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10600 14:00:13.896653 <6>[ 1.818419] hub 2-1:1.0: USB hub found
10601 14:00:13.899758 <6>[ 1.818836] hub 2-1:1.0: 3 ports detected
10602 14:00:14.068037 <6>[ 1.985722] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10603 14:00:14.188540 <6>[ 2.113187] hub 1-1.4:1.0: USB hub found
10604 14:00:14.191705 <6>[ 2.113631] hub 1-1.4:1.0: 2 ports detected
10605 14:00:14.272041 <6>[ 2.189958] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10606 14:00:14.483859 <6>[ 2.401714] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10607 14:00:14.667632 <6>[ 2.585718] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10608 14:00:25.484020 <6>[ 13.410716] ALSA device list:
10609 14:00:25.490957 <6>[ 13.410737] No soundcards found.
10610 14:00:25.494083 <6>[ 13.415031] Freeing unused kernel memory: 8448K
10611 14:00:25.500304 Loading, please <6>[ 13.415126] Run /init as init process
10612 14:00:25.500951 wait...
10613 14:00:25.515298 Starting version 247.3-7+deb11u2
10614 14:00:25.686327 <6>[ 13.605694] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10615 14:00:25.689682 <6>[ 13.609983] remoteproc remoteproc0: scp is available
10616 14:00:25.696183 <6>[ 13.610297] remoteproc remoteproc0: powering up scp
10617 14:00:25.702862 <6>[ 13.610311] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10618 14:00:25.709889 <6>[ 13.610375] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10619 14:00:25.734202 <6>[ 13.655126] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10620 14:00:25.741333 <6>[ 13.655179] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10621 14:00:25.751068 <6>[ 13.655184] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10622 14:00:25.757495 <3>[ 13.656668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10623 14:00:25.767445 <3>[ 13.656690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10624 14:00:25.773907 <3>[ 13.656697] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 14:00:25.783949 <3>[ 13.665857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10626 14:00:25.790908 <3>[ 13.665878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 14:00:25.800195 <3>[ 13.665882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10628 14:00:25.807126 <3>[ 13.665888] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10629 14:00:25.816873 <3>[ 13.665892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 14:00:25.823599 <3>[ 13.708265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10631 14:00:25.827067 <6>[ 13.723579] mc: Linux media interface: v0.10
10632 14:00:25.836875 <3>[ 13.725896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10633 14:00:25.843265 <3>[ 13.725916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10634 14:00:25.853503 <3>[ 13.725920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10635 14:00:25.860003 <3>[ 13.727086] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10636 14:00:25.869818 <3>[ 13.727108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10637 14:00:25.876811 <3>[ 13.727115] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10638 14:00:25.883791 <3>[ 13.727126] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10639 14:00:25.894139 <3>[ 13.727134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10640 14:00:25.900692 <3>[ 13.728661] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10641 14:00:25.908053 <4>[ 13.732851] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10642 14:00:25.914597 <4>[ 13.734960] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10643 14:00:25.924302 <6>[ 13.736239] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10644 14:00:25.930628 <6>[ 13.736245] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10645 14:00:25.937789 <6>[ 13.736255] remoteproc remoteproc0: remote processor scp is now up
10646 14:00:25.944035 <6>[ 13.769573] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10647 14:00:25.951378 <6>[ 13.778760] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10648 14:00:25.957514 <6>[ 13.778770] pci_bus 0000:00: root bus resource [bus 00-ff]
10649 14:00:25.963970 <6>[ 13.778778] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10650 14:00:25.974355 <6>[ 13.778783] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10651 14:00:25.980444 <6>[ 13.778847] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10652 14:00:25.987453 <6>[ 13.778877] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10653 14:00:25.994118 <6>[ 13.778986] pci 0000:00:00.0: supports D1 D2
10654 14:00:26.000675 <6>[ 13.778991] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10655 14:00:26.007188 <6>[ 13.780542] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10656 14:00:26.013743 <6>[ 13.780679] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10657 14:00:26.023905 <6>[ 13.780709] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10658 14:00:26.030045 <6>[ 13.780729] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10659 14:00:26.036761 <6>[ 13.780747] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10660 14:00:26.039689 <6>[ 13.780866] pci 0000:01:00.0: supports D1 D2
10661 14:00:26.046314 <6>[ 13.780869] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10662 14:00:26.053067 <6>[ 13.784913] videodev: Linux video capture interface: v2.00
10663 14:00:26.060403 <6>[ 13.789210] usbcore: registered new interface driver r8152
10664 14:00:26.066844 <6>[ 13.790082] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10665 14:00:26.073510 <6>[ 13.790257] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10666 14:00:26.082991 <6>[ 13.790266] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10667 14:00:26.089695 <6>[ 13.790294] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10668 14:00:26.099668 <6>[ 13.790317] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10669 14:00:26.106330 <6>[ 13.790337] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10670 14:00:26.112626 <6>[ 13.790355] pci 0000:00:00.0: PCI bridge to [bus 01]
10671 14:00:26.119257 <6>[ 13.790380] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10672 14:00:26.128934 <6>[ 13.790570] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10673 14:00:26.135512 <6>[ 13.790916] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10674 14:00:26.138980 <6>[ 13.793092] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10675 14:00:26.145628 <6>[ 13.793356] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10676 14:00:26.155771 <6>[ 13.793950] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10677 14:00:26.162348 <4>[ 13.800221] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10678 14:00:26.168695 <4>[ 13.800221] Fallback method does not support PEC.
10679 14:00:26.178551 <3>[ 13.815631] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10680 14:00:26.184996 <3>[ 13.838615] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10681 14:00:26.195347 <6>[ 13.843704] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10682 14:00:26.205302 <6>[ 13.850404] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10683 14:00:26.215189 <6>[ 13.850686] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10684 14:00:26.221665 <6>[ 13.869718] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10685 14:00:26.227802 <5>[ 13.871399] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10686 14:00:26.234609 <6>[ 13.877120] usbcore: registered new interface driver cdc_ether
10687 14:00:26.241333 <5>[ 13.885553] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10688 14:00:26.251375 <4>[ 13.885663] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10689 14:00:26.254908 <6>[ 13.885672] cfg80211: failed to load regulatory.db
10690 14:00:26.261608 <6>[ 13.891140] Bluetooth: Core ver 2.22
10691 14:00:26.264576 <6>[ 13.891159] usbcore: registered new interface driver r8153_ecm
10692 14:00:26.271093 <6>[ 13.891334] NET: Registered PF_BLUETOOTH protocol family
10693 14:00:26.277565 <6>[ 13.891338] Bluetooth: HCI device and connection manager initialized
10694 14:00:26.284168 <6>[ 13.891391] Bluetooth: HCI socket layer initialized
10695 14:00:26.287825 <6>[ 13.891405] Bluetooth: L2CAP socket layer initialized
10696 14:00:26.294257 <6>[ 13.891420] Bluetooth: SCO socket layer initialized
10697 14:00:26.301162 <6>[ 13.898720] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10698 14:00:26.314409 <6>[ 13.900060] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10699 14:00:26.320650 <6>[ 13.900258] usbcore: registered new interface driver uvcvideo
10700 14:00:26.327537 <4>[ 13.909463] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10701 14:00:26.337792 <4>[ 13.909471] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10702 14:00:26.343785 <6>[ 13.946728] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10703 14:00:26.347182 <6>[ 13.961560] usbcore: registered new interface driver btusb
10704 14:00:26.360462 <4>[ 13.963601] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10705 14:00:26.364005 <3>[ 13.963623] Bluetooth: hci0: Failed to load firmware file (-2)
10706 14:00:26.370539 <3>[ 13.963629] Bluetooth: hci0: Failed to set up firmware (-2)
10707 14:00:26.380148 <4>[ 13.963633] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10708 14:00:26.386388 <6>[ 13.973637] r8152 2-1.3:1.0 eth0: v1.12.13
10709 14:00:26.390137 <6>[ 13.987124] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10710 14:00:26.399652 <6>[ 13.989455] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10711 14:00:26.406898 <6>[ 13.989578] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10712 14:00:26.409866 <6>[ 14.009867] mt7921e 0000:01:00.0: ASIC revision: 79610010
10713 14:00:26.422996 <4>[ 14.104834] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10714 14:00:26.433389 <4>[ 14.212122] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10715 14:00:26.446807 <4>[ 14.319002] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10716 14:00:26.449637 Begin: Loading essential drivers ... done.
10717 14:00:26.452859 Begin: Running /scripts/init-premount ... done.
10718 14:00:26.459193 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10719 14:00:26.469350 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10720 14:00:26.472367 Device /sys/class/net/enx0024323078ff found
10721 14:00:26.472942 done.
10722 14:00:26.506348 <4>[ 14.423566] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10723 14:00:26.512929 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10724 14:00:26.609786 <4>[ 14.527014] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10725 14:00:26.714262 <4>[ 14.630641] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10726 14:00:26.818242 <4>[ 14.734546] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10727 14:00:26.921413 <4>[ 14.838696] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10728 14:00:27.026208 <4>[ 14.942681] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10729 14:00:27.129576 <4>[ 15.046616] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10730 14:00:27.223209 <3>[ 15.148509] mt7921e 0000:01:00.0: hardware init failed
10731 14:00:27.551859 IP-Config: no response after 2 secs - giving up
10732 14:00:27.598489 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10733 14:00:27.723260 <6>[ 15.648367] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10734 14:00:28.704594 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10735 14:00:28.710950 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10736 14:00:28.717358 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10737 14:00:28.724581 host : mt8192-asurada-spherion-r0-cbg-8
10738 14:00:28.730545 domain : lava-rack
10739 14:00:28.733664 rootserver: 192.168.201.1 rootpath:
10740 14:00:28.737069 filename :
10741 14:00:28.839641 done.
10742 14:00:28.847700 Begin: Running /scripts/nfs-bottom ... done.
10743 14:00:28.867277 Begin: Running /scripts/init-bottom ... done.
10744 14:00:30.147155 <6>[ 18.073362] NET: Registered PF_INET6 protocol family
10745 14:00:30.154604 <6>[ 18.080800] Segment Routing with IPv6
10746 14:00:30.158087 <6>[ 18.080892] In-situ OAM (IOAM) with IPv6
10747 14:00:30.302800 <30>[ 18.207465] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10748 14:00:30.305793 <30>[ 18.208464] systemd[1]: Detected architecture arm64.
10749 14:00:30.326897
10750 14:00:30.330173 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10751 14:00:30.330743
10752 14:00:30.350367 <30>[ 18.273453] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10753 14:00:31.365861 <30>[ 19.286967] systemd[1]: Queued start job for default target Graphical Interface.
10754 14:00:31.396954 [[0;32m OK [<30>[ 19.320147] systemd[1]: Created slice system-getty.slice.
10755 14:00:31.400533 0m] Created slice [0;1;39msystem-getty.slice[0m.
10756 14:00:31.419725 [[0;32m OK [0m] Created slic<30>[ 19.343150] systemd[1]: Created slice system-modprobe.slice.
10757 14:00:31.422846 e [0;1;39msystem-modprobe.slice[0m.
10758 14:00:31.443880 [[0;32m OK [0m] Created slic<30>[ 19.366984] systemd[1]: Created slice system-serial\x2dgetty.slice.
10759 14:00:31.449855 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10760 14:00:31.468018 [[0;32m OK [0m] Created slic<30>[ 19.391578] systemd[1]: Created slice User and Session Slice.
10761 14:00:31.471504 e [0;1;39mUser and Session Slice[0m.
10762 14:00:31.494660 [[0;32m OK [0m] Started [0;<30>[ 19.414548] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10763 14:00:31.497738 1;39mDispatch Password …ts to Console Directory Watch[0m.
10764 14:00:31.522762 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.442493] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10765 14:00:31.525694 sword R…uests to Wall Directory Watch[0m.
10766 14:00:31.553655 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.469869] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10767 14:00:31.559569 <30>[ 19.470071] systemd[1]: Reached target Local Encrypted Volumes.
10768 14:00:31.563520 l Encrypted Volumes[0m.
10769 14:00:31.582583 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.505849] systemd[1]: Reached target Paths.
10770 14:00:31.583154 s[0m.
10771 14:00:31.605791 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.525761] systemd[1]: Reached target Remote File Systems.
10772 14:00:31.606357 te File Systems[0m.
10773 14:00:31.626773 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.550090] systemd[1]: Reached target Slices.
10774 14:00:31.627378 es[0m.
10775 14:00:31.645972 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.569763] systemd[1]: Reached target Swap.
10776 14:00:31.646554 [0m.
10777 14:00:31.669995 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.590189] systemd[1]: Listening on initctl Compatibility Named Pipe.
10778 14:00:31.672945 l Compatibility Named Pipe[0m.
10779 14:00:31.683472 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.606549] systemd[1]: Listening on Journal Audit Socket.
10780 14:00:31.686470 l Audit Socket[0m.
10781 14:00:31.708150 [[0;32m OK [0m] Listening on<30>[ 19.631255] systemd[1]: Listening on Journal Socket (/dev/log).
10782 14:00:31.711094 [0;1;39mJournal Socket (/dev/log)[0m.
10783 14:00:31.731753 [[0;32m OK [0m] Listening on<30>[ 19.655004] systemd[1]: Listening on Journal Socket.
10784 14:00:31.735117 [0;1;39mJournal Socket[0m.
10785 14:00:31.752260 [[0;32m OK [0m] Listening on<30>[ 19.675794] systemd[1]: Listening on Network Service Netlink Socket.
10786 14:00:31.758951 [0;1;39mNetwork Service Netlink Socket[0m.
10787 14:00:31.778904 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 19.702430] systemd[1]: Listening on udev Control Socket.
10788 14:00:31.782246 ontrol Socket[0m.
10789 14:00:31.802945 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 19.726247] systemd[1]: Listening on udev Kernel Socket.
10790 14:00:31.806141 ernel Socket[0m.
10791 14:00:31.857959 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.777939] systemd[1]: Mounting Huge Pages File System...
10792 14:00:31.858510 m[0m...
10793 14:00:31.881586 Mounting [0;1;39mPOSIX Message Queue F<30>[ 19.801967] systemd[1]: Mounting POSIX Message Queue File System...
10794 14:00:31.882256 ile System[0m...
10795 14:00:31.909949 Mounting [0;1;39mKernel Debug File Sys<30>[ 19.830251] systemd[1]: Mounting Kernel Debug File System...
10796 14:00:31.910556 tem[0m...
10797 14:00:31.930092 <30>[ 19.850280] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10798 14:00:31.942989 Starting [0;1;39mCreate list of st…o<30>[ 19.855744] systemd[1]: Starting Create list of static device nodes for the current kernel...
10799 14:00:31.946282 des for the current kernel[0m...
10800 14:00:32.002621 Starting [0;1;39mLoad Kernel Module co<30>[ 19.922373] systemd[1]: Starting Load Kernel Module configfs...
10801 14:00:32.003193 nfigfs[0m...
10802 14:00:32.024131 Starting [0;1;39mLoad <30>[ 19.947503] systemd[1]: Starting Load Kernel Module drm...
10803 14:00:32.027495 Kernel Module drm[0m...
10804 14:00:32.055368 Starting [0;1;39mLoad <30>[ 19.978577] systemd[1]: Starting Load Kernel Module fuse...
10805 14:00:32.058255 Kernel Module fuse[0m...
10806 14:00:32.101693 <30>[ 20.023297] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10807 14:00:32.108307 <6>[ 20.024483] fuse: init (API version 7.37)
10808 14:00:32.139548 Starting [0;1;39mJourn<30>[ 20.062664] systemd[1]: Starting Journal Service...
10809 14:00:32.140111 al Service[0m...
10810 14:00:32.172344 Starting [0;1;39mLoad <30>[ 20.095120] systemd[1]: Starting Load Kernel Modules...
10811 14:00:32.174765 Kernel Modules[0m...
10812 14:00:32.194672 Starting [0;1;39mRemou<30>[ 20.118553] systemd[1]: Starting Remount Root and Kernel File Systems...
10813 14:00:32.201446 nt Root and Kernel File Systems[0m...
10814 14:00:32.226010 Starting [0;1;39mColdplug All udev Dev<30>[ 20.145815] systemd[1]: Starting Coldplug All udev Devices...
10815 14:00:32.226518 ices[0m...
10816 14:00:32.245664 [[0;32m OK [<30>[ 20.169203] systemd[1]: Mounted Huge Pages File System.
10817 14:00:32.248525 0m] Mounted [0;1;39mHuge Pages File System[0m.
10818 14:00:32.259130 [[0;32m OK [0m] Mounted [0;<30>[ 20.182617] systemd[1]: Mounted POSIX Message Queue File System.
10819 14:00:32.262168 1;39mPOSIX Message Queue File System[0m.
10820 14:00:32.288654 [[0;32m OK [<30>[ 20.211970] systemd[1]: Mounted Kernel Debug File System.
10821 14:00:32.292023 0m] Mounted [0;1;39mKernel Debug File System[0m.
10822 14:00:32.313602 <3>[ 20.236662] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10823 14:00:32.323871 <30>[ 20.238882] systemd[1]: Finished Create list of static device nodes for the current kernel.
10824 14:00:32.330191 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10825 14:00:32.352175 [[0;32m OK [0m] Finished [0<30>[ 20.274781] systemd[1]: modprobe@configfs.service: Succeeded.
10826 14:00:32.362365 ;1;39mLoad Kerne<3>[ 20.275349] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10827 14:00:32.371675 l Module configf<30>[ 20.275741] systemd[1]: Finished Load Kernel Module configfs.
10828 14:00:32.372150 s[0m.
10829 14:00:32.392552 [[0;32m OK [0m] Finished [0<30>[ 20.314483] systemd[1]: modprobe@drm.service: Succeeded.
10830 14:00:32.398732 ;1;39mLoad Kerne<30>[ 20.314987] systemd[1]: Finished Load Kernel Module drm.
10831 14:00:32.399207 l Module drm[0m.
10832 14:00:32.409394 <3>[ 20.333315] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10833 14:00:32.424063 [[0;32m OK [0m] Finished [0<30>[ 20.346762] systemd[1]: modprobe@fuse.service: Succeeded.
10834 14:00:32.430799 ;1;39mLoad Kerne<30>[ 20.347550] systemd[1]: Finished Load Kernel Module fuse.
10835 14:00:32.434148 l Module fuse[0m.
10836 14:00:32.452179 [[0;32m OK [0m] Finished [0<30>[ 20.375104] systemd[1]: Finished Load Kernel Modules.
10837 14:00:32.461449 ;1;39mLoad Kerne<3>[ 20.376769] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10838 14:00:32.462005 l Modules[0m.
10839 14:00:32.483683 [[0;32m OK [0m] Finished [0<30>[ 20.406899] systemd[1]: Finished Remount Root and Kernel File Systems.
10840 14:00:32.490056 ;1;39mRemount Root and Kernel File Systems[0m.
10841 14:00:32.496584 <3>[ 20.421280] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10842 14:00:32.529653 <3>[ 20.450472] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 14:00:32.558250 Mounting [0;1;39mFUSE Control File Sys<30>[ 20.477658] systemd[1]: Mounting FUSE Control File System...
10844 14:00:32.558821 tem[0m...
10845 14:00:32.564464 <3>[ 20.479240] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10846 14:00:32.581988 <30>[ 20.504939] systemd[1]: Mounting Kernel Configuration File System...
10847 14:00:32.584903 Mounting [0;1;39mKernel Configuration File System[0m...
10848 14:00:32.601268 <3>[ 20.521842] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10849 14:00:32.617529 <30>[ 20.540582] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10850 14:00:32.627500 <30>[ 20.540764] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10851 14:00:32.634189 <30>[ 20.543914] systemd[1]: Starting Load/Save Random Seed...
10852 14:00:32.637403 Starting [0;1;39mLoad/Save Random Seed[0m...
10853 14:00:32.653364 <3>[ 20.574389] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10854 14:00:32.669557 Startin<30>[ 20.593078] systemd[1]: Starting Apply Kernel Variables...
10855 14:00:32.673078 g [0;1;39mApply Kernel Variables[0m...
10856 14:00:32.694709 Starting [0;1;39mCreate System Users[<30>[ 20.618003] systemd[1]: Starting Create System Users...
10857 14:00:32.697821 0m...
10858 14:00:32.704059 <3>[ 20.618819] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 14:00:32.721640 [[0;32m OK [<30>[ 20.644782] systemd[1]: Mounted FUSE Control File System.
10860 14:00:32.724835 0m] Mounted [0;1;39mFUSE Control File System[0m.
10861 14:00:32.750011 [[0;32m OK [0m] Mounted [0;1;39mKernel Conf<30>[ 20.670460] systemd[1]: Mounted Kernel Configuration File System.
10862 14:00:32.750578 iguration File System[0m.
10863 14:00:32.771281 [[0;32m OK [0m] Finished [0<30>[ 20.694940] systemd[1]: Finished Load/Save Random Seed.
10864 14:00:32.774678 ;1;39mLoad/Save Random Seed[0m.
10865 14:00:32.794708 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 20.718267] systemd[1]: Started Journal Service.
10866 14:00:32.795185 vice[0m.
10867 14:00:32.812288 <4>[ 20.720682] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10868 14:00:32.818921 <3>[ 20.720691] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10869 14:00:32.827330 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10870 14:00:32.848158 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10871 14:00:32.858756 See 'systemctl status systemd-udev-trigger.service' for details.
10872 14:00:32.895343 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10873 14:00:32.911588 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10874 14:00:32.954811 Starting [0;1;39mCreat<46>[ 20.875992] systemd-journald[305]: Received client request to flush runtime journal.
10875 14:00:32.957946 e Static Device Nodes in /dev[0m...
10876 14:00:34.336664 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10877 14:00:34.355712 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10878 14:00:34.366804 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10879 14:00:34.382428 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10880 14:00:34.426822 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10881 14:00:34.454194 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10882 14:00:34.633297 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10883 14:00:34.688832 Starting [0;1;39mNetwork Service[0m...
10884 14:00:34.809138 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10885 14:00:34.864124 Starting [0;1;39mNetwork Time Synchronization[0m...
10886 14:00:34.885169 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10887 14:00:35.007639 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10888 14:00:35.031223 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10889 14:00:35.090680 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10890 14:00:35.388202 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10891 14:00:35.405672 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10892 14:00:35.451548 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10893 14:00:35.472496 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10894 14:00:35.486930 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10895 14:00:35.551090 Starting [0;1;39mNetwork Name Resolution[0m...
10896 14:00:35.567117 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10897 14:00:35.587684 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10898 14:00:35.690031 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10899 14:00:35.707170 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10900 14:00:35.726213 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10901 14:00:35.738055 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10902 14:00:35.754461 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10903 14:00:35.806299 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10904 14:00:35.830029 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10905 14:00:35.861751 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10906 14:00:36.581297 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10907 14:00:36.593785 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10908 14:00:36.623026 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10909 14:00:36.634388 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10910 14:00:36.649758 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10911 14:00:36.707600 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10912 14:00:36.967096 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10913 14:00:37.155402 Starting [0;1;39mUser Login Management[0m...
10914 14:00:37.443175 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10915 14:00:37.459206 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10916 14:00:37.477350 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10917 14:00:37.519578 Starting [0;1;39mPermit User Sessions[0m...
10918 14:00:37.545980 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10919 14:00:37.603608 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10920 14:00:37.643304 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10921 14:00:37.686965 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10922 14:00:37.702345 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10923 14:00:37.718787 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10924 14:00:37.737183 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10925 14:00:37.754913 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10926 14:00:37.799471 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10927 14:00:37.852322 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10928 14:00:37.926816
10929 14:00:37.927606
10930 14:00:37.929793 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10931 14:00:37.930262
10932 14:00:37.932827 debian-bullseye-arm64 login: root (automatic login)
10933 14:00:37.933366
10934 14:00:37.933931
10935 14:00:38.313602 Linux debian-bullseye-arm64 6.1.54-cip6-rt3 #1 SMP PREEMPT Thu Sep 21 13:44:36 UTC 2023 aarch64
10936 14:00:38.314171
10937 14:00:38.320205 The programs included with the Debian GNU/Linux system are free software;
10938 14:00:38.327316 the exact distribution terms for each program are described in the
10939 14:00:38.330782 individual files in /usr/share/doc/*/copyright.
10940 14:00:38.331246
10941 14:00:38.337025 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10942 14:00:38.340255 permitted by applicable law.
10943 14:00:38.461054 Matched prompt #10: / #
10945 14:00:38.462258 Setting prompt string to ['/ #']
10946 14:00:38.462738 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10948 14:00:38.463911 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10949 14:00:38.464399 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
10950 14:00:38.464791 Setting prompt string to ['/ #']
10951 14:00:38.465138 Forcing a shell prompt, looking for ['/ #']
10953 14:00:38.515960 / #
10954 14:00:38.516782 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10955 14:00:38.517326 Waiting using forced prompt support (timeout 00:02:30)
10956 14:00:38.522269
10957 14:00:38.523200 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10958 14:00:38.523788 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
10960 14:00:38.625044 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11588090/extract-nfsrootfs-oq143gd7'
10961 14:00:38.632017 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11588090/extract-nfsrootfs-oq143gd7'
10963 14:00:38.733701 / # export NFS_SERVER_IP='192.168.201.1'
10964 14:00:38.740081 export NFS_SERVER_IP='192.168.201.1'
10965 14:00:38.740948 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10966 14:00:38.741477 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
10967 14:00:38.741949 end: 2 depthcharge-action (duration 00:01:46) [common]
10968 14:00:38.742446 start: 3 lava-test-retry (timeout 00:01:00) [common]
10969 14:00:38.742934 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10970 14:00:38.743351 Using namespace: common
10972 14:00:38.844670 / # #
10973 14:00:38.845324 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10974 14:00:38.851611 #
10975 14:00:38.852477 Using /lava-11588090
10977 14:00:38.953747 / # export SHELL=/bin/sh
10978 14:00:38.960609 export SHELL=/bin/sh
10980 14:00:39.062245 / # . /lava-11588090/environment
10981 14:00:39.069265 . /lava-11588090/environment
10983 14:00:39.177967 / # /lava-11588090/bin/lava-test-runner /lava-11588090/0
10984 14:00:39.178623 Test shell timeout: 10s (minimum of the action and connection timeout)
10985 14:00:39.184720 /lava-11588090/bin/lava-test-runner /lava-11588090/0
10986 14:00:39.479875 + export TESTRUN_ID=0_dmesg
10987 14:00:39.482920 + cd /lava-11588090/0/tests/0_dmesg
10988 14:00:39.486053 + cat uuid
10989 14:00:39.498683 + UUID=11588090_1.6.2.3.1
10990 14:00:39.499204 + set +x
10991 14:00:39.508563 + KERNELCI_LA<8>[ 27.430304] <LAVA_SIGNAL_STARTRUN 0_dmesg 11588090_1.6.2.3.1>
10992 14:00:39.509377 Received signal: <STARTRUN> 0_dmesg 11588090_1.6.2.3.1
10993 14:00:39.509932 Starting test lava.0_dmesg (11588090_1.6.2.3.1)
10994 14:00:39.510528 Skipping test definition patterns.
10995 14:00:39.511942 VA=y /bin/sh /opt/kernelci/dmesg.sh
10996 14:00:39.649273 <8>[ 27.571561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10997 14:00:39.650148 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10999 14:00:39.749554 <8>[ 27.671474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11000 14:00:39.750356 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11002 14:00:39.835254 + set +x
11003 14:00:39.846053 <8>[ 27.765950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11004 14:00:39.846751 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11006 14:00:39.852212 <LAVA_TEST_RUNNE<8>[ 27.766691] <LAVA_SIGNAL_ENDRUN 0_dmesg 11588090_1.6.2.3.1>
11007 14:00:39.852899 Received signal: <ENDRUN> 0_dmesg 11588090_1.6.2.3.1
11008 14:00:39.853312 Ending use of test pattern.
11009 14:00:39.853636 Ending test lava.0_dmesg (11588090_1.6.2.3.1), duration 0.34
11011 14:00:39.855202 R EXIT>
11012 14:00:56.104926 / # <6>[ 44.033944] vpu: disabling
11013 14:00:56.108003 <6>[ 44.034068] vproc2: disabling
11014 14:00:56.111641 <6>[ 44.034119] vproc1: disabling
11015 14:00:56.115017 <6>[ 44.034167] vaud18: disabling
11016 14:00:56.122510 <6>[ 44.034375] vsram_others: disabling
11017 14:00:56.125614 <6>[ 44.034522] va09: disabling
11018 14:00:56.128714 <6>[ 44.034586] vsram_md: disabling
11019 14:00:56.132321 <6>[ 44.034696] Vgpu: disabling
11021 14:01:38.743807 end: 3.1 lava-test-shell (duration 00:01:00) [common]
11023 14:01:38.744836 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
11025 14:01:38.745636 end: 3 lava-test-retry (duration 00:01:00) [common]
11027 14:01:38.746890 Cleaning after the job
11028 14:01:38.747406 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/ramdisk
11029 14:01:38.750183 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/kernel
11030 14:01:38.762373 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/dtb
11031 14:01:38.762531 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/nfsrootfs
11032 14:01:38.834700 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588090/tftp-deploy-mrsx7v69/modules
11033 14:01:38.842050 start: 5.1 power-off (timeout 00:00:30) [common]
11034 14:01:38.842217 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11035 14:01:38.918659 >> Command sent successfully.
11036 14:01:38.929350 Returned 0 in 0 seconds
11037 14:01:39.030398 end: 5.1 power-off (duration 00:00:00) [common]
11039 14:01:39.032081 start: 5.2 read-feedback (timeout 00:10:00) [common]
11040 14:01:39.033516 Listened to connection for namespace 'common' for up to 1s
11041 14:01:40.034203 Finalising connection for namespace 'common'
11042 14:01:40.034914 Disconnecting from shell: Finalise
11043 14:01:40.136209 end: 5.2 read-feedback (duration 00:00:01) [common]
11044 14:01:40.136837 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11588090
11045 14:01:40.546807 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11588090
11046 14:01:40.547002 TestError: A test failed to run, look at the error message.