Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 0
- Boot result: UNKNOWN
- Warnings: 0
- Kernel Warnings: 0
1 13:57:25.256538 lava-dispatcher, installed at version: 2023.06
2 13:57:25.256749 start: 0 validate
3 13:57:25.256884 Start time: 2023-09-21 13:57:25.256877+00:00 (UTC)
4 13:57:25.257019 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:57:25.257168 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:57:25.527884 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:57:25.528676 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:58:01.552698 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:58:01.553444 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:58:01.826473 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:58:01.827240 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:58:03.597461 validate duration: 38.34
14 13:58:03.597757 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:58:03.597869 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:58:03.597972 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:58:03.598120 Not decompressing ramdisk as can be used compressed.
18 13:58:03.598218 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 13:58:03.598295 saving as /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/ramdisk/rootfs.cpio.gz
20 13:58:03.598399 total size: 34390042 (32 MB)
21 13:58:03.856441 progress 0 % (0 MB)
22 13:58:03.865652 progress 5 % (1 MB)
23 13:58:03.874513 progress 10 % (3 MB)
24 13:58:03.883825 progress 15 % (4 MB)
25 13:58:03.892588 progress 20 % (6 MB)
26 13:58:03.901615 progress 25 % (8 MB)
27 13:58:03.910558 progress 30 % (9 MB)
28 13:58:03.919838 progress 35 % (11 MB)
29 13:58:03.929100 progress 40 % (13 MB)
30 13:58:03.938322 progress 45 % (14 MB)
31 13:58:03.947244 progress 50 % (16 MB)
32 13:58:03.956336 progress 55 % (18 MB)
33 13:58:03.965224 progress 60 % (19 MB)
34 13:58:03.974296 progress 65 % (21 MB)
35 13:58:03.983190 progress 70 % (22 MB)
36 13:58:03.992302 progress 75 % (24 MB)
37 13:58:04.001195 progress 80 % (26 MB)
38 13:58:04.010299 progress 85 % (27 MB)
39 13:58:04.019153 progress 90 % (29 MB)
40 13:58:04.028057 progress 95 % (31 MB)
41 13:58:04.036822 progress 100 % (32 MB)
42 13:58:04.037033 32 MB downloaded in 0.44 s (74.77 MB/s)
43 13:58:04.037210 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:58:04.037479 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:58:04.037583 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:58:04.037684 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:58:04.037843 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:58:04.037947 saving as /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/kernel/Image
50 13:58:04.038047 total size: 49304064 (47 MB)
51 13:58:04.038149 No compression specified
52 13:58:04.039812 progress 0 % (0 MB)
53 13:58:04.052691 progress 5 % (2 MB)
54 13:58:04.065357 progress 10 % (4 MB)
55 13:58:04.078258 progress 15 % (7 MB)
56 13:58:04.090987 progress 20 % (9 MB)
57 13:58:04.103920 progress 25 % (11 MB)
58 13:58:04.116690 progress 30 % (14 MB)
59 13:58:04.129479 progress 35 % (16 MB)
60 13:58:04.142139 progress 40 % (18 MB)
61 13:58:04.155052 progress 45 % (21 MB)
62 13:58:04.167772 progress 50 % (23 MB)
63 13:58:04.180612 progress 55 % (25 MB)
64 13:58:04.193424 progress 60 % (28 MB)
65 13:58:04.206352 progress 65 % (30 MB)
66 13:58:04.222781 progress 70 % (32 MB)
67 13:58:04.243040 progress 75 % (35 MB)
68 13:58:04.260246 progress 80 % (37 MB)
69 13:58:04.273152 progress 85 % (39 MB)
70 13:58:04.286868 progress 90 % (42 MB)
71 13:58:04.300267 progress 95 % (44 MB)
72 13:58:04.312858 progress 100 % (47 MB)
73 13:58:04.313123 47 MB downloaded in 0.28 s (170.94 MB/s)
74 13:58:04.313302 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:58:04.313566 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:58:04.313669 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:58:04.313777 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:58:04.313931 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:58:04.314032 saving as /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/dtb/mt8192-asurada-spherion-r0.dtb
81 13:58:04.314133 total size: 47278 (0 MB)
82 13:58:04.314233 No compression specified
83 13:58:04.315989 progress 69 % (0 MB)
84 13:58:04.316316 progress 100 % (0 MB)
85 13:58:04.316614 0 MB downloaded in 0.00 s (18.18 MB/s)
86 13:58:04.316758 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:58:04.317012 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:58:04.317114 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:58:04.317214 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:58:04.317373 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:58:04.317472 saving as /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/modules/modules.tar
93 13:58:04.317571 total size: 8629568 (8 MB)
94 13:58:04.317672 Using unxz to decompress xz
95 13:58:04.322384 progress 0 % (0 MB)
96 13:58:04.344013 progress 5 % (0 MB)
97 13:58:04.366541 progress 10 % (0 MB)
98 13:58:04.392657 progress 15 % (1 MB)
99 13:58:04.418798 progress 20 % (1 MB)
100 13:58:04.444758 progress 25 % (2 MB)
101 13:58:04.472986 progress 30 % (2 MB)
102 13:58:04.498125 progress 35 % (2 MB)
103 13:58:04.523594 progress 40 % (3 MB)
104 13:58:04.548269 progress 45 % (3 MB)
105 13:58:04.575002 progress 50 % (4 MB)
106 13:58:04.600381 progress 55 % (4 MB)
107 13:58:04.626679 progress 60 % (4 MB)
108 13:58:04.650897 progress 65 % (5 MB)
109 13:58:04.677117 progress 70 % (5 MB)
110 13:58:04.702354 progress 75 % (6 MB)
111 13:58:04.730378 progress 80 % (6 MB)
112 13:58:04.760955 progress 85 % (7 MB)
113 13:58:04.792085 progress 90 % (7 MB)
114 13:58:04.816871 progress 95 % (7 MB)
115 13:58:04.841910 progress 100 % (8 MB)
116 13:58:04.847406 8 MB downloaded in 0.53 s (15.53 MB/s)
117 13:58:04.847654 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:58:04.847916 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:58:04.848010 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:58:04.848107 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:58:04.848189 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:58:04.848281 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:58:04.848507 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq
125 13:58:04.848644 makedir: /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin
126 13:58:04.848752 makedir: /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/tests
127 13:58:04.848854 makedir: /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/results
128 13:58:04.848974 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-add-keys
129 13:58:04.849122 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-add-sources
130 13:58:04.849257 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-background-process-start
131 13:58:04.849389 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-background-process-stop
132 13:58:04.849518 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-common-functions
133 13:58:04.849647 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-echo-ipv4
134 13:58:04.849777 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-install-packages
135 13:58:04.849902 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-installed-packages
136 13:58:04.850028 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-os-build
137 13:58:04.850155 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-probe-channel
138 13:58:04.850281 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-probe-ip
139 13:58:04.850408 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-target-ip
140 13:58:04.850533 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-target-mac
141 13:58:04.850658 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-target-storage
142 13:58:04.850829 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-test-case
143 13:58:04.850956 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-test-event
144 13:58:04.851081 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-test-feedback
145 13:58:04.851205 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-test-raise
146 13:58:04.851331 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-test-reference
147 13:58:04.851456 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-test-runner
148 13:58:04.851583 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-test-set
149 13:58:04.851711 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-test-shell
150 13:58:04.851841 Updating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-install-packages (oe)
151 13:58:04.852077 Updating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/bin/lava-installed-packages (oe)
152 13:58:04.852281 Creating /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/environment
153 13:58:04.852390 LAVA metadata
154 13:58:04.852467 - LAVA_JOB_ID=11588101
155 13:58:04.852533 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:58:04.852636 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:58:04.852702 skipped lava-vland-overlay
158 13:58:04.852777 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:58:04.852860 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:58:04.852923 skipped lava-multinode-overlay
161 13:58:04.852998 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:58:04.853082 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:58:04.853160 Loading test definitions
164 13:58:04.853252 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:58:04.853325 Using /lava-11588101 at stage 0
166 13:58:04.853635 uuid=11588101_1.5.2.3.1 testdef=None
167 13:58:04.853723 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:58:04.853811 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:58:04.854359 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:58:04.854575 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:58:04.855237 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:58:04.855467 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:58:04.856071 runner path: /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/0/tests/0_cros-ec test_uuid 11588101_1.5.2.3.1
176 13:58:04.856231 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:58:04.856439 Creating lava-test-runner.conf files
179 13:58:04.856503 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11588101/lava-overlay-bphz4sfq/lava-11588101/0 for stage 0
180 13:58:04.856593 - 0_cros-ec
181 13:58:04.856690 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:58:04.856779 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:58:04.863583 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:58:04.863731 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:58:04.863823 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:58:04.863913 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:58:04.863999 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:58:05.864098 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:58:05.864715 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:58:05.864945 extracting modules file /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11588101/extract-overlay-ramdisk-_q3xny3w/ramdisk
191 13:58:06.119860 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:58:06.120035 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 13:58:06.120137 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11588101/compress-overlay-21agv7lm/overlay-1.5.2.4.tar.gz to ramdisk
194 13:58:06.120209 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11588101/compress-overlay-21agv7lm/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11588101/extract-overlay-ramdisk-_q3xny3w/ramdisk
195 13:58:06.126920 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:58:06.127034 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 13:58:06.127124 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:58:06.127214 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 13:58:06.127290 Building ramdisk /var/lib/lava/dispatcher/tmp/11588101/extract-overlay-ramdisk-_q3xny3w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11588101/extract-overlay-ramdisk-_q3xny3w/ramdisk
200 13:58:06.890994 >> 271024 blocks
201 13:58:11.654569 rename /var/lib/lava/dispatcher/tmp/11588101/extract-overlay-ramdisk-_q3xny3w/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/ramdisk/ramdisk.cpio.gz
202 13:58:11.655095 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 13:58:11.655241 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 13:58:11.655362 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 13:58:11.655495 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/kernel/Image'
206 13:58:24.761439 Returned 0 in 13 seconds
207 13:58:24.862110 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/kernel/image.itb
208 13:58:25.587709 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:58:25.588087 output: Created: Thu Sep 21 14:58:25 2023
210 13:58:25.588164 output: Image 0 (kernel-1)
211 13:58:25.588232 output: Description:
212 13:58:25.588295 output: Created: Thu Sep 21 14:58:25 2023
213 13:58:25.588359 output: Type: Kernel Image
214 13:58:25.588424 output: Compression: lzma compressed
215 13:58:25.588483 output: Data Size: 11044874 Bytes = 10786.01 KiB = 10.53 MiB
216 13:58:25.588541 output: Architecture: AArch64
217 13:58:25.588600 output: OS: Linux
218 13:58:25.588655 output: Load Address: 0x00000000
219 13:58:25.588708 output: Entry Point: 0x00000000
220 13:58:25.588760 output: Hash algo: crc32
221 13:58:25.588813 output: Hash value: a5f1a0d7
222 13:58:25.588866 output: Image 1 (fdt-1)
223 13:58:25.588919 output: Description: mt8192-asurada-spherion-r0
224 13:58:25.588971 output: Created: Thu Sep 21 14:58:25 2023
225 13:58:25.589024 output: Type: Flat Device Tree
226 13:58:25.589076 output: Compression: uncompressed
227 13:58:25.589128 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:58:25.589180 output: Architecture: AArch64
229 13:58:25.589232 output: Hash algo: crc32
230 13:58:25.589284 output: Hash value: cc4352de
231 13:58:25.589336 output: Image 2 (ramdisk-1)
232 13:58:25.589388 output: Description: unavailable
233 13:58:25.589440 output: Created: Thu Sep 21 14:58:25 2023
234 13:58:25.589493 output: Type: RAMDisk Image
235 13:58:25.589545 output: Compression: Unknown Compression
236 13:58:25.589597 output: Data Size: 47523506 Bytes = 46409.67 KiB = 45.32 MiB
237 13:58:25.589649 output: Architecture: AArch64
238 13:58:25.589701 output: OS: Linux
239 13:58:25.589753 output: Load Address: unavailable
240 13:58:25.589806 output: Entry Point: unavailable
241 13:58:25.589859 output: Hash algo: crc32
242 13:58:25.589911 output: Hash value: 28c8e70a
243 13:58:25.589963 output: Default Configuration: 'conf-1'
244 13:58:25.590016 output: Configuration 0 (conf-1)
245 13:58:25.590068 output: Description: mt8192-asurada-spherion-r0
246 13:58:25.590120 output: Kernel: kernel-1
247 13:58:25.590172 output: Init Ramdisk: ramdisk-1
248 13:58:25.590224 output: FDT: fdt-1
249 13:58:25.590276 output: Loadables: kernel-1
250 13:58:25.590327 output:
251 13:58:25.590535 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 13:58:25.590635 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 13:58:25.590746 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 13:58:25.590845 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 13:58:25.590926 No LXC device requested
256 13:58:25.591007 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:58:25.591094 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 13:58:25.591172 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:58:25.591245 Checking files for TFTP limit of 4294967296 bytes.
260 13:58:25.591752 end: 1 tftp-deploy (duration 00:00:22) [common]
261 13:58:25.591851 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:58:25.591945 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:58:25.592067 substitutions:
264 13:58:25.592134 - {DTB}: 11588101/tftp-deploy-ier9qoce/dtb/mt8192-asurada-spherion-r0.dtb
265 13:58:25.592198 - {INITRD}: 11588101/tftp-deploy-ier9qoce/ramdisk/ramdisk.cpio.gz
266 13:58:25.592257 - {KERNEL}: 11588101/tftp-deploy-ier9qoce/kernel/Image
267 13:58:25.592315 - {LAVA_MAC}: None
268 13:58:25.592370 - {PRESEED_CONFIG}: None
269 13:58:25.592425 - {PRESEED_LOCAL}: None
270 13:58:25.592480 - {RAMDISK}: 11588101/tftp-deploy-ier9qoce/ramdisk/ramdisk.cpio.gz
271 13:58:25.592534 - {ROOT_PART}: None
272 13:58:25.592588 - {ROOT}: None
273 13:58:25.592641 - {SERVER_IP}: 192.168.201.1
274 13:58:25.592695 - {TEE}: None
275 13:58:25.592748 Parsed boot commands:
276 13:58:25.592801 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:58:25.592985 Parsed boot commands: tftpboot 192.168.201.1 11588101/tftp-deploy-ier9qoce/kernel/image.itb 11588101/tftp-deploy-ier9qoce/kernel/cmdline
278 13:58:25.593073 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:58:25.593159 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:58:25.593250 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:58:25.593335 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:58:25.593407 Not connected, no need to disconnect.
283 13:58:25.593480 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:58:25.593559 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:58:25.593624 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 13:58:25.597606 Setting prompt string to ['lava-test: # ']
287 13:58:25.597974 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:58:25.598088 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:58:25.598185 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:58:25.598277 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:58:25.598513 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 13:58:30.739759 >> Command sent successfully.
293 13:58:30.749571 Returned 0 in 5 seconds
294 13:58:30.850652 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:58:30.852078 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:58:30.852569 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:58:30.853003 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:58:30.853332 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:58:30.853680 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:58:30.854940 [Enter `^Ec?' for help]
302 13:58:31.017080
303 13:58:31.017644
304 13:58:31.017992 F0: 102B 0000
305 13:58:31.018311
306 13:58:31.018612 F3: 1001 0000 [0200]
307 13:58:31.020752
308 13:58:31.021288 F3: 1001 0000
309 13:58:31.021629
310 13:58:31.021941 F7: 102D 0000
311 13:58:31.022241
312 13:58:31.023750 F1: 0000 0000
313 13:58:31.024173
314 13:58:31.024507 V0: 0000 0000 [0001]
315 13:58:31.024836
316 13:58:31.027088 00: 0007 8000
317 13:58:31.027644
318 13:58:31.027988 01: 0000 0000
319 13:58:31.028309
320 13:58:31.030261 BP: 0C00 0209 [0000]
321 13:58:31.030843
322 13:58:31.031188 G0: 1182 0000
323 13:58:31.031504
324 13:58:31.034453 EC: 0000 0021 [4000]
325 13:58:31.034909
326 13:58:31.035247 S7: 0000 0000 [0000]
327 13:58:31.035558
328 13:58:31.035855 CC: 0000 0000 [0001]
329 13:58:31.037632
330 13:58:31.038049 T0: 0000 0040 [010F]
331 13:58:31.038381
332 13:58:31.038693 Jump to BL
333 13:58:31.039030
334 13:58:31.064027
335 13:58:31.064670
336 13:58:31.065128
337 13:58:31.071021 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 13:58:31.074522 ARM64: Exception handlers installed.
339 13:58:31.078409 ARM64: Testing exception
340 13:58:31.081618 ARM64: Done test exception
341 13:58:31.088220 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 13:58:31.098694 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 13:58:31.105278 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 13:58:31.115139 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 13:58:31.121730 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 13:58:31.128681 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 13:58:31.140246 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 13:58:31.147493 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 13:58:31.166783 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 13:58:31.170056 WDT: Last reset was cold boot
351 13:58:31.173601 SPI1(PAD0) initialized at 2873684 Hz
352 13:58:31.176588 SPI5(PAD0) initialized at 992727 Hz
353 13:58:31.180483 VBOOT: Loading verstage.
354 13:58:31.186652 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 13:58:31.190778 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 13:58:31.193548 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 13:58:31.196747 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 13:58:31.203998 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 13:58:31.210585 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 13:58:31.221826 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 13:58:31.222252
362 13:58:31.222630
363 13:58:31.231500 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 13:58:31.235490 ARM64: Exception handlers installed.
365 13:58:31.238446 ARM64: Testing exception
366 13:58:31.238970 ARM64: Done test exception
367 13:58:31.245294 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 13:58:31.249051 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 13:58:31.262876 Probing TPM: . done!
370 13:58:31.263383 TPM ready after 0 ms
371 13:58:31.270444 Connected to device vid:did:rid of 1ae0:0028:00
372 13:58:31.276838 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 13:58:31.335152 Initialized TPM device CR50 revision 0
374 13:58:31.347122 tlcl_send_startup: Startup return code is 0
375 13:58:31.347764 TPM: setup succeeded
376 13:58:31.358966 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 13:58:31.367947 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:58:31.378032 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 13:58:31.387904 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 13:58:31.390764 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 13:58:31.401950 in-header: 03 07 00 00 08 00 00 00
382 13:58:31.405978 in-data: aa e4 47 04 13 02 00 00
383 13:58:31.409618 Chrome EC: UHEPI supported
384 13:58:31.417037 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 13:58:31.419810 in-header: 03 ad 00 00 08 00 00 00
386 13:58:31.423583 in-data: 00 20 20 08 00 00 00 00
387 13:58:31.423667 Phase 1
388 13:58:31.427313 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 13:58:31.434708 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 13:58:31.438540 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 13:58:31.442938 Recovery requested (1009000e)
392 13:58:31.450441 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:58:31.456135 tlcl_extend: response is 0
394 13:58:31.465266 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:58:31.471020 tlcl_extend: response is 0
396 13:58:31.478023 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:58:31.497756 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
398 13:58:31.504457 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:58:31.504724
400 13:58:31.504876
401 13:58:31.515308 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:58:31.519163 ARM64: Exception handlers installed.
403 13:58:31.519556 ARM64: Testing exception
404 13:58:31.522840 ARM64: Done test exception
405 13:58:31.543670 pmic_efuse_setting: Set efuses in 11 msecs
406 13:58:31.547564 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:58:31.553540 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:58:31.557054 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:58:31.564357 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:58:31.568202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:58:31.571875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:58:31.575441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:58:31.582552 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:58:31.586518 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:58:31.590395 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:58:31.593907 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:58:31.601337 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:58:31.605354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:58:31.609377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:58:31.616572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:58:31.620568 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:58:31.627821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:58:31.631493 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:58:31.639463 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:58:31.642660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:58:31.650476 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:58:31.654427 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:58:31.661538 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:58:31.665422 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:58:31.673237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:58:31.676435 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:58:31.683961 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:58:31.688060 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:58:31.691243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:58:31.698497 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:58:31.702280 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:58:31.706017 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:58:31.713237 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:58:31.716775 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:58:31.724322 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:58:31.728176 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:58:31.731503 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:58:31.739080 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:58:31.742812 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:58:31.746593 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:58:31.750765 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:58:31.754276 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:58:31.761666 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:58:31.764963 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:58:31.769305 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:58:31.773360 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:58:31.776541 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:58:31.780211 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:58:31.787604 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:58:31.791286 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:58:31.794812 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:58:31.798705 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:58:31.806692 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 13:58:31.813845 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:58:31.817586 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:58:31.829093 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:58:31.836197 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:58:31.839469 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:58:31.843698 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:58:31.851146 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:58:31.854635 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x3
467 13:58:31.862157 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:58:31.865920 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 13:58:31.869780 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:58:31.880637 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 13:58:31.890516 [RTC]rtc_get_frequency_meter,154: input=23, output=979
472 13:58:31.900033 [RTC]rtc_get_frequency_meter,154: input=19, output=885
473 13:58:31.909507 [RTC]rtc_get_frequency_meter,154: input=17, output=838
474 13:58:31.918834 [RTC]rtc_get_frequency_meter,154: input=16, output=814
475 13:58:31.928372 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 13:58:31.937987 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 13:58:31.941869 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 13:58:31.945159 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 13:58:31.949381 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 13:58:31.956257 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 13:58:31.959881 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 13:58:31.963649 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 13:58:31.967248 ADC[4]: Raw value=901328 ID=7
484 13:58:31.970906 ADC[3]: Raw value=213336 ID=1
485 13:58:31.970989 RAM Code: 0x71
486 13:58:31.974883 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 13:58:31.978632 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 13:58:31.990439 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 13:58:31.993892 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 13:58:31.997313 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 13:58:32.001149 in-header: 03 07 00 00 08 00 00 00
492 13:58:32.004928 in-data: aa e4 47 04 13 02 00 00
493 13:58:32.008505 Chrome EC: UHEPI supported
494 13:58:32.015739 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 13:58:32.020080 in-header: 03 ed 00 00 08 00 00 00
496 13:58:32.023321 in-data: 80 20 60 08 00 00 00 00
497 13:58:32.027222 MRC: failed to locate region type 0.
498 13:58:32.031071 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 13:58:32.034960 DRAM-K: Running full calibration
500 13:58:32.042579 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 13:58:32.042659 header.status = 0x0
502 13:58:32.046271 header.version = 0x6 (expected: 0x6)
503 13:58:32.050105 header.size = 0xd00 (expected: 0xd00)
504 13:58:32.050192 header.flags = 0x0
505 13:58:32.056782 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 13:58:32.075696 read SPI 0x72590 0x1c583: 12504 us, 9284 KB/s, 74.272 Mbps
507 13:58:32.082982 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 13:58:32.086665 dram_init: ddr_geometry: 2
509 13:58:32.086752 [EMI] MDL number = 2
510 13:58:32.090622 [EMI] Get MDL freq = 0
511 13:58:32.090729 dram_init: ddr_type: 0
512 13:58:32.094283 is_discrete_lpddr4: 1
513 13:58:32.097944 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 13:58:32.098026
515 13:58:32.098091
516 13:58:32.098151 [Bian_co] ETT version 0.0.0.1
517 13:58:32.104932 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 13:58:32.105016
519 13:58:32.109102 dramc_set_vcore_voltage set vcore to 650000
520 13:58:32.109185 Read voltage for 800, 4
521 13:58:32.112290 Vio18 = 0
522 13:58:32.112373 Vcore = 650000
523 13:58:32.112438 Vdram = 0
524 13:58:32.112498 Vddq = 0
525 13:58:32.115936 Vmddr = 0
526 13:58:32.116017 dram_init: config_dvfs: 1
527 13:58:32.123023 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 13:58:32.129320 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 13:58:32.132792 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 13:58:32.136142 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 13:58:32.139182 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 13:58:32.143035 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 13:58:32.146199 MEM_TYPE=3, freq_sel=18
534 13:58:32.149275 sv_algorithm_assistance_LP4_1600
535 13:58:32.153125 ============ PULL DRAM RESETB DOWN ============
536 13:58:32.156440 ========== PULL DRAM RESETB DOWN end =========
537 13:58:32.162852 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 13:58:32.166874 ===================================
539 13:58:32.167049 LPDDR4 DRAM CONFIGURATION
540 13:58:32.169927 ===================================
541 13:58:32.173887 EX_ROW_EN[0] = 0x0
542 13:58:32.174079 EX_ROW_EN[1] = 0x0
543 13:58:32.176506 LP4Y_EN = 0x0
544 13:58:32.176654 WORK_FSP = 0x0
545 13:58:32.179761 WL = 0x2
546 13:58:32.179937 RL = 0x2
547 13:58:32.183683 BL = 0x2
548 13:58:32.183902 RPST = 0x0
549 13:58:32.186321 RD_PRE = 0x0
550 13:58:32.186478 WR_PRE = 0x1
551 13:58:32.189778 WR_PST = 0x0
552 13:58:32.189932 DBI_WR = 0x0
553 13:58:32.193164 DBI_RD = 0x0
554 13:58:32.196461 OTF = 0x1
555 13:58:32.196676 ===================================
556 13:58:32.200213 ===================================
557 13:58:32.203420 ANA top config
558 13:58:32.206662 ===================================
559 13:58:32.209888 DLL_ASYNC_EN = 0
560 13:58:32.210004 ALL_SLAVE_EN = 1
561 13:58:32.213473 NEW_RANK_MODE = 1
562 13:58:32.216440 DLL_IDLE_MODE = 1
563 13:58:32.219995 LP45_APHY_COMB_EN = 1
564 13:58:32.220087 TX_ODT_DIS = 1
565 13:58:32.223423 NEW_8X_MODE = 1
566 13:58:32.227001 ===================================
567 13:58:32.229908 ===================================
568 13:58:32.233390 data_rate = 1600
569 13:58:32.236814 CKR = 1
570 13:58:32.240532 DQ_P2S_RATIO = 8
571 13:58:32.243683 ===================================
572 13:58:32.246919 CA_P2S_RATIO = 8
573 13:58:32.247153 DQ_CA_OPEN = 0
574 13:58:32.250195 DQ_SEMI_OPEN = 0
575 13:58:32.253485 CA_SEMI_OPEN = 0
576 13:58:32.256877 CA_FULL_RATE = 0
577 13:58:32.261026 DQ_CKDIV4_EN = 1
578 13:58:32.261275 CA_CKDIV4_EN = 1
579 13:58:32.263825 CA_PREDIV_EN = 0
580 13:58:32.267377 PH8_DLY = 0
581 13:58:32.270809 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 13:58:32.274179 DQ_AAMCK_DIV = 4
583 13:58:32.277662 CA_AAMCK_DIV = 4
584 13:58:32.278161 CA_ADMCK_DIV = 4
585 13:58:32.280644 DQ_TRACK_CA_EN = 0
586 13:58:32.283999 CA_PICK = 800
587 13:58:32.287353 CA_MCKIO = 800
588 13:58:32.291257 MCKIO_SEMI = 0
589 13:58:32.294476 PLL_FREQ = 3068
590 13:58:32.294926 DQ_UI_PI_RATIO = 32
591 13:58:32.298837 CA_UI_PI_RATIO = 0
592 13:58:32.302457 ===================================
593 13:58:32.305942 ===================================
594 13:58:32.306357 memory_type:LPDDR4
595 13:58:32.310113 GP_NUM : 10
596 13:58:32.313800 SRAM_EN : 1
597 13:58:32.314215 MD32_EN : 0
598 13:58:32.317248 ===================================
599 13:58:32.321209 [ANA_INIT] >>>>>>>>>>>>>>
600 13:58:32.321630 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 13:58:32.325418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 13:58:32.328398 ===================================
603 13:58:32.332032 data_rate = 1600,PCW = 0X7600
604 13:58:32.335160 ===================================
605 13:58:32.338263 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 13:58:32.345183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:58:32.348332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 13:58:32.355234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 13:58:32.358468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:58:32.362504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 13:58:32.363060 [ANA_INIT] flow start
612 13:58:32.365448 [ANA_INIT] PLL >>>>>>>>
613 13:58:32.369017 [ANA_INIT] PLL <<<<<<<<
614 13:58:32.369542 [ANA_INIT] MIDPI >>>>>>>>
615 13:58:32.372564 [ANA_INIT] MIDPI <<<<<<<<
616 13:58:32.375318 [ANA_INIT] DLL >>>>>>>>
617 13:58:32.375736 [ANA_INIT] flow end
618 13:58:32.382213 ============ LP4 DIFF to SE enter ============
619 13:58:32.385448 ============ LP4 DIFF to SE exit ============
620 13:58:32.389345 [ANA_INIT] <<<<<<<<<<<<<
621 13:58:32.389876 [Flow] Enable top DCM control >>>>>
622 13:58:32.392371 [Flow] Enable top DCM control <<<<<
623 13:58:32.395414 Enable DLL master slave shuffle
624 13:58:32.401999 ==============================================================
625 13:58:32.406029 Gating Mode config
626 13:58:32.408843 ==============================================================
627 13:58:32.412289 Config description:
628 13:58:32.422771 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 13:58:32.429030 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 13:58:32.432451 SELPH_MODE 0: By rank 1: By Phase
631 13:58:32.438935 ==============================================================
632 13:58:32.442574 GAT_TRACK_EN = 1
633 13:58:32.446265 RX_GATING_MODE = 2
634 13:58:32.446931 RX_GATING_TRACK_MODE = 2
635 13:58:32.448858 SELPH_MODE = 1
636 13:58:32.452554 PICG_EARLY_EN = 1
637 13:58:32.455602 VALID_LAT_VALUE = 1
638 13:58:32.463003 ==============================================================
639 13:58:32.465919 Enter into Gating configuration >>>>
640 13:58:32.469182 Exit from Gating configuration <<<<
641 13:58:32.472369 Enter into DVFS_PRE_config >>>>>
642 13:58:32.482838 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 13:58:32.485892 Exit from DVFS_PRE_config <<<<<
644 13:58:32.489223 Enter into PICG configuration >>>>
645 13:58:32.493110 Exit from PICG configuration <<<<
646 13:58:32.496470 [RX_INPUT] configuration >>>>>
647 13:58:32.496995 [RX_INPUT] configuration <<<<<
648 13:58:32.503052 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 13:58:32.509581 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 13:58:32.513274 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 13:58:32.520451 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 13:58:32.527461 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 13:58:32.534141 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 13:58:32.537031 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 13:58:32.540747 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 13:58:32.543877 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 13:58:32.550639 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 13:58:32.554137 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 13:58:32.557425 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 13:58:32.560941 ===================================
661 13:58:32.564351 LPDDR4 DRAM CONFIGURATION
662 13:58:32.568069 ===================================
663 13:58:32.568600 EX_ROW_EN[0] = 0x0
664 13:58:32.571121 EX_ROW_EN[1] = 0x0
665 13:58:32.571682 LP4Y_EN = 0x0
666 13:58:32.574337 WORK_FSP = 0x0
667 13:58:32.574902 WL = 0x2
668 13:58:32.578275 RL = 0x2
669 13:58:32.578884 BL = 0x2
670 13:58:32.580669 RPST = 0x0
671 13:58:32.584770 RD_PRE = 0x0
672 13:58:32.585303 WR_PRE = 0x1
673 13:58:32.588165 WR_PST = 0x0
674 13:58:32.588698 DBI_WR = 0x0
675 13:58:32.591736 DBI_RD = 0x0
676 13:58:32.592265 OTF = 0x1
677 13:58:32.594471 ===================================
678 13:58:32.598118 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 13:58:32.601370 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 13:58:32.608173 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 13:58:32.611342 ===================================
682 13:58:32.615110 LPDDR4 DRAM CONFIGURATION
683 13:58:32.615639 ===================================
684 13:58:32.618141 EX_ROW_EN[0] = 0x10
685 13:58:32.621688 EX_ROW_EN[1] = 0x0
686 13:58:32.622218 LP4Y_EN = 0x0
687 13:58:32.624764 WORK_FSP = 0x0
688 13:58:32.625297 WL = 0x2
689 13:58:32.627818 RL = 0x2
690 13:58:32.628242 BL = 0x2
691 13:58:32.631407 RPST = 0x0
692 13:58:32.631829 RD_PRE = 0x0
693 13:58:32.634770 WR_PRE = 0x1
694 13:58:32.635329 WR_PST = 0x0
695 13:58:32.637832 DBI_WR = 0x0
696 13:58:32.638253 DBI_RD = 0x0
697 13:58:32.641603 OTF = 0x1
698 13:58:32.645103 ===================================
699 13:58:32.651465 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 13:58:32.654889 nWR fixed to 40
701 13:58:32.655420 [ModeRegInit_LP4] CH0 RK0
702 13:58:32.658841 [ModeRegInit_LP4] CH0 RK1
703 13:58:32.661971 [ModeRegInit_LP4] CH1 RK0
704 13:58:32.665008 [ModeRegInit_LP4] CH1 RK1
705 13:58:32.665432 match AC timing 13
706 13:58:32.668538 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 13:58:32.671463 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 13:58:32.678705 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 13:58:32.682174 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 13:58:32.688583 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 13:58:32.689115 [EMI DOE] emi_dcm 0
712 13:58:32.692141 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 13:58:32.695488 ==
714 13:58:32.698604 Dram Type= 6, Freq= 0, CH_0, rank 0
715 13:58:32.702365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 13:58:32.702938 ==
717 13:58:32.705342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 13:58:32.711979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 13:58:32.721805 [CA 0] Center 37 (7~68) winsize 62
720 13:58:32.725469 [CA 1] Center 37 (6~68) winsize 63
721 13:58:32.728226 [CA 2] Center 35 (5~66) winsize 62
722 13:58:32.731759 [CA 3] Center 34 (4~65) winsize 62
723 13:58:32.734940 [CA 4] Center 33 (3~64) winsize 62
724 13:58:32.738339 [CA 5] Center 33 (3~64) winsize 62
725 13:58:32.738913
726 13:58:32.741963 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 13:58:32.742520
728 13:58:32.745264 [CATrainingPosCal] consider 1 rank data
729 13:58:32.748358 u2DelayCellTimex100 = 270/100 ps
730 13:58:32.752115 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 13:58:32.755294 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 13:58:32.758349 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 13:58:32.765062 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 13:58:32.768663 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 13:58:32.771624 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 13:58:32.772053
737 13:58:32.775306 CA PerBit enable=1, Macro0, CA PI delay=33
738 13:58:32.775734
739 13:58:32.778227 [CBTSetCACLKResult] CA Dly = 33
740 13:58:32.778658 CS Dly: 5 (0~36)
741 13:58:32.779041 ==
742 13:58:32.781696 Dram Type= 6, Freq= 0, CH_0, rank 1
743 13:58:32.788740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 13:58:32.789274 ==
745 13:58:32.792343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 13:58:32.798508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 13:58:32.808047 [CA 0] Center 37 (6~68) winsize 63
748 13:58:32.810978 [CA 1] Center 37 (6~68) winsize 63
749 13:58:32.815110 [CA 2] Center 35 (4~66) winsize 63
750 13:58:32.818219 [CA 3] Center 34 (4~65) winsize 62
751 13:58:32.821215 [CA 4] Center 34 (3~65) winsize 63
752 13:58:32.824976 [CA 5] Center 33 (3~64) winsize 62
753 13:58:32.825513
754 13:58:32.827951 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 13:58:32.828382
756 13:58:32.831609 [CATrainingPosCal] consider 2 rank data
757 13:58:32.834861 u2DelayCellTimex100 = 270/100 ps
758 13:58:32.838240 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 13:58:32.841585 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
760 13:58:32.848160 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 13:58:32.851349 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 13:58:32.855205 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 13:58:32.858066 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 13:58:32.858588
765 13:58:32.861427 CA PerBit enable=1, Macro0, CA PI delay=33
766 13:58:32.861856
767 13:58:32.864539 [CBTSetCACLKResult] CA Dly = 33
768 13:58:32.865001 CS Dly: 6 (0~38)
769 13:58:32.865453
770 13:58:32.868975 ----->DramcWriteLeveling(PI) begin...
771 13:58:32.869530 ==
772 13:58:32.871680 Dram Type= 6, Freq= 0, CH_0, rank 0
773 13:58:32.875332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 13:58:32.879048 ==
775 13:58:32.879489 Write leveling (Byte 0): 29 => 29
776 13:58:32.882465 Write leveling (Byte 1): 30 => 30
777 13:58:32.886473 DramcWriteLeveling(PI) end<-----
778 13:58:32.887064
779 13:58:32.887516 ==
780 13:58:32.890520 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:58:32.893628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:58:32.894175 ==
783 13:58:32.896842 [Gating] SW mode calibration
784 13:58:32.904345 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 13:58:32.911327 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 13:58:32.914429 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:58:32.917203 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 13:58:32.924241 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 13:58:32.927641 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:58:32.930986 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:58:32.934298 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:58:32.941333 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:58:32.944170 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:58:32.947730 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:58:32.954873 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:58:32.958261 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:58:32.961166 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:58:32.967912 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:58:32.971205 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:58:32.974901 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:58:32.978464 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:58:32.984831 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:58:32.987676 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:58:32.991059 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 13:58:32.998064 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:58:33.001773 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:58:33.005723 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:58:33.011495 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:58:33.014802 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:58:33.018133 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:58:33.025064 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:58:33.028194 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 13:58:33.031480 0 9 12 | B1->B0 | 2929 3131 | 0 0 | (0 0) (0 0)
814 13:58:33.035173 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
815 13:58:33.042302 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:58:33.045354 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:58:33.048357 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:58:33.055734 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 13:58:33.058461 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 13:58:33.061571 0 10 8 | B1->B0 | 3333 2d2d | 0 1 | (0 1) (1 1)
821 13:58:33.068498 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
822 13:58:33.071849 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:58:33.075054 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:58:33.082056 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:58:33.085605 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:58:33.088936 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:58:33.092521 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:58:33.099865 0 11 8 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
829 13:58:33.102863 0 11 12 | B1->B0 | 3838 3d3d | 0 0 | (0 0) (0 0)
830 13:58:33.105836 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:58:33.112589 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:58:33.115987 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:58:33.119107 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:58:33.126074 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:58:33.129302 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 13:58:33.132335 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 13:58:33.139429 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 13:58:33.143070 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:58:33.146709 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:58:33.149777 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:58:33.156308 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:58:33.160121 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:58:33.163847 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:58:33.169598 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:58:33.173150 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:58:33.176442 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:58:33.183045 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:58:33.186287 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:58:33.190356 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:58:33.193450 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:58:33.200133 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:58:33.203469 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 13:58:33.207273 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
854 13:58:33.213603 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 13:58:33.214130 Total UI for P1: 0, mck2ui 16
856 13:58:33.220361 best dqsien dly found for B0: ( 0, 14, 10)
857 13:58:33.220934 Total UI for P1: 0, mck2ui 16
858 13:58:33.223782 best dqsien dly found for B1: ( 0, 14, 10)
859 13:58:33.230171 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
860 13:58:33.233761 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 13:58:33.234286
862 13:58:33.237345 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 13:58:33.240291 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 13:58:33.243692 [Gating] SW calibration Done
865 13:58:33.244215 ==
866 13:58:33.246934 Dram Type= 6, Freq= 0, CH_0, rank 0
867 13:58:33.250812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 13:58:33.251415 ==
869 13:58:33.253770 RX Vref Scan: 0
870 13:58:33.254294
871 13:58:33.254628 RX Vref 0 -> 0, step: 1
872 13:58:33.255086
873 13:58:33.257023 RX Delay -130 -> 252, step: 16
874 13:58:33.260692 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
875 13:58:33.267477 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
876 13:58:33.271050 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
877 13:58:33.274336 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
878 13:58:33.277560 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
879 13:58:33.281034 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
880 13:58:33.284354 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
881 13:58:33.290604 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
882 13:58:33.294032 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
883 13:58:33.297953 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
884 13:58:33.301274 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
885 13:58:33.304683 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
886 13:58:33.311087 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
887 13:58:33.314697 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
888 13:58:33.318027 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
889 13:58:33.321502 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
890 13:58:33.321979 ==
891 13:58:33.324322 Dram Type= 6, Freq= 0, CH_0, rank 0
892 13:58:33.327509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 13:58:33.331068 ==
894 13:58:33.331505 DQS Delay:
895 13:58:33.331838 DQS0 = 0, DQS1 = 0
896 13:58:33.334613 DQM Delay:
897 13:58:33.335173 DQM0 = 84, DQM1 = 78
898 13:58:33.335510 DQ Delay:
899 13:58:33.337875 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 13:58:33.341785 DQ4 =85, DQ5 =77, DQ6 =85, DQ7 =85
901 13:58:33.344734 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
902 13:58:33.348622 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
903 13:58:33.349088
904 13:58:33.349608
905 13:58:33.351462 ==
906 13:58:33.352122 Dram Type= 6, Freq= 0, CH_0, rank 0
907 13:58:33.358390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 13:58:33.358984 ==
909 13:58:33.359340
910 13:58:33.359771
911 13:58:33.361710 TX Vref Scan disable
912 13:58:33.362178 == TX Byte 0 ==
913 13:58:33.364686 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
914 13:58:33.371750 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
915 13:58:33.372181 == TX Byte 1 ==
916 13:58:33.374979 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
917 13:58:33.381810 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
918 13:58:33.382306 ==
919 13:58:33.385012 Dram Type= 6, Freq= 0, CH_0, rank 0
920 13:58:33.388502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 13:58:33.388971 ==
922 13:58:33.401422 TX Vref=22, minBit 5, minWin=27, winSum=441
923 13:58:33.404996 TX Vref=24, minBit 5, minWin=27, winSum=443
924 13:58:33.408188 TX Vref=26, minBit 3, minWin=27, winSum=445
925 13:58:33.411230 TX Vref=28, minBit 5, minWin=27, winSum=449
926 13:58:33.414893 TX Vref=30, minBit 2, minWin=28, winSum=456
927 13:58:33.418508 TX Vref=32, minBit 1, minWin=28, winSum=452
928 13:58:33.425141 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
929 13:58:33.425674
930 13:58:33.428324 Final TX Range 1 Vref 30
931 13:58:33.428858
932 13:58:33.429203 ==
933 13:58:33.431386 Dram Type= 6, Freq= 0, CH_0, rank 0
934 13:58:33.434964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 13:58:33.435499 ==
936 13:58:33.435847
937 13:58:33.436162
938 13:58:33.438272 TX Vref Scan disable
939 13:58:33.441543 == TX Byte 0 ==
940 13:58:33.444839 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
941 13:58:33.448171 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
942 13:58:33.451662 == TX Byte 1 ==
943 13:58:33.454804 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
944 13:58:33.458162 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
945 13:58:33.458605
946 13:58:33.461619 [DATLAT]
947 13:58:33.462043 Freq=800, CH0 RK0
948 13:58:33.462383
949 13:58:33.465216 DATLAT Default: 0xa
950 13:58:33.465641 0, 0xFFFF, sum = 0
951 13:58:33.468275 1, 0xFFFF, sum = 0
952 13:58:33.468804 2, 0xFFFF, sum = 0
953 13:58:33.472055 3, 0xFFFF, sum = 0
954 13:58:33.472667 4, 0xFFFF, sum = 0
955 13:58:33.475022 5, 0xFFFF, sum = 0
956 13:58:33.475558 6, 0xFFFF, sum = 0
957 13:58:33.479329 7, 0xFFFF, sum = 0
958 13:58:33.479874 8, 0xFFFF, sum = 0
959 13:58:33.481634 9, 0x0, sum = 1
960 13:58:33.482066 10, 0x0, sum = 2
961 13:58:33.485301 11, 0x0, sum = 3
962 13:58:33.485731 12, 0x0, sum = 4
963 13:58:33.488725 best_step = 10
964 13:58:33.489175
965 13:58:33.489507 ==
966 13:58:33.492498 Dram Type= 6, Freq= 0, CH_0, rank 0
967 13:58:33.495403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 13:58:33.495829 ==
969 13:58:33.496162 RX Vref Scan: 1
970 13:58:33.496473
971 13:58:33.498872 Set Vref Range= 32 -> 127
972 13:58:33.499407
973 13:58:33.501862 RX Vref 32 -> 127, step: 1
974 13:58:33.502279
975 13:58:33.505628 RX Delay -95 -> 252, step: 8
976 13:58:33.506146
977 13:58:33.508666 Set Vref, RX VrefLevel [Byte0]: 32
978 13:58:33.512105 [Byte1]: 32
979 13:58:33.512621
980 13:58:33.516020 Set Vref, RX VrefLevel [Byte0]: 33
981 13:58:33.519780 [Byte1]: 33
982 13:58:33.520202
983 13:58:33.523450 Set Vref, RX VrefLevel [Byte0]: 34
984 13:58:33.526204 [Byte1]: 34
985 13:58:33.526618
986 13:58:33.529242 Set Vref, RX VrefLevel [Byte0]: 35
987 13:58:33.532674 [Byte1]: 35
988 13:58:33.536872
989 13:58:33.537286 Set Vref, RX VrefLevel [Byte0]: 36
990 13:58:33.540328 [Byte1]: 36
991 13:58:33.544718
992 13:58:33.545194 Set Vref, RX VrefLevel [Byte0]: 37
993 13:58:33.548310 [Byte1]: 37
994 13:58:33.552018
995 13:58:33.552653 Set Vref, RX VrefLevel [Byte0]: 38
996 13:58:33.555874 [Byte1]: 38
997 13:58:33.559524
998 13:58:33.559948 Set Vref, RX VrefLevel [Byte0]: 39
999 13:58:33.562770 [Byte1]: 39
1000 13:58:33.567174
1001 13:58:33.567647 Set Vref, RX VrefLevel [Byte0]: 40
1002 13:58:33.570826 [Byte1]: 40
1003 13:58:33.575007
1004 13:58:33.575428 Set Vref, RX VrefLevel [Byte0]: 41
1005 13:58:33.578146 [Byte1]: 41
1006 13:58:33.582145
1007 13:58:33.582568 Set Vref, RX VrefLevel [Byte0]: 42
1008 13:58:33.585753 [Byte1]: 42
1009 13:58:33.589620
1010 13:58:33.590051 Set Vref, RX VrefLevel [Byte0]: 43
1011 13:58:33.593544 [Byte1]: 43
1012 13:58:33.597820
1013 13:58:33.598369 Set Vref, RX VrefLevel [Byte0]: 44
1014 13:58:33.601122 [Byte1]: 44
1015 13:58:33.605075
1016 13:58:33.605598 Set Vref, RX VrefLevel [Byte0]: 45
1017 13:58:33.608805 [Byte1]: 45
1018 13:58:33.612404
1019 13:58:33.612820 Set Vref, RX VrefLevel [Byte0]: 46
1020 13:58:33.616317 [Byte1]: 46
1021 13:58:33.620501
1022 13:58:33.621028 Set Vref, RX VrefLevel [Byte0]: 47
1023 13:58:33.623954 [Byte1]: 47
1024 13:58:33.628316
1025 13:58:33.628851 Set Vref, RX VrefLevel [Byte0]: 48
1026 13:58:33.631409 [Byte1]: 48
1027 13:58:33.635675
1028 13:58:33.636187 Set Vref, RX VrefLevel [Byte0]: 49
1029 13:58:33.638544 [Byte1]: 49
1030 13:58:33.643664
1031 13:58:33.644285 Set Vref, RX VrefLevel [Byte0]: 50
1032 13:58:33.647252 [Byte1]: 50
1033 13:58:33.650689
1034 13:58:33.651297 Set Vref, RX VrefLevel [Byte0]: 51
1035 13:58:33.653601 [Byte1]: 51
1036 13:58:33.657951
1037 13:58:33.658364 Set Vref, RX VrefLevel [Byte0]: 52
1038 13:58:33.661561 [Byte1]: 52
1039 13:58:33.665903
1040 13:58:33.666332 Set Vref, RX VrefLevel [Byte0]: 53
1041 13:58:33.669204 [Byte1]: 53
1042 13:58:33.673504
1043 13:58:33.674025 Set Vref, RX VrefLevel [Byte0]: 54
1044 13:58:33.676654 [Byte1]: 54
1045 13:58:33.680722
1046 13:58:33.681137 Set Vref, RX VrefLevel [Byte0]: 55
1047 13:58:33.684390 [Byte1]: 55
1048 13:58:33.688541
1049 13:58:33.688954 Set Vref, RX VrefLevel [Byte0]: 56
1050 13:58:33.691479 [Byte1]: 56
1051 13:58:33.696276
1052 13:58:33.696961 Set Vref, RX VrefLevel [Byte0]: 57
1053 13:58:33.699826 [Byte1]: 57
1054 13:58:33.703897
1055 13:58:33.704315 Set Vref, RX VrefLevel [Byte0]: 58
1056 13:58:33.707315 [Byte1]: 58
1057 13:58:33.711655
1058 13:58:33.712152 Set Vref, RX VrefLevel [Byte0]: 59
1059 13:58:33.714374 [Byte1]: 59
1060 13:58:33.718646
1061 13:58:33.719118 Set Vref, RX VrefLevel [Byte0]: 60
1062 13:58:33.722541 [Byte1]: 60
1063 13:58:33.726660
1064 13:58:33.727237 Set Vref, RX VrefLevel [Byte0]: 61
1065 13:58:33.729593 [Byte1]: 61
1066 13:58:33.733969
1067 13:58:33.734392 Set Vref, RX VrefLevel [Byte0]: 62
1068 13:58:33.737356 [Byte1]: 62
1069 13:58:33.742031
1070 13:58:33.742452 Set Vref, RX VrefLevel [Byte0]: 63
1071 13:58:33.745225 [Byte1]: 63
1072 13:58:33.749249
1073 13:58:33.749792 Set Vref, RX VrefLevel [Byte0]: 64
1074 13:58:33.752499 [Byte1]: 64
1075 13:58:33.756598
1076 13:58:33.757230 Set Vref, RX VrefLevel [Byte0]: 65
1077 13:58:33.760222 [Byte1]: 65
1078 13:58:33.764471
1079 13:58:33.764893 Set Vref, RX VrefLevel [Byte0]: 66
1080 13:58:33.767556 [Byte1]: 66
1081 13:58:33.772172
1082 13:58:33.772720 Set Vref, RX VrefLevel [Byte0]: 67
1083 13:58:33.775229 [Byte1]: 67
1084 13:58:33.779283
1085 13:58:33.779838 Set Vref, RX VrefLevel [Byte0]: 68
1086 13:58:33.783339 [Byte1]: 68
1087 13:58:33.787743
1088 13:58:33.788256 Set Vref, RX VrefLevel [Byte0]: 69
1089 13:58:33.790764 [Byte1]: 69
1090 13:58:33.795364
1091 13:58:33.795871 Set Vref, RX VrefLevel [Byte0]: 70
1092 13:58:33.798609 [Byte1]: 70
1093 13:58:33.802832
1094 13:58:33.803257 Set Vref, RX VrefLevel [Byte0]: 71
1095 13:58:33.806071 [Byte1]: 71
1096 13:58:33.810642
1097 13:58:33.811207 Set Vref, RX VrefLevel [Byte0]: 72
1098 13:58:33.813410 [Byte1]: 72
1099 13:58:33.817608
1100 13:58:33.818130 Set Vref, RX VrefLevel [Byte0]: 73
1101 13:58:33.821186 [Byte1]: 73
1102 13:58:33.825686
1103 13:58:33.826208 Set Vref, RX VrefLevel [Byte0]: 74
1104 13:58:33.829093 [Byte1]: 74
1105 13:58:33.833496
1106 13:58:33.834021 Set Vref, RX VrefLevel [Byte0]: 75
1107 13:58:33.836063 [Byte1]: 75
1108 13:58:33.840766
1109 13:58:33.841205 Set Vref, RX VrefLevel [Byte0]: 76
1110 13:58:33.843945 [Byte1]: 76
1111 13:58:33.848099
1112 13:58:33.848625 Final RX Vref Byte 0 = 61 to rank0
1113 13:58:33.851242 Final RX Vref Byte 1 = 54 to rank0
1114 13:58:33.854441 Final RX Vref Byte 0 = 61 to rank1
1115 13:58:33.858382 Final RX Vref Byte 1 = 54 to rank1==
1116 13:58:33.861796 Dram Type= 6, Freq= 0, CH_0, rank 0
1117 13:58:33.864784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1118 13:58:33.868354 ==
1119 13:58:33.868862 DQS Delay:
1120 13:58:33.869205 DQS0 = 0, DQS1 = 0
1121 13:58:33.871522 DQM Delay:
1122 13:58:33.872006 DQM0 = 88, DQM1 = 79
1123 13:58:33.875135 DQ Delay:
1124 13:58:33.875616 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1125 13:58:33.877950 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1126 13:58:33.881259 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1127 13:58:33.885399 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1128 13:58:33.885927
1129 13:58:33.888776
1130 13:58:33.894965 [DQSOSCAuto] RK0, (LSB)MR18= 0x260e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1131 13:58:33.898689 CH0 RK0: MR19=606, MR18=260E
1132 13:58:33.905735 CH0_RK0: MR19=0x606, MR18=0x260E, DQSOSC=400, MR23=63, INC=92, DEC=61
1133 13:58:33.906266
1134 13:58:33.909069 ----->DramcWriteLeveling(PI) begin...
1135 13:58:33.909603 ==
1136 13:58:33.911693 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 13:58:33.915213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 13:58:33.915743 ==
1139 13:58:33.918338 Write leveling (Byte 0): 32 => 32
1140 13:58:33.922251 Write leveling (Byte 1): 31 => 31
1141 13:58:33.925502 DramcWriteLeveling(PI) end<-----
1142 13:58:33.926048
1143 13:58:33.926393 ==
1144 13:58:33.929073 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 13:58:33.931871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 13:58:33.932295 ==
1147 13:58:33.935438 [Gating] SW mode calibration
1148 13:58:33.941968 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1149 13:58:33.945620 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1150 13:58:33.952168 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 13:58:33.995963 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1152 13:58:33.996779 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1153 13:58:33.997156 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:58:33.997478 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:58:33.997789 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:58:33.998160 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:58:33.998472 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:58:33.998816 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:58:33.999121 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:58:33.999411 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:58:34.028437 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:58:34.029324 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:58:34.029694 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:58:34.030015 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:58:34.030381 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:58:34.030693 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:58:34.031029 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1168 13:58:34.031321 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1169 13:58:34.036326 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:58:34.039505 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:58:34.042855 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:58:34.046763 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:58:34.053372 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:58:34.056857 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:58:34.059867 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:58:34.066817 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (1 1) (0 0)
1177 13:58:34.070133 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1178 13:58:34.073591 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 13:58:34.079736 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 13:58:34.083185 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:58:34.087061 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 13:58:34.093527 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 13:58:34.097403 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
1184 13:58:34.100079 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
1185 13:58:34.103212 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1186 13:58:34.110271 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:58:34.113787 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:58:34.117342 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:58:34.124202 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:58:34.128389 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:58:34.131717 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1192 13:58:34.135560 0 11 8 | B1->B0 | 2e2e 3e3e | 0 1 | (0 0) (0 0)
1193 13:58:34.138678 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
1194 13:58:34.145699 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 13:58:34.149241 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 13:58:34.153141 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:58:34.156379 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:58:34.163741 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 13:58:34.166820 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 13:58:34.170534 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1201 13:58:34.176871 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1202 13:58:34.179828 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:58:34.183211 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:58:34.190405 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:58:34.193296 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:58:34.196638 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:58:34.203468 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:58:34.206686 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:58:34.209859 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:58:34.213417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:58:34.220771 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:58:34.223615 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:58:34.227105 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:58:34.233744 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:58:34.237219 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 13:58:34.240568 Total UI for P1: 0, mck2ui 16
1217 13:58:34.244017 best dqsien dly found for B0: ( 0, 14, 2)
1218 13:58:34.247067 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 13:58:34.254118 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 13:58:34.254651 Total UI for P1: 0, mck2ui 16
1221 13:58:34.257351 best dqsien dly found for B1: ( 0, 14, 6)
1222 13:58:34.263609 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1223 13:58:34.267226 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1224 13:58:34.267640
1225 13:58:34.270805 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1226 13:58:34.274040 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1227 13:58:34.277558 [Gating] SW calibration Done
1228 13:58:34.278081 ==
1229 13:58:34.280818 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 13:58:34.284130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 13:58:34.284548 ==
1232 13:58:34.284880 RX Vref Scan: 0
1233 13:58:34.287370
1234 13:58:34.287781 RX Vref 0 -> 0, step: 1
1235 13:58:34.288107
1236 13:58:34.290571 RX Delay -130 -> 252, step: 16
1237 13:58:34.294176 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1238 13:58:34.297158 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1239 13:58:34.304304 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1240 13:58:34.307145 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1241 13:58:34.311030 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1242 13:58:34.314230 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1243 13:58:34.317408 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1244 13:58:34.324538 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1245 13:58:34.327679 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1246 13:58:34.330839 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1247 13:58:34.334303 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1248 13:58:34.338090 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1249 13:58:34.341091 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1250 13:58:34.347519 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1251 13:58:34.351259 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1252 13:58:34.354569 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1253 13:58:34.355128 ==
1254 13:58:34.357810 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 13:58:34.360878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 13:58:34.361490 ==
1257 13:58:34.364261 DQS Delay:
1258 13:58:34.364741 DQS0 = 0, DQS1 = 0
1259 13:58:34.367789 DQM Delay:
1260 13:58:34.368214 DQM0 = 85, DQM1 = 76
1261 13:58:34.368608 DQ Delay:
1262 13:58:34.370979 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1263 13:58:34.374589 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1264 13:58:34.378246 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1265 13:58:34.381201 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1266 13:58:34.381616
1267 13:58:34.382036
1268 13:58:34.382439 ==
1269 13:58:34.384703 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 13:58:34.391742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 13:58:34.392165 ==
1272 13:58:34.392646
1273 13:58:34.392991
1274 13:58:34.393290 TX Vref Scan disable
1275 13:58:34.395108 == TX Byte 0 ==
1276 13:58:34.398584 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1277 13:58:34.402004 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1278 13:58:34.405259 == TX Byte 1 ==
1279 13:58:34.408337 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1280 13:58:34.412247 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1281 13:58:34.415555 ==
1282 13:58:34.415969 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 13:58:34.422031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 13:58:34.422451 ==
1285 13:58:34.434005 TX Vref=22, minBit 3, minWin=27, winSum=446
1286 13:58:34.437558 TX Vref=24, minBit 3, minWin=27, winSum=448
1287 13:58:34.440817 TX Vref=26, minBit 9, minWin=27, winSum=451
1288 13:58:34.444340 TX Vref=28, minBit 9, minWin=27, winSum=455
1289 13:58:34.447691 TX Vref=30, minBit 3, minWin=28, winSum=457
1290 13:58:34.451134 TX Vref=32, minBit 4, minWin=28, winSum=456
1291 13:58:34.457365 [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 30
1292 13:58:34.457802
1293 13:58:34.461435 Final TX Range 1 Vref 30
1294 13:58:34.461849
1295 13:58:34.462172 ==
1296 13:58:34.464422 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 13:58:34.467660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 13:58:34.468078 ==
1299 13:58:34.468405
1300 13:58:34.468706
1301 13:58:34.471021 TX Vref Scan disable
1302 13:58:34.474530 == TX Byte 0 ==
1303 13:58:34.477746 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1304 13:58:34.480925 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1305 13:58:34.484509 == TX Byte 1 ==
1306 13:58:34.488062 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1307 13:58:34.491229 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1308 13:58:34.491407
1309 13:58:34.494262 [DATLAT]
1310 13:58:34.494438 Freq=800, CH0 RK1
1311 13:58:34.494579
1312 13:58:34.497821 DATLAT Default: 0xa
1313 13:58:34.497901 0, 0xFFFF, sum = 0
1314 13:58:34.500815 1, 0xFFFF, sum = 0
1315 13:58:34.500896 2, 0xFFFF, sum = 0
1316 13:58:34.504412 3, 0xFFFF, sum = 0
1317 13:58:34.504494 4, 0xFFFF, sum = 0
1318 13:58:34.508498 5, 0xFFFF, sum = 0
1319 13:58:34.508579 6, 0xFFFF, sum = 0
1320 13:58:34.511169 7, 0xFFFF, sum = 0
1321 13:58:34.511251 8, 0xFFFF, sum = 0
1322 13:58:34.514032 9, 0x0, sum = 1
1323 13:58:34.514112 10, 0x0, sum = 2
1324 13:58:34.517625 11, 0x0, sum = 3
1325 13:58:34.517707 12, 0x0, sum = 4
1326 13:58:34.521018 best_step = 10
1327 13:58:34.521098
1328 13:58:34.521161 ==
1329 13:58:34.524374 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 13:58:34.528068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 13:58:34.528149 ==
1332 13:58:34.528212 RX Vref Scan: 0
1333 13:58:34.528273
1334 13:58:34.530989 RX Vref 0 -> 0, step: 1
1335 13:58:34.531069
1336 13:58:34.534692 RX Delay -95 -> 252, step: 8
1337 13:58:34.538174 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1338 13:58:34.544644 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1339 13:58:34.547981 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1340 13:58:34.551882 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1341 13:58:34.554640 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1342 13:58:34.557875 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1343 13:58:34.561838 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1344 13:58:34.568326 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1345 13:58:34.571632 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1346 13:58:34.575037 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1347 13:58:34.577978 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1348 13:58:34.581369 iDelay=209, Bit 11, Center 72 (-31 ~ 176) 208
1349 13:58:34.588383 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1350 13:58:34.591688 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1351 13:58:34.595102 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1352 13:58:34.598108 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1353 13:58:34.598188 ==
1354 13:58:34.601488 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 13:58:34.608650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 13:58:34.608730 ==
1357 13:58:34.608793 DQS Delay:
1358 13:58:34.608852 DQS0 = 0, DQS1 = 0
1359 13:58:34.611885 DQM Delay:
1360 13:58:34.611965 DQM0 = 87, DQM1 = 78
1361 13:58:34.615331 DQ Delay:
1362 13:58:34.618326 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1363 13:58:34.618405 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1364 13:58:34.621596 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1365 13:58:34.625021 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1366 13:58:34.628328
1367 13:58:34.628407
1368 13:58:34.635634 [DQSOSCAuto] RK1, (LSB)MR18= 0x351d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1369 13:58:34.638497 CH0 RK1: MR19=606, MR18=351D
1370 13:58:34.645075 CH0_RK1: MR19=0x606, MR18=0x351D, DQSOSC=396, MR23=63, INC=94, DEC=62
1371 13:58:34.645157 [RxdqsGatingPostProcess] freq 800
1372 13:58:34.652300 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 13:58:34.655195 Pre-setting of DQS Precalculation
1374 13:58:34.661752 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 13:58:34.661835 ==
1376 13:58:34.665430 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 13:58:34.668538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 13:58:34.668619 ==
1379 13:58:34.672019 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 13:58:34.678646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 13:58:34.688843 [CA 0] Center 36 (6~66) winsize 61
1382 13:58:34.691828 [CA 1] Center 36 (6~66) winsize 61
1383 13:58:34.695029 [CA 2] Center 35 (5~65) winsize 61
1384 13:58:34.698702 [CA 3] Center 34 (3~65) winsize 63
1385 13:58:34.702757 [CA 4] Center 34 (4~65) winsize 62
1386 13:58:34.705615 [CA 5] Center 33 (3~64) winsize 62
1387 13:58:34.705695
1388 13:58:34.708899 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1389 13:58:34.708980
1390 13:58:34.712114 [CATrainingPosCal] consider 1 rank data
1391 13:58:34.715240 u2DelayCellTimex100 = 270/100 ps
1392 13:58:34.718927 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1393 13:58:34.722165 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1394 13:58:34.725520 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1395 13:58:34.732426 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1396 13:58:34.735477 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1397 13:58:34.739016 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 13:58:34.739097
1399 13:58:34.742034 CA PerBit enable=1, Macro0, CA PI delay=33
1400 13:58:34.742114
1401 13:58:34.745525 [CBTSetCACLKResult] CA Dly = 33
1402 13:58:34.745606 CS Dly: 5 (0~36)
1403 13:58:34.745670 ==
1404 13:58:34.748970 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 13:58:34.755580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 13:58:34.755686 ==
1407 13:58:34.758873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 13:58:34.765825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 13:58:34.774673 [CA 0] Center 36 (6~66) winsize 61
1410 13:58:34.777741 [CA 1] Center 36 (6~66) winsize 61
1411 13:58:34.781098 [CA 2] Center 34 (4~64) winsize 61
1412 13:58:34.784745 [CA 3] Center 33 (3~64) winsize 62
1413 13:58:34.788219 [CA 4] Center 34 (4~65) winsize 62
1414 13:58:34.792133 [CA 5] Center 33 (3~64) winsize 62
1415 13:58:34.792216
1416 13:58:34.795089 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1417 13:58:34.795172
1418 13:58:34.798960 [CATrainingPosCal] consider 2 rank data
1419 13:58:34.802862 u2DelayCellTimex100 = 270/100 ps
1420 13:58:34.806692 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 13:58:34.810608 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1422 13:58:34.814617 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1423 13:58:34.818072 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 13:58:34.821589 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1425 13:58:34.825094 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1426 13:58:34.825175
1427 13:58:34.828728 CA PerBit enable=1, Macro0, CA PI delay=33
1428 13:58:34.828810
1429 13:58:34.832135 [CBTSetCACLKResult] CA Dly = 33
1430 13:58:34.832217 CS Dly: 5 (0~36)
1431 13:58:34.832282
1432 13:58:34.835645 ----->DramcWriteLeveling(PI) begin...
1433 13:58:34.835727 ==
1434 13:58:34.838842 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 13:58:34.841844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 13:58:34.845304 ==
1437 13:58:34.845386 Write leveling (Byte 0): 28 => 28
1438 13:58:34.848703 Write leveling (Byte 1): 29 => 29
1439 13:58:34.852449 DramcWriteLeveling(PI) end<-----
1440 13:58:34.852530
1441 13:58:34.852595 ==
1442 13:58:34.855594 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 13:58:34.862119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 13:58:34.862201 ==
1445 13:58:34.862267 [Gating] SW mode calibration
1446 13:58:34.872393 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 13:58:34.875906 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 13:58:34.879344 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 13:58:34.886018 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 13:58:34.889472 0 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1451 13:58:34.892589 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:58:34.899559 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:58:34.902678 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:58:34.906116 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:58:34.912929 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:58:34.916358 0 7 0 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1457 13:58:34.919483 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:58:34.922932 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:58:34.929999 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1460 13:58:34.933000 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:58:34.936474 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:58:34.943087 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:58:34.946434 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:58:34.949857 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:58:34.956536 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1466 13:58:34.959773 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:58:34.962929 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:58:34.969995 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:58:34.972812 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:58:34.977011 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:58:34.979888 0 8 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1472 13:58:34.986838 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:58:34.990062 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1474 13:58:34.993434 0 9 8 | B1->B0 | 2727 2626 | 0 1 | (0 0) (1 1)
1475 13:58:35.000055 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 13:58:35.003255 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 13:58:35.006585 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 13:58:35.013389 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 13:58:35.017005 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 13:58:35.020125 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 13:58:35.026990 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 13:58:35.030124 0 10 8 | B1->B0 | 2d2d 3131 | 0 0 | (1 0) (0 0)
1483 13:58:35.033268 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1484 13:58:35.040384 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:58:35.043419 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:58:35.046959 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:58:35.050034 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:58:35.056977 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1489 13:58:35.060425 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1490 13:58:35.063960 0 11 8 | B1->B0 | 3737 3333 | 0 1 | (0 0) (0 0)
1491 13:58:35.070877 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 13:58:35.073797 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 13:58:35.077363 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 13:58:35.084342 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:58:35.087325 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 13:58:35.090636 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 13:58:35.097206 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1498 13:58:35.100521 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1499 13:58:35.104099 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:58:35.107182 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:58:35.114052 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:58:35.117368 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:58:35.120584 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:58:35.127701 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:58:35.131172 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:58:35.134362 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:58:35.141241 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:58:35.144383 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:58:35.148386 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:58:35.154714 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:58:35.158138 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:58:35.162266 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:58:35.164602 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:58:35.171476 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 13:58:35.174565 Total UI for P1: 0, mck2ui 16
1516 13:58:35.178356 best dqsien dly found for B0: ( 0, 14, 6)
1517 13:58:35.178439 Total UI for P1: 0, mck2ui 16
1518 13:58:35.184946 best dqsien dly found for B1: ( 0, 14, 6)
1519 13:58:35.187984 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1520 13:58:35.191280 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1521 13:58:35.191361
1522 13:58:35.195018 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1523 13:58:35.198224 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 13:58:35.201492 [Gating] SW calibration Done
1525 13:58:35.201599 ==
1526 13:58:35.204827 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 13:58:35.208191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 13:58:35.208273 ==
1529 13:58:35.211570 RX Vref Scan: 0
1530 13:58:35.211651
1531 13:58:35.211716 RX Vref 0 -> 0, step: 1
1532 13:58:35.211776
1533 13:58:35.215171 RX Delay -130 -> 252, step: 16
1534 13:58:35.218230 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1535 13:58:35.221764 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1536 13:58:35.228561 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1537 13:58:35.232061 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1538 13:58:35.235094 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1539 13:58:35.238569 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1540 13:58:35.242092 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1541 13:58:35.248630 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1542 13:58:35.251953 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1543 13:58:35.255382 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1544 13:58:35.258632 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1545 13:58:35.262140 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1546 13:58:35.268779 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1547 13:58:35.272322 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1548 13:58:35.275514 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1549 13:58:35.278921 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1550 13:58:35.279004 ==
1551 13:58:35.282189 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 13:58:35.285721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 13:58:35.289359 ==
1554 13:58:35.289439 DQS Delay:
1555 13:58:35.289504 DQS0 = 0, DQS1 = 0
1556 13:58:35.292488 DQM Delay:
1557 13:58:35.292567 DQM0 = 84, DQM1 = 73
1558 13:58:35.296288 DQ Delay:
1559 13:58:35.296368 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1560 13:58:35.299435 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =77
1561 13:58:35.302513 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1562 13:58:35.305932 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =77
1563 13:58:35.306012
1564 13:58:35.306075
1565 13:58:35.309267 ==
1566 13:58:35.312776 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 13:58:35.315886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 13:58:35.315967 ==
1569 13:58:35.316031
1570 13:58:35.316089
1571 13:58:35.319613 TX Vref Scan disable
1572 13:58:35.319694 == TX Byte 0 ==
1573 13:58:35.322612 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1574 13:58:35.329203 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1575 13:58:35.329298 == TX Byte 1 ==
1576 13:58:35.332557 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1577 13:58:35.339281 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1578 13:58:35.339362 ==
1579 13:58:35.342998 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 13:58:35.346070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 13:58:35.346150 ==
1582 13:58:35.359013 TX Vref=22, minBit 0, minWin=27, winSum=439
1583 13:58:35.362392 TX Vref=24, minBit 1, minWin=27, winSum=444
1584 13:58:35.365857 TX Vref=26, minBit 0, minWin=27, winSum=446
1585 13:58:35.369414 TX Vref=28, minBit 0, minWin=27, winSum=449
1586 13:58:35.372744 TX Vref=30, minBit 0, minWin=28, winSum=454
1587 13:58:35.376673 TX Vref=32, minBit 0, minWin=28, winSum=454
1588 13:58:35.383387 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1589 13:58:35.383469
1590 13:58:35.386534 Final TX Range 1 Vref 30
1591 13:58:35.386615
1592 13:58:35.386678 ==
1593 13:58:35.390451 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 13:58:35.393732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 13:58:35.393813 ==
1596 13:58:35.393876
1597 13:58:35.393935
1598 13:58:35.396672 TX Vref Scan disable
1599 13:58:35.400396 == TX Byte 0 ==
1600 13:58:35.403525 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1601 13:58:35.407007 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1602 13:58:35.410166 == TX Byte 1 ==
1603 13:58:35.413769 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1604 13:58:35.417181 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1605 13:58:35.417262
1606 13:58:35.417324 [DATLAT]
1607 13:58:35.420054 Freq=800, CH1 RK0
1608 13:58:35.420135
1609 13:58:35.423555 DATLAT Default: 0xa
1610 13:58:35.423635 0, 0xFFFF, sum = 0
1611 13:58:35.426739 1, 0xFFFF, sum = 0
1612 13:58:35.426835 2, 0xFFFF, sum = 0
1613 13:58:35.430399 3, 0xFFFF, sum = 0
1614 13:58:35.430480 4, 0xFFFF, sum = 0
1615 13:58:35.433704 5, 0xFFFF, sum = 0
1616 13:58:35.433786 6, 0xFFFF, sum = 0
1617 13:58:35.436756 7, 0xFFFF, sum = 0
1618 13:58:35.436858 8, 0xFFFF, sum = 0
1619 13:58:35.440194 9, 0x0, sum = 1
1620 13:58:35.440307 10, 0x0, sum = 2
1621 13:58:35.440373 11, 0x0, sum = 3
1622 13:58:35.443541 12, 0x0, sum = 4
1623 13:58:35.443622 best_step = 10
1624 13:58:35.443705
1625 13:58:35.446968 ==
1626 13:58:35.447049 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 13:58:35.453876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 13:58:35.453972 ==
1629 13:58:35.454036 RX Vref Scan: 1
1630 13:58:35.454096
1631 13:58:35.456763 Set Vref Range= 32 -> 127
1632 13:58:35.456843
1633 13:58:35.460439 RX Vref 32 -> 127, step: 1
1634 13:58:35.460519
1635 13:58:35.463670 RX Delay -111 -> 252, step: 8
1636 13:58:35.463751
1637 13:58:35.467240 Set Vref, RX VrefLevel [Byte0]: 32
1638 13:58:35.470169 [Byte1]: 32
1639 13:58:35.470249
1640 13:58:35.473452 Set Vref, RX VrefLevel [Byte0]: 33
1641 13:58:35.477136 [Byte1]: 33
1642 13:58:35.477217
1643 13:58:35.480131 Set Vref, RX VrefLevel [Byte0]: 34
1644 13:58:35.484059 [Byte1]: 34
1645 13:58:35.487292
1646 13:58:35.487398 Set Vref, RX VrefLevel [Byte0]: 35
1647 13:58:35.490681 [Byte1]: 35
1648 13:58:35.494851
1649 13:58:35.494932 Set Vref, RX VrefLevel [Byte0]: 36
1650 13:58:35.497843 [Byte1]: 36
1651 13:58:35.502067
1652 13:58:35.502163 Set Vref, RX VrefLevel [Byte0]: 37
1653 13:58:35.506048 [Byte1]: 37
1654 13:58:35.509896
1655 13:58:35.509977 Set Vref, RX VrefLevel [Byte0]: 38
1656 13:58:35.513472 [Byte1]: 38
1657 13:58:35.517564
1658 13:58:35.517645 Set Vref, RX VrefLevel [Byte0]: 39
1659 13:58:35.521206 [Byte1]: 39
1660 13:58:35.525783
1661 13:58:35.525869 Set Vref, RX VrefLevel [Byte0]: 40
1662 13:58:35.529105 [Byte1]: 40
1663 13:58:35.533386
1664 13:58:35.533465 Set Vref, RX VrefLevel [Byte0]: 41
1665 13:58:35.536169 [Byte1]: 41
1666 13:58:35.540445
1667 13:58:35.540525 Set Vref, RX VrefLevel [Byte0]: 42
1668 13:58:35.544070 [Byte1]: 42
1669 13:58:35.548376
1670 13:58:35.548455 Set Vref, RX VrefLevel [Byte0]: 43
1671 13:58:35.551686 [Byte1]: 43
1672 13:58:35.556408
1673 13:58:35.556488 Set Vref, RX VrefLevel [Byte0]: 44
1674 13:58:35.559173 [Byte1]: 44
1675 13:58:35.563521
1676 13:58:35.563612 Set Vref, RX VrefLevel [Byte0]: 45
1677 13:58:35.566685 [Byte1]: 45
1678 13:58:35.571457
1679 13:58:35.571548 Set Vref, RX VrefLevel [Byte0]: 46
1680 13:58:35.574320 [Byte1]: 46
1681 13:58:35.579009
1682 13:58:35.579089 Set Vref, RX VrefLevel [Byte0]: 47
1683 13:58:35.582294 [Byte1]: 47
1684 13:58:35.586504
1685 13:58:35.586584 Set Vref, RX VrefLevel [Byte0]: 48
1686 13:58:35.590306 [Byte1]: 48
1687 13:58:35.594125
1688 13:58:35.594205 Set Vref, RX VrefLevel [Byte0]: 49
1689 13:58:35.597510 [Byte1]: 49
1690 13:58:35.601673
1691 13:58:35.601753 Set Vref, RX VrefLevel [Byte0]: 50
1692 13:58:35.604810 [Byte1]: 50
1693 13:58:35.609534
1694 13:58:35.609614 Set Vref, RX VrefLevel [Byte0]: 51
1695 13:58:35.612604 [Byte1]: 51
1696 13:58:35.617215
1697 13:58:35.617295 Set Vref, RX VrefLevel [Byte0]: 52
1698 13:58:35.620329 [Byte1]: 52
1699 13:58:35.624569
1700 13:58:35.624649 Set Vref, RX VrefLevel [Byte0]: 53
1701 13:58:35.627929 [Byte1]: 53
1702 13:58:35.632155
1703 13:58:35.632235 Set Vref, RX VrefLevel [Byte0]: 54
1704 13:58:35.635760 [Byte1]: 54
1705 13:58:35.639849
1706 13:58:35.639928 Set Vref, RX VrefLevel [Byte0]: 55
1707 13:58:35.643170 [Byte1]: 55
1708 13:58:35.647693
1709 13:58:35.647774 Set Vref, RX VrefLevel [Byte0]: 56
1710 13:58:35.650668 [Byte1]: 56
1711 13:58:35.655071
1712 13:58:35.655151 Set Vref, RX VrefLevel [Byte0]: 57
1713 13:58:35.658725 [Byte1]: 57
1714 13:58:35.662808
1715 13:58:35.662889 Set Vref, RX VrefLevel [Byte0]: 58
1716 13:58:35.666043 [Byte1]: 58
1717 13:58:35.670155
1718 13:58:35.670238 Set Vref, RX VrefLevel [Byte0]: 59
1719 13:58:35.673687 [Byte1]: 59
1720 13:58:35.678244
1721 13:58:35.678324 Set Vref, RX VrefLevel [Byte0]: 60
1722 13:58:35.682082 [Byte1]: 60
1723 13:58:35.685848
1724 13:58:35.685932 Set Vref, RX VrefLevel [Byte0]: 61
1725 13:58:35.689057 [Byte1]: 61
1726 13:58:35.693632
1727 13:58:35.693712 Set Vref, RX VrefLevel [Byte0]: 62
1728 13:58:35.696905 [Byte1]: 62
1729 13:58:35.701022
1730 13:58:35.701102 Set Vref, RX VrefLevel [Byte0]: 63
1731 13:58:35.704364 [Byte1]: 63
1732 13:58:35.708590
1733 13:58:35.708670 Set Vref, RX VrefLevel [Byte0]: 64
1734 13:58:35.712170 [Byte1]: 64
1735 13:58:35.716575
1736 13:58:35.716655 Set Vref, RX VrefLevel [Byte0]: 65
1737 13:58:35.719908 [Byte1]: 65
1738 13:58:35.724217
1739 13:58:35.724297 Set Vref, RX VrefLevel [Byte0]: 66
1740 13:58:35.727009 [Byte1]: 66
1741 13:58:35.731445
1742 13:58:35.731551 Set Vref, RX VrefLevel [Byte0]: 67
1743 13:58:35.734879 [Byte1]: 67
1744 13:58:35.739582
1745 13:58:35.739662 Set Vref, RX VrefLevel [Byte0]: 68
1746 13:58:35.742647 [Byte1]: 68
1747 13:58:35.746842
1748 13:58:35.746922 Set Vref, RX VrefLevel [Byte0]: 69
1749 13:58:35.751046 [Byte1]: 69
1750 13:58:35.754695
1751 13:58:35.754817 Set Vref, RX VrefLevel [Byte0]: 70
1752 13:58:35.758044 [Byte1]: 70
1753 13:58:35.762745
1754 13:58:35.762839 Set Vref, RX VrefLevel [Byte0]: 71
1755 13:58:35.765676 [Byte1]: 71
1756 13:58:35.769977
1757 13:58:35.770057 Set Vref, RX VrefLevel [Byte0]: 72
1758 13:58:35.773640 [Byte1]: 72
1759 13:58:35.777347
1760 13:58:35.777428 Set Vref, RX VrefLevel [Byte0]: 73
1761 13:58:35.780534 [Byte1]: 73
1762 13:58:35.785002
1763 13:58:35.785083 Set Vref, RX VrefLevel [Byte0]: 74
1764 13:58:35.788206 [Byte1]: 74
1765 13:58:35.792889
1766 13:58:35.792968 Set Vref, RX VrefLevel [Byte0]: 75
1767 13:58:35.795846 [Byte1]: 75
1768 13:58:35.800486
1769 13:58:35.800566 Set Vref, RX VrefLevel [Byte0]: 76
1770 13:58:35.804180 [Byte1]: 76
1771 13:58:35.807917
1772 13:58:35.807997 Set Vref, RX VrefLevel [Byte0]: 77
1773 13:58:35.811360 [Byte1]: 77
1774 13:58:35.815921
1775 13:58:35.816000 Set Vref, RX VrefLevel [Byte0]: 78
1776 13:58:35.819479 [Byte1]: 78
1777 13:58:35.823268
1778 13:58:35.823347 Set Vref, RX VrefLevel [Byte0]: 79
1779 13:58:35.826863 [Byte1]: 79
1780 13:58:35.831235
1781 13:58:35.831315 Set Vref, RX VrefLevel [Byte0]: 80
1782 13:58:35.834336 [Byte1]: 80
1783 13:58:35.838598
1784 13:58:35.838704 Final RX Vref Byte 0 = 58 to rank0
1785 13:58:35.842371 Final RX Vref Byte 1 = 57 to rank0
1786 13:58:35.845629 Final RX Vref Byte 0 = 58 to rank1
1787 13:58:35.848744 Final RX Vref Byte 1 = 57 to rank1==
1788 13:58:35.852117 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 13:58:35.855315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 13:58:35.858667 ==
1791 13:58:35.858804 DQS Delay:
1792 13:58:35.858868 DQS0 = 0, DQS1 = 0
1793 13:58:35.862061 DQM Delay:
1794 13:58:35.862142 DQM0 = 83, DQM1 = 74
1795 13:58:35.865502 DQ Delay:
1796 13:58:35.865582 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1797 13:58:35.869239 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =76
1798 13:58:35.872229 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
1799 13:58:35.875786 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1800 13:58:35.875867
1801 13:58:35.878892
1802 13:58:35.885813 [DQSOSCAuto] RK0, (LSB)MR18= 0x2afe, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1803 13:58:35.889518 CH1 RK0: MR19=605, MR18=2AFE
1804 13:58:35.895750 CH1_RK0: MR19=0x605, MR18=0x2AFE, DQSOSC=399, MR23=63, INC=92, DEC=61
1805 13:58:35.895831
1806 13:58:35.899241 ----->DramcWriteLeveling(PI) begin...
1807 13:58:35.899323 ==
1808 13:58:35.902526 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 13:58:35.905827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 13:58:35.905908 ==
1811 13:58:35.909110 Write leveling (Byte 0): 30 => 30
1812 13:58:35.912968 Write leveling (Byte 1): 30 => 30
1813 13:58:35.915971 DramcWriteLeveling(PI) end<-----
1814 13:58:35.916051
1815 13:58:35.916115 ==
1816 13:58:35.919157 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 13:58:35.922923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 13:58:35.923004 ==
1819 13:58:35.925949 [Gating] SW mode calibration
1820 13:58:35.932556 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 13:58:35.936585 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 13:58:35.942902 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1823 13:58:35.946544 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1824 13:58:35.949472 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:58:35.956305 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:58:35.959700 0 6 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1827 13:58:35.963495 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:58:35.969678 0 6 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1829 13:58:35.973513 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:58:35.977172 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:58:35.983676 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:58:35.986462 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:58:35.990985 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:58:35.993378 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1835 13:58:36.000022 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 13:58:36.003570 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1837 13:58:36.006693 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:58:36.013786 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1839 13:58:36.016931 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1840 13:58:36.020389 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1841 13:58:36.026740 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:58:36.030214 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:58:36.033899 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 13:58:36.040561 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:58:36.044063 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:58:36.047184 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:58:36.050497 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:58:36.057386 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
1849 13:58:36.060433 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1850 13:58:36.064049 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 13:58:36.070600 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 13:58:36.074179 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1853 13:58:36.077156 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1854 13:58:36.084245 0 10 0 | B1->B0 | 3535 3333 | 0 0 | (0 0) (0 0)
1855 13:58:36.087711 0 10 4 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
1856 13:58:36.091006 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1857 13:58:36.094044 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1858 13:58:36.101006 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1859 13:58:36.103931 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1860 13:58:36.107493 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 13:58:36.114090 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1862 13:58:36.117423 0 11 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1863 13:58:36.120757 0 11 4 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
1864 13:58:36.127427 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
1865 13:58:36.130744 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 13:58:36.134489 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 13:58:36.141317 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 13:58:36.144404 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 13:58:36.147881 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 13:58:36.154608 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1871 13:58:36.158103 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1872 13:58:36.161283 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 13:58:36.164551 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 13:58:36.171456 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 13:58:36.174856 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 13:58:36.178208 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 13:58:36.184823 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 13:58:36.188399 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 13:58:36.191677 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 13:58:36.198265 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 13:58:36.201767 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 13:58:36.205339 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 13:58:36.208565 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 13:58:36.215420 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 13:58:36.218266 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 13:58:36.222271 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1887 13:58:36.228648 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1888 13:58:36.231776 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 13:58:36.235280 Total UI for P1: 0, mck2ui 16
1890 13:58:36.238399 best dqsien dly found for B0: ( 0, 14, 2)
1891 13:58:36.241882 Total UI for P1: 0, mck2ui 16
1892 13:58:36.245124 best dqsien dly found for B1: ( 0, 14, 4)
1893 13:58:36.248924 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1894 13:58:36.251913 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1895 13:58:36.251994
1896 13:58:36.255534 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1897 13:58:36.258544 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1898 13:58:36.262019 [Gating] SW calibration Done
1899 13:58:36.262099 ==
1900 13:58:36.265414 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 13:58:36.269048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 13:58:36.269135 ==
1903 13:58:36.272257 RX Vref Scan: 0
1904 13:58:36.272337
1905 13:58:36.275678 RX Vref 0 -> 0, step: 1
1906 13:58:36.275758
1907 13:58:36.275822 RX Delay -130 -> 252, step: 16
1908 13:58:36.282776 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1909 13:58:36.285747 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1910 13:58:36.288876 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1911 13:58:36.292326 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1912 13:58:36.295899 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1913 13:58:36.302696 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1914 13:58:36.306110 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1915 13:58:36.308822 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1916 13:58:36.312491 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1917 13:58:36.315872 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1918 13:58:36.319047 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1919 13:58:36.325911 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1920 13:58:36.329373 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1921 13:58:36.332683 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1922 13:58:36.335878 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1923 13:58:36.339541 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1924 13:58:36.343079 ==
1925 13:58:36.345776 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 13:58:36.349767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 13:58:36.349849 ==
1928 13:58:36.349913 DQS Delay:
1929 13:58:36.352779 DQS0 = 0, DQS1 = 0
1930 13:58:36.352858 DQM Delay:
1931 13:58:36.356422 DQM0 = 81, DQM1 = 79
1932 13:58:36.356502 DQ Delay:
1933 13:58:36.359836 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1934 13:58:36.362938 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1935 13:58:36.366471 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1936 13:58:36.369721 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1937 13:58:36.369802
1938 13:58:36.369865
1939 13:58:36.369923 ==
1940 13:58:36.373411 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 13:58:36.376975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 13:58:36.377056 ==
1943 13:58:36.377119
1944 13:58:36.377179
1945 13:58:36.379708 TX Vref Scan disable
1946 13:58:36.379788 == TX Byte 0 ==
1947 13:58:36.386500 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1948 13:58:36.389842 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1949 13:58:36.389923 == TX Byte 1 ==
1950 13:58:36.396611 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1951 13:58:36.399803 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1952 13:58:36.399884 ==
1953 13:58:36.403222 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 13:58:36.406512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 13:58:36.406592 ==
1956 13:58:36.420280 TX Vref=22, minBit 4, minWin=26, winSum=438
1957 13:58:36.423742 TX Vref=24, minBit 1, minWin=27, winSum=441
1958 13:58:36.427480 TX Vref=26, minBit 1, minWin=27, winSum=444
1959 13:58:36.430603 TX Vref=28, minBit 7, minWin=27, winSum=451
1960 13:58:36.433778 TX Vref=30, minBit 2, minWin=27, winSum=449
1961 13:58:36.437070 TX Vref=32, minBit 2, minWin=27, winSum=451
1962 13:58:36.443975 [TxChooseVref] Worse bit 7, Min win 27, Win sum 451, Final Vref 28
1963 13:58:36.444056
1964 13:58:36.447348 Final TX Range 1 Vref 28
1965 13:58:36.447429
1966 13:58:36.447493 ==
1967 13:58:36.450886 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 13:58:36.454358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 13:58:36.454439 ==
1970 13:58:36.454502
1971 13:58:36.454561
1972 13:58:36.457511 TX Vref Scan disable
1973 13:58:36.460672 == TX Byte 0 ==
1974 13:58:36.464101 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1975 13:58:36.467315 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1976 13:58:36.470680 == TX Byte 1 ==
1977 13:58:36.474032 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1978 13:58:36.477572 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1979 13:58:36.477655
1980 13:58:36.481273 [DATLAT]
1981 13:58:36.481354 Freq=800, CH1 RK1
1982 13:58:36.481417
1983 13:58:36.484263 DATLAT Default: 0xa
1984 13:58:36.484344 0, 0xFFFF, sum = 0
1985 13:58:36.487494 1, 0xFFFF, sum = 0
1986 13:58:36.487576 2, 0xFFFF, sum = 0
1987 13:58:36.490914 3, 0xFFFF, sum = 0
1988 13:58:36.491009 4, 0xFFFF, sum = 0
1989 13:58:36.494149 5, 0xFFFF, sum = 0
1990 13:58:36.494233 6, 0xFFFF, sum = 0
1991 13:58:36.497554 7, 0xFFFF, sum = 0
1992 13:58:36.497637 8, 0xFFFF, sum = 0
1993 13:58:36.501192 9, 0x0, sum = 1
1994 13:58:36.501274 10, 0x0, sum = 2
1995 13:58:36.504181 11, 0x0, sum = 3
1996 13:58:36.504263 12, 0x0, sum = 4
1997 13:58:36.507591 best_step = 10
1998 13:58:36.507673
1999 13:58:36.507738 ==
2000 13:58:36.511327 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 13:58:36.514503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 13:58:36.514585 ==
2003 13:58:36.514648 RX Vref Scan: 0
2004 13:58:36.514707
2005 13:58:36.517590 RX Vref 0 -> 0, step: 1
2006 13:58:36.517671
2007 13:58:36.520872 RX Delay -95 -> 252, step: 8
2008 13:58:36.524531 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2009 13:58:36.531226 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2010 13:58:36.534595 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2011 13:58:36.538224 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2012 13:58:36.541246 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2013 13:58:36.544814 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2014 13:58:36.548463 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2015 13:58:36.554677 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2016 13:58:36.558380 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2017 13:58:36.561615 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
2018 13:58:36.565269 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2019 13:58:36.568112 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2020 13:58:36.575046 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2021 13:58:36.578194 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2022 13:58:36.581540 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2023 13:58:36.584995 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2024 13:58:36.585079 ==
2025 13:58:36.588694 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 13:58:36.592020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 13:58:36.595221 ==
2028 13:58:36.595322 DQS Delay:
2029 13:58:36.595388 DQS0 = 0, DQS1 = 0
2030 13:58:36.598604 DQM Delay:
2031 13:58:36.598684 DQM0 = 80, DQM1 = 75
2032 13:58:36.601915 DQ Delay:
2033 13:58:36.601995 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2034 13:58:36.605339 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2035 13:58:36.608513 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68
2036 13:58:36.611828 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2037 13:58:36.611908
2038 13:58:36.615318
2039 13:58:36.622139 [DQSOSCAuto] RK1, (LSB)MR18= 0x222d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2040 13:58:36.625284 CH1 RK1: MR19=606, MR18=222D
2041 13:58:36.632223 CH1_RK1: MR19=0x606, MR18=0x222D, DQSOSC=398, MR23=63, INC=93, DEC=62
2042 13:58:36.632305 [RxdqsGatingPostProcess] freq 800
2043 13:58:36.638836 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2044 13:58:36.642433 Pre-setting of DQS Precalculation
2045 13:58:36.645729 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2046 13:58:36.655809 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2047 13:58:36.662576 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2048 13:58:36.662682
2049 13:58:36.662797
2050 13:58:36.665514 [Calibration Summary] 1600 Mbps
2051 13:58:36.665594 CH 0, Rank 0
2052 13:58:36.668963 SW Impedance : PASS
2053 13:58:36.669044 DUTY Scan : NO K
2054 13:58:36.672552 ZQ Calibration : PASS
2055 13:58:36.676097 Jitter Meter : NO K
2056 13:58:36.676177 CBT Training : PASS
2057 13:58:36.679139 Write leveling : PASS
2058 13:58:36.679220 RX DQS gating : PASS
2059 13:58:36.682599 RX DQ/DQS(RDDQC) : PASS
2060 13:58:36.685721 TX DQ/DQS : PASS
2061 13:58:36.685802 RX DATLAT : PASS
2062 13:58:36.689658 RX DQ/DQS(Engine): PASS
2063 13:58:36.692682 TX OE : NO K
2064 13:58:36.692762 All Pass.
2065 13:58:36.692825
2066 13:58:36.692884 CH 0, Rank 1
2067 13:58:36.696416 SW Impedance : PASS
2068 13:58:36.699155 DUTY Scan : NO K
2069 13:58:36.699245 ZQ Calibration : PASS
2070 13:58:36.702678 Jitter Meter : NO K
2071 13:58:36.705807 CBT Training : PASS
2072 13:58:36.705903 Write leveling : PASS
2073 13:58:36.709494 RX DQS gating : PASS
2074 13:58:36.712949 RX DQ/DQS(RDDQC) : PASS
2075 13:58:36.713030 TX DQ/DQS : PASS
2076 13:58:36.716379 RX DATLAT : PASS
2077 13:58:36.716459 RX DQ/DQS(Engine): PASS
2078 13:58:36.719539 TX OE : NO K
2079 13:58:36.719620 All Pass.
2080 13:58:36.719684
2081 13:58:36.722702 CH 1, Rank 0
2082 13:58:36.722822 SW Impedance : PASS
2083 13:58:36.725936 DUTY Scan : NO K
2084 13:58:36.729539 ZQ Calibration : PASS
2085 13:58:36.729619 Jitter Meter : NO K
2086 13:58:36.733163 CBT Training : PASS
2087 13:58:36.736187 Write leveling : PASS
2088 13:58:36.736267 RX DQS gating : PASS
2089 13:58:36.739622 RX DQ/DQS(RDDQC) : PASS
2090 13:58:36.743165 TX DQ/DQS : PASS
2091 13:58:36.743246 RX DATLAT : PASS
2092 13:58:36.746184 RX DQ/DQS(Engine): PASS
2093 13:58:36.746264 TX OE : NO K
2094 13:58:36.749579 All Pass.
2095 13:58:36.749660
2096 13:58:36.749723 CH 1, Rank 1
2097 13:58:36.753079 SW Impedance : PASS
2098 13:58:36.753159 DUTY Scan : NO K
2099 13:58:36.756455 ZQ Calibration : PASS
2100 13:58:36.759863 Jitter Meter : NO K
2101 13:58:36.759944 CBT Training : PASS
2102 13:58:36.763265 Write leveling : PASS
2103 13:58:36.766611 RX DQS gating : PASS
2104 13:58:36.766718 RX DQ/DQS(RDDQC) : PASS
2105 13:58:36.770077 TX DQ/DQS : PASS
2106 13:58:36.773625 RX DATLAT : PASS
2107 13:58:36.773706 RX DQ/DQS(Engine): PASS
2108 13:58:36.776779 TX OE : NO K
2109 13:58:36.776859 All Pass.
2110 13:58:36.776922
2111 13:58:36.780248 DramC Write-DBI off
2112 13:58:36.783540 PER_BANK_REFRESH: Hybrid Mode
2113 13:58:36.783621 TX_TRACKING: ON
2114 13:58:36.786930 [GetDramInforAfterCalByMRR] Vendor 6.
2115 13:58:36.790086 [GetDramInforAfterCalByMRR] Revision 606.
2116 13:58:36.793415 [GetDramInforAfterCalByMRR] Revision 2 0.
2117 13:58:36.793496 MR0 0x3b3b
2118 13:58:36.796805 MR8 0x5151
2119 13:58:36.800339 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 13:58:36.800419
2121 13:58:36.800482 MR0 0x3b3b
2122 13:58:36.803593 MR8 0x5151
2123 13:58:36.807252 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 13:58:36.807358
2125 13:58:36.813498 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2126 13:58:36.817031 [FAST_K] Save calibration result to emmc
2127 13:58:36.820504 [FAST_K] Save calibration result to emmc
2128 13:58:36.823908 dram_init: config_dvfs: 1
2129 13:58:36.827411 dramc_set_vcore_voltage set vcore to 662500
2130 13:58:36.830741 Read voltage for 1200, 2
2131 13:58:36.830822 Vio18 = 0
2132 13:58:36.833857 Vcore = 662500
2133 13:58:36.833936 Vdram = 0
2134 13:58:36.833999 Vddq = 0
2135 13:58:36.834058 Vmddr = 0
2136 13:58:36.840654 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2137 13:58:36.847675 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2138 13:58:36.847766 MEM_TYPE=3, freq_sel=15
2139 13:58:36.850780 sv_algorithm_assistance_LP4_1600
2140 13:58:36.854118 ============ PULL DRAM RESETB DOWN ============
2141 13:58:36.860640 ========== PULL DRAM RESETB DOWN end =========
2142 13:58:36.864511 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2143 13:58:36.867771 ===================================
2144 13:58:36.870629 LPDDR4 DRAM CONFIGURATION
2145 13:58:36.874333 ===================================
2146 13:58:36.874413 EX_ROW_EN[0] = 0x0
2147 13:58:36.877260 EX_ROW_EN[1] = 0x0
2148 13:58:36.877340 LP4Y_EN = 0x0
2149 13:58:36.880598 WORK_FSP = 0x0
2150 13:58:36.880678 WL = 0x4
2151 13:58:36.884223 RL = 0x4
2152 13:58:36.884303 BL = 0x2
2153 13:58:36.887773 RPST = 0x0
2154 13:58:36.887853 RD_PRE = 0x0
2155 13:58:36.890829 WR_PRE = 0x1
2156 13:58:36.890909 WR_PST = 0x0
2157 13:58:36.894598 DBI_WR = 0x0
2158 13:58:36.897565 DBI_RD = 0x0
2159 13:58:36.897644 OTF = 0x1
2160 13:58:36.900759 ===================================
2161 13:58:36.904246 ===================================
2162 13:58:36.904326 ANA top config
2163 13:58:36.907290 ===================================
2164 13:58:36.910599 DLL_ASYNC_EN = 0
2165 13:58:36.914333 ALL_SLAVE_EN = 0
2166 13:58:36.917267 NEW_RANK_MODE = 1
2167 13:58:36.917349 DLL_IDLE_MODE = 1
2168 13:58:36.920789 LP45_APHY_COMB_EN = 1
2169 13:58:36.924086 TX_ODT_DIS = 1
2170 13:58:36.927368 NEW_8X_MODE = 1
2171 13:58:36.930758 ===================================
2172 13:58:36.934108 ===================================
2173 13:58:36.937817 data_rate = 2400
2174 13:58:36.937898 CKR = 1
2175 13:58:36.940806 DQ_P2S_RATIO = 8
2176 13:58:36.944605 ===================================
2177 13:58:36.947609 CA_P2S_RATIO = 8
2178 13:58:36.951522 DQ_CA_OPEN = 0
2179 13:58:36.954254 DQ_SEMI_OPEN = 0
2180 13:58:36.957945 CA_SEMI_OPEN = 0
2181 13:58:36.958025 CA_FULL_RATE = 0
2182 13:58:36.960866 DQ_CKDIV4_EN = 0
2183 13:58:36.964637 CA_CKDIV4_EN = 0
2184 13:58:36.968088 CA_PREDIV_EN = 0
2185 13:58:36.971377 PH8_DLY = 17
2186 13:58:36.974597 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2187 13:58:36.974703 DQ_AAMCK_DIV = 4
2188 13:58:36.978192 CA_AAMCK_DIV = 4
2189 13:58:36.981042 CA_ADMCK_DIV = 4
2190 13:58:36.985138 DQ_TRACK_CA_EN = 0
2191 13:58:36.987716 CA_PICK = 1200
2192 13:58:36.991035 CA_MCKIO = 1200
2193 13:58:36.991116 MCKIO_SEMI = 0
2194 13:58:36.994600 PLL_FREQ = 2366
2195 13:58:36.998116 DQ_UI_PI_RATIO = 32
2196 13:58:37.001102 CA_UI_PI_RATIO = 0
2197 13:58:37.004623 ===================================
2198 13:58:37.007675 ===================================
2199 13:58:37.011145 memory_type:LPDDR4
2200 13:58:37.011226 GP_NUM : 10
2201 13:58:37.014876 SRAM_EN : 1
2202 13:58:37.018218 MD32_EN : 0
2203 13:58:37.018299 ===================================
2204 13:58:37.021413 [ANA_INIT] >>>>>>>>>>>>>>
2205 13:58:37.024739 <<<<<< [CONFIGURE PHASE]: ANA_TX
2206 13:58:37.028080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2207 13:58:37.031574 ===================================
2208 13:58:37.034756 data_rate = 2400,PCW = 0X5b00
2209 13:58:37.038136 ===================================
2210 13:58:37.041368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2211 13:58:37.048195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 13:58:37.052200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 13:58:37.058439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2214 13:58:37.062224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2215 13:58:37.065069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2216 13:58:37.065151 [ANA_INIT] flow start
2217 13:58:37.068554 [ANA_INIT] PLL >>>>>>>>
2218 13:58:37.071713 [ANA_INIT] PLL <<<<<<<<
2219 13:58:37.071793 [ANA_INIT] MIDPI >>>>>>>>
2220 13:58:37.075522 [ANA_INIT] MIDPI <<<<<<<<
2221 13:58:37.078352 [ANA_INIT] DLL >>>>>>>>
2222 13:58:37.078426 [ANA_INIT] DLL <<<<<<<<
2223 13:58:37.081837 [ANA_INIT] flow end
2224 13:58:37.085053 ============ LP4 DIFF to SE enter ============
2225 13:58:37.088762 ============ LP4 DIFF to SE exit ============
2226 13:58:37.091883 [ANA_INIT] <<<<<<<<<<<<<
2227 13:58:37.095172 [Flow] Enable top DCM control >>>>>
2228 13:58:37.098818 [Flow] Enable top DCM control <<<<<
2229 13:58:37.101986 Enable DLL master slave shuffle
2230 13:58:37.105201 ==============================================================
2231 13:58:37.109110 Gating Mode config
2232 13:58:37.115500 ==============================================================
2233 13:58:37.115582 Config description:
2234 13:58:37.125908 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2235 13:58:37.132231 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2236 13:58:37.135848 SELPH_MODE 0: By rank 1: By Phase
2237 13:58:37.142306 ==============================================================
2238 13:58:37.145624 GAT_TRACK_EN = 1
2239 13:58:37.149372 RX_GATING_MODE = 2
2240 13:58:37.152552 RX_GATING_TRACK_MODE = 2
2241 13:58:37.155885 SELPH_MODE = 1
2242 13:58:37.159286 PICG_EARLY_EN = 1
2243 13:58:37.162236 VALID_LAT_VALUE = 1
2244 13:58:37.166015 ==============================================================
2245 13:58:37.169002 Enter into Gating configuration >>>>
2246 13:58:37.172895 Exit from Gating configuration <<<<
2247 13:58:37.175768 Enter into DVFS_PRE_config >>>>>
2248 13:58:37.186082 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2249 13:58:37.189264 Exit from DVFS_PRE_config <<<<<
2250 13:58:37.192854 Enter into PICG configuration >>>>
2251 13:58:37.195926 Exit from PICG configuration <<<<
2252 13:58:37.199186 [RX_INPUT] configuration >>>>>
2253 13:58:37.202817 [RX_INPUT] configuration <<<<<
2254 13:58:37.206172 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2255 13:58:37.212898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2256 13:58:37.219200 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 13:58:37.225874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 13:58:37.232676 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 13:58:37.235935 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 13:58:37.243163 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2261 13:58:37.246212 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2262 13:58:37.249612 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2263 13:58:37.253032 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2264 13:58:37.256313 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2265 13:58:37.262893 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 13:58:37.266356 ===================================
2267 13:58:37.266437 LPDDR4 DRAM CONFIGURATION
2268 13:58:37.270123 ===================================
2269 13:58:37.272892 EX_ROW_EN[0] = 0x0
2270 13:58:37.276416 EX_ROW_EN[1] = 0x0
2271 13:58:37.276496 LP4Y_EN = 0x0
2272 13:58:37.279543 WORK_FSP = 0x0
2273 13:58:37.279623 WL = 0x4
2274 13:58:37.283370 RL = 0x4
2275 13:58:37.283449 BL = 0x2
2276 13:58:37.286274 RPST = 0x0
2277 13:58:37.286354 RD_PRE = 0x0
2278 13:58:37.289741 WR_PRE = 0x1
2279 13:58:37.289821 WR_PST = 0x0
2280 13:58:37.293388 DBI_WR = 0x0
2281 13:58:37.293468 DBI_RD = 0x0
2282 13:58:37.296889 OTF = 0x1
2283 13:58:37.299835 ===================================
2284 13:58:37.303628 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2285 13:58:37.306964 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2286 13:58:37.313620 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 13:58:37.317004 ===================================
2288 13:58:37.317085 LPDDR4 DRAM CONFIGURATION
2289 13:58:37.320626 ===================================
2290 13:58:37.323407 EX_ROW_EN[0] = 0x10
2291 13:58:37.323487 EX_ROW_EN[1] = 0x0
2292 13:58:37.327142 LP4Y_EN = 0x0
2293 13:58:37.327222 WORK_FSP = 0x0
2294 13:58:37.330294 WL = 0x4
2295 13:58:37.330373 RL = 0x4
2296 13:58:37.333656 BL = 0x2
2297 13:58:37.333735 RPST = 0x0
2298 13:58:37.337090 RD_PRE = 0x0
2299 13:58:37.337169 WR_PRE = 0x1
2300 13:58:37.340342 WR_PST = 0x0
2301 13:58:37.340421 DBI_WR = 0x0
2302 13:58:37.343978 DBI_RD = 0x0
2303 13:58:37.347009 OTF = 0x1
2304 13:58:37.347088 ===================================
2305 13:58:37.354206 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2306 13:58:37.354285 ==
2307 13:58:37.357497 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 13:58:37.363902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2309 13:58:37.363983 ==
2310 13:58:37.364046 [Duty_Offset_Calibration]
2311 13:58:37.367372 B0:2 B1:-1 CA:1
2312 13:58:37.367451
2313 13:58:37.370494 [DutyScan_Calibration_Flow] k_type=0
2314 13:58:37.379122
2315 13:58:37.379202 ==CLK 0==
2316 13:58:37.382179 Final CLK duty delay cell = -4
2317 13:58:37.385372 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2318 13:58:37.388965 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2319 13:58:37.392135 [-4] AVG Duty = 4953%(X100)
2320 13:58:37.392215
2321 13:58:37.395629 CH0 CLK Duty spec in!! Max-Min= 156%
2322 13:58:37.399340 [DutyScan_Calibration_Flow] ====Done====
2323 13:58:37.399436
2324 13:58:37.402226 [DutyScan_Calibration_Flow] k_type=1
2325 13:58:37.416846
2326 13:58:37.416924 ==DQS 0 ==
2327 13:58:37.420347 Final DQS duty delay cell = -4
2328 13:58:37.423885 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2329 13:58:37.426807 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2330 13:58:37.430492 [-4] AVG Duty = 4938%(X100)
2331 13:58:37.430571
2332 13:58:37.430633 ==DQS 1 ==
2333 13:58:37.433569 Final DQS duty delay cell = -4
2334 13:58:37.436856 [-4] MAX Duty = 5124%(X100), DQS PI = 18
2335 13:58:37.440008 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2336 13:58:37.443670 [-4] AVG Duty = 5062%(X100)
2337 13:58:37.443750
2338 13:58:37.447287 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2339 13:58:37.447367
2340 13:58:37.450368 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2341 13:58:37.453494 [DutyScan_Calibration_Flow] ====Done====
2342 13:58:37.453574
2343 13:58:37.456867 [DutyScan_Calibration_Flow] k_type=3
2344 13:58:37.474157
2345 13:58:37.474238 ==DQM 0 ==
2346 13:58:37.477381 Final DQM duty delay cell = 0
2347 13:58:37.480882 [0] MAX Duty = 5000%(X100), DQS PI = 46
2348 13:58:37.484001 [0] MIN Duty = 4907%(X100), DQS PI = 2
2349 13:58:37.484082 [0] AVG Duty = 4953%(X100)
2350 13:58:37.484145
2351 13:58:37.487803 ==DQM 1 ==
2352 13:58:37.490958 Final DQM duty delay cell = 0
2353 13:58:37.494322 [0] MAX Duty = 5124%(X100), DQS PI = 32
2354 13:58:37.497943 [0] MIN Duty = 4969%(X100), DQS PI = 10
2355 13:58:37.498023 [0] AVG Duty = 5046%(X100)
2356 13:58:37.498088
2357 13:58:37.500975 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2358 13:58:37.501056
2359 13:58:37.507739 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2360 13:58:37.511944 [DutyScan_Calibration_Flow] ====Done====
2361 13:58:37.512051
2362 13:58:37.514543 [DutyScan_Calibration_Flow] k_type=2
2363 13:58:37.529847
2364 13:58:37.529928 ==DQ 0 ==
2365 13:58:37.533186 Final DQ duty delay cell = -4
2366 13:58:37.536273 [-4] MAX Duty = 5062%(X100), DQS PI = 56
2367 13:58:37.540026 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2368 13:58:37.543036 [-4] AVG Duty = 4969%(X100)
2369 13:58:37.543117
2370 13:58:37.543181 ==DQ 1 ==
2371 13:58:37.546131 Final DQ duty delay cell = 0
2372 13:58:37.550132 [0] MAX Duty = 5031%(X100), DQS PI = 26
2373 13:58:37.553091 [0] MIN Duty = 4938%(X100), DQS PI = 6
2374 13:58:37.553172 [0] AVG Duty = 4984%(X100)
2375 13:58:37.553235
2376 13:58:37.556405 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2377 13:58:37.559925
2378 13:58:37.560005 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2379 13:58:37.566601 [DutyScan_Calibration_Flow] ====Done====
2380 13:58:37.566736 ==
2381 13:58:37.569959 Dram Type= 6, Freq= 0, CH_1, rank 0
2382 13:58:37.573212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2383 13:58:37.573321 ==
2384 13:58:37.576504 [Duty_Offset_Calibration]
2385 13:58:37.576586 B0:1 B1:1 CA:2
2386 13:58:37.576651
2387 13:58:37.580098 [DutyScan_Calibration_Flow] k_type=0
2388 13:58:37.589834
2389 13:58:37.589914 ==CLK 0==
2390 13:58:37.592929 Final CLK duty delay cell = 0
2391 13:58:37.596576 [0] MAX Duty = 5125%(X100), DQS PI = 24
2392 13:58:37.600443 [0] MIN Duty = 4969%(X100), DQS PI = 40
2393 13:58:37.600524 [0] AVG Duty = 5047%(X100)
2394 13:58:37.603744
2395 13:58:37.603823 CH1 CLK Duty spec in!! Max-Min= 156%
2396 13:58:37.609736 [DutyScan_Calibration_Flow] ====Done====
2397 13:58:37.609817
2398 13:58:37.613096 [DutyScan_Calibration_Flow] k_type=1
2399 13:58:37.629058
2400 13:58:37.629137 ==DQS 0 ==
2401 13:58:37.633026 Final DQS duty delay cell = 0
2402 13:58:37.635890 [0] MAX Duty = 5031%(X100), DQS PI = 18
2403 13:58:37.639355 [0] MIN Duty = 4844%(X100), DQS PI = 48
2404 13:58:37.639436 [0] AVG Duty = 4937%(X100)
2405 13:58:37.642509
2406 13:58:37.642589 ==DQS 1 ==
2407 13:58:37.646052 Final DQS duty delay cell = 0
2408 13:58:37.649185 [0] MAX Duty = 5062%(X100), DQS PI = 36
2409 13:58:37.652787 [0] MIN Duty = 4907%(X100), DQS PI = 0
2410 13:58:37.652867 [0] AVG Duty = 4984%(X100)
2411 13:58:37.652931
2412 13:58:37.659562 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2413 13:58:37.659643
2414 13:58:37.662832 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2415 13:58:37.666059 [DutyScan_Calibration_Flow] ====Done====
2416 13:58:37.666187
2417 13:58:37.669351 [DutyScan_Calibration_Flow] k_type=3
2418 13:58:37.685912
2419 13:58:37.685993 ==DQM 0 ==
2420 13:58:37.689470 Final DQM duty delay cell = 0
2421 13:58:37.692591 [0] MAX Duty = 5093%(X100), DQS PI = 18
2422 13:58:37.695894 [0] MIN Duty = 4907%(X100), DQS PI = 48
2423 13:58:37.695976 [0] AVG Duty = 5000%(X100)
2424 13:58:37.698965
2425 13:58:37.699046 ==DQM 1 ==
2426 13:58:37.702410 Final DQM duty delay cell = 0
2427 13:58:37.705538 [0] MAX Duty = 5156%(X100), DQS PI = 62
2428 13:58:37.709157 [0] MIN Duty = 4938%(X100), DQS PI = 24
2429 13:58:37.709240 [0] AVG Duty = 5047%(X100)
2430 13:58:37.712645
2431 13:58:37.716103 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2432 13:58:37.716185
2433 13:58:37.719147 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2434 13:58:37.722487 [DutyScan_Calibration_Flow] ====Done====
2435 13:58:37.722569
2436 13:58:37.725600 [DutyScan_Calibration_Flow] k_type=2
2437 13:58:37.742339
2438 13:58:37.742420 ==DQ 0 ==
2439 13:58:37.745815 Final DQ duty delay cell = 0
2440 13:58:37.749400 [0] MAX Duty = 5125%(X100), DQS PI = 18
2441 13:58:37.752764 [0] MIN Duty = 4969%(X100), DQS PI = 14
2442 13:58:37.752846 [0] AVG Duty = 5047%(X100)
2443 13:58:37.752911
2444 13:58:37.755760 ==DQ 1 ==
2445 13:58:37.759230 Final DQ duty delay cell = 0
2446 13:58:37.762415 [0] MAX Duty = 5093%(X100), DQS PI = 10
2447 13:58:37.765612 [0] MIN Duty = 5000%(X100), DQS PI = 4
2448 13:58:37.765695 [0] AVG Duty = 5046%(X100)
2449 13:58:37.765760
2450 13:58:37.769204 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2451 13:58:37.769286
2452 13:58:37.772637 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2453 13:58:37.775873 [DutyScan_Calibration_Flow] ====Done====
2454 13:58:37.780961 nWR fixed to 30
2455 13:58:37.784726 [ModeRegInit_LP4] CH0 RK0
2456 13:58:37.784808 [ModeRegInit_LP4] CH0 RK1
2457 13:58:37.787662 [ModeRegInit_LP4] CH1 RK0
2458 13:58:37.791076 [ModeRegInit_LP4] CH1 RK1
2459 13:58:37.791158 match AC timing 7
2460 13:58:37.797621 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2461 13:58:37.801213 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2462 13:58:37.804519 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2463 13:58:37.811256 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2464 13:58:37.814588 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2465 13:58:37.814670 ==
2466 13:58:37.818206 Dram Type= 6, Freq= 0, CH_0, rank 0
2467 13:58:37.821788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 13:58:37.821871 ==
2469 13:58:37.828809 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 13:58:37.834621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 13:58:37.842471 [CA 0] Center 40 (10~71) winsize 62
2472 13:58:37.845606 [CA 1] Center 39 (9~70) winsize 62
2473 13:58:37.849114 [CA 2] Center 36 (6~67) winsize 62
2474 13:58:37.852155 [CA 3] Center 36 (5~67) winsize 63
2475 13:58:37.855687 [CA 4] Center 34 (4~65) winsize 62
2476 13:58:37.858617 [CA 5] Center 34 (4~64) winsize 61
2477 13:58:37.858731
2478 13:58:37.862226 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2479 13:58:37.862308
2480 13:58:37.865509 [CATrainingPosCal] consider 1 rank data
2481 13:58:37.868752 u2DelayCellTimex100 = 270/100 ps
2482 13:58:37.872161 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2483 13:58:37.875732 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2484 13:58:37.882335 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2485 13:58:37.885998 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2486 13:58:37.889261 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2487 13:58:37.892365 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2488 13:58:37.892446
2489 13:58:37.895488 CA PerBit enable=1, Macro0, CA PI delay=34
2490 13:58:37.895570
2491 13:58:37.898982 [CBTSetCACLKResult] CA Dly = 34
2492 13:58:37.899064 CS Dly: 7 (0~38)
2493 13:58:37.899129 ==
2494 13:58:37.902354 Dram Type= 6, Freq= 0, CH_0, rank 1
2495 13:58:37.909217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 13:58:37.909308 ==
2497 13:58:37.912631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 13:58:37.918996 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2499 13:58:37.928001 [CA 0] Center 39 (9~70) winsize 62
2500 13:58:37.931410 [CA 1] Center 39 (9~70) winsize 62
2501 13:58:37.934818 [CA 2] Center 36 (6~67) winsize 62
2502 13:58:37.938420 [CA 3] Center 36 (5~67) winsize 63
2503 13:58:37.941451 [CA 4] Center 34 (4~65) winsize 62
2504 13:58:37.944851 [CA 5] Center 34 (4~64) winsize 61
2505 13:58:37.944932
2506 13:58:37.948500 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2507 13:58:37.948580
2508 13:58:37.951391 [CATrainingPosCal] consider 2 rank data
2509 13:58:37.955091 u2DelayCellTimex100 = 270/100 ps
2510 13:58:37.958577 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2511 13:58:37.961767 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2512 13:58:37.965043 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2513 13:58:37.971639 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2514 13:58:37.975142 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2515 13:58:37.978336 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2516 13:58:37.978416
2517 13:58:37.981946 CA PerBit enable=1, Macro0, CA PI delay=34
2518 13:58:37.982027
2519 13:58:37.985041 [CBTSetCACLKResult] CA Dly = 34
2520 13:58:37.985139 CS Dly: 8 (0~41)
2521 13:58:37.985217
2522 13:58:37.988396 ----->DramcWriteLeveling(PI) begin...
2523 13:58:37.988478 ==
2524 13:58:37.991634 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 13:58:37.998217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 13:58:37.998300 ==
2527 13:58:38.001671 Write leveling (Byte 0): 31 => 31
2528 13:58:38.004878 Write leveling (Byte 1): 29 => 29
2529 13:58:38.004959 DramcWriteLeveling(PI) end<-----
2530 13:58:38.005022
2531 13:58:38.008565 ==
2532 13:58:38.012250 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 13:58:38.014983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 13:58:38.015063 ==
2535 13:58:38.018316 [Gating] SW mode calibration
2536 13:58:38.025128 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2537 13:58:38.028570 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2538 13:58:38.035159 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 13:58:38.038861 0 15 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
2540 13:58:38.042151 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 13:58:38.048643 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 13:58:38.052353 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 13:58:38.055748 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 13:58:38.058629 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 13:58:38.065357 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 13:58:38.069093 1 0 0 | B1->B0 | 3434 3333 | 0 0 | (1 0) (0 1)
2547 13:58:38.072276 1 0 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2548 13:58:38.079326 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 13:58:38.082608 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 13:58:38.086114 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 13:58:38.092750 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 13:58:38.096231 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 13:58:38.099666 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 13:58:38.103059 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2555 13:58:38.109779 1 1 4 | B1->B0 | 3b3b 4545 | 1 0 | (1 1) (0 0)
2556 13:58:38.112783 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 13:58:38.116180 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 13:58:38.122925 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 13:58:38.126594 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 13:58:38.129529 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 13:58:38.136328 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 13:58:38.140080 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2563 13:58:38.142872 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 13:58:38.149673 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 13:58:38.153053 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 13:58:38.156197 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 13:58:38.162981 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 13:58:38.166266 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 13:58:38.170026 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 13:58:38.173452 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 13:58:38.179954 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 13:58:38.183324 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 13:58:38.186507 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 13:58:38.193510 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 13:58:38.196522 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 13:58:38.200092 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 13:58:38.206662 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 13:58:38.210159 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2579 13:58:38.213824 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 13:58:38.216648 Total UI for P1: 0, mck2ui 16
2581 13:58:38.220177 best dqsien dly found for B0: ( 1, 4, 0)
2582 13:58:38.223460 Total UI for P1: 0, mck2ui 16
2583 13:58:38.227068 best dqsien dly found for B1: ( 1, 4, 0)
2584 13:58:38.230835 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2585 13:58:38.233532 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2586 13:58:38.233613
2587 13:58:38.237287 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2588 13:58:38.240558 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2589 13:58:38.244104 [Gating] SW calibration Done
2590 13:58:38.244184 ==
2591 13:58:38.246911 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 13:58:38.250441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 13:58:38.253776 ==
2594 13:58:38.253857 RX Vref Scan: 0
2595 13:58:38.253921
2596 13:58:38.256879 RX Vref 0 -> 0, step: 1
2597 13:58:38.256960
2598 13:58:38.257023 RX Delay -40 -> 252, step: 8
2599 13:58:38.263810 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2600 13:58:38.267511 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2601 13:58:38.270837 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2602 13:58:38.274304 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2603 13:58:38.277538 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2604 13:58:38.284164 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2605 13:58:38.287516 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2606 13:58:38.290787 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2607 13:58:38.294317 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2608 13:58:38.297450 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2609 13:58:38.300919 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2610 13:58:38.307610 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2611 13:58:38.310945 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2612 13:58:38.314262 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2613 13:58:38.318104 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2614 13:58:38.321040 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2615 13:58:38.324619 ==
2616 13:58:38.324700 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 13:58:38.331393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 13:58:38.331473 ==
2619 13:58:38.331537 DQS Delay:
2620 13:58:38.334633 DQS0 = 0, DQS1 = 0
2621 13:58:38.334759 DQM Delay:
2622 13:58:38.338183 DQM0 = 115, DQM1 = 107
2623 13:58:38.338263 DQ Delay:
2624 13:58:38.341429 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2625 13:58:38.345228 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2626 13:58:38.348366 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2627 13:58:38.351599 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2628 13:58:38.351679
2629 13:58:38.351743
2630 13:58:38.351801 ==
2631 13:58:38.354687 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 13:58:38.358027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 13:58:38.358108 ==
2634 13:58:38.361635
2635 13:58:38.361715
2636 13:58:38.361778 TX Vref Scan disable
2637 13:58:38.364722 == TX Byte 0 ==
2638 13:58:38.368326 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2639 13:58:38.371819 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2640 13:58:38.375050 == TX Byte 1 ==
2641 13:58:38.378277 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2642 13:58:38.381637 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2643 13:58:38.381718 ==
2644 13:58:38.384712 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 13:58:38.391500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 13:58:38.391582 ==
2647 13:58:38.402249 TX Vref=22, minBit 1, minWin=24, winSum=418
2648 13:58:38.405339 TX Vref=24, minBit 1, minWin=25, winSum=421
2649 13:58:38.409015 TX Vref=26, minBit 0, minWin=26, winSum=428
2650 13:58:38.412683 TX Vref=28, minBit 1, minWin=25, winSum=430
2651 13:58:38.415870 TX Vref=30, minBit 0, minWin=26, winSum=429
2652 13:58:38.419322 TX Vref=32, minBit 0, minWin=26, winSum=430
2653 13:58:38.426035 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 32
2654 13:58:38.426118
2655 13:58:38.429581 Final TX Range 1 Vref 32
2656 13:58:38.429663
2657 13:58:38.429727 ==
2658 13:58:38.432665 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 13:58:38.435643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 13:58:38.435724 ==
2661 13:58:38.435789
2662 13:58:38.435849
2663 13:58:38.439082 TX Vref Scan disable
2664 13:58:38.443031 == TX Byte 0 ==
2665 13:58:38.446402 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2666 13:58:38.449182 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2667 13:58:38.452682 == TX Byte 1 ==
2668 13:58:38.456025 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2669 13:58:38.459254 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2670 13:58:38.459351
2671 13:58:38.463118 [DATLAT]
2672 13:58:38.463199 Freq=1200, CH0 RK0
2673 13:58:38.463264
2674 13:58:38.466586 DATLAT Default: 0xd
2675 13:58:38.466669 0, 0xFFFF, sum = 0
2676 13:58:38.469473 1, 0xFFFF, sum = 0
2677 13:58:38.469557 2, 0xFFFF, sum = 0
2678 13:58:38.472729 3, 0xFFFF, sum = 0
2679 13:58:38.472836 4, 0xFFFF, sum = 0
2680 13:58:38.476349 5, 0xFFFF, sum = 0
2681 13:58:38.476462 6, 0xFFFF, sum = 0
2682 13:58:38.479419 7, 0xFFFF, sum = 0
2683 13:58:38.479516 8, 0xFFFF, sum = 0
2684 13:58:38.482879 9, 0xFFFF, sum = 0
2685 13:58:38.482978 10, 0xFFFF, sum = 0
2686 13:58:38.486164 11, 0xFFFF, sum = 0
2687 13:58:38.486301 12, 0x0, sum = 1
2688 13:58:38.489601 13, 0x0, sum = 2
2689 13:58:38.489704 14, 0x0, sum = 3
2690 13:58:38.493056 15, 0x0, sum = 4
2691 13:58:38.493154 best_step = 13
2692 13:58:38.493219
2693 13:58:38.493279 ==
2694 13:58:38.496115 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 13:58:38.499788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 13:58:38.503620 ==
2697 13:58:38.503731 RX Vref Scan: 1
2698 13:58:38.503802
2699 13:58:38.506509 Set Vref Range= 32 -> 127
2700 13:58:38.506591
2701 13:58:38.509681 RX Vref 32 -> 127, step: 1
2702 13:58:38.509763
2703 13:58:38.509828 RX Delay -21 -> 252, step: 4
2704 13:58:38.509919
2705 13:58:38.513206 Set Vref, RX VrefLevel [Byte0]: 32
2706 13:58:38.516591 [Byte1]: 32
2707 13:58:38.520639
2708 13:58:38.520731 Set Vref, RX VrefLevel [Byte0]: 33
2709 13:58:38.524220 [Byte1]: 33
2710 13:58:38.528362
2711 13:58:38.528528 Set Vref, RX VrefLevel [Byte0]: 34
2712 13:58:38.531845 [Byte1]: 34
2713 13:58:38.536564
2714 13:58:38.536648 Set Vref, RX VrefLevel [Byte0]: 35
2715 13:58:38.539572 [Byte1]: 35
2716 13:58:38.544174
2717 13:58:38.544259 Set Vref, RX VrefLevel [Byte0]: 36
2718 13:58:38.547509 [Byte1]: 36
2719 13:58:38.552186
2720 13:58:38.552269 Set Vref, RX VrefLevel [Byte0]: 37
2721 13:58:38.555799 [Byte1]: 37
2722 13:58:38.559970
2723 13:58:38.560054 Set Vref, RX VrefLevel [Byte0]: 38
2724 13:58:38.563333 [Byte1]: 38
2725 13:58:38.567878
2726 13:58:38.567961 Set Vref, RX VrefLevel [Byte0]: 39
2727 13:58:38.571568 [Byte1]: 39
2728 13:58:38.575840
2729 13:58:38.575923 Set Vref, RX VrefLevel [Byte0]: 40
2730 13:58:38.579786 [Byte1]: 40
2731 13:58:38.583646
2732 13:58:38.583730 Set Vref, RX VrefLevel [Byte0]: 41
2733 13:58:38.587015 [Byte1]: 41
2734 13:58:38.591923
2735 13:58:38.592006 Set Vref, RX VrefLevel [Byte0]: 42
2736 13:58:38.595311 [Byte1]: 42
2737 13:58:38.600100
2738 13:58:38.600184 Set Vref, RX VrefLevel [Byte0]: 43
2739 13:58:38.603911 [Byte1]: 43
2740 13:58:38.607867
2741 13:58:38.607950 Set Vref, RX VrefLevel [Byte0]: 44
2742 13:58:38.611145 [Byte1]: 44
2743 13:58:38.615538
2744 13:58:38.615622 Set Vref, RX VrefLevel [Byte0]: 45
2745 13:58:38.618756 [Byte1]: 45
2746 13:58:38.623618
2747 13:58:38.623700 Set Vref, RX VrefLevel [Byte0]: 46
2748 13:58:38.626635 [Byte1]: 46
2749 13:58:38.631401
2750 13:58:38.631484 Set Vref, RX VrefLevel [Byte0]: 47
2751 13:58:38.634663 [Byte1]: 47
2752 13:58:38.639050
2753 13:58:38.639131 Set Vref, RX VrefLevel [Byte0]: 48
2754 13:58:38.642437 [Byte1]: 48
2755 13:58:38.647661
2756 13:58:38.647743 Set Vref, RX VrefLevel [Byte0]: 49
2757 13:58:38.650653 [Byte1]: 49
2758 13:58:38.655258
2759 13:58:38.655340 Set Vref, RX VrefLevel [Byte0]: 50
2760 13:58:38.658652 [Byte1]: 50
2761 13:58:38.663246
2762 13:58:38.663327 Set Vref, RX VrefLevel [Byte0]: 51
2763 13:58:38.669256 [Byte1]: 51
2764 13:58:38.669338
2765 13:58:38.673218 Set Vref, RX VrefLevel [Byte0]: 52
2766 13:58:38.676159 [Byte1]: 52
2767 13:58:38.676241
2768 13:58:38.679448 Set Vref, RX VrefLevel [Byte0]: 53
2769 13:58:38.682562 [Byte1]: 53
2770 13:58:38.686629
2771 13:58:38.686733 Set Vref, RX VrefLevel [Byte0]: 54
2772 13:58:38.690201 [Byte1]: 54
2773 13:58:38.694716
2774 13:58:38.694819 Set Vref, RX VrefLevel [Byte0]: 55
2775 13:58:38.698436 [Byte1]: 55
2776 13:58:38.702703
2777 13:58:38.702823 Set Vref, RX VrefLevel [Byte0]: 56
2778 13:58:38.705953 [Byte1]: 56
2779 13:58:38.710545
2780 13:58:38.710626 Set Vref, RX VrefLevel [Byte0]: 57
2781 13:58:38.714312 [Byte1]: 57
2782 13:58:38.718925
2783 13:58:38.719006 Set Vref, RX VrefLevel [Byte0]: 58
2784 13:58:38.722035 [Byte1]: 58
2785 13:58:38.726376
2786 13:58:38.726458 Set Vref, RX VrefLevel [Byte0]: 59
2787 13:58:38.729989 [Byte1]: 59
2788 13:58:38.734272
2789 13:58:38.734354 Set Vref, RX VrefLevel [Byte0]: 60
2790 13:58:38.737831 [Byte1]: 60
2791 13:58:38.742674
2792 13:58:38.742794 Set Vref, RX VrefLevel [Byte0]: 61
2793 13:58:38.745901 [Byte1]: 61
2794 13:58:38.750451
2795 13:58:38.750532 Set Vref, RX VrefLevel [Byte0]: 62
2796 13:58:38.753653 [Byte1]: 62
2797 13:58:38.758196
2798 13:58:38.758278 Set Vref, RX VrefLevel [Byte0]: 63
2799 13:58:38.761610 [Byte1]: 63
2800 13:58:38.766304
2801 13:58:38.766386 Set Vref, RX VrefLevel [Byte0]: 64
2802 13:58:38.769381 [Byte1]: 64
2803 13:58:38.773926
2804 13:58:38.774007 Set Vref, RX VrefLevel [Byte0]: 65
2805 13:58:38.777443 [Byte1]: 65
2806 13:58:38.781811
2807 13:58:38.781892 Set Vref, RX VrefLevel [Byte0]: 66
2808 13:58:38.785709 [Byte1]: 66
2809 13:58:38.789904
2810 13:58:38.789987 Set Vref, RX VrefLevel [Byte0]: 67
2811 13:58:38.793186 [Byte1]: 67
2812 13:58:38.798143
2813 13:58:38.798224 Set Vref, RX VrefLevel [Byte0]: 68
2814 13:58:38.801012 [Byte1]: 68
2815 13:58:38.805767
2816 13:58:38.805848 Final RX Vref Byte 0 = 53 to rank0
2817 13:58:38.809004 Final RX Vref Byte 1 = 51 to rank0
2818 13:58:38.812742 Final RX Vref Byte 0 = 53 to rank1
2819 13:58:38.816043 Final RX Vref Byte 1 = 51 to rank1==
2820 13:58:38.819096 Dram Type= 6, Freq= 0, CH_0, rank 0
2821 13:58:38.822655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 13:58:38.825750 ==
2823 13:58:38.825831 DQS Delay:
2824 13:58:38.825895 DQS0 = 0, DQS1 = 0
2825 13:58:38.829355 DQM Delay:
2826 13:58:38.829436 DQM0 = 115, DQM1 = 104
2827 13:58:38.832752 DQ Delay:
2828 13:58:38.836034 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2829 13:58:38.839667 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2830 13:58:38.842904 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2831 13:58:38.846502 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2832 13:58:38.846583
2833 13:58:38.846648
2834 13:58:38.853137 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2835 13:58:38.856086 CH0 RK0: MR19=303, MR18=FEED
2836 13:58:38.863388 CH0_RK0: MR19=0x303, MR18=0xFEED, DQSOSC=410, MR23=63, INC=39, DEC=26
2837 13:58:38.863470
2838 13:58:38.865944 ----->DramcWriteLeveling(PI) begin...
2839 13:58:38.866029 ==
2840 13:58:38.869422 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 13:58:38.872795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 13:58:38.872877 ==
2843 13:58:38.876026 Write leveling (Byte 0): 32 => 32
2844 13:58:38.879714 Write leveling (Byte 1): 26 => 26
2845 13:58:38.882891 DramcWriteLeveling(PI) end<-----
2846 13:58:38.882980
2847 13:58:38.883048 ==
2848 13:58:38.886437 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 13:58:38.889544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 13:58:38.889626 ==
2851 13:58:38.893019 [Gating] SW mode calibration
2852 13:58:38.899921 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2853 13:58:38.906293 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2854 13:58:38.910416 0 15 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2855 13:58:38.916494 0 15 4 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
2856 13:58:38.919771 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 13:58:38.923161 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 13:58:38.926594 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 13:58:38.933242 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 13:58:38.936660 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 13:58:38.939783 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
2862 13:58:38.946934 1 0 0 | B1->B0 | 2d2d 2424 | 0 0 | (0 1) (0 0)
2863 13:58:38.950081 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 13:58:38.953515 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 13:58:38.960229 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 13:58:38.963646 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 13:58:38.966849 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 13:58:38.973538 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2869 13:58:38.976968 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2870 13:58:38.980605 1 1 0 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
2871 13:58:38.983576 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2872 13:58:38.990252 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 13:58:38.993729 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 13:58:38.997152 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 13:58:39.004344 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 13:58:39.007463 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 13:58:39.011383 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2878 13:58:39.017435 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2879 13:58:39.020585 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 13:58:39.024478 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 13:58:39.027618 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 13:58:39.034455 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 13:58:39.037982 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 13:58:39.041130 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 13:58:39.047592 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 13:58:39.051306 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 13:58:39.054217 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 13:58:39.061167 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 13:58:39.064641 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 13:58:39.067687 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 13:58:39.075035 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 13:58:39.077827 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2893 13:58:39.081354 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2894 13:58:39.088034 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2895 13:58:39.088117 Total UI for P1: 0, mck2ui 16
2896 13:58:39.091444 best dqsien dly found for B0: ( 1, 3, 26)
2897 13:58:39.098281 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 13:58:39.101345 Total UI for P1: 0, mck2ui 16
2899 13:58:39.104981 best dqsien dly found for B1: ( 1, 4, 0)
2900 13:58:39.108050 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2901 13:58:39.111395 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2902 13:58:39.111511
2903 13:58:39.114589 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2904 13:58:39.118118 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2905 13:58:39.121389 [Gating] SW calibration Done
2906 13:58:39.121471 ==
2907 13:58:39.125126 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 13:58:39.128187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 13:58:39.128269 ==
2910 13:58:39.131950 RX Vref Scan: 0
2911 13:58:39.132032
2912 13:58:39.132096 RX Vref 0 -> 0, step: 1
2913 13:58:39.132156
2914 13:58:39.135061 RX Delay -40 -> 252, step: 8
2915 13:58:39.138292 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2916 13:58:39.141694 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2917 13:58:39.148294 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2918 13:58:39.151891 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2919 13:58:39.155043 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2920 13:58:39.158554 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2921 13:58:39.161876 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2922 13:58:39.168581 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2923 13:58:39.172163 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2924 13:58:39.175286 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2925 13:58:39.179079 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2926 13:58:39.182342 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2927 13:58:39.188616 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2928 13:58:39.191937 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2929 13:58:39.195410 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2930 13:58:39.198713 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2931 13:58:39.198816 ==
2932 13:58:39.202386 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 13:58:39.205566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 13:58:39.209363 ==
2935 13:58:39.209469 DQS Delay:
2936 13:58:39.209561 DQS0 = 0, DQS1 = 0
2937 13:58:39.212488 DQM Delay:
2938 13:58:39.212569 DQM0 = 115, DQM1 = 105
2939 13:58:39.215568 DQ Delay:
2940 13:58:39.218873 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2941 13:58:39.222566 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2942 13:58:39.225801 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2943 13:58:39.229250 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2944 13:58:39.229331
2945 13:58:39.229395
2946 13:58:39.229454 ==
2947 13:58:39.232565 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 13:58:39.236001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 13:58:39.236084 ==
2950 13:58:39.236148
2951 13:58:39.236208
2952 13:58:39.239548 TX Vref Scan disable
2953 13:58:39.239630 == TX Byte 0 ==
2954 13:58:39.246260 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2955 13:58:39.249146 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2956 13:58:39.249227 == TX Byte 1 ==
2957 13:58:39.256291 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2958 13:58:39.259336 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2959 13:58:39.259417 ==
2960 13:58:39.263185 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 13:58:39.265797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 13:58:39.265878 ==
2963 13:58:39.279463 TX Vref=22, minBit 7, minWin=25, winSum=424
2964 13:58:39.282642 TX Vref=24, minBit 5, minWin=25, winSum=431
2965 13:58:39.286052 TX Vref=26, minBit 3, minWin=26, winSum=435
2966 13:58:39.289461 TX Vref=28, minBit 3, minWin=26, winSum=436
2967 13:58:39.292662 TX Vref=30, minBit 0, minWin=27, winSum=439
2968 13:58:39.299221 TX Vref=32, minBit 0, minWin=27, winSum=439
2969 13:58:39.302616 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 30
2970 13:58:39.302742
2971 13:58:39.306334 Final TX Range 1 Vref 30
2972 13:58:39.306414
2973 13:58:39.306477 ==
2974 13:58:39.309470 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 13:58:39.312749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 13:58:39.312829 ==
2977 13:58:39.312893
2978 13:58:39.312952
2979 13:58:39.315967 TX Vref Scan disable
2980 13:58:39.319448 == TX Byte 0 ==
2981 13:58:39.322770 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2982 13:58:39.326419 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2983 13:58:39.329758 == TX Byte 1 ==
2984 13:58:39.333051 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2985 13:58:39.336324 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2986 13:58:39.336405
2987 13:58:39.339367 [DATLAT]
2988 13:58:39.339447 Freq=1200, CH0 RK1
2989 13:58:39.339542
2990 13:58:39.342914 DATLAT Default: 0xd
2991 13:58:39.342994 0, 0xFFFF, sum = 0
2992 13:58:39.346376 1, 0xFFFF, sum = 0
2993 13:58:39.346457 2, 0xFFFF, sum = 0
2994 13:58:39.349484 3, 0xFFFF, sum = 0
2995 13:58:39.349566 4, 0xFFFF, sum = 0
2996 13:58:39.353113 5, 0xFFFF, sum = 0
2997 13:58:39.353195 6, 0xFFFF, sum = 0
2998 13:58:39.356388 7, 0xFFFF, sum = 0
2999 13:58:39.356470 8, 0xFFFF, sum = 0
3000 13:58:39.359587 9, 0xFFFF, sum = 0
3001 13:58:39.359669 10, 0xFFFF, sum = 0
3002 13:58:39.362849 11, 0xFFFF, sum = 0
3003 13:58:39.362931 12, 0x0, sum = 1
3004 13:58:39.366402 13, 0x0, sum = 2
3005 13:58:39.366498 14, 0x0, sum = 3
3006 13:58:39.369518 15, 0x0, sum = 4
3007 13:58:39.369600 best_step = 13
3008 13:58:39.369663
3009 13:58:39.369721 ==
3010 13:58:39.373410 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 13:58:39.379712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 13:58:39.379795 ==
3013 13:58:39.379859 RX Vref Scan: 0
3014 13:58:39.379944
3015 13:58:39.383018 RX Vref 0 -> 0, step: 1
3016 13:58:39.383124
3017 13:58:39.386622 RX Delay -21 -> 252, step: 4
3018 13:58:39.389664 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3019 13:58:39.392903 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3020 13:58:39.399884 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3021 13:58:39.403397 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3022 13:58:39.406581 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3023 13:58:39.410139 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3024 13:58:39.413576 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3025 13:58:39.416548 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3026 13:58:39.423139 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3027 13:58:39.426834 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3028 13:58:39.429869 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3029 13:58:39.433517 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3030 13:58:39.436924 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3031 13:58:39.443392 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3032 13:58:39.447113 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3033 13:58:39.450453 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3034 13:58:39.450535 ==
3035 13:58:39.453776 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 13:58:39.456843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 13:58:39.456925 ==
3038 13:58:39.460264 DQS Delay:
3039 13:58:39.460346 DQS0 = 0, DQS1 = 0
3040 13:58:39.460411 DQM Delay:
3041 13:58:39.463649 DQM0 = 114, DQM1 = 105
3042 13:58:39.463730 DQ Delay:
3043 13:58:39.467016 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3044 13:58:39.470332 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =122
3045 13:58:39.473868 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =94
3046 13:58:39.480174 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3047 13:58:39.480255
3048 13:58:39.480320
3049 13:58:39.486869 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3050 13:58:39.490576 CH0 RK1: MR19=403, MR18=3F4
3051 13:58:39.497166 CH0_RK1: MR19=0x403, MR18=0x3F4, DQSOSC=408, MR23=63, INC=39, DEC=26
3052 13:58:39.500641 [RxdqsGatingPostProcess] freq 1200
3053 13:58:39.503737 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3054 13:58:39.507260 best DQS0 dly(2T, 0.5T) = (0, 12)
3055 13:58:39.510583 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 13:58:39.513881 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3057 13:58:39.517194 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 13:58:39.520707 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 13:58:39.523978 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 13:58:39.527320 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 13:58:39.530733 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 13:58:39.530817 Pre-setting of DQS Precalculation
3063 13:58:39.537471 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3064 13:58:39.537585 ==
3065 13:58:39.540805 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 13:58:39.544231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 13:58:39.544314 ==
3068 13:58:39.550955 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3069 13:58:39.557594 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3070 13:58:39.565149 [CA 0] Center 38 (8~68) winsize 61
3071 13:58:39.568271 [CA 1] Center 38 (8~68) winsize 61
3072 13:58:39.571650 [CA 2] Center 35 (5~65) winsize 61
3073 13:58:39.575295 [CA 3] Center 34 (4~65) winsize 62
3074 13:58:39.578242 [CA 4] Center 34 (4~65) winsize 62
3075 13:58:39.581879 [CA 5] Center 34 (4~64) winsize 61
3076 13:58:39.581960
3077 13:58:39.585253 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3078 13:58:39.585335
3079 13:58:39.588642 [CATrainingPosCal] consider 1 rank data
3080 13:58:39.592079 u2DelayCellTimex100 = 270/100 ps
3081 13:58:39.595269 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3082 13:58:39.598464 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3083 13:58:39.601864 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3084 13:58:39.608805 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3085 13:58:39.612121 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3086 13:58:39.615577 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3087 13:58:39.615652
3088 13:58:39.618838 CA PerBit enable=1, Macro0, CA PI delay=34
3089 13:58:39.618920
3090 13:58:39.622463 [CBTSetCACLKResult] CA Dly = 34
3091 13:58:39.622545 CS Dly: 6 (0~37)
3092 13:58:39.622609 ==
3093 13:58:39.625447 Dram Type= 6, Freq= 0, CH_1, rank 1
3094 13:58:39.632089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 13:58:39.632171 ==
3096 13:58:39.635774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 13:58:39.641977 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3098 13:58:39.650480 [CA 0] Center 38 (8~68) winsize 61
3099 13:58:39.654048 [CA 1] Center 38 (8~68) winsize 61
3100 13:58:39.657201 [CA 2] Center 35 (5~65) winsize 61
3101 13:58:39.660581 [CA 3] Center 34 (4~65) winsize 62
3102 13:58:39.664047 [CA 4] Center 34 (4~65) winsize 62
3103 13:58:39.667399 [CA 5] Center 33 (3~63) winsize 61
3104 13:58:39.667481
3105 13:58:39.670957 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3106 13:58:39.671039
3107 13:58:39.674249 [CATrainingPosCal] consider 2 rank data
3108 13:58:39.677365 u2DelayCellTimex100 = 270/100 ps
3109 13:58:39.680825 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3110 13:58:39.684025 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3111 13:58:39.687666 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3112 13:58:39.691225 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3113 13:58:39.697874 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3114 13:58:39.701194 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3115 13:58:39.701276
3116 13:58:39.704476 CA PerBit enable=1, Macro0, CA PI delay=33
3117 13:58:39.704557
3118 13:58:39.707483 [CBTSetCACLKResult] CA Dly = 33
3119 13:58:39.707564 CS Dly: 8 (0~41)
3120 13:58:39.707630
3121 13:58:39.710676 ----->DramcWriteLeveling(PI) begin...
3122 13:58:39.710784 ==
3123 13:58:39.714488 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 13:58:39.721140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 13:58:39.721237 ==
3126 13:58:39.724335 Write leveling (Byte 0): 26 => 26
3127 13:58:39.724417 Write leveling (Byte 1): 29 => 29
3128 13:58:39.727680 DramcWriteLeveling(PI) end<-----
3129 13:58:39.727762
3130 13:58:39.727826 ==
3131 13:58:39.730992 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 13:58:39.737903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 13:58:39.737985 ==
3134 13:58:39.738051 [Gating] SW mode calibration
3135 13:58:39.747913 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3136 13:58:39.751736 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3137 13:58:39.754711 0 15 0 | B1->B0 | 2828 2323 | 1 0 | (1 1) (0 0)
3138 13:58:39.761899 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 13:58:39.764682 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 13:58:39.768473 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 13:58:39.774766 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 13:58:39.778147 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 13:58:39.781908 0 15 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
3144 13:58:39.788121 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3145 13:58:39.791805 1 0 0 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
3146 13:58:39.795143 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 13:58:39.802033 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 13:58:39.805643 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 13:58:39.808917 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 13:58:39.812156 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 13:58:39.818638 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 13:58:39.822165 1 0 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3153 13:58:39.825817 1 1 0 | B1->B0 | 4141 3232 | 0 0 | (0 0) (0 0)
3154 13:58:39.832379 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 13:58:39.835541 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 13:58:39.838657 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 13:58:39.845299 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 13:58:39.848959 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 13:58:39.852355 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 13:58:39.859040 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3161 13:58:39.862174 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3162 13:58:39.865378 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 13:58:39.868811 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 13:58:39.875709 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 13:58:39.879450 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 13:58:39.882402 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 13:58:39.889486 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 13:58:39.892359 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 13:58:39.895825 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 13:58:39.902726 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 13:58:39.906019 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 13:58:39.909351 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 13:58:39.915710 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 13:58:39.919119 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 13:58:39.923077 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 13:58:39.926041 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3177 13:58:39.933111 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 13:58:39.936462 Total UI for P1: 0, mck2ui 16
3179 13:58:39.939227 best dqsien dly found for B0: ( 1, 3, 28)
3180 13:58:39.942861 Total UI for P1: 0, mck2ui 16
3181 13:58:39.945854 best dqsien dly found for B1: ( 1, 3, 30)
3182 13:58:39.949372 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3183 13:58:39.952631 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3184 13:58:39.952746
3185 13:58:39.956258 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3186 13:58:39.959509 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3187 13:58:39.962652 [Gating] SW calibration Done
3188 13:58:39.962772 ==
3189 13:58:39.966483 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 13:58:39.969610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 13:58:39.969714 ==
3192 13:58:39.972779 RX Vref Scan: 0
3193 13:58:39.972880
3194 13:58:39.972976 RX Vref 0 -> 0, step: 1
3195 13:58:39.973071
3196 13:58:39.976320 RX Delay -40 -> 252, step: 8
3197 13:58:39.979375 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3198 13:58:39.986153 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3199 13:58:39.989477 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3200 13:58:39.992983 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3201 13:58:39.996605 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3202 13:58:39.999875 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3203 13:58:40.006236 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3204 13:58:40.010229 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3205 13:58:40.013484 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3206 13:58:40.016241 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3207 13:58:40.019720 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3208 13:58:40.023310 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3209 13:58:40.029894 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3210 13:58:40.033427 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3211 13:58:40.036933 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3212 13:58:40.040177 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3213 13:58:40.040259 ==
3214 13:58:40.043964 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 13:58:40.050469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 13:58:40.050552 ==
3217 13:58:40.050618 DQS Delay:
3218 13:58:40.050678 DQS0 = 0, DQS1 = 0
3219 13:58:40.053686 DQM Delay:
3220 13:58:40.053768 DQM0 = 115, DQM1 = 108
3221 13:58:40.057230 DQ Delay:
3222 13:58:40.060140 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3223 13:58:40.063937 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3224 13:58:40.066912 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3225 13:58:40.070229 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3226 13:58:40.070346
3227 13:58:40.070439
3228 13:58:40.070528 ==
3229 13:58:40.073735 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 13:58:40.077369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 13:58:40.077452 ==
3232 13:58:40.077517
3233 13:58:40.077577
3234 13:58:40.080765 TX Vref Scan disable
3235 13:58:40.084202 == TX Byte 0 ==
3236 13:58:40.087344 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3237 13:58:40.091133 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3238 13:58:40.093921 == TX Byte 1 ==
3239 13:58:40.097675 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3240 13:58:40.100826 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3241 13:58:40.100927 ==
3242 13:58:40.104156 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 13:58:40.107870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 13:58:40.107947 ==
3245 13:58:40.120663 TX Vref=22, minBit 1, minWin=25, winSum=414
3246 13:58:40.123979 TX Vref=24, minBit 1, minWin=25, winSum=416
3247 13:58:40.127831 TX Vref=26, minBit 0, minWin=26, winSum=425
3248 13:58:40.130599 TX Vref=28, minBit 0, minWin=26, winSum=427
3249 13:58:40.133827 TX Vref=30, minBit 1, minWin=26, winSum=430
3250 13:58:40.137342 TX Vref=32, minBit 1, minWin=25, winSum=429
3251 13:58:40.143888 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3252 13:58:40.143960
3253 13:58:40.147400 Final TX Range 1 Vref 30
3254 13:58:40.147502
3255 13:58:40.147568 ==
3256 13:58:40.150925 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 13:58:40.153998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 13:58:40.154094 ==
3259 13:58:40.154188
3260 13:58:40.154280
3261 13:58:40.158082 TX Vref Scan disable
3262 13:58:40.161364 == TX Byte 0 ==
3263 13:58:40.164310 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3264 13:58:40.167684 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3265 13:58:40.171653 == TX Byte 1 ==
3266 13:58:40.174779 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3267 13:58:40.178101 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3268 13:58:40.178185
3269 13:58:40.180854 [DATLAT]
3270 13:58:40.180936 Freq=1200, CH1 RK0
3271 13:58:40.181001
3272 13:58:40.184588 DATLAT Default: 0xd
3273 13:58:40.184670 0, 0xFFFF, sum = 0
3274 13:58:40.187807 1, 0xFFFF, sum = 0
3275 13:58:40.187891 2, 0xFFFF, sum = 0
3276 13:58:40.190928 3, 0xFFFF, sum = 0
3277 13:58:40.191012 4, 0xFFFF, sum = 0
3278 13:58:40.194595 5, 0xFFFF, sum = 0
3279 13:58:40.194707 6, 0xFFFF, sum = 0
3280 13:58:40.197959 7, 0xFFFF, sum = 0
3281 13:58:40.198047 8, 0xFFFF, sum = 0
3282 13:58:40.201023 9, 0xFFFF, sum = 0
3283 13:58:40.201107 10, 0xFFFF, sum = 0
3284 13:58:40.204396 11, 0xFFFF, sum = 0
3285 13:58:40.204479 12, 0x0, sum = 1
3286 13:58:40.207908 13, 0x0, sum = 2
3287 13:58:40.207992 14, 0x0, sum = 3
3288 13:58:40.211232 15, 0x0, sum = 4
3289 13:58:40.211315 best_step = 13
3290 13:58:40.211380
3291 13:58:40.211440 ==
3292 13:58:40.214778 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 13:58:40.218276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 13:58:40.221418 ==
3295 13:58:40.221501 RX Vref Scan: 1
3296 13:58:40.221565
3297 13:58:40.224631 Set Vref Range= 32 -> 127
3298 13:58:40.224712
3299 13:58:40.227906 RX Vref 32 -> 127, step: 1
3300 13:58:40.228013
3301 13:58:40.228109 RX Delay -21 -> 252, step: 4
3302 13:58:40.228195
3303 13:58:40.231358 Set Vref, RX VrefLevel [Byte0]: 32
3304 13:58:40.234939 [Byte1]: 32
3305 13:58:40.239112
3306 13:58:40.239192 Set Vref, RX VrefLevel [Byte0]: 33
3307 13:58:40.242356 [Byte1]: 33
3308 13:58:40.246801
3309 13:58:40.246882 Set Vref, RX VrefLevel [Byte0]: 34
3310 13:58:40.249832 [Byte1]: 34
3311 13:58:40.254669
3312 13:58:40.254787 Set Vref, RX VrefLevel [Byte0]: 35
3313 13:58:40.258107 [Byte1]: 35
3314 13:58:40.262589
3315 13:58:40.262698 Set Vref, RX VrefLevel [Byte0]: 36
3316 13:58:40.265693 [Byte1]: 36
3317 13:58:40.270676
3318 13:58:40.270791 Set Vref, RX VrefLevel [Byte0]: 37
3319 13:58:40.273880 [Byte1]: 37
3320 13:58:40.278734
3321 13:58:40.278829 Set Vref, RX VrefLevel [Byte0]: 38
3322 13:58:40.281996 [Byte1]: 38
3323 13:58:40.286730
3324 13:58:40.286871 Set Vref, RX VrefLevel [Byte0]: 39
3325 13:58:40.289716 [Byte1]: 39
3326 13:58:40.294411
3327 13:58:40.294493 Set Vref, RX VrefLevel [Byte0]: 40
3328 13:58:40.297782 [Byte1]: 40
3329 13:58:40.302485
3330 13:58:40.302566 Set Vref, RX VrefLevel [Byte0]: 41
3331 13:58:40.305456 [Byte1]: 41
3332 13:58:40.310107
3333 13:58:40.310188 Set Vref, RX VrefLevel [Byte0]: 42
3334 13:58:40.313230 [Byte1]: 42
3335 13:58:40.318405
3336 13:58:40.318502 Set Vref, RX VrefLevel [Byte0]: 43
3337 13:58:40.321140 [Byte1]: 43
3338 13:58:40.326245
3339 13:58:40.326325 Set Vref, RX VrefLevel [Byte0]: 44
3340 13:58:40.329503 [Byte1]: 44
3341 13:58:40.334254
3342 13:58:40.334335 Set Vref, RX VrefLevel [Byte0]: 45
3343 13:58:40.337006 [Byte1]: 45
3344 13:58:40.342132
3345 13:58:40.342228 Set Vref, RX VrefLevel [Byte0]: 46
3346 13:58:40.345321 [Byte1]: 46
3347 13:58:40.349550
3348 13:58:40.349631 Set Vref, RX VrefLevel [Byte0]: 47
3349 13:58:40.353647 [Byte1]: 47
3350 13:58:40.357364
3351 13:58:40.357445 Set Vref, RX VrefLevel [Byte0]: 48
3352 13:58:40.360678 [Byte1]: 48
3353 13:58:40.365561
3354 13:58:40.365642 Set Vref, RX VrefLevel [Byte0]: 49
3355 13:58:40.368772 [Byte1]: 49
3356 13:58:40.373724
3357 13:58:40.373805 Set Vref, RX VrefLevel [Byte0]: 50
3358 13:58:40.376710 [Byte1]: 50
3359 13:58:40.381314
3360 13:58:40.381396 Set Vref, RX VrefLevel [Byte0]: 51
3361 13:58:40.384879 [Byte1]: 51
3362 13:58:40.389260
3363 13:58:40.392721 Set Vref, RX VrefLevel [Byte0]: 52
3364 13:58:40.395882 [Byte1]: 52
3365 13:58:40.395964
3366 13:58:40.399026 Set Vref, RX VrefLevel [Byte0]: 53
3367 13:58:40.402658 [Byte1]: 53
3368 13:58:40.402751
3369 13:58:40.406050 Set Vref, RX VrefLevel [Byte0]: 54
3370 13:58:40.409638 [Byte1]: 54
3371 13:58:40.413183
3372 13:58:40.413263 Set Vref, RX VrefLevel [Byte0]: 55
3373 13:58:40.416529 [Byte1]: 55
3374 13:58:40.421184
3375 13:58:40.421265 Set Vref, RX VrefLevel [Byte0]: 56
3376 13:58:40.424366 [Byte1]: 56
3377 13:58:40.428955
3378 13:58:40.429036 Set Vref, RX VrefLevel [Byte0]: 57
3379 13:58:40.432223 [Byte1]: 57
3380 13:58:40.437066
3381 13:58:40.437175 Set Vref, RX VrefLevel [Byte0]: 58
3382 13:58:40.440056 [Byte1]: 58
3383 13:58:40.445187
3384 13:58:40.445261 Set Vref, RX VrefLevel [Byte0]: 59
3385 13:58:40.447907 [Byte1]: 59
3386 13:58:40.452631
3387 13:58:40.452735 Set Vref, RX VrefLevel [Byte0]: 60
3388 13:58:40.456119 [Byte1]: 60
3389 13:58:40.460489
3390 13:58:40.460563 Set Vref, RX VrefLevel [Byte0]: 61
3391 13:58:40.463872 [Byte1]: 61
3392 13:58:40.468458
3393 13:58:40.468565 Set Vref, RX VrefLevel [Byte0]: 62
3394 13:58:40.471936 [Byte1]: 62
3395 13:58:40.476821
3396 13:58:40.476919 Set Vref, RX VrefLevel [Byte0]: 63
3397 13:58:40.479687 [Byte1]: 63
3398 13:58:40.484331
3399 13:58:40.484415 Set Vref, RX VrefLevel [Byte0]: 64
3400 13:58:40.487714 [Byte1]: 64
3401 13:58:40.492242
3402 13:58:40.492323 Set Vref, RX VrefLevel [Byte0]: 65
3403 13:58:40.495622 [Byte1]: 65
3404 13:58:40.500306
3405 13:58:40.500387 Set Vref, RX VrefLevel [Byte0]: 66
3406 13:58:40.503742 [Byte1]: 66
3407 13:58:40.508050
3408 13:58:40.508131 Set Vref, RX VrefLevel [Byte0]: 67
3409 13:58:40.511599 [Byte1]: 67
3410 13:58:40.515896
3411 13:58:40.515977 Set Vref, RX VrefLevel [Byte0]: 68
3412 13:58:40.519315 [Byte1]: 68
3413 13:58:40.523944
3414 13:58:40.524025 Set Vref, RX VrefLevel [Byte0]: 69
3415 13:58:40.527121 [Byte1]: 69
3416 13:58:40.531661
3417 13:58:40.531742 Set Vref, RX VrefLevel [Byte0]: 70
3418 13:58:40.535297 [Byte1]: 70
3419 13:58:40.539816
3420 13:58:40.539953 Final RX Vref Byte 0 = 58 to rank0
3421 13:58:40.543009 Final RX Vref Byte 1 = 54 to rank0
3422 13:58:40.546346 Final RX Vref Byte 0 = 58 to rank1
3423 13:58:40.549933 Final RX Vref Byte 1 = 54 to rank1==
3424 13:58:40.553098 Dram Type= 6, Freq= 0, CH_1, rank 0
3425 13:58:40.556429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 13:58:40.559733 ==
3427 13:58:40.559815 DQS Delay:
3428 13:58:40.559880 DQS0 = 0, DQS1 = 0
3429 13:58:40.563183 DQM Delay:
3430 13:58:40.563265 DQM0 = 115, DQM1 = 109
3431 13:58:40.566587 DQ Delay:
3432 13:58:40.570076 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3433 13:58:40.573577 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =112
3434 13:58:40.576643 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3435 13:58:40.580519 DQ12 =118, DQ13 =114, DQ14 =116, DQ15 =114
3436 13:58:40.580600
3437 13:58:40.580665
3438 13:58:40.587127 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e7, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
3439 13:58:40.590416 CH1 RK0: MR19=403, MR18=3E7
3440 13:58:40.597248 CH1_RK0: MR19=0x403, MR18=0x3E7, DQSOSC=408, MR23=63, INC=39, DEC=26
3441 13:58:40.597356
3442 13:58:40.600205 ----->DramcWriteLeveling(PI) begin...
3443 13:58:40.600308 ==
3444 13:58:40.603816 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 13:58:40.606863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 13:58:40.606951 ==
3447 13:58:40.610436 Write leveling (Byte 0): 26 => 26
3448 13:58:40.613645 Write leveling (Byte 1): 29 => 29
3449 13:58:40.616940 DramcWriteLeveling(PI) end<-----
3450 13:58:40.617038
3451 13:58:40.617139 ==
3452 13:58:40.620625 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 13:58:40.623890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 13:58:40.623993 ==
3455 13:58:40.627385 [Gating] SW mode calibration
3456 13:58:40.633725 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3457 13:58:40.640534 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3458 13:58:40.644221 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3459 13:58:40.647403 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3460 13:58:40.654096 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 13:58:40.657919 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 13:58:40.661142 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 13:58:40.667530 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3464 13:58:40.671041 0 15 24 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (0 1)
3465 13:58:40.674129 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3466 13:58:40.680801 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 13:58:40.684280 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 13:58:40.687848 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3469 13:58:40.694159 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3470 13:58:40.697608 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 13:58:40.700816 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 13:58:40.704806 1 0 24 | B1->B0 | 2525 4343 | 0 0 | (0 0) (1 1)
3473 13:58:40.710718 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 13:58:40.714132 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 13:58:40.717640 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 13:58:40.724061 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 13:58:40.727924 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 13:58:40.730865 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 13:58:40.737684 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 13:58:40.741009 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3481 13:58:40.744185 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3482 13:58:40.751076 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 13:58:40.754135 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 13:58:40.757421 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 13:58:40.764412 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 13:58:40.767620 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 13:58:40.771011 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 13:58:40.777932 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 13:58:40.781393 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 13:58:40.784803 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 13:58:40.791100 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 13:58:40.794600 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 13:58:40.798016 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 13:58:40.801091 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 13:58:40.807782 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 13:58:40.810868 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3497 13:58:40.814394 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3498 13:58:40.817552 Total UI for P1: 0, mck2ui 16
3499 13:58:40.820870 best dqsien dly found for B0: ( 1, 3, 24)
3500 13:58:40.827660 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 13:58:40.827739 Total UI for P1: 0, mck2ui 16
3502 13:58:40.834559 best dqsien dly found for B1: ( 1, 3, 26)
3503 13:58:40.837591 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3504 13:58:40.841432 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3505 13:58:40.841530
3506 13:58:40.844354 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3507 13:58:40.847903 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3508 13:58:40.851136 [Gating] SW calibration Done
3509 13:58:40.851210 ==
3510 13:58:40.854897 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 13:58:40.857763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 13:58:40.857866 ==
3513 13:58:40.861404 RX Vref Scan: 0
3514 13:58:40.861506
3515 13:58:40.861595 RX Vref 0 -> 0, step: 1
3516 13:58:40.861690
3517 13:58:40.864545 RX Delay -40 -> 252, step: 8
3518 13:58:40.867797 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3519 13:58:40.874873 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3520 13:58:40.877731 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3521 13:58:40.881170 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3522 13:58:40.884433 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3523 13:58:40.887686 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3524 13:58:40.894973 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3525 13:58:40.897945 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3526 13:58:40.900995 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3527 13:58:40.904512 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3528 13:58:40.907682 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3529 13:58:40.911445 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3530 13:58:40.917641 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3531 13:58:40.921070 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3532 13:58:40.924284 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3533 13:58:40.928148 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3534 13:58:40.928224 ==
3535 13:58:40.931390 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 13:58:40.938234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 13:58:40.938327 ==
3538 13:58:40.938392 DQS Delay:
3539 13:58:40.941131 DQS0 = 0, DQS1 = 0
3540 13:58:40.941207 DQM Delay:
3541 13:58:40.941275 DQM0 = 113, DQM1 = 110
3542 13:58:40.944781 DQ Delay:
3543 13:58:40.948236 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3544 13:58:40.951231 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3545 13:58:40.954729 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3546 13:58:40.957757 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3547 13:58:40.957830
3548 13:58:40.957895
3549 13:58:40.957955 ==
3550 13:58:40.961449 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 13:58:40.964475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 13:58:40.967655 ==
3553 13:58:40.967737
3554 13:58:40.967800
3555 13:58:40.967860 TX Vref Scan disable
3556 13:58:40.971361 == TX Byte 0 ==
3557 13:58:40.974478 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3558 13:58:40.978100 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3559 13:58:40.981258 == TX Byte 1 ==
3560 13:58:40.984519 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3561 13:58:40.987723 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3562 13:58:40.987805 ==
3563 13:58:40.991369 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 13:58:40.998238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 13:58:40.998320 ==
3566 13:58:41.008505 TX Vref=22, minBit 0, minWin=25, winSum=413
3567 13:58:41.011973 TX Vref=24, minBit 3, minWin=25, winSum=423
3568 13:58:41.015220 TX Vref=26, minBit 1, minWin=26, winSum=429
3569 13:58:41.018671 TX Vref=28, minBit 1, minWin=26, winSum=434
3570 13:58:41.022003 TX Vref=30, minBit 0, minWin=26, winSum=431
3571 13:58:41.025682 TX Vref=32, minBit 15, minWin=25, winSum=427
3572 13:58:41.031904 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 28
3573 13:58:41.031986
3574 13:58:41.035371 Final TX Range 1 Vref 28
3575 13:58:41.035454
3576 13:58:41.035519 ==
3577 13:58:41.039237 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 13:58:41.042133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 13:58:41.042215 ==
3580 13:58:41.042281
3581 13:58:41.042373
3582 13:58:41.045536 TX Vref Scan disable
3583 13:58:41.049352 == TX Byte 0 ==
3584 13:58:41.052015 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3585 13:58:41.055089 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3586 13:58:41.058572 == TX Byte 1 ==
3587 13:58:41.061940 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3588 13:58:41.065618 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3589 13:58:41.065700
3590 13:58:41.068468 [DATLAT]
3591 13:58:41.068574 Freq=1200, CH1 RK1
3592 13:58:41.068641
3593 13:58:41.072174 DATLAT Default: 0xd
3594 13:58:41.072255 0, 0xFFFF, sum = 0
3595 13:58:41.075132 1, 0xFFFF, sum = 0
3596 13:58:41.075215 2, 0xFFFF, sum = 0
3597 13:58:41.078434 3, 0xFFFF, sum = 0
3598 13:58:41.078518 4, 0xFFFF, sum = 0
3599 13:58:41.081977 5, 0xFFFF, sum = 0
3600 13:58:41.082060 6, 0xFFFF, sum = 0
3601 13:58:41.085173 7, 0xFFFF, sum = 0
3602 13:58:41.089248 8, 0xFFFF, sum = 0
3603 13:58:41.089332 9, 0xFFFF, sum = 0
3604 13:58:41.091887 10, 0xFFFF, sum = 0
3605 13:58:41.092001 11, 0xFFFF, sum = 0
3606 13:58:41.095181 12, 0x0, sum = 1
3607 13:58:41.095264 13, 0x0, sum = 2
3608 13:58:41.098982 14, 0x0, sum = 3
3609 13:58:41.099065 15, 0x0, sum = 4
3610 13:58:41.099134 best_step = 13
3611 13:58:41.099195
3612 13:58:41.101632 ==
3613 13:58:41.105393 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 13:58:41.108812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 13:58:41.108913 ==
3616 13:58:41.108980 RX Vref Scan: 0
3617 13:58:41.109072
3618 13:58:41.112179 RX Vref 0 -> 0, step: 1
3619 13:58:41.112260
3620 13:58:41.115455 RX Delay -21 -> 252, step: 4
3621 13:58:41.118674 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3622 13:58:41.125207 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3623 13:58:41.128435 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3624 13:58:41.131930 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3625 13:58:41.135414 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3626 13:58:41.138872 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3627 13:58:41.141717 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3628 13:58:41.148488 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3629 13:58:41.151834 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3630 13:58:41.155491 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3631 13:58:41.158895 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3632 13:58:41.162193 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3633 13:58:41.168646 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3634 13:58:41.172065 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3635 13:58:41.175210 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3636 13:58:41.178553 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3637 13:58:41.178635 ==
3638 13:58:41.182064 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 13:58:41.188891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 13:58:41.188974 ==
3641 13:58:41.189038 DQS Delay:
3642 13:58:41.189098 DQS0 = 0, DQS1 = 0
3643 13:58:41.191904 DQM Delay:
3644 13:58:41.191986 DQM0 = 113, DQM1 = 110
3645 13:58:41.195352 DQ Delay:
3646 13:58:41.198671 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3647 13:58:41.202049 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3648 13:58:41.205115 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3649 13:58:41.208845 DQ12 =116, DQ13 =118, DQ14 =118, DQ15 =120
3650 13:58:41.208927
3651 13:58:41.208992
3652 13:58:41.215424 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa03, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 412 ps
3653 13:58:41.218736 CH1 RK1: MR19=304, MR18=FA03
3654 13:58:41.225386 CH1_RK1: MR19=0x304, MR18=0xFA03, DQSOSC=408, MR23=63, INC=39, DEC=26
3655 13:58:41.228623 [RxdqsGatingPostProcess] freq 1200
3656 13:58:41.235137 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3657 13:58:41.238798 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 13:58:41.238886 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 13:58:41.241915 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 13:58:41.245782 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 13:58:41.248805 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 13:58:41.251869 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 13:58:41.255369 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 13:58:41.259083 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 13:58:41.261942 Pre-setting of DQS Precalculation
3666 13:58:41.269026 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3667 13:58:41.276122 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3668 13:58:41.282238 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3669 13:58:41.282342
3670 13:58:41.282437
3671 13:58:41.285976 [Calibration Summary] 2400 Mbps
3672 13:58:41.286076 CH 0, Rank 0
3673 13:58:41.288990 SW Impedance : PASS
3674 13:58:41.289087 DUTY Scan : NO K
3675 13:58:41.292295 ZQ Calibration : PASS
3676 13:58:41.295627 Jitter Meter : NO K
3677 13:58:41.295697 CBT Training : PASS
3678 13:58:41.298877 Write leveling : PASS
3679 13:58:41.302614 RX DQS gating : PASS
3680 13:58:41.302711 RX DQ/DQS(RDDQC) : PASS
3681 13:58:41.306259 TX DQ/DQS : PASS
3682 13:58:41.309002 RX DATLAT : PASS
3683 13:58:41.309096 RX DQ/DQS(Engine): PASS
3684 13:58:41.312496 TX OE : NO K
3685 13:58:41.312573 All Pass.
3686 13:58:41.312635
3687 13:58:41.315788 CH 0, Rank 1
3688 13:58:41.315859 SW Impedance : PASS
3689 13:58:41.319187 DUTY Scan : NO K
3690 13:58:41.319264 ZQ Calibration : PASS
3691 13:58:41.322673 Jitter Meter : NO K
3692 13:58:41.325958 CBT Training : PASS
3693 13:58:41.326058 Write leveling : PASS
3694 13:58:41.329144 RX DQS gating : PASS
3695 13:58:41.332389 RX DQ/DQS(RDDQC) : PASS
3696 13:58:41.332458 TX DQ/DQS : PASS
3697 13:58:41.336018 RX DATLAT : PASS
3698 13:58:41.339178 RX DQ/DQS(Engine): PASS
3699 13:58:41.339245 TX OE : NO K
3700 13:58:41.342479 All Pass.
3701 13:58:41.342571
3702 13:58:41.342658 CH 1, Rank 0
3703 13:58:41.346053 SW Impedance : PASS
3704 13:58:41.346120 DUTY Scan : NO K
3705 13:58:41.349407 ZQ Calibration : PASS
3706 13:58:41.352760 Jitter Meter : NO K
3707 13:58:41.352855 CBT Training : PASS
3708 13:58:41.355994 Write leveling : PASS
3709 13:58:41.359136 RX DQS gating : PASS
3710 13:58:41.359229 RX DQ/DQS(RDDQC) : PASS
3711 13:58:41.362684 TX DQ/DQS : PASS
3712 13:58:41.362812 RX DATLAT : PASS
3713 13:58:41.366288 RX DQ/DQS(Engine): PASS
3714 13:58:41.369417 TX OE : NO K
3715 13:58:41.369521 All Pass.
3716 13:58:41.369615
3717 13:58:41.369702 CH 1, Rank 1
3718 13:58:41.372798 SW Impedance : PASS
3719 13:58:41.376038 DUTY Scan : NO K
3720 13:58:41.376132 ZQ Calibration : PASS
3721 13:58:41.379612 Jitter Meter : NO K
3722 13:58:41.382987 CBT Training : PASS
3723 13:58:41.383062 Write leveling : PASS
3724 13:58:41.386162 RX DQS gating : PASS
3725 13:58:41.389510 RX DQ/DQS(RDDQC) : PASS
3726 13:58:41.389610 TX DQ/DQS : PASS
3727 13:58:41.392643 RX DATLAT : PASS
3728 13:58:41.392720 RX DQ/DQS(Engine): PASS
3729 13:58:41.396112 TX OE : NO K
3730 13:58:41.396187 All Pass.
3731 13:58:41.396250
3732 13:58:41.399407 DramC Write-DBI off
3733 13:58:41.402846 PER_BANK_REFRESH: Hybrid Mode
3734 13:58:41.402916 TX_TRACKING: ON
3735 13:58:41.412966 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3736 13:58:41.416379 [FAST_K] Save calibration result to emmc
3737 13:58:41.419560 dramc_set_vcore_voltage set vcore to 650000
3738 13:58:41.422944 Read voltage for 600, 5
3739 13:58:41.423027 Vio18 = 0
3740 13:58:41.423093 Vcore = 650000
3741 13:58:41.426413 Vdram = 0
3742 13:58:41.426494 Vddq = 0
3743 13:58:41.426558 Vmddr = 0
3744 13:58:41.433248 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3745 13:58:41.436626 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3746 13:58:41.439860 MEM_TYPE=3, freq_sel=19
3747 13:58:41.443062 sv_algorithm_assistance_LP4_1600
3748 13:58:41.446618 ============ PULL DRAM RESETB DOWN ============
3749 13:58:41.449583 ========== PULL DRAM RESETB DOWN end =========
3750 13:58:41.456073 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3751 13:58:41.459405 ===================================
3752 13:58:41.462885 LPDDR4 DRAM CONFIGURATION
3753 13:58:41.466220 ===================================
3754 13:58:41.466301 EX_ROW_EN[0] = 0x0
3755 13:58:41.469423 EX_ROW_EN[1] = 0x0
3756 13:58:41.469504 LP4Y_EN = 0x0
3757 13:58:41.472813 WORK_FSP = 0x0
3758 13:58:41.472895 WL = 0x2
3759 13:58:41.476331 RL = 0x2
3760 13:58:41.476413 BL = 0x2
3761 13:58:41.479422 RPST = 0x0
3762 13:58:41.479503 RD_PRE = 0x0
3763 13:58:41.482546 WR_PRE = 0x1
3764 13:58:41.482627 WR_PST = 0x0
3765 13:58:41.486220 DBI_WR = 0x0
3766 13:58:41.486301 DBI_RD = 0x0
3767 13:58:41.489230 OTF = 0x1
3768 13:58:41.492861 ===================================
3769 13:58:41.496050 ===================================
3770 13:58:41.496132 ANA top config
3771 13:58:41.499796 ===================================
3772 13:58:41.502476 DLL_ASYNC_EN = 0
3773 13:58:41.506088 ALL_SLAVE_EN = 1
3774 13:58:41.509409 NEW_RANK_MODE = 1
3775 13:58:41.509492 DLL_IDLE_MODE = 1
3776 13:58:41.512831 LP45_APHY_COMB_EN = 1
3777 13:58:41.516291 TX_ODT_DIS = 1
3778 13:58:41.519102 NEW_8X_MODE = 1
3779 13:58:41.522464 ===================================
3780 13:58:41.526388 ===================================
3781 13:58:41.529496 data_rate = 1200
3782 13:58:41.529570 CKR = 1
3783 13:58:41.532678 DQ_P2S_RATIO = 8
3784 13:58:41.535861 ===================================
3785 13:58:41.539313 CA_P2S_RATIO = 8
3786 13:58:41.542780 DQ_CA_OPEN = 0
3787 13:58:41.546614 DQ_SEMI_OPEN = 0
3788 13:58:41.549286 CA_SEMI_OPEN = 0
3789 13:58:41.549368 CA_FULL_RATE = 0
3790 13:58:41.552472 DQ_CKDIV4_EN = 1
3791 13:58:41.556042 CA_CKDIV4_EN = 1
3792 13:58:41.559304 CA_PREDIV_EN = 0
3793 13:58:41.562608 PH8_DLY = 0
3794 13:58:41.566090 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3795 13:58:41.566171 DQ_AAMCK_DIV = 4
3796 13:58:41.569288 CA_AAMCK_DIV = 4
3797 13:58:41.572628 CA_ADMCK_DIV = 4
3798 13:58:41.576416 DQ_TRACK_CA_EN = 0
3799 13:58:41.579524 CA_PICK = 600
3800 13:58:41.582558 CA_MCKIO = 600
3801 13:58:41.582656 MCKIO_SEMI = 0
3802 13:58:41.586407 PLL_FREQ = 2288
3803 13:58:41.589330 DQ_UI_PI_RATIO = 32
3804 13:58:41.592844 CA_UI_PI_RATIO = 0
3805 13:58:41.595962 ===================================
3806 13:58:41.599482 ===================================
3807 13:58:41.603005 memory_type:LPDDR4
3808 13:58:41.603100 GP_NUM : 10
3809 13:58:41.606381 SRAM_EN : 1
3810 13:58:41.609221 MD32_EN : 0
3811 13:58:41.612982 ===================================
3812 13:58:41.613081 [ANA_INIT] >>>>>>>>>>>>>>
3813 13:58:41.616297 <<<<<< [CONFIGURE PHASE]: ANA_TX
3814 13:58:41.619278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3815 13:58:41.622528 ===================================
3816 13:58:41.626086 data_rate = 1200,PCW = 0X5800
3817 13:58:41.629201 ===================================
3818 13:58:41.633022 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3819 13:58:41.639373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 13:58:41.643043 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 13:58:41.649274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3822 13:58:41.652753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3823 13:58:41.656117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3824 13:58:41.656210 [ANA_INIT] flow start
3825 13:58:41.659491 [ANA_INIT] PLL >>>>>>>>
3826 13:58:41.662523 [ANA_INIT] PLL <<<<<<<<
3827 13:58:41.662630 [ANA_INIT] MIDPI >>>>>>>>
3828 13:58:41.666164 [ANA_INIT] MIDPI <<<<<<<<
3829 13:58:41.669268 [ANA_INIT] DLL >>>>>>>>
3830 13:58:41.669380 [ANA_INIT] flow end
3831 13:58:41.676038 ============ LP4 DIFF to SE enter ============
3832 13:58:41.679537 ============ LP4 DIFF to SE exit ============
3833 13:58:41.682887 [ANA_INIT] <<<<<<<<<<<<<
3834 13:58:41.685973 [Flow] Enable top DCM control >>>>>
3835 13:58:41.689931 [Flow] Enable top DCM control <<<<<
3836 13:58:41.690054 Enable DLL master slave shuffle
3837 13:58:41.696597 ==============================================================
3838 13:58:41.700104 Gating Mode config
3839 13:58:41.702953 ==============================================================
3840 13:58:41.706121 Config description:
3841 13:58:41.716020 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3842 13:58:41.722623 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3843 13:58:41.725835 SELPH_MODE 0: By rank 1: By Phase
3844 13:58:41.732567 ==============================================================
3845 13:58:41.735924 GAT_TRACK_EN = 1
3846 13:58:41.739649 RX_GATING_MODE = 2
3847 13:58:41.742755 RX_GATING_TRACK_MODE = 2
3848 13:58:41.742831 SELPH_MODE = 1
3849 13:58:41.746632 PICG_EARLY_EN = 1
3850 13:58:41.749341 VALID_LAT_VALUE = 1
3851 13:58:41.756325 ==============================================================
3852 13:58:41.759329 Enter into Gating configuration >>>>
3853 13:58:41.762575 Exit from Gating configuration <<<<
3854 13:58:41.766531 Enter into DVFS_PRE_config >>>>>
3855 13:58:41.776052 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3856 13:58:41.779281 Exit from DVFS_PRE_config <<<<<
3857 13:58:41.783048 Enter into PICG configuration >>>>
3858 13:58:41.786183 Exit from PICG configuration <<<<
3859 13:58:41.789519 [RX_INPUT] configuration >>>>>
3860 13:58:41.793193 [RX_INPUT] configuration <<<<<
3861 13:58:41.796167 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3862 13:58:41.803047 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3863 13:58:41.809604 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3864 13:58:41.812678 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3865 13:58:41.820247 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 13:58:41.826298 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 13:58:41.829547 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3868 13:58:41.832630 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3869 13:58:41.839301 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3870 13:58:41.843076 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3871 13:58:41.846372 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3872 13:58:41.853145 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 13:58:41.856080 ===================================
3874 13:58:41.856155 LPDDR4 DRAM CONFIGURATION
3875 13:58:41.859870 ===================================
3876 13:58:41.862742 EX_ROW_EN[0] = 0x0
3877 13:58:41.862826 EX_ROW_EN[1] = 0x0
3878 13:58:41.866320 LP4Y_EN = 0x0
3879 13:58:41.869672 WORK_FSP = 0x0
3880 13:58:41.869755 WL = 0x2
3881 13:58:41.872988 RL = 0x2
3882 13:58:41.873078 BL = 0x2
3883 13:58:41.876055 RPST = 0x0
3884 13:58:41.876141 RD_PRE = 0x0
3885 13:58:41.879329 WR_PRE = 0x1
3886 13:58:41.879441 WR_PST = 0x0
3887 13:58:41.882674 DBI_WR = 0x0
3888 13:58:41.882799 DBI_RD = 0x0
3889 13:58:41.886226 OTF = 0x1
3890 13:58:41.889569 ===================================
3891 13:58:41.892920 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3892 13:58:41.896279 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3893 13:58:41.903085 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 13:58:41.903165 ===================================
3895 13:58:41.906582 LPDDR4 DRAM CONFIGURATION
3896 13:58:41.909619 ===================================
3897 13:58:41.912837 EX_ROW_EN[0] = 0x10
3898 13:58:41.912943 EX_ROW_EN[1] = 0x0
3899 13:58:41.916495 LP4Y_EN = 0x0
3900 13:58:41.916597 WORK_FSP = 0x0
3901 13:58:41.919528 WL = 0x2
3902 13:58:41.919602 RL = 0x2
3903 13:58:41.923058 BL = 0x2
3904 13:58:41.923132 RPST = 0x0
3905 13:58:41.926500 RD_PRE = 0x0
3906 13:58:41.926597 WR_PRE = 0x1
3907 13:58:41.929855 WR_PST = 0x0
3908 13:58:41.929953 DBI_WR = 0x0
3909 13:58:41.933043 DBI_RD = 0x0
3910 13:58:41.933143 OTF = 0x1
3911 13:58:41.936798 ===================================
3912 13:58:41.943204 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3913 13:58:41.947966 nWR fixed to 30
3914 13:58:41.951595 [ModeRegInit_LP4] CH0 RK0
3915 13:58:41.951672 [ModeRegInit_LP4] CH0 RK1
3916 13:58:41.954685 [ModeRegInit_LP4] CH1 RK0
3917 13:58:41.958087 [ModeRegInit_LP4] CH1 RK1
3918 13:58:41.958174 match AC timing 17
3919 13:58:41.964696 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3920 13:58:41.968069 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3921 13:58:41.971857 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3922 13:58:41.978114 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3923 13:58:41.981537 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3924 13:58:41.981638 ==
3925 13:58:41.984772 Dram Type= 6, Freq= 0, CH_0, rank 0
3926 13:58:41.988359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 13:58:41.988458 ==
3928 13:58:41.994716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 13:58:42.001858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3930 13:58:42.004919 [CA 0] Center 36 (6~66) winsize 61
3931 13:58:42.008106 [CA 1] Center 36 (6~66) winsize 61
3932 13:58:42.011843 [CA 2] Center 34 (4~65) winsize 62
3933 13:58:42.015195 [CA 3] Center 34 (4~64) winsize 61
3934 13:58:42.018117 [CA 4] Center 33 (3~64) winsize 62
3935 13:58:42.021514 [CA 5] Center 33 (3~64) winsize 62
3936 13:58:42.021612
3937 13:58:42.025017 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3938 13:58:42.025119
3939 13:58:42.028544 [CATrainingPosCal] consider 1 rank data
3940 13:58:42.031444 u2DelayCellTimex100 = 270/100 ps
3941 13:58:42.035158 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3942 13:58:42.038191 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3943 13:58:42.041735 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3944 13:58:42.045062 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3945 13:58:42.048131 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3946 13:58:42.051834 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3947 13:58:42.051908
3948 13:58:42.055231 CA PerBit enable=1, Macro0, CA PI delay=33
3949 13:58:42.058632
3950 13:58:42.058752 [CBTSetCACLKResult] CA Dly = 33
3951 13:58:42.061692 CS Dly: 3 (0~34)
3952 13:58:42.061785 ==
3953 13:58:42.064977 Dram Type= 6, Freq= 0, CH_0, rank 1
3954 13:58:42.068340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 13:58:42.068416 ==
3956 13:58:42.074918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 13:58:42.081520 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3958 13:58:42.084757 [CA 0] Center 35 (5~66) winsize 62
3959 13:58:42.088389 [CA 1] Center 35 (5~66) winsize 62
3960 13:58:42.091892 [CA 2] Center 34 (4~65) winsize 62
3961 13:58:42.095079 [CA 3] Center 34 (4~64) winsize 61
3962 13:58:42.098161 [CA 4] Center 33 (3~64) winsize 62
3963 13:58:42.101765 [CA 5] Center 33 (3~64) winsize 62
3964 13:58:42.101867
3965 13:58:42.105037 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3966 13:58:42.105117
3967 13:58:42.108604 [CATrainingPosCal] consider 2 rank data
3968 13:58:42.111556 u2DelayCellTimex100 = 270/100 ps
3969 13:58:42.115346 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3970 13:58:42.118136 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3971 13:58:42.121745 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3972 13:58:42.124997 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3973 13:58:42.128774 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 13:58:42.131508 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3975 13:58:42.131588
3976 13:58:42.138134 CA PerBit enable=1, Macro0, CA PI delay=33
3977 13:58:42.138216
3978 13:58:42.138279 [CBTSetCACLKResult] CA Dly = 33
3979 13:58:42.141888 CS Dly: 3 (0~35)
3980 13:58:42.141968
3981 13:58:42.144963 ----->DramcWriteLeveling(PI) begin...
3982 13:58:42.145045 ==
3983 13:58:42.148125 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 13:58:42.151668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 13:58:42.151750 ==
3986 13:58:42.155145 Write leveling (Byte 0): 33 => 33
3987 13:58:42.158308 Write leveling (Byte 1): 31 => 31
3988 13:58:42.162033 DramcWriteLeveling(PI) end<-----
3989 13:58:42.162113
3990 13:58:42.162177 ==
3991 13:58:42.164959 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 13:58:42.168124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 13:58:42.171468 ==
3994 13:58:42.171549 [Gating] SW mode calibration
3995 13:58:42.178654 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3996 13:58:42.184895 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3997 13:58:42.188373 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 13:58:42.195059 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 13:58:42.198864 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 13:58:42.201914 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 13:58:42.208454 0 9 16 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 1)
4002 13:58:42.211738 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 13:58:42.215210 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 13:58:42.218196 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 13:58:42.224953 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 13:58:42.228615 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 13:58:42.231768 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 13:58:42.238330 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 13:58:42.242016 0 10 16 | B1->B0 | 3232 3d3d | 0 0 | (0 0) (0 0)
4010 13:58:42.244937 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 13:58:42.251878 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 13:58:42.255379 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 13:58:42.258665 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 13:58:42.264868 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 13:58:42.268445 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 13:58:42.272068 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 13:58:42.278496 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4018 13:58:42.281978 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 13:58:42.285170 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 13:58:42.291987 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 13:58:42.295406 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 13:58:42.298903 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 13:58:42.302094 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 13:58:42.308554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 13:58:42.312036 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 13:58:42.315065 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 13:58:42.322049 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 13:58:42.325286 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 13:58:42.328478 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 13:58:42.335091 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 13:58:42.338466 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 13:58:42.341783 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 13:58:42.348712 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4034 13:58:42.351917 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 13:58:42.355442 Total UI for P1: 0, mck2ui 16
4036 13:58:42.358674 best dqsien dly found for B0: ( 0, 13, 16)
4037 13:58:42.362268 Total UI for P1: 0, mck2ui 16
4038 13:58:42.365300 best dqsien dly found for B1: ( 0, 13, 18)
4039 13:58:42.368734 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4040 13:58:42.372115 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4041 13:58:42.372196
4042 13:58:42.375649 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4043 13:58:42.378904 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4044 13:58:42.382118 [Gating] SW calibration Done
4045 13:58:42.382200 ==
4046 13:58:42.385891 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 13:58:42.389151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 13:58:42.389258 ==
4049 13:58:42.392256 RX Vref Scan: 0
4050 13:58:42.392324
4051 13:58:42.395531 RX Vref 0 -> 0, step: 1
4052 13:58:42.395610
4053 13:58:42.395674 RX Delay -230 -> 252, step: 16
4054 13:58:42.402596 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4055 13:58:42.405685 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4056 13:58:42.408815 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4057 13:58:42.412213 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4058 13:58:42.419083 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4059 13:58:42.422327 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4060 13:58:42.425678 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4061 13:58:42.429263 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4062 13:58:42.432266 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4063 13:58:42.439504 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4064 13:58:42.442152 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4065 13:58:42.445575 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4066 13:58:42.448862 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4067 13:58:42.455657 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4068 13:58:42.458876 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4069 13:58:42.462106 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4070 13:58:42.462186 ==
4071 13:58:42.465417 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 13:58:42.469231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 13:58:42.469313 ==
4074 13:58:42.472167 DQS Delay:
4075 13:58:42.472248 DQS0 = 0, DQS1 = 0
4076 13:58:42.475639 DQM Delay:
4077 13:58:42.475747 DQM0 = 40, DQM1 = 32
4078 13:58:42.475853 DQ Delay:
4079 13:58:42.478695 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4080 13:58:42.482290 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4081 13:58:42.485484 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4082 13:58:42.488745 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4083 13:58:42.488826
4084 13:58:42.488891
4085 13:58:42.492234 ==
4086 13:58:42.492314 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 13:58:42.499442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 13:58:42.499524 ==
4089 13:58:42.499589
4090 13:58:42.499648
4091 13:58:42.502235 TX Vref Scan disable
4092 13:58:42.502315 == TX Byte 0 ==
4093 13:58:42.505704 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4094 13:58:42.515082 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4095 13:58:42.515165 == TX Byte 1 ==
4096 13:58:42.515514 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4097 13:58:42.522677 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4098 13:58:42.522797 ==
4099 13:58:42.525396 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 13:58:42.528784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 13:58:42.528866 ==
4102 13:58:42.528932
4103 13:58:42.528993
4104 13:58:42.532330 TX Vref Scan disable
4105 13:58:42.536089 == TX Byte 0 ==
4106 13:58:42.538942 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4107 13:58:42.542463 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4108 13:58:42.545801 == TX Byte 1 ==
4109 13:58:42.548910 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4110 13:58:42.552460 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4111 13:58:42.552558
4112 13:58:42.555845 [DATLAT]
4113 13:58:42.555943 Freq=600, CH0 RK0
4114 13:58:42.556008
4115 13:58:42.559173 DATLAT Default: 0x9
4116 13:58:42.559255 0, 0xFFFF, sum = 0
4117 13:58:42.562403 1, 0xFFFF, sum = 0
4118 13:58:42.562486 2, 0xFFFF, sum = 0
4119 13:58:42.565737 3, 0xFFFF, sum = 0
4120 13:58:42.565820 4, 0xFFFF, sum = 0
4121 13:58:42.568922 5, 0xFFFF, sum = 0
4122 13:58:42.569005 6, 0xFFFF, sum = 0
4123 13:58:42.572234 7, 0xFFFF, sum = 0
4124 13:58:42.572317 8, 0x0, sum = 1
4125 13:58:42.576128 9, 0x0, sum = 2
4126 13:58:42.576210 10, 0x0, sum = 3
4127 13:58:42.576276 11, 0x0, sum = 4
4128 13:58:42.579365 best_step = 9
4129 13:58:42.579446
4130 13:58:42.579512 ==
4131 13:58:42.582593 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 13:58:42.585962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 13:58:42.586045 ==
4134 13:58:42.589642 RX Vref Scan: 1
4135 13:58:42.589728
4136 13:58:42.589793 RX Vref 0 -> 0, step: 1
4137 13:58:42.589854
4138 13:58:42.592606 RX Delay -195 -> 252, step: 8
4139 13:58:42.592688
4140 13:58:42.596059 Set Vref, RX VrefLevel [Byte0]: 53
4141 13:58:42.599077 [Byte1]: 51
4142 13:58:42.603545
4143 13:58:42.603625 Final RX Vref Byte 0 = 53 to rank0
4144 13:58:42.606693 Final RX Vref Byte 1 = 51 to rank0
4145 13:58:42.610441 Final RX Vref Byte 0 = 53 to rank1
4146 13:58:42.613434 Final RX Vref Byte 1 = 51 to rank1==
4147 13:58:42.616877 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 13:58:42.623721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 13:58:42.623802 ==
4150 13:58:42.623913 DQS Delay:
4151 13:58:42.623986 DQS0 = 0, DQS1 = 0
4152 13:58:42.627635 DQM Delay:
4153 13:58:42.627716 DQM0 = 42, DQM1 = 33
4154 13:58:42.630360 DQ Delay:
4155 13:58:42.634020 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4156 13:58:42.634101 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4157 13:58:42.637137 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4158 13:58:42.640480 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4159 13:58:42.643635
4160 13:58:42.643715
4161 13:58:42.650259 [DQSOSCAuto] RK0, (LSB)MR18= 0x4322, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4162 13:58:42.653657 CH0 RK0: MR19=808, MR18=4322
4163 13:58:42.660636 CH0_RK0: MR19=0x808, MR18=0x4322, DQSOSC=397, MR23=63, INC=166, DEC=110
4164 13:58:42.660717
4165 13:58:42.663764 ----->DramcWriteLeveling(PI) begin...
4166 13:58:42.663864 ==
4167 13:58:42.667170 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 13:58:42.670567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 13:58:42.670648 ==
4170 13:58:42.673958 Write leveling (Byte 0): 31 => 31
4171 13:58:42.677128 Write leveling (Byte 1): 30 => 30
4172 13:58:42.680395 DramcWriteLeveling(PI) end<-----
4173 13:58:42.680477
4174 13:58:42.680542 ==
4175 13:58:42.683626 Dram Type= 6, Freq= 0, CH_0, rank 1
4176 13:58:42.686922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 13:58:42.687003 ==
4178 13:58:42.690307 [Gating] SW mode calibration
4179 13:58:42.697495 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4180 13:58:42.703844 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4181 13:58:42.707494 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 13:58:42.710521 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 13:58:42.717119 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 13:58:42.720701 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4185 13:58:42.723859 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (0 1) (0 0)
4186 13:58:42.730685 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 13:58:42.734185 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 13:58:42.737539 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 13:58:42.740722 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 13:58:42.747247 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 13:58:42.750659 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 13:58:42.754025 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4193 13:58:42.760717 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4194 13:58:42.763971 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 13:58:42.767681 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 13:58:42.774294 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 13:58:42.777433 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 13:58:42.780843 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 13:58:42.787994 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 13:58:42.791093 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4201 13:58:42.794109 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4202 13:58:42.801237 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 13:58:42.804762 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 13:58:42.807858 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 13:58:42.810984 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 13:58:42.818197 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 13:58:42.821134 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 13:58:42.824649 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 13:58:42.831062 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 13:58:42.834155 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 13:58:42.837528 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 13:58:42.844235 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 13:58:42.847880 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 13:58:42.851118 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 13:58:42.857888 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 13:58:42.860892 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4217 13:58:42.864160 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4218 13:58:42.867860 Total UI for P1: 0, mck2ui 16
4219 13:58:42.871381 best dqsien dly found for B0: ( 0, 13, 12)
4220 13:58:42.877664 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 13:58:42.877746 Total UI for P1: 0, mck2ui 16
4222 13:58:42.881196 best dqsien dly found for B1: ( 0, 13, 16)
4223 13:58:42.887880 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4224 13:58:42.891055 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4225 13:58:42.891137
4226 13:58:42.894413 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4227 13:58:42.897722 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4228 13:58:42.901156 [Gating] SW calibration Done
4229 13:58:42.901238 ==
4230 13:58:42.904372 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 13:58:42.907983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 13:58:42.908069 ==
4233 13:58:42.911130 RX Vref Scan: 0
4234 13:58:42.911231
4235 13:58:42.911297 RX Vref 0 -> 0, step: 1
4236 13:58:42.911357
4237 13:58:42.914886 RX Delay -230 -> 252, step: 16
4238 13:58:42.918084 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4239 13:58:42.924767 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4240 13:58:42.927915 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4241 13:58:42.931061 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4242 13:58:42.934483 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4243 13:58:42.938075 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4244 13:58:42.944527 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4245 13:58:42.948579 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4246 13:58:42.951469 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4247 13:58:42.954552 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4248 13:58:42.958233 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4249 13:58:42.964584 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4250 13:58:42.968431 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4251 13:58:42.971326 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4252 13:58:42.974487 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4253 13:58:42.981620 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4254 13:58:42.981702 ==
4255 13:58:42.984845 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 13:58:42.988324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 13:58:42.988407 ==
4258 13:58:42.988472 DQS Delay:
4259 13:58:42.991333 DQS0 = 0, DQS1 = 0
4260 13:58:42.991415 DQM Delay:
4261 13:58:42.995012 DQM0 = 40, DQM1 = 32
4262 13:58:42.995094 DQ Delay:
4263 13:58:42.998450 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4264 13:58:43.001396 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4265 13:58:43.004766 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4266 13:58:43.008143 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4267 13:58:43.008255
4268 13:58:43.008320
4269 13:58:43.008381 ==
4270 13:58:43.011745 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 13:58:43.015601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 13:58:43.015683 ==
4273 13:58:43.015748
4274 13:58:43.018045
4275 13:58:43.018155 TX Vref Scan disable
4276 13:58:43.021670 == TX Byte 0 ==
4277 13:58:43.024929 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4278 13:58:43.028232 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4279 13:58:43.031824 == TX Byte 1 ==
4280 13:58:43.034931 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4281 13:58:43.038151 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4282 13:58:43.038264 ==
4283 13:58:43.041419 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 13:58:43.048321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 13:58:43.048404 ==
4286 13:58:43.048469
4287 13:58:43.048529
4288 13:58:43.048587 TX Vref Scan disable
4289 13:58:43.052772 == TX Byte 0 ==
4290 13:58:43.055936 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4291 13:58:43.059367 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4292 13:58:43.062578 == TX Byte 1 ==
4293 13:58:43.066217 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4294 13:58:43.069266 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4295 13:58:43.072782
4296 13:58:43.072864 [DATLAT]
4297 13:58:43.072928 Freq=600, CH0 RK1
4298 13:58:43.072988
4299 13:58:43.076290 DATLAT Default: 0x9
4300 13:58:43.076370 0, 0xFFFF, sum = 0
4301 13:58:43.079618 1, 0xFFFF, sum = 0
4302 13:58:43.079700 2, 0xFFFF, sum = 0
4303 13:58:43.083194 3, 0xFFFF, sum = 0
4304 13:58:43.083276 4, 0xFFFF, sum = 0
4305 13:58:43.086666 5, 0xFFFF, sum = 0
4306 13:58:43.086802 6, 0xFFFF, sum = 0
4307 13:58:43.089881 7, 0xFFFF, sum = 0
4308 13:58:43.089963 8, 0x0, sum = 1
4309 13:58:43.092893 9, 0x0, sum = 2
4310 13:58:43.092975 10, 0x0, sum = 3
4311 13:58:43.096313 11, 0x0, sum = 4
4312 13:58:43.096395 best_step = 9
4313 13:58:43.096459
4314 13:58:43.096518 ==
4315 13:58:43.099987 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 13:58:43.106108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 13:58:43.106190 ==
4318 13:58:43.106255 RX Vref Scan: 0
4319 13:58:43.106314
4320 13:58:43.109400 RX Vref 0 -> 0, step: 1
4321 13:58:43.109481
4322 13:58:43.112683 RX Delay -195 -> 252, step: 8
4323 13:58:43.115956 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4324 13:58:43.122564 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4325 13:58:43.125981 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4326 13:58:43.129445 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4327 13:58:43.133089 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4328 13:58:43.135959 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4329 13:58:43.142725 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4330 13:58:43.146173 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4331 13:58:43.149417 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4332 13:58:43.152661 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4333 13:58:43.159251 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4334 13:58:43.163226 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4335 13:58:43.165982 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4336 13:58:43.169794 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4337 13:58:43.176427 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4338 13:58:43.179463 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4339 13:58:43.179545 ==
4340 13:58:43.182633 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 13:58:43.186333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 13:58:43.186429 ==
4343 13:58:43.186494 DQS Delay:
4344 13:58:43.189596 DQS0 = 0, DQS1 = 0
4345 13:58:43.189677 DQM Delay:
4346 13:58:43.192981 DQM0 = 40, DQM1 = 33
4347 13:58:43.193078 DQ Delay:
4348 13:58:43.195915 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4349 13:58:43.199285 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4350 13:58:43.202646 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =20
4351 13:58:43.206016 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4352 13:58:43.206098
4353 13:58:43.206163
4354 13:58:43.215933 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4355 13:58:43.216017 CH0 RK1: MR19=808, MR18=4E30
4356 13:58:43.222744 CH0_RK1: MR19=0x808, MR18=0x4E30, DQSOSC=395, MR23=63, INC=168, DEC=112
4357 13:58:43.226292 [RxdqsGatingPostProcess] freq 600
4358 13:58:43.232492 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4359 13:58:43.236033 Pre-setting of DQS Precalculation
4360 13:58:43.239315 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4361 13:58:43.239412 ==
4362 13:58:43.242782 Dram Type= 6, Freq= 0, CH_1, rank 0
4363 13:58:43.245757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 13:58:43.245839 ==
4365 13:58:43.252656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 13:58:43.259036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4367 13:58:43.262485 [CA 0] Center 35 (5~66) winsize 62
4368 13:58:43.265783 [CA 1] Center 35 (5~66) winsize 62
4369 13:58:43.269549 [CA 2] Center 34 (4~64) winsize 61
4370 13:58:43.272449 [CA 3] Center 33 (3~64) winsize 62
4371 13:58:43.275957 [CA 4] Center 33 (3~64) winsize 62
4372 13:58:43.279237 [CA 5] Center 33 (3~64) winsize 62
4373 13:58:43.279318
4374 13:58:43.282345 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4375 13:58:43.282426
4376 13:58:43.285715 [CATrainingPosCal] consider 1 rank data
4377 13:58:43.289033 u2DelayCellTimex100 = 270/100 ps
4378 13:58:43.292383 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4379 13:58:43.295979 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4380 13:58:43.299461 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4381 13:58:43.302593 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4382 13:58:43.305675 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 13:58:43.312364 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4384 13:58:43.312445
4385 13:58:43.315814 CA PerBit enable=1, Macro0, CA PI delay=33
4386 13:58:43.315895
4387 13:58:43.319202 [CBTSetCACLKResult] CA Dly = 33
4388 13:58:43.319283 CS Dly: 6 (0~37)
4389 13:58:43.319347 ==
4390 13:58:43.322465 Dram Type= 6, Freq= 0, CH_1, rank 1
4391 13:58:43.326048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 13:58:43.329335 ==
4393 13:58:43.332502 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 13:58:43.339444 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4395 13:58:43.342543 [CA 0] Center 35 (5~66) winsize 62
4396 13:58:43.345941 [CA 1] Center 36 (6~66) winsize 61
4397 13:58:43.349371 [CA 2] Center 34 (3~65) winsize 63
4398 13:58:43.352429 [CA 3] Center 33 (3~64) winsize 62
4399 13:58:43.355808 [CA 4] Center 34 (3~65) winsize 63
4400 13:58:43.359090 [CA 5] Center 33 (3~64) winsize 62
4401 13:58:43.359171
4402 13:58:43.362394 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4403 13:58:43.362475
4404 13:58:43.365994 [CATrainingPosCal] consider 2 rank data
4405 13:58:43.369218 u2DelayCellTimex100 = 270/100 ps
4406 13:58:43.372397 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4407 13:58:43.375926 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4408 13:58:43.379201 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4409 13:58:43.382858 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4410 13:58:43.386073 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 13:58:43.392387 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 13:58:43.392468
4413 13:58:43.395732 CA PerBit enable=1, Macro0, CA PI delay=33
4414 13:58:43.395857
4415 13:58:43.399377 [CBTSetCACLKResult] CA Dly = 33
4416 13:58:43.399458 CS Dly: 6 (0~37)
4417 13:58:43.399526
4418 13:58:43.402632 ----->DramcWriteLeveling(PI) begin...
4419 13:58:43.402714 ==
4420 13:58:43.406127 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 13:58:43.409634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 13:58:43.413184 ==
4423 13:58:43.413264 Write leveling (Byte 0): 28 => 28
4424 13:58:43.415774 Write leveling (Byte 1): 31 => 31
4425 13:58:43.419312 DramcWriteLeveling(PI) end<-----
4426 13:58:43.419393
4427 13:58:43.419458 ==
4428 13:58:43.422611 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 13:58:43.429060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 13:58:43.429140 ==
4431 13:58:43.429205 [Gating] SW mode calibration
4432 13:58:43.439275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4433 13:58:43.442690 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4434 13:58:43.446075 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4435 13:58:43.453200 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 13:58:43.455977 0 9 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4437 13:58:43.459416 0 9 12 | B1->B0 | 3535 3333 | 0 1 | (0 0) (1 1)
4438 13:58:43.466160 0 9 16 | B1->B0 | 2727 2828 | 0 0 | (0 0) (1 0)
4439 13:58:43.469826 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 13:58:43.472744 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 13:58:43.479364 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4442 13:58:43.482615 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 13:58:43.486511 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 13:58:43.492876 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 13:58:43.496161 0 10 12 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (0 0)
4446 13:58:43.499435 0 10 16 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
4447 13:58:43.506151 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 13:58:43.509500 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 13:58:43.512854 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 13:58:43.519524 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 13:58:43.523026 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 13:58:43.526280 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 13:58:43.529585 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4454 13:58:43.536888 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4455 13:58:43.540077 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 13:58:43.543105 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 13:58:43.549940 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 13:58:43.553437 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 13:58:43.556614 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 13:58:43.562968 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 13:58:43.566342 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 13:58:43.569681 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 13:58:43.576766 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 13:58:43.580717 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 13:58:43.583170 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 13:58:43.589922 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 13:58:43.593722 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 13:58:43.596396 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 13:58:43.599695 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4470 13:58:43.606370 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 13:58:43.610056 Total UI for P1: 0, mck2ui 16
4472 13:58:43.613184 best dqsien dly found for B0: ( 0, 13, 14)
4473 13:58:43.616471 Total UI for P1: 0, mck2ui 16
4474 13:58:43.620091 best dqsien dly found for B1: ( 0, 13, 12)
4475 13:58:43.623113 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4476 13:58:43.627020 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4477 13:58:43.627101
4478 13:58:43.629964 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4479 13:58:43.633520 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4480 13:58:43.636955 [Gating] SW calibration Done
4481 13:58:43.637040 ==
4482 13:58:43.640216 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 13:58:43.643695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 13:58:43.643776 ==
4485 13:58:43.646868 RX Vref Scan: 0
4486 13:58:43.646948
4487 13:58:43.647013 RX Vref 0 -> 0, step: 1
4488 13:58:43.647073
4489 13:58:43.650107 RX Delay -230 -> 252, step: 16
4490 13:58:43.657146 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4491 13:58:43.659866 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4492 13:58:43.663166 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4493 13:58:43.666560 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4494 13:58:43.669896 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4495 13:58:43.676826 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4496 13:58:43.680107 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4497 13:58:43.683243 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4498 13:58:43.686865 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4499 13:58:43.689834 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4500 13:58:43.696872 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4501 13:58:43.700039 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4502 13:58:43.703522 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4503 13:58:43.706664 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4504 13:58:43.713311 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4505 13:58:43.716657 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4506 13:58:43.716731 ==
4507 13:58:43.720453 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 13:58:43.723432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 13:58:43.723514 ==
4510 13:58:43.727171 DQS Delay:
4511 13:58:43.727251 DQS0 = 0, DQS1 = 0
4512 13:58:43.727315 DQM Delay:
4513 13:58:43.730327 DQM0 = 44, DQM1 = 34
4514 13:58:43.730408 DQ Delay:
4515 13:58:43.733440 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4516 13:58:43.736680 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4517 13:58:43.740201 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4518 13:58:43.743573 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4519 13:58:43.743654
4520 13:58:43.743718
4521 13:58:43.743778 ==
4522 13:58:43.747027 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 13:58:43.753720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 13:58:43.753801 ==
4525 13:58:43.753866
4526 13:58:43.753925
4527 13:58:43.753983 TX Vref Scan disable
4528 13:58:43.757219 == TX Byte 0 ==
4529 13:58:43.760271 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4530 13:58:43.763818 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4531 13:58:43.767098 == TX Byte 1 ==
4532 13:58:43.770558 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4533 13:58:43.774082 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4534 13:58:43.777565 ==
4535 13:58:43.781007 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 13:58:43.783654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 13:58:43.783735 ==
4538 13:58:43.783799
4539 13:58:43.783858
4540 13:58:43.786982 TX Vref Scan disable
4541 13:58:43.787085 == TX Byte 0 ==
4542 13:58:43.793770 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4543 13:58:43.797231 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4544 13:58:43.797342 == TX Byte 1 ==
4545 13:58:43.803715 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 13:58:43.806990 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 13:58:43.807074
4548 13:58:43.807138 [DATLAT]
4549 13:58:43.810699 Freq=600, CH1 RK0
4550 13:58:43.810804
4551 13:58:43.810869 DATLAT Default: 0x9
4552 13:58:43.813783 0, 0xFFFF, sum = 0
4553 13:58:43.813866 1, 0xFFFF, sum = 0
4554 13:58:43.817564 2, 0xFFFF, sum = 0
4555 13:58:43.817647 3, 0xFFFF, sum = 0
4556 13:58:43.820736 4, 0xFFFF, sum = 0
4557 13:58:43.820819 5, 0xFFFF, sum = 0
4558 13:58:43.823892 6, 0xFFFF, sum = 0
4559 13:58:43.827238 7, 0xFFFF, sum = 0
4560 13:58:43.827321 8, 0x0, sum = 1
4561 13:58:43.827387 9, 0x0, sum = 2
4562 13:58:43.830478 10, 0x0, sum = 3
4563 13:58:43.830560 11, 0x0, sum = 4
4564 13:58:43.833617 best_step = 9
4565 13:58:43.833697
4566 13:58:43.833761 ==
4567 13:58:43.836986 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 13:58:43.840279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 13:58:43.840360 ==
4570 13:58:43.843745 RX Vref Scan: 1
4571 13:58:43.843825
4572 13:58:43.843889 RX Vref 0 -> 0, step: 1
4573 13:58:43.843949
4574 13:58:43.847291 RX Delay -195 -> 252, step: 8
4575 13:58:43.847372
4576 13:58:43.850619 Set Vref, RX VrefLevel [Byte0]: 58
4577 13:58:43.853519 [Byte1]: 54
4578 13:58:43.857693
4579 13:58:43.857773 Final RX Vref Byte 0 = 58 to rank0
4580 13:58:43.861349 Final RX Vref Byte 1 = 54 to rank0
4581 13:58:43.864369 Final RX Vref Byte 0 = 58 to rank1
4582 13:58:43.867778 Final RX Vref Byte 1 = 54 to rank1==
4583 13:58:43.870833 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 13:58:43.874461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 13:58:43.877729 ==
4586 13:58:43.877811 DQS Delay:
4587 13:58:43.877876 DQS0 = 0, DQS1 = 0
4588 13:58:43.880996 DQM Delay:
4589 13:58:43.881078 DQM0 = 41, DQM1 = 32
4590 13:58:43.884462 DQ Delay:
4591 13:58:43.884544 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4592 13:58:43.887858 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4593 13:58:43.891179 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4594 13:58:43.894455 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4595 13:58:43.894537
4596 13:58:43.898282
4597 13:58:43.904182 [DQSOSCAuto] RK0, (LSB)MR18= 0x460b, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4598 13:58:43.907680 CH1 RK0: MR19=808, MR18=460B
4599 13:58:43.914292 CH1_RK0: MR19=0x808, MR18=0x460B, DQSOSC=396, MR23=63, INC=167, DEC=111
4600 13:58:43.914375
4601 13:58:43.917633 ----->DramcWriteLeveling(PI) begin...
4602 13:58:43.917716 ==
4603 13:58:43.921085 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 13:58:43.924552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 13:58:43.924634 ==
4606 13:58:43.927520 Write leveling (Byte 0): 31 => 31
4607 13:58:43.931045 Write leveling (Byte 1): 31 => 31
4608 13:58:43.933980 DramcWriteLeveling(PI) end<-----
4609 13:58:43.934062
4610 13:58:43.934127 ==
4611 13:58:43.937941 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 13:58:43.940910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 13:58:43.940992 ==
4614 13:58:43.944328 [Gating] SW mode calibration
4615 13:58:43.950924 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4616 13:58:43.957650 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4617 13:58:43.961296 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 13:58:43.964182 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 13:58:43.970835 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4620 13:58:43.974050 0 9 12 | B1->B0 | 2f2f 2b2b | 0 0 | (1 0) (0 0)
4621 13:58:43.977687 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4622 13:58:43.984111 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 13:58:43.988038 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 13:58:43.991240 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4625 13:58:43.997678 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 13:58:44.000676 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 13:58:44.004222 0 10 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (1 1)
4628 13:58:44.010506 0 10 12 | B1->B0 | 3030 4141 | 0 0 | (0 0) (0 0)
4629 13:58:44.013875 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4630 13:58:44.017246 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 13:58:44.023921 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 13:58:44.027643 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 13:58:44.030597 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 13:58:44.036966 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 13:58:44.040449 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4636 13:58:44.044522 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4637 13:58:44.050632 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 13:58:44.054170 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 13:58:44.057213 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 13:58:44.060582 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 13:58:44.067769 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 13:58:44.070905 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 13:58:44.074258 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 13:58:44.080479 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 13:58:44.084002 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 13:58:44.087247 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 13:58:44.093978 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 13:58:44.097723 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 13:58:44.100886 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 13:58:44.107788 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 13:58:44.110865 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 13:58:44.113865 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4653 13:58:44.117728 Total UI for P1: 0, mck2ui 16
4654 13:58:44.121207 best dqsien dly found for B0: ( 0, 13, 10)
4655 13:58:44.124100 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 13:58:44.127304 Total UI for P1: 0, mck2ui 16
4657 13:58:44.130610 best dqsien dly found for B1: ( 0, 13, 12)
4658 13:58:44.137653 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4659 13:58:44.140787 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4660 13:58:44.140869
4661 13:58:44.144172 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4662 13:58:44.147515 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4663 13:58:44.150886 [Gating] SW calibration Done
4664 13:58:44.150993 ==
4665 13:58:44.154479 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 13:58:44.157902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 13:58:44.158010 ==
4668 13:58:44.158103 RX Vref Scan: 0
4669 13:58:44.161026
4670 13:58:44.161107 RX Vref 0 -> 0, step: 1
4671 13:58:44.161173
4672 13:58:44.164499 RX Delay -230 -> 252, step: 16
4673 13:58:44.167554 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4674 13:58:44.174184 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4675 13:58:44.177582 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4676 13:58:44.181281 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4677 13:58:44.184547 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4678 13:58:44.187632 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4679 13:58:44.194241 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4680 13:58:44.197497 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4681 13:58:44.201135 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4682 13:58:44.204166 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4683 13:58:44.210880 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4684 13:58:44.214354 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4685 13:58:44.218034 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4686 13:58:44.221031 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4687 13:58:44.224183 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4688 13:58:44.231372 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4689 13:58:44.231459 ==
4690 13:58:44.234735 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 13:58:44.237526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 13:58:44.237658 ==
4693 13:58:44.237756 DQS Delay:
4694 13:58:44.241405 DQS0 = 0, DQS1 = 0
4695 13:58:44.241487 DQM Delay:
4696 13:58:44.244597 DQM0 = 41, DQM1 = 38
4697 13:58:44.244680 DQ Delay:
4698 13:58:44.247806 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4699 13:58:44.251190 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4700 13:58:44.255034 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4701 13:58:44.257698 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4702 13:58:44.257781
4703 13:58:44.257847
4704 13:58:44.257909 ==
4705 13:58:44.260861 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 13:58:44.264665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 13:58:44.264810 ==
4708 13:58:44.264879
4709 13:58:44.268146
4710 13:58:44.268228 TX Vref Scan disable
4711 13:58:44.271453 == TX Byte 0 ==
4712 13:58:44.274330 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4713 13:58:44.277985 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4714 13:58:44.281395 == TX Byte 1 ==
4715 13:58:44.284590 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4716 13:58:44.288138 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4717 13:58:44.288221 ==
4718 13:58:44.291621 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 13:58:44.298308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 13:58:44.298391 ==
4721 13:58:44.298456
4722 13:58:44.298516
4723 13:58:44.298574 TX Vref Scan disable
4724 13:58:44.302125 == TX Byte 0 ==
4725 13:58:44.305576 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4726 13:58:44.309092 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4727 13:58:44.312023 == TX Byte 1 ==
4728 13:58:44.315679 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4729 13:58:44.322547 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4730 13:58:44.322630
4731 13:58:44.322695 [DATLAT]
4732 13:58:44.322795 Freq=600, CH1 RK1
4733 13:58:44.322855
4734 13:58:44.326024 DATLAT Default: 0x9
4735 13:58:44.326105 0, 0xFFFF, sum = 0
4736 13:58:44.328679 1, 0xFFFF, sum = 0
4737 13:58:44.328780 2, 0xFFFF, sum = 0
4738 13:58:44.332095 3, 0xFFFF, sum = 0
4739 13:58:44.332179 4, 0xFFFF, sum = 0
4740 13:58:44.335674 5, 0xFFFF, sum = 0
4741 13:58:44.338761 6, 0xFFFF, sum = 0
4742 13:58:44.338845 7, 0xFFFF, sum = 0
4743 13:58:44.338911 8, 0x0, sum = 1
4744 13:58:44.342030 9, 0x0, sum = 2
4745 13:58:44.342114 10, 0x0, sum = 3
4746 13:58:44.345758 11, 0x0, sum = 4
4747 13:58:44.345915 best_step = 9
4748 13:58:44.346079
4749 13:58:44.346160 ==
4750 13:58:44.349361 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 13:58:44.355689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 13:58:44.355772 ==
4753 13:58:44.355837 RX Vref Scan: 0
4754 13:58:44.355898
4755 13:58:44.358808 RX Vref 0 -> 0, step: 1
4756 13:58:44.358890
4757 13:58:44.362253 RX Delay -179 -> 252, step: 8
4758 13:58:44.365640 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4759 13:58:44.368818 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4760 13:58:44.375839 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4761 13:58:44.379094 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4762 13:58:44.382230 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4763 13:58:44.386023 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4764 13:58:44.392054 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4765 13:58:44.396022 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4766 13:58:44.398940 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4767 13:58:44.402249 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4768 13:58:44.406028 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4769 13:58:44.412397 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4770 13:58:44.416298 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4771 13:58:44.419422 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4772 13:58:44.422454 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4773 13:58:44.428948 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4774 13:58:44.429030 ==
4775 13:58:44.432433 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 13:58:44.435791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 13:58:44.435874 ==
4778 13:58:44.435940 DQS Delay:
4779 13:58:44.439287 DQS0 = 0, DQS1 = 0
4780 13:58:44.439368 DQM Delay:
4781 13:58:44.442872 DQM0 = 38, DQM1 = 34
4782 13:58:44.442971 DQ Delay:
4783 13:58:44.445840 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4784 13:58:44.449255 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4785 13:58:44.452502 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4786 13:58:44.455869 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4787 13:58:44.455989
4788 13:58:44.456053
4789 13:58:44.462646 [DQSOSCAuto] RK1, (LSB)MR18= 0x3746, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4790 13:58:44.465762 CH1 RK1: MR19=808, MR18=3746
4791 13:58:44.472385 CH1_RK1: MR19=0x808, MR18=0x3746, DQSOSC=396, MR23=63, INC=167, DEC=111
4792 13:58:44.476444 [RxdqsGatingPostProcess] freq 600
4793 13:58:44.482510 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4794 13:58:44.486099 Pre-setting of DQS Precalculation
4795 13:58:44.489383 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4796 13:58:44.496246 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4797 13:58:44.503135 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4798 13:58:44.503218
4799 13:58:44.503282
4800 13:58:44.505905 [Calibration Summary] 1200 Mbps
4801 13:58:44.509351 CH 0, Rank 0
4802 13:58:44.509473 SW Impedance : PASS
4803 13:58:44.512337 DUTY Scan : NO K
4804 13:58:44.516001 ZQ Calibration : PASS
4805 13:58:44.516084 Jitter Meter : NO K
4806 13:58:44.519074 CBT Training : PASS
4807 13:58:44.519156 Write leveling : PASS
4808 13:58:44.522546 RX DQS gating : PASS
4809 13:58:44.526028 RX DQ/DQS(RDDQC) : PASS
4810 13:58:44.526128 TX DQ/DQS : PASS
4811 13:58:44.529810 RX DATLAT : PASS
4812 13:58:44.532682 RX DQ/DQS(Engine): PASS
4813 13:58:44.532763 TX OE : NO K
4814 13:58:44.536155 All Pass.
4815 13:58:44.536237
4816 13:58:44.536303 CH 0, Rank 1
4817 13:58:44.539368 SW Impedance : PASS
4818 13:58:44.539449 DUTY Scan : NO K
4819 13:58:44.542799 ZQ Calibration : PASS
4820 13:58:44.546368 Jitter Meter : NO K
4821 13:58:44.546476 CBT Training : PASS
4822 13:58:44.549229 Write leveling : PASS
4823 13:58:44.552671 RX DQS gating : PASS
4824 13:58:44.552752 RX DQ/DQS(RDDQC) : PASS
4825 13:58:44.556188 TX DQ/DQS : PASS
4826 13:58:44.556270 RX DATLAT : PASS
4827 13:58:44.559553 RX DQ/DQS(Engine): PASS
4828 13:58:44.562602 TX OE : NO K
4829 13:58:44.562710 All Pass.
4830 13:58:44.562789
4831 13:58:44.562851 CH 1, Rank 0
4832 13:58:44.566167 SW Impedance : PASS
4833 13:58:44.569814 DUTY Scan : NO K
4834 13:58:44.569896 ZQ Calibration : PASS
4835 13:58:44.573143 Jitter Meter : NO K
4836 13:58:44.576251 CBT Training : PASS
4837 13:58:44.576333 Write leveling : PASS
4838 13:58:44.579558 RX DQS gating : PASS
4839 13:58:44.582861 RX DQ/DQS(RDDQC) : PASS
4840 13:58:44.582957 TX DQ/DQS : PASS
4841 13:58:44.586342 RX DATLAT : PASS
4842 13:58:44.589410 RX DQ/DQS(Engine): PASS
4843 13:58:44.589492 TX OE : NO K
4844 13:58:44.589557 All Pass.
4845 13:58:44.592814
4846 13:58:44.592896 CH 1, Rank 1
4847 13:58:44.596241 SW Impedance : PASS
4848 13:58:44.596323 DUTY Scan : NO K
4849 13:58:44.599702 ZQ Calibration : PASS
4850 13:58:44.599784 Jitter Meter : NO K
4851 13:58:44.602642 CBT Training : PASS
4852 13:58:44.606239 Write leveling : PASS
4853 13:58:44.606321 RX DQS gating : PASS
4854 13:58:44.609386 RX DQ/DQS(RDDQC) : PASS
4855 13:58:44.613215 TX DQ/DQS : PASS
4856 13:58:44.613297 RX DATLAT : PASS
4857 13:58:44.616424 RX DQ/DQS(Engine): PASS
4858 13:58:44.619679 TX OE : NO K
4859 13:58:44.619763 All Pass.
4860 13:58:44.619828
4861 13:58:44.619889 DramC Write-DBI off
4862 13:58:44.623372 PER_BANK_REFRESH: Hybrid Mode
4863 13:58:44.626165 TX_TRACKING: ON
4864 13:58:44.632902 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4865 13:58:44.636557 [FAST_K] Save calibration result to emmc
4866 13:58:44.643317 dramc_set_vcore_voltage set vcore to 662500
4867 13:58:44.643399 Read voltage for 933, 3
4868 13:58:44.643465 Vio18 = 0
4869 13:58:44.646177 Vcore = 662500
4870 13:58:44.646259 Vdram = 0
4871 13:58:44.646324 Vddq = 0
4872 13:58:44.649637 Vmddr = 0
4873 13:58:44.653164 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4874 13:58:44.659988 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4875 13:58:44.660086 MEM_TYPE=3, freq_sel=17
4876 13:58:44.663052 sv_algorithm_assistance_LP4_1600
4877 13:58:44.670113 ============ PULL DRAM RESETB DOWN ============
4878 13:58:44.673028 ========== PULL DRAM RESETB DOWN end =========
4879 13:58:44.676820 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4880 13:58:44.679601 ===================================
4881 13:58:44.683072 LPDDR4 DRAM CONFIGURATION
4882 13:58:44.686546 ===================================
4883 13:58:44.689834 EX_ROW_EN[0] = 0x0
4884 13:58:44.689956 EX_ROW_EN[1] = 0x0
4885 13:58:44.693113 LP4Y_EN = 0x0
4886 13:58:44.693196 WORK_FSP = 0x0
4887 13:58:44.696502 WL = 0x3
4888 13:58:44.696598 RL = 0x3
4889 13:58:44.699880 BL = 0x2
4890 13:58:44.699962 RPST = 0x0
4891 13:58:44.703072 RD_PRE = 0x0
4892 13:58:44.703170 WR_PRE = 0x1
4893 13:58:44.706371 WR_PST = 0x0
4894 13:58:44.706503 DBI_WR = 0x0
4895 13:58:44.709809 DBI_RD = 0x0
4896 13:58:44.709910 OTF = 0x1
4897 13:58:44.713178 ===================================
4898 13:58:44.716331 ===================================
4899 13:58:44.720399 ANA top config
4900 13:58:44.723306 ===================================
4901 13:58:44.723409 DLL_ASYNC_EN = 0
4902 13:58:44.726281 ALL_SLAVE_EN = 1
4903 13:58:44.729628 NEW_RANK_MODE = 1
4904 13:58:44.732916 DLL_IDLE_MODE = 1
4905 13:58:44.736509 LP45_APHY_COMB_EN = 1
4906 13:58:44.736622 TX_ODT_DIS = 1
4907 13:58:44.739553 NEW_8X_MODE = 1
4908 13:58:44.743032 ===================================
4909 13:58:44.746633 ===================================
4910 13:58:44.749732 data_rate = 1866
4911 13:58:44.752849 CKR = 1
4912 13:58:44.756671 DQ_P2S_RATIO = 8
4913 13:58:44.759849 ===================================
4914 13:58:44.759980 CA_P2S_RATIO = 8
4915 13:58:44.762891 DQ_CA_OPEN = 0
4916 13:58:44.766526 DQ_SEMI_OPEN = 0
4917 13:58:44.770062 CA_SEMI_OPEN = 0
4918 13:58:44.773274 CA_FULL_RATE = 0
4919 13:58:44.776601 DQ_CKDIV4_EN = 1
4920 13:58:44.776697 CA_CKDIV4_EN = 1
4921 13:58:44.779849 CA_PREDIV_EN = 0
4922 13:58:44.783070 PH8_DLY = 0
4923 13:58:44.786444 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4924 13:58:44.789772 DQ_AAMCK_DIV = 4
4925 13:58:44.793177 CA_AAMCK_DIV = 4
4926 13:58:44.793261 CA_ADMCK_DIV = 4
4927 13:58:44.796535 DQ_TRACK_CA_EN = 0
4928 13:58:44.799650 CA_PICK = 933
4929 13:58:44.803463 CA_MCKIO = 933
4930 13:58:44.806336 MCKIO_SEMI = 0
4931 13:58:44.810371 PLL_FREQ = 3732
4932 13:58:44.813110 DQ_UI_PI_RATIO = 32
4933 13:58:44.813192 CA_UI_PI_RATIO = 0
4934 13:58:44.816476 ===================================
4935 13:58:44.819527 ===================================
4936 13:58:44.823084 memory_type:LPDDR4
4937 13:58:44.826358 GP_NUM : 10
4938 13:58:44.826440 SRAM_EN : 1
4939 13:58:44.829765 MD32_EN : 0
4940 13:58:44.833037 ===================================
4941 13:58:44.836621 [ANA_INIT] >>>>>>>>>>>>>>
4942 13:58:44.836718 <<<<<< [CONFIGURE PHASE]: ANA_TX
4943 13:58:44.843194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4944 13:58:44.846415 ===================================
4945 13:58:44.846497 data_rate = 1866,PCW = 0X8f00
4946 13:58:44.849870 ===================================
4947 13:58:44.853139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4948 13:58:44.860128 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 13:58:44.866602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 13:58:44.869760 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4951 13:58:44.873274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4952 13:58:44.876815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4953 13:58:44.879812 [ANA_INIT] flow start
4954 13:58:44.879894 [ANA_INIT] PLL >>>>>>>>
4955 13:58:44.883010 [ANA_INIT] PLL <<<<<<<<
4956 13:58:44.886510 [ANA_INIT] MIDPI >>>>>>>>
4957 13:58:44.886592 [ANA_INIT] MIDPI <<<<<<<<
4958 13:58:44.890082 [ANA_INIT] DLL >>>>>>>>
4959 13:58:44.893194 [ANA_INIT] flow end
4960 13:58:44.896682 ============ LP4 DIFF to SE enter ============
4961 13:58:44.900241 ============ LP4 DIFF to SE exit ============
4962 13:58:44.903450 [ANA_INIT] <<<<<<<<<<<<<
4963 13:58:44.906596 [Flow] Enable top DCM control >>>>>
4964 13:58:44.910483 [Flow] Enable top DCM control <<<<<
4965 13:58:44.913221 Enable DLL master slave shuffle
4966 13:58:44.916728 ==============================================================
4967 13:58:44.919806 Gating Mode config
4968 13:58:44.927024 ==============================================================
4969 13:58:44.927107 Config description:
4970 13:58:44.936732 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4971 13:58:44.943740 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4972 13:58:44.946808 SELPH_MODE 0: By rank 1: By Phase
4973 13:58:44.953745 ==============================================================
4974 13:58:44.956856 GAT_TRACK_EN = 1
4975 13:58:44.959833 RX_GATING_MODE = 2
4976 13:58:44.963580 RX_GATING_TRACK_MODE = 2
4977 13:58:44.967120 SELPH_MODE = 1
4978 13:58:44.970112 PICG_EARLY_EN = 1
4979 13:58:44.970194 VALID_LAT_VALUE = 1
4980 13:58:44.976991 ==============================================================
4981 13:58:44.980344 Enter into Gating configuration >>>>
4982 13:58:44.983419 Exit from Gating configuration <<<<
4983 13:58:44.987166 Enter into DVFS_PRE_config >>>>>
4984 13:58:44.997601 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4985 13:58:45.000358 Exit from DVFS_PRE_config <<<<<
4986 13:58:45.004121 Enter into PICG configuration >>>>
4987 13:58:45.007195 Exit from PICG configuration <<<<
4988 13:58:45.010767 [RX_INPUT] configuration >>>>>
4989 13:58:45.013916 [RX_INPUT] configuration <<<<<
4990 13:58:45.017630 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4991 13:58:45.023986 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4992 13:58:45.030423 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 13:58:45.037239 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 13:58:45.040481 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4995 13:58:45.047114 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4996 13:58:45.051357 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4997 13:58:45.057189 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4998 13:58:45.060586 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4999 13:58:45.064421 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5000 13:58:45.067129 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5001 13:58:45.073728 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 13:58:45.077598 ===================================
5003 13:58:45.077680 LPDDR4 DRAM CONFIGURATION
5004 13:58:45.080893 ===================================
5005 13:58:45.083927 EX_ROW_EN[0] = 0x0
5006 13:58:45.087146 EX_ROW_EN[1] = 0x0
5007 13:58:45.087228 LP4Y_EN = 0x0
5008 13:58:45.090860 WORK_FSP = 0x0
5009 13:58:45.091012 WL = 0x3
5010 13:58:45.094071 RL = 0x3
5011 13:58:45.094155 BL = 0x2
5012 13:58:45.097175 RPST = 0x0
5013 13:58:45.097258 RD_PRE = 0x0
5014 13:58:45.100513 WR_PRE = 0x1
5015 13:58:45.100595 WR_PST = 0x0
5016 13:58:45.103810 DBI_WR = 0x0
5017 13:58:45.103892 DBI_RD = 0x0
5018 13:58:45.107616 OTF = 0x1
5019 13:58:45.110801 ===================================
5020 13:58:45.114056 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5021 13:58:45.117573 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5022 13:58:45.123995 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5023 13:58:45.127387 ===================================
5024 13:58:45.127469 LPDDR4 DRAM CONFIGURATION
5025 13:58:45.131255 ===================================
5026 13:58:45.134485 EX_ROW_EN[0] = 0x10
5027 13:58:45.134567 EX_ROW_EN[1] = 0x0
5028 13:58:45.137498 LP4Y_EN = 0x0
5029 13:58:45.137579 WORK_FSP = 0x0
5030 13:58:45.140922 WL = 0x3
5031 13:58:45.143989 RL = 0x3
5032 13:58:45.144097 BL = 0x2
5033 13:58:45.147464 RPST = 0x0
5034 13:58:45.147545 RD_PRE = 0x0
5035 13:58:45.151137 WR_PRE = 0x1
5036 13:58:45.151219 WR_PST = 0x0
5037 13:58:45.154462 DBI_WR = 0x0
5038 13:58:45.154543 DBI_RD = 0x0
5039 13:58:45.157415 OTF = 0x1
5040 13:58:45.161049 ===================================
5041 13:58:45.164622 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5042 13:58:45.169494 nWR fixed to 30
5043 13:58:45.172725 [ModeRegInit_LP4] CH0 RK0
5044 13:58:45.172829 [ModeRegInit_LP4] CH0 RK1
5045 13:58:45.175989 [ModeRegInit_LP4] CH1 RK0
5046 13:58:45.179541 [ModeRegInit_LP4] CH1 RK1
5047 13:58:45.179643 match AC timing 9
5048 13:58:45.186328 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5049 13:58:45.189422 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5050 13:58:45.192977 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5051 13:58:45.199708 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5052 13:58:45.202906 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5053 13:58:45.203070 ==
5054 13:58:45.206249 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 13:58:45.209543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5056 13:58:45.209625 ==
5057 13:58:45.215970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5058 13:58:45.223438 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5059 13:58:45.226104 [CA 0] Center 38 (8~69) winsize 62
5060 13:58:45.229956 [CA 1] Center 38 (8~69) winsize 62
5061 13:58:45.233134 [CA 2] Center 35 (5~66) winsize 62
5062 13:58:45.236165 [CA 3] Center 35 (4~66) winsize 63
5063 13:58:45.240022 [CA 4] Center 34 (4~64) winsize 61
5064 13:58:45.242816 [CA 5] Center 34 (4~64) winsize 61
5065 13:58:45.242898
5066 13:58:45.246109 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5067 13:58:45.246191
5068 13:58:45.249664 [CATrainingPosCal] consider 1 rank data
5069 13:58:45.252816 u2DelayCellTimex100 = 270/100 ps
5070 13:58:45.256645 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5071 13:58:45.259621 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5072 13:58:45.262857 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5073 13:58:45.266577 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5074 13:58:45.269780 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5075 13:58:45.272965 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5076 13:58:45.273047
5077 13:58:45.276686 CA PerBit enable=1, Macro0, CA PI delay=34
5078 13:58:45.279544
5079 13:58:45.279625 [CBTSetCACLKResult] CA Dly = 34
5080 13:58:45.283130 CS Dly: 6 (0~37)
5081 13:58:45.283227 ==
5082 13:58:45.286624 Dram Type= 6, Freq= 0, CH_0, rank 1
5083 13:58:45.289712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 13:58:45.289794 ==
5085 13:58:45.296468 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5086 13:58:45.303608 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5087 13:58:45.306395 [CA 0] Center 38 (8~69) winsize 62
5088 13:58:45.309820 [CA 1] Center 38 (8~69) winsize 62
5089 13:58:45.313154 [CA 2] Center 35 (5~66) winsize 62
5090 13:58:45.316583 [CA 3] Center 35 (4~66) winsize 63
5091 13:58:45.320194 [CA 4] Center 33 (3~64) winsize 62
5092 13:58:45.320291 [CA 5] Center 33 (3~64) winsize 62
5093 13:58:45.323514
5094 13:58:45.326784 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5095 13:58:45.326895
5096 13:58:45.330044 [CATrainingPosCal] consider 2 rank data
5097 13:58:45.333610 u2DelayCellTimex100 = 270/100 ps
5098 13:58:45.336700 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5099 13:58:45.340175 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5100 13:58:45.343403 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5101 13:58:45.346661 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5102 13:58:45.350048 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5103 13:58:45.353525 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5104 13:58:45.353614
5105 13:58:45.356754 CA PerBit enable=1, Macro0, CA PI delay=34
5106 13:58:45.356850
5107 13:58:45.359922 [CBTSetCACLKResult] CA Dly = 34
5108 13:58:45.363596 CS Dly: 7 (0~39)
5109 13:58:45.363678
5110 13:58:45.366695 ----->DramcWriteLeveling(PI) begin...
5111 13:58:45.366819 ==
5112 13:58:45.370270 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 13:58:45.373501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 13:58:45.373584 ==
5115 13:58:45.377389 Write leveling (Byte 0): 31 => 31
5116 13:58:45.380796 Write leveling (Byte 1): 29 => 29
5117 13:58:45.383372 DramcWriteLeveling(PI) end<-----
5118 13:58:45.383453
5119 13:58:45.383518 ==
5120 13:58:45.386850 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 13:58:45.390354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 13:58:45.390436 ==
5123 13:58:45.394068 [Gating] SW mode calibration
5124 13:58:45.400066 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5125 13:58:45.406780 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5126 13:58:45.409984 0 14 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5127 13:58:45.413333 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
5128 13:58:45.420256 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 13:58:45.423405 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 13:58:45.426797 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 13:58:45.433627 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 13:58:45.436829 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 13:58:45.440472 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5134 13:58:45.446851 0 15 0 | B1->B0 | 2f2f 2525 | 1 0 | (1 1) (0 0)
5135 13:58:45.450474 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5136 13:58:45.453734 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 13:58:45.460326 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 13:58:45.463724 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 13:58:45.467442 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 13:58:45.473561 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 13:58:45.477194 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 13:58:45.480105 1 0 0 | B1->B0 | 3333 3f3f | 1 1 | (0 0) (0 0)
5143 13:58:45.483579 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5144 13:58:45.490715 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 13:58:45.493634 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 13:58:45.497098 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 13:58:45.503534 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 13:58:45.507088 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 13:58:45.510429 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5150 13:58:45.517415 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5151 13:58:45.520599 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5152 13:58:45.523851 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 13:58:45.530330 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 13:58:45.533830 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 13:58:45.537281 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 13:58:45.544044 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 13:58:45.547448 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 13:58:45.550862 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 13:58:45.554102 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 13:58:45.560813 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 13:58:45.563861 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 13:58:45.567196 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 13:58:45.573745 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 13:58:45.577585 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 13:58:45.580538 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5166 13:58:45.587118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5167 13:58:45.590584 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5168 13:58:45.593868 Total UI for P1: 0, mck2ui 16
5169 13:58:45.597275 best dqsien dly found for B0: ( 1, 2, 30)
5170 13:58:45.600484 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 13:58:45.604217 Total UI for P1: 0, mck2ui 16
5172 13:58:45.607366 best dqsien dly found for B1: ( 1, 3, 0)
5173 13:58:45.610485 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5174 13:58:45.613816 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5175 13:58:45.613920
5176 13:58:45.621249 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5177 13:58:45.623858 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5178 13:58:45.623964 [Gating] SW calibration Done
5179 13:58:45.624061 ==
5180 13:58:45.627751 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 13:58:45.633753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 13:58:45.633838 ==
5183 13:58:45.633904 RX Vref Scan: 0
5184 13:58:45.633966
5185 13:58:45.637683 RX Vref 0 -> 0, step: 1
5186 13:58:45.637759
5187 13:58:45.640573 RX Delay -80 -> 252, step: 8
5188 13:58:45.643788 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5189 13:58:45.647257 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5190 13:58:45.650459 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5191 13:58:45.653930 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5192 13:58:45.660828 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5193 13:58:45.664035 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5194 13:58:45.667700 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5195 13:58:45.670477 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5196 13:58:45.674319 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5197 13:58:45.677655 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5198 13:58:45.684167 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5199 13:58:45.687251 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5200 13:58:45.690922 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5201 13:58:45.694205 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5202 13:58:45.697280 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5203 13:58:45.700948 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5204 13:58:45.704311 ==
5205 13:58:45.704389 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 13:58:45.711113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 13:58:45.711202 ==
5208 13:58:45.711288 DQS Delay:
5209 13:58:45.714380 DQS0 = 0, DQS1 = 0
5210 13:58:45.714481 DQM Delay:
5211 13:58:45.717541 DQM0 = 97, DQM1 = 87
5212 13:58:45.717644 DQ Delay:
5213 13:58:45.721096 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =95
5214 13:58:45.724557 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5215 13:58:45.727879 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5216 13:58:45.730816 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5217 13:58:45.730895
5218 13:58:45.730977
5219 13:58:45.731055 ==
5220 13:58:45.734099 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 13:58:45.737319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 13:58:45.737422 ==
5223 13:58:45.737524
5224 13:58:45.737623
5225 13:58:45.740761 TX Vref Scan disable
5226 13:58:45.744331 == TX Byte 0 ==
5227 13:58:45.747338 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5228 13:58:45.750654 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5229 13:58:45.754289 == TX Byte 1 ==
5230 13:58:45.757784 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5231 13:58:45.761153 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5232 13:58:45.761249 ==
5233 13:58:45.764224 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 13:58:45.767561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 13:58:45.770863 ==
5236 13:58:45.770939
5237 13:58:45.771021
5238 13:58:45.771098 TX Vref Scan disable
5239 13:58:45.774539 == TX Byte 0 ==
5240 13:58:45.777491 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5241 13:58:45.784317 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5242 13:58:45.784399 == TX Byte 1 ==
5243 13:58:45.787611 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5244 13:58:45.794262 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5245 13:58:45.794365
5246 13:58:45.794467 [DATLAT]
5247 13:58:45.794565 Freq=933, CH0 RK0
5248 13:58:45.794662
5249 13:58:45.797793 DATLAT Default: 0xd
5250 13:58:45.797897 0, 0xFFFF, sum = 0
5251 13:58:45.801221 1, 0xFFFF, sum = 0
5252 13:58:45.801332 2, 0xFFFF, sum = 0
5253 13:58:45.804299 3, 0xFFFF, sum = 0
5254 13:58:45.804377 4, 0xFFFF, sum = 0
5255 13:58:45.807509 5, 0xFFFF, sum = 0
5256 13:58:45.811014 6, 0xFFFF, sum = 0
5257 13:58:45.811087 7, 0xFFFF, sum = 0
5258 13:58:45.814232 8, 0xFFFF, sum = 0
5259 13:58:45.814334 9, 0xFFFF, sum = 0
5260 13:58:45.817651 10, 0x0, sum = 1
5261 13:58:45.817752 11, 0x0, sum = 2
5262 13:58:45.817844 12, 0x0, sum = 3
5263 13:58:45.820973 13, 0x0, sum = 4
5264 13:58:45.821076 best_step = 11
5265 13:58:45.821166
5266 13:58:45.821255 ==
5267 13:58:45.824345 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 13:58:45.830871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 13:58:45.830977 ==
5270 13:58:45.831073 RX Vref Scan: 1
5271 13:58:45.831163
5272 13:58:45.834328 RX Vref 0 -> 0, step: 1
5273 13:58:45.834401
5274 13:58:45.837809 RX Delay -69 -> 252, step: 4
5275 13:58:45.837909
5276 13:58:45.841066 Set Vref, RX VrefLevel [Byte0]: 53
5277 13:58:45.844517 [Byte1]: 51
5278 13:58:45.844620
5279 13:58:45.847418 Final RX Vref Byte 0 = 53 to rank0
5280 13:58:45.851371 Final RX Vref Byte 1 = 51 to rank0
5281 13:58:45.854653 Final RX Vref Byte 0 = 53 to rank1
5282 13:58:45.857564 Final RX Vref Byte 1 = 51 to rank1==
5283 13:58:45.861065 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 13:58:45.864197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 13:58:45.864276 ==
5286 13:58:45.867821 DQS Delay:
5287 13:58:45.867899 DQS0 = 0, DQS1 = 0
5288 13:58:45.870717 DQM Delay:
5289 13:58:45.870829 DQM0 = 97, DQM1 = 89
5290 13:58:45.870910 DQ Delay:
5291 13:58:45.874440 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =96
5292 13:58:45.877870 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5293 13:58:45.880985 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =80
5294 13:58:45.884611 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =100
5295 13:58:45.884717
5296 13:58:45.884813
5297 13:58:45.894677 [DQSOSCAuto] RK0, (LSB)MR18= 0x1904, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5298 13:58:45.898181 CH0 RK0: MR19=505, MR18=1904
5299 13:58:45.901391 CH0_RK0: MR19=0x505, MR18=0x1904, DQSOSC=413, MR23=63, INC=63, DEC=42
5300 13:58:45.901494
5301 13:58:45.908406 ----->DramcWriteLeveling(PI) begin...
5302 13:58:45.908510 ==
5303 13:58:45.911673 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 13:58:45.914537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 13:58:45.914638 ==
5306 13:58:45.918240 Write leveling (Byte 0): 31 => 31
5307 13:58:45.921095 Write leveling (Byte 1): 31 => 31
5308 13:58:45.924667 DramcWriteLeveling(PI) end<-----
5309 13:58:45.924767
5310 13:58:45.924856 ==
5311 13:58:45.928333 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 13:58:45.931263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 13:58:45.931340 ==
5314 13:58:45.934682 [Gating] SW mode calibration
5315 13:58:45.941197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5316 13:58:45.947879 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5317 13:58:45.951072 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5318 13:58:45.954261 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5319 13:58:45.961037 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 13:58:45.964827 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 13:58:45.967609 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 13:58:45.970973 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 13:58:45.978257 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5324 13:58:45.981330 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (0 0)
5325 13:58:45.984264 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (1 0)
5326 13:58:45.991104 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 13:58:45.994808 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 13:58:45.997955 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 13:58:46.004872 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 13:58:46.007920 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 13:58:46.011175 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5332 13:58:46.018127 0 15 28 | B1->B0 | 2c2c 3636 | 0 1 | (0 0) (0 0)
5333 13:58:46.021343 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
5334 13:58:46.024884 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 13:58:46.031437 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 13:58:46.035314 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 13:58:46.038395 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 13:58:46.041589 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 13:58:46.049062 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5340 13:58:46.051598 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5341 13:58:46.054621 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5342 13:58:46.061660 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 13:58:46.065138 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 13:58:46.068047 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 13:58:46.075220 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 13:58:46.078572 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 13:58:46.081650 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 13:58:46.088260 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 13:58:46.091530 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 13:58:46.094716 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 13:58:46.101345 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 13:58:46.105097 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 13:58:46.108529 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 13:58:46.115080 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 13:58:46.118382 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5356 13:58:46.122323 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5357 13:58:46.125559 Total UI for P1: 0, mck2ui 16
5358 13:58:46.128598 best dqsien dly found for B0: ( 1, 2, 24)
5359 13:58:46.132012 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5360 13:58:46.138372 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 13:58:46.138472 Total UI for P1: 0, mck2ui 16
5362 13:58:46.145592 best dqsien dly found for B1: ( 1, 2, 30)
5363 13:58:46.148853 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5364 13:58:46.152499 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5365 13:58:46.152574
5366 13:58:46.155097 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5367 13:58:46.158651 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5368 13:58:46.161807 [Gating] SW calibration Done
5369 13:58:46.161903 ==
5370 13:58:46.165443 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 13:58:46.168466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 13:58:46.168538 ==
5373 13:58:46.172088 RX Vref Scan: 0
5374 13:58:46.172163
5375 13:58:46.172234 RX Vref 0 -> 0, step: 1
5376 13:58:46.172322
5377 13:58:46.175111 RX Delay -80 -> 252, step: 8
5378 13:58:46.178498 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5379 13:58:46.185380 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5380 13:58:46.188472 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5381 13:58:46.191715 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5382 13:58:46.195405 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5383 13:58:46.198434 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5384 13:58:46.201864 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5385 13:58:46.205472 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5386 13:58:46.211989 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5387 13:58:46.215164 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5388 13:58:46.218995 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5389 13:58:46.221911 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5390 13:58:46.225666 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5391 13:58:46.228506 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5392 13:58:46.235861 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5393 13:58:46.239285 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5394 13:58:46.239360 ==
5395 13:58:46.241971 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 13:58:46.245786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 13:58:46.245863 ==
5398 13:58:46.245926 DQS Delay:
5399 13:58:46.248635 DQS0 = 0, DQS1 = 0
5400 13:58:46.248707 DQM Delay:
5401 13:58:46.252106 DQM0 = 97, DQM1 = 89
5402 13:58:46.252204 DQ Delay:
5403 13:58:46.255566 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5404 13:58:46.259001 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5405 13:58:46.262497 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5406 13:58:46.265809 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5407 13:58:46.265912
5408 13:58:46.266002
5409 13:58:46.266086 ==
5410 13:58:46.269304 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 13:58:46.272258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 13:58:46.275537 ==
5413 13:58:46.275612
5414 13:58:46.275675
5415 13:58:46.275735 TX Vref Scan disable
5416 13:58:46.279168 == TX Byte 0 ==
5417 13:58:46.282149 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5418 13:58:46.285622 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5419 13:58:46.288927 == TX Byte 1 ==
5420 13:58:46.292483 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5421 13:58:46.295730 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5422 13:58:46.295829 ==
5423 13:58:46.298934 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 13:58:46.305809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 13:58:46.305886 ==
5426 13:58:46.305950
5427 13:58:46.306013
5428 13:58:46.306074 TX Vref Scan disable
5429 13:58:46.309972 == TX Byte 0 ==
5430 13:58:46.313173 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5431 13:58:46.316535 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5432 13:58:46.319904 == TX Byte 1 ==
5433 13:58:46.323303 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5434 13:58:46.326582 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5435 13:58:46.329975
5436 13:58:46.330076 [DATLAT]
5437 13:58:46.330167 Freq=933, CH0 RK1
5438 13:58:46.330256
5439 13:58:46.333528 DATLAT Default: 0xb
5440 13:58:46.333624 0, 0xFFFF, sum = 0
5441 13:58:46.336786 1, 0xFFFF, sum = 0
5442 13:58:46.336888 2, 0xFFFF, sum = 0
5443 13:58:46.340167 3, 0xFFFF, sum = 0
5444 13:58:46.340269 4, 0xFFFF, sum = 0
5445 13:58:46.343724 5, 0xFFFF, sum = 0
5446 13:58:46.343827 6, 0xFFFF, sum = 0
5447 13:58:46.346832 7, 0xFFFF, sum = 0
5448 13:58:46.346908 8, 0xFFFF, sum = 0
5449 13:58:46.349992 9, 0xFFFF, sum = 0
5450 13:58:46.350068 10, 0x0, sum = 1
5451 13:58:46.353658 11, 0x0, sum = 2
5452 13:58:46.353757 12, 0x0, sum = 3
5453 13:58:46.357111 13, 0x0, sum = 4
5454 13:58:46.357211 best_step = 11
5455 13:58:46.357299
5456 13:58:46.357389 ==
5457 13:58:46.360127 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 13:58:46.366706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 13:58:46.366821 ==
5460 13:58:46.366887 RX Vref Scan: 0
5461 13:58:46.366947
5462 13:58:46.369928 RX Vref 0 -> 0, step: 1
5463 13:58:46.370026
5464 13:58:46.373364 RX Delay -61 -> 252, step: 4
5465 13:58:46.376762 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5466 13:58:46.380146 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5467 13:58:46.387160 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5468 13:58:46.390403 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5469 13:58:46.394046 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5470 13:58:46.397218 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5471 13:58:46.400648 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5472 13:58:46.403683 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5473 13:58:46.410179 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5474 13:58:46.414169 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5475 13:58:46.417127 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5476 13:58:46.420558 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5477 13:58:46.423542 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5478 13:58:46.427692 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5479 13:58:46.433884 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5480 13:58:46.436890 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5481 13:58:46.436993 ==
5482 13:58:46.440538 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 13:58:46.444460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 13:58:46.444575 ==
5485 13:58:46.444670 DQS Delay:
5486 13:58:46.447454 DQS0 = 0, DQS1 = 0
5487 13:58:46.447529 DQM Delay:
5488 13:58:46.450500 DQM0 = 95, DQM1 = 87
5489 13:58:46.450598 DQ Delay:
5490 13:58:46.453954 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5491 13:58:46.457233 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5492 13:58:46.460779 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5493 13:58:46.463942 DQ12 =92, DQ13 =94, DQ14 =96, DQ15 =94
5494 13:58:46.464029
5495 13:58:46.464095
5496 13:58:46.470398 [DQSOSCAuto] RK1, (LSB)MR18= 0x1906, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5497 13:58:46.474428 CH0 RK1: MR19=505, MR18=1906
5498 13:58:46.480591 CH0_RK1: MR19=0x505, MR18=0x1906, DQSOSC=413, MR23=63, INC=63, DEC=42
5499 13:58:46.484220 [RxdqsGatingPostProcess] freq 933
5500 13:58:46.490944 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5501 13:58:46.493824 best DQS0 dly(2T, 0.5T) = (0, 10)
5502 13:58:46.493934 best DQS1 dly(2T, 0.5T) = (0, 11)
5503 13:58:46.497676 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5504 13:58:46.500571 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5505 13:58:46.504102 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 13:58:46.507498 best DQS1 dly(2T, 0.5T) = (0, 10)
5507 13:58:46.511095 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 13:58:46.513979 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5509 13:58:46.517685 Pre-setting of DQS Precalculation
5510 13:58:46.524129 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5511 13:58:46.524216 ==
5512 13:58:46.527579 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 13:58:46.530702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 13:58:46.530828 ==
5515 13:58:46.537349 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 13:58:46.541156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5517 13:58:46.544791 [CA 0] Center 36 (6~67) winsize 62
5518 13:58:46.548175 [CA 1] Center 36 (6~67) winsize 62
5519 13:58:46.551374 [CA 2] Center 34 (4~64) winsize 61
5520 13:58:46.554631 [CA 3] Center 33 (3~64) winsize 62
5521 13:58:46.558686 [CA 4] Center 34 (3~65) winsize 63
5522 13:58:46.561494 [CA 5] Center 33 (3~64) winsize 62
5523 13:58:46.561566
5524 13:58:46.564999 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5525 13:58:46.565080
5526 13:58:46.568367 [CATrainingPosCal] consider 1 rank data
5527 13:58:46.571468 u2DelayCellTimex100 = 270/100 ps
5528 13:58:46.575077 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5529 13:58:46.578032 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 13:58:46.584502 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5531 13:58:46.587961 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5532 13:58:46.591573 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5533 13:58:46.594797 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5534 13:58:46.594903
5535 13:58:46.598335 CA PerBit enable=1, Macro0, CA PI delay=33
5536 13:58:46.598433
5537 13:58:46.601334 [CBTSetCACLKResult] CA Dly = 33
5538 13:58:46.601436 CS Dly: 4 (0~35)
5539 13:58:46.601530 ==
5540 13:58:46.604775 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 13:58:46.611753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 13:58:46.611858 ==
5543 13:58:46.615031 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5544 13:58:46.621613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5545 13:58:46.624804 [CA 0] Center 36 (6~67) winsize 62
5546 13:58:46.628095 [CA 1] Center 37 (7~67) winsize 61
5547 13:58:46.632403 [CA 2] Center 34 (4~64) winsize 61
5548 13:58:46.634827 [CA 3] Center 33 (3~64) winsize 62
5549 13:58:46.638646 [CA 4] Center 34 (4~64) winsize 61
5550 13:58:46.641559 [CA 5] Center 33 (3~63) winsize 61
5551 13:58:46.641637
5552 13:58:46.644869 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5553 13:58:46.644946
5554 13:58:46.648841 [CATrainingPosCal] consider 2 rank data
5555 13:58:46.651820 u2DelayCellTimex100 = 270/100 ps
5556 13:58:46.654912 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5557 13:58:46.658413 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5558 13:58:46.661766 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5559 13:58:46.668574 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5560 13:58:46.671743 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5561 13:58:46.674990 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5562 13:58:46.675091
5563 13:58:46.678278 CA PerBit enable=1, Macro0, CA PI delay=33
5564 13:58:46.678357
5565 13:58:46.681792 [CBTSetCACLKResult] CA Dly = 33
5566 13:58:46.681870 CS Dly: 5 (0~37)
5567 13:58:46.681951
5568 13:58:46.684930 ----->DramcWriteLeveling(PI) begin...
5569 13:58:46.685028 ==
5570 13:58:46.688234 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 13:58:46.695186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 13:58:46.695265 ==
5573 13:58:46.698812 Write leveling (Byte 0): 24 => 24
5574 13:58:46.701750 Write leveling (Byte 1): 30 => 30
5575 13:58:46.701853 DramcWriteLeveling(PI) end<-----
5576 13:58:46.701940
5577 13:58:46.704864 ==
5578 13:58:46.708318 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 13:58:46.711567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 13:58:46.711659 ==
5581 13:58:46.715262 [Gating] SW mode calibration
5582 13:58:46.721938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5583 13:58:46.725205 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5584 13:58:46.732049 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5585 13:58:46.735296 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5586 13:58:46.738582 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5587 13:58:46.745616 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5588 13:58:46.748736 0 14 16 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5589 13:58:46.751937 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 13:58:46.755776 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 13:58:46.761960 0 14 28 | B1->B0 | 3030 2f2f | 1 1 | (1 0) (1 0)
5592 13:58:46.765668 0 15 0 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5593 13:58:46.768773 0 15 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5594 13:58:46.775543 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5595 13:58:46.778651 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 13:58:46.782034 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 13:58:46.788931 0 15 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5598 13:58:46.791986 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 13:58:46.795494 0 15 28 | B1->B0 | 2726 2c2c | 1 0 | (0 0) (0 0)
5600 13:58:46.802528 1 0 0 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
5601 13:58:46.805745 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 13:58:46.808712 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 13:58:46.812460 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 13:58:46.818913 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 13:58:46.822430 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 13:58:46.825957 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 13:58:46.832209 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5608 13:58:46.835701 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5609 13:58:46.839378 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 13:58:46.845997 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 13:58:46.849060 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 13:58:46.852105 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 13:58:46.858853 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 13:58:46.862340 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 13:58:46.865543 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 13:58:46.872225 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 13:58:46.875957 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 13:58:46.879216 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 13:58:46.885946 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 13:58:46.889293 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 13:58:46.892511 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 13:58:46.898944 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5623 13:58:46.902248 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 13:58:46.905613 Total UI for P1: 0, mck2ui 16
5625 13:58:46.909410 best dqsien dly found for B0: ( 1, 2, 26)
5626 13:58:46.912639 Total UI for P1: 0, mck2ui 16
5627 13:58:46.916123 best dqsien dly found for B1: ( 1, 2, 24)
5628 13:58:46.919125 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5629 13:58:46.922414 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5630 13:58:46.922510
5631 13:58:46.925868 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5632 13:58:46.928928 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5633 13:58:46.932608 [Gating] SW calibration Done
5634 13:58:46.932702 ==
5635 13:58:46.935617 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 13:58:46.939195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 13:58:46.939294 ==
5638 13:58:46.942717 RX Vref Scan: 0
5639 13:58:46.942831
5640 13:58:46.942919 RX Vref 0 -> 0, step: 1
5641 13:58:46.943065
5642 13:58:46.946358 RX Delay -80 -> 252, step: 8
5643 13:58:46.949174 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5644 13:58:46.955924 iDelay=200, Bit 1, Center 91 (0 ~ 183) 184
5645 13:58:46.959236 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5646 13:58:46.962582 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5647 13:58:46.966039 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5648 13:58:46.969447 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5649 13:58:46.972881 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5650 13:58:46.975870 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5651 13:58:46.982547 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5652 13:58:46.985936 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5653 13:58:46.989509 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5654 13:58:46.992949 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5655 13:58:46.996228 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5656 13:58:47.002813 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5657 13:58:47.006297 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5658 13:58:47.009380 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5659 13:58:47.009480 ==
5660 13:58:47.012849 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 13:58:47.016029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 13:58:47.016108 ==
5663 13:58:47.019620 DQS Delay:
5664 13:58:47.019697 DQS0 = 0, DQS1 = 0
5665 13:58:47.019760 DQM Delay:
5666 13:58:47.022937 DQM0 = 95, DQM1 = 89
5667 13:58:47.023024 DQ Delay:
5668 13:58:47.026000 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5669 13:58:47.029233 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5670 13:58:47.033013 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5671 13:58:47.036282 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5672 13:58:47.036381
5673 13:58:47.036480
5674 13:58:47.036543 ==
5675 13:58:47.039833 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 13:58:47.046204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 13:58:47.046283 ==
5678 13:58:47.046347
5679 13:58:47.046411
5680 13:58:47.046474 TX Vref Scan disable
5681 13:58:47.049528 == TX Byte 0 ==
5682 13:58:47.053010 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5683 13:58:47.056666 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5684 13:58:47.059651 == TX Byte 1 ==
5685 13:58:47.062898 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5686 13:58:47.066579 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5687 13:58:47.069833 ==
5688 13:58:47.073338 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 13:58:47.076591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 13:58:47.076671 ==
5691 13:58:47.076754
5692 13:58:47.076846
5693 13:58:47.079572 TX Vref Scan disable
5694 13:58:47.079673 == TX Byte 0 ==
5695 13:58:47.086749 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5696 13:58:47.090083 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5697 13:58:47.090192 == TX Byte 1 ==
5698 13:58:47.096690 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5699 13:58:47.099766 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5700 13:58:47.099870
5701 13:58:47.099965 [DATLAT]
5702 13:58:47.103036 Freq=933, CH1 RK0
5703 13:58:47.103114
5704 13:58:47.103190 DATLAT Default: 0xd
5705 13:58:47.106467 0, 0xFFFF, sum = 0
5706 13:58:47.106567 1, 0xFFFF, sum = 0
5707 13:58:47.110127 2, 0xFFFF, sum = 0
5708 13:58:47.110229 3, 0xFFFF, sum = 0
5709 13:58:47.113423 4, 0xFFFF, sum = 0
5710 13:58:47.113519 5, 0xFFFF, sum = 0
5711 13:58:47.116295 6, 0xFFFF, sum = 0
5712 13:58:47.116395 7, 0xFFFF, sum = 0
5713 13:58:47.120167 8, 0xFFFF, sum = 0
5714 13:58:47.120273 9, 0xFFFF, sum = 0
5715 13:58:47.123187 10, 0x0, sum = 1
5716 13:58:47.123259 11, 0x0, sum = 2
5717 13:58:47.126855 12, 0x0, sum = 3
5718 13:58:47.126959 13, 0x0, sum = 4
5719 13:58:47.129827 best_step = 11
5720 13:58:47.129923
5721 13:58:47.130012 ==
5722 13:58:47.133115 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 13:58:47.136608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 13:58:47.136710 ==
5725 13:58:47.139755 RX Vref Scan: 1
5726 13:58:47.139825
5727 13:58:47.139890 RX Vref 0 -> 0, step: 1
5728 13:58:47.139948
5729 13:58:47.143675 RX Delay -61 -> 252, step: 4
5730 13:58:47.143770
5731 13:58:47.146603 Set Vref, RX VrefLevel [Byte0]: 58
5732 13:58:47.150273 [Byte1]: 54
5733 13:58:47.153648
5734 13:58:47.153745 Final RX Vref Byte 0 = 58 to rank0
5735 13:58:47.157090 Final RX Vref Byte 1 = 54 to rank0
5736 13:58:47.160343 Final RX Vref Byte 0 = 58 to rank1
5737 13:58:47.163530 Final RX Vref Byte 1 = 54 to rank1==
5738 13:58:47.166837 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 13:58:47.173646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 13:58:47.173746 ==
5741 13:58:47.173836 DQS Delay:
5742 13:58:47.173923 DQS0 = 0, DQS1 = 0
5743 13:58:47.176919 DQM Delay:
5744 13:58:47.177019 DQM0 = 97, DQM1 = 90
5745 13:58:47.180051 DQ Delay:
5746 13:58:47.183496 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =96
5747 13:58:47.186836 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5748 13:58:47.190580 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =86
5749 13:58:47.193753 DQ12 =98, DQ13 =96, DQ14 =98, DQ15 =96
5750 13:58:47.193862
5751 13:58:47.193942
5752 13:58:47.200358 [DQSOSCAuto] RK0, (LSB)MR18= 0x1af7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 413 ps
5753 13:58:47.203817 CH1 RK0: MR19=504, MR18=1AF7
5754 13:58:47.210693 CH1_RK0: MR19=0x504, MR18=0x1AF7, DQSOSC=413, MR23=63, INC=63, DEC=42
5755 13:58:47.210821
5756 13:58:47.214081 ----->DramcWriteLeveling(PI) begin...
5757 13:58:47.214186 ==
5758 13:58:47.217319 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 13:58:47.220658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 13:58:47.220731 ==
5761 13:58:47.223793 Write leveling (Byte 0): 30 => 30
5762 13:58:47.227080 Write leveling (Byte 1): 30 => 30
5763 13:58:47.230518 DramcWriteLeveling(PI) end<-----
5764 13:58:47.230613
5765 13:58:47.230704 ==
5766 13:58:47.234081 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 13:58:47.237148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 13:58:47.237220 ==
5769 13:58:47.240697 [Gating] SW mode calibration
5770 13:58:47.247564 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5771 13:58:47.254228 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5772 13:58:47.257216 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 13:58:47.260761 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 13:58:47.267514 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5775 13:58:47.270726 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 13:58:47.274075 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5777 13:58:47.280737 0 14 20 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
5778 13:58:47.284153 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
5779 13:58:47.287408 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5780 13:58:47.294395 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5781 13:58:47.297522 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 13:58:47.300665 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 13:58:47.304179 0 15 12 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5784 13:58:47.310856 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 13:58:47.314328 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 13:58:47.317837 0 15 24 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
5787 13:58:47.324434 0 15 28 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
5788 13:58:47.327757 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 13:58:47.331264 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 13:58:47.337832 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 13:58:47.341018 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 13:58:47.344342 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 13:58:47.351341 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 13:58:47.354399 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5795 13:58:47.358135 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5796 13:58:47.364466 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 13:58:47.367973 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 13:58:47.371035 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 13:58:47.374558 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 13:58:47.381196 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 13:58:47.384448 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 13:58:47.387707 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 13:58:47.394824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 13:58:47.397808 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 13:58:47.401751 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 13:58:47.408558 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 13:58:47.411284 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 13:58:47.414760 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 13:58:47.421309 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5810 13:58:47.424795 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5811 13:58:47.428219 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 13:58:47.431393 Total UI for P1: 0, mck2ui 16
5813 13:58:47.434645 best dqsien dly found for B0: ( 1, 2, 22)
5814 13:58:47.438068 Total UI for P1: 0, mck2ui 16
5815 13:58:47.441323 best dqsien dly found for B1: ( 1, 2, 24)
5816 13:58:47.444844 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5817 13:58:47.448405 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5818 13:58:47.448507
5819 13:58:47.451396 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5820 13:58:47.458181 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5821 13:58:47.458283 [Gating] SW calibration Done
5822 13:58:47.458374 ==
5823 13:58:47.461514 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 13:58:47.468413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 13:58:47.468514 ==
5826 13:58:47.468608 RX Vref Scan: 0
5827 13:58:47.468697
5828 13:58:47.471513 RX Vref 0 -> 0, step: 1
5829 13:58:47.471610
5830 13:58:47.474795 RX Delay -80 -> 252, step: 8
5831 13:58:47.478127 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5832 13:58:47.481625 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5833 13:58:47.484744 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5834 13:58:47.488076 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5835 13:58:47.491420 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5836 13:58:47.498209 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5837 13:58:47.501744 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5838 13:58:47.505620 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5839 13:58:47.508347 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5840 13:58:47.511699 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5841 13:58:47.518295 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5842 13:58:47.521431 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5843 13:58:47.524617 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5844 13:58:47.528408 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5845 13:58:47.531509 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5846 13:58:47.535041 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5847 13:58:47.535140 ==
5848 13:58:47.538058 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 13:58:47.544886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 13:58:47.544969 ==
5851 13:58:47.545037 DQS Delay:
5852 13:58:47.548269 DQS0 = 0, DQS1 = 0
5853 13:58:47.548345 DQM Delay:
5854 13:58:47.548440 DQM0 = 95, DQM1 = 89
5855 13:58:47.551550 DQ Delay:
5856 13:58:47.554853 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5857 13:58:47.558117 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5858 13:58:47.561605 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5859 13:58:47.564810 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5860 13:58:47.564909
5861 13:58:47.565009
5862 13:58:47.565096 ==
5863 13:58:47.568415 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 13:58:47.571484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 13:58:47.571596 ==
5866 13:58:47.571686
5867 13:58:47.571783
5868 13:58:47.574960 TX Vref Scan disable
5869 13:58:47.575032 == TX Byte 0 ==
5870 13:58:47.581744 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5871 13:58:47.585238 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5872 13:58:47.585317 == TX Byte 1 ==
5873 13:58:47.591517 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5874 13:58:47.594763 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5875 13:58:47.594877 ==
5876 13:58:47.598274 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 13:58:47.601453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 13:58:47.601562 ==
5879 13:58:47.601653
5880 13:58:47.601741
5881 13:58:47.604817 TX Vref Scan disable
5882 13:58:47.608403 == TX Byte 0 ==
5883 13:58:47.611555 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5884 13:58:47.615371 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5885 13:58:47.618312 == TX Byte 1 ==
5886 13:58:47.621891 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5887 13:58:47.625163 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5888 13:58:47.625270
5889 13:58:47.628682 [DATLAT]
5890 13:58:47.628779 Freq=933, CH1 RK1
5891 13:58:47.628869
5892 13:58:47.631753 DATLAT Default: 0xb
5893 13:58:47.631850 0, 0xFFFF, sum = 0
5894 13:58:47.635225 1, 0xFFFF, sum = 0
5895 13:58:47.635331 2, 0xFFFF, sum = 0
5896 13:58:47.638709 3, 0xFFFF, sum = 0
5897 13:58:47.638811 4, 0xFFFF, sum = 0
5898 13:58:47.641588 5, 0xFFFF, sum = 0
5899 13:58:47.641688 6, 0xFFFF, sum = 0
5900 13:58:47.645223 7, 0xFFFF, sum = 0
5901 13:58:47.645323 8, 0xFFFF, sum = 0
5902 13:58:47.648364 9, 0xFFFF, sum = 0
5903 13:58:47.648439 10, 0x0, sum = 1
5904 13:58:47.651579 11, 0x0, sum = 2
5905 13:58:47.651687 12, 0x0, sum = 3
5906 13:58:47.655253 13, 0x0, sum = 4
5907 13:58:47.655363 best_step = 11
5908 13:58:47.655454
5909 13:58:47.655541 ==
5910 13:58:47.658643 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 13:58:47.664900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 13:58:47.665001 ==
5913 13:58:47.665094 RX Vref Scan: 0
5914 13:58:47.665189
5915 13:58:47.668440 RX Vref 0 -> 0, step: 1
5916 13:58:47.668562
5917 13:58:47.671755 RX Delay -61 -> 252, step: 4
5918 13:58:47.674894 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5919 13:58:47.678219 iDelay=195, Bit 1, Center 88 (-5 ~ 182) 188
5920 13:58:47.685008 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5921 13:58:47.688332 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5922 13:58:47.691585 iDelay=195, Bit 4, Center 96 (3 ~ 190) 188
5923 13:58:47.694882 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5924 13:58:47.698478 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5925 13:58:47.701783 iDelay=195, Bit 7, Center 92 (3 ~ 182) 180
5926 13:58:47.704891 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5927 13:58:47.711556 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
5928 13:58:47.714872 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5929 13:58:47.718179 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5930 13:58:47.721509 iDelay=195, Bit 12, Center 100 (15 ~ 186) 172
5931 13:58:47.724980 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5932 13:58:47.731699 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5933 13:58:47.734808 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5934 13:58:47.734918 ==
5935 13:58:47.738295 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 13:58:47.741532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 13:58:47.741607 ==
5938 13:58:47.741671 DQS Delay:
5939 13:58:47.745743 DQS0 = 0, DQS1 = 0
5940 13:58:47.745817 DQM Delay:
5941 13:58:47.748631 DQM0 = 95, DQM1 = 90
5942 13:58:47.748704 DQ Delay:
5943 13:58:47.751804 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =94
5944 13:58:47.755068 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =92
5945 13:58:47.758400 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5946 13:58:47.762041 DQ12 =100, DQ13 =98, DQ14 =98, DQ15 =98
5947 13:58:47.762140
5948 13:58:47.762240
5949 13:58:47.772148 [DQSOSCAuto] RK1, (LSB)MR18= 0x1019, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5950 13:58:47.772260 CH1 RK1: MR19=505, MR18=1019
5951 13:58:47.778597 CH1_RK1: MR19=0x505, MR18=0x1019, DQSOSC=413, MR23=63, INC=63, DEC=42
5952 13:58:47.782049 [RxdqsGatingPostProcess] freq 933
5953 13:58:47.788703 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5954 13:58:47.791896 best DQS0 dly(2T, 0.5T) = (0, 10)
5955 13:58:47.795299 best DQS1 dly(2T, 0.5T) = (0, 10)
5956 13:58:47.798978 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5957 13:58:47.802138 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5958 13:58:47.802236 best DQS0 dly(2T, 0.5T) = (0, 10)
5959 13:58:47.805351 best DQS1 dly(2T, 0.5T) = (0, 10)
5960 13:58:47.808863 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5961 13:58:47.811760 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5962 13:58:47.815205 Pre-setting of DQS Precalculation
5963 13:58:47.822195 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5964 13:58:47.828757 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5965 13:58:47.835489 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5966 13:58:47.835587
5967 13:58:47.835680
5968 13:58:47.838727 [Calibration Summary] 1866 Mbps
5969 13:58:47.838801 CH 0, Rank 0
5970 13:58:47.842203 SW Impedance : PASS
5971 13:58:47.845381 DUTY Scan : NO K
5972 13:58:47.845474 ZQ Calibration : PASS
5973 13:58:47.848735 Jitter Meter : NO K
5974 13:58:47.852245 CBT Training : PASS
5975 13:58:47.852339 Write leveling : PASS
5976 13:58:47.855861 RX DQS gating : PASS
5977 13:58:47.855934 RX DQ/DQS(RDDQC) : PASS
5978 13:58:47.858983 TX DQ/DQS : PASS
5979 13:58:47.862561 RX DATLAT : PASS
5980 13:58:47.862691 RX DQ/DQS(Engine): PASS
5981 13:58:47.865936 TX OE : NO K
5982 13:58:47.866043 All Pass.
5983 13:58:47.866133
5984 13:58:47.868833 CH 0, Rank 1
5985 13:58:47.868939 SW Impedance : PASS
5986 13:58:47.872212 DUTY Scan : NO K
5987 13:58:47.875969 ZQ Calibration : PASS
5988 13:58:47.876069 Jitter Meter : NO K
5989 13:58:47.878854 CBT Training : PASS
5990 13:58:47.882398 Write leveling : PASS
5991 13:58:47.882471 RX DQS gating : PASS
5992 13:58:47.885822 RX DQ/DQS(RDDQC) : PASS
5993 13:58:47.885920 TX DQ/DQS : PASS
5994 13:58:47.888951 RX DATLAT : PASS
5995 13:58:47.892532 RX DQ/DQS(Engine): PASS
5996 13:58:47.892632 TX OE : NO K
5997 13:58:47.895590 All Pass.
5998 13:58:47.895666
5999 13:58:47.895728 CH 1, Rank 0
6000 13:58:47.899399 SW Impedance : PASS
6001 13:58:47.899472 DUTY Scan : NO K
6002 13:58:47.902365 ZQ Calibration : PASS
6003 13:58:47.905866 Jitter Meter : NO K
6004 13:58:47.905965 CBT Training : PASS
6005 13:58:47.909236 Write leveling : PASS
6006 13:58:47.912732 RX DQS gating : PASS
6007 13:58:47.912846 RX DQ/DQS(RDDQC) : PASS
6008 13:58:47.916022 TX DQ/DQS : PASS
6009 13:58:47.918860 RX DATLAT : PASS
6010 13:58:47.918958 RX DQ/DQS(Engine): PASS
6011 13:58:47.922822 TX OE : NO K
6012 13:58:47.922905 All Pass.
6013 13:58:47.922967
6014 13:58:47.925520 CH 1, Rank 1
6015 13:58:47.925618 SW Impedance : PASS
6016 13:58:47.928986 DUTY Scan : NO K
6017 13:58:47.929087 ZQ Calibration : PASS
6018 13:58:47.932632 Jitter Meter : NO K
6019 13:58:47.935714 CBT Training : PASS
6020 13:58:47.935785 Write leveling : PASS
6021 13:58:47.939054 RX DQS gating : PASS
6022 13:58:47.942335 RX DQ/DQS(RDDQC) : PASS
6023 13:58:47.942435 TX DQ/DQS : PASS
6024 13:58:47.945837 RX DATLAT : PASS
6025 13:58:47.948985 RX DQ/DQS(Engine): PASS
6026 13:58:47.949087 TX OE : NO K
6027 13:58:47.952591 All Pass.
6028 13:58:47.952674
6029 13:58:47.952734 DramC Write-DBI off
6030 13:58:47.955969 PER_BANK_REFRESH: Hybrid Mode
6031 13:58:47.956045 TX_TRACKING: ON
6032 13:58:47.965961 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6033 13:58:47.969242 [FAST_K] Save calibration result to emmc
6034 13:58:47.972529 dramc_set_vcore_voltage set vcore to 650000
6035 13:58:47.975771 Read voltage for 400, 6
6036 13:58:47.975841 Vio18 = 0
6037 13:58:47.979146 Vcore = 650000
6038 13:58:47.979222 Vdram = 0
6039 13:58:47.979284 Vddq = 0
6040 13:58:47.979343 Vmddr = 0
6041 13:58:47.985993 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6042 13:58:47.992639 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6043 13:58:47.992739 MEM_TYPE=3, freq_sel=20
6044 13:58:47.996037 sv_algorithm_assistance_LP4_800
6045 13:58:47.999153 ============ PULL DRAM RESETB DOWN ============
6046 13:58:48.006235 ========== PULL DRAM RESETB DOWN end =========
6047 13:58:48.009142 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6048 13:58:48.012550 ===================================
6049 13:58:48.016114 LPDDR4 DRAM CONFIGURATION
6050 13:58:48.019131 ===================================
6051 13:58:48.019215 EX_ROW_EN[0] = 0x0
6052 13:58:48.023105 EX_ROW_EN[1] = 0x0
6053 13:58:48.023191 LP4Y_EN = 0x0
6054 13:58:48.026625 WORK_FSP = 0x0
6055 13:58:48.026728 WL = 0x2
6056 13:58:48.029204 RL = 0x2
6057 13:58:48.029299 BL = 0x2
6058 13:58:48.032820 RPST = 0x0
6059 13:58:48.032905 RD_PRE = 0x0
6060 13:58:48.036158 WR_PRE = 0x1
6061 13:58:48.036254 WR_PST = 0x0
6062 13:58:48.039381 DBI_WR = 0x0
6063 13:58:48.039475 DBI_RD = 0x0
6064 13:58:48.042961 OTF = 0x1
6065 13:58:48.046038 ===================================
6066 13:58:48.049912 ===================================
6067 13:58:48.049984 ANA top config
6068 13:58:48.053233 ===================================
6069 13:58:48.056187 DLL_ASYNC_EN = 0
6070 13:58:48.059522 ALL_SLAVE_EN = 1
6071 13:58:48.063095 NEW_RANK_MODE = 1
6072 13:58:48.063199 DLL_IDLE_MODE = 1
6073 13:58:48.066158 LP45_APHY_COMB_EN = 1
6074 13:58:48.069765 TX_ODT_DIS = 1
6075 13:58:48.073061 NEW_8X_MODE = 1
6076 13:58:48.076649 ===================================
6077 13:58:48.079750 ===================================
6078 13:58:48.083219 data_rate = 800
6079 13:58:48.083351 CKR = 1
6080 13:58:48.086905 DQ_P2S_RATIO = 4
6081 13:58:48.089757 ===================================
6082 13:58:48.092931 CA_P2S_RATIO = 4
6083 13:58:48.096423 DQ_CA_OPEN = 0
6084 13:58:48.099723 DQ_SEMI_OPEN = 1
6085 13:58:48.103128 CA_SEMI_OPEN = 1
6086 13:58:48.103205 CA_FULL_RATE = 0
6087 13:58:48.106411 DQ_CKDIV4_EN = 0
6088 13:58:48.109870 CA_CKDIV4_EN = 1
6089 13:58:48.113116 CA_PREDIV_EN = 0
6090 13:58:48.116907 PH8_DLY = 0
6091 13:58:48.117008 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6092 13:58:48.120250 DQ_AAMCK_DIV = 0
6093 13:58:48.123003 CA_AAMCK_DIV = 0
6094 13:58:48.126882 CA_ADMCK_DIV = 4
6095 13:58:48.129836 DQ_TRACK_CA_EN = 0
6096 13:58:48.133154 CA_PICK = 800
6097 13:58:48.136519 CA_MCKIO = 400
6098 13:58:48.136622 MCKIO_SEMI = 400
6099 13:58:48.140122 PLL_FREQ = 3016
6100 13:58:48.143313 DQ_UI_PI_RATIO = 32
6101 13:58:48.146221 CA_UI_PI_RATIO = 32
6102 13:58:48.150225 ===================================
6103 13:58:48.153027 ===================================
6104 13:58:48.156782 memory_type:LPDDR4
6105 13:58:48.156884 GP_NUM : 10
6106 13:58:48.160362 SRAM_EN : 1
6107 13:58:48.163336 MD32_EN : 0
6108 13:58:48.166647 ===================================
6109 13:58:48.166783 [ANA_INIT] >>>>>>>>>>>>>>
6110 13:58:48.170267 <<<<<< [CONFIGURE PHASE]: ANA_TX
6111 13:58:48.173130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6112 13:58:48.176826 ===================================
6113 13:58:48.180122 data_rate = 800,PCW = 0X7400
6114 13:58:48.183846 ===================================
6115 13:58:48.186509 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6116 13:58:48.192980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6117 13:58:48.203419 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 13:58:48.206601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6119 13:58:48.210039 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6120 13:58:48.213336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6121 13:58:48.216844 [ANA_INIT] flow start
6122 13:58:48.220280 [ANA_INIT] PLL >>>>>>>>
6123 13:58:48.220359 [ANA_INIT] PLL <<<<<<<<
6124 13:58:48.224050 [ANA_INIT] MIDPI >>>>>>>>
6125 13:58:48.227283 [ANA_INIT] MIDPI <<<<<<<<
6126 13:58:48.227384 [ANA_INIT] DLL >>>>>>>>
6127 13:58:48.230549 [ANA_INIT] flow end
6128 13:58:48.233703 ============ LP4 DIFF to SE enter ============
6129 13:58:48.237029 ============ LP4 DIFF to SE exit ============
6130 13:58:48.240712 [ANA_INIT] <<<<<<<<<<<<<
6131 13:58:48.243721 [Flow] Enable top DCM control >>>>>
6132 13:58:48.246700 [Flow] Enable top DCM control <<<<<
6133 13:58:48.250367 Enable DLL master slave shuffle
6134 13:58:48.256534 ==============================================================
6135 13:58:48.256611 Gating Mode config
6136 13:58:48.263485 ==============================================================
6137 13:58:48.263585 Config description:
6138 13:58:48.274000 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6139 13:58:48.280137 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6140 13:58:48.287264 SELPH_MODE 0: By rank 1: By Phase
6141 13:58:48.290191 ==============================================================
6142 13:58:48.293314 GAT_TRACK_EN = 0
6143 13:58:48.297035 RX_GATING_MODE = 2
6144 13:58:48.300200 RX_GATING_TRACK_MODE = 2
6145 13:58:48.303632 SELPH_MODE = 1
6146 13:58:48.307507 PICG_EARLY_EN = 1
6147 13:58:48.310308 VALID_LAT_VALUE = 1
6148 13:58:48.316848 ==============================================================
6149 13:58:48.320311 Enter into Gating configuration >>>>
6150 13:58:48.323637 Exit from Gating configuration <<<<
6151 13:58:48.323718 Enter into DVFS_PRE_config >>>>>
6152 13:58:48.337008 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6153 13:58:48.340376 Exit from DVFS_PRE_config <<<<<
6154 13:58:48.343811 Enter into PICG configuration >>>>
6155 13:58:48.346957 Exit from PICG configuration <<<<
6156 13:58:48.347062 [RX_INPUT] configuration >>>>>
6157 13:58:48.350038 [RX_INPUT] configuration <<<<<
6158 13:58:48.356659 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6159 13:58:48.360097 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6160 13:58:48.366714 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 13:58:48.373458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 13:58:48.380241 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6163 13:58:48.386996 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6164 13:58:48.390350 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6165 13:58:48.393392 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6166 13:58:48.396830 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6167 13:58:48.403351 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6168 13:58:48.406606 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6169 13:58:48.410485 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 13:58:48.413812 ===================================
6171 13:58:48.416886 LPDDR4 DRAM CONFIGURATION
6172 13:58:48.420418 ===================================
6173 13:58:48.424114 EX_ROW_EN[0] = 0x0
6174 13:58:48.424185 EX_ROW_EN[1] = 0x0
6175 13:58:48.427240 LP4Y_EN = 0x0
6176 13:58:48.427310 WORK_FSP = 0x0
6177 13:58:48.430168 WL = 0x2
6178 13:58:48.430263 RL = 0x2
6179 13:58:48.433885 BL = 0x2
6180 13:58:48.434016 RPST = 0x0
6181 13:58:48.437126 RD_PRE = 0x0
6182 13:58:48.437221 WR_PRE = 0x1
6183 13:58:48.440277 WR_PST = 0x0
6184 13:58:48.440346 DBI_WR = 0x0
6185 13:58:48.443975 DBI_RD = 0x0
6186 13:58:48.444050 OTF = 0x1
6187 13:58:48.447042 ===================================
6188 13:58:48.450384 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6189 13:58:48.457457 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6190 13:58:48.460517 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6191 13:58:48.464297 ===================================
6192 13:58:48.467060 LPDDR4 DRAM CONFIGURATION
6193 13:58:48.470232 ===================================
6194 13:58:48.470326 EX_ROW_EN[0] = 0x10
6195 13:58:48.473904 EX_ROW_EN[1] = 0x0
6196 13:58:48.474001 LP4Y_EN = 0x0
6197 13:58:48.477053 WORK_FSP = 0x0
6198 13:58:48.480678 WL = 0x2
6199 13:58:48.480788 RL = 0x2
6200 13:58:48.483987 BL = 0x2
6201 13:58:48.484092 RPST = 0x0
6202 13:58:48.487089 RD_PRE = 0x0
6203 13:58:48.487161 WR_PRE = 0x1
6204 13:58:48.490294 WR_PST = 0x0
6205 13:58:48.490388 DBI_WR = 0x0
6206 13:58:48.493640 DBI_RD = 0x0
6207 13:58:48.493734 OTF = 0x1
6208 13:58:48.497096 ===================================
6209 13:58:48.503841 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6210 13:58:48.507424 nWR fixed to 30
6211 13:58:48.510869 [ModeRegInit_LP4] CH0 RK0
6212 13:58:48.510943 [ModeRegInit_LP4] CH0 RK1
6213 13:58:48.514301 [ModeRegInit_LP4] CH1 RK0
6214 13:58:48.517785 [ModeRegInit_LP4] CH1 RK1
6215 13:58:48.517880 match AC timing 19
6216 13:58:48.524703 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6217 13:58:48.527699 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6218 13:58:48.531349 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6219 13:58:48.537833 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6220 13:58:48.541460 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6221 13:58:48.541557 ==
6222 13:58:48.544743 Dram Type= 6, Freq= 0, CH_0, rank 0
6223 13:58:48.547674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6224 13:58:48.547755 ==
6225 13:58:48.554633 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6226 13:58:48.561070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6227 13:58:48.564617 [CA 0] Center 36 (8~64) winsize 57
6228 13:58:48.567737 [CA 1] Center 36 (8~64) winsize 57
6229 13:58:48.567836 [CA 2] Center 36 (8~64) winsize 57
6230 13:58:48.571696 [CA 3] Center 36 (8~64) winsize 57
6231 13:58:48.575008 [CA 4] Center 36 (8~64) winsize 57
6232 13:58:48.577846 [CA 5] Center 36 (8~64) winsize 57
6233 13:58:48.577996
6234 13:58:48.581208 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6235 13:58:48.581315
6236 13:58:48.584611 [CATrainingPosCal] consider 1 rank data
6237 13:58:48.587859 u2DelayCellTimex100 = 270/100 ps
6238 13:58:48.591778 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 13:58:48.597743 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 13:58:48.601329 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 13:58:48.605067 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 13:58:48.607790 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 13:58:48.611231 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 13:58:48.611312
6245 13:58:48.614482 CA PerBit enable=1, Macro0, CA PI delay=36
6246 13:58:48.614576
6247 13:58:48.618079 [CBTSetCACLKResult] CA Dly = 36
6248 13:58:48.618173 CS Dly: 1 (0~32)
6249 13:58:48.621028 ==
6250 13:58:48.624730 Dram Type= 6, Freq= 0, CH_0, rank 1
6251 13:58:48.627510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6252 13:58:48.627613 ==
6253 13:58:48.631111 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6254 13:58:48.637726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6255 13:58:48.641074 [CA 0] Center 36 (8~64) winsize 57
6256 13:58:48.644739 [CA 1] Center 36 (8~64) winsize 57
6257 13:58:48.647841 [CA 2] Center 36 (8~64) winsize 57
6258 13:58:48.651153 [CA 3] Center 36 (8~64) winsize 57
6259 13:58:48.654314 [CA 4] Center 36 (8~64) winsize 57
6260 13:58:48.657940 [CA 5] Center 36 (8~64) winsize 57
6261 13:58:48.658037
6262 13:58:48.661190 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6263 13:58:48.661265
6264 13:58:48.664560 [CATrainingPosCal] consider 2 rank data
6265 13:58:48.667778 u2DelayCellTimex100 = 270/100 ps
6266 13:58:48.671082 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 13:58:48.674256 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 13:58:48.677736 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 13:58:48.681018 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 13:58:48.684328 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 13:58:48.691136 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 13:58:48.691210
6273 13:58:48.694831 CA PerBit enable=1, Macro0, CA PI delay=36
6274 13:58:48.694928
6275 13:58:48.697592 [CBTSetCACLKResult] CA Dly = 36
6276 13:58:48.697678 CS Dly: 1 (0~32)
6277 13:58:48.697739
6278 13:58:48.701288 ----->DramcWriteLeveling(PI) begin...
6279 13:58:48.701387 ==
6280 13:58:48.704343 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 13:58:48.707609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 13:58:48.711066 ==
6283 13:58:48.711142 Write leveling (Byte 0): 40 => 8
6284 13:58:48.714440 Write leveling (Byte 1): 32 => 0
6285 13:58:48.717689 DramcWriteLeveling(PI) end<-----
6286 13:58:48.717786
6287 13:58:48.717886 ==
6288 13:58:48.721147 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 13:58:48.727739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 13:58:48.727815 ==
6291 13:58:48.727896 [Gating] SW mode calibration
6292 13:58:48.737769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6293 13:58:48.741176 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6294 13:58:48.744520 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6295 13:58:48.751609 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 13:58:48.754938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6297 13:58:48.758192 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 13:58:48.764813 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 13:58:48.768207 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 13:58:48.771089 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 13:58:48.777942 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 13:58:48.781646 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 13:58:48.784473 Total UI for P1: 0, mck2ui 16
6304 13:58:48.787909 best dqsien dly found for B0: ( 0, 14, 24)
6305 13:58:48.791128 Total UI for P1: 0, mck2ui 16
6306 13:58:48.794837 best dqsien dly found for B1: ( 0, 14, 24)
6307 13:58:48.798093 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6308 13:58:48.801403 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6309 13:58:48.801503
6310 13:58:48.804361 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6311 13:58:48.808156 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 13:58:48.811557 [Gating] SW calibration Done
6313 13:58:48.811632 ==
6314 13:58:48.814646 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 13:58:48.818206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 13:58:48.818311 ==
6317 13:58:48.821095 RX Vref Scan: 0
6318 13:58:48.821194
6319 13:58:48.824556 RX Vref 0 -> 0, step: 1
6320 13:58:48.824632
6321 13:58:48.827802 RX Delay -410 -> 252, step: 16
6322 13:58:48.831326 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6323 13:58:48.834829 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6324 13:58:48.838190 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6325 13:58:48.844586 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6326 13:58:48.848158 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6327 13:58:48.851284 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6328 13:58:48.854583 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6329 13:58:48.861266 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6330 13:58:48.864552 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6331 13:58:48.867749 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6332 13:58:48.871254 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6333 13:58:48.878180 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6334 13:58:48.880942 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6335 13:58:48.884521 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6336 13:58:48.887674 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6337 13:58:48.894661 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6338 13:58:48.894801 ==
6339 13:58:48.897860 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 13:58:48.901361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 13:58:48.901467 ==
6342 13:58:48.901567 DQS Delay:
6343 13:58:48.904594 DQS0 = 35, DQS1 = 51
6344 13:58:48.904701 DQM Delay:
6345 13:58:48.907947 DQM0 = 7, DQM1 = 10
6346 13:58:48.908050 DQ Delay:
6347 13:58:48.911193 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6348 13:58:48.914686 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6349 13:58:48.918102 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6350 13:58:48.921081 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6351 13:58:48.921179
6352 13:58:48.921278
6353 13:58:48.921364 ==
6354 13:58:48.924681 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 13:58:48.927990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 13:58:48.928086 ==
6357 13:58:48.928184
6358 13:58:48.928269
6359 13:58:48.931113 TX Vref Scan disable
6360 13:58:48.931182 == TX Byte 0 ==
6361 13:58:48.938033 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6362 13:58:48.941203 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6363 13:58:48.941307 == TX Byte 1 ==
6364 13:58:48.948323 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6365 13:58:48.951747 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6366 13:58:48.951824 ==
6367 13:58:48.955416 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 13:58:48.958267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 13:58:48.958367 ==
6370 13:58:48.958431
6371 13:58:48.958490
6372 13:58:48.961703 TX Vref Scan disable
6373 13:58:48.961847 == TX Byte 0 ==
6374 13:58:48.968166 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 13:58:48.971247 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 13:58:48.971322 == TX Byte 1 ==
6377 13:58:48.978171 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6378 13:58:48.981424 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6379 13:58:48.981529
6380 13:58:48.981612 [DATLAT]
6381 13:58:48.984947 Freq=400, CH0 RK0
6382 13:58:48.985054
6383 13:58:48.985135 DATLAT Default: 0xf
6384 13:58:48.988112 0, 0xFFFF, sum = 0
6385 13:58:48.988222 1, 0xFFFF, sum = 0
6386 13:58:48.991345 2, 0xFFFF, sum = 0
6387 13:58:48.991420 3, 0xFFFF, sum = 0
6388 13:58:48.994641 4, 0xFFFF, sum = 0
6389 13:58:48.994778 5, 0xFFFF, sum = 0
6390 13:58:48.998203 6, 0xFFFF, sum = 0
6391 13:58:48.998282 7, 0xFFFF, sum = 0
6392 13:58:49.001368 8, 0xFFFF, sum = 0
6393 13:58:49.001487 9, 0xFFFF, sum = 0
6394 13:58:49.005239 10, 0xFFFF, sum = 0
6395 13:58:49.008042 11, 0xFFFF, sum = 0
6396 13:58:49.008145 12, 0xFFFF, sum = 0
6397 13:58:49.011622 13, 0x0, sum = 1
6398 13:58:49.011710 14, 0x0, sum = 2
6399 13:58:49.011775 15, 0x0, sum = 3
6400 13:58:49.014864 16, 0x0, sum = 4
6401 13:58:49.014966 best_step = 14
6402 13:58:49.015062
6403 13:58:49.015154 ==
6404 13:58:49.018475 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 13:58:49.024904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 13:58:49.025015 ==
6407 13:58:49.025111 RX Vref Scan: 1
6408 13:58:49.025200
6409 13:58:49.027871 RX Vref 0 -> 0, step: 1
6410 13:58:49.027991
6411 13:58:49.031619 RX Delay -343 -> 252, step: 8
6412 13:58:49.031695
6413 13:58:49.034972 Set Vref, RX VrefLevel [Byte0]: 53
6414 13:58:49.038677 [Byte1]: 51
6415 13:58:49.038785
6416 13:58:49.041585 Final RX Vref Byte 0 = 53 to rank0
6417 13:58:49.045329 Final RX Vref Byte 1 = 51 to rank0
6418 13:58:49.048467 Final RX Vref Byte 0 = 53 to rank1
6419 13:58:49.051482 Final RX Vref Byte 1 = 51 to rank1==
6420 13:58:49.055355 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 13:58:49.058404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 13:58:49.061757 ==
6423 13:58:49.061863 DQS Delay:
6424 13:58:49.061956 DQS0 = 44, DQS1 = 60
6425 13:58:49.065483 DQM Delay:
6426 13:58:49.065577 DQM0 = 11, DQM1 = 16
6427 13:58:49.067988 DQ Delay:
6428 13:58:49.072007 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6429 13:58:49.072078 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6430 13:58:49.074736 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6431 13:58:49.078316 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6432 13:58:49.078422
6433 13:58:49.078514
6434 13:58:49.088260 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6435 13:58:49.091526 CH0 RK0: MR19=C0C, MR18=8E5C
6436 13:58:49.098639 CH0_RK0: MR19=0xC0C, MR18=0x8E5C, DQSOSC=392, MR23=63, INC=384, DEC=256
6437 13:58:49.098772 ==
6438 13:58:49.102000 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 13:58:49.104712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 13:58:49.104788 ==
6441 13:58:49.108085 [Gating] SW mode calibration
6442 13:58:49.115196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6443 13:58:49.118438 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6444 13:58:49.124738 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6445 13:58:49.128588 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 13:58:49.131606 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 13:58:49.138184 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 13:58:49.142105 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 13:58:49.144995 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 13:58:49.151696 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 13:58:49.155008 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 13:58:49.158494 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 13:58:49.161594 Total UI for P1: 0, mck2ui 16
6454 13:58:49.165187 best dqsien dly found for B0: ( 0, 14, 24)
6455 13:58:49.168766 Total UI for P1: 0, mck2ui 16
6456 13:58:49.172171 best dqsien dly found for B1: ( 0, 14, 24)
6457 13:58:49.175463 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6458 13:58:49.178695 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6459 13:58:49.178801
6460 13:58:49.181861 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6461 13:58:49.188579 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 13:58:49.188693 [Gating] SW calibration Done
6463 13:58:49.188786 ==
6464 13:58:49.191826 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 13:58:49.198839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 13:58:49.198916 ==
6467 13:58:49.198980 RX Vref Scan: 0
6468 13:58:49.199040
6469 13:58:49.201915 RX Vref 0 -> 0, step: 1
6470 13:58:49.202021
6471 13:58:49.205190 RX Delay -410 -> 252, step: 16
6472 13:58:49.208762 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6473 13:58:49.211886 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6474 13:58:49.218650 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6475 13:58:49.222077 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6476 13:58:49.225229 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6477 13:58:49.228871 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6478 13:58:49.235256 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6479 13:58:49.238493 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6480 13:58:49.241927 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6481 13:58:49.245433 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6482 13:58:49.252171 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6483 13:58:49.255204 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6484 13:58:49.258541 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6485 13:58:49.261919 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6486 13:58:49.268391 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6487 13:58:49.272173 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6488 13:58:49.272281 ==
6489 13:58:49.275071 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 13:58:49.279099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 13:58:49.279174 ==
6492 13:58:49.282286 DQS Delay:
6493 13:58:49.282363 DQS0 = 43, DQS1 = 51
6494 13:58:49.282426 DQM Delay:
6495 13:58:49.285238 DQM0 = 11, DQM1 = 10
6496 13:58:49.285313 DQ Delay:
6497 13:58:49.289169 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6498 13:58:49.292217 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6499 13:58:49.295319 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6500 13:58:49.298529 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6501 13:58:49.298603
6502 13:58:49.298693
6503 13:58:49.298820 ==
6504 13:58:49.302389 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 13:58:49.305857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 13:58:49.305956 ==
6507 13:58:49.306056
6508 13:58:49.306143
6509 13:58:49.308722 TX Vref Scan disable
6510 13:58:49.312139 == TX Byte 0 ==
6511 13:58:49.315583 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6512 13:58:49.318596 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6513 13:58:49.322747 == TX Byte 1 ==
6514 13:58:49.325594 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6515 13:58:49.328879 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6516 13:58:49.328982 ==
6517 13:58:49.332486 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 13:58:49.335631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 13:58:49.335701 ==
6520 13:58:49.335774
6521 13:58:49.335835
6522 13:58:49.339067 TX Vref Scan disable
6523 13:58:49.342222 == TX Byte 0 ==
6524 13:58:49.345390 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6525 13:58:49.348798 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6526 13:58:49.352613 == TX Byte 1 ==
6527 13:58:49.355716 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6528 13:58:49.358796 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6529 13:58:49.358899
6530 13:58:49.358963 [DATLAT]
6531 13:58:49.362211 Freq=400, CH0 RK1
6532 13:58:49.362313
6533 13:58:49.362400 DATLAT Default: 0xe
6534 13:58:49.365910 0, 0xFFFF, sum = 0
6535 13:58:49.366010 1, 0xFFFF, sum = 0
6536 13:58:49.368961 2, 0xFFFF, sum = 0
6537 13:58:49.369064 3, 0xFFFF, sum = 0
6538 13:58:49.372266 4, 0xFFFF, sum = 0
6539 13:58:49.375783 5, 0xFFFF, sum = 0
6540 13:58:49.375886 6, 0xFFFF, sum = 0
6541 13:58:49.378882 7, 0xFFFF, sum = 0
6542 13:58:49.378957 8, 0xFFFF, sum = 0
6543 13:58:49.382282 9, 0xFFFF, sum = 0
6544 13:58:49.382386 10, 0xFFFF, sum = 0
6545 13:58:49.385739 11, 0xFFFF, sum = 0
6546 13:58:49.385827 12, 0xFFFF, sum = 0
6547 13:58:49.389062 13, 0x0, sum = 1
6548 13:58:49.389137 14, 0x0, sum = 2
6549 13:58:49.392392 15, 0x0, sum = 3
6550 13:58:49.392498 16, 0x0, sum = 4
6551 13:58:49.392591 best_step = 14
6552 13:58:49.395611
6553 13:58:49.395716 ==
6554 13:58:49.398859 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 13:58:49.402402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 13:58:49.402486 ==
6557 13:58:49.402551 RX Vref Scan: 0
6558 13:58:49.402611
6559 13:58:49.405685 RX Vref 0 -> 0, step: 1
6560 13:58:49.405798
6561 13:58:49.409260 RX Delay -343 -> 252, step: 8
6562 13:58:49.416367 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6563 13:58:49.419575 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6564 13:58:49.422780 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6565 13:58:49.426324 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6566 13:58:49.432913 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6567 13:58:49.436284 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6568 13:58:49.439670 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6569 13:58:49.443047 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6570 13:58:49.449292 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6571 13:58:49.452664 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6572 13:58:49.456463 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6573 13:58:49.459947 iDelay=217, Bit 11, Center -52 (-287 ~ 184) 472
6574 13:58:49.466037 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6575 13:58:49.469396 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6576 13:58:49.472684 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6577 13:58:49.475936 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6578 13:58:49.479319 ==
6579 13:58:49.482829 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 13:58:49.486191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 13:58:49.486288 ==
6582 13:58:49.486352 DQS Delay:
6583 13:58:49.489917 DQS0 = 48, DQS1 = 56
6584 13:58:49.489997 DQM Delay:
6585 13:58:49.492818 DQM0 = 13, DQM1 = 11
6586 13:58:49.492939 DQ Delay:
6587 13:58:49.495959 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6588 13:58:49.499844 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6589 13:58:49.502960 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6590 13:58:49.506447 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6591 13:58:49.506566
6592 13:58:49.506671
6593 13:58:49.513264 [DQSOSCAuto] RK1, (LSB)MR18= 0x9e70, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6594 13:58:49.515987 CH0 RK1: MR19=C0C, MR18=9E70
6595 13:58:49.522849 CH0_RK1: MR19=0xC0C, MR18=0x9E70, DQSOSC=390, MR23=63, INC=388, DEC=258
6596 13:58:49.526140 [RxdqsGatingPostProcess] freq 400
6597 13:58:49.529444 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6598 13:58:49.532958 best DQS0 dly(2T, 0.5T) = (0, 10)
6599 13:58:49.536249 best DQS1 dly(2T, 0.5T) = (0, 10)
6600 13:58:49.539575 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6601 13:58:49.543082 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6602 13:58:49.546023 best DQS0 dly(2T, 0.5T) = (0, 10)
6603 13:58:49.549343 best DQS1 dly(2T, 0.5T) = (0, 10)
6604 13:58:49.553363 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6605 13:58:49.556035 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6606 13:58:49.559352 Pre-setting of DQS Precalculation
6607 13:58:49.562797 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6608 13:58:49.562878 ==
6609 13:58:49.566187 Dram Type= 6, Freq= 0, CH_1, rank 0
6610 13:58:49.572778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 13:58:49.572860 ==
6612 13:58:49.576687 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6613 13:58:49.583206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6614 13:58:49.586435 [CA 0] Center 36 (8~64) winsize 57
6615 13:58:49.589446 [CA 1] Center 36 (8~64) winsize 57
6616 13:58:49.592714 [CA 2] Center 36 (8~64) winsize 57
6617 13:58:49.596559 [CA 3] Center 36 (8~64) winsize 57
6618 13:58:49.599770 [CA 4] Center 36 (8~64) winsize 57
6619 13:58:49.602958 [CA 5] Center 36 (8~64) winsize 57
6620 13:58:49.603039
6621 13:58:49.606607 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6622 13:58:49.606690
6623 13:58:49.610012 [CATrainingPosCal] consider 1 rank data
6624 13:58:49.613154 u2DelayCellTimex100 = 270/100 ps
6625 13:58:49.616653 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 13:58:49.619785 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 13:58:49.623676 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 13:58:49.626190 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 13:58:49.629967 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 13:58:49.633213 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 13:58:49.633322
6632 13:58:49.640188 CA PerBit enable=1, Macro0, CA PI delay=36
6633 13:58:49.640284
6634 13:58:49.640348 [CBTSetCACLKResult] CA Dly = 36
6635 13:58:49.643071 CS Dly: 1 (0~32)
6636 13:58:49.643152 ==
6637 13:58:49.646379 Dram Type= 6, Freq= 0, CH_1, rank 1
6638 13:58:49.649964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 13:58:49.650046 ==
6640 13:58:49.656603 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6641 13:58:49.663057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6642 13:58:49.666383 [CA 0] Center 36 (8~64) winsize 57
6643 13:58:49.670388 [CA 1] Center 36 (8~64) winsize 57
6644 13:58:49.670487 [CA 2] Center 36 (8~64) winsize 57
6645 13:58:49.673213 [CA 3] Center 36 (8~64) winsize 57
6646 13:58:49.676836 [CA 4] Center 36 (8~64) winsize 57
6647 13:58:49.679885 [CA 5] Center 36 (8~64) winsize 57
6648 13:58:49.679966
6649 13:58:49.683017 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6650 13:58:49.683098
6651 13:58:49.689737 [CATrainingPosCal] consider 2 rank data
6652 13:58:49.689819 u2DelayCellTimex100 = 270/100 ps
6653 13:58:49.693193 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 13:58:49.700366 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 13:58:49.703373 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 13:58:49.706802 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 13:58:49.709901 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 13:58:49.713107 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 13:58:49.713212
6660 13:58:49.716652 CA PerBit enable=1, Macro0, CA PI delay=36
6661 13:58:49.716729
6662 13:58:49.720120 [CBTSetCACLKResult] CA Dly = 36
6663 13:58:49.720222 CS Dly: 1 (0~32)
6664 13:58:49.720326
6665 13:58:49.723226 ----->DramcWriteLeveling(PI) begin...
6666 13:58:49.726886 ==
6667 13:58:49.730353 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 13:58:49.733587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 13:58:49.733684 ==
6670 13:58:49.736884 Write leveling (Byte 0): 40 => 8
6671 13:58:49.740490 Write leveling (Byte 1): 40 => 8
6672 13:58:49.740560 DramcWriteLeveling(PI) end<-----
6673 13:58:49.743581
6674 13:58:49.743648 ==
6675 13:58:49.746818 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 13:58:49.750005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 13:58:49.750106 ==
6678 13:58:49.753599 [Gating] SW mode calibration
6679 13:58:49.760442 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6680 13:58:49.763505 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6681 13:58:49.770127 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6682 13:58:49.773542 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 13:58:49.776883 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 13:58:49.784015 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 13:58:49.787090 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 13:58:49.790096 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 13:58:49.797115 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 13:58:49.800372 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 13:58:49.803719 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 13:58:49.806857 Total UI for P1: 0, mck2ui 16
6691 13:58:49.810450 best dqsien dly found for B0: ( 0, 14, 24)
6692 13:58:49.814090 Total UI for P1: 0, mck2ui 16
6693 13:58:49.817257 best dqsien dly found for B1: ( 0, 14, 24)
6694 13:58:49.820213 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6695 13:58:49.823996 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6696 13:58:49.824081
6697 13:58:49.827122 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6698 13:58:49.833854 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 13:58:49.833954 [Gating] SW calibration Done
6700 13:58:49.834033 ==
6701 13:58:49.837035 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 13:58:49.843594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 13:58:49.843675 ==
6704 13:58:49.843739 RX Vref Scan: 0
6705 13:58:49.843800
6706 13:58:49.846957 RX Vref 0 -> 0, step: 1
6707 13:58:49.847065
6708 13:58:49.850344 RX Delay -410 -> 252, step: 16
6709 13:58:49.853545 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6710 13:58:49.857145 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6711 13:58:49.863591 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6712 13:58:49.867173 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6713 13:58:49.870104 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6714 13:58:49.873698 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6715 13:58:49.880466 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6716 13:58:49.883488 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6717 13:58:49.887084 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6718 13:58:49.890539 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6719 13:58:49.896802 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6720 13:58:49.900172 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6721 13:58:49.903873 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6722 13:58:49.907243 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6723 13:58:49.913832 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6724 13:58:49.917299 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6725 13:58:49.917381 ==
6726 13:58:49.920486 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 13:58:49.924010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 13:58:49.924092 ==
6729 13:58:49.927613 DQS Delay:
6730 13:58:49.927693 DQS0 = 51, DQS1 = 59
6731 13:58:49.927758 DQM Delay:
6732 13:58:49.930627 DQM0 = 18, DQM1 = 17
6733 13:58:49.930744 DQ Delay:
6734 13:58:49.933907 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6735 13:58:49.936829 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6736 13:58:49.940970 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6737 13:58:49.943633 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6738 13:58:49.943711
6739 13:58:49.943782
6740 13:58:49.943843 ==
6741 13:58:49.946877 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 13:58:49.953699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 13:58:49.953781 ==
6744 13:58:49.953845
6745 13:58:49.953905
6746 13:58:49.953962 TX Vref Scan disable
6747 13:58:49.957001 == TX Byte 0 ==
6748 13:58:49.960508 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6749 13:58:49.963299 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6750 13:58:49.967096 == TX Byte 1 ==
6751 13:58:49.970240 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 13:58:49.973459 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 13:58:49.973584 ==
6754 13:58:49.976929 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 13:58:49.983249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 13:58:49.983331 ==
6757 13:58:49.983396
6758 13:58:49.983455
6759 13:58:49.983512 TX Vref Scan disable
6760 13:58:49.986928 == TX Byte 0 ==
6761 13:58:49.990109 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 13:58:49.993261 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 13:58:49.997170 == TX Byte 1 ==
6764 13:58:50.000025 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 13:58:50.003654 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 13:58:50.003735
6767 13:58:50.006802 [DATLAT]
6768 13:58:50.006883 Freq=400, CH1 RK0
6769 13:58:50.006948
6770 13:58:50.010019 DATLAT Default: 0xf
6771 13:58:50.010100 0, 0xFFFF, sum = 0
6772 13:58:50.013704 1, 0xFFFF, sum = 0
6773 13:58:50.013786 2, 0xFFFF, sum = 0
6774 13:58:50.016725 3, 0xFFFF, sum = 0
6775 13:58:50.016839 4, 0xFFFF, sum = 0
6776 13:58:50.020404 5, 0xFFFF, sum = 0
6777 13:58:50.020487 6, 0xFFFF, sum = 0
6778 13:58:50.023541 7, 0xFFFF, sum = 0
6779 13:58:50.023622 8, 0xFFFF, sum = 0
6780 13:58:50.026650 9, 0xFFFF, sum = 0
6781 13:58:50.026762 10, 0xFFFF, sum = 0
6782 13:58:50.029965 11, 0xFFFF, sum = 0
6783 13:58:50.033652 12, 0xFFFF, sum = 0
6784 13:58:50.033735 13, 0x0, sum = 1
6785 13:58:50.036874 14, 0x0, sum = 2
6786 13:58:50.036956 15, 0x0, sum = 3
6787 13:58:50.037022 16, 0x0, sum = 4
6788 13:58:50.040094 best_step = 14
6789 13:58:50.040175
6790 13:58:50.040244 ==
6791 13:58:50.043181 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 13:58:50.046660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 13:58:50.046767 ==
6794 13:58:50.050139 RX Vref Scan: 1
6795 13:58:50.050220
6796 13:58:50.050284 RX Vref 0 -> 0, step: 1
6797 13:58:50.050345
6798 13:58:50.053508 RX Delay -359 -> 252, step: 8
6799 13:58:50.053589
6800 13:58:50.056958 Set Vref, RX VrefLevel [Byte0]: 58
6801 13:58:50.060007 [Byte1]: 54
6802 13:58:50.065405
6803 13:58:50.065485 Final RX Vref Byte 0 = 58 to rank0
6804 13:58:50.068816 Final RX Vref Byte 1 = 54 to rank0
6805 13:58:50.071800 Final RX Vref Byte 0 = 58 to rank1
6806 13:58:50.075318 Final RX Vref Byte 1 = 54 to rank1==
6807 13:58:50.078566 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 13:58:50.084939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 13:58:50.085021 ==
6810 13:58:50.085086 DQS Delay:
6811 13:58:50.088089 DQS0 = 48, DQS1 = 60
6812 13:58:50.088161 DQM Delay:
6813 13:58:50.088222 DQM0 = 12, DQM1 = 13
6814 13:58:50.091647 DQ Delay:
6815 13:58:50.095074 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6816 13:58:50.095155 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =12
6817 13:58:50.098230 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6818 13:58:50.101681 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6819 13:58:50.101758
6820 13:58:50.104720
6821 13:58:50.111575 [DQSOSCAuto] RK0, (LSB)MR18= 0x943c, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
6822 13:58:50.115059 CH1 RK0: MR19=C0C, MR18=943C
6823 13:58:50.121742 CH1_RK0: MR19=0xC0C, MR18=0x943C, DQSOSC=391, MR23=63, INC=386, DEC=257
6824 13:58:50.121826 ==
6825 13:58:50.125376 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 13:58:50.128263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 13:58:50.128333 ==
6828 13:58:50.131817 [Gating] SW mode calibration
6829 13:58:50.138277 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6830 13:58:50.141666 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6831 13:58:50.148537 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6832 13:58:50.151715 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6833 13:58:50.155353 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6834 13:58:50.161920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 13:58:50.165414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 13:58:50.168560 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 13:58:50.175230 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 13:58:50.179158 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 13:58:50.182181 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 13:58:50.185094 Total UI for P1: 0, mck2ui 16
6841 13:58:50.188700 best dqsien dly found for B0: ( 0, 14, 24)
6842 13:58:50.192130 Total UI for P1: 0, mck2ui 16
6843 13:58:50.195568 best dqsien dly found for B1: ( 0, 14, 24)
6844 13:58:50.198451 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6845 13:58:50.201552 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6846 13:58:50.201631
6847 13:58:50.208400 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6848 13:58:50.212043 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 13:58:50.212117 [Gating] SW calibration Done
6850 13:58:50.214933 ==
6851 13:58:50.218604 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 13:58:50.221869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 13:58:50.221944 ==
6854 13:58:50.222014 RX Vref Scan: 0
6855 13:58:50.222073
6856 13:58:50.225020 RX Vref 0 -> 0, step: 1
6857 13:58:50.225094
6858 13:58:50.228362 RX Delay -410 -> 252, step: 16
6859 13:58:50.231941 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6860 13:58:50.235162 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6861 13:58:50.241617 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6862 13:58:50.245090 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6863 13:58:50.248659 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6864 13:58:50.252068 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6865 13:58:50.258849 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6866 13:58:50.261625 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6867 13:58:50.265041 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6868 13:58:50.268156 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6869 13:58:50.274836 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6870 13:58:50.278371 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6871 13:58:50.281690 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6872 13:58:50.284930 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6873 13:58:50.291810 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6874 13:58:50.295252 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6875 13:58:50.295334 ==
6876 13:58:50.298546 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 13:58:50.302610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 13:58:50.302683 ==
6879 13:58:50.305450 DQS Delay:
6880 13:58:50.305528 DQS0 = 43, DQS1 = 59
6881 13:58:50.308798 DQM Delay:
6882 13:58:50.308876 DQM0 = 10, DQM1 = 19
6883 13:58:50.308962 DQ Delay:
6884 13:58:50.311889 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6885 13:58:50.315079 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6886 13:58:50.318490 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6887 13:58:50.321903 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =32
6888 13:58:50.321977
6889 13:58:50.322045
6890 13:58:50.322104 ==
6891 13:58:50.325158 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 13:58:50.331530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 13:58:50.331603 ==
6894 13:58:50.331667
6895 13:58:50.331726
6896 13:58:50.331793 TX Vref Scan disable
6897 13:58:50.334946 == TX Byte 0 ==
6898 13:58:50.338315 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6899 13:58:50.341616 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6900 13:58:50.344944 == TX Byte 1 ==
6901 13:58:50.348638 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6902 13:58:50.352071 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6903 13:58:50.352141 ==
6904 13:58:50.355366 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 13:58:50.361790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 13:58:50.361866 ==
6907 13:58:50.361929
6908 13:58:50.361987
6909 13:58:50.362052 TX Vref Scan disable
6910 13:58:50.365279 == TX Byte 0 ==
6911 13:58:50.368922 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6912 13:58:50.372336 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6913 13:58:50.375237 == TX Byte 1 ==
6914 13:58:50.378711 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6915 13:58:50.382028 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6916 13:58:50.382101
6917 13:58:50.385429 [DATLAT]
6918 13:58:50.385506 Freq=400, CH1 RK1
6919 13:58:50.385576
6920 13:58:50.389223 DATLAT Default: 0xe
6921 13:58:50.389296 0, 0xFFFF, sum = 0
6922 13:58:50.392137 1, 0xFFFF, sum = 0
6923 13:58:50.392211 2, 0xFFFF, sum = 0
6924 13:58:50.395524 3, 0xFFFF, sum = 0
6925 13:58:50.395603 4, 0xFFFF, sum = 0
6926 13:58:50.398839 5, 0xFFFF, sum = 0
6927 13:58:50.398912 6, 0xFFFF, sum = 0
6928 13:58:50.402157 7, 0xFFFF, sum = 0
6929 13:58:50.402240 8, 0xFFFF, sum = 0
6930 13:58:50.405258 9, 0xFFFF, sum = 0
6931 13:58:50.405331 10, 0xFFFF, sum = 0
6932 13:58:50.408629 11, 0xFFFF, sum = 0
6933 13:58:50.408704 12, 0xFFFF, sum = 0
6934 13:58:50.412414 13, 0x0, sum = 1
6935 13:58:50.412486 14, 0x0, sum = 2
6936 13:58:50.415636 15, 0x0, sum = 3
6937 13:58:50.415707 16, 0x0, sum = 4
6938 13:58:50.419191 best_step = 14
6939 13:58:50.419262
6940 13:58:50.419322 ==
6941 13:58:50.422052 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 13:58:50.425588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 13:58:50.425668 ==
6944 13:58:50.429008 RX Vref Scan: 0
6945 13:58:50.429086
6946 13:58:50.429147 RX Vref 0 -> 0, step: 1
6947 13:58:50.429205
6948 13:58:50.431967 RX Delay -359 -> 252, step: 8
6949 13:58:50.440304 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6950 13:58:50.443667 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6951 13:58:50.446968 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6952 13:58:50.450263 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6953 13:58:50.457041 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6954 13:58:50.460739 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6955 13:58:50.463943 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6956 13:58:50.466865 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6957 13:58:50.473473 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6958 13:58:50.476980 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6959 13:58:50.480115 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6960 13:58:50.483583 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6961 13:58:50.490469 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6962 13:58:50.493353 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6963 13:58:50.496767 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6964 13:58:50.503363 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6965 13:58:50.503445 ==
6966 13:58:50.506580 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 13:58:50.510246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 13:58:50.510326 ==
6969 13:58:50.510389 DQS Delay:
6970 13:58:50.513380 DQS0 = 52, DQS1 = 56
6971 13:58:50.513458 DQM Delay:
6972 13:58:50.516852 DQM0 = 13, DQM1 = 9
6973 13:58:50.516923 DQ Delay:
6974 13:58:50.520066 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6975 13:58:50.523668 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6976 13:58:50.527340 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6977 13:58:50.530317 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6978 13:58:50.530395
6979 13:58:50.530458
6980 13:58:50.536651 [DQSOSCAuto] RK1, (LSB)MR18= 0x7e93, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 393 ps
6981 13:58:50.540475 CH1 RK1: MR19=C0C, MR18=7E93
6982 13:58:50.546699 CH1_RK1: MR19=0xC0C, MR18=0x7E93, DQSOSC=391, MR23=63, INC=386, DEC=257
6983 13:58:50.550180 [RxdqsGatingPostProcess] freq 400
6984 13:58:50.553600 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6985 13:58:50.556814 best DQS0 dly(2T, 0.5T) = (0, 10)
6986 13:58:50.560234 best DQS1 dly(2T, 0.5T) = (0, 10)
6987 13:58:50.563497 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6988 13:58:50.566849 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6989 13:58:50.570116 best DQS0 dly(2T, 0.5T) = (0, 10)
6990 13:58:50.573558 best DQS1 dly(2T, 0.5T) = (0, 10)
6991 13:58:50.576837 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6992 13:58:50.580164 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6993 13:58:50.583635 Pre-setting of DQS Precalculation
6994 13:58:50.586545 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6995 13:58:50.596843 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6996 13:58:50.603230 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6997 13:58:50.603308
6998 13:58:50.603389
6999 13:58:50.606651 [Calibration Summary] 800 Mbps
7000 13:58:50.606782 CH 0, Rank 0
7001 13:58:50.609817 SW Impedance : PASS
7002 13:58:50.609891 DUTY Scan : NO K
7003 13:58:50.613019 ZQ Calibration : PASS
7004 13:58:50.616842 Jitter Meter : NO K
7005 13:58:50.616923 CBT Training : PASS
7006 13:58:50.620226 Write leveling : PASS
7007 13:58:50.623102 RX DQS gating : PASS
7008 13:58:50.623212 RX DQ/DQS(RDDQC) : PASS
7009 13:58:50.626341 TX DQ/DQS : PASS
7010 13:58:50.629693 RX DATLAT : PASS
7011 13:58:50.629767 RX DQ/DQS(Engine): PASS
7012 13:58:50.633289 TX OE : NO K
7013 13:58:50.633367 All Pass.
7014 13:58:50.633447
7015 13:58:50.636176 CH 0, Rank 1
7016 13:58:50.636272 SW Impedance : PASS
7017 13:58:50.639620 DUTY Scan : NO K
7018 13:58:50.643085 ZQ Calibration : PASS
7019 13:58:50.643166 Jitter Meter : NO K
7020 13:58:50.646270 CBT Training : PASS
7021 13:58:50.646369 Write leveling : NO K
7022 13:58:50.649789 RX DQS gating : PASS
7023 13:58:50.652933 RX DQ/DQS(RDDQC) : PASS
7024 13:58:50.653014 TX DQ/DQS : PASS
7025 13:58:50.656240 RX DATLAT : PASS
7026 13:58:50.659824 RX DQ/DQS(Engine): PASS
7027 13:58:50.659904 TX OE : NO K
7028 13:58:50.662977 All Pass.
7029 13:58:50.663083
7030 13:58:50.663183 CH 1, Rank 0
7031 13:58:50.666187 SW Impedance : PASS
7032 13:58:50.666288 DUTY Scan : NO K
7033 13:58:50.670070 ZQ Calibration : PASS
7034 13:58:50.672853 Jitter Meter : NO K
7035 13:58:50.672969 CBT Training : PASS
7036 13:58:50.676654 Write leveling : PASS
7037 13:58:50.679922 RX DQS gating : PASS
7038 13:58:50.680007 RX DQ/DQS(RDDQC) : PASS
7039 13:58:50.683416 TX DQ/DQS : PASS
7040 13:58:50.683495 RX DATLAT : PASS
7041 13:58:50.686520 RX DQ/DQS(Engine): PASS
7042 13:58:50.689859 TX OE : NO K
7043 13:58:50.689966 All Pass.
7044 13:58:50.690039
7045 13:58:50.690099 CH 1, Rank 1
7046 13:58:50.692923 SW Impedance : PASS
7047 13:58:50.696301 DUTY Scan : NO K
7048 13:58:50.696378 ZQ Calibration : PASS
7049 13:58:50.699949 Jitter Meter : NO K
7050 13:58:50.703002 CBT Training : PASS
7051 13:58:50.703079 Write leveling : NO K
7052 13:58:50.706325 RX DQS gating : PASS
7053 13:58:50.709819 RX DQ/DQS(RDDQC) : PASS
7054 13:58:50.709890 TX DQ/DQS : PASS
7055 13:58:50.713251 RX DATLAT : PASS
7056 13:58:50.716416 RX DQ/DQS(Engine): PASS
7057 13:58:50.716491 TX OE : NO K
7058 13:58:50.716562 All Pass.
7059 13:58:50.716646
7060 13:58:50.720270 DramC Write-DBI off
7061 13:58:50.723372 PER_BANK_REFRESH: Hybrid Mode
7062 13:58:50.723448 TX_TRACKING: ON
7063 13:58:50.733171 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7064 13:58:50.737061 [FAST_K] Save calibration result to emmc
7065 13:58:50.740641 dramc_set_vcore_voltage set vcore to 725000
7066 13:58:50.743187 Read voltage for 1600, 0
7067 13:58:50.743265 Vio18 = 0
7068 13:58:50.747060 Vcore = 725000
7069 13:58:50.747137 Vdram = 0
7070 13:58:50.747225 Vddq = 0
7071 13:58:50.747305 Vmddr = 0
7072 13:58:50.753086 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7073 13:58:50.756981 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7074 13:58:50.760386 MEM_TYPE=3, freq_sel=13
7075 13:58:50.763275 sv_algorithm_assistance_LP4_3733
7076 13:58:50.766649 ============ PULL DRAM RESETB DOWN ============
7077 13:58:50.773593 ========== PULL DRAM RESETB DOWN end =========
7078 13:58:50.776828 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7079 13:58:50.780319 ===================================
7080 13:58:50.783519 LPDDR4 DRAM CONFIGURATION
7081 13:58:50.786958 ===================================
7082 13:58:50.787041 EX_ROW_EN[0] = 0x0
7083 13:58:50.790215 EX_ROW_EN[1] = 0x0
7084 13:58:50.790289 LP4Y_EN = 0x0
7085 13:58:50.793561 WORK_FSP = 0x1
7086 13:58:50.793637 WL = 0x5
7087 13:58:50.796791 RL = 0x5
7088 13:58:50.796869 BL = 0x2
7089 13:58:50.799979 RPST = 0x0
7090 13:58:50.800062 RD_PRE = 0x0
7091 13:58:50.803216 WR_PRE = 0x1
7092 13:58:50.803323 WR_PST = 0x1
7093 13:58:50.806690 DBI_WR = 0x0
7094 13:58:50.806811 DBI_RD = 0x0
7095 13:58:50.810313 OTF = 0x1
7096 13:58:50.813438 ===================================
7097 13:58:50.816995 ===================================
7098 13:58:50.817073 ANA top config
7099 13:58:50.820345 ===================================
7100 13:58:50.823790 DLL_ASYNC_EN = 0
7101 13:58:50.826854 ALL_SLAVE_EN = 0
7102 13:58:50.830703 NEW_RANK_MODE = 1
7103 13:58:50.830818 DLL_IDLE_MODE = 1
7104 13:58:50.833429 LP45_APHY_COMB_EN = 1
7105 13:58:50.837100 TX_ODT_DIS = 0
7106 13:58:50.840036 NEW_8X_MODE = 1
7107 13:58:50.843732 ===================================
7108 13:58:50.846663 ===================================
7109 13:58:50.850232 data_rate = 3200
7110 13:58:50.850304 CKR = 1
7111 13:58:50.853536 DQ_P2S_RATIO = 8
7112 13:58:50.856726 ===================================
7113 13:58:50.860070 CA_P2S_RATIO = 8
7114 13:58:50.863619 DQ_CA_OPEN = 0
7115 13:58:50.867246 DQ_SEMI_OPEN = 0
7116 13:58:50.870205 CA_SEMI_OPEN = 0
7117 13:58:50.870277 CA_FULL_RATE = 0
7118 13:58:50.873761 DQ_CKDIV4_EN = 0
7119 13:58:50.877301 CA_CKDIV4_EN = 0
7120 13:58:50.880439 CA_PREDIV_EN = 0
7121 13:58:50.883538 PH8_DLY = 12
7122 13:58:50.883613 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7123 13:58:50.886869 DQ_AAMCK_DIV = 4
7124 13:58:50.890209 CA_AAMCK_DIV = 4
7125 13:58:50.893835 CA_ADMCK_DIV = 4
7126 13:58:50.896718 DQ_TRACK_CA_EN = 0
7127 13:58:50.900523 CA_PICK = 1600
7128 13:58:50.903457 CA_MCKIO = 1600
7129 13:58:50.903535 MCKIO_SEMI = 0
7130 13:58:50.907108 PLL_FREQ = 3068
7131 13:58:50.910215 DQ_UI_PI_RATIO = 32
7132 13:58:50.913436 CA_UI_PI_RATIO = 0
7133 13:58:50.916739 ===================================
7134 13:58:50.920544 ===================================
7135 13:58:50.923767 memory_type:LPDDR4
7136 13:58:50.923840 GP_NUM : 10
7137 13:58:50.927060 SRAM_EN : 1
7138 13:58:50.930444 MD32_EN : 0
7139 13:58:50.933539 ===================================
7140 13:58:50.933615 [ANA_INIT] >>>>>>>>>>>>>>
7141 13:58:50.936925 <<<<<< [CONFIGURE PHASE]: ANA_TX
7142 13:58:50.940499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7143 13:58:50.943606 ===================================
7144 13:58:50.947316 data_rate = 3200,PCW = 0X7600
7145 13:58:50.950428 ===================================
7146 13:58:50.953786 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7147 13:58:50.961127 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7148 13:58:50.963991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 13:58:50.970833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7150 13:58:50.974062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7151 13:58:50.977633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7152 13:58:50.977716 [ANA_INIT] flow start
7153 13:58:50.980516 [ANA_INIT] PLL >>>>>>>>
7154 13:58:50.984164 [ANA_INIT] PLL <<<<<<<<
7155 13:58:50.984265 [ANA_INIT] MIDPI >>>>>>>>
7156 13:58:50.987565 [ANA_INIT] MIDPI <<<<<<<<
7157 13:58:50.990298 [ANA_INIT] DLL >>>>>>>>
7158 13:58:50.990374 [ANA_INIT] DLL <<<<<<<<
7159 13:58:50.993777 [ANA_INIT] flow end
7160 13:58:50.997286 ============ LP4 DIFF to SE enter ============
7161 13:58:51.000454 ============ LP4 DIFF to SE exit ============
7162 13:58:51.004237 [ANA_INIT] <<<<<<<<<<<<<
7163 13:58:51.007288 [Flow] Enable top DCM control >>>>>
7164 13:58:51.010762 [Flow] Enable top DCM control <<<<<
7165 13:58:51.013690 Enable DLL master slave shuffle
7166 13:58:51.020597 ==============================================================
7167 13:58:51.020678 Gating Mode config
7168 13:58:51.027323 ==============================================================
7169 13:58:51.027401 Config description:
7170 13:58:51.037359 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7171 13:58:51.043996 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7172 13:58:51.050788 SELPH_MODE 0: By rank 1: By Phase
7173 13:58:51.054082 ==============================================================
7174 13:58:51.057276 GAT_TRACK_EN = 1
7175 13:58:51.060914 RX_GATING_MODE = 2
7176 13:58:51.063710 RX_GATING_TRACK_MODE = 2
7177 13:58:51.067547 SELPH_MODE = 1
7178 13:58:51.070591 PICG_EARLY_EN = 1
7179 13:58:51.074351 VALID_LAT_VALUE = 1
7180 13:58:51.077454 ==============================================================
7181 13:58:51.084320 Enter into Gating configuration >>>>
7182 13:58:51.084436 Exit from Gating configuration <<<<
7183 13:58:51.087332 Enter into DVFS_PRE_config >>>>>
7184 13:58:51.100899 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7185 13:58:51.104433 Exit from DVFS_PRE_config <<<<<
7186 13:58:51.107587 Enter into PICG configuration >>>>
7187 13:58:51.107662 Exit from PICG configuration <<<<
7188 13:58:51.110873 [RX_INPUT] configuration >>>>>
7189 13:58:51.114175 [RX_INPUT] configuration <<<<<
7190 13:58:51.120692 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7191 13:58:51.123942 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7192 13:58:51.130770 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 13:58:51.137611 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 13:58:51.144374 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7195 13:58:51.150968 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7196 13:58:51.153972 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7197 13:58:51.157387 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7198 13:58:51.160820 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7199 13:58:51.167975 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7200 13:58:51.170819 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7201 13:58:51.174119 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 13:58:51.177771 ===================================
7203 13:58:51.180751 LPDDR4 DRAM CONFIGURATION
7204 13:58:51.184378 ===================================
7205 13:58:51.184456 EX_ROW_EN[0] = 0x0
7206 13:58:51.187656 EX_ROW_EN[1] = 0x0
7207 13:58:51.190875 LP4Y_EN = 0x0
7208 13:58:51.190981 WORK_FSP = 0x1
7209 13:58:51.194208 WL = 0x5
7210 13:58:51.194311 RL = 0x5
7211 13:58:51.197566 BL = 0x2
7212 13:58:51.197665 RPST = 0x0
7213 13:58:51.200847 RD_PRE = 0x0
7214 13:58:51.200943 WR_PRE = 0x1
7215 13:58:51.204372 WR_PST = 0x1
7216 13:58:51.204479 DBI_WR = 0x0
7217 13:58:51.207622 DBI_RD = 0x0
7218 13:58:51.207768 OTF = 0x1
7219 13:58:51.211665 ===================================
7220 13:58:51.214469 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7221 13:58:51.220913 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7222 13:58:51.224113 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7223 13:58:51.227730 ===================================
7224 13:58:51.230872 LPDDR4 DRAM CONFIGURATION
7225 13:58:51.234348 ===================================
7226 13:58:51.234433 EX_ROW_EN[0] = 0x10
7227 13:58:51.237749 EX_ROW_EN[1] = 0x0
7228 13:58:51.237830 LP4Y_EN = 0x0
7229 13:58:51.241178 WORK_FSP = 0x1
7230 13:58:51.241259 WL = 0x5
7231 13:58:51.244296 RL = 0x5
7232 13:58:51.244377 BL = 0x2
7233 13:58:51.248110 RPST = 0x0
7234 13:58:51.248191 RD_PRE = 0x0
7235 13:58:51.250957 WR_PRE = 0x1
7236 13:58:51.254552 WR_PST = 0x1
7237 13:58:51.254649 DBI_WR = 0x0
7238 13:58:51.257882 DBI_RD = 0x0
7239 13:58:51.257963 OTF = 0x1
7240 13:58:51.261311 ===================================
7241 13:58:51.268113 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7242 13:58:51.268188 ==
7243 13:58:51.271295 Dram Type= 6, Freq= 0, CH_0, rank 0
7244 13:58:51.274583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7245 13:58:51.274658 ==
7246 13:58:51.277802 [Duty_Offset_Calibration]
7247 13:58:51.277873 B0:2 B1:-1 CA:1
7248 13:58:51.277940
7249 13:58:51.280954 [DutyScan_Calibration_Flow] k_type=0
7250 13:58:51.291438
7251 13:58:51.291524 ==CLK 0==
7252 13:58:51.294934 Final CLK duty delay cell = -4
7253 13:58:51.298415 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7254 13:58:51.301757 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7255 13:58:51.304857 [-4] AVG Duty = 4937%(X100)
7256 13:58:51.304933
7257 13:58:51.308172 CH0 CLK Duty spec in!! Max-Min= 187%
7258 13:58:51.311792 [DutyScan_Calibration_Flow] ====Done====
7259 13:58:51.311865
7260 13:58:51.314892 [DutyScan_Calibration_Flow] k_type=1
7261 13:58:51.331111
7262 13:58:51.331189 ==DQS 0 ==
7263 13:58:51.334583 Final DQS duty delay cell = 0
7264 13:58:51.337448 [0] MAX Duty = 5125%(X100), DQS PI = 20
7265 13:58:51.340829 [0] MIN Duty = 5000%(X100), DQS PI = 14
7266 13:58:51.344452 [0] AVG Duty = 5062%(X100)
7267 13:58:51.344530
7268 13:58:51.344607 ==DQS 1 ==
7269 13:58:51.347587 Final DQS duty delay cell = -4
7270 13:58:51.351023 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7271 13:58:51.354768 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7272 13:58:51.358014 [-4] AVG Duty = 5046%(X100)
7273 13:58:51.358084
7274 13:58:51.360796 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7275 13:58:51.360879
7276 13:58:51.364546 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7277 13:58:51.367633 [DutyScan_Calibration_Flow] ====Done====
7278 13:58:51.367703
7279 13:58:51.371256 [DutyScan_Calibration_Flow] k_type=3
7280 13:58:51.388424
7281 13:58:51.388509 ==DQM 0 ==
7282 13:58:51.391913 Final DQM duty delay cell = 0
7283 13:58:51.395023 [0] MAX Duty = 5000%(X100), DQS PI = 20
7284 13:58:51.398421 [0] MIN Duty = 4875%(X100), DQS PI = 6
7285 13:58:51.398497 [0] AVG Duty = 4937%(X100)
7286 13:58:51.401517
7287 13:58:51.401588 ==DQM 1 ==
7288 13:58:51.404768 Final DQM duty delay cell = 0
7289 13:58:51.408145 [0] MAX Duty = 5187%(X100), DQS PI = 56
7290 13:58:51.411809 [0] MIN Duty = 4969%(X100), DQS PI = 18
7291 13:58:51.411883 [0] AVG Duty = 5078%(X100)
7292 13:58:51.415035
7293 13:58:51.418529 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7294 13:58:51.418612
7295 13:58:51.421786 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7296 13:58:51.424730 [DutyScan_Calibration_Flow] ====Done====
7297 13:58:51.424813
7298 13:58:51.428473 [DutyScan_Calibration_Flow] k_type=2
7299 13:58:51.444703
7300 13:58:51.444814 ==DQ 0 ==
7301 13:58:51.447894 Final DQ duty delay cell = -4
7302 13:58:51.451191 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7303 13:58:51.454662 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7304 13:58:51.458013 [-4] AVG Duty = 4922%(X100)
7305 13:58:51.458085
7306 13:58:51.458146 ==DQ 1 ==
7307 13:58:51.461121 Final DQ duty delay cell = 0
7308 13:58:51.465048 [0] MAX Duty = 5031%(X100), DQS PI = 30
7309 13:58:51.467929 [0] MIN Duty = 4907%(X100), DQS PI = 18
7310 13:58:51.467998 [0] AVG Duty = 4969%(X100)
7311 13:58:51.471150
7312 13:58:51.474476 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7313 13:58:51.474545
7314 13:58:51.477831 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7315 13:58:51.481248 [DutyScan_Calibration_Flow] ====Done====
7316 13:58:51.481316 ==
7317 13:58:51.485179 Dram Type= 6, Freq= 0, CH_1, rank 0
7318 13:58:51.487983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7319 13:58:51.488063 ==
7320 13:58:51.491822 [Duty_Offset_Calibration]
7321 13:58:51.491894 B0:1 B1:1 CA:2
7322 13:58:51.491955
7323 13:58:51.494780 [DutyScan_Calibration_Flow] k_type=0
7324 13:58:51.505111
7325 13:58:51.505186 ==CLK 0==
7326 13:58:51.508753 Final CLK duty delay cell = 0
7327 13:58:51.511638 [0] MAX Duty = 5187%(X100), DQS PI = 24
7328 13:58:51.514905 [0] MIN Duty = 4938%(X100), DQS PI = 48
7329 13:58:51.514973 [0] AVG Duty = 5062%(X100)
7330 13:58:51.518529
7331 13:58:51.521839 CH1 CLK Duty spec in!! Max-Min= 249%
7332 13:58:51.525339 [DutyScan_Calibration_Flow] ====Done====
7333 13:58:51.525411
7334 13:58:51.528615 [DutyScan_Calibration_Flow] k_type=1
7335 13:58:51.544783
7336 13:58:51.544868 ==DQS 0 ==
7337 13:58:51.548753 Final DQS duty delay cell = 0
7338 13:58:51.551270 [0] MAX Duty = 5062%(X100), DQS PI = 22
7339 13:58:51.554776 [0] MIN Duty = 4813%(X100), DQS PI = 52
7340 13:58:51.558099 [0] AVG Duty = 4937%(X100)
7341 13:58:51.558173
7342 13:58:51.558233 ==DQS 1 ==
7343 13:58:51.561352 Final DQS duty delay cell = 0
7344 13:58:51.564590 [0] MAX Duty = 5062%(X100), DQS PI = 56
7345 13:58:51.568100 [0] MIN Duty = 4938%(X100), DQS PI = 12
7346 13:58:51.571529 [0] AVG Duty = 5000%(X100)
7347 13:58:51.571600
7348 13:58:51.574657 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7349 13:58:51.574731
7350 13:58:51.578098 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7351 13:58:51.581348 [DutyScan_Calibration_Flow] ====Done====
7352 13:58:51.581419
7353 13:58:51.584839 [DutyScan_Calibration_Flow] k_type=3
7354 13:58:51.601431
7355 13:58:51.601516 ==DQM 0 ==
7356 13:58:51.604815 Final DQM duty delay cell = 0
7357 13:58:51.608747 [0] MAX Duty = 5156%(X100), DQS PI = 20
7358 13:58:51.611522 [0] MIN Duty = 4844%(X100), DQS PI = 52
7359 13:58:51.611598 [0] AVG Duty = 5000%(X100)
7360 13:58:51.614900
7361 13:58:51.614973 ==DQM 1 ==
7362 13:58:51.618393 Final DQM duty delay cell = 0
7363 13:58:51.621938 [0] MAX Duty = 5156%(X100), DQS PI = 60
7364 13:58:51.624985 [0] MIN Duty = 4875%(X100), DQS PI = 22
7365 13:58:51.625056 [0] AVG Duty = 5015%(X100)
7366 13:58:51.628486
7367 13:58:51.631615 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7368 13:58:51.631685
7369 13:58:51.635263 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7370 13:58:51.638456 [DutyScan_Calibration_Flow] ====Done====
7371 13:58:51.638523
7372 13:58:51.641919 [DutyScan_Calibration_Flow] k_type=2
7373 13:58:51.658501
7374 13:58:51.658582 ==DQ 0 ==
7375 13:58:51.661926 Final DQ duty delay cell = 0
7376 13:58:51.665157 [0] MAX Duty = 5156%(X100), DQS PI = 20
7377 13:58:51.669013 [0] MIN Duty = 4907%(X100), DQS PI = 52
7378 13:58:51.669090 [0] AVG Duty = 5031%(X100)
7379 13:58:51.669163
7380 13:58:51.671766 ==DQ 1 ==
7381 13:58:51.675531 Final DQ duty delay cell = 0
7382 13:58:51.678731 [0] MAX Duty = 5093%(X100), DQS PI = 8
7383 13:58:51.681912 [0] MIN Duty = 5031%(X100), DQS PI = 0
7384 13:58:51.681982 [0] AVG Duty = 5062%(X100)
7385 13:58:51.682043
7386 13:58:51.685350 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7387 13:58:51.685439
7388 13:58:51.688719 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7389 13:58:51.692081 [DutyScan_Calibration_Flow] ====Done====
7390 13:58:51.697201 nWR fixed to 30
7391 13:58:51.700618 [ModeRegInit_LP4] CH0 RK0
7392 13:58:51.700707 [ModeRegInit_LP4] CH0 RK1
7393 13:58:51.703986 [ModeRegInit_LP4] CH1 RK0
7394 13:58:51.707414 [ModeRegInit_LP4] CH1 RK1
7395 13:58:51.707526 match AC timing 5
7396 13:58:51.714162 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7397 13:58:51.717294 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7398 13:58:51.721364 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7399 13:58:51.727809 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7400 13:58:51.731035 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7401 13:58:51.731107 [MiockJmeterHQA]
7402 13:58:51.731169
7403 13:58:51.734182 [DramcMiockJmeter] u1RxGatingPI = 0
7404 13:58:51.737586 0 : 4254, 4027
7405 13:58:51.737663 4 : 4253, 4026
7406 13:58:51.741677 8 : 4368, 4139
7407 13:58:51.741757 12 : 4255, 4027
7408 13:58:51.741821 16 : 4368, 4140
7409 13:58:51.744482 20 : 4257, 4029
7410 13:58:51.744554 24 : 4254, 4029
7411 13:58:51.747452 28 : 4255, 4029
7412 13:58:51.747522 32 : 4260, 4030
7413 13:58:51.751250 36 : 4258, 4030
7414 13:58:51.751357 40 : 4253, 4027
7415 13:58:51.754691 44 : 4370, 4145
7416 13:58:51.754818 48 : 4255, 4029
7417 13:58:51.754880 52 : 4255, 4031
7418 13:58:51.757739 56 : 4250, 4027
7419 13:58:51.757808 60 : 4253, 4029
7420 13:58:51.760875 64 : 4363, 4140
7421 13:58:51.760951 68 : 4250, 4027
7422 13:58:51.764548 72 : 4362, 4140
7423 13:58:51.764617 76 : 4250, 4027
7424 13:58:51.767564 80 : 4360, 4137
7425 13:58:51.767632 84 : 4252, 4030
7426 13:58:51.767699 88 : 4363, 4140
7427 13:58:51.770767 92 : 4361, 4138
7428 13:58:51.770837 96 : 4250, 3399
7429 13:58:51.774433 100 : 4253, 0
7430 13:58:51.774507 104 : 4250, 0
7431 13:58:51.774566 108 : 4253, 0
7432 13:58:51.778106 112 : 4250, 0
7433 13:58:51.778175 116 : 4250, 0
7434 13:58:51.781016 120 : 4254, 0
7435 13:58:51.781085 124 : 4363, 0
7436 13:58:51.781144 128 : 4253, 0
7437 13:58:51.784356 132 : 4363, 0
7438 13:58:51.784457 136 : 4361, 0
7439 13:58:51.787832 140 : 4361, 0
7440 13:58:51.787910 144 : 4363, 0
7441 13:58:51.787981 148 : 4250, 0
7442 13:58:51.790973 152 : 4361, 0
7443 13:58:51.791056 156 : 4250, 0
7444 13:58:51.791121 160 : 4250, 0
7445 13:58:51.794672 164 : 4250, 0
7446 13:58:51.794795 168 : 4250, 0
7447 13:58:51.797769 172 : 4255, 0
7448 13:58:51.797838 176 : 4250, 0
7449 13:58:51.797898 180 : 4250, 0
7450 13:58:51.800842 184 : 4366, 0
7451 13:58:51.800912 188 : 4250, 0
7452 13:58:51.804567 192 : 4250, 0
7453 13:58:51.804671 196 : 4368, 0
7454 13:58:51.804759 200 : 4254, 0
7455 13:58:51.807512 204 : 4252, 0
7456 13:58:51.807593 208 : 4250, 0
7457 13:58:51.811225 212 : 4257, 123
7458 13:58:51.811295 216 : 4360, 3946
7459 13:58:51.811362 220 : 4253, 4029
7460 13:58:51.814609 224 : 4250, 4027
7461 13:58:51.814705 228 : 4255, 4031
7462 13:58:51.817676 232 : 4250, 4026
7463 13:58:51.817744 236 : 4363, 4138
7464 13:58:51.820860 240 : 4253, 4029
7465 13:58:51.820944 244 : 4252, 4030
7466 13:58:51.824134 248 : 4361, 4137
7467 13:58:51.824207 252 : 4253, 4029
7468 13:58:51.827534 256 : 4363, 4140
7469 13:58:51.827603 260 : 4250, 4027
7470 13:58:51.831335 264 : 4360, 4137
7471 13:58:51.831410 268 : 4250, 4027
7472 13:58:51.831471 272 : 4255, 4029
7473 13:58:51.834581 276 : 4252, 4030
7474 13:58:51.834676 280 : 4363, 4139
7475 13:58:51.838081 284 : 4255, 4029
7476 13:58:51.838150 288 : 4250, 4026
7477 13:58:51.841184 292 : 4363, 4140
7478 13:58:51.841253 296 : 4250, 4027
7479 13:58:51.844571 300 : 4250, 4026
7480 13:58:51.844642 304 : 4250, 4026
7481 13:58:51.847716 308 : 4252, 4029
7482 13:58:51.847784 312 : 4255, 4029
7483 13:58:51.850901 316 : 4364, 4140
7484 13:58:51.850970 320 : 4255, 4029
7485 13:58:51.854610 324 : 4360, 4137
7486 13:58:51.854706 328 : 4250, 4027
7487 13:58:51.854779 332 : 4250, 2928
7488 13:58:51.857901 336 : 4250, 51
7489 13:58:51.857970
7490 13:58:51.861491 MIOCK jitter meter ch=0
7491 13:58:51.861587
7492 13:58:51.861691 1T = (336-100) = 236 dly cells
7493 13:58:51.868003 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7494 13:58:51.868076 ==
7495 13:58:51.871278 Dram Type= 6, Freq= 0, CH_0, rank 0
7496 13:58:51.874500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7497 13:58:51.877823 ==
7498 13:58:51.881484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7499 13:58:51.884429 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7500 13:58:51.891306 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7501 13:58:51.894604 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7502 13:58:51.905105 [CA 0] Center 44 (14~75) winsize 62
7503 13:58:51.908577 [CA 1] Center 44 (14~74) winsize 61
7504 13:58:51.911651 [CA 2] Center 39 (10~68) winsize 59
7505 13:58:51.915007 [CA 3] Center 39 (10~68) winsize 59
7506 13:58:51.918790 [CA 4] Center 37 (7~67) winsize 61
7507 13:58:51.921606 [CA 5] Center 37 (7~67) winsize 61
7508 13:58:51.921676
7509 13:58:51.924854 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7510 13:58:51.924932
7511 13:58:51.928128 [CATrainingPosCal] consider 1 rank data
7512 13:58:51.931602 u2DelayCellTimex100 = 275/100 ps
7513 13:58:51.935118 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7514 13:58:51.941771 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7515 13:58:51.945382 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7516 13:58:51.948325 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7517 13:58:51.951639 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7518 13:58:51.955385 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7519 13:58:51.955454
7520 13:58:51.958472 CA PerBit enable=1, Macro0, CA PI delay=37
7521 13:58:51.958541
7522 13:58:51.961611 [CBTSetCACLKResult] CA Dly = 37
7523 13:58:51.965044 CS Dly: 11 (0~42)
7524 13:58:51.968762 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7525 13:58:51.972181 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7526 13:58:51.972253 ==
7527 13:58:51.975566 Dram Type= 6, Freq= 0, CH_0, rank 1
7528 13:58:51.978445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 13:58:51.978514 ==
7530 13:58:51.984981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7531 13:58:51.988381 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7532 13:58:51.995125 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7533 13:58:51.998856 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7534 13:58:52.008846 [CA 0] Center 44 (14~75) winsize 62
7535 13:58:52.012772 [CA 1] Center 44 (14~75) winsize 62
7536 13:58:52.015472 [CA 2] Center 40 (11~69) winsize 59
7537 13:58:52.018949 [CA 3] Center 39 (10~69) winsize 60
7538 13:58:52.022375 [CA 4] Center 37 (8~67) winsize 60
7539 13:58:52.025573 [CA 5] Center 37 (7~67) winsize 61
7540 13:58:52.025645
7541 13:58:52.029121 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7542 13:58:52.029190
7543 13:58:52.032306 [CATrainingPosCal] consider 2 rank data
7544 13:58:52.035611 u2DelayCellTimex100 = 275/100 ps
7545 13:58:52.038716 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7546 13:58:52.045425 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7547 13:58:52.049026 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7548 13:58:52.051993 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7549 13:58:52.055701 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7550 13:58:52.059302 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7551 13:58:52.059373
7552 13:58:52.062108 CA PerBit enable=1, Macro0, CA PI delay=37
7553 13:58:52.062176
7554 13:58:52.065782 [CBTSetCACLKResult] CA Dly = 37
7555 13:58:52.069019 CS Dly: 12 (0~44)
7556 13:58:52.072166 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7557 13:58:52.076029 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7558 13:58:52.076108
7559 13:58:52.078895 ----->DramcWriteLeveling(PI) begin...
7560 13:58:52.078968 ==
7561 13:58:52.082032 Dram Type= 6, Freq= 0, CH_0, rank 0
7562 13:58:52.085427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7563 13:58:52.088794 ==
7564 13:58:52.088870 Write leveling (Byte 0): 32 => 32
7565 13:58:52.092160 Write leveling (Byte 1): 27 => 27
7566 13:58:52.095281 DramcWriteLeveling(PI) end<-----
7567 13:58:52.095354
7568 13:58:52.095423 ==
7569 13:58:52.098930 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 13:58:52.105634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 13:58:52.105710 ==
7572 13:58:52.105774 [Gating] SW mode calibration
7573 13:58:52.116127 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7574 13:58:52.118869 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7575 13:58:52.122446 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 13:58:52.128807 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 13:58:52.132143 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 13:58:52.135791 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 13:58:52.142531 1 4 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7580 13:58:52.145566 1 4 20 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7581 13:58:52.148897 1 4 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7582 13:58:52.155414 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 13:58:52.158758 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 13:58:52.162275 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 13:58:52.168962 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 13:58:52.172592 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7587 13:58:52.175465 1 5 16 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7588 13:58:52.182372 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
7589 13:58:52.185922 1 5 24 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
7590 13:58:52.188965 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 13:58:52.192353 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 13:58:52.199197 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 13:58:52.202344 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 13:58:52.206082 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 13:58:52.212532 1 6 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7596 13:58:52.215934 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7597 13:58:52.219269 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7598 13:58:52.226035 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 13:58:52.229428 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 13:58:52.232637 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 13:58:52.239330 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 13:58:52.242702 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 13:58:52.245845 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7604 13:58:52.253088 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7605 13:58:52.256270 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7606 13:58:52.259243 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 13:58:52.266007 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 13:58:52.269127 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 13:58:52.273064 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 13:58:52.276009 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 13:58:52.282553 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 13:58:52.285823 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 13:58:52.289236 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 13:58:52.296062 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 13:58:52.299528 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 13:58:52.302893 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 13:58:52.309217 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 13:58:52.312516 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 13:58:52.315987 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7620 13:58:52.323107 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7621 13:58:52.323188 Total UI for P1: 0, mck2ui 16
7622 13:58:52.329185 best dqsien dly found for B0: ( 1, 9, 16)
7623 13:58:52.332640 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 13:58:52.336423 Total UI for P1: 0, mck2ui 16
7625 13:58:52.339226 best dqsien dly found for B1: ( 1, 9, 20)
7626 13:58:52.342794 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7627 13:58:52.346062 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7628 13:58:52.346172
7629 13:58:52.349182 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7630 13:58:52.352951 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7631 13:58:52.356182 [Gating] SW calibration Done
7632 13:58:52.356264 ==
7633 13:58:52.359547 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 13:58:52.362896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 13:58:52.362969 ==
7636 13:58:52.366061 RX Vref Scan: 0
7637 13:58:52.366131
7638 13:58:52.369392 RX Vref 0 -> 0, step: 1
7639 13:58:52.369463
7640 13:58:52.369524 RX Delay 0 -> 252, step: 8
7641 13:58:52.376116 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7642 13:58:52.379856 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7643 13:58:52.382824 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7644 13:58:52.386010 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7645 13:58:52.389374 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7646 13:58:52.396483 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7647 13:58:52.399535 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7648 13:58:52.403147 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7649 13:58:52.405974 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7650 13:58:52.409637 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7651 13:58:52.416019 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7652 13:58:52.419863 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7653 13:58:52.423013 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7654 13:58:52.426624 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7655 13:58:52.429641 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7656 13:58:52.436204 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7657 13:58:52.436324 ==
7658 13:58:52.439802 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 13:58:52.443044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 13:58:52.443118 ==
7661 13:58:52.443179 DQS Delay:
7662 13:58:52.446140 DQS0 = 0, DQS1 = 0
7663 13:58:52.446217 DQM Delay:
7664 13:58:52.449994 DQM0 = 131, DQM1 = 124
7665 13:58:52.450064 DQ Delay:
7666 13:58:52.453175 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
7667 13:58:52.456779 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7668 13:58:52.459556 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7669 13:58:52.462897 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7670 13:58:52.462975
7671 13:58:52.463037
7672 13:58:52.466457 ==
7673 13:58:52.466530 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 13:58:52.473057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 13:58:52.473132 ==
7676 13:58:52.473195
7677 13:58:52.473261
7678 13:58:52.476647 TX Vref Scan disable
7679 13:58:52.476717 == TX Byte 0 ==
7680 13:58:52.479500 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7681 13:58:52.486117 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7682 13:58:52.486207 == TX Byte 1 ==
7683 13:58:52.489484 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7684 13:58:52.496295 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7685 13:58:52.496373 ==
7686 13:58:52.499816 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 13:58:52.502713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 13:58:52.502827 ==
7689 13:58:52.517200
7690 13:58:52.520624 TX Vref early break, caculate TX vref
7691 13:58:52.524245 TX Vref=16, minBit 7, minWin=20, winSum=350
7692 13:58:52.527138 TX Vref=18, minBit 1, minWin=21, winSum=364
7693 13:58:52.530787 TX Vref=20, minBit 0, minWin=22, winSum=374
7694 13:58:52.534359 TX Vref=22, minBit 0, minWin=23, winSum=386
7695 13:58:52.537368 TX Vref=24, minBit 1, minWin=23, winSum=394
7696 13:58:52.544292 TX Vref=26, minBit 0, minWin=24, winSum=404
7697 13:58:52.547589 TX Vref=28, minBit 1, minWin=24, winSum=410
7698 13:58:52.550462 TX Vref=30, minBit 4, minWin=23, winSum=410
7699 13:58:52.554033 TX Vref=32, minBit 0, minWin=24, winSum=406
7700 13:58:52.557643 TX Vref=34, minBit 0, minWin=23, winSum=392
7701 13:58:52.560981 TX Vref=36, minBit 4, minWin=22, winSum=380
7702 13:58:52.567331 [TxChooseVref] Worse bit 1, Min win 24, Win sum 410, Final Vref 28
7703 13:58:52.567402
7704 13:58:52.571216 Final TX Range 0 Vref 28
7705 13:58:52.571286
7706 13:58:52.571352 ==
7707 13:58:52.574059 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 13:58:52.577508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 13:58:52.577580 ==
7710 13:58:52.577641
7711 13:58:52.577704
7712 13:58:52.581122 TX Vref Scan disable
7713 13:58:52.587467 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7714 13:58:52.587544 == TX Byte 0 ==
7715 13:58:52.590599 u2DelayCellOfst[0]=14 cells (4 PI)
7716 13:58:52.594583 u2DelayCellOfst[1]=17 cells (5 PI)
7717 13:58:52.597833 u2DelayCellOfst[2]=10 cells (3 PI)
7718 13:58:52.601077 u2DelayCellOfst[3]=14 cells (4 PI)
7719 13:58:52.604199 u2DelayCellOfst[4]=10 cells (3 PI)
7720 13:58:52.607558 u2DelayCellOfst[5]=0 cells (0 PI)
7721 13:58:52.611064 u2DelayCellOfst[6]=17 cells (5 PI)
7722 13:58:52.614464 u2DelayCellOfst[7]=17 cells (5 PI)
7723 13:58:52.617658 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7724 13:58:52.620995 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7725 13:58:52.624284 == TX Byte 1 ==
7726 13:58:52.624356 u2DelayCellOfst[8]=0 cells (0 PI)
7727 13:58:52.627514 u2DelayCellOfst[9]=0 cells (0 PI)
7728 13:58:52.630909 u2DelayCellOfst[10]=7 cells (2 PI)
7729 13:58:52.634498 u2DelayCellOfst[11]=0 cells (0 PI)
7730 13:58:52.637684 u2DelayCellOfst[12]=10 cells (3 PI)
7731 13:58:52.640815 u2DelayCellOfst[13]=10 cells (3 PI)
7732 13:58:52.644243 u2DelayCellOfst[14]=14 cells (4 PI)
7733 13:58:52.647826 u2DelayCellOfst[15]=10 cells (3 PI)
7734 13:58:52.651091 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7735 13:58:52.657778 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7736 13:58:52.657854 DramC Write-DBI on
7737 13:58:52.657916 ==
7738 13:58:52.660732 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 13:58:52.664425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 13:58:52.664491 ==
7741 13:58:52.668028
7742 13:58:52.668098
7743 13:58:52.668157 TX Vref Scan disable
7744 13:58:52.670776 == TX Byte 0 ==
7745 13:58:52.674047 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7746 13:58:52.677392 == TX Byte 1 ==
7747 13:58:52.680952 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7748 13:58:52.681025 DramC Write-DBI off
7749 13:58:52.684794
7750 13:58:52.684869 [DATLAT]
7751 13:58:52.684932 Freq=1600, CH0 RK0
7752 13:58:52.684998
7753 13:58:52.687601 DATLAT Default: 0xf
7754 13:58:52.687672 0, 0xFFFF, sum = 0
7755 13:58:52.691278 1, 0xFFFF, sum = 0
7756 13:58:52.691357 2, 0xFFFF, sum = 0
7757 13:58:52.694882 3, 0xFFFF, sum = 0
7758 13:58:52.694953 4, 0xFFFF, sum = 0
7759 13:58:52.697577 5, 0xFFFF, sum = 0
7760 13:58:52.697644 6, 0xFFFF, sum = 0
7761 13:58:52.701049 7, 0xFFFF, sum = 0
7762 13:58:52.704070 8, 0xFFFF, sum = 0
7763 13:58:52.704140 9, 0xFFFF, sum = 0
7764 13:58:52.707832 10, 0xFFFF, sum = 0
7765 13:58:52.707911 11, 0xFFFF, sum = 0
7766 13:58:52.711260 12, 0xFFFF, sum = 0
7767 13:58:52.711338 13, 0xFFFF, sum = 0
7768 13:58:52.714542 14, 0x0, sum = 1
7769 13:58:52.714609 15, 0x0, sum = 2
7770 13:58:52.717831 16, 0x0, sum = 3
7771 13:58:52.717903 17, 0x0, sum = 4
7772 13:58:52.717963 best_step = 15
7773 13:58:52.720848
7774 13:58:52.720912 ==
7775 13:58:52.724458 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 13:58:52.727869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 13:58:52.727955 ==
7778 13:58:52.728041 RX Vref Scan: 1
7779 13:58:52.728124
7780 13:58:52.730905 Set Vref Range= 24 -> 127
7781 13:58:52.730989
7782 13:58:52.734423 RX Vref 24 -> 127, step: 1
7783 13:58:52.734508
7784 13:58:52.737842 RX Delay 11 -> 252, step: 4
7785 13:58:52.737927
7786 13:58:52.740901 Set Vref, RX VrefLevel [Byte0]: 24
7787 13:58:52.744228 [Byte1]: 24
7788 13:58:52.744312
7789 13:58:52.747759 Set Vref, RX VrefLevel [Byte0]: 25
7790 13:58:52.751048 [Byte1]: 25
7791 13:58:52.751133
7792 13:58:52.754509 Set Vref, RX VrefLevel [Byte0]: 26
7793 13:58:52.757784 [Byte1]: 26
7794 13:58:52.761117
7795 13:58:52.761201 Set Vref, RX VrefLevel [Byte0]: 27
7796 13:58:52.764665 [Byte1]: 27
7797 13:58:52.768717
7798 13:58:52.768795 Set Vref, RX VrefLevel [Byte0]: 28
7799 13:58:52.771932 [Byte1]: 28
7800 13:58:52.776609
7801 13:58:52.776683 Set Vref, RX VrefLevel [Byte0]: 29
7802 13:58:52.779742 [Byte1]: 29
7803 13:58:52.783830
7804 13:58:52.783906 Set Vref, RX VrefLevel [Byte0]: 30
7805 13:58:52.787448 [Byte1]: 30
7806 13:58:52.791708
7807 13:58:52.791786 Set Vref, RX VrefLevel [Byte0]: 31
7808 13:58:52.794804 [Byte1]: 31
7809 13:58:52.799423
7810 13:58:52.799502 Set Vref, RX VrefLevel [Byte0]: 32
7811 13:58:52.802698 [Byte1]: 32
7812 13:58:52.806756
7813 13:58:52.806830 Set Vref, RX VrefLevel [Byte0]: 33
7814 13:58:52.810019 [Byte1]: 33
7815 13:58:52.814343
7816 13:58:52.814422 Set Vref, RX VrefLevel [Byte0]: 34
7817 13:58:52.817437 [Byte1]: 34
7818 13:58:52.822277
7819 13:58:52.822352 Set Vref, RX VrefLevel [Byte0]: 35
7820 13:58:52.825433 [Byte1]: 35
7821 13:58:52.829646
7822 13:58:52.829719 Set Vref, RX VrefLevel [Byte0]: 36
7823 13:58:52.832672 [Byte1]: 36
7824 13:58:52.837556
7825 13:58:52.837634 Set Vref, RX VrefLevel [Byte0]: 37
7826 13:58:52.840514 [Byte1]: 37
7827 13:58:52.844658
7828 13:58:52.844737 Set Vref, RX VrefLevel [Byte0]: 38
7829 13:58:52.848011 [Byte1]: 38
7830 13:58:52.853034
7831 13:58:52.853106 Set Vref, RX VrefLevel [Byte0]: 39
7832 13:58:52.855621 [Byte1]: 39
7833 13:58:52.860583
7834 13:58:52.860659 Set Vref, RX VrefLevel [Byte0]: 40
7835 13:58:52.863927 [Byte1]: 40
7836 13:58:52.867853
7837 13:58:52.867931 Set Vref, RX VrefLevel [Byte0]: 41
7838 13:58:52.871321 [Byte1]: 41
7839 13:58:52.875457
7840 13:58:52.875529 Set Vref, RX VrefLevel [Byte0]: 42
7841 13:58:52.882156 [Byte1]: 42
7842 13:58:52.882231
7843 13:58:52.885036 Set Vref, RX VrefLevel [Byte0]: 43
7844 13:58:52.888318 [Byte1]: 43
7845 13:58:52.888401
7846 13:58:52.891973 Set Vref, RX VrefLevel [Byte0]: 44
7847 13:58:52.895433 [Byte1]: 44
7848 13:58:52.895507
7849 13:58:52.898646 Set Vref, RX VrefLevel [Byte0]: 45
7850 13:58:52.901690 [Byte1]: 45
7851 13:58:52.905827
7852 13:58:52.905900 Set Vref, RX VrefLevel [Byte0]: 46
7853 13:58:52.909306 [Byte1]: 46
7854 13:58:52.913337
7855 13:58:52.913409 Set Vref, RX VrefLevel [Byte0]: 47
7856 13:58:52.916864 [Byte1]: 47
7857 13:58:52.921460
7858 13:58:52.921532 Set Vref, RX VrefLevel [Byte0]: 48
7859 13:58:52.924627 [Byte1]: 48
7860 13:58:52.928529
7861 13:58:52.928614 Set Vref, RX VrefLevel [Byte0]: 49
7862 13:58:52.932047 [Byte1]: 49
7863 13:58:52.936194
7864 13:58:52.936271 Set Vref, RX VrefLevel [Byte0]: 50
7865 13:58:52.939818 [Byte1]: 50
7866 13:58:52.943919
7867 13:58:52.943990 Set Vref, RX VrefLevel [Byte0]: 51
7868 13:58:52.947079 [Byte1]: 51
7869 13:58:52.951502
7870 13:58:52.951572 Set Vref, RX VrefLevel [Byte0]: 52
7871 13:58:52.954691 [Byte1]: 52
7872 13:58:52.958935
7873 13:58:52.959013 Set Vref, RX VrefLevel [Byte0]: 53
7874 13:58:52.962384 [Byte1]: 53
7875 13:58:52.966653
7876 13:58:52.966774 Set Vref, RX VrefLevel [Byte0]: 54
7877 13:58:52.969831 [Byte1]: 54
7878 13:58:52.974205
7879 13:58:52.974280 Set Vref, RX VrefLevel [Byte0]: 55
7880 13:58:52.977798 [Byte1]: 55
7881 13:58:52.981956
7882 13:58:52.982031 Set Vref, RX VrefLevel [Byte0]: 56
7883 13:58:52.985289 [Byte1]: 56
7884 13:58:52.989520
7885 13:58:52.989604 Set Vref, RX VrefLevel [Byte0]: 57
7886 13:58:52.992743 [Byte1]: 57
7887 13:58:52.997540
7888 13:58:52.997612 Set Vref, RX VrefLevel [Byte0]: 58
7889 13:58:53.000659 [Byte1]: 58
7890 13:58:53.004817
7891 13:58:53.004917 Set Vref, RX VrefLevel [Byte0]: 59
7892 13:58:53.008333 [Byte1]: 59
7893 13:58:53.012221
7894 13:58:53.012299 Set Vref, RX VrefLevel [Byte0]: 60
7895 13:58:53.015912 [Byte1]: 60
7896 13:58:53.019745
7897 13:58:53.019818 Set Vref, RX VrefLevel [Byte0]: 61
7898 13:58:53.023180 [Byte1]: 61
7899 13:58:53.027790
7900 13:58:53.027862 Set Vref, RX VrefLevel [Byte0]: 62
7901 13:58:53.030964 [Byte1]: 62
7902 13:58:53.035091
7903 13:58:53.035163 Set Vref, RX VrefLevel [Byte0]: 63
7904 13:58:53.038315 [Byte1]: 63
7905 13:58:53.042703
7906 13:58:53.042786 Set Vref, RX VrefLevel [Byte0]: 64
7907 13:58:53.046472 [Byte1]: 64
7908 13:58:53.050520
7909 13:58:53.050592 Set Vref, RX VrefLevel [Byte0]: 65
7910 13:58:53.053854 [Byte1]: 65
7911 13:58:53.058178
7912 13:58:53.058251 Set Vref, RX VrefLevel [Byte0]: 66
7913 13:58:53.061548 [Byte1]: 66
7914 13:58:53.065945
7915 13:58:53.066027 Set Vref, RX VrefLevel [Byte0]: 67
7916 13:58:53.069003 [Byte1]: 67
7917 13:58:53.072957
7918 13:58:53.073032 Set Vref, RX VrefLevel [Byte0]: 68
7919 13:58:53.076632 [Byte1]: 68
7920 13:58:53.080813
7921 13:58:53.080896 Set Vref, RX VrefLevel [Byte0]: 69
7922 13:58:53.084114 [Byte1]: 69
7923 13:58:53.088501
7924 13:58:53.088579 Set Vref, RX VrefLevel [Byte0]: 70
7925 13:58:53.091723 [Byte1]: 70
7926 13:58:53.096419
7927 13:58:53.096501 Set Vref, RX VrefLevel [Byte0]: 71
7928 13:58:53.099119 [Byte1]: 71
7929 13:58:53.104404
7930 13:58:53.104478 Set Vref, RX VrefLevel [Byte0]: 72
7931 13:58:53.107260 [Byte1]: 72
7932 13:58:53.111199
7933 13:58:53.111270 Set Vref, RX VrefLevel [Byte0]: 73
7934 13:58:53.114801 [Byte1]: 73
7935 13:58:53.118967
7936 13:58:53.119039 Set Vref, RX VrefLevel [Byte0]: 74
7937 13:58:53.122239 [Byte1]: 74
7938 13:58:53.126435
7939 13:58:53.126517 Set Vref, RX VrefLevel [Byte0]: 75
7940 13:58:53.129745 [Byte1]: 75
7941 13:58:53.133940
7942 13:58:53.134012 Set Vref, RX VrefLevel [Byte0]: 76
7943 13:58:53.137368 [Byte1]: 76
7944 13:58:53.141728
7945 13:58:53.141800 Set Vref, RX VrefLevel [Byte0]: 77
7946 13:58:53.144919 [Byte1]: 77
7947 13:58:53.149602
7948 13:58:53.149683 Final RX Vref Byte 0 = 59 to rank0
7949 13:58:53.152840 Final RX Vref Byte 1 = 61 to rank0
7950 13:58:53.156127 Final RX Vref Byte 0 = 59 to rank1
7951 13:58:53.159044 Final RX Vref Byte 1 = 61 to rank1==
7952 13:58:53.162679 Dram Type= 6, Freq= 0, CH_0, rank 0
7953 13:58:53.169464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 13:58:53.169541 ==
7955 13:58:53.169604 DQS Delay:
7956 13:58:53.169664 DQS0 = 0, DQS1 = 0
7957 13:58:53.172790 DQM Delay:
7958 13:58:53.172869 DQM0 = 129, DQM1 = 121
7959 13:58:53.175926 DQ Delay:
7960 13:58:53.179202 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7961 13:58:53.182815 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7962 13:58:53.186310 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7963 13:58:53.189842 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7964 13:58:53.189921
7965 13:58:53.189992
7966 13:58:53.190053
7967 13:58:53.193023 [DramC_TX_OE_Calibration] TA2
7968 13:58:53.195945 Original DQ_B0 (3 6) =30, OEN = 27
7969 13:58:53.199864 Original DQ_B1 (3 6) =30, OEN = 27
7970 13:58:53.202791 24, 0x0, End_B0=24 End_B1=24
7971 13:58:53.202867 25, 0x0, End_B0=25 End_B1=25
7972 13:58:53.206130 26, 0x0, End_B0=26 End_B1=26
7973 13:58:53.209342 27, 0x0, End_B0=27 End_B1=27
7974 13:58:53.212591 28, 0x0, End_B0=28 End_B1=28
7975 13:58:53.212663 29, 0x0, End_B0=29 End_B1=29
7976 13:58:53.215889 30, 0x0, End_B0=30 End_B1=30
7977 13:58:53.219562 31, 0x4141, End_B0=30 End_B1=30
7978 13:58:53.222831 Byte0 end_step=30 best_step=27
7979 13:58:53.226223 Byte1 end_step=30 best_step=27
7980 13:58:53.229395 Byte0 TX OE(2T, 0.5T) = (3, 3)
7981 13:58:53.229468 Byte1 TX OE(2T, 0.5T) = (3, 3)
7982 13:58:53.229529
7983 13:58:53.232398
7984 13:58:53.239679 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7985 13:58:53.242567 CH0 RK0: MR19=303, MR18=1206
7986 13:58:53.249720 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
7987 13:58:53.249811
7988 13:58:53.252841 ----->DramcWriteLeveling(PI) begin...
7989 13:58:53.252920 ==
7990 13:58:53.256254 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 13:58:53.259308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 13:58:53.259380 ==
7993 13:58:53.262658 Write leveling (Byte 0): 34 => 34
7994 13:58:53.265821 Write leveling (Byte 1): 28 => 28
7995 13:58:53.269398 DramcWriteLeveling(PI) end<-----
7996 13:58:53.269468
7997 13:58:53.269535 ==
7998 13:58:53.272604 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 13:58:53.275933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 13:58:53.276008 ==
8001 13:58:53.279118 [Gating] SW mode calibration
8002 13:58:53.286049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8003 13:58:53.292337 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8004 13:58:53.296091 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 13:58:53.299301 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 13:58:53.305752 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 13:58:53.309295 1 4 12 | B1->B0 | 2323 3332 | 0 1 | (0 0) (1 1)
8008 13:58:53.312762 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8009 13:58:53.319825 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
8010 13:58:53.322789 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 13:58:53.325882 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 13:58:53.332604 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 13:58:53.336239 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 13:58:53.339409 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8015 13:58:53.342473 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8016 13:58:53.349412 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8017 13:58:53.352654 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8018 13:58:53.355828 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8019 13:58:53.362589 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 13:58:53.366296 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 13:58:53.369607 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 13:58:53.376269 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
8023 13:58:53.379595 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8024 13:58:53.382908 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8025 13:58:53.389713 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8026 13:58:53.392857 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 13:58:53.396377 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 13:58:53.403082 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 13:58:53.405934 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 13:58:53.409704 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 13:58:53.415919 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 13:58:53.419325 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8033 13:58:53.422802 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8034 13:58:53.426016 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8035 13:58:53.432867 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 13:58:53.436099 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 13:58:53.439881 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 13:58:53.446024 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 13:58:53.449483 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 13:58:53.452979 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 13:58:53.459963 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 13:58:53.463253 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 13:58:53.466175 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 13:58:53.473026 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 13:58:53.476206 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 13:58:53.479626 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 13:58:53.486422 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8048 13:58:53.489518 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8049 13:58:53.493081 Total UI for P1: 0, mck2ui 16
8050 13:58:53.496445 best dqsien dly found for B0: ( 1, 9, 10)
8051 13:58:53.499574 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8052 13:58:53.503247 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 13:58:53.506203 Total UI for P1: 0, mck2ui 16
8054 13:58:53.509925 best dqsien dly found for B1: ( 1, 9, 20)
8055 13:58:53.513123 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8056 13:58:53.516461 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8057 13:58:53.519619
8058 13:58:53.523067 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8059 13:58:53.526569 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8060 13:58:53.530044 [Gating] SW calibration Done
8061 13:58:53.530124 ==
8062 13:58:53.533103 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 13:58:53.536531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 13:58:53.536612 ==
8065 13:58:53.536676 RX Vref Scan: 0
8066 13:58:53.539828
8067 13:58:53.539908 RX Vref 0 -> 0, step: 1
8068 13:58:53.539972
8069 13:58:53.543211 RX Delay 0 -> 252, step: 8
8070 13:58:53.546518 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8071 13:58:53.550042 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8072 13:58:53.556939 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8073 13:58:53.559595 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8074 13:58:53.563069 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8075 13:58:53.566618 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8076 13:58:53.569915 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8077 13:58:53.573101 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8078 13:58:53.579953 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8079 13:58:53.583391 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8080 13:58:53.586406 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8081 13:58:53.589947 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8082 13:58:53.593340 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8083 13:58:53.600207 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8084 13:58:53.603333 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8085 13:58:53.606815 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8086 13:58:53.606899 ==
8087 13:58:53.610552 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 13:58:53.613372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 13:58:53.616810 ==
8090 13:58:53.616891 DQS Delay:
8091 13:58:53.616955 DQS0 = 0, DQS1 = 0
8092 13:58:53.620055 DQM Delay:
8093 13:58:53.620136 DQM0 = 132, DQM1 = 124
8094 13:58:53.623048 DQ Delay:
8095 13:58:53.626989 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8096 13:58:53.630033 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8097 13:58:53.633274 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8098 13:58:53.636733 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8099 13:58:53.636815
8100 13:58:53.636879
8101 13:58:53.636938 ==
8102 13:58:53.639842 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 13:58:53.643351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 13:58:53.643432 ==
8105 13:58:53.643497
8106 13:58:53.643556
8107 13:58:53.646550 TX Vref Scan disable
8108 13:58:53.650265 == TX Byte 0 ==
8109 13:58:53.653427 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8110 13:58:53.656647 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8111 13:58:53.659781 == TX Byte 1 ==
8112 13:58:53.663407 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8113 13:58:53.666616 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8114 13:58:53.666697 ==
8115 13:58:53.670320 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 13:58:53.673355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 13:58:53.676380 ==
8118 13:58:53.689829
8119 13:58:53.693380 TX Vref early break, caculate TX vref
8120 13:58:53.696567 TX Vref=16, minBit 1, minWin=23, winSum=379
8121 13:58:53.699852 TX Vref=18, minBit 1, minWin=23, winSum=386
8122 13:58:53.703113 TX Vref=20, minBit 2, minWin=23, winSum=395
8123 13:58:53.706863 TX Vref=22, minBit 0, minWin=23, winSum=405
8124 13:58:53.710202 TX Vref=24, minBit 1, minWin=24, winSum=406
8125 13:58:53.716578 TX Vref=26, minBit 0, minWin=25, winSum=418
8126 13:58:53.719656 TX Vref=28, minBit 2, minWin=25, winSum=425
8127 13:58:53.723135 TX Vref=30, minBit 0, minWin=25, winSum=419
8128 13:58:53.726611 TX Vref=32, minBit 0, minWin=25, winSum=414
8129 13:58:53.729969 TX Vref=34, minBit 0, minWin=24, winSum=406
8130 13:58:53.732992 TX Vref=36, minBit 2, minWin=24, winSum=399
8131 13:58:53.739786 [TxChooseVref] Worse bit 2, Min win 25, Win sum 425, Final Vref 28
8132 13:58:53.739867
8133 13:58:53.743363 Final TX Range 0 Vref 28
8134 13:58:53.743445
8135 13:58:53.743508 ==
8136 13:58:53.746695 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 13:58:53.749741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 13:58:53.749822 ==
8139 13:58:53.749886
8140 13:58:53.749945
8141 13:58:53.753490 TX Vref Scan disable
8142 13:58:53.760082 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8143 13:58:53.760180 == TX Byte 0 ==
8144 13:58:53.763187 u2DelayCellOfst[0]=14 cells (4 PI)
8145 13:58:53.766981 u2DelayCellOfst[1]=17 cells (5 PI)
8146 13:58:53.769842 u2DelayCellOfst[2]=10 cells (3 PI)
8147 13:58:53.773406 u2DelayCellOfst[3]=10 cells (3 PI)
8148 13:58:53.776577 u2DelayCellOfst[4]=10 cells (3 PI)
8149 13:58:53.779694 u2DelayCellOfst[5]=0 cells (0 PI)
8150 13:58:53.783182 u2DelayCellOfst[6]=17 cells (5 PI)
8151 13:58:53.786730 u2DelayCellOfst[7]=17 cells (5 PI)
8152 13:58:53.789786 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8153 13:58:53.793044 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8154 13:58:53.796398 == TX Byte 1 ==
8155 13:58:53.796470 u2DelayCellOfst[8]=0 cells (0 PI)
8156 13:58:53.800229 u2DelayCellOfst[9]=0 cells (0 PI)
8157 13:58:53.803067 u2DelayCellOfst[10]=7 cells (2 PI)
8158 13:58:53.806828 u2DelayCellOfst[11]=0 cells (0 PI)
8159 13:58:53.809737 u2DelayCellOfst[12]=14 cells (4 PI)
8160 13:58:53.812991 u2DelayCellOfst[13]=14 cells (4 PI)
8161 13:58:53.816605 u2DelayCellOfst[14]=17 cells (5 PI)
8162 13:58:53.819817 u2DelayCellOfst[15]=10 cells (3 PI)
8163 13:58:53.823247 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8164 13:58:53.830054 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8165 13:58:53.830136 DramC Write-DBI on
8166 13:58:53.830201 ==
8167 13:58:53.833053 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 13:58:53.836494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 13:58:53.836575 ==
8170 13:58:53.839825
8171 13:58:53.839906
8172 13:58:53.839970 TX Vref Scan disable
8173 13:58:53.843267 == TX Byte 0 ==
8174 13:58:53.846990 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8175 13:58:53.849819 == TX Byte 1 ==
8176 13:58:53.853384 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8177 13:58:53.856719 DramC Write-DBI off
8178 13:58:53.856800
8179 13:58:53.856894 [DATLAT]
8180 13:58:53.856958 Freq=1600, CH0 RK1
8181 13:58:53.857017
8182 13:58:53.860022 DATLAT Default: 0xf
8183 13:58:53.860103 0, 0xFFFF, sum = 0
8184 13:58:53.863277 1, 0xFFFF, sum = 0
8185 13:58:53.863359 2, 0xFFFF, sum = 0
8186 13:58:53.866355 3, 0xFFFF, sum = 0
8187 13:58:53.870234 4, 0xFFFF, sum = 0
8188 13:58:53.870316 5, 0xFFFF, sum = 0
8189 13:58:53.873036 6, 0xFFFF, sum = 0
8190 13:58:53.873118 7, 0xFFFF, sum = 0
8191 13:58:53.876942 8, 0xFFFF, sum = 0
8192 13:58:53.877023 9, 0xFFFF, sum = 0
8193 13:58:53.880052 10, 0xFFFF, sum = 0
8194 13:58:53.880158 11, 0xFFFF, sum = 0
8195 13:58:53.883098 12, 0xFFFF, sum = 0
8196 13:58:53.883180 13, 0xFFFF, sum = 0
8197 13:58:53.886424 14, 0x0, sum = 1
8198 13:58:53.886506 15, 0x0, sum = 2
8199 13:58:53.889917 16, 0x0, sum = 3
8200 13:58:53.889999 17, 0x0, sum = 4
8201 13:58:53.893436 best_step = 15
8202 13:58:53.893517
8203 13:58:53.893582 ==
8204 13:58:53.896441 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 13:58:53.900104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 13:58:53.900186 ==
8207 13:58:53.900252 RX Vref Scan: 0
8208 13:58:53.900312
8209 13:58:53.903099 RX Vref 0 -> 0, step: 1
8210 13:58:53.903196
8211 13:58:53.907069 RX Delay 3 -> 252, step: 4
8212 13:58:53.909706 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8213 13:58:53.916510 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8214 13:58:53.920066 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8215 13:58:53.923372 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8216 13:58:53.926494 iDelay=191, Bit 4, Center 126 (71 ~ 182) 112
8217 13:58:53.929720 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8218 13:58:53.933116 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8219 13:58:53.940225 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8220 13:58:53.943028 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8221 13:58:53.946555 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8222 13:58:53.949779 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8223 13:58:53.953182 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8224 13:58:53.959789 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8225 13:58:53.963795 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8226 13:58:53.966508 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8227 13:58:53.970306 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8228 13:58:53.970449 ==
8229 13:58:53.973850 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 13:58:53.980296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 13:58:53.980402 ==
8232 13:58:53.980482 DQS Delay:
8233 13:58:53.980541 DQS0 = 0, DQS1 = 0
8234 13:58:53.983307 DQM Delay:
8235 13:58:53.983388 DQM0 = 127, DQM1 = 122
8236 13:58:53.986696 DQ Delay:
8237 13:58:53.989839 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8238 13:58:53.993427 DQ4 =126, DQ5 =116, DQ6 =134, DQ7 =136
8239 13:58:53.997014 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =116
8240 13:58:54.000026 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
8241 13:58:54.000107
8242 13:58:54.000171
8243 13:58:54.000231
8244 13:58:54.003861 [DramC_TX_OE_Calibration] TA2
8245 13:58:54.006833 Original DQ_B0 (3 6) =30, OEN = 27
8246 13:58:54.010173 Original DQ_B1 (3 6) =30, OEN = 27
8247 13:58:54.013686 24, 0x0, End_B0=24 End_B1=24
8248 13:58:54.013769 25, 0x0, End_B0=25 End_B1=25
8249 13:58:54.016836 26, 0x0, End_B0=26 End_B1=26
8250 13:58:54.020499 27, 0x0, End_B0=27 End_B1=27
8251 13:58:54.023702 28, 0x0, End_B0=28 End_B1=28
8252 13:58:54.023784 29, 0x0, End_B0=29 End_B1=29
8253 13:58:54.027182 30, 0x0, End_B0=30 End_B1=30
8254 13:58:54.030138 31, 0x4141, End_B0=30 End_B1=30
8255 13:58:54.033747 Byte0 end_step=30 best_step=27
8256 13:58:54.036801 Byte1 end_step=30 best_step=27
8257 13:58:54.040393 Byte0 TX OE(2T, 0.5T) = (3, 3)
8258 13:58:54.040474 Byte1 TX OE(2T, 0.5T) = (3, 3)
8259 13:58:54.040539
8260 13:58:54.040599
8261 13:58:54.050400 [DQSOSCAuto] RK1, (LSB)MR18= 0x180c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8262 13:58:54.053916 CH0 RK1: MR19=303, MR18=180C
8263 13:58:54.060340 CH0_RK1: MR19=0x303, MR18=0x180C, DQSOSC=397, MR23=63, INC=23, DEC=15
8264 13:58:54.060421 [RxdqsGatingPostProcess] freq 1600
8265 13:58:54.066873 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8266 13:58:54.070495 best DQS0 dly(2T, 0.5T) = (1, 1)
8267 13:58:54.073885 best DQS1 dly(2T, 0.5T) = (1, 1)
8268 13:58:54.077154 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8269 13:58:54.080403 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8270 13:58:54.083741 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 13:58:54.086682 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 13:58:54.090113 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 13:58:54.090195 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 13:58:54.093496 Pre-setting of DQS Precalculation
8275 13:58:54.100259 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8276 13:58:54.100342 ==
8277 13:58:54.103681 Dram Type= 6, Freq= 0, CH_1, rank 0
8278 13:58:54.107013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 13:58:54.107095 ==
8280 13:58:54.113559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8281 13:58:54.116896 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8282 13:58:54.120624 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8283 13:58:54.127075 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8284 13:58:54.136234 [CA 0] Center 42 (14~71) winsize 58
8285 13:58:54.139462 [CA 1] Center 42 (13~71) winsize 59
8286 13:58:54.143117 [CA 2] Center 37 (8~66) winsize 59
8287 13:58:54.146108 [CA 3] Center 36 (7~65) winsize 59
8288 13:58:54.149735 [CA 4] Center 37 (7~67) winsize 61
8289 13:58:54.152946 [CA 5] Center 36 (7~66) winsize 60
8290 13:58:54.153028
8291 13:58:54.156073 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8292 13:58:54.156155
8293 13:58:54.159812 [CATrainingPosCal] consider 1 rank data
8294 13:58:54.162825 u2DelayCellTimex100 = 275/100 ps
8295 13:58:54.166141 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8296 13:58:54.173071 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8297 13:58:54.176546 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8298 13:58:54.179460 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8299 13:58:54.182787 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8300 13:58:54.186085 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8301 13:58:54.186167
8302 13:58:54.189565 CA PerBit enable=1, Macro0, CA PI delay=36
8303 13:58:54.189645
8304 13:58:54.193013 [CBTSetCACLKResult] CA Dly = 36
8305 13:58:54.193122 CS Dly: 8 (0~39)
8306 13:58:54.199632 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8307 13:58:54.202885 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8308 13:58:54.202967 ==
8309 13:58:54.206344 Dram Type= 6, Freq= 0, CH_1, rank 1
8310 13:58:54.209531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 13:58:54.209612 ==
8312 13:58:54.216101 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 13:58:54.219712 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 13:58:54.223149 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 13:58:54.229639 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 13:58:54.239628 [CA 0] Center 42 (13~72) winsize 60
8317 13:58:54.242665 [CA 1] Center 42 (14~71) winsize 58
8318 13:58:54.246134 [CA 2] Center 37 (9~66) winsize 58
8319 13:58:54.249336 [CA 3] Center 37 (8~66) winsize 59
8320 13:58:54.252550 [CA 4] Center 38 (9~67) winsize 59
8321 13:58:54.255848 [CA 5] Center 36 (7~66) winsize 60
8322 13:58:54.255929
8323 13:58:54.259427 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8324 13:58:54.259509
8325 13:58:54.262847 [CATrainingPosCal] consider 2 rank data
8326 13:58:54.265946 u2DelayCellTimex100 = 275/100 ps
8327 13:58:54.269536 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8328 13:58:54.276031 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8329 13:58:54.279504 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8330 13:58:54.282821 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8331 13:58:54.286256 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8332 13:58:54.289739 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8333 13:58:54.289820
8334 13:58:54.292933 CA PerBit enable=1, Macro0, CA PI delay=36
8335 13:58:54.293040
8336 13:58:54.296077 [CBTSetCACLKResult] CA Dly = 36
8337 13:58:54.296160 CS Dly: 10 (0~44)
8338 13:58:54.302968 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 13:58:54.306527 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 13:58:54.306635
8341 13:58:54.309964 ----->DramcWriteLeveling(PI) begin...
8342 13:58:54.310037 ==
8343 13:58:54.312944 Dram Type= 6, Freq= 0, CH_1, rank 0
8344 13:58:54.316278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 13:58:54.316360 ==
8346 13:58:54.319640 Write leveling (Byte 0): 27 => 27
8347 13:58:54.322867 Write leveling (Byte 1): 29 => 29
8348 13:58:54.326130 DramcWriteLeveling(PI) end<-----
8349 13:58:54.326212
8350 13:58:54.326276 ==
8351 13:58:54.329918 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 13:58:54.332923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 13:58:54.335904 ==
8354 13:58:54.335985 [Gating] SW mode calibration
8355 13:58:54.346155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8356 13:58:54.350143 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8357 13:58:54.352892 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 13:58:54.359824 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 13:58:54.362961 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 13:58:54.366463 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 13:58:54.372917 1 4 16 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
8362 13:58:54.376264 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 13:58:54.379682 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 13:58:54.386418 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 13:58:54.389592 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 13:58:54.393143 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 13:58:54.399388 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 13:58:54.403300 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8369 13:58:54.406419 1 5 16 | B1->B0 | 2e2e 3232 | 0 0 | (1 0) (0 1)
8370 13:58:54.409886 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8371 13:58:54.416643 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 13:58:54.419969 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 13:58:54.422941 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 13:58:54.430024 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 13:58:54.432956 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 13:58:54.436497 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 13:58:54.442997 1 6 16 | B1->B0 | 3d3d 3535 | 0 0 | (0 0) (0 0)
8378 13:58:54.446491 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 13:58:54.450122 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 13:58:54.456585 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 13:58:54.460228 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 13:58:54.463225 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 13:58:54.470109 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 13:58:54.473279 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8385 13:58:54.476600 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8386 13:58:54.479932 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8387 13:58:54.486648 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 13:58:54.489901 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 13:58:54.493295 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 13:58:54.500100 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 13:58:54.503768 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 13:58:54.506603 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 13:58:54.513523 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 13:58:54.516843 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 13:58:54.519913 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 13:58:54.527091 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 13:58:54.530848 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 13:58:54.533727 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 13:58:54.540432 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 13:58:54.543655 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 13:58:54.546881 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8402 13:58:54.550328 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 13:58:54.553693 Total UI for P1: 0, mck2ui 16
8404 13:58:54.556746 best dqsien dly found for B0: ( 1, 9, 16)
8405 13:58:54.560224 Total UI for P1: 0, mck2ui 16
8406 13:58:54.563485 best dqsien dly found for B1: ( 1, 9, 16)
8407 13:58:54.566885 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8408 13:58:54.570473 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8409 13:58:54.573513
8410 13:58:54.576778 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8411 13:58:54.580240 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8412 13:58:54.583991 [Gating] SW calibration Done
8413 13:58:54.584063 ==
8414 13:58:54.586718 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 13:58:54.590524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 13:58:54.590604 ==
8417 13:58:54.590668 RX Vref Scan: 0
8418 13:58:54.590766
8419 13:58:54.594027 RX Vref 0 -> 0, step: 1
8420 13:58:54.594130
8421 13:58:54.597489 RX Delay 0 -> 252, step: 8
8422 13:58:54.600346 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8423 13:58:54.603832 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8424 13:58:54.610780 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8425 13:58:54.613659 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8426 13:58:54.616889 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8427 13:58:54.620282 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8428 13:58:54.623535 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8429 13:58:54.627110 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8430 13:58:54.633775 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8431 13:58:54.637502 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8432 13:58:54.640348 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8433 13:58:54.643795 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8434 13:58:54.647089 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8435 13:58:54.654008 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8436 13:58:54.657634 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8437 13:58:54.660550 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8438 13:58:54.660632 ==
8439 13:58:54.663638 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 13:58:54.666993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 13:58:54.667076 ==
8442 13:58:54.670219 DQS Delay:
8443 13:58:54.670301 DQS0 = 0, DQS1 = 0
8444 13:58:54.674104 DQM Delay:
8445 13:58:54.674212 DQM0 = 135, DQM1 = 127
8446 13:58:54.677376 DQ Delay:
8447 13:58:54.680217 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8448 13:58:54.683818 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8449 13:58:54.687164 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8450 13:58:54.690347 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8451 13:58:54.690428
8452 13:58:54.690493
8453 13:58:54.690553 ==
8454 13:58:54.693960 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 13:58:54.697251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 13:58:54.697334 ==
8457 13:58:54.697399
8458 13:58:54.697459
8459 13:58:54.700327 TX Vref Scan disable
8460 13:58:54.703460 == TX Byte 0 ==
8461 13:58:54.706878 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8462 13:58:54.710443 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8463 13:58:54.713531 == TX Byte 1 ==
8464 13:58:54.717023 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8465 13:58:54.720477 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8466 13:58:54.720558 ==
8467 13:58:54.723875 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 13:58:54.726928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 13:58:54.730466 ==
8470 13:58:54.742337
8471 13:58:54.745698 TX Vref early break, caculate TX vref
8472 13:58:54.748918 TX Vref=16, minBit 8, minWin=21, winSum=359
8473 13:58:54.752728 TX Vref=18, minBit 5, minWin=21, winSum=364
8474 13:58:54.756230 TX Vref=20, minBit 8, minWin=21, winSum=374
8475 13:58:54.759103 TX Vref=22, minBit 8, minWin=22, winSum=387
8476 13:58:54.762847 TX Vref=24, minBit 5, minWin=23, winSum=396
8477 13:58:54.766037 TX Vref=26, minBit 0, minWin=24, winSum=406
8478 13:58:54.772448 TX Vref=28, minBit 0, minWin=25, winSum=411
8479 13:58:54.775968 TX Vref=30, minBit 5, minWin=25, winSum=416
8480 13:58:54.779453 TX Vref=32, minBit 8, minWin=24, winSum=406
8481 13:58:54.782932 TX Vref=34, minBit 11, minWin=23, winSum=397
8482 13:58:54.786240 TX Vref=36, minBit 8, minWin=23, winSum=388
8483 13:58:54.792787 [TxChooseVref] Worse bit 5, Min win 25, Win sum 416, Final Vref 30
8484 13:58:54.792895
8485 13:58:54.796258 Final TX Range 0 Vref 30
8486 13:58:54.796340
8487 13:58:54.796405 ==
8488 13:58:54.799141 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 13:58:54.802599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 13:58:54.802704 ==
8491 13:58:54.802795
8492 13:58:54.802857
8493 13:58:54.806071 TX Vref Scan disable
8494 13:58:54.812449 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8495 13:58:54.812531 == TX Byte 0 ==
8496 13:58:54.816232 u2DelayCellOfst[0]=21 cells (6 PI)
8497 13:58:54.819623 u2DelayCellOfst[1]=10 cells (3 PI)
8498 13:58:54.822932 u2DelayCellOfst[2]=0 cells (0 PI)
8499 13:58:54.826262 u2DelayCellOfst[3]=7 cells (2 PI)
8500 13:58:54.829460 u2DelayCellOfst[4]=7 cells (2 PI)
8501 13:58:54.832544 u2DelayCellOfst[5]=21 cells (6 PI)
8502 13:58:54.836113 u2DelayCellOfst[6]=17 cells (5 PI)
8503 13:58:54.836196 u2DelayCellOfst[7]=7 cells (2 PI)
8504 13:58:54.842668 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8505 13:58:54.845917 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8506 13:58:54.845999 == TX Byte 1 ==
8507 13:58:54.849429 u2DelayCellOfst[8]=0 cells (0 PI)
8508 13:58:54.852957 u2DelayCellOfst[9]=7 cells (2 PI)
8509 13:58:54.856374 u2DelayCellOfst[10]=10 cells (3 PI)
8510 13:58:54.859257 u2DelayCellOfst[11]=7 cells (2 PI)
8511 13:58:54.862695 u2DelayCellOfst[12]=14 cells (4 PI)
8512 13:58:54.866282 u2DelayCellOfst[13]=17 cells (5 PI)
8513 13:58:54.869467 u2DelayCellOfst[14]=17 cells (5 PI)
8514 13:58:54.872627 u2DelayCellOfst[15]=17 cells (5 PI)
8515 13:58:54.876222 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8516 13:58:54.879410 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8517 13:58:54.882616 DramC Write-DBI on
8518 13:58:54.882697 ==
8519 13:58:54.885992 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 13:58:54.889591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 13:58:54.889674 ==
8522 13:58:54.889738
8523 13:58:54.889798
8524 13:58:54.892809 TX Vref Scan disable
8525 13:58:54.896172 == TX Byte 0 ==
8526 13:58:54.899570 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8527 13:58:54.902924 == TX Byte 1 ==
8528 13:58:54.906785 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8529 13:58:54.906867 DramC Write-DBI off
8530 13:58:54.906931
8531 13:58:54.909737 [DATLAT]
8532 13:58:54.909818 Freq=1600, CH1 RK0
8533 13:58:54.909882
8534 13:58:54.912720 DATLAT Default: 0xf
8535 13:58:54.912802 0, 0xFFFF, sum = 0
8536 13:58:54.916275 1, 0xFFFF, sum = 0
8537 13:58:54.916359 2, 0xFFFF, sum = 0
8538 13:58:54.919460 3, 0xFFFF, sum = 0
8539 13:58:54.919544 4, 0xFFFF, sum = 0
8540 13:58:54.922931 5, 0xFFFF, sum = 0
8541 13:58:54.923014 6, 0xFFFF, sum = 0
8542 13:58:54.926247 7, 0xFFFF, sum = 0
8543 13:58:54.926329 8, 0xFFFF, sum = 0
8544 13:58:54.929622 9, 0xFFFF, sum = 0
8545 13:58:54.929705 10, 0xFFFF, sum = 0
8546 13:58:54.932949 11, 0xFFFF, sum = 0
8547 13:58:54.936365 12, 0xFFFF, sum = 0
8548 13:58:54.936448 13, 0xFFFF, sum = 0
8549 13:58:54.936515 14, 0x0, sum = 1
8550 13:58:54.939784 15, 0x0, sum = 2
8551 13:58:54.939867 16, 0x0, sum = 3
8552 13:58:54.942911 17, 0x0, sum = 4
8553 13:58:54.942994 best_step = 15
8554 13:58:54.943059
8555 13:58:54.943134 ==
8556 13:58:54.946059 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 13:58:54.953430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 13:58:54.953513 ==
8559 13:58:54.953578 RX Vref Scan: 1
8560 13:58:54.953638
8561 13:58:54.956697 Set Vref Range= 24 -> 127
8562 13:58:54.956779
8563 13:58:54.959606 RX Vref 24 -> 127, step: 1
8564 13:58:54.959688
8565 13:58:54.963155 RX Delay 11 -> 252, step: 4
8566 13:58:54.963237
8567 13:58:54.966397 Set Vref, RX VrefLevel [Byte0]: 24
8568 13:58:54.966479 [Byte1]: 24
8569 13:58:54.970598
8570 13:58:54.970696 Set Vref, RX VrefLevel [Byte0]: 25
8571 13:58:54.974268 [Byte1]: 25
8572 13:58:54.978436
8573 13:58:54.978518 Set Vref, RX VrefLevel [Byte0]: 26
8574 13:58:54.982054 [Byte1]: 26
8575 13:58:54.986108
8576 13:58:54.986190 Set Vref, RX VrefLevel [Byte0]: 27
8577 13:58:54.989005 [Byte1]: 27
8578 13:58:54.993566
8579 13:58:54.993648 Set Vref, RX VrefLevel [Byte0]: 28
8580 13:58:54.997086 [Byte1]: 28
8581 13:58:55.001137
8582 13:58:55.001218 Set Vref, RX VrefLevel [Byte0]: 29
8583 13:58:55.004719 [Byte1]: 29
8584 13:58:55.008980
8585 13:58:55.009061 Set Vref, RX VrefLevel [Byte0]: 30
8586 13:58:55.012338 [Byte1]: 30
8587 13:58:55.016601
8588 13:58:55.016682 Set Vref, RX VrefLevel [Byte0]: 31
8589 13:58:55.019653 [Byte1]: 31
8590 13:58:55.024249
8591 13:58:55.024330 Set Vref, RX VrefLevel [Byte0]: 32
8592 13:58:55.027596 [Byte1]: 32
8593 13:58:55.031522
8594 13:58:55.031604 Set Vref, RX VrefLevel [Byte0]: 33
8595 13:58:55.035057 [Byte1]: 33
8596 13:58:55.039241
8597 13:58:55.039355 Set Vref, RX VrefLevel [Byte0]: 34
8598 13:58:55.042524 [Byte1]: 34
8599 13:58:55.046883
8600 13:58:55.046963 Set Vref, RX VrefLevel [Byte0]: 35
8601 13:58:55.050182 [Byte1]: 35
8602 13:58:55.054478
8603 13:58:55.054599 Set Vref, RX VrefLevel [Byte0]: 36
8604 13:58:55.057680 [Byte1]: 36
8605 13:58:55.062080
8606 13:58:55.062161 Set Vref, RX VrefLevel [Byte0]: 37
8607 13:58:55.065222 [Byte1]: 37
8608 13:58:55.070042
8609 13:58:55.070123 Set Vref, RX VrefLevel [Byte0]: 38
8610 13:58:55.073025 [Byte1]: 38
8611 13:58:55.077317
8612 13:58:55.077398 Set Vref, RX VrefLevel [Byte0]: 39
8613 13:58:55.080482 [Byte1]: 39
8614 13:58:55.085051
8615 13:58:55.085132 Set Vref, RX VrefLevel [Byte0]: 40
8616 13:58:55.088197 [Byte1]: 40
8617 13:58:55.092897
8618 13:58:55.092995 Set Vref, RX VrefLevel [Byte0]: 41
8619 13:58:55.095949 [Byte1]: 41
8620 13:58:55.100314
8621 13:58:55.100396 Set Vref, RX VrefLevel [Byte0]: 42
8622 13:58:55.103691 [Byte1]: 42
8623 13:58:55.107897
8624 13:58:55.107983 Set Vref, RX VrefLevel [Byte0]: 43
8625 13:58:55.111161 [Byte1]: 43
8626 13:58:55.115375
8627 13:58:55.115508 Set Vref, RX VrefLevel [Byte0]: 44
8628 13:58:55.118862 [Byte1]: 44
8629 13:58:55.123112
8630 13:58:55.123192 Set Vref, RX VrefLevel [Byte0]: 45
8631 13:58:55.126337 [Byte1]: 45
8632 13:58:55.130984
8633 13:58:55.133745 Set Vref, RX VrefLevel [Byte0]: 46
8634 13:58:55.137084 [Byte1]: 46
8635 13:58:55.137164
8636 13:58:55.140502 Set Vref, RX VrefLevel [Byte0]: 47
8637 13:58:55.143623 [Byte1]: 47
8638 13:58:55.143704
8639 13:58:55.147261 Set Vref, RX VrefLevel [Byte0]: 48
8640 13:58:55.150327 [Byte1]: 48
8641 13:58:55.150425
8642 13:58:55.153960 Set Vref, RX VrefLevel [Byte0]: 49
8643 13:58:55.157194 [Byte1]: 49
8644 13:58:55.161216
8645 13:58:55.161296 Set Vref, RX VrefLevel [Byte0]: 50
8646 13:58:55.164495 [Byte1]: 50
8647 13:58:55.168768
8648 13:58:55.168843 Set Vref, RX VrefLevel [Byte0]: 51
8649 13:58:55.172035 [Byte1]: 51
8650 13:58:55.176366
8651 13:58:55.176436 Set Vref, RX VrefLevel [Byte0]: 52
8652 13:58:55.179878 [Byte1]: 52
8653 13:58:55.184176
8654 13:58:55.184255 Set Vref, RX VrefLevel [Byte0]: 53
8655 13:58:55.187077 [Byte1]: 53
8656 13:58:55.191642
8657 13:58:55.191722 Set Vref, RX VrefLevel [Byte0]: 54
8658 13:58:55.195009 [Byte1]: 54
8659 13:58:55.199067
8660 13:58:55.199147 Set Vref, RX VrefLevel [Byte0]: 55
8661 13:58:55.202778 [Byte1]: 55
8662 13:58:55.206858
8663 13:58:55.206945 Set Vref, RX VrefLevel [Byte0]: 56
8664 13:58:55.209921 [Byte1]: 56
8665 13:58:55.214481
8666 13:58:55.214561 Set Vref, RX VrefLevel [Byte0]: 57
8667 13:58:55.217507 [Byte1]: 57
8668 13:58:55.221759
8669 13:58:55.221840 Set Vref, RX VrefLevel [Byte0]: 58
8670 13:58:55.225296 [Byte1]: 58
8671 13:58:55.229762
8672 13:58:55.229842 Set Vref, RX VrefLevel [Byte0]: 59
8673 13:58:55.233130 [Byte1]: 59
8674 13:58:55.237047
8675 13:58:55.237128 Set Vref, RX VrefLevel [Byte0]: 60
8676 13:58:55.240805 [Byte1]: 60
8677 13:58:55.245074
8678 13:58:55.245154 Set Vref, RX VrefLevel [Byte0]: 61
8679 13:58:55.248328 [Byte1]: 61
8680 13:58:55.252575
8681 13:58:55.252655 Set Vref, RX VrefLevel [Byte0]: 62
8682 13:58:55.255783 [Byte1]: 62
8683 13:58:55.260249
8684 13:58:55.260329 Set Vref, RX VrefLevel [Byte0]: 63
8685 13:58:55.266463 [Byte1]: 63
8686 13:58:55.266568
8687 13:58:55.270073 Set Vref, RX VrefLevel [Byte0]: 64
8688 13:58:55.273098 [Byte1]: 64
8689 13:58:55.273179
8690 13:58:55.276604 Set Vref, RX VrefLevel [Byte0]: 65
8691 13:58:55.279909 [Byte1]: 65
8692 13:58:55.279990
8693 13:58:55.283283 Set Vref, RX VrefLevel [Byte0]: 66
8694 13:58:55.286324 [Byte1]: 66
8695 13:58:55.290817
8696 13:58:55.290897 Set Vref, RX VrefLevel [Byte0]: 67
8697 13:58:55.293620 [Byte1]: 67
8698 13:58:55.298227
8699 13:58:55.298308 Set Vref, RX VrefLevel [Byte0]: 68
8700 13:58:55.301587 [Byte1]: 68
8701 13:58:55.305956
8702 13:58:55.306036 Set Vref, RX VrefLevel [Byte0]: 69
8703 13:58:55.308791 [Byte1]: 69
8704 13:58:55.313664
8705 13:58:55.313745 Set Vref, RX VrefLevel [Byte0]: 70
8706 13:58:55.317085 [Byte1]: 70
8707 13:58:55.320880
8708 13:58:55.320962 Set Vref, RX VrefLevel [Byte0]: 71
8709 13:58:55.324242 [Byte1]: 71
8710 13:58:55.328583
8711 13:58:55.328665 Set Vref, RX VrefLevel [Byte0]: 72
8712 13:58:55.332241 [Byte1]: 72
8713 13:58:55.336270
8714 13:58:55.336351 Set Vref, RX VrefLevel [Byte0]: 73
8715 13:58:55.339346 [Byte1]: 73
8716 13:58:55.343605
8717 13:58:55.343687 Set Vref, RX VrefLevel [Byte0]: 74
8718 13:58:55.347136 [Byte1]: 74
8719 13:58:55.351446
8720 13:58:55.351527 Set Vref, RX VrefLevel [Byte0]: 75
8721 13:58:55.354735 [Byte1]: 75
8722 13:58:55.359306
8723 13:58:55.359388 Set Vref, RX VrefLevel [Byte0]: 76
8724 13:58:55.365336 [Byte1]: 76
8725 13:58:55.365418
8726 13:58:55.368816 Final RX Vref Byte 0 = 57 to rank0
8727 13:58:55.372235 Final RX Vref Byte 1 = 55 to rank0
8728 13:58:55.375362 Final RX Vref Byte 0 = 57 to rank1
8729 13:58:55.379107 Final RX Vref Byte 1 = 55 to rank1==
8730 13:58:55.382213 Dram Type= 6, Freq= 0, CH_1, rank 0
8731 13:58:55.385567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 13:58:55.385649 ==
8733 13:58:55.385714 DQS Delay:
8734 13:58:55.389247 DQS0 = 0, DQS1 = 0
8735 13:58:55.389330 DQM Delay:
8736 13:58:55.392217 DQM0 = 131, DQM1 = 124
8737 13:58:55.392298 DQ Delay:
8738 13:58:55.395262 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8739 13:58:55.398611 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8740 13:58:55.402013 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
8741 13:58:55.405794 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8742 13:58:55.405876
8743 13:58:55.405940
8744 13:58:55.406000
8745 13:58:55.409155 [DramC_TX_OE_Calibration] TA2
8746 13:58:55.412093 Original DQ_B0 (3 6) =30, OEN = 27
8747 13:58:55.415321 Original DQ_B1 (3 6) =30, OEN = 27
8748 13:58:55.419068 24, 0x0, End_B0=24 End_B1=24
8749 13:58:55.422330 25, 0x0, End_B0=25 End_B1=25
8750 13:58:55.422414 26, 0x0, End_B0=26 End_B1=26
8751 13:58:55.425406 27, 0x0, End_B0=27 End_B1=27
8752 13:58:55.428408 28, 0x0, End_B0=28 End_B1=28
8753 13:58:55.431934 29, 0x0, End_B0=29 End_B1=29
8754 13:58:55.435619 30, 0x0, End_B0=30 End_B1=30
8755 13:58:55.435709 31, 0x5151, End_B0=30 End_B1=30
8756 13:58:55.438868 Byte0 end_step=30 best_step=27
8757 13:58:55.441759 Byte1 end_step=30 best_step=27
8758 13:58:55.445199 Byte0 TX OE(2T, 0.5T) = (3, 3)
8759 13:58:55.448440 Byte1 TX OE(2T, 0.5T) = (3, 3)
8760 13:58:55.448522
8761 13:58:55.448587
8762 13:58:55.455298 [DQSOSCAuto] RK0, (LSB)MR18= 0x1802, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
8763 13:58:55.458653 CH1 RK0: MR19=303, MR18=1802
8764 13:58:55.465373 CH1_RK0: MR19=0x303, MR18=0x1802, DQSOSC=397, MR23=63, INC=23, DEC=15
8765 13:58:55.465456
8766 13:58:55.468635 ----->DramcWriteLeveling(PI) begin...
8767 13:58:55.468719 ==
8768 13:58:55.471718 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 13:58:55.475349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 13:58:55.475432 ==
8771 13:58:55.478733 Write leveling (Byte 0): 25 => 25
8772 13:58:55.482139 Write leveling (Byte 1): 28 => 28
8773 13:58:55.484947 DramcWriteLeveling(PI) end<-----
8774 13:58:55.485028
8775 13:58:55.485093 ==
8776 13:58:55.488521 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 13:58:55.492069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 13:58:55.495066 ==
8779 13:58:55.495148 [Gating] SW mode calibration
8780 13:58:55.505134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8781 13:58:55.508509 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8782 13:58:55.512009 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 13:58:55.518595 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 13:58:55.521912 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
8785 13:58:55.525247 1 4 12 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8786 13:58:55.531788 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 13:58:55.535464 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 13:58:55.538472 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 13:58:55.545368 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 13:58:55.548559 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 13:58:55.552026 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8792 13:58:55.558891 1 5 8 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 0)
8793 13:58:55.562414 1 5 12 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
8794 13:58:55.565243 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 13:58:55.568644 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 13:58:55.575688 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 13:58:55.578746 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 13:58:55.582159 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 13:58:55.588765 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 13:58:55.592075 1 6 8 | B1->B0 | 2828 3e3e | 0 0 | (0 0) (0 0)
8801 13:58:55.595896 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
8802 13:58:55.602268 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 13:58:55.605701 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 13:58:55.608895 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 13:58:55.615686 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 13:58:55.619222 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 13:58:55.622426 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8808 13:58:55.625825 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8809 13:58:55.632218 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8810 13:58:55.635596 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8811 13:58:55.638906 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 13:58:55.645723 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 13:58:55.649395 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 13:58:55.652573 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 13:58:55.659264 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 13:58:55.662487 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 13:58:55.666662 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 13:58:55.672458 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 13:58:55.676513 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 13:58:55.679090 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 13:58:55.685801 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 13:58:55.689424 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 13:58:55.692607 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8824 13:58:55.699136 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8825 13:58:55.702534 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8826 13:58:55.706226 Total UI for P1: 0, mck2ui 16
8827 13:58:55.709510 best dqsien dly found for B0: ( 1, 9, 6)
8828 13:58:55.712838 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 13:58:55.716041 Total UI for P1: 0, mck2ui 16
8830 13:58:55.719207 best dqsien dly found for B1: ( 1, 9, 10)
8831 13:58:55.722684 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8832 13:58:55.725889 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8833 13:58:55.725969
8834 13:58:55.729289 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8835 13:58:55.732961 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8836 13:58:55.736001 [Gating] SW calibration Done
8837 13:58:55.736082 ==
8838 13:58:55.739538 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 13:58:55.743076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 13:58:55.746335 ==
8841 13:58:55.746415 RX Vref Scan: 0
8842 13:58:55.746478
8843 13:58:55.749591 RX Vref 0 -> 0, step: 1
8844 13:58:55.749684
8845 13:58:55.749748 RX Delay 0 -> 252, step: 8
8846 13:58:55.756526 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8847 13:58:55.759847 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8848 13:58:55.762894 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8849 13:58:55.766630 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8850 13:58:55.769825 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8851 13:58:55.776483 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8852 13:58:55.780116 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8853 13:58:55.783265 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8854 13:58:55.786658 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8855 13:58:55.789756 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8856 13:58:55.796317 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8857 13:58:55.799732 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8858 13:58:55.803019 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8859 13:58:55.806313 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8860 13:58:55.809752 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8861 13:58:55.816316 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8862 13:58:55.816423 ==
8863 13:58:55.819681 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 13:58:55.822906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 13:58:55.822987 ==
8866 13:58:55.823051 DQS Delay:
8867 13:58:55.826301 DQS0 = 0, DQS1 = 0
8868 13:58:55.826381 DQM Delay:
8869 13:58:55.829827 DQM0 = 132, DQM1 = 127
8870 13:58:55.829907 DQ Delay:
8871 13:58:55.832904 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8872 13:58:55.836493 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8873 13:58:55.840045 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8874 13:58:55.843514 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8875 13:58:55.843594
8876 13:58:55.846504
8877 13:58:55.846622 ==
8878 13:58:55.850147 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 13:58:55.852852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 13:58:55.852933 ==
8881 13:58:55.852997
8882 13:58:55.853057
8883 13:58:55.856170 TX Vref Scan disable
8884 13:58:55.856250 == TX Byte 0 ==
8885 13:58:55.862976 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8886 13:58:55.866598 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8887 13:58:55.866678 == TX Byte 1 ==
8888 13:58:55.872486 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8889 13:58:55.875918 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8890 13:58:55.875999 ==
8891 13:58:55.879416 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 13:58:55.882979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 13:58:55.883060 ==
8894 13:58:55.897019
8895 13:58:55.900738 TX Vref early break, caculate TX vref
8896 13:58:55.904104 TX Vref=16, minBit 8, minWin=22, winSum=374
8897 13:58:55.907177 TX Vref=18, minBit 8, minWin=22, winSum=385
8898 13:58:55.910363 TX Vref=20, minBit 8, minWin=22, winSum=396
8899 13:58:55.913755 TX Vref=22, minBit 8, minWin=23, winSum=400
8900 13:58:55.917510 TX Vref=24, minBit 9, minWin=24, winSum=412
8901 13:58:55.923922 TX Vref=26, minBit 11, minWin=24, winSum=419
8902 13:58:55.927512 TX Vref=28, minBit 8, minWin=25, winSum=420
8903 13:58:55.930642 TX Vref=30, minBit 4, minWin=25, winSum=421
8904 13:58:55.934152 TX Vref=32, minBit 0, minWin=25, winSum=412
8905 13:58:55.937116 TX Vref=34, minBit 15, minWin=24, winSum=404
8906 13:58:55.940636 TX Vref=36, minBit 0, minWin=23, winSum=392
8907 13:58:55.947596 [TxChooseVref] Worse bit 4, Min win 25, Win sum 421, Final Vref 30
8908 13:58:55.947677
8909 13:58:55.950854 Final TX Range 0 Vref 30
8910 13:58:55.950934
8911 13:58:55.950997 ==
8912 13:58:55.954063 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 13:58:55.957323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 13:58:55.957407 ==
8915 13:58:55.957478
8916 13:58:55.957538
8917 13:58:55.960889 TX Vref Scan disable
8918 13:58:55.967296 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8919 13:58:55.967377 == TX Byte 0 ==
8920 13:58:55.970638 u2DelayCellOfst[0]=17 cells (5 PI)
8921 13:58:55.974020 u2DelayCellOfst[1]=14 cells (4 PI)
8922 13:58:55.977575 u2DelayCellOfst[2]=0 cells (0 PI)
8923 13:58:55.981192 u2DelayCellOfst[3]=7 cells (2 PI)
8924 13:58:55.984502 u2DelayCellOfst[4]=7 cells (2 PI)
8925 13:58:55.987428 u2DelayCellOfst[5]=21 cells (6 PI)
8926 13:58:55.990933 u2DelayCellOfst[6]=17 cells (5 PI)
8927 13:58:55.991014 u2DelayCellOfst[7]=3 cells (1 PI)
8928 13:58:55.997713 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8929 13:58:56.000976 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8930 13:58:56.001052 == TX Byte 1 ==
8931 13:58:56.004140 u2DelayCellOfst[8]=0 cells (0 PI)
8932 13:58:56.007290 u2DelayCellOfst[9]=3 cells (1 PI)
8933 13:58:56.010914 u2DelayCellOfst[10]=7 cells (2 PI)
8934 13:58:56.014356 u2DelayCellOfst[11]=3 cells (1 PI)
8935 13:58:56.017591 u2DelayCellOfst[12]=10 cells (3 PI)
8936 13:58:56.020882 u2DelayCellOfst[13]=14 cells (4 PI)
8937 13:58:56.024215 u2DelayCellOfst[14]=10 cells (3 PI)
8938 13:58:56.027492 u2DelayCellOfst[15]=10 cells (3 PI)
8939 13:58:56.031070 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8940 13:58:56.034473 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8941 13:58:56.037665 DramC Write-DBI on
8942 13:58:56.037746 ==
8943 13:58:56.041011 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 13:58:56.044273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 13:58:56.044355 ==
8946 13:58:56.044428
8947 13:58:56.044489
8948 13:58:56.047752 TX Vref Scan disable
8949 13:58:56.051134 == TX Byte 0 ==
8950 13:58:56.054919 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8951 13:58:56.057780 == TX Byte 1 ==
8952 13:58:56.060743 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8953 13:58:56.060824 DramC Write-DBI off
8954 13:58:56.060887
8955 13:58:56.064109 [DATLAT]
8956 13:58:56.064216 Freq=1600, CH1 RK1
8957 13:58:56.064292
8958 13:58:56.067620 DATLAT Default: 0xf
8959 13:58:56.067726 0, 0xFFFF, sum = 0
8960 13:58:56.070668 1, 0xFFFF, sum = 0
8961 13:58:56.070801 2, 0xFFFF, sum = 0
8962 13:58:56.074244 3, 0xFFFF, sum = 0
8963 13:58:56.074352 4, 0xFFFF, sum = 0
8964 13:58:56.077613 5, 0xFFFF, sum = 0
8965 13:58:56.077703 6, 0xFFFF, sum = 0
8966 13:58:56.081253 7, 0xFFFF, sum = 0
8967 13:58:56.081335 8, 0xFFFF, sum = 0
8968 13:58:56.084186 9, 0xFFFF, sum = 0
8969 13:58:56.084268 10, 0xFFFF, sum = 0
8970 13:58:56.087433 11, 0xFFFF, sum = 0
8971 13:58:56.091354 12, 0xFFFF, sum = 0
8972 13:58:56.091435 13, 0xFFFF, sum = 0
8973 13:58:56.094686 14, 0x0, sum = 1
8974 13:58:56.094798 15, 0x0, sum = 2
8975 13:58:56.094864 16, 0x0, sum = 3
8976 13:58:56.097834 17, 0x0, sum = 4
8977 13:58:56.097917 best_step = 15
8978 13:58:56.097982
8979 13:58:56.101099 ==
8980 13:58:56.101181 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 13:58:56.107507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 13:58:56.107590 ==
8983 13:58:56.107655 RX Vref Scan: 0
8984 13:58:56.107716
8985 13:58:56.110923 RX Vref 0 -> 0, step: 1
8986 13:58:56.111005
8987 13:58:56.114164 RX Delay 11 -> 252, step: 4
8988 13:58:56.117726 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8989 13:58:56.120937 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8990 13:58:56.127455 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8991 13:58:56.130967 iDelay=195, Bit 3, Center 128 (79 ~ 178) 100
8992 13:58:56.134100 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8993 13:58:56.137383 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8994 13:58:56.140905 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8995 13:58:56.147524 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8996 13:58:56.150727 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8997 13:58:56.154358 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8998 13:58:56.157509 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8999 13:58:56.160948 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
9000 13:58:56.167192 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9001 13:58:56.170628 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9002 13:58:56.174691 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9003 13:58:56.177297 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9004 13:58:56.177379 ==
9005 13:58:56.180810 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 13:58:56.187882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 13:58:56.187966 ==
9008 13:58:56.188032 DQS Delay:
9009 13:58:56.188134 DQS0 = 0, DQS1 = 0
9010 13:58:56.190576 DQM Delay:
9011 13:58:56.190683 DQM0 = 129, DQM1 = 126
9012 13:58:56.193983 DQ Delay:
9013 13:58:56.198089 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =128
9014 13:58:56.200943 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9015 13:58:56.204039 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =116
9016 13:58:56.207337 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
9017 13:58:56.207420
9018 13:58:56.207485
9019 13:58:56.207545
9020 13:58:56.210561 [DramC_TX_OE_Calibration] TA2
9021 13:58:56.214084 Original DQ_B0 (3 6) =30, OEN = 27
9022 13:58:56.217471 Original DQ_B1 (3 6) =30, OEN = 27
9023 13:58:56.220720 24, 0x0, End_B0=24 End_B1=24
9024 13:58:56.220802 25, 0x0, End_B0=25 End_B1=25
9025 13:58:56.223834 26, 0x0, End_B0=26 End_B1=26
9026 13:58:56.227195 27, 0x0, End_B0=27 End_B1=27
9027 13:58:56.230617 28, 0x0, End_B0=28 End_B1=28
9028 13:58:56.230754 29, 0x0, End_B0=29 End_B1=29
9029 13:58:56.234017 30, 0x0, End_B0=30 End_B1=30
9030 13:58:56.237230 31, 0x4141, End_B0=30 End_B1=30
9031 13:58:56.240499 Byte0 end_step=30 best_step=27
9032 13:58:56.243900 Byte1 end_step=30 best_step=27
9033 13:58:56.247130 Byte0 TX OE(2T, 0.5T) = (3, 3)
9034 13:58:56.247211 Byte1 TX OE(2T, 0.5T) = (3, 3)
9035 13:58:56.250399
9036 13:58:56.250480
9037 13:58:56.257094 [DQSOSCAuto] RK1, (LSB)MR18= 0xf15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9038 13:58:56.260542 CH1 RK1: MR19=303, MR18=F15
9039 13:58:56.267739 CH1_RK1: MR19=0x303, MR18=0xF15, DQSOSC=399, MR23=63, INC=23, DEC=15
9040 13:58:56.267822 [RxdqsGatingPostProcess] freq 1600
9041 13:58:56.274002 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9042 13:58:56.277057 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 13:58:56.280374 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 13:58:56.283976 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 13:58:56.287643 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 13:58:56.290625 best DQS0 dly(2T, 0.5T) = (1, 1)
9047 13:58:56.294559 best DQS1 dly(2T, 0.5T) = (1, 1)
9048 13:58:56.294671 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9049 13:58:56.297642 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9050 13:58:56.300583 Pre-setting of DQS Precalculation
9051 13:58:56.307226 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9052 13:58:56.314487 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9053 13:58:56.320935 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9054 13:58:56.321018
9055 13:58:56.321083
9056 13:58:56.323936 [Calibration Summary] 3200 Mbps
9057 13:58:56.327553 CH 0, Rank 0
9058 13:58:56.327635 SW Impedance : PASS
9059 13:58:56.330815 DUTY Scan : NO K
9060 13:58:56.330896 ZQ Calibration : PASS
9061 13:58:56.334165 Jitter Meter : NO K
9062 13:58:56.337312 CBT Training : PASS
9063 13:58:56.337393 Write leveling : PASS
9064 13:58:56.340812 RX DQS gating : PASS
9065 13:58:56.344238 RX DQ/DQS(RDDQC) : PASS
9066 13:58:56.344319 TX DQ/DQS : PASS
9067 13:58:56.347722 RX DATLAT : PASS
9068 13:58:56.351017 RX DQ/DQS(Engine): PASS
9069 13:58:56.351124 TX OE : PASS
9070 13:58:56.354204 All Pass.
9071 13:58:56.354301
9072 13:58:56.354389 CH 0, Rank 1
9073 13:58:56.357880 SW Impedance : PASS
9074 13:58:56.357987 DUTY Scan : NO K
9075 13:58:56.361160 ZQ Calibration : PASS
9076 13:58:56.364306 Jitter Meter : NO K
9077 13:58:56.364388 CBT Training : PASS
9078 13:58:56.367859 Write leveling : PASS
9079 13:58:56.367941 RX DQS gating : PASS
9080 13:58:56.370977 RX DQ/DQS(RDDQC) : PASS
9081 13:58:56.374460 TX DQ/DQS : PASS
9082 13:58:56.374543 RX DATLAT : PASS
9083 13:58:56.377687 RX DQ/DQS(Engine): PASS
9084 13:58:56.380913 TX OE : PASS
9085 13:58:56.380995 All Pass.
9086 13:58:56.381060
9087 13:58:56.381120 CH 1, Rank 0
9088 13:58:56.384121 SW Impedance : PASS
9089 13:58:56.387364 DUTY Scan : NO K
9090 13:58:56.387446 ZQ Calibration : PASS
9091 13:58:56.391546 Jitter Meter : NO K
9092 13:58:56.394307 CBT Training : PASS
9093 13:58:56.394388 Write leveling : PASS
9094 13:58:56.397988 RX DQS gating : PASS
9095 13:58:56.401177 RX DQ/DQS(RDDQC) : PASS
9096 13:58:56.401259 TX DQ/DQS : PASS
9097 13:58:56.404438 RX DATLAT : PASS
9098 13:58:56.404520 RX DQ/DQS(Engine): PASS
9099 13:58:56.407764 TX OE : PASS
9100 13:58:56.407846 All Pass.
9101 13:58:56.407911
9102 13:58:56.410933 CH 1, Rank 1
9103 13:58:56.411015 SW Impedance : PASS
9104 13:58:56.414397 DUTY Scan : NO K
9105 13:58:56.417950 ZQ Calibration : PASS
9106 13:58:56.418031 Jitter Meter : NO K
9107 13:58:56.421150 CBT Training : PASS
9108 13:58:56.424593 Write leveling : PASS
9109 13:58:56.424675 RX DQS gating : PASS
9110 13:58:56.427810 RX DQ/DQS(RDDQC) : PASS
9111 13:58:56.431026 TX DQ/DQS : PASS
9112 13:58:56.431108 RX DATLAT : PASS
9113 13:58:56.434623 RX DQ/DQS(Engine): PASS
9114 13:58:56.437872 TX OE : PASS
9115 13:58:56.437954 All Pass.
9116 13:58:56.438019
9117 13:58:56.438080 DramC Write-DBI on
9118 13:58:56.441250 PER_BANK_REFRESH: Hybrid Mode
9119 13:58:56.444215 TX_TRACKING: ON
9120 13:58:56.451034 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9121 13:58:56.461191 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9122 13:58:56.467671 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9123 13:58:56.471147 [FAST_K] Save calibration result to emmc
9124 13:58:56.474260 sync common calibartion params.
9125 13:58:56.474342 sync cbt_mode0:1, 1:1
9126 13:58:56.477866 dram_init: ddr_geometry: 2
9127 13:58:56.481266 dram_init: ddr_geometry: 2
9128 13:58:56.484587 dram_init: ddr_geometry: 2
9129 13:58:56.484668 0:dram_rank_size:100000000
9130 13:58:56.487951 1:dram_rank_size:100000000
9131 13:58:56.494324 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9132 13:58:56.494406 DFS_SHUFFLE_HW_MODE: ON
9133 13:58:56.498130 dramc_set_vcore_voltage set vcore to 725000
9134 13:58:56.501532 Read voltage for 1600, 0
9135 13:58:56.501629 Vio18 = 0
9136 13:58:56.504547 Vcore = 725000
9137 13:58:56.504629 Vdram = 0
9138 13:58:56.504694 Vddq = 0
9139 13:58:56.507819 Vmddr = 0
9140 13:58:56.507900 switch to 3200 Mbps bootup
9141 13:58:56.511115 [DramcRunTimeConfig]
9142 13:58:56.511197 PHYPLL
9143 13:58:56.514709 DPM_CONTROL_AFTERK: ON
9144 13:58:56.514832 PER_BANK_REFRESH: ON
9145 13:58:56.518037 REFRESH_OVERHEAD_REDUCTION: ON
9146 13:58:56.521092 CMD_PICG_NEW_MODE: OFF
9147 13:58:56.521172 XRTWTW_NEW_MODE: ON
9148 13:58:56.524606 XRTRTR_NEW_MODE: ON
9149 13:58:56.524686 TX_TRACKING: ON
9150 13:58:56.528316 RDSEL_TRACKING: OFF
9151 13:58:56.531259 DQS Precalculation for DVFS: ON
9152 13:58:56.531340 RX_TRACKING: OFF
9153 13:58:56.534675 HW_GATING DBG: ON
9154 13:58:56.534802 ZQCS_ENABLE_LP4: ON
9155 13:58:56.538022 RX_PICG_NEW_MODE: ON
9156 13:58:56.538095 TX_PICG_NEW_MODE: ON
9157 13:58:56.541298 ENABLE_RX_DCM_DPHY: ON
9158 13:58:56.544545 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9159 13:58:56.548068 DUMMY_READ_FOR_TRACKING: OFF
9160 13:58:56.548149 !!! SPM_CONTROL_AFTERK: OFF
9161 13:58:56.551282 !!! SPM could not control APHY
9162 13:58:56.554517 IMPEDANCE_TRACKING: ON
9163 13:58:56.554623 TEMP_SENSOR: ON
9164 13:58:56.557875 HW_SAVE_FOR_SR: OFF
9165 13:58:56.561285 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9166 13:58:56.565037 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9167 13:58:56.565118 Read ODT Tracking: ON
9168 13:58:56.567973 Refresh Rate DeBounce: ON
9169 13:58:56.571408 DFS_NO_QUEUE_FLUSH: ON
9170 13:58:56.574470 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9171 13:58:56.574551 ENABLE_DFS_RUNTIME_MRW: OFF
9172 13:58:56.578069 DDR_RESERVE_NEW_MODE: ON
9173 13:58:56.581590 MR_CBT_SWITCH_FREQ: ON
9174 13:58:56.581670 =========================
9175 13:58:56.601612 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9176 13:58:56.605206 dram_init: ddr_geometry: 2
9177 13:58:56.623421 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9178 13:58:56.626896 dram_init: dram init end (result: 0)
9179 13:58:56.633378 DRAM-K: Full calibration passed in 24586 msecs
9180 13:58:56.636961 MRC: failed to locate region type 0.
9181 13:58:56.637043 DRAM rank0 size:0x100000000,
9182 13:58:56.640251 DRAM rank1 size=0x100000000
9183 13:58:56.649928 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9184 13:58:56.657027 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9185 13:58:56.663562 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9186 13:58:56.669918 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9187 13:58:56.674039 DRAM rank0 size:0x100000000,
9188 13:58:56.676757 DRAM rank1 size=0x100000000
9189 13:58:56.676831 CBMEM:
9190 13:58:56.680201 IMD: root @ 0xfffff000 254 entries.
9191 13:58:56.683652 IMD: root @ 0xffffec00 62 entries.
9192 13:58:56.686710 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9193 13:58:56.690054 WARNING: RO_VPD is uninitialized or empty.
9194 13:58:56.697274 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9195 13:58:56.703425 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9196 13:58:56.716481 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9197 13:58:56.727582 BS: romstage times (exec / console): total (unknown) / 24086 ms
9198 13:58:56.727663
9199 13:58:56.727728
9200 13:58:56.737482 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9201 13:58:56.740717 ARM64: Exception handlers installed.
9202 13:58:56.744089 ARM64: Testing exception
9203 13:58:56.747716 ARM64: Done test exception
9204 13:58:56.747797 Enumerating buses...
9205 13:58:56.751034 Show all devs... Before device enumeration.
9206 13:58:56.754161 Root Device: enabled 1
9207 13:58:56.757516 CPU_CLUSTER: 0: enabled 1
9208 13:58:56.757596 CPU: 00: enabled 1
9209 13:58:56.760898 Compare with tree...
9210 13:58:56.760979 Root Device: enabled 1
9211 13:58:56.764187 CPU_CLUSTER: 0: enabled 1
9212 13:58:56.767410 CPU: 00: enabled 1
9213 13:58:56.767492 Root Device scanning...
9214 13:58:56.770678 scan_static_bus for Root Device
9215 13:58:56.774026 CPU_CLUSTER: 0 enabled
9216 13:58:56.777186 scan_static_bus for Root Device done
9217 13:58:56.781362 scan_bus: bus Root Device finished in 8 msecs
9218 13:58:56.781443 done
9219 13:58:56.787381 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9220 13:58:56.790960 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9221 13:58:56.797427 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9222 13:58:56.800689 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9223 13:58:56.803752 Allocating resources...
9224 13:58:56.803833 Reading resources...
9225 13:58:56.810549 Root Device read_resources bus 0 link: 0
9226 13:58:56.810656 DRAM rank0 size:0x100000000,
9227 13:58:56.814008 DRAM rank1 size=0x100000000
9228 13:58:56.817383 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9229 13:58:56.820724 CPU: 00 missing read_resources
9230 13:58:56.824115 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9231 13:58:56.830582 Root Device read_resources bus 0 link: 0 done
9232 13:58:56.830689 Done reading resources.
9233 13:58:56.837563 Show resources in subtree (Root Device)...After reading.
9234 13:58:56.840655 Root Device child on link 0 CPU_CLUSTER: 0
9235 13:58:56.844053 CPU_CLUSTER: 0 child on link 0 CPU: 00
9236 13:58:56.854004 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9237 13:58:56.854086 CPU: 00
9238 13:58:56.857381 Root Device assign_resources, bus 0 link: 0
9239 13:58:56.861031 CPU_CLUSTER: 0 missing set_resources
9240 13:58:56.864459 Root Device assign_resources, bus 0 link: 0 done
9241 13:58:56.867967 Done setting resources.
9242 13:58:56.874237 Show resources in subtree (Root Device)...After assigning values.
9243 13:58:56.878023 Root Device child on link 0 CPU_CLUSTER: 0
9244 13:58:56.881302 CPU_CLUSTER: 0 child on link 0 CPU: 00
9245 13:58:56.890921 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9246 13:58:56.891002 CPU: 00
9247 13:58:56.894223 Done allocating resources.
9248 13:58:56.897351 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9249 13:58:56.901122 Enabling resources...
9250 13:58:56.901211 done.
9251 13:58:56.904552 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9252 13:58:56.907530 Initializing devices...
9253 13:58:56.911166 Root Device init
9254 13:58:56.911247 init hardware done!
9255 13:58:56.914442 0x00000018: ctrlr->caps
9256 13:58:56.914551 52.000 MHz: ctrlr->f_max
9257 13:58:56.917660 0.400 MHz: ctrlr->f_min
9258 13:58:56.920763 0x40ff8080: ctrlr->voltages
9259 13:58:56.920846 sclk: 390625
9260 13:58:56.923969 Bus Width = 1
9261 13:58:56.924050 sclk: 390625
9262 13:58:56.924114 Bus Width = 1
9263 13:58:56.927510 Early init status = 3
9264 13:58:56.930485 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9265 13:58:56.936200 in-header: 03 fc 00 00 01 00 00 00
9266 13:58:56.939183 in-data: 00
9267 13:58:56.942471 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9268 13:58:56.948702 in-header: 03 fd 00 00 00 00 00 00
9269 13:58:56.951736 in-data:
9270 13:58:56.955176 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9271 13:58:56.959029 in-header: 03 fc 00 00 01 00 00 00
9272 13:58:56.962496 in-data: 00
9273 13:58:56.966102 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9274 13:58:56.971681 in-header: 03 fd 00 00 00 00 00 00
9275 13:58:56.975160 in-data:
9276 13:58:56.978357 [SSUSB] Setting up USB HOST controller...
9277 13:58:56.981395 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9278 13:58:56.985087 [SSUSB] phy power-on done.
9279 13:58:56.988253 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9280 13:58:56.995006 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9281 13:58:56.998304 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9282 13:58:57.004819 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9283 13:58:57.011521 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9284 13:58:57.018553 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9285 13:58:57.024795 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9286 13:58:57.031896 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9287 13:58:57.031979 SPM: binary array size = 0x9dc
9288 13:58:57.038193 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9289 13:58:57.045073 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9290 13:58:57.051384 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9291 13:58:57.055031 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9292 13:58:57.058251 configure_display: Starting display init
9293 13:58:57.094993 anx7625_power_on_init: Init interface.
9294 13:58:57.097958 anx7625_disable_pd_protocol: Disabled PD feature.
9295 13:58:57.101459 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9296 13:58:57.129275 anx7625_start_dp_work: Secure OCM version=00
9297 13:58:57.132818 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9298 13:58:57.147034 sp_tx_get_edid_block: EDID Block = 1
9299 13:58:57.249860 Extracted contents:
9300 13:58:57.253178 header: 00 ff ff ff ff ff ff 00
9301 13:58:57.256470 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9302 13:58:57.259832 version: 01 04
9303 13:58:57.263226 basic params: 95 1f 11 78 0a
9304 13:58:57.266541 chroma info: 76 90 94 55 54 90 27 21 50 54
9305 13:58:57.269988 established: 00 00 00
9306 13:58:57.276422 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9307 13:58:57.279894 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9308 13:58:57.286468 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9309 13:58:57.293554 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9310 13:58:57.299784 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9311 13:58:57.303204 extensions: 00
9312 13:58:57.303327 checksum: fb
9313 13:58:57.303450
9314 13:58:57.306527 Manufacturer: IVO Model 57d Serial Number 0
9315 13:58:57.309938 Made week 0 of 2020
9316 13:58:57.310018 EDID version: 1.4
9317 13:58:57.313131 Digital display
9318 13:58:57.316332 6 bits per primary color channel
9319 13:58:57.316415 DisplayPort interface
9320 13:58:57.319740 Maximum image size: 31 cm x 17 cm
9321 13:58:57.319822 Gamma: 220%
9322 13:58:57.323207 Check DPMS levels
9323 13:58:57.326472 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9324 13:58:57.329774 First detailed timing is preferred timing
9325 13:58:57.333285 Established timings supported:
9326 13:58:57.336399 Standard timings supported:
9327 13:58:57.336480 Detailed timings
9328 13:58:57.343639 Hex of detail: 383680a07038204018303c0035ae10000019
9329 13:58:57.346412 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9330 13:58:57.350092 0780 0798 07c8 0820 hborder 0
9331 13:58:57.357057 0438 043b 0447 0458 vborder 0
9332 13:58:57.357139 -hsync -vsync
9333 13:58:57.360146 Did detailed timing
9334 13:58:57.363421 Hex of detail: 000000000000000000000000000000000000
9335 13:58:57.366946 Manufacturer-specified data, tag 0
9336 13:58:57.373680 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9337 13:58:57.373762 ASCII string: InfoVision
9338 13:58:57.380062 Hex of detail: 000000fe00523134304e574635205248200a
9339 13:58:57.380149 ASCII string: R140NWF5 RH
9340 13:58:57.383547 Checksum
9341 13:58:57.383629 Checksum: 0xfb (valid)
9342 13:58:57.390253 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9343 13:58:57.390335 DSI data_rate: 832800000 bps
9344 13:58:57.397279 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9345 13:58:57.400784 anx7625_parse_edid: pixelclock(138800).
9346 13:58:57.403931 hactive(1920), hsync(48), hfp(24), hbp(88)
9347 13:58:57.407339 vactive(1080), vsync(12), vfp(3), vbp(17)
9348 13:58:57.411039 anx7625_dsi_config: config dsi.
9349 13:58:57.417487 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9350 13:58:57.432257 anx7625_dsi_config: success to config DSI
9351 13:58:57.435063 anx7625_dp_start: MIPI phy setup OK.
9352 13:58:57.438694 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9353 13:58:57.441751 mtk_ddp_mode_set invalid vrefresh 60
9354 13:58:57.445366 main_disp_path_setup
9355 13:58:57.445447 ovl_layer_smi_id_en
9356 13:58:57.448769 ovl_layer_smi_id_en
9357 13:58:57.448850 ccorr_config
9358 13:58:57.448915 aal_config
9359 13:58:57.452178 gamma_config
9360 13:58:57.452259 postmask_config
9361 13:58:57.455619 dither_config
9362 13:58:57.458585 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9363 13:58:57.465460 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9364 13:58:57.468666 Root Device init finished in 555 msecs
9365 13:58:57.468747 CPU_CLUSTER: 0 init
9366 13:58:57.479061 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9367 13:58:57.481961 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9368 13:58:57.485454 APU_MBOX 0x190000b0 = 0x10001
9369 13:58:57.488936 APU_MBOX 0x190001b0 = 0x10001
9370 13:58:57.492214 APU_MBOX 0x190005b0 = 0x10001
9371 13:58:57.492296 APU_MBOX 0x190006b0 = 0x10001
9372 13:58:57.499127 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9373 13:58:57.511112 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9374 13:58:57.523126 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9375 13:58:57.529883 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9376 13:58:57.541789 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9377 13:58:57.550652 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9378 13:58:57.554094 CPU_CLUSTER: 0 init finished in 81 msecs
9379 13:58:57.557240 Devices initialized
9380 13:58:57.560822 Show all devs... After init.
9381 13:58:57.560904 Root Device: enabled 1
9382 13:58:57.564232 CPU_CLUSTER: 0: enabled 1
9383 13:58:57.567432 CPU: 00: enabled 1
9384 13:58:57.570854 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9385 13:58:57.574257 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9386 13:58:57.577335 ELOG: NV offset 0x57f000 size 0x1000
9387 13:58:57.584023 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9388 13:58:57.590973 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9389 13:58:57.594393 ELOG: Event(17) added with size 13 at 2023-09-21 13:58:59 UTC
9390 13:58:57.597369 out: cmd=0x121: 03 db 21 01 00 00 00 00
9391 13:58:57.601410 in-header: 03 cc 00 00 2c 00 00 00
9392 13:58:57.614566 in-data: 93 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9393 13:58:57.620863 ELOG: Event(A1) added with size 10 at 2023-09-21 13:58:59 UTC
9394 13:58:57.627537 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9395 13:58:57.634252 ELOG: Event(A0) added with size 9 at 2023-09-21 13:58:59 UTC
9396 13:58:57.637614 elog_add_boot_reason: Logged dev mode boot
9397 13:58:57.640899 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9398 13:58:57.644329 Finalize devices...
9399 13:58:57.644410 Devices finalized
9400 13:58:57.651053 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9401 13:58:57.654285 Writing coreboot table at 0xffe64000
9402 13:58:57.657484 0. 000000000010a000-0000000000113fff: RAMSTAGE
9403 13:58:57.660736 1. 0000000040000000-00000000400fffff: RAM
9404 13:58:57.664268 2. 0000000040100000-000000004032afff: RAMSTAGE
9405 13:58:57.670990 3. 000000004032b000-00000000545fffff: RAM
9406 13:58:57.674064 4. 0000000054600000-000000005465ffff: BL31
9407 13:58:57.677550 5. 0000000054660000-00000000ffe63fff: RAM
9408 13:58:57.681001 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9409 13:58:57.687592 7. 0000000100000000-000000023fffffff: RAM
9410 13:58:57.687674 Passing 5 GPIOs to payload:
9411 13:58:57.694350 NAME | PORT | POLARITY | VALUE
9412 13:58:57.697970 EC in RW | 0x000000aa | low | undefined
9413 13:58:57.704382 EC interrupt | 0x00000005 | low | undefined
9414 13:58:57.707772 TPM interrupt | 0x000000ab | high | undefined
9415 13:58:57.711471 SD card detect | 0x00000011 | high | undefined
9416 13:58:57.717514 speaker enable | 0x00000093 | high | undefined
9417 13:58:57.721215 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9418 13:58:57.724930 in-header: 03 f9 00 00 02 00 00 00
9419 13:58:57.725011 in-data: 02 00
9420 13:58:57.727878 ADC[4]: Raw value=899852 ID=7
9421 13:58:57.731057 ADC[3]: Raw value=213336 ID=1
9422 13:58:57.731155 RAM Code: 0x71
9423 13:58:57.734492 ADC[6]: Raw value=74557 ID=0
9424 13:58:57.737549 ADC[5]: Raw value=211860 ID=1
9425 13:58:57.737630 SKU Code: 0x1
9426 13:58:57.744387 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ae81
9427 13:58:57.748402 coreboot table: 964 bytes.
9428 13:58:57.750956 IMD ROOT 0. 0xfffff000 0x00001000
9429 13:58:57.754546 IMD SMALL 1. 0xffffe000 0x00001000
9430 13:58:57.757862 RO MCACHE 2. 0xffffc000 0x00001104
9431 13:58:57.760855 CONSOLE 3. 0xfff7c000 0x00080000
9432 13:58:57.764848 FMAP 4. 0xfff7b000 0x00000452
9433 13:58:57.767444 TIME STAMP 5. 0xfff7a000 0x00000910
9434 13:58:57.770871 VBOOT WORK 6. 0xfff66000 0x00014000
9435 13:58:57.774268 RAMOOPS 7. 0xffe66000 0x00100000
9436 13:58:57.777526 COREBOOT 8. 0xffe64000 0x00002000
9437 13:58:57.777607 IMD small region:
9438 13:58:57.780980 IMD ROOT 0. 0xffffec00 0x00000400
9439 13:58:57.784487 VPD 1. 0xffffeb80 0x0000006c
9440 13:58:57.788456 MMC STATUS 2. 0xffffeb60 0x00000004
9441 13:58:57.794272 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9442 13:58:57.794354 Probing TPM: done!
9443 13:58:57.801240 Connected to device vid:did:rid of 1ae0:0028:00
9444 13:58:57.808004 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9445 13:58:57.811043 Initialized TPM device CR50 revision 0
9446 13:58:57.814707 Checking cr50 for pending updates
9447 13:58:57.820414 Reading cr50 TPM mode
9448 13:58:57.829048 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9449 13:58:57.835629 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9450 13:58:57.875760 read SPI 0x3990ec 0x4f1b0: 34856 us, 9295 KB/s, 74.360 Mbps
9451 13:58:57.879223 Checking segment from ROM address 0x40100000
9452 13:58:57.882825 Checking segment from ROM address 0x4010001c
9453 13:58:57.889248 Loading segment from ROM address 0x40100000
9454 13:58:57.889329 code (compression=0)
9455 13:58:57.895910 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9456 13:58:57.906214 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9457 13:58:57.906297 it's not compressed!
9458 13:58:57.913007 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9459 13:58:57.916737 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9460 13:58:57.936450 Loading segment from ROM address 0x4010001c
9461 13:58:57.936533 Entry Point 0x80000000
9462 13:58:57.940114 Loaded segments
9463 13:58:57.943237 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9464 13:58:57.949723 Jumping to boot code at 0x80000000(0xffe64000)
9465 13:58:57.956358 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9466 13:58:57.963263 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9467 13:58:57.970674 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9468 13:58:57.973912 Checking segment from ROM address 0x40100000
9469 13:58:57.977325 Checking segment from ROM address 0x4010001c
9470 13:58:57.984000 Loading segment from ROM address 0x40100000
9471 13:58:57.984081 code (compression=1)
9472 13:58:57.991031 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9473 13:58:58.001039 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9474 13:58:58.001137 using LZMA
9475 13:58:58.008888 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9476 13:58:58.016017 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9477 13:58:58.019425 Loading segment from ROM address 0x4010001c
9478 13:58:58.019507 Entry Point 0x54601000
9479 13:58:58.022518 Loaded segments
9480 13:58:58.026296 NOTICE: MT8192 bl31_setup
9481 13:58:58.032739 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9482 13:58:58.035953 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9483 13:58:58.039873 WARNING: region 0:
9484 13:58:58.042852 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 13:58:58.042933 WARNING: region 1:
9486 13:58:58.049238 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9487 13:58:58.052839 WARNING: region 2:
9488 13:58:58.056579 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9489 13:58:58.059842 WARNING: region 3:
9490 13:58:58.063014 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 13:58:58.066374 WARNING: region 4:
9492 13:58:58.069884 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9493 13:58:58.072728 WARNING: region 5:
9494 13:58:58.076545 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 13:58:58.079770 WARNING: region 6:
9496 13:58:58.082915 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 13:58:58.082996 WARNING: region 7:
9498 13:58:58.089386 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 13:58:58.096183 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9500 13:58:58.099858 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9501 13:58:58.103312 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9502 13:58:58.106336 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9503 13:58:58.113219 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9504 13:58:58.116481 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9505 13:58:58.123295 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9506 13:58:58.126994 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9507 13:58:58.130136 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9508 13:58:58.136625 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9509 13:58:58.140219 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9510 13:58:58.143606 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9511 13:58:58.150287 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9512 13:58:58.154459 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9513 13:58:58.157215 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9514 13:58:58.163634 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9515 13:58:58.166919 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9516 13:58:58.170279 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9517 13:58:58.177119 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9518 13:58:58.181204 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9519 13:58:58.187631 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9520 13:58:58.190611 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9521 13:58:58.194015 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9522 13:58:58.200974 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9523 13:58:58.204172 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9524 13:58:58.207568 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9525 13:58:58.214173 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9526 13:58:58.217557 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9527 13:58:58.224400 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9528 13:58:58.227722 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9529 13:58:58.231407 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9530 13:58:58.237567 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9531 13:58:58.241124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9532 13:58:58.244823 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9533 13:58:58.247838 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9534 13:58:58.254632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9535 13:58:58.257709 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9536 13:58:58.261165 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9537 13:58:58.264618 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9538 13:58:58.271376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9539 13:58:58.274594 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9540 13:58:58.278183 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9541 13:58:58.281154 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9542 13:58:58.288283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9543 13:58:58.291828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9544 13:58:58.295300 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9545 13:58:58.298068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9546 13:58:58.305307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9547 13:58:58.308332 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9548 13:58:58.311493 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9549 13:58:58.318755 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9550 13:58:58.321823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9551 13:58:58.328764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9552 13:58:58.331764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9553 13:58:58.335119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9554 13:58:58.342083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9555 13:58:58.345788 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9556 13:58:58.352231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9557 13:58:58.355710 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9558 13:58:58.362250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9559 13:58:58.365436 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9560 13:58:58.368835 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9561 13:58:58.376094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9562 13:58:58.379048 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9563 13:58:58.385974 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9564 13:58:58.389069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9565 13:58:58.395600 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9566 13:58:58.399355 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9567 13:58:58.402842 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9568 13:58:58.409405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9569 13:58:58.412481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9570 13:58:58.419520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9571 13:58:58.422797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9572 13:58:58.425883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9573 13:58:58.432756 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9574 13:58:58.435940 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9575 13:58:58.442618 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9576 13:58:58.446363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9577 13:58:58.453051 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9578 13:58:58.456155 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9579 13:58:58.459800 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9580 13:58:58.466055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9581 13:58:58.469613 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9582 13:58:58.476143 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9583 13:58:58.480189 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9584 13:58:58.486684 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9585 13:58:58.489901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9586 13:58:58.493649 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9587 13:58:58.499682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9588 13:58:58.503304 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9589 13:58:58.509738 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9590 13:58:58.513356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9591 13:58:58.516547 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9592 13:58:58.523336 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9593 13:58:58.526884 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9594 13:58:58.533398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9595 13:58:58.536904 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9596 13:58:58.539998 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9597 13:58:58.543551 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9598 13:58:58.550424 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9599 13:58:58.553427 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9600 13:58:58.557104 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9601 13:58:58.563748 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9602 13:58:58.567391 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9603 13:58:58.574320 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9604 13:58:58.577630 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9605 13:58:58.581075 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9606 13:58:58.587431 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9607 13:58:58.590565 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9608 13:58:58.593850 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9609 13:58:58.600740 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9610 13:58:58.604246 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9611 13:58:58.610853 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9612 13:58:58.614125 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9613 13:58:58.617431 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9614 13:58:58.624396 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9615 13:58:58.627569 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9616 13:58:58.630898 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9617 13:58:58.637629 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9618 13:58:58.641290 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9619 13:58:58.644859 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9620 13:58:58.647879 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9621 13:58:58.651535 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9622 13:58:58.658007 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9623 13:58:58.661363 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9624 13:58:58.664535 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9625 13:58:58.671325 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9626 13:58:58.674707 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9627 13:58:58.681567 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9628 13:58:58.684514 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9629 13:58:58.688259 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9630 13:58:58.694500 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9631 13:58:58.698322 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9632 13:58:58.704882 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9633 13:58:58.708185 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9634 13:58:58.711676 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9635 13:58:58.717986 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9636 13:58:58.721519 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9637 13:58:58.724910 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9638 13:58:58.731352 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9639 13:58:58.734926 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9640 13:58:58.741708 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9641 13:58:58.745060 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9642 13:58:58.748802 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9643 13:58:58.755152 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9644 13:58:58.758433 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9645 13:58:58.762761 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9646 13:58:58.768473 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9647 13:58:58.771879 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9648 13:58:58.778838 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9649 13:58:58.782012 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9650 13:58:58.785560 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9651 13:58:58.791889 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9652 13:58:58.795536 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9653 13:58:58.798956 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9654 13:58:58.805307 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9655 13:58:58.808649 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9656 13:58:58.815611 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9657 13:58:58.818929 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9658 13:58:58.822383 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9659 13:58:58.828843 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9660 13:58:58.832360 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9661 13:58:58.835443 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9662 13:58:58.842606 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9663 13:58:58.845798 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9664 13:58:58.852804 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9665 13:58:58.855969 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9666 13:58:58.859107 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9667 13:58:58.865582 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9668 13:58:58.868916 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9669 13:58:58.872302 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9670 13:58:58.879342 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9671 13:58:58.882292 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9672 13:58:58.889731 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9673 13:58:58.892445 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9674 13:58:58.895626 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9675 13:58:58.902545 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9676 13:58:58.905932 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9677 13:58:58.912564 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9678 13:58:58.916082 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9679 13:58:58.918939 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9680 13:58:58.925999 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9681 13:58:58.929325 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9682 13:58:58.932506 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9683 13:58:58.939285 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9684 13:58:58.942636 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9685 13:58:58.945931 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9686 13:58:58.952763 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9687 13:58:58.956010 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9688 13:58:58.962727 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9689 13:58:58.966279 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9690 13:58:58.972742 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9691 13:58:58.975740 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9692 13:58:58.978978 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9693 13:58:58.985714 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9694 13:58:58.989524 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9695 13:58:58.995840 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9696 13:58:58.999504 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9697 13:58:59.002453 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9698 13:58:59.009249 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9699 13:58:59.012848 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9700 13:58:59.019600 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9701 13:58:59.022642 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9702 13:58:59.026203 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9703 13:58:59.032812 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9704 13:58:59.035911 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9705 13:58:59.042976 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9706 13:58:59.046181 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9707 13:58:59.049296 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9708 13:58:59.056258 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9709 13:58:59.059528 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9710 13:58:59.066247 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9711 13:58:59.069620 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9712 13:58:59.076378 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9713 13:58:59.079740 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9714 13:58:59.083185 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9715 13:58:59.089493 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9716 13:58:59.092901 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9717 13:58:59.099776 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9718 13:58:59.103377 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9719 13:58:59.106277 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9720 13:58:59.113051 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9721 13:58:59.116493 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9722 13:58:59.123124 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9723 13:58:59.126592 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9724 13:58:59.130027 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9725 13:58:59.136346 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9726 13:58:59.140097 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9727 13:58:59.146471 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9728 13:58:59.149621 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9729 13:58:59.153181 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9730 13:58:59.156289 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9731 13:58:59.159908 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9732 13:58:59.166398 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9733 13:58:59.169800 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9734 13:58:59.173492 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9735 13:58:59.180087 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9736 13:58:59.183693 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9737 13:58:59.187242 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9738 13:58:59.193636 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9739 13:58:59.197449 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9740 13:58:59.203933 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9741 13:58:59.207074 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9742 13:58:59.210290 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9743 13:58:59.217117 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9744 13:58:59.220277 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9745 13:58:59.224237 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9746 13:58:59.230826 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9747 13:58:59.233879 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9748 13:58:59.237733 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9749 13:58:59.244232 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9750 13:58:59.247819 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9751 13:58:59.254168 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9752 13:58:59.257505 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9753 13:58:59.260764 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9754 13:58:59.267304 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9755 13:58:59.270870 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9756 13:58:59.274177 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9757 13:58:59.281163 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9758 13:58:59.284487 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9759 13:58:59.287441 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9760 13:58:59.294479 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9761 13:58:59.297467 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9762 13:58:59.300988 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9763 13:58:59.307615 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9764 13:58:59.310795 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9765 13:58:59.317594 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9766 13:58:59.320612 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9767 13:58:59.324741 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9768 13:58:59.327267 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9769 13:58:59.334412 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9770 13:58:59.337396 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9771 13:58:59.341015 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9772 13:58:59.343999 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9773 13:58:59.347468 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9774 13:58:59.354599 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9775 13:58:59.358262 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9776 13:58:59.361235 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9777 13:58:59.364656 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9778 13:58:59.370979 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9779 13:58:59.374633 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9780 13:58:59.377582 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9781 13:58:59.384568 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9782 13:58:59.387790 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9783 13:58:59.391365 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9784 13:58:59.398139 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9785 13:58:59.401177 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9786 13:58:59.407632 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9787 13:58:59.411109 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9788 13:58:59.414534 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9789 13:58:59.421079 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9790 13:58:59.424315 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9791 13:58:59.431608 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9792 13:58:59.434426 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9793 13:58:59.441000 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9794 13:58:59.444969 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9795 13:58:59.447586 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9796 13:58:59.454243 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9797 13:58:59.457783 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9798 13:58:59.461014 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9799 13:58:59.468060 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9800 13:58:59.471242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9801 13:58:59.478378 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9802 13:58:59.480952 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9803 13:58:59.488103 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9804 13:58:59.491355 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9805 13:58:59.494902 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9806 13:58:59.501068 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9807 13:58:59.504763 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9808 13:58:59.507815 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9809 13:58:59.514970 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9810 13:58:59.518231 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9811 13:58:59.525033 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9812 13:58:59.528091 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9813 13:58:59.531708 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9814 13:58:59.537892 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9815 13:58:59.541403 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9816 13:58:59.548326 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9817 13:58:59.551606 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9818 13:58:59.557949 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9819 13:58:59.561924 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9820 13:58:59.564684 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9821 13:58:59.571667 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9822 13:58:59.574949 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9823 13:58:59.578152 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9824 13:58:59.585429 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9825 13:58:59.588018 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9826 13:58:59.595408 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9827 13:58:59.598620 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9828 13:58:59.601377 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9829 13:58:59.608462 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9830 13:58:59.611670 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9831 13:58:59.618702 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9832 13:58:59.621486 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9833 13:58:59.625097 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9834 13:58:59.632363 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9835 13:58:59.635118 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9836 13:58:59.641683 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9837 13:58:59.645530 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9838 13:58:59.648656 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9839 13:58:59.655150 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9840 13:58:59.658930 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9841 13:58:59.665512 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9842 13:58:59.668421 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9843 13:58:59.672182 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9844 13:58:59.679185 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9845 13:58:59.682560 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9846 13:58:59.688401 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9847 13:58:59.692307 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9848 13:58:59.695438 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9849 13:58:59.701819 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9850 13:58:59.705333 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9851 13:58:59.712053 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9852 13:58:59.715302 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9853 13:58:59.718373 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9854 13:58:59.725620 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9855 13:58:59.728900 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9856 13:58:59.735370 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9857 13:58:59.739173 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9858 13:58:59.745496 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9859 13:58:59.749002 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9860 13:58:59.752139 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9861 13:58:59.758599 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9862 13:58:59.762806 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9863 13:58:59.768972 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9864 13:58:59.771995 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9865 13:58:59.779344 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9866 13:58:59.782842 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9867 13:58:59.785821 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9868 13:58:59.792395 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9869 13:58:59.795960 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9870 13:58:59.802409 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9871 13:58:59.805396 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9872 13:58:59.808745 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9873 13:58:59.815562 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9874 13:58:59.818760 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9875 13:58:59.825739 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9876 13:58:59.829322 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9877 13:58:59.835513 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9878 13:58:59.838836 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9879 13:58:59.842636 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9880 13:58:59.849804 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9881 13:58:59.852668 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9882 13:58:59.859409 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9883 13:58:59.862392 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9884 13:58:59.868896 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9885 13:58:59.872344 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9886 13:58:59.875863 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9887 13:58:59.882688 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9888 13:58:59.885799 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9889 13:58:59.892874 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9890 13:58:59.895912 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9891 13:58:59.902575 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9892 13:58:59.906276 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9893 13:58:59.909752 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9894 13:58:59.916129 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9895 13:58:59.919451 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9896 13:58:59.926529 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9897 13:58:59.929433 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9898 13:58:59.935967 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9899 13:58:59.939105 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9900 13:58:59.942817 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9901 13:58:59.949604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9902 13:58:59.952705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9903 13:58:59.959176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9904 13:58:59.962454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9905 13:58:59.966137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9906 13:58:59.972766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9907 13:58:59.976217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9908 13:58:59.982897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9909 13:58:59.986457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9910 13:58:59.993281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9911 13:58:59.996623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9912 13:59:00.002943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9913 13:59:00.006271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9914 13:59:00.012662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9915 13:59:00.016070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9916 13:59:00.023094 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9917 13:59:00.026480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9918 13:59:00.032927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9919 13:59:00.036097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9920 13:59:00.042686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9921 13:59:00.046444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9922 13:59:00.049932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9923 13:59:00.056180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9924 13:59:00.059461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9925 13:59:00.066139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9926 13:59:00.070289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9927 13:59:00.076415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9928 13:59:00.079594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9929 13:59:00.086161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9930 13:59:00.090216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9931 13:59:00.096666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9932 13:59:00.099634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9933 13:59:00.106233 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9934 13:59:00.106697 INFO: [APUAPC] vio 0
9935 13:59:00.113346 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9936 13:59:00.116492 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9937 13:59:00.119754 INFO: [APUAPC] D0_APC_0: 0x400510
9938 13:59:00.123248 INFO: [APUAPC] D0_APC_1: 0x0
9939 13:59:00.126678 INFO: [APUAPC] D0_APC_2: 0x1540
9940 13:59:00.130467 INFO: [APUAPC] D0_APC_3: 0x0
9941 13:59:00.133148 INFO: [APUAPC] D1_APC_0: 0xffffffff
9942 13:59:00.136323 INFO: [APUAPC] D1_APC_1: 0xffffffff
9943 13:59:00.140102 INFO: [APUAPC] D1_APC_2: 0x3fffff
9944 13:59:00.142984 INFO: [APUAPC] D1_APC_3: 0x0
9945 13:59:00.146013 INFO: [APUAPC] D2_APC_0: 0xffffffff
9946 13:59:00.150267 INFO: [APUAPC] D2_APC_1: 0xffffffff
9947 13:59:00.153060 INFO: [APUAPC] D2_APC_2: 0x3fffff
9948 13:59:00.156678 INFO: [APUAPC] D2_APC_3: 0x0
9949 13:59:00.159550 INFO: [APUAPC] D3_APC_0: 0xffffffff
9950 13:59:00.163154 INFO: [APUAPC] D3_APC_1: 0xffffffff
9951 13:59:00.166210 INFO: [APUAPC] D3_APC_2: 0x3fffff
9952 13:59:00.166630 INFO: [APUAPC] D3_APC_3: 0x0
9953 13:59:00.169490 INFO: [APUAPC] D4_APC_0: 0xffffffff
9954 13:59:00.176286 INFO: [APUAPC] D4_APC_1: 0xffffffff
9955 13:59:00.180082 INFO: [APUAPC] D4_APC_2: 0x3fffff
9956 13:59:00.180500 INFO: [APUAPC] D4_APC_3: 0x0
9957 13:59:00.183794 INFO: [APUAPC] D5_APC_0: 0xffffffff
9958 13:59:00.186604 INFO: [APUAPC] D5_APC_1: 0xffffffff
9959 13:59:00.190355 INFO: [APUAPC] D5_APC_2: 0x3fffff
9960 13:59:00.193380 INFO: [APUAPC] D5_APC_3: 0x0
9961 13:59:00.196553 INFO: [APUAPC] D6_APC_0: 0xffffffff
9962 13:59:00.200384 INFO: [APUAPC] D6_APC_1: 0xffffffff
9963 13:59:00.203233 INFO: [APUAPC] D6_APC_2: 0x3fffff
9964 13:59:00.206615 INFO: [APUAPC] D6_APC_3: 0x0
9965 13:59:00.210477 INFO: [APUAPC] D7_APC_0: 0xffffffff
9966 13:59:00.213462 INFO: [APUAPC] D7_APC_1: 0xffffffff
9967 13:59:00.217153 INFO: [APUAPC] D7_APC_2: 0x3fffff
9968 13:59:00.219949 INFO: [APUAPC] D7_APC_3: 0x0
9969 13:59:00.223575 INFO: [APUAPC] D8_APC_0: 0xffffffff
9970 13:59:00.226864 INFO: [APUAPC] D8_APC_1: 0xffffffff
9971 13:59:00.230108 INFO: [APUAPC] D8_APC_2: 0x3fffff
9972 13:59:00.233283 INFO: [APUAPC] D8_APC_3: 0x0
9973 13:59:00.237211 INFO: [APUAPC] D9_APC_0: 0xffffffff
9974 13:59:00.240711 INFO: [APUAPC] D9_APC_1: 0xffffffff
9975 13:59:00.243191 INFO: [APUAPC] D9_APC_2: 0x3fffff
9976 13:59:00.246975 INFO: [APUAPC] D9_APC_3: 0x0
9977 13:59:00.250262 INFO: [APUAPC] D10_APC_0: 0xffffffff
9978 13:59:00.253831 INFO: [APUAPC] D10_APC_1: 0xffffffff
9979 13:59:00.256931 INFO: [APUAPC] D10_APC_2: 0x3fffff
9980 13:59:00.260646 INFO: [APUAPC] D10_APC_3: 0x0
9981 13:59:00.263301 INFO: [APUAPC] D11_APC_0: 0xffffffff
9982 13:59:00.267043 INFO: [APUAPC] D11_APC_1: 0xffffffff
9983 13:59:00.269948 INFO: [APUAPC] D11_APC_2: 0x3fffff
9984 13:59:00.273641 INFO: [APUAPC] D11_APC_3: 0x0
9985 13:59:00.276830 INFO: [APUAPC] D12_APC_0: 0xffffffff
9986 13:59:00.280086 INFO: [APUAPC] D12_APC_1: 0xffffffff
9987 13:59:00.283623 INFO: [APUAPC] D12_APC_2: 0x3fffff
9988 13:59:00.287128 INFO: [APUAPC] D12_APC_3: 0x0
9989 13:59:00.290238 INFO: [APUAPC] D13_APC_0: 0xffffffff
9990 13:59:00.293906 INFO: [APUAPC] D13_APC_1: 0xffffffff
9991 13:59:00.297161 INFO: [APUAPC] D13_APC_2: 0x3fffff
9992 13:59:00.300469 INFO: [APUAPC] D13_APC_3: 0x0
9993 13:59:00.303108 INFO: [APUAPC] D14_APC_0: 0xffffffff
9994 13:59:00.306827 INFO: [APUAPC] D14_APC_1: 0xffffffff
9995 13:59:00.310083 INFO: [APUAPC] D14_APC_2: 0x3fffff
9996 13:59:00.313594 INFO: [APUAPC] D14_APC_3: 0x0
9997 13:59:00.317297 INFO: [APUAPC] D15_APC_0: 0xffffffff
9998 13:59:00.320460 INFO: [APUAPC] D15_APC_1: 0xffffffff
9999 13:59:00.323437 INFO: [APUAPC] D15_APC_2: 0x3fffff
10000 13:59:00.326564 INFO: [APUAPC] D15_APC_3: 0x0
10001 13:59:00.330493 INFO: [APUAPC] APC_CON: 0x4
10002 13:59:00.333450 INFO: [NOCDAPC] D0_APC_0: 0x0
10003 13:59:00.333931 INFO: [NOCDAPC] D0_APC_1: 0x0
10004 13:59:00.336588 INFO: [NOCDAPC] D1_APC_0: 0x0
10005 13:59:00.339896 INFO: [NOCDAPC] D1_APC_1: 0xfff
10006 13:59:00.344115 INFO: [NOCDAPC] D2_APC_0: 0x0
10007 13:59:00.346809 INFO: [NOCDAPC] D2_APC_1: 0xfff
10008 13:59:00.349983 INFO: [NOCDAPC] D3_APC_0: 0x0
10009 13:59:00.353933 INFO: [NOCDAPC] D3_APC_1: 0xfff
10010 13:59:00.357026 INFO: [NOCDAPC] D4_APC_0: 0x0
10011 13:59:00.360176 INFO: [NOCDAPC] D4_APC_1: 0xfff
10012 13:59:00.363403 INFO: [NOCDAPC] D5_APC_0: 0x0
10013 13:59:00.367335 INFO: [NOCDAPC] D5_APC_1: 0xfff
10014 13:59:00.367911 INFO: [NOCDAPC] D6_APC_0: 0x0
10015 13:59:00.370562 INFO: [NOCDAPC] D6_APC_1: 0xfff
10016 13:59:00.374004 INFO: [NOCDAPC] D7_APC_0: 0x0
10017 13:59:00.376603 INFO: [NOCDAPC] D7_APC_1: 0xfff
10018 13:59:00.379964 INFO: [NOCDAPC] D8_APC_0: 0x0
10019 13:59:00.383304 INFO: [NOCDAPC] D8_APC_1: 0xfff
10020 13:59:00.387080 INFO: [NOCDAPC] D9_APC_0: 0x0
10021 13:59:00.390472 INFO: [NOCDAPC] D9_APC_1: 0xfff
10022 13:59:00.393552 INFO: [NOCDAPC] D10_APC_0: 0x0
10023 13:59:00.397396 INFO: [NOCDAPC] D10_APC_1: 0xfff
10024 13:59:00.397956 INFO: [NOCDAPC] D11_APC_0: 0x0
10025 13:59:00.400108 INFO: [NOCDAPC] D11_APC_1: 0xfff
10026 13:59:00.403765 INFO: [NOCDAPC] D12_APC_0: 0x0
10027 13:59:00.406899 INFO: [NOCDAPC] D12_APC_1: 0xfff
10028 13:59:00.410811 INFO: [NOCDAPC] D13_APC_0: 0x0
10029 13:59:00.414081 INFO: [NOCDAPC] D13_APC_1: 0xfff
10030 13:59:00.417140 INFO: [NOCDAPC] D14_APC_0: 0x0
10031 13:59:00.420091 INFO: [NOCDAPC] D14_APC_1: 0xfff
10032 13:59:00.423873 INFO: [NOCDAPC] D15_APC_0: 0x0
10033 13:59:00.426697 INFO: [NOCDAPC] D15_APC_1: 0xfff
10034 13:59:00.430041 INFO: [NOCDAPC] APC_CON: 0x4
10035 13:59:00.433686 INFO: [APUAPC] set_apusys_apc done
10036 13:59:00.437054 INFO: [DEVAPC] devapc_init done
10037 13:59:00.440307 INFO: GICv3 without legacy support detected.
10038 13:59:00.443692 INFO: ARM GICv3 driver initialized in EL3
10039 13:59:00.447060 INFO: Maximum SPI INTID supported: 639
10040 13:59:00.450306 INFO: BL31: Initializing runtime services
10041 13:59:00.456830 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10042 13:59:00.460966 INFO: SPM: enable CPC mode
10043 13:59:00.463438 INFO: mcdi ready for mcusys-off-idle and system suspend
10044 13:59:00.470455 INFO: BL31: Preparing for EL3 exit to normal world
10045 13:59:00.474006 INFO: Entry point address = 0x80000000
10046 13:59:00.477023 INFO: SPSR = 0x8
10047 13:59:00.481185
10048 13:59:00.481646
10049 13:59:00.482012
10050 13:59:00.484853 Starting depthcharge on Spherion...
10051 13:59:00.485314
10052 13:59:00.485681 Wipe memory regions:
10053 13:59:00.486023
10054 13:59:00.488668 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10055 13:59:00.489208 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10056 13:59:00.489631 Setting prompt string to ['asurada:']
10057 13:59:00.490050 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10058 13:59:00.490792 [0x00000040000000, 0x00000054600000)
10059 13:59:00.610718
10060 13:59:00.611331 [0x00000054660000, 0x00000080000000)
10061 13:59:00.870860
10062 13:59:00.871425 [0x000000821a7280, 0x000000ffe64000)
10063 13:59:01.615321
10064 13:59:01.615990 [0x00000100000000, 0x00000240000000)
10065 13:59:03.505512
10066 13:59:03.508849 Initializing XHCI USB controller at 0x11200000.
10067 13:59:04.547365
10068 13:59:04.550438 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10069 13:59:04.550995
10070 13:59:04.551329
10071 13:59:04.551632
10072 13:59:04.552359 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 13:59:04.653717 asurada: tftpboot 192.168.201.1 11588101/tftp-deploy-ier9qoce/kernel/image.itb 11588101/tftp-deploy-ier9qoce/kernel/cmdline
10075 13:59:04.654362 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 13:59:04.654897 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10077 13:59:04.659216 tftpboot 192.168.201.1 11588101/tftp-deploy-ier9qoce/kernel/image.ittp-deploy-ier9qoce/kernel/cmdline
10078 13:59:04.659637
10079 13:59:04.659963 Waiting for link
10080 13:59:04.819848
10081 13:59:04.820356 R8152: Initializing
10082 13:59:04.820687
10083 13:59:04.823138 Version 6 (ocp_data = 5c30)
10084 13:59:04.823564
10085 13:59:04.826821 R8152: Done initializing
10086 13:59:04.827340
10087 13:59:04.827680 Adding net device
10088 13:59:06.751855
10089 13:59:06.752381 done.
10090 13:59:06.752722
10091 13:59:06.753031 MAC: 00:24:32:30:78:52
10092 13:59:06.753332
10093 13:59:06.755302 Sending DHCP discover... done.
10094 13:59:06.755717
10095 13:59:11.610647 Waiting for reply... done.
10096 13:59:11.611201
10097 13:59:11.611539 Sending DHCP request... done.
10098 13:59:11.613450
10099 13:59:11.617366 Waiting for reply... done.
10100 13:59:11.617780
10101 13:59:11.618109 My ip is 192.168.201.14
10102 13:59:11.618414
10103 13:59:11.620414 The DHCP server ip is 192.168.201.1
10104 13:59:11.620831
10105 13:59:11.627218 TFTP server IP predefined by user: 192.168.201.1
10106 13:59:11.627633
10107 13:59:11.630917 Bootfile predefined by user: 11588101/tftp-deploy-ier9qoce/kernel/image.itb
10108 13:59:11.633796
10109 13:59:11.634278 Sending tftp read request... done.
10110 13:59:11.634608
10111 13:59:11.643163 Waiting for the transfer...
10112 13:59:11.643577
10113 13:59:12.252974 00000000 ################################################################
10114 13:59:12.253121
10115 13:59:12.834139 00080000 ################################################################
10116 13:59:12.834286
10117 13:59:13.421295 00100000 ################################################################
10118 13:59:13.421439
10119 13:59:14.001402 00180000 ################################################################
10120 13:59:14.001537
10121 13:59:14.570206 00200000 ################################################################
10122 13:59:14.570340
10123 13:59:15.176655 00280000 ################################################################
10124 13:59:15.176797
10125 13:59:15.833210 00300000 ################################################################
10126 13:59:15.833340
10127 13:59:16.523749 00380000 ################################################################
10128 13:59:16.523883
10129 13:59:17.104517 00400000 ################################################################
10130 13:59:17.104648
10131 13:59:17.674593 00480000 ################################################################
10132 13:59:17.674733
10133 13:59:18.285208 00500000 ################################################################
10134 13:59:18.285376
10135 13:59:18.890613 00580000 ################################################################
10136 13:59:18.890784
10137 13:59:19.482008 00600000 ################################################################
10138 13:59:19.482182
10139 13:59:20.073556 00680000 ################################################################
10140 13:59:20.073695
10141 13:59:20.683345 00700000 ################################################################
10142 13:59:20.683479
10143 13:59:21.275163 00780000 ################################################################
10144 13:59:21.275298
10145 13:59:21.835156 00800000 ################################################################
10146 13:59:21.835291
10147 13:59:22.390317 00880000 ################################################################
10148 13:59:22.390450
10149 13:59:22.964808 00900000 ################################################################
10150 13:59:22.964946
10151 13:59:23.536018 00980000 ################################################################
10152 13:59:23.536184
10153 13:59:24.172379 00a00000 ################################################################
10154 13:59:24.172888
10155 13:59:24.866828 00a80000 ################################################################
10156 13:59:24.867340
10157 13:59:25.528395 00b00000 ################################################################
10158 13:59:25.528909
10159 13:59:26.227088 00b80000 ################################################################
10160 13:59:26.227598
10161 13:59:26.878109 00c00000 ################################################################
10162 13:59:26.878255
10163 13:59:27.505548 00c80000 ################################################################
10164 13:59:27.505694
10165 13:59:28.163230 00d00000 ################################################################
10166 13:59:28.163364
10167 13:59:28.803605 00d80000 ################################################################
10168 13:59:28.804354
10169 13:59:29.502585 00e00000 ################################################################
10170 13:59:29.503125
10171 13:59:30.196413 00e80000 ################################################################
10172 13:59:30.196923
10173 13:59:30.905047 00f00000 ################################################################
10174 13:59:30.905621
10175 13:59:31.587185 00f80000 ################################################################
10176 13:59:31.587385
10177 13:59:32.260712 01000000 ################################################################
10178 13:59:32.261215
10179 13:59:32.939270 01080000 ################################################################
10180 13:59:32.939403
10181 13:59:33.553227 01100000 ################################################################
10182 13:59:33.553358
10183 13:59:34.148457 01180000 ################################################################
10184 13:59:34.148639
10185 13:59:34.806330 01200000 ################################################################
10186 13:59:34.806880
10187 13:59:35.471506 01280000 ################################################################
10188 13:59:35.472031
10189 13:59:36.169148 01300000 ################################################################
10190 13:59:36.169651
10191 13:59:36.806428 01380000 ################################################################
10192 13:59:36.806966
10193 13:59:37.472833 01400000 ################################################################
10194 13:59:37.473342
10195 13:59:38.142560 01480000 ################################################################
10196 13:59:38.143146
10197 13:59:38.813141 01500000 ################################################################
10198 13:59:38.813657
10199 13:59:39.498411 01580000 ################################################################
10200 13:59:39.498963
10201 13:59:40.170240 01600000 ################################################################
10202 13:59:40.170766
10203 13:59:40.848296 01680000 ################################################################
10204 13:59:40.848442
10205 13:59:41.424240 01700000 ################################################################
10206 13:59:41.424383
10207 13:59:42.013769 01780000 ################################################################
10208 13:59:42.013913
10209 13:59:42.612509 01800000 ################################################################
10210 13:59:42.612652
10211 13:59:43.238689 01880000 ################################################################
10212 13:59:43.238851
10213 13:59:43.927296 01900000 ################################################################
10214 13:59:43.927802
10215 13:59:44.602116 01980000 ################################################################
10216 13:59:44.602624
10217 13:59:45.259998 01a00000 ################################################################
10218 13:59:45.260547
10219 13:59:45.943761 01a80000 ################################################################
10220 13:59:45.944277
10221 13:59:46.622509 01b00000 ################################################################
10222 13:59:46.623059
10223 13:59:47.226640 01b80000 ################################################################
10224 13:59:47.226856
10225 13:59:47.831155 01c00000 ################################################################
10226 13:59:47.831529
10227 13:59:48.503225 01c80000 ################################################################
10228 13:59:48.503739
10229 13:59:49.205923 01d00000 ################################################################
10230 13:59:49.206435
10232 14:03:25.490451 end: 2.2.4 bootloader-commands (duration 00:04:25) [common]
10234 14:03:25.492205 depthcharge-retry failed: 1 of 1 attempts. 'bootloader-commands timed out after 265 seconds'
10236 14:03:25.493568 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
10239 14:03:25.495809 end: 2 depthcharge-action (duration 00:05:00) [common]
10241 14:03:25.497081 Cleaning after the job
10242 14:03:25.497564 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/ramdisk
10243 14:03:25.528657 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/kernel
10244 14:03:25.561331 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/dtb
10245 14:03:25.561573 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588101/tftp-deploy-ier9qoce/modules
10246 14:03:25.569049 start: 4.1 power-off (timeout 00:00:30) [common]
10247 14:03:25.569217 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
10248 14:03:25.649849 >> Command sent successfully.
10249 14:03:25.655358 Returned 0 in 0 seconds
10250 14:03:25.756444 end: 4.1 power-off (duration 00:00:00) [common]
10252 14:03:25.758172 start: 4.2 read-feedback (timeout 00:10:00) [common]
10253 14:03:25.759619 Listened to connection for namespace 'common' for up to 1s
10254 14:03:26.760266 Finalising connection for namespace 'common'
10255 14:03:26.760962 Disconnecting from shell: Finalise
10256 14:03:26.761363 01d80000 #########################
10257 14:03:26.862387 end: 4.2 read-feedback (duration 00:00:01) [common]
10258 14:03:26.863203 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11588101
10259 14:03:27.021680 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11588101
10260 14:03:27.021876 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.