Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 132
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 20
1 13:58:58.085992 lava-dispatcher, installed at version: 2023.06
2 13:58:58.086215 start: 0 validate
3 13:58:58.086377 Start time: 2023-09-21 13:58:58.086369+00:00 (UTC)
4 13:58:58.086519 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:58:58.086708 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:58:58.353579 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:58:58.353765 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:59:10.864744 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:59:10.864971 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:59:11.132730 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:59:11.132938 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:59:14.896118 validate duration: 16.81
14 13:59:14.896382 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:59:14.896481 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:59:14.896569 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:59:14.896692 Not decompressing ramdisk as can be used compressed.
18 13:59:14.896782 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 13:59:14.896848 saving as /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/ramdisk/rootfs.cpio.gz
20 13:59:14.896913 total size: 84918747 (80 MB)
21 13:59:15.162017 progress 0 % (0 MB)
22 13:59:15.185372 progress 5 % (4 MB)
23 13:59:15.216517 progress 10 % (8 MB)
24 13:59:15.248942 progress 15 % (12 MB)
25 13:59:15.281870 progress 20 % (16 MB)
26 13:59:15.313187 progress 25 % (20 MB)
27 13:59:15.336813 progress 30 % (24 MB)
28 13:59:15.359273 progress 35 % (28 MB)
29 13:59:15.381573 progress 40 % (32 MB)
30 13:59:15.404104 progress 45 % (36 MB)
31 13:59:15.427842 progress 50 % (40 MB)
32 13:59:15.450921 progress 55 % (44 MB)
33 13:59:15.473457 progress 60 % (48 MB)
34 13:59:15.496382 progress 65 % (52 MB)
35 13:59:15.519711 progress 70 % (56 MB)
36 13:59:15.543031 progress 75 % (60 MB)
37 13:59:15.566168 progress 80 % (64 MB)
38 13:59:15.589475 progress 85 % (68 MB)
39 13:59:15.612260 progress 90 % (72 MB)
40 13:59:15.634499 progress 95 % (76 MB)
41 13:59:15.656225 progress 100 % (80 MB)
42 13:59:15.656480 80 MB downloaded in 0.76 s (106.62 MB/s)
43 13:59:15.656651 end: 1.1.1 http-download (duration 00:00:01) [common]
45 13:59:15.656896 end: 1.1 download-retry (duration 00:00:01) [common]
46 13:59:15.656987 start: 1.2 download-retry (timeout 00:09:59) [common]
47 13:59:15.657070 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 13:59:15.657212 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:59:15.657283 saving as /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/kernel/Image
50 13:59:15.657345 total size: 49304064 (47 MB)
51 13:59:15.657407 No compression specified
52 13:59:15.658471 progress 0 % (0 MB)
53 13:59:15.671416 progress 5 % (2 MB)
54 13:59:15.684487 progress 10 % (4 MB)
55 13:59:15.702774 progress 15 % (7 MB)
56 13:59:15.719780 progress 20 % (9 MB)
57 13:59:15.733043 progress 25 % (11 MB)
58 13:59:15.745889 progress 30 % (14 MB)
59 13:59:15.758844 progress 35 % (16 MB)
60 13:59:15.771715 progress 40 % (18 MB)
61 13:59:15.784858 progress 45 % (21 MB)
62 13:59:15.797901 progress 50 % (23 MB)
63 13:59:15.813559 progress 55 % (25 MB)
64 13:59:15.828654 progress 60 % (28 MB)
65 13:59:15.841895 progress 65 % (30 MB)
66 13:59:15.855005 progress 70 % (32 MB)
67 13:59:15.867928 progress 75 % (35 MB)
68 13:59:15.882730 progress 80 % (37 MB)
69 13:59:15.901926 progress 85 % (39 MB)
70 13:59:15.921312 progress 90 % (42 MB)
71 13:59:15.938901 progress 95 % (44 MB)
72 13:59:15.952251 progress 100 % (47 MB)
73 13:59:15.952499 47 MB downloaded in 0.30 s (159.31 MB/s)
74 13:59:15.952657 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:59:15.952975 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:59:15.953084 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:59:15.953187 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:59:15.953334 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:59:15.953404 saving as /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/dtb/mt8192-asurada-spherion-r0.dtb
81 13:59:15.953466 total size: 47278 (0 MB)
82 13:59:15.953528 No compression specified
83 13:59:15.954703 progress 69 % (0 MB)
84 13:59:15.955014 progress 100 % (0 MB)
85 13:59:15.955216 0 MB downloaded in 0.00 s (25.81 MB/s)
86 13:59:15.955391 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:59:15.955740 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:59:15.955857 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:59:15.955972 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:59:15.956123 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:59:15.956219 saving as /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/modules/modules.tar
93 13:59:15.956308 total size: 8629568 (8 MB)
94 13:59:15.956399 Using unxz to decompress xz
95 13:59:15.961047 progress 0 % (0 MB)
96 13:59:15.983842 progress 5 % (0 MB)
97 13:59:16.006979 progress 10 % (0 MB)
98 13:59:16.034732 progress 15 % (1 MB)
99 13:59:16.061892 progress 20 % (1 MB)
100 13:59:16.089529 progress 25 % (2 MB)
101 13:59:16.126717 progress 30 % (2 MB)
102 13:59:16.160563 progress 35 % (2 MB)
103 13:59:16.186432 progress 40 % (3 MB)
104 13:59:16.211096 progress 45 % (3 MB)
105 13:59:16.247283 progress 50 % (4 MB)
106 13:59:16.282466 progress 55 % (4 MB)
107 13:59:16.312807 progress 60 % (4 MB)
108 13:59:16.338016 progress 65 % (5 MB)
109 13:59:16.365017 progress 70 % (5 MB)
110 13:59:16.398003 progress 75 % (6 MB)
111 13:59:16.434392 progress 80 % (6 MB)
112 13:59:16.474172 progress 85 % (7 MB)
113 13:59:16.507461 progress 90 % (7 MB)
114 13:59:16.533882 progress 95 % (7 MB)
115 13:59:16.559003 progress 100 % (8 MB)
116 13:59:16.564411 8 MB downloaded in 0.61 s (13.53 MB/s)
117 13:59:16.564720 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:59:16.565124 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:59:16.565249 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 13:59:16.565376 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 13:59:16.565489 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:59:16.565616 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 13:59:16.565891 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy
125 13:59:16.566067 makedir: /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin
126 13:59:16.566208 makedir: /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/tests
127 13:59:16.566341 makedir: /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/results
128 13:59:16.566493 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-add-keys
129 13:59:16.566679 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-add-sources
130 13:59:16.566854 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-background-process-start
131 13:59:16.567021 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-background-process-stop
132 13:59:16.567183 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-common-functions
133 13:59:16.567344 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-echo-ipv4
134 13:59:16.567507 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-install-packages
135 13:59:16.567681 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-installed-packages
136 13:59:16.567845 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-os-build
137 13:59:16.568006 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-probe-channel
138 13:59:16.568167 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-probe-ip
139 13:59:16.568328 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-target-ip
140 13:59:16.568488 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-target-mac
141 13:59:16.568647 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-target-storage
142 13:59:16.568814 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-test-case
143 13:59:16.568975 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-test-event
144 13:59:16.569136 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-test-feedback
145 13:59:16.569301 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-test-raise
146 13:59:16.569462 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-test-reference
147 13:59:16.569623 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-test-runner
148 13:59:16.569783 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-test-set
149 13:59:16.569949 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-test-shell
150 13:59:16.570114 Updating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-install-packages (oe)
151 13:59:16.570305 Updating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/bin/lava-installed-packages (oe)
152 13:59:16.570469 Creating /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/environment
153 13:59:16.570604 LAVA metadata
154 13:59:16.570708 - LAVA_JOB_ID=11588075
155 13:59:16.570803 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:59:16.570944 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 13:59:16.571038 skipped lava-vland-overlay
158 13:59:16.571144 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:59:16.571258 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 13:59:16.571350 skipped lava-multinode-overlay
161 13:59:16.571471 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:59:16.571590 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 13:59:16.571712 Loading test definitions
164 13:59:16.571808 start: 1.5.2.3.1 git-repo-action (timeout 00:09:58) [common]
165 13:59:16.571886 Using /lava-11588075 at stage 0
166 13:59:16.571986 Fetching tests from https://github.com/kernelci/kernelci-core
167 13:59:16.572071 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/0/tests/0_sleep'
168 13:59:17.350617 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/0/tests/0_sleep
169 13:59:17.352993 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 13:59:17.353766 uuid=11588075_1.5.2.3.1 testdef=None
171 13:59:17.354030 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 13:59:17.354590 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 13:59:17.355984 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 13:59:17.356529 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 13:59:17.358069 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 13:59:17.358639 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 13:59:17.360254 runner path: /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/0/tests/0_sleep test_uuid 11588075_1.5.2.3.1
181 13:59:17.360425 sleep_params='mem freeze'
182 13:59:17.360695 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 13:59:17.361344 Creating lava-test-runner.conf files
185 13:59:17.361491 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11588075/lava-overlay-ol8pd5yy/lava-11588075/0 for stage 0
186 13:59:17.361673 - 0_sleep
187 13:59:17.361879 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 13:59:17.362067 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 13:59:17.527621 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 13:59:17.527785 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:57) [common]
191 13:59:17.527883 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 13:59:17.527986 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 13:59:17.528079 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
194 13:59:20.221335 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 13:59:20.221787 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 13:59:20.221919 extracting modules file /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11588075/extract-overlay-ramdisk-auebo01i/ramdisk
197 13:59:20.479057 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 13:59:20.479235 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
199 13:59:20.479334 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11588075/compress-overlay-2anbvf46/overlay-1.5.2.4.tar.gz to ramdisk
200 13:59:20.479410 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11588075/compress-overlay-2anbvf46/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11588075/extract-overlay-ramdisk-auebo01i/ramdisk
201 13:59:20.588432 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 13:59:20.588676 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
203 13:59:20.588840 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 13:59:20.588988 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
205 13:59:20.589130 Building ramdisk /var/lib/lava/dispatcher/tmp/11588075/extract-overlay-ramdisk-auebo01i/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11588075/extract-overlay-ramdisk-auebo01i/ramdisk
206 13:59:22.276282 >> 563449 blocks
207 13:59:33.137692 rename /var/lib/lava/dispatcher/tmp/11588075/extract-overlay-ramdisk-auebo01i/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/ramdisk/ramdisk.cpio.gz
208 13:59:33.138170 end: 1.5.7 compress-ramdisk (duration 00:00:13) [common]
209 13:59:33.138309 start: 1.5.8 prepare-kernel (timeout 00:09:42) [common]
210 13:59:33.138413 start: 1.5.8.1 prepare-fit (timeout 00:09:42) [common]
211 13:59:33.138528 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/kernel/Image'
212 13:59:46.776170 Returned 0 in 13 seconds
213 13:59:46.876785 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/kernel/image.itb
214 13:59:48.248909 output: FIT description: Kernel Image image with one or more FDT blobs
215 13:59:48.249401 output: Created: Thu Sep 21 14:59:47 2023
216 13:59:48.249545 output: Image 0 (kernel-1)
217 13:59:48.249667 output: Description:
218 13:59:48.249782 output: Created: Thu Sep 21 14:59:47 2023
219 13:59:48.249900 output: Type: Kernel Image
220 13:59:48.250010 output: Compression: lzma compressed
221 13:59:48.250120 output: Data Size: 11044874 Bytes = 10786.01 KiB = 10.53 MiB
222 13:59:48.250235 output: Architecture: AArch64
223 13:59:48.250353 output: OS: Linux
224 13:59:48.250464 output: Load Address: 0x00000000
225 13:59:48.250568 output: Entry Point: 0x00000000
226 13:59:48.250673 output: Hash algo: crc32
227 13:59:48.250775 output: Hash value: a5f1a0d7
228 13:59:48.250881 output: Image 1 (fdt-1)
229 13:59:48.250983 output: Description: mt8192-asurada-spherion-r0
230 13:59:48.251089 output: Created: Thu Sep 21 14:59:47 2023
231 13:59:48.251191 output: Type: Flat Device Tree
232 13:59:48.251296 output: Compression: uncompressed
233 13:59:48.251398 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 13:59:48.251504 output: Architecture: AArch64
235 13:59:48.251603 output: Hash algo: crc32
236 13:59:48.251777 output: Hash value: cc4352de
237 13:59:48.251879 output: Image 2 (ramdisk-1)
238 13:59:48.251984 output: Description: unavailable
239 13:59:48.252085 output: Created: Thu Sep 21 14:59:47 2023
240 13:59:48.252191 output: Type: RAMDisk Image
241 13:59:48.252293 output: Compression: Unknown Compression
242 13:59:48.252399 output: Data Size: 98320332 Bytes = 96015.95 KiB = 93.77 MiB
243 13:59:48.252502 output: Architecture: AArch64
244 13:59:48.252609 output: OS: Linux
245 13:59:48.252710 output: Load Address: unavailable
246 13:59:48.252817 output: Entry Point: unavailable
247 13:59:48.252945 output: Hash algo: crc32
248 13:59:48.253045 output: Hash value: d95e6abd
249 13:59:48.253161 output: Default Configuration: 'conf-1'
250 13:59:48.253248 output: Configuration 0 (conf-1)
251 13:59:48.253331 output: Description: mt8192-asurada-spherion-r0
252 13:59:48.253414 output: Kernel: kernel-1
253 13:59:48.253497 output: Init Ramdisk: ramdisk-1
254 13:59:48.253579 output: FDT: fdt-1
255 13:59:48.253660 output: Loadables: kernel-1
256 13:59:48.253741 output:
257 13:59:48.253974 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 13:59:48.254100 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 13:59:48.254234 end: 1.5 prepare-tftp-overlay (duration 00:00:32) [common]
260 13:59:48.254358 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:27) [common]
261 13:59:48.254472 No LXC device requested
262 13:59:48.254585 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 13:59:48.254704 start: 1.7 deploy-device-env (timeout 00:09:27) [common]
264 13:59:48.254810 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 13:59:48.254917 Checking files for TFTP limit of 4294967296 bytes.
266 13:59:48.255563 end: 1 tftp-deploy (duration 00:00:33) [common]
267 13:59:48.255740 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 13:59:48.255859 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 13:59:48.256020 substitutions:
270 13:59:48.256113 - {DTB}: 11588075/tftp-deploy-x8a14o6p/dtb/mt8192-asurada-spherion-r0.dtb
271 13:59:48.256206 - {INITRD}: 11588075/tftp-deploy-x8a14o6p/ramdisk/ramdisk.cpio.gz
272 13:59:48.256293 - {KERNEL}: 11588075/tftp-deploy-x8a14o6p/kernel/Image
273 13:59:48.256388 - {LAVA_MAC}: None
274 13:59:48.256474 - {PRESEED_CONFIG}: None
275 13:59:48.256558 - {PRESEED_LOCAL}: None
276 13:59:48.256641 - {RAMDISK}: 11588075/tftp-deploy-x8a14o6p/ramdisk/ramdisk.cpio.gz
277 13:59:48.256723 - {ROOT_PART}: None
278 13:59:48.256805 - {ROOT}: None
279 13:59:48.256899 - {SERVER_IP}: 192.168.201.1
280 13:59:48.256981 - {TEE}: None
281 13:59:48.257065 Parsed boot commands:
282 13:59:48.257148 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 13:59:48.257370 Parsed boot commands: tftpboot 192.168.201.1 11588075/tftp-deploy-x8a14o6p/kernel/image.itb 11588075/tftp-deploy-x8a14o6p/kernel/cmdline
284 13:59:48.257493 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 13:59:48.257604 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 13:59:48.257726 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 13:59:48.257841 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 13:59:48.257938 Not connected, no need to disconnect.
289 13:59:48.258041 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 13:59:48.258148 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 13:59:48.258242 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
292 13:59:48.262345 Setting prompt string to ['lava-test: # ']
293 13:59:48.262710 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 13:59:48.262815 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 13:59:48.262925 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 13:59:48.263081 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 13:59:48.263427 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
298 13:59:53.398120 >> Command sent successfully.
299 13:59:53.400636 Returned 0 in 5 seconds
300 13:59:53.500995 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 13:59:53.501321 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 13:59:53.501423 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 13:59:53.501516 Setting prompt string to 'Starting depthcharge on Spherion...'
305 13:59:53.501587 Changing prompt to 'Starting depthcharge on Spherion...'
306 13:59:53.501660 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 13:59:53.501920 [Enter `^Ec?' for help]
308 13:59:53.673810
309 13:59:53.673958
310 13:59:53.674029 F0: 102B 0000
311 13:59:53.674094
312 13:59:53.674155 F3: 1001 0000 [0200]
313 13:59:53.674224
314 13:59:53.677270 F3: 1001 0000
315 13:59:53.677350
316 13:59:53.677417 F7: 102D 0000
317 13:59:53.677477
318 13:59:53.677535 F1: 0000 0000
319 13:59:53.677600
320 13:59:53.681032 V0: 0000 0000 [0001]
321 13:59:53.681116
322 13:59:53.681179 00: 0007 8000
323 13:59:53.681245
324 13:59:53.685116 01: 0000 0000
325 13:59:53.685199
326 13:59:53.685263 BP: 0C00 0209 [0000]
327 13:59:53.685323
328 13:59:53.685382 G0: 1182 0000
329 13:59:53.685445
330 13:59:53.688695 EC: 0000 0021 [4000]
331 13:59:53.688769
332 13:59:53.688832 S7: 0000 0000 [0000]
333 13:59:53.692444
334 13:59:53.692518 CC: 0000 0000 [0001]
335 13:59:53.692581
336 13:59:53.692641 T0: 0000 0040 [010F]
337 13:59:53.695622
338 13:59:53.695706 Jump to BL
339 13:59:53.695768
340 13:59:53.720341
341 13:59:53.720445
342 13:59:53.720515
343 13:59:53.727891 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 13:59:53.731556 ARM64: Exception handlers installed.
345 13:59:53.735492 ARM64: Testing exception
346 13:59:53.735607 ARM64: Done test exception
347 13:59:53.742733 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 13:59:53.754743 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 13:59:53.761551 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 13:59:53.771621 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 13:59:53.778244 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 13:59:53.784980 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 13:59:53.796788 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 13:59:53.803792 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 13:59:53.823263 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 13:59:53.826032 WDT: Last reset was cold boot
357 13:59:53.829494 SPI1(PAD0) initialized at 2873684 Hz
358 13:59:53.833245 SPI5(PAD0) initialized at 992727 Hz
359 13:59:53.836621 VBOOT: Loading verstage.
360 13:59:53.843473 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 13:59:53.846438 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 13:59:53.850043 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 13:59:53.853257 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 13:59:53.860466 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 13:59:53.866926 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 13:59:53.877995 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 13:59:53.878133
368 13:59:53.878261
369 13:59:53.888784 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 13:59:53.892411 ARM64: Exception handlers installed.
371 13:59:53.892543 ARM64: Testing exception
372 13:59:53.895306 ARM64: Done test exception
373 13:59:53.898908 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 13:59:53.905700 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 13:59:53.918948 Probing TPM: . done!
376 13:59:53.919063 TPM ready after 0 ms
377 13:59:53.925930 Connected to device vid:did:rid of 1ae0:0028:00
378 13:59:53.932967 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 13:59:53.993652 Initialized TPM device CR50 revision 0
380 13:59:54.005871 tlcl_send_startup: Startup return code is 0
381 13:59:54.006025 TPM: setup succeeded
382 13:59:54.016930 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 13:59:54.026175 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 13:59:54.040387 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 13:59:54.047937 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 13:59:54.051542 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 13:59:54.054747 in-header: 03 07 00 00 08 00 00 00
388 13:59:54.058347 in-data: aa e4 47 04 13 02 00 00
389 13:59:54.058431 Chrome EC: UHEPI supported
390 13:59:54.065994 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 13:59:54.069480 in-header: 03 95 00 00 08 00 00 00
392 13:59:54.073136 in-data: 18 20 20 08 00 00 00 00
393 13:59:54.073277 Phase 1
394 13:59:54.077253 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 13:59:54.084603 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 13:59:54.088306 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 13:59:54.092057 Recovery requested (1009000e)
398 13:59:54.103653 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 13:59:54.107554 tlcl_extend: response is 0
400 13:59:54.118958 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 13:59:54.122479 tlcl_extend: response is 0
402 13:59:54.130170 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 13:59:54.148834 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 13:59:54.155906 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 13:59:54.156046
406 13:59:54.156166
407 13:59:54.165752 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 13:59:54.168879 ARM64: Exception handlers installed.
409 13:59:54.172496 ARM64: Testing exception
410 13:59:54.172627 ARM64: Done test exception
411 13:59:54.194650 pmic_efuse_setting: Set efuses in 11 msecs
412 13:59:54.198106 pmwrap_interface_init: Select PMIF_VLD_RDY
413 13:59:54.204893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 13:59:54.207901 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 13:59:54.214854 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 13:59:54.218780 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 13:59:54.222503 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 13:59:54.229169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 13:59:54.232752 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 13:59:54.236206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 13:59:54.243865 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 13:59:54.247333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 13:59:54.250947 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 13:59:54.254583 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 13:59:54.261908 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 13:59:54.265409 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 13:59:54.272358 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 13:59:54.279908 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 13:59:54.283275 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 13:59:54.291159 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 13:59:54.294486 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 13:59:54.302250 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 13:59:54.305679 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 13:59:54.313740 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 13:59:54.317416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 13:59:54.325151 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 13:59:54.328561 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 13:59:54.332481 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 13:59:54.339647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 13:59:54.343178 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 13:59:54.350314 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 13:59:54.353830 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 13:59:54.357939 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 13:59:54.365156 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 13:59:54.368689 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 13:59:54.372245 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 13:59:54.379827 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 13:59:54.383188 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 13:59:54.386901 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 13:59:54.394958 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 13:59:54.398169 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 13:59:54.401518 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 13:59:54.405096 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 13:59:54.412711 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 13:59:54.416631 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 13:59:54.419952 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 13:59:54.424150 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 13:59:54.427751 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 13:59:54.431100 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 13:59:54.438423 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 13:59:54.442216 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 13:59:54.446142 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 13:59:54.449483 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 13:59:54.457214 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 13:59:54.464627 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 13:59:54.471366 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 13:59:54.478478 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 13:59:54.485960 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 13:59:54.493325 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 13:59:54.497205 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 13:59:54.500493 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 13:59:54.508367 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x35
473 13:59:54.511470 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 13:59:54.519543 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 13:59:54.523022 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 13:59:54.532623 [RTC]rtc_get_frequency_meter,154: input=15, output=758
477 13:59:54.541971 [RTC]rtc_get_frequency_meter,154: input=23, output=942
478 13:59:54.551234 [RTC]rtc_get_frequency_meter,154: input=19, output=848
479 13:59:54.560236 [RTC]rtc_get_frequency_meter,154: input=17, output=805
480 13:59:54.570406 [RTC]rtc_get_frequency_meter,154: input=16, output=780
481 13:59:54.579866 [RTC]rtc_get_frequency_meter,154: input=16, output=782
482 13:59:54.590377 [RTC]rtc_get_frequency_meter,154: input=17, output=805
483 13:59:54.593059 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 13:59:54.597162 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 13:59:54.600987 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 13:59:54.608190 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 13:59:54.612142 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 13:59:54.615716 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 13:59:54.619692 ADC[4]: Raw value=906573 ID=7
490 13:59:54.619783 ADC[3]: Raw value=213441 ID=1
491 13:59:54.623690 RAM Code: 0x71
492 13:59:54.627265 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 13:59:54.630501 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 13:59:54.641307 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 13:59:54.644942 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 13:59:54.648501 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 13:59:54.653027 in-header: 03 07 00 00 08 00 00 00
498 13:59:54.656899 in-data: aa e4 47 04 13 02 00 00
499 13:59:54.660911 Chrome EC: UHEPI supported
500 13:59:54.667935 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 13:59:54.671931 in-header: 03 95 00 00 08 00 00 00
502 13:59:54.672022 in-data: 18 20 20 08 00 00 00 00
503 13:59:54.675083 MRC: failed to locate region type 0.
504 13:59:54.682516 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 13:59:54.686540 DRAM-K: Running full calibration
506 13:59:54.693619 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 13:59:54.693747 header.status = 0x0
508 13:59:54.697705 header.version = 0x6 (expected: 0x6)
509 13:59:54.701601 header.size = 0xd00 (expected: 0xd00)
510 13:59:54.701737 header.flags = 0x0
511 13:59:54.708122 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 13:59:54.727878 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
513 13:59:54.735418 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 13:59:54.735516 dram_init: ddr_geometry: 2
515 13:59:54.739078 [EMI] MDL number = 2
516 13:59:54.739160 [EMI] Get MDL freq = 0
517 13:59:54.743178 dram_init: ddr_type: 0
518 13:59:54.743255 is_discrete_lpddr4: 1
519 13:59:54.747568 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 13:59:54.747720
521 13:59:54.747835
522 13:59:54.750786 [Bian_co] ETT version 0.0.0.1
523 13:59:54.754787 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 13:59:54.754924
525 13:59:54.758519 dramc_set_vcore_voltage set vcore to 650000
526 13:59:54.762088 Read voltage for 800, 4
527 13:59:54.762226 Vio18 = 0
528 13:59:54.765667 Vcore = 650000
529 13:59:54.765799 Vdram = 0
530 13:59:54.765920 Vddq = 0
531 13:59:54.766038 Vmddr = 0
532 13:59:54.769644 dram_init: config_dvfs: 1
533 13:59:54.773535 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 13:59:54.780616 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 13:59:54.784731 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
536 13:59:54.788324 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
537 13:59:54.791695 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
538 13:59:54.794699 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
539 13:59:54.798161 MEM_TYPE=3, freq_sel=18
540 13:59:54.798270 sv_algorithm_assistance_LP4_1600
541 13:59:54.805123 ============ PULL DRAM RESETB DOWN ============
542 13:59:54.808356 ========== PULL DRAM RESETB DOWN end =========
543 13:59:54.811960 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 13:59:54.815477 ===================================
545 13:59:54.819441 LPDDR4 DRAM CONFIGURATION
546 13:59:54.823470 ===================================
547 13:59:54.823580 EX_ROW_EN[0] = 0x0
548 13:59:54.826754 EX_ROW_EN[1] = 0x0
549 13:59:54.826863 LP4Y_EN = 0x0
550 13:59:54.830460 WORK_FSP = 0x0
551 13:59:54.830563 WL = 0x2
552 13:59:54.833799 RL = 0x2
553 13:59:54.833904 BL = 0x2
554 13:59:54.836826 RPST = 0x0
555 13:59:54.836928 RD_PRE = 0x0
556 13:59:54.840259 WR_PRE = 0x1
557 13:59:54.840335 WR_PST = 0x0
558 13:59:54.843771 DBI_WR = 0x0
559 13:59:54.843872 DBI_RD = 0x0
560 13:59:54.847416 OTF = 0x1
561 13:59:54.850247 ===================================
562 13:59:54.854544 ===================================
563 13:59:54.854669 ANA top config
564 13:59:54.858309 ===================================
565 13:59:54.861714 DLL_ASYNC_EN = 0
566 13:59:54.861850 ALL_SLAVE_EN = 1
567 13:59:54.864900 NEW_RANK_MODE = 1
568 13:59:54.868274 DLL_IDLE_MODE = 1
569 13:59:54.871611 LP45_APHY_COMB_EN = 1
570 13:59:54.871743 TX_ODT_DIS = 1
571 13:59:54.874933 NEW_8X_MODE = 1
572 13:59:54.878742 ===================================
573 13:59:54.882254 ===================================
574 13:59:54.885893 data_rate = 1600
575 13:59:54.889090 CKR = 1
576 13:59:54.889167 DQ_P2S_RATIO = 8
577 13:59:54.892478 ===================================
578 13:59:54.895746 CA_P2S_RATIO = 8
579 13:59:54.899169 DQ_CA_OPEN = 0
580 13:59:54.902954 DQ_SEMI_OPEN = 0
581 13:59:54.905960 CA_SEMI_OPEN = 0
582 13:59:54.906086 CA_FULL_RATE = 0
583 13:59:54.909505 DQ_CKDIV4_EN = 1
584 13:59:54.912915 CA_CKDIV4_EN = 1
585 13:59:54.916099 CA_PREDIV_EN = 0
586 13:59:54.919580 PH8_DLY = 0
587 13:59:54.922987 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 13:59:54.923115 DQ_AAMCK_DIV = 4
589 13:59:54.926303 CA_AAMCK_DIV = 4
590 13:59:54.929619 CA_ADMCK_DIV = 4
591 13:59:54.932883 DQ_TRACK_CA_EN = 0
592 13:59:54.936153 CA_PICK = 800
593 13:59:54.939586 CA_MCKIO = 800
594 13:59:54.939720 MCKIO_SEMI = 0
595 13:59:54.943204 PLL_FREQ = 3068
596 13:59:54.946747 DQ_UI_PI_RATIO = 32
597 13:59:54.950811 CA_UI_PI_RATIO = 0
598 13:59:54.955051 ===================================
599 13:59:54.955174 ===================================
600 13:59:54.958550 memory_type:LPDDR4
601 13:59:54.962437 GP_NUM : 10
602 13:59:54.962557 SRAM_EN : 1
603 13:59:54.965952 MD32_EN : 0
604 13:59:54.969605 ===================================
605 13:59:54.969703 [ANA_INIT] >>>>>>>>>>>>>>
606 13:59:54.973217 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 13:59:54.977498 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 13:59:54.980308 ===================================
609 13:59:54.983582 data_rate = 1600,PCW = 0X7600
610 13:59:54.987004 ===================================
611 13:59:54.990272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 13:59:54.994072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 13:59:55.000544 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 13:59:55.003981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 13:59:55.007331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 13:59:55.010626 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 13:59:55.013767 [ANA_INIT] flow start
618 13:59:55.017352 [ANA_INIT] PLL >>>>>>>>
619 13:59:55.017431 [ANA_INIT] PLL <<<<<<<<
620 13:59:55.020469 [ANA_INIT] MIDPI >>>>>>>>
621 13:59:55.023709 [ANA_INIT] MIDPI <<<<<<<<
622 13:59:55.026931 [ANA_INIT] DLL >>>>>>>>
623 13:59:55.027056 [ANA_INIT] flow end
624 13:59:55.030343 ============ LP4 DIFF to SE enter ============
625 13:59:55.036960 ============ LP4 DIFF to SE exit ============
626 13:59:55.037042 [ANA_INIT] <<<<<<<<<<<<<
627 13:59:55.040426 [Flow] Enable top DCM control >>>>>
628 13:59:55.043911 [Flow] Enable top DCM control <<<<<
629 13:59:55.046810 Enable DLL master slave shuffle
630 13:59:55.053926 ==============================================================
631 13:59:55.054003 Gating Mode config
632 13:59:55.060370 ==============================================================
633 13:59:55.064067 Config description:
634 13:59:55.070711 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 13:59:55.077175 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 13:59:55.083932 SELPH_MODE 0: By rank 1: By Phase
637 13:59:55.090800 ==============================================================
638 13:59:55.090918 GAT_TRACK_EN = 1
639 13:59:55.093689 RX_GATING_MODE = 2
640 13:59:55.097055 RX_GATING_TRACK_MODE = 2
641 13:59:55.100430 SELPH_MODE = 1
642 13:59:55.104118 PICG_EARLY_EN = 1
643 13:59:55.107278 VALID_LAT_VALUE = 1
644 13:59:55.114252 ==============================================================
645 13:59:55.117482 Enter into Gating configuration >>>>
646 13:59:55.120647 Exit from Gating configuration <<<<
647 13:59:55.123743 Enter into DVFS_PRE_config >>>>>
648 13:59:55.133835 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 13:59:55.137248 Exit from DVFS_PRE_config <<<<<
650 13:59:55.140506 Enter into PICG configuration >>>>
651 13:59:55.143697 Exit from PICG configuration <<<<
652 13:59:55.143782 [RX_INPUT] configuration >>>>>
653 13:59:55.147071 [RX_INPUT] configuration <<<<<
654 13:59:55.154165 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 13:59:55.157433 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 13:59:55.163891 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 13:59:55.170911 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 13:59:55.177566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 13:59:55.184256 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 13:59:55.187370 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 13:59:55.190827 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 13:59:55.197199 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 13:59:55.200926 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 13:59:55.204247 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 13:59:55.207422 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 13:59:55.211449 ===================================
667 13:59:55.214387 LPDDR4 DRAM CONFIGURATION
668 13:59:55.217654 ===================================
669 13:59:55.220893 EX_ROW_EN[0] = 0x0
670 13:59:55.220979 EX_ROW_EN[1] = 0x0
671 13:59:55.224059 LP4Y_EN = 0x0
672 13:59:55.224138 WORK_FSP = 0x0
673 13:59:55.227414 WL = 0x2
674 13:59:55.227493 RL = 0x2
675 13:59:55.230574 BL = 0x2
676 13:59:55.230677 RPST = 0x0
677 13:59:55.233967 RD_PRE = 0x0
678 13:59:55.234049 WR_PRE = 0x1
679 13:59:55.237599 WR_PST = 0x0
680 13:59:55.237697 DBI_WR = 0x0
681 13:59:55.240598 DBI_RD = 0x0
682 13:59:55.240686 OTF = 0x1
683 13:59:55.244348 ===================================
684 13:59:55.250957 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 13:59:55.254204 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 13:59:55.257356 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 13:59:55.260756 ===================================
688 13:59:55.264323 LPDDR4 DRAM CONFIGURATION
689 13:59:55.267474 ===================================
690 13:59:55.267561 EX_ROW_EN[0] = 0x10
691 13:59:55.271279 EX_ROW_EN[1] = 0x0
692 13:59:55.274313 LP4Y_EN = 0x0
693 13:59:55.274393 WORK_FSP = 0x0
694 13:59:55.278000 WL = 0x2
695 13:59:55.278099 RL = 0x2
696 13:59:55.281199 BL = 0x2
697 13:59:55.281288 RPST = 0x0
698 13:59:55.284296 RD_PRE = 0x0
699 13:59:55.284384 WR_PRE = 0x1
700 13:59:55.287581 WR_PST = 0x0
701 13:59:55.287706 DBI_WR = 0x0
702 13:59:55.291211 DBI_RD = 0x0
703 13:59:55.291299 OTF = 0x1
704 13:59:55.294169 ===================================
705 13:59:55.301278 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 13:59:55.304960 nWR fixed to 40
707 13:59:55.308483 [ModeRegInit_LP4] CH0 RK0
708 13:59:55.308565 [ModeRegInit_LP4] CH0 RK1
709 13:59:55.311489 [ModeRegInit_LP4] CH1 RK0
710 13:59:55.315080 [ModeRegInit_LP4] CH1 RK1
711 13:59:55.315156 match AC timing 13
712 13:59:55.321708 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 13:59:55.324769 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 13:59:55.328216 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 13:59:55.335076 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 13:59:55.338636 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 13:59:55.338713 [EMI DOE] emi_dcm 0
718 13:59:55.345047 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 13:59:55.345129 ==
720 13:59:55.348589 Dram Type= 6, Freq= 0, CH_0, rank 0
721 13:59:55.351957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 13:59:55.352036 ==
723 13:59:55.358672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 13:59:55.361774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 13:59:55.372398 [CA 0] Center 36 (6~67) winsize 62
726 13:59:55.375445 [CA 1] Center 36 (6~67) winsize 62
727 13:59:55.379043 [CA 2] Center 34 (4~65) winsize 62
728 13:59:55.382687 [CA 3] Center 34 (4~64) winsize 61
729 13:59:55.385515 [CA 4] Center 33 (2~64) winsize 63
730 13:59:55.389272 [CA 5] Center 32 (3~62) winsize 60
731 13:59:55.389350
732 13:59:55.392424 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 13:59:55.392507
734 13:59:55.395895 [CATrainingPosCal] consider 1 rank data
735 13:59:55.399426 u2DelayCellTimex100 = 270/100 ps
736 13:59:55.402431 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
737 13:59:55.405820 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
738 13:59:55.409544 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
739 13:59:55.415734 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
740 13:59:55.419325 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
741 13:59:55.422463 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
742 13:59:55.422547
743 13:59:55.425891 CA PerBit enable=1, Macro0, CA PI delay=32
744 13:59:55.425970
745 13:59:55.428939 [CBTSetCACLKResult] CA Dly = 32
746 13:59:55.429017 CS Dly: 4 (0~35)
747 13:59:55.429083 ==
748 13:59:55.432375 Dram Type= 6, Freq= 0, CH_0, rank 1
749 13:59:55.438957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 13:59:55.439078 ==
751 13:59:55.442706 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 13:59:55.448970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 13:59:55.458461 [CA 0] Center 36 (6~67) winsize 62
754 13:59:55.461717 [CA 1] Center 36 (6~67) winsize 62
755 13:59:55.465166 [CA 2] Center 34 (3~65) winsize 63
756 13:59:55.468416 [CA 3] Center 33 (3~64) winsize 62
757 13:59:55.472209 [CA 4] Center 32 (2~63) winsize 62
758 13:59:55.475414 [CA 5] Center 32 (2~63) winsize 62
759 13:59:55.475494
760 13:59:55.478604 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 13:59:55.478716
762 13:59:55.481969 [CATrainingPosCal] consider 2 rank data
763 13:59:55.485382 u2DelayCellTimex100 = 270/100 ps
764 13:59:55.488593 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
765 13:59:55.491889 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
766 13:59:55.498846 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
767 13:59:55.502004 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
768 13:59:55.505149 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
769 13:59:55.508963 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
770 13:59:55.509044
771 13:59:55.511932 CA PerBit enable=1, Macro0, CA PI delay=32
772 13:59:55.512036
773 13:59:55.515469 [CBTSetCACLKResult] CA Dly = 32
774 13:59:55.515587 CS Dly: 4 (0~36)
775 13:59:55.515685
776 13:59:55.519145 ----->DramcWriteLeveling(PI) begin...
777 13:59:55.522616 ==
778 13:59:55.522695 Dram Type= 6, Freq= 0, CH_0, rank 0
779 13:59:55.529393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 13:59:55.529478 ==
781 13:59:55.532843 Write leveling (Byte 0): 31 => 31
782 13:59:55.532950 Write leveling (Byte 1): 30 => 30
783 13:59:55.536416 DramcWriteLeveling(PI) end<-----
784 13:59:55.536516
785 13:59:55.536612 ==
786 13:59:55.540596 Dram Type= 6, Freq= 0, CH_0, rank 0
787 13:59:55.543678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 13:59:55.543806 ==
789 13:59:55.547258 [Gating] SW mode calibration
790 13:59:55.554330 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 13:59:55.561366 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 13:59:55.564623 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 13:59:55.568128 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 13:59:55.574700 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 13:59:55.577691 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:59:55.581440 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:59:55.587783 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:59:55.591208 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:59:55.594436 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:59:55.601498 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:59:55.604561 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:59:55.607870 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:59:55.611218 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:59:55.618189 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:59:55.621478 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:59:55.624710 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:59:55.631555 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:59:55.634499 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:59:55.638054 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:59:55.644781 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:59:55.648281 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:59:55.651446 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 13:59:55.658195 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 13:59:55.661269 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 13:59:55.664632 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 13:59:55.671874 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 13:59:55.674708 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 13:59:55.678142 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
819 13:59:55.681533 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
820 13:59:55.688192 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 13:59:55.691695 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 13:59:55.695283 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 13:59:55.702113 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 13:59:55.705640 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 13:59:55.708460 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
826 13:59:55.715158 0 10 8 | B1->B0 | 3232 2525 | 1 0 | (1 0) (1 0)
827 13:59:55.718354 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
828 13:59:55.721494 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 13:59:55.728589 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 13:59:55.731713 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 13:59:55.735532 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 13:59:55.742380 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 13:59:55.745477 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
834 13:59:55.748392 0 11 8 | B1->B0 | 2d2d 3b3a | 1 1 | (0 0) (0 0)
835 13:59:55.751896 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
836 13:59:55.758562 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 13:59:55.762312 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 13:59:55.765713 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 13:59:55.772227 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 13:59:55.775791 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 13:59:55.778527 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 13:59:55.785506 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
843 13:59:55.788712 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
844 13:59:55.792318 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:59:55.798949 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:59:55.802715 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:59:55.805501 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:59:55.809213 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:59:55.816086 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:59:55.818783 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:59:55.822173 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:59:55.828952 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 13:59:55.832486 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 13:59:55.835459 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 13:59:55.842571 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 13:59:55.845725 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 13:59:55.849286 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 13:59:55.855473 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 13:59:55.855583 Total UI for P1: 0, mck2ui 16
860 13:59:55.862686 best dqsien dly found for B0: ( 0, 14, 4)
861 13:59:55.865641 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 13:59:55.869275 Total UI for P1: 0, mck2ui 16
863 13:59:55.872288 best dqsien dly found for B1: ( 0, 14, 8)
864 13:59:55.876581 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
865 13:59:55.879755 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 13:59:55.879840
867 13:59:55.883388 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
868 13:59:55.886459 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 13:59:55.889955 [Gating] SW calibration Done
870 13:59:55.890041 ==
871 13:59:55.893375 Dram Type= 6, Freq= 0, CH_0, rank 0
872 13:59:55.896829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 13:59:55.896963 ==
874 13:59:55.900172 RX Vref Scan: 0
875 13:59:55.900301
876 13:59:55.900417 RX Vref 0 -> 0, step: 1
877 13:59:55.900532
878 13:59:55.903134 RX Delay -130 -> 252, step: 16
879 13:59:55.906604 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
880 13:59:55.913198 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
881 13:59:55.916840 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
882 13:59:55.919847 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
883 13:59:55.923452 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 13:59:55.926863 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
885 13:59:55.933215 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
886 13:59:55.936844 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
887 13:59:55.939911 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
888 13:59:55.943329 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
889 13:59:55.946888 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
890 13:59:55.953250 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
891 13:59:55.956715 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
892 13:59:55.960072 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
893 13:59:55.963344 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
894 13:59:55.966672 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
895 13:59:55.966758 ==
896 13:59:55.970356 Dram Type= 6, Freq= 0, CH_0, rank 0
897 13:59:55.976770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 13:59:55.976856 ==
899 13:59:55.976924 DQS Delay:
900 13:59:55.980198 DQS0 = 0, DQS1 = 0
901 13:59:55.980283 DQM Delay:
902 13:59:55.980351 DQM0 = 93, DQM1 = 85
903 13:59:55.983283 DQ Delay:
904 13:59:55.986950 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
905 13:59:55.990038 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
906 13:59:55.993595 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
907 13:59:55.996880 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
908 13:59:55.996965
909 13:59:55.997032
910 13:59:55.997094 ==
911 13:59:56.000292 Dram Type= 6, Freq= 0, CH_0, rank 0
912 13:59:56.004017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 13:59:56.004108 ==
914 13:59:56.004175
915 13:59:56.004237
916 13:59:56.006744 TX Vref Scan disable
917 13:59:56.010423 == TX Byte 0 ==
918 13:59:56.014112 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
919 13:59:56.016874 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
920 13:59:56.016960 == TX Byte 1 ==
921 13:59:56.023336 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
922 13:59:56.027066 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
923 13:59:56.027151 ==
924 13:59:56.030380 Dram Type= 6, Freq= 0, CH_0, rank 0
925 13:59:56.033827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 13:59:56.033913 ==
927 13:59:56.047987 TX Vref=22, minBit 4, minWin=27, winSum=447
928 13:59:56.051439 TX Vref=24, minBit 8, minWin=27, winSum=450
929 13:59:56.054326 TX Vref=26, minBit 9, minWin=27, winSum=454
930 13:59:56.057850 TX Vref=28, minBit 0, minWin=28, winSum=455
931 13:59:56.061433 TX Vref=30, minBit 3, minWin=28, winSum=458
932 13:59:56.064410 TX Vref=32, minBit 6, minWin=28, winSum=457
933 13:59:56.071228 [TxChooseVref] Worse bit 3, Min win 28, Win sum 458, Final Vref 30
934 13:59:56.071320
935 13:59:56.074729 Final TX Range 1 Vref 30
936 13:59:56.074815
937 13:59:56.074882 ==
938 13:59:56.078195 Dram Type= 6, Freq= 0, CH_0, rank 0
939 13:59:56.081567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 13:59:56.081653 ==
941 13:59:56.081724
942 13:59:56.081786
943 13:59:56.084783 TX Vref Scan disable
944 13:59:56.087789 == TX Byte 0 ==
945 13:59:56.091559 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
946 13:59:56.094404 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
947 13:59:56.098101 == TX Byte 1 ==
948 13:59:56.101434 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
949 13:59:56.104865 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
950 13:59:56.104950
951 13:59:56.108441 [DATLAT]
952 13:59:56.108525 Freq=800, CH0 RK0
953 13:59:56.108592
954 13:59:56.111384 DATLAT Default: 0xa
955 13:59:56.111468 0, 0xFFFF, sum = 0
956 13:59:56.114469 1, 0xFFFF, sum = 0
957 13:59:56.114555 2, 0xFFFF, sum = 0
958 13:59:56.117863 3, 0xFFFF, sum = 0
959 13:59:56.117950 4, 0xFFFF, sum = 0
960 13:59:56.121473 5, 0xFFFF, sum = 0
961 13:59:56.121582 6, 0xFFFF, sum = 0
962 13:59:56.124919 7, 0xFFFF, sum = 0
963 13:59:56.125030 8, 0xFFFF, sum = 0
964 13:59:56.127848 9, 0x0, sum = 1
965 13:59:56.127957 10, 0x0, sum = 2
966 13:59:56.131608 11, 0x0, sum = 3
967 13:59:56.131703 12, 0x0, sum = 4
968 13:59:56.134439 best_step = 10
969 13:59:56.134516
970 13:59:56.134587 ==
971 13:59:56.137935 Dram Type= 6, Freq= 0, CH_0, rank 0
972 13:59:56.141495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 13:59:56.141578 ==
974 13:59:56.141645 RX Vref Scan: 1
975 13:59:56.145269
976 13:59:56.145346 Set Vref Range= 32 -> 127
977 13:59:56.145410
978 13:59:56.148201 RX Vref 32 -> 127, step: 1
979 13:59:56.148278
980 13:59:56.151605 RX Delay -95 -> 252, step: 8
981 13:59:56.151701
982 13:59:56.155016 Set Vref, RX VrefLevel [Byte0]: 32
983 13:59:56.158156 [Byte1]: 32
984 13:59:56.158236
985 13:59:56.161671 Set Vref, RX VrefLevel [Byte0]: 33
986 13:59:56.165431 [Byte1]: 33
987 13:59:56.165536
988 13:59:56.168228 Set Vref, RX VrefLevel [Byte0]: 34
989 13:59:56.172029 [Byte1]: 34
990 13:59:56.175746
991 13:59:56.175829 Set Vref, RX VrefLevel [Byte0]: 35
992 13:59:56.178843 [Byte1]: 35
993 13:59:56.183352
994 13:59:56.183458 Set Vref, RX VrefLevel [Byte0]: 36
995 13:59:56.187056 [Byte1]: 36
996 13:59:56.190742
997 13:59:56.190824 Set Vref, RX VrefLevel [Byte0]: 37
998 13:59:56.194198 [Byte1]: 37
999 13:59:56.198900
1000 13:59:56.198980 Set Vref, RX VrefLevel [Byte0]: 38
1001 13:59:56.202703 [Byte1]: 38
1002 13:59:56.206598
1003 13:59:56.206678 Set Vref, RX VrefLevel [Byte0]: 39
1004 13:59:56.209301 [Byte1]: 39
1005 13:59:56.214244
1006 13:59:56.214349 Set Vref, RX VrefLevel [Byte0]: 40
1007 13:59:56.217582 [Byte1]: 40
1008 13:59:56.221868
1009 13:59:56.221975 Set Vref, RX VrefLevel [Byte0]: 41
1010 13:59:56.224814 [Byte1]: 41
1011 13:59:56.228559
1012 13:59:56.228665 Set Vref, RX VrefLevel [Byte0]: 42
1013 13:59:56.231999 [Byte1]: 42
1014 13:59:56.236174
1015 13:59:56.236249 Set Vref, RX VrefLevel [Byte0]: 43
1016 13:59:56.239693 [Byte1]: 43
1017 13:59:56.243762
1018 13:59:56.243843 Set Vref, RX VrefLevel [Byte0]: 44
1019 13:59:56.247243 [Byte1]: 44
1020 13:59:56.251355
1021 13:59:56.251459 Set Vref, RX VrefLevel [Byte0]: 45
1022 13:59:56.254943 [Byte1]: 45
1023 13:59:56.258960
1024 13:59:56.259062 Set Vref, RX VrefLevel [Byte0]: 46
1025 13:59:56.262342 [Byte1]: 46
1026 13:59:56.266913
1027 13:59:56.266998 Set Vref, RX VrefLevel [Byte0]: 47
1028 13:59:56.270040 [Byte1]: 47
1029 13:59:56.274510
1030 13:59:56.274593 Set Vref, RX VrefLevel [Byte0]: 48
1031 13:59:56.277543 [Byte1]: 48
1032 13:59:56.282022
1033 13:59:56.282106 Set Vref, RX VrefLevel [Byte0]: 49
1034 13:59:56.284961 [Byte1]: 49
1035 13:59:56.289650
1036 13:59:56.289763 Set Vref, RX VrefLevel [Byte0]: 50
1037 13:59:56.292483 [Byte1]: 50
1038 13:59:56.296945
1039 13:59:56.297024 Set Vref, RX VrefLevel [Byte0]: 51
1040 13:59:56.300387 [Byte1]: 51
1041 13:59:56.304593
1042 13:59:56.304676 Set Vref, RX VrefLevel [Byte0]: 52
1043 13:59:56.307918 [Byte1]: 52
1044 13:59:56.312038
1045 13:59:56.312125 Set Vref, RX VrefLevel [Byte0]: 53
1046 13:59:56.315508 [Byte1]: 53
1047 13:59:56.320296
1048 13:59:56.320377 Set Vref, RX VrefLevel [Byte0]: 54
1049 13:59:56.322993 [Byte1]: 54
1050 13:59:56.327817
1051 13:59:56.327900 Set Vref, RX VrefLevel [Byte0]: 55
1052 13:59:56.331118 [Byte1]: 55
1053 13:59:56.335480
1054 13:59:56.335565 Set Vref, RX VrefLevel [Byte0]: 56
1055 13:59:56.338299 [Byte1]: 56
1056 13:59:56.342568
1057 13:59:56.342652 Set Vref, RX VrefLevel [Byte0]: 57
1058 13:59:56.345903 [Byte1]: 57
1059 13:59:56.350402
1060 13:59:56.350488 Set Vref, RX VrefLevel [Byte0]: 58
1061 13:59:56.353356 [Byte1]: 58
1062 13:59:56.358111
1063 13:59:56.358194 Set Vref, RX VrefLevel [Byte0]: 59
1064 13:59:56.361016 [Byte1]: 59
1065 13:59:56.365706
1066 13:59:56.365815 Set Vref, RX VrefLevel [Byte0]: 60
1067 13:59:56.368697 [Byte1]: 60
1068 13:59:56.372884
1069 13:59:56.372967 Set Vref, RX VrefLevel [Byte0]: 61
1070 13:59:56.376470 [Byte1]: 61
1071 13:59:56.380606
1072 13:59:56.380689 Set Vref, RX VrefLevel [Byte0]: 62
1073 13:59:56.384159 [Byte1]: 62
1074 13:59:56.388389
1075 13:59:56.388478 Set Vref, RX VrefLevel [Byte0]: 63
1076 13:59:56.391929 [Byte1]: 63
1077 13:59:56.395910
1078 13:59:56.395986 Set Vref, RX VrefLevel [Byte0]: 64
1079 13:59:56.399247 [Byte1]: 64
1080 13:59:56.403485
1081 13:59:56.403569 Set Vref, RX VrefLevel [Byte0]: 65
1082 13:59:56.407130 [Byte1]: 65
1083 13:59:56.410989
1084 13:59:56.411071 Set Vref, RX VrefLevel [Byte0]: 66
1085 13:59:56.414608 [Byte1]: 66
1086 13:59:56.418708
1087 13:59:56.418791 Set Vref, RX VrefLevel [Byte0]: 67
1088 13:59:56.422046 [Byte1]: 67
1089 13:59:56.426769
1090 13:59:56.426853 Set Vref, RX VrefLevel [Byte0]: 68
1091 13:59:56.429432 [Byte1]: 68
1092 13:59:56.434091
1093 13:59:56.434168 Set Vref, RX VrefLevel [Byte0]: 69
1094 13:59:56.437054 [Byte1]: 69
1095 13:59:56.441323
1096 13:59:56.441430 Set Vref, RX VrefLevel [Byte0]: 70
1097 13:59:56.444685 [Byte1]: 70
1098 13:59:56.449525
1099 13:59:56.449663 Set Vref, RX VrefLevel [Byte0]: 71
1100 13:59:56.452251 [Byte1]: 71
1101 13:59:56.456838
1102 13:59:56.456922 Set Vref, RX VrefLevel [Byte0]: 72
1103 13:59:56.459920 [Byte1]: 72
1104 13:59:56.463970
1105 13:59:56.464053 Set Vref, RX VrefLevel [Byte0]: 73
1106 13:59:56.467836 [Byte1]: 73
1107 13:59:56.471665
1108 13:59:56.471782 Set Vref, RX VrefLevel [Byte0]: 74
1109 13:59:56.475176 [Byte1]: 74
1110 13:59:56.479538
1111 13:59:56.479679 Set Vref, RX VrefLevel [Byte0]: 75
1112 13:59:56.482736 [Byte1]: 75
1113 13:59:56.487239
1114 13:59:56.487364 Set Vref, RX VrefLevel [Byte0]: 76
1115 13:59:56.490116 [Byte1]: 76
1116 13:59:56.494707
1117 13:59:56.494842 Set Vref, RX VrefLevel [Byte0]: 77
1118 13:59:56.498354 [Byte1]: 77
1119 13:59:56.502277
1120 13:59:56.502403 Final RX Vref Byte 0 = 50 to rank0
1121 13:59:56.505962 Final RX Vref Byte 1 = 56 to rank0
1122 13:59:56.509137 Final RX Vref Byte 0 = 50 to rank1
1123 13:59:56.512427 Final RX Vref Byte 1 = 56 to rank1==
1124 13:59:56.515741 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 13:59:56.519172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 13:59:56.522774 ==
1127 13:59:56.522907 DQS Delay:
1128 13:59:56.523032 DQS0 = 0, DQS1 = 0
1129 13:59:56.525696 DQM Delay:
1130 13:59:56.525817 DQM0 = 91, DQM1 = 84
1131 13:59:56.529039 DQ Delay:
1132 13:59:56.529167 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1133 13:59:56.532714 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1134 13:59:56.536081 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1135 13:59:56.539134 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1136 13:59:56.542490
1137 13:59:56.542617
1138 13:59:56.549364 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1139 13:59:56.552302 CH0 RK0: MR19=606, MR18=4F45
1140 13:59:56.559004 CH0_RK0: MR19=0x606, MR18=0x4F45, DQSOSC=390, MR23=63, INC=97, DEC=64
1141 13:59:56.559141
1142 13:59:56.562344 ----->DramcWriteLeveling(PI) begin...
1143 13:59:56.562467 ==
1144 13:59:56.566084 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 13:59:56.569369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 13:59:56.569493 ==
1147 13:59:56.572461 Write leveling (Byte 0): 34 => 34
1148 13:59:56.576197 Write leveling (Byte 1): 28 => 28
1149 13:59:56.579175 DramcWriteLeveling(PI) end<-----
1150 13:59:56.579287
1151 13:59:56.579398 ==
1152 13:59:56.582572 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 13:59:56.585937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 13:59:56.586016 ==
1155 13:59:56.589415 [Gating] SW mode calibration
1156 13:59:56.636343 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 13:59:56.636709 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 13:59:56.636834 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 13:59:56.636949 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1160 13:59:56.637060 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1161 13:59:56.637189 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:59:56.637303 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:59:56.637427 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:59:56.637538 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:59:56.637651 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:59:56.680879 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:59:56.681209 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:59:56.681352 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:59:56.681460 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:59:56.681569 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:59:56.681699 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:59:56.681811 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:59:56.681915 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:59:56.682023 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:59:56.682150 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1176 13:59:56.704179 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1177 13:59:56.704496 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:59:56.704633 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:59:56.704747 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:59:56.705053 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:59:56.707814 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:59:56.711157 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:59:56.714727 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:59:56.721519 0 9 8 | B1->B0 | 2e2e 3130 | 1 1 | (1 1) (1 1)
1185 13:59:56.724912 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 13:59:56.727816 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 13:59:56.735000 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 13:59:56.738114 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 13:59:56.741301 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 13:59:56.744596 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 13:59:56.751515 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1192 13:59:56.754503 0 10 8 | B1->B0 | 2525 2929 | 0 0 | (1 0) (0 0)
1193 13:59:56.758059 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 13:59:56.764509 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 13:59:56.768739 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 13:59:56.772728 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 13:59:56.776284 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 13:59:56.780079 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 13:59:56.787396 0 11 4 | B1->B0 | 2a2a 2626 | 1 0 | (0 0) (0 0)
1200 13:59:56.790475 0 11 8 | B1->B0 | 3c3c 3e3e | 1 0 | (0 0) (0 0)
1201 13:59:56.794227 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 13:59:56.800920 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 13:59:56.804160 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 13:59:56.807571 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 13:59:56.810690 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 13:59:56.817750 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 13:59:56.820922 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 13:59:56.824502 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1209 13:59:56.831010 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:59:56.834964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:59:56.837920 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:59:56.844439 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:59:56.847775 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:59:56.851643 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:59:56.854877 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 13:59:56.861201 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 13:59:56.864614 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 13:59:56.868292 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 13:59:56.874599 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 13:59:56.877856 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 13:59:56.881448 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 13:59:56.887907 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 13:59:56.891531 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 13:59:56.894466 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1225 13:59:56.901574 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 13:59:56.901697 Total UI for P1: 0, mck2ui 16
1227 13:59:56.908055 best dqsien dly found for B0: ( 0, 14, 8)
1228 13:59:56.908180 Total UI for P1: 0, mck2ui 16
1229 13:59:56.911658 best dqsien dly found for B1: ( 0, 14, 8)
1230 13:59:56.918427 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1231 13:59:56.921571 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1232 13:59:56.921692
1233 13:59:56.925097 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1234 13:59:56.927868 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1235 13:59:56.931322 [Gating] SW calibration Done
1236 13:59:56.931443 ==
1237 13:59:56.934546 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 13:59:56.937907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 13:59:56.938013 ==
1240 13:59:56.938107 RX Vref Scan: 0
1241 13:59:56.941632
1242 13:59:56.941714 RX Vref 0 -> 0, step: 1
1243 13:59:56.941779
1244 13:59:56.945015 RX Delay -130 -> 252, step: 16
1245 13:59:56.948145 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1246 13:59:56.951617 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1247 13:59:56.958430 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1248 13:59:56.961331 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1249 13:59:56.964965 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1250 13:59:56.968302 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1251 13:59:56.971534 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1252 13:59:56.975058 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
1253 13:59:56.982032 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1254 13:59:56.985838 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1255 13:59:56.988503 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1256 13:59:56.991976 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1257 13:59:56.995527 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1258 13:59:57.002043 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1259 13:59:57.005854 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1260 13:59:57.008747 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1261 13:59:57.008848 ==
1262 13:59:57.011927 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 13:59:57.015606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 13:59:57.018761 ==
1265 13:59:57.018839 DQS Delay:
1266 13:59:57.018909 DQS0 = 0, DQS1 = 0
1267 13:59:57.022075 DQM Delay:
1268 13:59:57.022155 DQM0 = 90, DQM1 = 81
1269 13:59:57.025083 DQ Delay:
1270 13:59:57.025164 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1271 13:59:57.028969 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1272 13:59:57.031887 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1273 13:59:57.035286 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1274 13:59:57.035399
1275 13:59:57.038722
1276 13:59:57.038824 ==
1277 13:59:57.042501 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 13:59:57.045791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 13:59:57.045871 ==
1280 13:59:57.045943
1281 13:59:57.046002
1282 13:59:57.048944 TX Vref Scan disable
1283 13:59:57.049029 == TX Byte 0 ==
1284 13:59:57.055461 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1285 13:59:57.058992 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1286 13:59:57.059094 == TX Byte 1 ==
1287 13:59:57.065672 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1288 13:59:57.068502 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1289 13:59:57.068620 ==
1290 13:59:57.072255 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 13:59:57.075820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 13:59:57.075903 ==
1293 13:59:57.089652 TX Vref=22, minBit 8, minWin=27, winSum=449
1294 13:59:57.093057 TX Vref=24, minBit 1, minWin=28, winSum=455
1295 13:59:57.096106 TX Vref=26, minBit 1, minWin=28, winSum=454
1296 13:59:57.100027 TX Vref=28, minBit 1, minWin=28, winSum=457
1297 13:59:57.102873 TX Vref=30, minBit 2, minWin=28, winSum=457
1298 13:59:57.106381 TX Vref=32, minBit 8, minWin=27, winSum=453
1299 13:59:57.113130 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 28
1300 13:59:57.113246
1301 13:59:57.116640 Final TX Range 1 Vref 28
1302 13:59:57.116723
1303 13:59:57.116788 ==
1304 13:59:57.119985 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 13:59:57.123251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 13:59:57.123360 ==
1307 13:59:57.123454
1308 13:59:57.126330
1309 13:59:57.126445 TX Vref Scan disable
1310 13:59:57.129780 == TX Byte 0 ==
1311 13:59:57.132637 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1312 13:59:57.136454 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1313 13:59:57.139408 == TX Byte 1 ==
1314 13:59:57.142812 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1315 13:59:57.146415 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1316 13:59:57.146507
1317 13:59:57.149902 [DATLAT]
1318 13:59:57.150005 Freq=800, CH0 RK1
1319 13:59:57.150071
1320 13:59:57.153333 DATLAT Default: 0xa
1321 13:59:57.153420 0, 0xFFFF, sum = 0
1322 13:59:57.156463 1, 0xFFFF, sum = 0
1323 13:59:57.156559 2, 0xFFFF, sum = 0
1324 13:59:57.159839 3, 0xFFFF, sum = 0
1325 13:59:57.159918 4, 0xFFFF, sum = 0
1326 13:59:57.163539 5, 0xFFFF, sum = 0
1327 13:59:57.163654 6, 0xFFFF, sum = 0
1328 13:59:57.166249 7, 0xFFFF, sum = 0
1329 13:59:57.166350 8, 0xFFFF, sum = 0
1330 13:59:57.169801 9, 0x0, sum = 1
1331 13:59:57.169903 10, 0x0, sum = 2
1332 13:59:57.173124 11, 0x0, sum = 3
1333 13:59:57.173207 12, 0x0, sum = 4
1334 13:59:57.176563 best_step = 10
1335 13:59:57.176636
1336 13:59:57.176698 ==
1337 13:59:57.179821 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 13:59:57.183298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 13:59:57.183400 ==
1340 13:59:57.186562 RX Vref Scan: 0
1341 13:59:57.186670
1342 13:59:57.186773 RX Vref 0 -> 0, step: 1
1343 13:59:57.186864
1344 13:59:57.189868 RX Delay -95 -> 252, step: 8
1345 13:59:57.196953 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1346 13:59:57.199532 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1347 13:59:57.203340 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1348 13:59:57.206624 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1349 13:59:57.209883 iDelay=209, Bit 4, Center 100 (-7 ~ 208) 216
1350 13:59:57.216221 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1351 13:59:57.220099 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1352 13:59:57.223160 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1353 13:59:57.226646 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1354 13:59:57.230314 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1355 13:59:57.233047 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1356 13:59:57.239839 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1357 13:59:57.243369 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1358 13:59:57.246313 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1359 13:59:57.249665 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1360 13:59:57.256710 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1361 13:59:57.256832 ==
1362 13:59:57.259624 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 13:59:57.263446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 13:59:57.263520 ==
1365 13:59:57.263590 DQS Delay:
1366 13:59:57.266948 DQS0 = 0, DQS1 = 0
1367 13:59:57.267047 DQM Delay:
1368 13:59:57.270021 DQM0 = 94, DQM1 = 84
1369 13:59:57.270097 DQ Delay:
1370 13:59:57.273431 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =92
1371 13:59:57.277101 DQ4 =100, DQ5 =84, DQ6 =96, DQ7 =100
1372 13:59:57.279864 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1373 13:59:57.283242 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
1374 13:59:57.283344
1375 13:59:57.283439
1376 13:59:57.290016 [DQSOSCAuto] RK1, (LSB)MR18= 0x4818, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
1377 13:59:57.293457 CH0 RK1: MR19=606, MR18=4818
1378 13:59:57.299670 CH0_RK1: MR19=0x606, MR18=0x4818, DQSOSC=391, MR23=63, INC=96, DEC=64
1379 13:59:57.303309 [RxdqsGatingPostProcess] freq 800
1380 13:59:57.310016 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 13:59:57.310101 Pre-setting of DQS Precalculation
1382 13:59:57.317027 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 13:59:57.317110 ==
1384 13:59:57.320061 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 13:59:57.323559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 13:59:57.323671 ==
1387 13:59:57.330287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 13:59:57.336890 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 13:59:57.344774 [CA 0] Center 36 (6~67) winsize 62
1390 13:59:57.347800 [CA 1] Center 36 (6~67) winsize 62
1391 13:59:57.351118 [CA 2] Center 35 (5~66) winsize 62
1392 13:59:57.354824 [CA 3] Center 34 (4~65) winsize 62
1393 13:59:57.357923 [CA 4] Center 35 (5~65) winsize 61
1394 13:59:57.361553 [CA 5] Center 34 (4~64) winsize 61
1395 13:59:57.361640
1396 13:59:57.364316 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1397 13:59:57.364412
1398 13:59:57.367902 [CATrainingPosCal] consider 1 rank data
1399 13:59:57.371184 u2DelayCellTimex100 = 270/100 ps
1400 13:59:57.374755 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1401 13:59:57.377690 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1402 13:59:57.384574 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1403 13:59:57.387599 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1404 13:59:57.391297 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1405 13:59:57.394225 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1406 13:59:57.394308
1407 13:59:57.397826 CA PerBit enable=1, Macro0, CA PI delay=34
1408 13:59:57.397933
1409 13:59:57.400756 [CBTSetCACLKResult] CA Dly = 34
1410 13:59:57.400841 CS Dly: 6 (0~37)
1411 13:59:57.404137 ==
1412 13:59:57.404238 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 13:59:57.411370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 13:59:57.411473 ==
1415 13:59:57.414459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 13:59:57.420895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 13:59:57.430958 [CA 0] Center 36 (6~67) winsize 62
1418 13:59:57.434338 [CA 1] Center 36 (6~67) winsize 62
1419 13:59:57.438615 [CA 2] Center 35 (4~66) winsize 63
1420 13:59:57.442263 [CA 3] Center 34 (4~65) winsize 62
1421 13:59:57.445408 [CA 4] Center 35 (5~66) winsize 62
1422 13:59:57.449259 [CA 5] Center 34 (4~65) winsize 62
1423 13:59:57.449338
1424 13:59:57.452508 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1425 13:59:57.452585
1426 13:59:57.456584 [CATrainingPosCal] consider 2 rank data
1427 13:59:57.456668 u2DelayCellTimex100 = 270/100 ps
1428 13:59:57.460699 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 13:59:57.464488 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 13:59:57.467607 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1431 13:59:57.474518 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 13:59:57.477890 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1433 13:59:57.480841 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1434 13:59:57.480921
1435 13:59:57.484589 CA PerBit enable=1, Macro0, CA PI delay=34
1436 13:59:57.484665
1437 13:59:57.487996 [CBTSetCACLKResult] CA Dly = 34
1438 13:59:57.488114 CS Dly: 6 (0~38)
1439 13:59:57.488212
1440 13:59:57.491489 ----->DramcWriteLeveling(PI) begin...
1441 13:59:57.491568 ==
1442 13:59:57.494373 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 13:59:57.501158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 13:59:57.501264 ==
1445 13:59:57.504478 Write leveling (Byte 0): 25 => 25
1446 13:59:57.504572 Write leveling (Byte 1): 26 => 26
1447 13:59:57.507830 DramcWriteLeveling(PI) end<-----
1448 13:59:57.507926
1449 13:59:57.511248 ==
1450 13:59:57.511359 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 13:59:57.517917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 13:59:57.517999 ==
1453 13:59:57.521341 [Gating] SW mode calibration
1454 13:59:57.527906 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 13:59:57.531436 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 13:59:57.538240 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1457 13:59:57.541210 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1458 13:59:57.544668 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1459 13:59:57.551109 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:59:57.554678 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:59:57.558378 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:59:57.561183 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:59:57.568116 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:59:57.571029 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:59:57.574762 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:59:57.581244 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:59:57.584446 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:59:57.588038 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:59:57.595024 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:59:57.597730 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:59:57.601612 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:59:57.608057 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1473 13:59:57.611229 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1474 13:59:57.614477 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:59:57.621571 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:59:57.624725 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:59:57.628159 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:59:57.634772 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 13:59:57.638501 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 13:59:57.641531 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:59:57.644586 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1482 13:59:57.651283 0 9 8 | B1->B0 | 3131 3333 | 0 1 | (0 0) (1 1)
1483 13:59:57.654589 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 13:59:57.658190 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 13:59:57.664807 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 13:59:57.668214 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 13:59:57.672136 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 13:59:57.678247 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1489 13:59:57.681565 0 10 4 | B1->B0 | 3131 2b2b | 1 1 | (1 0) (1 1)
1490 13:59:57.684769 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1491 13:59:57.691761 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:59:57.694952 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 13:59:57.698421 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 13:59:57.705755 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 13:59:57.708406 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 13:59:57.712018 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 13:59:57.715088 0 11 4 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 0)
1498 13:59:57.721840 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1499 13:59:57.725548 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 13:59:57.728592 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 13:59:57.735303 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 13:59:57.738726 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 13:59:57.741744 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 13:59:57.748675 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 13:59:57.752201 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1506 13:59:57.755127 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1507 13:59:57.762157 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:59:57.765872 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:59:57.768704 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:59:57.775416 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:59:57.778887 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:59:57.782004 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:59:57.788399 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:59:57.792036 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 13:59:57.795597 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 13:59:57.798505 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 13:59:57.805558 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 13:59:57.808604 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 13:59:57.811982 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 13:59:57.818412 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 13:59:57.821949 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1522 13:59:57.825161 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1523 13:59:57.828542 Total UI for P1: 0, mck2ui 16
1524 13:59:57.831997 best dqsien dly found for B0: ( 0, 14, 4)
1525 13:59:57.838385 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 13:59:57.838474 Total UI for P1: 0, mck2ui 16
1527 13:59:57.845320 best dqsien dly found for B1: ( 0, 14, 6)
1528 13:59:57.848757 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1529 13:59:57.851734 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1530 13:59:57.851814
1531 13:59:57.855256 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1532 13:59:57.859043 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1533 13:59:57.861853 [Gating] SW calibration Done
1534 13:59:57.861938 ==
1535 13:59:57.865201 Dram Type= 6, Freq= 0, CH_1, rank 0
1536 13:59:57.868606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1537 13:59:57.868748 ==
1538 13:59:57.872122 RX Vref Scan: 0
1539 13:59:57.872246
1540 13:59:57.872380 RX Vref 0 -> 0, step: 1
1541 13:59:57.872489
1542 13:59:57.875308 RX Delay -130 -> 252, step: 16
1543 13:59:57.878770 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1544 13:59:57.885190 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1545 13:59:57.888854 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1546 13:59:57.892151 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1547 13:59:57.895592 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1548 13:59:57.898726 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1549 13:59:57.902074 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1550 13:59:57.908854 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1551 13:59:57.912029 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1552 13:59:57.915484 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1553 13:59:57.918868 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1554 13:59:57.922192 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1555 13:59:57.928967 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1556 13:59:57.932475 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1557 13:59:57.935454 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1558 13:59:57.939140 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1559 13:59:57.939252 ==
1560 13:59:57.942293 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 13:59:57.948940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1562 13:59:57.949067 ==
1563 13:59:57.949184 DQS Delay:
1564 13:59:57.949288 DQS0 = 0, DQS1 = 0
1565 13:59:57.952507 DQM Delay:
1566 13:59:57.952630 DQM0 = 92, DQM1 = 87
1567 13:59:57.955364 DQ Delay:
1568 13:59:57.959033 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1569 13:59:57.962135 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1570 13:59:57.965731 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1571 13:59:57.968985 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1572 13:59:57.969109
1573 13:59:57.969224
1574 13:59:57.969338 ==
1575 13:59:57.972377 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 13:59:57.975340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 13:59:57.975465 ==
1578 13:59:57.975573
1579 13:59:57.975689
1580 13:59:57.979113 TX Vref Scan disable
1581 13:59:57.979235 == TX Byte 0 ==
1582 13:59:57.985517 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1583 13:59:57.988779 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1584 13:59:57.988903 == TX Byte 1 ==
1585 13:59:57.995657 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1586 13:59:57.999305 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1587 13:59:57.999409 ==
1588 13:59:58.002646 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 13:59:58.005702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 13:59:58.005812 ==
1591 13:59:58.019579 TX Vref=22, minBit 0, minWin=26, winSum=438
1592 13:59:58.023030 TX Vref=24, minBit 0, minWin=26, winSum=438
1593 13:59:58.026012 TX Vref=26, minBit 5, minWin=26, winSum=443
1594 13:59:58.029438 TX Vref=28, minBit 2, minWin=27, winSum=449
1595 13:59:58.033109 TX Vref=30, minBit 1, minWin=27, winSum=446
1596 13:59:58.036125 TX Vref=32, minBit 1, minWin=27, winSum=448
1597 13:59:58.043138 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 28
1598 13:59:58.043253
1599 13:59:58.046520 Final TX Range 1 Vref 28
1600 13:59:58.046632
1601 13:59:58.046718 ==
1602 13:59:58.049552 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 13:59:58.053362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 13:59:58.053448 ==
1605 13:59:58.053534
1606 13:59:58.053634
1607 13:59:58.056491 TX Vref Scan disable
1608 13:59:58.059657 == TX Byte 0 ==
1609 13:59:58.062994 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1610 13:59:58.066509 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1611 13:59:58.069734 == TX Byte 1 ==
1612 13:59:58.073333 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1613 13:59:58.076438 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1614 13:59:58.076525
1615 13:59:58.079921 [DATLAT]
1616 13:59:58.080006 Freq=800, CH1 RK0
1617 13:59:58.080094
1618 13:59:58.083285 DATLAT Default: 0xa
1619 13:59:58.083424 0, 0xFFFF, sum = 0
1620 13:59:58.086300 1, 0xFFFF, sum = 0
1621 13:59:58.086425 2, 0xFFFF, sum = 0
1622 13:59:58.089947 3, 0xFFFF, sum = 0
1623 13:59:58.090079 4, 0xFFFF, sum = 0
1624 13:59:58.092930 5, 0xFFFF, sum = 0
1625 13:59:58.093067 6, 0xFFFF, sum = 0
1626 13:59:58.096364 7, 0xFFFF, sum = 0
1627 13:59:58.096503 8, 0xFFFF, sum = 0
1628 13:59:58.099476 9, 0x0, sum = 1
1629 13:59:58.099604 10, 0x0, sum = 2
1630 13:59:58.103330 11, 0x0, sum = 3
1631 13:59:58.103467 12, 0x0, sum = 4
1632 13:59:58.106601 best_step = 10
1633 13:59:58.106732
1634 13:59:58.106836 ==
1635 13:59:58.109649 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 13:59:58.113331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 13:59:58.113467 ==
1638 13:59:58.113586 RX Vref Scan: 1
1639 13:59:58.116481
1640 13:59:58.116611 Set Vref Range= 32 -> 127
1641 13:59:58.116728
1642 13:59:58.119964 RX Vref 32 -> 127, step: 1
1643 13:59:58.120097
1644 13:59:58.123012 RX Delay -79 -> 252, step: 8
1645 13:59:58.123133
1646 13:59:58.126598 Set Vref, RX VrefLevel [Byte0]: 32
1647 13:59:58.129743 [Byte1]: 32
1648 13:59:58.129874
1649 13:59:58.133056 Set Vref, RX VrefLevel [Byte0]: 33
1650 13:59:58.136454 [Byte1]: 33
1651 13:59:58.136583
1652 13:59:58.139996 Set Vref, RX VrefLevel [Byte0]: 34
1653 13:59:58.143320 [Byte1]: 34
1654 13:59:58.146884
1655 13:59:58.146971 Set Vref, RX VrefLevel [Byte0]: 35
1656 13:59:58.150502 [Byte1]: 35
1657 13:59:58.154458
1658 13:59:58.154545 Set Vref, RX VrefLevel [Byte0]: 36
1659 13:59:58.157816 [Byte1]: 36
1660 13:59:58.161740
1661 13:59:58.161827 Set Vref, RX VrefLevel [Byte0]: 37
1662 13:59:58.165436 [Byte1]: 37
1663 13:59:58.169634
1664 13:59:58.169720 Set Vref, RX VrefLevel [Byte0]: 38
1665 13:59:58.172853 [Byte1]: 38
1666 13:59:58.177052
1667 13:59:58.177139 Set Vref, RX VrefLevel [Byte0]: 39
1668 13:59:58.180247 [Byte1]: 39
1669 13:59:58.184549
1670 13:59:58.184629 Set Vref, RX VrefLevel [Byte0]: 40
1671 13:59:58.188070 [Byte1]: 40
1672 13:59:58.192451
1673 13:59:58.192537 Set Vref, RX VrefLevel [Byte0]: 41
1674 13:59:58.195810 [Byte1]: 41
1675 13:59:58.199590
1676 13:59:58.199692 Set Vref, RX VrefLevel [Byte0]: 42
1677 13:59:58.203254 [Byte1]: 42
1678 13:59:58.207483
1679 13:59:58.207589 Set Vref, RX VrefLevel [Byte0]: 43
1680 13:59:58.210678 [Byte1]: 43
1681 13:59:58.214926
1682 13:59:58.215003 Set Vref, RX VrefLevel [Byte0]: 44
1683 13:59:58.218513 [Byte1]: 44
1684 13:59:58.222740
1685 13:59:58.222825 Set Vref, RX VrefLevel [Byte0]: 45
1686 13:59:58.225485 [Byte1]: 45
1687 13:59:58.229727
1688 13:59:58.229811 Set Vref, RX VrefLevel [Byte0]: 46
1689 13:59:58.233165 [Byte1]: 46
1690 13:59:58.237582
1691 13:59:58.237667 Set Vref, RX VrefLevel [Byte0]: 47
1692 13:59:58.240586 [Byte1]: 47
1693 13:59:58.245112
1694 13:59:58.245199 Set Vref, RX VrefLevel [Byte0]: 48
1695 13:59:58.248570 [Byte1]: 48
1696 13:59:58.252229
1697 13:59:58.252314 Set Vref, RX VrefLevel [Byte0]: 49
1698 13:59:58.255959 [Byte1]: 49
1699 13:59:58.259852
1700 13:59:58.259937 Set Vref, RX VrefLevel [Byte0]: 50
1701 13:59:58.263294 [Byte1]: 50
1702 13:59:58.267936
1703 13:59:58.268036 Set Vref, RX VrefLevel [Byte0]: 51
1704 13:59:58.270664 [Byte1]: 51
1705 13:59:58.274962
1706 13:59:58.275048 Set Vref, RX VrefLevel [Byte0]: 52
1707 13:59:58.278710 [Byte1]: 52
1708 13:59:58.282712
1709 13:59:58.282819 Set Vref, RX VrefLevel [Byte0]: 53
1710 13:59:58.286243 [Byte1]: 53
1711 13:59:58.290327
1712 13:59:58.290416 Set Vref, RX VrefLevel [Byte0]: 54
1713 13:59:58.293447 [Byte1]: 54
1714 13:59:58.297882
1715 13:59:58.298008 Set Vref, RX VrefLevel [Byte0]: 55
1716 13:59:58.301242 [Byte1]: 55
1717 13:59:58.305075
1718 13:59:58.305162 Set Vref, RX VrefLevel [Byte0]: 56
1719 13:59:58.308524 [Byte1]: 56
1720 13:59:58.313031
1721 13:59:58.313121 Set Vref, RX VrefLevel [Byte0]: 57
1722 13:59:58.316277 [Byte1]: 57
1723 13:59:58.320458
1724 13:59:58.320582 Set Vref, RX VrefLevel [Byte0]: 58
1725 13:59:58.323612 [Byte1]: 58
1726 13:59:58.328170
1727 13:59:58.328278 Set Vref, RX VrefLevel [Byte0]: 59
1728 13:59:58.331325 [Byte1]: 59
1729 13:59:58.335208
1730 13:59:58.335324 Set Vref, RX VrefLevel [Byte0]: 60
1731 13:59:58.338834 [Byte1]: 60
1732 13:59:58.342815
1733 13:59:58.342904 Set Vref, RX VrefLevel [Byte0]: 61
1734 13:59:58.346600 [Byte1]: 61
1735 13:59:58.350562
1736 13:59:58.350686 Set Vref, RX VrefLevel [Byte0]: 62
1737 13:59:58.353681 [Byte1]: 62
1738 13:59:58.357887
1739 13:59:58.358006 Set Vref, RX VrefLevel [Byte0]: 63
1740 13:59:58.361439 [Byte1]: 63
1741 13:59:58.365936
1742 13:59:58.366055 Set Vref, RX VrefLevel [Byte0]: 64
1743 13:59:58.368996 [Byte1]: 64
1744 13:59:58.373445
1745 13:59:58.373559 Set Vref, RX VrefLevel [Byte0]: 65
1746 13:59:58.376437 [Byte1]: 65
1747 13:59:58.380551
1748 13:59:58.380642 Set Vref, RX VrefLevel [Byte0]: 66
1749 13:59:58.384104 [Byte1]: 66
1750 13:59:58.388087
1751 13:59:58.388194 Set Vref, RX VrefLevel [Byte0]: 67
1752 13:59:58.391563 [Byte1]: 67
1753 13:59:58.395882
1754 13:59:58.395993 Set Vref, RX VrefLevel [Byte0]: 68
1755 13:59:58.399394 [Byte1]: 68
1756 13:59:58.403587
1757 13:59:58.403697 Set Vref, RX VrefLevel [Byte0]: 69
1758 13:59:58.406522 [Byte1]: 69
1759 13:59:58.410806
1760 13:59:58.410916 Set Vref, RX VrefLevel [Byte0]: 70
1761 13:59:58.414410 [Byte1]: 70
1762 13:59:58.418474
1763 13:59:58.418584 Set Vref, RX VrefLevel [Byte0]: 71
1764 13:59:58.421687 [Byte1]: 71
1765 13:59:58.426220
1766 13:59:58.426326 Set Vref, RX VrefLevel [Byte0]: 72
1767 13:59:58.429139 [Byte1]: 72
1768 13:59:58.433555
1769 13:59:58.433670 Final RX Vref Byte 0 = 57 to rank0
1770 13:59:58.437060 Final RX Vref Byte 1 = 58 to rank0
1771 13:59:58.440113 Final RX Vref Byte 0 = 57 to rank1
1772 13:59:58.443425 Final RX Vref Byte 1 = 58 to rank1==
1773 13:59:58.446986 Dram Type= 6, Freq= 0, CH_1, rank 0
1774 13:59:58.453837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1775 13:59:58.453985 ==
1776 13:59:58.454104 DQS Delay:
1777 13:59:58.454218 DQS0 = 0, DQS1 = 0
1778 13:59:58.457004 DQM Delay:
1779 13:59:58.457125 DQM0 = 96, DQM1 = 90
1780 13:59:58.460793 DQ Delay:
1781 13:59:58.463705 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1782 13:59:58.466814 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1783 13:59:58.470427 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1784 13:59:58.473945 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1785 13:59:58.474049
1786 13:59:58.474145
1787 13:59:58.480710 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1788 13:59:58.483592 CH1 RK0: MR19=606, MR18=2D49
1789 13:59:58.490110 CH1_RK0: MR19=0x606, MR18=0x2D49, DQSOSC=391, MR23=63, INC=96, DEC=64
1790 13:59:58.490192
1791 13:59:58.493517 ----->DramcWriteLeveling(PI) begin...
1792 13:59:58.493596 ==
1793 13:59:58.496738 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 13:59:58.500298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 13:59:58.500393 ==
1796 13:59:58.503626 Write leveling (Byte 0): 28 => 28
1797 13:59:58.507192 Write leveling (Byte 1): 28 => 28
1798 13:59:58.510084 DramcWriteLeveling(PI) end<-----
1799 13:59:58.510164
1800 13:59:58.510229 ==
1801 13:59:58.513855 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 13:59:58.516822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 13:59:58.516909 ==
1804 13:59:58.520521 [Gating] SW mode calibration
1805 13:59:58.526862 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1806 13:59:58.556737 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1807 13:59:58.556885 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1808 13:59:58.556990 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1809 13:59:58.557097 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 13:59:58.557194 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 13:59:58.557286 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:59:58.560619 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:59:58.563769 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:59:58.567536 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:59:58.574002 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:59:58.577215 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:59:58.580327 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:59:58.583822 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:59:58.591048 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:59:58.594414 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:59:58.597208 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:59:58.604112 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:59:58.607096 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1824 13:59:58.610678 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:59:58.617464 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:59:58.621079 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:59:58.623917 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:59:58.630896 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:59:58.634466 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:59:58.637388 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:59:58.644592 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:59:58.647563 0 9 4 | B1->B0 | 2727 2323 | 1 0 | (1 1) (0 0)
1833 13:59:58.651041 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1834 13:59:58.654067 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 13:59:58.660809 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 13:59:58.664426 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 13:59:58.667311 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 13:59:58.674386 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 13:59:58.677839 0 10 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1840 13:59:58.681175 0 10 4 | B1->B0 | 2727 2f2f | 0 0 | (1 0) (0 1)
1841 13:59:58.687739 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1842 13:59:58.690702 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:59:58.694178 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 13:59:58.700969 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:59:58.704300 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:59:58.707527 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:59:58.714295 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1848 13:59:58.717671 0 11 4 | B1->B0 | 3838 2f2f | 1 0 | (0 0) (0 0)
1849 13:59:58.721332 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 13:59:58.727860 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 13:59:58.730826 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 13:59:58.734412 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 13:59:58.737768 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 13:59:58.744697 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 13:59:58.747716 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1856 13:59:58.751274 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1857 13:59:58.757658 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1858 13:59:58.761268 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 13:59:58.764486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 13:59:58.771154 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 13:59:58.774095 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:59:58.777832 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:59:58.784265 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:59:58.787843 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:59:58.790852 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:59:58.797925 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:59:58.801141 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:59:58.804332 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:59:58.810912 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:59:58.814594 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:59:58.817649 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1872 13:59:58.824404 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1873 13:59:58.824509 Total UI for P1: 0, mck2ui 16
1874 13:59:58.827831 best dqsien dly found for B1: ( 0, 14, 0)
1875 13:59:58.834653 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 13:59:58.837768 Total UI for P1: 0, mck2ui 16
1877 13:59:58.841355 best dqsien dly found for B0: ( 0, 14, 4)
1878 13:59:58.844440 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1879 13:59:58.847987 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1880 13:59:58.848062
1881 13:59:58.851615 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1882 13:59:58.854613 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1883 13:59:58.858188 [Gating] SW calibration Done
1884 13:59:58.858290 ==
1885 13:59:58.861646 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 13:59:58.864758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 13:59:58.864855 ==
1888 13:59:58.868360 RX Vref Scan: 0
1889 13:59:58.868431
1890 13:59:58.868497 RX Vref 0 -> 0, step: 1
1891 13:59:58.868555
1892 13:59:58.871500 RX Delay -130 -> 252, step: 16
1893 13:59:58.874888 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1894 13:59:58.881377 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1895 13:59:58.884924 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1896 13:59:58.888721 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1897 13:59:58.891449 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1898 13:59:58.894918 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1899 13:59:58.901462 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1900 13:59:58.905402 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1901 13:59:58.908057 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1902 13:59:58.911711 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1903 13:59:58.915181 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1904 13:59:58.918038 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1905 13:59:58.924751 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1906 13:59:58.928200 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1907 13:59:58.931342 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1908 13:59:58.934983 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1909 13:59:58.935113 ==
1910 13:59:58.938353 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 13:59:58.944758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 13:59:58.944883 ==
1913 13:59:58.944991 DQS Delay:
1914 13:59:58.948334 DQS0 = 0, DQS1 = 0
1915 13:59:58.948457 DQM Delay:
1916 13:59:58.948574 DQM0 = 93, DQM1 = 93
1917 13:59:58.951662 DQ Delay:
1918 13:59:58.954939 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1919 13:59:58.958235 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1920 13:59:58.961515 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1921 13:59:58.964928 DQ12 =101, DQ13 =101, DQ14 =93, DQ15 =101
1922 13:59:58.965055
1923 13:59:58.965170
1924 13:59:58.965283 ==
1925 13:59:58.968208 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 13:59:58.971966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 13:59:58.972099 ==
1928 13:59:58.972211
1929 13:59:58.972317
1930 13:59:58.975117 TX Vref Scan disable
1931 13:59:58.978677 == TX Byte 0 ==
1932 13:59:58.981561 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1933 13:59:58.985014 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1934 13:59:58.988962 == TX Byte 1 ==
1935 13:59:58.991777 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1936 13:59:58.995271 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1937 13:59:58.995359 ==
1938 13:59:58.998180 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 13:59:59.001826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 13:59:59.004878 ==
1941 13:59:59.016239 TX Vref=22, minBit 0, minWin=27, winSum=443
1942 13:59:59.019836 TX Vref=24, minBit 0, minWin=27, winSum=445
1943 13:59:59.023196 TX Vref=26, minBit 2, minWin=27, winSum=450
1944 13:59:59.026131 TX Vref=28, minBit 2, minWin=27, winSum=450
1945 13:59:59.029515 TX Vref=30, minBit 2, minWin=27, winSum=452
1946 13:59:59.032920 TX Vref=32, minBit 2, minWin=27, winSum=450
1947 13:59:59.039709 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 30
1948 13:59:59.039793
1949 13:59:59.042797 Final TX Range 1 Vref 30
1950 13:59:59.042900
1951 13:59:59.042997 ==
1952 13:59:59.046368 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 13:59:59.049487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 13:59:59.049595 ==
1955 13:59:59.049697
1956 13:59:59.052906
1957 13:59:59.052998 TX Vref Scan disable
1958 13:59:59.055864 == TX Byte 0 ==
1959 13:59:59.059420 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1960 13:59:59.062931 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1961 13:59:59.066279 == TX Byte 1 ==
1962 13:59:59.069247 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1963 13:59:59.072622 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1964 13:59:59.076179
1965 13:59:59.076257 [DATLAT]
1966 13:59:59.076360 Freq=800, CH1 RK1
1967 13:59:59.076460
1968 13:59:59.079657 DATLAT Default: 0xa
1969 13:59:59.079734 0, 0xFFFF, sum = 0
1970 13:59:59.082844 1, 0xFFFF, sum = 0
1971 13:59:59.082961 2, 0xFFFF, sum = 0
1972 13:59:59.086034 3, 0xFFFF, sum = 0
1973 13:59:59.086140 4, 0xFFFF, sum = 0
1974 13:59:59.089531 5, 0xFFFF, sum = 0
1975 13:59:59.089666 6, 0xFFFF, sum = 0
1976 13:59:59.092903 7, 0xFFFF, sum = 0
1977 13:59:59.096204 8, 0xFFFF, sum = 0
1978 13:59:59.096332 9, 0x0, sum = 1
1979 13:59:59.096452 10, 0x0, sum = 2
1980 13:59:59.099567 11, 0x0, sum = 3
1981 13:59:59.099695 12, 0x0, sum = 4
1982 13:59:59.102907 best_step = 10
1983 13:59:59.102992
1984 13:59:59.103077 ==
1985 13:59:59.106223 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 13:59:59.109550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 13:59:59.109662 ==
1988 13:59:59.113107 RX Vref Scan: 0
1989 13:59:59.113214
1990 13:59:59.113316 RX Vref 0 -> 0, step: 1
1991 13:59:59.113416
1992 13:59:59.116190 RX Delay -63 -> 252, step: 8
1993 13:59:59.122711 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1994 13:59:59.126291 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1995 13:59:59.129839 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1996 13:59:59.132916 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1997 13:59:59.136541 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1998 13:59:59.139562 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1999 13:59:59.146049 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2000 13:59:59.149358 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2001 13:59:59.152835 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2002 13:59:59.156591 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2003 13:59:59.160186 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2004 13:59:59.166534 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2005 13:59:59.169919 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2006 13:59:59.172731 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2007 13:59:59.176254 iDelay=209, Bit 14, Center 100 (1 ~ 200) 200
2008 13:59:59.180017 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2009 13:59:59.180144 ==
2010 13:59:59.182736 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 13:59:59.189727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 13:59:59.189855 ==
2013 13:59:59.189974 DQS Delay:
2014 13:59:59.193128 DQS0 = 0, DQS1 = 0
2015 13:59:59.193257 DQM Delay:
2016 13:59:59.193374 DQM0 = 97, DQM1 = 91
2017 13:59:59.196391 DQ Delay:
2018 13:59:59.199884 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2019 13:59:59.203321 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2020 13:59:59.206642 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =88
2021 13:59:59.209758 DQ12 =100, DQ13 =96, DQ14 =100, DQ15 =96
2022 13:59:59.209885
2023 13:59:59.209999
2024 13:59:59.216448 [DQSOSCAuto] RK1, (LSB)MR18= 0x450f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2025 13:59:59.219505 CH1 RK1: MR19=606, MR18=450F
2026 13:59:59.226612 CH1_RK1: MR19=0x606, MR18=0x450F, DQSOSC=392, MR23=63, INC=96, DEC=64
2027 13:59:59.229505 [RxdqsGatingPostProcess] freq 800
2028 13:59:59.233127 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2029 13:59:59.236695 Pre-setting of DQS Precalculation
2030 13:59:59.243165 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2031 13:59:59.250041 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2032 13:59:59.256888 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2033 13:59:59.256996
2034 13:59:59.257089
2035 13:59:59.259812 [Calibration Summary] 1600 Mbps
2036 13:59:59.259892 CH 0, Rank 0
2037 13:59:59.263145 SW Impedance : PASS
2038 13:59:59.267034 DUTY Scan : NO K
2039 13:59:59.267107 ZQ Calibration : PASS
2040 13:59:59.269869 Jitter Meter : NO K
2041 13:59:59.273422 CBT Training : PASS
2042 13:59:59.273494 Write leveling : PASS
2043 13:59:59.276837 RX DQS gating : PASS
2044 13:59:59.279774 RX DQ/DQS(RDDQC) : PASS
2045 13:59:59.279843 TX DQ/DQS : PASS
2046 13:59:59.283275 RX DATLAT : PASS
2047 13:59:59.283400 RX DQ/DQS(Engine): PASS
2048 13:59:59.286411 TX OE : NO K
2049 13:59:59.286537 All Pass.
2050 13:59:59.286651
2051 13:59:59.289873 CH 0, Rank 1
2052 13:59:59.290000 SW Impedance : PASS
2053 13:59:59.293300 DUTY Scan : NO K
2054 13:59:59.296611 ZQ Calibration : PASS
2055 13:59:59.296733 Jitter Meter : NO K
2056 13:59:59.299749 CBT Training : PASS
2057 13:59:59.303144 Write leveling : PASS
2058 13:59:59.303266 RX DQS gating : PASS
2059 13:59:59.306643 RX DQ/DQS(RDDQC) : PASS
2060 13:59:59.310235 TX DQ/DQS : PASS
2061 13:59:59.310360 RX DATLAT : PASS
2062 13:59:59.313461 RX DQ/DQS(Engine): PASS
2063 13:59:59.316964 TX OE : NO K
2064 13:59:59.317091 All Pass.
2065 13:59:59.317203
2066 13:59:59.317316 CH 1, Rank 0
2067 13:59:59.320505 SW Impedance : PASS
2068 13:59:59.323325 DUTY Scan : NO K
2069 13:59:59.323451 ZQ Calibration : PASS
2070 13:59:59.327147 Jitter Meter : NO K
2071 13:59:59.327270 CBT Training : PASS
2072 13:59:59.329985 Write leveling : PASS
2073 13:59:59.333162 RX DQS gating : PASS
2074 13:59:59.333290 RX DQ/DQS(RDDQC) : PASS
2075 13:59:59.336799 TX DQ/DQS : PASS
2076 13:59:59.339788 RX DATLAT : PASS
2077 13:59:59.339916 RX DQ/DQS(Engine): PASS
2078 13:59:59.343367 TX OE : NO K
2079 13:59:59.343454 All Pass.
2080 13:59:59.343522
2081 13:59:59.346798 CH 1, Rank 1
2082 13:59:59.346872 SW Impedance : PASS
2083 13:59:59.350089 DUTY Scan : NO K
2084 13:59:59.353615 ZQ Calibration : PASS
2085 13:59:59.353693 Jitter Meter : NO K
2086 13:59:59.356429 CBT Training : PASS
2087 13:59:59.360142 Write leveling : PASS
2088 13:59:59.360227 RX DQS gating : PASS
2089 13:59:59.363247 RX DQ/DQS(RDDQC) : PASS
2090 13:59:59.366548 TX DQ/DQS : PASS
2091 13:59:59.366655 RX DATLAT : PASS
2092 13:59:59.370396 RX DQ/DQS(Engine): PASS
2093 13:59:59.370500 TX OE : NO K
2094 13:59:59.373349 All Pass.
2095 13:59:59.373432
2096 13:59:59.373498 DramC Write-DBI off
2097 13:59:59.376707 PER_BANK_REFRESH: Hybrid Mode
2098 13:59:59.380209 TX_TRACKING: ON
2099 13:59:59.383258 [GetDramInforAfterCalByMRR] Vendor 6.
2100 13:59:59.386918 [GetDramInforAfterCalByMRR] Revision 606.
2101 13:59:59.390484 [GetDramInforAfterCalByMRR] Revision 2 0.
2102 13:59:59.390568 MR0 0x3b3b
2103 13:59:59.390634 MR8 0x5151
2104 13:59:59.396975 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 13:59:59.397059
2106 13:59:59.397124 MR0 0x3b3b
2107 13:59:59.397187 MR8 0x5151
2108 13:59:59.400160 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 13:59:59.400269
2110 13:59:59.410405 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2111 13:59:59.413639 [FAST_K] Save calibration result to emmc
2112 13:59:59.417428 [FAST_K] Save calibration result to emmc
2113 13:59:59.420195 dram_init: config_dvfs: 1
2114 13:59:59.423990 dramc_set_vcore_voltage set vcore to 662500
2115 13:59:59.426827 Read voltage for 1200, 2
2116 13:59:59.426935 Vio18 = 0
2117 13:59:59.427034 Vcore = 662500
2118 13:59:59.430509 Vdram = 0
2119 13:59:59.430614 Vddq = 0
2120 13:59:59.430706 Vmddr = 0
2121 13:59:59.437146 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2122 13:59:59.440531 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2123 13:59:59.443846 MEM_TYPE=3, freq_sel=15
2124 13:59:59.446718 sv_algorithm_assistance_LP4_1600
2125 13:59:59.450221 ============ PULL DRAM RESETB DOWN ============
2126 13:59:59.453675 ========== PULL DRAM RESETB DOWN end =========
2127 13:59:59.460291 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2128 13:59:59.463619 ===================================
2129 13:59:59.463712 LPDDR4 DRAM CONFIGURATION
2130 13:59:59.467196 ===================================
2131 13:59:59.470494 EX_ROW_EN[0] = 0x0
2132 13:59:59.473858 EX_ROW_EN[1] = 0x0
2133 13:59:59.473942 LP4Y_EN = 0x0
2134 13:59:59.477051 WORK_FSP = 0x0
2135 13:59:59.477134 WL = 0x4
2136 13:59:59.480665 RL = 0x4
2137 13:59:59.480748 BL = 0x2
2138 13:59:59.484235 RPST = 0x0
2139 13:59:59.484318 RD_PRE = 0x0
2140 13:59:59.487317 WR_PRE = 0x1
2141 13:59:59.487400 WR_PST = 0x0
2142 13:59:59.490579 DBI_WR = 0x0
2143 13:59:59.490708 DBI_RD = 0x0
2144 13:59:59.494179 OTF = 0x1
2145 13:59:59.496979 ===================================
2146 13:59:59.500486 ===================================
2147 13:59:59.500568 ANA top config
2148 13:59:59.503579 ===================================
2149 13:59:59.507284 DLL_ASYNC_EN = 0
2150 13:59:59.510779 ALL_SLAVE_EN = 0
2151 13:59:59.510869 NEW_RANK_MODE = 1
2152 13:59:59.514068 DLL_IDLE_MODE = 1
2153 13:59:59.516977 LP45_APHY_COMB_EN = 1
2154 13:59:59.520520 TX_ODT_DIS = 1
2155 13:59:59.523737 NEW_8X_MODE = 1
2156 13:59:59.527152 ===================================
2157 13:59:59.530596 ===================================
2158 13:59:59.530698 data_rate = 2400
2159 13:59:59.533793 CKR = 1
2160 13:59:59.537170 DQ_P2S_RATIO = 8
2161 13:59:59.541046 ===================================
2162 13:59:59.544149 CA_P2S_RATIO = 8
2163 13:59:59.547284 DQ_CA_OPEN = 0
2164 13:59:59.551079 DQ_SEMI_OPEN = 0
2165 13:59:59.551164 CA_SEMI_OPEN = 0
2166 13:59:59.553927 CA_FULL_RATE = 0
2167 13:59:59.557341 DQ_CKDIV4_EN = 0
2168 13:59:59.560858 CA_CKDIV4_EN = 0
2169 13:59:59.563800 CA_PREDIV_EN = 0
2170 13:59:59.563884 PH8_DLY = 17
2171 13:59:59.567100 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2172 13:59:59.570591 DQ_AAMCK_DIV = 4
2173 13:59:59.573958 CA_AAMCK_DIV = 4
2174 13:59:59.577152 CA_ADMCK_DIV = 4
2175 13:59:59.580668 DQ_TRACK_CA_EN = 0
2176 13:59:59.584080 CA_PICK = 1200
2177 13:59:59.584167 CA_MCKIO = 1200
2178 13:59:59.587429 MCKIO_SEMI = 0
2179 13:59:59.590641 PLL_FREQ = 2366
2180 13:59:59.593733 DQ_UI_PI_RATIO = 32
2181 13:59:59.597239 CA_UI_PI_RATIO = 0
2182 13:59:59.600770 ===================================
2183 13:59:59.604378 ===================================
2184 13:59:59.607359 memory_type:LPDDR4
2185 13:59:59.607468 GP_NUM : 10
2186 13:59:59.610818 SRAM_EN : 1
2187 13:59:59.610916 MD32_EN : 0
2188 13:59:59.613930 ===================================
2189 13:59:59.617298 [ANA_INIT] >>>>>>>>>>>>>>
2190 13:59:59.620621 <<<<<< [CONFIGURE PHASE]: ANA_TX
2191 13:59:59.624450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2192 13:59:59.627322 ===================================
2193 13:59:59.630808 data_rate = 2400,PCW = 0X5b00
2194 13:59:59.633891 ===================================
2195 13:59:59.637439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2196 13:59:59.640966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 13:59:59.647516 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 13:59:59.651109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2199 13:59:59.654218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2200 13:59:59.657688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2201 13:59:59.661184 [ANA_INIT] flow start
2202 13:59:59.664225 [ANA_INIT] PLL >>>>>>>>
2203 13:59:59.664329 [ANA_INIT] PLL <<<<<<<<
2204 13:59:59.667631 [ANA_INIT] MIDPI >>>>>>>>
2205 13:59:59.670708 [ANA_INIT] MIDPI <<<<<<<<
2206 13:59:59.674141 [ANA_INIT] DLL >>>>>>>>
2207 13:59:59.674239 [ANA_INIT] DLL <<<<<<<<
2208 13:59:59.677661 [ANA_INIT] flow end
2209 13:59:59.680950 ============ LP4 DIFF to SE enter ============
2210 13:59:59.684655 ============ LP4 DIFF to SE exit ============
2211 13:59:59.687772 [ANA_INIT] <<<<<<<<<<<<<
2212 13:59:59.690815 [Flow] Enable top DCM control >>>>>
2213 13:59:59.694395 [Flow] Enable top DCM control <<<<<
2214 13:59:59.697387 Enable DLL master slave shuffle
2215 13:59:59.700595 ==============================================================
2216 13:59:59.704259 Gating Mode config
2217 13:59:59.710517 ==============================================================
2218 13:59:59.710609 Config description:
2219 13:59:59.721063 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2220 13:59:59.727387 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2221 13:59:59.733985 SELPH_MODE 0: By rank 1: By Phase
2222 13:59:59.737762 ==============================================================
2223 13:59:59.740940 GAT_TRACK_EN = 1
2224 13:59:59.744213 RX_GATING_MODE = 2
2225 13:59:59.747626 RX_GATING_TRACK_MODE = 2
2226 13:59:59.750678 SELPH_MODE = 1
2227 13:59:59.754218 PICG_EARLY_EN = 1
2228 13:59:59.757545 VALID_LAT_VALUE = 1
2229 13:59:59.760589 ==============================================================
2230 13:59:59.764106 Enter into Gating configuration >>>>
2231 13:59:59.767118 Exit from Gating configuration <<<<
2232 13:59:59.770909 Enter into DVFS_PRE_config >>>>>
2233 13:59:59.784452 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2234 13:59:59.784540 Exit from DVFS_PRE_config <<<<<
2235 13:59:59.787711 Enter into PICG configuration >>>>
2236 13:59:59.791226 Exit from PICG configuration <<<<
2237 13:59:59.794121 [RX_INPUT] configuration >>>>>
2238 13:59:59.797558 [RX_INPUT] configuration <<<<<
2239 13:59:59.804523 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2240 13:59:59.807850 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2241 13:59:59.814446 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 13:59:59.821170 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 13:59:59.828005 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 13:59:59.834394 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 13:59:59.837824 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2246 13:59:59.841292 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2247 13:59:59.844200 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2248 13:59:59.851279 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2249 13:59:59.854216 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2250 13:59:59.858080 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2251 13:59:59.860854 ===================================
2252 13:59:59.864496 LPDDR4 DRAM CONFIGURATION
2253 13:59:59.868139 ===================================
2254 13:59:59.868253 EX_ROW_EN[0] = 0x0
2255 13:59:59.871153 EX_ROW_EN[1] = 0x0
2256 13:59:59.871241 LP4Y_EN = 0x0
2257 13:59:59.874628 WORK_FSP = 0x0
2258 13:59:59.874718 WL = 0x4
2259 13:59:59.878190 RL = 0x4
2260 13:59:59.878273 BL = 0x2
2261 13:59:59.881388 RPST = 0x0
2262 13:59:59.881478 RD_PRE = 0x0
2263 13:59:59.884609 WR_PRE = 0x1
2264 13:59:59.887751 WR_PST = 0x0
2265 13:59:59.887869 DBI_WR = 0x0
2266 13:59:59.891223 DBI_RD = 0x0
2267 13:59:59.891299 OTF = 0x1
2268 13:59:59.894892 ===================================
2269 13:59:59.897855 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2270 13:59:59.901318 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2271 13:59:59.907828 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2272 13:59:59.911496 ===================================
2273 13:59:59.914707 LPDDR4 DRAM CONFIGURATION
2274 13:59:59.914786 ===================================
2275 13:59:59.917960 EX_ROW_EN[0] = 0x10
2276 13:59:59.921281 EX_ROW_EN[1] = 0x0
2277 13:59:59.921355 LP4Y_EN = 0x0
2278 13:59:59.924810 WORK_FSP = 0x0
2279 13:59:59.924881 WL = 0x4
2280 13:59:59.927990 RL = 0x4
2281 13:59:59.928076 BL = 0x2
2282 13:59:59.931156 RPST = 0x0
2283 13:59:59.931233 RD_PRE = 0x0
2284 13:59:59.934401 WR_PRE = 0x1
2285 13:59:59.934471 WR_PST = 0x0
2286 13:59:59.937664 DBI_WR = 0x0
2287 13:59:59.937745 DBI_RD = 0x0
2288 13:59:59.941302 OTF = 0x1
2289 13:59:59.944704 ===================================
2290 13:59:59.951066 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2291 13:59:59.951149 ==
2292 13:59:59.954602 Dram Type= 6, Freq= 0, CH_0, rank 0
2293 13:59:59.958213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2294 13:59:59.958321 ==
2295 13:59:59.961521 [Duty_Offset_Calibration]
2296 13:59:59.961626 B0:2 B1:1 CA:1
2297 13:59:59.961723
2298 13:59:59.964725 [DutyScan_Calibration_Flow] k_type=0
2299 13:59:59.974773
2300 13:59:59.974862 ==CLK 0==
2301 13:59:59.978307 Final CLK duty delay cell = 0
2302 13:59:59.981964 [0] MAX Duty = 5187%(X100), DQS PI = 24
2303 13:59:59.985543 [0] MIN Duty = 4875%(X100), DQS PI = 0
2304 13:59:59.985620 [0] AVG Duty = 5031%(X100)
2305 13:59:59.985705
2306 13:59:59.988394 CH0 CLK Duty spec in!! Max-Min= 312%
2307 13:59:59.994760 [DutyScan_Calibration_Flow] ====Done====
2308 13:59:59.994849
2309 13:59:59.998695 [DutyScan_Calibration_Flow] k_type=1
2310 14:00:00.013502
2311 14:00:00.013587 ==DQS 0 ==
2312 14:00:00.016670 Final DQS duty delay cell = -4
2313 14:00:00.020434 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2314 14:00:00.023796 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2315 14:00:00.027121 [-4] AVG Duty = 4937%(X100)
2316 14:00:00.027231
2317 14:00:00.027324 ==DQS 1 ==
2318 14:00:00.030756 Final DQS duty delay cell = 0
2319 14:00:00.033745 [0] MAX Duty = 5156%(X100), DQS PI = 0
2320 14:00:00.037211 [0] MIN Duty = 5000%(X100), DQS PI = 34
2321 14:00:00.037285 [0] AVG Duty = 5078%(X100)
2322 14:00:00.040532
2323 14:00:00.043849 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2324 14:00:00.043924
2325 14:00:00.047032 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2326 14:00:00.050575 [DutyScan_Calibration_Flow] ====Done====
2327 14:00:00.050679
2328 14:00:00.053682 [DutyScan_Calibration_Flow] k_type=3
2329 14:00:00.070294
2330 14:00:00.070405 ==DQM 0 ==
2331 14:00:00.073678 Final DQM duty delay cell = 0
2332 14:00:00.076993 [0] MAX Duty = 5156%(X100), DQS PI = 30
2333 14:00:00.080028 [0] MIN Duty = 4906%(X100), DQS PI = 58
2334 14:00:00.083647 [0] AVG Duty = 5031%(X100)
2335 14:00:00.083730
2336 14:00:00.083814 ==DQM 1 ==
2337 14:00:00.087062 Final DQM duty delay cell = 0
2338 14:00:00.090618 [0] MAX Duty = 5125%(X100), DQS PI = 58
2339 14:00:00.093846 [0] MIN Duty = 5031%(X100), DQS PI = 18
2340 14:00:00.093950 [0] AVG Duty = 5078%(X100)
2341 14:00:00.097479
2342 14:00:00.100565 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2343 14:00:00.100646
2344 14:00:00.104065 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2345 14:00:00.106876 [DutyScan_Calibration_Flow] ====Done====
2346 14:00:00.106953
2347 14:00:00.110504 [DutyScan_Calibration_Flow] k_type=2
2348 14:00:00.126845
2349 14:00:00.126951 ==DQ 0 ==
2350 14:00:00.129962 Final DQ duty delay cell = 0
2351 14:00:00.133567 [0] MAX Duty = 5031%(X100), DQS PI = 24
2352 14:00:00.136595 [0] MIN Duty = 4875%(X100), DQS PI = 0
2353 14:00:00.136688 [0] AVG Duty = 4953%(X100)
2354 14:00:00.136773
2355 14:00:00.140186 ==DQ 1 ==
2356 14:00:00.143163 Final DQ duty delay cell = 0
2357 14:00:00.146656 [0] MAX Duty = 5093%(X100), DQS PI = 10
2358 14:00:00.150156 [0] MIN Duty = 4938%(X100), DQS PI = 36
2359 14:00:00.150232 [0] AVG Duty = 5015%(X100)
2360 14:00:00.150314
2361 14:00:00.153859 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2362 14:00:00.153934
2363 14:00:00.160214 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2364 14:00:00.163464 [DutyScan_Calibration_Flow] ====Done====
2365 14:00:00.163571 ==
2366 14:00:00.167181 Dram Type= 6, Freq= 0, CH_1, rank 0
2367 14:00:00.170519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 14:00:00.170619 ==
2369 14:00:00.174234 [Duty_Offset_Calibration]
2370 14:00:00.174346 B0:1 B1:0 CA:0
2371 14:00:00.174442
2372 14:00:00.177135 [DutyScan_Calibration_Flow] k_type=0
2373 14:00:00.186008
2374 14:00:00.186120 ==CLK 0==
2375 14:00:00.189159 Final CLK duty delay cell = -4
2376 14:00:00.192852 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2377 14:00:00.195926 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2378 14:00:00.199729 [-4] AVG Duty = 4953%(X100)
2379 14:00:00.199811
2380 14:00:00.202539 CH1 CLK Duty spec in!! Max-Min= 156%
2381 14:00:00.206057 [DutyScan_Calibration_Flow] ====Done====
2382 14:00:00.206161
2383 14:00:00.209182 [DutyScan_Calibration_Flow] k_type=1
2384 14:00:00.225700
2385 14:00:00.225812 ==DQS 0 ==
2386 14:00:00.229025 Final DQS duty delay cell = 0
2387 14:00:00.232685 [0] MAX Duty = 5062%(X100), DQS PI = 10
2388 14:00:00.235565 [0] MIN Duty = 4875%(X100), DQS PI = 0
2389 14:00:00.235674 [0] AVG Duty = 4968%(X100)
2390 14:00:00.238883
2391 14:00:00.238962 ==DQS 1 ==
2392 14:00:00.242283 Final DQS duty delay cell = 0
2393 14:00:00.245950 [0] MAX Duty = 5218%(X100), DQS PI = 18
2394 14:00:00.249226 [0] MIN Duty = 4969%(X100), DQS PI = 10
2395 14:00:00.249306 [0] AVG Duty = 5093%(X100)
2396 14:00:00.252588
2397 14:00:00.255469 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2398 14:00:00.255574
2399 14:00:00.259091 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2400 14:00:00.262375 [DutyScan_Calibration_Flow] ====Done====
2401 14:00:00.262485
2402 14:00:00.265783 [DutyScan_Calibration_Flow] k_type=3
2403 14:00:00.282219
2404 14:00:00.282334 ==DQM 0 ==
2405 14:00:00.285584 Final DQM duty delay cell = 0
2406 14:00:00.289418 [0] MAX Duty = 5156%(X100), DQS PI = 6
2407 14:00:00.292674 [0] MIN Duty = 5031%(X100), DQS PI = 0
2408 14:00:00.292778 [0] AVG Duty = 5093%(X100)
2409 14:00:00.292881
2410 14:00:00.295726 ==DQM 1 ==
2411 14:00:00.299293 Final DQM duty delay cell = 0
2412 14:00:00.302584 [0] MAX Duty = 5031%(X100), DQS PI = 16
2413 14:00:00.305608 [0] MIN Duty = 4907%(X100), DQS PI = 36
2414 14:00:00.305716 [0] AVG Duty = 4969%(X100)
2415 14:00:00.309077
2416 14:00:00.312359 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2417 14:00:00.312438
2418 14:00:00.315574 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2419 14:00:00.319246 [DutyScan_Calibration_Flow] ====Done====
2420 14:00:00.319347
2421 14:00:00.322091 [DutyScan_Calibration_Flow] k_type=2
2422 14:00:00.338608
2423 14:00:00.338719 ==DQ 0 ==
2424 14:00:00.341787 Final DQ duty delay cell = -4
2425 14:00:00.344690 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2426 14:00:00.347989 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2427 14:00:00.351425 [-4] AVG Duty = 4984%(X100)
2428 14:00:00.351528
2429 14:00:00.351620 ==DQ 1 ==
2430 14:00:00.355142 Final DQ duty delay cell = 0
2431 14:00:00.358159 [0] MAX Duty = 5125%(X100), DQS PI = 20
2432 14:00:00.361706 [0] MIN Duty = 4969%(X100), DQS PI = 12
2433 14:00:00.361790 [0] AVG Duty = 5047%(X100)
2434 14:00:00.364922
2435 14:00:00.367903 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2436 14:00:00.368012
2437 14:00:00.371337 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2438 14:00:00.374824 [DutyScan_Calibration_Flow] ====Done====
2439 14:00:00.378718 nWR fixed to 30
2440 14:00:00.378803 [ModeRegInit_LP4] CH0 RK0
2441 14:00:00.382099 [ModeRegInit_LP4] CH0 RK1
2442 14:00:00.385302 [ModeRegInit_LP4] CH1 RK0
2443 14:00:00.385386 [ModeRegInit_LP4] CH1 RK1
2444 14:00:00.388102 match AC timing 7
2445 14:00:00.391857 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2446 14:00:00.394716 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2447 14:00:00.401861 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2448 14:00:00.405022 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2449 14:00:00.411837 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2450 14:00:00.411946 ==
2451 14:00:00.415247 Dram Type= 6, Freq= 0, CH_0, rank 0
2452 14:00:00.418236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2453 14:00:00.418339 ==
2454 14:00:00.425027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2455 14:00:00.428525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2456 14:00:00.438044 [CA 0] Center 39 (8~70) winsize 63
2457 14:00:00.441628 [CA 1] Center 39 (8~70) winsize 63
2458 14:00:00.444677 [CA 2] Center 35 (5~66) winsize 62
2459 14:00:00.448394 [CA 3] Center 34 (4~65) winsize 62
2460 14:00:00.451920 [CA 4] Center 33 (3~64) winsize 62
2461 14:00:00.455306 [CA 5] Center 32 (3~62) winsize 60
2462 14:00:00.455389
2463 14:00:00.458322 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2464 14:00:00.458398
2465 14:00:00.461891 [CATrainingPosCal] consider 1 rank data
2466 14:00:00.465100 u2DelayCellTimex100 = 270/100 ps
2467 14:00:00.468686 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2468 14:00:00.471655 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2469 14:00:00.478717 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2470 14:00:00.481896 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2471 14:00:00.485017 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2472 14:00:00.488322 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2473 14:00:00.488414
2474 14:00:00.491880 CA PerBit enable=1, Macro0, CA PI delay=32
2475 14:00:00.491965
2476 14:00:00.495010 [CBTSetCACLKResult] CA Dly = 32
2477 14:00:00.495122 CS Dly: 6 (0~37)
2478 14:00:00.495199 ==
2479 14:00:00.498885 Dram Type= 6, Freq= 0, CH_0, rank 1
2480 14:00:00.504889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 14:00:00.504979 ==
2482 14:00:00.508544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 14:00:00.514899 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2484 14:00:00.523706 [CA 0] Center 38 (8~69) winsize 62
2485 14:00:00.527123 [CA 1] Center 38 (8~69) winsize 62
2486 14:00:00.530621 [CA 2] Center 35 (4~66) winsize 63
2487 14:00:00.534132 [CA 3] Center 34 (4~65) winsize 62
2488 14:00:00.537704 [CA 4] Center 33 (3~64) winsize 62
2489 14:00:00.540675 [CA 5] Center 32 (3~62) winsize 60
2490 14:00:00.540784
2491 14:00:00.544548 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2492 14:00:00.544660
2493 14:00:00.547521 [CATrainingPosCal] consider 2 rank data
2494 14:00:00.551282 u2DelayCellTimex100 = 270/100 ps
2495 14:00:00.554150 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2496 14:00:00.557602 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2497 14:00:00.561199 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2498 14:00:00.567857 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2499 14:00:00.571221 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2500 14:00:00.574710 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2501 14:00:00.574790
2502 14:00:00.577814 CA PerBit enable=1, Macro0, CA PI delay=32
2503 14:00:00.577891
2504 14:00:00.581287 [CBTSetCACLKResult] CA Dly = 32
2505 14:00:00.581363 CS Dly: 6 (0~38)
2506 14:00:00.581432
2507 14:00:00.584345 ----->DramcWriteLeveling(PI) begin...
2508 14:00:00.584422 ==
2509 14:00:00.587670 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 14:00:00.594338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 14:00:00.594426 ==
2512 14:00:00.597604 Write leveling (Byte 0): 34 => 34
2513 14:00:00.601052 Write leveling (Byte 1): 29 => 29
2514 14:00:00.601130 DramcWriteLeveling(PI) end<-----
2515 14:00:00.601194
2516 14:00:00.604197 ==
2517 14:00:00.607767 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 14:00:00.610982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 14:00:00.611072 ==
2520 14:00:00.614638 [Gating] SW mode calibration
2521 14:00:00.621090 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2522 14:00:00.624353 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2523 14:00:00.631073 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2524 14:00:00.634416 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2525 14:00:00.637527 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 14:00:00.644267 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 14:00:00.647527 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 14:00:00.651164 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 14:00:00.657774 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2530 14:00:00.661050 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2531 14:00:00.664904 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2532 14:00:00.668114 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 14:00:00.674812 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 14:00:00.677780 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 14:00:00.681434 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 14:00:00.688049 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 14:00:00.691666 1 0 24 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2538 14:00:00.694368 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2539 14:00:00.700930 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
2540 14:00:00.704574 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 14:00:00.707597 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 14:00:00.714816 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 14:00:00.717625 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 14:00:00.721235 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 14:00:00.728029 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2546 14:00:00.731824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2547 14:00:00.734715 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2548 14:00:00.741329 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 14:00:00.744733 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 14:00:00.748206 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 14:00:00.751071 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 14:00:00.758127 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 14:00:00.761694 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 14:00:00.764933 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 14:00:00.771629 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 14:00:00.774693 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 14:00:00.778014 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 14:00:00.784567 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 14:00:00.788409 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 14:00:00.791614 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 14:00:00.798170 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 14:00:00.801701 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2563 14:00:00.804670 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2564 14:00:00.808220 Total UI for P1: 0, mck2ui 16
2565 14:00:00.811890 best dqsien dly found for B0: ( 1, 3, 28)
2566 14:00:00.818213 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 14:00:00.818297 Total UI for P1: 0, mck2ui 16
2568 14:00:00.821473 best dqsien dly found for B1: ( 1, 4, 0)
2569 14:00:00.827974 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2570 14:00:00.831560 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2571 14:00:00.831654
2572 14:00:00.835486 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2573 14:00:00.838301 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2574 14:00:00.841660 [Gating] SW calibration Done
2575 14:00:00.841744 ==
2576 14:00:00.845153 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 14:00:00.848424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 14:00:00.848507 ==
2579 14:00:00.848573 RX Vref Scan: 0
2580 14:00:00.851409
2581 14:00:00.851492 RX Vref 0 -> 0, step: 1
2582 14:00:00.851558
2583 14:00:00.854788 RX Delay -40 -> 252, step: 8
2584 14:00:00.858134 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2585 14:00:00.861566 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2586 14:00:00.868454 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2587 14:00:00.871584 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2588 14:00:00.875047 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2589 14:00:00.878579 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2590 14:00:00.881983 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2591 14:00:00.888835 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2592 14:00:00.891646 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2593 14:00:00.895259 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2594 14:00:00.899054 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2595 14:00:00.901852 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2596 14:00:00.905446 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2597 14:00:00.912158 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2598 14:00:00.915003 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2599 14:00:00.918807 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2600 14:00:00.918916 ==
2601 14:00:00.922102 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 14:00:00.925279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 14:00:00.925363 ==
2604 14:00:00.928630 DQS Delay:
2605 14:00:00.928713 DQS0 = 0, DQS1 = 0
2606 14:00:00.932098 DQM Delay:
2607 14:00:00.932182 DQM0 = 121, DQM1 = 113
2608 14:00:00.935417 DQ Delay:
2609 14:00:00.938519 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2610 14:00:00.941831 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2611 14:00:00.945498 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2612 14:00:00.948366 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2613 14:00:00.948440
2614 14:00:00.948503
2615 14:00:00.948562 ==
2616 14:00:00.952052 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 14:00:00.955303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 14:00:00.955417 ==
2619 14:00:00.955512
2620 14:00:00.955605
2621 14:00:00.958716 TX Vref Scan disable
2622 14:00:00.962104 == TX Byte 0 ==
2623 14:00:00.965609 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2624 14:00:00.968405 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2625 14:00:00.971925 == TX Byte 1 ==
2626 14:00:00.975563 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2627 14:00:00.978844 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2628 14:00:00.978922 ==
2629 14:00:00.981768 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 14:00:00.985224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 14:00:00.988241 ==
2632 14:00:00.999124 TX Vref=22, minBit 4, minWin=24, winSum=404
2633 14:00:01.002384 TX Vref=24, minBit 0, minWin=25, winSum=410
2634 14:00:01.005843 TX Vref=26, minBit 7, minWin=25, winSum=418
2635 14:00:01.008960 TX Vref=28, minBit 11, minWin=25, winSum=419
2636 14:00:01.012526 TX Vref=30, minBit 0, minWin=26, winSum=423
2637 14:00:01.019197 TX Vref=32, minBit 10, minWin=25, winSum=418
2638 14:00:01.022595 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
2639 14:00:01.022705
2640 14:00:01.025763 Final TX Range 1 Vref 30
2641 14:00:01.025874
2642 14:00:01.025968 ==
2643 14:00:01.029158 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 14:00:01.032144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 14:00:01.032254 ==
2646 14:00:01.035720
2647 14:00:01.035803
2648 14:00:01.035869 TX Vref Scan disable
2649 14:00:01.038825 == TX Byte 0 ==
2650 14:00:01.042320 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2651 14:00:01.045437 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2652 14:00:01.048632 == TX Byte 1 ==
2653 14:00:01.052131 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2654 14:00:01.055848 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2655 14:00:01.058926
2656 14:00:01.059029 [DATLAT]
2657 14:00:01.059121 Freq=1200, CH0 RK0
2658 14:00:01.059211
2659 14:00:01.062429 DATLAT Default: 0xd
2660 14:00:01.062513 0, 0xFFFF, sum = 0
2661 14:00:01.065403 1, 0xFFFF, sum = 0
2662 14:00:01.065531 2, 0xFFFF, sum = 0
2663 14:00:01.068778 3, 0xFFFF, sum = 0
2664 14:00:01.068905 4, 0xFFFF, sum = 0
2665 14:00:01.072011 5, 0xFFFF, sum = 0
2666 14:00:01.075621 6, 0xFFFF, sum = 0
2667 14:00:01.075758 7, 0xFFFF, sum = 0
2668 14:00:01.079151 8, 0xFFFF, sum = 0
2669 14:00:01.079278 9, 0xFFFF, sum = 0
2670 14:00:01.082239 10, 0xFFFF, sum = 0
2671 14:00:01.082368 11, 0xFFFF, sum = 0
2672 14:00:01.086118 12, 0x0, sum = 1
2673 14:00:01.086243 13, 0x0, sum = 2
2674 14:00:01.088969 14, 0x0, sum = 3
2675 14:00:01.089076 15, 0x0, sum = 4
2676 14:00:01.089172 best_step = 13
2677 14:00:01.089262
2678 14:00:01.092484 ==
2679 14:00:01.095404 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 14:00:01.098876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 14:00:01.098964 ==
2682 14:00:01.099030 RX Vref Scan: 1
2683 14:00:01.099091
2684 14:00:01.102188 Set Vref Range= 32 -> 127
2685 14:00:01.102271
2686 14:00:01.105935 RX Vref 32 -> 127, step: 1
2687 14:00:01.106018
2688 14:00:01.108797 RX Delay -13 -> 252, step: 4
2689 14:00:01.108881
2690 14:00:01.112231 Set Vref, RX VrefLevel [Byte0]: 32
2691 14:00:01.115395 [Byte1]: 32
2692 14:00:01.115478
2693 14:00:01.119125 Set Vref, RX VrefLevel [Byte0]: 33
2694 14:00:01.122554 [Byte1]: 33
2695 14:00:01.122664
2696 14:00:01.125905 Set Vref, RX VrefLevel [Byte0]: 34
2697 14:00:01.128989 [Byte1]: 34
2698 14:00:01.132888
2699 14:00:01.133011 Set Vref, RX VrefLevel [Byte0]: 35
2700 14:00:01.136496 [Byte1]: 35
2701 14:00:01.141126
2702 14:00:01.141254 Set Vref, RX VrefLevel [Byte0]: 36
2703 14:00:01.144706 [Byte1]: 36
2704 14:00:01.148615
2705 14:00:01.148739 Set Vref, RX VrefLevel [Byte0]: 37
2706 14:00:01.152245 [Byte1]: 37
2707 14:00:01.156655
2708 14:00:01.156775 Set Vref, RX VrefLevel [Byte0]: 38
2709 14:00:01.159963 [Byte1]: 38
2710 14:00:01.164672
2711 14:00:01.164793 Set Vref, RX VrefLevel [Byte0]: 39
2712 14:00:01.168303 [Byte1]: 39
2713 14:00:01.172505
2714 14:00:01.172633 Set Vref, RX VrefLevel [Byte0]: 40
2715 14:00:01.175676 [Byte1]: 40
2716 14:00:01.180596
2717 14:00:01.180721 Set Vref, RX VrefLevel [Byte0]: 41
2718 14:00:01.183885 [Byte1]: 41
2719 14:00:01.188598
2720 14:00:01.188722 Set Vref, RX VrefLevel [Byte0]: 42
2721 14:00:01.191691 [Byte1]: 42
2722 14:00:01.195984
2723 14:00:01.196067 Set Vref, RX VrefLevel [Byte0]: 43
2724 14:00:01.199737 [Byte1]: 43
2725 14:00:01.204376
2726 14:00:01.204459 Set Vref, RX VrefLevel [Byte0]: 44
2727 14:00:01.207290 [Byte1]: 44
2728 14:00:01.211815
2729 14:00:01.211944 Set Vref, RX VrefLevel [Byte0]: 45
2730 14:00:01.215393 [Byte1]: 45
2731 14:00:01.219846
2732 14:00:01.219924 Set Vref, RX VrefLevel [Byte0]: 46
2733 14:00:01.223007 [Byte1]: 46
2734 14:00:01.228080
2735 14:00:01.228163 Set Vref, RX VrefLevel [Byte0]: 47
2736 14:00:01.231203 [Byte1]: 47
2737 14:00:01.235860
2738 14:00:01.235942 Set Vref, RX VrefLevel [Byte0]: 48
2739 14:00:01.238959 [Byte1]: 48
2740 14:00:01.243579
2741 14:00:01.243673 Set Vref, RX VrefLevel [Byte0]: 49
2742 14:00:01.247207 [Byte1]: 49
2743 14:00:01.251160
2744 14:00:01.251242 Set Vref, RX VrefLevel [Byte0]: 50
2745 14:00:01.257850 [Byte1]: 50
2746 14:00:01.257933
2747 14:00:01.261078 Set Vref, RX VrefLevel [Byte0]: 51
2748 14:00:01.264364 [Byte1]: 51
2749 14:00:01.264470
2750 14:00:01.267932 Set Vref, RX VrefLevel [Byte0]: 52
2751 14:00:01.270975 [Byte1]: 52
2752 14:00:01.275093
2753 14:00:01.275180 Set Vref, RX VrefLevel [Byte0]: 53
2754 14:00:01.278608 [Byte1]: 53
2755 14:00:01.282708
2756 14:00:01.282812 Set Vref, RX VrefLevel [Byte0]: 54
2757 14:00:01.286554 [Byte1]: 54
2758 14:00:01.290917
2759 14:00:01.291021 Set Vref, RX VrefLevel [Byte0]: 55
2760 14:00:01.294416 [Byte1]: 55
2761 14:00:01.298660
2762 14:00:01.298765 Set Vref, RX VrefLevel [Byte0]: 56
2763 14:00:01.302427 [Byte1]: 56
2764 14:00:01.306731
2765 14:00:01.306818 Set Vref, RX VrefLevel [Byte0]: 57
2766 14:00:01.310340 [Byte1]: 57
2767 14:00:01.314756
2768 14:00:01.314859 Set Vref, RX VrefLevel [Byte0]: 58
2769 14:00:01.317689 [Byte1]: 58
2770 14:00:01.322295
2771 14:00:01.322373 Set Vref, RX VrefLevel [Byte0]: 59
2772 14:00:01.325946 [Byte1]: 59
2773 14:00:01.330234
2774 14:00:01.330316 Set Vref, RX VrefLevel [Byte0]: 60
2775 14:00:01.333548 [Byte1]: 60
2776 14:00:01.338241
2777 14:00:01.338324 Set Vref, RX VrefLevel [Byte0]: 61
2778 14:00:01.341520 [Byte1]: 61
2779 14:00:01.346333
2780 14:00:01.346442 Set Vref, RX VrefLevel [Byte0]: 62
2781 14:00:01.349649 [Byte1]: 62
2782 14:00:01.354006
2783 14:00:01.354088 Set Vref, RX VrefLevel [Byte0]: 63
2784 14:00:01.357248 [Byte1]: 63
2785 14:00:01.361959
2786 14:00:01.362075 Set Vref, RX VrefLevel [Byte0]: 64
2787 14:00:01.365397 [Byte1]: 64
2788 14:00:01.369979
2789 14:00:01.370096 Set Vref, RX VrefLevel [Byte0]: 65
2790 14:00:01.373125 [Byte1]: 65
2791 14:00:01.377649
2792 14:00:01.377733 Set Vref, RX VrefLevel [Byte0]: 66
2793 14:00:01.381536 [Byte1]: 66
2794 14:00:01.385465
2795 14:00:01.385576 Set Vref, RX VrefLevel [Byte0]: 67
2796 14:00:01.389071 [Byte1]: 67
2797 14:00:01.393656
2798 14:00:01.393756 Set Vref, RX VrefLevel [Byte0]: 68
2799 14:00:01.396878 [Byte1]: 68
2800 14:00:01.401334
2801 14:00:01.401418 Set Vref, RX VrefLevel [Byte0]: 69
2802 14:00:01.404989 [Byte1]: 69
2803 14:00:01.409096
2804 14:00:01.409180 Set Vref, RX VrefLevel [Byte0]: 70
2805 14:00:01.412999 [Byte1]: 70
2806 14:00:01.416854
2807 14:00:01.416940 Final RX Vref Byte 0 = 54 to rank0
2808 14:00:01.420406 Final RX Vref Byte 1 = 52 to rank0
2809 14:00:01.424194 Final RX Vref Byte 0 = 54 to rank1
2810 14:00:01.426861 Final RX Vref Byte 1 = 52 to rank1==
2811 14:00:01.430588 Dram Type= 6, Freq= 0, CH_0, rank 0
2812 14:00:01.437351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2813 14:00:01.437438 ==
2814 14:00:01.437505 DQS Delay:
2815 14:00:01.437567 DQS0 = 0, DQS1 = 0
2816 14:00:01.440573 DQM Delay:
2817 14:00:01.440657 DQM0 = 120, DQM1 = 112
2818 14:00:01.443688 DQ Delay:
2819 14:00:01.447153 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2820 14:00:01.450670 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2821 14:00:01.453583 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2822 14:00:01.457136 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =122
2823 14:00:01.457219
2824 14:00:01.457285
2825 14:00:01.463928 [DQSOSCAuto] RK0, (LSB)MR18= 0x1710, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2826 14:00:01.467220 CH0 RK0: MR19=404, MR18=1710
2827 14:00:01.474120 CH0_RK0: MR19=0x404, MR18=0x1710, DQSOSC=401, MR23=63, INC=40, DEC=27
2828 14:00:01.474250
2829 14:00:01.477594 ----->DramcWriteLeveling(PI) begin...
2830 14:00:01.477682 ==
2831 14:00:01.480294 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 14:00:01.483688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 14:00:01.487239 ==
2834 14:00:01.487316 Write leveling (Byte 0): 33 => 33
2835 14:00:01.490877 Write leveling (Byte 1): 28 => 28
2836 14:00:01.493731 DramcWriteLeveling(PI) end<-----
2837 14:00:01.493815
2838 14:00:01.493881 ==
2839 14:00:01.497234 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 14:00:01.504013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 14:00:01.504097 ==
2842 14:00:01.504175 [Gating] SW mode calibration
2843 14:00:01.513604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2844 14:00:01.517228 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2845 14:00:01.520868 0 15 0 | B1->B0 | 3333 3030 | 1 1 | (0 0) (1 1)
2846 14:00:01.527486 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 14:00:01.530846 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 14:00:01.533894 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 14:00:01.540928 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 14:00:01.543763 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 14:00:01.547166 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 14:00:01.554162 0 15 28 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (0 1)
2853 14:00:01.557512 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 14:00:01.561049 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 14:00:01.567922 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 14:00:01.570873 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 14:00:01.574102 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 14:00:01.577520 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 14:00:01.584644 1 0 24 | B1->B0 | 2626 2828 | 0 1 | (0 0) (0 0)
2860 14:00:01.587740 1 0 28 | B1->B0 | 3c3c 3d3d | 0 0 | (0 0) (0 0)
2861 14:00:01.590995 1 1 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
2862 14:00:01.597969 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 14:00:01.600998 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 14:00:01.604636 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 14:00:01.611023 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 14:00:01.614271 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 14:00:01.617558 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 14:00:01.624814 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2869 14:00:01.627607 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2870 14:00:01.631137 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 14:00:01.637627 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 14:00:01.641331 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 14:00:01.644910 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 14:00:01.651361 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 14:00:01.654567 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 14:00:01.658152 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 14:00:01.661145 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 14:00:01.668085 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 14:00:01.671732 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 14:00:01.674553 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 14:00:01.681564 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 14:00:01.684856 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 14:00:01.688242 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 14:00:01.694635 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2885 14:00:01.698005 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 14:00:01.701671 Total UI for P1: 0, mck2ui 16
2887 14:00:01.705036 best dqsien dly found for B0: ( 1, 3, 28)
2888 14:00:01.707937 Total UI for P1: 0, mck2ui 16
2889 14:00:01.711721 best dqsien dly found for B1: ( 1, 3, 30)
2890 14:00:01.715217 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2891 14:00:01.718403 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2892 14:00:01.718532
2893 14:00:01.721722 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2894 14:00:01.725073 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2895 14:00:01.728211 [Gating] SW calibration Done
2896 14:00:01.728341 ==
2897 14:00:01.731691 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 14:00:01.735377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 14:00:01.735506 ==
2900 14:00:01.738856 RX Vref Scan: 0
2901 14:00:01.738979
2902 14:00:01.739108 RX Vref 0 -> 0, step: 1
2903 14:00:01.741693
2904 14:00:01.741825 RX Delay -40 -> 252, step: 8
2905 14:00:01.748353 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2906 14:00:01.751767 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2907 14:00:01.755325 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2908 14:00:01.758402 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2909 14:00:01.761846 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2910 14:00:01.765104 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2911 14:00:01.771439 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2912 14:00:01.774994 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2913 14:00:01.778553 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2914 14:00:01.781712 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2915 14:00:01.785338 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2916 14:00:01.791762 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2917 14:00:01.795456 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2918 14:00:01.798673 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2919 14:00:01.801729 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2920 14:00:01.805273 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2921 14:00:01.808814 ==
2922 14:00:01.812313 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 14:00:01.815127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 14:00:01.815211 ==
2925 14:00:01.815277 DQS Delay:
2926 14:00:01.818498 DQS0 = 0, DQS1 = 0
2927 14:00:01.818581 DQM Delay:
2928 14:00:01.822113 DQM0 = 122, DQM1 = 113
2929 14:00:01.822197 DQ Delay:
2930 14:00:01.825502 DQ0 =119, DQ1 =119, DQ2 =123, DQ3 =119
2931 14:00:01.828773 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2932 14:00:01.832255 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2933 14:00:01.835521 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2934 14:00:01.835603
2935 14:00:01.835679
2936 14:00:01.835740 ==
2937 14:00:01.838821 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 14:00:01.845584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 14:00:01.845671 ==
2940 14:00:01.845737
2941 14:00:01.845798
2942 14:00:01.845857 TX Vref Scan disable
2943 14:00:01.848970 == TX Byte 0 ==
2944 14:00:01.851980 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2945 14:00:01.858766 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2946 14:00:01.858850 == TX Byte 1 ==
2947 14:00:01.862231 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2948 14:00:01.868716 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2949 14:00:01.868826 ==
2950 14:00:01.871917 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 14:00:01.875213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 14:00:01.875297 ==
2953 14:00:01.887098 TX Vref=22, minBit 3, minWin=25, winSum=409
2954 14:00:01.890402 TX Vref=24, minBit 3, minWin=25, winSum=417
2955 14:00:01.893704 TX Vref=26, minBit 3, minWin=25, winSum=421
2956 14:00:01.896828 TX Vref=28, minBit 10, minWin=25, winSum=421
2957 14:00:01.900446 TX Vref=30, minBit 1, minWin=26, winSum=427
2958 14:00:01.903984 TX Vref=32, minBit 0, minWin=26, winSum=420
2959 14:00:01.910144 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
2960 14:00:01.910272
2961 14:00:01.913693 Final TX Range 1 Vref 30
2962 14:00:01.913818
2963 14:00:01.913928 ==
2964 14:00:01.917298 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 14:00:01.920292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 14:00:01.920418 ==
2967 14:00:01.920531
2968 14:00:01.920640
2969 14:00:01.924085 TX Vref Scan disable
2970 14:00:01.927120 == TX Byte 0 ==
2971 14:00:01.930511 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2972 14:00:01.933898 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2973 14:00:01.937200 == TX Byte 1 ==
2974 14:00:01.940563 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2975 14:00:01.944409 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2976 14:00:01.944530
2977 14:00:01.947096 [DATLAT]
2978 14:00:01.947211 Freq=1200, CH0 RK1
2979 14:00:01.947323
2980 14:00:01.950288 DATLAT Default: 0xd
2981 14:00:01.950402 0, 0xFFFF, sum = 0
2982 14:00:01.953828 1, 0xFFFF, sum = 0
2983 14:00:01.953955 2, 0xFFFF, sum = 0
2984 14:00:01.956835 3, 0xFFFF, sum = 0
2985 14:00:01.956959 4, 0xFFFF, sum = 0
2986 14:00:01.960631 5, 0xFFFF, sum = 0
2987 14:00:01.960756 6, 0xFFFF, sum = 0
2988 14:00:01.964098 7, 0xFFFF, sum = 0
2989 14:00:01.964225 8, 0xFFFF, sum = 0
2990 14:00:01.967305 9, 0xFFFF, sum = 0
2991 14:00:01.970774 10, 0xFFFF, sum = 0
2992 14:00:01.970881 11, 0xFFFF, sum = 0
2993 14:00:01.973688 12, 0x0, sum = 1
2994 14:00:01.973788 13, 0x0, sum = 2
2995 14:00:01.973879 14, 0x0, sum = 3
2996 14:00:01.976968 15, 0x0, sum = 4
2997 14:00:01.977095 best_step = 13
2998 14:00:01.977209
2999 14:00:01.977319 ==
3000 14:00:01.980496 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 14:00:01.987629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 14:00:01.987767 ==
3003 14:00:01.987882 RX Vref Scan: 0
3004 14:00:01.987991
3005 14:00:01.990338 RX Vref 0 -> 0, step: 1
3006 14:00:01.990455
3007 14:00:01.994220 RX Delay -13 -> 252, step: 4
3008 14:00:01.997660 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3009 14:00:02.000851 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3010 14:00:02.007041 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3011 14:00:02.010390 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3012 14:00:02.014265 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3013 14:00:02.017464 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3014 14:00:02.020864 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3015 14:00:02.027574 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3016 14:00:02.030967 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3017 14:00:02.034086 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3018 14:00:02.037286 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3019 14:00:02.040614 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3020 14:00:02.047515 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3021 14:00:02.050444 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3022 14:00:02.054083 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3023 14:00:02.057464 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3024 14:00:02.057588 ==
3025 14:00:02.060429 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 14:00:02.064029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 14:00:02.067296 ==
3028 14:00:02.067417 DQS Delay:
3029 14:00:02.067532 DQS0 = 0, DQS1 = 0
3030 14:00:02.070766 DQM Delay:
3031 14:00:02.070888 DQM0 = 121, DQM1 = 111
3032 14:00:02.074469 DQ Delay:
3033 14:00:02.077323 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3034 14:00:02.080707 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3035 14:00:02.084457 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =104
3036 14:00:02.087239 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =120
3037 14:00:02.087387
3038 14:00:02.087497
3039 14:00:02.093940 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 402 ps
3040 14:00:02.096977 CH0 RK1: MR19=403, MR18=13F4
3041 14:00:02.104095 CH0_RK1: MR19=0x403, MR18=0x13F4, DQSOSC=402, MR23=63, INC=40, DEC=27
3042 14:00:02.107102 [RxdqsGatingPostProcess] freq 1200
3043 14:00:02.113932 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3044 14:00:02.117164 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 14:00:02.117286 best DQS1 dly(2T, 0.5T) = (0, 12)
3046 14:00:02.120575 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 14:00:02.123954 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3048 14:00:02.127707 best DQS0 dly(2T, 0.5T) = (0, 11)
3049 14:00:02.130417 best DQS1 dly(2T, 0.5T) = (0, 11)
3050 14:00:02.134190 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3051 14:00:02.137111 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3052 14:00:02.140614 Pre-setting of DQS Precalculation
3053 14:00:02.147399 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3054 14:00:02.147486 ==
3055 14:00:02.150943 Dram Type= 6, Freq= 0, CH_1, rank 0
3056 14:00:02.154191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 14:00:02.154318 ==
3058 14:00:02.160817 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3059 14:00:02.163717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3060 14:00:02.173482 [CA 0] Center 37 (7~68) winsize 62
3061 14:00:02.177082 [CA 1] Center 37 (7~68) winsize 62
3062 14:00:02.180094 [CA 2] Center 35 (5~65) winsize 61
3063 14:00:02.183642 [CA 3] Center 34 (4~64) winsize 61
3064 14:00:02.186600 [CA 4] Center 34 (4~64) winsize 61
3065 14:00:02.190088 [CA 5] Center 33 (3~63) winsize 61
3066 14:00:02.190196
3067 14:00:02.193829 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3068 14:00:02.193928
3069 14:00:02.196681 [CATrainingPosCal] consider 1 rank data
3070 14:00:02.200478 u2DelayCellTimex100 = 270/100 ps
3071 14:00:02.203889 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3072 14:00:02.206677 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3073 14:00:02.213887 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3074 14:00:02.217383 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3075 14:00:02.220188 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3076 14:00:02.224208 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3077 14:00:02.224342
3078 14:00:02.226805 CA PerBit enable=1, Macro0, CA PI delay=33
3079 14:00:02.226912
3080 14:00:02.230202 [CBTSetCACLKResult] CA Dly = 33
3081 14:00:02.230313 CS Dly: 7 (0~38)
3082 14:00:02.230407 ==
3083 14:00:02.233457 Dram Type= 6, Freq= 0, CH_1, rank 1
3084 14:00:02.240631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 14:00:02.240718 ==
3086 14:00:02.244094 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3087 14:00:02.250975 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3088 14:00:02.259032 [CA 0] Center 37 (7~68) winsize 62
3089 14:00:02.262635 [CA 1] Center 38 (7~69) winsize 63
3090 14:00:02.265677 [CA 2] Center 35 (5~65) winsize 61
3091 14:00:02.269233 [CA 3] Center 35 (5~65) winsize 61
3092 14:00:02.272462 [CA 4] Center 34 (4~65) winsize 62
3093 14:00:02.275941 [CA 5] Center 33 (4~63) winsize 60
3094 14:00:02.276051
3095 14:00:02.278986 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3096 14:00:02.279086
3097 14:00:02.282741 [CATrainingPosCal] consider 2 rank data
3098 14:00:02.286157 u2DelayCellTimex100 = 270/100 ps
3099 14:00:02.289157 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3100 14:00:02.292702 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3101 14:00:02.299131 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3102 14:00:02.302672 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3103 14:00:02.306250 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3104 14:00:02.309129 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3105 14:00:02.309255
3106 14:00:02.312626 CA PerBit enable=1, Macro0, CA PI delay=33
3107 14:00:02.312714
3108 14:00:02.316039 [CBTSetCACLKResult] CA Dly = 33
3109 14:00:02.316120 CS Dly: 8 (0~41)
3110 14:00:02.316202
3111 14:00:02.319105 ----->DramcWriteLeveling(PI) begin...
3112 14:00:02.319182 ==
3113 14:00:02.322847 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 14:00:02.329152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 14:00:02.329244 ==
3116 14:00:02.332635 Write leveling (Byte 0): 27 => 27
3117 14:00:02.336128 Write leveling (Byte 1): 27 => 27
3118 14:00:02.336236 DramcWriteLeveling(PI) end<-----
3119 14:00:02.339131
3120 14:00:02.339236 ==
3121 14:00:02.342888 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 14:00:02.346101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 14:00:02.346179 ==
3124 14:00:02.349934 [Gating] SW mode calibration
3125 14:00:02.356238 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3126 14:00:02.359204 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3127 14:00:02.365967 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3128 14:00:02.369471 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 14:00:02.373259 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 14:00:02.379588 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 14:00:02.382870 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 14:00:02.386038 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 14:00:02.393102 0 15 24 | B1->B0 | 3232 2d2d | 0 1 | (0 0) (1 0)
3134 14:00:02.396441 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3135 14:00:02.399548 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 14:00:02.406315 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 14:00:02.409342 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 14:00:02.413153 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 14:00:02.415962 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 14:00:02.422912 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3141 14:00:02.426293 1 0 24 | B1->B0 | 2e2e 3e3e | 1 0 | (0 0) (0 0)
3142 14:00:02.429436 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 14:00:02.436189 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 14:00:02.439201 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 14:00:02.442946 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 14:00:02.449791 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 14:00:02.452773 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 14:00:02.456205 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 14:00:02.462843 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3150 14:00:02.465982 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3151 14:00:02.469537 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 14:00:02.475989 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 14:00:02.479071 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 14:00:02.482622 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 14:00:02.489571 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 14:00:02.492958 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 14:00:02.495772 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 14:00:02.502546 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 14:00:02.505842 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 14:00:02.509453 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 14:00:02.515997 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 14:00:02.519028 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 14:00:02.522621 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 14:00:02.529312 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 14:00:02.532345 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3166 14:00:02.535646 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3167 14:00:02.539392 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 14:00:02.542790 Total UI for P1: 0, mck2ui 16
3169 14:00:02.545827 best dqsien dly found for B0: ( 1, 3, 26)
3170 14:00:02.549026 Total UI for P1: 0, mck2ui 16
3171 14:00:02.552578 best dqsien dly found for B1: ( 1, 3, 26)
3172 14:00:02.555968 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3173 14:00:02.559498 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3174 14:00:02.559620
3175 14:00:02.566457 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3176 14:00:02.569006 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3177 14:00:02.572494 [Gating] SW calibration Done
3178 14:00:02.572620 ==
3179 14:00:02.575690 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 14:00:02.579554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 14:00:02.579672 ==
3182 14:00:02.579742 RX Vref Scan: 0
3183 14:00:02.579805
3184 14:00:02.582436 RX Vref 0 -> 0, step: 1
3185 14:00:02.582535
3186 14:00:02.585988 RX Delay -40 -> 252, step: 8
3187 14:00:02.589480 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3188 14:00:02.592626 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3189 14:00:02.599208 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3190 14:00:02.602734 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3191 14:00:02.605967 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3192 14:00:02.609187 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3193 14:00:02.612952 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3194 14:00:02.616317 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3195 14:00:02.622950 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3196 14:00:02.626199 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3197 14:00:02.629368 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3198 14:00:02.633204 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3199 14:00:02.636103 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3200 14:00:02.642966 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3201 14:00:02.646145 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3202 14:00:02.649164 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3203 14:00:02.649294 ==
3204 14:00:02.652541 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 14:00:02.655915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 14:00:02.659355 ==
3207 14:00:02.659513 DQS Delay:
3208 14:00:02.659628 DQS0 = 0, DQS1 = 0
3209 14:00:02.662908 DQM Delay:
3210 14:00:02.663066 DQM0 = 120, DQM1 = 116
3211 14:00:02.666508 DQ Delay:
3212 14:00:02.669341 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3213 14:00:02.672544 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3214 14:00:02.675696 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3215 14:00:02.679231 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3216 14:00:02.679369
3217 14:00:02.679480
3218 14:00:02.679589 ==
3219 14:00:02.682632 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 14:00:02.686273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 14:00:02.686400 ==
3222 14:00:02.686517
3223 14:00:02.686629
3224 14:00:02.689221 TX Vref Scan disable
3225 14:00:02.692812 == TX Byte 0 ==
3226 14:00:02.696216 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3227 14:00:02.699245 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3228 14:00:02.702981 == TX Byte 1 ==
3229 14:00:02.706185 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3230 14:00:02.709182 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3231 14:00:02.709307 ==
3232 14:00:02.712712 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 14:00:02.719122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 14:00:02.719249 ==
3235 14:00:02.729098 TX Vref=22, minBit 11, minWin=24, winSum=411
3236 14:00:02.732318 TX Vref=24, minBit 10, minWin=25, winSum=419
3237 14:00:02.735830 TX Vref=26, minBit 9, minWin=25, winSum=422
3238 14:00:02.739407 TX Vref=28, minBit 10, minWin=25, winSum=426
3239 14:00:02.742482 TX Vref=30, minBit 9, minWin=26, winSum=428
3240 14:00:02.748971 TX Vref=32, minBit 9, minWin=26, winSum=426
3241 14:00:02.752329 [TxChooseVref] Worse bit 9, Min win 26, Win sum 428, Final Vref 30
3242 14:00:02.752458
3243 14:00:02.756077 Final TX Range 1 Vref 30
3244 14:00:02.756183
3245 14:00:02.756278 ==
3246 14:00:02.759396 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 14:00:02.762599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 14:00:02.762718 ==
3249 14:00:02.765890
3250 14:00:02.766012
3251 14:00:02.766127 TX Vref Scan disable
3252 14:00:02.769339 == TX Byte 0 ==
3253 14:00:02.772643 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3254 14:00:02.775666 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3255 14:00:02.779041 == TX Byte 1 ==
3256 14:00:02.782647 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3257 14:00:02.786239 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3258 14:00:02.788995
3259 14:00:02.789102 [DATLAT]
3260 14:00:02.789195 Freq=1200, CH1 RK0
3261 14:00:02.789295
3262 14:00:02.792618 DATLAT Default: 0xd
3263 14:00:02.792720 0, 0xFFFF, sum = 0
3264 14:00:02.796181 1, 0xFFFF, sum = 0
3265 14:00:02.796294 2, 0xFFFF, sum = 0
3266 14:00:02.799324 3, 0xFFFF, sum = 0
3267 14:00:02.799425 4, 0xFFFF, sum = 0
3268 14:00:02.802581 5, 0xFFFF, sum = 0
3269 14:00:02.805972 6, 0xFFFF, sum = 0
3270 14:00:02.806076 7, 0xFFFF, sum = 0
3271 14:00:02.809199 8, 0xFFFF, sum = 0
3272 14:00:02.809301 9, 0xFFFF, sum = 0
3273 14:00:02.812486 10, 0xFFFF, sum = 0
3274 14:00:02.812588 11, 0xFFFF, sum = 0
3275 14:00:02.816104 12, 0x0, sum = 1
3276 14:00:02.816213 13, 0x0, sum = 2
3277 14:00:02.819166 14, 0x0, sum = 3
3278 14:00:02.819268 15, 0x0, sum = 4
3279 14:00:02.819366 best_step = 13
3280 14:00:02.819454
3281 14:00:02.823014 ==
3282 14:00:02.826287 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 14:00:02.829069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 14:00:02.829197 ==
3285 14:00:02.829314 RX Vref Scan: 1
3286 14:00:02.829426
3287 14:00:02.832806 Set Vref Range= 32 -> 127
3288 14:00:02.832932
3289 14:00:02.836243 RX Vref 32 -> 127, step: 1
3290 14:00:02.836368
3291 14:00:02.839706 RX Delay -5 -> 252, step: 4
3292 14:00:02.839833
3293 14:00:02.843253 Set Vref, RX VrefLevel [Byte0]: 32
3294 14:00:02.846047 [Byte1]: 32
3295 14:00:02.846170
3296 14:00:02.849718 Set Vref, RX VrefLevel [Byte0]: 33
3297 14:00:02.852608 [Byte1]: 33
3298 14:00:02.852735
3299 14:00:02.856496 Set Vref, RX VrefLevel [Byte0]: 34
3300 14:00:02.859323 [Byte1]: 34
3301 14:00:02.863191
3302 14:00:02.863275 Set Vref, RX VrefLevel [Byte0]: 35
3303 14:00:02.866299 [Byte1]: 35
3304 14:00:02.871235
3305 14:00:02.871317 Set Vref, RX VrefLevel [Byte0]: 36
3306 14:00:02.874683 [Byte1]: 36
3307 14:00:02.879366
3308 14:00:02.879449 Set Vref, RX VrefLevel [Byte0]: 37
3309 14:00:02.882238 [Byte1]: 37
3310 14:00:02.886855
3311 14:00:02.886938 Set Vref, RX VrefLevel [Byte0]: 38
3312 14:00:02.890287 [Byte1]: 38
3313 14:00:02.894715
3314 14:00:02.894838 Set Vref, RX VrefLevel [Byte0]: 39
3315 14:00:02.898102 [Byte1]: 39
3316 14:00:02.902721
3317 14:00:02.902798 Set Vref, RX VrefLevel [Byte0]: 40
3318 14:00:02.906151 [Byte1]: 40
3319 14:00:02.910168
3320 14:00:02.910271 Set Vref, RX VrefLevel [Byte0]: 41
3321 14:00:02.914005 [Byte1]: 41
3322 14:00:02.918455
3323 14:00:02.918566 Set Vref, RX VrefLevel [Byte0]: 42
3324 14:00:02.921522 [Byte1]: 42
3325 14:00:02.926306
3326 14:00:02.926408 Set Vref, RX VrefLevel [Byte0]: 43
3327 14:00:02.929317 [Byte1]: 43
3328 14:00:02.933813
3329 14:00:02.933886 Set Vref, RX VrefLevel [Byte0]: 44
3330 14:00:02.937259 [Byte1]: 44
3331 14:00:02.941509
3332 14:00:02.941587 Set Vref, RX VrefLevel [Byte0]: 45
3333 14:00:02.944813 [Byte1]: 45
3334 14:00:02.949515
3335 14:00:02.949621 Set Vref, RX VrefLevel [Byte0]: 46
3336 14:00:02.953086 [Byte1]: 46
3337 14:00:02.957606
3338 14:00:02.957717 Set Vref, RX VrefLevel [Byte0]: 47
3339 14:00:02.960574 [Byte1]: 47
3340 14:00:02.965514
3341 14:00:02.965614 Set Vref, RX VrefLevel [Byte0]: 48
3342 14:00:02.968597 [Byte1]: 48
3343 14:00:02.973254
3344 14:00:02.973336 Set Vref, RX VrefLevel [Byte0]: 49
3345 14:00:02.976679 [Byte1]: 49
3346 14:00:02.981157
3347 14:00:02.981267 Set Vref, RX VrefLevel [Byte0]: 50
3348 14:00:02.984106 [Byte1]: 50
3349 14:00:02.988677
3350 14:00:02.988765 Set Vref, RX VrefLevel [Byte0]: 51
3351 14:00:02.992073 [Byte1]: 51
3352 14:00:02.996747
3353 14:00:02.996865 Set Vref, RX VrefLevel [Byte0]: 52
3354 14:00:03.000120 [Byte1]: 52
3355 14:00:03.004870
3356 14:00:03.004984 Set Vref, RX VrefLevel [Byte0]: 53
3357 14:00:03.008145 [Byte1]: 53
3358 14:00:03.012315
3359 14:00:03.012420 Set Vref, RX VrefLevel [Byte0]: 54
3360 14:00:03.016010 [Byte1]: 54
3361 14:00:03.020077
3362 14:00:03.020179 Set Vref, RX VrefLevel [Byte0]: 55
3363 14:00:03.023648 [Byte1]: 55
3364 14:00:03.028640
3365 14:00:03.028724 Set Vref, RX VrefLevel [Byte0]: 56
3366 14:00:03.031392 [Byte1]: 56
3367 14:00:03.036163
3368 14:00:03.036246 Set Vref, RX VrefLevel [Byte0]: 57
3369 14:00:03.039151 [Byte1]: 57
3370 14:00:03.043950
3371 14:00:03.044033 Set Vref, RX VrefLevel [Byte0]: 58
3372 14:00:03.047321 [Byte1]: 58
3373 14:00:03.052264
3374 14:00:03.052373 Set Vref, RX VrefLevel [Byte0]: 59
3375 14:00:03.055009 [Byte1]: 59
3376 14:00:03.059305
3377 14:00:03.059410 Set Vref, RX VrefLevel [Byte0]: 60
3378 14:00:03.063041 [Byte1]: 60
3379 14:00:03.067751
3380 14:00:03.067829 Set Vref, RX VrefLevel [Byte0]: 61
3381 14:00:03.070609 [Byte1]: 61
3382 14:00:03.075370
3383 14:00:03.075477 Set Vref, RX VrefLevel [Byte0]: 62
3384 14:00:03.078338 [Byte1]: 62
3385 14:00:03.083113
3386 14:00:03.083200 Set Vref, RX VrefLevel [Byte0]: 63
3387 14:00:03.086232 [Byte1]: 63
3388 14:00:03.090938
3389 14:00:03.091069 Set Vref, RX VrefLevel [Byte0]: 64
3390 14:00:03.094304 [Byte1]: 64
3391 14:00:03.098814
3392 14:00:03.098920 Set Vref, RX VrefLevel [Byte0]: 65
3393 14:00:03.101970 [Byte1]: 65
3394 14:00:03.106848
3395 14:00:03.106931 Set Vref, RX VrefLevel [Byte0]: 66
3396 14:00:03.110266 [Byte1]: 66
3397 14:00:03.114776
3398 14:00:03.114859 Set Vref, RX VrefLevel [Byte0]: 67
3399 14:00:03.118341 [Byte1]: 67
3400 14:00:03.122492
3401 14:00:03.122575 Set Vref, RX VrefLevel [Byte0]: 68
3402 14:00:03.125533 [Byte1]: 68
3403 14:00:03.130540
3404 14:00:03.130624 Final RX Vref Byte 0 = 53 to rank0
3405 14:00:03.133537 Final RX Vref Byte 1 = 53 to rank0
3406 14:00:03.137004 Final RX Vref Byte 0 = 53 to rank1
3407 14:00:03.140280 Final RX Vref Byte 1 = 53 to rank1==
3408 14:00:03.144018 Dram Type= 6, Freq= 0, CH_1, rank 0
3409 14:00:03.147246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3410 14:00:03.150374 ==
3411 14:00:03.150458 DQS Delay:
3412 14:00:03.150524 DQS0 = 0, DQS1 = 0
3413 14:00:03.153718 DQM Delay:
3414 14:00:03.153800 DQM0 = 120, DQM1 = 117
3415 14:00:03.157193 DQ Delay:
3416 14:00:03.160565 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3417 14:00:03.164247 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3418 14:00:03.166819 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3419 14:00:03.170327 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3420 14:00:03.170418
3421 14:00:03.170513
3422 14:00:03.176942 [DQSOSCAuto] RK0, (LSB)MR18= 0x416, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3423 14:00:03.180690 CH1 RK0: MR19=404, MR18=416
3424 14:00:03.187402 CH1_RK0: MR19=0x404, MR18=0x416, DQSOSC=401, MR23=63, INC=40, DEC=27
3425 14:00:03.187507
3426 14:00:03.190179 ----->DramcWriteLeveling(PI) begin...
3427 14:00:03.190292 ==
3428 14:00:03.193626 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 14:00:03.197092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 14:00:03.197203 ==
3431 14:00:03.200160 Write leveling (Byte 0): 25 => 25
3432 14:00:03.203679 Write leveling (Byte 1): 28 => 28
3433 14:00:03.207214 DramcWriteLeveling(PI) end<-----
3434 14:00:03.207317
3435 14:00:03.207418 ==
3436 14:00:03.210683 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 14:00:03.213932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 14:00:03.217317 ==
3439 14:00:03.217421 [Gating] SW mode calibration
3440 14:00:03.223909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3441 14:00:03.230706 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3442 14:00:03.233960 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 14:00:03.240969 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 14:00:03.243844 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 14:00:03.247427 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 14:00:03.253878 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 14:00:03.257429 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3448 14:00:03.260802 0 15 24 | B1->B0 | 2626 3232 | 1 1 | (1 0) (1 1)
3449 14:00:03.264409 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)
3450 14:00:03.270773 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 14:00:03.274207 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 14:00:03.277741 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 14:00:03.284275 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 14:00:03.287289 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 14:00:03.290976 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3456 14:00:03.297458 1 0 24 | B1->B0 | 4444 2e2e | 0 0 | (1 1) (0 0)
3457 14:00:03.300780 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3458 14:00:03.304420 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 14:00:03.310586 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 14:00:03.314471 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 14:00:03.317381 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 14:00:03.324208 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 14:00:03.327291 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3464 14:00:03.330928 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3465 14:00:03.337516 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3466 14:00:03.340725 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 14:00:03.343949 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 14:00:03.350665 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 14:00:03.354409 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 14:00:03.357181 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 14:00:03.363904 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 14:00:03.367363 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 14:00:03.370729 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 14:00:03.377223 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 14:00:03.380761 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 14:00:03.384156 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 14:00:03.387144 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 14:00:03.393825 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 14:00:03.397494 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3480 14:00:03.400590 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3481 14:00:03.407545 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3482 14:00:03.410504 Total UI for P1: 0, mck2ui 16
3483 14:00:03.414020 best dqsien dly found for B1: ( 1, 3, 22)
3484 14:00:03.416781 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 14:00:03.420406 Total UI for P1: 0, mck2ui 16
3486 14:00:03.423544 best dqsien dly found for B0: ( 1, 3, 26)
3487 14:00:03.427388 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3488 14:00:03.430559 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3489 14:00:03.430670
3490 14:00:03.433931 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3491 14:00:03.436847 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3492 14:00:03.440397 [Gating] SW calibration Done
3493 14:00:03.440507 ==
3494 14:00:03.443883 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 14:00:03.450344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 14:00:03.450424 ==
3497 14:00:03.450497 RX Vref Scan: 0
3498 14:00:03.450593
3499 14:00:03.453526 RX Vref 0 -> 0, step: 1
3500 14:00:03.453606
3501 14:00:03.457119 RX Delay -40 -> 252, step: 8
3502 14:00:03.460517 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3503 14:00:03.463295 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3504 14:00:03.467135 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3505 14:00:03.470223 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3506 14:00:03.476725 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3507 14:00:03.480305 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3508 14:00:03.483643 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3509 14:00:03.486697 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3510 14:00:03.490251 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3511 14:00:03.496616 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3512 14:00:03.499713 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3513 14:00:03.503239 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3514 14:00:03.506670 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3515 14:00:03.513233 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3516 14:00:03.516807 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3517 14:00:03.519624 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3518 14:00:03.519709 ==
3519 14:00:03.523451 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 14:00:03.526830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 14:00:03.526916 ==
3522 14:00:03.529879 DQS Delay:
3523 14:00:03.529982 DQS0 = 0, DQS1 = 0
3524 14:00:03.536812 DQM Delay:
3525 14:00:03.536903 DQM0 = 120, DQM1 = 118
3526 14:00:03.536968 DQ Delay:
3527 14:00:03.537030 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3528 14:00:03.542919 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3529 14:00:03.546788 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3530 14:00:03.549906 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3531 14:00:03.550009
3532 14:00:03.550102
3533 14:00:03.550203 ==
3534 14:00:03.553286 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 14:00:03.556340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 14:00:03.556417 ==
3537 14:00:03.556480
3538 14:00:03.556546
3539 14:00:03.559717 TX Vref Scan disable
3540 14:00:03.563176 == TX Byte 0 ==
3541 14:00:03.566229 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3542 14:00:03.569936 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3543 14:00:03.573274 == TX Byte 1 ==
3544 14:00:03.576401 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3545 14:00:03.579966 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3546 14:00:03.580073 ==
3547 14:00:03.582965 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 14:00:03.586338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 14:00:03.586444 ==
3550 14:00:03.599442 TX Vref=22, minBit 10, minWin=25, winSum=420
3551 14:00:03.603124 TX Vref=24, minBit 2, minWin=26, winSum=424
3552 14:00:03.605996 TX Vref=26, minBit 2, minWin=26, winSum=426
3553 14:00:03.609605 TX Vref=28, minBit 8, minWin=26, winSum=434
3554 14:00:03.612444 TX Vref=30, minBit 9, minWin=26, winSum=435
3555 14:00:03.619596 TX Vref=32, minBit 1, minWin=26, winSum=432
3556 14:00:03.622497 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3557 14:00:03.622607
3558 14:00:03.626127 Final TX Range 1 Vref 30
3559 14:00:03.626231
3560 14:00:03.626327 ==
3561 14:00:03.629151 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 14:00:03.632731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 14:00:03.635920 ==
3564 14:00:03.636023
3565 14:00:03.636125
3566 14:00:03.636218 TX Vref Scan disable
3567 14:00:03.639162 == TX Byte 0 ==
3568 14:00:03.642590 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3569 14:00:03.645965 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3570 14:00:03.649379 == TX Byte 1 ==
3571 14:00:03.652556 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3572 14:00:03.656089 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3573 14:00:03.659514
3574 14:00:03.659614 [DATLAT]
3575 14:00:03.659697 Freq=1200, CH1 RK1
3576 14:00:03.659760
3577 14:00:03.662655 DATLAT Default: 0xd
3578 14:00:03.662753 0, 0xFFFF, sum = 0
3579 14:00:03.665588 1, 0xFFFF, sum = 0
3580 14:00:03.665695 2, 0xFFFF, sum = 0
3581 14:00:03.669075 3, 0xFFFF, sum = 0
3582 14:00:03.672251 4, 0xFFFF, sum = 0
3583 14:00:03.672328 5, 0xFFFF, sum = 0
3584 14:00:03.675714 6, 0xFFFF, sum = 0
3585 14:00:03.675794 7, 0xFFFF, sum = 0
3586 14:00:03.679301 8, 0xFFFF, sum = 0
3587 14:00:03.679423 9, 0xFFFF, sum = 0
3588 14:00:03.682196 10, 0xFFFF, sum = 0
3589 14:00:03.682315 11, 0xFFFF, sum = 0
3590 14:00:03.685530 12, 0x0, sum = 1
3591 14:00:03.685643 13, 0x0, sum = 2
3592 14:00:03.688939 14, 0x0, sum = 3
3593 14:00:03.689052 15, 0x0, sum = 4
3594 14:00:03.689149 best_step = 13
3595 14:00:03.692466
3596 14:00:03.692573 ==
3597 14:00:03.696004 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 14:00:03.699126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 14:00:03.699237 ==
3600 14:00:03.699344 RX Vref Scan: 0
3601 14:00:03.699434
3602 14:00:03.702845 RX Vref 0 -> 0, step: 1
3603 14:00:03.702952
3604 14:00:03.705882 RX Delay -5 -> 252, step: 4
3605 14:00:03.708938 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3606 14:00:03.716073 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3607 14:00:03.719028 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3608 14:00:03.722488 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3609 14:00:03.725469 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3610 14:00:03.728930 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3611 14:00:03.735480 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3612 14:00:03.739036 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3613 14:00:03.742223 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3614 14:00:03.745821 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3615 14:00:03.749146 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3616 14:00:03.755764 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3617 14:00:03.758820 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3618 14:00:03.762128 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3619 14:00:03.765516 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3620 14:00:03.768565 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3621 14:00:03.772214 ==
3622 14:00:03.775335 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 14:00:03.778687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 14:00:03.778792 ==
3625 14:00:03.778898 DQS Delay:
3626 14:00:03.781908 DQS0 = 0, DQS1 = 0
3627 14:00:03.782021 DQM Delay:
3628 14:00:03.785285 DQM0 = 120, DQM1 = 118
3629 14:00:03.785373 DQ Delay:
3630 14:00:03.788655 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3631 14:00:03.792052 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3632 14:00:03.795774 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3633 14:00:03.798743 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3634 14:00:03.798839
3635 14:00:03.798942
3636 14:00:03.808713 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3637 14:00:03.812006 CH1 RK1: MR19=403, MR18=13F0
3638 14:00:03.815149 CH1_RK1: MR19=0x403, MR18=0x13F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3639 14:00:03.818354 [RxdqsGatingPostProcess] freq 1200
3640 14:00:03.825226 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3641 14:00:03.828445 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 14:00:03.831704 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 14:00:03.835339 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 14:00:03.838365 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 14:00:03.841975 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 14:00:03.844949 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 14:00:03.848704 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 14:00:03.851544 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 14:00:03.855100 Pre-setting of DQS Precalculation
3650 14:00:03.858594 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3651 14:00:03.864990 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3652 14:00:03.871721 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3653 14:00:03.871817
3654 14:00:03.871887
3655 14:00:03.875275 [Calibration Summary] 2400 Mbps
3656 14:00:03.878182 CH 0, Rank 0
3657 14:00:03.878289 SW Impedance : PASS
3658 14:00:03.881595 DUTY Scan : NO K
3659 14:00:03.885109 ZQ Calibration : PASS
3660 14:00:03.885189 Jitter Meter : NO K
3661 14:00:03.888286 CBT Training : PASS
3662 14:00:03.891463 Write leveling : PASS
3663 14:00:03.891568 RX DQS gating : PASS
3664 14:00:03.894936 RX DQ/DQS(RDDQC) : PASS
3665 14:00:03.898013 TX DQ/DQS : PASS
3666 14:00:03.898126 RX DATLAT : PASS
3667 14:00:03.901873 RX DQ/DQS(Engine): PASS
3668 14:00:03.901975 TX OE : NO K
3669 14:00:03.904775 All Pass.
3670 14:00:03.904885
3671 14:00:03.904993 CH 0, Rank 1
3672 14:00:03.908290 SW Impedance : PASS
3673 14:00:03.908402 DUTY Scan : NO K
3674 14:00:03.911767 ZQ Calibration : PASS
3675 14:00:03.915274 Jitter Meter : NO K
3676 14:00:03.915376 CBT Training : PASS
3677 14:00:03.918297 Write leveling : PASS
3678 14:00:03.921700 RX DQS gating : PASS
3679 14:00:03.921811 RX DQ/DQS(RDDQC) : PASS
3680 14:00:03.924816 TX DQ/DQS : PASS
3681 14:00:03.928301 RX DATLAT : PASS
3682 14:00:03.928381 RX DQ/DQS(Engine): PASS
3683 14:00:03.931610 TX OE : NO K
3684 14:00:03.931712 All Pass.
3685 14:00:03.931805
3686 14:00:03.934671 CH 1, Rank 0
3687 14:00:03.934781 SW Impedance : PASS
3688 14:00:03.938024 DUTY Scan : NO K
3689 14:00:03.941911 ZQ Calibration : PASS
3690 14:00:03.942015 Jitter Meter : NO K
3691 14:00:03.944731 CBT Training : PASS
3692 14:00:03.947918 Write leveling : PASS
3693 14:00:03.948020 RX DQS gating : PASS
3694 14:00:03.951617 RX DQ/DQS(RDDQC) : PASS
3695 14:00:03.951711 TX DQ/DQS : PASS
3696 14:00:03.954988 RX DATLAT : PASS
3697 14:00:03.958157 RX DQ/DQS(Engine): PASS
3698 14:00:03.958245 TX OE : NO K
3699 14:00:03.961800 All Pass.
3700 14:00:03.961877
3701 14:00:03.961940 CH 1, Rank 1
3702 14:00:03.964699 SW Impedance : PASS
3703 14:00:03.964802 DUTY Scan : NO K
3704 14:00:03.967933 ZQ Calibration : PASS
3705 14:00:03.971568 Jitter Meter : NO K
3706 14:00:03.971673 CBT Training : PASS
3707 14:00:03.974576 Write leveling : PASS
3708 14:00:03.977930 RX DQS gating : PASS
3709 14:00:03.978008 RX DQ/DQS(RDDQC) : PASS
3710 14:00:03.981263 TX DQ/DQS : PASS
3711 14:00:03.984548 RX DATLAT : PASS
3712 14:00:03.984659 RX DQ/DQS(Engine): PASS
3713 14:00:03.987879 TX OE : NO K
3714 14:00:03.987985 All Pass.
3715 14:00:03.988077
3716 14:00:03.991574 DramC Write-DBI off
3717 14:00:03.994609 PER_BANK_REFRESH: Hybrid Mode
3718 14:00:03.994687 TX_TRACKING: ON
3719 14:00:04.004639 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3720 14:00:04.008194 [FAST_K] Save calibration result to emmc
3721 14:00:04.011110 dramc_set_vcore_voltage set vcore to 650000
3722 14:00:04.014524 Read voltage for 600, 5
3723 14:00:04.014637 Vio18 = 0
3724 14:00:04.014724 Vcore = 650000
3725 14:00:04.018470 Vdram = 0
3726 14:00:04.018577 Vddq = 0
3727 14:00:04.018680 Vmddr = 0
3728 14:00:04.024704 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3729 14:00:04.027938 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3730 14:00:04.031169 MEM_TYPE=3, freq_sel=19
3731 14:00:04.034567 sv_algorithm_assistance_LP4_1600
3732 14:00:04.037994 ============ PULL DRAM RESETB DOWN ============
3733 14:00:04.040905 ========== PULL DRAM RESETB DOWN end =========
3734 14:00:04.047530 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3735 14:00:04.050988 ===================================
3736 14:00:04.051095 LPDDR4 DRAM CONFIGURATION
3737 14:00:04.054478 ===================================
3738 14:00:04.057514 EX_ROW_EN[0] = 0x0
3739 14:00:04.061256 EX_ROW_EN[1] = 0x0
3740 14:00:04.061363 LP4Y_EN = 0x0
3741 14:00:04.064485 WORK_FSP = 0x0
3742 14:00:04.064590 WL = 0x2
3743 14:00:04.067962 RL = 0x2
3744 14:00:04.068073 BL = 0x2
3745 14:00:04.070990 RPST = 0x0
3746 14:00:04.071095 RD_PRE = 0x0
3747 14:00:04.074631 WR_PRE = 0x1
3748 14:00:04.074734 WR_PST = 0x0
3749 14:00:04.077930 DBI_WR = 0x0
3750 14:00:04.078032 DBI_RD = 0x0
3751 14:00:04.081108 OTF = 0x1
3752 14:00:04.084205 ===================================
3753 14:00:04.087500 ===================================
3754 14:00:04.087603 ANA top config
3755 14:00:04.090908 ===================================
3756 14:00:04.094126 DLL_ASYNC_EN = 0
3757 14:00:04.097958 ALL_SLAVE_EN = 1
3758 14:00:04.098062 NEW_RANK_MODE = 1
3759 14:00:04.100811 DLL_IDLE_MODE = 1
3760 14:00:04.104538 LP45_APHY_COMB_EN = 1
3761 14:00:04.107970 TX_ODT_DIS = 1
3762 14:00:04.111107 NEW_8X_MODE = 1
3763 14:00:04.114691 ===================================
3764 14:00:04.117702 ===================================
3765 14:00:04.117807 data_rate = 1200
3766 14:00:04.121113 CKR = 1
3767 14:00:04.124438 DQ_P2S_RATIO = 8
3768 14:00:04.127745 ===================================
3769 14:00:04.130987 CA_P2S_RATIO = 8
3770 14:00:04.134459 DQ_CA_OPEN = 0
3771 14:00:04.137628 DQ_SEMI_OPEN = 0
3772 14:00:04.137731 CA_SEMI_OPEN = 0
3773 14:00:04.141000 CA_FULL_RATE = 0
3774 14:00:04.143945 DQ_CKDIV4_EN = 1
3775 14:00:04.147483 CA_CKDIV4_EN = 1
3776 14:00:04.150691 CA_PREDIV_EN = 0
3777 14:00:04.153961 PH8_DLY = 0
3778 14:00:04.154064 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3779 14:00:04.157595 DQ_AAMCK_DIV = 4
3780 14:00:04.161105 CA_AAMCK_DIV = 4
3781 14:00:04.163978 CA_ADMCK_DIV = 4
3782 14:00:04.167264 DQ_TRACK_CA_EN = 0
3783 14:00:04.170803 CA_PICK = 600
3784 14:00:04.174267 CA_MCKIO = 600
3785 14:00:04.174374 MCKIO_SEMI = 0
3786 14:00:04.177783 PLL_FREQ = 2288
3787 14:00:04.180801 DQ_UI_PI_RATIO = 32
3788 14:00:04.183928 CA_UI_PI_RATIO = 0
3789 14:00:04.187256 ===================================
3790 14:00:04.190702 ===================================
3791 14:00:04.194009 memory_type:LPDDR4
3792 14:00:04.194116 GP_NUM : 10
3793 14:00:04.197517 SRAM_EN : 1
3794 14:00:04.200545 MD32_EN : 0
3795 14:00:04.200649 ===================================
3796 14:00:04.203917 [ANA_INIT] >>>>>>>>>>>>>>
3797 14:00:04.207167 <<<<<< [CONFIGURE PHASE]: ANA_TX
3798 14:00:04.210635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3799 14:00:04.213770 ===================================
3800 14:00:04.217353 data_rate = 1200,PCW = 0X5800
3801 14:00:04.220649 ===================================
3802 14:00:04.224178 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3803 14:00:04.230332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 14:00:04.233903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 14:00:04.240354 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3806 14:00:04.243854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3807 14:00:04.247181 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3808 14:00:04.247286 [ANA_INIT] flow start
3809 14:00:04.250668 [ANA_INIT] PLL >>>>>>>>
3810 14:00:04.254011 [ANA_INIT] PLL <<<<<<<<
3811 14:00:04.254116 [ANA_INIT] MIDPI >>>>>>>>
3812 14:00:04.257318 [ANA_INIT] MIDPI <<<<<<<<
3813 14:00:04.260641 [ANA_INIT] DLL >>>>>>>>
3814 14:00:04.260749 [ANA_INIT] flow end
3815 14:00:04.267067 ============ LP4 DIFF to SE enter ============
3816 14:00:04.270435 ============ LP4 DIFF to SE exit ============
3817 14:00:04.273987 [ANA_INIT] <<<<<<<<<<<<<
3818 14:00:04.276869 [Flow] Enable top DCM control >>>>>
3819 14:00:04.280150 [Flow] Enable top DCM control <<<<<
3820 14:00:04.280264 Enable DLL master slave shuffle
3821 14:00:04.286981 ==============================================================
3822 14:00:04.289927 Gating Mode config
3823 14:00:04.293520 ==============================================================
3824 14:00:04.297257 Config description:
3825 14:00:04.307035 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3826 14:00:04.313341 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3827 14:00:04.316989 SELPH_MODE 0: By rank 1: By Phase
3828 14:00:04.323210 ==============================================================
3829 14:00:04.326389 GAT_TRACK_EN = 1
3830 14:00:04.330021 RX_GATING_MODE = 2
3831 14:00:04.333491 RX_GATING_TRACK_MODE = 2
3832 14:00:04.336511 SELPH_MODE = 1
3833 14:00:04.336617 PICG_EARLY_EN = 1
3834 14:00:04.340081 VALID_LAT_VALUE = 1
3835 14:00:04.346678 ==============================================================
3836 14:00:04.349664 Enter into Gating configuration >>>>
3837 14:00:04.353510 Exit from Gating configuration <<<<
3838 14:00:04.356512 Enter into DVFS_PRE_config >>>>>
3839 14:00:04.366911 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3840 14:00:04.370174 Exit from DVFS_PRE_config <<<<<
3841 14:00:04.373913 Enter into PICG configuration >>>>
3842 14:00:04.377145 Exit from PICG configuration <<<<
3843 14:00:04.380013 [RX_INPUT] configuration >>>>>
3844 14:00:04.383556 [RX_INPUT] configuration <<<<<
3845 14:00:04.386456 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3846 14:00:04.393171 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3847 14:00:04.399768 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 14:00:04.406706 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 14:00:04.413135 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 14:00:04.416574 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 14:00:04.423109 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3852 14:00:04.426831 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3853 14:00:04.429649 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3854 14:00:04.433289 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3855 14:00:04.439610 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3856 14:00:04.443225 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 14:00:04.446108 ===================================
3858 14:00:04.449442 LPDDR4 DRAM CONFIGURATION
3859 14:00:04.452855 ===================================
3860 14:00:04.452963 EX_ROW_EN[0] = 0x0
3861 14:00:04.456413 EX_ROW_EN[1] = 0x0
3862 14:00:04.456492 LP4Y_EN = 0x0
3863 14:00:04.459399 WORK_FSP = 0x0
3864 14:00:04.459501 WL = 0x2
3865 14:00:04.463002 RL = 0x2
3866 14:00:04.463077 BL = 0x2
3867 14:00:04.466582 RPST = 0x0
3868 14:00:04.466685 RD_PRE = 0x0
3869 14:00:04.469603 WR_PRE = 0x1
3870 14:00:04.469705 WR_PST = 0x0
3871 14:00:04.473005 DBI_WR = 0x0
3872 14:00:04.473110 DBI_RD = 0x0
3873 14:00:04.476016 OTF = 0x1
3874 14:00:04.479597 ===================================
3875 14:00:04.483147 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3876 14:00:04.486635 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3877 14:00:04.493104 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 14:00:04.496142 ===================================
3879 14:00:04.499699 LPDDR4 DRAM CONFIGURATION
3880 14:00:04.499773 ===================================
3881 14:00:04.502741 EX_ROW_EN[0] = 0x10
3882 14:00:04.506482 EX_ROW_EN[1] = 0x0
3883 14:00:04.506581 LP4Y_EN = 0x0
3884 14:00:04.509596 WORK_FSP = 0x0
3885 14:00:04.509695 WL = 0x2
3886 14:00:04.512676 RL = 0x2
3887 14:00:04.512747 BL = 0x2
3888 14:00:04.516248 RPST = 0x0
3889 14:00:04.516349 RD_PRE = 0x0
3890 14:00:04.519301 WR_PRE = 0x1
3891 14:00:04.519405 WR_PST = 0x0
3892 14:00:04.522788 DBI_WR = 0x0
3893 14:00:04.522889 DBI_RD = 0x0
3894 14:00:04.526193 OTF = 0x1
3895 14:00:04.529368 ===================================
3896 14:00:04.536165 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3897 14:00:04.539513 nWR fixed to 30
3898 14:00:04.542961 [ModeRegInit_LP4] CH0 RK0
3899 14:00:04.543066 [ModeRegInit_LP4] CH0 RK1
3900 14:00:04.545938 [ModeRegInit_LP4] CH1 RK0
3901 14:00:04.549533 [ModeRegInit_LP4] CH1 RK1
3902 14:00:04.549617 match AC timing 17
3903 14:00:04.556158 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3904 14:00:04.559413 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3905 14:00:04.562867 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3906 14:00:04.569444 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3907 14:00:04.572960 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3908 14:00:04.573048 ==
3909 14:00:04.575911 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 14:00:04.579276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 14:00:04.579390 ==
3912 14:00:04.585924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 14:00:04.592839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3914 14:00:04.595805 [CA 0] Center 35 (5~66) winsize 62
3915 14:00:04.599558 [CA 1] Center 35 (5~66) winsize 62
3916 14:00:04.602680 [CA 2] Center 33 (3~64) winsize 62
3917 14:00:04.606048 [CA 3] Center 33 (2~64) winsize 63
3918 14:00:04.609579 [CA 4] Center 33 (2~64) winsize 63
3919 14:00:04.612631 [CA 5] Center 32 (2~63) winsize 62
3920 14:00:04.612735
3921 14:00:04.616324 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3922 14:00:04.616436
3923 14:00:04.619031 [CATrainingPosCal] consider 1 rank data
3924 14:00:04.622847 u2DelayCellTimex100 = 270/100 ps
3925 14:00:04.625725 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3926 14:00:04.629305 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3927 14:00:04.632963 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3928 14:00:04.636249 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3929 14:00:04.639297 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3930 14:00:04.642631 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3931 14:00:04.642736
3932 14:00:04.649129 CA PerBit enable=1, Macro0, CA PI delay=32
3933 14:00:04.649259
3934 14:00:04.649366 [CBTSetCACLKResult] CA Dly = 32
3935 14:00:04.652307 CS Dly: 5 (0~36)
3936 14:00:04.652429 ==
3937 14:00:04.655801 Dram Type= 6, Freq= 0, CH_0, rank 1
3938 14:00:04.659177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 14:00:04.659308 ==
3940 14:00:04.665958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 14:00:04.672120 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3942 14:00:04.675413 [CA 0] Center 35 (5~66) winsize 62
3943 14:00:04.678860 [CA 1] Center 35 (5~66) winsize 62
3944 14:00:04.682282 [CA 2] Center 34 (3~65) winsize 63
3945 14:00:04.685384 [CA 3] Center 33 (3~64) winsize 62
3946 14:00:04.688861 [CA 4] Center 32 (2~63) winsize 62
3947 14:00:04.692331 [CA 5] Center 32 (2~63) winsize 62
3948 14:00:04.692428
3949 14:00:04.695384 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3950 14:00:04.695458
3951 14:00:04.698607 [CATrainingPosCal] consider 2 rank data
3952 14:00:04.702031 u2DelayCellTimex100 = 270/100 ps
3953 14:00:04.705666 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3954 14:00:04.708720 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3955 14:00:04.711802 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3956 14:00:04.715425 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3957 14:00:04.718541 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3958 14:00:04.725041 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3959 14:00:04.725148
3960 14:00:04.728640 CA PerBit enable=1, Macro0, CA PI delay=32
3961 14:00:04.728745
3962 14:00:04.732457 [CBTSetCACLKResult] CA Dly = 32
3963 14:00:04.732562 CS Dly: 5 (0~36)
3964 14:00:04.732657
3965 14:00:04.735329 ----->DramcWriteLeveling(PI) begin...
3966 14:00:04.735434 ==
3967 14:00:04.739042 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 14:00:04.742167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 14:00:04.745146 ==
3970 14:00:04.745251 Write leveling (Byte 0): 36 => 36
3971 14:00:04.748642 Write leveling (Byte 1): 31 => 31
3972 14:00:04.752158 DramcWriteLeveling(PI) end<-----
3973 14:00:04.752259
3974 14:00:04.752356 ==
3975 14:00:04.755093 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 14:00:04.762075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 14:00:04.762187 ==
3978 14:00:04.765053 [Gating] SW mode calibration
3979 14:00:04.771917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3980 14:00:04.775415 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3981 14:00:04.781954 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 14:00:04.785306 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 14:00:04.788516 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 14:00:04.795175 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
3985 14:00:04.798509 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
3986 14:00:04.801905 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 14:00:04.805103 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 14:00:04.811593 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 14:00:04.815166 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 14:00:04.818085 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 14:00:04.824741 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3992 14:00:04.828657 0 10 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3993 14:00:04.831441 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3994 14:00:04.838281 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 14:00:04.841694 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 14:00:04.844822 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 14:00:04.851603 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 14:00:04.854539 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 14:00:04.857828 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 14:00:04.864550 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4001 14:00:04.868288 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4002 14:00:04.871236 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 14:00:04.878216 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 14:00:04.881448 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 14:00:04.884533 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 14:00:04.890831 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 14:00:04.894587 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 14:00:04.897536 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 14:00:04.904602 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 14:00:04.907817 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 14:00:04.911081 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 14:00:04.917707 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 14:00:04.921051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 14:00:04.924048 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 14:00:04.931172 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 14:00:04.934406 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4017 14:00:04.937321 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4018 14:00:04.940950 Total UI for P1: 0, mck2ui 16
4019 14:00:04.944488 best dqsien dly found for B0: ( 0, 13, 12)
4020 14:00:04.951040 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 14:00:04.951149 Total UI for P1: 0, mck2ui 16
4022 14:00:04.954154 best dqsien dly found for B1: ( 0, 13, 16)
4023 14:00:04.960677 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4024 14:00:04.964395 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4025 14:00:04.964473
4026 14:00:04.967288 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4027 14:00:04.971081 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4028 14:00:04.973936 [Gating] SW calibration Done
4029 14:00:04.974059 ==
4030 14:00:04.977665 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 14:00:04.980607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 14:00:04.980750 ==
4033 14:00:04.984469 RX Vref Scan: 0
4034 14:00:04.984609
4035 14:00:04.984750 RX Vref 0 -> 0, step: 1
4036 14:00:04.984892
4037 14:00:04.987996 RX Delay -230 -> 252, step: 16
4038 14:00:04.990797 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4039 14:00:04.997455 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4040 14:00:05.001024 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4041 14:00:05.003937 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4042 14:00:05.007536 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4043 14:00:05.013888 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4044 14:00:05.017382 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4045 14:00:05.020973 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4046 14:00:05.023719 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4047 14:00:05.027001 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4048 14:00:05.033576 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4049 14:00:05.036997 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4050 14:00:05.040774 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4051 14:00:05.043566 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4052 14:00:05.050745 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4053 14:00:05.053841 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4054 14:00:05.053926 ==
4055 14:00:05.057552 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 14:00:05.060569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 14:00:05.060679 ==
4058 14:00:05.064006 DQS Delay:
4059 14:00:05.064111 DQS0 = 0, DQS1 = 0
4060 14:00:05.064183 DQM Delay:
4061 14:00:05.067389 DQM0 = 51, DQM1 = 45
4062 14:00:05.067523 DQ Delay:
4063 14:00:05.070390 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4064 14:00:05.073842 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4065 14:00:05.076815 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4066 14:00:05.080307 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =49
4067 14:00:05.080395
4068 14:00:05.080483
4069 14:00:05.080565 ==
4070 14:00:05.084054 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 14:00:05.090458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 14:00:05.090544 ==
4073 14:00:05.090631
4074 14:00:05.090713
4075 14:00:05.090792 TX Vref Scan disable
4076 14:00:05.093967 == TX Byte 0 ==
4077 14:00:05.097575 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4078 14:00:05.103886 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4079 14:00:05.103973 == TX Byte 1 ==
4080 14:00:05.107366 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4081 14:00:05.114059 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4082 14:00:05.114146 ==
4083 14:00:05.117062 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 14:00:05.120892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 14:00:05.120978 ==
4086 14:00:05.121065
4087 14:00:05.121146
4088 14:00:05.123628 TX Vref Scan disable
4089 14:00:05.127159 == TX Byte 0 ==
4090 14:00:05.130380 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4091 14:00:05.133637 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4092 14:00:05.137114 == TX Byte 1 ==
4093 14:00:05.140280 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4094 14:00:05.143542 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4095 14:00:05.143658
4096 14:00:05.143752 [DATLAT]
4097 14:00:05.147140 Freq=600, CH0 RK0
4098 14:00:05.147246
4099 14:00:05.147349 DATLAT Default: 0x9
4100 14:00:05.150212 0, 0xFFFF, sum = 0
4101 14:00:05.153817 1, 0xFFFF, sum = 0
4102 14:00:05.153903 2, 0xFFFF, sum = 0
4103 14:00:05.156862 3, 0xFFFF, sum = 0
4104 14:00:05.156945 4, 0xFFFF, sum = 0
4105 14:00:05.160568 5, 0xFFFF, sum = 0
4106 14:00:05.160648 6, 0xFFFF, sum = 0
4107 14:00:05.163963 7, 0xFFFF, sum = 0
4108 14:00:05.164076 8, 0x0, sum = 1
4109 14:00:05.164183 9, 0x0, sum = 2
4110 14:00:05.166999 10, 0x0, sum = 3
4111 14:00:05.167103 11, 0x0, sum = 4
4112 14:00:05.170763 best_step = 9
4113 14:00:05.170867
4114 14:00:05.170946 ==
4115 14:00:05.173461 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 14:00:05.177219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 14:00:05.177332 ==
4118 14:00:05.180230 RX Vref Scan: 1
4119 14:00:05.180331
4120 14:00:05.180421 RX Vref 0 -> 0, step: 1
4121 14:00:05.180515
4122 14:00:05.183883 RX Delay -163 -> 252, step: 8
4123 14:00:05.183953
4124 14:00:05.186858 Set Vref, RX VrefLevel [Byte0]: 54
4125 14:00:05.189971 [Byte1]: 52
4126 14:00:05.194212
4127 14:00:05.194287 Final RX Vref Byte 0 = 54 to rank0
4128 14:00:05.197945 Final RX Vref Byte 1 = 52 to rank0
4129 14:00:05.201154 Final RX Vref Byte 0 = 54 to rank1
4130 14:00:05.204645 Final RX Vref Byte 1 = 52 to rank1==
4131 14:00:05.208136 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 14:00:05.214309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 14:00:05.214388 ==
4134 14:00:05.214452 DQS Delay:
4135 14:00:05.214517 DQS0 = 0, DQS1 = 0
4136 14:00:05.217617 DQM Delay:
4137 14:00:05.217709 DQM0 = 53, DQM1 = 45
4138 14:00:05.221090 DQ Delay:
4139 14:00:05.224042 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4140 14:00:05.224120 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =56
4141 14:00:05.227674 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4142 14:00:05.231199 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4143 14:00:05.234485
4144 14:00:05.234557
4145 14:00:05.241379 [DQSOSCAuto] RK0, (LSB)MR18= 0x7063, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4146 14:00:05.244662 CH0 RK0: MR19=808, MR18=7063
4147 14:00:05.251344 CH0_RK0: MR19=0x808, MR18=0x7063, DQSOSC=388, MR23=63, INC=174, DEC=116
4148 14:00:05.251429
4149 14:00:05.254593 ----->DramcWriteLeveling(PI) begin...
4150 14:00:05.254678 ==
4151 14:00:05.257815 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 14:00:05.260918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 14:00:05.260999 ==
4154 14:00:05.264833 Write leveling (Byte 0): 33 => 33
4155 14:00:05.267605 Write leveling (Byte 1): 30 => 30
4156 14:00:05.271394 DramcWriteLeveling(PI) end<-----
4157 14:00:05.271472
4158 14:00:05.271535 ==
4159 14:00:05.274246 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 14:00:05.277977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 14:00:05.278100 ==
4162 14:00:05.281428 [Gating] SW mode calibration
4163 14:00:05.287387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4164 14:00:05.294146 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4165 14:00:05.297759 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 14:00:05.300813 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 14:00:05.307890 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 14:00:05.310642 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
4169 14:00:05.314126 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
4170 14:00:05.320681 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 14:00:05.324489 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 14:00:05.327507 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 14:00:05.333959 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 14:00:05.337550 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 14:00:05.340645 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 14:00:05.347220 0 10 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
4177 14:00:05.350578 0 10 16 | B1->B0 | 3e3e 3e3e | 1 0 | (0 0) (0 0)
4178 14:00:05.353951 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 14:00:05.360580 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 14:00:05.364010 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 14:00:05.367185 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 14:00:05.373585 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 14:00:05.377075 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 14:00:05.380502 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 14:00:05.387138 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4186 14:00:05.390055 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 14:00:05.393745 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 14:00:05.399957 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 14:00:05.403650 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 14:00:05.406819 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 14:00:05.413778 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 14:00:05.416550 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 14:00:05.419982 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 14:00:05.426565 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 14:00:05.429992 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 14:00:05.433653 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 14:00:05.440224 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 14:00:05.443260 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 14:00:05.446445 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 14:00:05.452959 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 14:00:05.456727 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 14:00:05.459852 Total UI for P1: 0, mck2ui 16
4203 14:00:05.463359 best dqsien dly found for B0: ( 0, 13, 14)
4204 14:00:05.466972 Total UI for P1: 0, mck2ui 16
4205 14:00:05.469965 best dqsien dly found for B1: ( 0, 13, 14)
4206 14:00:05.473368 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4207 14:00:05.476700 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4208 14:00:05.476783
4209 14:00:05.479803 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4210 14:00:05.483133 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4211 14:00:05.486584 [Gating] SW calibration Done
4212 14:00:05.486693 ==
4213 14:00:05.489827 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 14:00:05.492718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 14:00:05.492822 ==
4216 14:00:05.496338 RX Vref Scan: 0
4217 14:00:05.496416
4218 14:00:05.499853 RX Vref 0 -> 0, step: 1
4219 14:00:05.499929
4220 14:00:05.502882 RX Delay -230 -> 252, step: 16
4221 14:00:05.506360 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4222 14:00:05.509521 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4223 14:00:05.512603 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4224 14:00:05.516389 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4225 14:00:05.522596 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4226 14:00:05.526104 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4227 14:00:05.529477 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4228 14:00:05.532530 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4229 14:00:05.539105 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4230 14:00:05.542879 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4231 14:00:05.546017 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4232 14:00:05.549448 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4233 14:00:05.555792 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4234 14:00:05.559174 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4235 14:00:05.562555 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4236 14:00:05.566089 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4237 14:00:05.566192 ==
4238 14:00:05.569502 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 14:00:05.576129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 14:00:05.576221 ==
4241 14:00:05.576311 DQS Delay:
4242 14:00:05.576397 DQS0 = 0, DQS1 = 0
4243 14:00:05.579277 DQM Delay:
4244 14:00:05.579359 DQM0 = 50, DQM1 = 42
4245 14:00:05.582441 DQ Delay:
4246 14:00:05.585819 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4247 14:00:05.589067 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4248 14:00:05.592471 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4249 14:00:05.595855 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4250 14:00:05.595946
4251 14:00:05.596031
4252 14:00:05.596108 ==
4253 14:00:05.599144 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 14:00:05.602944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 14:00:05.603036 ==
4256 14:00:05.603119
4257 14:00:05.603204
4258 14:00:05.606231 TX Vref Scan disable
4259 14:00:05.606309 == TX Byte 0 ==
4260 14:00:05.612445 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4261 14:00:05.616171 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4262 14:00:05.616255 == TX Byte 1 ==
4263 14:00:05.622478 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4264 14:00:05.625959 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4265 14:00:05.626046 ==
4266 14:00:05.629023 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 14:00:05.632671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 14:00:05.632761 ==
4269 14:00:05.632852
4270 14:00:05.632931
4271 14:00:05.635471 TX Vref Scan disable
4272 14:00:05.639285 == TX Byte 0 ==
4273 14:00:05.642458 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4274 14:00:05.649016 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4275 14:00:05.649102 == TX Byte 1 ==
4276 14:00:05.652218 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4277 14:00:05.658899 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4278 14:00:05.658983
4279 14:00:05.659073 [DATLAT]
4280 14:00:05.659160 Freq=600, CH0 RK1
4281 14:00:05.659237
4282 14:00:05.662416 DATLAT Default: 0x9
4283 14:00:05.662504 0, 0xFFFF, sum = 0
4284 14:00:05.665945 1, 0xFFFF, sum = 0
4285 14:00:05.666026 2, 0xFFFF, sum = 0
4286 14:00:05.668854 3, 0xFFFF, sum = 0
4287 14:00:05.668934 4, 0xFFFF, sum = 0
4288 14:00:05.672305 5, 0xFFFF, sum = 0
4289 14:00:05.675518 6, 0xFFFF, sum = 0
4290 14:00:05.675629 7, 0xFFFF, sum = 0
4291 14:00:05.679259 8, 0x0, sum = 1
4292 14:00:05.679348 9, 0x0, sum = 2
4293 14:00:05.679457 10, 0x0, sum = 3
4294 14:00:05.682083 11, 0x0, sum = 4
4295 14:00:05.682169 best_step = 9
4296 14:00:05.682257
4297 14:00:05.682336 ==
4298 14:00:05.686007 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 14:00:05.691882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 14:00:05.692000 ==
4301 14:00:05.692096 RX Vref Scan: 0
4302 14:00:05.692184
4303 14:00:05.695276 RX Vref 0 -> 0, step: 1
4304 14:00:05.695386
4305 14:00:05.698811 RX Delay -179 -> 252, step: 8
4306 14:00:05.702279 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4307 14:00:05.708882 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4308 14:00:05.711942 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4309 14:00:05.715581 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4310 14:00:05.718658 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4311 14:00:05.722206 iDelay=197, Bit 5, Center 48 (-91 ~ 188) 280
4312 14:00:05.725861 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4313 14:00:05.732377 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4314 14:00:05.735592 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4315 14:00:05.738916 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4316 14:00:05.742237 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4317 14:00:05.748715 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4318 14:00:05.752128 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4319 14:00:05.755909 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4320 14:00:05.758693 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4321 14:00:05.762351 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4322 14:00:05.765290 ==
4323 14:00:05.765400 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 14:00:05.772152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 14:00:05.772285 ==
4326 14:00:05.772380 DQS Delay:
4327 14:00:05.775767 DQS0 = 0, DQS1 = 0
4328 14:00:05.775852 DQM Delay:
4329 14:00:05.778651 DQM0 = 53, DQM1 = 46
4330 14:00:05.778766 DQ Delay:
4331 14:00:05.782277 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4332 14:00:05.785356 DQ4 =56, DQ5 =48, DQ6 =56, DQ7 =56
4333 14:00:05.788849 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4334 14:00:05.792347 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4335 14:00:05.792454
4336 14:00:05.792517
4337 14:00:05.798427 [DQSOSCAuto] RK1, (LSB)MR18= 0x6423, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4338 14:00:05.802068 CH0 RK1: MR19=808, MR18=6423
4339 14:00:05.808445 CH0_RK1: MR19=0x808, MR18=0x6423, DQSOSC=391, MR23=63, INC=171, DEC=114
4340 14:00:05.811934 [RxdqsGatingPostProcess] freq 600
4341 14:00:05.815465 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4342 14:00:05.818578 Pre-setting of DQS Precalculation
4343 14:00:05.825333 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4344 14:00:05.825410 ==
4345 14:00:05.828587 Dram Type= 6, Freq= 0, CH_1, rank 0
4346 14:00:05.832469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 14:00:05.832582 ==
4348 14:00:05.839214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4349 14:00:05.845239 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4350 14:00:05.848699 [CA 0] Center 36 (5~67) winsize 63
4351 14:00:05.852191 [CA 1] Center 36 (5~67) winsize 63
4352 14:00:05.854987 [CA 2] Center 34 (4~65) winsize 62
4353 14:00:05.858561 [CA 3] Center 34 (3~65) winsize 63
4354 14:00:05.861844 [CA 4] Center 34 (4~65) winsize 62
4355 14:00:05.864936 [CA 5] Center 33 (3~64) winsize 62
4356 14:00:05.865027
4357 14:00:05.868994 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4358 14:00:05.869086
4359 14:00:05.871665 [CATrainingPosCal] consider 1 rank data
4360 14:00:05.875291 u2DelayCellTimex100 = 270/100 ps
4361 14:00:05.878522 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4362 14:00:05.882156 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4363 14:00:05.885394 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4364 14:00:05.888522 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4365 14:00:05.891886 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4366 14:00:05.895073 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4367 14:00:05.895149
4368 14:00:05.901396 CA PerBit enable=1, Macro0, CA PI delay=33
4369 14:00:05.901487
4370 14:00:05.901580 [CBTSetCACLKResult] CA Dly = 33
4371 14:00:05.904828 CS Dly: 5 (0~36)
4372 14:00:05.904910 ==
4373 14:00:05.908289 Dram Type= 6, Freq= 0, CH_1, rank 1
4374 14:00:05.911536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 14:00:05.911653 ==
4376 14:00:05.918390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4377 14:00:05.925201 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4378 14:00:05.928116 [CA 0] Center 36 (6~67) winsize 62
4379 14:00:05.931724 [CA 1] Center 36 (5~67) winsize 63
4380 14:00:05.934940 [CA 2] Center 34 (4~65) winsize 62
4381 14:00:05.938108 [CA 3] Center 34 (4~65) winsize 62
4382 14:00:05.941675 [CA 4] Center 34 (4~65) winsize 62
4383 14:00:05.944860 [CA 5] Center 34 (3~65) winsize 63
4384 14:00:05.944981
4385 14:00:05.948385 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4386 14:00:05.948524
4387 14:00:05.951938 [CATrainingPosCal] consider 2 rank data
4388 14:00:05.954751 u2DelayCellTimex100 = 270/100 ps
4389 14:00:05.958193 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4390 14:00:05.961533 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4391 14:00:05.964777 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4392 14:00:05.968264 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4393 14:00:05.971569 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4394 14:00:05.975086 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4395 14:00:05.975194
4396 14:00:05.981464 CA PerBit enable=1, Macro0, CA PI delay=33
4397 14:00:05.981548
4398 14:00:05.981620 [CBTSetCACLKResult] CA Dly = 33
4399 14:00:05.984911 CS Dly: 6 (0~38)
4400 14:00:05.984990
4401 14:00:05.988285 ----->DramcWriteLeveling(PI) begin...
4402 14:00:05.988363 ==
4403 14:00:05.991824 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 14:00:05.994864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 14:00:05.994948 ==
4406 14:00:05.998400 Write leveling (Byte 0): 29 => 29
4407 14:00:06.001224 Write leveling (Byte 1): 30 => 30
4408 14:00:06.004872 DramcWriteLeveling(PI) end<-----
4409 14:00:06.004951
4410 14:00:06.005017 ==
4411 14:00:06.008319 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 14:00:06.015067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 14:00:06.015148 ==
4414 14:00:06.015220 [Gating] SW mode calibration
4415 14:00:06.024748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4416 14:00:06.028063 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4417 14:00:06.031335 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 14:00:06.037882 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 14:00:06.040969 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 14:00:06.044767 0 9 12 | B1->B0 | 2e2e 2d2d | 1 0 | (1 0) (0 0)
4421 14:00:06.051091 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 14:00:06.054495 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 14:00:06.058085 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 14:00:06.064298 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 14:00:06.067623 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 14:00:06.071216 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 14:00:06.078050 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4428 14:00:06.081557 0 10 12 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
4429 14:00:06.084686 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 14:00:06.091063 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 14:00:06.094632 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 14:00:06.097623 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 14:00:06.104569 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 14:00:06.107474 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 14:00:06.110980 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 14:00:06.117859 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4437 14:00:06.121027 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 14:00:06.124584 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 14:00:06.131065 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 14:00:06.134725 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 14:00:06.137567 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 14:00:06.140810 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 14:00:06.147520 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 14:00:06.151121 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 14:00:06.154189 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 14:00:06.161170 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 14:00:06.164404 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 14:00:06.167337 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 14:00:06.174206 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 14:00:06.177506 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 14:00:06.180852 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4452 14:00:06.187400 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4453 14:00:06.190447 Total UI for P1: 0, mck2ui 16
4454 14:00:06.194228 best dqsien dly found for B0: ( 0, 13, 8)
4455 14:00:06.197557 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 14:00:06.200486 Total UI for P1: 0, mck2ui 16
4457 14:00:06.204249 best dqsien dly found for B1: ( 0, 13, 12)
4458 14:00:06.207285 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4459 14:00:06.210839 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4460 14:00:06.210923
4461 14:00:06.213827 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4462 14:00:06.217336 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4463 14:00:06.220672 [Gating] SW calibration Done
4464 14:00:06.220788 ==
4465 14:00:06.223821 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 14:00:06.227224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 14:00:06.230350 ==
4468 14:00:06.230465 RX Vref Scan: 0
4469 14:00:06.230564
4470 14:00:06.234110 RX Vref 0 -> 0, step: 1
4471 14:00:06.234194
4472 14:00:06.237018 RX Delay -230 -> 252, step: 16
4473 14:00:06.240732 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4474 14:00:06.243841 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4475 14:00:06.247470 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4476 14:00:06.253692 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4477 14:00:06.257526 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4478 14:00:06.260507 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4479 14:00:06.264011 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4480 14:00:06.267025 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4481 14:00:06.273963 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4482 14:00:06.277273 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4483 14:00:06.280262 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4484 14:00:06.283816 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4485 14:00:06.290429 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4486 14:00:06.293546 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4487 14:00:06.297397 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4488 14:00:06.300083 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4489 14:00:06.300182 ==
4490 14:00:06.303646 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 14:00:06.306920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 14:00:06.310487 ==
4493 14:00:06.310563 DQS Delay:
4494 14:00:06.310641 DQS0 = 0, DQS1 = 0
4495 14:00:06.313779 DQM Delay:
4496 14:00:06.313864 DQM0 = 53, DQM1 = 50
4497 14:00:06.316726 DQ Delay:
4498 14:00:06.320281 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =49
4499 14:00:06.320363 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4500 14:00:06.323456 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4501 14:00:06.330142 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4502 14:00:06.330228
4503 14:00:06.330302
4504 14:00:06.330399 ==
4505 14:00:06.333501 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 14:00:06.336834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 14:00:06.336912 ==
4508 14:00:06.336975
4509 14:00:06.337040
4510 14:00:06.340047 TX Vref Scan disable
4511 14:00:06.340119 == TX Byte 0 ==
4512 14:00:06.346397 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4513 14:00:06.349805 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4514 14:00:06.349882 == TX Byte 1 ==
4515 14:00:06.356400 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4516 14:00:06.359880 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4517 14:00:06.359977 ==
4518 14:00:06.363199 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 14:00:06.366302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 14:00:06.366384 ==
4521 14:00:06.366452
4522 14:00:06.366512
4523 14:00:06.369585 TX Vref Scan disable
4524 14:00:06.373257 == TX Byte 0 ==
4525 14:00:06.376262 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4526 14:00:06.379630 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4527 14:00:06.382910 == TX Byte 1 ==
4528 14:00:06.386474 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4529 14:00:06.393281 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4530 14:00:06.393376
4531 14:00:06.393459 [DATLAT]
4532 14:00:06.393553 Freq=600, CH1 RK0
4533 14:00:06.393628
4534 14:00:06.396266 DATLAT Default: 0x9
4535 14:00:06.396383 0, 0xFFFF, sum = 0
4536 14:00:06.399741 1, 0xFFFF, sum = 0
4537 14:00:06.399831 2, 0xFFFF, sum = 0
4538 14:00:06.402860 3, 0xFFFF, sum = 0
4539 14:00:06.406394 4, 0xFFFF, sum = 0
4540 14:00:06.406507 5, 0xFFFF, sum = 0
4541 14:00:06.409393 6, 0xFFFF, sum = 0
4542 14:00:06.409494 7, 0xFFFF, sum = 0
4543 14:00:06.409587 8, 0x0, sum = 1
4544 14:00:06.413088 9, 0x0, sum = 2
4545 14:00:06.413193 10, 0x0, sum = 3
4546 14:00:06.416713 11, 0x0, sum = 4
4547 14:00:06.416792 best_step = 9
4548 14:00:06.416874
4549 14:00:06.416966 ==
4550 14:00:06.419522 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 14:00:06.426392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 14:00:06.426515 ==
4553 14:00:06.426618 RX Vref Scan: 1
4554 14:00:06.426730
4555 14:00:06.430008 RX Vref 0 -> 0, step: 1
4556 14:00:06.430120
4557 14:00:06.432913 RX Delay -163 -> 252, step: 8
4558 14:00:06.433009
4559 14:00:06.436368 Set Vref, RX VrefLevel [Byte0]: 53
4560 14:00:06.439668 [Byte1]: 53
4561 14:00:06.439772
4562 14:00:06.443347 Final RX Vref Byte 0 = 53 to rank0
4563 14:00:06.446468 Final RX Vref Byte 1 = 53 to rank0
4564 14:00:06.449698 Final RX Vref Byte 0 = 53 to rank1
4565 14:00:06.452808 Final RX Vref Byte 1 = 53 to rank1==
4566 14:00:06.456332 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 14:00:06.459743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 14:00:06.459829 ==
4569 14:00:06.463279 DQS Delay:
4570 14:00:06.463376 DQS0 = 0, DQS1 = 0
4571 14:00:06.463459 DQM Delay:
4572 14:00:06.466188 DQM0 = 48, DQM1 = 45
4573 14:00:06.466263 DQ Delay:
4574 14:00:06.469873 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4575 14:00:06.472864 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4576 14:00:06.476440 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4577 14:00:06.479678 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4578 14:00:06.479781
4579 14:00:06.479876
4580 14:00:06.489621 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4581 14:00:06.489737 CH1 RK0: MR19=808, MR18=4C72
4582 14:00:06.496576 CH1_RK0: MR19=0x808, MR18=0x4C72, DQSOSC=388, MR23=63, INC=174, DEC=116
4583 14:00:06.496656
4584 14:00:06.499745 ----->DramcWriteLeveling(PI) begin...
4585 14:00:06.502654 ==
4586 14:00:06.502772 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 14:00:06.509682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 14:00:06.509762 ==
4589 14:00:06.513273 Write leveling (Byte 0): 30 => 30
4590 14:00:06.516134 Write leveling (Byte 1): 30 => 30
4591 14:00:06.519861 DramcWriteLeveling(PI) end<-----
4592 14:00:06.519940
4593 14:00:06.520008 ==
4594 14:00:06.522833 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 14:00:06.526429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 14:00:06.526534 ==
4597 14:00:06.529533 [Gating] SW mode calibration
4598 14:00:06.536030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4599 14:00:06.539437 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4600 14:00:06.545929 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 14:00:06.549456 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 14:00:06.552785 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4603 14:00:06.559435 0 9 12 | B1->B0 | 2f2f 3030 | 0 1 | (0 1) (1 0)
4604 14:00:06.562953 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4605 14:00:06.566233 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 14:00:06.572804 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 14:00:06.575619 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 14:00:06.579337 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 14:00:06.585611 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 14:00:06.589398 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4611 14:00:06.592610 0 10 12 | B1->B0 | 3939 3535 | 0 1 | (0 0) (0 0)
4612 14:00:06.599244 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4613 14:00:06.602285 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 14:00:06.605806 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 14:00:06.612057 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 14:00:06.615915 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 14:00:06.619076 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 14:00:06.625646 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 14:00:06.629460 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4620 14:00:06.632469 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4621 14:00:06.639323 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 14:00:06.642758 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 14:00:06.645487 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 14:00:06.651898 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 14:00:06.655405 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 14:00:06.659024 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 14:00:06.665413 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 14:00:06.668925 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 14:00:06.672008 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 14:00:06.678399 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 14:00:06.681972 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 14:00:06.685073 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 14:00:06.691517 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 14:00:06.695011 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 14:00:06.698286 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 14:00:06.702011 Total UI for P1: 0, mck2ui 16
4637 14:00:06.704865 best dqsien dly found for B0: ( 0, 13, 10)
4638 14:00:06.708454 Total UI for P1: 0, mck2ui 16
4639 14:00:06.711439 best dqsien dly found for B1: ( 0, 13, 10)
4640 14:00:06.715346 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4641 14:00:06.718382 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4642 14:00:06.718510
4643 14:00:06.722366 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4644 14:00:06.728461 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4645 14:00:06.728591 [Gating] SW calibration Done
4646 14:00:06.728706 ==
4647 14:00:06.731485 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 14:00:06.738703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 14:00:06.738815 ==
4650 14:00:06.738917 RX Vref Scan: 0
4651 14:00:06.739011
4652 14:00:06.741975 RX Vref 0 -> 0, step: 1
4653 14:00:06.742079
4654 14:00:06.744951 RX Delay -230 -> 252, step: 16
4655 14:00:06.748482 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4656 14:00:06.751908 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4657 14:00:06.755279 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4658 14:00:06.761677 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4659 14:00:06.765344 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4660 14:00:06.768330 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4661 14:00:06.772069 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4662 14:00:06.775034 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4663 14:00:06.781579 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4664 14:00:06.784895 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4665 14:00:06.788459 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4666 14:00:06.791814 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4667 14:00:06.798381 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4668 14:00:06.801546 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4669 14:00:06.805069 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4670 14:00:06.808518 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4671 14:00:06.811755 ==
4672 14:00:06.811858 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 14:00:06.818241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 14:00:06.818344 ==
4675 14:00:06.818437 DQS Delay:
4676 14:00:06.821424 DQS0 = 0, DQS1 = 0
4677 14:00:06.821526 DQM Delay:
4678 14:00:06.824820 DQM0 = 50, DQM1 = 48
4679 14:00:06.824923 DQ Delay:
4680 14:00:06.827980 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4681 14:00:06.831589 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4682 14:00:06.834957 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4683 14:00:06.838254 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4684 14:00:06.838356
4685 14:00:06.838449
4686 14:00:06.838538 ==
4687 14:00:06.841201 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 14:00:06.844550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 14:00:06.844632 ==
4690 14:00:06.844697
4691 14:00:06.844757
4692 14:00:06.847965 TX Vref Scan disable
4693 14:00:06.851654 == TX Byte 0 ==
4694 14:00:06.854606 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4695 14:00:06.858127 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4696 14:00:06.861596 == TX Byte 1 ==
4697 14:00:06.864710 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4698 14:00:06.868231 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4699 14:00:06.868350 ==
4700 14:00:06.871440 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 14:00:06.874895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 14:00:06.877873 ==
4703 14:00:06.878001
4704 14:00:06.878121
4705 14:00:06.878234 TX Vref Scan disable
4706 14:00:06.881723 == TX Byte 0 ==
4707 14:00:06.885151 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4708 14:00:06.888910 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4709 14:00:06.891915 == TX Byte 1 ==
4710 14:00:06.895405 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4711 14:00:06.901837 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4712 14:00:06.901964
4713 14:00:06.902082 [DATLAT]
4714 14:00:06.902192 Freq=600, CH1 RK1
4715 14:00:06.902306
4716 14:00:06.905530 DATLAT Default: 0x9
4717 14:00:06.905653 0, 0xFFFF, sum = 0
4718 14:00:06.908285 1, 0xFFFF, sum = 0
4719 14:00:06.908408 2, 0xFFFF, sum = 0
4720 14:00:06.911505 3, 0xFFFF, sum = 0
4721 14:00:06.915226 4, 0xFFFF, sum = 0
4722 14:00:06.915354 5, 0xFFFF, sum = 0
4723 14:00:06.918681 6, 0xFFFF, sum = 0
4724 14:00:06.918805 7, 0xFFFF, sum = 0
4725 14:00:06.918925 8, 0x0, sum = 1
4726 14:00:06.921544 9, 0x0, sum = 2
4727 14:00:06.921671 10, 0x0, sum = 3
4728 14:00:06.924647 11, 0x0, sum = 4
4729 14:00:06.924770 best_step = 9
4730 14:00:06.924888
4731 14:00:06.925002 ==
4732 14:00:06.928614 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 14:00:06.934928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 14:00:06.935057 ==
4735 14:00:06.935175 RX Vref Scan: 0
4736 14:00:06.935290
4737 14:00:06.938337 RX Vref 0 -> 0, step: 1
4738 14:00:06.938457
4739 14:00:06.941232 RX Delay -163 -> 252, step: 8
4740 14:00:06.944656 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4741 14:00:06.951552 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4742 14:00:06.955246 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4743 14:00:06.957886 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4744 14:00:06.961490 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4745 14:00:06.964538 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4746 14:00:06.971703 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4747 14:00:06.974812 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4748 14:00:06.978091 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4749 14:00:06.981142 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4750 14:00:06.984727 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4751 14:00:06.991167 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4752 14:00:06.994959 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4753 14:00:06.998219 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4754 14:00:07.001379 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4755 14:00:07.008054 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4756 14:00:07.008133 ==
4757 14:00:07.011151 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 14:00:07.014800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 14:00:07.014878 ==
4760 14:00:07.014942 DQS Delay:
4761 14:00:07.018039 DQS0 = 0, DQS1 = 0
4762 14:00:07.018141 DQM Delay:
4763 14:00:07.021400 DQM0 = 48, DQM1 = 46
4764 14:00:07.021473 DQ Delay:
4765 14:00:07.025020 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4766 14:00:07.027795 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4767 14:00:07.031150 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4768 14:00:07.034600 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4769 14:00:07.034675
4770 14:00:07.034737
4771 14:00:07.041464 [DQSOSCAuto] RK1, (LSB)MR18= 0x691f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4772 14:00:07.044637 CH1 RK1: MR19=808, MR18=691F
4773 14:00:07.051123 CH1_RK1: MR19=0x808, MR18=0x691F, DQSOSC=390, MR23=63, INC=172, DEC=114
4774 14:00:07.054468 [RxdqsGatingPostProcess] freq 600
4775 14:00:07.061036 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4776 14:00:07.061146 Pre-setting of DQS Precalculation
4777 14:00:07.068056 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4778 14:00:07.074875 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4779 14:00:07.081318 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4780 14:00:07.081401
4781 14:00:07.081466
4782 14:00:07.084577 [Calibration Summary] 1200 Mbps
4783 14:00:07.087578 CH 0, Rank 0
4784 14:00:07.087689 SW Impedance : PASS
4785 14:00:07.091526 DUTY Scan : NO K
4786 14:00:07.094398 ZQ Calibration : PASS
4787 14:00:07.094501 Jitter Meter : NO K
4788 14:00:07.098330 CBT Training : PASS
4789 14:00:07.098407 Write leveling : PASS
4790 14:00:07.101008 RX DQS gating : PASS
4791 14:00:07.104488 RX DQ/DQS(RDDQC) : PASS
4792 14:00:07.104570 TX DQ/DQS : PASS
4793 14:00:07.107930 RX DATLAT : PASS
4794 14:00:07.111414 RX DQ/DQS(Engine): PASS
4795 14:00:07.111492 TX OE : NO K
4796 14:00:07.114390 All Pass.
4797 14:00:07.114459
4798 14:00:07.114521 CH 0, Rank 1
4799 14:00:07.118031 SW Impedance : PASS
4800 14:00:07.118106 DUTY Scan : NO K
4801 14:00:07.121187 ZQ Calibration : PASS
4802 14:00:07.124529 Jitter Meter : NO K
4803 14:00:07.124626 CBT Training : PASS
4804 14:00:07.127801 Write leveling : PASS
4805 14:00:07.131555 RX DQS gating : PASS
4806 14:00:07.131660 RX DQ/DQS(RDDQC) : PASS
4807 14:00:07.134752 TX DQ/DQS : PASS
4808 14:00:07.134848 RX DATLAT : PASS
4809 14:00:07.137579 RX DQ/DQS(Engine): PASS
4810 14:00:07.140990 TX OE : NO K
4811 14:00:07.141087 All Pass.
4812 14:00:07.141177
4813 14:00:07.141264 CH 1, Rank 0
4814 14:00:07.144237 SW Impedance : PASS
4815 14:00:07.147845 DUTY Scan : NO K
4816 14:00:07.147920 ZQ Calibration : PASS
4817 14:00:07.151251 Jitter Meter : NO K
4818 14:00:07.154504 CBT Training : PASS
4819 14:00:07.154604 Write leveling : PASS
4820 14:00:07.157590 RX DQS gating : PASS
4821 14:00:07.160953 RX DQ/DQS(RDDQC) : PASS
4822 14:00:07.161025 TX DQ/DQS : PASS
4823 14:00:07.164176 RX DATLAT : PASS
4824 14:00:07.167928 RX DQ/DQS(Engine): PASS
4825 14:00:07.168001 TX OE : NO K
4826 14:00:07.171165 All Pass.
4827 14:00:07.171267
4828 14:00:07.171358 CH 1, Rank 1
4829 14:00:07.174006 SW Impedance : PASS
4830 14:00:07.174110 DUTY Scan : NO K
4831 14:00:07.177209 ZQ Calibration : PASS
4832 14:00:07.180937 Jitter Meter : NO K
4833 14:00:07.181034 CBT Training : PASS
4834 14:00:07.184017 Write leveling : PASS
4835 14:00:07.187330 RX DQS gating : PASS
4836 14:00:07.187429 RX DQ/DQS(RDDQC) : PASS
4837 14:00:07.190812 TX DQ/DQS : PASS
4838 14:00:07.194355 RX DATLAT : PASS
4839 14:00:07.194456 RX DQ/DQS(Engine): PASS
4840 14:00:07.197432 TX OE : NO K
4841 14:00:07.197507 All Pass.
4842 14:00:07.197568
4843 14:00:07.201159 DramC Write-DBI off
4844 14:00:07.203988 PER_BANK_REFRESH: Hybrid Mode
4845 14:00:07.204087 TX_TRACKING: ON
4846 14:00:07.214303 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4847 14:00:07.217518 [FAST_K] Save calibration result to emmc
4848 14:00:07.220837 dramc_set_vcore_voltage set vcore to 662500
4849 14:00:07.220910 Read voltage for 933, 3
4850 14:00:07.224217 Vio18 = 0
4851 14:00:07.224314 Vcore = 662500
4852 14:00:07.224405 Vdram = 0
4853 14:00:07.227650 Vddq = 0
4854 14:00:07.227719 Vmddr = 0
4855 14:00:07.230719 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4856 14:00:07.237131 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4857 14:00:07.241011 MEM_TYPE=3, freq_sel=17
4858 14:00:07.244126 sv_algorithm_assistance_LP4_1600
4859 14:00:07.247562 ============ PULL DRAM RESETB DOWN ============
4860 14:00:07.250348 ========== PULL DRAM RESETB DOWN end =========
4861 14:00:07.257148 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 14:00:07.260538 ===================================
4863 14:00:07.260682 LPDDR4 DRAM CONFIGURATION
4864 14:00:07.264008 ===================================
4865 14:00:07.267406 EX_ROW_EN[0] = 0x0
4866 14:00:07.267507 EX_ROW_EN[1] = 0x0
4867 14:00:07.270751 LP4Y_EN = 0x0
4868 14:00:07.270870 WORK_FSP = 0x0
4869 14:00:07.274279 WL = 0x3
4870 14:00:07.277197 RL = 0x3
4871 14:00:07.277314 BL = 0x2
4872 14:00:07.280449 RPST = 0x0
4873 14:00:07.280551 RD_PRE = 0x0
4874 14:00:07.284082 WR_PRE = 0x1
4875 14:00:07.284205 WR_PST = 0x0
4876 14:00:07.287053 DBI_WR = 0x0
4877 14:00:07.287185 DBI_RD = 0x0
4878 14:00:07.290507 OTF = 0x1
4879 14:00:07.293946 ===================================
4880 14:00:07.296929 ===================================
4881 14:00:07.297033 ANA top config
4882 14:00:07.300668 ===================================
4883 14:00:07.303645 DLL_ASYNC_EN = 0
4884 14:00:07.307198 ALL_SLAVE_EN = 1
4885 14:00:07.307310 NEW_RANK_MODE = 1
4886 14:00:07.310800 DLL_IDLE_MODE = 1
4887 14:00:07.313609 LP45_APHY_COMB_EN = 1
4888 14:00:07.316946 TX_ODT_DIS = 1
4889 14:00:07.320213 NEW_8X_MODE = 1
4890 14:00:07.323835 ===================================
4891 14:00:07.326735 ===================================
4892 14:00:07.326844 data_rate = 1866
4893 14:00:07.330588 CKR = 1
4894 14:00:07.333557 DQ_P2S_RATIO = 8
4895 14:00:07.337089 ===================================
4896 14:00:07.340361 CA_P2S_RATIO = 8
4897 14:00:07.343827 DQ_CA_OPEN = 0
4898 14:00:07.346905 DQ_SEMI_OPEN = 0
4899 14:00:07.347011 CA_SEMI_OPEN = 0
4900 14:00:07.350137 CA_FULL_RATE = 0
4901 14:00:07.353722 DQ_CKDIV4_EN = 1
4902 14:00:07.356921 CA_CKDIV4_EN = 1
4903 14:00:07.359863 CA_PREDIV_EN = 0
4904 14:00:07.363589 PH8_DLY = 0
4905 14:00:07.363689 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4906 14:00:07.366643 DQ_AAMCK_DIV = 4
4907 14:00:07.370038 CA_AAMCK_DIV = 4
4908 14:00:07.373006 CA_ADMCK_DIV = 4
4909 14:00:07.376853 DQ_TRACK_CA_EN = 0
4910 14:00:07.379740 CA_PICK = 933
4911 14:00:07.379843 CA_MCKIO = 933
4912 14:00:07.383418 MCKIO_SEMI = 0
4913 14:00:07.386335 PLL_FREQ = 3732
4914 14:00:07.389709 DQ_UI_PI_RATIO = 32
4915 14:00:07.393303 CA_UI_PI_RATIO = 0
4916 14:00:07.396840 ===================================
4917 14:00:07.399927 ===================================
4918 14:00:07.403112 memory_type:LPDDR4
4919 14:00:07.403215 GP_NUM : 10
4920 14:00:07.407074 SRAM_EN : 1
4921 14:00:07.407179 MD32_EN : 0
4922 14:00:07.410198 ===================================
4923 14:00:07.413251 [ANA_INIT] >>>>>>>>>>>>>>
4924 14:00:07.416451 <<<<<< [CONFIGURE PHASE]: ANA_TX
4925 14:00:07.420022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4926 14:00:07.423335 ===================================
4927 14:00:07.426823 data_rate = 1866,PCW = 0X8f00
4928 14:00:07.429630 ===================================
4929 14:00:07.433225 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4930 14:00:07.439876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 14:00:07.442911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 14:00:07.450295 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4933 14:00:07.452879 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4934 14:00:07.456212 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4935 14:00:07.456322 [ANA_INIT] flow start
4936 14:00:07.459647 [ANA_INIT] PLL >>>>>>>>
4937 14:00:07.462889 [ANA_INIT] PLL <<<<<<<<
4938 14:00:07.462996 [ANA_INIT] MIDPI >>>>>>>>
4939 14:00:07.466131 [ANA_INIT] MIDPI <<<<<<<<
4940 14:00:07.470164 [ANA_INIT] DLL >>>>>>>>
4941 14:00:07.470281 [ANA_INIT] flow end
4942 14:00:07.476614 ============ LP4 DIFF to SE enter ============
4943 14:00:07.479728 ============ LP4 DIFF to SE exit ============
4944 14:00:07.483006 [ANA_INIT] <<<<<<<<<<<<<
4945 14:00:07.483118 [Flow] Enable top DCM control >>>>>
4946 14:00:07.486573 [Flow] Enable top DCM control <<<<<
4947 14:00:07.489304 Enable DLL master slave shuffle
4948 14:00:07.496457 ==============================================================
4949 14:00:07.499383 Gating Mode config
4950 14:00:07.502724 ==============================================================
4951 14:00:07.506034 Config description:
4952 14:00:07.516206 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4953 14:00:07.522772 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4954 14:00:07.526073 SELPH_MODE 0: By rank 1: By Phase
4955 14:00:07.532864 ==============================================================
4956 14:00:07.536061 GAT_TRACK_EN = 1
4957 14:00:07.539673 RX_GATING_MODE = 2
4958 14:00:07.539783 RX_GATING_TRACK_MODE = 2
4959 14:00:07.542670 SELPH_MODE = 1
4960 14:00:07.546339 PICG_EARLY_EN = 1
4961 14:00:07.550095 VALID_LAT_VALUE = 1
4962 14:00:07.556698 ==============================================================
4963 14:00:07.559861 Enter into Gating configuration >>>>
4964 14:00:07.562708 Exit from Gating configuration <<<<
4965 14:00:07.566507 Enter into DVFS_PRE_config >>>>>
4966 14:00:07.576229 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4967 14:00:07.579647 Exit from DVFS_PRE_config <<<<<
4968 14:00:07.582551 Enter into PICG configuration >>>>
4969 14:00:07.586372 Exit from PICG configuration <<<<
4970 14:00:07.589288 [RX_INPUT] configuration >>>>>
4971 14:00:07.592501 [RX_INPUT] configuration <<<<<
4972 14:00:07.596162 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4973 14:00:07.602712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4974 14:00:07.609143 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 14:00:07.616303 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 14:00:07.619227 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 14:00:07.626278 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 14:00:07.629330 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4979 14:00:07.635981 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4980 14:00:07.639221 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4981 14:00:07.642911 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4982 14:00:07.645926 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4983 14:00:07.653020 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 14:00:07.655926 ===================================
4985 14:00:07.656052 LPDDR4 DRAM CONFIGURATION
4986 14:00:07.659000 ===================================
4987 14:00:07.662353 EX_ROW_EN[0] = 0x0
4988 14:00:07.665671 EX_ROW_EN[1] = 0x0
4989 14:00:07.665794 LP4Y_EN = 0x0
4990 14:00:07.669169 WORK_FSP = 0x0
4991 14:00:07.669300 WL = 0x3
4992 14:00:07.672959 RL = 0x3
4993 14:00:07.673090 BL = 0x2
4994 14:00:07.675860 RPST = 0x0
4995 14:00:07.675985 RD_PRE = 0x0
4996 14:00:07.679275 WR_PRE = 0x1
4997 14:00:07.679402 WR_PST = 0x0
4998 14:00:07.682932 DBI_WR = 0x0
4999 14:00:07.683054 DBI_RD = 0x0
5000 14:00:07.686102 OTF = 0x1
5001 14:00:07.689413 ===================================
5002 14:00:07.692526 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5003 14:00:07.695979 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5004 14:00:07.702595 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 14:00:07.706083 ===================================
5006 14:00:07.706208 LPDDR4 DRAM CONFIGURATION
5007 14:00:07.709456 ===================================
5008 14:00:07.712864 EX_ROW_EN[0] = 0x10
5009 14:00:07.712986 EX_ROW_EN[1] = 0x0
5010 14:00:07.715768 LP4Y_EN = 0x0
5011 14:00:07.719121 WORK_FSP = 0x0
5012 14:00:07.719242 WL = 0x3
5013 14:00:07.722154 RL = 0x3
5014 14:00:07.722282 BL = 0x2
5015 14:00:07.725593 RPST = 0x0
5016 14:00:07.725718 RD_PRE = 0x0
5017 14:00:07.729115 WR_PRE = 0x1
5018 14:00:07.729247 WR_PST = 0x0
5019 14:00:07.732672 DBI_WR = 0x0
5020 14:00:07.732803 DBI_RD = 0x0
5021 14:00:07.735876 OTF = 0x1
5022 14:00:07.739326 ===================================
5023 14:00:07.745831 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5024 14:00:07.749225 nWR fixed to 30
5025 14:00:07.749356 [ModeRegInit_LP4] CH0 RK0
5026 14:00:07.752292 [ModeRegInit_LP4] CH0 RK1
5027 14:00:07.755894 [ModeRegInit_LP4] CH1 RK0
5028 14:00:07.756022 [ModeRegInit_LP4] CH1 RK1
5029 14:00:07.759103 match AC timing 9
5030 14:00:07.762139 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5031 14:00:07.765644 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5032 14:00:07.772489 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5033 14:00:07.775729 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5034 14:00:07.782173 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5035 14:00:07.782254 ==
5036 14:00:07.785770 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 14:00:07.788774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5038 14:00:07.788858 ==
5039 14:00:07.796077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5040 14:00:07.798958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5041 14:00:07.803046 [CA 0] Center 37 (7~68) winsize 62
5042 14:00:07.806424 [CA 1] Center 37 (7~68) winsize 62
5043 14:00:07.809664 [CA 2] Center 34 (4~65) winsize 62
5044 14:00:07.813175 [CA 3] Center 34 (3~65) winsize 63
5045 14:00:07.816659 [CA 4] Center 33 (3~64) winsize 62
5046 14:00:07.820160 [CA 5] Center 32 (2~62) winsize 61
5047 14:00:07.820236
5048 14:00:07.823170 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5049 14:00:07.823242
5050 14:00:07.826719 [CATrainingPosCal] consider 1 rank data
5051 14:00:07.830078 u2DelayCellTimex100 = 270/100 ps
5052 14:00:07.833018 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5053 14:00:07.836848 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5054 14:00:07.843053 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5055 14:00:07.846510 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5056 14:00:07.850002 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5057 14:00:07.853260 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5058 14:00:07.853337
5059 14:00:07.856533 CA PerBit enable=1, Macro0, CA PI delay=32
5060 14:00:07.856639
5061 14:00:07.860031 [CBTSetCACLKResult] CA Dly = 32
5062 14:00:07.860106 CS Dly: 5 (0~36)
5063 14:00:07.862849 ==
5064 14:00:07.866460 Dram Type= 6, Freq= 0, CH_0, rank 1
5065 14:00:07.869641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 14:00:07.869717 ==
5067 14:00:07.873011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 14:00:07.879922 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5069 14:00:07.883394 [CA 0] Center 37 (7~68) winsize 62
5070 14:00:07.886541 [CA 1] Center 37 (7~68) winsize 62
5071 14:00:07.890058 [CA 2] Center 34 (4~65) winsize 62
5072 14:00:07.893093 [CA 3] Center 34 (4~65) winsize 62
5073 14:00:07.896733 [CA 4] Center 33 (3~63) winsize 61
5074 14:00:07.899814 [CA 5] Center 32 (2~63) winsize 62
5075 14:00:07.899887
5076 14:00:07.903573 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5077 14:00:07.903656
5078 14:00:07.906734 [CATrainingPosCal] consider 2 rank data
5079 14:00:07.910300 u2DelayCellTimex100 = 270/100 ps
5080 14:00:07.912948 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5081 14:00:07.919694 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5082 14:00:07.923327 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5083 14:00:07.926196 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5084 14:00:07.929907 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5085 14:00:07.933250 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5086 14:00:07.933385
5087 14:00:07.936444 CA PerBit enable=1, Macro0, CA PI delay=32
5088 14:00:07.936574
5089 14:00:07.939953 [CBTSetCACLKResult] CA Dly = 32
5090 14:00:07.942901 CS Dly: 5 (0~37)
5091 14:00:07.943031
5092 14:00:07.946346 ----->DramcWriteLeveling(PI) begin...
5093 14:00:07.946473 ==
5094 14:00:07.949941 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 14:00:07.953196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 14:00:07.953323 ==
5097 14:00:07.956455 Write leveling (Byte 0): 33 => 33
5098 14:00:07.959730 Write leveling (Byte 1): 30 => 30
5099 14:00:07.962986 DramcWriteLeveling(PI) end<-----
5100 14:00:07.963106
5101 14:00:07.963219 ==
5102 14:00:07.966177 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 14:00:07.969737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 14:00:07.969863 ==
5105 14:00:07.972861 [Gating] SW mode calibration
5106 14:00:07.979659 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5107 14:00:07.986219 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5108 14:00:07.989921 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5109 14:00:07.992948 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 14:00:07.999861 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 14:00:08.003420 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 14:00:08.006322 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 14:00:08.012842 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 14:00:08.016329 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5115 14:00:08.019263 0 14 28 | B1->B0 | 3232 2828 | 1 0 | (1 1) (1 0)
5116 14:00:08.025905 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5117 14:00:08.029680 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 14:00:08.033177 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 14:00:08.036359 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 14:00:08.042640 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 14:00:08.046409 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 14:00:08.049233 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5123 14:00:08.056025 0 15 28 | B1->B0 | 2424 3c3c | 1 0 | (0 0) (0 0)
5124 14:00:08.059310 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5125 14:00:08.062950 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 14:00:08.069334 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 14:00:08.072847 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 14:00:08.076234 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 14:00:08.082799 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 14:00:08.086333 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5131 14:00:08.089085 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5132 14:00:08.096408 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5133 14:00:08.099270 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 14:00:08.102668 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 14:00:08.109653 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 14:00:08.112546 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 14:00:08.116288 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 14:00:08.122748 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 14:00:08.125826 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 14:00:08.129213 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 14:00:08.132806 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 14:00:08.139487 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 14:00:08.142519 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 14:00:08.145989 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 14:00:08.152747 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 14:00:08.156196 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5147 14:00:08.159623 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5148 14:00:08.165733 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5149 14:00:08.169421 Total UI for P1: 0, mck2ui 16
5150 14:00:08.173188 best dqsien dly found for B0: ( 1, 2, 26)
5151 14:00:08.175820 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 14:00:08.179381 Total UI for P1: 0, mck2ui 16
5153 14:00:08.182179 best dqsien dly found for B1: ( 1, 3, 0)
5154 14:00:08.185929 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5155 14:00:08.188909 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5156 14:00:08.189054
5157 14:00:08.192447 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5158 14:00:08.195792 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5159 14:00:08.199191 [Gating] SW calibration Done
5160 14:00:08.199317 ==
5161 14:00:08.202396 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 14:00:08.209001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 14:00:08.209133 ==
5164 14:00:08.209249 RX Vref Scan: 0
5165 14:00:08.209362
5166 14:00:08.212523 RX Vref 0 -> 0, step: 1
5167 14:00:08.212647
5168 14:00:08.215520 RX Delay -80 -> 252, step: 8
5169 14:00:08.219186 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5170 14:00:08.222202 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5171 14:00:08.225976 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5172 14:00:08.228675 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5173 14:00:08.232264 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5174 14:00:08.238668 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5175 14:00:08.242374 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5176 14:00:08.245666 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5177 14:00:08.249120 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5178 14:00:08.252144 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5179 14:00:08.255529 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5180 14:00:08.262458 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5181 14:00:08.265348 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5182 14:00:08.269095 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5183 14:00:08.272093 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5184 14:00:08.275548 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5185 14:00:08.278662 ==
5186 14:00:08.282321 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 14:00:08.285897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 14:00:08.286014 ==
5189 14:00:08.286109 DQS Delay:
5190 14:00:08.288471 DQS0 = 0, DQS1 = 0
5191 14:00:08.288548 DQM Delay:
5192 14:00:08.292083 DQM0 = 103, DQM1 = 95
5193 14:00:08.292156 DQ Delay:
5194 14:00:08.295527 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5195 14:00:08.298955 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =115
5196 14:00:08.302011 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5197 14:00:08.304999 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5198 14:00:08.305122
5199 14:00:08.305233
5200 14:00:08.305345 ==
5201 14:00:08.308454 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 14:00:08.311606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 14:00:08.315494 ==
5204 14:00:08.315605
5205 14:00:08.315689
5206 14:00:08.315751 TX Vref Scan disable
5207 14:00:08.318301 == TX Byte 0 ==
5208 14:00:08.321916 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5209 14:00:08.324897 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5210 14:00:08.328612 == TX Byte 1 ==
5211 14:00:08.332254 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5212 14:00:08.335015 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5213 14:00:08.338314 ==
5214 14:00:08.338435 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 14:00:08.345418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 14:00:08.345503 ==
5217 14:00:08.345571
5218 14:00:08.345632
5219 14:00:08.348350 TX Vref Scan disable
5220 14:00:08.348428 == TX Byte 0 ==
5221 14:00:08.355033 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5222 14:00:08.358185 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5223 14:00:08.358263 == TX Byte 1 ==
5224 14:00:08.365396 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5225 14:00:08.368128 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5226 14:00:08.368203
5227 14:00:08.368267 [DATLAT]
5228 14:00:08.371731 Freq=933, CH0 RK0
5229 14:00:08.371815
5230 14:00:08.371879 DATLAT Default: 0xd
5231 14:00:08.374765 0, 0xFFFF, sum = 0
5232 14:00:08.374842 1, 0xFFFF, sum = 0
5233 14:00:08.378457 2, 0xFFFF, sum = 0
5234 14:00:08.378557 3, 0xFFFF, sum = 0
5235 14:00:08.381221 4, 0xFFFF, sum = 0
5236 14:00:08.381296 5, 0xFFFF, sum = 0
5237 14:00:08.384927 6, 0xFFFF, sum = 0
5238 14:00:08.385000 7, 0xFFFF, sum = 0
5239 14:00:08.388416 8, 0xFFFF, sum = 0
5240 14:00:08.388492 9, 0xFFFF, sum = 0
5241 14:00:08.391296 10, 0x0, sum = 1
5242 14:00:08.391409 11, 0x0, sum = 2
5243 14:00:08.394750 12, 0x0, sum = 3
5244 14:00:08.394825 13, 0x0, sum = 4
5245 14:00:08.397810 best_step = 11
5246 14:00:08.397890
5247 14:00:08.397954 ==
5248 14:00:08.401240 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 14:00:08.404635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 14:00:08.404719 ==
5251 14:00:08.407862 RX Vref Scan: 1
5252 14:00:08.407934
5253 14:00:08.407995 RX Vref 0 -> 0, step: 1
5254 14:00:08.408062
5255 14:00:08.411389 RX Delay -53 -> 252, step: 4
5256 14:00:08.411466
5257 14:00:08.414304 Set Vref, RX VrefLevel [Byte0]: 54
5258 14:00:08.417601 [Byte1]: 52
5259 14:00:08.422183
5260 14:00:08.422260 Final RX Vref Byte 0 = 54 to rank0
5261 14:00:08.425673 Final RX Vref Byte 1 = 52 to rank0
5262 14:00:08.429081 Final RX Vref Byte 0 = 54 to rank1
5263 14:00:08.432097 Final RX Vref Byte 1 = 52 to rank1==
5264 14:00:08.435547 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 14:00:08.442345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 14:00:08.442432 ==
5267 14:00:08.442497 DQS Delay:
5268 14:00:08.445253 DQS0 = 0, DQS1 = 0
5269 14:00:08.445352 DQM Delay:
5270 14:00:08.445426 DQM0 = 103, DQM1 = 94
5271 14:00:08.448425 DQ Delay:
5272 14:00:08.452143 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5273 14:00:08.455557 DQ4 =104, DQ5 =94, DQ6 =112, DQ7 =108
5274 14:00:08.458477 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =88
5275 14:00:08.461847 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5276 14:00:08.461924
5277 14:00:08.462009
5278 14:00:08.468932 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f27, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5279 14:00:08.472201 CH0 RK0: MR19=505, MR18=2F27
5280 14:00:08.478750 CH0_RK0: MR19=0x505, MR18=0x2F27, DQSOSC=407, MR23=63, INC=65, DEC=43
5281 14:00:08.478831
5282 14:00:08.482138 ----->DramcWriteLeveling(PI) begin...
5283 14:00:08.482249 ==
5284 14:00:08.485141 Dram Type= 6, Freq= 0, CH_0, rank 1
5285 14:00:08.488683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 14:00:08.488764 ==
5287 14:00:08.491697 Write leveling (Byte 0): 32 => 32
5288 14:00:08.495187 Write leveling (Byte 1): 29 => 29
5289 14:00:08.498913 DramcWriteLeveling(PI) end<-----
5290 14:00:08.498989
5291 14:00:08.499074 ==
5292 14:00:08.502024 Dram Type= 6, Freq= 0, CH_0, rank 1
5293 14:00:08.505614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 14:00:08.508832 ==
5295 14:00:08.508907 [Gating] SW mode calibration
5296 14:00:08.518335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5297 14:00:08.521830 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5298 14:00:08.525122 0 14 0 | B1->B0 | 3131 3333 | 0 1 | (0 0) (1 1)
5299 14:00:08.531719 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 14:00:08.535710 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 14:00:08.538778 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 14:00:08.545419 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 14:00:08.548326 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 14:00:08.552066 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5305 14:00:08.558894 0 14 28 | B1->B0 | 2828 2b2b | 0 0 | (0 0) (0 0)
5306 14:00:08.561866 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5307 14:00:08.565048 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 14:00:08.571419 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 14:00:08.574720 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 14:00:08.578505 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 14:00:08.585330 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 14:00:08.587957 0 15 24 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
5313 14:00:08.591911 0 15 28 | B1->B0 | 3939 3636 | 1 1 | (0 0) (1 1)
5314 14:00:08.598151 1 0 0 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
5315 14:00:08.601730 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 14:00:08.604712 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 14:00:08.611248 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 14:00:08.614982 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 14:00:08.618204 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 14:00:08.624735 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 14:00:08.628136 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5322 14:00:08.631873 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 14:00:08.634743 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 14:00:08.641490 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 14:00:08.645029 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 14:00:08.648030 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 14:00:08.654875 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 14:00:08.658182 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 14:00:08.661884 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 14:00:08.668223 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 14:00:08.671556 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 14:00:08.674979 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 14:00:08.681561 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 14:00:08.684900 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 14:00:08.688426 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 14:00:08.694810 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 14:00:08.698203 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 14:00:08.701439 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 14:00:08.704595 Total UI for P1: 0, mck2ui 16
5340 14:00:08.707818 best dqsien dly found for B0: ( 1, 2, 30)
5341 14:00:08.711224 Total UI for P1: 0, mck2ui 16
5342 14:00:08.714727 best dqsien dly found for B1: ( 1, 2, 30)
5343 14:00:08.717922 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5344 14:00:08.721335 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5345 14:00:08.721432
5346 14:00:08.724674 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5347 14:00:08.731178 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5348 14:00:08.731256 [Gating] SW calibration Done
5349 14:00:08.731321 ==
5350 14:00:08.734901 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 14:00:08.741195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 14:00:08.741274 ==
5353 14:00:08.741337 RX Vref Scan: 0
5354 14:00:08.741396
5355 14:00:08.744595 RX Vref 0 -> 0, step: 1
5356 14:00:08.744665
5357 14:00:08.747856 RX Delay -80 -> 252, step: 8
5358 14:00:08.751421 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5359 14:00:08.754439 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5360 14:00:08.757961 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5361 14:00:08.764383 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5362 14:00:08.768056 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5363 14:00:08.770932 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5364 14:00:08.774801 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5365 14:00:08.777585 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5366 14:00:08.781219 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5367 14:00:08.787598 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5368 14:00:08.791009 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5369 14:00:08.794680 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5370 14:00:08.797958 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5371 14:00:08.800977 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5372 14:00:08.804884 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5373 14:00:08.811008 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5374 14:00:08.811086 ==
5375 14:00:08.814693 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 14:00:08.817829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 14:00:08.817908 ==
5378 14:00:08.817976 DQS Delay:
5379 14:00:08.821063 DQS0 = 0, DQS1 = 0
5380 14:00:08.821161 DQM Delay:
5381 14:00:08.824637 DQM0 = 105, DQM1 = 94
5382 14:00:08.824712 DQ Delay:
5383 14:00:08.827358 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5384 14:00:08.830666 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =111
5385 14:00:08.834100 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5386 14:00:08.837343 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5387 14:00:08.837418
5388 14:00:08.837506
5389 14:00:08.837604 ==
5390 14:00:08.841037 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 14:00:08.847342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 14:00:08.847420 ==
5393 14:00:08.847526
5394 14:00:08.847625
5395 14:00:08.847733 TX Vref Scan disable
5396 14:00:08.850897 == TX Byte 0 ==
5397 14:00:08.853887 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5398 14:00:08.860524 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5399 14:00:08.860631 == TX Byte 1 ==
5400 14:00:08.864052 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5401 14:00:08.867796 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5402 14:00:08.870668 ==
5403 14:00:08.874108 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 14:00:08.877555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 14:00:08.877661 ==
5406 14:00:08.877734
5407 14:00:08.877795
5408 14:00:08.881005 TX Vref Scan disable
5409 14:00:08.881133 == TX Byte 0 ==
5410 14:00:08.887171 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5411 14:00:08.890862 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5412 14:00:08.890967 == TX Byte 1 ==
5413 14:00:08.897294 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5414 14:00:08.900367 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5415 14:00:08.900471
5416 14:00:08.900565 [DATLAT]
5417 14:00:08.903844 Freq=933, CH0 RK1
5418 14:00:08.903915
5419 14:00:08.903976 DATLAT Default: 0xb
5420 14:00:08.907225 0, 0xFFFF, sum = 0
5421 14:00:08.907328 1, 0xFFFF, sum = 0
5422 14:00:08.910625 2, 0xFFFF, sum = 0
5423 14:00:08.910732 3, 0xFFFF, sum = 0
5424 14:00:08.913717 4, 0xFFFF, sum = 0
5425 14:00:08.913791 5, 0xFFFF, sum = 0
5426 14:00:08.917050 6, 0xFFFF, sum = 0
5427 14:00:08.920820 7, 0xFFFF, sum = 0
5428 14:00:08.920928 8, 0xFFFF, sum = 0
5429 14:00:08.924240 9, 0xFFFF, sum = 0
5430 14:00:08.924322 10, 0x0, sum = 1
5431 14:00:08.924388 11, 0x0, sum = 2
5432 14:00:08.927210 12, 0x0, sum = 3
5433 14:00:08.927315 13, 0x0, sum = 4
5434 14:00:08.930111 best_step = 11
5435 14:00:08.930212
5436 14:00:08.930303 ==
5437 14:00:08.933635 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 14:00:08.937186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 14:00:08.937263 ==
5440 14:00:08.940402 RX Vref Scan: 0
5441 14:00:08.940504
5442 14:00:08.940594 RX Vref 0 -> 0, step: 1
5443 14:00:08.943502
5444 14:00:08.943597 RX Delay -45 -> 252, step: 4
5445 14:00:08.951030 iDelay=195, Bit 0, Center 102 (15 ~ 190) 176
5446 14:00:08.954383 iDelay=195, Bit 1, Center 106 (19 ~ 194) 176
5447 14:00:08.957657 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5448 14:00:08.961421 iDelay=195, Bit 3, Center 102 (15 ~ 190) 176
5449 14:00:08.964260 iDelay=195, Bit 4, Center 106 (19 ~ 194) 176
5450 14:00:08.970803 iDelay=195, Bit 5, Center 96 (7 ~ 186) 180
5451 14:00:08.974483 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5452 14:00:08.977498 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5453 14:00:08.981151 iDelay=195, Bit 8, Center 88 (7 ~ 170) 164
5454 14:00:08.984169 iDelay=195, Bit 9, Center 84 (-1 ~ 170) 172
5455 14:00:08.987618 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5456 14:00:08.994287 iDelay=195, Bit 11, Center 88 (7 ~ 170) 164
5457 14:00:08.997410 iDelay=195, Bit 12, Center 98 (15 ~ 182) 168
5458 14:00:09.000732 iDelay=195, Bit 13, Center 98 (15 ~ 182) 168
5459 14:00:09.004299 iDelay=195, Bit 14, Center 104 (19 ~ 190) 172
5460 14:00:09.007400 iDelay=195, Bit 15, Center 102 (19 ~ 186) 168
5461 14:00:09.010812 ==
5462 14:00:09.014258 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 14:00:09.017415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 14:00:09.017489 ==
5465 14:00:09.017552 DQS Delay:
5466 14:00:09.020552 DQS0 = 0, DQS1 = 0
5467 14:00:09.020626 DQM Delay:
5468 14:00:09.024238 DQM0 = 104, DQM1 = 94
5469 14:00:09.024324 DQ Delay:
5470 14:00:09.027202 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5471 14:00:09.031083 DQ4 =106, DQ5 =96, DQ6 =108, DQ7 =110
5472 14:00:09.034353 DQ8 =88, DQ9 =84, DQ10 =94, DQ11 =88
5473 14:00:09.037090 DQ12 =98, DQ13 =98, DQ14 =104, DQ15 =102
5474 14:00:09.037186
5475 14:00:09.037249
5476 14:00:09.047682 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 407 ps
5477 14:00:09.047781 CH0 RK1: MR19=505, MR18=2D05
5478 14:00:09.053931 CH0_RK1: MR19=0x505, MR18=0x2D05, DQSOSC=407, MR23=63, INC=65, DEC=43
5479 14:00:09.057067 [RxdqsGatingPostProcess] freq 933
5480 14:00:09.063910 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5481 14:00:09.067538 best DQS0 dly(2T, 0.5T) = (0, 10)
5482 14:00:09.070670 best DQS1 dly(2T, 0.5T) = (0, 11)
5483 14:00:09.074210 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5484 14:00:09.077341 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5485 14:00:09.080838 best DQS0 dly(2T, 0.5T) = (0, 10)
5486 14:00:09.080943 best DQS1 dly(2T, 0.5T) = (0, 10)
5487 14:00:09.083645 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5488 14:00:09.087224 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5489 14:00:09.090222 Pre-setting of DQS Precalculation
5490 14:00:09.097478 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5491 14:00:09.097558 ==
5492 14:00:09.100614 Dram Type= 6, Freq= 0, CH_1, rank 0
5493 14:00:09.103683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5494 14:00:09.103794 ==
5495 14:00:09.110158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5496 14:00:09.117068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5497 14:00:09.120425 [CA 0] Center 36 (6~67) winsize 62
5498 14:00:09.123916 [CA 1] Center 37 (6~68) winsize 63
5499 14:00:09.126944 [CA 2] Center 34 (4~65) winsize 62
5500 14:00:09.130628 [CA 3] Center 34 (4~65) winsize 62
5501 14:00:09.133742 [CA 4] Center 34 (4~64) winsize 61
5502 14:00:09.137060 [CA 5] Center 33 (3~64) winsize 62
5503 14:00:09.137146
5504 14:00:09.140167 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5505 14:00:09.140244
5506 14:00:09.143505 [CATrainingPosCal] consider 1 rank data
5507 14:00:09.147210 u2DelayCellTimex100 = 270/100 ps
5508 14:00:09.150425 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5509 14:00:09.153855 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5510 14:00:09.156645 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5511 14:00:09.160045 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5512 14:00:09.163319 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5513 14:00:09.167038 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5514 14:00:09.167115
5515 14:00:09.170231 CA PerBit enable=1, Macro0, CA PI delay=33
5516 14:00:09.173346
5517 14:00:09.173456 [CBTSetCACLKResult] CA Dly = 33
5518 14:00:09.176972 CS Dly: 6 (0~37)
5519 14:00:09.177079 ==
5520 14:00:09.180330 Dram Type= 6, Freq= 0, CH_1, rank 1
5521 14:00:09.183415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 14:00:09.183525 ==
5523 14:00:09.190107 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 14:00:09.196798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5525 14:00:09.200492 [CA 0] Center 36 (6~67) winsize 62
5526 14:00:09.203470 [CA 1] Center 37 (7~68) winsize 62
5527 14:00:09.206790 [CA 2] Center 35 (5~65) winsize 61
5528 14:00:09.210431 [CA 3] Center 34 (4~65) winsize 62
5529 14:00:09.213636 [CA 4] Center 34 (4~65) winsize 62
5530 14:00:09.216569 [CA 5] Center 33 (3~64) winsize 62
5531 14:00:09.216689
5532 14:00:09.220232 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5533 14:00:09.220338
5534 14:00:09.223571 [CATrainingPosCal] consider 2 rank data
5535 14:00:09.226961 u2DelayCellTimex100 = 270/100 ps
5536 14:00:09.230290 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5537 14:00:09.233662 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5538 14:00:09.236546 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5539 14:00:09.239973 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5540 14:00:09.243332 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5541 14:00:09.247031 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5542 14:00:09.247109
5543 14:00:09.250128 CA PerBit enable=1, Macro0, CA PI delay=33
5544 14:00:09.253448
5545 14:00:09.253526 [CBTSetCACLKResult] CA Dly = 33
5546 14:00:09.256650 CS Dly: 7 (0~40)
5547 14:00:09.256756
5548 14:00:09.260031 ----->DramcWriteLeveling(PI) begin...
5549 14:00:09.260131 ==
5550 14:00:09.263090 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 14:00:09.266672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 14:00:09.266776 ==
5553 14:00:09.270032 Write leveling (Byte 0): 27 => 27
5554 14:00:09.273775 Write leveling (Byte 1): 28 => 28
5555 14:00:09.276558 DramcWriteLeveling(PI) end<-----
5556 14:00:09.276668
5557 14:00:09.276766 ==
5558 14:00:09.279833 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 14:00:09.283292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 14:00:09.286409 ==
5561 14:00:09.286520 [Gating] SW mode calibration
5562 14:00:09.293580 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5563 14:00:09.300256 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5564 14:00:09.303340 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 14:00:09.309810 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 14:00:09.313530 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 14:00:09.316756 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 14:00:09.323137 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 14:00:09.326624 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5570 14:00:09.329898 0 14 24 | B1->B0 | 3434 2e2e | 0 0 | (1 0) (1 0)
5571 14:00:09.336309 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5572 14:00:09.339879 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 14:00:09.342999 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 14:00:09.349922 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 14:00:09.353218 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 14:00:09.356370 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 14:00:09.362921 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 14:00:09.366186 0 15 24 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
5579 14:00:09.369551 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5580 14:00:09.372895 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 14:00:09.379590 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 14:00:09.382884 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 14:00:09.386472 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 14:00:09.392887 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 14:00:09.396609 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 14:00:09.399811 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5587 14:00:09.406313 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5588 14:00:09.409444 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 14:00:09.413012 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 14:00:09.419545 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 14:00:09.423150 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 14:00:09.426229 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 14:00:09.432545 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 14:00:09.435896 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 14:00:09.439154 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 14:00:09.445653 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 14:00:09.449375 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 14:00:09.452876 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 14:00:09.459285 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 14:00:09.462487 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 14:00:09.465592 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 14:00:09.472319 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5603 14:00:09.476138 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 14:00:09.479181 Total UI for P1: 0, mck2ui 16
5605 14:00:09.482465 best dqsien dly found for B0: ( 1, 2, 24)
5606 14:00:09.486269 Total UI for P1: 0, mck2ui 16
5607 14:00:09.488859 best dqsien dly found for B1: ( 1, 2, 24)
5608 14:00:09.492210 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5609 14:00:09.495809 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5610 14:00:09.495885
5611 14:00:09.498800 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5612 14:00:09.502219 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5613 14:00:09.505551 [Gating] SW calibration Done
5614 14:00:09.505625 ==
5615 14:00:09.508959 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 14:00:09.512299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 14:00:09.515450 ==
5618 14:00:09.515557 RX Vref Scan: 0
5619 14:00:09.515656
5620 14:00:09.519273 RX Vref 0 -> 0, step: 1
5621 14:00:09.519345
5622 14:00:09.519406 RX Delay -80 -> 252, step: 8
5623 14:00:09.525527 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5624 14:00:09.529071 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5625 14:00:09.532306 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5626 14:00:09.535816 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5627 14:00:09.539096 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5628 14:00:09.542551 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5629 14:00:09.549025 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5630 14:00:09.552417 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5631 14:00:09.555901 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5632 14:00:09.558953 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5633 14:00:09.562538 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5634 14:00:09.565883 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5635 14:00:09.572477 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5636 14:00:09.575665 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5637 14:00:09.578601 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5638 14:00:09.582508 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5639 14:00:09.582588 ==
5640 14:00:09.585596 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 14:00:09.591920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 14:00:09.592029 ==
5643 14:00:09.592134 DQS Delay:
5644 14:00:09.595606 DQS0 = 0, DQS1 = 0
5645 14:00:09.595727 DQM Delay:
5646 14:00:09.595822 DQM0 = 102, DQM1 = 98
5647 14:00:09.598840 DQ Delay:
5648 14:00:09.602106 DQ0 =103, DQ1 =99, DQ2 =91, DQ3 =99
5649 14:00:09.605839 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5650 14:00:09.609090 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5651 14:00:09.612479 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5652 14:00:09.612585
5653 14:00:09.612695
5654 14:00:09.612795 ==
5655 14:00:09.615757 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 14:00:09.618773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 14:00:09.618876 ==
5658 14:00:09.618977
5659 14:00:09.619081
5660 14:00:09.622137 TX Vref Scan disable
5661 14:00:09.625524 == TX Byte 0 ==
5662 14:00:09.628575 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5663 14:00:09.632053 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5664 14:00:09.635701 == TX Byte 1 ==
5665 14:00:09.638693 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5666 14:00:09.641831 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5667 14:00:09.641927 ==
5668 14:00:09.645482 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 14:00:09.648535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 14:00:09.652196 ==
5671 14:00:09.652271
5672 14:00:09.652334
5673 14:00:09.652393 TX Vref Scan disable
5674 14:00:09.655911 == TX Byte 0 ==
5675 14:00:09.659037 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5676 14:00:09.665515 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5677 14:00:09.665600 == TX Byte 1 ==
5678 14:00:09.669166 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5679 14:00:09.676223 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5680 14:00:09.676310
5681 14:00:09.676397 [DATLAT]
5682 14:00:09.676478 Freq=933, CH1 RK0
5683 14:00:09.676558
5684 14:00:09.678998 DATLAT Default: 0xd
5685 14:00:09.679137 0, 0xFFFF, sum = 0
5686 14:00:09.682459 1, 0xFFFF, sum = 0
5687 14:00:09.682561 2, 0xFFFF, sum = 0
5688 14:00:09.685829 3, 0xFFFF, sum = 0
5689 14:00:09.688701 4, 0xFFFF, sum = 0
5690 14:00:09.688790 5, 0xFFFF, sum = 0
5691 14:00:09.692243 6, 0xFFFF, sum = 0
5692 14:00:09.692330 7, 0xFFFF, sum = 0
5693 14:00:09.695722 8, 0xFFFF, sum = 0
5694 14:00:09.695809 9, 0xFFFF, sum = 0
5695 14:00:09.698733 10, 0x0, sum = 1
5696 14:00:09.698820 11, 0x0, sum = 2
5697 14:00:09.702218 12, 0x0, sum = 3
5698 14:00:09.702320 13, 0x0, sum = 4
5699 14:00:09.702407 best_step = 11
5700 14:00:09.702488
5701 14:00:09.705460 ==
5702 14:00:09.708707 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 14:00:09.712164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 14:00:09.712248 ==
5705 14:00:09.712333 RX Vref Scan: 1
5706 14:00:09.712412
5707 14:00:09.715812 RX Vref 0 -> 0, step: 1
5708 14:00:09.715896
5709 14:00:09.718898 RX Delay -45 -> 252, step: 4
5710 14:00:09.718974
5711 14:00:09.722042 Set Vref, RX VrefLevel [Byte0]: 53
5712 14:00:09.725492 [Byte1]: 53
5713 14:00:09.725597
5714 14:00:09.728820 Final RX Vref Byte 0 = 53 to rank0
5715 14:00:09.732100 Final RX Vref Byte 1 = 53 to rank0
5716 14:00:09.735187 Final RX Vref Byte 0 = 53 to rank1
5717 14:00:09.738406 Final RX Vref Byte 1 = 53 to rank1==
5718 14:00:09.741948 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 14:00:09.745748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 14:00:09.745835 ==
5721 14:00:09.748625 DQS Delay:
5722 14:00:09.748710 DQS0 = 0, DQS1 = 0
5723 14:00:09.752470 DQM Delay:
5724 14:00:09.752555 DQM0 = 103, DQM1 = 99
5725 14:00:09.752657 DQ Delay:
5726 14:00:09.755506 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5727 14:00:09.758567 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5728 14:00:09.762178 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =92
5729 14:00:09.768795 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5730 14:00:09.768880
5731 14:00:09.768963
5732 14:00:09.775418 [DQSOSCAuto] RK0, (LSB)MR18= 0x182f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5733 14:00:09.778820 CH1 RK0: MR19=505, MR18=182F
5734 14:00:09.785528 CH1_RK0: MR19=0x505, MR18=0x182F, DQSOSC=407, MR23=63, INC=65, DEC=43
5735 14:00:09.785610
5736 14:00:09.788395 ----->DramcWriteLeveling(PI) begin...
5737 14:00:09.788483 ==
5738 14:00:09.791929 Dram Type= 6, Freq= 0, CH_1, rank 1
5739 14:00:09.795404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 14:00:09.795511 ==
5741 14:00:09.798948 Write leveling (Byte 0): 28 => 28
5742 14:00:09.801885 Write leveling (Byte 1): 29 => 29
5743 14:00:09.805054 DramcWriteLeveling(PI) end<-----
5744 14:00:09.805132
5745 14:00:09.805214 ==
5746 14:00:09.808473 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 14:00:09.812305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 14:00:09.812415 ==
5749 14:00:09.815670 [Gating] SW mode calibration
5750 14:00:09.822196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5751 14:00:09.828946 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5752 14:00:09.832154 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 14:00:09.835570 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 14:00:09.842130 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 14:00:09.845786 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 14:00:09.849014 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 14:00:09.855890 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 14:00:09.859058 0 14 24 | B1->B0 | 2c2c 2f2f | 0 0 | (0 0) (0 0)
5759 14:00:09.862007 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5760 14:00:09.868462 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 14:00:09.872019 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 14:00:09.875693 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 14:00:09.882036 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 14:00:09.885049 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 14:00:09.888794 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 14:00:09.895224 0 15 24 | B1->B0 | 3939 2424 | 0 0 | (0 0) (0 0)
5767 14:00:09.898972 0 15 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5768 14:00:09.901834 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 14:00:09.908393 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 14:00:09.912103 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 14:00:09.915372 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 14:00:09.921757 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 14:00:09.925327 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 14:00:09.928447 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5775 14:00:09.935740 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 14:00:09.938388 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 14:00:09.941835 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 14:00:09.948427 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 14:00:09.951813 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 14:00:09.955225 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 14:00:09.958688 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 14:00:09.965569 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 14:00:09.968473 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 14:00:09.972227 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 14:00:09.979046 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 14:00:09.981636 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 14:00:09.985047 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 14:00:09.991634 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 14:00:09.995311 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 14:00:09.998310 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5791 14:00:10.005485 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5792 14:00:10.005594 Total UI for P1: 0, mck2ui 16
5793 14:00:10.012069 best dqsien dly found for B0: ( 1, 2, 24)
5794 14:00:10.015689 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 14:00:10.018377 Total UI for P1: 0, mck2ui 16
5796 14:00:10.022028 best dqsien dly found for B1: ( 1, 2, 26)
5797 14:00:10.025458 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5798 14:00:10.028638 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5799 14:00:10.028741
5800 14:00:10.032365 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5801 14:00:10.035216 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5802 14:00:10.038545 [Gating] SW calibration Done
5803 14:00:10.038654 ==
5804 14:00:10.042454 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 14:00:10.045650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 14:00:10.045762 ==
5807 14:00:10.048784 RX Vref Scan: 0
5808 14:00:10.048868
5809 14:00:10.052119 RX Vref 0 -> 0, step: 1
5810 14:00:10.052203
5811 14:00:10.052269 RX Delay -80 -> 252, step: 8
5812 14:00:10.059497 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5813 14:00:10.062109 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5814 14:00:10.065501 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5815 14:00:10.069205 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5816 14:00:10.072161 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5817 14:00:10.075124 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5818 14:00:10.082031 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5819 14:00:10.085233 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5820 14:00:10.088768 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5821 14:00:10.091656 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5822 14:00:10.095551 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5823 14:00:10.098696 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5824 14:00:10.105125 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5825 14:00:10.108674 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5826 14:00:10.111905 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5827 14:00:10.115293 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5828 14:00:10.115397 ==
5829 14:00:10.118527 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 14:00:10.125007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 14:00:10.125116 ==
5832 14:00:10.125213 DQS Delay:
5833 14:00:10.125315 DQS0 = 0, DQS1 = 0
5834 14:00:10.128664 DQM Delay:
5835 14:00:10.128769 DQM0 = 103, DQM1 = 99
5836 14:00:10.132351 DQ Delay:
5837 14:00:10.135013 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =99
5838 14:00:10.138608 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5839 14:00:10.141673 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5840 14:00:10.145089 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5841 14:00:10.145193
5842 14:00:10.145285
5843 14:00:10.145377 ==
5844 14:00:10.148462 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 14:00:10.152083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 14:00:10.152175 ==
5847 14:00:10.152250
5848 14:00:10.152352
5849 14:00:10.154762 TX Vref Scan disable
5850 14:00:10.158251 == TX Byte 0 ==
5851 14:00:10.161440 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5852 14:00:10.164855 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5853 14:00:10.168188 == TX Byte 1 ==
5854 14:00:10.171276 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5855 14:00:10.174730 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5856 14:00:10.174837 ==
5857 14:00:10.178414 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 14:00:10.181468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 14:00:10.185263 ==
5860 14:00:10.185364
5861 14:00:10.185456
5862 14:00:10.185559 TX Vref Scan disable
5863 14:00:10.188443 == TX Byte 0 ==
5864 14:00:10.192197 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5865 14:00:10.198224 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5866 14:00:10.198327 == TX Byte 1 ==
5867 14:00:10.201863 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5868 14:00:10.208077 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5869 14:00:10.208182
5870 14:00:10.208278 [DATLAT]
5871 14:00:10.208373 Freq=933, CH1 RK1
5872 14:00:10.208470
5873 14:00:10.211775 DATLAT Default: 0xb
5874 14:00:10.211879 0, 0xFFFF, sum = 0
5875 14:00:10.215573 1, 0xFFFF, sum = 0
5876 14:00:10.215692 2, 0xFFFF, sum = 0
5877 14:00:10.218245 3, 0xFFFF, sum = 0
5878 14:00:10.221350 4, 0xFFFF, sum = 0
5879 14:00:10.221452 5, 0xFFFF, sum = 0
5880 14:00:10.224950 6, 0xFFFF, sum = 0
5881 14:00:10.225055 7, 0xFFFF, sum = 0
5882 14:00:10.228506 8, 0xFFFF, sum = 0
5883 14:00:10.228609 9, 0xFFFF, sum = 0
5884 14:00:10.231568 10, 0x0, sum = 1
5885 14:00:10.231703 11, 0x0, sum = 2
5886 14:00:10.235089 12, 0x0, sum = 3
5887 14:00:10.235194 13, 0x0, sum = 4
5888 14:00:10.235304 best_step = 11
5889 14:00:10.235434
5890 14:00:10.238061 ==
5891 14:00:10.238162 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 14:00:10.244630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 14:00:10.244736 ==
5894 14:00:10.244831 RX Vref Scan: 0
5895 14:00:10.244920
5896 14:00:10.248256 RX Vref 0 -> 0, step: 1
5897 14:00:10.248355
5898 14:00:10.251702 RX Delay -45 -> 252, step: 4
5899 14:00:10.254950 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5900 14:00:10.261614 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5901 14:00:10.265029 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5902 14:00:10.267957 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5903 14:00:10.271412 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5904 14:00:10.274525 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5905 14:00:10.281962 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5906 14:00:10.285224 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5907 14:00:10.288071 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5908 14:00:10.291355 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5909 14:00:10.294633 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5910 14:00:10.297797 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5911 14:00:10.304684 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5912 14:00:10.308177 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5913 14:00:10.311312 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5914 14:00:10.314667 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5915 14:00:10.314746 ==
5916 14:00:10.318256 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 14:00:10.324917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 14:00:10.325000 ==
5919 14:00:10.325071 DQS Delay:
5920 14:00:10.325132 DQS0 = 0, DQS1 = 0
5921 14:00:10.328005 DQM Delay:
5922 14:00:10.328109 DQM0 = 104, DQM1 = 99
5923 14:00:10.331428 DQ Delay:
5924 14:00:10.335081 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5925 14:00:10.338286 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5926 14:00:10.341348 DQ8 =92, DQ9 =90, DQ10 =98, DQ11 =94
5927 14:00:10.344808 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5928 14:00:10.344918
5929 14:00:10.345009
5930 14:00:10.351301 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5931 14:00:10.354589 CH1 RK1: MR19=505, MR18=2E01
5932 14:00:10.361378 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5933 14:00:10.364853 [RxdqsGatingPostProcess] freq 933
5934 14:00:10.371400 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5935 14:00:10.371483 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 14:00:10.374962 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 14:00:10.377728 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 14:00:10.381320 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 14:00:10.384389 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 14:00:10.387629 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 14:00:10.390895 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 14:00:10.394342 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 14:00:10.397973 Pre-setting of DQS Precalculation
5944 14:00:10.404833 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5945 14:00:10.411672 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5946 14:00:10.418012 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5947 14:00:10.418097
5948 14:00:10.418164
5949 14:00:10.421902 [Calibration Summary] 1866 Mbps
5950 14:00:10.421977 CH 0, Rank 0
5951 14:00:10.424689 SW Impedance : PASS
5952 14:00:10.424812 DUTY Scan : NO K
5953 14:00:10.428381 ZQ Calibration : PASS
5954 14:00:10.431440 Jitter Meter : NO K
5955 14:00:10.431563 CBT Training : PASS
5956 14:00:10.434977 Write leveling : PASS
5957 14:00:10.438257 RX DQS gating : PASS
5958 14:00:10.438386 RX DQ/DQS(RDDQC) : PASS
5959 14:00:10.441636 TX DQ/DQS : PASS
5960 14:00:10.444942 RX DATLAT : PASS
5961 14:00:10.445063 RX DQ/DQS(Engine): PASS
5962 14:00:10.448353 TX OE : NO K
5963 14:00:10.448485 All Pass.
5964 14:00:10.448597
5965 14:00:10.451323 CH 0, Rank 1
5966 14:00:10.451456 SW Impedance : PASS
5967 14:00:10.454910 DUTY Scan : NO K
5968 14:00:10.455033 ZQ Calibration : PASS
5969 14:00:10.458472 Jitter Meter : NO K
5970 14:00:10.461503 CBT Training : PASS
5971 14:00:10.461633 Write leveling : PASS
5972 14:00:10.464805 RX DQS gating : PASS
5973 14:00:10.467994 RX DQ/DQS(RDDQC) : PASS
5974 14:00:10.468124 TX DQ/DQS : PASS
5975 14:00:10.471728 RX DATLAT : PASS
5976 14:00:10.474751 RX DQ/DQS(Engine): PASS
5977 14:00:10.474872 TX OE : NO K
5978 14:00:10.477816 All Pass.
5979 14:00:10.477941
5980 14:00:10.478064 CH 1, Rank 0
5981 14:00:10.481259 SW Impedance : PASS
5982 14:00:10.481381 DUTY Scan : NO K
5983 14:00:10.484689 ZQ Calibration : PASS
5984 14:00:10.487800 Jitter Meter : NO K
5985 14:00:10.487921 CBT Training : PASS
5986 14:00:10.491557 Write leveling : PASS
5987 14:00:10.494409 RX DQS gating : PASS
5988 14:00:10.494538 RX DQ/DQS(RDDQC) : PASS
5989 14:00:10.497948 TX DQ/DQS : PASS
5990 14:00:10.501231 RX DATLAT : PASS
5991 14:00:10.501362 RX DQ/DQS(Engine): PASS
5992 14:00:10.504666 TX OE : NO K
5993 14:00:10.504801 All Pass.
5994 14:00:10.504913
5995 14:00:10.507694 CH 1, Rank 1
5996 14:00:10.507827 SW Impedance : PASS
5997 14:00:10.510830 DUTY Scan : NO K
5998 14:00:10.514194 ZQ Calibration : PASS
5999 14:00:10.514326 Jitter Meter : NO K
6000 14:00:10.517550 CBT Training : PASS
6001 14:00:10.517672 Write leveling : PASS
6002 14:00:10.521249 RX DQS gating : PASS
6003 14:00:10.524227 RX DQ/DQS(RDDQC) : PASS
6004 14:00:10.524330 TX DQ/DQS : PASS
6005 14:00:10.527903 RX DATLAT : PASS
6006 14:00:10.531408 RX DQ/DQS(Engine): PASS
6007 14:00:10.531508 TX OE : NO K
6008 14:00:10.534448 All Pass.
6009 14:00:10.534571
6010 14:00:10.534694 DramC Write-DBI off
6011 14:00:10.537641 PER_BANK_REFRESH: Hybrid Mode
6012 14:00:10.540910 TX_TRACKING: ON
6013 14:00:10.547750 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6014 14:00:10.551100 [FAST_K] Save calibration result to emmc
6015 14:00:10.554323 dramc_set_vcore_voltage set vcore to 650000
6016 14:00:10.557575 Read voltage for 400, 6
6017 14:00:10.557659 Vio18 = 0
6018 14:00:10.561074 Vcore = 650000
6019 14:00:10.561208 Vdram = 0
6020 14:00:10.561324 Vddq = 0
6021 14:00:10.564201 Vmddr = 0
6022 14:00:10.567973 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6023 14:00:10.574404 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6024 14:00:10.574485 MEM_TYPE=3, freq_sel=20
6025 14:00:10.577208 sv_algorithm_assistance_LP4_800
6026 14:00:10.583983 ============ PULL DRAM RESETB DOWN ============
6027 14:00:10.587223 ========== PULL DRAM RESETB DOWN end =========
6028 14:00:10.590634 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6029 14:00:10.594141 ===================================
6030 14:00:10.597104 LPDDR4 DRAM CONFIGURATION
6031 14:00:10.600770 ===================================
6032 14:00:10.600883 EX_ROW_EN[0] = 0x0
6033 14:00:10.603789 EX_ROW_EN[1] = 0x0
6034 14:00:10.607339 LP4Y_EN = 0x0
6035 14:00:10.607457 WORK_FSP = 0x0
6036 14:00:10.610793 WL = 0x2
6037 14:00:10.610869 RL = 0x2
6038 14:00:10.614062 BL = 0x2
6039 14:00:10.614169 RPST = 0x0
6040 14:00:10.617066 RD_PRE = 0x0
6041 14:00:10.617170 WR_PRE = 0x1
6042 14:00:10.620331 WR_PST = 0x0
6043 14:00:10.620442 DBI_WR = 0x0
6044 14:00:10.624171 DBI_RD = 0x0
6045 14:00:10.624284 OTF = 0x1
6046 14:00:10.627143 ===================================
6047 14:00:10.630799 ===================================
6048 14:00:10.634067 ANA top config
6049 14:00:10.637188 ===================================
6050 14:00:10.637272 DLL_ASYNC_EN = 0
6051 14:00:10.640536 ALL_SLAVE_EN = 1
6052 14:00:10.643715 NEW_RANK_MODE = 1
6053 14:00:10.647405 DLL_IDLE_MODE = 1
6054 14:00:10.650548 LP45_APHY_COMB_EN = 1
6055 14:00:10.650647 TX_ODT_DIS = 1
6056 14:00:10.653650 NEW_8X_MODE = 1
6057 14:00:10.657175 ===================================
6058 14:00:10.660722 ===================================
6059 14:00:10.663565 data_rate = 800
6060 14:00:10.666797 CKR = 1
6061 14:00:10.670418 DQ_P2S_RATIO = 4
6062 14:00:10.673916 ===================================
6063 14:00:10.673990 CA_P2S_RATIO = 4
6064 14:00:10.677164 DQ_CA_OPEN = 0
6065 14:00:10.680548 DQ_SEMI_OPEN = 1
6066 14:00:10.683655 CA_SEMI_OPEN = 1
6067 14:00:10.687334 CA_FULL_RATE = 0
6068 14:00:10.690078 DQ_CKDIV4_EN = 0
6069 14:00:10.690169 CA_CKDIV4_EN = 1
6070 14:00:10.693702 CA_PREDIV_EN = 0
6071 14:00:10.697107 PH8_DLY = 0
6072 14:00:10.700481 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6073 14:00:10.703632 DQ_AAMCK_DIV = 0
6074 14:00:10.706911 CA_AAMCK_DIV = 0
6075 14:00:10.707017 CA_ADMCK_DIV = 4
6076 14:00:10.710442 DQ_TRACK_CA_EN = 0
6077 14:00:10.713677 CA_PICK = 800
6078 14:00:10.717127 CA_MCKIO = 400
6079 14:00:10.720125 MCKIO_SEMI = 400
6080 14:00:10.723553 PLL_FREQ = 3016
6081 14:00:10.726980 DQ_UI_PI_RATIO = 32
6082 14:00:10.730698 CA_UI_PI_RATIO = 32
6083 14:00:10.730798 ===================================
6084 14:00:10.733716 ===================================
6085 14:00:10.737278 memory_type:LPDDR4
6086 14:00:10.739998 GP_NUM : 10
6087 14:00:10.740073 SRAM_EN : 1
6088 14:00:10.743734 MD32_EN : 0
6089 14:00:10.746811 ===================================
6090 14:00:10.750306 [ANA_INIT] >>>>>>>>>>>>>>
6091 14:00:10.753726 <<<<<< [CONFIGURE PHASE]: ANA_TX
6092 14:00:10.756578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6093 14:00:10.760454 ===================================
6094 14:00:10.760588 data_rate = 800,PCW = 0X7400
6095 14:00:10.763713 ===================================
6096 14:00:10.766652 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6097 14:00:10.773729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 14:00:10.786485 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 14:00:10.789906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6100 14:00:10.793319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6101 14:00:10.796541 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6102 14:00:10.799945 [ANA_INIT] flow start
6103 14:00:10.800019 [ANA_INIT] PLL >>>>>>>>
6104 14:00:10.803431 [ANA_INIT] PLL <<<<<<<<
6105 14:00:10.806923 [ANA_INIT] MIDPI >>>>>>>>
6106 14:00:10.807033 [ANA_INIT] MIDPI <<<<<<<<
6107 14:00:10.810198 [ANA_INIT] DLL >>>>>>>>
6108 14:00:10.813386 [ANA_INIT] flow end
6109 14:00:10.816576 ============ LP4 DIFF to SE enter ============
6110 14:00:10.820026 ============ LP4 DIFF to SE exit ============
6111 14:00:10.823170 [ANA_INIT] <<<<<<<<<<<<<
6112 14:00:10.826549 [Flow] Enable top DCM control >>>>>
6113 14:00:10.829691 [Flow] Enable top DCM control <<<<<
6114 14:00:10.833184 Enable DLL master slave shuffle
6115 14:00:10.836144 ==============================================================
6116 14:00:10.839599 Gating Mode config
6117 14:00:10.846479 ==============================================================
6118 14:00:10.846592 Config description:
6119 14:00:10.856229 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6120 14:00:10.863376 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6121 14:00:10.866632 SELPH_MODE 0: By rank 1: By Phase
6122 14:00:10.873102 ==============================================================
6123 14:00:10.876328 GAT_TRACK_EN = 0
6124 14:00:10.879951 RX_GATING_MODE = 2
6125 14:00:10.882941 RX_GATING_TRACK_MODE = 2
6126 14:00:10.886675 SELPH_MODE = 1
6127 14:00:10.889665 PICG_EARLY_EN = 1
6128 14:00:10.893015 VALID_LAT_VALUE = 1
6129 14:00:10.896067 ==============================================================
6130 14:00:10.899648 Enter into Gating configuration >>>>
6131 14:00:10.902794 Exit from Gating configuration <<<<
6132 14:00:10.906462 Enter into DVFS_PRE_config >>>>>
6133 14:00:10.919723 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6134 14:00:10.919810 Exit from DVFS_PRE_config <<<<<
6135 14:00:10.922912 Enter into PICG configuration >>>>
6136 14:00:10.926350 Exit from PICG configuration <<<<
6137 14:00:10.929838 [RX_INPUT] configuration >>>>>
6138 14:00:10.932778 [RX_INPUT] configuration <<<<<
6139 14:00:10.939351 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6140 14:00:10.942959 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6141 14:00:10.949948 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 14:00:10.956336 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 14:00:10.963042 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 14:00:10.969907 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 14:00:10.972715 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6146 14:00:10.976327 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6147 14:00:10.979197 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6148 14:00:10.986076 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6149 14:00:10.989783 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6150 14:00:10.993007 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6151 14:00:10.995928 ===================================
6152 14:00:10.999585 LPDDR4 DRAM CONFIGURATION
6153 14:00:11.002768 ===================================
6154 14:00:11.002852 EX_ROW_EN[0] = 0x0
6155 14:00:11.006449 EX_ROW_EN[1] = 0x0
6156 14:00:11.009654 LP4Y_EN = 0x0
6157 14:00:11.009764 WORK_FSP = 0x0
6158 14:00:11.012987 WL = 0x2
6159 14:00:11.013100 RL = 0x2
6160 14:00:11.016003 BL = 0x2
6161 14:00:11.016078 RPST = 0x0
6162 14:00:11.019500 RD_PRE = 0x0
6163 14:00:11.019607 WR_PRE = 0x1
6164 14:00:11.022696 WR_PST = 0x0
6165 14:00:11.022811 DBI_WR = 0x0
6166 14:00:11.026305 DBI_RD = 0x0
6167 14:00:11.026409 OTF = 0x1
6168 14:00:11.029433 ===================================
6169 14:00:11.032776 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6170 14:00:11.039283 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6171 14:00:11.042726 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 14:00:11.046281 ===================================
6173 14:00:11.049272 LPDDR4 DRAM CONFIGURATION
6174 14:00:11.052974 ===================================
6175 14:00:11.053079 EX_ROW_EN[0] = 0x10
6176 14:00:11.056102 EX_ROW_EN[1] = 0x0
6177 14:00:11.056209 LP4Y_EN = 0x0
6178 14:00:11.059648 WORK_FSP = 0x0
6179 14:00:11.059744 WL = 0x2
6180 14:00:11.062569 RL = 0x2
6181 14:00:11.065813 BL = 0x2
6182 14:00:11.065923 RPST = 0x0
6183 14:00:11.069364 RD_PRE = 0x0
6184 14:00:11.069445 WR_PRE = 0x1
6185 14:00:11.072394 WR_PST = 0x0
6186 14:00:11.072492 DBI_WR = 0x0
6187 14:00:11.076063 DBI_RD = 0x0
6188 14:00:11.076158 OTF = 0x1
6189 14:00:11.079115 ===================================
6190 14:00:11.086051 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6191 14:00:11.089949 nWR fixed to 30
6192 14:00:11.092724 [ModeRegInit_LP4] CH0 RK0
6193 14:00:11.092829 [ModeRegInit_LP4] CH0 RK1
6194 14:00:11.096383 [ModeRegInit_LP4] CH1 RK0
6195 14:00:11.099491 [ModeRegInit_LP4] CH1 RK1
6196 14:00:11.099601 match AC timing 19
6197 14:00:11.106229 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6198 14:00:11.109532 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6199 14:00:11.113150 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6200 14:00:11.119412 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6201 14:00:11.122603 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6202 14:00:11.122690 ==
6203 14:00:11.126198 Dram Type= 6, Freq= 0, CH_0, rank 0
6204 14:00:11.129459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6205 14:00:11.129536 ==
6206 14:00:11.136055 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6207 14:00:11.142505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6208 14:00:11.146528 [CA 0] Center 36 (8~64) winsize 57
6209 14:00:11.149344 [CA 1] Center 36 (8~64) winsize 57
6210 14:00:11.152790 [CA 2] Center 36 (8~64) winsize 57
6211 14:00:11.155754 [CA 3] Center 36 (8~64) winsize 57
6212 14:00:11.155838 [CA 4] Center 36 (8~64) winsize 57
6213 14:00:11.159358 [CA 5] Center 36 (8~64) winsize 57
6214 14:00:11.159441
6215 14:00:11.166127 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6216 14:00:11.166238
6217 14:00:11.169628 [CATrainingPosCal] consider 1 rank data
6218 14:00:11.173208 u2DelayCellTimex100 = 270/100 ps
6219 14:00:11.176177 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 14:00:11.179594 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 14:00:11.182950 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 14:00:11.186157 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 14:00:11.189788 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 14:00:11.192677 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 14:00:11.192760
6226 14:00:11.195931 CA PerBit enable=1, Macro0, CA PI delay=36
6227 14:00:11.196014
6228 14:00:11.199306 [CBTSetCACLKResult] CA Dly = 36
6229 14:00:11.202643 CS Dly: 1 (0~32)
6230 14:00:11.202726 ==
6231 14:00:11.206167 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 14:00:11.209325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 14:00:11.209409 ==
6234 14:00:11.216119 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 14:00:11.219303 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 14:00:11.222783 [CA 0] Center 36 (8~64) winsize 57
6237 14:00:11.225628 [CA 1] Center 36 (8~64) winsize 57
6238 14:00:11.229207 [CA 2] Center 36 (8~64) winsize 57
6239 14:00:11.232772 [CA 3] Center 36 (8~64) winsize 57
6240 14:00:11.236006 [CA 4] Center 36 (8~64) winsize 57
6241 14:00:11.239449 [CA 5] Center 36 (8~64) winsize 57
6242 14:00:11.239566
6243 14:00:11.242902 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 14:00:11.243021
6245 14:00:11.245855 [CATrainingPosCal] consider 2 rank data
6246 14:00:11.248986 u2DelayCellTimex100 = 270/100 ps
6247 14:00:11.252350 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 14:00:11.256335 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 14:00:11.259258 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 14:00:11.265976 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 14:00:11.269375 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 14:00:11.272467 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 14:00:11.272546
6254 14:00:11.276077 CA PerBit enable=1, Macro0, CA PI delay=36
6255 14:00:11.276185
6256 14:00:11.279087 [CBTSetCACLKResult] CA Dly = 36
6257 14:00:11.279160 CS Dly: 1 (0~32)
6258 14:00:11.279222
6259 14:00:11.282133 ----->DramcWriteLeveling(PI) begin...
6260 14:00:11.282229 ==
6261 14:00:11.285818 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 14:00:11.292596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 14:00:11.292680 ==
6264 14:00:11.295633 Write leveling (Byte 0): 40 => 8
6265 14:00:11.299087 Write leveling (Byte 1): 40 => 8
6266 14:00:11.299191 DramcWriteLeveling(PI) end<-----
6267 14:00:11.299283
6268 14:00:11.302728 ==
6269 14:00:11.306175 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 14:00:11.308838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 14:00:11.308953 ==
6272 14:00:11.312257 [Gating] SW mode calibration
6273 14:00:11.318956 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6274 14:00:11.322403 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6275 14:00:11.329129 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 14:00:11.332612 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 14:00:11.335500 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 14:00:11.342060 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 14:00:11.345515 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 14:00:11.349137 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 14:00:11.355560 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 14:00:11.359143 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 14:00:11.362825 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 14:00:11.365973 Total UI for P1: 0, mck2ui 16
6285 14:00:11.369144 best dqsien dly found for B0: ( 0, 14, 24)
6286 14:00:11.372695 Total UI for P1: 0, mck2ui 16
6287 14:00:11.375660 best dqsien dly found for B1: ( 0, 14, 24)
6288 14:00:11.379192 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6289 14:00:11.382666 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6290 14:00:11.382750
6291 14:00:11.385666 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 14:00:11.392258 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 14:00:11.392347 [Gating] SW calibration Done
6294 14:00:11.392413 ==
6295 14:00:11.395836 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 14:00:11.402603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 14:00:11.402691 ==
6298 14:00:11.402758 RX Vref Scan: 0
6299 14:00:11.402820
6300 14:00:11.405985 RX Vref 0 -> 0, step: 1
6301 14:00:11.406069
6302 14:00:11.409314 RX Delay -410 -> 252, step: 16
6303 14:00:11.412182 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6304 14:00:11.415802 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6305 14:00:11.422297 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6306 14:00:11.425759 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6307 14:00:11.429095 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6308 14:00:11.432348 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6309 14:00:11.439133 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6310 14:00:11.442352 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6311 14:00:11.445446 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6312 14:00:11.449228 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6313 14:00:11.455542 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6314 14:00:11.459300 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6315 14:00:11.462272 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6316 14:00:11.465962 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6317 14:00:11.472444 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6318 14:00:11.475825 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6319 14:00:11.475908 ==
6320 14:00:11.479035 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 14:00:11.482210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 14:00:11.482293 ==
6323 14:00:11.485649 DQS Delay:
6324 14:00:11.485738 DQS0 = 27, DQS1 = 35
6325 14:00:11.485804 DQM Delay:
6326 14:00:11.488907 DQM0 = 10, DQM1 = 12
6327 14:00:11.488982 DQ Delay:
6328 14:00:11.492668 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6329 14:00:11.495282 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6330 14:00:11.498902 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6331 14:00:11.502041 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6332 14:00:11.502113
6333 14:00:11.502180
6334 14:00:11.502237 ==
6335 14:00:11.505577 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 14:00:11.509134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 14:00:11.512103 ==
6338 14:00:11.512177
6339 14:00:11.512239
6340 14:00:11.512297 TX Vref Scan disable
6341 14:00:11.515652 == TX Byte 0 ==
6342 14:00:11.518614 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 14:00:11.522611 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 14:00:11.525395 == TX Byte 1 ==
6345 14:00:11.528899 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 14:00:11.531737 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 14:00:11.531818 ==
6348 14:00:11.535207 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 14:00:11.542189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 14:00:11.542277 ==
6351 14:00:11.542344
6352 14:00:11.542406
6353 14:00:11.542464 TX Vref Scan disable
6354 14:00:11.545120 == TX Byte 0 ==
6355 14:00:11.548390 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 14:00:11.552068 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 14:00:11.555155 == TX Byte 1 ==
6358 14:00:11.558481 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 14:00:11.561504 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 14:00:11.561587
6361 14:00:11.565271 [DATLAT]
6362 14:00:11.565354 Freq=400, CH0 RK0
6363 14:00:11.565419
6364 14:00:11.568167 DATLAT Default: 0xf
6365 14:00:11.568249 0, 0xFFFF, sum = 0
6366 14:00:11.571820 1, 0xFFFF, sum = 0
6367 14:00:11.571905 2, 0xFFFF, sum = 0
6368 14:00:11.575216 3, 0xFFFF, sum = 0
6369 14:00:11.575300 4, 0xFFFF, sum = 0
6370 14:00:11.578321 5, 0xFFFF, sum = 0
6371 14:00:11.578406 6, 0xFFFF, sum = 0
6372 14:00:11.581774 7, 0xFFFF, sum = 0
6373 14:00:11.581858 8, 0xFFFF, sum = 0
6374 14:00:11.585066 9, 0xFFFF, sum = 0
6375 14:00:11.585150 10, 0xFFFF, sum = 0
6376 14:00:11.588177 11, 0xFFFF, sum = 0
6377 14:00:11.591531 12, 0xFFFF, sum = 0
6378 14:00:11.591649 13, 0x0, sum = 1
6379 14:00:11.591719 14, 0x0, sum = 2
6380 14:00:11.594680 15, 0x0, sum = 3
6381 14:00:11.594755 16, 0x0, sum = 4
6382 14:00:11.597952 best_step = 14
6383 14:00:11.598027
6384 14:00:11.598098 ==
6385 14:00:11.601902 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 14:00:11.604729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 14:00:11.604804 ==
6388 14:00:11.608388 RX Vref Scan: 1
6389 14:00:11.608459
6390 14:00:11.608527 RX Vref 0 -> 0, step: 1
6391 14:00:11.611372
6392 14:00:11.611456 RX Delay -311 -> 252, step: 8
6393 14:00:11.611523
6394 14:00:11.615042 Set Vref, RX VrefLevel [Byte0]: 54
6395 14:00:11.617877 [Byte1]: 52
6396 14:00:11.623153
6397 14:00:11.623236 Final RX Vref Byte 0 = 54 to rank0
6398 14:00:11.626284 Final RX Vref Byte 1 = 52 to rank0
6399 14:00:11.629430 Final RX Vref Byte 0 = 54 to rank1
6400 14:00:11.633149 Final RX Vref Byte 1 = 52 to rank1==
6401 14:00:11.636279 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 14:00:11.642857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 14:00:11.642943 ==
6404 14:00:11.643045 DQS Delay:
6405 14:00:11.646089 DQS0 = 24, DQS1 = 36
6406 14:00:11.646170 DQM Delay:
6407 14:00:11.646235 DQM0 = 7, DQM1 = 13
6408 14:00:11.649596 DQ Delay:
6409 14:00:11.652718 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6410 14:00:11.652802 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6411 14:00:11.656198 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6412 14:00:11.659942 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6413 14:00:11.660054
6414 14:00:11.660153
6415 14:00:11.669875 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6416 14:00:11.673066 CH0 RK0: MR19=C0C, MR18=CBB8
6417 14:00:11.679343 CH0_RK0: MR19=0xC0C, MR18=0xCBB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6418 14:00:11.679429 ==
6419 14:00:11.682727 Dram Type= 6, Freq= 0, CH_0, rank 1
6420 14:00:11.686154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 14:00:11.686268 ==
6422 14:00:11.689482 [Gating] SW mode calibration
6423 14:00:11.696092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6424 14:00:11.699532 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6425 14:00:11.706410 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 14:00:11.709689 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 14:00:11.712736 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 14:00:11.719177 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 14:00:11.722878 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 14:00:11.725759 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 14:00:11.732583 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 14:00:11.735904 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 14:00:11.739544 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 14:00:11.742475 Total UI for P1: 0, mck2ui 16
6435 14:00:11.745969 best dqsien dly found for B0: ( 0, 14, 24)
6436 14:00:11.749429 Total UI for P1: 0, mck2ui 16
6437 14:00:11.752697 best dqsien dly found for B1: ( 0, 14, 24)
6438 14:00:11.755886 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6439 14:00:11.759299 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6440 14:00:11.759424
6441 14:00:11.765989 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 14:00:11.769402 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 14:00:11.772507 [Gating] SW calibration Done
6444 14:00:11.772634 ==
6445 14:00:11.775957 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 14:00:11.779299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 14:00:11.779427 ==
6448 14:00:11.779532 RX Vref Scan: 0
6449 14:00:11.779650
6450 14:00:11.782299 RX Vref 0 -> 0, step: 1
6451 14:00:11.782423
6452 14:00:11.785968 RX Delay -410 -> 252, step: 16
6453 14:00:11.789148 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6454 14:00:11.795920 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6455 14:00:11.799108 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6456 14:00:11.802145 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6457 14:00:11.805627 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6458 14:00:11.812194 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6459 14:00:11.815535 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6460 14:00:11.818563 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6461 14:00:11.822358 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6462 14:00:11.828909 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6463 14:00:11.831986 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6464 14:00:11.835506 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6465 14:00:11.838710 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6466 14:00:11.845207 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6467 14:00:11.848807 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6468 14:00:11.851743 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6469 14:00:11.851872 ==
6470 14:00:11.855351 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 14:00:11.858733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 14:00:11.862112 ==
6473 14:00:11.862238 DQS Delay:
6474 14:00:11.862347 DQS0 = 19, DQS1 = 35
6475 14:00:11.865080 DQM Delay:
6476 14:00:11.865199 DQM0 = 5, DQM1 = 11
6477 14:00:11.868291 DQ Delay:
6478 14:00:11.868430 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6479 14:00:11.871611 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6480 14:00:11.875491 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6481 14:00:11.878515 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6482 14:00:11.878632
6483 14:00:11.878756
6484 14:00:11.878868 ==
6485 14:00:11.882063 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 14:00:11.888527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 14:00:11.888655 ==
6488 14:00:11.888771
6489 14:00:11.888873
6490 14:00:11.889000 TX Vref Scan disable
6491 14:00:11.891600 == TX Byte 0 ==
6492 14:00:11.895137 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6493 14:00:11.898212 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6494 14:00:11.901633 == TX Byte 1 ==
6495 14:00:11.905058 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6496 14:00:11.908803 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6497 14:00:11.911841 ==
6498 14:00:11.914636 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 14:00:11.918680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 14:00:11.918819 ==
6501 14:00:11.918930
6502 14:00:11.919038
6503 14:00:11.921471 TX Vref Scan disable
6504 14:00:11.921578 == TX Byte 0 ==
6505 14:00:11.925094 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6506 14:00:11.931396 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6507 14:00:11.931533 == TX Byte 1 ==
6508 14:00:11.934762 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6509 14:00:11.938043 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6510 14:00:11.941421
6511 14:00:11.941507 [DATLAT]
6512 14:00:11.941572 Freq=400, CH0 RK1
6513 14:00:11.941634
6514 14:00:11.944435 DATLAT Default: 0xe
6515 14:00:11.944545 0, 0xFFFF, sum = 0
6516 14:00:11.948197 1, 0xFFFF, sum = 0
6517 14:00:11.948281 2, 0xFFFF, sum = 0
6518 14:00:11.951198 3, 0xFFFF, sum = 0
6519 14:00:11.951305 4, 0xFFFF, sum = 0
6520 14:00:11.954910 5, 0xFFFF, sum = 0
6521 14:00:11.958165 6, 0xFFFF, sum = 0
6522 14:00:11.958271 7, 0xFFFF, sum = 0
6523 14:00:11.961244 8, 0xFFFF, sum = 0
6524 14:00:11.961350 9, 0xFFFF, sum = 0
6525 14:00:11.964646 10, 0xFFFF, sum = 0
6526 14:00:11.964753 11, 0xFFFF, sum = 0
6527 14:00:11.967669 12, 0xFFFF, sum = 0
6528 14:00:11.967746 13, 0x0, sum = 1
6529 14:00:11.971152 14, 0x0, sum = 2
6530 14:00:11.971231 15, 0x0, sum = 3
6531 14:00:11.974526 16, 0x0, sum = 4
6532 14:00:11.974634 best_step = 14
6533 14:00:11.974727
6534 14:00:11.974816 ==
6535 14:00:11.977749 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 14:00:11.981182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 14:00:11.981288 ==
6538 14:00:11.984522 RX Vref Scan: 0
6539 14:00:11.984594
6540 14:00:11.987551 RX Vref 0 -> 0, step: 1
6541 14:00:11.987662
6542 14:00:11.987744 RX Delay -311 -> 252, step: 8
6543 14:00:11.996604 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6544 14:00:12.000135 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6545 14:00:12.003063 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6546 14:00:12.006861 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6547 14:00:12.013343 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6548 14:00:12.016298 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6549 14:00:12.019750 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6550 14:00:12.023546 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6551 14:00:12.029696 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6552 14:00:12.033303 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6553 14:00:12.036280 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6554 14:00:12.039920 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6555 14:00:12.046463 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6556 14:00:12.049933 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6557 14:00:12.053174 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6558 14:00:12.056522 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6559 14:00:12.060030 ==
6560 14:00:12.063187 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 14:00:12.066489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 14:00:12.066603 ==
6563 14:00:12.066701 DQS Delay:
6564 14:00:12.070011 DQS0 = 24, DQS1 = 32
6565 14:00:12.070119 DQM Delay:
6566 14:00:12.072947 DQM0 = 8, DQM1 = 9
6567 14:00:12.073058 DQ Delay:
6568 14:00:12.076558 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6569 14:00:12.079715 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6570 14:00:12.083353 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6571 14:00:12.086940 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6572 14:00:12.087017
6573 14:00:12.087081
6574 14:00:12.093158 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf5f, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6575 14:00:12.096573 CH0 RK1: MR19=C0C, MR18=BF5F
6576 14:00:12.103250 CH0_RK1: MR19=0xC0C, MR18=0xBF5F, DQSOSC=386, MR23=63, INC=396, DEC=264
6577 14:00:12.106671 [RxdqsGatingPostProcess] freq 400
6578 14:00:12.110031 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6579 14:00:12.112991 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 14:00:12.116526 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 14:00:12.119654 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 14:00:12.123395 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 14:00:12.126298 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 14:00:12.129745 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 14:00:12.133247 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 14:00:12.136401 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 14:00:12.139852 Pre-setting of DQS Precalculation
6588 14:00:12.142881 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6589 14:00:12.142990 ==
6590 14:00:12.146384 Dram Type= 6, Freq= 0, CH_1, rank 0
6591 14:00:12.153004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 14:00:12.153115 ==
6593 14:00:12.156567 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6594 14:00:12.162899 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6595 14:00:12.166247 [CA 0] Center 36 (8~64) winsize 57
6596 14:00:12.169795 [CA 1] Center 36 (8~64) winsize 57
6597 14:00:12.173186 [CA 2] Center 36 (8~64) winsize 57
6598 14:00:12.176220 [CA 3] Center 36 (8~64) winsize 57
6599 14:00:12.179721 [CA 4] Center 36 (8~64) winsize 57
6600 14:00:12.182822 [CA 5] Center 36 (8~64) winsize 57
6601 14:00:12.182901
6602 14:00:12.185914 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6603 14:00:12.185993
6604 14:00:12.189641 [CATrainingPosCal] consider 1 rank data
6605 14:00:12.193016 u2DelayCellTimex100 = 270/100 ps
6606 14:00:12.196322 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 14:00:12.199589 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 14:00:12.202876 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 14:00:12.206344 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 14:00:12.209267 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 14:00:12.212553 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 14:00:12.212653
6613 14:00:12.219289 CA PerBit enable=1, Macro0, CA PI delay=36
6614 14:00:12.219373
6615 14:00:12.223099 [CBTSetCACLKResult] CA Dly = 36
6616 14:00:12.223205 CS Dly: 1 (0~32)
6617 14:00:12.223318 ==
6618 14:00:12.226008 Dram Type= 6, Freq= 0, CH_1, rank 1
6619 14:00:12.229426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 14:00:12.229508 ==
6621 14:00:12.235930 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 14:00:12.242681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6623 14:00:12.246017 [CA 0] Center 36 (8~64) winsize 57
6624 14:00:12.249262 [CA 1] Center 36 (8~64) winsize 57
6625 14:00:12.252852 [CA 2] Center 36 (8~64) winsize 57
6626 14:00:12.255909 [CA 3] Center 36 (8~64) winsize 57
6627 14:00:12.259290 [CA 4] Center 36 (8~64) winsize 57
6628 14:00:12.259390 [CA 5] Center 36 (8~64) winsize 57
6629 14:00:12.259489
6630 14:00:12.266380 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6631 14:00:12.266458
6632 14:00:12.269334 [CATrainingPosCal] consider 2 rank data
6633 14:00:12.272906 u2DelayCellTimex100 = 270/100 ps
6634 14:00:12.275915 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 14:00:12.279576 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 14:00:12.282775 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 14:00:12.286317 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 14:00:12.289148 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 14:00:12.292719 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 14:00:12.292811
6641 14:00:12.296162 CA PerBit enable=1, Macro0, CA PI delay=36
6642 14:00:12.296251
6643 14:00:12.299049 [CBTSetCACLKResult] CA Dly = 36
6644 14:00:12.302750 CS Dly: 1 (0~32)
6645 14:00:12.302868
6646 14:00:12.306164 ----->DramcWriteLeveling(PI) begin...
6647 14:00:12.306269 ==
6648 14:00:12.309021 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 14:00:12.312378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 14:00:12.312491 ==
6651 14:00:12.315966 Write leveling (Byte 0): 40 => 8
6652 14:00:12.319199 Write leveling (Byte 1): 40 => 8
6653 14:00:12.322657 DramcWriteLeveling(PI) end<-----
6654 14:00:12.322766
6655 14:00:12.322871 ==
6656 14:00:12.325895 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 14:00:12.329110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 14:00:12.329193 ==
6659 14:00:12.332316 [Gating] SW mode calibration
6660 14:00:12.339232 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6661 14:00:12.345691 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6662 14:00:12.349059 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 14:00:12.352665 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 14:00:12.359186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 14:00:12.362659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 14:00:12.365669 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 14:00:12.372674 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 14:00:12.375646 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 14:00:12.379058 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 14:00:12.385590 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 14:00:12.385677 Total UI for P1: 0, mck2ui 16
6672 14:00:12.392230 best dqsien dly found for B0: ( 0, 14, 24)
6673 14:00:12.392314 Total UI for P1: 0, mck2ui 16
6674 14:00:12.398716 best dqsien dly found for B1: ( 0, 14, 24)
6675 14:00:12.402076 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6676 14:00:12.405680 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6677 14:00:12.405774
6678 14:00:12.408609 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 14:00:12.412259 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 14:00:12.415544 [Gating] SW calibration Done
6681 14:00:12.415663 ==
6682 14:00:12.418397 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 14:00:12.422013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 14:00:12.422098 ==
6685 14:00:12.425291 RX Vref Scan: 0
6686 14:00:12.425374
6687 14:00:12.425440 RX Vref 0 -> 0, step: 1
6688 14:00:12.429129
6689 14:00:12.429211 RX Delay -410 -> 252, step: 16
6690 14:00:12.435292 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6691 14:00:12.438637 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6692 14:00:12.442090 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6693 14:00:12.445400 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6694 14:00:12.451698 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6695 14:00:12.455223 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6696 14:00:12.458574 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6697 14:00:12.461685 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6698 14:00:12.468180 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6699 14:00:12.471742 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6700 14:00:12.474789 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6701 14:00:12.478537 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6702 14:00:12.485060 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6703 14:00:12.488420 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6704 14:00:12.491407 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6705 14:00:12.497988 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6706 14:00:12.498071 ==
6707 14:00:12.501407 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 14:00:12.504716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 14:00:12.504800 ==
6710 14:00:12.504866 DQS Delay:
6711 14:00:12.507834 DQS0 = 27, DQS1 = 35
6712 14:00:12.507917 DQM Delay:
6713 14:00:12.511209 DQM0 = 10, DQM1 = 13
6714 14:00:12.511292 DQ Delay:
6715 14:00:12.514802 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6716 14:00:12.517992 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6717 14:00:12.521583 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6718 14:00:12.524342 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6719 14:00:12.524426
6720 14:00:12.524491
6721 14:00:12.524552 ==
6722 14:00:12.527786 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 14:00:12.531078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 14:00:12.531165 ==
6725 14:00:12.531231
6726 14:00:12.531292
6727 14:00:12.535003 TX Vref Scan disable
6728 14:00:12.535086 == TX Byte 0 ==
6729 14:00:12.541006 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 14:00:12.544453 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 14:00:12.544591 == TX Byte 1 ==
6732 14:00:12.550822 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 14:00:12.554666 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 14:00:12.554795 ==
6735 14:00:12.557560 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 14:00:12.561502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 14:00:12.561621 ==
6738 14:00:12.561742
6739 14:00:12.561855
6740 14:00:12.564170 TX Vref Scan disable
6741 14:00:12.564296 == TX Byte 0 ==
6742 14:00:12.571048 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 14:00:12.574387 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 14:00:12.574518 == TX Byte 1 ==
6745 14:00:12.580865 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 14:00:12.584638 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 14:00:12.584765
6748 14:00:12.584886 [DATLAT]
6749 14:00:12.587587 Freq=400, CH1 RK0
6750 14:00:12.587723
6751 14:00:12.587844 DATLAT Default: 0xf
6752 14:00:12.591407 0, 0xFFFF, sum = 0
6753 14:00:12.591534 1, 0xFFFF, sum = 0
6754 14:00:12.594162 2, 0xFFFF, sum = 0
6755 14:00:12.594287 3, 0xFFFF, sum = 0
6756 14:00:12.597937 4, 0xFFFF, sum = 0
6757 14:00:12.598060 5, 0xFFFF, sum = 0
6758 14:00:12.601041 6, 0xFFFF, sum = 0
6759 14:00:12.601163 7, 0xFFFF, sum = 0
6760 14:00:12.604757 8, 0xFFFF, sum = 0
6761 14:00:12.607599 9, 0xFFFF, sum = 0
6762 14:00:12.607738 10, 0xFFFF, sum = 0
6763 14:00:12.611072 11, 0xFFFF, sum = 0
6764 14:00:12.611201 12, 0xFFFF, sum = 0
6765 14:00:12.614070 13, 0x0, sum = 1
6766 14:00:12.614191 14, 0x0, sum = 2
6767 14:00:12.617740 15, 0x0, sum = 3
6768 14:00:12.617871 16, 0x0, sum = 4
6769 14:00:12.617983 best_step = 14
6770 14:00:12.618103
6771 14:00:12.621170 ==
6772 14:00:12.624518 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 14:00:12.627372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 14:00:12.627504 ==
6775 14:00:12.627620 RX Vref Scan: 1
6776 14:00:12.627745
6777 14:00:12.631060 RX Vref 0 -> 0, step: 1
6778 14:00:12.631184
6779 14:00:12.634037 RX Delay -311 -> 252, step: 8
6780 14:00:12.634163
6781 14:00:12.637595 Set Vref, RX VrefLevel [Byte0]: 53
6782 14:00:12.640825 [Byte1]: 53
6783 14:00:12.644160
6784 14:00:12.644285 Final RX Vref Byte 0 = 53 to rank0
6785 14:00:12.647608 Final RX Vref Byte 1 = 53 to rank0
6786 14:00:12.650866 Final RX Vref Byte 0 = 53 to rank1
6787 14:00:12.654526 Final RX Vref Byte 1 = 53 to rank1==
6788 14:00:12.657922 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 14:00:12.664283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 14:00:12.664415 ==
6791 14:00:12.664538 DQS Delay:
6792 14:00:12.667950 DQS0 = 28, DQS1 = 32
6793 14:00:12.668075 DQM Delay:
6794 14:00:12.668199 DQM0 = 10, DQM1 = 10
6795 14:00:12.670682 DQ Delay:
6796 14:00:12.674339 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6797 14:00:12.674459 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6798 14:00:12.677534 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6799 14:00:12.680922 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6800 14:00:12.681046
6801 14:00:12.681167
6802 14:00:12.690964 [DQSOSCAuto] RK0, (LSB)MR18= 0x96cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6803 14:00:12.694089 CH1 RK0: MR19=C0C, MR18=96CF
6804 14:00:12.700901 CH1_RK0: MR19=0xC0C, MR18=0x96CF, DQSOSC=384, MR23=63, INC=400, DEC=267
6805 14:00:12.700993 ==
6806 14:00:12.704206 Dram Type= 6, Freq= 0, CH_1, rank 1
6807 14:00:12.707216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 14:00:12.707315 ==
6809 14:00:12.710799 [Gating] SW mode calibration
6810 14:00:12.717492 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6811 14:00:12.724193 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6812 14:00:12.727379 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 14:00:12.730901 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 14:00:12.736857 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 14:00:12.740760 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 14:00:12.743689 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 14:00:12.747256 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 14:00:12.754058 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 14:00:12.757066 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 14:00:12.760388 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 14:00:12.764073 Total UI for P1: 0, mck2ui 16
6822 14:00:12.767329 best dqsien dly found for B0: ( 0, 14, 24)
6823 14:00:12.770434 Total UI for P1: 0, mck2ui 16
6824 14:00:12.773563 best dqsien dly found for B1: ( 0, 14, 24)
6825 14:00:12.777221 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6826 14:00:12.780409 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6827 14:00:12.784064
6828 14:00:12.786954 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 14:00:12.790462 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 14:00:12.793857 [Gating] SW calibration Done
6831 14:00:12.793943 ==
6832 14:00:12.797037 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 14:00:12.800589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 14:00:12.800667 ==
6835 14:00:12.800730 RX Vref Scan: 0
6836 14:00:12.800796
6837 14:00:12.803989 RX Vref 0 -> 0, step: 1
6838 14:00:12.804058
6839 14:00:12.807124 RX Delay -410 -> 252, step: 16
6840 14:00:12.810267 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6841 14:00:12.817270 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6842 14:00:12.820279 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6843 14:00:12.823785 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6844 14:00:12.826792 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6845 14:00:12.833343 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6846 14:00:12.837129 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6847 14:00:12.839874 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6848 14:00:12.843309 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6849 14:00:12.850246 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6850 14:00:12.853605 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6851 14:00:12.856627 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6852 14:00:12.859777 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6853 14:00:12.866357 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6854 14:00:12.870330 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6855 14:00:12.873091 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6856 14:00:12.873161 ==
6857 14:00:12.876839 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 14:00:12.883152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 14:00:12.883227 ==
6860 14:00:12.883313 DQS Delay:
6861 14:00:12.883395 DQS0 = 35, DQS1 = 35
6862 14:00:12.886510 DQM Delay:
6863 14:00:12.886605 DQM0 = 18, DQM1 = 15
6864 14:00:12.890026 DQ Delay:
6865 14:00:12.893105 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6866 14:00:12.896546 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6867 14:00:12.896649 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6868 14:00:12.899594 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6869 14:00:12.902965
6870 14:00:12.903057
6871 14:00:12.903117 ==
6872 14:00:12.906412 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 14:00:12.909791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 14:00:12.909882 ==
6875 14:00:12.909945
6876 14:00:12.910002
6877 14:00:12.912935 TX Vref Scan disable
6878 14:00:12.913005 == TX Byte 0 ==
6879 14:00:12.916610 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6880 14:00:12.923064 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6881 14:00:12.923139 == TX Byte 1 ==
6882 14:00:12.926228 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6883 14:00:12.932642 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6884 14:00:12.932716 ==
6885 14:00:12.936404 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 14:00:12.939373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 14:00:12.939447 ==
6888 14:00:12.939510
6889 14:00:12.939575
6890 14:00:12.942995 TX Vref Scan disable
6891 14:00:12.943066 == TX Byte 0 ==
6892 14:00:12.945786 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6893 14:00:12.952572 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6894 14:00:12.952673 == TX Byte 1 ==
6895 14:00:12.955830 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6896 14:00:12.962638 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6897 14:00:12.962740
6898 14:00:12.962805 [DATLAT]
6899 14:00:12.966014 Freq=400, CH1 RK1
6900 14:00:12.966130
6901 14:00:12.966222 DATLAT Default: 0xe
6902 14:00:12.969246 0, 0xFFFF, sum = 0
6903 14:00:12.969325 1, 0xFFFF, sum = 0
6904 14:00:12.972594 2, 0xFFFF, sum = 0
6905 14:00:12.972665 3, 0xFFFF, sum = 0
6906 14:00:12.976189 4, 0xFFFF, sum = 0
6907 14:00:12.976288 5, 0xFFFF, sum = 0
6908 14:00:12.979290 6, 0xFFFF, sum = 0
6909 14:00:12.979401 7, 0xFFFF, sum = 0
6910 14:00:12.982367 8, 0xFFFF, sum = 0
6911 14:00:12.982440 9, 0xFFFF, sum = 0
6912 14:00:12.985814 10, 0xFFFF, sum = 0
6913 14:00:12.985884 11, 0xFFFF, sum = 0
6914 14:00:12.989534 12, 0xFFFF, sum = 0
6915 14:00:12.989612 13, 0x0, sum = 1
6916 14:00:12.993012 14, 0x0, sum = 2
6917 14:00:12.993088 15, 0x0, sum = 3
6918 14:00:12.995981 16, 0x0, sum = 4
6919 14:00:12.996056 best_step = 14
6920 14:00:12.996118
6921 14:00:12.996176 ==
6922 14:00:12.999126 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 14:00:13.005878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 14:00:13.005970 ==
6925 14:00:13.006039 RX Vref Scan: 0
6926 14:00:13.006099
6927 14:00:13.009227 RX Vref 0 -> 0, step: 1
6928 14:00:13.009303
6929 14:00:13.012243 RX Delay -311 -> 252, step: 8
6930 14:00:13.019027 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6931 14:00:13.022452 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6932 14:00:13.026021 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6933 14:00:13.029039 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6934 14:00:13.035882 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6935 14:00:13.039206 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6936 14:00:13.042814 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6937 14:00:13.045864 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6938 14:00:13.049654 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6939 14:00:13.055958 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6940 14:00:13.059676 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6941 14:00:13.062307 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6942 14:00:13.065999 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6943 14:00:13.072887 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6944 14:00:13.075610 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6945 14:00:13.079530 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6946 14:00:13.079649 ==
6947 14:00:13.082222 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 14:00:13.088935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 14:00:13.089030 ==
6950 14:00:13.089120 DQS Delay:
6951 14:00:13.092319 DQS0 = 28, DQS1 = 36
6952 14:00:13.092393 DQM Delay:
6953 14:00:13.092474 DQM0 = 11, DQM1 = 14
6954 14:00:13.096018 DQ Delay:
6955 14:00:13.098880 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6956 14:00:13.102530 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6957 14:00:13.102612 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6958 14:00:13.105514 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6959 14:00:13.108962
6960 14:00:13.109079
6961 14:00:13.115529 [DQSOSCAuto] RK1, (LSB)MR18= 0xcc5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
6962 14:00:13.118874 CH1 RK1: MR19=C0C, MR18=CC5C
6963 14:00:13.125719 CH1_RK1: MR19=0xC0C, MR18=0xCC5C, DQSOSC=384, MR23=63, INC=400, DEC=267
6964 14:00:13.128602 [RxdqsGatingPostProcess] freq 400
6965 14:00:13.132172 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6966 14:00:13.135528 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 14:00:13.139193 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 14:00:13.142209 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 14:00:13.145669 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 14:00:13.149275 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 14:00:13.152296 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 14:00:13.155307 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 14:00:13.158977 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 14:00:13.162011 Pre-setting of DQS Precalculation
6975 14:00:13.165775 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6976 14:00:13.172170 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6977 14:00:13.181906 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6978 14:00:13.181991
6979 14:00:13.182057
6980 14:00:13.185393 [Calibration Summary] 800 Mbps
6981 14:00:13.185477 CH 0, Rank 0
6982 14:00:13.189108 SW Impedance : PASS
6983 14:00:13.189191 DUTY Scan : NO K
6984 14:00:13.191833 ZQ Calibration : PASS
6985 14:00:13.191932 Jitter Meter : NO K
6986 14:00:13.195237 CBT Training : PASS
6987 14:00:13.198900 Write leveling : PASS
6988 14:00:13.199010 RX DQS gating : PASS
6989 14:00:13.201963 RX DQ/DQS(RDDQC) : PASS
6990 14:00:13.205111 TX DQ/DQS : PASS
6991 14:00:13.205192 RX DATLAT : PASS
6992 14:00:13.208399 RX DQ/DQS(Engine): PASS
6993 14:00:13.212164 TX OE : NO K
6994 14:00:13.212272 All Pass.
6995 14:00:13.212363
6996 14:00:13.212452 CH 0, Rank 1
6997 14:00:13.215497 SW Impedance : PASS
6998 14:00:13.218524 DUTY Scan : NO K
6999 14:00:13.218629 ZQ Calibration : PASS
7000 14:00:13.222093 Jitter Meter : NO K
7001 14:00:13.225139 CBT Training : PASS
7002 14:00:13.225216 Write leveling : NO K
7003 14:00:13.228638 RX DQS gating : PASS
7004 14:00:13.232127 RX DQ/DQS(RDDQC) : PASS
7005 14:00:13.232210 TX DQ/DQS : PASS
7006 14:00:13.235124 RX DATLAT : PASS
7007 14:00:13.238695 RX DQ/DQS(Engine): PASS
7008 14:00:13.238783 TX OE : NO K
7009 14:00:13.238850 All Pass.
7010 14:00:13.241673
7011 14:00:13.241772 CH 1, Rank 0
7012 14:00:13.244857 SW Impedance : PASS
7013 14:00:13.244973 DUTY Scan : NO K
7014 14:00:13.248366 ZQ Calibration : PASS
7015 14:00:13.248468 Jitter Meter : NO K
7016 14:00:13.252102 CBT Training : PASS
7017 14:00:13.255254 Write leveling : PASS
7018 14:00:13.255331 RX DQS gating : PASS
7019 14:00:13.258187 RX DQ/DQS(RDDQC) : PASS
7020 14:00:13.261900 TX DQ/DQS : PASS
7021 14:00:13.261991 RX DATLAT : PASS
7022 14:00:13.265109 RX DQ/DQS(Engine): PASS
7023 14:00:13.268477 TX OE : NO K
7024 14:00:13.268579 All Pass.
7025 14:00:13.268659
7026 14:00:13.268719 CH 1, Rank 1
7027 14:00:13.271835 SW Impedance : PASS
7028 14:00:13.274812 DUTY Scan : NO K
7029 14:00:13.274910 ZQ Calibration : PASS
7030 14:00:13.278491 Jitter Meter : NO K
7031 14:00:13.281946 CBT Training : PASS
7032 14:00:13.282029 Write leveling : NO K
7033 14:00:13.285288 RX DQS gating : PASS
7034 14:00:13.288501 RX DQ/DQS(RDDQC) : PASS
7035 14:00:13.288601 TX DQ/DQS : PASS
7036 14:00:13.291652 RX DATLAT : PASS
7037 14:00:13.291735 RX DQ/DQS(Engine): PASS
7038 14:00:13.295196 TX OE : NO K
7039 14:00:13.295299 All Pass.
7040 14:00:13.295400
7041 14:00:13.298289 DramC Write-DBI off
7042 14:00:13.301761 PER_BANK_REFRESH: Hybrid Mode
7043 14:00:13.301867 TX_TRACKING: ON
7044 14:00:13.312035 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7045 14:00:13.315186 [FAST_K] Save calibration result to emmc
7046 14:00:13.318054 dramc_set_vcore_voltage set vcore to 725000
7047 14:00:13.321746 Read voltage for 1600, 0
7048 14:00:13.321834 Vio18 = 0
7049 14:00:13.324790 Vcore = 725000
7050 14:00:13.324896 Vdram = 0
7051 14:00:13.324986 Vddq = 0
7052 14:00:13.325078 Vmddr = 0
7053 14:00:13.331864 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7054 14:00:13.338300 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7055 14:00:13.338404 MEM_TYPE=3, freq_sel=13
7056 14:00:13.341402 sv_algorithm_assistance_LP4_3733
7057 14:00:13.344954 ============ PULL DRAM RESETB DOWN ============
7058 14:00:13.351757 ========== PULL DRAM RESETB DOWN end =========
7059 14:00:13.354658 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7060 14:00:13.358207 ===================================
7061 14:00:13.361858 LPDDR4 DRAM CONFIGURATION
7062 14:00:13.364741 ===================================
7063 14:00:13.364823 EX_ROW_EN[0] = 0x0
7064 14:00:13.368248 EX_ROW_EN[1] = 0x0
7065 14:00:13.368330 LP4Y_EN = 0x0
7066 14:00:13.371585 WORK_FSP = 0x1
7067 14:00:13.371692 WL = 0x5
7068 14:00:13.375193 RL = 0x5
7069 14:00:13.375276 BL = 0x2
7070 14:00:13.378100 RPST = 0x0
7071 14:00:13.378183 RD_PRE = 0x0
7072 14:00:13.381485 WR_PRE = 0x1
7073 14:00:13.381575 WR_PST = 0x1
7074 14:00:13.385107 DBI_WR = 0x0
7075 14:00:13.385189 DBI_RD = 0x0
7076 14:00:13.387968 OTF = 0x1
7077 14:00:13.391656 ===================================
7078 14:00:13.394926 ===================================
7079 14:00:13.395029 ANA top config
7080 14:00:13.398071 ===================================
7081 14:00:13.401742 DLL_ASYNC_EN = 0
7082 14:00:13.405112 ALL_SLAVE_EN = 0
7083 14:00:13.408314 NEW_RANK_MODE = 1
7084 14:00:13.408389 DLL_IDLE_MODE = 1
7085 14:00:13.411434 LP45_APHY_COMB_EN = 1
7086 14:00:13.414941 TX_ODT_DIS = 0
7087 14:00:13.418494 NEW_8X_MODE = 1
7088 14:00:13.421252 ===================================
7089 14:00:13.424767 ===================================
7090 14:00:13.428312 data_rate = 3200
7091 14:00:13.431831 CKR = 1
7092 14:00:13.431971 DQ_P2S_RATIO = 8
7093 14:00:13.434790 ===================================
7094 14:00:13.438307 CA_P2S_RATIO = 8
7095 14:00:13.441702 DQ_CA_OPEN = 0
7096 14:00:13.444678 DQ_SEMI_OPEN = 0
7097 14:00:13.448336 CA_SEMI_OPEN = 0
7098 14:00:13.448459 CA_FULL_RATE = 0
7099 14:00:13.451607 DQ_CKDIV4_EN = 0
7100 14:00:13.454606 CA_CKDIV4_EN = 0
7101 14:00:13.458099 CA_PREDIV_EN = 0
7102 14:00:13.461187 PH8_DLY = 12
7103 14:00:13.464638 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7104 14:00:13.467690 DQ_AAMCK_DIV = 4
7105 14:00:13.467792 CA_AAMCK_DIV = 4
7106 14:00:13.471151 CA_ADMCK_DIV = 4
7107 14:00:13.474590 DQ_TRACK_CA_EN = 0
7108 14:00:13.477788 CA_PICK = 1600
7109 14:00:13.481051 CA_MCKIO = 1600
7110 14:00:13.484397 MCKIO_SEMI = 0
7111 14:00:13.488070 PLL_FREQ = 3068
7112 14:00:13.488153 DQ_UI_PI_RATIO = 32
7113 14:00:13.490974 CA_UI_PI_RATIO = 0
7114 14:00:13.494390 ===================================
7115 14:00:13.498092 ===================================
7116 14:00:13.501045 memory_type:LPDDR4
7117 14:00:13.504532 GP_NUM : 10
7118 14:00:13.504660 SRAM_EN : 1
7119 14:00:13.507603 MD32_EN : 0
7120 14:00:13.511376 ===================================
7121 14:00:13.511500 [ANA_INIT] >>>>>>>>>>>>>>
7122 14:00:13.514758 <<<<<< [CONFIGURE PHASE]: ANA_TX
7123 14:00:13.517698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7124 14:00:13.521461 ===================================
7125 14:00:13.524973 data_rate = 3200,PCW = 0X7600
7126 14:00:13.527879 ===================================
7127 14:00:13.531268 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7128 14:00:13.537999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 14:00:13.541216 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 14:00:13.547674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7131 14:00:13.551522 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7132 14:00:13.554291 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7133 14:00:13.558080 [ANA_INIT] flow start
7134 14:00:13.558206 [ANA_INIT] PLL >>>>>>>>
7135 14:00:13.561041 [ANA_INIT] PLL <<<<<<<<
7136 14:00:13.564237 [ANA_INIT] MIDPI >>>>>>>>
7137 14:00:13.564320 [ANA_INIT] MIDPI <<<<<<<<
7138 14:00:13.567553 [ANA_INIT] DLL >>>>>>>>
7139 14:00:13.571392 [ANA_INIT] DLL <<<<<<<<
7140 14:00:13.571521 [ANA_INIT] flow end
7141 14:00:13.577558 ============ LP4 DIFF to SE enter ============
7142 14:00:13.581110 ============ LP4 DIFF to SE exit ============
7143 14:00:13.584335 [ANA_INIT] <<<<<<<<<<<<<
7144 14:00:13.587502 [Flow] Enable top DCM control >>>>>
7145 14:00:13.590922 [Flow] Enable top DCM control <<<<<
7146 14:00:13.591048 Enable DLL master slave shuffle
7147 14:00:13.597479 ==============================================================
7148 14:00:13.600796 Gating Mode config
7149 14:00:13.604077 ==============================================================
7150 14:00:13.607519 Config description:
7151 14:00:13.617278 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7152 14:00:13.623731 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7153 14:00:13.627258 SELPH_MODE 0: By rank 1: By Phase
7154 14:00:13.633662 ==============================================================
7155 14:00:13.637116 GAT_TRACK_EN = 1
7156 14:00:13.640368 RX_GATING_MODE = 2
7157 14:00:13.643750 RX_GATING_TRACK_MODE = 2
7158 14:00:13.647060 SELPH_MODE = 1
7159 14:00:13.647164 PICG_EARLY_EN = 1
7160 14:00:13.650436 VALID_LAT_VALUE = 1
7161 14:00:13.657166 ==============================================================
7162 14:00:13.660180 Enter into Gating configuration >>>>
7163 14:00:13.663614 Exit from Gating configuration <<<<
7164 14:00:13.667380 Enter into DVFS_PRE_config >>>>>
7165 14:00:13.677419 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7166 14:00:13.680592 Exit from DVFS_PRE_config <<<<<
7167 14:00:13.683968 Enter into PICG configuration >>>>
7168 14:00:13.687032 Exit from PICG configuration <<<<
7169 14:00:13.690451 [RX_INPUT] configuration >>>>>
7170 14:00:13.693779 [RX_INPUT] configuration <<<<<
7171 14:00:13.697372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7172 14:00:13.703740 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7173 14:00:13.710523 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 14:00:13.716761 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 14:00:13.723256 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 14:00:13.727112 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 14:00:13.733595 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7178 14:00:13.736721 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7179 14:00:13.740357 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7180 14:00:13.743184 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7181 14:00:13.750014 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7182 14:00:13.753628 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7183 14:00:13.756797 ===================================
7184 14:00:13.760131 LPDDR4 DRAM CONFIGURATION
7185 14:00:13.763143 ===================================
7186 14:00:13.763242 EX_ROW_EN[0] = 0x0
7187 14:00:13.766909 EX_ROW_EN[1] = 0x0
7188 14:00:13.767013 LP4Y_EN = 0x0
7189 14:00:13.769686 WORK_FSP = 0x1
7190 14:00:13.769784 WL = 0x5
7191 14:00:13.773081 RL = 0x5
7192 14:00:13.773157 BL = 0x2
7193 14:00:13.776860 RPST = 0x0
7194 14:00:13.776933 RD_PRE = 0x0
7195 14:00:13.779814 WR_PRE = 0x1
7196 14:00:13.783277 WR_PST = 0x1
7197 14:00:13.783376 DBI_WR = 0x0
7198 14:00:13.786246 DBI_RD = 0x0
7199 14:00:13.786345 OTF = 0x1
7200 14:00:13.790085 ===================================
7201 14:00:13.793216 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7202 14:00:13.796544 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7203 14:00:13.803167 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 14:00:13.806559 ===================================
7205 14:00:13.809522 LPDDR4 DRAM CONFIGURATION
7206 14:00:13.813092 ===================================
7207 14:00:13.813198 EX_ROW_EN[0] = 0x10
7208 14:00:13.816128 EX_ROW_EN[1] = 0x0
7209 14:00:13.816233 LP4Y_EN = 0x0
7210 14:00:13.819749 WORK_FSP = 0x1
7211 14:00:13.819827 WL = 0x5
7212 14:00:13.823197 RL = 0x5
7213 14:00:13.823296 BL = 0x2
7214 14:00:13.826040 RPST = 0x0
7215 14:00:13.826144 RD_PRE = 0x0
7216 14:00:13.829647 WR_PRE = 0x1
7217 14:00:13.829749 WR_PST = 0x1
7218 14:00:13.832789 DBI_WR = 0x0
7219 14:00:13.832900 DBI_RD = 0x0
7220 14:00:13.836039 OTF = 0x1
7221 14:00:13.839539 ===================================
7222 14:00:13.845930 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7223 14:00:13.846039 ==
7224 14:00:13.849729 Dram Type= 6, Freq= 0, CH_0, rank 0
7225 14:00:13.853028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7226 14:00:13.853102 ==
7227 14:00:13.855881 [Duty_Offset_Calibration]
7228 14:00:13.855956 B0:2 B1:1 CA:1
7229 14:00:13.856018
7230 14:00:13.859241 [DutyScan_Calibration_Flow] k_type=0
7231 14:00:13.871053
7232 14:00:13.871160 ==CLK 0==
7233 14:00:13.873946 Final CLK duty delay cell = 0
7234 14:00:13.877196 [0] MAX Duty = 5156%(X100), DQS PI = 22
7235 14:00:13.880409 [0] MIN Duty = 4876%(X100), DQS PI = 48
7236 14:00:13.880490 [0] AVG Duty = 5016%(X100)
7237 14:00:13.884047
7238 14:00:13.886955 CH0 CLK Duty spec in!! Max-Min= 280%
7239 14:00:13.890396 [DutyScan_Calibration_Flow] ====Done====
7240 14:00:13.890494
7241 14:00:13.893907 [DutyScan_Calibration_Flow] k_type=1
7242 14:00:13.909705
7243 14:00:13.909812 ==DQS 0 ==
7244 14:00:13.912916 Final DQS duty delay cell = -4
7245 14:00:13.916523 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7246 14:00:13.919839 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7247 14:00:13.923257 [-4] AVG Duty = 4891%(X100)
7248 14:00:13.923354
7249 14:00:13.923445 ==DQS 1 ==
7250 14:00:13.926701 Final DQS duty delay cell = 0
7251 14:00:13.929664 [0] MAX Duty = 5187%(X100), DQS PI = 18
7252 14:00:13.933196 [0] MIN Duty = 5031%(X100), DQS PI = 52
7253 14:00:13.936496 [0] AVG Duty = 5109%(X100)
7254 14:00:13.936595
7255 14:00:13.939464 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7256 14:00:13.939560
7257 14:00:13.943037 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7258 14:00:13.946293 [DutyScan_Calibration_Flow] ====Done====
7259 14:00:13.946394
7260 14:00:13.949568 [DutyScan_Calibration_Flow] k_type=3
7261 14:00:13.966422
7262 14:00:13.966547 ==DQM 0 ==
7263 14:00:13.969659 Final DQM duty delay cell = 0
7264 14:00:13.973632 [0] MAX Duty = 5218%(X100), DQS PI = 32
7265 14:00:13.976278 [0] MIN Duty = 4876%(X100), DQS PI = 60
7266 14:00:13.976350 [0] AVG Duty = 5047%(X100)
7267 14:00:13.979631
7268 14:00:13.979727 ==DQM 1 ==
7269 14:00:13.983395 Final DQM duty delay cell = -4
7270 14:00:13.986317 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7271 14:00:13.990056 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7272 14:00:13.992856 [-4] AVG Duty = 4891%(X100)
7273 14:00:13.992930
7274 14:00:13.996299 CH0 DQM 0 Duty spec in!! Max-Min= 342%
7275 14:00:13.996375
7276 14:00:13.999836 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7277 14:00:14.002619 [DutyScan_Calibration_Flow] ====Done====
7278 14:00:14.002718
7279 14:00:14.006347 [DutyScan_Calibration_Flow] k_type=2
7280 14:00:14.024035
7281 14:00:14.024144 ==DQ 0 ==
7282 14:00:14.027785 Final DQ duty delay cell = 0
7283 14:00:14.030465 [0] MAX Duty = 5062%(X100), DQS PI = 24
7284 14:00:14.034021 [0] MIN Duty = 4907%(X100), DQS PI = 0
7285 14:00:14.034132 [0] AVG Duty = 4984%(X100)
7286 14:00:14.034226
7287 14:00:14.037067 ==DQ 1 ==
7288 14:00:14.040895 Final DQ duty delay cell = 0
7289 14:00:14.043978 [0] MAX Duty = 5156%(X100), DQS PI = 22
7290 14:00:14.047667 [0] MIN Duty = 4907%(X100), DQS PI = 34
7291 14:00:14.047743 [0] AVG Duty = 5031%(X100)
7292 14:00:14.047807
7293 14:00:14.050365 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7294 14:00:14.053943
7295 14:00:14.057355 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7296 14:00:14.060592 [DutyScan_Calibration_Flow] ====Done====
7297 14:00:14.060694 ==
7298 14:00:14.063698 Dram Type= 6, Freq= 0, CH_1, rank 0
7299 14:00:14.067079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 14:00:14.067196 ==
7301 14:00:14.070402 [Duty_Offset_Calibration]
7302 14:00:14.070503 B0:1 B1:0 CA:0
7303 14:00:14.070569
7304 14:00:14.073783 [DutyScan_Calibration_Flow] k_type=0
7305 14:00:14.083209
7306 14:00:14.083338 ==CLK 0==
7307 14:00:14.086481 Final CLK duty delay cell = -4
7308 14:00:14.089820 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7309 14:00:14.093397 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7310 14:00:14.096682 [-4] AVG Duty = 4922%(X100)
7311 14:00:14.096807
7312 14:00:14.100208 CH1 CLK Duty spec in!! Max-Min= 156%
7313 14:00:14.103389 [DutyScan_Calibration_Flow] ====Done====
7314 14:00:14.103512
7315 14:00:14.106290 [DutyScan_Calibration_Flow] k_type=1
7316 14:00:14.123491
7317 14:00:14.123619 ==DQS 0 ==
7318 14:00:14.126722 Final DQS duty delay cell = 0
7319 14:00:14.129964 [0] MAX Duty = 5094%(X100), DQS PI = 28
7320 14:00:14.133191 [0] MIN Duty = 4844%(X100), DQS PI = 48
7321 14:00:14.136695 [0] AVG Duty = 4969%(X100)
7322 14:00:14.136779
7323 14:00:14.136844 ==DQS 1 ==
7324 14:00:14.139980 Final DQS duty delay cell = 0
7325 14:00:14.143152 [0] MAX Duty = 5249%(X100), DQS PI = 16
7326 14:00:14.146408 [0] MIN Duty = 4969%(X100), DQS PI = 6
7327 14:00:14.150129 [0] AVG Duty = 5109%(X100)
7328 14:00:14.150242
7329 14:00:14.153236 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7330 14:00:14.153330
7331 14:00:14.156320 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7332 14:00:14.160027 [DutyScan_Calibration_Flow] ====Done====
7333 14:00:14.160129
7334 14:00:14.163300 [DutyScan_Calibration_Flow] k_type=3
7335 14:00:14.180036
7336 14:00:14.180176 ==DQM 0 ==
7337 14:00:14.183334 Final DQM duty delay cell = 0
7338 14:00:14.186870 [0] MAX Duty = 5187%(X100), DQS PI = 10
7339 14:00:14.190118 [0] MIN Duty = 4969%(X100), DQS PI = 46
7340 14:00:14.193202 [0] AVG Duty = 5078%(X100)
7341 14:00:14.193332
7342 14:00:14.193451 ==DQM 1 ==
7343 14:00:14.196782 Final DQM duty delay cell = 0
7344 14:00:14.200297 [0] MAX Duty = 5093%(X100), DQS PI = 16
7345 14:00:14.203488 [0] MIN Duty = 4907%(X100), DQS PI = 34
7346 14:00:14.206918 [0] AVG Duty = 5000%(X100)
7347 14:00:14.207042
7348 14:00:14.210279 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7349 14:00:14.210404
7350 14:00:14.213303 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7351 14:00:14.216934 [DutyScan_Calibration_Flow] ====Done====
7352 14:00:14.217060
7353 14:00:14.220032 [DutyScan_Calibration_Flow] k_type=2
7354 14:00:14.236483
7355 14:00:14.236611 ==DQ 0 ==
7356 14:00:14.239606 Final DQ duty delay cell = -4
7357 14:00:14.242984 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7358 14:00:14.246399 [-4] MIN Duty = 4875%(X100), DQS PI = 48
7359 14:00:14.249349 [-4] AVG Duty = 4968%(X100)
7360 14:00:14.249456
7361 14:00:14.249550 ==DQ 1 ==
7362 14:00:14.252918 Final DQ duty delay cell = 0
7363 14:00:14.256115 [0] MAX Duty = 5125%(X100), DQS PI = 20
7364 14:00:14.259759 [0] MIN Duty = 4938%(X100), DQS PI = 8
7365 14:00:14.262743 [0] AVG Duty = 5031%(X100)
7366 14:00:14.262848
7367 14:00:14.266171 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7368 14:00:14.266255
7369 14:00:14.269842 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7370 14:00:14.272656 [DutyScan_Calibration_Flow] ====Done====
7371 14:00:14.276179 nWR fixed to 30
7372 14:00:14.279262 [ModeRegInit_LP4] CH0 RK0
7373 14:00:14.279345 [ModeRegInit_LP4] CH0 RK1
7374 14:00:14.283073 [ModeRegInit_LP4] CH1 RK0
7375 14:00:14.285891 [ModeRegInit_LP4] CH1 RK1
7376 14:00:14.286017 match AC timing 5
7377 14:00:14.292554 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7378 14:00:14.296019 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7379 14:00:14.299174 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7380 14:00:14.306072 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7381 14:00:14.309310 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7382 14:00:14.309434 [MiockJmeterHQA]
7383 14:00:14.309551
7384 14:00:14.312584 [DramcMiockJmeter] u1RxGatingPI = 0
7385 14:00:14.316263 0 : 4368, 4140
7386 14:00:14.316390 4 : 4363, 4137
7387 14:00:14.319280 8 : 4253, 4026
7388 14:00:14.319403 12 : 4363, 4137
7389 14:00:14.322265 16 : 4252, 4027
7390 14:00:14.322392 20 : 4252, 4027
7391 14:00:14.322509 24 : 4363, 4137
7392 14:00:14.325800 28 : 4252, 4027
7393 14:00:14.325929 32 : 4361, 4137
7394 14:00:14.329275 36 : 4252, 4027
7395 14:00:14.329404 40 : 4250, 4027
7396 14:00:14.332143 44 : 4250, 4026
7397 14:00:14.332272 48 : 4250, 4027
7398 14:00:14.332384 52 : 4361, 4138
7399 14:00:14.335972 56 : 4250, 4027
7400 14:00:14.336099 60 : 4360, 4137
7401 14:00:14.338862 64 : 4361, 4138
7402 14:00:14.338987 68 : 4250, 4026
7403 14:00:14.342195 72 : 4252, 4029
7404 14:00:14.342323 76 : 4361, 4137
7405 14:00:14.345726 80 : 4250, 4027
7406 14:00:14.345852 84 : 4363, 4139
7407 14:00:14.345973 88 : 4250, 67
7408 14:00:14.349195 92 : 4363, 0
7409 14:00:14.349323 96 : 4250, 0
7410 14:00:14.352497 100 : 4363, 0
7411 14:00:14.352627 104 : 4252, 0
7412 14:00:14.352746 108 : 4250, 0
7413 14:00:14.355319 112 : 4253, 0
7414 14:00:14.355446 116 : 4252, 0
7415 14:00:14.359128 120 : 4250, 0
7416 14:00:14.359257 124 : 4250, 0
7417 14:00:14.359372 128 : 4252, 0
7418 14:00:14.361718 132 : 4360, 0
7419 14:00:14.361847 136 : 4250, 0
7420 14:00:14.361965 140 : 4250, 0
7421 14:00:14.365413 144 : 4255, 0
7422 14:00:14.365541 148 : 4361, 0
7423 14:00:14.368457 152 : 4250, 0
7424 14:00:14.368583 156 : 4253, 0
7425 14:00:14.368701 160 : 4253, 0
7426 14:00:14.371939 164 : 4361, 0
7427 14:00:14.372066 168 : 4250, 0
7428 14:00:14.375299 172 : 4250, 0
7429 14:00:14.375428 176 : 4250, 0
7430 14:00:14.375547 180 : 4252, 0
7431 14:00:14.378861 184 : 4360, 0
7432 14:00:14.378989 188 : 4360, 0
7433 14:00:14.382172 192 : 4250, 0
7434 14:00:14.382299 196 : 4253, 0
7435 14:00:14.382419 200 : 4361, 0
7436 14:00:14.385540 204 : 4249, 1350
7437 14:00:14.385669 208 : 4363, 4118
7438 14:00:14.388757 212 : 4361, 4137
7439 14:00:14.388870 216 : 4250, 4026
7440 14:00:14.392185 220 : 4250, 4027
7441 14:00:14.392265 224 : 4250, 4026
7442 14:00:14.395429 228 : 4250, 4026
7443 14:00:14.395561 232 : 4250, 4026
7444 14:00:14.398389 236 : 4250, 4027
7445 14:00:14.398517 240 : 4250, 4026
7446 14:00:14.398636 244 : 4363, 4140
7447 14:00:14.402376 248 : 4255, 4029
7448 14:00:14.402503 252 : 4249, 4027
7449 14:00:14.405207 256 : 4250, 4026
7450 14:00:14.405336 260 : 4363, 4140
7451 14:00:14.408855 264 : 4361, 4137
7452 14:00:14.408980 268 : 4250, 4027
7453 14:00:14.411709 272 : 4361, 4137
7454 14:00:14.411849 276 : 4252, 4029
7455 14:00:14.415726 280 : 4250, 4026
7456 14:00:14.415880 284 : 4252, 4029
7457 14:00:14.418870 288 : 4250, 4027
7458 14:00:14.418998 292 : 4252, 4029
7459 14:00:14.421949 296 : 4363, 4140
7460 14:00:14.422078 300 : 4252, 4027
7461 14:00:14.422196 304 : 4249, 4027
7462 14:00:14.425060 308 : 4250, 3956
7463 14:00:14.425182 312 : 4363, 1884
7464 14:00:14.425303
7465 14:00:14.428575 MIOCK jitter meter ch=0
7466 14:00:14.428700
7467 14:00:14.431705 1T = (312-88) = 224 dly cells
7468 14:00:14.438326 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7469 14:00:14.438455 ==
7470 14:00:14.441793 Dram Type= 6, Freq= 0, CH_0, rank 0
7471 14:00:14.444849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7472 14:00:14.444978 ==
7473 14:00:14.451838 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7474 14:00:14.455095 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7475 14:00:14.458466 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7476 14:00:14.465224 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7477 14:00:14.474043 [CA 0] Center 42 (12~73) winsize 62
7478 14:00:14.477067 [CA 1] Center 42 (12~73) winsize 62
7479 14:00:14.480747 [CA 2] Center 37 (7~67) winsize 61
7480 14:00:14.483577 [CA 3] Center 37 (7~67) winsize 61
7481 14:00:14.487190 [CA 4] Center 36 (6~66) winsize 61
7482 14:00:14.490963 [CA 5] Center 35 (6~64) winsize 59
7483 14:00:14.491048
7484 14:00:14.493543 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7485 14:00:14.493625
7486 14:00:14.497233 [CATrainingPosCal] consider 1 rank data
7487 14:00:14.500561 u2DelayCellTimex100 = 290/100 ps
7488 14:00:14.504082 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7489 14:00:14.510675 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7490 14:00:14.513510 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7491 14:00:14.516955 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7492 14:00:14.520536 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7493 14:00:14.524009 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7494 14:00:14.524092
7495 14:00:14.527319 CA PerBit enable=1, Macro0, CA PI delay=35
7496 14:00:14.527402
7497 14:00:14.530120 [CBTSetCACLKResult] CA Dly = 35
7498 14:00:14.533921 CS Dly: 9 (0~40)
7499 14:00:14.537151 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7500 14:00:14.540698 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7501 14:00:14.540782 ==
7502 14:00:14.543769 Dram Type= 6, Freq= 0, CH_0, rank 1
7503 14:00:14.547222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 14:00:14.547305 ==
7505 14:00:14.554118 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 14:00:14.557192 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 14:00:14.564039 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 14:00:14.567315 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 14:00:14.577350 [CA 0] Center 42 (12~73) winsize 62
7510 14:00:14.580488 [CA 1] Center 42 (12~73) winsize 62
7511 14:00:14.583770 [CA 2] Center 38 (8~68) winsize 61
7512 14:00:14.586760 [CA 3] Center 37 (8~67) winsize 60
7513 14:00:14.590671 [CA 4] Center 36 (6~66) winsize 61
7514 14:00:14.593400 [CA 5] Center 35 (5~65) winsize 61
7515 14:00:14.593475
7516 14:00:14.596877 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7517 14:00:14.596949
7518 14:00:14.600251 [CATrainingPosCal] consider 2 rank data
7519 14:00:14.603544 u2DelayCellTimex100 = 290/100 ps
7520 14:00:14.606736 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7521 14:00:14.613732 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7522 14:00:14.616679 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7523 14:00:14.620186 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7524 14:00:14.623528 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7525 14:00:14.626534 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7526 14:00:14.626640
7527 14:00:14.630040 CA PerBit enable=1, Macro0, CA PI delay=35
7528 14:00:14.630142
7529 14:00:14.633400 [CBTSetCACLKResult] CA Dly = 35
7530 14:00:14.637077 CS Dly: 10 (0~42)
7531 14:00:14.639902 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 14:00:14.643140 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 14:00:14.643247
7534 14:00:14.646670 ----->DramcWriteLeveling(PI) begin...
7535 14:00:14.646774 ==
7536 14:00:14.650237 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 14:00:14.653329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 14:00:14.656567 ==
7539 14:00:14.656676 Write leveling (Byte 0): 37 => 37
7540 14:00:14.660269 Write leveling (Byte 1): 28 => 28
7541 14:00:14.663735 DramcWriteLeveling(PI) end<-----
7542 14:00:14.663813
7543 14:00:14.663877 ==
7544 14:00:14.666640 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 14:00:14.673671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 14:00:14.673756 ==
7547 14:00:14.676794 [Gating] SW mode calibration
7548 14:00:14.683218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7549 14:00:14.686829 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7550 14:00:14.693349 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 14:00:14.696582 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 14:00:14.699849 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7553 14:00:14.706844 1 4 12 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)
7554 14:00:14.710107 1 4 16 | B1->B0 | 2525 3635 | 0 1 | (0 0) (0 0)
7555 14:00:14.713124 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7556 14:00:14.716739 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7557 14:00:14.723281 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7558 14:00:14.726535 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7559 14:00:14.729861 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7560 14:00:14.737000 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7561 14:00:14.739887 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
7562 14:00:14.742927 1 5 16 | B1->B0 | 3434 2928 | 1 1 | (1 0) (0 0)
7563 14:00:14.749778 1 5 20 | B1->B0 | 2828 2727 | 1 0 | (1 0) (0 0)
7564 14:00:14.753215 1 5 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7565 14:00:14.756785 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
7566 14:00:14.762927 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7567 14:00:14.766370 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7568 14:00:14.769880 1 6 8 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7569 14:00:14.776311 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7570 14:00:14.779739 1 6 16 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
7571 14:00:14.783013 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7572 14:00:14.789605 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 14:00:14.793315 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 14:00:14.796645 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 14:00:14.803142 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 14:00:14.806328 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 14:00:14.809387 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 14:00:14.816415 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7579 14:00:14.819620 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 14:00:14.822956 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 14:00:14.826134 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 14:00:14.833005 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 14:00:14.836519 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 14:00:14.839829 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 14:00:14.846373 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 14:00:14.849442 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 14:00:14.852837 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 14:00:14.859779 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 14:00:14.862834 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 14:00:14.866210 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 14:00:14.872834 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 14:00:14.876387 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7593 14:00:14.879409 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 14:00:14.886176 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7595 14:00:14.889520 Total UI for P1: 0, mck2ui 16
7596 14:00:14.892866 best dqsien dly found for B0: ( 1, 9, 10)
7597 14:00:14.896191 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7598 14:00:14.899303 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 14:00:14.902722 Total UI for P1: 0, mck2ui 16
7600 14:00:14.905670 best dqsien dly found for B1: ( 1, 9, 20)
7601 14:00:14.909343 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7602 14:00:14.912805 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7603 14:00:14.912909
7604 14:00:14.919432 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7605 14:00:14.922700 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7606 14:00:14.926007 [Gating] SW calibration Done
7607 14:00:14.926108 ==
7608 14:00:14.929344 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 14:00:14.933110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 14:00:14.933195 ==
7611 14:00:14.933263 RX Vref Scan: 0
7612 14:00:14.933326
7613 14:00:14.935748 RX Vref 0 -> 0, step: 1
7614 14:00:14.935832
7615 14:00:14.939348 RX Delay 0 -> 252, step: 8
7616 14:00:14.942475 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7617 14:00:14.945587 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7618 14:00:14.952614 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7619 14:00:14.955715 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7620 14:00:14.959103 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7621 14:00:14.962634 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7622 14:00:14.965695 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7623 14:00:14.969214 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7624 14:00:14.975629 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7625 14:00:14.979255 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7626 14:00:14.982346 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7627 14:00:14.986090 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7628 14:00:14.989219 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7629 14:00:14.995602 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7630 14:00:14.998983 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7631 14:00:15.002353 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7632 14:00:15.002481 ==
7633 14:00:15.005876 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 14:00:15.008868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 14:00:15.012448 ==
7636 14:00:15.012571 DQS Delay:
7637 14:00:15.012692 DQS0 = 0, DQS1 = 0
7638 14:00:15.015420 DQM Delay:
7639 14:00:15.015544 DQM0 = 137, DQM1 = 130
7640 14:00:15.019060 DQ Delay:
7641 14:00:15.022080 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7642 14:00:15.025707 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7643 14:00:15.028711 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7644 14:00:15.032157 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7645 14:00:15.032282
7646 14:00:15.032397
7647 14:00:15.032512 ==
7648 14:00:15.035706 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 14:00:15.038841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 14:00:15.038971 ==
7651 14:00:15.039088
7652 14:00:15.042151
7653 14:00:15.042263 TX Vref Scan disable
7654 14:00:15.045419 == TX Byte 0 ==
7655 14:00:15.048710 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7656 14:00:15.052264 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7657 14:00:15.055570 == TX Byte 1 ==
7658 14:00:15.058861 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7659 14:00:15.062143 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7660 14:00:15.062271 ==
7661 14:00:15.065226 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 14:00:15.071686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 14:00:15.071816 ==
7664 14:00:15.083582
7665 14:00:15.086428 TX Vref early break, caculate TX vref
7666 14:00:15.090112 TX Vref=16, minBit 3, minWin=22, winSum=378
7667 14:00:15.093102 TX Vref=18, minBit 0, minWin=23, winSum=384
7668 14:00:15.096870 TX Vref=20, minBit 4, minWin=23, winSum=396
7669 14:00:15.100097 TX Vref=22, minBit 1, minWin=24, winSum=407
7670 14:00:15.103068 TX Vref=24, minBit 0, minWin=25, winSum=413
7671 14:00:15.109842 TX Vref=26, minBit 2, minWin=25, winSum=419
7672 14:00:15.113441 TX Vref=28, minBit 1, minWin=25, winSum=425
7673 14:00:15.116842 TX Vref=30, minBit 1, minWin=24, winSum=407
7674 14:00:15.120016 TX Vref=32, minBit 6, minWin=23, winSum=401
7675 14:00:15.126613 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 28
7676 14:00:15.126734
7677 14:00:15.126848 Final TX Range 0 Vref 28
7678 14:00:15.130127
7679 14:00:15.130246 ==
7680 14:00:15.133216 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 14:00:15.136687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 14:00:15.136808 ==
7683 14:00:15.136925
7684 14:00:15.137029
7685 14:00:15.140074 TX Vref Scan disable
7686 14:00:15.143555 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7687 14:00:15.146468 == TX Byte 0 ==
7688 14:00:15.149846 u2DelayCellOfst[0]=10 cells (3 PI)
7689 14:00:15.153414 u2DelayCellOfst[1]=13 cells (4 PI)
7690 14:00:15.156315 u2DelayCellOfst[2]=10 cells (3 PI)
7691 14:00:15.159867 u2DelayCellOfst[3]=10 cells (3 PI)
7692 14:00:15.159992 u2DelayCellOfst[4]=6 cells (2 PI)
7693 14:00:15.163577 u2DelayCellOfst[5]=0 cells (0 PI)
7694 14:00:15.166694 u2DelayCellOfst[6]=16 cells (5 PI)
7695 14:00:15.170067 u2DelayCellOfst[7]=16 cells (5 PI)
7696 14:00:15.176754 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7697 14:00:15.179919 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7698 14:00:15.180040 == TX Byte 1 ==
7699 14:00:15.183257 u2DelayCellOfst[8]=0 cells (0 PI)
7700 14:00:15.186675 u2DelayCellOfst[9]=0 cells (0 PI)
7701 14:00:15.190272 u2DelayCellOfst[10]=10 cells (3 PI)
7702 14:00:15.193820 u2DelayCellOfst[11]=3 cells (1 PI)
7703 14:00:15.196677 u2DelayCellOfst[12]=10 cells (3 PI)
7704 14:00:15.199643 u2DelayCellOfst[13]=10 cells (3 PI)
7705 14:00:15.203464 u2DelayCellOfst[14]=13 cells (4 PI)
7706 14:00:15.206957 u2DelayCellOfst[15]=13 cells (4 PI)
7707 14:00:15.209769 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7708 14:00:15.213365 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7709 14:00:15.216670 DramC Write-DBI on
7710 14:00:15.216777 ==
7711 14:00:15.219931 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 14:00:15.222970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 14:00:15.223055 ==
7714 14:00:15.223121
7715 14:00:15.223182
7716 14:00:15.226541 TX Vref Scan disable
7717 14:00:15.230158 == TX Byte 0 ==
7718 14:00:15.233195 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7719 14:00:15.233280 == TX Byte 1 ==
7720 14:00:15.239795 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7721 14:00:15.239906 DramC Write-DBI off
7722 14:00:15.240003
7723 14:00:15.243194 [DATLAT]
7724 14:00:15.243277 Freq=1600, CH0 RK0
7725 14:00:15.243344
7726 14:00:15.246765 DATLAT Default: 0xf
7727 14:00:15.246849 0, 0xFFFF, sum = 0
7728 14:00:15.250209 1, 0xFFFF, sum = 0
7729 14:00:15.250294 2, 0xFFFF, sum = 0
7730 14:00:15.253095 3, 0xFFFF, sum = 0
7731 14:00:15.253180 4, 0xFFFF, sum = 0
7732 14:00:15.256672 5, 0xFFFF, sum = 0
7733 14:00:15.256758 6, 0xFFFF, sum = 0
7734 14:00:15.260182 7, 0xFFFF, sum = 0
7735 14:00:15.260267 8, 0xFFFF, sum = 0
7736 14:00:15.263334 9, 0xFFFF, sum = 0
7737 14:00:15.263420 10, 0xFFFF, sum = 0
7738 14:00:15.266510 11, 0xFFFF, sum = 0
7739 14:00:15.266595 12, 0xFFFF, sum = 0
7740 14:00:15.269657 13, 0xFFFF, sum = 0
7741 14:00:15.269770 14, 0x0, sum = 1
7742 14:00:15.273076 15, 0x0, sum = 2
7743 14:00:15.273178 16, 0x0, sum = 3
7744 14:00:15.276488 17, 0x0, sum = 4
7745 14:00:15.276565 best_step = 15
7746 14:00:15.276629
7747 14:00:15.276690 ==
7748 14:00:15.279824 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 14:00:15.286192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 14:00:15.286291 ==
7751 14:00:15.286358 RX Vref Scan: 1
7752 14:00:15.286420
7753 14:00:15.289809 Set Vref Range= 24 -> 127
7754 14:00:15.289886
7755 14:00:15.293057 RX Vref 24 -> 127, step: 1
7756 14:00:15.293130
7757 14:00:15.296610 RX Delay 19 -> 252, step: 4
7758 14:00:15.296686
7759 14:00:15.296754 Set Vref, RX VrefLevel [Byte0]: 24
7760 14:00:15.299912 [Byte1]: 24
7761 14:00:15.304155
7762 14:00:15.304264 Set Vref, RX VrefLevel [Byte0]: 25
7763 14:00:15.307906 [Byte1]: 25
7764 14:00:15.311922
7765 14:00:15.312029 Set Vref, RX VrefLevel [Byte0]: 26
7766 14:00:15.314808 [Byte1]: 26
7767 14:00:15.319094
7768 14:00:15.319175 Set Vref, RX VrefLevel [Byte0]: 27
7769 14:00:15.322776 [Byte1]: 27
7770 14:00:15.326832
7771 14:00:15.326912 Set Vref, RX VrefLevel [Byte0]: 28
7772 14:00:15.329836 [Byte1]: 28
7773 14:00:15.334565
7774 14:00:15.334670 Set Vref, RX VrefLevel [Byte0]: 29
7775 14:00:15.337428 [Byte1]: 29
7776 14:00:15.341697
7777 14:00:15.341828 Set Vref, RX VrefLevel [Byte0]: 30
7778 14:00:15.345244 [Byte1]: 30
7779 14:00:15.349628
7780 14:00:15.349752 Set Vref, RX VrefLevel [Byte0]: 31
7781 14:00:15.352920 [Byte1]: 31
7782 14:00:15.357321
7783 14:00:15.357426 Set Vref, RX VrefLevel [Byte0]: 32
7784 14:00:15.360487 [Byte1]: 32
7785 14:00:15.365264
7786 14:00:15.365392 Set Vref, RX VrefLevel [Byte0]: 33
7787 14:00:15.367897 [Byte1]: 33
7788 14:00:15.372129
7789 14:00:15.372256 Set Vref, RX VrefLevel [Byte0]: 34
7790 14:00:15.375440 [Byte1]: 34
7791 14:00:15.379785
7792 14:00:15.379909 Set Vref, RX VrefLevel [Byte0]: 35
7793 14:00:15.383071 [Byte1]: 35
7794 14:00:15.387564
7795 14:00:15.387693 Set Vref, RX VrefLevel [Byte0]: 36
7796 14:00:15.390881 [Byte1]: 36
7797 14:00:15.394914
7798 14:00:15.395037 Set Vref, RX VrefLevel [Byte0]: 37
7799 14:00:15.398281 [Byte1]: 37
7800 14:00:15.402393
7801 14:00:15.402518 Set Vref, RX VrefLevel [Byte0]: 38
7802 14:00:15.405629 [Byte1]: 38
7803 14:00:15.410124
7804 14:00:15.410241 Set Vref, RX VrefLevel [Byte0]: 39
7805 14:00:15.413322 [Byte1]: 39
7806 14:00:15.417728
7807 14:00:15.417855 Set Vref, RX VrefLevel [Byte0]: 40
7808 14:00:15.421171 [Byte1]: 40
7809 14:00:15.425176
7810 14:00:15.425300 Set Vref, RX VrefLevel [Byte0]: 41
7811 14:00:15.428699 [Byte1]: 41
7812 14:00:15.432737
7813 14:00:15.432843 Set Vref, RX VrefLevel [Byte0]: 42
7814 14:00:15.435892 [Byte1]: 42
7815 14:00:15.440605
7816 14:00:15.440704 Set Vref, RX VrefLevel [Byte0]: 43
7817 14:00:15.443762 [Byte1]: 43
7818 14:00:15.447931
7819 14:00:15.448017 Set Vref, RX VrefLevel [Byte0]: 44
7820 14:00:15.451440 [Byte1]: 44
7821 14:00:15.455729
7822 14:00:15.455811 Set Vref, RX VrefLevel [Byte0]: 45
7823 14:00:15.458735 [Byte1]: 45
7824 14:00:15.462920
7825 14:00:15.463003 Set Vref, RX VrefLevel [Byte0]: 46
7826 14:00:15.466761 [Byte1]: 46
7827 14:00:15.470537
7828 14:00:15.470622 Set Vref, RX VrefLevel [Byte0]: 47
7829 14:00:15.474093 [Byte1]: 47
7830 14:00:15.478654
7831 14:00:15.478738 Set Vref, RX VrefLevel [Byte0]: 48
7832 14:00:15.481351 [Byte1]: 48
7833 14:00:15.485589
7834 14:00:15.485673 Set Vref, RX VrefLevel [Byte0]: 49
7835 14:00:15.488860 [Byte1]: 49
7836 14:00:15.493307
7837 14:00:15.493391 Set Vref, RX VrefLevel [Byte0]: 50
7838 14:00:15.496480 [Byte1]: 50
7839 14:00:15.500992
7840 14:00:15.501122 Set Vref, RX VrefLevel [Byte0]: 51
7841 14:00:15.504234 [Byte1]: 51
7842 14:00:15.508798
7843 14:00:15.508922 Set Vref, RX VrefLevel [Byte0]: 52
7844 14:00:15.511690 [Byte1]: 52
7845 14:00:15.515939
7846 14:00:15.516061 Set Vref, RX VrefLevel [Byte0]: 53
7847 14:00:15.519385 [Byte1]: 53
7848 14:00:15.523499
7849 14:00:15.523620 Set Vref, RX VrefLevel [Byte0]: 54
7850 14:00:15.527041 [Byte1]: 54
7851 14:00:15.531405
7852 14:00:15.531527 Set Vref, RX VrefLevel [Byte0]: 55
7853 14:00:15.534327 [Byte1]: 55
7854 14:00:15.538801
7855 14:00:15.538927 Set Vref, RX VrefLevel [Byte0]: 56
7856 14:00:15.542262 [Byte1]: 56
7857 14:00:15.546147
7858 14:00:15.546259 Set Vref, RX VrefLevel [Byte0]: 57
7859 14:00:15.549910 [Byte1]: 57
7860 14:00:15.554041
7861 14:00:15.554143 Set Vref, RX VrefLevel [Byte0]: 58
7862 14:00:15.557506 [Byte1]: 58
7863 14:00:15.561698
7864 14:00:15.561798 Set Vref, RX VrefLevel [Byte0]: 59
7865 14:00:15.564645 [Byte1]: 59
7866 14:00:15.569084
7867 14:00:15.569189 Set Vref, RX VrefLevel [Byte0]: 60
7868 14:00:15.572288 [Byte1]: 60
7869 14:00:15.576622
7870 14:00:15.576739 Set Vref, RX VrefLevel [Byte0]: 61
7871 14:00:15.579828 [Byte1]: 61
7872 14:00:15.584722
7873 14:00:15.584854 Set Vref, RX VrefLevel [Byte0]: 62
7874 14:00:15.587646 [Byte1]: 62
7875 14:00:15.592108
7876 14:00:15.592195 Set Vref, RX VrefLevel [Byte0]: 63
7877 14:00:15.595305 [Byte1]: 63
7878 14:00:15.599331
7879 14:00:15.599460 Set Vref, RX VrefLevel [Byte0]: 64
7880 14:00:15.602547 [Byte1]: 64
7881 14:00:15.607128
7882 14:00:15.607251 Set Vref, RX VrefLevel [Byte0]: 65
7883 14:00:15.609993 [Byte1]: 65
7884 14:00:15.614574
7885 14:00:15.614652 Set Vref, RX VrefLevel [Byte0]: 66
7886 14:00:15.617834 [Byte1]: 66
7887 14:00:15.621892
7888 14:00:15.622017 Set Vref, RX VrefLevel [Byte0]: 67
7889 14:00:15.625750 [Byte1]: 67
7890 14:00:15.629854
7891 14:00:15.629975 Set Vref, RX VrefLevel [Byte0]: 68
7892 14:00:15.633116 [Byte1]: 68
7893 14:00:15.637185
7894 14:00:15.637307 Set Vref, RX VrefLevel [Byte0]: 69
7895 14:00:15.640681 [Byte1]: 69
7896 14:00:15.644650
7897 14:00:15.644776 Set Vref, RX VrefLevel [Byte0]: 70
7898 14:00:15.648164 [Byte1]: 70
7899 14:00:15.652525
7900 14:00:15.652648 Set Vref, RX VrefLevel [Byte0]: 71
7901 14:00:15.655747 [Byte1]: 71
7902 14:00:15.659752
7903 14:00:15.659877 Set Vref, RX VrefLevel [Byte0]: 72
7904 14:00:15.663500 [Byte1]: 72
7905 14:00:15.667392
7906 14:00:15.667514 Set Vref, RX VrefLevel [Byte0]: 73
7907 14:00:15.670722 [Byte1]: 73
7908 14:00:15.675244
7909 14:00:15.675357 Set Vref, RX VrefLevel [Byte0]: 74
7910 14:00:15.678200 [Byte1]: 74
7911 14:00:15.682563
7912 14:00:15.682666 Set Vref, RX VrefLevel [Byte0]: 75
7913 14:00:15.685785 [Byte1]: 75
7914 14:00:15.690250
7915 14:00:15.690370 Final RX Vref Byte 0 = 54 to rank0
7916 14:00:15.693841 Final RX Vref Byte 1 = 59 to rank0
7917 14:00:15.697252 Final RX Vref Byte 0 = 54 to rank1
7918 14:00:15.699919 Final RX Vref Byte 1 = 59 to rank1==
7919 14:00:15.704053 Dram Type= 6, Freq= 0, CH_0, rank 0
7920 14:00:15.710369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7921 14:00:15.710504 ==
7922 14:00:15.710594 DQS Delay:
7923 14:00:15.710715 DQS0 = 0, DQS1 = 0
7924 14:00:15.713550 DQM Delay:
7925 14:00:15.713649 DQM0 = 133, DQM1 = 127
7926 14:00:15.716839 DQ Delay:
7927 14:00:15.720615 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7928 14:00:15.723420 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7929 14:00:15.726891 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7930 14:00:15.730400 DQ12 =130, DQ13 =134, DQ14 =138, DQ15 =134
7931 14:00:15.730505
7932 14:00:15.730596
7933 14:00:15.730694
7934 14:00:15.733442 [DramC_TX_OE_Calibration] TA2
7935 14:00:15.737016 Original DQ_B0 (3 6) =30, OEN = 27
7936 14:00:15.740497 Original DQ_B1 (3 6) =30, OEN = 27
7937 14:00:15.743555 24, 0x0, End_B0=24 End_B1=24
7938 14:00:15.743632 25, 0x0, End_B0=25 End_B1=25
7939 14:00:15.747154 26, 0x0, End_B0=26 End_B1=26
7940 14:00:15.750440 27, 0x0, End_B0=27 End_B1=27
7941 14:00:15.753897 28, 0x0, End_B0=28 End_B1=28
7942 14:00:15.754007 29, 0x0, End_B0=29 End_B1=29
7943 14:00:15.756718 30, 0x0, End_B0=30 End_B1=30
7944 14:00:15.760489 31, 0x4141, End_B0=30 End_B1=30
7945 14:00:15.763524 Byte0 end_step=30 best_step=27
7946 14:00:15.766701 Byte1 end_step=30 best_step=27
7947 14:00:15.770215 Byte0 TX OE(2T, 0.5T) = (3, 3)
7948 14:00:15.770328 Byte1 TX OE(2T, 0.5T) = (3, 3)
7949 14:00:15.773393
7950 14:00:15.773496
7951 14:00:15.780589 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7952 14:00:15.783377 CH0 RK0: MR19=303, MR18=2420
7953 14:00:15.789946 CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16
7954 14:00:15.790062
7955 14:00:15.793180 ----->DramcWriteLeveling(PI) begin...
7956 14:00:15.793266 ==
7957 14:00:15.796776 Dram Type= 6, Freq= 0, CH_0, rank 1
7958 14:00:15.800186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 14:00:15.800292 ==
7960 14:00:15.803456 Write leveling (Byte 0): 34 => 34
7961 14:00:15.806700 Write leveling (Byte 1): 27 => 27
7962 14:00:15.810058 DramcWriteLeveling(PI) end<-----
7963 14:00:15.810135
7964 14:00:15.810203 ==
7965 14:00:15.813387 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 14:00:15.816733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 14:00:15.816848 ==
7968 14:00:15.820031 [Gating] SW mode calibration
7969 14:00:15.826585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7970 14:00:15.833052 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7971 14:00:15.836049 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7972 14:00:15.839765 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7973 14:00:15.846468 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7974 14:00:15.849485 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7975 14:00:15.853062 1 4 16 | B1->B0 | 3131 3535 | 0 1 | (0 0) (1 1)
7976 14:00:15.859178 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7977 14:00:15.862367 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7978 14:00:15.866098 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7979 14:00:15.872837 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7980 14:00:15.876021 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7981 14:00:15.879183 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7982 14:00:15.886224 1 5 12 | B1->B0 | 3434 3130 | 1 1 | (1 0) (1 0)
7983 14:00:15.889302 1 5 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
7984 14:00:15.892367 1 5 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7985 14:00:15.899519 1 5 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7986 14:00:15.903063 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7987 14:00:15.906142 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7988 14:00:15.912885 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7989 14:00:15.915731 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
7990 14:00:15.918946 1 6 12 | B1->B0 | 2323 3b3a | 0 1 | (0 0) (0 0)
7991 14:00:15.925884 1 6 16 | B1->B0 | 3939 4645 | 0 1 | (0 0) (0 0)
7992 14:00:15.929168 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 14:00:15.932579 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 14:00:15.939269 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 14:00:15.942462 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 14:00:15.946151 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 14:00:15.952358 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 14:00:15.955928 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7999 14:00:15.959461 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8000 14:00:15.962735 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8001 14:00:15.969105 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 14:00:15.972581 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 14:00:15.976084 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 14:00:15.982543 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 14:00:15.985601 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 14:00:15.989133 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 14:00:15.995625 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 14:00:15.999002 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 14:00:16.002503 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 14:00:16.008916 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 14:00:16.012160 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 14:00:16.015670 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 14:00:16.022533 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 14:00:16.025834 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8015 14:00:16.028989 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 14:00:16.032444 Total UI for P1: 0, mck2ui 16
8017 14:00:16.035675 best dqsien dly found for B0: ( 1, 9, 12)
8018 14:00:16.039180 Total UI for P1: 0, mck2ui 16
8019 14:00:16.042223 best dqsien dly found for B1: ( 1, 9, 12)
8020 14:00:16.045377 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8021 14:00:16.049064 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8022 14:00:16.049164
8023 14:00:16.055723 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8024 14:00:16.059158 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8025 14:00:16.062202 [Gating] SW calibration Done
8026 14:00:16.062324 ==
8027 14:00:16.065772 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 14:00:16.068736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 14:00:16.068860 ==
8030 14:00:16.068970 RX Vref Scan: 0
8031 14:00:16.069082
8032 14:00:16.072389 RX Vref 0 -> 0, step: 1
8033 14:00:16.072511
8034 14:00:16.075426 RX Delay 0 -> 252, step: 8
8035 14:00:16.079048 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8036 14:00:16.082208 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8037 14:00:16.085254 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8038 14:00:16.092250 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8039 14:00:16.095202 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8040 14:00:16.098488 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8041 14:00:16.102299 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8042 14:00:16.105545 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8043 14:00:16.111855 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8044 14:00:16.115250 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8045 14:00:16.118394 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8046 14:00:16.122047 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8047 14:00:16.125273 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8048 14:00:16.131814 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8049 14:00:16.135317 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8050 14:00:16.138792 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8051 14:00:16.138877 ==
8052 14:00:16.142242 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 14:00:16.145403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 14:00:16.148981 ==
8055 14:00:16.149089 DQS Delay:
8056 14:00:16.149183 DQS0 = 0, DQS1 = 0
8057 14:00:16.151947 DQM Delay:
8058 14:00:16.152049 DQM0 = 136, DQM1 = 128
8059 14:00:16.155319 DQ Delay:
8060 14:00:16.158765 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8061 14:00:16.162471 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8062 14:00:16.165548 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8063 14:00:16.169076 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8064 14:00:16.169151
8065 14:00:16.169215
8066 14:00:16.169281 ==
8067 14:00:16.172199 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 14:00:16.175425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 14:00:16.175500 ==
8070 14:00:16.175563
8071 14:00:16.175622
8072 14:00:16.178550 TX Vref Scan disable
8073 14:00:16.182451 == TX Byte 0 ==
8074 14:00:16.185323 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8075 14:00:16.188787 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8076 14:00:16.191697 == TX Byte 1 ==
8077 14:00:16.195266 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8078 14:00:16.198381 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8079 14:00:16.198479 ==
8080 14:00:16.201893 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 14:00:16.208054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 14:00:16.208138 ==
8083 14:00:16.220659
8084 14:00:16.224329 TX Vref early break, caculate TX vref
8085 14:00:16.227265 TX Vref=16, minBit 3, minWin=23, winSum=391
8086 14:00:16.230737 TX Vref=18, minBit 0, minWin=24, winSum=399
8087 14:00:16.234070 TX Vref=20, minBit 1, minWin=24, winSum=409
8088 14:00:16.237528 TX Vref=22, minBit 1, minWin=24, winSum=412
8089 14:00:16.240762 TX Vref=24, minBit 1, minWin=25, winSum=421
8090 14:00:16.247226 TX Vref=26, minBit 1, minWin=25, winSum=424
8091 14:00:16.250681 TX Vref=28, minBit 0, minWin=26, winSum=423
8092 14:00:16.254587 TX Vref=30, minBit 7, minWin=25, winSum=420
8093 14:00:16.257915 TX Vref=32, minBit 0, minWin=25, winSum=411
8094 14:00:16.261281 TX Vref=34, minBit 0, minWin=24, winSum=401
8095 14:00:16.267362 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
8096 14:00:16.267449
8097 14:00:16.271166 Final TX Range 0 Vref 28
8098 14:00:16.271250
8099 14:00:16.271318 ==
8100 14:00:16.274285 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 14:00:16.277462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 14:00:16.277546 ==
8103 14:00:16.277612
8104 14:00:16.277674
8105 14:00:16.281019 TX Vref Scan disable
8106 14:00:16.287547 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8107 14:00:16.287664 == TX Byte 0 ==
8108 14:00:16.290688 u2DelayCellOfst[0]=13 cells (4 PI)
8109 14:00:16.294266 u2DelayCellOfst[1]=13 cells (4 PI)
8110 14:00:16.297343 u2DelayCellOfst[2]=10 cells (3 PI)
8111 14:00:16.300758 u2DelayCellOfst[3]=10 cells (3 PI)
8112 14:00:16.304044 u2DelayCellOfst[4]=6 cells (2 PI)
8113 14:00:16.307537 u2DelayCellOfst[5]=0 cells (0 PI)
8114 14:00:16.310941 u2DelayCellOfst[6]=16 cells (5 PI)
8115 14:00:16.311023 u2DelayCellOfst[7]=13 cells (4 PI)
8116 14:00:16.317404 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8117 14:00:16.320447 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8118 14:00:16.323986 == TX Byte 1 ==
8119 14:00:16.324069 u2DelayCellOfst[8]=0 cells (0 PI)
8120 14:00:16.326888 u2DelayCellOfst[9]=0 cells (0 PI)
8121 14:00:16.330373 u2DelayCellOfst[10]=3 cells (1 PI)
8122 14:00:16.334057 u2DelayCellOfst[11]=0 cells (0 PI)
8123 14:00:16.336943 u2DelayCellOfst[12]=10 cells (3 PI)
8124 14:00:16.340346 u2DelayCellOfst[13]=6 cells (2 PI)
8125 14:00:16.343763 u2DelayCellOfst[14]=10 cells (3 PI)
8126 14:00:16.347004 u2DelayCellOfst[15]=6 cells (2 PI)
8127 14:00:16.350790 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8128 14:00:16.354035 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8129 14:00:16.356892 DramC Write-DBI on
8130 14:00:16.356985 ==
8131 14:00:16.360331 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 14:00:16.363872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 14:00:16.363951 ==
8134 14:00:16.364020
8135 14:00:16.366877
8136 14:00:16.366953 TX Vref Scan disable
8137 14:00:16.370076 == TX Byte 0 ==
8138 14:00:16.373720 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8139 14:00:16.376970 == TX Byte 1 ==
8140 14:00:16.380466 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8141 14:00:16.380559 DramC Write-DBI off
8142 14:00:16.380626
8143 14:00:16.383552 [DATLAT]
8144 14:00:16.383661 Freq=1600, CH0 RK1
8145 14:00:16.383729
8146 14:00:16.386920 DATLAT Default: 0xf
8147 14:00:16.386992 0, 0xFFFF, sum = 0
8148 14:00:16.390162 1, 0xFFFF, sum = 0
8149 14:00:16.390236 2, 0xFFFF, sum = 0
8150 14:00:16.393597 3, 0xFFFF, sum = 0
8151 14:00:16.393683 4, 0xFFFF, sum = 0
8152 14:00:16.397290 5, 0xFFFF, sum = 0
8153 14:00:16.397365 6, 0xFFFF, sum = 0
8154 14:00:16.400321 7, 0xFFFF, sum = 0
8155 14:00:16.403670 8, 0xFFFF, sum = 0
8156 14:00:16.403748 9, 0xFFFF, sum = 0
8157 14:00:16.406732 10, 0xFFFF, sum = 0
8158 14:00:16.406834 11, 0xFFFF, sum = 0
8159 14:00:16.410379 12, 0xFFFF, sum = 0
8160 14:00:16.410488 13, 0xFFFF, sum = 0
8161 14:00:16.413370 14, 0x0, sum = 1
8162 14:00:16.413441 15, 0x0, sum = 2
8163 14:00:16.416605 16, 0x0, sum = 3
8164 14:00:16.416679 17, 0x0, sum = 4
8165 14:00:16.420094 best_step = 15
8166 14:00:16.420169
8167 14:00:16.420231 ==
8168 14:00:16.423717 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 14:00:16.427213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 14:00:16.427286 ==
8171 14:00:16.427353 RX Vref Scan: 0
8172 14:00:16.427426
8173 14:00:16.430738 RX Vref 0 -> 0, step: 1
8174 14:00:16.430847
8175 14:00:16.433398 RX Delay 19 -> 252, step: 4
8176 14:00:16.437060 iDelay=191, Bit 0, Center 132 (79 ~ 186) 108
8177 14:00:16.443415 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8178 14:00:16.447182 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8179 14:00:16.450434 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8180 14:00:16.453557 iDelay=191, Bit 4, Center 138 (87 ~ 190) 104
8181 14:00:16.456909 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8182 14:00:16.460263 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8183 14:00:16.466673 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8184 14:00:16.470026 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8185 14:00:16.473801 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8186 14:00:16.477097 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8187 14:00:16.480104 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8188 14:00:16.486603 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8189 14:00:16.490161 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8190 14:00:16.493278 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8191 14:00:16.496652 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8192 14:00:16.496728 ==
8193 14:00:16.500100 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 14:00:16.506571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 14:00:16.506656 ==
8196 14:00:16.506724 DQS Delay:
8197 14:00:16.509819 DQS0 = 0, DQS1 = 0
8198 14:00:16.509903 DQM Delay:
8199 14:00:16.513352 DQM0 = 134, DQM1 = 127
8200 14:00:16.513425 DQ Delay:
8201 14:00:16.516915 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
8202 14:00:16.519844 DQ4 =138, DQ5 =124, DQ6 =140, DQ7 =142
8203 14:00:16.523420 DQ8 =118, DQ9 =116, DQ10 =130, DQ11 =118
8204 14:00:16.527138 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8205 14:00:16.527210
8206 14:00:16.527279
8207 14:00:16.527339
8208 14:00:16.529922 [DramC_TX_OE_Calibration] TA2
8209 14:00:16.533719 Original DQ_B0 (3 6) =30, OEN = 27
8210 14:00:16.536422 Original DQ_B1 (3 6) =30, OEN = 27
8211 14:00:16.540086 24, 0x0, End_B0=24 End_B1=24
8212 14:00:16.540174 25, 0x0, End_B0=25 End_B1=25
8213 14:00:16.543755 26, 0x0, End_B0=26 End_B1=26
8214 14:00:16.546589 27, 0x0, End_B0=27 End_B1=27
8215 14:00:16.550226 28, 0x0, End_B0=28 End_B1=28
8216 14:00:16.553233 29, 0x0, End_B0=29 End_B1=29
8217 14:00:16.553346 30, 0x0, End_B0=30 End_B1=30
8218 14:00:16.556746 31, 0x4141, End_B0=30 End_B1=30
8219 14:00:16.559756 Byte0 end_step=30 best_step=27
8220 14:00:16.563495 Byte1 end_step=30 best_step=27
8221 14:00:16.566602 Byte0 TX OE(2T, 0.5T) = (3, 3)
8222 14:00:16.570168 Byte1 TX OE(2T, 0.5T) = (3, 3)
8223 14:00:16.570243
8224 14:00:16.570307
8225 14:00:16.576918 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8226 14:00:16.579988 CH0 RK1: MR19=303, MR18=2008
8227 14:00:16.586669 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8228 14:00:16.589629 [RxdqsGatingPostProcess] freq 1600
8229 14:00:16.592971 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8230 14:00:16.596488 best DQS0 dly(2T, 0.5T) = (1, 1)
8231 14:00:16.599651 best DQS1 dly(2T, 0.5T) = (1, 1)
8232 14:00:16.603061 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8233 14:00:16.606441 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8234 14:00:16.609509 best DQS0 dly(2T, 0.5T) = (1, 1)
8235 14:00:16.613068 best DQS1 dly(2T, 0.5T) = (1, 1)
8236 14:00:16.616619 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8237 14:00:16.620013 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8238 14:00:16.623409 Pre-setting of DQS Precalculation
8239 14:00:16.626574 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8240 14:00:16.626659 ==
8241 14:00:16.630015 Dram Type= 6, Freq= 0, CH_1, rank 0
8242 14:00:16.632967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 14:00:16.633050 ==
8244 14:00:16.639942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8245 14:00:16.642884 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8246 14:00:16.649741 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8247 14:00:16.653187 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8248 14:00:16.663419 [CA 0] Center 42 (13~72) winsize 60
8249 14:00:16.666448 [CA 1] Center 42 (13~72) winsize 60
8250 14:00:16.669926 [CA 2] Center 39 (10~68) winsize 59
8251 14:00:16.673100 [CA 3] Center 39 (10~68) winsize 59
8252 14:00:16.676664 [CA 4] Center 38 (9~68) winsize 60
8253 14:00:16.679825 [CA 5] Center 37 (8~67) winsize 60
8254 14:00:16.679898
8255 14:00:16.683175 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8256 14:00:16.683248
8257 14:00:16.686708 [CATrainingPosCal] consider 1 rank data
8258 14:00:16.689809 u2DelayCellTimex100 = 290/100 ps
8259 14:00:16.696372 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8260 14:00:16.699921 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8261 14:00:16.702871 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8262 14:00:16.706560 CA3 delay=39 (10~68),Diff = 2 PI (6 cell)
8263 14:00:16.709626 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8264 14:00:16.713236 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8265 14:00:16.713315
8266 14:00:16.716443 CA PerBit enable=1, Macro0, CA PI delay=37
8267 14:00:16.716522
8268 14:00:16.719737 [CBTSetCACLKResult] CA Dly = 37
8269 14:00:16.723279 CS Dly: 12 (0~43)
8270 14:00:16.726514 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8271 14:00:16.729843 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8272 14:00:16.729916 ==
8273 14:00:16.733165 Dram Type= 6, Freq= 0, CH_1, rank 1
8274 14:00:16.736349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 14:00:16.739588 ==
8276 14:00:16.742911 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8277 14:00:16.746331 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8278 14:00:16.752882 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8279 14:00:16.759131 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8280 14:00:16.766645 [CA 0] Center 42 (13~72) winsize 60
8281 14:00:16.769756 [CA 1] Center 42 (13~72) winsize 60
8282 14:00:16.773138 [CA 2] Center 39 (10~69) winsize 60
8283 14:00:16.776743 [CA 3] Center 38 (9~68) winsize 60
8284 14:00:16.780115 [CA 4] Center 39 (9~69) winsize 61
8285 14:00:16.783388 [CA 5] Center 38 (9~68) winsize 60
8286 14:00:16.783462
8287 14:00:16.786726 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8288 14:00:16.786797
8289 14:00:16.789803 [CATrainingPosCal] consider 2 rank data
8290 14:00:16.793396 u2DelayCellTimex100 = 290/100 ps
8291 14:00:16.796486 CA0 delay=42 (13~72),Diff = 4 PI (13 cell)
8292 14:00:16.803187 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8293 14:00:16.806932 CA2 delay=39 (10~68),Diff = 1 PI (3 cell)
8294 14:00:16.809888 CA3 delay=39 (10~68),Diff = 1 PI (3 cell)
8295 14:00:16.813154 CA4 delay=38 (9~68),Diff = 0 PI (0 cell)
8296 14:00:16.816432 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8297 14:00:16.816503
8298 14:00:16.819740 CA PerBit enable=1, Macro0, CA PI delay=38
8299 14:00:16.819815
8300 14:00:16.823251 [CBTSetCACLKResult] CA Dly = 38
8301 14:00:16.826819 CS Dly: 12 (0~44)
8302 14:00:16.829989 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8303 14:00:16.833375 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8304 14:00:16.833453
8305 14:00:16.836722 ----->DramcWriteLeveling(PI) begin...
8306 14:00:16.836794 ==
8307 14:00:16.839538 Dram Type= 6, Freq= 0, CH_1, rank 0
8308 14:00:16.846750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 14:00:16.846879 ==
8310 14:00:16.850237 Write leveling (Byte 0): 25 => 25
8311 14:00:16.850343 Write leveling (Byte 1): 26 => 26
8312 14:00:16.853200 DramcWriteLeveling(PI) end<-----
8313 14:00:16.853273
8314 14:00:16.853334 ==
8315 14:00:16.856347 Dram Type= 6, Freq= 0, CH_1, rank 0
8316 14:00:16.863148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 14:00:16.863259 ==
8318 14:00:16.866692 [Gating] SW mode calibration
8319 14:00:16.873249 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8320 14:00:16.876229 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8321 14:00:16.883056 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 14:00:16.886162 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 14:00:16.889548 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8324 14:00:16.896376 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8325 14:00:16.899948 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 14:00:16.903093 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 14:00:16.909494 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 14:00:16.912995 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 14:00:16.916070 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 14:00:16.919495 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 14:00:16.926204 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
8332 14:00:16.929430 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
8333 14:00:16.933061 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 14:00:16.939764 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 14:00:16.943277 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 14:00:16.945796 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 14:00:16.952772 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 14:00:16.955974 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 14:00:16.959158 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
8340 14:00:16.966601 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8341 14:00:16.969691 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 14:00:16.972604 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 14:00:16.979216 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 14:00:16.982653 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 14:00:16.985810 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 14:00:16.992502 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 14:00:16.995566 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8348 14:00:16.999158 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8349 14:00:17.005998 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 14:00:17.008699 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 14:00:17.012077 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 14:00:17.018931 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 14:00:17.022062 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 14:00:17.025479 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 14:00:17.032216 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 14:00:17.035344 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 14:00:17.038932 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 14:00:17.045489 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 14:00:17.048950 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 14:00:17.051806 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 14:00:17.058654 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 14:00:17.062037 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 14:00:17.065600 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8364 14:00:17.072167 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8365 14:00:17.075545 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 14:00:17.078971 Total UI for P1: 0, mck2ui 16
8367 14:00:17.081870 best dqsien dly found for B0: ( 1, 9, 10)
8368 14:00:17.085556 Total UI for P1: 0, mck2ui 16
8369 14:00:17.088393 best dqsien dly found for B1: ( 1, 9, 10)
8370 14:00:17.092297 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8371 14:00:17.095193 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8372 14:00:17.095269
8373 14:00:17.098776 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8374 14:00:17.101688 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8375 14:00:17.105174 [Gating] SW calibration Done
8376 14:00:17.105257 ==
8377 14:00:17.108565 Dram Type= 6, Freq= 0, CH_1, rank 0
8378 14:00:17.111515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8379 14:00:17.115435 ==
8380 14:00:17.115508 RX Vref Scan: 0
8381 14:00:17.115571
8382 14:00:17.118551 RX Vref 0 -> 0, step: 1
8383 14:00:17.118618
8384 14:00:17.118678 RX Delay 0 -> 252, step: 8
8385 14:00:17.124791 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8386 14:00:17.128392 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8387 14:00:17.131630 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8388 14:00:17.135077 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8389 14:00:17.138217 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8390 14:00:17.144853 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8391 14:00:17.148001 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8392 14:00:17.151467 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8393 14:00:17.154861 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8394 14:00:17.158447 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8395 14:00:17.165000 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8396 14:00:17.168131 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8397 14:00:17.171922 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8398 14:00:17.175080 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8399 14:00:17.178027 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8400 14:00:17.185100 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8401 14:00:17.185176 ==
8402 14:00:17.187841 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 14:00:17.191196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 14:00:17.191274 ==
8405 14:00:17.191336 DQS Delay:
8406 14:00:17.194693 DQS0 = 0, DQS1 = 0
8407 14:00:17.194767 DQM Delay:
8408 14:00:17.198338 DQM0 = 136, DQM1 = 132
8409 14:00:17.198413 DQ Delay:
8410 14:00:17.201236 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8411 14:00:17.205182 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8412 14:00:17.207897 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8413 14:00:17.211404 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8414 14:00:17.215027
8415 14:00:17.215097
8416 14:00:17.215158 ==
8417 14:00:17.217963 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 14:00:17.221650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 14:00:17.221719 ==
8420 14:00:17.221786
8421 14:00:17.221843
8422 14:00:17.224479 TX Vref Scan disable
8423 14:00:17.224549 == TX Byte 0 ==
8424 14:00:17.228528 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8425 14:00:17.234575 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8426 14:00:17.234654 == TX Byte 1 ==
8427 14:00:17.241210 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8428 14:00:17.244704 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8429 14:00:17.244776 ==
8430 14:00:17.247918 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 14:00:17.251316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 14:00:17.251409 ==
8433 14:00:17.264149
8434 14:00:17.267443 TX Vref early break, caculate TX vref
8435 14:00:17.270720 TX Vref=16, minBit 1, minWin=22, winSum=379
8436 14:00:17.274083 TX Vref=18, minBit 1, minWin=23, winSum=391
8437 14:00:17.277425 TX Vref=20, minBit 0, minWin=23, winSum=393
8438 14:00:17.281035 TX Vref=22, minBit 1, minWin=24, winSum=410
8439 14:00:17.284242 TX Vref=24, minBit 0, minWin=25, winSum=420
8440 14:00:17.290795 TX Vref=26, minBit 1, minWin=25, winSum=430
8441 14:00:17.294567 TX Vref=28, minBit 0, minWin=25, winSum=429
8442 14:00:17.297338 TX Vref=30, minBit 6, minWin=24, winSum=421
8443 14:00:17.300744 TX Vref=32, minBit 6, minWin=24, winSum=417
8444 14:00:17.304108 TX Vref=34, minBit 0, minWin=24, winSum=404
8445 14:00:17.310948 [TxChooseVref] Worse bit 1, Min win 25, Win sum 430, Final Vref 26
8446 14:00:17.311026
8447 14:00:17.314071 Final TX Range 0 Vref 26
8448 14:00:17.314153
8449 14:00:17.314220 ==
8450 14:00:17.317782 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 14:00:17.320777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 14:00:17.320853 ==
8453 14:00:17.320918
8454 14:00:17.320978
8455 14:00:17.324371 TX Vref Scan disable
8456 14:00:17.331130 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8457 14:00:17.331208 == TX Byte 0 ==
8458 14:00:17.334634 u2DelayCellOfst[0]=16 cells (5 PI)
8459 14:00:17.337784 u2DelayCellOfst[1]=10 cells (3 PI)
8460 14:00:17.340793 u2DelayCellOfst[2]=0 cells (0 PI)
8461 14:00:17.343849 u2DelayCellOfst[3]=3 cells (1 PI)
8462 14:00:17.347760 u2DelayCellOfst[4]=6 cells (2 PI)
8463 14:00:17.350575 u2DelayCellOfst[5]=16 cells (5 PI)
8464 14:00:17.350654 u2DelayCellOfst[6]=16 cells (5 PI)
8465 14:00:17.353912 u2DelayCellOfst[7]=6 cells (2 PI)
8466 14:00:17.360951 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8467 14:00:17.364524 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8468 14:00:17.364635 == TX Byte 1 ==
8469 14:00:17.367550 u2DelayCellOfst[8]=0 cells (0 PI)
8470 14:00:17.370567 u2DelayCellOfst[9]=3 cells (1 PI)
8471 14:00:17.374218 u2DelayCellOfst[10]=10 cells (3 PI)
8472 14:00:17.377694 u2DelayCellOfst[11]=6 cells (2 PI)
8473 14:00:17.381054 u2DelayCellOfst[12]=16 cells (5 PI)
8474 14:00:17.384384 u2DelayCellOfst[13]=16 cells (5 PI)
8475 14:00:17.387504 u2DelayCellOfst[14]=16 cells (5 PI)
8476 14:00:17.390756 u2DelayCellOfst[15]=16 cells (5 PI)
8477 14:00:17.394202 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8478 14:00:17.397170 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8479 14:00:17.400619 DramC Write-DBI on
8480 14:00:17.400697 ==
8481 14:00:17.403999 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 14:00:17.407550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 14:00:17.407623 ==
8484 14:00:17.407701
8485 14:00:17.407770
8486 14:00:17.410410 TX Vref Scan disable
8487 14:00:17.413816 == TX Byte 0 ==
8488 14:00:17.417258 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8489 14:00:17.420696 == TX Byte 1 ==
8490 14:00:17.423704 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8491 14:00:17.423775 DramC Write-DBI off
8492 14:00:17.423836
8493 14:00:17.427339 [DATLAT]
8494 14:00:17.427410 Freq=1600, CH1 RK0
8495 14:00:17.427470
8496 14:00:17.430678 DATLAT Default: 0xf
8497 14:00:17.430745 0, 0xFFFF, sum = 0
8498 14:00:17.433714 1, 0xFFFF, sum = 0
8499 14:00:17.433782 2, 0xFFFF, sum = 0
8500 14:00:17.437154 3, 0xFFFF, sum = 0
8501 14:00:17.437226 4, 0xFFFF, sum = 0
8502 14:00:17.440616 5, 0xFFFF, sum = 0
8503 14:00:17.440721 6, 0xFFFF, sum = 0
8504 14:00:17.444036 7, 0xFFFF, sum = 0
8505 14:00:17.444111 8, 0xFFFF, sum = 0
8506 14:00:17.447118 9, 0xFFFF, sum = 0
8507 14:00:17.450661 10, 0xFFFF, sum = 0
8508 14:00:17.450775 11, 0xFFFF, sum = 0
8509 14:00:17.453811 12, 0xFFFF, sum = 0
8510 14:00:17.453910 13, 0xFFFF, sum = 0
8511 14:00:17.457305 14, 0x0, sum = 1
8512 14:00:17.457406 15, 0x0, sum = 2
8513 14:00:17.460551 16, 0x0, sum = 3
8514 14:00:17.460625 17, 0x0, sum = 4
8515 14:00:17.460687 best_step = 15
8516 14:00:17.460762
8517 14:00:17.463791 ==
8518 14:00:17.467206 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 14:00:17.470635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 14:00:17.470717 ==
8521 14:00:17.470791 RX Vref Scan: 1
8522 14:00:17.470853
8523 14:00:17.474022 Set Vref Range= 24 -> 127
8524 14:00:17.474098
8525 14:00:17.476891 RX Vref 24 -> 127, step: 1
8526 14:00:17.476978
8527 14:00:17.480492 RX Delay 27 -> 252, step: 4
8528 14:00:17.480566
8529 14:00:17.483865 Set Vref, RX VrefLevel [Byte0]: 24
8530 14:00:17.487427 [Byte1]: 24
8531 14:00:17.487529
8532 14:00:17.490321 Set Vref, RX VrefLevel [Byte0]: 25
8533 14:00:17.493961 [Byte1]: 25
8534 14:00:17.494037
8535 14:00:17.496905 Set Vref, RX VrefLevel [Byte0]: 26
8536 14:00:17.500443 [Byte1]: 26
8537 14:00:17.500522
8538 14:00:17.504031 Set Vref, RX VrefLevel [Byte0]: 27
8539 14:00:17.507171 [Byte1]: 27
8540 14:00:17.511055
8541 14:00:17.511168 Set Vref, RX VrefLevel [Byte0]: 28
8542 14:00:17.514439 [Byte1]: 28
8543 14:00:17.518897
8544 14:00:17.518973 Set Vref, RX VrefLevel [Byte0]: 29
8545 14:00:17.522003 [Byte1]: 29
8546 14:00:17.526213
8547 14:00:17.526322 Set Vref, RX VrefLevel [Byte0]: 30
8548 14:00:17.529340 [Byte1]: 30
8549 14:00:17.533839
8550 14:00:17.533911 Set Vref, RX VrefLevel [Byte0]: 31
8551 14:00:17.539897 [Byte1]: 31
8552 14:00:17.539971
8553 14:00:17.543497 Set Vref, RX VrefLevel [Byte0]: 32
8554 14:00:17.546573 [Byte1]: 32
8555 14:00:17.546645
8556 14:00:17.550090 Set Vref, RX VrefLevel [Byte0]: 33
8557 14:00:17.553663 [Byte1]: 33
8558 14:00:17.553739
8559 14:00:17.556857 Set Vref, RX VrefLevel [Byte0]: 34
8560 14:00:17.559705 [Byte1]: 34
8561 14:00:17.564008
8562 14:00:17.564109 Set Vref, RX VrefLevel [Byte0]: 35
8563 14:00:17.567305 [Byte1]: 35
8564 14:00:17.571115
8565 14:00:17.571186 Set Vref, RX VrefLevel [Byte0]: 36
8566 14:00:17.574747 [Byte1]: 36
8567 14:00:17.578812
8568 14:00:17.578888 Set Vref, RX VrefLevel [Byte0]: 37
8569 14:00:17.582140 [Byte1]: 37
8570 14:00:17.586569
8571 14:00:17.586662 Set Vref, RX VrefLevel [Byte0]: 38
8572 14:00:17.589549 [Byte1]: 38
8573 14:00:17.594244
8574 14:00:17.594328 Set Vref, RX VrefLevel [Byte0]: 39
8575 14:00:17.597182 [Byte1]: 39
8576 14:00:17.601798
8577 14:00:17.601882 Set Vref, RX VrefLevel [Byte0]: 40
8578 14:00:17.604779 [Byte1]: 40
8579 14:00:17.608869
8580 14:00:17.608950 Set Vref, RX VrefLevel [Byte0]: 41
8581 14:00:17.612579 [Byte1]: 41
8582 14:00:17.616565
8583 14:00:17.616648 Set Vref, RX VrefLevel [Byte0]: 42
8584 14:00:17.620133 [Byte1]: 42
8585 14:00:17.623889
8586 14:00:17.623960 Set Vref, RX VrefLevel [Byte0]: 43
8587 14:00:17.627473 [Byte1]: 43
8588 14:00:17.631437
8589 14:00:17.631514 Set Vref, RX VrefLevel [Byte0]: 44
8590 14:00:17.634925 [Byte1]: 44
8591 14:00:17.639085
8592 14:00:17.639190 Set Vref, RX VrefLevel [Byte0]: 45
8593 14:00:17.642827 [Byte1]: 45
8594 14:00:17.646451
8595 14:00:17.646533 Set Vref, RX VrefLevel [Byte0]: 46
8596 14:00:17.650089 [Byte1]: 46
8597 14:00:17.654047
8598 14:00:17.654123 Set Vref, RX VrefLevel [Byte0]: 47
8599 14:00:17.657738 [Byte1]: 47
8600 14:00:17.661868
8601 14:00:17.661941 Set Vref, RX VrefLevel [Byte0]: 48
8602 14:00:17.665023 [Byte1]: 48
8603 14:00:17.669061
8604 14:00:17.669133 Set Vref, RX VrefLevel [Byte0]: 49
8605 14:00:17.672723 [Byte1]: 49
8606 14:00:17.676698
8607 14:00:17.676771 Set Vref, RX VrefLevel [Byte0]: 50
8608 14:00:17.679911 [Byte1]: 50
8609 14:00:17.684121
8610 14:00:17.684197 Set Vref, RX VrefLevel [Byte0]: 51
8611 14:00:17.687476 [Byte1]: 51
8612 14:00:17.691998
8613 14:00:17.692072 Set Vref, RX VrefLevel [Byte0]: 52
8614 14:00:17.694952 [Byte1]: 52
8615 14:00:17.699439
8616 14:00:17.699540 Set Vref, RX VrefLevel [Byte0]: 53
8617 14:00:17.703215 [Byte1]: 53
8618 14:00:17.707259
8619 14:00:17.707341 Set Vref, RX VrefLevel [Byte0]: 54
8620 14:00:17.709935 [Byte1]: 54
8621 14:00:17.714288
8622 14:00:17.714367 Set Vref, RX VrefLevel [Byte0]: 55
8623 14:00:17.717852 [Byte1]: 55
8624 14:00:17.722161
8625 14:00:17.722241 Set Vref, RX VrefLevel [Byte0]: 56
8626 14:00:17.725727 [Byte1]: 56
8627 14:00:17.729855
8628 14:00:17.729927 Set Vref, RX VrefLevel [Byte0]: 57
8629 14:00:17.732716 [Byte1]: 57
8630 14:00:17.737209
8631 14:00:17.737317 Set Vref, RX VrefLevel [Byte0]: 58
8632 14:00:17.740529 [Byte1]: 58
8633 14:00:17.744938
8634 14:00:17.745011 Set Vref, RX VrefLevel [Byte0]: 59
8635 14:00:17.747785 [Byte1]: 59
8636 14:00:17.751974
8637 14:00:17.752076 Set Vref, RX VrefLevel [Byte0]: 60
8638 14:00:17.755909 [Byte1]: 60
8639 14:00:17.759802
8640 14:00:17.759881 Set Vref, RX VrefLevel [Byte0]: 61
8641 14:00:17.762745 [Byte1]: 61
8642 14:00:17.767224
8643 14:00:17.767300 Set Vref, RX VrefLevel [Byte0]: 62
8644 14:00:17.770503 [Byte1]: 62
8645 14:00:17.774915
8646 14:00:17.774991 Set Vref, RX VrefLevel [Byte0]: 63
8647 14:00:17.778170 [Byte1]: 63
8648 14:00:17.782200
8649 14:00:17.782282 Set Vref, RX VrefLevel [Byte0]: 64
8650 14:00:17.785642 [Byte1]: 64
8651 14:00:17.790079
8652 14:00:17.790158 Set Vref, RX VrefLevel [Byte0]: 65
8653 14:00:17.793023 [Byte1]: 65
8654 14:00:17.797529
8655 14:00:17.797613 Set Vref, RX VrefLevel [Byte0]: 66
8656 14:00:17.800514 [Byte1]: 66
8657 14:00:17.804692
8658 14:00:17.804769 Set Vref, RX VrefLevel [Byte0]: 67
8659 14:00:17.808155 [Byte1]: 67
8660 14:00:17.812077
8661 14:00:17.812169 Set Vref, RX VrefLevel [Byte0]: 68
8662 14:00:17.815391 [Byte1]: 68
8663 14:00:17.819980
8664 14:00:17.820074 Set Vref, RX VrefLevel [Byte0]: 69
8665 14:00:17.822961 [Byte1]: 69
8666 14:00:17.827209
8667 14:00:17.827303 Set Vref, RX VrefLevel [Byte0]: 70
8668 14:00:17.830868 [Byte1]: 70
8669 14:00:17.835063
8670 14:00:17.835150 Set Vref, RX VrefLevel [Byte0]: 71
8671 14:00:17.838402 [Byte1]: 71
8672 14:00:17.842676
8673 14:00:17.842770 Set Vref, RX VrefLevel [Byte0]: 72
8674 14:00:17.845925 [Byte1]: 72
8675 14:00:17.850035
8676 14:00:17.850118 Set Vref, RX VrefLevel [Byte0]: 73
8677 14:00:17.853645 [Byte1]: 73
8678 14:00:17.857934
8679 14:00:17.858017 Set Vref, RX VrefLevel [Byte0]: 74
8680 14:00:17.860638 [Byte1]: 74
8681 14:00:17.865242
8682 14:00:17.865357 Set Vref, RX VrefLevel [Byte0]: 75
8683 14:00:17.868358 [Byte1]: 75
8684 14:00:17.872560
8685 14:00:17.872643 Set Vref, RX VrefLevel [Byte0]: 76
8686 14:00:17.876278 [Byte1]: 76
8687 14:00:17.880367
8688 14:00:17.880449 Set Vref, RX VrefLevel [Byte0]: 77
8689 14:00:17.883785 [Byte1]: 77
8690 14:00:17.888249
8691 14:00:17.888333 Final RX Vref Byte 0 = 57 to rank0
8692 14:00:17.890954 Final RX Vref Byte 1 = 57 to rank0
8693 14:00:17.894461 Final RX Vref Byte 0 = 57 to rank1
8694 14:00:17.897823 Final RX Vref Byte 1 = 57 to rank1==
8695 14:00:17.900971 Dram Type= 6, Freq= 0, CH_1, rank 0
8696 14:00:17.907813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8697 14:00:17.907902 ==
8698 14:00:17.907969 DQS Delay:
8699 14:00:17.908031 DQS0 = 0, DQS1 = 0
8700 14:00:17.911332 DQM Delay:
8701 14:00:17.911415 DQM0 = 134, DQM1 = 131
8702 14:00:17.914157 DQ Delay:
8703 14:00:17.917657 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8704 14:00:17.921024 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8705 14:00:17.924613 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =124
8706 14:00:17.927693 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8707 14:00:17.927777
8708 14:00:17.927843
8709 14:00:17.927904
8710 14:00:17.931271 [DramC_TX_OE_Calibration] TA2
8711 14:00:17.934518 Original DQ_B0 (3 6) =30, OEN = 27
8712 14:00:17.937915 Original DQ_B1 (3 6) =30, OEN = 27
8713 14:00:17.940895 24, 0x0, End_B0=24 End_B1=24
8714 14:00:17.940979 25, 0x0, End_B0=25 End_B1=25
8715 14:00:17.944293 26, 0x0, End_B0=26 End_B1=26
8716 14:00:17.947889 27, 0x0, End_B0=27 End_B1=27
8717 14:00:17.950655 28, 0x0, End_B0=28 End_B1=28
8718 14:00:17.950740 29, 0x0, End_B0=29 End_B1=29
8719 14:00:17.954321 30, 0x0, End_B0=30 End_B1=30
8720 14:00:17.957471 31, 0x4141, End_B0=30 End_B1=30
8721 14:00:17.961047 Byte0 end_step=30 best_step=27
8722 14:00:17.963979 Byte1 end_step=30 best_step=27
8723 14:00:17.967526 Byte0 TX OE(2T, 0.5T) = (3, 3)
8724 14:00:17.967609 Byte1 TX OE(2T, 0.5T) = (3, 3)
8725 14:00:17.970763
8726 14:00:17.970845
8727 14:00:17.977582 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8728 14:00:17.980710 CH1 RK0: MR19=303, MR18=1623
8729 14:00:17.987527 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8730 14:00:17.987611
8731 14:00:17.990604 ----->DramcWriteLeveling(PI) begin...
8732 14:00:17.990689 ==
8733 14:00:17.994277 Dram Type= 6, Freq= 0, CH_1, rank 1
8734 14:00:17.997282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8735 14:00:17.997367 ==
8736 14:00:18.000933 Write leveling (Byte 0): 26 => 26
8737 14:00:18.003962 Write leveling (Byte 1): 27 => 27
8738 14:00:18.007359 DramcWriteLeveling(PI) end<-----
8739 14:00:18.007442
8740 14:00:18.007508 ==
8741 14:00:18.010572 Dram Type= 6, Freq= 0, CH_1, rank 1
8742 14:00:18.014020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 14:00:18.014139 ==
8744 14:00:18.017219 [Gating] SW mode calibration
8745 14:00:18.024246 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8746 14:00:18.030561 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8747 14:00:18.034589 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 14:00:18.037464 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 14:00:18.043970 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8750 14:00:18.047444 1 4 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8751 14:00:18.050824 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 14:00:18.057577 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 14:00:18.060571 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 14:00:18.063990 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 14:00:18.070836 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 14:00:18.074173 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8757 14:00:18.077142 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8758 14:00:18.084289 1 5 12 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (1 0)
8759 14:00:18.087434 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 14:00:18.090652 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 14:00:18.096893 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 14:00:18.100215 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 14:00:18.103874 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 14:00:18.110785 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 14:00:18.113690 1 6 8 | B1->B0 | 3434 2323 | 1 0 | (0 0) (0 0)
8766 14:00:18.116933 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 14:00:18.123540 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 14:00:18.127170 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 14:00:18.130233 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 14:00:18.133841 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 14:00:18.140170 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 14:00:18.143988 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8773 14:00:18.147186 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8774 14:00:18.153570 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8775 14:00:18.156902 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8776 14:00:18.160179 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 14:00:18.167158 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 14:00:18.170144 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 14:00:18.173925 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 14:00:18.180345 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 14:00:18.183855 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 14:00:18.186817 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 14:00:18.193224 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 14:00:18.197117 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 14:00:18.200449 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 14:00:18.206894 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 14:00:18.210091 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 14:00:18.213241 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8789 14:00:18.219739 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8790 14:00:18.223527 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8791 14:00:18.226387 Total UI for P1: 0, mck2ui 16
8792 14:00:18.229785 best dqsien dly found for B1: ( 1, 9, 6)
8793 14:00:18.233066 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 14:00:18.236686 Total UI for P1: 0, mck2ui 16
8795 14:00:18.240229 best dqsien dly found for B0: ( 1, 9, 12)
8796 14:00:18.243310 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8797 14:00:18.247077 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8798 14:00:18.247162
8799 14:00:18.250203 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8800 14:00:18.256603 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8801 14:00:18.256690 [Gating] SW calibration Done
8802 14:00:18.256781 ==
8803 14:00:18.260003 Dram Type= 6, Freq= 0, CH_1, rank 1
8804 14:00:18.266907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8805 14:00:18.266992 ==
8806 14:00:18.267059 RX Vref Scan: 0
8807 14:00:18.267129
8808 14:00:18.269917 RX Vref 0 -> 0, step: 1
8809 14:00:18.270057
8810 14:00:18.273643 RX Delay 0 -> 252, step: 8
8811 14:00:18.277016 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8812 14:00:18.280233 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8813 14:00:18.283158 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8814 14:00:18.286845 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8815 14:00:18.293402 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8816 14:00:18.296713 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8817 14:00:18.299712 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8818 14:00:18.303396 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8819 14:00:18.306539 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8820 14:00:18.313229 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8821 14:00:18.316947 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8822 14:00:18.319766 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8823 14:00:18.323585 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8824 14:00:18.329553 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8825 14:00:18.333266 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8826 14:00:18.336278 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8827 14:00:18.336404 ==
8828 14:00:18.339885 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 14:00:18.343112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 14:00:18.343241 ==
8831 14:00:18.346322 DQS Delay:
8832 14:00:18.346452 DQS0 = 0, DQS1 = 0
8833 14:00:18.349809 DQM Delay:
8834 14:00:18.349939 DQM0 = 136, DQM1 = 133
8835 14:00:18.350057 DQ Delay:
8836 14:00:18.353120 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8837 14:00:18.359512 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8838 14:00:18.362745 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8839 14:00:18.366562 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8840 14:00:18.366693
8841 14:00:18.366816
8842 14:00:18.366928 ==
8843 14:00:18.369363 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 14:00:18.372974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 14:00:18.373107 ==
8846 14:00:18.373220
8847 14:00:18.373342
8848 14:00:18.376088 TX Vref Scan disable
8849 14:00:18.379840 == TX Byte 0 ==
8850 14:00:18.383127 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8851 14:00:18.386172 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8852 14:00:18.389792 == TX Byte 1 ==
8853 14:00:18.392833 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8854 14:00:18.396663 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8855 14:00:18.396769 ==
8856 14:00:18.399455 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 14:00:18.402863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 14:00:18.402965 ==
8859 14:00:18.418007
8860 14:00:18.421592 TX Vref early break, caculate TX vref
8861 14:00:18.424602 TX Vref=16, minBit 2, minWin=23, winSum=387
8862 14:00:18.427908 TX Vref=18, minBit 2, minWin=23, winSum=396
8863 14:00:18.431438 TX Vref=20, minBit 1, minWin=23, winSum=407
8864 14:00:18.434801 TX Vref=22, minBit 0, minWin=25, winSum=414
8865 14:00:18.438078 TX Vref=24, minBit 0, minWin=25, winSum=420
8866 14:00:18.444780 TX Vref=26, minBit 0, minWin=25, winSum=424
8867 14:00:18.447826 TX Vref=28, minBit 0, minWin=25, winSum=426
8868 14:00:18.451193 TX Vref=30, minBit 0, minWin=25, winSum=421
8869 14:00:18.454566 TX Vref=32, minBit 0, minWin=25, winSum=416
8870 14:00:18.458185 TX Vref=34, minBit 0, minWin=24, winSum=406
8871 14:00:18.461043 TX Vref=36, minBit 1, minWin=23, winSum=399
8872 14:00:18.467807 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8873 14:00:18.467889
8874 14:00:18.471283 Final TX Range 0 Vref 28
8875 14:00:18.471383
8876 14:00:18.471485 ==
8877 14:00:18.474748 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 14:00:18.477835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 14:00:18.477936 ==
8880 14:00:18.478040
8881 14:00:18.478133
8882 14:00:18.481244 TX Vref Scan disable
8883 14:00:18.488082 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8884 14:00:18.488163 == TX Byte 0 ==
8885 14:00:18.491100 u2DelayCellOfst[0]=20 cells (6 PI)
8886 14:00:18.494871 u2DelayCellOfst[1]=10 cells (3 PI)
8887 14:00:18.498338 u2DelayCellOfst[2]=0 cells (0 PI)
8888 14:00:18.501219 u2DelayCellOfst[3]=6 cells (2 PI)
8889 14:00:18.504819 u2DelayCellOfst[4]=10 cells (3 PI)
8890 14:00:18.507825 u2DelayCellOfst[5]=16 cells (5 PI)
8891 14:00:18.511474 u2DelayCellOfst[6]=16 cells (5 PI)
8892 14:00:18.514293 u2DelayCellOfst[7]=6 cells (2 PI)
8893 14:00:18.517935 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8894 14:00:18.521281 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8895 14:00:18.524629 == TX Byte 1 ==
8896 14:00:18.524744 u2DelayCellOfst[8]=0 cells (0 PI)
8897 14:00:18.528007 u2DelayCellOfst[9]=0 cells (0 PI)
8898 14:00:18.530886 u2DelayCellOfst[10]=10 cells (3 PI)
8899 14:00:18.534173 u2DelayCellOfst[11]=3 cells (1 PI)
8900 14:00:18.537665 u2DelayCellOfst[12]=13 cells (4 PI)
8901 14:00:18.541191 u2DelayCellOfst[13]=16 cells (5 PI)
8902 14:00:18.544377 u2DelayCellOfst[14]=16 cells (5 PI)
8903 14:00:18.547737 u2DelayCellOfst[15]=16 cells (5 PI)
8904 14:00:18.551134 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8905 14:00:18.557717 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8906 14:00:18.557799 DramC Write-DBI on
8907 14:00:18.557865 ==
8908 14:00:18.561478 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 14:00:18.564388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 14:00:18.567752 ==
8911 14:00:18.567865
8912 14:00:18.567930
8913 14:00:18.567990 TX Vref Scan disable
8914 14:00:18.571481 == TX Byte 0 ==
8915 14:00:18.574611 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8916 14:00:18.577859 == TX Byte 1 ==
8917 14:00:18.581114 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8918 14:00:18.584531 DramC Write-DBI off
8919 14:00:18.584627
8920 14:00:18.584691 [DATLAT]
8921 14:00:18.584780 Freq=1600, CH1 RK1
8922 14:00:18.584838
8923 14:00:18.587553 DATLAT Default: 0xf
8924 14:00:18.587682 0, 0xFFFF, sum = 0
8925 14:00:18.591411 1, 0xFFFF, sum = 0
8926 14:00:18.591547 2, 0xFFFF, sum = 0
8927 14:00:18.594588 3, 0xFFFF, sum = 0
8928 14:00:18.597666 4, 0xFFFF, sum = 0
8929 14:00:18.597748 5, 0xFFFF, sum = 0
8930 14:00:18.601360 6, 0xFFFF, sum = 0
8931 14:00:18.601442 7, 0xFFFF, sum = 0
8932 14:00:18.604627 8, 0xFFFF, sum = 0
8933 14:00:18.604709 9, 0xFFFF, sum = 0
8934 14:00:18.607706 10, 0xFFFF, sum = 0
8935 14:00:18.607816 11, 0xFFFF, sum = 0
8936 14:00:18.611245 12, 0xFFFF, sum = 0
8937 14:00:18.611349 13, 0xFFFF, sum = 0
8938 14:00:18.614324 14, 0x0, sum = 1
8939 14:00:18.614407 15, 0x0, sum = 2
8940 14:00:18.618088 16, 0x0, sum = 3
8941 14:00:18.618173 17, 0x0, sum = 4
8942 14:00:18.621099 best_step = 15
8943 14:00:18.621182
8944 14:00:18.621247 ==
8945 14:00:18.624435 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 14:00:18.627494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 14:00:18.627581 ==
8948 14:00:18.627657 RX Vref Scan: 0
8949 14:00:18.631011
8950 14:00:18.631093 RX Vref 0 -> 0, step: 1
8951 14:00:18.631158
8952 14:00:18.634472 RX Delay 19 -> 252, step: 4
8953 14:00:18.638063 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8954 14:00:18.641685 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8955 14:00:18.647887 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8956 14:00:18.651163 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8957 14:00:18.654235 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8958 14:00:18.657706 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8959 14:00:18.661494 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8960 14:00:18.667955 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8961 14:00:18.670902 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8962 14:00:18.674461 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8963 14:00:18.677773 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8964 14:00:18.681198 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8965 14:00:18.688496 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8966 14:00:18.691183 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8967 14:00:18.694339 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8968 14:00:18.698046 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8969 14:00:18.698129 ==
8970 14:00:18.701302 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 14:00:18.707495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 14:00:18.707606 ==
8973 14:00:18.707695 DQS Delay:
8974 14:00:18.707758 DQS0 = 0, DQS1 = 0
8975 14:00:18.711231 DQM Delay:
8976 14:00:18.711314 DQM0 = 134, DQM1 = 130
8977 14:00:18.714576 DQ Delay:
8978 14:00:18.717618 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8979 14:00:18.721155 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8980 14:00:18.724059 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8981 14:00:18.727758 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8982 14:00:18.727835
8983 14:00:18.727922
8984 14:00:18.728005
8985 14:00:18.730701 [DramC_TX_OE_Calibration] TA2
8986 14:00:18.734346 Original DQ_B0 (3 6) =30, OEN = 27
8987 14:00:18.737324 Original DQ_B1 (3 6) =30, OEN = 27
8988 14:00:18.740823 24, 0x0, End_B0=24 End_B1=24
8989 14:00:18.740905 25, 0x0, End_B0=25 End_B1=25
8990 14:00:18.743879 26, 0x0, End_B0=26 End_B1=26
8991 14:00:18.747698 27, 0x0, End_B0=27 End_B1=27
8992 14:00:18.750631 28, 0x0, End_B0=28 End_B1=28
8993 14:00:18.754085 29, 0x0, End_B0=29 End_B1=29
8994 14:00:18.754171 30, 0x0, End_B0=30 End_B1=30
8995 14:00:18.757887 31, 0x4545, End_B0=30 End_B1=30
8996 14:00:18.760877 Byte0 end_step=30 best_step=27
8997 14:00:18.764115 Byte1 end_step=30 best_step=27
8998 14:00:18.767645 Byte0 TX OE(2T, 0.5T) = (3, 3)
8999 14:00:18.770469 Byte1 TX OE(2T, 0.5T) = (3, 3)
9000 14:00:18.770552
9001 14:00:18.770618
9002 14:00:18.777258 [DQSOSCAuto] RK1, (LSB)MR18= 0x250a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
9003 14:00:18.780798 CH1 RK1: MR19=303, MR18=250A
9004 14:00:18.787429 CH1_RK1: MR19=0x303, MR18=0x250A, DQSOSC=391, MR23=63, INC=24, DEC=16
9005 14:00:18.790605 [RxdqsGatingPostProcess] freq 1600
9006 14:00:18.793641 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9007 14:00:18.797148 best DQS0 dly(2T, 0.5T) = (1, 1)
9008 14:00:18.800665 best DQS1 dly(2T, 0.5T) = (1, 1)
9009 14:00:18.803729 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9010 14:00:18.806952 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9011 14:00:18.810308 best DQS0 dly(2T, 0.5T) = (1, 1)
9012 14:00:18.814058 best DQS1 dly(2T, 0.5T) = (1, 1)
9013 14:00:18.816793 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9014 14:00:18.820562 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9015 14:00:18.824174 Pre-setting of DQS Precalculation
9016 14:00:18.827473 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9017 14:00:18.833880 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9018 14:00:18.843600 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9019 14:00:18.843703
9020 14:00:18.843771
9021 14:00:18.843833 [Calibration Summary] 3200 Mbps
9022 14:00:18.847033 CH 0, Rank 0
9023 14:00:18.847116 SW Impedance : PASS
9024 14:00:18.850689 DUTY Scan : NO K
9025 14:00:18.853824 ZQ Calibration : PASS
9026 14:00:18.853908 Jitter Meter : NO K
9027 14:00:18.856804 CBT Training : PASS
9028 14:00:18.860431 Write leveling : PASS
9029 14:00:18.860514 RX DQS gating : PASS
9030 14:00:18.863591 RX DQ/DQS(RDDQC) : PASS
9031 14:00:18.867009 TX DQ/DQS : PASS
9032 14:00:18.867092 RX DATLAT : PASS
9033 14:00:18.870319 RX DQ/DQS(Engine): PASS
9034 14:00:18.873734 TX OE : PASS
9035 14:00:18.873817 All Pass.
9036 14:00:18.873883
9037 14:00:18.873944 CH 0, Rank 1
9038 14:00:18.876672 SW Impedance : PASS
9039 14:00:18.880251 DUTY Scan : NO K
9040 14:00:18.880335 ZQ Calibration : PASS
9041 14:00:18.883317 Jitter Meter : NO K
9042 14:00:18.886817 CBT Training : PASS
9043 14:00:18.886925 Write leveling : PASS
9044 14:00:18.890417 RX DQS gating : PASS
9045 14:00:18.893115 RX DQ/DQS(RDDQC) : PASS
9046 14:00:18.893224 TX DQ/DQS : PASS
9047 14:00:18.896929 RX DATLAT : PASS
9048 14:00:18.897007 RX DQ/DQS(Engine): PASS
9049 14:00:18.899867 TX OE : PASS
9050 14:00:18.899947 All Pass.
9051 14:00:18.900034
9052 14:00:18.903553 CH 1, Rank 0
9053 14:00:18.903670 SW Impedance : PASS
9054 14:00:18.906366 DUTY Scan : NO K
9055 14:00:18.909680 ZQ Calibration : PASS
9056 14:00:18.909757 Jitter Meter : NO K
9057 14:00:18.913045 CBT Training : PASS
9058 14:00:18.916642 Write leveling : PASS
9059 14:00:18.916724 RX DQS gating : PASS
9060 14:00:18.919764 RX DQ/DQS(RDDQC) : PASS
9061 14:00:18.923314 TX DQ/DQS : PASS
9062 14:00:18.923393 RX DATLAT : PASS
9063 14:00:18.926698 RX DQ/DQS(Engine): PASS
9064 14:00:18.929549 TX OE : PASS
9065 14:00:18.929643 All Pass.
9066 14:00:18.929728
9067 14:00:18.929807 CH 1, Rank 1
9068 14:00:18.933495 SW Impedance : PASS
9069 14:00:18.936384 DUTY Scan : NO K
9070 14:00:18.936467 ZQ Calibration : PASS
9071 14:00:18.940086 Jitter Meter : NO K
9072 14:00:18.943163 CBT Training : PASS
9073 14:00:18.943265 Write leveling : PASS
9074 14:00:18.946827 RX DQS gating : PASS
9075 14:00:18.949742 RX DQ/DQS(RDDQC) : PASS
9076 14:00:18.949844 TX DQ/DQS : PASS
9077 14:00:18.953415 RX DATLAT : PASS
9078 14:00:18.953520 RX DQ/DQS(Engine): PASS
9079 14:00:18.956253 TX OE : PASS
9080 14:00:18.956375 All Pass.
9081 14:00:18.956461
9082 14:00:18.959812 DramC Write-DBI on
9083 14:00:18.962854 PER_BANK_REFRESH: Hybrid Mode
9084 14:00:18.962932 TX_TRACKING: ON
9085 14:00:18.973079 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9086 14:00:18.979589 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9087 14:00:18.986921 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9088 14:00:18.993475 [FAST_K] Save calibration result to emmc
9089 14:00:18.993564 sync common calibartion params.
9090 14:00:18.996656 sync cbt_mode0:1, 1:1
9091 14:00:19.000208 dram_init: ddr_geometry: 2
9092 14:00:19.000293 dram_init: ddr_geometry: 2
9093 14:00:19.003027 dram_init: ddr_geometry: 2
9094 14:00:19.006206 0:dram_rank_size:100000000
9095 14:00:19.009662 1:dram_rank_size:100000000
9096 14:00:19.012802 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9097 14:00:19.016105 DFS_SHUFFLE_HW_MODE: ON
9098 14:00:19.019568 dramc_set_vcore_voltage set vcore to 725000
9099 14:00:19.023210 Read voltage for 1600, 0
9100 14:00:19.023296 Vio18 = 0
9101 14:00:19.026350 Vcore = 725000
9102 14:00:19.026430 Vdram = 0
9103 14:00:19.026519 Vddq = 0
9104 14:00:19.026600 Vmddr = 0
9105 14:00:19.029584 switch to 3200 Mbps bootup
9106 14:00:19.033189 [DramcRunTimeConfig]
9107 14:00:19.033272 PHYPLL
9108 14:00:19.033356 DPM_CONTROL_AFTERK: ON
9109 14:00:19.036576 PER_BANK_REFRESH: ON
9110 14:00:19.039867 REFRESH_OVERHEAD_REDUCTION: ON
9111 14:00:19.039947 CMD_PICG_NEW_MODE: OFF
9112 14:00:19.042887 XRTWTW_NEW_MODE: ON
9113 14:00:19.046161 XRTRTR_NEW_MODE: ON
9114 14:00:19.046241 TX_TRACKING: ON
9115 14:00:19.049690 RDSEL_TRACKING: OFF
9116 14:00:19.049769 DQS Precalculation for DVFS: ON
9117 14:00:19.052737 RX_TRACKING: OFF
9118 14:00:19.052819 HW_GATING DBG: ON
9119 14:00:19.056279 ZQCS_ENABLE_LP4: ON
9120 14:00:19.059242 RX_PICG_NEW_MODE: ON
9121 14:00:19.059363 TX_PICG_NEW_MODE: ON
9122 14:00:19.062781 ENABLE_RX_DCM_DPHY: ON
9123 14:00:19.066247 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9124 14:00:19.066373 DUMMY_READ_FOR_TRACKING: OFF
9125 14:00:19.069265 !!! SPM_CONTROL_AFTERK: OFF
9126 14:00:19.072869 !!! SPM could not control APHY
9127 14:00:19.076542 IMPEDANCE_TRACKING: ON
9128 14:00:19.076624 TEMP_SENSOR: ON
9129 14:00:19.079599 HW_SAVE_FOR_SR: OFF
9130 14:00:19.079734 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9131 14:00:19.086030 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9132 14:00:19.086158 Read ODT Tracking: ON
9133 14:00:19.089047 Refresh Rate DeBounce: ON
9134 14:00:19.092657 DFS_NO_QUEUE_FLUSH: ON
9135 14:00:19.095761 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9136 14:00:19.095884 ENABLE_DFS_RUNTIME_MRW: OFF
9137 14:00:19.099226 DDR_RESERVE_NEW_MODE: ON
9138 14:00:19.102401 MR_CBT_SWITCH_FREQ: ON
9139 14:00:19.102526 =========================
9140 14:00:19.122327 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9141 14:00:19.125542 dram_init: ddr_geometry: 2
9142 14:00:19.143732 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9143 14:00:19.147173 dram_init: dram init end (result: 0)
9144 14:00:19.153679 DRAM-K: Full calibration passed in 24455 msecs
9145 14:00:19.157274 MRC: failed to locate region type 0.
9146 14:00:19.157362 DRAM rank0 size:0x100000000,
9147 14:00:19.160874 DRAM rank1 size=0x100000000
9148 14:00:19.170886 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9149 14:00:19.176973 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9150 14:00:19.184254 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9151 14:00:19.190490 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9152 14:00:19.194021 DRAM rank0 size:0x100000000,
9153 14:00:19.197180 DRAM rank1 size=0x100000000
9154 14:00:19.197263 CBMEM:
9155 14:00:19.200666 IMD: root @ 0xfffff000 254 entries.
9156 14:00:19.203811 IMD: root @ 0xffffec00 62 entries.
9157 14:00:19.206942 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9158 14:00:19.210402 WARNING: RO_VPD is uninitialized or empty.
9159 14:00:19.217031 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9160 14:00:19.224165 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9161 14:00:19.236707 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9162 14:00:19.247973 BS: romstage times (exec / console): total (unknown) / 23985 ms
9163 14:00:19.248057
9164 14:00:19.248130
9165 14:00:19.257837 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9166 14:00:19.261386 ARM64: Exception handlers installed.
9167 14:00:19.264543 ARM64: Testing exception
9168 14:00:19.268205 ARM64: Done test exception
9169 14:00:19.268286 Enumerating buses...
9170 14:00:19.270934 Show all devs... Before device enumeration.
9171 14:00:19.274522 Root Device: enabled 1
9172 14:00:19.278034 CPU_CLUSTER: 0: enabled 1
9173 14:00:19.278162 CPU: 00: enabled 1
9174 14:00:19.280937 Compare with tree...
9175 14:00:19.281060 Root Device: enabled 1
9176 14:00:19.284407 CPU_CLUSTER: 0: enabled 1
9177 14:00:19.288029 CPU: 00: enabled 1
9178 14:00:19.288130 Root Device scanning...
9179 14:00:19.291527 scan_static_bus for Root Device
9180 14:00:19.294619 CPU_CLUSTER: 0 enabled
9181 14:00:19.297550 scan_static_bus for Root Device done
9182 14:00:19.300887 scan_bus: bus Root Device finished in 8 msecs
9183 14:00:19.300972 done
9184 14:00:19.307620 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9185 14:00:19.311252 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9186 14:00:19.317881 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9187 14:00:19.320932 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9188 14:00:19.324297 Allocating resources...
9189 14:00:19.328050 Reading resources...
9190 14:00:19.331125 Root Device read_resources bus 0 link: 0
9191 14:00:19.331210 DRAM rank0 size:0x100000000,
9192 14:00:19.334645 DRAM rank1 size=0x100000000
9193 14:00:19.337578 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9194 14:00:19.341284 CPU: 00 missing read_resources
9195 14:00:19.344376 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9196 14:00:19.351025 Root Device read_resources bus 0 link: 0 done
9197 14:00:19.351137 Done reading resources.
9198 14:00:19.357641 Show resources in subtree (Root Device)...After reading.
9199 14:00:19.360845 Root Device child on link 0 CPU_CLUSTER: 0
9200 14:00:19.364404 CPU_CLUSTER: 0 child on link 0 CPU: 00
9201 14:00:19.374311 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9202 14:00:19.374408 CPU: 00
9203 14:00:19.377469 Root Device assign_resources, bus 0 link: 0
9204 14:00:19.380750 CPU_CLUSTER: 0 missing set_resources
9205 14:00:19.384222 Root Device assign_resources, bus 0 link: 0 done
9206 14:00:19.387680 Done setting resources.
9207 14:00:19.394252 Show resources in subtree (Root Device)...After assigning values.
9208 14:00:19.397557 Root Device child on link 0 CPU_CLUSTER: 0
9209 14:00:19.401125 CPU_CLUSTER: 0 child on link 0 CPU: 00
9210 14:00:19.410439 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9211 14:00:19.410554 CPU: 00
9212 14:00:19.414001 Done allocating resources.
9213 14:00:19.417439 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9214 14:00:19.420629 Enabling resources...
9215 14:00:19.420704 done.
9216 14:00:19.427009 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9217 14:00:19.427087 Initializing devices...
9218 14:00:19.430884 Root Device init
9219 14:00:19.430958 init hardware done!
9220 14:00:19.433742 0x00000018: ctrlr->caps
9221 14:00:19.437272 52.000 MHz: ctrlr->f_max
9222 14:00:19.437348 0.400 MHz: ctrlr->f_min
9223 14:00:19.440261 0x40ff8080: ctrlr->voltages
9224 14:00:19.440368 sclk: 390625
9225 14:00:19.443938 Bus Width = 1
9226 14:00:19.444052 sclk: 390625
9227 14:00:19.446899 Bus Width = 1
9228 14:00:19.447023 Early init status = 3
9229 14:00:19.453700 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9230 14:00:19.457106 in-header: 03 fc 00 00 01 00 00 00
9231 14:00:19.457188 in-data: 00
9232 14:00:19.463460 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9233 14:00:19.466673 in-header: 03 fd 00 00 00 00 00 00
9234 14:00:19.470241 in-data:
9235 14:00:19.473538 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9236 14:00:19.477415 in-header: 03 fc 00 00 01 00 00 00
9237 14:00:19.480970 in-data: 00
9238 14:00:19.484019 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9239 14:00:19.490060 in-header: 03 fd 00 00 00 00 00 00
9240 14:00:19.492706 in-data:
9241 14:00:19.496367 [SSUSB] Setting up USB HOST controller...
9242 14:00:19.499650 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9243 14:00:19.502925 [SSUSB] phy power-on done.
9244 14:00:19.506792 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9245 14:00:19.513293 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9246 14:00:19.515998 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9247 14:00:19.523245 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9248 14:00:19.529389 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9249 14:00:19.536054 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9250 14:00:19.542654 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9251 14:00:19.549425 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9252 14:00:19.552510 SPM: binary array size = 0x9dc
9253 14:00:19.556104 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9254 14:00:19.562727 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9255 14:00:19.569480 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9256 14:00:19.572859 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9257 14:00:19.579439 configure_display: Starting display init
9258 14:00:19.612776 anx7625_power_on_init: Init interface.
9259 14:00:19.616245 anx7625_disable_pd_protocol: Disabled PD feature.
9260 14:00:19.619819 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9261 14:00:19.647392 anx7625_start_dp_work: Secure OCM version=00
9262 14:00:19.650882 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9263 14:00:19.665733 sp_tx_get_edid_block: EDID Block = 1
9264 14:00:19.768199 Extracted contents:
9265 14:00:19.771467 header: 00 ff ff ff ff ff ff 00
9266 14:00:19.774720 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9267 14:00:19.778021 version: 01 04
9268 14:00:19.781256 basic params: 95 1f 11 78 0a
9269 14:00:19.784905 chroma info: 76 90 94 55 54 90 27 21 50 54
9270 14:00:19.787807 established: 00 00 00
9271 14:00:19.794367 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9272 14:00:19.797766 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9273 14:00:19.804560 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9274 14:00:19.811400 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9275 14:00:19.818058 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9276 14:00:19.821387 extensions: 00
9277 14:00:19.821467 checksum: fb
9278 14:00:19.821533
9279 14:00:19.824863 Manufacturer: IVO Model 57d Serial Number 0
9280 14:00:19.828230 Made week 0 of 2020
9281 14:00:19.828306 EDID version: 1.4
9282 14:00:19.831324 Digital display
9283 14:00:19.834563 6 bits per primary color channel
9284 14:00:19.834645 DisplayPort interface
9285 14:00:19.837695 Maximum image size: 31 cm x 17 cm
9286 14:00:19.841158 Gamma: 220%
9287 14:00:19.841241 Check DPMS levels
9288 14:00:19.844814 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9289 14:00:19.848505 First detailed timing is preferred timing
9290 14:00:19.851248 Established timings supported:
9291 14:00:19.854956 Standard timings supported:
9292 14:00:19.855032 Detailed timings
9293 14:00:19.861380 Hex of detail: 383680a07038204018303c0035ae10000019
9294 14:00:19.864145 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9295 14:00:19.871413 0780 0798 07c8 0820 hborder 0
9296 14:00:19.874282 0438 043b 0447 0458 vborder 0
9297 14:00:19.877748 -hsync -vsync
9298 14:00:19.877823 Did detailed timing
9299 14:00:19.880786 Hex of detail: 000000000000000000000000000000000000
9300 14:00:19.884117 Manufacturer-specified data, tag 0
9301 14:00:19.890860 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9302 14:00:19.894231 ASCII string: InfoVision
9303 14:00:19.897099 Hex of detail: 000000fe00523134304e574635205248200a
9304 14:00:19.900812 ASCII string: R140NWF5 RH
9305 14:00:19.900895 Checksum
9306 14:00:19.903881 Checksum: 0xfb (valid)
9307 14:00:19.907668 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9308 14:00:19.910871 DSI data_rate: 832800000 bps
9309 14:00:19.917038 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9310 14:00:19.920622 anx7625_parse_edid: pixelclock(138800).
9311 14:00:19.924173 hactive(1920), hsync(48), hfp(24), hbp(88)
9312 14:00:19.927588 vactive(1080), vsync(12), vfp(3), vbp(17)
9313 14:00:19.930811 anx7625_dsi_config: config dsi.
9314 14:00:19.937246 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9315 14:00:19.950347 anx7625_dsi_config: success to config DSI
9316 14:00:19.953222 anx7625_dp_start: MIPI phy setup OK.
9317 14:00:19.956574 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9318 14:00:19.959994 mtk_ddp_mode_set invalid vrefresh 60
9319 14:00:19.963076 main_disp_path_setup
9320 14:00:19.963153 ovl_layer_smi_id_en
9321 14:00:19.966708 ovl_layer_smi_id_en
9322 14:00:19.966786 ccorr_config
9323 14:00:19.966857 aal_config
9324 14:00:19.970139 gamma_config
9325 14:00:19.970247 postmask_config
9326 14:00:19.973498 dither_config
9327 14:00:19.976793 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9328 14:00:19.983443 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9329 14:00:19.986390 Root Device init finished in 553 msecs
9330 14:00:19.990232 CPU_CLUSTER: 0 init
9331 14:00:19.996621 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9332 14:00:19.999995 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9333 14:00:20.003124 APU_MBOX 0x190000b0 = 0x10001
9334 14:00:20.006487 APU_MBOX 0x190001b0 = 0x10001
9335 14:00:20.009784 APU_MBOX 0x190005b0 = 0x10001
9336 14:00:20.012781 APU_MBOX 0x190006b0 = 0x10001
9337 14:00:20.016540 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9338 14:00:20.028939 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9339 14:00:20.041668 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9340 14:00:20.047726 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9341 14:00:20.059631 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9342 14:00:20.069202 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9343 14:00:20.071982 CPU_CLUSTER: 0 init finished in 81 msecs
9344 14:00:20.075219 Devices initialized
9345 14:00:20.078898 Show all devs... After init.
9346 14:00:20.078976 Root Device: enabled 1
9347 14:00:20.082127 CPU_CLUSTER: 0: enabled 1
9348 14:00:20.085748 CPU: 00: enabled 1
9349 14:00:20.088531 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9350 14:00:20.092196 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9351 14:00:20.095144 ELOG: NV offset 0x57f000 size 0x1000
9352 14:00:20.102122 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9353 14:00:20.108922 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9354 14:00:20.111941 ELOG: Event(17) added with size 13 at 2023-09-21 13:58:53 UTC
9355 14:00:20.115033 out: cmd=0x121: 03 db 21 01 00 00 00 00
9356 14:00:20.119264 in-header: 03 e0 00 00 2c 00 00 00
9357 14:00:20.132587 in-data: 7f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9358 14:00:20.139585 ELOG: Event(A1) added with size 10 at 2023-09-21 13:58:53 UTC
9359 14:00:20.145826 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9360 14:00:20.149284 ELOG: Event(A0) added with size 9 at 2023-09-21 13:58:53 UTC
9361 14:00:20.155684 elog_add_boot_reason: Logged dev mode boot
9362 14:00:20.159157 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9363 14:00:20.162739 Finalize devices...
9364 14:00:20.162821 Devices finalized
9365 14:00:20.169152 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9366 14:00:20.172881 Writing coreboot table at 0xffe64000
9367 14:00:20.175958 0. 000000000010a000-0000000000113fff: RAMSTAGE
9368 14:00:20.179285 1. 0000000040000000-00000000400fffff: RAM
9369 14:00:20.182783 2. 0000000040100000-000000004032afff: RAMSTAGE
9370 14:00:20.185984 3. 000000004032b000-00000000545fffff: RAM
9371 14:00:20.192709 4. 0000000054600000-000000005465ffff: BL31
9372 14:00:20.196126 5. 0000000054660000-00000000ffe63fff: RAM
9373 14:00:20.199110 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9374 14:00:20.205623 7. 0000000100000000-000000023fffffff: RAM
9375 14:00:20.205728 Passing 5 GPIOs to payload:
9376 14:00:20.212284 NAME | PORT | POLARITY | VALUE
9377 14:00:20.215752 EC in RW | 0x000000aa | low | undefined
9378 14:00:20.222138 EC interrupt | 0x00000005 | low | undefined
9379 14:00:20.225708 TPM interrupt | 0x000000ab | high | undefined
9380 14:00:20.229322 SD card detect | 0x00000011 | high | undefined
9381 14:00:20.235576 speaker enable | 0x00000093 | high | undefined
9382 14:00:20.238912 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9383 14:00:20.241878 in-header: 03 f9 00 00 02 00 00 00
9384 14:00:20.241951 in-data: 02 00
9385 14:00:20.245482 ADC[4]: Raw value=905096 ID=7
9386 14:00:20.248688 ADC[3]: Raw value=213441 ID=1
9387 14:00:20.248760 RAM Code: 0x71
9388 14:00:20.252098 ADC[6]: Raw value=75332 ID=0
9389 14:00:20.255110 ADC[5]: Raw value=213072 ID=1
9390 14:00:20.255186 SKU Code: 0x1
9391 14:00:20.262269 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b7d7
9392 14:00:20.265295 coreboot table: 964 bytes.
9393 14:00:20.268490 IMD ROOT 0. 0xfffff000 0x00001000
9394 14:00:20.272141 IMD SMALL 1. 0xffffe000 0x00001000
9395 14:00:20.275085 RO MCACHE 2. 0xffffc000 0x00001104
9396 14:00:20.278846 CONSOLE 3. 0xfff7c000 0x00080000
9397 14:00:20.281680 FMAP 4. 0xfff7b000 0x00000452
9398 14:00:20.285522 TIME STAMP 5. 0xfff7a000 0x00000910
9399 14:00:20.288662 VBOOT WORK 6. 0xfff66000 0x00014000
9400 14:00:20.291911 RAMOOPS 7. 0xffe66000 0x00100000
9401 14:00:20.295120 COREBOOT 8. 0xffe64000 0x00002000
9402 14:00:20.295211 IMD small region:
9403 14:00:20.298637 IMD ROOT 0. 0xffffec00 0x00000400
9404 14:00:20.301784 VPD 1. 0xffffeb80 0x0000006c
9405 14:00:20.305110 MMC STATUS 2. 0xffffeb60 0x00000004
9406 14:00:20.311475 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9407 14:00:20.314989 Probing TPM: done!
9408 14:00:20.318453 Connected to device vid:did:rid of 1ae0:0028:00
9409 14:00:20.328717 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9410 14:00:20.331600 Initialized TPM device CR50 revision 0
9411 14:00:20.335523 Checking cr50 for pending updates
9412 14:00:20.338478 Reading cr50 TPM mode
9413 14:00:20.347226 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9414 14:00:20.354147 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9415 14:00:20.394227 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9416 14:00:20.397252 Checking segment from ROM address 0x40100000
9417 14:00:20.400581 Checking segment from ROM address 0x4010001c
9418 14:00:20.407707 Loading segment from ROM address 0x40100000
9419 14:00:20.407796 code (compression=0)
9420 14:00:20.414157 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9421 14:00:20.424035 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9422 14:00:20.424122 it's not compressed!
9423 14:00:20.430688 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9424 14:00:20.434347 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9425 14:00:20.454570 Loading segment from ROM address 0x4010001c
9426 14:00:20.454658 Entry Point 0x80000000
9427 14:00:20.458095 Loaded segments
9428 14:00:20.461261 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9429 14:00:20.467784 Jumping to boot code at 0x80000000(0xffe64000)
9430 14:00:20.474754 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9431 14:00:20.481245 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9432 14:00:20.489185 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9433 14:00:20.492495 Checking segment from ROM address 0x40100000
9434 14:00:20.495542 Checking segment from ROM address 0x4010001c
9435 14:00:20.502266 Loading segment from ROM address 0x40100000
9436 14:00:20.502398 code (compression=1)
9437 14:00:20.508673 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9438 14:00:20.519115 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9439 14:00:20.519244 using LZMA
9440 14:00:20.527284 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9441 14:00:20.534173 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9442 14:00:20.537600 Loading segment from ROM address 0x4010001c
9443 14:00:20.537726 Entry Point 0x54601000
9444 14:00:20.540810 Loaded segments
9445 14:00:20.544285 NOTICE: MT8192 bl31_setup
9446 14:00:20.550765 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9447 14:00:20.554275 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9448 14:00:20.557816 WARNING: region 0:
9449 14:00:20.560792 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9450 14:00:20.560926 WARNING: region 1:
9451 14:00:20.567865 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9452 14:00:20.570862 WARNING: region 2:
9453 14:00:20.574335 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9454 14:00:20.577904 WARNING: region 3:
9455 14:00:20.581405 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9456 14:00:20.584270 WARNING: region 4:
9457 14:00:20.587944 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9458 14:00:20.591174 WARNING: region 5:
9459 14:00:20.594768 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 14:00:20.597778 WARNING: region 6:
9461 14:00:20.601254 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 14:00:20.601387 WARNING: region 7:
9463 14:00:20.607442 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 14:00:20.614150 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9465 14:00:20.617693 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9466 14:00:20.621230 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9467 14:00:20.628285 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9468 14:00:20.631101 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9469 14:00:20.634723 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9470 14:00:20.641045 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9471 14:00:20.644446 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9472 14:00:20.647573 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9473 14:00:20.654314 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9474 14:00:20.657948 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9475 14:00:20.661528 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9476 14:00:20.667880 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9477 14:00:20.671063 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9478 14:00:20.677715 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9479 14:00:20.681284 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9480 14:00:20.684328 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9481 14:00:20.690769 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9482 14:00:20.694505 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9483 14:00:20.697942 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9484 14:00:20.704535 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9485 14:00:20.707727 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9486 14:00:20.714244 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9487 14:00:20.717872 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9488 14:00:20.724634 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9489 14:00:20.727774 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9490 14:00:20.731515 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9491 14:00:20.737624 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9492 14:00:20.740830 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9493 14:00:20.744455 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9494 14:00:20.751177 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9495 14:00:20.754528 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9496 14:00:20.757781 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9497 14:00:20.764760 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9498 14:00:20.767551 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9499 14:00:20.771132 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9500 14:00:20.774494 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9501 14:00:20.780785 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9502 14:00:20.784187 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9503 14:00:20.787792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9504 14:00:20.790864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9505 14:00:20.797867 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9506 14:00:20.801025 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9507 14:00:20.804346 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9508 14:00:20.807892 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9509 14:00:20.814540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9510 14:00:20.817770 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9511 14:00:20.820958 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9512 14:00:20.827941 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9513 14:00:20.831217 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9514 14:00:20.834747 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9515 14:00:20.841360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9516 14:00:20.844310 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9517 14:00:20.850973 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9518 14:00:20.854388 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9519 14:00:20.860953 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9520 14:00:20.864301 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9521 14:00:20.867995 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9522 14:00:20.874460 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9523 14:00:20.877904 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9524 14:00:20.885006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9525 14:00:20.887643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9526 14:00:20.894706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9527 14:00:20.897773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9528 14:00:20.904754 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9529 14:00:20.907564 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9530 14:00:20.911088 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9531 14:00:20.917776 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9532 14:00:20.921136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9533 14:00:20.927864 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9534 14:00:20.931464 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9535 14:00:20.934548 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9536 14:00:20.941639 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9537 14:00:20.944553 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9538 14:00:20.951136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9539 14:00:20.954590 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9540 14:00:20.961516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9541 14:00:20.964348 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9542 14:00:20.971413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9543 14:00:20.974764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9544 14:00:20.977945 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9545 14:00:20.984325 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9546 14:00:20.988273 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9547 14:00:20.994607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9548 14:00:20.998068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9549 14:00:21.001185 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9550 14:00:21.008088 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9551 14:00:21.011778 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9552 14:00:21.018308 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9553 14:00:21.021559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9554 14:00:21.028099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9555 14:00:21.031560 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9556 14:00:21.035122 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9557 14:00:21.041866 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9558 14:00:21.044902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9559 14:00:21.051373 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9560 14:00:21.054971 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9561 14:00:21.058587 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9562 14:00:21.061627 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9563 14:00:21.068410 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9564 14:00:21.071912 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9565 14:00:21.075153 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9566 14:00:21.081757 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9567 14:00:21.085144 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9568 14:00:21.091439 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9569 14:00:21.094870 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9570 14:00:21.098361 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9571 14:00:21.105227 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9572 14:00:21.108316 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9573 14:00:21.114935 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9574 14:00:21.118285 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9575 14:00:21.121986 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9576 14:00:21.128307 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9577 14:00:21.131863 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9578 14:00:21.138705 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9579 14:00:21.141601 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9580 14:00:21.145210 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9581 14:00:21.148534 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9582 14:00:21.155084 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9583 14:00:21.158333 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9584 14:00:21.162004 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9585 14:00:21.165164 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9586 14:00:21.171660 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9587 14:00:21.175546 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9588 14:00:21.178295 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9589 14:00:21.185214 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9590 14:00:21.188732 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9591 14:00:21.195401 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9592 14:00:21.198686 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9593 14:00:21.202015 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9594 14:00:21.208694 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9595 14:00:21.211558 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9596 14:00:21.214914 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9597 14:00:21.222087 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9598 14:00:21.225266 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9599 14:00:21.231624 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9600 14:00:21.235045 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9601 14:00:21.238694 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9602 14:00:21.245401 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9603 14:00:21.248877 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9604 14:00:21.255108 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9605 14:00:21.258577 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9606 14:00:21.261956 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9607 14:00:21.268598 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9608 14:00:21.272233 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9609 14:00:21.275231 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9610 14:00:21.281781 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9611 14:00:21.285434 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9612 14:00:21.291969 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9613 14:00:21.295353 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9614 14:00:21.298787 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9615 14:00:21.305405 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9616 14:00:21.308687 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9617 14:00:21.312599 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9618 14:00:21.318563 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9619 14:00:21.321947 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9620 14:00:21.328688 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9621 14:00:21.332177 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9622 14:00:21.335533 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9623 14:00:21.342016 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9624 14:00:21.345652 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9625 14:00:21.352268 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9626 14:00:21.355764 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9627 14:00:21.358577 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9628 14:00:21.365334 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9629 14:00:21.368821 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9630 14:00:21.372018 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9631 14:00:21.378864 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9632 14:00:21.381804 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9633 14:00:21.389085 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9634 14:00:21.391958 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9635 14:00:21.395559 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9636 14:00:21.402166 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9637 14:00:21.405811 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9638 14:00:21.408715 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9639 14:00:21.415526 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9640 14:00:21.418944 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9641 14:00:21.425405 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9642 14:00:21.429196 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9643 14:00:21.432092 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9644 14:00:21.439068 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9645 14:00:21.442237 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9646 14:00:21.448896 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9647 14:00:21.452138 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9648 14:00:21.455201 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9649 14:00:21.462550 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9650 14:00:21.465646 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9651 14:00:21.472271 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9652 14:00:21.475265 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9653 14:00:21.478947 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9654 14:00:21.485362 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9655 14:00:21.488854 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9656 14:00:21.495273 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9657 14:00:21.498817 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9658 14:00:21.501907 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9659 14:00:21.508456 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9660 14:00:21.512233 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9661 14:00:21.518461 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9662 14:00:21.521998 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9663 14:00:21.528634 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9664 14:00:21.531927 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9665 14:00:21.535220 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9666 14:00:21.541707 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9667 14:00:21.545001 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9668 14:00:21.551888 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9669 14:00:21.555254 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9670 14:00:21.561854 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9671 14:00:21.565012 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9672 14:00:21.568083 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9673 14:00:21.574829 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9674 14:00:21.578348 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9675 14:00:21.584776 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9676 14:00:21.588114 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9677 14:00:21.591815 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9678 14:00:21.597973 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9679 14:00:21.601301 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9680 14:00:21.608098 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9681 14:00:21.611479 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9682 14:00:21.618098 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9683 14:00:21.621112 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9684 14:00:21.624848 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9685 14:00:21.631221 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9686 14:00:21.634740 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9687 14:00:21.641532 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9688 14:00:21.644369 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9689 14:00:21.647776 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9690 14:00:21.654293 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9691 14:00:21.657871 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9692 14:00:21.664466 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9693 14:00:21.667725 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9694 14:00:21.671277 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9695 14:00:21.674461 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9696 14:00:21.680987 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9697 14:00:21.684373 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9698 14:00:21.687497 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9699 14:00:21.694343 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9700 14:00:21.697371 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9701 14:00:21.700788 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9702 14:00:21.707669 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9703 14:00:21.710744 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9704 14:00:21.714225 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9705 14:00:21.720952 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9706 14:00:21.724667 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9707 14:00:21.727516 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9708 14:00:21.734309 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9709 14:00:21.737840 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9710 14:00:21.744411 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9711 14:00:21.747489 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9712 14:00:21.751103 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9713 14:00:21.757625 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9714 14:00:21.761264 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9715 14:00:21.764368 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9716 14:00:21.771228 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9717 14:00:21.774041 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9718 14:00:21.777842 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9719 14:00:21.784118 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9720 14:00:21.787331 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9721 14:00:21.794383 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9722 14:00:21.797273 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9723 14:00:21.800489 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9724 14:00:21.807069 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9725 14:00:21.810951 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9726 14:00:21.814141 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9727 14:00:21.821040 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9728 14:00:21.823841 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9729 14:00:21.830509 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9730 14:00:21.833979 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9731 14:00:21.837048 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9732 14:00:21.844302 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9733 14:00:21.847257 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9734 14:00:21.850792 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9735 14:00:21.853946 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9736 14:00:21.857408 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9737 14:00:21.863458 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9738 14:00:21.866939 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9739 14:00:21.870029 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9740 14:00:21.873666 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9741 14:00:21.880200 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9742 14:00:21.883829 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9743 14:00:21.886879 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9744 14:00:21.893230 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9745 14:00:21.896747 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9746 14:00:21.900182 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9747 14:00:21.906669 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9748 14:00:21.910235 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9749 14:00:21.913728 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9750 14:00:21.920426 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9751 14:00:21.923589 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9752 14:00:21.929907 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9753 14:00:21.933788 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9754 14:00:21.936899 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9755 14:00:21.943649 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9756 14:00:21.946660 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9757 14:00:21.953581 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9758 14:00:21.957063 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9759 14:00:21.963457 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9760 14:00:21.966740 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9761 14:00:21.970455 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9762 14:00:21.976775 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9763 14:00:21.979933 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9764 14:00:21.986800 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9765 14:00:21.990220 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9766 14:00:21.993296 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9767 14:00:21.999629 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9768 14:00:22.003115 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9769 14:00:22.009745 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9770 14:00:22.013382 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9771 14:00:22.016422 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9772 14:00:22.022930 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9773 14:00:22.026354 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9774 14:00:22.032865 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9775 14:00:22.036116 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9776 14:00:22.043189 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9777 14:00:22.046487 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9778 14:00:22.049837 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9779 14:00:22.056472 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9780 14:00:22.060007 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9781 14:00:22.066077 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9782 14:00:22.069573 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9783 14:00:22.072989 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9784 14:00:22.079523 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9785 14:00:22.083100 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9786 14:00:22.089970 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9787 14:00:22.092668 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9788 14:00:22.096368 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9789 14:00:22.102763 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9790 14:00:22.106227 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9791 14:00:22.112635 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9792 14:00:22.116023 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9793 14:00:22.119370 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9794 14:00:22.126274 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9795 14:00:22.129353 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9796 14:00:22.136362 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9797 14:00:22.139192 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9798 14:00:22.142814 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9799 14:00:22.149379 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9800 14:00:22.152743 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9801 14:00:22.159268 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9802 14:00:22.162667 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9803 14:00:22.166258 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9804 14:00:22.172444 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9805 14:00:22.175785 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9806 14:00:22.182793 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9807 14:00:22.185942 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9808 14:00:22.192485 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9809 14:00:22.196353 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9810 14:00:22.199282 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9811 14:00:22.205932 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9812 14:00:22.209226 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9813 14:00:22.216109 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9814 14:00:22.218933 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9815 14:00:22.222439 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9816 14:00:22.229091 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9817 14:00:22.232686 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9818 14:00:22.239410 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9819 14:00:22.242418 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9820 14:00:22.245784 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9821 14:00:22.252577 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9822 14:00:22.255819 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9823 14:00:22.262182 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9824 14:00:22.265896 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9825 14:00:22.272252 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9826 14:00:22.275407 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9827 14:00:22.279131 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9828 14:00:22.285658 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9829 14:00:22.289087 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9830 14:00:22.295880 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9831 14:00:22.298912 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9832 14:00:22.305971 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9833 14:00:22.308852 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9834 14:00:22.312367 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9835 14:00:22.319208 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9836 14:00:22.322136 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9837 14:00:22.329266 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9838 14:00:22.332433 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9839 14:00:22.339135 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9840 14:00:22.342095 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9841 14:00:22.345772 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9842 14:00:22.352263 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9843 14:00:22.355878 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9844 14:00:22.362163 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9845 14:00:22.365507 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9846 14:00:22.372248 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9847 14:00:22.375190 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9848 14:00:22.382414 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9849 14:00:22.385488 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9850 14:00:22.389012 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9851 14:00:22.395038 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9852 14:00:22.398444 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9853 14:00:22.405131 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9854 14:00:22.408764 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9855 14:00:22.415265 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9856 14:00:22.418592 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9857 14:00:22.422251 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9858 14:00:22.428440 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9859 14:00:22.431889 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9860 14:00:22.438356 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9861 14:00:22.441978 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9862 14:00:22.448140 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9863 14:00:22.451883 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9864 14:00:22.458336 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9865 14:00:22.461383 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9866 14:00:22.464850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9867 14:00:22.471238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9868 14:00:22.474609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9869 14:00:22.481089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9870 14:00:22.484746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9871 14:00:22.491355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9872 14:00:22.494990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9873 14:00:22.501268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9874 14:00:22.504964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9875 14:00:22.511283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9876 14:00:22.514325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9877 14:00:22.521091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9878 14:00:22.524157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9879 14:00:22.527557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9880 14:00:22.534500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9881 14:00:22.537715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9882 14:00:22.544158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9883 14:00:22.547754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9884 14:00:22.554019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9885 14:00:22.557586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9886 14:00:22.564206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9887 14:00:22.567660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9888 14:00:22.574054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9889 14:00:22.577741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9890 14:00:22.583983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9891 14:00:22.587867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9892 14:00:22.594078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9893 14:00:22.597350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9894 14:00:22.603875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9895 14:00:22.607128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9896 14:00:22.614130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9897 14:00:22.617220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9898 14:00:22.623904 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9899 14:00:22.624014 INFO: [APUAPC] vio 0
9900 14:00:22.630749 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9901 14:00:22.634012 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9902 14:00:22.637480 INFO: [APUAPC] D0_APC_0: 0x400510
9903 14:00:22.641061 INFO: [APUAPC] D0_APC_1: 0x0
9904 14:00:22.644357 INFO: [APUAPC] D0_APC_2: 0x1540
9905 14:00:22.647148 INFO: [APUAPC] D0_APC_3: 0x0
9906 14:00:22.650675 INFO: [APUAPC] D1_APC_0: 0xffffffff
9907 14:00:22.654394 INFO: [APUAPC] D1_APC_1: 0xffffffff
9908 14:00:22.657076 INFO: [APUAPC] D1_APC_2: 0x3fffff
9909 14:00:22.660888 INFO: [APUAPC] D1_APC_3: 0x0
9910 14:00:22.664536 INFO: [APUAPC] D2_APC_0: 0xffffffff
9911 14:00:22.667430 INFO: [APUAPC] D2_APC_1: 0xffffffff
9912 14:00:22.670908 INFO: [APUAPC] D2_APC_2: 0x3fffff
9913 14:00:22.673888 INFO: [APUAPC] D2_APC_3: 0x0
9914 14:00:22.677322 INFO: [APUAPC] D3_APC_0: 0xffffffff
9915 14:00:22.680990 INFO: [APUAPC] D3_APC_1: 0xffffffff
9916 14:00:22.683814 INFO: [APUAPC] D3_APC_2: 0x3fffff
9917 14:00:22.687460 INFO: [APUAPC] D3_APC_3: 0x0
9918 14:00:22.690935 INFO: [APUAPC] D4_APC_0: 0xffffffff
9919 14:00:22.693981 INFO: [APUAPC] D4_APC_1: 0xffffffff
9920 14:00:22.697758 INFO: [APUAPC] D4_APC_2: 0x3fffff
9921 14:00:22.697854 INFO: [APUAPC] D4_APC_3: 0x0
9922 14:00:22.700941 INFO: [APUAPC] D5_APC_0: 0xffffffff
9923 14:00:22.703766 INFO: [APUAPC] D5_APC_1: 0xffffffff
9924 14:00:22.707216 INFO: [APUAPC] D5_APC_2: 0x3fffff
9925 14:00:22.710815 INFO: [APUAPC] D5_APC_3: 0x0
9926 14:00:22.713995 INFO: [APUAPC] D6_APC_0: 0xffffffff
9927 14:00:22.717472 INFO: [APUAPC] D6_APC_1: 0xffffffff
9928 14:00:22.720862 INFO: [APUAPC] D6_APC_2: 0x3fffff
9929 14:00:22.724031 INFO: [APUAPC] D6_APC_3: 0x0
9930 14:00:22.727345 INFO: [APUAPC] D7_APC_0: 0xffffffff
9931 14:00:22.730705 INFO: [APUAPC] D7_APC_1: 0xffffffff
9932 14:00:22.733623 INFO: [APUAPC] D7_APC_2: 0x3fffff
9933 14:00:22.737161 INFO: [APUAPC] D7_APC_3: 0x0
9934 14:00:22.740759 INFO: [APUAPC] D8_APC_0: 0xffffffff
9935 14:00:22.744165 INFO: [APUAPC] D8_APC_1: 0xffffffff
9936 14:00:22.747051 INFO: [APUAPC] D8_APC_2: 0x3fffff
9937 14:00:22.750661 INFO: [APUAPC] D8_APC_3: 0x0
9938 14:00:22.753607 INFO: [APUAPC] D9_APC_0: 0xffffffff
9939 14:00:22.757027 INFO: [APUAPC] D9_APC_1: 0xffffffff
9940 14:00:22.760806 INFO: [APUAPC] D9_APC_2: 0x3fffff
9941 14:00:22.763755 INFO: [APUAPC] D9_APC_3: 0x0
9942 14:00:22.767516 INFO: [APUAPC] D10_APC_0: 0xffffffff
9943 14:00:22.770206 INFO: [APUAPC] D10_APC_1: 0xffffffff
9944 14:00:22.773824 INFO: [APUAPC] D10_APC_2: 0x3fffff
9945 14:00:22.776967 INFO: [APUAPC] D10_APC_3: 0x0
9946 14:00:22.780476 INFO: [APUAPC] D11_APC_0: 0xffffffff
9947 14:00:22.783980 INFO: [APUAPC] D11_APC_1: 0xffffffff
9948 14:00:22.786832 INFO: [APUAPC] D11_APC_2: 0x3fffff
9949 14:00:22.790219 INFO: [APUAPC] D11_APC_3: 0x0
9950 14:00:22.793799 INFO: [APUAPC] D12_APC_0: 0xffffffff
9951 14:00:22.797009 INFO: [APUAPC] D12_APC_1: 0xffffffff
9952 14:00:22.800561 INFO: [APUAPC] D12_APC_2: 0x3fffff
9953 14:00:22.803632 INFO: [APUAPC] D12_APC_3: 0x0
9954 14:00:22.807085 INFO: [APUAPC] D13_APC_0: 0xffffffff
9955 14:00:22.810403 INFO: [APUAPC] D13_APC_1: 0xffffffff
9956 14:00:22.813818 INFO: [APUAPC] D13_APC_2: 0x3fffff
9957 14:00:22.816737 INFO: [APUAPC] D13_APC_3: 0x0
9958 14:00:22.820478 INFO: [APUAPC] D14_APC_0: 0xffffffff
9959 14:00:22.823880 INFO: [APUAPC] D14_APC_1: 0xffffffff
9960 14:00:22.826787 INFO: [APUAPC] D14_APC_2: 0x3fffff
9961 14:00:22.830298 INFO: [APUAPC] D14_APC_3: 0x0
9962 14:00:22.833497 INFO: [APUAPC] D15_APC_0: 0xffffffff
9963 14:00:22.836914 INFO: [APUAPC] D15_APC_1: 0xffffffff
9964 14:00:22.840486 INFO: [APUAPC] D15_APC_2: 0x3fffff
9965 14:00:22.843459 INFO: [APUAPC] D15_APC_3: 0x0
9966 14:00:22.847363 INFO: [APUAPC] APC_CON: 0x4
9967 14:00:22.850391 INFO: [NOCDAPC] D0_APC_0: 0x0
9968 14:00:22.853651 INFO: [NOCDAPC] D0_APC_1: 0x0
9969 14:00:22.856792 INFO: [NOCDAPC] D1_APC_0: 0x0
9970 14:00:22.856905 INFO: [NOCDAPC] D1_APC_1: 0xfff
9971 14:00:22.860116 INFO: [NOCDAPC] D2_APC_0: 0x0
9972 14:00:22.863745 INFO: [NOCDAPC] D2_APC_1: 0xfff
9973 14:00:22.866904 INFO: [NOCDAPC] D3_APC_0: 0x0
9974 14:00:22.870012 INFO: [NOCDAPC] D3_APC_1: 0xfff
9975 14:00:22.873589 INFO: [NOCDAPC] D4_APC_0: 0x0
9976 14:00:22.876578 INFO: [NOCDAPC] D4_APC_1: 0xfff
9977 14:00:22.879683 INFO: [NOCDAPC] D5_APC_0: 0x0
9978 14:00:22.883055 INFO: [NOCDAPC] D5_APC_1: 0xfff
9979 14:00:22.886554 INFO: [NOCDAPC] D6_APC_0: 0x0
9980 14:00:22.889701 INFO: [NOCDAPC] D6_APC_1: 0xfff
9981 14:00:22.893033 INFO: [NOCDAPC] D7_APC_0: 0x0
9982 14:00:22.893115 INFO: [NOCDAPC] D7_APC_1: 0xfff
9983 14:00:22.896520 INFO: [NOCDAPC] D8_APC_0: 0x0
9984 14:00:22.899500 INFO: [NOCDAPC] D8_APC_1: 0xfff
9985 14:00:22.903133 INFO: [NOCDAPC] D9_APC_0: 0x0
9986 14:00:22.906117 INFO: [NOCDAPC] D9_APC_1: 0xfff
9987 14:00:22.909664 INFO: [NOCDAPC] D10_APC_0: 0x0
9988 14:00:22.913223 INFO: [NOCDAPC] D10_APC_1: 0xfff
9989 14:00:22.916356 INFO: [NOCDAPC] D11_APC_0: 0x0
9990 14:00:22.919771 INFO: [NOCDAPC] D11_APC_1: 0xfff
9991 14:00:22.923063 INFO: [NOCDAPC] D12_APC_0: 0x0
9992 14:00:22.926206 INFO: [NOCDAPC] D12_APC_1: 0xfff
9993 14:00:22.929605 INFO: [NOCDAPC] D13_APC_0: 0x0
9994 14:00:22.932686 INFO: [NOCDAPC] D13_APC_1: 0xfff
9995 14:00:22.936187 INFO: [NOCDAPC] D14_APC_0: 0x0
9996 14:00:22.936310 INFO: [NOCDAPC] D14_APC_1: 0xfff
9997 14:00:22.939427 INFO: [NOCDAPC] D15_APC_0: 0x0
9998 14:00:22.942974 INFO: [NOCDAPC] D15_APC_1: 0xfff
9999 14:00:22.946416 INFO: [NOCDAPC] APC_CON: 0x4
10000 14:00:22.949574 INFO: [APUAPC] set_apusys_apc done
10001 14:00:22.952774 INFO: [DEVAPC] devapc_init done
10002 14:00:22.956255 INFO: GICv3 without legacy support detected.
10003 14:00:22.963020 INFO: ARM GICv3 driver initialized in EL3
10004 14:00:22.965927 INFO: Maximum SPI INTID supported: 639
10005 14:00:22.969288 INFO: BL31: Initializing runtime services
10006 14:00:22.976183 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10007 14:00:22.979369 INFO: SPM: enable CPC mode
10008 14:00:22.982420 INFO: mcdi ready for mcusys-off-idle and system suspend
10009 14:00:22.989294 INFO: BL31: Preparing for EL3 exit to normal world
10010 14:00:22.992906 INFO: Entry point address = 0x80000000
10011 14:00:22.992988 INFO: SPSR = 0x8
10012 14:00:22.999028
10013 14:00:22.999109
10014 14:00:22.999203
10015 14:00:23.002182 Starting depthcharge on Spherion...
10016 14:00:23.002311
10017 14:00:23.002406 Wipe memory regions:
10018 14:00:23.002467
10019 14:00:23.003161 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10020 14:00:23.003259 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10021 14:00:23.003341 Setting prompt string to ['asurada:']
10022 14:00:23.003424 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10023 14:00:23.005653 [0x00000040000000, 0x00000054600000)
10024 14:00:23.128401
10025 14:00:23.128563 [0x00000054660000, 0x00000080000000)
10026 14:00:23.388791
10027 14:00:23.388927 [0x000000821a7280, 0x000000ffe64000)
10028 14:00:24.133781
10029 14:00:24.133916 [0x00000100000000, 0x00000240000000)
10030 14:00:26.024376
10031 14:00:26.026849 Initializing XHCI USB controller at 0x11200000.
10032 14:00:27.065002
10033 14:00:27.068375 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10034 14:00:27.068462
10035 14:00:27.068528
10036 14:00:27.068589
10037 14:00:27.068874 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10039 14:00:27.169212 asurada: tftpboot 192.168.201.1 11588075/tftp-deploy-x8a14o6p/kernel/image.itb 11588075/tftp-deploy-x8a14o6p/kernel/cmdline
10040 14:00:27.169382 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10041 14:00:27.169500 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10042 14:00:27.174148 tftpboot 192.168.201.1 11588075/tftp-deploy-x8a14o6p/kernel/image.ittp-deploy-x8a14o6p/kernel/cmdline
10043 14:00:27.174231
10044 14:00:27.174295 Waiting for link
10045 14:00:27.334409
10046 14:00:27.334536 R8152: Initializing
10047 14:00:27.334603
10048 14:00:27.337719 Version 9 (ocp_data = 6010)
10049 14:00:27.337802
10050 14:00:27.341323 R8152: Done initializing
10051 14:00:27.341405
10052 14:00:27.341518 Adding net device
10053 14:00:29.212985
10054 14:00:29.213172 done.
10055 14:00:29.213286
10056 14:00:29.213397 MAC: 00:e0:4c:78:7a:aa
10057 14:00:29.213508
10058 14:00:29.216624 Sending DHCP discover... done.
10059 14:00:29.216748
10060 14:00:36.740273 Waiting for reply... done.
10061 14:00:36.740532
10062 14:00:36.740649 Sending DHCP request... done.
10063 14:00:36.740756
10064 14:00:36.747505 Waiting for reply... done.
10065 14:00:36.747629
10066 14:00:36.747786 My ip is 192.168.201.12
10067 14:00:36.747896
10068 14:00:36.751013 The DHCP server ip is 192.168.201.1
10069 14:00:36.751136
10070 14:00:36.758090 TFTP server IP predefined by user: 192.168.201.1
10071 14:00:36.758214
10072 14:00:36.764634 Bootfile predefined by user: 11588075/tftp-deploy-x8a14o6p/kernel/image.itb
10073 14:00:36.764758
10074 14:00:36.764868 Sending tftp read request... done.
10075 14:00:36.768195
10076 14:00:36.771104 Waiting for the transfer...
10077 14:00:36.771239
10078 14:00:37.039228 00000000 ################################################################
10079 14:00:37.039431
10080 14:00:37.303469 00080000 ################################################################
10081 14:00:37.303678
10082 14:00:37.579320 00100000 ################################################################
10083 14:00:37.579468
10084 14:00:37.842046 00180000 ################################################################
10085 14:00:37.842192
10086 14:00:38.101917 00200000 ################################################################
10087 14:00:38.102072
10088 14:00:38.362123 00280000 ################################################################
10089 14:00:38.362261
10090 14:00:38.637569 00300000 ################################################################
10091 14:00:38.637781
10092 14:00:38.919900 00380000 ################################################################
10093 14:00:38.920049
10094 14:00:39.189576 00400000 ################################################################
10095 14:00:39.189725
10096 14:00:39.445813 00480000 ################################################################
10097 14:00:39.445945
10098 14:00:39.709234 00500000 ################################################################
10099 14:00:39.709428
10100 14:00:39.969579 00580000 ################################################################
10101 14:00:39.969774
10102 14:00:40.232989 00600000 ################################################################
10103 14:00:40.233126
10104 14:00:40.501284 00680000 ################################################################
10105 14:00:40.501445
10106 14:00:40.755813 00700000 ################################################################
10107 14:00:40.755980
10108 14:00:41.005464 00780000 ################################################################
10109 14:00:41.005680
10110 14:00:41.260658 00800000 ################################################################
10111 14:00:41.260828
10112 14:00:41.513777 00880000 ################################################################
10113 14:00:41.513927
10114 14:00:41.767333 00900000 ################################################################
10115 14:00:41.767506
10116 14:00:42.022501 00980000 ################################################################
10117 14:00:42.022653
10118 14:00:42.283778 00a00000 ################################################################
10119 14:00:42.284009
10120 14:00:42.547762 00a80000 ################################################################
10121 14:00:42.547961
10122 14:00:42.811562 00b00000 ################################################################
10123 14:00:42.811762
10124 14:00:43.090767 00b80000 ################################################################
10125 14:00:43.090906
10126 14:00:43.363816 00c00000 ################################################################
10127 14:00:43.364015
10128 14:00:43.645959 00c80000 ################################################################
10129 14:00:43.646098
10130 14:00:43.918972 00d00000 ################################################################
10131 14:00:43.919145
10132 14:00:44.196560 00d80000 ################################################################
10133 14:00:44.196699
10134 14:00:44.463634 00e00000 ################################################################
10135 14:00:44.463804
10136 14:00:44.736726 00e80000 ################################################################
10137 14:00:44.736909
10138 14:00:45.004614 00f00000 ################################################################
10139 14:00:45.004771
10140 14:00:45.269996 00f80000 ################################################################
10141 14:00:45.270136
10142 14:00:45.556411 01000000 ################################################################
10143 14:00:45.556546
10144 14:00:45.820119 01080000 ################################################################
10145 14:00:45.820255
10146 14:00:46.082359 01100000 ################################################################
10147 14:00:46.082521
10148 14:00:46.354393 01180000 ################################################################
10149 14:00:46.354562
10150 14:00:46.630192 01200000 ################################################################
10151 14:00:46.630321
10152 14:00:46.918136 01280000 ################################################################
10153 14:00:46.918274
10154 14:00:47.178613 01300000 ################################################################
10155 14:00:47.178778
10156 14:00:47.445638 01380000 ################################################################
10157 14:00:47.445778
10158 14:00:47.702582 01400000 ################################################################
10159 14:00:47.702747
10160 14:00:47.960093 01480000 ################################################################
10161 14:00:47.960263
10162 14:00:48.214679 01500000 ################################################################
10163 14:00:48.214887
10164 14:00:48.474557 01580000 ################################################################
10165 14:00:48.474715
10166 14:00:48.747915 01600000 ################################################################
10167 14:00:48.748125
10168 14:00:49.049637 01680000 ################################################################
10169 14:00:49.049846
10170 14:00:49.343705 01700000 ################################################################
10171 14:00:49.343921
10172 14:00:49.619992 01780000 ################################################################
10173 14:00:49.620225
10174 14:00:49.886399 01800000 ################################################################
10175 14:00:49.886580
10176 14:00:50.152476 01880000 ################################################################
10177 14:00:50.152650
10178 14:00:50.412957 01900000 ################################################################
10179 14:00:50.413129
10180 14:00:50.680470 01980000 ################################################################
10181 14:00:50.680629
10182 14:00:50.944472 01a00000 ################################################################
10183 14:00:50.944663
10184 14:00:51.213050 01a80000 ################################################################
10185 14:00:51.213210
10186 14:00:51.498838 01b00000 ################################################################
10187 14:00:51.499001
10188 14:00:51.789419 01b80000 ################################################################
10189 14:00:51.789607
10190 14:00:52.068167 01c00000 ################################################################
10191 14:00:52.068327
10192 14:00:52.332698 01c80000 ################################################################
10193 14:00:52.332832
10194 14:00:52.593331 01d00000 ################################################################
10195 14:00:52.593501
10196 14:00:52.849568 01d80000 ################################################################
10197 14:00:52.849703
10198 14:00:53.140090 01e00000 ################################################################
10199 14:00:53.140218
10200 14:00:53.413016 01e80000 ################################################################
10201 14:00:53.413178
10202 14:00:53.666789 01f00000 ################################################################
10203 14:00:53.666921
10204 14:00:53.919122 01f80000 ################################################################
10205 14:00:53.919253
10206 14:00:54.180780 02000000 ################################################################
10207 14:00:54.180911
10208 14:00:54.460416 02080000 ################################################################
10209 14:00:54.460552
10210 14:00:54.736969 02100000 ################################################################
10211 14:00:54.737131
10212 14:00:55.021210 02180000 ################################################################
10213 14:00:55.021363
10214 14:00:55.287139 02200000 ################################################################
10215 14:00:55.287300
10216 14:00:55.545357 02280000 ################################################################
10217 14:00:55.545494
10218 14:00:55.833032 02300000 ################################################################
10219 14:00:55.833248
10220 14:00:56.109179 02380000 ################################################################
10221 14:00:56.109323
10222 14:00:56.399857 02400000 ################################################################
10223 14:00:56.399998
10224 14:00:56.683935 02480000 ################################################################
10225 14:00:56.684086
10226 14:00:56.966172 02500000 ################################################################
10227 14:00:56.966319
10228 14:00:57.257117 02580000 ################################################################
10229 14:00:57.257265
10230 14:00:57.556078 02600000 ################################################################
10231 14:00:57.556224
10232 14:00:57.856694 02680000 ################################################################
10233 14:00:57.856834
10234 14:00:58.156868 02700000 ################################################################
10235 14:00:58.157010
10236 14:00:58.447757 02780000 ################################################################
10237 14:00:58.447928
10238 14:00:58.746438 02800000 ################################################################
10239 14:00:58.746580
10240 14:00:59.008946 02880000 ################################################################
10241 14:00:59.009093
10242 14:00:59.300881 02900000 ################################################################
10243 14:00:59.301040
10244 14:00:59.584855 02980000 ################################################################
10245 14:00:59.584999
10246 14:00:59.848732 02a00000 ################################################################
10247 14:00:59.848871
10248 14:01:00.143542 02a80000 ################################################################
10249 14:01:00.143741
10250 14:01:00.411404 02b00000 ################################################################
10251 14:01:00.411552
10252 14:01:00.664796 02b80000 ################################################################
10253 14:01:00.664937
10254 14:01:00.918553 02c00000 ################################################################
10255 14:01:00.918695
10256 14:01:01.205031 02c80000 ################################################################
10257 14:01:01.205201
10258 14:01:01.492685 02d00000 ################################################################
10259 14:01:01.492830
10260 14:01:01.793570 02d80000 ################################################################
10261 14:01:01.793749
10262 14:01:02.094893 02e00000 ################################################################
10263 14:01:02.095072
10264 14:01:02.393770 02e80000 ################################################################
10265 14:01:02.393915
10266 14:01:02.694004 02f00000 ################################################################
10267 14:01:02.694150
10268 14:01:02.992623 02f80000 ################################################################
10269 14:01:02.992767
10270 14:01:03.279933 03000000 ################################################################
10271 14:01:03.280077
10272 14:01:03.574422 03080000 ################################################################
10273 14:01:03.574598
10274 14:01:03.876479 03100000 ################################################################
10275 14:01:03.876675
10276 14:01:04.168373 03180000 ################################################################
10277 14:01:04.168579
10278 14:01:04.460721 03200000 ################################################################
10279 14:01:04.460866
10280 14:01:04.756566 03280000 ################################################################
10281 14:01:04.756708
10282 14:01:05.042895 03300000 ################################################################
10283 14:01:05.043035
10284 14:01:05.341823 03380000 ################################################################
10285 14:01:05.341971
10286 14:01:05.619604 03400000 ################################################################
10287 14:01:05.619773
10288 14:01:05.879446 03480000 ################################################################
10289 14:01:05.879589
10290 14:01:06.150454 03500000 ################################################################
10291 14:01:06.150599
10292 14:01:06.427285 03580000 ################################################################
10293 14:01:06.427459
10294 14:01:06.710509 03600000 ################################################################
10295 14:01:06.710656
10296 14:01:06.999050 03680000 ################################################################
10297 14:01:06.999196
10298 14:01:07.293021 03700000 ################################################################
10299 14:01:07.293164
10300 14:01:07.578490 03780000 ################################################################
10301 14:01:07.578631
10302 14:01:07.863802 03800000 ################################################################
10303 14:01:07.863945
10304 14:01:08.150886 03880000 ################################################################
10305 14:01:08.151094
10306 14:01:08.447945 03900000 ################################################################
10307 14:01:08.448104
10308 14:01:08.744366 03980000 ################################################################
10309 14:01:08.744575
10310 14:01:09.044214 03a00000 ################################################################
10311 14:01:09.044368
10312 14:01:09.336147 03a80000 ################################################################
10313 14:01:09.336350
10314 14:01:09.633184 03b00000 ################################################################
10315 14:01:09.633397
10316 14:01:09.929490 03b80000 ################################################################
10317 14:01:09.929660
10318 14:01:10.229778 03c00000 ################################################################
10319 14:01:10.229925
10320 14:01:10.527960 03c80000 ################################################################
10321 14:01:10.528110
10322 14:01:10.822791 03d00000 ################################################################
10323 14:01:10.822939
10324 14:01:11.124942 03d80000 ################################################################
10325 14:01:11.125088
10326 14:01:11.420673 03e00000 ################################################################
10327 14:01:11.420817
10328 14:01:11.696593 03e80000 ################################################################
10329 14:01:11.696743
10330 14:01:11.976547 03f00000 ################################################################
10331 14:01:11.976691
10332 14:01:12.259505 03f80000 ################################################################
10333 14:01:12.259713
10334 14:01:12.541569 04000000 ################################################################
10335 14:01:12.541727
10336 14:01:12.817686 04080000 ################################################################
10337 14:01:12.817832
10338 14:01:13.098808 04100000 ################################################################
10339 14:01:13.098950
10340 14:01:13.377559 04180000 ################################################################
10341 14:01:13.377701
10342 14:01:13.659949 04200000 ################################################################
10343 14:01:13.660100
10344 14:01:13.939655 04280000 ################################################################
10345 14:01:13.939810
10346 14:01:14.227801 04300000 ################################################################
10347 14:01:14.228007
10348 14:01:14.518106 04380000 ################################################################
10349 14:01:14.518247
10350 14:01:14.794492 04400000 ################################################################
10351 14:01:14.794639
10352 14:01:15.068682 04480000 ################################################################
10353 14:01:15.068824
10354 14:01:15.343587 04500000 ################################################################
10355 14:01:15.343750
10356 14:01:15.623319 04580000 ################################################################
10357 14:01:15.623488
10358 14:01:15.916690 04600000 ################################################################
10359 14:01:15.916835
10360 14:01:16.203303 04680000 ################################################################
10361 14:01:16.203447
10362 14:01:16.487159 04700000 ################################################################
10363 14:01:16.487304
10364 14:01:16.777392 04780000 ################################################################
10365 14:01:16.777591
10366 14:01:17.068577 04800000 ################################################################
10367 14:01:17.068790
10368 14:01:17.353955 04880000 ################################################################
10369 14:01:17.354157
10370 14:01:17.636422 04900000 ################################################################
10371 14:01:17.636635
10372 14:01:17.921319 04980000 ################################################################
10373 14:01:17.921465
10374 14:01:18.207591 04a00000 ################################################################
10375 14:01:18.207831
10376 14:01:18.501462 04a80000 ################################################################
10377 14:01:18.501668
10378 14:01:18.797799 04b00000 ################################################################
10379 14:01:18.798010
10380 14:01:19.076486 04b80000 ################################################################
10381 14:01:19.076634
10382 14:01:19.355274 04c00000 ################################################################
10383 14:01:19.355482
10384 14:01:19.632634 04c80000 ################################################################
10385 14:01:19.632836
10386 14:01:19.914342 04d00000 ################################################################
10387 14:01:19.914480
10388 14:01:20.206296 04d80000 ################################################################
10389 14:01:20.206469
10390 14:01:20.489357 04e00000 ################################################################
10391 14:01:20.489506
10392 14:01:20.751168 04e80000 ################################################################
10393 14:01:20.751318
10394 14:01:21.034460 04f00000 ################################################################
10395 14:01:21.034610
10396 14:01:21.298919 04f80000 ################################################################
10397 14:01:21.299189
10398 14:01:21.573898 05000000 ################################################################
10399 14:01:21.574042
10400 14:01:21.837652 05080000 ################################################################
10401 14:01:21.837836
10402 14:01:22.108517 05100000 ################################################################
10403 14:01:22.108718
10404 14:01:22.377513 05180000 ################################################################
10405 14:01:22.377688
10406 14:01:22.663981 05200000 ################################################################
10407 14:01:22.664133
10408 14:01:22.925680 05280000 ################################################################
10409 14:01:22.925870
10410 14:01:23.176419 05300000 ################################################################
10411 14:01:23.176636
10412 14:01:23.444707 05380000 ################################################################
10413 14:01:23.444852
10414 14:01:23.720471 05400000 ################################################################
10415 14:01:23.720637
10416 14:01:23.981550 05480000 ################################################################
10417 14:01:23.981701
10418 14:01:24.249743 05500000 ################################################################
10419 14:01:24.249957
10420 14:01:24.516331 05580000 ################################################################
10421 14:01:24.516477
10422 14:01:24.783140 05600000 ################################################################
10423 14:01:24.783361
10424 14:01:25.039490 05680000 ################################################################
10425 14:01:25.039712
10426 14:01:25.300019 05700000 ################################################################
10427 14:01:25.300169
10428 14:01:25.562351 05780000 ################################################################
10429 14:01:25.562551
10430 14:01:25.838000 05800000 ################################################################
10431 14:01:25.838151
10432 14:01:26.108143 05880000 ################################################################
10433 14:01:26.108356
10434 14:01:26.376744 05900000 ################################################################
10435 14:01:26.376960
10436 14:01:26.647047 05980000 ################################################################
10437 14:01:26.647232
10438 14:01:26.928863 05a00000 ################################################################
10439 14:01:26.929008
10440 14:01:27.200411 05a80000 ################################################################
10441 14:01:27.200585
10442 14:01:27.470562 05b00000 ################################################################
10443 14:01:27.470738
10444 14:01:27.723565 05b80000 ################################################################
10445 14:01:27.723736
10446 14:01:27.981986 05c00000 ################################################################
10447 14:01:27.982129
10448 14:01:28.248902 05c80000 ################################################################
10449 14:01:28.249035
10450 14:01:28.515927 05d00000 ################################################################
10451 14:01:28.516095
10452 14:01:28.779581 05d80000 ################################################################
10453 14:01:28.779746
10454 14:01:29.043509 05e00000 ################################################################
10455 14:01:29.043689
10456 14:01:29.318495 05e80000 ################################################################
10457 14:01:29.318660
10458 14:01:29.600367 05f00000 ################################################################
10459 14:01:29.600570
10460 14:01:29.871566 05f80000 ################################################################
10461 14:01:29.871739
10462 14:01:30.132623 06000000 ################################################################
10463 14:01:30.132837
10464 14:01:30.389609 06080000 ################################################################
10465 14:01:30.389766
10466 14:01:30.657498 06100000 ################################################################
10467 14:01:30.657653
10468 14:01:30.944250 06180000 ################################################################
10469 14:01:30.944402
10470 14:01:31.201941 06200000 ################################################################
10471 14:01:31.202129
10472 14:01:31.459947 06280000 ################################################################
10473 14:01:31.460098
10474 14:01:31.712799 06300000 ################################################################
10475 14:01:31.712959
10476 14:01:31.973299 06380000 ################################################################
10477 14:01:31.973512
10478 14:01:32.238124 06400000 ################################################################
10479 14:01:32.238301
10480 14:01:32.534248 06480000 ################################################################
10481 14:01:32.534462
10482 14:01:32.821989 06500000 ################################################################
10483 14:01:32.822145
10484 14:01:33.104232 06580000 ################################################################
10485 14:01:33.104388
10486 14:01:33.390693 06600000 ################################################################
10487 14:01:33.390876
10488 14:01:33.684295 06680000 ################################################################
10489 14:01:33.684448
10490 14:01:33.960220 06700000 ################################################################
10491 14:01:33.960375
10492 14:01:34.238039 06780000 ################################################################
10493 14:01:34.238186
10494 14:01:34.441868 06800000 ############################################# done.
10495 14:01:34.442083
10496 14:01:34.445518 The bootfile was 109414518 bytes long.
10497 14:01:34.445656
10498 14:01:34.448500 Sending tftp read request... done.
10499 14:01:34.448639
10500 14:01:34.452162 Waiting for the transfer...
10501 14:01:34.452279
10502 14:01:34.452376 00000000 # done.
10503 14:01:34.452471
10504 14:01:34.461750 Command line loaded dynamically from TFTP file: 11588075/tftp-deploy-x8a14o6p/kernel/cmdline
10505 14:01:34.461883
10506 14:01:34.475444 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10507 14:01:34.475588
10508 14:01:34.475668 Loading FIT.
10509 14:01:34.475732
10510 14:01:34.478349 Image ramdisk-1 has 98320332 bytes.
10511 14:01:34.478434
10512 14:01:34.481859 Image fdt-1 has 47278 bytes.
10513 14:01:34.481948
10514 14:01:34.485037 Image kernel-1 has 11044874 bytes.
10515 14:01:34.485124
10516 14:01:34.495019 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10517 14:01:34.495151
10518 14:01:34.511503 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10519 14:01:34.511735
10520 14:01:34.515060 Choosing best match conf-1 for compat google,spherion-rev2.
10521 14:01:34.520680
10522 14:01:34.592460 Connected to device vid:did:rid of 1ae0:0028:00
10523 14:01:34.602403
10524 14:01:34.605169 tpm_get_response: command 0x17b, return code 0x0
10525 14:01:34.605304
10526 14:01:34.608503 ec_init: CrosEC protocol v3 supported (256, 248)
10527 14:01:34.612920
10528 14:01:34.616359 tpm_cleanup: add release locality here.
10529 14:01:34.616501
10530 14:01:34.616615 Shutting down all USB controllers.
10531 14:01:34.619376
10532 14:01:34.619494 Removing current net device
10533 14:01:34.619605
10534 14:01:34.625759 Exiting depthcharge with code 4 at timestamp: 100901716
10535 14:01:34.625902
10536 14:01:34.629262 LZMA decompressing kernel-1 to 0x821a6718
10537 14:01:34.629391
10538 14:01:34.632888 LZMA decompressing kernel-1 to 0x40000000
10539 14:01:36.020783
10540 14:01:36.021000 jumping to kernel
10541 14:01:36.021779 end: 2.2.4 bootloader-commands (duration 00:01:13) [common]
10542 14:01:36.021982 start: 2.2.5 auto-login-action (timeout 00:03:12) [common]
10543 14:01:36.022109 Setting prompt string to ['Linux version [0-9]']
10544 14:01:36.022229 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10545 14:01:36.022343 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10546 14:01:36.103145
10547 14:01:36.106522 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10548 14:01:36.110234 start: 2.2.5.1 login-action (timeout 00:03:12) [common]
10549 14:01:36.110387 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10550 14:01:36.110509 Setting prompt string to []
10551 14:01:36.110639 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10552 14:01:36.110761 Using line separator: #'\n'#
10553 14:01:36.110868 No login prompt set.
10554 14:01:36.110981 Parsing kernel messages
10555 14:01:36.111083 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10556 14:01:36.111273 [login-action] Waiting for messages, (timeout 00:03:12)
10557 14:01:36.129619 [ 0.000000] Linux version 6.1.54-cip6-rt3 (KernelCI@build-j53691-arm64-gcc-10-defconfig-arm64-chromebook-2d8w4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Sep 21 13:44:36 UTC 2023
10558 14:01:36.133211 [ 0.000000] random: crng init done
10559 14:01:36.139825 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10560 14:01:36.143008 [ 0.000000] efi: UEFI not found.
10561 14:01:36.150295 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10562 14:01:36.160032 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10563 14:01:36.166565 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10564 14:01:36.176415 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10565 14:01:36.183067 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10566 14:01:36.189282 [ 0.000000] printk: bootconsole [mtk8250] enabled
10567 14:01:36.196638 [ 0.000000] NUMA: No NUMA configuration found
10568 14:01:36.202469 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10569 14:01:36.206105 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10570 14:01:36.209263 [ 0.000000] Zone ranges:
10571 14:01:36.216104 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10572 14:01:36.219447 [ 0.000000] DMA32 empty
10573 14:01:36.225742 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10574 14:01:36.229186 [ 0.000000] Movable zone start for each node
10575 14:01:36.232315 [ 0.000000] Early memory node ranges
10576 14:01:36.238964 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10577 14:01:36.245487 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10578 14:01:36.252501 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10579 14:01:36.259366 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10580 14:01:36.265753 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10581 14:01:36.271878 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10582 14:01:36.327554 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10583 14:01:36.333947 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10584 14:01:36.341154 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10585 14:01:36.344083 [ 0.000000] psci: probing for conduit method from DT.
10586 14:01:36.350695 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10587 14:01:36.354239 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10588 14:01:36.360913 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10589 14:01:36.364098 [ 0.000000] psci: SMC Calling Convention v1.2
10590 14:01:36.370712 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10591 14:01:36.373756 [ 0.000000] Detected VIPT I-cache on CPU0
10592 14:01:36.381000 [ 0.000000] CPU features: detected: GIC system register CPU interface
10593 14:01:36.387270 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10594 14:01:36.393905 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10595 14:01:36.400572 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10596 14:01:36.407398 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10597 14:01:36.417495 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10598 14:01:36.420453 [ 0.000000] alternatives: applying boot alternatives
10599 14:01:36.423955 [ 0.000000] Fallback order for Node 0: 0
10600 14:01:36.433993 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10601 14:01:36.434085 [ 0.000000] Policy zone: Normal
10602 14:01:36.450424 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10603 14:01:36.460515 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10604 14:01:36.472078 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10605 14:01:36.481587 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10606 14:01:36.488631 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10607 14:01:36.491578 <6>[ 0.000000] software IO TLB: area num 8.
10608 14:01:36.548527 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10609 14:01:36.697430 <6>[ 0.000000] Memory: 7873408K/8385536K available (17984K kernel code, 4116K rwdata, 17472K rodata, 8448K init, 615K bss, 479360K reserved, 32768K cma-reserved)
10610 14:01:36.703987 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10611 14:01:36.710486 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10612 14:01:36.713790 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10613 14:01:36.720465 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10614 14:01:36.727304 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10615 14:01:36.730284 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10616 14:01:36.740546 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10617 14:01:36.746962 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10618 14:01:36.753704 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10619 14:01:36.760106 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10620 14:01:36.763615 <6>[ 0.000000] GICv3: 608 SPIs implemented
10621 14:01:36.766916 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10622 14:01:36.773386 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10623 14:01:36.776658 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10624 14:01:36.783414 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10625 14:01:36.796599 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10626 14:01:36.807279 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10627 14:01:36.816836 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10628 14:01:36.823679 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10629 14:01:36.837341 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10630 14:01:36.844293 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10631 14:01:36.850614 <6>[ 0.009186] Console: colour dummy device 80x25
10632 14:01:36.861003 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10633 14:01:36.863976 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10634 14:01:36.870259 <6>[ 0.029222] LSM: Security Framework initializing
10635 14:01:36.877006 <6>[ 0.034162] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10636 14:01:36.887011 <6>[ 0.042017] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10637 14:01:36.893793 <6>[ 0.051419] cblist_init_generic: Setting adjustable number of callback queues.
10638 14:01:36.900493 <6>[ 0.058860] cblist_init_generic: Setting shift to 3 and lim to 1.
10639 14:01:36.910334 <6>[ 0.065197] cblist_init_generic: Setting adjustable number of callback queues.
10640 14:01:36.913545 <6>[ 0.072671] cblist_init_generic: Setting shift to 3 and lim to 1.
10641 14:01:36.920057 <6>[ 0.079109] rcu: Hierarchical SRCU implementation.
10642 14:01:36.926678 <6>[ 0.079111] rcu: Max phase no-delay instances is 1000.
10643 14:01:36.934048 <6>[ 0.079135] printk: bootconsole [mtk8250] printing thread started
10644 14:01:36.940624 <6>[ 0.097428] EFI services will not be available.
10645 14:01:36.943461 <6>[ 0.097627] smp: Bringing up secondary CPUs ...
10646 14:01:36.946856 <6>[ 0.097936] Detected VIPT I-cache on CPU1
10647 14:01:36.953395 <6>[ 0.098005] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10648 14:01:36.960192 <6>[ 0.098034] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10649 14:01:36.972129 <6>[ 0.125892] Detected VIPT I-cache on CPU2
10650 14:01:36.978714 <6>[ 0.125942] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10651 14:01:36.985601 <6>[ 0.125959] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10652 14:01:36.991882 <6>[ 0.126217] Detected VIPT I-cache on CPU3
10653 14:01:36.998396 <6>[ 0.126266] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10654 14:01:37.005100 <6>[ 0.126280] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10655 14:01:37.008607 <6>[ 0.126591] CPU features: detected: Spectre-v4
10656 14:01:37.015191 <6>[ 0.126598] CPU features: detected: Spectre-BHB
10657 14:01:37.019232 <6>[ 0.126602] Detected PIPT I-cache on CPU4
10658 14:01:37.024881 <6>[ 0.126662] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10659 14:01:37.032191 <6>[ 0.126678] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10660 14:01:37.038506 <6>[ 0.126972] Detected PIPT I-cache on CPU5
10661 14:01:37.044861 <6>[ 0.127034] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10662 14:01:37.051905 <6>[ 0.127052] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10663 14:01:37.054891 <6>[ 0.127329] Detected PIPT I-cache on CPU6
10664 14:01:37.061652 <6>[ 0.127393] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10665 14:01:37.068511 <6>[ 0.127410] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10666 14:01:37.075180 <6>[ 0.127704] Detected PIPT I-cache on CPU7
10667 14:01:37.081427 <6>[ 0.127768] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10668 14:01:37.088730 <6>[ 0.127785] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10669 14:01:37.091579 <6>[ 0.127831] smp: Brought up 1 node, 8 CPUs
10670 14:01:37.098204 <6>[ 0.127836] SMP: Total of 8 processors activated.
10671 14:01:37.101662 <6>[ 0.127839] CPU features: detected: 32-bit EL0 Support
10672 14:01:37.111304 <6>[ 0.127841] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10673 14:01:37.118086 <6>[ 0.127843] CPU features: detected: Common not Private translations
10674 14:01:37.125142 <6>[ 0.127845] CPU features: detected: CRC32 instructions
10675 14:01:37.128112 <6>[ 0.127848] CPU features: detected: RCpc load-acquire (LDAPR)
10676 14:01:37.134926 <6>[ 0.127849] CPU features: detected: LSE atomic instructions
10677 14:01:37.141669 <6>[ 0.127851] CPU features: detected: Privileged Access Never
10678 14:01:37.144877 <6>[ 0.127853] CPU features: detected: RAS Extension Support
10679 14:01:37.154635 <6>[ 0.127855] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10680 14:01:37.158024 <6>[ 0.127920] CPU: All CPU(s) started at EL2
10681 14:01:37.164780 <6>[ 0.127922] alternatives: applying system-wide alternatives
10682 14:01:37.168103 <6>[ 0.141009] devtmpfs: initialized
10683 14:01:37.177877 <6>[ 0.147309] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10684 14:01:37.199125 ��YV�.]Y�Y�PF_INET protocol family
10685 14:01:37.205610 <6>[ 0.364<362] printk: console [ttyS0] printing thread started
10686 14:01:37.212347 6>[ <6>[ 0.364386] printk: console [ttyS0] enabled
10687 14:01:37.218907 0.228651] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10688 14:01:37.226535 <6>[ 0.364390] printk: bootconsole [mtk8250] disabled
10689 14:01:37.233157 <6>[ 0.382481] printk: bootconsole [mtk8250] printing thread stopped
10690 14:01:37.236358 <6>[ 0.383792] SuperH (H)SCI(F) driver initialized
10691 14:01:37.243015 <6>[ 0.384277] msm_serial: driver initialized
10692 14:01:37.249580 <6>[ 0.388892] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10693 14:01:37.259861 <6>[ 0.388921] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10694 14:01:37.266518 <6>[ 0.388950] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10695 14:01:37.285871 <6>[ 0.388980] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10696 14:01:37.294041 <6>[ 0.389001] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10697 14:01:37.294349 <6>[ 0.389029] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10698 14:01:37.310921 <6>[ 0.389057] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10699 14:01:37.311061 <6>[ 0.389170] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10700 14:01:37.321241 <6>[ 0.389199] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10701 14:01:37.321331 <6>[ 0.400282] loop: module loaded
10702 14:01:37.328381 <6>[ 0.402891] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10703 14:01:37.336502 <4>[ 0.419592] mtk-pmic-keys: Failed to locate of_node [id: -1]
10704 14:01:37.339476 <6>[ 0.420482] megasas: 07.719.03.00-rc1
10705 14:01:37.346435 <6>[ 0.432792] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10706 14:01:37.350027 <6>[ 0.432921] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10707 14:01:37.356333 <6>[ 0.444590] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10708 14:01:37.366386 <6>[ 0.498503] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10709 14:01:41.070231 <6>[ 4.226465] Freeing initrd memory: 96012K
10710 14:01:41.076899 <6>[ 4.232546] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10711 14:01:41.080129 <6>[ 4.237286] tun: Universal TUN/TAP device driver, 1.6
10712 14:01:41.083097 <6>[ 4.238075] thunder_xcv, ver 1.0
10713 14:01:41.086771 <6>[ 4.238091] thunder_bgx, ver 1.0
10714 14:01:41.090241 <6>[ 4.238107] nicpf, ver 1.0
10715 14:01:41.099736 <6>[ 4.239149] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10716 14:01:41.103242 <6>[ 4.239152] hns3: Copyright (c) 2017 Huawei Corporation.
10717 14:01:41.106422 <6>[ 4.239179] hclge is initializing
10718 14:01:41.113228 <6>[ 4.239200] e1000: Intel(R) PRO/1000 Network Driver
10719 14:01:41.119568 <6>[ 4.239202] e1000: Copyright (c) 1999-2006 Intel Corporation.
10720 14:01:41.123568 <6>[ 4.239221] e1000e: Intel(R) PRO/1000 Network Driver
10721 14:01:41.130381 <6>[ 4.239223] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10722 14:01:41.134317 <6>[ 4.239237] igb: Intel(R) Gigabit Ethernet Network Driver
10723 14:01:41.141431 <6>[ 4.239239] igb: Copyright (c) 2007-2014 Intel Corporation.
10724 14:01:41.147930 <6>[ 4.239252] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10725 14:01:41.154763 <6>[ 4.239254] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10726 14:01:41.158409 <6>[ 4.239554] sky2: driver version 1.30
10727 14:01:41.164613 <6>[ 4.240625] VFIO - User Level meta-driver version: 0.3
10728 14:01:41.168272 <6>[ 4.243475] usbcore: registered new interface driver usb-storage
10729 14:01:41.174675 <6>[ 4.243654] usbcore: registered new device driver onboard-usb-hub
10730 14:01:41.181345 <6>[ 4.246412] mt6397-rtc mt6359-rtc: registered as rtc0
10731 14:01:41.191178 <6>[ 4.246564] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-21T14:00:14 UTC (1695304814)
10732 14:01:41.194492 <6>[ 4.247181] i2c_dev: i2c /dev entries driver
10733 14:01:41.201100 <6>[ 4.254315] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10734 14:01:41.207612 <6>[ 4.270324] cpu cpu0: EM: created perf domain
10735 14:01:41.210947 <6>[ 4.270642] cpu cpu4: EM: created perf domain
10736 14:01:41.217709 <6>[ 4.271955] sdhci: Secure Digital Host Controller Interface driver
10737 14:01:41.224132 <6>[ 4.271956] sdhci: Copyright(c) Pierre Ossman
10738 14:01:41.228002 <6>[ 4.272317] Synopsys Designware Multimedia Card Interface Driver
10739 14:01:41.234349 <6>[ 4.272677] sdhci-pltfm: SDHCI platform and OF driver helper
10740 14:01:41.237334 <6>[ 4.277220] mmc0: CQHCI version 5.10
10741 14:01:41.244496 <6>[ 4.283083] ledtrig-cpu: registered to indicate activity on CPUs
10742 14:01:41.251044 <6>[ 4.283888] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10743 14:01:41.257863 <6>[ 4.284161] usbcore: registered new interface driver usbhid
10744 14:01:41.260940 <6>[ 4.284163] usbhid: USB HID core driver
10745 14:01:41.267335 <6>[ 4.284287] spi_master spi0: will run message pump with realtime priority
10746 14:01:41.280505 <6>[ 4.314754] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10747 14:01:41.294083 <6>[ 4.317905] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10748 14:01:41.300651 <6>[ 4.319024] cros-ec-spi spi0.0: Chrome EC device registered
10749 14:01:41.310312 <6>[ 4.331585] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10750 14:01:41.313826 <6>[ 4.332565] NET: Registered PF_PACKET protocol family
10751 14:01:41.320236 <6>[ 4.332637] 9pnet: Installing 9P2000 support
10752 14:01:41.323797 <5>[ 4.332669] Key type dns_resolver registered
10753 14:01:41.326875 <6>[ 4.333033] registered taskstats version 1
10754 14:01:41.333519 <5>[ 4.333047] Loading compiled-in X.509 certificates
10755 14:01:41.343817 <4>[ 4.349034] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10756 14:01:41.353642 <4>[ 4.349174] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10757 14:01:41.359821 <3>[ 4.349188] debugfs: File 'uA_load' in directory '/' already present!
10758 14:01:41.366465 <3>[ 4.349196] debugfs: File 'min_uV' in directory '/' already present!
10759 14:01:41.373171 <3>[ 4.349199] debugfs: File 'max_uV' in directory '/' already present!
10760 14:01:41.383257 <3>[ 4.349202] debugfs: File 'constraint_flags' in directory '/' already present!
10761 14:01:41.389708 <3>[ 4.351038] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10762 14:01:41.396309 <6>[ 4.357861] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10763 14:01:41.403469 <6>[ 4.358508] xhci-mtk 11200000.usb: xHCI Host Controller
10764 14:01:41.410068 <6>[ 4.358527] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10765 14:01:41.419517 <6>[ 4.358796] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10766 14:01:41.426204 <6>[ 4.358866] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10767 14:01:41.429813 <6>[ 4.358974] xhci-mtk 11200000.usb: xHCI Host Controller
10768 14:01:41.439409 <6>[ 4.358989] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10769 14:01:41.446095 <6>[ 4.359003] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10770 14:01:41.449645 <6>[ 4.359781] hub 1-0:1.0: USB hub found
10771 14:01:41.452918 <6>[ 4.359844] hub 1-0:1.0: 1 port detected
10772 14:01:41.463185 <6>[ 4.360261] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10773 14:01:41.466280 <6>[ 4.360935] hub 2-0:1.0: USB hub found
10774 14:01:41.469310 <6>[ 4.360995] hub 2-0:1.0: 1 port detected
10775 14:01:41.476066 <6>[ 4.365227] mtk-msdc 11f70000.mmc: Got CD GPIO
10776 14:01:41.479626 <6>[ 4.371823] mmc0: Command Queue Engine enabled
10777 14:01:41.486360 <6>[ 4.371836] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10778 14:01:41.489657 <6>[ 4.372632] mmcblk0: mmc0:0001 DA4128 116 GiB
10779 14:01:41.495991 <6>[ 4.376212] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10780 14:01:41.502473 <6>[ 4.377529] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10781 14:01:41.506265 <6>[ 4.378339] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10782 14:01:41.512656 <6>[ 4.379143] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10783 14:01:41.522872 <6>[ 4.382333] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10784 14:01:41.529663 <6>[ 4.382340] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10785 14:01:41.539356 <4>[ 4.382506] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10786 14:01:41.546188 <6>[ 4.383139] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10787 14:01:41.555552 <6>[ 4.383142] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10788 14:01:41.562592 <6>[ 4.383257] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10789 14:01:41.569000 <6>[ 4.383271] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10790 14:01:41.579438 <6>[ 4.383275] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10791 14:01:41.586035 <6>[ 4.383281] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10792 14:01:41.595565 <6>[ 4.384784] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10793 14:01:41.605349 <6>[ 4.384802] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10794 14:01:41.612353 <6>[ 4.384808] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10795 14:01:41.622117 <6>[ 4.384814] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10796 14:01:41.628867 <6>[ 4.384820] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10797 14:01:41.638479 <6>[ 4.384827] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10798 14:01:41.645136 <6>[ 4.384833] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10799 14:01:41.655388 <6>[ 4.384839] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10800 14:01:41.661947 <6>[ 4.384845] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10801 14:01:41.671640 <6>[ 4.384851] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10802 14:01:41.678237 <6>[ 4.384857] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10803 14:01:41.688083 <6>[ 4.384863] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10804 14:01:41.694760 <6>[ 4.384869] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10805 14:01:41.704916 <6>[ 4.384875] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10806 14:01:41.711510 <6>[ 4.384880] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10807 14:01:41.717933 <6>[ 4.385414] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10808 14:01:41.724948 <6>[ 4.386392] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10809 14:01:41.731533 <6>[ 4.386946] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10810 14:01:41.737866 <6>[ 4.387563] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10811 14:01:41.744789 <6>[ 4.388201] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10812 14:01:41.754771 <6>[ 4.388396] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10813 14:01:41.764619 <6>[ 4.388408] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10814 14:01:41.774456 <6>[ 4.388413] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10815 14:01:41.781252 <6>[ 4.388419] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10816 14:01:41.791175 <6>[ 4.388429] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10817 14:01:41.801185 <6>[ 4.388436] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10818 14:01:41.810671 <6>[ 4.388443] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10819 14:01:41.821001 <6>[ 4.388450] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10820 14:01:41.827723 <6>[ 4.388454] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10821 14:01:41.837526 <6>[ 4.388461] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10822 14:01:41.850309 <6>[ 4.388465] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10823 14:01:41.857241 <6>[ 4.389056] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10824 14:01:41.864043 <6>[ 4.741816] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10825 14:01:41.867326 <6>[ 4.768288] hub 2-1:1.0: USB hub found
10826 14:01:41.873538 <6>[ 4.768595] hub 2-1:1.0: 3 ports detected
10827 14:01:41.880508 <6>[ 4.897562] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10828 14:01:41.893920 <6>[ 5.050041] hub 1-1:1.0: USB hub found
10829 14:01:41.896954 <6>[ 5.050391] hub 1-1:1.0: 4 ports detected
10830 14:01:41.973448 <6>[ 5.125886] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10831 14:01:42.209552 <6>[ 5.361688] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10832 14:01:42.330210 <6>[ 5.489341] hub 1-1.4:1.0: USB hub found
10833 14:01:42.333355 <6>[ 5.489794] hub 1-1.4:1.0: 2 ports detected
10834 14:01:42.625327 <6>[ 5.777687] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10835 14:01:42.809169 <6>[ 5.961689] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10836 14:01:53.513841 <6>[ 16.674721] ALSA device list:
10837 14:01:53.520605 <6>[ 16.674744] No soundcards found.
10838 14:01:53.523609 <6>[ 16.679235] Freeing unused kernel memory: 8448K
10839 14:01:53.527014 <6>[ 16.679403] Run /init as init process
10840 14:01:53.564560 <6>[ 16.721684] NET: Registered PF_INET6 protocol family
10841 14:01:53.567875 <6>[ 16.722764] Segment Routing with IPv6
10842 14:01:53.571154 <6>[ 16.722782] In-situ OAM (IOAM) with IPv6
10843 14:01:53.575669
10844 14:01:53.598930 Welcome to [1mDebian GNU/Linux <30>[ 16.738996] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10845 14:01:53.605337 <30>[ 16.739396] systemd[1]: Detected architecture arm64.
10846 14:01:53.605452 11 (bullseye)[0m!
10847 14:01:53.608769
10848 14:01:53.624879 <30>[ 16.781644] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10849 14:01:53.740145 <30>[ 16.894456] systemd[1]: Queued start job for default target Graphical Interface.
10850 14:01:53.781368 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 16.938296] systemd[1]: Created slice system-getty.slice.
10851 14:01:53.784759 m-getty.slice[0m.
10852 14:01:53.808166 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 16.962161] systemd[1]: Created slice system-modprobe.slice.
10853 14:01:53.808296 m-modprobe.slice[0m.
10854 14:01:53.832511 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 16.986428] systemd[1]: Created slice system-serial\x2dgetty.slice.
10855 14:01:53.835457 m-serial\x2dgetty.slice[0m.
10856 14:01:53.856466 [[0;32m OK [0m] Created slice [0;1;39mUser <30>[ 17.010538] systemd[1]: Created slice User and Session Slice.
10857 14:01:53.856582 and Session Slice[0m.
10858 14:01:53.881049 [[0;32m OK [0m] Started [0;<30>[ 17.034470] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10859 14:01:53.884254 1;39mDispatch Password …ts to Console Directory Watch[0m.
10860 14:01:53.908342 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 17.062424] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10861 14:01:53.911584 sword R…uests to Wall Directory Watch[0m.
10862 14:01:53.939771 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 17.090172] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10863 14:01:53.946604 <30>[ 17.090422] systemd[1]: Reached target Local Encrypted Volumes.
10864 14:01:53.949782 l Encrypted Volumes[0m.
10865 14:01:53.968371 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 17.125780] systemd[1]: Reached target Paths.
10866 14:01:53.968484 s[0m.
10867 14:01:53.991709 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 17.145670] systemd[1]: Reached target Remote File Systems.
10868 14:01:53.991829 te File Systems[0m.
10869 14:01:54.013071 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 17.170062] systemd[1]: Reached target Slices.
10870 14:01:54.013184 es[0m.
10871 14:01:54.032505 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 17.189710] systemd[1]: Reached target Swap.
10872 14:01:54.032632 [0m.
10873 14:01:54.056538 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 17.210188] systemd[1]: Listening on initctl Compatibility Named Pipe.
10874 14:01:54.059780 l Compatibility Named Pipe[0m.
10875 14:01:54.066713 <30>[ 17.225346] systemd[1]: Listening on Journal Audit Socket.
10876 14:01:54.072709 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10877 14:01:54.089500 [[0;32m OK [0m] Listening on<30>[ 17.246852] systemd[1]: Listening on Journal Socket (/dev/log).
10878 14:01:54.092803 [0;1;39mJournal Socket (/dev/log)[0m.
10879 14:01:54.113726 [[0;32m OK [0m] Listening on<30>[ 17.270934] systemd[1]: Listening on Journal Socket.
10880 14:01:54.116945 [0;1;39mJournal Socket[0m.
10881 14:01:54.133102 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 17.290243] systemd[1]: Listening on udev Control Socket.
10882 14:01:54.136123 ontrol Socket[0m.
10883 14:01:54.157428 [[0;32m OK [0m] Listening on<30>[ 17.314722] systemd[1]: Listening on udev Kernel Socket.
10884 14:01:54.160813 [0;1;39mudev Kernel Socket[0m.
10885 14:01:54.219918 Mounting [0;1;39mHuge Pages File Syste<30>[ 17.373800] systemd[1]: Mounting Huge Pages File System...
10886 14:01:54.220057 m[0m...
10887 14:01:54.243557 Mounting [0;1;39mPOSIX Message Queue F<30>[ 17.397567] systemd[1]: Mounting POSIX Message Queue File System...
10888 14:01:54.243692 ile System[0m...
10889 14:01:54.271567 Mounting [0;1;39mKernel Debug File Sys<30>[ 17.425655] systemd[1]: Mounting Kernel Debug File System...
10890 14:01:54.271757 tem[0m...
10891 14:01:54.292284 <30>[ 17.446097] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10892 14:01:54.305516 Starting [0;1;39mCreate list of st…o<30>[ 17.450388] systemd[1]: Starting Create list of static device nodes for the current kernel...
10893 14:01:54.308265 des for the current kernel[0m...
10894 14:01:54.335791 Starting [0;1;39mLoad Kernel Module co<30>[ 17.489698] systemd[1]: Starting Load Kernel Module configfs...
10895 14:01:54.335931 nfigfs[0m...
10896 14:01:54.359916 Starting [0;1;39mLoad Kernel Module dr<30>[ 17.513866] systemd[1]: Starting Load Kernel Module drm...
10897 14:01:54.360088 m[0m...
10898 14:01:54.380010 <30>[ 17.533734] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10899 14:01:54.386603 <30>[ 17.539051] systemd[1]: Starting Journal Service...
10900 14:01:54.389894 Starting [0;1;39mJournal Service[0m...
10901 14:01:54.410787 Startin<30>[ 17.568193] systemd[1]: Starting Load Kernel Modules...
10902 14:01:54.414232 g [0;1;39mLoad Kernel Modules[0m...
10903 14:01:54.438259 Starting [0;1;39mRemou<30>[ 17.594967] systemd[1]: Starting Remount Root and Kernel File Systems...
10904 14:01:54.444767 nt Root and Kernel File Systems[0m...
10905 14:01:54.467954 Starting [0;1;39mColdplug All udev Dev<30>[ 17.621984] systemd[1]: Starting Coldplug All udev Devices...
10906 14:01:54.468098 ices[0m...
10907 14:01:54.484427 [[0;32m OK [<30>[ 17.644916] systemd[1]: Started Journal Service.
10908 14:01:54.491074 0m] Started [0;1;39mJournal Service[0m.
10909 14:01:54.508227 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10910 14:01:54.526470 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10911 14:01:54.542203 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10912 14:01:54.561900 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10913 14:01:54.582699 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10914 14:01:54.603261 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10915 14:01:54.627073 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10916 14:01:54.651192 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10917 14:01:54.669103 See 'systemctl status systemd-remount-fs.service' for details.
10918 14:01:54.725445 Mounting [0;1;39mKernel Configuration File System[0m...
10919 14:01:54.745252 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10920 14:01:54.765561 Starting [0;1;39mLoad/Save Random Seed[0m...
10921 14:01:54.784103 <46>[ 17.928141] systemd-journald[190]: Received client request to flush runtime journal.
10922 14:01:54.790816 Starting [0;1;39mApply Kernel Variables[0m...
10923 14:01:54.809257 Starting [0;1;39mCreate System Users[0m...
10924 14:01:54.829696 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10925 14:01:54.846507 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10926 14:01:54.866125 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10927 14:01:54.878454 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10928 14:01:54.894958 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10929 14:01:54.910299 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10930 14:01:54.961546 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10931 14:01:54.983180 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10932 14:01:55.001286 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10933 14:01:55.016918 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10934 14:01:55.065506 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10935 14:01:55.091277 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10936 14:01:55.112401 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10937 14:01:55.132611 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10938 14:01:55.179848 Starting [0;1;39mNetwork Time Synchronization[0m...
10939 14:01:55.198841 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10940 14:01:55.241943 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10941 14:01:55.268195 <6>[ 18.422339] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10942 14:01:55.288211 <6>[ 18.441665] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10943 14:01:55.294518 <6>[ 18.441759] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10944 14:01:55.304380 <6>[ 18.441770] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10945 14:01:55.316809 <6>[ 18.475886] remoteproc remoteproc0: scp is available
10946 14:01:55.327045 Starting [0;1;39mLoad/<6>[ 18.476237] remoteproc remoteproc0: powering up scp
10947 14:01:55.333403 Save Screen …o<6>[ 18.476255] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10948 14:01:55.343111 f leds:white:kbd<6>[ 18.476355] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10949 14:01:55.346504 <6>[ 18.487291] usbcore: registered new interface driver r8152
10950 14:01:55.356800 <3>[ 18.513762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10951 14:01:55.363305 <3>[ 18.513781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10952 14:01:55.372882 <3>[ 18.513790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10953 14:01:55.373079 _backlight[0m...
10954 14:01:55.383792 <3>[ 18.539953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10955 14:01:55.390538 <3>[ 18.539993] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10956 14:01:55.400363 <3>[ 18.539998] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10957 14:01:55.407047 <3>[ 18.540005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10958 14:01:55.417294 <3>[ 18.540009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10959 14:01:55.426985 [[0;32m OK [0m] Started [0;1;39mNetwork Tim<3>[ 18.549893] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10960 14:01:55.437170 e Synchronizatio<6>[ 18.553946] usbcore: registered new interface driver cdc_ether
10961 14:01:55.437357 n[0m.
10962 14:01:55.443510 <3>[ 18.560041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10963 14:01:55.454110 <3>[ 18.560067] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10964 14:01:55.461004 <3>[ 18.560075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10965 14:01:55.467662 <6>[ 18.567343] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10966 14:01:55.474633 <6>[ 18.567343] usbcore: registered new interface driver r8153_ecm
10967 14:01:55.480913 [[0;32m OK [<6>[ 18.567352] pci_bus 0000:00: root bus resource [bus 00-ff]
10968 14:01:55.491291 0m] Finished [0<6>[ 18.567357] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10969 14:01:55.501482 ;1;39mLoad/Save <6>[ 18.567360] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10970 14:01:55.508318 Screen …s of l<6>[ 18.567391] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10971 14:01:55.518262 <6>[ 18.567404] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10972 14:01:55.521180 <6>[ 18.567476] pci 0000:00:00.0: supports D1 D2
10973 14:01:55.527705 <6>[ 18.567478] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10974 14:01:55.534317 <6>[ 18.568426] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10975 14:01:55.545002 eds:white:kbd_ba<3>[ 18.568886] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10976 14:01:55.545190 cklight[0m.
10977 14:01:55.555153 <3>[ 18.568905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10978 14:01:55.561483 <3>[ 18.568915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10979 14:01:55.571725 <3>[ 18.568927] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10980 14:01:55.581340 <3>[ 18.568935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10981 14:01:55.588316 [[0;32m OK [<4>[ 18.569161] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10982 14:01:55.598305 0m] Found device<3>[ 18.569659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10983 14:01:55.604823 <4>[ 18.570733] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10984 14:01:55.612618 <6>[ 18.570793] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10985 14:01:55.619129 [0;1;39m/dev/t<6>[ 18.570835] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10986 14:01:55.628709 <6>[ 18.570861] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10987 14:01:55.636473 <6>[ 18.570880] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10988 14:01:55.640184 <6>[ 18.571027] pci 0000:01:00.0: supports D1 D2
10989 14:01:55.646441 <6>[ 18.571031] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10990 14:01:55.652914 <6>[ 18.573786] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10991 14:01:55.656340 tyS0[0m.
10992 14:01:55.662840 <6>[ 18.580494] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10993 14:01:55.669731 <6>[ 18.602631] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10994 14:01:55.679730 <6>[ 18.602684] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10995 14:01:55.683046 <6>[ 18.602691] remoteproc remoteproc0: remote processor scp is now up
10996 14:01:55.693200 <4>[ 18.605003] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10997 14:01:55.696684 <4>[ 18.605003] Fallback method does not support PEC.
10998 14:01:55.710172 [[0;32m OK [<3>[ 18.624073] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 14:01:55.713161 0m] Finished [0<6>[ 18.624684] mc: Linux media interface: v0.10
11000 14:01:55.720469 <6>[ 18.626179] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11001 14:01:55.730278 ;1;39mUpdate UTM<6>[ 18.626229] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11002 14:01:55.737473 <6>[ 18.626232] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11003 14:01:55.747942 P about System B<6>[ 18.626244] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11004 14:01:55.754466 <6>[ 18.626257] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11005 14:01:55.765794 <6>[ 18.626269] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11006 14:01:55.772145 oot/Shutdown[0m<6>[ 18.626283] pci 0000:00:00.0: PCI bridge to [bus 01]
11007 14:01:55.772267 .
11008 14:01:55.778508 <6>[ 18.626289] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11009 14:01:55.785589 <6>[ 18.642376] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11010 14:01:55.795953 <4>[ 18.649217] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11011 14:01:55.802106 <4>[ 18.649231] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11012 14:01:55.813060 <3>[ 18.658397] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11013 14:01:55.816290 <6>[ 18.673296] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11014 14:01:55.822972 <6>[ 18.678360] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11015 14:01:55.833654 <6>[ 18.679975] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11016 14:01:55.843812 <6>[ 18.694504] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11017 14:01:55.849960 <6>[ 18.695871] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11018 14:01:55.859989 <3>[ 18.710895] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11019 14:01:55.866987 <6>[ 18.730228] videodev: Linux video capture interface: v2.00
11020 14:01:55.869821 <6>[ 18.730393] r8152 2-1.3:1.0 eth0: v1.12.13
11021 14:01:55.879576 <3>[ 18.775216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 14:01:55.883215 <6>[ 18.795212] Bluetooth: Core ver 2.22
11023 14:01:55.889788 <6>[ 18.795344] NET: Registered PF_BLUETOOTH protocol family
11024 14:01:55.896546 <6>[ 18.795347] Bluetooth: HCI device and connection manager initialized
11025 14:01:55.899885 <6>[ 18.795366] Bluetooth: HCI socket layer initialized
11026 14:01:55.906744 <6>[ 18.795372] Bluetooth: L2CAP socket layer initialized
11027 14:01:55.910086 <6>[ 18.795382] Bluetooth: SCO socket layer initialized
11028 14:01:55.919521 <3>[ 18.801973] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11029 14:01:55.929313 <3>[ 18.831991] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11030 14:01:55.935989 <6>[ 18.866146] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11031 14:01:55.942770 <3>[ 18.870055] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11032 14:01:55.953181 <3>[ 18.872562] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
11033 14:01:55.965969 <6>[ 18.881128] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11034 14:01:55.969067 <6>[ 18.881470] usbcore: registered new interface driver uvcvideo
11035 14:01:55.975818 <6>[ 18.882172] usbcore: registered new interface driver btusb
11036 14:01:55.985919 <5>[ 18.883317] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11037 14:01:55.992417 <6>[ 18.888069] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11038 14:01:56.002452 <4>[ 18.888519] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11039 14:01:56.009226 <3>[ 18.888541] Bluetooth: hci0: Failed to load firmware file (-2)
11040 14:01:56.016121 <3>[ 18.888547] Bluetooth: hci0: Failed to set up firmware (-2)
11041 14:01:56.025732 <4>[ 18.888556] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11042 14:01:56.032307 <6>[ 18.890474] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11043 14:01:56.039044 <5>[ 18.900565] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11044 14:01:56.045381 <6>[ 18.907610] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11045 14:01:56.052082 <6>[ 18.908866] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11046 14:01:56.062125 <3>[ 18.909473] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11047 14:01:56.069011 <3>[ 18.910433] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
11048 14:01:56.078851 <4>[ 19.223116] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11049 14:01:56.085528 <6>[ 19.223132] cfg80211: failed to load regulatory.db
11050 14:01:56.088767 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11051 14:01:56.105515 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11052 14:01:56.123830 <6>[ 19.280520] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11053 14:01:56.130844 <6>[ 19.280631] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11054 14:01:56.140291 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.<6>[ 19.297587] mt7921e 0000:01:00.0: ASIC revision: 79610010
11055 14:01:56.143686
11056 14:01:56.157354 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11057 14:01:56.172896 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11058 14:01:56.192752 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11059 14:01:56.204436 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11060 14:01:56.228364 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11061 14:01:56.243413 <4>[ 19.393474] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11062 14:01:56.250034 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11063 14:01:56.265025 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11064 14:01:56.284539 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11065 14:01:56.344014 [[0;32m OK [0m] Started [0;<4>[ 19.497171] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11066 14:01:56.346886 1;39mD-Bus System Message Bus[0m.
11067 14:01:56.383849 Starting [0;1;39mUser Login Management[0m...
11068 14:01:56.399384 Starting [0;1;39mPermit User Sessions[0m...
11069 14:01:56.422276 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11070 14:01:56.450726 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11071 14:01:56.460409 <4>[ 19.609768] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11072 14:01:56.473047 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11073 14:01:56.483840 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11074 14:01:56.501293 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11075 14:01:56.518493 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11076 14:01:56.537162 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11077 14:01:56.556435 [[0;32m OK [0m] Reached targ<4>[ 19.708377] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11078 14:01:56.560204 et [0;1;39mMulti-User System[0m.
11079 14:01:56.577346 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11080 14:01:56.634962 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11081 14:01:56.662972 <4>[ 19.816728] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11082 14:01:56.681276 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11083 14:01:56.723713
11084 14:01:56.723874
11085 14:01:56.726372 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11086 14:01:56.726461
11087 14:01:56.729740 debian-bullseye-arm64 login: root (automatic login)
11088 14:01:56.729837
11089 14:01:56.729925
11090 14:01:56.776979 Linux debian-bullseye-arm64 6.1.54-cip6-rt3 #1 SMP PREEMPT Thu S<4>[ 19.925814] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11091 14:01:56.777133 ep 21 13:44:36 UTC 2023 aarch64
11092 14:01:56.780709
11093 14:01:56.786835 The programs included with the Debian GNU/Linux system are free software;
11094 14:01:56.790384 the exact distribution terms for each program are described in the
11095 14:01:56.797309 individual files in /usr/share/doc/*/copyright.
11096 14:01:56.797427
11097 14:01:56.799929 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11098 14:01:56.803299 permitted by applicable law.
11099 14:01:56.803659 Matched prompt #10: / #
11101 14:01:56.803893 Setting prompt string to ['/ #']
11102 14:01:56.804005 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11104 14:01:56.804235 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11105 14:01:56.804340 start: 2.2.6 expect-shell-connection (timeout 00:02:51) [common]
11106 14:01:56.804444 Setting prompt string to ['/ #']
11107 14:01:56.804540 Forcing a shell prompt, looking for ['/ #']
11109 14:01:56.854824 / #
11110 14:01:56.855022 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11111 14:01:56.855130 Waiting using forced prompt support (timeout 00:02:30)
11112 14:01:56.860383
11113 14:01:56.864657 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11114 14:01:56.864787 start: 2.2.7 export-device-env (timeout 00:02:51) [common]
11115 14:01:56.864904 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11116 14:01:56.865014 end: 2.2 depthcharge-retry (duration 00:02:09) [common]
11117 14:01:56.865120 end: 2 depthcharge-action (duration 00:02:09) [common]
11118 14:01:56.865225 start: 3 lava-test-retry (timeout 00:05:00) [common]
11119 14:01:56.865335 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11120 14:01:56.865450 Using namespace: common
11122 14:01:56.965870 / # #
11123 14:01:56.966055 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11124 14:01:56.966199 <4>[ 20.036436] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11125 14:01:56.971530 #
11126 14:01:56.976410 Using /lava-11588075
11128 14:01:57.076845 / # export SHELL=/bin/sh
11129 14:01:57.077093 <4>[ 20.144551] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11130 14:01:57.082092 export SHELL=/bin/sh
11132 14:01:57.186195 / # . /lava-11588075/environment
11133 14:01:57.186466 <4>[ 20.251903] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11134 14:01:57.192101 . /lava-11588075/environment
11136 14:01:57.292723 / # /lava-11588075/bin/lava-test-runner /lava-11588075/0
11137 14:01:57.292931 Test shell timeout: 10s (minimum of the action and connection timeout)
11138 14:01:57.293333 <4>[ 20.360110] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11139 14:01:57.298527 /lava-11588075/bin/lava-test-runner /lava-11588075/0
11140 14:01:57.339794 <3>[ 20.466168] mt7921e 0000:01:00.0: hardware init failed
11141 14:01:57.339956 + export TESTRUN_ID=0_sleep
11142 14:01:57.340052 + cd /lava-11588075/0/tests/0_sleep
11143 14:01:57.340137 + cat uuid
11144 14:01:57.340219 + UUID=11588075_1.5.2.3.1
11145 14:01:57.340490 + set +x
11146 14:01:57.340598 <LAVA_SIGNAL_STARTRUN 0_sleep 11588075_1.5.2.3.1>
11147 14:01:57.340700 + ./config/lava/sleep/sleep.sh mem freeze
11148 14:01:57.340987 Received signal: <STARTRUN> 0_sleep 11588075_1.5.2.3.1
11149 14:01:57.341094 Starting test lava.0_sleep (11588075_1.5.2.3.1)
11150 14:01:57.341199 Skipping test definition patterns.
11151 14:01:57.341345 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11153 14:01:57.343220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11154 14:01:57.346185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11155 14:01:57.346446 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11157 14:01:57.349685 rtcwake: assuming RTC uses UTC ...
11158 14:01:57.356307 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 14:00:37 2023
11159 14:01:57.364143 <6>[ 20.521250] PM: suspend entry (deep)
11160 14:01:57.368033 <6>[ 20.521319] Filesystems sync: 0.000 seconds
11161 14:01:57.371182 <6>[ 20.524286] Freezing user space processes
11162 14:01:57.377993 <6>[ 20.526176] Freezing user space processes completed (elapsed 0.001 seconds)
11163 14:01:57.380757 <6>[ 20.526187] OOM killer disabled.
11164 14:01:57.387439 <6>[ 20.526190] Freezing remaining freezable tasks
11165 14:01:57.394074 <6>[ 20.527538] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11166 14:01:57.400409 <6>[ 20.527548] printk: Suspending console(s) (use no_console_suspend to debug)
11167 14:02:00.875919 <3>[ 23.809874] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11168 14:02:00.886082 <3>[ 23.809924] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11169 14:02:00.896216 <3>[ 23.809965] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11170 14:02:00.902989 <3>[ 23.810007] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11171 14:02:00.909419 <3>[ 23.810234] PM: Some devices failed to suspend, or early wake event detected
11172 14:02:00.916218 <4>[ 23.825531] typec port0-partner: PM: parent port0 should not be sleeping
11173 14:02:00.984308 <6>[ 24.141798] OOM killer enabled.
11174 14:02:00.986975 <6>[ 24.141810] Restarting tasks ... done.
11175 14:02:00.990572 <5>[ 24.145970] random: crng reseeded on system resumption
11176 14:02:00.993793 rtcwake: write error
11177 14:02:00.997018 <6>[ 24.158386] PM: suspend exit
11178 14:02:01.003933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11179 14:02:01.004285 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11181 14:02:01.007291 rtcwake: assuming RTC uses UTC ...
11182 14:02:01.013731 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 14:00:40 2023
11183 14:02:01.028063 <6>[ 24.187285] PM: suspend entry (deep)
11184 14:02:01.031437 <6>[ 24.187329] Filesystems sync: 0.000 seconds
11185 14:02:01.034715 <6>[ 24.187961] Freezing user space processes
11186 14:02:01.041165 <6>[ 24.189528] Freezing user space processes completed (elapsed 0.001 seconds)
11187 14:02:01.044730 <6>[ 24.189534] OOM killer disabled.
11188 14:02:01.051397 <6>[ 24.189536] Freezing remaining freezable tasks
11189 14:02:01.058544 <6>[ 24.190726] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11190 14:02:01.064695 <6>[ 24.190730] printk: Suspending console(s) (use no_console_suspend to debug)
11191 14:02:04.459959 <3>[ 27.393706] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11192 14:02:04.469634 <3>[ 27.393730] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11193 14:02:04.479809 <3>[ 27.393760] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11194 14:02:04.486509 <3>[ 27.393791] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11195 14:02:04.493247 <3>[ 27.394223] PM: Some devices failed to suspend, or early wake event detected
11196 14:02:04.564811 <6>[ 27.725772] OOM killer enabled.
11197 14:02:04.570906 <6>[ 27.725784] Restarting tasks ... done.
11198 14:02:04.574423 <5>[ 27.728483] random: crng reseeded on system resumption
11199 14:02:04.578122 rtcwake: write error
11200 14:02:04.581389 <6>[ 27.742448] PM: suspend exit
11201 14:02:04.587829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11202 14:02:04.588099 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11204 14:02:04.591215 rtcwake: assuming RTC uses UTC ...
11205 14:02:04.597445 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 14:00:44 2023
11206 14:02:04.611403 <6>[ 27.771685] PM: suspend entry (deep)
11207 14:02:04.614850 <6>[ 27.771733] Filesystems sync: 0.000 seconds
11208 14:02:04.618012 <6>[ 27.772356] Freezing user space processes
11209 14:02:04.625580 <6>[ 27.773554] Freezing user space processes completed (elapsed 0.001 seconds)
11210 14:02:04.628706 <6>[ 27.773561] OOM killer disabled.
11211 14:02:04.635042 <6>[ 27.773562] Freezing remaining freezable tasks
11212 14:02:04.641835 <6>[ 27.774978] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11213 14:02:04.648219 <6>[ 27.774988] printk: Suspending console(s) (use no_console_suspend to debug)
11214 14:02:08.043080 <3>[ 30.977718] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11215 14:02:08.053298 <3>[ 30.977743] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11216 14:02:08.063524 <3>[ 30.977778] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11217 14:02:08.069596 <3>[ 30.977812] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11218 14:02:08.076207 <3>[ 30.978160] PM: Some devices failed to suspend, or early wake event detected
11219 14:02:08.148257 <6>[ 31.309792] OOM killer enabled.
11220 14:02:08.154545 <6>[ 31.309803] Restarting tasks ... done.
11221 14:02:08.158051 <5>[ 31.311998] random: crng reseeded on system resumption
11222 14:02:08.161523 rtcwake: write error
11223 14:02:08.164880 <6>[ 31.326534] PM: suspend exit
11224 14:02:08.171533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11225 14:02:08.171794 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11227 14:02:08.174738 rtcwake: assuming RTC uses UTC ...
11228 14:02:08.181464 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 14:00:47 2023
11229 14:02:08.195425 <6>[ 31.355265] PM: suspend entry (deep)
11230 14:02:08.198460 <6>[ 31.355320] Filesystems sync: 0.000 seconds
11231 14:02:08.201826 <6>[ 31.355851] Freezing user space processes
11232 14:02:08.208535 <6>[ 31.357673] Freezing user space processes completed (elapsed 0.001 seconds)
11233 14:02:08.215228 <6>[ 31.357682] OOM killer disabled.
11234 14:02:08.218193 <6>[ 31.357685] Freezing remaining freezable tasks
11235 14:02:08.225206 <6>[ 31.359101] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11236 14:02:08.232043 <6>[ 31.359112] printk: Suspending console(s) (use no_console_suspend to debug)
11237 14:02:11.626902 <3>[ 34.561723] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11238 14:02:11.637003 <3>[ 34.561751] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11239 14:02:11.646826 <3>[ 34.561794] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11240 14:02:11.653774 <3>[ 34.561892] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11241 14:02:11.660026 <3>[ 34.562076] PM: Some devices failed to suspend, or early wake event detected
11242 14:02:11.730685 rtcwake: write error
11243 14:02:11.733924 <6>[ 34.893778] OOM killer enabled.
11244 14:02:11.737228 <6>[ 34.893790] Restarting tasks ... done.
11245 14:02:11.744071 <5>[ 34.895727] random: crng reseeded on system resumption
11246 14:02:11.747254 <6>[ 34.896557] PM: suspend exit
11247 14:02:11.750855 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11249 14:02:11.754062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11250 14:02:11.754158 rtcwake: assuming RTC uses UTC ...
11251 14:02:11.760475 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 14:00:51 2023
11252 14:02:11.774734 <6>[ 34.935876] PM: suspend entry (deep)
11253 14:02:11.777967 <6>[ 34.935930] Filesystems sync: 0.000 seconds
11254 14:02:11.781329 <6>[ 34.936470] Freezing user space processes
11255 14:02:11.787771 <6>[ 34.938117] Freezing user space processes completed (elapsed 0.001 seconds)
11256 14:02:11.791494 <6>[ 34.938123] OOM killer disabled.
11257 14:02:11.798018 <6>[ 34.938125] Freezing remaining freezable tasks
11258 14:02:11.804492 <6>[ 34.939568] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11259 14:02:11.811445 <6>[ 34.939580] printk: Suspending console(s) (use no_console_suspend to debug)
11260 14:02:15.210597 <3>[ 38.145690] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11261 14:02:15.220397 <3>[ 38.145713] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11262 14:02:15.230131 <3>[ 38.145743] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11263 14:02:15.237413 <3>[ 38.145773] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11264 14:02:15.244261 <3>[ 38.145976] PM: Some devices failed to suspend, or early wake event detected
11265 14:02:15.318686 <6>[ 38.477770] OOM killer enabled.
11266 14:02:15.321955 rtcwake: write e<6>[ 38.477782] Restarting tasks ... done.
11267 14:02:15.328320 <5>[ 38.481192] random: crng reseeded on system resumption
11268 14:02:15.331737 <6>[ 38.485189] PM: suspend exit
11269 14:02:15.331820 rror
11270 14:02:15.338467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11271 14:02:15.338723 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11273 14:02:15.341553 rtcwake: assuming RTC uses UTC ...
11274 14:02:15.345109 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 14:00:55 2023
11275 14:02:15.358398 <6>[ 38.520749] PM: suspend entry (deep)
11276 14:02:15.361575 <6>[ 38.520791] Filesystems sync: 0.000 seconds
11277 14:02:15.365053 <6>[ 38.521319] Freezing user space processes
11278 14:02:15.371837 <6>[ 38.529433] Freezing user space processes completed (elapsed 0.008 seconds)
11279 14:02:15.375361 <6>[ 38.529441] OOM killer disabled.
11280 14:02:15.381985 <6>[ 38.529445] Freezing remaining freezable tasks
11281 14:02:15.388551 <6>[ 38.530837] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11282 14:02:15.395227 <6>[ 38.530847] printk: Suspending console(s) (use no_console_suspend to debug)
11283 14:02:18.794270 <3>[ 41.729737] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11284 14:02:18.803921 <3>[ 41.729766] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11285 14:02:18.813849 <3>[ 41.729809] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11286 14:02:18.820657 <3>[ 41.729850] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11287 14:02:18.827504 <3>[ 41.730100] PM: Some devices failed to suspend, or early wake event detected
11288 14:02:18.901233 rtcwake: <6>[ 42.061774] OOM killer enabled.
11289 14:02:18.901358 write error
11290 14:02:18.904370 <6>[ 42.061786] Restarting tasks ... done.
11291 14:02:18.911251 <5>[ 42.063556] random: crng reseeded on system resumption
11292 14:02:18.914806 <LAVA_SIGNAL_TES<6>[ 42.064619] PM: suspend exit
11293 14:02:18.917788 Received signal: <TES<6>[> 42.064619] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11294 14:02:18.921114 TCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11295 14:02:18.921219 rtcwake: assuming RTC uses UTC ...
11296 14:02:18.927909 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 14:00:58 2023
11297 14:02:18.946109 <6>[ 42.105550] PM: suspend entry (deep)
11298 14:02:18.949485 <6>[ 42.105627] Filesystems sync: 0.000 seconds
11299 14:02:18.952593 <6>[ 42.106164] Freezing user space processes
11300 14:02:18.959169 <6>[ 42.107911] Freezing user space processes completed (elapsed 0.001 seconds)
11301 14:02:18.962396 <6>[ 42.107921] OOM killer disabled.
11302 14:02:18.969123 <6>[ 42.107923] Freezing remaining freezable tasks
11303 14:02:18.975730 <6>[ 42.109337] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11304 14:02:18.982501 <6>[ 42.109350] printk: Suspending console(s) (use no_console_suspend to debug)
11305 14:02:22.377866 <3>[ 45.313839] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11306 14:02:22.387220 <3>[ 45.313885] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11307 14:02:22.397476 <3>[ 45.313942] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11308 14:02:22.404194 <3>[ 45.313989] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11309 14:02:22.410912 <3>[ 45.314233] PM: Some devices failed to suspend, or early wake event detected
11310 14:02:22.481283 rtcwake: write error
11311 14:02:22.484699 <6>[ 45.645780] OOM killer enabled.
11312 14:02:22.491316 <LAVA_SIGNAL_TES<6>[ 45.645793] Restarting tasks ... done.
11313 14:02:22.491571 Received signal: <TES<6>[> 45.645793] Restarting tasks ... done.
TCASE TEST_CASE_<5
11314 14:02:22.498110 TCASE TEST_CASE_<5>[ 45.647749] random: crng reseeded on system resumption
11315 14:02:22.501662 ID=rtcwake-mem-7<6>[ 45.648511] PM: suspend exit
11316 14:02:22.504731 RESULT=fail>
11317 14:02:22.504804 rtcwake: assuming RTC uses UTC ...
11318 14:02:22.511530 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 14:01:02 2023
11319 14:02:22.525839 <6>[ 45.686405] PM: suspend entry (deep)
11320 14:02:22.529238 <6>[ 45.686459] Filesystems sync: 0.000 seconds
11321 14:02:22.532169 <6>[ 45.686985] Freezing user space processes
11322 14:02:22.538861 <6>[ 45.688663] Freezing user space processes completed (elapsed 0.001 seconds)
11323 14:02:22.542183 <6>[ 45.688673] OOM killer disabled.
11324 14:02:22.548923 <6>[ 45.688675] Freezing remaining freezable tasks
11325 14:02:22.555269 <6>[ 45.689989] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11326 14:02:22.562180 <6>[ 45.689995] printk: Suspending console(s) (use no_console_suspend to debug)
11327 14:02:25.965853 <6>[ 48.129847] vpu: disabling
11328 14:02:25.969158 <6>[ 48.129951] vproc2: disabling
11329 14:02:25.972622 <6>[ 48.129995] vproc1: disabling
11330 14:02:25.976154 <6>[ 48.130040] vaud18: disabling
11331 14:02:25.979083 <6>[ 48.130247] vsram_others: disabling
11332 14:02:25.982910 <6>[ 48.130415] va09: disabling
11333 14:02:25.986167 <6>[ 48.130479] vsram_md: disabling
11334 14:02:25.989515 <6>[ 48.130589] Vgpu: disabling
11335 14:02:25.995745 <3>[ 48.897685] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11336 14:02:26.005842 <3>[ 48.897710] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11337 14:02:26.016030 <3>[ 48.897743] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11338 14:02:26.022728 <3>[ 48.897778] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11339 14:02:26.029270 <3>[ 48.897948] PM: Some devices failed to suspend, or early wake event detected
11340 14:02:26.077750 <6>[ 49.237744] OOM killer enabled.
11341 14:02:26.080992 <6>[ 49.237756] Restarting tasks ... done.
11342 14:02:26.087853 rtcwake: <5>[ 49.239760] random: crng reseeded on system resumption
11343 14:02:26.090621 <6>[ 49.243786] PM: suspend exit
11344 14:02:26.090708 write error
11345 14:02:26.100114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11346 14:02:26.100378 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11348 14:02:26.103012 rtcwake: assuming RTC uses UTC ...
11349 14:02:26.110125 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 14:01:05 2023
11350 14:02:26.125122 <6>[ 49.287844] PM: suspend entry (deep)
11351 14:02:26.128605 <6>[ 49.287897] Filesystems sync: 0.000 seconds
11352 14:02:26.131993 <6>[ 49.288438] Freezing user space processes
11353 14:02:26.138555 <6>[ 49.290004] Freezing user space processes completed (elapsed 0.001 seconds)
11354 14:02:26.142280 <6>[ 49.290009] OOM killer disabled.
11355 14:02:26.148698 <6>[ 49.290010] Freezing remaining freezable tasks
11356 14:02:26.154973 <6>[ 49.291335] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11357 14:02:26.161907 <6>[ 49.291346] printk: Suspending console(s) (use no_console_suspend to debug)
11358 14:02:29.545130 <3>[ 52.481762] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11359 14:02:29.555192 <3>[ 52.481795] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11360 14:02:29.564747 <3>[ 52.481840] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11361 14:02:29.571632 <3>[ 52.481888] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11362 14:02:29.578446 <3>[ 52.482116] PM: Some devices failed to suspend, or early wake event detected
11363 14:02:29.648220 rtcwake: write error
11364 14:02:29.651906 <6>[ 52.813756] OOM killer enabled.
11365 14:02:29.655479 <6>[ 52.813767] Restarting tasks ... done.
11366 14:02:29.662058 <5>[ 52.815459] random: crng reseeded on system resumption
11367 14:02:29.664992 <LAVA_SIGNAL_TES<6>[ 52.816308] PM: suspend exit
11368 14:02:29.668281 TCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11369 14:02:29.668581 Received signal: <TES<6>[> 52.816308] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11370 14:02:29.671987 rtcwake: assuming RTC uses UTC ...
11371 14:02:29.678238 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 14:01:09 2023
11372 14:02:29.692975 <6>[ 52.857171] PM: suspend entry (deep)
11373 14:02:29.696311 <6>[ 52.857216] Filesystems sync: 0.000 seconds
11374 14:02:29.699675 <6>[ 52.857926] Freezing user space processes
11375 14:02:29.706200 <6>[ 52.861759] Freezing user space processes completed (elapsed 0.003 seconds)
11376 14:02:29.709784 <6>[ 52.861770] OOM killer disabled.
11377 14:02:29.716339 <6>[ 52.861772] Freezing remaining freezable tasks
11378 14:02:29.723057 <6>[ 52.863148] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11379 14:02:29.729553 <6>[ 52.863158] printk: Suspending console(s) (use no_console_suspend to debug)
11380 14:02:33.128305 <3>[ 56.065716] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11381 14:02:33.138762 <3>[ 56.065745] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11382 14:02:33.148266 <3>[ 56.065788] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11383 14:02:33.154909 <3>[ 56.065832] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11384 14:02:33.162036 <3>[ 56.066094] PM: Some devices failed to suspend, or early wake event detected
11385 14:02:33.232041 rtcwake: write error
11386 14:02:33.234975 <6>[ 56.397780] OOM killer enabled.
11387 14:02:33.242032 <LAVA_SIGNAL_TES<6>[ 56.397792] Restarting tasks ... done.
11388 14:02:33.242293 Received signal: <TES<6>[> 56.397792] Restarting tasks ... done.
TCASE TEST_CASE_<5
11389 14:02:33.248599 TCASE TEST_CASE_<5>[ 56.399423] random: crng reseeded on system resumption
11390 14:02:33.252118 ID=rtcwake-mem-1<6>[ 56.400159] PM: suspend exit
11391 14:02:33.254989 0 RESULT=fail>
11392 14:02:33.255073 rtcwake: assuming RTC uses UTC ...
11393 14:02:33.261667 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 14:01:13 2023
11394 14:02:33.280814 <6>[ 56.442698] PM: suspend entry (s2idle)
11395 14:02:33.283995 <6>[ 56.442749] Filesystems sync: 0.000 seconds
11396 14:02:33.287050 <6>[ 56.443296] Freezing user space processes
11397 14:02:33.293489 <6>[ 56.445007] Freezing user space processes completed (elapsed 0.001 seconds)
11398 14:02:33.300456 <6>[ 56.445019] OOM killer disabled.
11399 14:02:33.303678 <6>[ 56.445021] Freezing remaining freezable tasks
11400 14:02:33.310273 <6>[ 56.446378] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11401 14:02:33.316957 <6>[ 56.446390] printk: Suspending console(s) (use no_console_suspend to debug)
11402 14:02:36.716245 <3>[ 59.649691] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11403 14:02:36.726106 <3>[ 59.649714] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11404 14:02:36.736426 <3>[ 59.649748] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11405 14:02:36.743248 <3>[ 59.649780] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11406 14:02:36.749520 <3>[ 59.649991] PM: Some devices failed to suspend, or early wake event detected
11407 14:02:36.820057 rtcwake: write error
11408 14:02:36.823378 <6>[ 59.985816] OOM killer enabled.
11409 14:02:36.826543 <6>[ 59.985828] Restarting tasks ... done.
11410 14:02:36.833490 <5>[ 59.987738] random: crng reseeded on system resumption
11411 14:02:36.836842 <6>[ 59.988713] PM: suspend exit
11412 14:02:36.843669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11413 14:02:36.844021 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11415 14:02:36.846813 rtcwake: assuming RTC uses UTC ...
11416 14:02:36.850126 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 14:01:16 2023
11417 14:02:36.863872 <6>[ 60.028292] PM: suspend entry (s2idle)
11418 14:02:36.867420 <6>[ 60.028337] Filesystems sync: 0.000 seconds
11419 14:02:36.870955 <6>[ 60.028887] Freezing user space processes
11420 14:02:36.877390 <6>[ 60.030617] Freezing user space processes completed (elapsed 0.001 seconds)
11421 14:02:36.884020 <6>[ 60.030629] OOM killer disabled.
11422 14:02:36.887457 <6>[ 60.030631] Freezing remaining freezable tasks
11423 14:02:36.893987 <6>[ 60.032070] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11424 14:02:36.900531 <6>[ 60.032081] printk: Suspending console(s) (use no_console_suspend to debug)
11425 14:02:40.299847 <3>[ 63.233839] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11426 14:02:40.310021 <3>[ 63.233882] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11427 14:02:40.319541 <3>[ 63.233943] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11428 14:02:40.326495 <3>[ 63.233995] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11429 14:02:40.333249 <3>[ 63.234277] PM: Some devices failed to suspend, or early wake event detected
11430 14:02:40.403350 rtcwake: write error
11431 14:02:40.406802 <6>[ 63.569777] OOM killer enabled.
11432 14:02:40.413319 <LAVA_SIGNAL_TES<6>[ 63.569789] Restarting tasks ... done.
11433 14:02:40.413634 Received signal: <TES<6>[> 63.569789] Restarting tasks ... done.
TCASE TEST_CASE_<5
11434 14:02:40.420177 TCASE TEST_CASE_<5>[ 63.571704] random: crng reseeded on system resumption
11435 14:02:40.423342 ID=rtcwake-freez<6>[ 63.572534] PM: suspend exit
11436 14:02:40.426632 e-2 RESULT=fail>
11437 14:02:40.430219 rtcwake: assuming RTC uses UTC ...
11438 14:02:40.433654 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 14:01:20 2023
11439 14:02:40.451588 <6>[ 63.615004] PM: suspend entry (s2idle)
11440 14:02:40.454882 <6>[ 63.615046] Filesystems sync: 0.000 seconds
11441 14:02:40.458602 <6>[ 63.615560] Freezing user space processes
11442 14:02:40.464963 <6>[ 63.617196] Freezing user space processes completed (elapsed 0.001 seconds)
11443 14:02:40.468254 <6>[ 63.617207] OOM killer disabled.
11444 14:02:40.475248 <6>[ 63.617209] Freezing remaining freezable tasks
11445 14:02:40.481618 <6>[ 63.618532] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11446 14:02:40.488228 <6>[ 63.618542] printk: Suspending console(s) (use no_console_suspend to debug)
11447 14:02:43.879268 <3>[ 66.817675] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11448 14:02:43.889414 <3>[ 66.817697] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11449 14:02:43.899661 <3>[ 66.817725] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11450 14:02:43.906014 <3>[ 66.817754] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11451 14:02:43.912963 <3>[ 66.817983] PM: Some devices failed to suspend, or early wake event detected
11452 14:02:43.984321 <6>[ 67.149780] OOM killer enabled.
11453 14:02:43.991258 <6>[ 67.149791] Restarting tasks ... done.
11454 14:02:43.994518 <5>[ 67.152686] random: crng reseeded on system resumption
11455 14:02:43.998830 rtcwake: write error
11456 14:02:44.001388 <6>[ 67.167004] PM: suspend exit
11457 14:02:44.008314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11458 14:02:44.008575 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11460 14:02:44.011504 rtcwake: assuming RTC uses UTC ...
11461 14:02:44.014449 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 14:01:23 2023
11462 14:02:44.031597 <6>[ 67.195349] PM: suspend entry (s2idle)
11463 14:02:44.034903 <6>[ 67.195400] Filesystems sync: 0.000 seconds
11464 14:02:44.038257 <6>[ 67.195937] Freezing user space processes
11465 14:02:44.044432 <6>[ 67.197667] Freezing user space processes completed (elapsed 0.001 seconds)
11466 14:02:44.047817 <6>[ 67.197677] OOM killer disabled.
11467 14:02:44.054800 <6>[ 67.197679] Freezing remaining freezable tasks
11468 14:02:44.061227 <6>[ 67.199040] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11469 14:02:44.068234 <6>[ 67.199051] printk: Suspending console(s) (use no_console_suspend to debug)
11470 14:02:47.467105 <3>[ 70.401710] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11471 14:02:47.477122 <3>[ 70.401738] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11472 14:02:47.487055 <3>[ 70.401781] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11473 14:02:47.493584 <3>[ 70.401826] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11474 14:02:47.500271 <3>[ 70.402086] PM: Some devices failed to suspend, or early wake event detected
11475 14:02:47.574638 <6>[ 70.737778] OOM killer enabled.
11476 14:02:47.578081 rtcwake: write error
11477 14:02:47.581632 <6>[ 70.737790] Restarting tasks ... done.
11478 14:02:47.588182 <LAVA_SIGNAL_TES<5>[ 70.746142] random: crng reseeded on system resumption
11479 14:02:47.591469 TCASE TEST_CASE_<6>[ 70.747334] PM: suspend exit
11480 14:02:47.591731 Received signal: <TES<5>[> 70.746142] random: crng reseeded on system resumption
TCASE TEST_CASE_<6
11481 14:02:47.594965 ID=rtcwake-freeze-4 RESULT=fail>
11482 14:02:47.598444 rtcwake: assuming RTC uses UTC ...
11483 14:02:47.604561 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 14:01:27 2023
11484 14:02:47.618779 <6>[ 70.785297] PM: suspend entry (s2idle)
11485 14:02:47.622358 <6>[ 70.785341] Filesystems sync: 0.000 seconds
11486 14:02:47.626181 <6>[ 70.786101] Freezing user space processes
11487 14:02:47.632357 <6>[ 70.789774] Freezing user space processes completed (elapsed 0.003 seconds)
11488 14:02:47.636088 <6>[ 70.789786] OOM killer disabled.
11489 14:02:47.642244 <6>[ 70.789788] Freezing remaining freezable tasks
11490 14:02:47.649433 <6>[ 70.797715] Freezing remaining freezable tasks completed (elapsed 0.007 seconds)
11491 14:02:47.655491 <6>[ 70.797727] printk: Suspending console(s) (use no_console_suspend to debug)
11492 14:02:51.054561 <3>[ 73.985713] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11493 14:02:51.064380 <3>[ 73.985740] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11494 14:02:51.074338 <3>[ 73.985783] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11495 14:02:51.081049 <3>[ 73.985824] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11496 14:02:51.087932 <3>[ 73.986056] PM: Some devices failed to suspend, or early wake event detected
11497 14:02:51.162742 <6>[ 74.325779] OOM killer enabled.
11498 14:02:51.165601 rtcwake: write error
11499 14:02:51.168799 <6>[ 74.325792] Restarting tasks ... done.
11500 14:02:51.175854 <LAVA_SIGNAL_TES<5>[ 74.333829] random: crng reseeded on system resumption
11501 14:02:51.179613 Received signal: <TES<5>[> 74.333829] random: crng reseeded on system resumption
TCASE TEST_CASE_<6
11502 14:02:51.182582 TCASE TEST_CASE_<6>[ 74.335622] PM: suspend exit
11503 14:02:51.182665 ID=rtcwake-freeze-5 RESULT=fail>
11504 14:02:51.185845 rtcwake: assuming RTC uses UTC ...
11505 14:02:51.192678 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 14:01:30 2023
11506 14:02:51.211021 <6>[ 74.373634] PM: suspend entry (s2idle)
11507 14:02:51.213852 <6>[ 74.373680] Filesystems sync: 0.000 seconds
11508 14:02:51.217002 <6>[ 74.374186] Freezing user space processes
11509 14:02:51.224224 <6>[ 74.375832] Freezing user space processes completed (elapsed 0.001 seconds)
11510 14:02:51.230698 <6>[ 74.375843] OOM killer disabled.
11511 14:02:51.234192 <6>[ 74.375845] Freezing remaining freezable tasks
11512 14:02:51.240413 <6>[ 74.377233] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11513 14:02:51.246779 <6>[ 74.377247] printk: Suspending console(s) (use no_console_suspend to debug)
11514 14:02:54.630132 <3>[ 77.569793] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11515 14:02:54.640271 <3>[ 77.569822] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11516 14:02:54.650255 <3>[ 77.569868] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11517 14:02:54.656643 <3>[ 77.569910] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11518 14:02:54.663402 <3>[ 77.570150] PM: Some devices failed to suspend, or early wake event detected
11519 14:02:54.734286 rtcwake: write error
11520 14:02:54.737954 <6>[ 77.901807] OOM killer enabled.
11521 14:02:54.740666 <6>[ 77.901819] Restarting tasks ... done.
11522 14:02:54.747538 <5>[ 77.903733] random: crng reseeded on system resumption
11523 14:02:54.750686 <LAVA_SIGNAL_TES<6>[ 77.904764] PM: suspend exit
11524 14:02:54.754169 Received signal: <TES<6>[> 77.904764] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11525 14:02:54.757659 TCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11526 14:02:54.757743 rtcwake: assuming RTC uses UTC ...
11527 14:02:54.764093 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 14:01:34 2023
11528 14:02:54.782355 <6>[ 77.945665] PM: suspend entry (s2idle)
11529 14:02:54.785777 <6>[ 77.945711] Filesystems sync: 0.000 seconds
11530 14:02:54.788801 <6>[ 77.946240] Freezing user space processes
11531 14:02:54.795806 <6>[ 77.947888] Freezing user space processes completed (elapsed 0.001 seconds)
11532 14:02:54.798717 <6>[ 77.947899] OOM killer disabled.
11533 14:02:54.805634 <6>[ 77.947901] Freezing remaining freezable tasks
11534 14:02:54.812116 <6>[ 77.949238] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11535 14:02:54.819223 <6>[ 77.949251] printk: Suspending console(s) (use no_console_suspend to debug)
11536 14:02:58.221983 <3>[ 81.153709] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11537 14:02:58.231796 <3>[ 81.153737] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11538 14:02:58.241740 <3>[ 81.153781] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11539 14:02:58.248181 <3>[ 81.153822] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11540 14:02:58.255212 <3>[ 81.154076] PM: Some devices failed to suspend, or early wake event detected
11541 14:02:58.329348 rtcwake: <6>[ 81.493779] OOM killer enabled.
11542 14:02:58.329512 write error
11543 14:02:58.332674 <6>[ 81.493790] Restarting tasks ... done.
11544 14:02:58.339305 <5>[ 81.495875] random: crng reseeded on system resumption
11545 14:02:58.342277 <6>[ 81.496892] PM: suspend exit
11546 14:02:58.349443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11547 14:02:58.349757 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11549 14:02:58.352367 rtcwake: assuming RTC uses UTC ...
11550 14:02:58.359092 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 14:01:38 2023
11551 14:02:58.377605 <6>[ 81.542768] PM: suspend entry (s2idle)
11552 14:02:58.381092 <6>[ 81.542824] Filesystems sync: 0.000 seconds
11553 14:02:58.384217 <6>[ 81.543350] Freezing user space processes
11554 14:02:58.390823 <6>[ 81.544998] Freezing user space processes completed (elapsed 0.001 seconds)
11555 14:02:58.397622 <6>[ 81.545009] OOM killer disabled.
11556 14:02:58.401007 <6>[ 81.545011] Freezing remaining freezable tasks
11557 14:02:58.407934 <6>[ 81.546376] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11558 14:02:58.414466 <6>[ 81.546387] printk: Suspending console(s) (use no_console_suspend to debug)
11559 14:03:01.796857 <3>[ 84.737752] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11560 14:03:01.807375 <3>[ 84.737781] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11561 14:03:01.817105 <3>[ 84.737824] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11562 14:03:01.823963 <3>[ 84.737866] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11563 14:03:01.830484 <3>[ 84.738099] PM: Some devices failed to suspend, or early wake event detected
11564 14:03:01.901325 rtcwake: write error
11565 14:03:01.904536 <6>[ 85.069774] OOM killer enabled.
11566 14:03:01.907506 <6>[ 85.069785] Restarting tasks ... done.
11567 14:03:01.914785 <5>[ 85.071684] random: crng reseeded on system resumption
11568 14:03:01.917770 <LAVA_SIGNAL_TES<6>[ 85.072525] PM: suspend exit
11569 14:03:01.921312 Received signal: <TES<6>[> 85.072525] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11570 14:03:01.924440 TCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11571 14:03:01.924523 rtcwake: assuming RTC uses UTC ...
11572 14:03:01.931105 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 14:01:41 2023
11573 14:03:01.949779 <6>[ 85.113430] PM: suspend entry (s2idle)
11574 14:03:01.952448 <6>[ 85.113480] Filesystems sync: 0.000 seconds
11575 14:03:01.955818 <6>[ 85.114069] Freezing user space processes
11576 14:03:01.963000 <6>[ 85.115764] Freezing user space processes completed (elapsed 0.001 seconds)
11577 14:03:01.969277 <6>[ 85.115776] OOM killer disabled.
11578 14:03:01.973109 <6>[ 85.115778] Freezing remaining freezable tasks
11579 14:03:01.979176 <6>[ 85.117148] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11580 14:03:01.986019 <6>[ 85.117161] printk: Suspending console(s) (use no_console_suspend to debug)
11581 14:03:05.380973 <3>[ 88.321705] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11582 14:03:05.390919 <3>[ 88.321732] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11583 14:03:05.401226 <3>[ 88.321771] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11584 14:03:05.407623 <3>[ 88.321810] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11585 14:03:05.413976 <3>[ 88.322055] PM: Some devices failed to suspend, or early wake event detected
11586 14:03:05.488574 <6>[ 88.653780] OOM killer enabled.
11587 14:03:05.491931 <6>[ 88.653792] Restarting tasks ... done.
11588 14:03:05.498838 rtcwake: write e<5>[ 88.656874] random: crng reseeded on system resumption
11589 14:03:05.498926 rror
11590 14:03:05.502236 <6>[ 88.665015] PM: suspend exit
11591 14:03:05.508718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11592 14:03:05.508982 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11594 14:03:05.512252 rtcwake: assuming RTC uses UTC ...
11595 14:03:05.515791 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 14:01:45 2023
11596 14:03:05.532588 <6>[ 88.698174] PM: suspend entry (s2idle)
11597 14:03:05.535828 <6>[ 88.698228] Filesystems sync: 0.000 seconds
11598 14:03:05.539141 <6>[ 88.698771] Freezing user space processes
11599 14:03:05.545742 <6>[ 88.700486] Freezing user space processes completed (elapsed 0.001 seconds)
11600 14:03:05.553130 <6>[ 88.700498] OOM killer disabled.
11601 14:03:05.556720 <6>[ 88.700500] Freezing remaining freezable tasks
11602 14:03:05.563305 <6>[ 88.701619] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11603 14:03:05.569586 <6>[ 88.701631] printk: Suspending console(s) (use no_console_suspend to debug)
11604 14:03:08.964343 <3>[ 91.905755] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11605 14:03:08.974484 <3>[ 91.905784] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11606 14:03:08.984687 <3>[ 91.905826] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11607 14:03:08.991084 <3>[ 91.905867] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11608 14:03:08.997489 <3>[ 91.906169] PM: Some devices failed to suspend, or early wake event detected
11609 14:03:09.072390 <6>[ 92.237774] OOM killer enabled.
11610 14:03:09.075859 rtcwake: <6>[ 92.237785] Restarting tasks ... done.
11611 14:03:09.075996 write error
11612 14:03:09.082382 <5>[ 92.239887] random: crng reseeded on system resumption
11613 14:03:09.085379 <6>[ 92.245008] PM: suspend exit
11614 14:03:09.094908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11615 14:03:09.095173 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11617 14:03:09.098160 + set +x
11618 14:03:09.101250 <LAVA_SIGNAL_ENDRUN 0_sleep 11588075_1.5.2.3.1>
11619 14:03:09.101333 <LAVA_TEST_RUNNER EXIT>
11620 14:03:09.101572 Received signal: <ENDRUN> 0_sleep 11588075_1.5.2.3.1
11621 14:03:09.101652 Ending use of test pattern.
11622 14:03:09.101713 Ending test lava.0_sleep (11588075_1.5.2.3.1), duration 71.76
11624 14:03:09.101943 ok: lava_test_shell seems to have completed
11625 14:03:09.102087 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-3: fail
rtcwake-freeze-7: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-8: fail
11626 14:03:09.102187 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11627 14:03:09.102275 end: 3 lava-test-retry (duration 00:01:12) [common]
11628 14:03:09.102361 start: 4 finalize (timeout 00:06:06) [common]
11629 14:03:09.102451 start: 4.1 power-off (timeout 00:00:30) [common]
11630 14:03:09.102609 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11631 14:03:09.179233 >> Command sent successfully.
11632 14:03:09.181683 Returned 0 in 0 seconds
11633 14:03:09.282141 end: 4.1 power-off (duration 00:00:00) [common]
11635 14:03:09.282477 start: 4.2 read-feedback (timeout 00:06:06) [common]
11636 14:03:09.282752 Listened to connection for namespace 'common' for up to 1s
11637 14:03:09.283055 Listened to connection for namespace 'common' for up to 1s
11638 14:03:10.283745 Finalising connection for namespace 'common'
11639 14:03:10.284001 Disconnecting from shell: Finalise
11640 14:03:10.284105 / #
11641 14:03:10.384462 end: 4.2 read-feedback (duration 00:00:01) [common]
11642 14:03:10.384631 end: 4 finalize (duration 00:00:01) [common]
11643 14:03:10.384789 Cleaning after the job
11644 14:03:10.384924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/ramdisk
11645 14:03:10.399102 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/kernel
11646 14:03:10.422573 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/dtb
11647 14:03:10.422782 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588075/tftp-deploy-x8a14o6p/modules
11648 14:03:10.430246 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11588075
11649 14:03:10.604684 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11588075
11650 14:03:10.604854 Job finished correctly