Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 0
- Boot result: UNKNOWN
- Warnings: 0
- Kernel Warnings: 0
1 13:57:19.926566 lava-dispatcher, installed at version: 2023.06
2 13:57:19.926769 start: 0 validate
3 13:57:19.926899 Start time: 2023-09-21 13:57:19.926891+00:00 (UTC)
4 13:57:19.927027 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:57:19.927221 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:57:20.200292 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:57:20.201083 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:58:18.294154 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:58:18.294909 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:58:18.565527 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:58:18.566228 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.54-cip6-101-gb060fea6ba099%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:58:21.335578 validate duration: 61.41
14 13:58:21.335845 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:58:21.335950 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:58:21.336039 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:58:21.336170 Not decompressing ramdisk as can be used compressed.
18 13:58:21.336254 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 13:58:21.336324 saving as /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/ramdisk/rootfs.cpio.gz
20 13:58:21.336388 total size: 26246609 (25 MB)
21 13:58:21.602921 progress 0 % (0 MB)
22 13:58:21.610008 progress 5 % (1 MB)
23 13:58:21.617074 progress 10 % (2 MB)
24 13:58:21.623989 progress 15 % (3 MB)
25 13:58:21.630733 progress 20 % (5 MB)
26 13:58:21.637523 progress 25 % (6 MB)
27 13:58:21.644362 progress 30 % (7 MB)
28 13:58:21.651258 progress 35 % (8 MB)
29 13:58:21.658139 progress 40 % (10 MB)
30 13:58:21.665021 progress 45 % (11 MB)
31 13:58:21.671890 progress 50 % (12 MB)
32 13:58:21.678700 progress 55 % (13 MB)
33 13:58:21.685483 progress 60 % (15 MB)
34 13:58:21.692287 progress 65 % (16 MB)
35 13:58:21.699179 progress 70 % (17 MB)
36 13:58:21.706167 progress 75 % (18 MB)
37 13:58:21.713095 progress 80 % (20 MB)
38 13:58:21.720063 progress 85 % (21 MB)
39 13:58:21.726818 progress 90 % (22 MB)
40 13:58:21.733521 progress 95 % (23 MB)
41 13:58:21.740219 progress 100 % (25 MB)
42 13:58:21.740492 25 MB downloaded in 0.40 s (61.94 MB/s)
43 13:58:21.740646 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:58:21.740888 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:58:21.740978 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:58:21.741063 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:58:21.741185 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:58:21.741255 saving as /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/kernel/Image
50 13:58:21.741316 total size: 49304064 (47 MB)
51 13:58:21.741379 No compression specified
52 13:58:21.742497 progress 0 % (0 MB)
53 13:58:21.755599 progress 5 % (2 MB)
54 13:58:21.768692 progress 10 % (4 MB)
55 13:58:21.781653 progress 15 % (7 MB)
56 13:58:21.794357 progress 20 % (9 MB)
57 13:58:21.807487 progress 25 % (11 MB)
58 13:58:21.820425 progress 30 % (14 MB)
59 13:58:21.833309 progress 35 % (16 MB)
60 13:58:21.846294 progress 40 % (18 MB)
61 13:58:21.859329 progress 45 % (21 MB)
62 13:58:21.872147 progress 50 % (23 MB)
63 13:58:21.885135 progress 55 % (25 MB)
64 13:58:21.898140 progress 60 % (28 MB)
65 13:58:21.912461 progress 65 % (30 MB)
66 13:58:21.926300 progress 70 % (32 MB)
67 13:58:21.939239 progress 75 % (35 MB)
68 13:58:21.952245 progress 80 % (37 MB)
69 13:58:21.965521 progress 85 % (39 MB)
70 13:58:21.979359 progress 90 % (42 MB)
71 13:58:21.992737 progress 95 % (44 MB)
72 13:58:22.006253 progress 100 % (47 MB)
73 13:58:22.006581 47 MB downloaded in 0.27 s (177.26 MB/s)
74 13:58:22.006739 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:58:22.007136 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:58:22.007246 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:58:22.007339 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:58:22.007483 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:58:22.007554 saving as /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/dtb/mt8192-asurada-spherion-r0.dtb
81 13:58:22.007616 total size: 47278 (0 MB)
82 13:58:22.007678 No compression specified
83 13:58:22.008950 progress 69 % (0 MB)
84 13:58:22.009232 progress 100 % (0 MB)
85 13:58:22.009391 0 MB downloaded in 0.00 s (25.43 MB/s)
86 13:58:22.009516 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:58:22.009747 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:58:22.009833 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:58:22.009917 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:58:22.010033 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.54-cip6-101-gb060fea6ba099/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:58:22.010108 saving as /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/modules/modules.tar
93 13:58:22.010205 total size: 8629568 (8 MB)
94 13:58:22.010292 Using unxz to decompress xz
95 13:58:22.014563 progress 0 % (0 MB)
96 13:58:22.036374 progress 5 % (0 MB)
97 13:58:22.058687 progress 10 % (0 MB)
98 13:58:22.084672 progress 15 % (1 MB)
99 13:58:22.110420 progress 20 % (1 MB)
100 13:58:22.136602 progress 25 % (2 MB)
101 13:58:22.165424 progress 30 % (2 MB)
102 13:58:22.190293 progress 35 % (2 MB)
103 13:58:22.215454 progress 40 % (3 MB)
104 13:58:22.239630 progress 45 % (3 MB)
105 13:58:22.266388 progress 50 % (4 MB)
106 13:58:22.291722 progress 55 % (4 MB)
107 13:58:22.318301 progress 60 % (4 MB)
108 13:58:22.341268 progress 65 % (5 MB)
109 13:58:22.366377 progress 70 % (5 MB)
110 13:58:22.390565 progress 75 % (6 MB)
111 13:58:22.417131 progress 80 % (6 MB)
112 13:58:22.446069 progress 85 % (7 MB)
113 13:58:22.475800 progress 90 % (7 MB)
114 13:58:22.500300 progress 95 % (7 MB)
115 13:58:22.523658 progress 100 % (8 MB)
116 13:58:22.528908 8 MB downloaded in 0.52 s (15.87 MB/s)
117 13:58:22.529172 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:58:22.529439 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:58:22.529535 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:58:22.529634 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:58:22.529718 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:58:22.529808 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:58:22.530027 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex
125 13:58:22.530167 makedir: /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin
126 13:58:22.530276 makedir: /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/tests
127 13:58:22.530394 makedir: /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/results
128 13:58:22.530525 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-add-keys
129 13:58:22.530681 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-add-sources
130 13:58:22.530817 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-background-process-start
131 13:58:22.530951 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-background-process-stop
132 13:58:22.531107 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-common-functions
133 13:58:22.531251 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-echo-ipv4
134 13:58:22.531383 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-install-packages
135 13:58:22.531514 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-installed-packages
136 13:58:22.531641 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-os-build
137 13:58:22.531769 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-probe-channel
138 13:58:22.531897 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-probe-ip
139 13:58:22.532026 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-target-ip
140 13:58:22.532154 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-target-mac
141 13:58:22.532282 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-target-storage
142 13:58:22.532416 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-test-case
143 13:58:22.532543 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-test-event
144 13:58:22.532669 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-test-feedback
145 13:58:22.532837 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-test-raise
146 13:58:22.533062 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-test-reference
147 13:58:22.533281 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-test-runner
148 13:58:22.533493 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-test-set
149 13:58:22.533701 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-test-shell
150 13:58:22.533909 Updating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-install-packages (oe)
151 13:58:22.534165 Updating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/bin/lava-installed-packages (oe)
152 13:58:22.534372 Creating /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/environment
153 13:58:22.534541 LAVA metadata
154 13:58:22.534668 - LAVA_JOB_ID=11588083
155 13:58:22.534775 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:58:22.534940 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:58:22.535052 skipped lava-vland-overlay
158 13:58:22.535216 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:58:22.535349 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:58:22.535471 skipped lava-multinode-overlay
161 13:58:22.535597 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:58:22.535734 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:58:22.535861 Loading test definitions
164 13:58:22.536014 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:58:22.536137 Using /lava-11588083 at stage 0
166 13:58:22.536620 uuid=11588083_1.5.2.3.1 testdef=None
167 13:58:22.536755 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:58:22.536891 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:58:22.537698 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:58:22.538068 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:58:22.539043 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:58:22.539471 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:58:22.540429 runner path: /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11588083_1.5.2.3.1
176 13:58:22.540657 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:58:22.541005 Creating lava-test-runner.conf files
179 13:58:22.541110 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11588083/lava-overlay-o9udf5ex/lava-11588083/0 for stage 0
180 13:58:22.541249 - 0_v4l2-compliance-mtk-vcodec-enc
181 13:58:22.541403 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:58:22.541538 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:58:22.551575 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:58:22.551745 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:58:22.551884 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:58:22.552025 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:58:22.552167 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:58:23.277141 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:58:23.277544 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:58:23.277668 extracting modules file /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11588083/extract-overlay-ramdisk-bv3kw7ic/ramdisk
191 13:58:23.508933 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:58:23.509112 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:58:23.509209 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11588083/compress-overlay-jineblk9/overlay-1.5.2.4.tar.gz to ramdisk
194 13:58:23.509284 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11588083/compress-overlay-jineblk9/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11588083/extract-overlay-ramdisk-bv3kw7ic/ramdisk
195 13:58:23.516063 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:58:23.516180 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:58:23.516270 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:58:23.516360 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:58:23.516438 Building ramdisk /var/lib/lava/dispatcher/tmp/11588083/extract-overlay-ramdisk-bv3kw7ic/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11588083/extract-overlay-ramdisk-bv3kw7ic/ramdisk
200 13:58:24.140162 >> 228384 blocks
201 13:58:28.108546 rename /var/lib/lava/dispatcher/tmp/11588083/extract-overlay-ramdisk-bv3kw7ic/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/ramdisk/ramdisk.cpio.gz
202 13:58:28.109013 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 13:58:28.109145 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 13:58:28.109247 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 13:58:28.109362 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/kernel/Image'
206 13:58:41.118825 Returned 0 in 13 seconds
207 13:58:41.219528 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/kernel/image.itb
208 13:58:41.841361 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:58:41.841752 output: Created: Thu Sep 21 14:58:41 2023
210 13:58:41.841830 output: Image 0 (kernel-1)
211 13:58:41.841896 output: Description:
212 13:58:41.841961 output: Created: Thu Sep 21 14:58:41 2023
213 13:58:41.842026 output: Type: Kernel Image
214 13:58:41.842089 output: Compression: lzma compressed
215 13:58:41.842148 output: Data Size: 11044874 Bytes = 10786.01 KiB = 10.53 MiB
216 13:58:41.842209 output: Architecture: AArch64
217 13:58:41.842270 output: OS: Linux
218 13:58:41.842326 output: Load Address: 0x00000000
219 13:58:41.842382 output: Entry Point: 0x00000000
220 13:58:41.842436 output: Hash algo: crc32
221 13:58:41.842489 output: Hash value: a5f1a0d7
222 13:58:41.842542 output: Image 1 (fdt-1)
223 13:58:41.842596 output: Description: mt8192-asurada-spherion-r0
224 13:58:41.842648 output: Created: Thu Sep 21 14:58:41 2023
225 13:58:41.842701 output: Type: Flat Device Tree
226 13:58:41.842755 output: Compression: uncompressed
227 13:58:41.842808 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:58:41.842861 output: Architecture: AArch64
229 13:58:41.842914 output: Hash algo: crc32
230 13:58:41.842967 output: Hash value: cc4352de
231 13:58:41.843020 output: Image 2 (ramdisk-1)
232 13:58:41.843081 output: Description: unavailable
233 13:58:41.843172 output: Created: Thu Sep 21 14:58:41 2023
234 13:58:41.843225 output: Type: RAMDisk Image
235 13:58:41.843281 output: Compression: Unknown Compression
236 13:58:41.843334 output: Data Size: 39347049 Bytes = 38424.85 KiB = 37.52 MiB
237 13:58:41.843387 output: Architecture: AArch64
238 13:58:41.843440 output: OS: Linux
239 13:58:41.843493 output: Load Address: unavailable
240 13:58:41.843546 output: Entry Point: unavailable
241 13:58:41.843598 output: Hash algo: crc32
242 13:58:41.843664 output: Hash value: 3126e70a
243 13:58:41.843718 output: Default Configuration: 'conf-1'
244 13:58:41.843798 output: Configuration 0 (conf-1)
245 13:58:41.843865 output: Description: mt8192-asurada-spherion-r0
246 13:58:41.843918 output: Kernel: kernel-1
247 13:58:41.843971 output: Init Ramdisk: ramdisk-1
248 13:58:41.844024 output: FDT: fdt-1
249 13:58:41.844077 output: Loadables: kernel-1
250 13:58:41.844129 output:
251 13:58:41.844338 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 13:58:41.844439 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 13:58:41.844540 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 13:58:41.844637 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 13:58:41.844713 No LXC device requested
256 13:58:41.844796 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:58:41.844883 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 13:58:41.844964 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:58:41.845034 Checking files for TFTP limit of 4294967296 bytes.
260 13:58:41.845543 end: 1 tftp-deploy (duration 00:00:21) [common]
261 13:58:41.845646 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:58:41.845738 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:58:41.845859 substitutions:
264 13:58:41.845925 - {DTB}: 11588083/tftp-deploy-103ah0cn/dtb/mt8192-asurada-spherion-r0.dtb
265 13:58:41.845991 - {INITRD}: 11588083/tftp-deploy-103ah0cn/ramdisk/ramdisk.cpio.gz
266 13:58:41.846051 - {KERNEL}: 11588083/tftp-deploy-103ah0cn/kernel/Image
267 13:58:41.846109 - {LAVA_MAC}: None
268 13:58:41.846165 - {PRESEED_CONFIG}: None
269 13:58:41.846221 - {PRESEED_LOCAL}: None
270 13:58:41.846276 - {RAMDISK}: 11588083/tftp-deploy-103ah0cn/ramdisk/ramdisk.cpio.gz
271 13:58:41.846331 - {ROOT_PART}: None
272 13:58:41.846386 - {ROOT}: None
273 13:58:41.846440 - {SERVER_IP}: 192.168.201.1
274 13:58:41.846497 - {TEE}: None
275 13:58:41.846552 Parsed boot commands:
276 13:58:41.846605 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:58:41.846780 Parsed boot commands: tftpboot 192.168.201.1 11588083/tftp-deploy-103ah0cn/kernel/image.itb 11588083/tftp-deploy-103ah0cn/kernel/cmdline
278 13:58:41.846872 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:58:41.846958 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:58:41.847089 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:58:41.847216 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:58:41.847292 Not connected, no need to disconnect.
283 13:58:41.847368 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:58:41.847450 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:58:41.847518 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 13:58:41.851532 Setting prompt string to ['lava-test: # ']
287 13:58:41.851894 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:58:41.852002 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:58:41.852106 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:58:41.852195 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:58:41.852399 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 13:58:47.000974 >> Command sent successfully.
293 13:58:47.011352 Returned 0 in 5 seconds
294 13:58:47.112545 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:58:47.114308 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:58:47.114873 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:58:47.115421 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:58:47.115822 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:58:47.116224 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:58:47.117947 [Enter `^Ec?' for help]
302 13:58:47.279021
303 13:58:47.279620
304 13:58:47.280000 F0: 102B 0000
305 13:58:47.280357
306 13:58:47.280694 F3: 1001 0000 [0200]
307 13:58:47.282490
308 13:58:47.282968 F3: 1001 0000
309 13:58:47.283419
310 13:58:47.283779 F7: 102D 0000
311 13:58:47.284118
312 13:58:47.285583 F1: 0000 0000
313 13:58:47.286051
314 13:58:47.286387 V0: 0000 0000 [0001]
315 13:58:47.286719
316 13:58:47.289108 00: 0007 8000
317 13:58:47.289553
318 13:58:47.289895 01: 0000 0000
319 13:58:47.290218
320 13:58:47.291835 BP: 0C00 0209 [0000]
321 13:58:47.292263
322 13:58:47.292602 G0: 1182 0000
323 13:58:47.292921
324 13:58:47.295610 EC: 0000 0021 [4000]
325 13:58:47.296031
326 13:58:47.296371 S7: 0000 0000 [0000]
327 13:58:47.296687
328 13:58:47.299217 CC: 0000 0000 [0001]
329 13:58:47.299643
330 13:58:47.299986 T0: 0000 0040 [010F]
331 13:58:47.300307
332 13:58:47.302490 Jump to BL
333 13:58:47.302930
334 13:58:47.325870
335 13:58:47.326407
336 13:58:47.326750
337 13:58:47.333578 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 13:58:47.337259 ARM64: Exception handlers installed.
339 13:58:47.340781 ARM64: Testing exception
340 13:58:47.344287 ARM64: Done test exception
341 13:58:47.351254 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 13:58:47.361937 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 13:58:47.368680 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 13:58:47.378060 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 13:58:47.384819 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 13:58:47.391207 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 13:58:47.402723 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 13:58:47.409666 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 13:58:47.429221 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 13:58:47.432403 WDT: Last reset was cold boot
351 13:58:47.436102 SPI1(PAD0) initialized at 2873684 Hz
352 13:58:47.439009 SPI5(PAD0) initialized at 992727 Hz
353 13:58:47.442324 VBOOT: Loading verstage.
354 13:58:47.449193 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 13:58:47.452605 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 13:58:47.455686 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 13:58:47.459266 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 13:58:47.466366 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 13:58:47.472972 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 13:58:47.483805 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 13:58:47.484377
362 13:58:47.484750
363 13:58:47.493964 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 13:58:47.497477 ARM64: Exception handlers installed.
365 13:58:47.500637 ARM64: Testing exception
366 13:58:47.501109 ARM64: Done test exception
367 13:58:47.507411 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 13:58:47.511867 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 13:58:47.525305 Probing TPM: . done!
370 13:58:47.525866 TPM ready after 0 ms
371 13:58:47.534044 Connected to device vid:did:rid of 1ae0:0028:00
372 13:58:47.540408 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 13:58:47.605686 Initialized TPM device CR50 revision 0
374 13:58:47.616489 tlcl_send_startup: Startup return code is 0
375 13:58:47.617048 TPM: setup succeeded
376 13:58:47.628083 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 13:58:47.636992 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:58:47.648845 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 13:58:47.658447 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 13:58:47.662113 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 13:58:47.665781 in-header: 03 07 00 00 08 00 00 00
382 13:58:47.669511 in-data: aa e4 47 04 13 02 00 00
383 13:58:47.673231 Chrome EC: UHEPI supported
384 13:58:47.679926 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 13:58:47.683697 in-header: 03 95 00 00 08 00 00 00
386 13:58:47.687250 in-data: 18 20 20 08 00 00 00 00
387 13:58:47.687675 Phase 1
388 13:58:47.690783 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 13:58:47.698985 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 13:58:47.702917 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 13:58:47.706321 Recovery requested (1009000e)
392 13:58:47.714445 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:58:47.720192 tlcl_extend: response is 0
394 13:58:47.729582 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:58:47.734662 tlcl_extend: response is 0
396 13:58:47.741761 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:58:47.761639 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 13:58:47.767895 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:58:47.768369
400 13:58:47.768742
401 13:58:47.778037 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:58:47.781442 ARM64: Exception handlers installed.
403 13:58:47.784277 ARM64: Testing exception
404 13:58:47.784752 ARM64: Done test exception
405 13:58:47.806866 pmic_efuse_setting: Set efuses in 11 msecs
406 13:58:47.810347 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:58:47.816732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:58:47.820781 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:58:47.827704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:58:47.830961 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:58:47.835206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:58:47.842343 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:58:47.846519 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:58:47.850045 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:58:47.853837 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:58:47.860888 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:58:47.864407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:58:47.867675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:58:47.871600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:58:47.879311 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:58:47.886187 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:58:47.890314 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:58:47.897072 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:58:47.900888 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:58:47.908561 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:58:47.912064 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:58:47.919515 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:58:47.922898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:58:47.929882 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:58:47.933662 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:58:47.940991 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:58:47.944842 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:58:47.952174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:58:47.956024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:58:47.962679 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:58:47.966283 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:58:47.969997 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:58:47.977452 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:58:47.981062 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:58:47.984792 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:58:47.992096 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:58:47.995706 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:58:47.999440 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:58:48.006574 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:58:48.010720 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:58:48.014282 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:58:48.017790 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:58:48.025517 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:58:48.028600 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:58:48.032199 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:58:48.036315 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:58:48.040153 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:58:48.043245 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:58:48.050683 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:58:48.054384 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:58:48.058150 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:58:48.062374 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:58:48.069570 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 13:58:48.077108 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:58:48.084909 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:58:48.092178 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:58:48.099866 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:58:48.103412 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:58:48.106271 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:58:48.113276 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:58:48.120621 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3a
467 13:58:48.123997 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:58:48.132155 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 13:58:48.135003 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:58:48.144177 [RTC]rtc_get_frequency_meter,154: input=15, output=853
471 13:58:48.153488 [RTC]rtc_get_frequency_meter,154: input=7, output=725
472 13:58:48.163080 [RTC]rtc_get_frequency_meter,154: input=11, output=790
473 13:58:48.172057 [RTC]rtc_get_frequency_meter,154: input=13, output=821
474 13:58:48.182134 [RTC]rtc_get_frequency_meter,154: input=12, output=805
475 13:58:48.190914 [RTC]rtc_get_frequency_meter,154: input=11, output=788
476 13:58:48.201286 [RTC]rtc_get_frequency_meter,154: input=12, output=806
477 13:58:48.204828 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 13:58:48.211929 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 13:58:48.215499 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 13:58:48.219546 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 13:58:48.223301 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 13:58:48.226756 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 13:58:48.230441 ADC[4]: Raw value=903694 ID=7
484 13:58:48.234181 ADC[3]: Raw value=213916 ID=1
485 13:58:48.234266 RAM Code: 0x71
486 13:58:48.238056 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 13:58:48.245000 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 13:58:48.252592 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 13:58:48.260424 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 13:58:48.264020 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 13:58:48.267354 in-header: 03 07 00 00 08 00 00 00
492 13:58:48.267437 in-data: aa e4 47 04 13 02 00 00
493 13:58:48.271052 Chrome EC: UHEPI supported
494 13:58:48.278048 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 13:58:48.281592 in-header: 03 95 00 00 08 00 00 00
496 13:58:48.285894 in-data: 18 20 20 08 00 00 00 00
497 13:58:48.289317 MRC: failed to locate region type 0.
498 13:58:48.292775 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 13:58:48.296571 DRAM-K: Running full calibration
500 13:58:48.304108 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 13:58:48.304191 header.status = 0x0
502 13:58:48.307491 header.version = 0x6 (expected: 0x6)
503 13:58:48.311212 header.size = 0xd00 (expected: 0xd00)
504 13:58:48.315217 header.flags = 0x0
505 13:58:48.319001 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 13:58:48.338824 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 13:58:48.345754 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 13:58:48.345837 dram_init: ddr_geometry: 2
509 13:58:48.349508 [EMI] MDL number = 2
510 13:58:48.353379 [EMI] Get MDL freq = 0
511 13:58:48.353460 dram_init: ddr_type: 0
512 13:58:48.357238 is_discrete_lpddr4: 1
513 13:58:48.357327 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 13:58:48.357392
515 13:58:48.360806
516 13:58:48.360888 [Bian_co] ETT version 0.0.0.1
517 13:58:48.368277 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 13:58:48.368365
519 13:58:48.371700 dramc_set_vcore_voltage set vcore to 650000
520 13:58:48.371795 Read voltage for 800, 4
521 13:58:48.371864 Vio18 = 0
522 13:58:48.375744 Vcore = 650000
523 13:58:48.375821 Vdram = 0
524 13:58:48.375893 Vddq = 0
525 13:58:48.375954 Vmddr = 0
526 13:58:48.379746 dram_init: config_dvfs: 1
527 13:58:48.385516 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 13:58:48.389188 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 13:58:48.392503 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 13:58:48.399527 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 13:58:48.399612 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 13:58:48.406995 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 13:58:48.407101 MEM_TYPE=3, freq_sel=18
534 13:58:48.410883 sv_algorithm_assistance_LP4_1600
535 13:58:48.414547 ============ PULL DRAM RESETB DOWN ============
536 13:58:48.417961 ========== PULL DRAM RESETB DOWN end =========
537 13:58:48.424745 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 13:58:48.428384 ===================================
539 13:58:48.428464 LPDDR4 DRAM CONFIGURATION
540 13:58:48.431298 ===================================
541 13:58:48.434800 EX_ROW_EN[0] = 0x0
542 13:58:48.434916 EX_ROW_EN[1] = 0x0
543 13:58:48.438487 LP4Y_EN = 0x0
544 13:58:48.441322 WORK_FSP = 0x0
545 13:58:48.441403 WL = 0x2
546 13:58:48.444801 RL = 0x2
547 13:58:48.444873 BL = 0x2
548 13:58:48.448044 RPST = 0x0
549 13:58:48.448117 RD_PRE = 0x0
550 13:58:48.451666 WR_PRE = 0x1
551 13:58:48.451737 WR_PST = 0x0
552 13:58:48.454740 DBI_WR = 0x0
553 13:58:48.454815 DBI_RD = 0x0
554 13:58:48.457874 OTF = 0x1
555 13:58:48.461649 ===================================
556 13:58:48.464580 ===================================
557 13:58:48.464656 ANA top config
558 13:58:48.468583 ===================================
559 13:58:48.471452 DLL_ASYNC_EN = 0
560 13:58:48.474818 ALL_SLAVE_EN = 1
561 13:58:48.474899 NEW_RANK_MODE = 1
562 13:58:48.478061 DLL_IDLE_MODE = 1
563 13:58:48.481320 LP45_APHY_COMB_EN = 1
564 13:58:48.484648 TX_ODT_DIS = 1
565 13:58:48.488245 NEW_8X_MODE = 1
566 13:58:48.488327 ===================================
567 13:58:48.491095 ===================================
568 13:58:48.494780 data_rate = 1600
569 13:58:48.498042 CKR = 1
570 13:58:48.501115 DQ_P2S_RATIO = 8
571 13:58:48.504956 ===================================
572 13:58:48.508750 CA_P2S_RATIO = 8
573 13:58:48.512261 DQ_CA_OPEN = 0
574 13:58:48.512343 DQ_SEMI_OPEN = 0
575 13:58:48.515202 CA_SEMI_OPEN = 0
576 13:58:48.518538 CA_FULL_RATE = 0
577 13:58:48.521815 DQ_CKDIV4_EN = 1
578 13:58:48.525012 CA_CKDIV4_EN = 1
579 13:58:48.525081 CA_PREDIV_EN = 0
580 13:58:48.529123 PH8_DLY = 0
581 13:58:48.532137 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 13:58:48.534962 DQ_AAMCK_DIV = 4
583 13:58:48.538645 CA_AAMCK_DIV = 4
584 13:58:48.541701 CA_ADMCK_DIV = 4
585 13:58:48.541774 DQ_TRACK_CA_EN = 0
586 13:58:48.545067 CA_PICK = 800
587 13:58:48.549035 CA_MCKIO = 800
588 13:58:48.552483 MCKIO_SEMI = 0
589 13:58:48.556535 PLL_FREQ = 3068
590 13:58:48.556648 DQ_UI_PI_RATIO = 32
591 13:58:48.560236 CA_UI_PI_RATIO = 0
592 13:58:48.563962 ===================================
593 13:58:48.567850 ===================================
594 13:58:48.571287 memory_type:LPDDR4
595 13:58:48.571368 GP_NUM : 10
596 13:58:48.575232 SRAM_EN : 1
597 13:58:48.575310 MD32_EN : 0
598 13:58:48.578752 ===================================
599 13:58:48.582366 [ANA_INIT] >>>>>>>>>>>>>>
600 13:58:48.585528 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 13:58:48.588834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 13:58:48.592274 ===================================
603 13:58:48.592354 data_rate = 1600,PCW = 0X7600
604 13:58:48.595801 ===================================
605 13:58:48.598787 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 13:58:48.605535 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:58:48.612517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 13:58:48.615788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 13:58:48.618944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:58:48.621951 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 13:58:48.626014 [ANA_INIT] flow start
612 13:58:48.626086 [ANA_INIT] PLL >>>>>>>>
613 13:58:48.629228 [ANA_INIT] PLL <<<<<<<<
614 13:58:48.632329 [ANA_INIT] MIDPI >>>>>>>>
615 13:58:48.635319 [ANA_INIT] MIDPI <<<<<<<<
616 13:58:48.635389 [ANA_INIT] DLL >>>>>>>>
617 13:58:48.638610 [ANA_INIT] flow end
618 13:58:48.642566 ============ LP4 DIFF to SE enter ============
619 13:58:48.645462 ============ LP4 DIFF to SE exit ============
620 13:58:48.648861 [ANA_INIT] <<<<<<<<<<<<<
621 13:58:48.652231 [Flow] Enable top DCM control >>>>>
622 13:58:48.655326 [Flow] Enable top DCM control <<<<<
623 13:58:48.658475 Enable DLL master slave shuffle
624 13:58:48.665471 ==============================================================
625 13:58:48.665566 Gating Mode config
626 13:58:48.671627 ==============================================================
627 13:58:48.671701 Config description:
628 13:58:48.681954 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 13:58:48.688669 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 13:58:48.695647 SELPH_MODE 0: By rank 1: By Phase
631 13:58:48.698438 ==============================================================
632 13:58:48.702155 GAT_TRACK_EN = 1
633 13:58:48.705478 RX_GATING_MODE = 2
634 13:58:48.708523 RX_GATING_TRACK_MODE = 2
635 13:58:48.712066 SELPH_MODE = 1
636 13:58:48.715237 PICG_EARLY_EN = 1
637 13:58:48.719270 VALID_LAT_VALUE = 1
638 13:58:48.721702 ==============================================================
639 13:58:48.725988 Enter into Gating configuration >>>>
640 13:58:48.728798 Exit from Gating configuration <<<<
641 13:58:48.731752 Enter into DVFS_PRE_config >>>>>
642 13:58:48.745100 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 13:58:48.748184 Exit from DVFS_PRE_config <<<<<
644 13:58:48.751595 Enter into PICG configuration >>>>
645 13:58:48.755420 Exit from PICG configuration <<<<
646 13:58:48.755530 [RX_INPUT] configuration >>>>>
647 13:58:48.758673 [RX_INPUT] configuration <<<<<
648 13:58:48.765053 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 13:58:48.768214 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 13:58:48.774850 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 13:58:48.781847 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 13:58:48.788141 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 13:58:48.794987 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 13:58:48.798299 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 13:58:48.801838 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 13:58:48.808182 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 13:58:48.811424 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 13:58:48.815094 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 13:58:48.817981 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 13:58:48.821356 ===================================
661 13:58:48.824881 LPDDR4 DRAM CONFIGURATION
662 13:58:48.828290 ===================================
663 13:58:48.831835 EX_ROW_EN[0] = 0x0
664 13:58:48.831918 EX_ROW_EN[1] = 0x0
665 13:58:48.834604 LP4Y_EN = 0x0
666 13:58:48.834687 WORK_FSP = 0x0
667 13:58:48.838066 WL = 0x2
668 13:58:48.838147 RL = 0x2
669 13:58:48.841211 BL = 0x2
670 13:58:48.841293 RPST = 0x0
671 13:58:48.845031 RD_PRE = 0x0
672 13:58:48.845112 WR_PRE = 0x1
673 13:58:48.848155 WR_PST = 0x0
674 13:58:48.848236 DBI_WR = 0x0
675 13:58:48.851478 DBI_RD = 0x0
676 13:58:48.855011 OTF = 0x1
677 13:58:48.855147 ===================================
678 13:58:48.861207 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 13:58:48.864550 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 13:58:48.868233 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 13:58:48.871372 ===================================
682 13:58:48.874649 LPDDR4 DRAM CONFIGURATION
683 13:58:48.877727 ===================================
684 13:58:48.881156 EX_ROW_EN[0] = 0x10
685 13:58:48.881237 EX_ROW_EN[1] = 0x0
686 13:58:48.884800 LP4Y_EN = 0x0
687 13:58:48.884880 WORK_FSP = 0x0
688 13:58:48.887787 WL = 0x2
689 13:58:48.887868 RL = 0x2
690 13:58:48.891311 BL = 0x2
691 13:58:48.891392 RPST = 0x0
692 13:58:48.894525 RD_PRE = 0x0
693 13:58:48.894606 WR_PRE = 0x1
694 13:58:48.897611 WR_PST = 0x0
695 13:58:48.897692 DBI_WR = 0x0
696 13:58:48.901158 DBI_RD = 0x0
697 13:58:48.901239 OTF = 0x1
698 13:58:48.904502 ===================================
699 13:58:48.911255 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 13:58:48.916250 nWR fixed to 40
701 13:58:48.919248 [ModeRegInit_LP4] CH0 RK0
702 13:58:48.919331 [ModeRegInit_LP4] CH0 RK1
703 13:58:48.922306 [ModeRegInit_LP4] CH1 RK0
704 13:58:48.925979 [ModeRegInit_LP4] CH1 RK1
705 13:58:48.926062 match AC timing 13
706 13:58:48.932106 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 13:58:48.935586 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 13:58:48.938972 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 13:58:48.945499 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 13:58:48.949005 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 13:58:48.951882 [EMI DOE] emi_dcm 0
712 13:58:48.955324 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 13:58:48.955408 ==
714 13:58:48.958939 Dram Type= 6, Freq= 0, CH_0, rank 0
715 13:58:48.962484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 13:58:48.962595 ==
717 13:58:48.968528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 13:58:48.975356 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 13:58:48.983228 [CA 0] Center 37 (7~68) winsize 62
720 13:58:48.986688 [CA 1] Center 37 (7~68) winsize 62
721 13:58:48.990162 [CA 2] Center 34 (4~65) winsize 62
722 13:58:48.993515 [CA 3] Center 34 (4~65) winsize 62
723 13:58:48.996786 [CA 4] Center 33 (3~64) winsize 62
724 13:58:48.999852 [CA 5] Center 33 (3~64) winsize 62
725 13:58:48.999935
726 13:58:49.002965 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 13:58:49.003081
728 13:58:49.006285 [CATrainingPosCal] consider 1 rank data
729 13:58:49.009614 u2DelayCellTimex100 = 270/100 ps
730 13:58:49.013101 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 13:58:49.019879 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 13:58:49.023360 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 13:58:49.026418 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 13:58:49.029842 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 13:58:49.032835 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 13:58:49.032918
737 13:58:49.036143 CA PerBit enable=1, Macro0, CA PI delay=33
738 13:58:49.036237
739 13:58:49.039586 [CBTSetCACLKResult] CA Dly = 33
740 13:58:49.039668 CS Dly: 5 (0~36)
741 13:58:49.042967 ==
742 13:58:49.043083 Dram Type= 6, Freq= 0, CH_0, rank 1
743 13:58:49.049705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 13:58:49.049789 ==
745 13:58:49.053433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 13:58:49.059480 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 13:58:49.069583 [CA 0] Center 38 (7~69) winsize 63
748 13:58:49.072761 [CA 1] Center 37 (7~68) winsize 62
749 13:58:49.075845 [CA 2] Center 35 (4~66) winsize 63
750 13:58:49.079457 [CA 3] Center 35 (4~66) winsize 63
751 13:58:49.083010 [CA 4] Center 34 (3~65) winsize 63
752 13:58:49.086248 [CA 5] Center 33 (3~64) winsize 62
753 13:58:49.086331
754 13:58:49.089458 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 13:58:49.089541
756 13:58:49.093235 [CATrainingPosCal] consider 2 rank data
757 13:58:49.096565 u2DelayCellTimex100 = 270/100 ps
758 13:58:49.099703 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 13:58:49.102798 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 13:58:49.109591 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 13:58:49.112690 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 13:58:49.115933 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 13:58:49.119739 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 13:58:49.119822
765 13:58:49.122840 CA PerBit enable=1, Macro0, CA PI delay=33
766 13:58:49.122922
767 13:58:49.126072 [CBTSetCACLKResult] CA Dly = 33
768 13:58:49.126155 CS Dly: 6 (0~38)
769 13:58:49.126224
770 13:58:49.129962 ----->DramcWriteLeveling(PI) begin...
771 13:58:49.130049 ==
772 13:58:49.133257 Dram Type= 6, Freq= 0, CH_0, rank 0
773 13:58:49.137388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 13:58:49.140597 ==
775 13:58:49.140680 Write leveling (Byte 0): 31 => 31
776 13:58:49.144745 Write leveling (Byte 1): 26 => 26
777 13:58:49.148095 DramcWriteLeveling(PI) end<-----
778 13:58:49.148178
779 13:58:49.148244 ==
780 13:58:49.151494 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:58:49.154478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:58:49.157892 ==
783 13:58:49.157975 [Gating] SW mode calibration
784 13:58:49.164740 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 13:58:49.171671 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 13:58:49.174781 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:58:49.178124 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 13:58:49.184859 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 13:58:49.188057 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:58:49.191568 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:58:49.198194 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:58:49.201590 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:58:49.204732 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:58:49.211815 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:58:49.214927 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:58:49.218459 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:58:49.224758 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:58:49.228219 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:58:49.231456 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:58:49.238393 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:58:49.241304 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:58:49.244728 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:58:49.251016 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 13:58:49.254984 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 13:58:49.257653 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:58:49.264286 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:58:49.267631 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:58:49.270982 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:58:49.277562 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:58:49.281203 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:58:49.284425 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:58:49.290962 0 9 8 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
813 13:58:49.294256 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
814 13:58:49.297521 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:58:49.304515 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:58:49.307820 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:58:49.310672 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:58:49.317657 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
819 13:58:49.320586 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
820 13:58:49.323852 0 10 8 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 0)
821 13:58:49.330595 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
822 13:58:49.334313 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:58:49.337506 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:58:49.340611 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:58:49.347303 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:58:49.350477 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:58:49.353951 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
828 13:58:49.360669 0 11 8 | B1->B0 | 2a2a 4545 | 0 0 | (0 0) (0 0)
829 13:58:49.364137 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
830 13:58:49.367044 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:58:49.374207 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:58:49.377376 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:58:49.380951 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:58:49.387381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 13:58:49.390565 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 13:58:49.394245 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 13:58:49.400658 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 13:58:49.404103 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:58:49.407059 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:58:49.414728 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:58:49.417674 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:58:49.420889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:58:49.427081 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:58:49.430231 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:58:49.434075 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:58:49.440693 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:58:49.443857 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:58:49.447143 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:58:49.453579 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:58:49.457455 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:58:49.460690 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 13:58:49.463438 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 13:58:49.470236 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 13:58:49.473847 Total UI for P1: 0, mck2ui 16
855 13:58:49.477203 best dqsien dly found for B0: ( 0, 14, 6)
856 13:58:49.480425 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 13:58:49.484078 Total UI for P1: 0, mck2ui 16
858 13:58:49.486670 best dqsien dly found for B1: ( 0, 14, 12)
859 13:58:49.490462 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 13:58:49.494378 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
861 13:58:49.494462
862 13:58:49.497025 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 13:58:49.500264 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
864 13:58:49.503724 [Gating] SW calibration Done
865 13:58:49.503807 ==
866 13:58:49.507540 Dram Type= 6, Freq= 0, CH_0, rank 0
867 13:58:49.510796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 13:58:49.513708 ==
869 13:58:49.513792 RX Vref Scan: 0
870 13:58:49.513858
871 13:58:49.517160 RX Vref 0 -> 0, step: 1
872 13:58:49.517243
873 13:58:49.520442 RX Delay -130 -> 252, step: 16
874 13:58:49.523876 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 13:58:49.527069 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 13:58:49.530673 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 13:58:49.533895 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 13:58:49.540337 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
879 13:58:49.543901 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 13:58:49.547357 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
881 13:58:49.550543 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
882 13:58:49.553844 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 13:58:49.557184 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
884 13:58:49.563906 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 13:58:49.567732 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 13:58:49.570434 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 13:58:49.574000 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 13:58:49.580735 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 13:58:49.584258 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 13:58:49.584341 ==
891 13:58:49.587518 Dram Type= 6, Freq= 0, CH_0, rank 0
892 13:58:49.591042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 13:58:49.591166 ==
894 13:58:49.591233 DQS Delay:
895 13:58:49.593886 DQS0 = 0, DQS1 = 0
896 13:58:49.593969 DQM Delay:
897 13:58:49.597162 DQM0 = 88, DQM1 = 77
898 13:58:49.597245 DQ Delay:
899 13:58:49.601119 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 13:58:49.604004 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
901 13:58:49.607697 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
902 13:58:49.611301 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
903 13:58:49.611383
904 13:58:49.611449
905 13:58:49.611510 ==
906 13:58:49.613914 Dram Type= 6, Freq= 0, CH_0, rank 0
907 13:58:49.617287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 13:58:49.620471 ==
909 13:58:49.620554
910 13:58:49.620621
911 13:58:49.620682 TX Vref Scan disable
912 13:58:49.623892 == TX Byte 0 ==
913 13:58:49.627433 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
914 13:58:49.634457 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
915 13:58:49.634587 == TX Byte 1 ==
916 13:58:49.637050 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
917 13:58:49.643666 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
918 13:58:49.643775 ==
919 13:58:49.647322 Dram Type= 6, Freq= 0, CH_0, rank 0
920 13:58:49.650380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 13:58:49.650478 ==
922 13:58:49.663036 TX Vref=22, minBit 0, minWin=27, winSum=440
923 13:58:49.666382 TX Vref=24, minBit 1, minWin=27, winSum=440
924 13:58:49.670092 TX Vref=26, minBit 0, minWin=27, winSum=441
925 13:58:49.673361 TX Vref=28, minBit 1, minWin=27, winSum=447
926 13:58:49.676565 TX Vref=30, minBit 0, minWin=28, winSum=452
927 13:58:49.684157 TX Vref=32, minBit 2, minWin=27, winSum=447
928 13:58:49.686360 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
929 13:58:49.686444
930 13:58:49.689891 Final TX Range 1 Vref 30
931 13:58:49.689974
932 13:58:49.690040 ==
933 13:58:49.693072 Dram Type= 6, Freq= 0, CH_0, rank 0
934 13:58:49.696456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 13:58:49.696540 ==
936 13:58:49.696608
937 13:58:49.699899
938 13:58:49.699981 TX Vref Scan disable
939 13:58:49.703110 == TX Byte 0 ==
940 13:58:49.706824 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
941 13:58:49.713352 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
942 13:58:49.713436 == TX Byte 1 ==
943 13:58:49.716276 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
944 13:58:49.723348 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
945 13:58:49.723430
946 13:58:49.723496 [DATLAT]
947 13:58:49.723557 Freq=800, CH0 RK0
948 13:58:49.723616
949 13:58:49.726491 DATLAT Default: 0xa
950 13:58:49.726573 0, 0xFFFF, sum = 0
951 13:58:49.730154 1, 0xFFFF, sum = 0
952 13:58:49.730238 2, 0xFFFF, sum = 0
953 13:58:49.733374 3, 0xFFFF, sum = 0
954 13:58:49.736579 4, 0xFFFF, sum = 0
955 13:58:49.736663 5, 0xFFFF, sum = 0
956 13:58:49.739671 6, 0xFFFF, sum = 0
957 13:58:49.739754 7, 0xFFFF, sum = 0
958 13:58:49.743360 8, 0xFFFF, sum = 0
959 13:58:49.743443 9, 0x0, sum = 1
960 13:58:49.743510 10, 0x0, sum = 2
961 13:58:49.746749 11, 0x0, sum = 3
962 13:58:49.746833 12, 0x0, sum = 4
963 13:58:49.749554 best_step = 10
964 13:58:49.749636
965 13:58:49.749702 ==
966 13:58:49.753086 Dram Type= 6, Freq= 0, CH_0, rank 0
967 13:58:49.756802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 13:58:49.756895 ==
969 13:58:49.760041 RX Vref Scan: 1
970 13:58:49.760123
971 13:58:49.760189 Set Vref Range= 32 -> 127
972 13:58:49.763270
973 13:58:49.763352 RX Vref 32 -> 127, step: 1
974 13:58:49.763416
975 13:58:49.766452 RX Delay -95 -> 252, step: 8
976 13:58:49.766534
977 13:58:49.770060 Set Vref, RX VrefLevel [Byte0]: 32
978 13:58:49.773216 [Byte1]: 32
979 13:58:49.773299
980 13:58:49.776624 Set Vref, RX VrefLevel [Byte0]: 33
981 13:58:49.779503 [Byte1]: 33
982 13:58:49.783716
983 13:58:49.783798 Set Vref, RX VrefLevel [Byte0]: 34
984 13:58:49.787056 [Byte1]: 34
985 13:58:49.791349
986 13:58:49.791431 Set Vref, RX VrefLevel [Byte0]: 35
987 13:58:49.794882 [Byte1]: 35
988 13:58:49.799037
989 13:58:49.799159 Set Vref, RX VrefLevel [Byte0]: 36
990 13:58:49.802091 [Byte1]: 36
991 13:58:49.806489
992 13:58:49.806572 Set Vref, RX VrefLevel [Byte0]: 37
993 13:58:49.809771 [Byte1]: 37
994 13:58:49.814252
995 13:58:49.814335 Set Vref, RX VrefLevel [Byte0]: 38
996 13:58:49.817870 [Byte1]: 38
997 13:58:49.822053
998 13:58:49.822135 Set Vref, RX VrefLevel [Byte0]: 39
999 13:58:49.824828 [Byte1]: 39
1000 13:58:49.829880
1001 13:58:49.829962 Set Vref, RX VrefLevel [Byte0]: 40
1002 13:58:49.832761 [Byte1]: 40
1003 13:58:49.836971
1004 13:58:49.837071 Set Vref, RX VrefLevel [Byte0]: 41
1005 13:58:49.839961 [Byte1]: 41
1006 13:58:49.844461
1007 13:58:49.844542 Set Vref, RX VrefLevel [Byte0]: 42
1008 13:58:49.848109 [Byte1]: 42
1009 13:58:49.851849
1010 13:58:49.851930 Set Vref, RX VrefLevel [Byte0]: 43
1011 13:58:49.855398 [Byte1]: 43
1012 13:58:49.859355
1013 13:58:49.859436 Set Vref, RX VrefLevel [Byte0]: 44
1014 13:58:49.862858 [Byte1]: 44
1015 13:58:49.867382
1016 13:58:49.867505 Set Vref, RX VrefLevel [Byte0]: 45
1017 13:58:49.870302 [Byte1]: 45
1018 13:58:49.874531
1019 13:58:49.874611 Set Vref, RX VrefLevel [Byte0]: 46
1020 13:58:49.878029 [Byte1]: 46
1021 13:58:49.882473
1022 13:58:49.882553 Set Vref, RX VrefLevel [Byte0]: 47
1023 13:58:49.886305 [Byte1]: 47
1024 13:58:49.889665
1025 13:58:49.889749 Set Vref, RX VrefLevel [Byte0]: 48
1026 13:58:49.893634 [Byte1]: 48
1027 13:58:49.897284
1028 13:58:49.897364 Set Vref, RX VrefLevel [Byte0]: 49
1029 13:58:49.900887 [Byte1]: 49
1030 13:58:49.905026
1031 13:58:49.905110 Set Vref, RX VrefLevel [Byte0]: 50
1032 13:58:49.908576 [Byte1]: 50
1033 13:58:49.912453
1034 13:58:49.912533 Set Vref, RX VrefLevel [Byte0]: 51
1035 13:58:49.916187 [Byte1]: 51
1036 13:58:49.920401
1037 13:58:49.920480 Set Vref, RX VrefLevel [Byte0]: 52
1038 13:58:49.923670 [Byte1]: 52
1039 13:58:49.927886
1040 13:58:49.927966 Set Vref, RX VrefLevel [Byte0]: 53
1041 13:58:49.931007 [Byte1]: 53
1042 13:58:49.935316
1043 13:58:49.935396 Set Vref, RX VrefLevel [Byte0]: 54
1044 13:58:49.938813 [Byte1]: 54
1045 13:58:49.943015
1046 13:58:49.943152 Set Vref, RX VrefLevel [Byte0]: 55
1047 13:58:49.946508 [Byte1]: 55
1048 13:58:49.950555
1049 13:58:49.950642 Set Vref, RX VrefLevel [Byte0]: 56
1050 13:58:49.953817 [Byte1]: 56
1051 13:58:49.958741
1052 13:58:49.958821 Set Vref, RX VrefLevel [Byte0]: 57
1053 13:58:49.961345 [Byte1]: 57
1054 13:58:49.966102
1055 13:58:49.966182 Set Vref, RX VrefLevel [Byte0]: 58
1056 13:58:49.969291 [Byte1]: 58
1057 13:58:49.973653
1058 13:58:49.973733 Set Vref, RX VrefLevel [Byte0]: 59
1059 13:58:49.976776 [Byte1]: 59
1060 13:58:49.981075
1061 13:58:49.981155 Set Vref, RX VrefLevel [Byte0]: 60
1062 13:58:49.984409 [Byte1]: 60
1063 13:58:49.988462
1064 13:58:49.988542 Set Vref, RX VrefLevel [Byte0]: 61
1065 13:58:49.991768 [Byte1]: 61
1066 13:58:49.996127
1067 13:58:49.996207 Set Vref, RX VrefLevel [Byte0]: 62
1068 13:58:49.999386 [Byte1]: 62
1069 13:58:50.003831
1070 13:58:50.003911 Set Vref, RX VrefLevel [Byte0]: 63
1071 13:58:50.006965 [Byte1]: 63
1072 13:58:50.011517
1073 13:58:50.011597 Set Vref, RX VrefLevel [Byte0]: 64
1074 13:58:50.014860 [Byte1]: 64
1075 13:58:50.018995
1076 13:58:50.019111 Set Vref, RX VrefLevel [Byte0]: 65
1077 13:58:50.022480 [Byte1]: 65
1078 13:58:50.026674
1079 13:58:50.026751 Set Vref, RX VrefLevel [Byte0]: 66
1080 13:58:50.029858 [Byte1]: 66
1081 13:58:50.034218
1082 13:58:50.034290 Set Vref, RX VrefLevel [Byte0]: 67
1083 13:58:50.037213 [Byte1]: 67
1084 13:58:50.041529
1085 13:58:50.041608 Set Vref, RX VrefLevel [Byte0]: 68
1086 13:58:50.045169 [Byte1]: 68
1087 13:58:50.049576
1088 13:58:50.049657 Set Vref, RX VrefLevel [Byte0]: 69
1089 13:58:50.052865 [Byte1]: 69
1090 13:58:50.057303
1091 13:58:50.057375 Set Vref, RX VrefLevel [Byte0]: 70
1092 13:58:50.060932 [Byte1]: 70
1093 13:58:50.064749
1094 13:58:50.064834 Set Vref, RX VrefLevel [Byte0]: 71
1095 13:58:50.067736 [Byte1]: 71
1096 13:58:50.071915
1097 13:58:50.071990 Set Vref, RX VrefLevel [Byte0]: 72
1098 13:58:50.075472 [Byte1]: 72
1099 13:58:50.079904
1100 13:58:50.079980 Set Vref, RX VrefLevel [Byte0]: 73
1101 13:58:50.082841 [Byte1]: 73
1102 13:58:50.087456
1103 13:58:50.087533 Set Vref, RX VrefLevel [Byte0]: 74
1104 13:58:50.090586 [Byte1]: 74
1105 13:58:50.095001
1106 13:58:50.095139 Set Vref, RX VrefLevel [Byte0]: 75
1107 13:58:50.098444 [Byte1]: 75
1108 13:58:50.102422
1109 13:58:50.102504 Set Vref, RX VrefLevel [Byte0]: 76
1110 13:58:50.105989 [Byte1]: 76
1111 13:58:50.110751
1112 13:58:50.110857 Final RX Vref Byte 0 = 54 to rank0
1113 13:58:50.114113 Final RX Vref Byte 1 = 61 to rank0
1114 13:58:50.116835 Final RX Vref Byte 0 = 54 to rank1
1115 13:58:50.120377 Final RX Vref Byte 1 = 61 to rank1==
1116 13:58:50.123646 Dram Type= 6, Freq= 0, CH_0, rank 0
1117 13:58:50.130309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1118 13:58:50.130391 ==
1119 13:58:50.130455 DQS Delay:
1120 13:58:50.130513 DQS0 = 0, DQS1 = 0
1121 13:58:50.133552 DQM Delay:
1122 13:58:50.133632 DQM0 = 88, DQM1 = 76
1123 13:58:50.137047 DQ Delay:
1124 13:58:50.140317 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1125 13:58:50.143730 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1126 13:58:50.143810 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =72
1127 13:58:50.149877 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1128 13:58:50.149957
1129 13:58:50.150021
1130 13:58:50.157038 [DQSOSCAuto] RK0, (LSB)MR18= 0x312a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1131 13:58:50.159813 CH0 RK0: MR19=606, MR18=312A
1132 13:58:50.166201 CH0_RK0: MR19=0x606, MR18=0x312A, DQSOSC=397, MR23=63, INC=93, DEC=62
1133 13:58:50.166280
1134 13:58:50.170285 ----->DramcWriteLeveling(PI) begin...
1135 13:58:50.170370 ==
1136 13:58:50.172976 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 13:58:50.176374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 13:58:50.176450 ==
1139 13:58:50.179944 Write leveling (Byte 0): 32 => 32
1140 13:58:50.183267 Write leveling (Byte 1): 27 => 27
1141 13:58:50.186912 DramcWriteLeveling(PI) end<-----
1142 13:58:50.186987
1143 13:58:50.187058 ==
1144 13:58:50.189441 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 13:58:50.234432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 13:58:50.234529 ==
1147 13:58:50.234599 [Gating] SW mode calibration
1148 13:58:50.235288 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1149 13:58:50.235733 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1150 13:58:50.235810 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 13:58:50.236364 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1152 13:58:50.236618 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:58:50.236872 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:58:50.236961 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:58:50.237033 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:58:50.246826 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:58:50.247138 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:58:50.250683 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:58:50.254295 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:58:50.257380 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:58:50.260558 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:58:50.266839 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:58:50.270216 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:58:50.273376 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:58:50.280340 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:58:50.283604 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 13:58:50.286767 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1168 13:58:50.293496 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1169 13:58:50.297152 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:58:50.300252 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:58:50.306943 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:58:50.310229 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:58:50.313871 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:58:50.320137 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:58:50.323804 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:58:50.327016 0 9 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
1177 13:58:50.333376 0 9 12 | B1->B0 | 3433 3434 | 1 1 | (1 1) (1 1)
1178 13:58:50.337051 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 13:58:50.339936 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 13:58:50.346426 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:58:50.349687 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 13:58:50.353055 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 13:58:50.359892 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1184 13:58:50.363245 0 10 8 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
1185 13:58:50.366314 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:58:50.373260 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:58:50.376945 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:58:50.381153 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:58:50.383941 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:58:50.387574 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:58:50.394408 0 11 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
1192 13:58:50.397966 0 11 8 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
1193 13:58:50.401109 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 13:58:50.408572 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 13:58:50.411817 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 13:58:50.414881 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:58:50.421597 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:58:50.424415 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 13:58:50.427846 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1200 13:58:50.434384 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1201 13:58:50.437992 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:58:50.441200 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:58:50.444648 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:58:50.451506 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:58:50.454612 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:58:50.457894 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:58:50.464874 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:58:50.467671 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:58:50.470983 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:58:50.477963 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:58:50.480934 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:58:50.484655 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:58:50.491519 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:58:50.494570 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:58:50.498155 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1216 13:58:50.504554 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1217 13:58:50.504635 Total UI for P1: 0, mck2ui 16
1218 13:58:50.510994 best dqsien dly found for B0: ( 0, 14, 4)
1219 13:58:50.514314 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 13:58:50.517664 Total UI for P1: 0, mck2ui 16
1221 13:58:50.520960 best dqsien dly found for B1: ( 0, 14, 8)
1222 13:58:50.524637 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1223 13:58:50.527819 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1224 13:58:50.527892
1225 13:58:50.531309 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1226 13:58:50.534261 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1227 13:58:50.537889 [Gating] SW calibration Done
1228 13:58:50.537964 ==
1229 13:58:50.541139 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 13:58:50.544908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 13:58:50.544983 ==
1232 13:58:50.547710 RX Vref Scan: 0
1233 13:58:50.547784
1234 13:58:50.550989 RX Vref 0 -> 0, step: 1
1235 13:58:50.551063
1236 13:58:50.551177 RX Delay -130 -> 252, step: 16
1237 13:58:50.557940 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1238 13:58:50.561193 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1239 13:58:50.564648 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1240 13:58:50.568004 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1241 13:58:50.571588 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1242 13:58:50.578559 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1243 13:58:50.581240 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1244 13:58:50.584677 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1245 13:58:50.588002 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1246 13:58:50.591467 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1247 13:58:50.598034 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1248 13:58:50.601792 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1249 13:58:50.604356 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1250 13:58:50.607766 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1251 13:58:50.614525 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1252 13:58:50.617543 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1253 13:58:50.617627 ==
1254 13:58:50.620855 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 13:58:50.624219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 13:58:50.624297 ==
1257 13:58:50.624383 DQS Delay:
1258 13:58:50.627985 DQS0 = 0, DQS1 = 0
1259 13:58:50.628065 DQM Delay:
1260 13:58:50.631371 DQM0 = 90, DQM1 = 78
1261 13:58:50.631451 DQ Delay:
1262 13:58:50.634535 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
1263 13:58:50.637526 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1264 13:58:50.641081 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1265 13:58:50.644494 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1266 13:58:50.644593
1267 13:58:50.644678
1268 13:58:50.644758 ==
1269 13:58:50.647780 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 13:58:50.650748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 13:58:50.654061 ==
1272 13:58:50.654138
1273 13:58:50.654219
1274 13:58:50.654298 TX Vref Scan disable
1275 13:58:50.657491 == TX Byte 0 ==
1276 13:58:50.661056 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1277 13:58:50.664105 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1278 13:58:50.667770 == TX Byte 1 ==
1279 13:58:50.671114 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1280 13:58:50.674240 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1281 13:58:50.674319 ==
1282 13:58:50.677606 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 13:58:50.684299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 13:58:50.684382 ==
1285 13:58:50.697249 TX Vref=22, minBit 0, minWin=27, winSum=441
1286 13:58:50.699858 TX Vref=24, minBit 1, minWin=27, winSum=448
1287 13:58:50.703404 TX Vref=26, minBit 1, minWin=27, winSum=447
1288 13:58:50.706858 TX Vref=28, minBit 1, minWin=27, winSum=450
1289 13:58:50.710174 TX Vref=30, minBit 1, minWin=27, winSum=448
1290 13:58:50.713453 TX Vref=32, minBit 1, minWin=27, winSum=449
1291 13:58:50.720034 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 28
1292 13:58:50.720113
1293 13:58:50.723567 Final TX Range 1 Vref 28
1294 13:58:50.723640
1295 13:58:50.723706 ==
1296 13:58:50.727032 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 13:58:50.730265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 13:58:50.730340 ==
1299 13:58:50.733051
1300 13:58:50.733125
1301 13:58:50.733191 TX Vref Scan disable
1302 13:58:50.736710 == TX Byte 0 ==
1303 13:58:50.740682 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1304 13:58:50.743462 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1305 13:58:50.746864 == TX Byte 1 ==
1306 13:58:50.750186 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1307 13:58:50.753227 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1308 13:58:50.756877
1309 13:58:50.756952 [DATLAT]
1310 13:58:50.757016 Freq=800, CH0 RK1
1311 13:58:50.757081
1312 13:58:50.760395 DATLAT Default: 0xa
1313 13:58:50.760479 0, 0xFFFF, sum = 0
1314 13:58:50.763603 1, 0xFFFF, sum = 0
1315 13:58:50.763684 2, 0xFFFF, sum = 0
1316 13:58:50.766679 3, 0xFFFF, sum = 0
1317 13:58:50.769803 4, 0xFFFF, sum = 0
1318 13:58:50.769886 5, 0xFFFF, sum = 0
1319 13:58:50.773505 6, 0xFFFF, sum = 0
1320 13:58:50.773593 7, 0xFFFF, sum = 0
1321 13:58:50.776284 8, 0xFFFF, sum = 0
1322 13:58:50.776365 9, 0x0, sum = 1
1323 13:58:50.779562 10, 0x0, sum = 2
1324 13:58:50.779644 11, 0x0, sum = 3
1325 13:58:50.779709 12, 0x0, sum = 4
1326 13:58:50.783377 best_step = 10
1327 13:58:50.783482
1328 13:58:50.783554 ==
1329 13:58:50.786420 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 13:58:50.789617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 13:58:50.789698 ==
1332 13:58:50.793159 RX Vref Scan: 0
1333 13:58:50.793239
1334 13:58:50.793303 RX Vref 0 -> 0, step: 1
1335 13:58:50.796345
1336 13:58:50.796423 RX Delay -95 -> 252, step: 8
1337 13:58:50.803457 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1338 13:58:50.806786 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1339 13:58:50.810137 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1340 13:58:50.813532 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1341 13:58:50.816871 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1342 13:58:50.823276 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1343 13:58:50.826657 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1344 13:58:50.829883 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1345 13:58:50.833441 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1346 13:58:50.836890 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1347 13:58:50.843564 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1348 13:58:50.846522 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1349 13:58:50.849610 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1350 13:58:50.853294 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1351 13:58:50.859611 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1352 13:58:50.863299 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1353 13:58:50.863373 ==
1354 13:58:50.866344 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 13:58:50.869592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 13:58:50.869671 ==
1357 13:58:50.872684 DQS Delay:
1358 13:58:50.872755 DQS0 = 0, DQS1 = 0
1359 13:58:50.872824 DQM Delay:
1360 13:58:50.876947 DQM0 = 86, DQM1 = 76
1361 13:58:50.877028 DQ Delay:
1362 13:58:50.879810 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1363 13:58:50.883003 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1364 13:58:50.886065 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1365 13:58:50.889603 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1366 13:58:50.889686
1367 13:58:50.889765
1368 13:58:50.899760 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1369 13:58:50.899840 CH0 RK1: MR19=606, MR18=2C28
1370 13:58:50.906399 CH0_RK1: MR19=0x606, MR18=0x2C28, DQSOSC=398, MR23=63, INC=93, DEC=62
1371 13:58:50.909913 [RxdqsGatingPostProcess] freq 800
1372 13:58:50.916538 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 13:58:50.919670 Pre-setting of DQS Precalculation
1374 13:58:50.922921 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 13:58:50.923002 ==
1376 13:58:50.926069 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 13:58:50.932909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 13:58:50.932991 ==
1379 13:58:50.936084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 13:58:50.942885 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 13:58:50.952039 [CA 0] Center 36 (6~67) winsize 62
1382 13:58:50.955002 [CA 1] Center 36 (6~67) winsize 62
1383 13:58:50.958058 [CA 2] Center 35 (5~65) winsize 61
1384 13:58:50.961357 [CA 3] Center 34 (4~65) winsize 62
1385 13:58:50.964982 [CA 4] Center 34 (4~65) winsize 62
1386 13:58:50.968248 [CA 5] Center 34 (3~65) winsize 63
1387 13:58:50.968328
1388 13:58:50.971613 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1389 13:58:50.971738
1390 13:58:50.974971 [CATrainingPosCal] consider 1 rank data
1391 13:58:50.977922 u2DelayCellTimex100 = 270/100 ps
1392 13:58:50.981551 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 13:58:50.988017 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1394 13:58:50.991423 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1395 13:58:50.994774 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 13:58:50.998093 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 13:58:51.001039 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1398 13:58:51.001122
1399 13:58:51.005111 CA PerBit enable=1, Macro0, CA PI delay=34
1400 13:58:51.005189
1401 13:58:51.008061 [CBTSetCACLKResult] CA Dly = 34
1402 13:58:51.011233 CS Dly: 4 (0~35)
1403 13:58:51.011310 ==
1404 13:58:51.014589 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 13:58:51.018223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 13:58:51.018300 ==
1407 13:58:51.021277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 13:58:51.028005 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 13:58:51.037934 [CA 0] Center 36 (6~67) winsize 62
1410 13:58:51.041650 [CA 1] Center 36 (6~67) winsize 62
1411 13:58:51.045173 [CA 2] Center 34 (4~65) winsize 62
1412 13:58:51.048526 [CA 3] Center 34 (3~65) winsize 63
1413 13:58:51.051618 [CA 4] Center 34 (3~65) winsize 63
1414 13:58:51.055443 [CA 5] Center 33 (3~64) winsize 62
1415 13:58:51.055553
1416 13:58:51.058897 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1417 13:58:51.059006
1418 13:58:51.062796 [CATrainingPosCal] consider 2 rank data
1419 13:58:51.066352 u2DelayCellTimex100 = 270/100 ps
1420 13:58:51.069795 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1421 13:58:51.073754 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1422 13:58:51.077369 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1423 13:58:51.080479 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 13:58:51.084216 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1425 13:58:51.087283 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1426 13:58:51.087360
1427 13:58:51.090649 CA PerBit enable=1, Macro0, CA PI delay=33
1428 13:58:51.090725
1429 13:58:51.094202 [CBTSetCACLKResult] CA Dly = 33
1430 13:58:51.097224 CS Dly: 5 (0~37)
1431 13:58:51.097303
1432 13:58:51.100524 ----->DramcWriteLeveling(PI) begin...
1433 13:58:51.100602 ==
1434 13:58:51.103972 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 13:58:51.106978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 13:58:51.107052 ==
1437 13:58:51.110636 Write leveling (Byte 0): 25 => 25
1438 13:58:51.113898 Write leveling (Byte 1): 26 => 26
1439 13:58:51.117017 DramcWriteLeveling(PI) end<-----
1440 13:58:51.117090
1441 13:58:51.117170 ==
1442 13:58:51.120508 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 13:58:51.124287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 13:58:51.124364 ==
1445 13:58:51.127222 [Gating] SW mode calibration
1446 13:58:51.133991 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 13:58:51.140536 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 13:58:51.144076 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 13:58:51.147299 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 13:58:51.153563 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:58:51.156957 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:58:51.160692 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:58:51.167284 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:58:51.170395 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:58:51.173667 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:58:51.180231 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:58:51.183769 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:58:51.186990 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:58:51.193635 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:58:51.196813 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:58:51.200544 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:58:51.206958 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:58:51.210027 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:58:51.213522 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:58:51.217371 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 13:58:51.223640 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:58:51.226699 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:58:51.230215 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:58:51.236503 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:58:51.239787 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:58:51.243347 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:58:51.250367 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:58:51.253330 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1474 13:58:51.256772 0 9 8 | B1->B0 | 2e2e 3333 | 0 1 | (0 0) (1 1)
1475 13:58:51.263087 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 13:58:51.266636 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 13:58:51.270088 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 13:58:51.276917 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 13:58:51.280428 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 13:58:51.283093 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 13:58:51.290060 0 10 4 | B1->B0 | 3232 3030 | 1 1 | (1 1) (1 0)
1482 13:58:51.293226 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
1483 13:58:51.296954 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:58:51.303471 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:58:51.306680 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:58:51.309794 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:58:51.316485 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:58:51.320283 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:58:51.322975 0 11 4 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
1490 13:58:51.329910 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1491 13:58:51.333530 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 13:58:51.336743 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 13:58:51.339937 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 13:58:51.346776 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:58:51.349990 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 13:58:51.353563 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 13:58:51.359597 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 13:58:51.363451 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:58:51.366899 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:58:51.373112 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:58:51.376374 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:58:51.379861 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:58:51.386247 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:58:51.389679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:58:51.393282 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:58:51.400029 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:58:51.402793 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:58:51.406146 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:58:51.413460 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:58:51.416140 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:58:51.419550 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:58:51.426376 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:58:51.429841 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1514 13:58:51.433044 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1515 13:58:51.435968 Total UI for P1: 0, mck2ui 16
1516 13:58:51.439295 best dqsien dly found for B1: ( 0, 14, 6)
1517 13:58:51.446335 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 13:58:51.446424 Total UI for P1: 0, mck2ui 16
1519 13:58:51.449999 best dqsien dly found for B0: ( 0, 14, 6)
1520 13:58:51.456429 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1521 13:58:51.459259 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1522 13:58:51.459339
1523 13:58:51.462946 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 13:58:51.466101 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 13:58:51.469431 [Gating] SW calibration Done
1526 13:58:51.469511 ==
1527 13:58:51.472738 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 13:58:51.476406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 13:58:51.476487 ==
1530 13:58:51.479163 RX Vref Scan: 0
1531 13:58:51.479243
1532 13:58:51.479306 RX Vref 0 -> 0, step: 1
1533 13:58:51.479365
1534 13:58:51.482488 RX Delay -130 -> 252, step: 16
1535 13:58:51.486338 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1536 13:58:51.492933 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1537 13:58:51.496161 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1538 13:58:51.499326 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1539 13:58:51.502671 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1540 13:58:51.506044 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1541 13:58:51.512896 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1542 13:58:51.516110 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1543 13:58:51.519673 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1544 13:58:51.523083 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1545 13:58:51.526028 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1546 13:58:51.532856 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1547 13:58:51.535808 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1548 13:58:51.539044 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1549 13:58:51.542598 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1550 13:58:51.546034 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1551 13:58:51.546114 ==
1552 13:58:51.549133 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 13:58:51.556278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 13:58:51.556359 ==
1555 13:58:51.556424 DQS Delay:
1556 13:58:51.559193 DQS0 = 0, DQS1 = 0
1557 13:58:51.559273 DQM Delay:
1558 13:58:51.562723 DQM0 = 88, DQM1 = 86
1559 13:58:51.562835 DQ Delay:
1560 13:58:51.565531 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1561 13:58:51.568964 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1562 13:58:51.572507 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1563 13:58:51.576175 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1564 13:58:51.576255
1565 13:58:51.576318
1566 13:58:51.576377 ==
1567 13:58:51.579294 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 13:58:51.582667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 13:58:51.582753 ==
1570 13:58:51.582859
1571 13:58:51.582958
1572 13:58:51.585921 TX Vref Scan disable
1573 13:58:51.589352 == TX Byte 0 ==
1574 13:58:51.592379 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1575 13:58:51.595627 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1576 13:58:51.599226 == TX Byte 1 ==
1577 13:58:51.602521 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1578 13:58:51.605620 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1579 13:58:51.605694 ==
1580 13:58:51.608857 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 13:58:51.612547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 13:58:51.615416 ==
1583 13:58:51.627664 TX Vref=22, minBit 0, minWin=27, winSum=441
1584 13:58:51.630975 TX Vref=24, minBit 2, minWin=26, winSum=446
1585 13:58:51.634160 TX Vref=26, minBit 5, minWin=27, winSum=449
1586 13:58:51.637648 TX Vref=28, minBit 4, minWin=27, winSum=454
1587 13:58:51.641109 TX Vref=30, minBit 0, minWin=28, winSum=456
1588 13:58:51.644402 TX Vref=32, minBit 3, minWin=27, winSum=455
1589 13:58:51.650877 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1590 13:58:51.650958
1591 13:58:51.653976 Final TX Range 1 Vref 30
1592 13:58:51.654057
1593 13:58:51.654120 ==
1594 13:58:51.657407 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 13:58:51.660497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 13:58:51.660578 ==
1597 13:58:51.660642
1598 13:58:51.660702
1599 13:58:51.664039 TX Vref Scan disable
1600 13:58:51.667359 == TX Byte 0 ==
1601 13:58:51.670405 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1602 13:58:51.673823 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1603 13:58:51.677070 == TX Byte 1 ==
1604 13:58:51.680572 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1605 13:58:51.683797 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1606 13:58:51.683897
1607 13:58:51.686947 [DATLAT]
1608 13:58:51.687027 Freq=800, CH1 RK0
1609 13:58:51.687124
1610 13:58:51.690478 DATLAT Default: 0xa
1611 13:58:51.690552 0, 0xFFFF, sum = 0
1612 13:58:51.693952 1, 0xFFFF, sum = 0
1613 13:58:51.694027 2, 0xFFFF, sum = 0
1614 13:58:51.696974 3, 0xFFFF, sum = 0
1615 13:58:51.697050 4, 0xFFFF, sum = 0
1616 13:58:51.700383 5, 0xFFFF, sum = 0
1617 13:58:51.700461 6, 0xFFFF, sum = 0
1618 13:58:51.704473 7, 0xFFFF, sum = 0
1619 13:58:51.704556 8, 0xFFFF, sum = 0
1620 13:58:51.707492 9, 0x0, sum = 1
1621 13:58:51.707574 10, 0x0, sum = 2
1622 13:58:51.710210 11, 0x0, sum = 3
1623 13:58:51.710291 12, 0x0, sum = 4
1624 13:58:51.713689 best_step = 10
1625 13:58:51.713769
1626 13:58:51.713834 ==
1627 13:58:51.716908 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 13:58:51.720358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 13:58:51.720439 ==
1630 13:58:51.723305 RX Vref Scan: 1
1631 13:58:51.723384
1632 13:58:51.723466 Set Vref Range= 32 -> 127
1633 13:58:51.723543
1634 13:58:51.726690 RX Vref 32 -> 127, step: 1
1635 13:58:51.726761
1636 13:58:51.730285 RX Delay -95 -> 252, step: 8
1637 13:58:51.730362
1638 13:58:51.733673 Set Vref, RX VrefLevel [Byte0]: 32
1639 13:58:51.737026 [Byte1]: 32
1640 13:58:51.737099
1641 13:58:51.740179 Set Vref, RX VrefLevel [Byte0]: 33
1642 13:58:51.743088 [Byte1]: 33
1643 13:58:51.747248
1644 13:58:51.747325 Set Vref, RX VrefLevel [Byte0]: 34
1645 13:58:51.750456 [Byte1]: 34
1646 13:58:51.754359
1647 13:58:51.754434 Set Vref, RX VrefLevel [Byte0]: 35
1648 13:58:51.757965 [Byte1]: 35
1649 13:58:51.761924
1650 13:58:51.761997 Set Vref, RX VrefLevel [Byte0]: 36
1651 13:58:51.765583 [Byte1]: 36
1652 13:58:51.769940
1653 13:58:51.770014 Set Vref, RX VrefLevel [Byte0]: 37
1654 13:58:51.772833 [Byte1]: 37
1655 13:58:51.777586
1656 13:58:51.777665 Set Vref, RX VrefLevel [Byte0]: 38
1657 13:58:51.781017 [Byte1]: 38
1658 13:58:51.784840
1659 13:58:51.784920 Set Vref, RX VrefLevel [Byte0]: 39
1660 13:58:51.788231 [Byte1]: 39
1661 13:58:51.793055
1662 13:58:51.793139 Set Vref, RX VrefLevel [Byte0]: 40
1663 13:58:51.795930 [Byte1]: 40
1664 13:58:51.800811
1665 13:58:51.800924 Set Vref, RX VrefLevel [Byte0]: 41
1666 13:58:51.803559 [Byte1]: 41
1667 13:58:51.808092
1668 13:58:51.808171 Set Vref, RX VrefLevel [Byte0]: 42
1669 13:58:51.811296 [Byte1]: 42
1670 13:58:51.815198
1671 13:58:51.815271 Set Vref, RX VrefLevel [Byte0]: 43
1672 13:58:51.819206 [Byte1]: 43
1673 13:58:51.823018
1674 13:58:51.823098 Set Vref, RX VrefLevel [Byte0]: 44
1675 13:58:51.826152 [Byte1]: 44
1676 13:58:51.830990
1677 13:58:51.831066 Set Vref, RX VrefLevel [Byte0]: 45
1678 13:58:51.834059 [Byte1]: 45
1679 13:58:51.838332
1680 13:58:51.838411 Set Vref, RX VrefLevel [Byte0]: 46
1681 13:58:51.841619 [Byte1]: 46
1682 13:58:51.845899
1683 13:58:51.845971 Set Vref, RX VrefLevel [Byte0]: 47
1684 13:58:51.849378 [Byte1]: 47
1685 13:58:51.853252
1686 13:58:51.853332 Set Vref, RX VrefLevel [Byte0]: 48
1687 13:58:51.857026 [Byte1]: 48
1688 13:58:51.861064
1689 13:58:51.861138 Set Vref, RX VrefLevel [Byte0]: 49
1690 13:58:51.864265 [Byte1]: 49
1691 13:58:51.868323
1692 13:58:51.868397 Set Vref, RX VrefLevel [Byte0]: 50
1693 13:58:51.871768 [Byte1]: 50
1694 13:58:51.876205
1695 13:58:51.876290 Set Vref, RX VrefLevel [Byte0]: 51
1696 13:58:51.879444 [Byte1]: 51
1697 13:58:51.884616
1698 13:58:51.884694 Set Vref, RX VrefLevel [Byte0]: 52
1699 13:58:51.887021 [Byte1]: 52
1700 13:58:51.891467
1701 13:58:51.891547 Set Vref, RX VrefLevel [Byte0]: 53
1702 13:58:51.894642 [Byte1]: 53
1703 13:58:51.898931
1704 13:58:51.899007 Set Vref, RX VrefLevel [Byte0]: 54
1705 13:58:51.902129 [Byte1]: 54
1706 13:58:51.906483
1707 13:58:51.906555 Set Vref, RX VrefLevel [Byte0]: 55
1708 13:58:51.909769 [Byte1]: 55
1709 13:58:51.914243
1710 13:58:51.914319 Set Vref, RX VrefLevel [Byte0]: 56
1711 13:58:51.917277 [Byte1]: 56
1712 13:58:51.921743
1713 13:58:51.921817 Set Vref, RX VrefLevel [Byte0]: 57
1714 13:58:51.924883 [Byte1]: 57
1715 13:58:51.929473
1716 13:58:51.929544 Set Vref, RX VrefLevel [Byte0]: 58
1717 13:58:51.933090 [Byte1]: 58
1718 13:58:51.937444
1719 13:58:51.937517 Set Vref, RX VrefLevel [Byte0]: 59
1720 13:58:51.940245 [Byte1]: 59
1721 13:58:51.944339
1722 13:58:51.944419 Set Vref, RX VrefLevel [Byte0]: 60
1723 13:58:51.947612 [Byte1]: 60
1724 13:58:51.952364
1725 13:58:51.952437 Set Vref, RX VrefLevel [Byte0]: 61
1726 13:58:51.955421 [Byte1]: 61
1727 13:58:51.959642
1728 13:58:51.959718 Set Vref, RX VrefLevel [Byte0]: 62
1729 13:58:51.962981 [Byte1]: 62
1730 13:58:51.967839
1731 13:58:51.967914 Set Vref, RX VrefLevel [Byte0]: 63
1732 13:58:51.970583 [Byte1]: 63
1733 13:58:51.974724
1734 13:58:51.974804 Set Vref, RX VrefLevel [Byte0]: 64
1735 13:58:51.978111 [Byte1]: 64
1736 13:58:51.982756
1737 13:58:51.982833 Set Vref, RX VrefLevel [Byte0]: 65
1738 13:58:51.985772 [Byte1]: 65
1739 13:58:51.990142
1740 13:58:51.990220 Set Vref, RX VrefLevel [Byte0]: 66
1741 13:58:51.993759 [Byte1]: 66
1742 13:58:51.998381
1743 13:58:51.998459 Set Vref, RX VrefLevel [Byte0]: 67
1744 13:58:52.001176 [Byte1]: 67
1745 13:58:52.005590
1746 13:58:52.005671 Set Vref, RX VrefLevel [Byte0]: 68
1747 13:58:52.008888 [Byte1]: 68
1748 13:58:52.013531
1749 13:58:52.013610 Set Vref, RX VrefLevel [Byte0]: 69
1750 13:58:52.016311 [Byte1]: 69
1751 13:58:52.020540
1752 13:58:52.020616 Set Vref, RX VrefLevel [Byte0]: 70
1753 13:58:52.023748 [Byte1]: 70
1754 13:58:52.028104
1755 13:58:52.028177 Set Vref, RX VrefLevel [Byte0]: 71
1756 13:58:52.031474 [Byte1]: 71
1757 13:58:52.036045
1758 13:58:52.036123 Set Vref, RX VrefLevel [Byte0]: 72
1759 13:58:52.038817 [Byte1]: 72
1760 13:58:52.043472
1761 13:58:52.043552 Set Vref, RX VrefLevel [Byte0]: 73
1762 13:58:52.046773 [Byte1]: 73
1763 13:58:52.051280
1764 13:58:52.051353 Set Vref, RX VrefLevel [Byte0]: 74
1765 13:58:52.054304 [Byte1]: 74
1766 13:58:52.058832
1767 13:58:52.058904 Set Vref, RX VrefLevel [Byte0]: 75
1768 13:58:52.062172 [Byte1]: 75
1769 13:58:52.066011
1770 13:58:52.066082 Set Vref, RX VrefLevel [Byte0]: 76
1771 13:58:52.069206 [Byte1]: 76
1772 13:58:52.073494
1773 13:58:52.073575 Final RX Vref Byte 0 = 54 to rank0
1774 13:58:52.076817 Final RX Vref Byte 1 = 56 to rank0
1775 13:58:52.080343 Final RX Vref Byte 0 = 54 to rank1
1776 13:58:52.083517 Final RX Vref Byte 1 = 56 to rank1==
1777 13:58:52.086827 Dram Type= 6, Freq= 0, CH_1, rank 0
1778 13:58:52.093277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1779 13:58:52.093355 ==
1780 13:58:52.093439 DQS Delay:
1781 13:58:52.096873 DQS0 = 0, DQS1 = 0
1782 13:58:52.096946 DQM Delay:
1783 13:58:52.097025 DQM0 = 85, DQM1 = 79
1784 13:58:52.100096 DQ Delay:
1785 13:58:52.103482 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1786 13:58:52.106823 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =84
1787 13:58:52.110383 DQ8 =68, DQ9 =72, DQ10 =76, DQ11 =72
1788 13:58:52.113353 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1789 13:58:52.113433
1790 13:58:52.113515
1791 13:58:52.120377 [DQSOSCAuto] RK0, (LSB)MR18= 0x182b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1792 13:58:52.123785 CH1 RK0: MR19=606, MR18=182B
1793 13:58:52.130219 CH1_RK0: MR19=0x606, MR18=0x182B, DQSOSC=398, MR23=63, INC=93, DEC=62
1794 13:58:52.130299
1795 13:58:52.133248 ----->DramcWriteLeveling(PI) begin...
1796 13:58:52.133325 ==
1797 13:58:52.137025 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 13:58:52.140021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 13:58:52.140101 ==
1800 13:58:52.143380 Write leveling (Byte 0): 27 => 27
1801 13:58:52.146581 Write leveling (Byte 1): 31 => 31
1802 13:58:52.150802 DramcWriteLeveling(PI) end<-----
1803 13:58:52.150879
1804 13:58:52.150982 ==
1805 13:58:52.153661 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 13:58:52.156929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 13:58:52.157006 ==
1808 13:58:52.160300 [Gating] SW mode calibration
1809 13:58:52.167049 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1810 13:58:52.173591 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1811 13:58:52.176811 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1812 13:58:52.180035 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1813 13:58:52.186595 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:58:52.189930 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:58:52.193036 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:58:52.200021 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:58:52.203049 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:58:52.206539 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:58:52.213323 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:58:52.216712 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:58:52.220307 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:58:52.226502 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:58:52.229836 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:58:52.233410 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:58:52.239481 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:58:52.242984 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:58:52.246436 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:58:52.252772 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1829 13:58:52.256035 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1830 13:58:52.259801 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:58:52.266502 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:58:52.269530 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:58:52.272745 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:58:52.279779 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 13:58:52.283000 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 13:58:52.286191 0 9 4 | B1->B0 | 2323 3131 | 0 0 | (1 1) (0 0)
1837 13:58:52.292677 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
1838 13:58:52.296553 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 13:58:52.299408 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 13:58:52.302774 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 13:58:52.309567 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 13:58:52.313119 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 13:58:52.316159 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1844 13:58:52.322693 0 10 4 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
1845 13:58:52.325825 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1846 13:58:52.329048 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:58:52.335735 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:58:52.339599 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 13:58:52.342432 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 13:58:52.349585 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 13:58:52.352693 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1852 13:58:52.356126 0 11 4 | B1->B0 | 2828 4141 | 0 0 | (0 0) (1 1)
1853 13:58:52.362643 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1854 13:58:52.366029 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 13:58:52.369530 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 13:58:52.375830 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 13:58:52.379336 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 13:58:52.382493 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 13:58:52.389158 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 13:58:52.392984 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1861 13:58:52.396047 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:58:52.402581 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:58:52.405891 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:58:52.409044 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:58:52.415600 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:58:52.419058 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:58:52.422347 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:58:52.429102 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:58:52.432462 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:58:52.435704 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:58:52.439626 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:58:52.445491 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 13:58:52.449291 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 13:58:52.452295 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 13:58:52.459110 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1876 13:58:52.462636 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1877 13:58:52.465679 Total UI for P1: 0, mck2ui 16
1878 13:58:52.468728 best dqsien dly found for B0: ( 0, 14, 0)
1879 13:58:52.472221 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1880 13:58:52.478979 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 13:58:52.481999 Total UI for P1: 0, mck2ui 16
1882 13:58:52.485584 best dqsien dly found for B1: ( 0, 14, 6)
1883 13:58:52.489297 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1884 13:58:52.492040 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1885 13:58:52.492112
1886 13:58:52.495447 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1887 13:58:52.498653 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1888 13:58:52.502031 [Gating] SW calibration Done
1889 13:58:52.502103 ==
1890 13:58:52.505404 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 13:58:52.508640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1892 13:58:52.508708 ==
1893 13:58:52.512439 RX Vref Scan: 0
1894 13:58:52.512509
1895 13:58:52.512568 RX Vref 0 -> 0, step: 1
1896 13:58:52.512625
1897 13:58:52.515620 RX Delay -130 -> 252, step: 16
1898 13:58:52.521831 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1899 13:58:52.525260 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1900 13:58:52.528741 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1901 13:58:52.532052 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1902 13:58:52.535315 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1903 13:58:52.538644 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1904 13:58:52.545036 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1905 13:58:52.548611 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1906 13:58:52.552021 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1907 13:58:52.555264 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1908 13:58:52.558693 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1909 13:58:52.565049 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1910 13:58:52.568736 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1911 13:58:52.572298 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1912 13:58:52.575297 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1913 13:58:52.581392 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1914 13:58:52.581499 ==
1915 13:58:52.585333 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 13:58:52.588690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 13:58:52.588774 ==
1918 13:58:52.588860 DQS Delay:
1919 13:58:52.591383 DQS0 = 0, DQS1 = 0
1920 13:58:52.591466 DQM Delay:
1921 13:58:52.594928 DQM0 = 83, DQM1 = 82
1922 13:58:52.595011 DQ Delay:
1923 13:58:52.598403 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1924 13:58:52.601386 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1925 13:58:52.605480 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1926 13:58:52.608220 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1927 13:58:52.608299
1928 13:58:52.608381
1929 13:58:52.608461 ==
1930 13:58:52.611408 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 13:58:52.614797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 13:58:52.614877 ==
1933 13:58:52.614977
1934 13:58:52.618351
1935 13:58:52.618434 TX Vref Scan disable
1936 13:58:52.621500 == TX Byte 0 ==
1937 13:58:52.624771 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1938 13:58:52.628070 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1939 13:58:52.631817 == TX Byte 1 ==
1940 13:58:52.634758 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1941 13:58:52.638145 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1942 13:58:52.638244 ==
1943 13:58:52.641628 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 13:58:52.648192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 13:58:52.648298 ==
1946 13:58:52.660001 TX Vref=22, minBit 3, minWin=27, winSum=448
1947 13:58:52.663537 TX Vref=24, minBit 1, minWin=27, winSum=450
1948 13:58:52.667603 TX Vref=26, minBit 0, minWin=28, winSum=453
1949 13:58:52.670138 TX Vref=28, minBit 0, minWin=28, winSum=454
1950 13:58:52.673946 TX Vref=30, minBit 1, minWin=27, winSum=452
1951 13:58:52.680057 TX Vref=32, minBit 1, minWin=27, winSum=453
1952 13:58:52.683194 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 28
1953 13:58:52.683301
1954 13:58:52.686776 Final TX Range 1 Vref 28
1955 13:58:52.686880
1956 13:58:52.686973 ==
1957 13:58:52.690303 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 13:58:52.693766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 13:58:52.693867 ==
1960 13:58:52.696658
1961 13:58:52.696756
1962 13:58:52.696846 TX Vref Scan disable
1963 13:58:52.700374 == TX Byte 0 ==
1964 13:58:52.703424 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1965 13:58:52.710066 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1966 13:58:52.710165 == TX Byte 1 ==
1967 13:58:52.714222 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1968 13:58:52.720044 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1969 13:58:52.720149
1970 13:58:52.720243 [DATLAT]
1971 13:58:52.720337 Freq=800, CH1 RK1
1972 13:58:52.720437
1973 13:58:52.724074 DATLAT Default: 0xa
1974 13:58:52.724181 0, 0xFFFF, sum = 0
1975 13:58:52.727008 1, 0xFFFF, sum = 0
1976 13:58:52.727163 2, 0xFFFF, sum = 0
1977 13:58:52.730291 3, 0xFFFF, sum = 0
1978 13:58:52.730409 4, 0xFFFF, sum = 0
1979 13:58:52.733677 5, 0xFFFF, sum = 0
1980 13:58:52.736874 6, 0xFFFF, sum = 0
1981 13:58:52.736975 7, 0xFFFF, sum = 0
1982 13:58:52.739949 8, 0xFFFF, sum = 0
1983 13:58:52.740047 9, 0x0, sum = 1
1984 13:58:52.740157 10, 0x0, sum = 2
1985 13:58:52.743576 11, 0x0, sum = 3
1986 13:58:52.743682 12, 0x0, sum = 4
1987 13:58:52.746575 best_step = 10
1988 13:58:52.746678
1989 13:58:52.746766 ==
1990 13:58:52.749813 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 13:58:52.753379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 13:58:52.753475 ==
1993 13:58:52.756555 RX Vref Scan: 0
1994 13:58:52.756651
1995 13:58:52.756751 RX Vref 0 -> 0, step: 1
1996 13:58:52.756841
1997 13:58:52.760276 RX Delay -95 -> 252, step: 8
1998 13:58:52.766932 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1999 13:58:52.770560 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2000 13:58:52.773745 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2001 13:58:52.777162 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2002 13:58:52.780457 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2003 13:58:52.787108 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2004 13:58:52.789995 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2005 13:58:52.793703 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2006 13:58:52.797270 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2007 13:58:52.799964 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2008 13:58:52.807349 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2009 13:58:52.809808 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2010 13:58:52.813462 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2011 13:58:52.816379 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2012 13:58:52.823203 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2013 13:58:52.826398 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2014 13:58:52.826496 ==
2015 13:58:52.829785 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 13:58:52.833197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 13:58:52.833305 ==
2018 13:58:52.833397 DQS Delay:
2019 13:58:52.836499 DQS0 = 0, DQS1 = 0
2020 13:58:52.836598 DQM Delay:
2021 13:58:52.839681 DQM0 = 86, DQM1 = 82
2022 13:58:52.839788 DQ Delay:
2023 13:58:52.843068 DQ0 =88, DQ1 =84, DQ2 =76, DQ3 =84
2024 13:58:52.846599 DQ4 =88, DQ5 =96, DQ6 =92, DQ7 =84
2025 13:58:52.849748 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2026 13:58:52.853374 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2027 13:58:52.853487
2028 13:58:52.853581
2029 13:58:52.863093 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2030 13:58:52.863216 CH1 RK1: MR19=606, MR18=1E39
2031 13:58:52.869939 CH1_RK1: MR19=0x606, MR18=0x1E39, DQSOSC=395, MR23=63, INC=94, DEC=63
2032 13:58:52.873509 [RxdqsGatingPostProcess] freq 800
2033 13:58:52.879540 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2034 13:58:52.883356 Pre-setting of DQS Precalculation
2035 13:58:52.886223 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2036 13:58:52.893019 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2037 13:58:52.902772 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2038 13:58:52.902883
2039 13:58:52.902979
2040 13:58:52.903068 [Calibration Summary] 1600 Mbps
2041 13:58:52.906116 CH 0, Rank 0
2042 13:58:52.906222 SW Impedance : PASS
2043 13:58:52.909706 DUTY Scan : NO K
2044 13:58:52.912895 ZQ Calibration : PASS
2045 13:58:52.912994 Jitter Meter : NO K
2046 13:58:52.916369 CBT Training : PASS
2047 13:58:52.919986 Write leveling : PASS
2048 13:58:52.920091 RX DQS gating : PASS
2049 13:58:52.923262 RX DQ/DQS(RDDQC) : PASS
2050 13:58:52.926459 TX DQ/DQS : PASS
2051 13:58:52.926556 RX DATLAT : PASS
2052 13:58:52.929629 RX DQ/DQS(Engine): PASS
2053 13:58:52.933148 TX OE : NO K
2054 13:58:52.933256 All Pass.
2055 13:58:52.933350
2056 13:58:52.933438 CH 0, Rank 1
2057 13:58:52.936637 SW Impedance : PASS
2058 13:58:52.939393 DUTY Scan : NO K
2059 13:58:52.939491 ZQ Calibration : PASS
2060 13:58:52.942893 Jitter Meter : NO K
2061 13:58:52.946331 CBT Training : PASS
2062 13:58:52.946431 Write leveling : PASS
2063 13:58:52.949500 RX DQS gating : PASS
2064 13:58:52.952840 RX DQ/DQS(RDDQC) : PASS
2065 13:58:52.952924 TX DQ/DQS : PASS
2066 13:58:52.956195 RX DATLAT : PASS
2067 13:58:52.956278 RX DQ/DQS(Engine): PASS
2068 13:58:52.959487 TX OE : NO K
2069 13:58:52.959571 All Pass.
2070 13:58:52.959655
2071 13:58:52.963064 CH 1, Rank 0
2072 13:58:52.963170 SW Impedance : PASS
2073 13:58:52.966225 DUTY Scan : NO K
2074 13:58:52.969877 ZQ Calibration : PASS
2075 13:58:52.969960 Jitter Meter : NO K
2076 13:58:52.972999 CBT Training : PASS
2077 13:58:52.976337 Write leveling : PASS
2078 13:58:52.976421 RX DQS gating : PASS
2079 13:58:52.979782 RX DQ/DQS(RDDQC) : PASS
2080 13:58:52.983384 TX DQ/DQS : PASS
2081 13:58:52.983468 RX DATLAT : PASS
2082 13:58:52.985994 RX DQ/DQS(Engine): PASS
2083 13:58:52.989736 TX OE : NO K
2084 13:58:52.989820 All Pass.
2085 13:58:52.989904
2086 13:58:52.989984 CH 1, Rank 1
2087 13:58:52.992688 SW Impedance : PASS
2088 13:58:52.996069 DUTY Scan : NO K
2089 13:58:52.996152 ZQ Calibration : PASS
2090 13:58:52.999690 Jitter Meter : NO K
2091 13:58:52.999774 CBT Training : PASS
2092 13:58:53.003036 Write leveling : PASS
2093 13:58:53.006541 RX DQS gating : PASS
2094 13:58:53.006624 RX DQ/DQS(RDDQC) : PASS
2095 13:58:53.009384 TX DQ/DQS : PASS
2096 13:58:53.013245 RX DATLAT : PASS
2097 13:58:53.013328 RX DQ/DQS(Engine): PASS
2098 13:58:53.016070 TX OE : NO K
2099 13:58:53.016154 All Pass.
2100 13:58:53.016239
2101 13:58:53.019622 DramC Write-DBI off
2102 13:58:53.023109 PER_BANK_REFRESH: Hybrid Mode
2103 13:58:53.023206 TX_TRACKING: ON
2104 13:58:53.026168 [GetDramInforAfterCalByMRR] Vendor 6.
2105 13:58:53.029578 [GetDramInforAfterCalByMRR] Revision 606.
2106 13:58:53.032968 [GetDramInforAfterCalByMRR] Revision 2 0.
2107 13:58:53.036053 MR0 0x3b3b
2108 13:58:53.036135 MR8 0x5151
2109 13:58:53.039243 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 13:58:53.039326
2111 13:58:53.039412 MR0 0x3b3b
2112 13:58:53.042871 MR8 0x5151
2113 13:58:53.046175 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 13:58:53.046258
2115 13:58:53.056093 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2116 13:58:53.059612 [FAST_K] Save calibration result to emmc
2117 13:58:53.063000 [FAST_K] Save calibration result to emmc
2118 13:58:53.063106 dram_init: config_dvfs: 1
2119 13:58:53.069608 dramc_set_vcore_voltage set vcore to 662500
2120 13:58:53.069692 Read voltage for 1200, 2
2121 13:58:53.072802 Vio18 = 0
2122 13:58:53.072885 Vcore = 662500
2123 13:58:53.072985 Vdram = 0
2124 13:58:53.075979 Vddq = 0
2125 13:58:53.076062 Vmddr = 0
2126 13:58:53.079353 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2127 13:58:53.086572 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2128 13:58:53.089257 MEM_TYPE=3, freq_sel=15
2129 13:58:53.092872 sv_algorithm_assistance_LP4_1600
2130 13:58:53.095884 ============ PULL DRAM RESETB DOWN ============
2131 13:58:53.099325 ========== PULL DRAM RESETB DOWN end =========
2132 13:58:53.102702 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2133 13:58:53.106083 ===================================
2134 13:58:53.109507 LPDDR4 DRAM CONFIGURATION
2135 13:58:53.112594 ===================================
2136 13:58:53.116067 EX_ROW_EN[0] = 0x0
2137 13:58:53.116150 EX_ROW_EN[1] = 0x0
2138 13:58:53.119045 LP4Y_EN = 0x0
2139 13:58:53.119152 WORK_FSP = 0x0
2140 13:58:53.122754 WL = 0x4
2141 13:58:53.122838 RL = 0x4
2142 13:58:53.126332 BL = 0x2
2143 13:58:53.126414 RPST = 0x0
2144 13:58:53.129951 RD_PRE = 0x0
2145 13:58:53.130034 WR_PRE = 0x1
2146 13:58:53.132536 WR_PST = 0x0
2147 13:58:53.132619 DBI_WR = 0x0
2148 13:58:53.135960 DBI_RD = 0x0
2149 13:58:53.139468 OTF = 0x1
2150 13:58:53.139552 ===================================
2151 13:58:53.142591 ===================================
2152 13:58:53.146024 ANA top config
2153 13:58:53.149032 ===================================
2154 13:58:53.152527 DLL_ASYNC_EN = 0
2155 13:58:53.152639 ALL_SLAVE_EN = 0
2156 13:58:53.155781 NEW_RANK_MODE = 1
2157 13:58:53.159252 DLL_IDLE_MODE = 1
2158 13:58:53.162341 LP45_APHY_COMB_EN = 1
2159 13:58:53.165621 TX_ODT_DIS = 1
2160 13:58:53.165725 NEW_8X_MODE = 1
2161 13:58:53.168941 ===================================
2162 13:58:53.172691 ===================================
2163 13:58:53.175449 data_rate = 2400
2164 13:58:53.178999 CKR = 1
2165 13:58:53.182342 DQ_P2S_RATIO = 8
2166 13:58:53.185815 ===================================
2167 13:58:53.189217 CA_P2S_RATIO = 8
2168 13:58:53.192146 DQ_CA_OPEN = 0
2169 13:58:53.192227 DQ_SEMI_OPEN = 0
2170 13:58:53.195480 CA_SEMI_OPEN = 0
2171 13:58:53.199036 CA_FULL_RATE = 0
2172 13:58:53.202365 DQ_CKDIV4_EN = 0
2173 13:58:53.205791 CA_CKDIV4_EN = 0
2174 13:58:53.208962 CA_PREDIV_EN = 0
2175 13:58:53.209063 PH8_DLY = 17
2176 13:58:53.212273 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2177 13:58:53.215631 DQ_AAMCK_DIV = 4
2178 13:58:53.218819 CA_AAMCK_DIV = 4
2179 13:58:53.222324 CA_ADMCK_DIV = 4
2180 13:58:53.225305 DQ_TRACK_CA_EN = 0
2181 13:58:53.225405 CA_PICK = 1200
2182 13:58:53.228628 CA_MCKIO = 1200
2183 13:58:53.231715 MCKIO_SEMI = 0
2184 13:58:53.235382 PLL_FREQ = 2366
2185 13:58:53.238684 DQ_UI_PI_RATIO = 32
2186 13:58:53.242119 CA_UI_PI_RATIO = 0
2187 13:58:53.245233 ===================================
2188 13:58:53.248778 ===================================
2189 13:58:53.251883 memory_type:LPDDR4
2190 13:58:53.251983 GP_NUM : 10
2191 13:58:53.255531 SRAM_EN : 1
2192 13:58:53.255606 MD32_EN : 0
2193 13:58:53.258393 ===================================
2194 13:58:53.261506 [ANA_INIT] >>>>>>>>>>>>>>
2195 13:58:53.265248 <<<<<< [CONFIGURE PHASE]: ANA_TX
2196 13:58:53.268467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2197 13:58:53.271695 ===================================
2198 13:58:53.274921 data_rate = 2400,PCW = 0X5b00
2199 13:58:53.278557 ===================================
2200 13:58:53.281725 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2201 13:58:53.288713 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 13:58:53.291517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 13:58:53.298483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2204 13:58:53.302011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2205 13:58:53.304920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2206 13:58:53.305024 [ANA_INIT] flow start
2207 13:58:53.308246 [ANA_INIT] PLL >>>>>>>>
2208 13:58:53.311425 [ANA_INIT] PLL <<<<<<<<
2209 13:58:53.311499 [ANA_INIT] MIDPI >>>>>>>>
2210 13:58:53.315063 [ANA_INIT] MIDPI <<<<<<<<
2211 13:58:53.318404 [ANA_INIT] DLL >>>>>>>>
2212 13:58:53.318523 [ANA_INIT] DLL <<<<<<<<
2213 13:58:53.321392 [ANA_INIT] flow end
2214 13:58:53.324834 ============ LP4 DIFF to SE enter ============
2215 13:58:53.328282 ============ LP4 DIFF to SE exit ============
2216 13:58:53.331264 [ANA_INIT] <<<<<<<<<<<<<
2217 13:58:53.334812 [Flow] Enable top DCM control >>>>>
2218 13:58:53.338020 [Flow] Enable top DCM control <<<<<
2219 13:58:53.341390 Enable DLL master slave shuffle
2220 13:58:53.347794 ==============================================================
2221 13:58:53.347896 Gating Mode config
2222 13:58:53.354245 ==============================================================
2223 13:58:53.357837 Config description:
2224 13:58:53.364643 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2225 13:58:53.370864 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2226 13:58:53.377567 SELPH_MODE 0: By rank 1: By Phase
2227 13:58:53.383941 ==============================================================
2228 13:58:53.387382 GAT_TRACK_EN = 1
2229 13:58:53.387462 RX_GATING_MODE = 2
2230 13:58:53.390513 RX_GATING_TRACK_MODE = 2
2231 13:58:53.393859 SELPH_MODE = 1
2232 13:58:53.397438 PICG_EARLY_EN = 1
2233 13:58:53.400677 VALID_LAT_VALUE = 1
2234 13:58:53.407477 ==============================================================
2235 13:58:53.410647 Enter into Gating configuration >>>>
2236 13:58:53.413791 Exit from Gating configuration <<<<
2237 13:58:53.416863 Enter into DVFS_PRE_config >>>>>
2238 13:58:53.427432 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2239 13:58:53.430448 Exit from DVFS_PRE_config <<<<<
2240 13:58:53.433378 Enter into PICG configuration >>>>
2241 13:58:53.436844 Exit from PICG configuration <<<<
2242 13:58:53.440059 [RX_INPUT] configuration >>>>>
2243 13:58:53.443315 [RX_INPUT] configuration <<<<<
2244 13:58:53.446795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2245 13:58:53.453814 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2246 13:58:53.460258 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 13:58:53.467618 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 13:58:53.470013 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 13:58:53.476709 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 13:58:53.480137 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2251 13:58:53.487086 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2252 13:58:53.490336 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2253 13:58:53.493265 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2254 13:58:53.496584 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2255 13:58:53.503180 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2256 13:58:53.506833 ===================================
2257 13:58:53.506914 LPDDR4 DRAM CONFIGURATION
2258 13:58:53.509765 ===================================
2259 13:58:53.513349 EX_ROW_EN[0] = 0x0
2260 13:58:53.516620 EX_ROW_EN[1] = 0x0
2261 13:58:53.516700 LP4Y_EN = 0x0
2262 13:58:53.520062 WORK_FSP = 0x0
2263 13:58:53.520169 WL = 0x4
2264 13:58:53.522957 RL = 0x4
2265 13:58:53.523059 BL = 0x2
2266 13:58:53.526293 RPST = 0x0
2267 13:58:53.526394 RD_PRE = 0x0
2268 13:58:53.529556 WR_PRE = 0x1
2269 13:58:53.529657 WR_PST = 0x0
2270 13:58:53.533198 DBI_WR = 0x0
2271 13:58:53.533296 DBI_RD = 0x0
2272 13:58:53.536554 OTF = 0x1
2273 13:58:53.539716 ===================================
2274 13:58:53.543583 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2275 13:58:53.546140 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2276 13:58:53.552870 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2277 13:58:53.556051 ===================================
2278 13:58:53.556164 LPDDR4 DRAM CONFIGURATION
2279 13:58:53.559353 ===================================
2280 13:58:53.562667 EX_ROW_EN[0] = 0x10
2281 13:58:53.566175 EX_ROW_EN[1] = 0x0
2282 13:58:53.566274 LP4Y_EN = 0x0
2283 13:58:53.569261 WORK_FSP = 0x0
2284 13:58:53.569360 WL = 0x4
2285 13:58:53.572631 RL = 0x4
2286 13:58:53.572733 BL = 0x2
2287 13:58:53.575947 RPST = 0x0
2288 13:58:53.576052 RD_PRE = 0x0
2289 13:58:53.579232 WR_PRE = 0x1
2290 13:58:53.579333 WR_PST = 0x0
2291 13:58:53.582618 DBI_WR = 0x0
2292 13:58:53.582715 DBI_RD = 0x0
2293 13:58:53.585958 OTF = 0x1
2294 13:58:53.589447 ===================================
2295 13:58:53.596086 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2296 13:58:53.596181 ==
2297 13:58:53.599738 Dram Type= 6, Freq= 0, CH_0, rank 0
2298 13:58:53.602373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2299 13:58:53.602470 ==
2300 13:58:53.606076 [Duty_Offset_Calibration]
2301 13:58:53.606170 B0:2 B1:0 CA:4
2302 13:58:53.606264
2303 13:58:53.609403 [DutyScan_Calibration_Flow] k_type=0
2304 13:58:53.619036
2305 13:58:53.619163 ==CLK 0==
2306 13:58:53.622328 Final CLK duty delay cell = -4
2307 13:58:53.625174 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2308 13:58:53.629027 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2309 13:58:53.632357 [-4] AVG Duty = 4953%(X100)
2310 13:58:53.632461
2311 13:58:53.635305 CH0 CLK Duty spec in!! Max-Min= 218%
2312 13:58:53.638728 [DutyScan_Calibration_Flow] ====Done====
2313 13:58:53.638837
2314 13:58:53.641962 [DutyScan_Calibration_Flow] k_type=1
2315 13:58:53.657597
2316 13:58:53.657709 ==DQS 0 ==
2317 13:58:53.660840 Final DQS duty delay cell = -4
2318 13:58:53.664193 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2319 13:58:53.667577 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2320 13:58:53.670543 [-4] AVG Duty = 4922%(X100)
2321 13:58:53.670649
2322 13:58:53.670750 ==DQS 1 ==
2323 13:58:53.674212 Final DQS duty delay cell = 0
2324 13:58:53.677484 [0] MAX Duty = 5125%(X100), DQS PI = 4
2325 13:58:53.680839 [0] MIN Duty = 5000%(X100), DQS PI = 0
2326 13:58:53.683932 [0] AVG Duty = 5062%(X100)
2327 13:58:53.684012
2328 13:58:53.687195 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2329 13:58:53.687275
2330 13:58:53.690598 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2331 13:58:53.693987 [DutyScan_Calibration_Flow] ====Done====
2332 13:58:53.694066
2333 13:58:53.697064 [DutyScan_Calibration_Flow] k_type=3
2334 13:58:53.714002
2335 13:58:53.714081 ==DQM 0 ==
2336 13:58:53.717595 Final DQM duty delay cell = 0
2337 13:58:53.720827 [0] MAX Duty = 5125%(X100), DQS PI = 20
2338 13:58:53.723851 [0] MIN Duty = 4844%(X100), DQS PI = 50
2339 13:58:53.727602 [0] AVG Duty = 4984%(X100)
2340 13:58:53.727681
2341 13:58:53.727744 ==DQM 1 ==
2342 13:58:53.730992 Final DQM duty delay cell = 0
2343 13:58:53.734266 [0] MAX Duty = 4969%(X100), DQS PI = 0
2344 13:58:53.737710 [0] MIN Duty = 4875%(X100), DQS PI = 20
2345 13:58:53.737790 [0] AVG Duty = 4922%(X100)
2346 13:58:53.740792
2347 13:58:53.744221 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2348 13:58:53.744300
2349 13:58:53.747093 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2350 13:58:53.750731 [DutyScan_Calibration_Flow] ====Done====
2351 13:58:53.750811
2352 13:58:53.754227 [DutyScan_Calibration_Flow] k_type=2
2353 13:58:53.770558
2354 13:58:53.770638 ==DQ 0 ==
2355 13:58:53.773927 Final DQ duty delay cell = 0
2356 13:58:53.777038 [0] MAX Duty = 5125%(X100), DQS PI = 18
2357 13:58:53.780567 [0] MIN Duty = 4938%(X100), DQS PI = 58
2358 13:58:53.780689 [0] AVG Duty = 5031%(X100)
2359 13:58:53.783976
2360 13:58:53.784091 ==DQ 1 ==
2361 13:58:53.786904 Final DQ duty delay cell = 0
2362 13:58:53.790866 [0] MAX Duty = 5125%(X100), DQS PI = 4
2363 13:58:53.793738 [0] MIN Duty = 4938%(X100), DQS PI = 16
2364 13:58:53.793843 [0] AVG Duty = 5031%(X100)
2365 13:58:53.793945
2366 13:58:53.797014 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2367 13:58:53.801268
2368 13:58:53.803497 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2369 13:58:53.807185 [DutyScan_Calibration_Flow] ====Done====
2370 13:58:53.807290 ==
2371 13:58:53.810239 Dram Type= 6, Freq= 0, CH_1, rank 0
2372 13:58:53.813763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 13:58:53.813863 ==
2374 13:58:53.816938 [Duty_Offset_Calibration]
2375 13:58:53.817038 B0:0 B1:-1 CA:3
2376 13:58:53.817138
2377 13:58:53.820597 [DutyScan_Calibration_Flow] k_type=0
2378 13:58:53.829578
2379 13:58:53.829680 ==CLK 0==
2380 13:58:53.833158 Final CLK duty delay cell = -4
2381 13:58:53.836232 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2382 13:58:53.840280 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2383 13:58:53.843003 [-4] AVG Duty = 4938%(X100)
2384 13:58:53.843138
2385 13:58:53.846040 CH1 CLK Duty spec in!! Max-Min= 124%
2386 13:58:53.849976 [DutyScan_Calibration_Flow] ====Done====
2387 13:58:53.850079
2388 13:58:53.852743 [DutyScan_Calibration_Flow] k_type=1
2389 13:58:53.869272
2390 13:58:53.869376 ==DQS 0 ==
2391 13:58:53.872675 Final DQS duty delay cell = 0
2392 13:58:53.875738 [0] MAX Duty = 5124%(X100), DQS PI = 18
2393 13:58:53.879282 [0] MIN Duty = 4907%(X100), DQS PI = 38
2394 13:58:53.882634 [0] AVG Duty = 5015%(X100)
2395 13:58:53.882735
2396 13:58:53.882828 ==DQS 1 ==
2397 13:58:53.885870 Final DQS duty delay cell = 0
2398 13:58:53.889534 [0] MAX Duty = 5156%(X100), DQS PI = 8
2399 13:58:53.892343 [0] MIN Duty = 5031%(X100), DQS PI = 22
2400 13:58:53.896135 [0] AVG Duty = 5093%(X100)
2401 13:58:53.896240
2402 13:58:53.898920 CH1 DQS 0 Duty spec in!! Max-Min= 217%
2403 13:58:53.899019
2404 13:58:53.902970 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2405 13:58:53.905821 [DutyScan_Calibration_Flow] ====Done====
2406 13:58:53.905920
2407 13:58:53.908972 [DutyScan_Calibration_Flow] k_type=3
2408 13:58:53.925583
2409 13:58:53.925686 ==DQM 0 ==
2410 13:58:53.928863 Final DQM duty delay cell = 0
2411 13:58:53.932027 [0] MAX Duty = 5031%(X100), DQS PI = 28
2412 13:58:53.935501 [0] MIN Duty = 4813%(X100), DQS PI = 38
2413 13:58:53.939035 [0] AVG Duty = 4922%(X100)
2414 13:58:53.939129
2415 13:58:53.939195 ==DQM 1 ==
2416 13:58:53.942276 Final DQM duty delay cell = 0
2417 13:58:53.945492 [0] MAX Duty = 5000%(X100), DQS PI = 34
2418 13:58:53.948828 [0] MIN Duty = 4844%(X100), DQS PI = 0
2419 13:58:53.952474 [0] AVG Duty = 4922%(X100)
2420 13:58:53.952571
2421 13:58:53.955834 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2422 13:58:53.955936
2423 13:58:53.958925 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2424 13:58:53.962075 [DutyScan_Calibration_Flow] ====Done====
2425 13:58:53.962165
2426 13:58:53.965339 [DutyScan_Calibration_Flow] k_type=2
2427 13:58:53.981143
2428 13:58:53.981251 ==DQ 0 ==
2429 13:58:53.984640 Final DQ duty delay cell = -4
2430 13:58:53.988029 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2431 13:58:53.991955 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2432 13:58:53.995481 [-4] AVG Duty = 4937%(X100)
2433 13:58:53.995587
2434 13:58:53.995680 ==DQ 1 ==
2435 13:58:53.997867 Final DQ duty delay cell = 0
2436 13:58:54.001553 [0] MAX Duty = 5031%(X100), DQS PI = 32
2437 13:58:54.005286 [0] MIN Duty = 4844%(X100), DQS PI = 62
2438 13:58:54.005388 [0] AVG Duty = 4937%(X100)
2439 13:58:54.007782
2440 13:58:54.011542 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2441 13:58:54.011651
2442 13:58:54.014732 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2443 13:58:54.018342 [DutyScan_Calibration_Flow] ====Done====
2444 13:58:54.021226 nWR fixed to 30
2445 13:58:54.021327 [ModeRegInit_LP4] CH0 RK0
2446 13:58:54.024875 [ModeRegInit_LP4] CH0 RK1
2447 13:58:54.027815 [ModeRegInit_LP4] CH1 RK0
2448 13:58:54.031193 [ModeRegInit_LP4] CH1 RK1
2449 13:58:54.031267 match AC timing 7
2450 13:58:54.037859 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2451 13:58:54.041354 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2452 13:58:54.044551 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2453 13:58:54.050974 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2454 13:58:54.054375 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2455 13:58:54.054477 ==
2456 13:58:54.057933 Dram Type= 6, Freq= 0, CH_0, rank 0
2457 13:58:54.061254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2458 13:58:54.061354 ==
2459 13:58:54.068136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2460 13:58:54.074675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2461 13:58:54.082257 [CA 0] Center 39 (9~70) winsize 62
2462 13:58:54.084984 [CA 1] Center 39 (9~70) winsize 62
2463 13:58:54.088428 [CA 2] Center 35 (5~66) winsize 62
2464 13:58:54.091927 [CA 3] Center 35 (5~66) winsize 62
2465 13:58:54.095202 [CA 4] Center 33 (3~64) winsize 62
2466 13:58:54.098236 [CA 5] Center 33 (3~63) winsize 61
2467 13:58:54.098340
2468 13:58:54.101939 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2469 13:58:54.102025
2470 13:58:54.104956 [CATrainingPosCal] consider 1 rank data
2471 13:58:54.108365 u2DelayCellTimex100 = 270/100 ps
2472 13:58:54.111756 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2473 13:58:54.115092 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2474 13:58:54.121701 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2475 13:58:54.124851 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2476 13:58:54.128513 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2477 13:58:54.131822 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2478 13:58:54.131928
2479 13:58:54.134738 CA PerBit enable=1, Macro0, CA PI delay=33
2480 13:58:54.134840
2481 13:58:54.138538 [CBTSetCACLKResult] CA Dly = 33
2482 13:58:54.138638 CS Dly: 7 (0~38)
2483 13:58:54.141388 ==
2484 13:58:54.141490 Dram Type= 6, Freq= 0, CH_0, rank 1
2485 13:58:54.148569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2486 13:58:54.148673 ==
2487 13:58:54.151339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2488 13:58:54.158454 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2489 13:58:54.167347 [CA 0] Center 39 (9~70) winsize 62
2490 13:58:54.170868 [CA 1] Center 39 (9~70) winsize 62
2491 13:58:54.174010 [CA 2] Center 35 (5~66) winsize 62
2492 13:58:54.177203 [CA 3] Center 35 (5~66) winsize 62
2493 13:58:54.180569 [CA 4] Center 34 (4~65) winsize 62
2494 13:58:54.184263 [CA 5] Center 33 (3~63) winsize 61
2495 13:58:54.184365
2496 13:58:54.187501 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2497 13:58:54.187599
2498 13:58:54.190640 [CATrainingPosCal] consider 2 rank data
2499 13:58:54.193802 u2DelayCellTimex100 = 270/100 ps
2500 13:58:54.197253 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2501 13:58:54.201227 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2502 13:58:54.207328 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 13:58:54.210839 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2504 13:58:54.213735 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2505 13:58:54.217303 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2506 13:58:54.217401
2507 13:58:54.221045 CA PerBit enable=1, Macro0, CA PI delay=33
2508 13:58:54.221144
2509 13:58:54.224221 [CBTSetCACLKResult] CA Dly = 33
2510 13:58:54.224321 CS Dly: 8 (0~41)
2511 13:58:54.224414
2512 13:58:54.227431 ----->DramcWriteLeveling(PI) begin...
2513 13:58:54.230742 ==
2514 13:58:54.234182 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 13:58:54.237099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 13:58:54.237201 ==
2517 13:58:54.240666 Write leveling (Byte 0): 32 => 32
2518 13:58:54.243949 Write leveling (Byte 1): 27 => 27
2519 13:58:54.247230 DramcWriteLeveling(PI) end<-----
2520 13:58:54.247306
2521 13:58:54.247369 ==
2522 13:58:54.250634 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 13:58:54.254380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 13:58:54.254483 ==
2525 13:58:54.257232 [Gating] SW mode calibration
2526 13:58:54.263804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2527 13:58:54.271005 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2528 13:58:54.273770 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2529 13:58:54.277249 0 15 4 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
2530 13:58:54.280473 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 13:58:54.286973 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 13:58:54.290756 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 13:58:54.293502 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 13:58:54.300556 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2535 13:58:54.304289 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2536 13:58:54.306978 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
2537 13:58:54.313457 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 13:58:54.316986 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 13:58:54.320152 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 13:58:54.326975 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 13:58:54.330034 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 13:58:54.334055 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2543 13:58:54.340001 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2544 13:58:54.344024 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2545 13:58:54.346635 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2546 13:58:54.353195 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 13:58:54.356842 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 13:58:54.359848 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 13:58:54.366626 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 13:58:54.369869 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 13:58:54.373141 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2552 13:58:54.379751 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2553 13:58:54.382936 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 13:58:54.386474 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:58:54.392959 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 13:58:54.396297 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 13:58:54.400039 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 13:58:54.406901 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 13:58:54.409988 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 13:58:54.412921 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 13:58:54.419729 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:58:54.422941 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 13:58:54.426184 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 13:58:54.432931 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 13:58:54.436126 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 13:58:54.439946 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 13:58:54.446133 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 13:58:54.449818 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2569 13:58:54.453032 Total UI for P1: 0, mck2ui 16
2570 13:58:54.456184 best dqsien dly found for B0: ( 1, 3, 28)
2571 13:58:54.459415 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 13:58:54.462957 Total UI for P1: 0, mck2ui 16
2573 13:58:54.466090 best dqsien dly found for B1: ( 1, 4, 0)
2574 13:58:54.469469 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2575 13:58:54.473164 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2576 13:58:54.473256
2577 13:58:54.475970 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2578 13:58:54.482775 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2579 13:58:54.482868 [Gating] SW calibration Done
2580 13:58:54.482936 ==
2581 13:58:54.485943 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 13:58:54.492374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 13:58:54.492461 ==
2584 13:58:54.492529 RX Vref Scan: 0
2585 13:58:54.492592
2586 13:58:54.495999 RX Vref 0 -> 0, step: 1
2587 13:58:54.496082
2588 13:58:54.499517 RX Delay -40 -> 252, step: 8
2589 13:58:54.502470 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2590 13:58:54.505634 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2591 13:58:54.509169 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2592 13:58:54.516541 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2593 13:58:54.519197 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2594 13:58:54.522462 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2595 13:58:54.525876 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2596 13:58:54.529788 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2597 13:58:54.532857 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2598 13:58:54.538966 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2599 13:58:54.542450 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2600 13:58:54.545844 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2601 13:58:54.549360 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2602 13:58:54.552572 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2603 13:58:54.559065 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2604 13:58:54.562548 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2605 13:58:54.562629 ==
2606 13:58:54.565652 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 13:58:54.568734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 13:58:54.568817 ==
2609 13:58:54.572703 DQS Delay:
2610 13:58:54.572784 DQS0 = 0, DQS1 = 0
2611 13:58:54.575808 DQM Delay:
2612 13:58:54.575937 DQM0 = 117, DQM1 = 108
2613 13:58:54.576004 DQ Delay:
2614 13:58:54.579041 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2615 13:58:54.585540 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2616 13:58:54.588597 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2617 13:58:54.592080 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2618 13:58:54.592189
2619 13:58:54.592281
2620 13:58:54.592378 ==
2621 13:58:54.595464 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 13:58:54.598759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 13:58:54.598861 ==
2624 13:58:54.598959
2625 13:58:54.599049
2626 13:58:54.602111 TX Vref Scan disable
2627 13:58:54.605613 == TX Byte 0 ==
2628 13:58:54.608633 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2629 13:58:54.611997 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2630 13:58:54.615190 == TX Byte 1 ==
2631 13:58:54.618696 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2632 13:58:54.622118 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2633 13:58:54.622219 ==
2634 13:58:54.625396 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 13:58:54.628573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 13:58:54.631588 ==
2637 13:58:54.642204 TX Vref=22, minBit 0, minWin=25, winSum=408
2638 13:58:54.645432 TX Vref=24, minBit 4, minWin=25, winSum=415
2639 13:58:54.648628 TX Vref=26, minBit 4, minWin=25, winSum=422
2640 13:58:54.652289 TX Vref=28, minBit 1, minWin=26, winSum=429
2641 13:58:54.655282 TX Vref=30, minBit 10, minWin=26, winSum=430
2642 13:58:54.662042 TX Vref=32, minBit 5, minWin=26, winSum=426
2643 13:58:54.665339 [TxChooseVref] Worse bit 10, Min win 26, Win sum 430, Final Vref 30
2644 13:58:54.665421
2645 13:58:54.668586 Final TX Range 1 Vref 30
2646 13:58:54.668669
2647 13:58:54.668748 ==
2648 13:58:54.671986 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 13:58:54.675531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 13:58:54.678406 ==
2651 13:58:54.678488
2652 13:58:54.678553
2653 13:58:54.678630 TX Vref Scan disable
2654 13:58:54.682329 == TX Byte 0 ==
2655 13:58:54.685190 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2656 13:58:54.692037 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2657 13:58:54.692121 == TX Byte 1 ==
2658 13:58:54.695416 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2659 13:58:54.701867 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2660 13:58:54.701948
2661 13:58:54.702014 [DATLAT]
2662 13:58:54.702074 Freq=1200, CH0 RK0
2663 13:58:54.702133
2664 13:58:54.705240 DATLAT Default: 0xd
2665 13:58:54.705321 0, 0xFFFF, sum = 0
2666 13:58:54.708347 1, 0xFFFF, sum = 0
2667 13:58:54.711651 2, 0xFFFF, sum = 0
2668 13:58:54.711733 3, 0xFFFF, sum = 0
2669 13:58:54.715123 4, 0xFFFF, sum = 0
2670 13:58:54.715206 5, 0xFFFF, sum = 0
2671 13:58:54.718636 6, 0xFFFF, sum = 0
2672 13:58:54.718719 7, 0xFFFF, sum = 0
2673 13:58:54.721722 8, 0xFFFF, sum = 0
2674 13:58:54.721804 9, 0xFFFF, sum = 0
2675 13:58:54.725107 10, 0xFFFF, sum = 0
2676 13:58:54.725190 11, 0xFFFF, sum = 0
2677 13:58:54.728388 12, 0x0, sum = 1
2678 13:58:54.728471 13, 0x0, sum = 2
2679 13:58:54.731921 14, 0x0, sum = 3
2680 13:58:54.732003 15, 0x0, sum = 4
2681 13:58:54.735317 best_step = 13
2682 13:58:54.735398
2683 13:58:54.735463 ==
2684 13:58:54.738396 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 13:58:54.741775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 13:58:54.741857 ==
2687 13:58:54.741923 RX Vref Scan: 1
2688 13:58:54.741983
2689 13:58:54.745055 Set Vref Range= 32 -> 127
2690 13:58:54.745136
2691 13:58:54.748471 RX Vref 32 -> 127, step: 1
2692 13:58:54.748552
2693 13:58:54.751936 RX Delay -21 -> 252, step: 4
2694 13:58:54.752017
2695 13:58:54.755661 Set Vref, RX VrefLevel [Byte0]: 32
2696 13:58:54.758159 [Byte1]: 32
2697 13:58:54.758239
2698 13:58:54.761635 Set Vref, RX VrefLevel [Byte0]: 33
2699 13:58:54.765119 [Byte1]: 33
2700 13:58:54.768652
2701 13:58:54.768733 Set Vref, RX VrefLevel [Byte0]: 34
2702 13:58:54.772125 [Byte1]: 34
2703 13:58:54.776779
2704 13:58:54.776860 Set Vref, RX VrefLevel [Byte0]: 35
2705 13:58:54.779795 [Byte1]: 35
2706 13:58:54.784406
2707 13:58:54.784487 Set Vref, RX VrefLevel [Byte0]: 36
2708 13:58:54.788005 [Byte1]: 36
2709 13:58:54.792374
2710 13:58:54.792455 Set Vref, RX VrefLevel [Byte0]: 37
2711 13:58:54.795718 [Byte1]: 37
2712 13:58:54.800673
2713 13:58:54.800755 Set Vref, RX VrefLevel [Byte0]: 38
2714 13:58:54.803687 [Byte1]: 38
2715 13:58:54.808060
2716 13:58:54.808141 Set Vref, RX VrefLevel [Byte0]: 39
2717 13:58:54.811718 [Byte1]: 39
2718 13:58:54.816391
2719 13:58:54.816472 Set Vref, RX VrefLevel [Byte0]: 40
2720 13:58:54.819762 [Byte1]: 40
2721 13:58:54.824024
2722 13:58:54.824105 Set Vref, RX VrefLevel [Byte0]: 41
2723 13:58:54.827213 [Byte1]: 41
2724 13:58:54.831973
2725 13:58:54.832053 Set Vref, RX VrefLevel [Byte0]: 42
2726 13:58:54.835364 [Byte1]: 42
2727 13:58:54.839975
2728 13:58:54.840055 Set Vref, RX VrefLevel [Byte0]: 43
2729 13:58:54.843012 [Byte1]: 43
2730 13:58:54.848148
2731 13:58:54.848229 Set Vref, RX VrefLevel [Byte0]: 44
2732 13:58:54.851443 [Byte1]: 44
2733 13:58:54.855999
2734 13:58:54.856080 Set Vref, RX VrefLevel [Byte0]: 45
2735 13:58:54.859121 [Byte1]: 45
2736 13:58:54.863715
2737 13:58:54.863800 Set Vref, RX VrefLevel [Byte0]: 46
2738 13:58:54.866930 [Byte1]: 46
2739 13:58:54.871967
2740 13:58:54.872048 Set Vref, RX VrefLevel [Byte0]: 47
2741 13:58:54.874759 [Byte1]: 47
2742 13:58:54.879658
2743 13:58:54.879769 Set Vref, RX VrefLevel [Byte0]: 48
2744 13:58:54.883058 [Byte1]: 48
2745 13:58:54.887355
2746 13:58:54.887459 Set Vref, RX VrefLevel [Byte0]: 49
2747 13:58:54.890816 [Byte1]: 49
2748 13:58:54.895372
2749 13:58:54.895481 Set Vref, RX VrefLevel [Byte0]: 50
2750 13:58:54.898615 [Byte1]: 50
2751 13:58:54.903362
2752 13:58:54.903473 Set Vref, RX VrefLevel [Byte0]: 51
2753 13:58:54.906773 [Byte1]: 51
2754 13:58:54.911539
2755 13:58:54.911614 Set Vref, RX VrefLevel [Byte0]: 52
2756 13:58:54.914271 [Byte1]: 52
2757 13:58:54.919399
2758 13:58:54.919472 Set Vref, RX VrefLevel [Byte0]: 53
2759 13:58:54.922269 [Byte1]: 53
2760 13:58:54.927335
2761 13:58:54.927437 Set Vref, RX VrefLevel [Byte0]: 54
2762 13:58:54.930285 [Byte1]: 54
2763 13:58:54.934805
2764 13:58:54.934906 Set Vref, RX VrefLevel [Byte0]: 55
2765 13:58:54.938614 [Byte1]: 55
2766 13:58:54.943340
2767 13:58:54.943446 Set Vref, RX VrefLevel [Byte0]: 56
2768 13:58:54.946007 [Byte1]: 56
2769 13:58:54.951069
2770 13:58:54.951181 Set Vref, RX VrefLevel [Byte0]: 57
2771 13:58:54.954250 [Byte1]: 57
2772 13:58:54.958815
2773 13:58:54.958919 Set Vref, RX VrefLevel [Byte0]: 58
2774 13:58:54.962091 [Byte1]: 58
2775 13:58:54.967375
2776 13:58:54.967478 Set Vref, RX VrefLevel [Byte0]: 59
2777 13:58:54.970100 [Byte1]: 59
2778 13:58:54.974537
2779 13:58:54.974640 Set Vref, RX VrefLevel [Byte0]: 60
2780 13:58:54.977718 [Byte1]: 60
2781 13:58:54.982792
2782 13:58:54.982894 Set Vref, RX VrefLevel [Byte0]: 61
2783 13:58:54.986052 [Byte1]: 61
2784 13:58:54.990478
2785 13:58:54.990580 Set Vref, RX VrefLevel [Byte0]: 62
2786 13:58:54.993830 [Byte1]: 62
2787 13:58:54.998991
2788 13:58:54.999135 Set Vref, RX VrefLevel [Byte0]: 63
2789 13:58:55.001830 [Byte1]: 63
2790 13:58:55.006102
2791 13:58:55.006209 Set Vref, RX VrefLevel [Byte0]: 64
2792 13:58:55.009874 [Byte1]: 64
2793 13:58:55.014283
2794 13:58:55.014387 Set Vref, RX VrefLevel [Byte0]: 65
2795 13:58:55.017685 [Byte1]: 65
2796 13:58:55.022227
2797 13:58:55.022330 Set Vref, RX VrefLevel [Byte0]: 66
2798 13:58:55.025397 [Byte1]: 66
2799 13:58:55.029955
2800 13:58:55.030058 Final RX Vref Byte 0 = 53 to rank0
2801 13:58:55.033405 Final RX Vref Byte 1 = 51 to rank0
2802 13:58:55.036990 Final RX Vref Byte 0 = 53 to rank1
2803 13:58:55.040303 Final RX Vref Byte 1 = 51 to rank1==
2804 13:58:55.043480 Dram Type= 6, Freq= 0, CH_0, rank 0
2805 13:58:55.049854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2806 13:58:55.049958 ==
2807 13:58:55.050052 DQS Delay:
2808 13:58:55.050134 DQS0 = 0, DQS1 = 0
2809 13:58:55.053049 DQM Delay:
2810 13:58:55.053150 DQM0 = 117, DQM1 = 105
2811 13:58:55.056267 DQ Delay:
2812 13:58:55.060365 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2813 13:58:55.063484 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2814 13:58:55.066286 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =100
2815 13:58:55.069460 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =112
2816 13:58:55.069559
2817 13:58:55.069651
2818 13:58:55.079618 [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2819 13:58:55.079726 CH0 RK0: MR19=403, MR18=4FF
2820 13:58:55.086454 CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2821 13:58:55.086559
2822 13:58:55.089958 ----->DramcWriteLeveling(PI) begin...
2823 13:58:55.090060 ==
2824 13:58:55.092931 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 13:58:55.099358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 13:58:55.099457 ==
2827 13:58:55.102569 Write leveling (Byte 0): 30 => 30
2828 13:58:55.102683 Write leveling (Byte 1): 25 => 25
2829 13:58:55.106058 DramcWriteLeveling(PI) end<-----
2830 13:58:55.106157
2831 13:58:55.106263 ==
2832 13:58:55.109551 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 13:58:55.116158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 13:58:55.116264 ==
2835 13:58:55.119213 [Gating] SW mode calibration
2836 13:58:55.125907 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2837 13:58:55.129659 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2838 13:58:55.135960 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2839 13:58:55.138931 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2840 13:58:55.142673 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 13:58:55.149235 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 13:58:55.152712 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 13:58:55.155639 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 13:58:55.162722 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2845 13:58:55.166204 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
2846 13:58:55.168984 1 0 0 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
2847 13:58:55.175886 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 13:58:55.179562 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 13:58:55.182609 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 13:58:55.185709 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 13:58:55.192434 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 13:58:55.195559 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2853 13:58:55.198820 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2854 13:58:55.205462 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
2855 13:58:55.209190 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 13:58:55.212543 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 13:58:55.218479 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 13:58:55.222092 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 13:58:55.225459 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 13:58:55.231943 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2861 13:58:55.235379 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2862 13:58:55.238738 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2863 13:58:55.245428 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 13:58:55.248687 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 13:58:55.252163 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 13:58:55.258595 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 13:58:55.261715 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 13:58:55.265424 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 13:58:55.271928 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 13:58:55.275268 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 13:58:55.278645 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 13:58:55.285143 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 13:58:55.288717 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 13:58:55.291736 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 13:58:55.298534 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 13:58:55.301983 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2877 13:58:55.305311 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2878 13:58:55.308554 Total UI for P1: 0, mck2ui 16
2879 13:58:55.311606 best dqsien dly found for B0: ( 1, 3, 24)
2880 13:58:55.318416 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 13:58:55.318524 Total UI for P1: 0, mck2ui 16
2882 13:58:55.321892 best dqsien dly found for B1: ( 1, 3, 28)
2883 13:58:55.328311 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2884 13:58:55.331432 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2885 13:58:55.331524
2886 13:58:55.334948 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2887 13:58:55.338390 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2888 13:58:55.341398 [Gating] SW calibration Done
2889 13:58:55.341511 ==
2890 13:58:55.344998 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 13:58:55.348349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 13:58:55.348460 ==
2893 13:58:55.351728 RX Vref Scan: 0
2894 13:58:55.351837
2895 13:58:55.351929 RX Vref 0 -> 0, step: 1
2896 13:58:55.352036
2897 13:58:55.354625 RX Delay -40 -> 252, step: 8
2898 13:58:55.358378 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2899 13:58:55.364670 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2900 13:58:55.368392 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2901 13:58:55.371428 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2902 13:58:55.374719 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2903 13:58:55.377770 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2904 13:58:55.384476 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2905 13:58:55.388696 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2906 13:58:55.391045 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2907 13:58:55.394570 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2908 13:58:55.398376 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2909 13:58:55.404389 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2910 13:58:55.407957 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2911 13:58:55.410988 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2912 13:58:55.414371 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2913 13:58:55.417724 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2914 13:58:55.421550 ==
2915 13:58:55.424329 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 13:58:55.427712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 13:58:55.427815 ==
2918 13:58:55.427923 DQS Delay:
2919 13:58:55.430965 DQS0 = 0, DQS1 = 0
2920 13:58:55.431089 DQM Delay:
2921 13:58:55.434148 DQM0 = 115, DQM1 = 107
2922 13:58:55.434250 DQ Delay:
2923 13:58:55.437623 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2924 13:58:55.440992 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2925 13:58:55.444423 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2926 13:58:55.447423 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2927 13:58:55.447505
2928 13:58:55.447570
2929 13:58:55.447630 ==
2930 13:58:55.450965 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 13:58:55.457391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 13:58:55.457478 ==
2933 13:58:55.457544
2934 13:58:55.457603
2935 13:58:55.457662 TX Vref Scan disable
2936 13:58:55.461144 == TX Byte 0 ==
2937 13:58:55.464964 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2938 13:58:55.470916 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2939 13:58:55.471031 == TX Byte 1 ==
2940 13:58:55.474346 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2941 13:58:55.480764 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2942 13:58:55.480878 ==
2943 13:58:55.484176 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 13:58:55.487364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 13:58:55.487446 ==
2946 13:58:55.499681 TX Vref=22, minBit 0, minWin=25, winSum=417
2947 13:58:55.502460 TX Vref=24, minBit 1, minWin=26, winSum=424
2948 13:58:55.505828 TX Vref=26, minBit 2, minWin=26, winSum=430
2949 13:58:55.509134 TX Vref=28, minBit 2, minWin=26, winSum=427
2950 13:58:55.513182 TX Vref=30, minBit 12, minWin=26, winSum=433
2951 13:58:55.519683 TX Vref=32, minBit 4, minWin=26, winSum=432
2952 13:58:55.522702 [TxChooseVref] Worse bit 12, Min win 26, Win sum 433, Final Vref 30
2953 13:58:55.522784
2954 13:58:55.526310 Final TX Range 1 Vref 30
2955 13:58:55.526392
2956 13:58:55.526457 ==
2957 13:58:55.529946 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 13:58:55.532724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 13:58:55.532806 ==
2960 13:58:55.536090
2961 13:58:55.536171
2962 13:58:55.536235 TX Vref Scan disable
2963 13:58:55.539056 == TX Byte 0 ==
2964 13:58:55.542794 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2965 13:58:55.545840 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2966 13:58:55.549211 == TX Byte 1 ==
2967 13:58:55.552589 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2968 13:58:55.559197 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2969 13:58:55.559278
2970 13:58:55.559343 [DATLAT]
2971 13:58:55.559403 Freq=1200, CH0 RK1
2972 13:58:55.559462
2973 13:58:55.562617 DATLAT Default: 0xd
2974 13:58:55.562697 0, 0xFFFF, sum = 0
2975 13:58:55.565787 1, 0xFFFF, sum = 0
2976 13:58:55.565869 2, 0xFFFF, sum = 0
2977 13:58:55.569367 3, 0xFFFF, sum = 0
2978 13:58:55.572484 4, 0xFFFF, sum = 0
2979 13:58:55.572570 5, 0xFFFF, sum = 0
2980 13:58:55.575707 6, 0xFFFF, sum = 0
2981 13:58:55.575817 7, 0xFFFF, sum = 0
2982 13:58:55.579468 8, 0xFFFF, sum = 0
2983 13:58:55.579551 9, 0xFFFF, sum = 0
2984 13:58:55.582403 10, 0xFFFF, sum = 0
2985 13:58:55.582485 11, 0xFFFF, sum = 0
2986 13:58:55.585974 12, 0x0, sum = 1
2987 13:58:55.586056 13, 0x0, sum = 2
2988 13:58:55.588948 14, 0x0, sum = 3
2989 13:58:55.589031 15, 0x0, sum = 4
2990 13:58:55.589097 best_step = 13
2991 13:58:55.592770
2992 13:58:55.592855 ==
2993 13:58:55.595818 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 13:58:55.599113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 13:58:55.599209 ==
2996 13:58:55.599278 RX Vref Scan: 0
2997 13:58:55.599340
2998 13:58:55.602214 RX Vref 0 -> 0, step: 1
2999 13:58:55.602295
3000 13:58:55.605581 RX Delay -21 -> 252, step: 4
3001 13:58:55.608875 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3002 13:58:55.615414 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3003 13:58:55.618876 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3004 13:58:55.622030 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3005 13:58:55.625554 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3006 13:58:55.628853 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3007 13:58:55.635321 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3008 13:58:55.638664 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3009 13:58:55.642152 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3010 13:58:55.645847 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3011 13:58:55.648842 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3012 13:58:55.655359 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3013 13:58:55.658945 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3014 13:58:55.662284 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3015 13:58:55.665577 iDelay=195, Bit 14, Center 118 (51 ~ 186) 136
3016 13:58:55.671741 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3017 13:58:55.671852 ==
3018 13:58:55.675108 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 13:58:55.678490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 13:58:55.678600 ==
3021 13:58:55.678694 DQS Delay:
3022 13:58:55.681549 DQS0 = 0, DQS1 = 0
3023 13:58:55.681650 DQM Delay:
3024 13:58:55.685046 DQM0 = 115, DQM1 = 105
3025 13:58:55.685143 DQ Delay:
3026 13:58:55.688371 DQ0 =112, DQ1 =116, DQ2 =110, DQ3 =112
3027 13:58:55.691623 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3028 13:58:55.695333 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =98
3029 13:58:55.698136 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3030 13:58:55.698244
3031 13:58:55.698336
3032 13:58:55.708200 [DQSOSCAuto] RK1, (LSB)MR18= 0xfffd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3033 13:58:55.711747 CH0 RK1: MR19=303, MR18=FFFD
3034 13:58:55.714941 CH0_RK1: MR19=0x303, MR18=0xFFFD, DQSOSC=410, MR23=63, INC=39, DEC=26
3035 13:58:55.717947 [RxdqsGatingPostProcess] freq 1200
3036 13:58:55.724833 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3037 13:58:55.728113 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 13:58:55.731409 best DQS1 dly(2T, 0.5T) = (0, 12)
3039 13:58:55.734720 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 13:58:55.737999 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3041 13:58:55.742078 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 13:58:55.744910 best DQS1 dly(2T, 0.5T) = (0, 11)
3043 13:58:55.748261 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 13:58:55.751332 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3045 13:58:55.751431 Pre-setting of DQS Precalculation
3046 13:58:55.758153 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3047 13:58:55.758252 ==
3048 13:58:55.761636 Dram Type= 6, Freq= 0, CH_1, rank 0
3049 13:58:55.765120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 13:58:55.765217 ==
3051 13:58:55.771154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3052 13:58:55.777933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3053 13:58:55.785342 [CA 0] Center 38 (8~68) winsize 61
3054 13:58:55.789053 [CA 1] Center 37 (7~68) winsize 62
3055 13:58:55.792349 [CA 2] Center 35 (5~65) winsize 61
3056 13:58:55.795329 [CA 3] Center 34 (4~64) winsize 61
3057 13:58:55.798744 [CA 4] Center 34 (4~64) winsize 61
3058 13:58:55.802419 [CA 5] Center 34 (4~64) winsize 61
3059 13:58:55.802521
3060 13:58:55.805896 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3061 13:58:55.805998
3062 13:58:55.808545 [CATrainingPosCal] consider 1 rank data
3063 13:58:55.812564 u2DelayCellTimex100 = 270/100 ps
3064 13:58:55.815780 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3065 13:58:55.818797 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3066 13:58:55.825262 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3067 13:58:55.828697 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3068 13:58:55.832006 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3069 13:58:55.835316 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3070 13:58:55.835410
3071 13:58:55.838882 CA PerBit enable=1, Macro0, CA PI delay=34
3072 13:58:55.838977
3073 13:58:55.842048 [CBTSetCACLKResult] CA Dly = 34
3074 13:58:55.842145 CS Dly: 5 (0~36)
3075 13:58:55.845278 ==
3076 13:58:55.845388 Dram Type= 6, Freq= 0, CH_1, rank 1
3077 13:58:55.852248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 13:58:55.852357 ==
3079 13:58:55.855422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3080 13:58:55.862225 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3081 13:58:55.870807 [CA 0] Center 37 (7~68) winsize 62
3082 13:58:55.874741 [CA 1] Center 37 (7~68) winsize 62
3083 13:58:55.877598 [CA 2] Center 35 (5~65) winsize 61
3084 13:58:55.881147 [CA 3] Center 33 (3~64) winsize 62
3085 13:58:55.884209 [CA 4] Center 34 (4~64) winsize 61
3086 13:58:55.887412 [CA 5] Center 33 (3~63) winsize 61
3087 13:58:55.887512
3088 13:58:55.890987 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3089 13:58:55.891109
3090 13:58:55.894052 [CATrainingPosCal] consider 2 rank data
3091 13:58:55.897624 u2DelayCellTimex100 = 270/100 ps
3092 13:58:55.900876 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3093 13:58:55.907565 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3094 13:58:55.910677 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3095 13:58:55.914359 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 13:58:55.917571 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 13:58:55.920714 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3098 13:58:55.920811
3099 13:58:55.924116 CA PerBit enable=1, Macro0, CA PI delay=33
3100 13:58:55.924221
3101 13:58:55.927187 [CBTSetCACLKResult] CA Dly = 33
3102 13:58:55.927293 CS Dly: 6 (0~39)
3103 13:58:55.931647
3104 13:58:55.934189 ----->DramcWriteLeveling(PI) begin...
3105 13:58:55.934271 ==
3106 13:58:55.937278 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 13:58:55.940729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 13:58:55.940812 ==
3109 13:58:55.944147 Write leveling (Byte 0): 24 => 24
3110 13:58:55.947522 Write leveling (Byte 1): 27 => 27
3111 13:58:55.950637 DramcWriteLeveling(PI) end<-----
3112 13:58:55.950736
3113 13:58:55.950829 ==
3114 13:58:55.954013 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 13:58:55.957180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 13:58:55.957277 ==
3117 13:58:55.960843 [Gating] SW mode calibration
3118 13:58:55.967339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3119 13:58:55.973821 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3120 13:58:55.977236 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3121 13:58:55.980480 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 13:58:55.987687 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 13:58:55.990393 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 13:58:55.994059 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 13:58:56.000517 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 13:58:56.003958 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3127 13:58:56.007276 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
3128 13:58:56.010720 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 13:58:56.017603 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 13:58:56.020404 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 13:58:56.023548 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 13:58:56.030281 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 13:58:56.034003 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 13:58:56.037070 1 0 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
3135 13:58:56.043527 1 0 28 | B1->B0 | 3e3e 4545 | 1 0 | (0 0) (0 0)
3136 13:58:56.047270 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 13:58:56.050081 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 13:58:56.056646 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 13:58:56.060238 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 13:58:56.063262 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 13:58:56.069604 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 13:58:56.072922 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 13:58:56.076529 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3144 13:58:56.082919 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 13:58:56.086379 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 13:58:56.090099 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 13:58:56.096583 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 13:58:56.099555 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 13:58:56.102745 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 13:58:56.109426 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 13:58:56.112545 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 13:58:56.116048 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 13:58:56.122618 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 13:58:56.125683 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 13:58:56.129088 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 13:58:56.135939 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 13:58:56.139284 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 13:58:56.142680 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 13:58:56.148922 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3160 13:58:56.152438 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 13:58:56.155874 Total UI for P1: 0, mck2ui 16
3162 13:58:56.158938 best dqsien dly found for B0: ( 1, 3, 28)
3163 13:58:56.162141 Total UI for P1: 0, mck2ui 16
3164 13:58:56.165850 best dqsien dly found for B1: ( 1, 3, 28)
3165 13:58:56.169053 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3166 13:58:56.171908 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3167 13:58:56.172030
3168 13:58:56.175409 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3169 13:58:56.179147 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3170 13:58:56.181975 [Gating] SW calibration Done
3171 13:58:56.182076 ==
3172 13:58:56.185721 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 13:58:56.192206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 13:58:56.192316 ==
3175 13:58:56.192415 RX Vref Scan: 0
3176 13:58:56.192516
3177 13:58:56.195696 RX Vref 0 -> 0, step: 1
3178 13:58:56.195804
3179 13:58:56.198964 RX Delay -40 -> 252, step: 8
3180 13:58:56.202139 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3181 13:58:56.205410 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3182 13:58:56.208744 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3183 13:58:56.212258 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3184 13:58:56.218981 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3185 13:58:56.222114 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3186 13:58:56.225307 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3187 13:58:56.229005 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3188 13:58:56.232026 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3189 13:58:56.238926 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3190 13:58:56.242036 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3191 13:58:56.246098 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3192 13:58:56.248948 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3193 13:58:56.251874 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3194 13:58:56.258761 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3195 13:58:56.261788 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3196 13:58:56.261886 ==
3197 13:58:56.265326 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 13:58:56.268845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 13:58:56.268944 ==
3200 13:58:56.271863 DQS Delay:
3201 13:58:56.271931 DQS0 = 0, DQS1 = 0
3202 13:58:56.271991 DQM Delay:
3203 13:58:56.275436 DQM0 = 116, DQM1 = 112
3204 13:58:56.275533 DQ Delay:
3205 13:58:56.278814 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3206 13:58:56.282102 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3207 13:58:56.285163 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3208 13:58:56.291957 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3209 13:58:56.292066
3210 13:58:56.292160
3211 13:58:56.292248 ==
3212 13:58:56.295611 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 13:58:56.298630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 13:58:56.298728 ==
3215 13:58:56.298827
3216 13:58:56.298916
3217 13:58:56.301845 TX Vref Scan disable
3218 13:58:56.301942 == TX Byte 0 ==
3219 13:58:56.308470 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3220 13:58:56.311686 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3221 13:58:56.311787 == TX Byte 1 ==
3222 13:58:56.318544 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3223 13:58:56.321549 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3224 13:58:56.321649 ==
3225 13:58:56.325176 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 13:58:56.328247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 13:58:56.328350 ==
3228 13:58:56.341442 TX Vref=22, minBit 3, minWin=24, winSum=408
3229 13:58:56.344490 TX Vref=24, minBit 9, minWin=24, winSum=416
3230 13:58:56.347977 TX Vref=26, minBit 3, minWin=25, winSum=423
3231 13:58:56.352139 TX Vref=28, minBit 9, minWin=25, winSum=426
3232 13:58:56.354747 TX Vref=30, minBit 9, minWin=25, winSum=427
3233 13:58:56.361546 TX Vref=32, minBit 8, minWin=26, winSum=428
3234 13:58:56.364397 [TxChooseVref] Worse bit 8, Min win 26, Win sum 428, Final Vref 32
3235 13:58:56.364500
3236 13:58:56.367907 Final TX Range 1 Vref 32
3237 13:58:56.368015
3238 13:58:56.368106 ==
3239 13:58:56.371393 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 13:58:56.374351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 13:58:56.374461 ==
3242 13:58:56.378244
3243 13:58:56.378345
3244 13:58:56.378446 TX Vref Scan disable
3245 13:58:56.381056 == TX Byte 0 ==
3246 13:58:56.384529 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3247 13:58:56.387835 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3248 13:58:56.390941 == TX Byte 1 ==
3249 13:58:56.394464 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3250 13:58:56.397664 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3251 13:58:56.401485
3252 13:58:56.401591 [DATLAT]
3253 13:58:56.401686 Freq=1200, CH1 RK0
3254 13:58:56.401774
3255 13:58:56.404364 DATLAT Default: 0xd
3256 13:58:56.404459 0, 0xFFFF, sum = 0
3257 13:58:56.407794 1, 0xFFFF, sum = 0
3258 13:58:56.407893 2, 0xFFFF, sum = 0
3259 13:58:56.411319 3, 0xFFFF, sum = 0
3260 13:58:56.411416 4, 0xFFFF, sum = 0
3261 13:58:56.414754 5, 0xFFFF, sum = 0
3262 13:58:56.417905 6, 0xFFFF, sum = 0
3263 13:58:56.418002 7, 0xFFFF, sum = 0
3264 13:58:56.420989 8, 0xFFFF, sum = 0
3265 13:58:56.421095 9, 0xFFFF, sum = 0
3266 13:58:56.424580 10, 0xFFFF, sum = 0
3267 13:58:56.424683 11, 0xFFFF, sum = 0
3268 13:58:56.427874 12, 0x0, sum = 1
3269 13:58:56.427972 13, 0x0, sum = 2
3270 13:58:56.431195 14, 0x0, sum = 3
3271 13:58:56.431304 15, 0x0, sum = 4
3272 13:58:56.431395 best_step = 13
3273 13:58:56.431491
3274 13:58:56.434171 ==
3275 13:58:56.437931 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 13:58:56.441144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 13:58:56.441245 ==
3278 13:58:56.441347 RX Vref Scan: 1
3279 13:58:56.441438
3280 13:58:56.444032 Set Vref Range= 32 -> 127
3281 13:58:56.444134
3282 13:58:56.447485 RX Vref 32 -> 127, step: 1
3283 13:58:56.447556
3284 13:58:56.450677 RX Delay -13 -> 252, step: 4
3285 13:58:56.450774
3286 13:58:56.454384 Set Vref, RX VrefLevel [Byte0]: 32
3287 13:58:56.457317 [Byte1]: 32
3288 13:58:56.457420
3289 13:58:56.460726 Set Vref, RX VrefLevel [Byte0]: 33
3290 13:58:56.464848 [Byte1]: 33
3291 13:58:56.464956
3292 13:58:56.467477 Set Vref, RX VrefLevel [Byte0]: 34
3293 13:58:56.471205 [Byte1]: 34
3294 13:58:56.475926
3295 13:58:56.476028 Set Vref, RX VrefLevel [Byte0]: 35
3296 13:58:56.478598 [Byte1]: 35
3297 13:58:56.483227
3298 13:58:56.483303 Set Vref, RX VrefLevel [Byte0]: 36
3299 13:58:56.486742 [Byte1]: 36
3300 13:58:56.491179
3301 13:58:56.491278 Set Vref, RX VrefLevel [Byte0]: 37
3302 13:58:56.494540 [Byte1]: 37
3303 13:58:56.498907
3304 13:58:56.499001 Set Vref, RX VrefLevel [Byte0]: 38
3305 13:58:56.502240 [Byte1]: 38
3306 13:58:56.506637
3307 13:58:56.506734 Set Vref, RX VrefLevel [Byte0]: 39
3308 13:58:56.510011 [Byte1]: 39
3309 13:58:56.514639
3310 13:58:56.514736 Set Vref, RX VrefLevel [Byte0]: 40
3311 13:58:56.518368 [Byte1]: 40
3312 13:58:56.522476
3313 13:58:56.522583 Set Vref, RX VrefLevel [Byte0]: 41
3314 13:58:56.525880 [Byte1]: 41
3315 13:58:56.530714
3316 13:58:56.530820 Set Vref, RX VrefLevel [Byte0]: 42
3317 13:58:56.533603 [Byte1]: 42
3318 13:58:56.538102
3319 13:58:56.538208 Set Vref, RX VrefLevel [Byte0]: 43
3320 13:58:56.541887 [Byte1]: 43
3321 13:58:56.546060
3322 13:58:56.546147 Set Vref, RX VrefLevel [Byte0]: 44
3323 13:58:56.549539 [Byte1]: 44
3324 13:58:56.554167
3325 13:58:56.554276 Set Vref, RX VrefLevel [Byte0]: 45
3326 13:58:56.557333 [Byte1]: 45
3327 13:58:56.562138
3328 13:58:56.562241 Set Vref, RX VrefLevel [Byte0]: 46
3329 13:58:56.565383 [Byte1]: 46
3330 13:58:56.569743
3331 13:58:56.569841 Set Vref, RX VrefLevel [Byte0]: 47
3332 13:58:56.573061 [Byte1]: 47
3333 13:58:56.577758
3334 13:58:56.577863 Set Vref, RX VrefLevel [Byte0]: 48
3335 13:58:56.580875 [Byte1]: 48
3336 13:58:56.585749
3337 13:58:56.585856 Set Vref, RX VrefLevel [Byte0]: 49
3338 13:58:56.589035 [Byte1]: 49
3339 13:58:56.593944
3340 13:58:56.594050 Set Vref, RX VrefLevel [Byte0]: 50
3341 13:58:56.596807 [Byte1]: 50
3342 13:58:56.601170
3343 13:58:56.601272 Set Vref, RX VrefLevel [Byte0]: 51
3344 13:58:56.604520 [Byte1]: 51
3345 13:58:56.609190
3346 13:58:56.609291 Set Vref, RX VrefLevel [Byte0]: 52
3347 13:58:56.612573 [Byte1]: 52
3348 13:58:56.617548
3349 13:58:56.617650 Set Vref, RX VrefLevel [Byte0]: 53
3350 13:58:56.620596 [Byte1]: 53
3351 13:58:56.625194
3352 13:58:56.625288 Set Vref, RX VrefLevel [Byte0]: 54
3353 13:58:56.628121 [Byte1]: 54
3354 13:58:56.632935
3355 13:58:56.636200 Set Vref, RX VrefLevel [Byte0]: 55
3356 13:58:56.639191 [Byte1]: 55
3357 13:58:56.639286
3358 13:58:56.642616 Set Vref, RX VrefLevel [Byte0]: 56
3359 13:58:56.645999 [Byte1]: 56
3360 13:58:56.646099
3361 13:58:56.649225 Set Vref, RX VrefLevel [Byte0]: 57
3362 13:58:56.652423 [Byte1]: 57
3363 13:58:56.656313
3364 13:58:56.656412 Set Vref, RX VrefLevel [Byte0]: 58
3365 13:58:56.659958 [Byte1]: 58
3366 13:58:56.664567
3367 13:58:56.664661 Set Vref, RX VrefLevel [Byte0]: 59
3368 13:58:56.667712 [Byte1]: 59
3369 13:58:56.672318
3370 13:58:56.672388 Set Vref, RX VrefLevel [Byte0]: 60
3371 13:58:56.675691 [Byte1]: 60
3372 13:58:56.680436
3373 13:58:56.680544 Set Vref, RX VrefLevel [Byte0]: 61
3374 13:58:56.683844 [Byte1]: 61
3375 13:58:56.688057
3376 13:58:56.688159 Set Vref, RX VrefLevel [Byte0]: 62
3377 13:58:56.691448 [Byte1]: 62
3378 13:58:56.696453
3379 13:58:56.696553 Set Vref, RX VrefLevel [Byte0]: 63
3380 13:58:56.699849 [Byte1]: 63
3381 13:58:56.703718
3382 13:58:56.703828 Set Vref, RX VrefLevel [Byte0]: 64
3383 13:58:56.707520 [Byte1]: 64
3384 13:58:56.711485
3385 13:58:56.711584 Set Vref, RX VrefLevel [Byte0]: 65
3386 13:58:56.715199 [Byte1]: 65
3387 13:58:56.719392
3388 13:58:56.719489 Final RX Vref Byte 0 = 51 to rank0
3389 13:58:56.723061 Final RX Vref Byte 1 = 53 to rank0
3390 13:58:56.726132 Final RX Vref Byte 0 = 51 to rank1
3391 13:58:56.729651 Final RX Vref Byte 1 = 53 to rank1==
3392 13:58:56.732831 Dram Type= 6, Freq= 0, CH_1, rank 0
3393 13:58:56.739381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3394 13:58:56.739484 ==
3395 13:58:56.739577 DQS Delay:
3396 13:58:56.739671 DQS0 = 0, DQS1 = 0
3397 13:58:56.742840 DQM Delay:
3398 13:58:56.742950 DQM0 = 114, DQM1 = 113
3399 13:58:56.745934 DQ Delay:
3400 13:58:56.749427 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3401 13:58:56.752954 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3402 13:58:56.755795 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =108
3403 13:58:56.759071 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =122
3404 13:58:56.759190
3405 13:58:56.759253
3406 13:58:56.769596 [DQSOSCAuto] RK0, (LSB)MR18= 0xf703, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3407 13:58:56.769696 CH1 RK0: MR19=304, MR18=F703
3408 13:58:56.776047 CH1_RK0: MR19=0x304, MR18=0xF703, DQSOSC=408, MR23=63, INC=39, DEC=26
3409 13:58:56.776146
3410 13:58:56.779427 ----->DramcWriteLeveling(PI) begin...
3411 13:58:56.779601 ==
3412 13:58:56.782399 Dram Type= 6, Freq= 0, CH_1, rank 1
3413 13:58:56.788978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 13:58:56.789085 ==
3415 13:58:56.792305 Write leveling (Byte 0): 25 => 25
3416 13:58:56.792406 Write leveling (Byte 1): 28 => 28
3417 13:58:56.795833 DramcWriteLeveling(PI) end<-----
3418 13:58:56.795929
3419 13:58:56.800076 ==
3420 13:58:56.800173 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 13:58:56.805840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 13:58:56.805935 ==
3423 13:58:56.809098 [Gating] SW mode calibration
3424 13:58:56.815670 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3425 13:58:56.819402 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3426 13:58:56.825956 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 13:58:56.829251 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 13:58:56.832785 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 13:58:56.839002 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 13:58:56.843107 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 13:58:56.845966 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3432 13:58:56.852361 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
3433 13:58:56.855895 0 15 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
3434 13:58:56.858998 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 13:58:56.865437 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 13:58:56.869484 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 13:58:56.872492 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 13:58:56.879196 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 13:58:56.882168 1 0 20 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
3440 13:58:56.885333 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3441 13:58:56.888993 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3442 13:58:56.895263 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 13:58:56.898522 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 13:58:56.901987 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 13:58:56.908514 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 13:58:56.911636 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 13:58:56.918585 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3448 13:58:56.921781 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3449 13:58:56.925476 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3450 13:58:56.928479 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 13:58:56.935195 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 13:58:56.938154 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 13:58:56.941929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 13:58:56.948456 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 13:58:56.951834 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 13:58:56.954930 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 13:58:56.961823 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 13:58:56.965471 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 13:58:56.968362 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 13:58:56.975165 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 13:58:56.978068 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 13:58:56.981576 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 13:58:56.987769 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3464 13:58:56.991616 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3465 13:58:56.994402 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3466 13:58:56.997857 Total UI for P1: 0, mck2ui 16
3467 13:58:57.001166 best dqsien dly found for B0: ( 1, 3, 22)
3468 13:58:57.007694 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 13:58:57.007809 Total UI for P1: 0, mck2ui 16
3470 13:58:57.014332 best dqsien dly found for B1: ( 1, 3, 28)
3471 13:58:57.017780 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3472 13:58:57.020758 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3473 13:58:57.020878
3474 13:58:57.024398 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3475 13:58:57.027930 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3476 13:58:57.031149 [Gating] SW calibration Done
3477 13:58:57.031234 ==
3478 13:58:57.034056 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 13:58:57.037880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 13:58:57.037963 ==
3481 13:58:57.040774 RX Vref Scan: 0
3482 13:58:57.040888
3483 13:58:57.041027 RX Vref 0 -> 0, step: 1
3484 13:58:57.044157
3485 13:58:57.044255 RX Delay -40 -> 252, step: 8
3486 13:58:57.050490 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3487 13:58:57.053833 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3488 13:58:57.057451 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3489 13:58:57.061046 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3490 13:58:57.063954 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3491 13:58:57.070319 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3492 13:58:57.073912 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3493 13:58:57.077326 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3494 13:58:57.080547 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3495 13:58:57.084151 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3496 13:58:57.090067 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3497 13:58:57.093303 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3498 13:58:57.096839 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3499 13:58:57.099930 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3500 13:58:57.106527 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3501 13:58:57.109950 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3502 13:58:57.110031 ==
3503 13:58:57.113409 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 13:58:57.116542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 13:58:57.116625 ==
3506 13:58:57.116690 DQS Delay:
3507 13:58:57.119836 DQS0 = 0, DQS1 = 0
3508 13:58:57.119916 DQM Delay:
3509 13:58:57.123317 DQM0 = 114, DQM1 = 111
3510 13:58:57.123399 DQ Delay:
3511 13:58:57.126752 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3512 13:58:57.129489 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3513 13:58:57.132806 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3514 13:58:57.139991 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3515 13:58:57.140073
3516 13:58:57.140138
3517 13:58:57.140199 ==
3518 13:58:57.142738 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 13:58:57.146563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 13:58:57.146645 ==
3521 13:58:57.146711
3522 13:58:57.146771
3523 13:58:57.149355 TX Vref Scan disable
3524 13:58:57.149436 == TX Byte 0 ==
3525 13:58:57.156259 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3526 13:58:57.159473 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3527 13:58:57.159554 == TX Byte 1 ==
3528 13:58:57.165954 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3529 13:58:57.169701 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3530 13:58:57.169786 ==
3531 13:58:57.172471 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 13:58:57.176077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 13:58:57.176160 ==
3534 13:58:57.188887 TX Vref=22, minBit 9, minWin=25, winSum=422
3535 13:58:57.192136 TX Vref=24, minBit 9, minWin=25, winSum=422
3536 13:58:57.195514 TX Vref=26, minBit 1, minWin=26, winSum=431
3537 13:58:57.198640 TX Vref=28, minBit 9, minWin=24, winSum=428
3538 13:58:57.202090 TX Vref=30, minBit 1, minWin=26, winSum=434
3539 13:58:57.208334 TX Vref=32, minBit 8, minWin=26, winSum=434
3540 13:58:57.212086 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 30
3541 13:58:57.212168
3542 13:58:57.215296 Final TX Range 1 Vref 30
3543 13:58:57.215408
3544 13:58:57.215500 ==
3545 13:58:57.218633 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 13:58:57.222031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 13:58:57.224892 ==
3548 13:58:57.224972
3549 13:58:57.225037
3550 13:58:57.225097 TX Vref Scan disable
3551 13:58:57.228602 == TX Byte 0 ==
3552 13:58:57.232158 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3553 13:58:57.238102 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3554 13:58:57.238183 == TX Byte 1 ==
3555 13:58:57.241594 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3556 13:58:57.248171 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3557 13:58:57.248253
3558 13:58:57.248318 [DATLAT]
3559 13:58:57.248378 Freq=1200, CH1 RK1
3560 13:58:57.248463
3561 13:58:57.251484 DATLAT Default: 0xd
3562 13:58:57.254925 0, 0xFFFF, sum = 0
3563 13:58:57.255008 1, 0xFFFF, sum = 0
3564 13:58:57.258124 2, 0xFFFF, sum = 0
3565 13:58:57.258207 3, 0xFFFF, sum = 0
3566 13:58:57.261256 4, 0xFFFF, sum = 0
3567 13:58:57.261338 5, 0xFFFF, sum = 0
3568 13:58:57.264266 6, 0xFFFF, sum = 0
3569 13:58:57.264349 7, 0xFFFF, sum = 0
3570 13:58:57.267872 8, 0xFFFF, sum = 0
3571 13:58:57.267955 9, 0xFFFF, sum = 0
3572 13:58:57.271103 10, 0xFFFF, sum = 0
3573 13:58:57.271200 11, 0xFFFF, sum = 0
3574 13:58:57.274706 12, 0x0, sum = 1
3575 13:58:57.274789 13, 0x0, sum = 2
3576 13:58:57.277508 14, 0x0, sum = 3
3577 13:58:57.277591 15, 0x0, sum = 4
3578 13:58:57.280977 best_step = 13
3579 13:58:57.281059
3580 13:58:57.281123 ==
3581 13:58:57.284308 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 13:58:57.287652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 13:58:57.287734 ==
3584 13:58:57.290641 RX Vref Scan: 0
3585 13:58:57.290722
3586 13:58:57.290786 RX Vref 0 -> 0, step: 1
3587 13:58:57.290846
3588 13:58:57.294523 RX Delay -13 -> 252, step: 4
3589 13:58:57.300445 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3590 13:58:57.303956 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3591 13:58:57.307675 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3592 13:58:57.310846 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3593 13:58:57.317566 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3594 13:58:57.320506 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3595 13:58:57.323493 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3596 13:58:57.327359 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3597 13:58:57.330532 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3598 13:58:57.337195 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3599 13:58:57.340189 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3600 13:58:57.343727 iDelay=195, Bit 11, Center 108 (47 ~ 170) 124
3601 13:58:57.346700 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3602 13:58:57.349995 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3603 13:58:57.356693 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3604 13:58:57.359719 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3605 13:58:57.359801 ==
3606 13:58:57.363505 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 13:58:57.366541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 13:58:57.366622 ==
3609 13:58:57.369502 DQS Delay:
3610 13:58:57.369583 DQS0 = 0, DQS1 = 0
3611 13:58:57.373171 DQM Delay:
3612 13:58:57.373251 DQM0 = 115, DQM1 = 112
3613 13:58:57.373316 DQ Delay:
3614 13:58:57.379360 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3615 13:58:57.382967 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =114
3616 13:58:57.385956 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =108
3617 13:58:57.389340 DQ12 =120, DQ13 =116, DQ14 =118, DQ15 =122
3618 13:58:57.389422
3619 13:58:57.389486
3620 13:58:57.396133 [DQSOSCAuto] RK1, (LSB)MR18= 0xf80a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3621 13:58:57.399313 CH1 RK1: MR19=304, MR18=F80A
3622 13:58:57.405758 CH1_RK1: MR19=0x304, MR18=0xF80A, DQSOSC=406, MR23=63, INC=39, DEC=26
3623 13:58:57.409731 [RxdqsGatingPostProcess] freq 1200
3624 13:58:57.416103 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3625 13:58:57.419241 best DQS0 dly(2T, 0.5T) = (0, 11)
3626 13:58:57.419323 best DQS1 dly(2T, 0.5T) = (0, 11)
3627 13:58:57.422513 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3628 13:58:57.425855 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3629 13:58:57.429224 best DQS0 dly(2T, 0.5T) = (0, 11)
3630 13:58:57.432448 best DQS1 dly(2T, 0.5T) = (0, 11)
3631 13:58:57.435608 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3632 13:58:57.439257 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3633 13:58:57.442464 Pre-setting of DQS Precalculation
3634 13:58:57.449214 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3635 13:58:57.455388 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3636 13:58:57.462157 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3637 13:58:57.462239
3638 13:58:57.462303
3639 13:58:57.465213 [Calibration Summary] 2400 Mbps
3640 13:58:57.465295 CH 0, Rank 0
3641 13:58:57.468618 SW Impedance : PASS
3642 13:58:57.472421 DUTY Scan : NO K
3643 13:58:57.472503 ZQ Calibration : PASS
3644 13:58:57.475558 Jitter Meter : NO K
3645 13:58:57.478791 CBT Training : PASS
3646 13:58:57.478873 Write leveling : PASS
3647 13:58:57.481723 RX DQS gating : PASS
3648 13:58:57.484883 RX DQ/DQS(RDDQC) : PASS
3649 13:58:57.484964 TX DQ/DQS : PASS
3650 13:58:57.488571 RX DATLAT : PASS
3651 13:58:57.491382 RX DQ/DQS(Engine): PASS
3652 13:58:57.491463 TX OE : NO K
3653 13:58:57.494850 All Pass.
3654 13:58:57.494930
3655 13:58:57.494994 CH 0, Rank 1
3656 13:58:57.498164 SW Impedance : PASS
3657 13:58:57.498245 DUTY Scan : NO K
3658 13:58:57.501313 ZQ Calibration : PASS
3659 13:58:57.504934 Jitter Meter : NO K
3660 13:58:57.505015 CBT Training : PASS
3661 13:58:57.507931 Write leveling : PASS
3662 13:58:57.511328 RX DQS gating : PASS
3663 13:58:57.511410 RX DQ/DQS(RDDQC) : PASS
3664 13:58:57.514808 TX DQ/DQS : PASS
3665 13:58:57.518153 RX DATLAT : PASS
3666 13:58:57.518234 RX DQ/DQS(Engine): PASS
3667 13:58:57.520921 TX OE : NO K
3668 13:58:57.521002 All Pass.
3669 13:58:57.521067
3670 13:58:57.524145 CH 1, Rank 0
3671 13:58:57.524226 SW Impedance : PASS
3672 13:58:57.527514 DUTY Scan : NO K
3673 13:58:57.531307 ZQ Calibration : PASS
3674 13:58:57.531388 Jitter Meter : NO K
3675 13:58:57.534505 CBT Training : PASS
3676 13:58:57.534586 Write leveling : PASS
3677 13:58:57.537506 RX DQS gating : PASS
3678 13:58:57.540820 RX DQ/DQS(RDDQC) : PASS
3679 13:58:57.540901 TX DQ/DQS : PASS
3680 13:58:57.543993 RX DATLAT : PASS
3681 13:58:57.547608 RX DQ/DQS(Engine): PASS
3682 13:58:57.547733 TX OE : NO K
3683 13:58:57.550888 All Pass.
3684 13:58:57.550969
3685 13:58:57.551033 CH 1, Rank 1
3686 13:58:57.554088 SW Impedance : PASS
3687 13:58:57.554169 DUTY Scan : NO K
3688 13:58:57.557265 ZQ Calibration : PASS
3689 13:58:57.560847 Jitter Meter : NO K
3690 13:58:57.560945 CBT Training : PASS
3691 13:58:57.563917 Write leveling : PASS
3692 13:58:57.567234 RX DQS gating : PASS
3693 13:58:57.567345 RX DQ/DQS(RDDQC) : PASS
3694 13:58:57.570899 TX DQ/DQS : PASS
3695 13:58:57.574133 RX DATLAT : PASS
3696 13:58:57.574237 RX DQ/DQS(Engine): PASS
3697 13:58:57.577654 TX OE : NO K
3698 13:58:57.577764 All Pass.
3699 13:58:57.577858
3700 13:58:57.580750 DramC Write-DBI off
3701 13:58:57.584257 PER_BANK_REFRESH: Hybrid Mode
3702 13:58:57.584366 TX_TRACKING: ON
3703 13:58:57.593798 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3704 13:58:57.601074 [FAST_K] Save calibration result to emmc
3705 13:58:57.601181 dramc_set_vcore_voltage set vcore to 650000
3706 13:58:57.603821 Read voltage for 600, 5
3707 13:58:57.603920 Vio18 = 0
3708 13:58:57.604023 Vcore = 650000
3709 13:58:57.606753 Vdram = 0
3710 13:58:57.606850 Vddq = 0
3711 13:58:57.606946 Vmddr = 0
3712 13:58:57.614040 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3713 13:58:57.616999 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3714 13:58:57.619999 MEM_TYPE=3, freq_sel=19
3715 13:58:57.623412 sv_algorithm_assistance_LP4_1600
3716 13:58:57.626603 ============ PULL DRAM RESETB DOWN ============
3717 13:58:57.633185 ========== PULL DRAM RESETB DOWN end =========
3718 13:58:57.636405 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3719 13:58:57.639968 ===================================
3720 13:58:57.642922 LPDDR4 DRAM CONFIGURATION
3721 13:58:57.646401 ===================================
3722 13:58:57.646512 EX_ROW_EN[0] = 0x0
3723 13:58:57.649681 EX_ROW_EN[1] = 0x0
3724 13:58:57.649783 LP4Y_EN = 0x0
3725 13:58:57.652879 WORK_FSP = 0x0
3726 13:58:57.652982 WL = 0x2
3727 13:58:57.656228 RL = 0x2
3728 13:58:57.656329 BL = 0x2
3729 13:58:57.659405 RPST = 0x0
3730 13:58:57.659506 RD_PRE = 0x0
3731 13:58:57.662851 WR_PRE = 0x1
3732 13:58:57.665995 WR_PST = 0x0
3733 13:58:57.666097 DBI_WR = 0x0
3734 13:58:57.669111 DBI_RD = 0x0
3735 13:58:57.669211 OTF = 0x1
3736 13:58:57.672577 ===================================
3737 13:58:57.675775 ===================================
3738 13:58:57.679360 ANA top config
3739 13:58:57.682787 ===================================
3740 13:58:57.682904 DLL_ASYNC_EN = 0
3741 13:58:57.685913 ALL_SLAVE_EN = 1
3742 13:58:57.689016 NEW_RANK_MODE = 1
3743 13:58:57.692619 DLL_IDLE_MODE = 1
3744 13:58:57.692699 LP45_APHY_COMB_EN = 1
3745 13:58:57.695919 TX_ODT_DIS = 1
3746 13:58:57.698915 NEW_8X_MODE = 1
3747 13:58:57.702397 ===================================
3748 13:58:57.705387 ===================================
3749 13:58:57.708902 data_rate = 1200
3750 13:58:57.712093 CKR = 1
3751 13:58:57.715376 DQ_P2S_RATIO = 8
3752 13:58:57.718818 ===================================
3753 13:58:57.718900 CA_P2S_RATIO = 8
3754 13:58:57.721807 DQ_CA_OPEN = 0
3755 13:58:57.725378 DQ_SEMI_OPEN = 0
3756 13:58:57.729051 CA_SEMI_OPEN = 0
3757 13:58:57.731944 CA_FULL_RATE = 0
3758 13:58:57.735018 DQ_CKDIV4_EN = 1
3759 13:58:57.735120 CA_CKDIV4_EN = 1
3760 13:58:57.738293 CA_PREDIV_EN = 0
3761 13:58:57.742136 PH8_DLY = 0
3762 13:58:57.745196 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3763 13:58:57.748411 DQ_AAMCK_DIV = 4
3764 13:58:57.751467 CA_AAMCK_DIV = 4
3765 13:58:57.751549 CA_ADMCK_DIV = 4
3766 13:58:57.754758 DQ_TRACK_CA_EN = 0
3767 13:58:57.758453 CA_PICK = 600
3768 13:58:57.761525 CA_MCKIO = 600
3769 13:58:57.764545 MCKIO_SEMI = 0
3770 13:58:57.767916 PLL_FREQ = 2288
3771 13:58:57.771272 DQ_UI_PI_RATIO = 32
3772 13:58:57.774558 CA_UI_PI_RATIO = 0
3773 13:58:57.777800 ===================================
3774 13:58:57.781103 ===================================
3775 13:58:57.781184 memory_type:LPDDR4
3776 13:58:57.784365 GP_NUM : 10
3777 13:58:57.787722 SRAM_EN : 1
3778 13:58:57.787803 MD32_EN : 0
3779 13:58:57.790842 ===================================
3780 13:58:57.794068 [ANA_INIT] >>>>>>>>>>>>>>
3781 13:58:57.797709 <<<<<< [CONFIGURE PHASE]: ANA_TX
3782 13:58:57.800914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3783 13:58:57.804260 ===================================
3784 13:58:57.808090 data_rate = 1200,PCW = 0X5800
3785 13:58:57.810766 ===================================
3786 13:58:57.814074 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3787 13:58:57.817248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3788 13:58:57.823950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3789 13:58:57.827030 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3790 13:58:57.830577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3791 13:58:57.837362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3792 13:58:57.837464 [ANA_INIT] flow start
3793 13:58:57.840183 [ANA_INIT] PLL >>>>>>>>
3794 13:58:57.840283 [ANA_INIT] PLL <<<<<<<<
3795 13:58:57.844032 [ANA_INIT] MIDPI >>>>>>>>
3796 13:58:57.847061 [ANA_INIT] MIDPI <<<<<<<<
3797 13:58:57.850264 [ANA_INIT] DLL >>>>>>>>
3798 13:58:57.850364 [ANA_INIT] flow end
3799 13:58:57.853620 ============ LP4 DIFF to SE enter ============
3800 13:58:57.860256 ============ LP4 DIFF to SE exit ============
3801 13:58:57.860356 [ANA_INIT] <<<<<<<<<<<<<
3802 13:58:57.863257 [Flow] Enable top DCM control >>>>>
3803 13:58:57.866671 [Flow] Enable top DCM control <<<<<
3804 13:58:57.869851 Enable DLL master slave shuffle
3805 13:58:57.876699 ==============================================================
3806 13:58:57.880123 Gating Mode config
3807 13:58:57.884059 ==============================================================
3808 13:58:57.886434 Config description:
3809 13:58:57.896356 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3810 13:58:57.902952 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3811 13:58:57.906343 SELPH_MODE 0: By rank 1: By Phase
3812 13:58:57.912858 ==============================================================
3813 13:58:57.915962 GAT_TRACK_EN = 1
3814 13:58:57.919511 RX_GATING_MODE = 2
3815 13:58:57.922435 RX_GATING_TRACK_MODE = 2
3816 13:58:57.925985 SELPH_MODE = 1
3817 13:58:57.926113 PICG_EARLY_EN = 1
3818 13:58:57.929367 VALID_LAT_VALUE = 1
3819 13:58:57.935674 ==============================================================
3820 13:58:57.938837 Enter into Gating configuration >>>>
3821 13:58:57.942202 Exit from Gating configuration <<<<
3822 13:58:57.945939 Enter into DVFS_PRE_config >>>>>
3823 13:58:57.955647 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3824 13:58:57.958693 Exit from DVFS_PRE_config <<<<<
3825 13:58:57.962070 Enter into PICG configuration >>>>
3826 13:58:57.965463 Exit from PICG configuration <<<<
3827 13:58:57.968590 [RX_INPUT] configuration >>>>>
3828 13:58:57.972231 [RX_INPUT] configuration <<<<<
3829 13:58:57.978683 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3830 13:58:57.981981 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3831 13:58:57.988596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3832 13:58:57.994961 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3833 13:58:58.002485 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3834 13:58:58.008165 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3835 13:58:58.011635 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3836 13:58:58.015036 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3837 13:58:58.018577 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3838 13:58:58.025138 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3839 13:58:58.028691 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3840 13:58:58.031231 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3841 13:58:58.034511 ===================================
3842 13:58:58.038231 LPDDR4 DRAM CONFIGURATION
3843 13:58:58.041268 ===================================
3844 13:58:58.044436 EX_ROW_EN[0] = 0x0
3845 13:58:58.044517 EX_ROW_EN[1] = 0x0
3846 13:58:58.047477 LP4Y_EN = 0x0
3847 13:58:58.047560 WORK_FSP = 0x0
3848 13:58:58.051101 WL = 0x2
3849 13:58:58.051198 RL = 0x2
3850 13:58:58.054789 BL = 0x2
3851 13:58:58.054870 RPST = 0x0
3852 13:58:58.057921 RD_PRE = 0x0
3853 13:58:58.058002 WR_PRE = 0x1
3854 13:58:58.060897 WR_PST = 0x0
3855 13:58:58.060977 DBI_WR = 0x0
3856 13:58:58.064166 DBI_RD = 0x0
3857 13:58:58.064247 OTF = 0x1
3858 13:58:58.067326 ===================================
3859 13:58:58.073854 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3860 13:58:58.077521 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3861 13:58:58.080964 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 13:58:58.084150 ===================================
3863 13:58:58.087413 LPDDR4 DRAM CONFIGURATION
3864 13:58:58.090647 ===================================
3865 13:58:58.093810 EX_ROW_EN[0] = 0x10
3866 13:58:58.093892 EX_ROW_EN[1] = 0x0
3867 13:58:58.097510 LP4Y_EN = 0x0
3868 13:58:58.097591 WORK_FSP = 0x0
3869 13:58:58.100797 WL = 0x2
3870 13:58:58.100878 RL = 0x2
3871 13:58:58.103536 BL = 0x2
3872 13:58:58.103617 RPST = 0x0
3873 13:58:58.107130 RD_PRE = 0x0
3874 13:58:58.107211 WR_PRE = 0x1
3875 13:58:58.110265 WR_PST = 0x0
3876 13:58:58.110373 DBI_WR = 0x0
3877 13:58:58.113332 DBI_RD = 0x0
3878 13:58:58.113413 OTF = 0x1
3879 13:58:58.117325 ===================================
3880 13:58:58.123373 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3881 13:58:58.128357 nWR fixed to 30
3882 13:58:58.131721 [ModeRegInit_LP4] CH0 RK0
3883 13:58:58.131803 [ModeRegInit_LP4] CH0 RK1
3884 13:58:58.134908 [ModeRegInit_LP4] CH1 RK0
3885 13:58:58.138145 [ModeRegInit_LP4] CH1 RK1
3886 13:58:58.138252 match AC timing 17
3887 13:58:58.145271 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3888 13:58:58.148342 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3889 13:58:58.151762 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3890 13:58:58.158074 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3891 13:58:58.162283 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3892 13:58:58.162404 ==
3893 13:58:58.164810 Dram Type= 6, Freq= 0, CH_0, rank 0
3894 13:58:58.167841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3895 13:58:58.167923 ==
3896 13:58:58.174315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3897 13:58:58.181454 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3898 13:58:58.184559 [CA 0] Center 36 (6~67) winsize 62
3899 13:58:58.187707 [CA 1] Center 36 (5~67) winsize 63
3900 13:58:58.191426 [CA 2] Center 34 (4~65) winsize 62
3901 13:58:58.194451 [CA 3] Center 34 (4~65) winsize 62
3902 13:58:58.197790 [CA 4] Center 33 (3~64) winsize 62
3903 13:58:58.201105 [CA 5] Center 33 (2~64) winsize 63
3904 13:58:58.201186
3905 13:58:58.204442 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3906 13:58:58.204523
3907 13:58:58.207302 [CATrainingPosCal] consider 1 rank data
3908 13:58:58.210823 u2DelayCellTimex100 = 270/100 ps
3909 13:58:58.214238 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3910 13:58:58.217096 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3911 13:58:58.221025 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3912 13:58:58.227133 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3913 13:58:58.230467 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3914 13:58:58.233923 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3915 13:58:58.234004
3916 13:58:58.237210 CA PerBit enable=1, Macro0, CA PI delay=33
3917 13:58:58.237291
3918 13:58:58.240132 [CBTSetCACLKResult] CA Dly = 33
3919 13:58:58.240214 CS Dly: 5 (0~36)
3920 13:58:58.240278 ==
3921 13:58:58.243704 Dram Type= 6, Freq= 0, CH_0, rank 1
3922 13:58:58.250143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 13:58:58.250226 ==
3924 13:58:58.253563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 13:58:58.260299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3926 13:58:58.263861 [CA 0] Center 36 (6~67) winsize 62
3927 13:58:58.267176 [CA 1] Center 36 (6~67) winsize 62
3928 13:58:58.270620 [CA 2] Center 34 (4~65) winsize 62
3929 13:58:58.273757 [CA 3] Center 34 (4~65) winsize 62
3930 13:58:58.276943 [CA 4] Center 34 (3~65) winsize 63
3931 13:58:58.280084 [CA 5] Center 33 (3~64) winsize 62
3932 13:58:58.280192
3933 13:58:58.283674 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3934 13:58:58.283756
3935 13:58:58.287325 [CATrainingPosCal] consider 2 rank data
3936 13:58:58.290193 u2DelayCellTimex100 = 270/100 ps
3937 13:58:58.293266 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3938 13:58:58.299905 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3939 13:58:58.303211 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3940 13:58:58.306916 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3941 13:58:58.309852 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3942 13:58:58.313228 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3943 13:58:58.313309
3944 13:58:58.316666 CA PerBit enable=1, Macro0, CA PI delay=33
3945 13:58:58.316746
3946 13:58:58.320087 [CBTSetCACLKResult] CA Dly = 33
3947 13:58:58.323015 CS Dly: 5 (0~37)
3948 13:58:58.323153
3949 13:58:58.326411 ----->DramcWriteLeveling(PI) begin...
3950 13:58:58.326492 ==
3951 13:58:58.330104 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 13:58:58.332949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 13:58:58.333030 ==
3954 13:58:58.336646 Write leveling (Byte 0): 31 => 31
3955 13:58:58.339535 Write leveling (Byte 1): 28 => 28
3956 13:58:58.342942 DramcWriteLeveling(PI) end<-----
3957 13:58:58.343048
3958 13:58:58.343163 ==
3959 13:58:58.346311 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 13:58:58.349405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 13:58:58.349486 ==
3962 13:58:58.353146 [Gating] SW mode calibration
3963 13:58:58.359350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3964 13:58:58.366156 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3965 13:58:58.369407 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 13:58:58.372458 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3967 13:58:58.379305 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 13:58:58.383053 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3969 13:58:58.385695 0 9 16 | B1->B0 | 3030 2424 | 0 0 | (1 1) (0 0)
3970 13:58:58.392180 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3971 13:58:58.395632 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 13:58:58.399356 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 13:58:58.406033 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 13:58:58.408988 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 13:58:58.412056 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 13:58:58.418713 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3977 13:58:58.421883 0 10 16 | B1->B0 | 3a3a 4040 | 0 0 | (0 0) (0 0)
3978 13:58:58.425569 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 13:58:58.432150 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 13:58:58.435471 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 13:58:58.438812 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 13:58:58.445234 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 13:58:58.448318 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 13:58:58.451797 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3985 13:58:58.458253 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3986 13:58:58.461684 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 13:58:58.465032 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 13:58:58.471674 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 13:58:58.475360 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 13:58:58.478108 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 13:58:58.484789 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 13:58:58.488322 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 13:58:58.491338 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 13:58:58.497964 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 13:58:58.501168 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 13:58:58.504579 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 13:58:58.511055 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 13:58:58.514697 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 13:58:58.517909 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 13:58:58.524472 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 13:58:58.527684 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 13:58:58.530869 Total UI for P1: 0, mck2ui 16
4003 13:58:58.534598 best dqsien dly found for B0: ( 0, 13, 14)
4004 13:58:58.537457 Total UI for P1: 0, mck2ui 16
4005 13:58:58.540982 best dqsien dly found for B1: ( 0, 13, 14)
4006 13:58:58.544253 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4007 13:58:58.547609 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4008 13:58:58.547689
4009 13:58:58.550662 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4010 13:58:58.557750 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4011 13:58:58.557831 [Gating] SW calibration Done
4012 13:58:58.557898 ==
4013 13:58:58.560675 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 13:58:58.567184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 13:58:58.567265 ==
4016 13:58:58.567330 RX Vref Scan: 0
4017 13:58:58.567389
4018 13:58:58.570562 RX Vref 0 -> 0, step: 1
4019 13:58:58.570641
4020 13:58:58.573770 RX Delay -230 -> 252, step: 16
4021 13:58:58.577136 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4022 13:58:58.580489 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4023 13:58:58.586898 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4024 13:58:58.590208 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4025 13:58:58.594059 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4026 13:58:58.596905 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4027 13:58:58.600112 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4028 13:58:58.606831 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4029 13:58:58.610339 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4030 13:58:58.613336 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4031 13:58:58.616836 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4032 13:58:58.623058 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4033 13:58:58.626237 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4034 13:58:58.629843 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4035 13:58:58.633093 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4036 13:58:58.639400 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4037 13:58:58.639481 ==
4038 13:58:58.643005 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 13:58:58.645985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 13:58:58.646066 ==
4041 13:58:58.646130 DQS Delay:
4042 13:58:58.649301 DQS0 = 0, DQS1 = 0
4043 13:58:58.649381 DQM Delay:
4044 13:58:58.652809 DQM0 = 40, DQM1 = 33
4045 13:58:58.652915 DQ Delay:
4046 13:58:58.656380 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4047 13:58:58.659018 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4048 13:58:58.662475 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4049 13:58:58.665609 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =33
4050 13:58:58.665689
4051 13:58:58.665753
4052 13:58:58.665813 ==
4053 13:58:58.669048 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 13:58:58.675423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 13:58:58.675504 ==
4056 13:58:58.675568
4057 13:58:58.675627
4058 13:58:58.675685 TX Vref Scan disable
4059 13:58:58.679349 == TX Byte 0 ==
4060 13:58:58.682476 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4061 13:58:58.689175 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4062 13:58:58.689258 == TX Byte 1 ==
4063 13:58:58.692290 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4064 13:58:58.698992 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4065 13:58:58.699101 ==
4066 13:58:58.702452 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 13:58:58.705550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 13:58:58.705632 ==
4069 13:58:58.705696
4070 13:58:58.705755
4071 13:58:58.708767 TX Vref Scan disable
4072 13:58:58.712113 == TX Byte 0 ==
4073 13:58:58.715559 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4074 13:58:58.719331 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4075 13:58:58.722044 == TX Byte 1 ==
4076 13:58:58.725206 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4077 13:58:58.728926 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4078 13:58:58.729083
4079 13:58:58.729152 [DATLAT]
4080 13:58:58.731921 Freq=600, CH0 RK0
4081 13:58:58.732002
4082 13:58:58.735281 DATLAT Default: 0x9
4083 13:58:58.735361 0, 0xFFFF, sum = 0
4084 13:58:58.738917 1, 0xFFFF, sum = 0
4085 13:58:58.739012 2, 0xFFFF, sum = 0
4086 13:58:58.742052 3, 0xFFFF, sum = 0
4087 13:58:58.742134 4, 0xFFFF, sum = 0
4088 13:58:58.745041 5, 0xFFFF, sum = 0
4089 13:58:58.745124 6, 0xFFFF, sum = 0
4090 13:58:58.748666 7, 0xFFFF, sum = 0
4091 13:58:58.748748 8, 0x0, sum = 1
4092 13:58:58.751682 9, 0x0, sum = 2
4093 13:58:58.751765 10, 0x0, sum = 3
4094 13:58:58.755119 11, 0x0, sum = 4
4095 13:58:58.755201 best_step = 9
4096 13:58:58.755265
4097 13:58:58.755324 ==
4098 13:58:58.758163 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 13:58:58.761641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 13:58:58.761722 ==
4101 13:58:58.765040 RX Vref Scan: 1
4102 13:58:58.765119
4103 13:58:58.768258 RX Vref 0 -> 0, step: 1
4104 13:58:58.768339
4105 13:58:58.768403 RX Delay -195 -> 252, step: 8
4106 13:58:58.771737
4107 13:58:58.771818 Set Vref, RX VrefLevel [Byte0]: 53
4108 13:58:58.775049 [Byte1]: 51
4109 13:58:58.779468
4110 13:58:58.779551 Final RX Vref Byte 0 = 53 to rank0
4111 13:58:58.782980 Final RX Vref Byte 1 = 51 to rank0
4112 13:58:58.786002 Final RX Vref Byte 0 = 53 to rank1
4113 13:58:58.789326 Final RX Vref Byte 1 = 51 to rank1==
4114 13:58:58.792558 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 13:58:58.799573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 13:58:58.799655 ==
4117 13:58:58.799719 DQS Delay:
4118 13:58:58.802489 DQS0 = 0, DQS1 = 0
4119 13:58:58.802569 DQM Delay:
4120 13:58:58.802632 DQM0 = 41, DQM1 = 34
4121 13:58:58.806062 DQ Delay:
4122 13:58:58.808934 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4123 13:58:58.812279 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4124 13:58:58.815539 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4125 13:58:58.818874 DQ12 =40, DQ13 =44, DQ14 =44, DQ15 =40
4126 13:58:58.818955
4127 13:58:58.819019
4128 13:58:58.825522 [DQSOSCAuto] RK0, (LSB)MR18= 0x534a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
4129 13:58:58.828904 CH0 RK0: MR19=808, MR18=534A
4130 13:58:58.835559 CH0_RK0: MR19=0x808, MR18=0x534A, DQSOSC=394, MR23=63, INC=168, DEC=112
4131 13:58:58.835641
4132 13:58:58.839029 ----->DramcWriteLeveling(PI) begin...
4133 13:58:58.839152 ==
4134 13:58:58.842224 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 13:58:58.845404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 13:58:58.845485 ==
4137 13:58:58.848650 Write leveling (Byte 0): 35 => 35
4138 13:58:58.851925 Write leveling (Byte 1): 28 => 28
4139 13:58:58.855485 DramcWriteLeveling(PI) end<-----
4140 13:58:58.855566
4141 13:58:58.855631 ==
4142 13:58:58.858602 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 13:58:58.862258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 13:58:58.865073 ==
4145 13:58:58.865154 [Gating] SW mode calibration
4146 13:58:58.875259 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4147 13:58:58.878299 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4148 13:58:58.881796 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4149 13:58:58.888367 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4150 13:58:58.891474 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4151 13:58:58.894992 0 9 12 | B1->B0 | 3434 3232 | 0 1 | (0 1) (1 0)
4152 13:58:58.901778 0 9 16 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
4153 13:58:58.904611 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 13:58:58.908223 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 13:58:58.914604 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 13:58:58.917992 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 13:58:58.921402 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 13:58:58.927609 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4159 13:58:58.930943 0 10 12 | B1->B0 | 2929 3535 | 0 1 | (0 0) (1 1)
4160 13:58:58.934481 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4161 13:58:58.940979 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 13:58:58.944637 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 13:58:58.948104 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 13:58:58.954219 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 13:58:58.957334 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 13:58:58.961056 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4167 13:58:58.967335 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4168 13:58:58.970665 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 13:58:58.973608 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 13:58:58.981318 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 13:58:58.983872 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 13:58:58.986953 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 13:58:58.993398 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 13:58:58.997161 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 13:58:59.000146 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 13:58:59.006547 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 13:58:59.010170 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 13:58:59.013482 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 13:58:59.020039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 13:58:59.023010 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 13:58:59.026641 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 13:58:59.032907 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 13:58:59.036859 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4184 13:58:59.039912 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 13:58:59.042837 Total UI for P1: 0, mck2ui 16
4186 13:58:59.046433 best dqsien dly found for B0: ( 0, 13, 12)
4187 13:58:59.049696 Total UI for P1: 0, mck2ui 16
4188 13:58:59.052793 best dqsien dly found for B1: ( 0, 13, 12)
4189 13:58:59.056535 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4190 13:58:59.062794 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4191 13:58:59.062870
4192 13:58:59.066027 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4193 13:58:59.069423 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4194 13:58:59.072956 [Gating] SW calibration Done
4195 13:58:59.073030 ==
4196 13:58:59.076314 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 13:58:59.079434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 13:58:59.079516 ==
4199 13:58:59.082897 RX Vref Scan: 0
4200 13:58:59.082994
4201 13:58:59.083059 RX Vref 0 -> 0, step: 1
4202 13:58:59.083161
4203 13:58:59.086079 RX Delay -230 -> 252, step: 16
4204 13:58:59.089363 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4205 13:58:59.095663 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4206 13:58:59.098977 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4207 13:58:59.102741 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4208 13:58:59.105634 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4209 13:58:59.112539 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4210 13:58:59.115829 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4211 13:58:59.118952 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4212 13:58:59.122353 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4213 13:58:59.125670 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4214 13:58:59.132323 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4215 13:58:59.135441 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4216 13:58:59.138880 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4217 13:58:59.141867 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4218 13:58:59.148827 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4219 13:58:59.152300 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4220 13:58:59.152380 ==
4221 13:58:59.155079 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 13:58:59.158490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 13:58:59.158571 ==
4224 13:58:59.161935 DQS Delay:
4225 13:58:59.162015 DQS0 = 0, DQS1 = 0
4226 13:58:59.165353 DQM Delay:
4227 13:58:59.165432 DQM0 = 41, DQM1 = 32
4228 13:58:59.165496 DQ Delay:
4229 13:58:59.168511 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4230 13:58:59.171827 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4231 13:58:59.174992 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4232 13:58:59.178701 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4233 13:58:59.178780
4234 13:58:59.178844
4235 13:58:59.181680 ==
4236 13:58:59.185250 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 13:58:59.188384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 13:58:59.188457 ==
4239 13:58:59.188520
4240 13:58:59.188578
4241 13:58:59.191582 TX Vref Scan disable
4242 13:58:59.191662 == TX Byte 0 ==
4243 13:58:59.197827 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4244 13:58:59.201240 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4245 13:58:59.201321 == TX Byte 1 ==
4246 13:58:59.207758 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4247 13:58:59.211504 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4248 13:58:59.211599 ==
4249 13:58:59.214522 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 13:58:59.217770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 13:58:59.217851 ==
4252 13:58:59.217916
4253 13:58:59.217976
4254 13:58:59.221082 TX Vref Scan disable
4255 13:58:59.224362 == TX Byte 0 ==
4256 13:58:59.228341 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4257 13:58:59.234397 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4258 13:58:59.234477 == TX Byte 1 ==
4259 13:58:59.237849 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4260 13:58:59.244792 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4261 13:58:59.244874
4262 13:58:59.244938 [DATLAT]
4263 13:58:59.244998 Freq=600, CH0 RK1
4264 13:58:59.245057
4265 13:58:59.247775 DATLAT Default: 0x9
4266 13:58:59.247855 0, 0xFFFF, sum = 0
4267 13:58:59.251357 1, 0xFFFF, sum = 0
4268 13:58:59.254334 2, 0xFFFF, sum = 0
4269 13:58:59.254416 3, 0xFFFF, sum = 0
4270 13:58:59.257736 4, 0xFFFF, sum = 0
4271 13:58:59.257820 5, 0xFFFF, sum = 0
4272 13:58:59.260986 6, 0xFFFF, sum = 0
4273 13:58:59.261069 7, 0xFFFF, sum = 0
4274 13:58:59.264242 8, 0x0, sum = 1
4275 13:58:59.264324 9, 0x0, sum = 2
4276 13:58:59.264389 10, 0x0, sum = 3
4277 13:58:59.267314 11, 0x0, sum = 4
4278 13:58:59.267395 best_step = 9
4279 13:58:59.267459
4280 13:58:59.271422 ==
4281 13:58:59.271503 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 13:58:59.277273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 13:58:59.277355 ==
4284 13:58:59.277420 RX Vref Scan: 0
4285 13:58:59.277479
4286 13:58:59.280933 RX Vref 0 -> 0, step: 1
4287 13:58:59.281014
4288 13:58:59.284063 RX Delay -195 -> 252, step: 8
4289 13:58:59.290380 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4290 13:58:59.294029 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4291 13:58:59.297888 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4292 13:58:59.300531 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4293 13:58:59.304099 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4294 13:58:59.310875 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4295 13:58:59.313680 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4296 13:58:59.317013 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4297 13:58:59.320387 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4298 13:58:59.327131 iDelay=197, Bit 9, Center 20 (-139 ~ 180) 320
4299 13:58:59.330589 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4300 13:58:59.333918 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4301 13:58:59.336917 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4302 13:58:59.343595 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4303 13:58:59.347036 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4304 13:58:59.350184 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4305 13:58:59.350266 ==
4306 13:58:59.353503 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 13:58:59.356807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 13:58:59.356888 ==
4309 13:58:59.359962 DQS Delay:
4310 13:58:59.360042 DQS0 = 0, DQS1 = 0
4311 13:58:59.363501 DQM Delay:
4312 13:58:59.363581 DQM0 = 40, DQM1 = 34
4313 13:58:59.363645 DQ Delay:
4314 13:58:59.366819 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4315 13:58:59.369936 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4316 13:58:59.373357 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4317 13:58:59.376418 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4318 13:58:59.376497
4319 13:58:59.376565
4320 13:58:59.386608 [DQSOSCAuto] RK1, (LSB)MR18= 0x413d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4321 13:58:59.389519 CH0 RK1: MR19=808, MR18=413D
4322 13:58:59.396071 CH0_RK1: MR19=0x808, MR18=0x413D, DQSOSC=397, MR23=63, INC=166, DEC=110
4323 13:58:59.399752 [RxdqsGatingPostProcess] freq 600
4324 13:58:59.402970 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4325 13:58:59.406208 Pre-setting of DQS Precalculation
4326 13:58:59.412640 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4327 13:58:59.412721 ==
4328 13:58:59.415754 Dram Type= 6, Freq= 0, CH_1, rank 0
4329 13:58:59.419339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 13:58:59.419419 ==
4331 13:58:59.426017 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4332 13:58:59.429322 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4333 13:58:59.433662 [CA 0] Center 36 (6~66) winsize 61
4334 13:58:59.436819 [CA 1] Center 35 (5~66) winsize 62
4335 13:58:59.439934 [CA 2] Center 34 (4~65) winsize 62
4336 13:58:59.443994 [CA 3] Center 34 (4~65) winsize 62
4337 13:58:59.446981 [CA 4] Center 34 (4~65) winsize 62
4338 13:58:59.450291 [CA 5] Center 34 (3~65) winsize 63
4339 13:58:59.450372
4340 13:58:59.453548 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4341 13:58:59.453651
4342 13:58:59.456624 [CATrainingPosCal] consider 1 rank data
4343 13:58:59.459907 u2DelayCellTimex100 = 270/100 ps
4344 13:58:59.463070 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4345 13:58:59.470078 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4346 13:58:59.473418 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4347 13:58:59.476487 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4348 13:58:59.479749 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4349 13:58:59.483445 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4350 13:58:59.483526
4351 13:58:59.486172 CA PerBit enable=1, Macro0, CA PI delay=34
4352 13:58:59.486253
4353 13:58:59.489828 [CBTSetCACLKResult] CA Dly = 34
4354 13:58:59.492861 CS Dly: 5 (0~36)
4355 13:58:59.492942 ==
4356 13:58:59.496450 Dram Type= 6, Freq= 0, CH_1, rank 1
4357 13:58:59.500140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 13:58:59.500221 ==
4359 13:58:59.506436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4360 13:58:59.510016 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4361 13:58:59.513660 [CA 0] Center 36 (6~66) winsize 61
4362 13:58:59.517202 [CA 1] Center 36 (6~66) winsize 61
4363 13:58:59.519821 [CA 2] Center 34 (4~65) winsize 62
4364 13:58:59.523363 [CA 3] Center 34 (3~65) winsize 63
4365 13:58:59.526426 [CA 4] Center 34 (3~65) winsize 63
4366 13:58:59.529819 [CA 5] Center 33 (3~64) winsize 62
4367 13:58:59.529899
4368 13:58:59.533703 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4369 13:58:59.533785
4370 13:58:59.536353 [CATrainingPosCal] consider 2 rank data
4371 13:58:59.539639 u2DelayCellTimex100 = 270/100 ps
4372 13:58:59.543410 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4373 13:58:59.550078 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4374 13:58:59.552966 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 13:58:59.556511 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4376 13:58:59.559966 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 13:58:59.563168 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4378 13:58:59.563248
4379 13:58:59.566145 CA PerBit enable=1, Macro0, CA PI delay=33
4380 13:58:59.566225
4381 13:58:59.569677 [CBTSetCACLKResult] CA Dly = 33
4382 13:58:59.572872 CS Dly: 5 (0~37)
4383 13:58:59.572952
4384 13:58:59.576076 ----->DramcWriteLeveling(PI) begin...
4385 13:58:59.576173 ==
4386 13:58:59.579144 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 13:58:59.582810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 13:58:59.582890 ==
4389 13:58:59.585962 Write leveling (Byte 0): 31 => 31
4390 13:58:59.589852 Write leveling (Byte 1): 30 => 30
4391 13:58:59.592308 DramcWriteLeveling(PI) end<-----
4392 13:58:59.592419
4393 13:58:59.592525 ==
4394 13:58:59.595733 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 13:58:59.598913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 13:58:59.599020 ==
4397 13:58:59.602378 [Gating] SW mode calibration
4398 13:58:59.608949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4399 13:58:59.615573 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4400 13:58:59.619057 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4401 13:58:59.622474 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 13:58:59.628893 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4403 13:58:59.632012 0 9 12 | B1->B0 | 2f2f 2f2f | 0 1 | (0 0) (1 0)
4404 13:58:59.635027 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 13:58:59.642571 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 13:58:59.645029 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 13:58:59.651732 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 13:58:59.654948 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 13:58:59.658204 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 13:58:59.664793 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4411 13:58:59.668253 0 10 12 | B1->B0 | 2e2e 3838 | 0 0 | (0 0) (1 1)
4412 13:58:59.671658 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 13:58:59.678203 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 13:58:59.681079 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 13:58:59.684637 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 13:58:59.691459 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 13:58:59.694294 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 13:58:59.698201 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 13:58:59.704349 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4420 13:58:59.708069 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 13:58:59.711558 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 13:58:59.717350 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 13:58:59.721058 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 13:58:59.724417 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 13:58:59.727410 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 13:58:59.734109 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 13:58:59.737473 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 13:58:59.744328 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 13:58:59.747337 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 13:58:59.750409 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 13:58:59.757118 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 13:58:59.760242 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 13:58:59.763873 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 13:58:59.770382 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 13:58:59.773453 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4436 13:58:59.776540 Total UI for P1: 0, mck2ui 16
4437 13:58:59.779731 best dqsien dly found for B0: ( 0, 13, 10)
4438 13:58:59.783498 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4439 13:58:59.789668 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 13:58:59.789749 Total UI for P1: 0, mck2ui 16
4441 13:58:59.793296 best dqsien dly found for B1: ( 0, 13, 14)
4442 13:58:59.800375 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4443 13:58:59.803385 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4444 13:58:59.803465
4445 13:58:59.806203 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4446 13:58:59.809654 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4447 13:58:59.812804 [Gating] SW calibration Done
4448 13:58:59.812884 ==
4449 13:58:59.816313 Dram Type= 6, Freq= 0, CH_1, rank 0
4450 13:58:59.819421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 13:58:59.819502 ==
4452 13:58:59.822747 RX Vref Scan: 0
4453 13:58:59.822827
4454 13:58:59.822889 RX Vref 0 -> 0, step: 1
4455 13:58:59.822948
4456 13:58:59.825949 RX Delay -230 -> 252, step: 16
4457 13:58:59.832940 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4458 13:58:59.835915 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4459 13:58:59.839339 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4460 13:58:59.842603 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4461 13:58:59.845591 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4462 13:58:59.852185 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4463 13:58:59.855827 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4464 13:58:59.859582 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4465 13:58:59.862613 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4466 13:58:59.869008 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4467 13:58:59.872013 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4468 13:58:59.875554 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4469 13:58:59.879112 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4470 13:58:59.885671 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4471 13:58:59.888811 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4472 13:58:59.892225 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4473 13:58:59.892325 ==
4474 13:58:59.896253 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 13:58:59.898721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 13:58:59.902067 ==
4477 13:58:59.902166 DQS Delay:
4478 13:58:59.902231 DQS0 = 0, DQS1 = 0
4479 13:58:59.905275 DQM Delay:
4480 13:58:59.905346 DQM0 = 42, DQM1 = 39
4481 13:58:59.908592 DQ Delay:
4482 13:58:59.911963 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4483 13:58:59.914893 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4484 13:58:59.918445 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4485 13:58:59.921773 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4486 13:58:59.921874
4487 13:58:59.921964
4488 13:58:59.922052 ==
4489 13:58:59.924961 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 13:58:59.927860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 13:58:59.927929 ==
4492 13:58:59.927995
4493 13:58:59.928058
4494 13:58:59.931766 TX Vref Scan disable
4495 13:58:59.931835 == TX Byte 0 ==
4496 13:58:59.937741 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4497 13:58:59.941324 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4498 13:58:59.941418 == TX Byte 1 ==
4499 13:58:59.948091 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4500 13:58:59.951225 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4501 13:58:59.951328 ==
4502 13:58:59.954319 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 13:58:59.957594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 13:58:59.960994 ==
4505 13:58:59.961092
4506 13:58:59.961188
4507 13:58:59.961276 TX Vref Scan disable
4508 13:58:59.965012 == TX Byte 0 ==
4509 13:58:59.968659 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4510 13:58:59.974639 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4511 13:58:59.974740 == TX Byte 1 ==
4512 13:58:59.977972 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4513 13:58:59.984563 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4514 13:58:59.984643
4515 13:58:59.984714 [DATLAT]
4516 13:58:59.984775 Freq=600, CH1 RK0
4517 13:58:59.984836
4518 13:58:59.987984 DATLAT Default: 0x9
4519 13:58:59.988057 0, 0xFFFF, sum = 0
4520 13:58:59.991370 1, 0xFFFF, sum = 0
4521 13:58:59.994311 2, 0xFFFF, sum = 0
4522 13:58:59.994415 3, 0xFFFF, sum = 0
4523 13:58:59.997624 4, 0xFFFF, sum = 0
4524 13:58:59.997732 5, 0xFFFF, sum = 0
4525 13:59:00.001215 6, 0xFFFF, sum = 0
4526 13:59:00.001318 7, 0xFFFF, sum = 0
4527 13:59:00.004458 8, 0x0, sum = 1
4528 13:59:00.004555 9, 0x0, sum = 2
4529 13:59:00.007627 10, 0x0, sum = 3
4530 13:59:00.007723 11, 0x0, sum = 4
4531 13:59:00.007820 best_step = 9
4532 13:59:00.007906
4533 13:59:00.011415 ==
4534 13:59:00.013859 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 13:59:00.017985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 13:59:00.018086 ==
4537 13:59:00.018180 RX Vref Scan: 1
4538 13:59:00.018272
4539 13:59:00.020925 RX Vref 0 -> 0, step: 1
4540 13:59:00.021018
4541 13:59:00.023973 RX Delay -179 -> 252, step: 8
4542 13:59:00.024044
4543 13:59:00.027586 Set Vref, RX VrefLevel [Byte0]: 51
4544 13:59:00.030379 [Byte1]: 53
4545 13:59:00.030477
4546 13:59:00.034222 Final RX Vref Byte 0 = 51 to rank0
4547 13:59:00.037736 Final RX Vref Byte 1 = 53 to rank0
4548 13:59:00.040595 Final RX Vref Byte 0 = 51 to rank1
4549 13:59:00.043736 Final RX Vref Byte 1 = 53 to rank1==
4550 13:59:00.047059 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 13:59:00.050703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 13:59:00.053447 ==
4553 13:59:00.053549 DQS Delay:
4554 13:59:00.053640 DQS0 = 0, DQS1 = 0
4555 13:59:00.057536 DQM Delay:
4556 13:59:00.057637 DQM0 = 41, DQM1 = 34
4557 13:59:00.060406 DQ Delay:
4558 13:59:00.063795 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4559 13:59:00.063903 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4560 13:59:00.066995 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4561 13:59:00.073935 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4562 13:59:00.074040
4563 13:59:00.074137
4564 13:59:00.079947 [DQSOSCAuto] RK0, (LSB)MR18= 0x3650, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
4565 13:59:00.083552 CH1 RK0: MR19=808, MR18=3650
4566 13:59:00.089824 CH1_RK0: MR19=0x808, MR18=0x3650, DQSOSC=394, MR23=63, INC=168, DEC=112
4567 13:59:00.089928
4568 13:59:00.093255 ----->DramcWriteLeveling(PI) begin...
4569 13:59:00.093363 ==
4570 13:59:00.096618 Dram Type= 6, Freq= 0, CH_1, rank 1
4571 13:59:00.099794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 13:59:00.099875 ==
4573 13:59:00.102953 Write leveling (Byte 0): 28 => 28
4574 13:59:00.106665 Write leveling (Byte 1): 32 => 32
4575 13:59:00.109729 DramcWriteLeveling(PI) end<-----
4576 13:59:00.109830
4577 13:59:00.109934 ==
4578 13:59:00.112667 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 13:59:00.116841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 13:59:00.119458 ==
4581 13:59:00.119538 [Gating] SW mode calibration
4582 13:59:00.125932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4583 13:59:00.132797 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4584 13:59:00.135765 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4585 13:59:00.142518 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4586 13:59:00.146302 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4587 13:59:00.149415 0 9 12 | B1->B0 | 2f2f 2727 | 1 0 | (0 0) (0 1)
4588 13:59:00.155559 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 13:59:00.158918 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 13:59:00.162250 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 13:59:00.168718 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 13:59:00.172088 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 13:59:00.175189 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 13:59:00.181941 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4595 13:59:00.185079 0 10 12 | B1->B0 | 2424 3838 | 0 1 | (0 0) (0 0)
4596 13:59:00.188552 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4597 13:59:00.194982 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 13:59:00.198274 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 13:59:00.201665 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 13:59:00.208220 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 13:59:00.211790 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 13:59:00.214951 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4603 13:59:00.221739 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 13:59:00.224970 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 13:59:00.228204 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 13:59:00.234787 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 13:59:00.238155 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 13:59:00.241171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 13:59:00.248020 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 13:59:00.251326 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 13:59:00.254921 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 13:59:00.261126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 13:59:00.264672 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 13:59:00.267545 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 13:59:00.275037 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 13:59:00.277482 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 13:59:00.280980 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 13:59:00.287497 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 13:59:00.290868 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4620 13:59:00.294218 Total UI for P1: 0, mck2ui 16
4621 13:59:00.297129 best dqsien dly found for B0: ( 0, 13, 10)
4622 13:59:00.301388 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 13:59:00.304317 Total UI for P1: 0, mck2ui 16
4624 13:59:00.306976 best dqsien dly found for B1: ( 0, 13, 12)
4625 13:59:00.310539 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4626 13:59:00.313698 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4627 13:59:00.317197
4628 13:59:00.320985 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4629 13:59:00.323987 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4630 13:59:00.327287 [Gating] SW calibration Done
4631 13:59:00.327369 ==
4632 13:59:00.330533 Dram Type= 6, Freq= 0, CH_1, rank 1
4633 13:59:00.333567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 13:59:00.333649 ==
4635 13:59:00.333747 RX Vref Scan: 0
4636 13:59:00.336788
4637 13:59:00.336869 RX Vref 0 -> 0, step: 1
4638 13:59:00.336934
4639 13:59:00.340468 RX Delay -230 -> 252, step: 16
4640 13:59:00.343496 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4641 13:59:00.350060 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4642 13:59:00.353336 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4643 13:59:00.357006 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4644 13:59:00.360007 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4645 13:59:00.363803 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4646 13:59:00.370258 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4647 13:59:00.373654 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4648 13:59:00.377059 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4649 13:59:00.380250 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4650 13:59:00.386763 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4651 13:59:00.389756 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4652 13:59:00.393430 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4653 13:59:00.396668 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4654 13:59:00.403002 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4655 13:59:00.406714 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4656 13:59:00.406795 ==
4657 13:59:00.409522 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 13:59:00.412955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 13:59:00.413038 ==
4660 13:59:00.416560 DQS Delay:
4661 13:59:00.416646 DQS0 = 0, DQS1 = 0
4662 13:59:00.416711 DQM Delay:
4663 13:59:00.419730 DQM0 = 44, DQM1 = 42
4664 13:59:00.419810 DQ Delay:
4665 13:59:00.422997 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4666 13:59:00.426265 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4667 13:59:00.429929 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4668 13:59:00.432870 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4669 13:59:00.432951
4670 13:59:00.433015
4671 13:59:00.433076 ==
4672 13:59:00.436137 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 13:59:00.442510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 13:59:00.442592 ==
4675 13:59:00.442656
4676 13:59:00.442716
4677 13:59:00.442773 TX Vref Scan disable
4678 13:59:00.446711 == TX Byte 0 ==
4679 13:59:00.450204 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4680 13:59:00.453829 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4681 13:59:00.456770 == TX Byte 1 ==
4682 13:59:00.460350 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4683 13:59:00.466794 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4684 13:59:00.466879 ==
4685 13:59:00.469800 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 13:59:00.473538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 13:59:00.473619 ==
4688 13:59:00.473684
4689 13:59:00.473744
4690 13:59:00.476146 TX Vref Scan disable
4691 13:59:00.479882 == TX Byte 0 ==
4692 13:59:00.483343 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4693 13:59:00.486354 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4694 13:59:00.489802 == TX Byte 1 ==
4695 13:59:00.493026 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4696 13:59:00.496223 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4697 13:59:00.496304
4698 13:59:00.496369 [DATLAT]
4699 13:59:00.499398 Freq=600, CH1 RK1
4700 13:59:00.499488
4701 13:59:00.503001 DATLAT Default: 0x9
4702 13:59:00.503108 0, 0xFFFF, sum = 0
4703 13:59:00.506127 1, 0xFFFF, sum = 0
4704 13:59:00.506210 2, 0xFFFF, sum = 0
4705 13:59:00.509347 3, 0xFFFF, sum = 0
4706 13:59:00.509430 4, 0xFFFF, sum = 0
4707 13:59:00.513130 5, 0xFFFF, sum = 0
4708 13:59:00.513213 6, 0xFFFF, sum = 0
4709 13:59:00.515959 7, 0xFFFF, sum = 0
4710 13:59:00.516042 8, 0x0, sum = 1
4711 13:59:00.519380 9, 0x0, sum = 2
4712 13:59:00.519463 10, 0x0, sum = 3
4713 13:59:00.522745 11, 0x0, sum = 4
4714 13:59:00.522828 best_step = 9
4715 13:59:00.522892
4716 13:59:00.522953 ==
4717 13:59:00.525763 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 13:59:00.529090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 13:59:00.529172 ==
4720 13:59:00.532529 RX Vref Scan: 0
4721 13:59:00.532611
4722 13:59:00.536164 RX Vref 0 -> 0, step: 1
4723 13:59:00.536246
4724 13:59:00.536311 RX Delay -179 -> 252, step: 8
4725 13:59:00.543701 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4726 13:59:00.547249 iDelay=205, Bit 1, Center 32 (-131 ~ 196) 328
4727 13:59:00.550391 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4728 13:59:00.553589 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4729 13:59:00.560223 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4730 13:59:00.563322 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4731 13:59:00.567024 iDelay=205, Bit 6, Center 40 (-115 ~ 196) 312
4732 13:59:00.570002 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4733 13:59:00.576352 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4734 13:59:00.579971 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4735 13:59:00.583013 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4736 13:59:00.586589 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4737 13:59:00.593355 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4738 13:59:00.596476 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4739 13:59:00.599592 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4740 13:59:00.602886 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4741 13:59:00.603000 ==
4742 13:59:00.606502 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 13:59:00.613318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 13:59:00.613399 ==
4745 13:59:00.613464 DQS Delay:
4746 13:59:00.616439 DQS0 = 0, DQS1 = 0
4747 13:59:00.616520 DQM Delay:
4748 13:59:00.616585 DQM0 = 36, DQM1 = 35
4749 13:59:00.619682 DQ Delay:
4750 13:59:00.622721 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4751 13:59:00.625851 DQ4 =36, DQ5 =44, DQ6 =40, DQ7 =32
4752 13:59:00.629402 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =28
4753 13:59:00.632906 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4754 13:59:00.632986
4755 13:59:00.633050
4756 13:59:00.639823 [DQSOSCAuto] RK1, (LSB)MR18= 0x365a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4757 13:59:00.642339 CH1 RK1: MR19=808, MR18=365A
4758 13:59:00.649158 CH1_RK1: MR19=0x808, MR18=0x365A, DQSOSC=392, MR23=63, INC=170, DEC=113
4759 13:59:00.653144 [RxdqsGatingPostProcess] freq 600
4760 13:59:00.659005 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4761 13:59:00.659147 Pre-setting of DQS Precalculation
4762 13:59:00.665749 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4763 13:59:00.672411 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4764 13:59:00.678996 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4765 13:59:00.679084
4766 13:59:00.679151
4767 13:59:00.682340 [Calibration Summary] 1200 Mbps
4768 13:59:00.686016 CH 0, Rank 0
4769 13:59:00.686101 SW Impedance : PASS
4770 13:59:00.688921 DUTY Scan : NO K
4771 13:59:00.689003 ZQ Calibration : PASS
4772 13:59:00.691832 Jitter Meter : NO K
4773 13:59:00.695242 CBT Training : PASS
4774 13:59:00.695323 Write leveling : PASS
4775 13:59:00.698806 RX DQS gating : PASS
4776 13:59:00.702154 RX DQ/DQS(RDDQC) : PASS
4777 13:59:00.702236 TX DQ/DQS : PASS
4778 13:59:00.705844 RX DATLAT : PASS
4779 13:59:00.708439 RX DQ/DQS(Engine): PASS
4780 13:59:00.708520 TX OE : NO K
4781 13:59:00.712150 All Pass.
4782 13:59:00.712230
4783 13:59:00.712295 CH 0, Rank 1
4784 13:59:00.715060 SW Impedance : PASS
4785 13:59:00.715182 DUTY Scan : NO K
4786 13:59:00.718889 ZQ Calibration : PASS
4787 13:59:00.721799 Jitter Meter : NO K
4788 13:59:00.721880 CBT Training : PASS
4789 13:59:00.724952 Write leveling : PASS
4790 13:59:00.728230 RX DQS gating : PASS
4791 13:59:00.728312 RX DQ/DQS(RDDQC) : PASS
4792 13:59:00.731856 TX DQ/DQS : PASS
4793 13:59:00.734980 RX DATLAT : PASS
4794 13:59:00.735061 RX DQ/DQS(Engine): PASS
4795 13:59:00.738515 TX OE : NO K
4796 13:59:00.738597 All Pass.
4797 13:59:00.738662
4798 13:59:00.741576 CH 1, Rank 0
4799 13:59:00.741661 SW Impedance : PASS
4800 13:59:00.745417 DUTY Scan : NO K
4801 13:59:00.748233 ZQ Calibration : PASS
4802 13:59:00.748315 Jitter Meter : NO K
4803 13:59:00.751336 CBT Training : PASS
4804 13:59:00.754976 Write leveling : PASS
4805 13:59:00.755058 RX DQS gating : PASS
4806 13:59:00.757726 RX DQ/DQS(RDDQC) : PASS
4807 13:59:00.757807 TX DQ/DQS : PASS
4808 13:59:00.761503 RX DATLAT : PASS
4809 13:59:00.764710 RX DQ/DQS(Engine): PASS
4810 13:59:00.764792 TX OE : NO K
4811 13:59:00.767892 All Pass.
4812 13:59:00.767974
4813 13:59:00.768039 CH 1, Rank 1
4814 13:59:00.771124 SW Impedance : PASS
4815 13:59:00.771219 DUTY Scan : NO K
4816 13:59:00.774739 ZQ Calibration : PASS
4817 13:59:00.777641 Jitter Meter : NO K
4818 13:59:00.777723 CBT Training : PASS
4819 13:59:00.781130 Write leveling : PASS
4820 13:59:00.784673 RX DQS gating : PASS
4821 13:59:00.784755 RX DQ/DQS(RDDQC) : PASS
4822 13:59:00.787574 TX DQ/DQS : PASS
4823 13:59:00.790885 RX DATLAT : PASS
4824 13:59:00.790966 RX DQ/DQS(Engine): PASS
4825 13:59:00.794132 TX OE : NO K
4826 13:59:00.794214 All Pass.
4827 13:59:00.794280
4828 13:59:00.798107 DramC Write-DBI off
4829 13:59:00.800746 PER_BANK_REFRESH: Hybrid Mode
4830 13:59:00.800828 TX_TRACKING: ON
4831 13:59:00.810728 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4832 13:59:00.814297 [FAST_K] Save calibration result to emmc
4833 13:59:00.817338 dramc_set_vcore_voltage set vcore to 662500
4834 13:59:00.820510 Read voltage for 933, 3
4835 13:59:00.820591 Vio18 = 0
4836 13:59:00.820657 Vcore = 662500
4837 13:59:00.823675 Vdram = 0
4838 13:59:00.823756 Vddq = 0
4839 13:59:00.823821 Vmddr = 0
4840 13:59:00.830581 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4841 13:59:00.833914 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4842 13:59:00.837539 MEM_TYPE=3, freq_sel=17
4843 13:59:00.840316 sv_algorithm_assistance_LP4_1600
4844 13:59:00.843760 ============ PULL DRAM RESETB DOWN ============
4845 13:59:00.850220 ========== PULL DRAM RESETB DOWN end =========
4846 13:59:00.853713 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4847 13:59:00.856853 ===================================
4848 13:59:00.860446 LPDDR4 DRAM CONFIGURATION
4849 13:59:00.863517 ===================================
4850 13:59:00.863599 EX_ROW_EN[0] = 0x0
4851 13:59:00.867133 EX_ROW_EN[1] = 0x0
4852 13:59:00.867229 LP4Y_EN = 0x0
4853 13:59:00.870142 WORK_FSP = 0x0
4854 13:59:00.870224 WL = 0x3
4855 13:59:00.873818 RL = 0x3
4856 13:59:00.873899 BL = 0x2
4857 13:59:00.876829 RPST = 0x0
4858 13:59:00.876910 RD_PRE = 0x0
4859 13:59:00.879817 WR_PRE = 0x1
4860 13:59:00.883462 WR_PST = 0x0
4861 13:59:00.883545 DBI_WR = 0x0
4862 13:59:00.886271 DBI_RD = 0x0
4863 13:59:00.886353 OTF = 0x1
4864 13:59:00.889981 ===================================
4865 13:59:00.893057 ===================================
4866 13:59:00.896182 ANA top config
4867 13:59:00.899499 ===================================
4868 13:59:00.899581 DLL_ASYNC_EN = 0
4869 13:59:00.903303 ALL_SLAVE_EN = 1
4870 13:59:00.906308 NEW_RANK_MODE = 1
4871 13:59:00.910398 DLL_IDLE_MODE = 1
4872 13:59:00.910480 LP45_APHY_COMB_EN = 1
4873 13:59:00.912673 TX_ODT_DIS = 1
4874 13:59:00.916391 NEW_8X_MODE = 1
4875 13:59:00.919358 ===================================
4876 13:59:00.922959 ===================================
4877 13:59:00.925995 data_rate = 1866
4878 13:59:00.929400 CKR = 1
4879 13:59:00.933016 DQ_P2S_RATIO = 8
4880 13:59:00.935895 ===================================
4881 13:59:00.935978 CA_P2S_RATIO = 8
4882 13:59:00.939109 DQ_CA_OPEN = 0
4883 13:59:00.942775 DQ_SEMI_OPEN = 0
4884 13:59:00.945809 CA_SEMI_OPEN = 0
4885 13:59:00.949297 CA_FULL_RATE = 0
4886 13:59:00.952537 DQ_CKDIV4_EN = 1
4887 13:59:00.952619 CA_CKDIV4_EN = 1
4888 13:59:00.955680 CA_PREDIV_EN = 0
4889 13:59:00.958969 PH8_DLY = 0
4890 13:59:00.962121 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4891 13:59:00.965535 DQ_AAMCK_DIV = 4
4892 13:59:00.968935 CA_AAMCK_DIV = 4
4893 13:59:00.969017 CA_ADMCK_DIV = 4
4894 13:59:00.972270 DQ_TRACK_CA_EN = 0
4895 13:59:00.975362 CA_PICK = 933
4896 13:59:00.978848 CA_MCKIO = 933
4897 13:59:00.982155 MCKIO_SEMI = 0
4898 13:59:00.985374 PLL_FREQ = 3732
4899 13:59:00.988703 DQ_UI_PI_RATIO = 32
4900 13:59:00.992009 CA_UI_PI_RATIO = 0
4901 13:59:00.995111 ===================================
4902 13:59:00.998463 ===================================
4903 13:59:00.998545 memory_type:LPDDR4
4904 13:59:01.001517 GP_NUM : 10
4905 13:59:01.004902 SRAM_EN : 1
4906 13:59:01.004985 MD32_EN : 0
4907 13:59:01.008397 ===================================
4908 13:59:01.011586 [ANA_INIT] >>>>>>>>>>>>>>
4909 13:59:01.014664 <<<<<< [CONFIGURE PHASE]: ANA_TX
4910 13:59:01.018192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4911 13:59:01.021631 ===================================
4912 13:59:01.024536 data_rate = 1866,PCW = 0X8f00
4913 13:59:01.028148 ===================================
4914 13:59:01.031207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4915 13:59:01.034974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4916 13:59:01.041328 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4917 13:59:01.044695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4918 13:59:01.047942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4919 13:59:01.051409 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4920 13:59:01.054946 [ANA_INIT] flow start
4921 13:59:01.057623 [ANA_INIT] PLL >>>>>>>>
4922 13:59:01.057705 [ANA_INIT] PLL <<<<<<<<
4923 13:59:01.061468 [ANA_INIT] MIDPI >>>>>>>>
4924 13:59:01.064296 [ANA_INIT] MIDPI <<<<<<<<
4925 13:59:01.067563 [ANA_INIT] DLL >>>>>>>>
4926 13:59:01.067645 [ANA_INIT] flow end
4927 13:59:01.070855 ============ LP4 DIFF to SE enter ============
4928 13:59:01.077267 ============ LP4 DIFF to SE exit ============
4929 13:59:01.077349 [ANA_INIT] <<<<<<<<<<<<<
4930 13:59:01.080523 [Flow] Enable top DCM control >>>>>
4931 13:59:01.083979 [Flow] Enable top DCM control <<<<<
4932 13:59:01.087238 Enable DLL master slave shuffle
4933 13:59:01.094053 ==============================================================
4934 13:59:01.094137 Gating Mode config
4935 13:59:01.101084 ==============================================================
4936 13:59:01.104131 Config description:
4937 13:59:01.113745 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4938 13:59:01.120716 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4939 13:59:01.123973 SELPH_MODE 0: By rank 1: By Phase
4940 13:59:01.130540 ==============================================================
4941 13:59:01.134110 GAT_TRACK_EN = 1
4942 13:59:01.136892 RX_GATING_MODE = 2
4943 13:59:01.140472 RX_GATING_TRACK_MODE = 2
4944 13:59:01.140553 SELPH_MODE = 1
4945 13:59:01.143411 PICG_EARLY_EN = 1
4946 13:59:01.147008 VALID_LAT_VALUE = 1
4947 13:59:01.153254 ==============================================================
4948 13:59:01.156779 Enter into Gating configuration >>>>
4949 13:59:01.159922 Exit from Gating configuration <<<<
4950 13:59:01.163434 Enter into DVFS_PRE_config >>>>>
4951 13:59:01.173539 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4952 13:59:01.176724 Exit from DVFS_PRE_config <<<<<
4953 13:59:01.179615 Enter into PICG configuration >>>>
4954 13:59:01.182972 Exit from PICG configuration <<<<
4955 13:59:01.186211 [RX_INPUT] configuration >>>>>
4956 13:59:01.189522 [RX_INPUT] configuration <<<<<
4957 13:59:01.192736 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4958 13:59:01.199674 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4959 13:59:01.206275 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4960 13:59:01.212808 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4961 13:59:01.219444 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4962 13:59:01.226358 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4963 13:59:01.229288 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4964 13:59:01.232942 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4965 13:59:01.236005 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4966 13:59:01.239390 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4967 13:59:01.245900 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4968 13:59:01.249260 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4969 13:59:01.252684 ===================================
4970 13:59:01.255540 LPDDR4 DRAM CONFIGURATION
4971 13:59:01.258967 ===================================
4972 13:59:01.259047 EX_ROW_EN[0] = 0x0
4973 13:59:01.262632 EX_ROW_EN[1] = 0x0
4974 13:59:01.262713 LP4Y_EN = 0x0
4975 13:59:01.265643 WORK_FSP = 0x0
4976 13:59:01.268889 WL = 0x3
4977 13:59:01.268970 RL = 0x3
4978 13:59:01.272528 BL = 0x2
4979 13:59:01.272610 RPST = 0x0
4980 13:59:01.275520 RD_PRE = 0x0
4981 13:59:01.275601 WR_PRE = 0x1
4982 13:59:01.278717 WR_PST = 0x0
4983 13:59:01.278798 DBI_WR = 0x0
4984 13:59:01.282262 DBI_RD = 0x0
4985 13:59:01.282369 OTF = 0x1
4986 13:59:01.285250 ===================================
4987 13:59:01.288831 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4988 13:59:01.295571 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4989 13:59:01.298814 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4990 13:59:01.301981 ===================================
4991 13:59:01.305343 LPDDR4 DRAM CONFIGURATION
4992 13:59:01.308634 ===================================
4993 13:59:01.308716 EX_ROW_EN[0] = 0x10
4994 13:59:01.311795 EX_ROW_EN[1] = 0x0
4995 13:59:01.311876 LP4Y_EN = 0x0
4996 13:59:01.315232 WORK_FSP = 0x0
4997 13:59:01.315313 WL = 0x3
4998 13:59:01.318582 RL = 0x3
4999 13:59:01.322273 BL = 0x2
5000 13:59:01.322355 RPST = 0x0
5001 13:59:01.324970 RD_PRE = 0x0
5002 13:59:01.325051 WR_PRE = 0x1
5003 13:59:01.328499 WR_PST = 0x0
5004 13:59:01.328580 DBI_WR = 0x0
5005 13:59:01.332133 DBI_RD = 0x0
5006 13:59:01.332214 OTF = 0x1
5007 13:59:01.335108 ===================================
5008 13:59:01.341501 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5009 13:59:01.346123 nWR fixed to 30
5010 13:59:01.349247 [ModeRegInit_LP4] CH0 RK0
5011 13:59:01.349329 [ModeRegInit_LP4] CH0 RK1
5012 13:59:01.352448 [ModeRegInit_LP4] CH1 RK0
5013 13:59:01.356066 [ModeRegInit_LP4] CH1 RK1
5014 13:59:01.356148 match AC timing 9
5015 13:59:01.362089 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5016 13:59:01.365445 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5017 13:59:01.369007 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5018 13:59:01.375266 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5019 13:59:01.378729 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5020 13:59:01.378811 ==
5021 13:59:01.381811 Dram Type= 6, Freq= 0, CH_0, rank 0
5022 13:59:01.385382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5023 13:59:01.385465 ==
5024 13:59:01.391621 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5025 13:59:01.398146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5026 13:59:01.401476 [CA 0] Center 37 (7~68) winsize 62
5027 13:59:01.405212 [CA 1] Center 37 (7~68) winsize 62
5028 13:59:01.408173 [CA 2] Center 34 (4~64) winsize 61
5029 13:59:01.411528 [CA 3] Center 34 (4~65) winsize 62
5030 13:59:01.415155 [CA 4] Center 32 (2~63) winsize 62
5031 13:59:01.418036 [CA 5] Center 32 (2~63) winsize 62
5032 13:59:01.418117
5033 13:59:01.421112 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5034 13:59:01.421193
5035 13:59:01.424630 [CATrainingPosCal] consider 1 rank data
5036 13:59:01.428114 u2DelayCellTimex100 = 270/100 ps
5037 13:59:01.430999 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5038 13:59:01.434460 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5039 13:59:01.437802 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5040 13:59:01.444204 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5041 13:59:01.447813 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5042 13:59:01.451218 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5043 13:59:01.451300
5044 13:59:01.454702 CA PerBit enable=1, Macro0, CA PI delay=32
5045 13:59:01.454798
5046 13:59:01.457514 [CBTSetCACLKResult] CA Dly = 32
5047 13:59:01.457595 CS Dly: 5 (0~36)
5048 13:59:01.457660 ==
5049 13:59:01.460900 Dram Type= 6, Freq= 0, CH_0, rank 1
5050 13:59:01.467300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5051 13:59:01.467383 ==
5052 13:59:01.470803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5053 13:59:01.477052 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5054 13:59:01.481106 [CA 0] Center 37 (7~68) winsize 62
5055 13:59:01.484448 [CA 1] Center 37 (7~68) winsize 62
5056 13:59:01.487224 [CA 2] Center 34 (4~65) winsize 62
5057 13:59:01.490800 [CA 3] Center 34 (4~65) winsize 62
5058 13:59:01.493874 [CA 4] Center 33 (3~64) winsize 62
5059 13:59:01.497103 [CA 5] Center 33 (3~63) winsize 61
5060 13:59:01.497184
5061 13:59:01.500528 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5062 13:59:01.500642
5063 13:59:01.503643 [CATrainingPosCal] consider 2 rank data
5064 13:59:01.507470 u2DelayCellTimex100 = 270/100 ps
5065 13:59:01.510470 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5066 13:59:01.516840 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5067 13:59:01.520148 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5068 13:59:01.523359 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5069 13:59:01.526824 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5070 13:59:01.530212 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5071 13:59:01.530307
5072 13:59:01.533169 CA PerBit enable=1, Macro0, CA PI delay=33
5073 13:59:01.533250
5074 13:59:01.536546 [CBTSetCACLKResult] CA Dly = 33
5075 13:59:01.540145 CS Dly: 6 (0~39)
5076 13:59:01.540226
5077 13:59:01.543034 ----->DramcWriteLeveling(PI) begin...
5078 13:59:01.543142 ==
5079 13:59:01.546803 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 13:59:01.549768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 13:59:01.549851 ==
5082 13:59:01.553624 Write leveling (Byte 0): 34 => 34
5083 13:59:01.556656 Write leveling (Byte 1): 28 => 28
5084 13:59:01.560040 DramcWriteLeveling(PI) end<-----
5085 13:59:01.560121
5086 13:59:01.560185 ==
5087 13:59:01.563463 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 13:59:01.566482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 13:59:01.566573 ==
5090 13:59:01.569703 [Gating] SW mode calibration
5091 13:59:01.576078 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5092 13:59:01.582516 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5093 13:59:01.586601 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5094 13:59:01.593082 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 13:59:01.596684 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 13:59:01.600001 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 13:59:01.606127 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 13:59:01.609359 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 13:59:01.612770 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 13:59:01.616202 0 14 28 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
5101 13:59:01.622894 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5102 13:59:01.626177 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 13:59:01.628911 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 13:59:01.636271 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 13:59:01.639041 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 13:59:01.642203 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 13:59:01.649139 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5108 13:59:01.652223 0 15 28 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (1 1)
5109 13:59:01.655240 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5110 13:59:01.662158 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 13:59:01.665455 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 13:59:01.668793 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 13:59:01.675038 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 13:59:01.678419 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 13:59:01.681553 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 13:59:01.688249 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5117 13:59:01.692172 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5118 13:59:01.695089 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5119 13:59:01.702071 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 13:59:01.704900 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 13:59:01.708291 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 13:59:01.714934 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 13:59:01.718375 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 13:59:01.721200 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 13:59:01.727940 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 13:59:01.731318 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 13:59:01.734937 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 13:59:01.741180 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 13:59:01.744536 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 13:59:01.748317 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 13:59:01.754413 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 13:59:01.757771 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5133 13:59:01.760829 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5134 13:59:01.764489 Total UI for P1: 0, mck2ui 16
5135 13:59:01.767654 best dqsien dly found for B0: ( 1, 2, 28)
5136 13:59:01.774052 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 13:59:01.777260 Total UI for P1: 0, mck2ui 16
5138 13:59:01.780711 best dqsien dly found for B1: ( 1, 3, 0)
5139 13:59:01.784083 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5140 13:59:01.787521 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5141 13:59:01.787603
5142 13:59:01.790851 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5143 13:59:01.794426 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5144 13:59:01.797481 [Gating] SW calibration Done
5145 13:59:01.797562 ==
5146 13:59:01.800538 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 13:59:01.804366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 13:59:01.804448 ==
5149 13:59:01.807121 RX Vref Scan: 0
5150 13:59:01.807202
5151 13:59:01.807267 RX Vref 0 -> 0, step: 1
5152 13:59:01.810582
5153 13:59:01.810662 RX Delay -80 -> 252, step: 8
5154 13:59:01.817209 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5155 13:59:01.821318 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5156 13:59:01.823988 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5157 13:59:01.826920 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5158 13:59:01.830128 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5159 13:59:01.833986 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5160 13:59:01.840221 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5161 13:59:01.843954 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5162 13:59:01.846860 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5163 13:59:01.850072 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5164 13:59:01.853998 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5165 13:59:01.860257 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5166 13:59:01.863404 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5167 13:59:01.866625 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5168 13:59:01.870019 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5169 13:59:01.873367 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5170 13:59:01.873447 ==
5171 13:59:01.876887 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 13:59:01.884026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 13:59:01.884108 ==
5174 13:59:01.884172 DQS Delay:
5175 13:59:01.884232 DQS0 = 0, DQS1 = 0
5176 13:59:01.886778 DQM Delay:
5177 13:59:01.886858 DQM0 = 100, DQM1 = 89
5178 13:59:01.889804 DQ Delay:
5179 13:59:01.892982 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5180 13:59:01.896605 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =111
5181 13:59:01.899854 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5182 13:59:01.903087 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5183 13:59:01.903168
5184 13:59:01.903232
5185 13:59:01.903291 ==
5186 13:59:01.906117 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 13:59:01.909660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 13:59:01.909741 ==
5189 13:59:01.909804
5190 13:59:01.909863
5191 13:59:01.912716 TX Vref Scan disable
5192 13:59:01.916187 == TX Byte 0 ==
5193 13:59:01.919578 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5194 13:59:01.922877 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5195 13:59:01.926116 == TX Byte 1 ==
5196 13:59:01.929471 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5197 13:59:01.932954 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5198 13:59:01.933035 ==
5199 13:59:01.936109 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 13:59:01.939850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 13:59:01.942551 ==
5202 13:59:01.942631
5203 13:59:01.942695
5204 13:59:01.942754 TX Vref Scan disable
5205 13:59:01.946691 == TX Byte 0 ==
5206 13:59:01.949795 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5207 13:59:01.956262 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5208 13:59:01.956343 == TX Byte 1 ==
5209 13:59:01.959812 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5210 13:59:01.966323 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5211 13:59:01.966439
5212 13:59:01.966537 [DATLAT]
5213 13:59:01.966628 Freq=933, CH0 RK0
5214 13:59:01.966727
5215 13:59:01.969544 DATLAT Default: 0xd
5216 13:59:01.972939 0, 0xFFFF, sum = 0
5217 13:59:01.973046 1, 0xFFFF, sum = 0
5218 13:59:01.976266 2, 0xFFFF, sum = 0
5219 13:59:01.976375 3, 0xFFFF, sum = 0
5220 13:59:01.979312 4, 0xFFFF, sum = 0
5221 13:59:01.979410 5, 0xFFFF, sum = 0
5222 13:59:01.982743 6, 0xFFFF, sum = 0
5223 13:59:01.982842 7, 0xFFFF, sum = 0
5224 13:59:01.985983 8, 0xFFFF, sum = 0
5225 13:59:01.986064 9, 0xFFFF, sum = 0
5226 13:59:01.989024 10, 0x0, sum = 1
5227 13:59:01.989106 11, 0x0, sum = 2
5228 13:59:01.992719 12, 0x0, sum = 3
5229 13:59:01.992800 13, 0x0, sum = 4
5230 13:59:01.995738 best_step = 11
5231 13:59:01.995819
5232 13:59:01.995883 ==
5233 13:59:01.999039 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 13:59:02.002336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 13:59:02.002417 ==
5236 13:59:02.002481 RX Vref Scan: 1
5237 13:59:02.005353
5238 13:59:02.005433 RX Vref 0 -> 0, step: 1
5239 13:59:02.005497
5240 13:59:02.009068 RX Delay -61 -> 252, step: 4
5241 13:59:02.009149
5242 13:59:02.011883 Set Vref, RX VrefLevel [Byte0]: 53
5243 13:59:02.015563 [Byte1]: 51
5244 13:59:02.018937
5245 13:59:02.019033 Final RX Vref Byte 0 = 53 to rank0
5246 13:59:02.022471 Final RX Vref Byte 1 = 51 to rank0
5247 13:59:02.025843 Final RX Vref Byte 0 = 53 to rank1
5248 13:59:02.028983 Final RX Vref Byte 1 = 51 to rank1==
5249 13:59:02.032153 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 13:59:02.039007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 13:59:02.039149 ==
5252 13:59:02.039215 DQS Delay:
5253 13:59:02.039276 DQS0 = 0, DQS1 = 0
5254 13:59:02.042031 DQM Delay:
5255 13:59:02.042111 DQM0 = 98, DQM1 = 87
5256 13:59:02.045663 DQ Delay:
5257 13:59:02.048957 DQ0 =100, DQ1 =98, DQ2 =92, DQ3 =96
5258 13:59:02.052250 DQ4 =98, DQ5 =90, DQ6 =108, DQ7 =106
5259 13:59:02.055212 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =82
5260 13:59:02.058500 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =94
5261 13:59:02.058581
5262 13:59:02.058644
5263 13:59:02.065053 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
5264 13:59:02.068539 CH0 RK0: MR19=505, MR18=1F19
5265 13:59:02.074806 CH0_RK0: MR19=0x505, MR18=0x1F19, DQSOSC=412, MR23=63, INC=63, DEC=42
5266 13:59:02.074890
5267 13:59:02.078457 ----->DramcWriteLeveling(PI) begin...
5268 13:59:02.078539 ==
5269 13:59:02.081421 Dram Type= 6, Freq= 0, CH_0, rank 1
5270 13:59:02.084642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 13:59:02.084725 ==
5272 13:59:02.088291 Write leveling (Byte 0): 31 => 31
5273 13:59:02.091541 Write leveling (Byte 1): 29 => 29
5274 13:59:02.095190 DramcWriteLeveling(PI) end<-----
5275 13:59:02.095271
5276 13:59:02.095335 ==
5277 13:59:02.098120 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 13:59:02.104469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 13:59:02.104577 ==
5280 13:59:02.104674 [Gating] SW mode calibration
5281 13:59:02.115391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5282 13:59:02.117553 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5283 13:59:02.120973 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
5284 13:59:02.128266 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 13:59:02.130683 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 13:59:02.134205 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 13:59:02.141274 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 13:59:02.144538 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 13:59:02.147968 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 13:59:02.154029 0 14 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
5291 13:59:02.157559 0 15 0 | B1->B0 | 3030 2525 | 1 0 | (1 0) (0 0)
5292 13:59:02.160764 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5293 13:59:02.167096 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 13:59:02.170619 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 13:59:02.174251 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 13:59:02.180638 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 13:59:02.184051 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5298 13:59:02.187507 0 15 28 | B1->B0 | 2828 3d3d | 0 0 | (0 0) (0 0)
5299 13:59:02.193386 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5300 13:59:02.197338 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 13:59:02.200471 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 13:59:02.207253 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 13:59:02.210225 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 13:59:02.213193 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 13:59:02.219767 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5306 13:59:02.223326 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5307 13:59:02.229888 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 13:59:02.232871 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 13:59:02.236605 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 13:59:02.243099 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 13:59:02.246431 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 13:59:02.249717 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 13:59:02.256057 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 13:59:02.259409 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 13:59:02.262672 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 13:59:02.268991 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 13:59:02.272650 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 13:59:02.275695 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 13:59:02.282457 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 13:59:02.285780 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 13:59:02.288977 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 13:59:02.295726 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5323 13:59:02.295808 Total UI for P1: 0, mck2ui 16
5324 13:59:02.298857 best dqsien dly found for B0: ( 1, 2, 26)
5325 13:59:02.305522 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5326 13:59:02.308693 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5327 13:59:02.312120 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 13:59:02.315240 Total UI for P1: 0, mck2ui 16
5329 13:59:02.318900 best dqsien dly found for B1: ( 1, 3, 0)
5330 13:59:02.325515 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5331 13:59:02.328841 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5332 13:59:02.328921
5333 13:59:02.331901 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5334 13:59:02.334932 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5335 13:59:02.338609 [Gating] SW calibration Done
5336 13:59:02.338690 ==
5337 13:59:02.342311 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 13:59:02.345247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 13:59:02.345329 ==
5340 13:59:02.348392 RX Vref Scan: 0
5341 13:59:02.348471
5342 13:59:02.348534 RX Vref 0 -> 0, step: 1
5343 13:59:02.348594
5344 13:59:02.351855 RX Delay -80 -> 252, step: 8
5345 13:59:02.355199 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5346 13:59:02.358134 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5347 13:59:02.365046 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5348 13:59:02.367980 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5349 13:59:02.371297 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5350 13:59:02.375200 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5351 13:59:02.378386 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5352 13:59:02.381615 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5353 13:59:02.387822 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5354 13:59:02.391354 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5355 13:59:02.394782 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5356 13:59:02.397963 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5357 13:59:02.401352 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5358 13:59:02.404457 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5359 13:59:02.411420 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5360 13:59:02.414598 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5361 13:59:02.414679 ==
5362 13:59:02.417961 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 13:59:02.421075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 13:59:02.421155 ==
5365 13:59:02.424317 DQS Delay:
5366 13:59:02.424399 DQS0 = 0, DQS1 = 0
5367 13:59:02.424463 DQM Delay:
5368 13:59:02.427700 DQM0 = 97, DQM1 = 89
5369 13:59:02.427780 DQ Delay:
5370 13:59:02.430940 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5371 13:59:02.434505 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5372 13:59:02.437388 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5373 13:59:02.440944 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91
5374 13:59:02.441024
5375 13:59:02.441087
5376 13:59:02.444147 ==
5377 13:59:02.444226 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 13:59:02.451097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 13:59:02.451194 ==
5380 13:59:02.451258
5381 13:59:02.451318
5382 13:59:02.453928 TX Vref Scan disable
5383 13:59:02.454007 == TX Byte 0 ==
5384 13:59:02.457557 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5385 13:59:02.464274 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5386 13:59:02.464355 == TX Byte 1 ==
5387 13:59:02.467541 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5388 13:59:02.474158 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5389 13:59:02.474239 ==
5390 13:59:02.477613 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 13:59:02.480602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 13:59:02.480683 ==
5393 13:59:02.480747
5394 13:59:02.480807
5395 13:59:02.483808 TX Vref Scan disable
5396 13:59:02.486981 == TX Byte 0 ==
5397 13:59:02.490814 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5398 13:59:02.493777 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5399 13:59:02.496924 == TX Byte 1 ==
5400 13:59:02.500133 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5401 13:59:02.503266 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5402 13:59:02.503346
5403 13:59:02.506799 [DATLAT]
5404 13:59:02.506879 Freq=933, CH0 RK1
5405 13:59:02.506944
5406 13:59:02.509835 DATLAT Default: 0xb
5407 13:59:02.509915 0, 0xFFFF, sum = 0
5408 13:59:02.513433 1, 0xFFFF, sum = 0
5409 13:59:02.513515 2, 0xFFFF, sum = 0
5410 13:59:02.516716 3, 0xFFFF, sum = 0
5411 13:59:02.516799 4, 0xFFFF, sum = 0
5412 13:59:02.519777 5, 0xFFFF, sum = 0
5413 13:59:02.519859 6, 0xFFFF, sum = 0
5414 13:59:02.523435 7, 0xFFFF, sum = 0
5415 13:59:02.523518 8, 0xFFFF, sum = 0
5416 13:59:02.526460 9, 0xFFFF, sum = 0
5417 13:59:02.526541 10, 0x0, sum = 1
5418 13:59:02.529522 11, 0x0, sum = 2
5419 13:59:02.529608 12, 0x0, sum = 3
5420 13:59:02.532719 13, 0x0, sum = 4
5421 13:59:02.532801 best_step = 11
5422 13:59:02.532865
5423 13:59:02.532924 ==
5424 13:59:02.536609 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 13:59:02.543169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 13:59:02.543251 ==
5427 13:59:02.543336 RX Vref Scan: 0
5428 13:59:02.543411
5429 13:59:02.546088 RX Vref 0 -> 0, step: 1
5430 13:59:02.546168
5431 13:59:02.549617 RX Delay -53 -> 252, step: 4
5432 13:59:02.552857 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5433 13:59:02.556256 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5434 13:59:02.562451 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5435 13:59:02.566077 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5436 13:59:02.569234 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5437 13:59:02.572473 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5438 13:59:02.575886 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5439 13:59:02.582221 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5440 13:59:02.585904 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5441 13:59:02.589023 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5442 13:59:02.592635 iDelay=195, Bit 10, Center 86 (-5 ~ 178) 184
5443 13:59:02.597067 iDelay=195, Bit 11, Center 80 (-9 ~ 170) 180
5444 13:59:02.602086 iDelay=195, Bit 12, Center 92 (3 ~ 182) 180
5445 13:59:02.605910 iDelay=195, Bit 13, Center 94 (7 ~ 182) 176
5446 13:59:02.608810 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5447 13:59:02.612314 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5448 13:59:02.612395 ==
5449 13:59:02.615543 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 13:59:02.618794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 13:59:02.618904 ==
5452 13:59:02.621878 DQS Delay:
5453 13:59:02.621959 DQS0 = 0, DQS1 = 0
5454 13:59:02.625611 DQM Delay:
5455 13:59:02.625727 DQM0 = 97, DQM1 = 87
5456 13:59:02.628719 DQ Delay:
5457 13:59:02.628799 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =94
5458 13:59:02.631949 DQ4 =100, DQ5 =86, DQ6 =108, DQ7 =104
5459 13:59:02.634962 DQ8 =80, DQ9 =76, DQ10 =86, DQ11 =80
5460 13:59:02.641530 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =94
5461 13:59:02.641611
5462 13:59:02.641675
5463 13:59:02.648682 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5464 13:59:02.651729 CH0 RK1: MR19=505, MR18=1B18
5465 13:59:02.658241 CH0_RK1: MR19=0x505, MR18=0x1B18, DQSOSC=413, MR23=63, INC=63, DEC=42
5466 13:59:02.661399 [RxdqsGatingPostProcess] freq 933
5467 13:59:02.664646 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5468 13:59:02.668423 best DQS0 dly(2T, 0.5T) = (0, 10)
5469 13:59:02.671342 best DQS1 dly(2T, 0.5T) = (0, 11)
5470 13:59:02.674558 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5471 13:59:02.677767 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5472 13:59:02.681400 best DQS0 dly(2T, 0.5T) = (0, 10)
5473 13:59:02.684900 best DQS1 dly(2T, 0.5T) = (0, 11)
5474 13:59:02.687450 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5475 13:59:02.691371 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5476 13:59:02.694567 Pre-setting of DQS Precalculation
5477 13:59:02.698025 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5478 13:59:02.700756 ==
5479 13:59:02.700837 Dram Type= 6, Freq= 0, CH_1, rank 0
5480 13:59:02.707916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 13:59:02.708002 ==
5482 13:59:02.710488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5483 13:59:02.717455 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5484 13:59:02.720832 [CA 0] Center 36 (6~67) winsize 62
5485 13:59:02.724296 [CA 1] Center 36 (6~67) winsize 62
5486 13:59:02.727884 [CA 2] Center 34 (4~65) winsize 62
5487 13:59:02.730711 [CA 3] Center 33 (3~64) winsize 62
5488 13:59:02.734287 [CA 4] Center 34 (4~65) winsize 62
5489 13:59:02.737549 [CA 5] Center 33 (3~64) winsize 62
5490 13:59:02.737630
5491 13:59:02.740415 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5492 13:59:02.740495
5493 13:59:02.743930 [CATrainingPosCal] consider 1 rank data
5494 13:59:02.747368 u2DelayCellTimex100 = 270/100 ps
5495 13:59:02.750795 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5496 13:59:02.757114 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5497 13:59:02.760672 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5498 13:59:02.763635 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5499 13:59:02.766948 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5500 13:59:02.770959 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5501 13:59:02.771041
5502 13:59:02.773945 CA PerBit enable=1, Macro0, CA PI delay=33
5503 13:59:02.774062
5504 13:59:02.776875 [CBTSetCACLKResult] CA Dly = 33
5505 13:59:02.780411 CS Dly: 5 (0~36)
5506 13:59:02.780491 ==
5507 13:59:02.783703 Dram Type= 6, Freq= 0, CH_1, rank 1
5508 13:59:02.786712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 13:59:02.786793 ==
5510 13:59:02.793235 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5511 13:59:02.796738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5512 13:59:02.801153 [CA 0] Center 36 (6~66) winsize 61
5513 13:59:02.804448 [CA 1] Center 36 (6~67) winsize 62
5514 13:59:02.807721 [CA 2] Center 34 (4~65) winsize 62
5515 13:59:02.810914 [CA 3] Center 33 (3~64) winsize 62
5516 13:59:02.814130 [CA 4] Center 33 (3~64) winsize 62
5517 13:59:02.817280 [CA 5] Center 33 (3~64) winsize 62
5518 13:59:02.817360
5519 13:59:02.820816 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5520 13:59:02.820922
5521 13:59:02.823879 [CATrainingPosCal] consider 2 rank data
5522 13:59:02.827288 u2DelayCellTimex100 = 270/100 ps
5523 13:59:02.830473 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5524 13:59:02.837335 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5525 13:59:02.840357 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5526 13:59:02.843347 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5527 13:59:02.846759 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5528 13:59:02.850203 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5529 13:59:02.850284
5530 13:59:02.853384 CA PerBit enable=1, Macro0, CA PI delay=33
5531 13:59:02.853465
5532 13:59:02.856535 [CBTSetCACLKResult] CA Dly = 33
5533 13:59:02.860352 CS Dly: 6 (0~38)
5534 13:59:02.860433
5535 13:59:02.863403 ----->DramcWriteLeveling(PI) begin...
5536 13:59:02.863529 ==
5537 13:59:02.866979 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 13:59:02.870143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 13:59:02.870243 ==
5540 13:59:02.873272 Write leveling (Byte 0): 27 => 27
5541 13:59:02.876672 Write leveling (Byte 1): 28 => 28
5542 13:59:02.879690 DramcWriteLeveling(PI) end<-----
5543 13:59:02.879771
5544 13:59:02.879835 ==
5545 13:59:02.883670 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 13:59:02.886446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 13:59:02.886552 ==
5548 13:59:02.889408 [Gating] SW mode calibration
5549 13:59:02.896273 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5550 13:59:02.902864 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5551 13:59:02.906462 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 13:59:02.912734 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 13:59:02.916232 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 13:59:02.918951 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 13:59:02.925553 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 13:59:02.929155 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 13:59:02.932529 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5558 13:59:02.939211 0 14 28 | B1->B0 | 2e2e 2424 | 0 0 | (1 0) (1 0)
5559 13:59:02.942617 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 13:59:02.945825 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 13:59:02.952089 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 13:59:02.955478 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 13:59:02.958583 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 13:59:02.965142 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 13:59:02.968725 0 15 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
5566 13:59:02.972208 0 15 28 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
5567 13:59:02.978440 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 13:59:02.981571 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 13:59:02.985149 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 13:59:02.991629 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 13:59:02.995039 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 13:59:02.998596 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 13:59:03.004976 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 13:59:03.008097 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5575 13:59:03.011469 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 13:59:03.017836 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 13:59:03.021013 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 13:59:03.024638 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 13:59:03.031558 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 13:59:03.034469 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 13:59:03.037660 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 13:59:03.045026 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 13:59:03.047921 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 13:59:03.050893 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 13:59:03.057840 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 13:59:03.061088 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 13:59:03.064962 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 13:59:03.070569 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 13:59:03.074153 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5590 13:59:03.077484 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5591 13:59:03.083660 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 13:59:03.083741 Total UI for P1: 0, mck2ui 16
5593 13:59:03.090285 best dqsien dly found for B0: ( 1, 2, 28)
5594 13:59:03.090366 Total UI for P1: 0, mck2ui 16
5595 13:59:03.096748 best dqsien dly found for B1: ( 1, 2, 26)
5596 13:59:03.100448 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5597 13:59:03.103584 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5598 13:59:03.103665
5599 13:59:03.106828 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5600 13:59:03.110377 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5601 13:59:03.113330 [Gating] SW calibration Done
5602 13:59:03.113412 ==
5603 13:59:03.116692 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 13:59:03.120146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 13:59:03.120227 ==
5606 13:59:03.123624 RX Vref Scan: 0
5607 13:59:03.123705
5608 13:59:03.123769 RX Vref 0 -> 0, step: 1
5609 13:59:03.123829
5610 13:59:03.126662 RX Delay -80 -> 252, step: 8
5611 13:59:03.133116 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5612 13:59:03.136894 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5613 13:59:03.139973 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5614 13:59:03.143060 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5615 13:59:03.146679 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5616 13:59:03.149459 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5617 13:59:03.156496 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5618 13:59:03.159622 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5619 13:59:03.162532 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5620 13:59:03.166110 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5621 13:59:03.169648 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5622 13:59:03.172567 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5623 13:59:03.178971 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5624 13:59:03.182511 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5625 13:59:03.185735 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5626 13:59:03.188956 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5627 13:59:03.189037 ==
5628 13:59:03.192369 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 13:59:03.199048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 13:59:03.199153 ==
5631 13:59:03.199218 DQS Delay:
5632 13:59:03.199277 DQS0 = 0, DQS1 = 0
5633 13:59:03.202034 DQM Delay:
5634 13:59:03.202114 DQM0 = 100, DQM1 = 96
5635 13:59:03.205765 DQ Delay:
5636 13:59:03.209081 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5637 13:59:03.212056 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5638 13:59:03.215691 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5639 13:59:03.219087 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5640 13:59:03.219183
5641 13:59:03.219247
5642 13:59:03.219308 ==
5643 13:59:03.221999 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 13:59:03.225700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 13:59:03.225782 ==
5646 13:59:03.225846
5647 13:59:03.225905
5648 13:59:03.228650 TX Vref Scan disable
5649 13:59:03.232058 == TX Byte 0 ==
5650 13:59:03.235064 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5651 13:59:03.238509 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5652 13:59:03.241581 == TX Byte 1 ==
5653 13:59:03.244900 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5654 13:59:03.248512 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5655 13:59:03.248611 ==
5656 13:59:03.251601 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 13:59:03.257916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 13:59:03.258032 ==
5659 13:59:03.258124
5660 13:59:03.258229
5661 13:59:03.258320 TX Vref Scan disable
5662 13:59:03.262408 == TX Byte 0 ==
5663 13:59:03.265634 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5664 13:59:03.272252 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5665 13:59:03.272366 == TX Byte 1 ==
5666 13:59:03.275290 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5667 13:59:03.282076 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5668 13:59:03.282185
5669 13:59:03.282290 [DATLAT]
5670 13:59:03.282379 Freq=933, CH1 RK0
5671 13:59:03.282484
5672 13:59:03.285410 DATLAT Default: 0xd
5673 13:59:03.288668 0, 0xFFFF, sum = 0
5674 13:59:03.288769 1, 0xFFFF, sum = 0
5675 13:59:03.292172 2, 0xFFFF, sum = 0
5676 13:59:03.292279 3, 0xFFFF, sum = 0
5677 13:59:03.295343 4, 0xFFFF, sum = 0
5678 13:59:03.295451 5, 0xFFFF, sum = 0
5679 13:59:03.298370 6, 0xFFFF, sum = 0
5680 13:59:03.298486 7, 0xFFFF, sum = 0
5681 13:59:03.301568 8, 0xFFFF, sum = 0
5682 13:59:03.301674 9, 0xFFFF, sum = 0
5683 13:59:03.304909 10, 0x0, sum = 1
5684 13:59:03.305013 11, 0x0, sum = 2
5685 13:59:03.307931 12, 0x0, sum = 3
5686 13:59:03.308031 13, 0x0, sum = 4
5687 13:59:03.311923 best_step = 11
5688 13:59:03.312027
5689 13:59:03.312127 ==
5690 13:59:03.314674 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 13:59:03.318356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 13:59:03.318465 ==
5693 13:59:03.318560 RX Vref Scan: 1
5694 13:59:03.321151
5695 13:59:03.321256 RX Vref 0 -> 0, step: 1
5696 13:59:03.321347
5697 13:59:03.324967 RX Delay -53 -> 252, step: 4
5698 13:59:03.325064
5699 13:59:03.328250 Set Vref, RX VrefLevel [Byte0]: 51
5700 13:59:03.331090 [Byte1]: 53
5701 13:59:03.334774
5702 13:59:03.334873 Final RX Vref Byte 0 = 51 to rank0
5703 13:59:03.337953 Final RX Vref Byte 1 = 53 to rank0
5704 13:59:03.341086 Final RX Vref Byte 0 = 51 to rank1
5705 13:59:03.344465 Final RX Vref Byte 1 = 53 to rank1==
5706 13:59:03.347834 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 13:59:03.354446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 13:59:03.354552 ==
5709 13:59:03.354657 DQS Delay:
5710 13:59:03.357960 DQS0 = 0, DQS1 = 0
5711 13:59:03.358062 DQM Delay:
5712 13:59:03.358162 DQM0 = 98, DQM1 = 94
5713 13:59:03.361628 DQ Delay:
5714 13:59:03.364528 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98
5715 13:59:03.367604 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5716 13:59:03.371223 DQ8 =80, DQ9 =84, DQ10 =96, DQ11 =88
5717 13:59:03.373988 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5718 13:59:03.374095
5719 13:59:03.374187
5720 13:59:03.380999 [DQSOSCAuto] RK0, (LSB)MR18= 0x919, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 419 ps
5721 13:59:03.384261 CH1 RK0: MR19=505, MR18=919
5722 13:59:03.390504 CH1_RK0: MR19=0x505, MR18=0x919, DQSOSC=413, MR23=63, INC=63, DEC=42
5723 13:59:03.390608
5724 13:59:03.393632 ----->DramcWriteLeveling(PI) begin...
5725 13:59:03.393734 ==
5726 13:59:03.397208 Dram Type= 6, Freq= 0, CH_1, rank 1
5727 13:59:03.400704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 13:59:03.403642 ==
5729 13:59:03.403743 Write leveling (Byte 0): 25 => 25
5730 13:59:03.406722 Write leveling (Byte 1): 25 => 25
5731 13:59:03.410435 DramcWriteLeveling(PI) end<-----
5732 13:59:03.410530
5733 13:59:03.410648 ==
5734 13:59:03.413707 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 13:59:03.420113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 13:59:03.420213 ==
5737 13:59:03.420306 [Gating] SW mode calibration
5738 13:59:03.430274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5739 13:59:03.433535 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5740 13:59:03.440228 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 13:59:03.443048 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 13:59:03.446861 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 13:59:03.452969 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 13:59:03.456526 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 13:59:03.459475 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 13:59:03.466227 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
5747 13:59:03.469511 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5748 13:59:03.472740 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 13:59:03.479488 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 13:59:03.482916 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 13:59:03.486417 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 13:59:03.492601 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 13:59:03.495652 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 13:59:03.499219 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5755 13:59:03.505936 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5756 13:59:03.509333 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 13:59:03.512430 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 13:59:03.518758 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 13:59:03.521942 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 13:59:03.525545 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 13:59:03.531961 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 13:59:03.535485 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5763 13:59:03.538569 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5764 13:59:03.545042 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 13:59:03.548715 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 13:59:03.551782 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 13:59:03.558173 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 13:59:03.561673 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 13:59:03.565100 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 13:59:03.571773 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 13:59:03.574668 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 13:59:03.578560 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 13:59:03.584552 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 13:59:03.587924 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 13:59:03.591347 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 13:59:03.598133 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 13:59:03.601308 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 13:59:03.604535 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5779 13:59:03.610972 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5780 13:59:03.611078 Total UI for P1: 0, mck2ui 16
5781 13:59:03.617854 best dqsien dly found for B0: ( 1, 2, 24)
5782 13:59:03.621277 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 13:59:03.624491 Total UI for P1: 0, mck2ui 16
5784 13:59:03.627611 best dqsien dly found for B1: ( 1, 2, 26)
5785 13:59:03.630911 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5786 13:59:03.634349 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5787 13:59:03.634447
5788 13:59:03.637955 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5789 13:59:03.640582 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5790 13:59:03.644387 [Gating] SW calibration Done
5791 13:59:03.644494 ==
5792 13:59:03.647179 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 13:59:03.650500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 13:59:03.653984 ==
5795 13:59:03.654084 RX Vref Scan: 0
5796 13:59:03.654179
5797 13:59:03.657506 RX Vref 0 -> 0, step: 1
5798 13:59:03.657604
5799 13:59:03.660403 RX Delay -80 -> 252, step: 8
5800 13:59:03.663726 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5801 13:59:03.667210 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5802 13:59:03.670487 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5803 13:59:03.673620 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5804 13:59:03.680719 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5805 13:59:03.683705 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5806 13:59:03.686584 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5807 13:59:03.690198 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5808 13:59:03.693424 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5809 13:59:03.696682 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5810 13:59:03.703640 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5811 13:59:03.706484 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5812 13:59:03.709745 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5813 13:59:03.713053 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5814 13:59:03.716519 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5815 13:59:03.722799 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5816 13:59:03.722897 ==
5817 13:59:03.726097 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 13:59:03.729827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 13:59:03.729922 ==
5820 13:59:03.730013 DQS Delay:
5821 13:59:03.732899 DQS0 = 0, DQS1 = 0
5822 13:59:03.732967 DQM Delay:
5823 13:59:03.736062 DQM0 = 97, DQM1 = 94
5824 13:59:03.736131 DQ Delay:
5825 13:59:03.739594 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5826 13:59:03.742804 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5827 13:59:03.746058 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5828 13:59:03.749205 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5829 13:59:03.749298
5830 13:59:03.749387
5831 13:59:03.749475 ==
5832 13:59:03.752426 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 13:59:03.758994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 13:59:03.759141 ==
5835 13:59:03.759238
5836 13:59:03.759339
5837 13:59:03.759427 TX Vref Scan disable
5838 13:59:03.762698 == TX Byte 0 ==
5839 13:59:03.766776 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5840 13:59:03.772341 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5841 13:59:03.772449 == TX Byte 1 ==
5842 13:59:03.775654 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5843 13:59:03.782514 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5844 13:59:03.782629 ==
5845 13:59:03.785594 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 13:59:03.789038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 13:59:03.789137 ==
5848 13:59:03.789235
5849 13:59:03.789334
5850 13:59:03.792347 TX Vref Scan disable
5851 13:59:03.792448 == TX Byte 0 ==
5852 13:59:03.798666 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5853 13:59:03.802918 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5854 13:59:03.803016 == TX Byte 1 ==
5855 13:59:03.808769 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5856 13:59:03.812221 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5857 13:59:03.812318
5858 13:59:03.812407 [DATLAT]
5859 13:59:03.815765 Freq=933, CH1 RK1
5860 13:59:03.815863
5861 13:59:03.815964 DATLAT Default: 0xb
5862 13:59:03.818814 0, 0xFFFF, sum = 0
5863 13:59:03.818921 1, 0xFFFF, sum = 0
5864 13:59:03.821811 2, 0xFFFF, sum = 0
5865 13:59:03.821950 3, 0xFFFF, sum = 0
5866 13:59:03.825479 4, 0xFFFF, sum = 0
5867 13:59:03.828840 5, 0xFFFF, sum = 0
5868 13:59:03.828944 6, 0xFFFF, sum = 0
5869 13:59:03.832082 7, 0xFFFF, sum = 0
5870 13:59:03.832184 8, 0xFFFF, sum = 0
5871 13:59:03.835181 9, 0xFFFF, sum = 0
5872 13:59:03.835251 10, 0x0, sum = 1
5873 13:59:03.838715 11, 0x0, sum = 2
5874 13:59:03.838876 12, 0x0, sum = 3
5875 13:59:03.841685 13, 0x0, sum = 4
5876 13:59:03.841789 best_step = 11
5877 13:59:03.841891
5878 13:59:03.841982 ==
5879 13:59:03.845456 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 13:59:03.848941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 13:59:03.849047 ==
5882 13:59:03.851622 RX Vref Scan: 0
5883 13:59:03.851726
5884 13:59:03.854909 RX Vref 0 -> 0, step: 1
5885 13:59:03.855038
5886 13:59:03.855136 RX Delay -53 -> 252, step: 4
5887 13:59:03.862722 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5888 13:59:03.866221 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5889 13:59:03.869467 iDelay=199, Bit 2, Center 88 (-1 ~ 178) 180
5890 13:59:03.872453 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5891 13:59:03.876142 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5892 13:59:03.882432 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5893 13:59:03.885583 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5894 13:59:03.888962 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5895 13:59:03.892222 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5896 13:59:03.895566 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5897 13:59:03.898739 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5898 13:59:03.905757 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5899 13:59:03.908915 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5900 13:59:03.912746 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5901 13:59:03.915410 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5902 13:59:03.922043 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5903 13:59:03.922124 ==
5904 13:59:03.925531 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 13:59:03.928987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 13:59:03.929068 ==
5907 13:59:03.929133 DQS Delay:
5908 13:59:03.932055 DQS0 = 0, DQS1 = 0
5909 13:59:03.932135 DQM Delay:
5910 13:59:03.935229 DQM0 = 97, DQM1 = 93
5911 13:59:03.935310 DQ Delay:
5912 13:59:03.938699 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
5913 13:59:03.941691 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5914 13:59:03.945492 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =86
5915 13:59:03.948617 DQ12 =100, DQ13 =102, DQ14 =98, DQ15 =102
5916 13:59:03.948698
5917 13:59:03.948762
5918 13:59:03.958635 [DQSOSCAuto] RK1, (LSB)MR18= 0xd23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5919 13:59:03.958718 CH1 RK1: MR19=505, MR18=D23
5920 13:59:03.965003 CH1_RK1: MR19=0x505, MR18=0xD23, DQSOSC=410, MR23=63, INC=64, DEC=42
5921 13:59:03.968129 [RxdqsGatingPostProcess] freq 933
5922 13:59:03.974677 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5923 13:59:03.978645 best DQS0 dly(2T, 0.5T) = (0, 10)
5924 13:59:03.981391 best DQS1 dly(2T, 0.5T) = (0, 10)
5925 13:59:03.984929 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5926 13:59:03.988421 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5927 13:59:03.991501 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 13:59:03.994587 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 13:59:03.994687 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 13:59:03.997874 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 13:59:04.000881 Pre-setting of DQS Precalculation
5932 13:59:04.007445 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5933 13:59:04.014101 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5934 13:59:04.020923 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5935 13:59:04.021025
5936 13:59:04.021127
5937 13:59:04.024202 [Calibration Summary] 1866 Mbps
5938 13:59:04.027922 CH 0, Rank 0
5939 13:59:04.027994 SW Impedance : PASS
5940 13:59:04.030770 DUTY Scan : NO K
5941 13:59:04.034071 ZQ Calibration : PASS
5942 13:59:04.034176 Jitter Meter : NO K
5943 13:59:04.037580 CBT Training : PASS
5944 13:59:04.040567 Write leveling : PASS
5945 13:59:04.040664 RX DQS gating : PASS
5946 13:59:04.043835 RX DQ/DQS(RDDQC) : PASS
5947 13:59:04.047265 TX DQ/DQS : PASS
5948 13:59:04.047335 RX DATLAT : PASS
5949 13:59:04.050429 RX DQ/DQS(Engine): PASS
5950 13:59:04.053650 TX OE : NO K
5951 13:59:04.053751 All Pass.
5952 13:59:04.053844
5953 13:59:04.053932 CH 0, Rank 1
5954 13:59:04.057182 SW Impedance : PASS
5955 13:59:04.060184 DUTY Scan : NO K
5956 13:59:04.060284 ZQ Calibration : PASS
5957 13:59:04.063765 Jitter Meter : NO K
5958 13:59:04.063836 CBT Training : PASS
5959 13:59:04.066574 Write leveling : PASS
5960 13:59:04.070283 RX DQS gating : PASS
5961 13:59:04.070353 RX DQ/DQS(RDDQC) : PASS
5962 13:59:04.073921 TX DQ/DQS : PASS
5963 13:59:04.076853 RX DATLAT : PASS
5964 13:59:04.076951 RX DQ/DQS(Engine): PASS
5965 13:59:04.080028 TX OE : NO K
5966 13:59:04.080132 All Pass.
5967 13:59:04.080226
5968 13:59:04.083249 CH 1, Rank 0
5969 13:59:04.083346 SW Impedance : PASS
5970 13:59:04.086312 DUTY Scan : NO K
5971 13:59:04.089602 ZQ Calibration : PASS
5972 13:59:04.089702 Jitter Meter : NO K
5973 13:59:04.092891 CBT Training : PASS
5974 13:59:04.096764 Write leveling : PASS
5975 13:59:04.096864 RX DQS gating : PASS
5976 13:59:04.099685 RX DQ/DQS(RDDQC) : PASS
5977 13:59:04.102981 TX DQ/DQS : PASS
5978 13:59:04.103086 RX DATLAT : PASS
5979 13:59:04.106258 RX DQ/DQS(Engine): PASS
5980 13:59:04.109509 TX OE : NO K
5981 13:59:04.109611 All Pass.
5982 13:59:04.109701
5983 13:59:04.109790 CH 1, Rank 1
5984 13:59:04.112846 SW Impedance : PASS
5985 13:59:04.116268 DUTY Scan : NO K
5986 13:59:04.116341 ZQ Calibration : PASS
5987 13:59:04.119939 Jitter Meter : NO K
5988 13:59:04.122839 CBT Training : PASS
5989 13:59:04.122935 Write leveling : PASS
5990 13:59:04.126253 RX DQS gating : PASS
5991 13:59:04.129365 RX DQ/DQS(RDDQC) : PASS
5992 13:59:04.129463 TX DQ/DQS : PASS
5993 13:59:04.132786 RX DATLAT : PASS
5994 13:59:04.132891 RX DQ/DQS(Engine): PASS
5995 13:59:04.136223 TX OE : NO K
5996 13:59:04.136324 All Pass.
5997 13:59:04.136419
5998 13:59:04.140099 DramC Write-DBI off
5999 13:59:04.142992 PER_BANK_REFRESH: Hybrid Mode
6000 13:59:04.143102 TX_TRACKING: ON
6001 13:59:04.152764 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6002 13:59:04.155878 [FAST_K] Save calibration result to emmc
6003 13:59:04.159049 dramc_set_vcore_voltage set vcore to 650000
6004 13:59:04.162595 Read voltage for 400, 6
6005 13:59:04.162694 Vio18 = 0
6006 13:59:04.165640 Vcore = 650000
6007 13:59:04.165714 Vdram = 0
6008 13:59:04.165781 Vddq = 0
6009 13:59:04.165840 Vmddr = 0
6010 13:59:04.172511 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6011 13:59:04.179396 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6012 13:59:04.179472 MEM_TYPE=3, freq_sel=20
6013 13:59:04.182412 sv_algorithm_assistance_LP4_800
6014 13:59:04.185464 ============ PULL DRAM RESETB DOWN ============
6015 13:59:04.192219 ========== PULL DRAM RESETB DOWN end =========
6016 13:59:04.195671 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6017 13:59:04.198955 ===================================
6018 13:59:04.202219 LPDDR4 DRAM CONFIGURATION
6019 13:59:04.205408 ===================================
6020 13:59:04.205489 EX_ROW_EN[0] = 0x0
6021 13:59:04.208600 EX_ROW_EN[1] = 0x0
6022 13:59:04.211987 LP4Y_EN = 0x0
6023 13:59:04.212067 WORK_FSP = 0x0
6024 13:59:04.214881 WL = 0x2
6025 13:59:04.214961 RL = 0x2
6026 13:59:04.218689 BL = 0x2
6027 13:59:04.218769 RPST = 0x0
6028 13:59:04.221733 RD_PRE = 0x0
6029 13:59:04.221813 WR_PRE = 0x1
6030 13:59:04.225078 WR_PST = 0x0
6031 13:59:04.225158 DBI_WR = 0x0
6032 13:59:04.228394 DBI_RD = 0x0
6033 13:59:04.228474 OTF = 0x1
6034 13:59:04.231464 ===================================
6035 13:59:04.235013 ===================================
6036 13:59:04.238608 ANA top config
6037 13:59:04.241542 ===================================
6038 13:59:04.244833 DLL_ASYNC_EN = 0
6039 13:59:04.244930 ALL_SLAVE_EN = 1
6040 13:59:04.248285 NEW_RANK_MODE = 1
6041 13:59:04.251085 DLL_IDLE_MODE = 1
6042 13:59:04.254646 LP45_APHY_COMB_EN = 1
6043 13:59:04.254742 TX_ODT_DIS = 1
6044 13:59:04.258004 NEW_8X_MODE = 1
6045 13:59:04.261116 ===================================
6046 13:59:04.264435 ===================================
6047 13:59:04.267804 data_rate = 800
6048 13:59:04.270928 CKR = 1
6049 13:59:04.274459 DQ_P2S_RATIO = 4
6050 13:59:04.277515 ===================================
6051 13:59:04.281301 CA_P2S_RATIO = 4
6052 13:59:04.281398 DQ_CA_OPEN = 0
6053 13:59:04.284792 DQ_SEMI_OPEN = 1
6054 13:59:04.287515 CA_SEMI_OPEN = 1
6055 13:59:04.290775 CA_FULL_RATE = 0
6056 13:59:04.294885 DQ_CKDIV4_EN = 0
6057 13:59:04.297304 CA_CKDIV4_EN = 1
6058 13:59:04.297402 CA_PREDIV_EN = 0
6059 13:59:04.300617 PH8_DLY = 0
6060 13:59:04.304093 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6061 13:59:04.307311 DQ_AAMCK_DIV = 0
6062 13:59:04.310548 CA_AAMCK_DIV = 0
6063 13:59:04.313921 CA_ADMCK_DIV = 4
6064 13:59:04.317569 DQ_TRACK_CA_EN = 0
6065 13:59:04.317669 CA_PICK = 800
6066 13:59:04.320608 CA_MCKIO = 400
6067 13:59:04.324631 MCKIO_SEMI = 400
6068 13:59:04.327273 PLL_FREQ = 3016
6069 13:59:04.330025 DQ_UI_PI_RATIO = 32
6070 13:59:04.333319 CA_UI_PI_RATIO = 32
6071 13:59:04.336789 ===================================
6072 13:59:04.340095 ===================================
6073 13:59:04.343238 memory_type:LPDDR4
6074 13:59:04.343314 GP_NUM : 10
6075 13:59:04.346399 SRAM_EN : 1
6076 13:59:04.346495 MD32_EN : 0
6077 13:59:04.349909 ===================================
6078 13:59:04.354199 [ANA_INIT] >>>>>>>>>>>>>>
6079 13:59:04.356329 <<<<<< [CONFIGURE PHASE]: ANA_TX
6080 13:59:04.359670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6081 13:59:04.362944 ===================================
6082 13:59:04.366448 data_rate = 800,PCW = 0X7400
6083 13:59:04.370076 ===================================
6084 13:59:04.373078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6085 13:59:04.379576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6086 13:59:04.389915 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6087 13:59:04.393102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6088 13:59:04.396792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6089 13:59:04.399686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6090 13:59:04.403048 [ANA_INIT] flow start
6091 13:59:04.406114 [ANA_INIT] PLL >>>>>>>>
6092 13:59:04.406182 [ANA_INIT] PLL <<<<<<<<
6093 13:59:04.409728 [ANA_INIT] MIDPI >>>>>>>>
6094 13:59:04.412944 [ANA_INIT] MIDPI <<<<<<<<
6095 13:59:04.415965 [ANA_INIT] DLL >>>>>>>>
6096 13:59:04.416038 [ANA_INIT] flow end
6097 13:59:04.419521 ============ LP4 DIFF to SE enter ============
6098 13:59:04.425920 ============ LP4 DIFF to SE exit ============
6099 13:59:04.426015 [ANA_INIT] <<<<<<<<<<<<<
6100 13:59:04.429149 [Flow] Enable top DCM control >>>>>
6101 13:59:04.432493 [Flow] Enable top DCM control <<<<<
6102 13:59:04.435635 Enable DLL master slave shuffle
6103 13:59:04.442282 ==============================================================
6104 13:59:04.442363 Gating Mode config
6105 13:59:04.448772 ==============================================================
6106 13:59:04.452154 Config description:
6107 13:59:04.462186 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6108 13:59:04.468648 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6109 13:59:04.472342 SELPH_MODE 0: By rank 1: By Phase
6110 13:59:04.478642 ==============================================================
6111 13:59:04.482217 GAT_TRACK_EN = 0
6112 13:59:04.485161 RX_GATING_MODE = 2
6113 13:59:04.488459 RX_GATING_TRACK_MODE = 2
6114 13:59:04.491537 SELPH_MODE = 1
6115 13:59:04.491612 PICG_EARLY_EN = 1
6116 13:59:04.494973 VALID_LAT_VALUE = 1
6117 13:59:04.501765 ==============================================================
6118 13:59:04.505046 Enter into Gating configuration >>>>
6119 13:59:04.508064 Exit from Gating configuration <<<<
6120 13:59:04.511716 Enter into DVFS_PRE_config >>>>>
6121 13:59:04.521511 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6122 13:59:04.524764 Exit from DVFS_PRE_config <<<<<
6123 13:59:04.527795 Enter into PICG configuration >>>>
6124 13:59:04.531246 Exit from PICG configuration <<<<
6125 13:59:04.534267 [RX_INPUT] configuration >>>>>
6126 13:59:04.538099 [RX_INPUT] configuration <<<<<
6127 13:59:04.544026 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6128 13:59:04.547582 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6129 13:59:04.553843 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6130 13:59:04.560568 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6131 13:59:04.567636 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6132 13:59:04.574407 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6133 13:59:04.577804 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6134 13:59:04.580834 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6135 13:59:04.583989 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6136 13:59:04.590402 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6137 13:59:04.593709 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6138 13:59:04.597142 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6139 13:59:04.601114 ===================================
6140 13:59:04.603690 LPDDR4 DRAM CONFIGURATION
6141 13:59:04.606813 ===================================
6142 13:59:04.610605 EX_ROW_EN[0] = 0x0
6143 13:59:04.610692 EX_ROW_EN[1] = 0x0
6144 13:59:04.613570 LP4Y_EN = 0x0
6145 13:59:04.613662 WORK_FSP = 0x0
6146 13:59:04.616891 WL = 0x2
6147 13:59:04.616959 RL = 0x2
6148 13:59:04.619988 BL = 0x2
6149 13:59:04.620083 RPST = 0x0
6150 13:59:04.623470 RD_PRE = 0x0
6151 13:59:04.623536 WR_PRE = 0x1
6152 13:59:04.626686 WR_PST = 0x0
6153 13:59:04.626778 DBI_WR = 0x0
6154 13:59:04.629939 DBI_RD = 0x0
6155 13:59:04.630039 OTF = 0x1
6156 13:59:04.633264 ===================================
6157 13:59:04.639881 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6158 13:59:04.643209 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6159 13:59:04.646648 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6160 13:59:04.649604 ===================================
6161 13:59:04.653417 LPDDR4 DRAM CONFIGURATION
6162 13:59:04.656548 ===================================
6163 13:59:04.659641 EX_ROW_EN[0] = 0x10
6164 13:59:04.659740 EX_ROW_EN[1] = 0x0
6165 13:59:04.663192 LP4Y_EN = 0x0
6166 13:59:04.663260 WORK_FSP = 0x0
6167 13:59:04.665955 WL = 0x2
6168 13:59:04.666052 RL = 0x2
6169 13:59:04.669285 BL = 0x2
6170 13:59:04.669378 RPST = 0x0
6171 13:59:04.672964 RD_PRE = 0x0
6172 13:59:04.673063 WR_PRE = 0x1
6173 13:59:04.675896 WR_PST = 0x0
6174 13:59:04.675965 DBI_WR = 0x0
6175 13:59:04.679964 DBI_RD = 0x0
6176 13:59:04.680029 OTF = 0x1
6177 13:59:04.682726 ===================================
6178 13:59:04.689397 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6179 13:59:04.693957 nWR fixed to 30
6180 13:59:04.697361 [ModeRegInit_LP4] CH0 RK0
6181 13:59:04.697462 [ModeRegInit_LP4] CH0 RK1
6182 13:59:04.700744 [ModeRegInit_LP4] CH1 RK0
6183 13:59:04.704164 [ModeRegInit_LP4] CH1 RK1
6184 13:59:04.704267 match AC timing 19
6185 13:59:04.710579 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6186 13:59:04.714083 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6187 13:59:04.717020 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6188 13:59:04.723674 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6189 13:59:04.727421 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6190 13:59:04.727491 ==
6191 13:59:04.730060 Dram Type= 6, Freq= 0, CH_0, rank 0
6192 13:59:04.733651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6193 13:59:04.733748 ==
6194 13:59:04.739976 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6195 13:59:04.746669 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6196 13:59:04.750036 [CA 0] Center 36 (8~64) winsize 57
6197 13:59:04.753558 [CA 1] Center 36 (8~64) winsize 57
6198 13:59:04.756487 [CA 2] Center 36 (8~64) winsize 57
6199 13:59:04.760107 [CA 3] Center 36 (8~64) winsize 57
6200 13:59:04.763299 [CA 4] Center 36 (8~64) winsize 57
6201 13:59:04.766554 [CA 5] Center 36 (8~64) winsize 57
6202 13:59:04.766642
6203 13:59:04.770060 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6204 13:59:04.770158
6205 13:59:04.774081 [CATrainingPosCal] consider 1 rank data
6206 13:59:04.776415 u2DelayCellTimex100 = 270/100 ps
6207 13:59:04.779726 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 13:59:04.782983 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 13:59:04.786275 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 13:59:04.789794 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 13:59:04.793258 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 13:59:04.796397 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 13:59:04.796471
6214 13:59:04.802979 CA PerBit enable=1, Macro0, CA PI delay=36
6215 13:59:04.803086
6216 13:59:04.803180 [CBTSetCACLKResult] CA Dly = 36
6217 13:59:04.806125 CS Dly: 1 (0~32)
6218 13:59:04.806220 ==
6219 13:59:04.809635 Dram Type= 6, Freq= 0, CH_0, rank 1
6220 13:59:04.813015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6221 13:59:04.813090 ==
6222 13:59:04.819356 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6223 13:59:04.825938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6224 13:59:04.829553 [CA 0] Center 36 (8~64) winsize 57
6225 13:59:04.832345 [CA 1] Center 36 (8~64) winsize 57
6226 13:59:04.835765 [CA 2] Center 36 (8~64) winsize 57
6227 13:59:04.839012 [CA 3] Center 36 (8~64) winsize 57
6228 13:59:04.839110 [CA 4] Center 36 (8~64) winsize 57
6229 13:59:04.842582 [CA 5] Center 36 (8~64) winsize 57
6230 13:59:04.842651
6231 13:59:04.848957 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6232 13:59:04.849032
6233 13:59:04.852379 [CATrainingPosCal] consider 2 rank data
6234 13:59:04.855824 u2DelayCellTimex100 = 270/100 ps
6235 13:59:04.858737 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 13:59:04.862016 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 13:59:04.865726 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 13:59:04.868827 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 13:59:04.871947 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 13:59:04.875226 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 13:59:04.875300
6242 13:59:04.879081 CA PerBit enable=1, Macro0, CA PI delay=36
6243 13:59:04.879182
6244 13:59:04.882395 [CBTSetCACLKResult] CA Dly = 36
6245 13:59:04.885026 CS Dly: 1 (0~32)
6246 13:59:04.885095
6247 13:59:04.888568 ----->DramcWriteLeveling(PI) begin...
6248 13:59:04.888674 ==
6249 13:59:04.892483 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 13:59:04.895248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 13:59:04.895320 ==
6252 13:59:04.898665 Write leveling (Byte 0): 40 => 8
6253 13:59:04.901713 Write leveling (Byte 1): 40 => 8
6254 13:59:04.905221 DramcWriteLeveling(PI) end<-----
6255 13:59:04.905319
6256 13:59:04.905407 ==
6257 13:59:04.908899 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 13:59:04.911997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 13:59:04.912069 ==
6260 13:59:04.914788 [Gating] SW mode calibration
6261 13:59:04.921880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6262 13:59:04.928120 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6263 13:59:04.931764 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6264 13:59:04.938476 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6265 13:59:04.941560 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 13:59:04.944461 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 13:59:04.951655 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 13:59:04.954798 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 13:59:04.957530 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 13:59:04.964363 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 13:59:04.967763 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 13:59:04.970955 Total UI for P1: 0, mck2ui 16
6273 13:59:04.974567 best dqsien dly found for B0: ( 0, 14, 24)
6274 13:59:04.977443 Total UI for P1: 0, mck2ui 16
6275 13:59:04.980790 best dqsien dly found for B1: ( 0, 14, 24)
6276 13:59:04.984163 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6277 13:59:04.987607 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6278 13:59:04.987705
6279 13:59:04.990645 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6280 13:59:04.994399 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6281 13:59:04.997573 [Gating] SW calibration Done
6282 13:59:04.997672 ==
6283 13:59:05.000533 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 13:59:05.007013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 13:59:05.007116 ==
6286 13:59:05.007185 RX Vref Scan: 0
6287 13:59:05.007244
6288 13:59:05.010207 RX Vref 0 -> 0, step: 1
6289 13:59:05.010277
6290 13:59:05.013624 RX Delay -410 -> 252, step: 16
6291 13:59:05.019008 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6292 13:59:05.020096 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6293 13:59:05.026936 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6294 13:59:05.030175 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6295 13:59:05.033620 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6296 13:59:05.037123 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6297 13:59:05.043315 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6298 13:59:05.046540 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6299 13:59:05.050108 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6300 13:59:05.053073 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6301 13:59:05.060075 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6302 13:59:05.063331 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6303 13:59:05.066402 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6304 13:59:05.069704 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6305 13:59:05.076557 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6306 13:59:05.079655 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6307 13:59:05.079726 ==
6308 13:59:05.082813 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 13:59:05.086135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 13:59:05.086207 ==
6311 13:59:05.089566 DQS Delay:
6312 13:59:05.089664 DQS0 = 35, DQS1 = 59
6313 13:59:05.092997 DQM Delay:
6314 13:59:05.093097 DQM0 = 5, DQM1 = 17
6315 13:59:05.093188 DQ Delay:
6316 13:59:05.096406 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6317 13:59:05.099216 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6318 13:59:05.102581 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6319 13:59:05.106078 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6320 13:59:05.106152
6321 13:59:05.106213
6322 13:59:05.106271 ==
6323 13:59:05.109627 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 13:59:05.116111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 13:59:05.116184 ==
6326 13:59:05.116271
6327 13:59:05.116357
6328 13:59:05.116442 TX Vref Scan disable
6329 13:59:05.119100 == TX Byte 0 ==
6330 13:59:05.122417 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 13:59:05.126221 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 13:59:05.129398 == TX Byte 1 ==
6333 13:59:05.132418 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6334 13:59:05.136059 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6335 13:59:05.138898 ==
6336 13:59:05.138968 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 13:59:05.145360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 13:59:05.145436 ==
6339 13:59:05.145497
6340 13:59:05.145555
6341 13:59:05.148608 TX Vref Scan disable
6342 13:59:05.148708 == TX Byte 0 ==
6343 13:59:05.152184 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 13:59:05.158534 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 13:59:05.158645 == TX Byte 1 ==
6346 13:59:05.162340 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 13:59:05.168378 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 13:59:05.168480
6349 13:59:05.168574 [DATLAT]
6350 13:59:05.168661 Freq=400, CH0 RK0
6351 13:59:05.168748
6352 13:59:05.171894 DATLAT Default: 0xf
6353 13:59:05.171964 0, 0xFFFF, sum = 0
6354 13:59:05.175257 1, 0xFFFF, sum = 0
6355 13:59:05.178370 2, 0xFFFF, sum = 0
6356 13:59:05.178471 3, 0xFFFF, sum = 0
6357 13:59:05.182035 4, 0xFFFF, sum = 0
6358 13:59:05.182105 5, 0xFFFF, sum = 0
6359 13:59:05.185098 6, 0xFFFF, sum = 0
6360 13:59:05.185193 7, 0xFFFF, sum = 0
6361 13:59:05.188497 8, 0xFFFF, sum = 0
6362 13:59:05.188569 9, 0xFFFF, sum = 0
6363 13:59:05.191424 10, 0xFFFF, sum = 0
6364 13:59:05.191490 11, 0xFFFF, sum = 0
6365 13:59:05.195435 12, 0xFFFF, sum = 0
6366 13:59:05.195510 13, 0x0, sum = 1
6367 13:59:05.198219 14, 0x0, sum = 2
6368 13:59:05.198314 15, 0x0, sum = 3
6369 13:59:05.201866 16, 0x0, sum = 4
6370 13:59:05.201960 best_step = 14
6371 13:59:05.202049
6372 13:59:05.202134 ==
6373 13:59:05.204627 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 13:59:05.211788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 13:59:05.211868 ==
6376 13:59:05.211930 RX Vref Scan: 1
6377 13:59:05.211989
6378 13:59:05.214853 RX Vref 0 -> 0, step: 1
6379 13:59:05.214945
6380 13:59:05.218085 RX Delay -359 -> 252, step: 8
6381 13:59:05.218177
6382 13:59:05.221145 Set Vref, RX VrefLevel [Byte0]: 53
6383 13:59:05.224439 [Byte1]: 51
6384 13:59:05.224506
6385 13:59:05.228303 Final RX Vref Byte 0 = 53 to rank0
6386 13:59:05.231398 Final RX Vref Byte 1 = 51 to rank0
6387 13:59:05.234809 Final RX Vref Byte 0 = 53 to rank1
6388 13:59:05.238427 Final RX Vref Byte 1 = 51 to rank1==
6389 13:59:05.240910 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 13:59:05.244430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 13:59:05.247592 ==
6392 13:59:05.247686 DQS Delay:
6393 13:59:05.247775 DQS0 = 44, DQS1 = 56
6394 13:59:05.250606 DQM Delay:
6395 13:59:05.250697 DQM0 = 10, DQM1 = 12
6396 13:59:05.254134 DQ Delay:
6397 13:59:05.257547 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6398 13:59:05.257644 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6399 13:59:05.260826 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6400 13:59:05.264155 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =20
6401 13:59:05.264227
6402 13:59:05.267455
6403 13:59:05.273873 [DQSOSCAuto] RK0, (LSB)MR18= 0x9488, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6404 13:59:05.277481 CH0 RK0: MR19=C0C, MR18=9488
6405 13:59:05.283976 CH0_RK0: MR19=0xC0C, MR18=0x9488, DQSOSC=391, MR23=63, INC=386, DEC=257
6406 13:59:05.284074 ==
6407 13:59:05.287207 Dram Type= 6, Freq= 0, CH_0, rank 1
6408 13:59:05.290667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 13:59:05.290790 ==
6410 13:59:05.293706 [Gating] SW mode calibration
6411 13:59:05.300329 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6412 13:59:05.307131 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6413 13:59:05.310190 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6414 13:59:05.313235 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6415 13:59:05.320534 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6416 13:59:05.323444 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 13:59:05.326881 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 13:59:05.333054 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 13:59:05.336398 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 13:59:05.340164 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 13:59:05.346638 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 13:59:05.346718 Total UI for P1: 0, mck2ui 16
6423 13:59:05.353455 best dqsien dly found for B0: ( 0, 14, 24)
6424 13:59:05.353537 Total UI for P1: 0, mck2ui 16
6425 13:59:05.359890 best dqsien dly found for B1: ( 0, 14, 24)
6426 13:59:05.363301 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6427 13:59:05.366369 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6428 13:59:05.366450
6429 13:59:05.369743 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6430 13:59:05.372978 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6431 13:59:05.375980 [Gating] SW calibration Done
6432 13:59:05.376061 ==
6433 13:59:05.379744 Dram Type= 6, Freq= 0, CH_0, rank 1
6434 13:59:05.382662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 13:59:05.382743 ==
6436 13:59:05.386179 RX Vref Scan: 0
6437 13:59:05.386259
6438 13:59:05.386324 RX Vref 0 -> 0, step: 1
6439 13:59:05.389711
6440 13:59:05.389791 RX Delay -410 -> 252, step: 16
6441 13:59:05.396120 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6442 13:59:05.399003 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6443 13:59:05.402659 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6444 13:59:05.405818 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6445 13:59:05.412181 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6446 13:59:05.415556 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6447 13:59:05.419118 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6448 13:59:05.425567 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6449 13:59:05.428701 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6450 13:59:05.432041 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6451 13:59:05.435436 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6452 13:59:05.442180 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6453 13:59:05.445233 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6454 13:59:05.448482 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6455 13:59:05.451651 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6456 13:59:05.459109 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6457 13:59:05.459205 ==
6458 13:59:05.462223 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 13:59:05.465416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 13:59:05.465497 ==
6461 13:59:05.465561 DQS Delay:
6462 13:59:05.468625 DQS0 = 35, DQS1 = 51
6463 13:59:05.468705 DQM Delay:
6464 13:59:05.472230 DQM0 = 7, DQM1 = 10
6465 13:59:05.472311 DQ Delay:
6466 13:59:05.475348 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6467 13:59:05.478691 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6468 13:59:05.481661 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6469 13:59:05.484876 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6470 13:59:05.484957
6471 13:59:05.485021
6472 13:59:05.485080 ==
6473 13:59:05.488208 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 13:59:05.491953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 13:59:05.492034 ==
6476 13:59:05.492098
6477 13:59:05.492158
6478 13:59:05.494931 TX Vref Scan disable
6479 13:59:05.498460 == TX Byte 0 ==
6480 13:59:05.501479 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6481 13:59:05.504978 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6482 13:59:05.505080 == TX Byte 1 ==
6483 13:59:05.511236 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6484 13:59:05.514786 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6485 13:59:05.514893 ==
6486 13:59:05.517963 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 13:59:05.521146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 13:59:05.521222 ==
6489 13:59:05.521285
6490 13:59:05.524449
6491 13:59:05.524518 TX Vref Scan disable
6492 13:59:05.528166 == TX Byte 0 ==
6493 13:59:05.531228 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6494 13:59:05.534505 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6495 13:59:05.537994 == TX Byte 1 ==
6496 13:59:05.541072 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6497 13:59:05.544529 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6498 13:59:05.544604
6499 13:59:05.544669 [DATLAT]
6500 13:59:05.547641 Freq=400, CH0 RK1
6501 13:59:05.547710
6502 13:59:05.547771 DATLAT Default: 0xe
6503 13:59:05.551205 0, 0xFFFF, sum = 0
6504 13:59:05.554553 1, 0xFFFF, sum = 0
6505 13:59:05.554653 2, 0xFFFF, sum = 0
6506 13:59:05.557660 3, 0xFFFF, sum = 0
6507 13:59:05.557731 4, 0xFFFF, sum = 0
6508 13:59:05.561240 5, 0xFFFF, sum = 0
6509 13:59:05.561318 6, 0xFFFF, sum = 0
6510 13:59:05.564243 7, 0xFFFF, sum = 0
6511 13:59:05.564344 8, 0xFFFF, sum = 0
6512 13:59:05.567710 9, 0xFFFF, sum = 0
6513 13:59:05.567814 10, 0xFFFF, sum = 0
6514 13:59:05.570913 11, 0xFFFF, sum = 0
6515 13:59:05.571015 12, 0xFFFF, sum = 0
6516 13:59:05.574558 13, 0x0, sum = 1
6517 13:59:05.574658 14, 0x0, sum = 2
6518 13:59:05.577561 15, 0x0, sum = 3
6519 13:59:05.577663 16, 0x0, sum = 4
6520 13:59:05.581221 best_step = 14
6521 13:59:05.581322
6522 13:59:05.581412 ==
6523 13:59:05.584467 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 13:59:05.587390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 13:59:05.587489 ==
6526 13:59:05.590801 RX Vref Scan: 0
6527 13:59:05.590897
6528 13:59:05.591006 RX Vref 0 -> 0, step: 1
6529 13:59:05.591118
6530 13:59:05.593939 RX Delay -343 -> 252, step: 8
6531 13:59:05.601598 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6532 13:59:05.605076 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6533 13:59:05.608456 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6534 13:59:05.614656 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6535 13:59:05.617863 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6536 13:59:05.621577 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6537 13:59:05.624828 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6538 13:59:05.631134 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6539 13:59:05.634728 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6540 13:59:05.638153 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6541 13:59:05.641204 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6542 13:59:05.648344 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6543 13:59:05.651376 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6544 13:59:05.654730 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6545 13:59:05.658334 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6546 13:59:05.664439 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6547 13:59:05.664549 ==
6548 13:59:05.667779 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 13:59:05.670967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 13:59:05.671066 ==
6551 13:59:05.671157 DQS Delay:
6552 13:59:05.674717 DQS0 = 44, DQS1 = 60
6553 13:59:05.674815 DQM Delay:
6554 13:59:05.677761 DQM0 = 9, DQM1 = 14
6555 13:59:05.677858 DQ Delay:
6556 13:59:05.681150 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6557 13:59:05.684525 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6558 13:59:05.687677 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6559 13:59:05.691109 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =20
6560 13:59:05.691216
6561 13:59:05.691306
6562 13:59:05.697399 [DQSOSCAuto] RK1, (LSB)MR18= 0x8680, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6563 13:59:05.700623 CH0 RK1: MR19=C0C, MR18=8680
6564 13:59:05.707679 CH0_RK1: MR19=0xC0C, MR18=0x8680, DQSOSC=393, MR23=63, INC=382, DEC=254
6565 13:59:05.710904 [RxdqsGatingPostProcess] freq 400
6566 13:59:05.717438 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6567 13:59:05.720397 best DQS0 dly(2T, 0.5T) = (0, 10)
6568 13:59:05.724231 best DQS1 dly(2T, 0.5T) = (0, 10)
6569 13:59:05.727670 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6570 13:59:05.730427 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6571 13:59:05.730507 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 13:59:05.734129 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 13:59:05.737085 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 13:59:05.740548 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 13:59:05.743486 Pre-setting of DQS Precalculation
6576 13:59:05.750530 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6577 13:59:05.750611 ==
6578 13:59:05.753680 Dram Type= 6, Freq= 0, CH_1, rank 0
6579 13:59:05.756556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 13:59:05.756637 ==
6581 13:59:05.763332 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6582 13:59:05.770235 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6583 13:59:05.773383 [CA 0] Center 36 (8~64) winsize 57
6584 13:59:05.776454 [CA 1] Center 36 (8~64) winsize 57
6585 13:59:05.776535 [CA 2] Center 36 (8~64) winsize 57
6586 13:59:05.780227 [CA 3] Center 36 (8~64) winsize 57
6587 13:59:05.783381 [CA 4] Center 36 (8~64) winsize 57
6588 13:59:05.786885 [CA 5] Center 36 (8~64) winsize 57
6589 13:59:05.786990
6590 13:59:05.789586 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6591 13:59:05.793255
6592 13:59:05.796241 [CATrainingPosCal] consider 1 rank data
6593 13:59:05.796340 u2DelayCellTimex100 = 270/100 ps
6594 13:59:05.802971 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 13:59:05.806399 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 13:59:05.810053 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 13:59:05.813057 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 13:59:05.816029 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 13:59:05.819548 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 13:59:05.819629
6601 13:59:05.822586 CA PerBit enable=1, Macro0, CA PI delay=36
6602 13:59:05.822765
6603 13:59:05.826243 [CBTSetCACLKResult] CA Dly = 36
6604 13:59:05.829350 CS Dly: 1 (0~32)
6605 13:59:05.829431 ==
6606 13:59:05.832425 Dram Type= 6, Freq= 0, CH_1, rank 1
6607 13:59:05.836133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 13:59:05.836214 ==
6609 13:59:05.842728 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6610 13:59:05.848978 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6611 13:59:05.849058 [CA 0] Center 36 (8~64) winsize 57
6612 13:59:05.852495 [CA 1] Center 36 (8~64) winsize 57
6613 13:59:05.856011 [CA 2] Center 36 (8~64) winsize 57
6614 13:59:05.859030 [CA 3] Center 36 (8~64) winsize 57
6615 13:59:05.862070 [CA 4] Center 36 (8~64) winsize 57
6616 13:59:05.865347 [CA 5] Center 36 (8~64) winsize 57
6617 13:59:05.865429
6618 13:59:05.869253 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6619 13:59:05.869334
6620 13:59:05.875397 [CATrainingPosCal] consider 2 rank data
6621 13:59:05.875478 u2DelayCellTimex100 = 270/100 ps
6622 13:59:05.878719 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 13:59:05.885237 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 13:59:05.888501 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 13:59:05.891874 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 13:59:05.894924 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 13:59:05.898709 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 13:59:05.898788
6629 13:59:05.901506 CA PerBit enable=1, Macro0, CA PI delay=36
6630 13:59:05.901578
6631 13:59:05.905073 [CBTSetCACLKResult] CA Dly = 36
6632 13:59:05.908136 CS Dly: 1 (0~32)
6633 13:59:05.908237
6634 13:59:05.911786 ----->DramcWriteLeveling(PI) begin...
6635 13:59:05.911887 ==
6636 13:59:05.914692 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 13:59:05.918406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 13:59:05.918485 ==
6639 13:59:05.921346 Write leveling (Byte 0): 40 => 8
6640 13:59:05.924957 Write leveling (Byte 1): 40 => 8
6641 13:59:05.927997 DramcWriteLeveling(PI) end<-----
6642 13:59:05.928071
6643 13:59:05.928133 ==
6644 13:59:05.931106 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 13:59:05.934630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 13:59:05.934732 ==
6647 13:59:05.937937 [Gating] SW mode calibration
6648 13:59:05.944798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6649 13:59:05.951162 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6650 13:59:05.954456 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6651 13:59:05.957993 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6652 13:59:05.964294 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 13:59:05.967521 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 13:59:05.970885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 13:59:05.978058 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 13:59:05.980896 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 13:59:05.983970 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 13:59:05.990968 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 13:59:05.994058 Total UI for P1: 0, mck2ui 16
6660 13:59:05.997466 best dqsien dly found for B0: ( 0, 14, 24)
6661 13:59:05.997565 Total UI for P1: 0, mck2ui 16
6662 13:59:06.003783 best dqsien dly found for B1: ( 0, 14, 24)
6663 13:59:06.006937 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6664 13:59:06.010384 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6665 13:59:06.010482
6666 13:59:06.014234 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6667 13:59:06.016851 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6668 13:59:06.020532 [Gating] SW calibration Done
6669 13:59:06.020610 ==
6670 13:59:06.023548 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 13:59:06.026800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 13:59:06.026896 ==
6673 13:59:06.030657 RX Vref Scan: 0
6674 13:59:06.030759
6675 13:59:06.033721 RX Vref 0 -> 0, step: 1
6676 13:59:06.033822
6677 13:59:06.033914 RX Delay -410 -> 252, step: 16
6678 13:59:06.040499 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6679 13:59:06.043760 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6680 13:59:06.046897 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6681 13:59:06.053790 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6682 13:59:06.056591 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6683 13:59:06.060193 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6684 13:59:06.063140 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6685 13:59:06.069852 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6686 13:59:06.073175 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6687 13:59:06.076683 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6688 13:59:06.079896 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6689 13:59:06.086351 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6690 13:59:06.089928 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6691 13:59:06.092928 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6692 13:59:06.096333 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6693 13:59:06.102661 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6694 13:59:06.102765 ==
6695 13:59:06.105828 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 13:59:06.109187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 13:59:06.109286 ==
6698 13:59:06.112332 DQS Delay:
6699 13:59:06.112429 DQS0 = 35, DQS1 = 51
6700 13:59:06.112518 DQM Delay:
6701 13:59:06.115951 DQM0 = 6, DQM1 = 13
6702 13:59:06.116059 DQ Delay:
6703 13:59:06.119638 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6704 13:59:06.122274 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6705 13:59:06.126151 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6706 13:59:06.129398 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6707 13:59:06.129500
6708 13:59:06.129604
6709 13:59:06.129694 ==
6710 13:59:06.132211 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 13:59:06.135443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 13:59:06.139029 ==
6713 13:59:06.139134
6714 13:59:06.139200
6715 13:59:06.139298 TX Vref Scan disable
6716 13:59:06.142447 == TX Byte 0 ==
6717 13:59:06.145374 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 13:59:06.149320 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 13:59:06.152010 == TX Byte 1 ==
6720 13:59:06.155733 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6721 13:59:06.158708 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6722 13:59:06.158789 ==
6723 13:59:06.162352 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 13:59:06.165695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 13:59:06.168437 ==
6726 13:59:06.168517
6727 13:59:06.168581
6728 13:59:06.168640 TX Vref Scan disable
6729 13:59:06.172207 == TX Byte 0 ==
6730 13:59:06.175289 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 13:59:06.178451 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 13:59:06.181864 == TX Byte 1 ==
6733 13:59:06.185534 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 13:59:06.188520 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 13:59:06.188601
6736 13:59:06.191566 [DATLAT]
6737 13:59:06.191646 Freq=400, CH1 RK0
6738 13:59:06.191711
6739 13:59:06.195034 DATLAT Default: 0xf
6740 13:59:06.195153 0, 0xFFFF, sum = 0
6741 13:59:06.198358 1, 0xFFFF, sum = 0
6742 13:59:06.198440 2, 0xFFFF, sum = 0
6743 13:59:06.201595 3, 0xFFFF, sum = 0
6744 13:59:06.201677 4, 0xFFFF, sum = 0
6745 13:59:06.205320 5, 0xFFFF, sum = 0
6746 13:59:06.205402 6, 0xFFFF, sum = 0
6747 13:59:06.208155 7, 0xFFFF, sum = 0
6748 13:59:06.208237 8, 0xFFFF, sum = 0
6749 13:59:06.211609 9, 0xFFFF, sum = 0
6750 13:59:06.215017 10, 0xFFFF, sum = 0
6751 13:59:06.215138 11, 0xFFFF, sum = 0
6752 13:59:06.218448 12, 0xFFFF, sum = 0
6753 13:59:06.218530 13, 0x0, sum = 1
6754 13:59:06.221871 14, 0x0, sum = 2
6755 13:59:06.221953 15, 0x0, sum = 3
6756 13:59:06.222020 16, 0x0, sum = 4
6757 13:59:06.225110 best_step = 14
6758 13:59:06.225190
6759 13:59:06.225254 ==
6760 13:59:06.228265 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 13:59:06.231999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 13:59:06.232081 ==
6763 13:59:06.234524 RX Vref Scan: 1
6764 13:59:06.234604
6765 13:59:06.237859 RX Vref 0 -> 0, step: 1
6766 13:59:06.237939
6767 13:59:06.238003 RX Delay -343 -> 252, step: 8
6768 13:59:06.238062
6769 13:59:06.241323 Set Vref, RX VrefLevel [Byte0]: 51
6770 13:59:06.244660 [Byte1]: 53
6771 13:59:06.249877
6772 13:59:06.249956 Final RX Vref Byte 0 = 51 to rank0
6773 13:59:06.253442 Final RX Vref Byte 1 = 53 to rank0
6774 13:59:06.256456 Final RX Vref Byte 0 = 51 to rank1
6775 13:59:06.260449 Final RX Vref Byte 1 = 53 to rank1==
6776 13:59:06.263054 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 13:59:06.270125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 13:59:06.270207 ==
6779 13:59:06.270272 DQS Delay:
6780 13:59:06.273144 DQS0 = 44, DQS1 = 52
6781 13:59:06.273225 DQM Delay:
6782 13:59:06.273289 DQM0 = 9, DQM1 = 11
6783 13:59:06.275990 DQ Delay:
6784 13:59:06.279509 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6785 13:59:06.282820 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6786 13:59:06.282900 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6787 13:59:06.285650 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =16
6788 13:59:06.289142
6789 13:59:06.289269
6790 13:59:06.295934 [DQSOSCAuto] RK0, (LSB)MR18= 0x7399, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6791 13:59:06.298785 CH1 RK0: MR19=C0C, MR18=7399
6792 13:59:06.305934 CH1_RK0: MR19=0xC0C, MR18=0x7399, DQSOSC=390, MR23=63, INC=388, DEC=258
6793 13:59:06.306016 ==
6794 13:59:06.309251 Dram Type= 6, Freq= 0, CH_1, rank 1
6795 13:59:06.312404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 13:59:06.312485 ==
6797 13:59:06.315922 [Gating] SW mode calibration
6798 13:59:06.322598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6799 13:59:06.328743 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6800 13:59:06.332023 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6801 13:59:06.335757 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6802 13:59:06.341806 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6803 13:59:06.345991 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 13:59:06.348679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 13:59:06.355713 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 13:59:06.358382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 13:59:06.361915 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 13:59:06.368381 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 13:59:06.368463 Total UI for P1: 0, mck2ui 16
6810 13:59:06.374716 best dqsien dly found for B0: ( 0, 14, 24)
6811 13:59:06.374798 Total UI for P1: 0, mck2ui 16
6812 13:59:06.381654 best dqsien dly found for B1: ( 0, 14, 24)
6813 13:59:06.384624 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6814 13:59:06.388035 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6815 13:59:06.388128
6816 13:59:06.391692 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6817 13:59:06.394582 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6818 13:59:06.397862 [Gating] SW calibration Done
6819 13:59:06.397944 ==
6820 13:59:06.401231 Dram Type= 6, Freq= 0, CH_1, rank 1
6821 13:59:06.405048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 13:59:06.405129 ==
6823 13:59:06.407632 RX Vref Scan: 0
6824 13:59:06.407713
6825 13:59:06.410858 RX Vref 0 -> 0, step: 1
6826 13:59:06.410938
6827 13:59:06.411002 RX Delay -410 -> 252, step: 16
6828 13:59:06.417717 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6829 13:59:06.420834 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6830 13:59:06.424471 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6831 13:59:06.430830 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6832 13:59:06.434419 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6833 13:59:06.438194 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6834 13:59:06.440664 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6835 13:59:06.447389 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6836 13:59:06.450982 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6837 13:59:06.454589 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6838 13:59:06.457422 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6839 13:59:06.464027 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6840 13:59:06.467064 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6841 13:59:06.471094 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6842 13:59:06.473748 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6843 13:59:06.480268 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6844 13:59:06.480370 ==
6845 13:59:06.483541 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 13:59:06.486995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 13:59:06.487105 ==
6848 13:59:06.487187 DQS Delay:
6849 13:59:06.490761 DQS0 = 43, DQS1 = 51
6850 13:59:06.490841 DQM Delay:
6851 13:59:06.493747 DQM0 = 10, DQM1 = 14
6852 13:59:06.493827 DQ Delay:
6853 13:59:06.496644 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6854 13:59:06.500233 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6855 13:59:06.503040 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6856 13:59:06.506491 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6857 13:59:06.506572
6858 13:59:06.506636
6859 13:59:06.506697 ==
6860 13:59:06.510598 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 13:59:06.513033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 13:59:06.516720 ==
6863 13:59:06.516842
6864 13:59:06.516936
6865 13:59:06.516995 TX Vref Scan disable
6866 13:59:06.520234 == TX Byte 0 ==
6867 13:59:06.523035 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6868 13:59:06.526283 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6869 13:59:06.529541 == TX Byte 1 ==
6870 13:59:06.533334 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6871 13:59:06.536357 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6872 13:59:06.536438 ==
6873 13:59:06.539662 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 13:59:06.546338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 13:59:06.546419 ==
6876 13:59:06.546484
6877 13:59:06.546544
6878 13:59:06.546601 TX Vref Scan disable
6879 13:59:06.549420 == TX Byte 0 ==
6880 13:59:06.552731 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6881 13:59:06.555966 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6882 13:59:06.559607 == TX Byte 1 ==
6883 13:59:06.562540 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6884 13:59:06.565960 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6885 13:59:06.566041
6886 13:59:06.569447 [DATLAT]
6887 13:59:06.569527 Freq=400, CH1 RK1
6888 13:59:06.569641
6889 13:59:06.572832 DATLAT Default: 0xe
6890 13:59:06.572914 0, 0xFFFF, sum = 0
6891 13:59:06.576195 1, 0xFFFF, sum = 0
6892 13:59:06.576304 2, 0xFFFF, sum = 0
6893 13:59:06.579242 3, 0xFFFF, sum = 0
6894 13:59:06.579325 4, 0xFFFF, sum = 0
6895 13:59:06.582501 5, 0xFFFF, sum = 0
6896 13:59:06.582584 6, 0xFFFF, sum = 0
6897 13:59:06.585861 7, 0xFFFF, sum = 0
6898 13:59:06.585944 8, 0xFFFF, sum = 0
6899 13:59:06.589404 9, 0xFFFF, sum = 0
6900 13:59:06.589498 10, 0xFFFF, sum = 0
6901 13:59:06.592291 11, 0xFFFF, sum = 0
6902 13:59:06.595835 12, 0xFFFF, sum = 0
6903 13:59:06.595932 13, 0x0, sum = 1
6904 13:59:06.595998 14, 0x0, sum = 2
6905 13:59:06.598933 15, 0x0, sum = 3
6906 13:59:06.599033 16, 0x0, sum = 4
6907 13:59:06.602301 best_step = 14
6908 13:59:06.602397
6909 13:59:06.602485 ==
6910 13:59:06.605398 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 13:59:06.609013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 13:59:06.609096 ==
6913 13:59:06.612241 RX Vref Scan: 0
6914 13:59:06.612312
6915 13:59:06.612388 RX Vref 0 -> 0, step: 1
6916 13:59:06.615373
6917 13:59:06.615442 RX Delay -343 -> 252, step: 8
6918 13:59:06.623602 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6919 13:59:06.627166 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6920 13:59:06.630441 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6921 13:59:06.637395 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6922 13:59:06.640035 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6923 13:59:06.643609 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6924 13:59:06.647454 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6925 13:59:06.653854 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6926 13:59:06.656825 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6927 13:59:06.659854 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6928 13:59:06.663415 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6929 13:59:06.670147 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6930 13:59:06.673338 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6931 13:59:06.676956 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6932 13:59:06.679695 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6933 13:59:06.686211 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6934 13:59:06.686288 ==
6935 13:59:06.690152 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 13:59:06.692946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 13:59:06.693031 ==
6938 13:59:06.693097 DQS Delay:
6939 13:59:06.696731 DQS0 = 48, DQS1 = 52
6940 13:59:06.696815 DQM Delay:
6941 13:59:06.699599 DQM0 = 11, DQM1 = 10
6942 13:59:06.699682 DQ Delay:
6943 13:59:06.702946 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6944 13:59:06.706089 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6945 13:59:06.709631 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6946 13:59:06.712887 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6947 13:59:06.712974
6948 13:59:06.713059
6949 13:59:06.722568 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ab0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6950 13:59:06.722654 CH1 RK1: MR19=C0C, MR18=7AB0
6951 13:59:06.729398 CH1_RK1: MR19=0xC0C, MR18=0x7AB0, DQSOSC=387, MR23=63, INC=394, DEC=262
6952 13:59:06.732700 [RxdqsGatingPostProcess] freq 400
6953 13:59:06.739448 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6954 13:59:06.742334 best DQS0 dly(2T, 0.5T) = (0, 10)
6955 13:59:06.745761 best DQS1 dly(2T, 0.5T) = (0, 10)
6956 13:59:06.749318 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6957 13:59:06.752113 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6958 13:59:06.755868 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 13:59:06.759276 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 13:59:06.762089 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 13:59:06.765484 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 13:59:06.765566 Pre-setting of DQS Precalculation
6963 13:59:06.771894 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6964 13:59:06.778687 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6965 13:59:06.785079 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6966 13:59:06.785161
6967 13:59:06.785225
6968 13:59:06.788534 [Calibration Summary] 800 Mbps
6969 13:59:06.791808 CH 0, Rank 0
6970 13:59:06.791904 SW Impedance : PASS
6971 13:59:06.795523 DUTY Scan : NO K
6972 13:59:06.798346 ZQ Calibration : PASS
6973 13:59:06.798429 Jitter Meter : NO K
6974 13:59:06.802020 CBT Training : PASS
6975 13:59:06.804811 Write leveling : PASS
6976 13:59:06.804892 RX DQS gating : PASS
6977 13:59:06.808286 RX DQ/DQS(RDDQC) : PASS
6978 13:59:06.811680 TX DQ/DQS : PASS
6979 13:59:06.811762 RX DATLAT : PASS
6980 13:59:06.815223 RX DQ/DQS(Engine): PASS
6981 13:59:06.815304 TX OE : NO K
6982 13:59:06.818450 All Pass.
6983 13:59:06.818531
6984 13:59:06.818596 CH 0, Rank 1
6985 13:59:06.821554 SW Impedance : PASS
6986 13:59:06.821682 DUTY Scan : NO K
6987 13:59:06.825096 ZQ Calibration : PASS
6988 13:59:06.828310 Jitter Meter : NO K
6989 13:59:06.828391 CBT Training : PASS
6990 13:59:06.831272 Write leveling : NO K
6991 13:59:06.834973 RX DQS gating : PASS
6992 13:59:06.835134 RX DQ/DQS(RDDQC) : PASS
6993 13:59:06.838390 TX DQ/DQS : PASS
6994 13:59:06.841399 RX DATLAT : PASS
6995 13:59:06.841472 RX DQ/DQS(Engine): PASS
6996 13:59:06.844798 TX OE : NO K
6997 13:59:06.844880 All Pass.
6998 13:59:06.844945
6999 13:59:06.847814 CH 1, Rank 0
7000 13:59:06.847924 SW Impedance : PASS
7001 13:59:06.851231 DUTY Scan : NO K
7002 13:59:06.854559 ZQ Calibration : PASS
7003 13:59:06.854661 Jitter Meter : NO K
7004 13:59:06.857681 CBT Training : PASS
7005 13:59:06.861019 Write leveling : PASS
7006 13:59:06.861146 RX DQS gating : PASS
7007 13:59:06.864518 RX DQ/DQS(RDDQC) : PASS
7008 13:59:06.867530 TX DQ/DQS : PASS
7009 13:59:06.867631 RX DATLAT : PASS
7010 13:59:06.871068 RX DQ/DQS(Engine): PASS
7011 13:59:06.874555 TX OE : NO K
7012 13:59:06.874657 All Pass.
7013 13:59:06.874749
7014 13:59:06.874843 CH 1, Rank 1
7015 13:59:06.877845 SW Impedance : PASS
7016 13:59:06.881190 DUTY Scan : NO K
7017 13:59:06.881291 ZQ Calibration : PASS
7018 13:59:06.883939 Jitter Meter : NO K
7019 13:59:06.887370 CBT Training : PASS
7020 13:59:06.887476 Write leveling : NO K
7021 13:59:06.890428 RX DQS gating : PASS
7022 13:59:06.893845 RX DQ/DQS(RDDQC) : PASS
7023 13:59:06.893961 TX DQ/DQS : PASS
7024 13:59:06.897092 RX DATLAT : PASS
7025 13:59:06.897176 RX DQ/DQS(Engine): PASS
7026 13:59:06.900700 TX OE : NO K
7027 13:59:06.900802 All Pass.
7028 13:59:06.900894
7029 13:59:06.903648 DramC Write-DBI off
7030 13:59:06.907224 PER_BANK_REFRESH: Hybrid Mode
7031 13:59:06.907328 TX_TRACKING: ON
7032 13:59:06.917293 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7033 13:59:06.920542 [FAST_K] Save calibration result to emmc
7034 13:59:06.923477 dramc_set_vcore_voltage set vcore to 725000
7035 13:59:06.926776 Read voltage for 1600, 0
7036 13:59:06.926849 Vio18 = 0
7037 13:59:06.930455 Vcore = 725000
7038 13:59:06.930551 Vdram = 0
7039 13:59:06.930639 Vddq = 0
7040 13:59:06.930729 Vmddr = 0
7041 13:59:06.936563 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7042 13:59:06.943540 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7043 13:59:06.943641 MEM_TYPE=3, freq_sel=13
7044 13:59:06.946573 sv_algorithm_assistance_LP4_3733
7045 13:59:06.950039 ============ PULL DRAM RESETB DOWN ============
7046 13:59:06.956478 ========== PULL DRAM RESETB DOWN end =========
7047 13:59:06.959777 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7048 13:59:06.963040 ===================================
7049 13:59:06.966482 LPDDR4 DRAM CONFIGURATION
7050 13:59:06.969580 ===================================
7051 13:59:06.969677 EX_ROW_EN[0] = 0x0
7052 13:59:06.973063 EX_ROW_EN[1] = 0x0
7053 13:59:06.976276 LP4Y_EN = 0x0
7054 13:59:06.976376 WORK_FSP = 0x1
7055 13:59:06.979977 WL = 0x5
7056 13:59:06.980052 RL = 0x5
7057 13:59:06.982969 BL = 0x2
7058 13:59:06.983069 RPST = 0x0
7059 13:59:06.986479 RD_PRE = 0x0
7060 13:59:06.986551 WR_PRE = 0x1
7061 13:59:06.989490 WR_PST = 0x1
7062 13:59:06.989560 DBI_WR = 0x0
7063 13:59:06.993060 DBI_RD = 0x0
7064 13:59:06.993132 OTF = 0x1
7065 13:59:06.996481 ===================================
7066 13:59:06.999438 ===================================
7067 13:59:07.002678 ANA top config
7068 13:59:07.006177 ===================================
7069 13:59:07.006254 DLL_ASYNC_EN = 0
7070 13:59:07.009465 ALL_SLAVE_EN = 0
7071 13:59:07.012775 NEW_RANK_MODE = 1
7072 13:59:07.016040 DLL_IDLE_MODE = 1
7073 13:59:07.019280 LP45_APHY_COMB_EN = 1
7074 13:59:07.019383 TX_ODT_DIS = 0
7075 13:59:07.022521 NEW_8X_MODE = 1
7076 13:59:07.026411 ===================================
7077 13:59:07.029406 ===================================
7078 13:59:07.032816 data_rate = 3200
7079 13:59:07.036040 CKR = 1
7080 13:59:07.039172 DQ_P2S_RATIO = 8
7081 13:59:07.042635 ===================================
7082 13:59:07.045937 CA_P2S_RATIO = 8
7083 13:59:07.046035 DQ_CA_OPEN = 0
7084 13:59:07.048893 DQ_SEMI_OPEN = 0
7085 13:59:07.052418 CA_SEMI_OPEN = 0
7086 13:59:07.055443 CA_FULL_RATE = 0
7087 13:59:07.058818 DQ_CKDIV4_EN = 0
7088 13:59:07.062182 CA_CKDIV4_EN = 0
7089 13:59:07.062254 CA_PREDIV_EN = 0
7090 13:59:07.065443 PH8_DLY = 12
7091 13:59:07.069110 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7092 13:59:07.072136 DQ_AAMCK_DIV = 4
7093 13:59:07.075529 CA_AAMCK_DIV = 4
7094 13:59:07.078592 CA_ADMCK_DIV = 4
7095 13:59:07.078692 DQ_TRACK_CA_EN = 0
7096 13:59:07.081771 CA_PICK = 1600
7097 13:59:07.085780 CA_MCKIO = 1600
7098 13:59:07.088537 MCKIO_SEMI = 0
7099 13:59:07.091740 PLL_FREQ = 3068
7100 13:59:07.095037 DQ_UI_PI_RATIO = 32
7101 13:59:07.098610 CA_UI_PI_RATIO = 0
7102 13:59:07.101485 ===================================
7103 13:59:07.104991 ===================================
7104 13:59:07.105092 memory_type:LPDDR4
7105 13:59:07.108615 GP_NUM : 10
7106 13:59:07.111722 SRAM_EN : 1
7107 13:59:07.111817 MD32_EN : 0
7108 13:59:07.114907 ===================================
7109 13:59:07.118286 [ANA_INIT] >>>>>>>>>>>>>>
7110 13:59:07.121617 <<<<<< [CONFIGURE PHASE]: ANA_TX
7111 13:59:07.124854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7112 13:59:07.128666 ===================================
7113 13:59:07.131285 data_rate = 3200,PCW = 0X7600
7114 13:59:07.134512 ===================================
7115 13:59:07.137891 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7116 13:59:07.141511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7117 13:59:07.148224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7118 13:59:07.154633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7119 13:59:07.158090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7120 13:59:07.161375 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7121 13:59:07.161485 [ANA_INIT] flow start
7122 13:59:07.164524 [ANA_INIT] PLL >>>>>>>>
7123 13:59:07.168061 [ANA_INIT] PLL <<<<<<<<
7124 13:59:07.168165 [ANA_INIT] MIDPI >>>>>>>>
7125 13:59:07.171402 [ANA_INIT] MIDPI <<<<<<<<
7126 13:59:07.174274 [ANA_INIT] DLL >>>>>>>>
7127 13:59:07.174365 [ANA_INIT] DLL <<<<<<<<
7128 13:59:07.177769 [ANA_INIT] flow end
7129 13:59:07.181154 ============ LP4 DIFF to SE enter ============
7130 13:59:07.184587 ============ LP4 DIFF to SE exit ============
7131 13:59:07.187663 [ANA_INIT] <<<<<<<<<<<<<
7132 13:59:07.190913 [Flow] Enable top DCM control >>>>>
7133 13:59:07.194408 [Flow] Enable top DCM control <<<<<
7134 13:59:07.197755 Enable DLL master slave shuffle
7135 13:59:07.204060 ==============================================================
7136 13:59:07.204160 Gating Mode config
7137 13:59:07.210509 ==============================================================
7138 13:59:07.214008 Config description:
7139 13:59:07.220872 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7140 13:59:07.227291 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7141 13:59:07.233860 SELPH_MODE 0: By rank 1: By Phase
7142 13:59:07.240378 ==============================================================
7143 13:59:07.240460 GAT_TRACK_EN = 1
7144 13:59:07.243909 RX_GATING_MODE = 2
7145 13:59:07.247411 RX_GATING_TRACK_MODE = 2
7146 13:59:07.250237 SELPH_MODE = 1
7147 13:59:07.253586 PICG_EARLY_EN = 1
7148 13:59:07.257412 VALID_LAT_VALUE = 1
7149 13:59:07.263634 ==============================================================
7150 13:59:07.266892 Enter into Gating configuration >>>>
7151 13:59:07.270174 Exit from Gating configuration <<<<
7152 13:59:07.273664 Enter into DVFS_PRE_config >>>>>
7153 13:59:07.283204 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7154 13:59:07.286811 Exit from DVFS_PRE_config <<<<<
7155 13:59:07.290057 Enter into PICG configuration >>>>
7156 13:59:07.293357 Exit from PICG configuration <<<<
7157 13:59:07.296577 [RX_INPUT] configuration >>>>>
7158 13:59:07.299825 [RX_INPUT] configuration <<<<<
7159 13:59:07.303376 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7160 13:59:07.309805 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7161 13:59:07.316126 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7162 13:59:07.323322 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7163 13:59:07.326399 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7164 13:59:07.332665 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7165 13:59:07.335920 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7166 13:59:07.342650 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7167 13:59:07.346500 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7168 13:59:07.349732 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7169 13:59:07.352567 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7170 13:59:07.359455 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7171 13:59:07.362517 ===================================
7172 13:59:07.366247 LPDDR4 DRAM CONFIGURATION
7173 13:59:07.369335 ===================================
7174 13:59:07.369417 EX_ROW_EN[0] = 0x0
7175 13:59:07.372684 EX_ROW_EN[1] = 0x0
7176 13:59:07.372766 LP4Y_EN = 0x0
7177 13:59:07.375632 WORK_FSP = 0x1
7178 13:59:07.375712 WL = 0x5
7179 13:59:07.379373 RL = 0x5
7180 13:59:07.379455 BL = 0x2
7181 13:59:07.382393 RPST = 0x0
7182 13:59:07.382473 RD_PRE = 0x0
7183 13:59:07.386150 WR_PRE = 0x1
7184 13:59:07.386232 WR_PST = 0x1
7185 13:59:07.388977 DBI_WR = 0x0
7186 13:59:07.389059 DBI_RD = 0x0
7187 13:59:07.392281 OTF = 0x1
7188 13:59:07.395907 ===================================
7189 13:59:07.399004 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7190 13:59:07.402004 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7191 13:59:07.408693 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7192 13:59:07.412093 ===================================
7193 13:59:07.415538 LPDDR4 DRAM CONFIGURATION
7194 13:59:07.418507 ===================================
7195 13:59:07.418588 EX_ROW_EN[0] = 0x10
7196 13:59:07.421974 EX_ROW_EN[1] = 0x0
7197 13:59:07.422082 LP4Y_EN = 0x0
7198 13:59:07.425559 WORK_FSP = 0x1
7199 13:59:07.425641 WL = 0x5
7200 13:59:07.428525 RL = 0x5
7201 13:59:07.428607 BL = 0x2
7202 13:59:07.431642 RPST = 0x0
7203 13:59:07.431724 RD_PRE = 0x0
7204 13:59:07.434977 WR_PRE = 0x1
7205 13:59:07.435060 WR_PST = 0x1
7206 13:59:07.438835 DBI_WR = 0x0
7207 13:59:07.438929 DBI_RD = 0x0
7208 13:59:07.441965 OTF = 0x1
7209 13:59:07.444914 ===================================
7210 13:59:07.451559 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7211 13:59:07.451677 ==
7212 13:59:07.455040 Dram Type= 6, Freq= 0, CH_0, rank 0
7213 13:59:07.458808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7214 13:59:07.458890 ==
7215 13:59:07.461455 [Duty_Offset_Calibration]
7216 13:59:07.461539 B0:2 B1:0 CA:4
7217 13:59:07.461605
7218 13:59:07.464799 [DutyScan_Calibration_Flow] k_type=0
7219 13:59:07.475509
7220 13:59:07.475591 ==CLK 0==
7221 13:59:07.478685 Final CLK duty delay cell = -4
7222 13:59:07.482012 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7223 13:59:07.485329 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7224 13:59:07.488851 [-4] AVG Duty = 4922%(X100)
7225 13:59:07.488934
7226 13:59:07.491603 CH0 CLK Duty spec in!! Max-Min= 218%
7227 13:59:07.495030 [DutyScan_Calibration_Flow] ====Done====
7228 13:59:07.495136
7229 13:59:07.498422 [DutyScan_Calibration_Flow] k_type=1
7230 13:59:07.514482
7231 13:59:07.514564 ==DQS 0 ==
7232 13:59:07.517916 Final DQS duty delay cell = -4
7233 13:59:07.521402 [-4] MAX Duty = 4938%(X100), DQS PI = 48
7234 13:59:07.524729 [-4] MIN Duty = 4782%(X100), DQS PI = 2
7235 13:59:07.527805 [-4] AVG Duty = 4860%(X100)
7236 13:59:07.527933
7237 13:59:07.527998 ==DQS 1 ==
7238 13:59:07.531998 Final DQS duty delay cell = 0
7239 13:59:07.534444 [0] MAX Duty = 5156%(X100), DQS PI = 0
7240 13:59:07.537875 [0] MIN Duty = 4969%(X100), DQS PI = 10
7241 13:59:07.541142 [0] AVG Duty = 5062%(X100)
7242 13:59:07.541224
7243 13:59:07.544541 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7244 13:59:07.544648
7245 13:59:07.547468 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7246 13:59:07.550713 [DutyScan_Calibration_Flow] ====Done====
7247 13:59:07.550828
7248 13:59:07.554227 [DutyScan_Calibration_Flow] k_type=3
7249 13:59:07.572214
7250 13:59:07.572293 ==DQM 0 ==
7251 13:59:07.575479 Final DQM duty delay cell = 0
7252 13:59:07.578754 [0] MAX Duty = 5124%(X100), DQS PI = 20
7253 13:59:07.582780 [0] MIN Duty = 4875%(X100), DQS PI = 54
7254 13:59:07.585578 [0] AVG Duty = 4999%(X100)
7255 13:59:07.585680
7256 13:59:07.585778 ==DQM 1 ==
7257 13:59:07.588435 Final DQM duty delay cell = 0
7258 13:59:07.591702 [0] MAX Duty = 4969%(X100), DQS PI = 0
7259 13:59:07.595116 [0] MIN Duty = 4844%(X100), DQS PI = 16
7260 13:59:07.598404 [0] AVG Duty = 4906%(X100)
7261 13:59:07.598509
7262 13:59:07.602057 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7263 13:59:07.602157
7264 13:59:07.605165 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7265 13:59:07.608602 [DutyScan_Calibration_Flow] ====Done====
7266 13:59:07.608700
7267 13:59:07.611674 [DutyScan_Calibration_Flow] k_type=2
7268 13:59:07.629467
7269 13:59:07.629550 ==DQ 0 ==
7270 13:59:07.632912 Final DQ duty delay cell = 0
7271 13:59:07.635829 [0] MAX Duty = 5156%(X100), DQS PI = 22
7272 13:59:07.639294 [0] MIN Duty = 4938%(X100), DQS PI = 14
7273 13:59:07.639374 [0] AVG Duty = 5047%(X100)
7274 13:59:07.642634
7275 13:59:07.642744 ==DQ 1 ==
7276 13:59:07.646009 Final DQ duty delay cell = 0
7277 13:59:07.649143 [0] MAX Duty = 5187%(X100), DQS PI = 2
7278 13:59:07.652531 [0] MIN Duty = 4907%(X100), DQS PI = 32
7279 13:59:07.652611 [0] AVG Duty = 5047%(X100)
7280 13:59:07.655751
7281 13:59:07.659015 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7282 13:59:07.659141
7283 13:59:07.662358 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7284 13:59:07.666039 [DutyScan_Calibration_Flow] ====Done====
7285 13:59:07.666119 ==
7286 13:59:07.669050 Dram Type= 6, Freq= 0, CH_1, rank 0
7287 13:59:07.672361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7288 13:59:07.672440 ==
7289 13:59:07.675373 [Duty_Offset_Calibration]
7290 13:59:07.675488 B0:0 B1:-1 CA:3
7291 13:59:07.675587
7292 13:59:07.678533 [DutyScan_Calibration_Flow] k_type=0
7293 13:59:07.688543
7294 13:59:07.688646 ==CLK 0==
7295 13:59:07.692217 Final CLK duty delay cell = -4
7296 13:59:07.695331 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7297 13:59:07.698700 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7298 13:59:07.701720 [-4] AVG Duty = 4937%(X100)
7299 13:59:07.701820
7300 13:59:07.705247 CH1 CLK Duty spec in!! Max-Min= 125%
7301 13:59:07.708262 [DutyScan_Calibration_Flow] ====Done====
7302 13:59:07.708338
7303 13:59:07.711927 [DutyScan_Calibration_Flow] k_type=1
7304 13:59:07.728144
7305 13:59:07.728225 ==DQS 0 ==
7306 13:59:07.731054 Final DQS duty delay cell = 0
7307 13:59:07.735018 [0] MAX Duty = 5250%(X100), DQS PI = 28
7308 13:59:07.738051 [0] MIN Duty = 4907%(X100), DQS PI = 56
7309 13:59:07.741319 [0] AVG Duty = 5078%(X100)
7310 13:59:07.741428
7311 13:59:07.741521 ==DQS 1 ==
7312 13:59:07.744854 Final DQS duty delay cell = -4
7313 13:59:07.747567 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7314 13:59:07.751000 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7315 13:59:07.754584 [-4] AVG Duty = 4906%(X100)
7316 13:59:07.754683
7317 13:59:07.757854 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7318 13:59:07.757954
7319 13:59:07.761075 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7320 13:59:07.764493 [DutyScan_Calibration_Flow] ====Done====
7321 13:59:07.764596
7322 13:59:07.767647 [DutyScan_Calibration_Flow] k_type=3
7323 13:59:07.785037
7324 13:59:07.785142 ==DQM 0 ==
7325 13:59:07.788268 Final DQM duty delay cell = 0
7326 13:59:07.792051 [0] MAX Duty = 5062%(X100), DQS PI = 30
7327 13:59:07.795032 [0] MIN Duty = 4782%(X100), DQS PI = 40
7328 13:59:07.798521 [0] AVG Duty = 4922%(X100)
7329 13:59:07.798630
7330 13:59:07.798725 ==DQM 1 ==
7331 13:59:07.801979 Final DQM duty delay cell = 0
7332 13:59:07.805498 [0] MAX Duty = 5000%(X100), DQS PI = 30
7333 13:59:07.807900 [0] MIN Duty = 4813%(X100), DQS PI = 12
7334 13:59:07.811900 [0] AVG Duty = 4906%(X100)
7335 13:59:07.812003
7336 13:59:07.814668 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7337 13:59:07.814747
7338 13:59:07.817925 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7339 13:59:07.821166 [DutyScan_Calibration_Flow] ====Done====
7340 13:59:07.821265
7341 13:59:07.824479 [DutyScan_Calibration_Flow] k_type=2
7342 13:59:07.841112
7343 13:59:07.841228 ==DQ 0 ==
7344 13:59:07.844516 Final DQ duty delay cell = -4
7345 13:59:07.847717 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7346 13:59:07.851229 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7347 13:59:07.854615 [-4] AVG Duty = 4891%(X100)
7348 13:59:07.854714
7349 13:59:07.854813 ==DQ 1 ==
7350 13:59:07.858084 Final DQ duty delay cell = 0
7351 13:59:07.861431 [0] MAX Duty = 5062%(X100), DQS PI = 32
7352 13:59:07.864537 [0] MIN Duty = 4875%(X100), DQS PI = 0
7353 13:59:07.867839 [0] AVG Duty = 4968%(X100)
7354 13:59:07.867934
7355 13:59:07.871011 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7356 13:59:07.871134
7357 13:59:07.874536 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7358 13:59:07.878072 [DutyScan_Calibration_Flow] ====Done====
7359 13:59:07.881152 nWR fixed to 30
7360 13:59:07.884385 [ModeRegInit_LP4] CH0 RK0
7361 13:59:07.884455 [ModeRegInit_LP4] CH0 RK1
7362 13:59:07.887652 [ModeRegInit_LP4] CH1 RK0
7363 13:59:07.891014 [ModeRegInit_LP4] CH1 RK1
7364 13:59:07.891136 match AC timing 5
7365 13:59:07.897942 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7366 13:59:07.901094 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7367 13:59:07.904593 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7368 13:59:07.910890 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7369 13:59:07.914093 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7370 13:59:07.914197 [MiockJmeterHQA]
7371 13:59:07.914291
7372 13:59:07.917247 [DramcMiockJmeter] u1RxGatingPI = 0
7373 13:59:07.920815 0 : 4252, 4026
7374 13:59:07.920924 4 : 4252, 4027
7375 13:59:07.923638 8 : 4368, 4140
7376 13:59:07.923737 12 : 4368, 4140
7377 13:59:07.927333 16 : 4257, 4029
7378 13:59:07.927409 20 : 4260, 4029
7379 13:59:07.927472 24 : 4253, 4026
7380 13:59:07.930377 28 : 4253, 4026
7381 13:59:07.930474 32 : 4252, 4027
7382 13:59:07.933794 36 : 4254, 4029
7383 13:59:07.933896 40 : 4363, 4138
7384 13:59:07.936902 44 : 4252, 4027
7385 13:59:07.937006 48 : 4252, 4027
7386 13:59:07.940447 52 : 4252, 4027
7387 13:59:07.940517 56 : 4255, 4029
7388 13:59:07.940581 60 : 4252, 4027
7389 13:59:07.943405 64 : 4363, 4140
7390 13:59:07.943472 68 : 4361, 4137
7391 13:59:07.946889 72 : 4250, 4027
7392 13:59:07.946993 76 : 4252, 4030
7393 13:59:07.950209 80 : 4250, 4026
7394 13:59:07.950301 84 : 4250, 4027
7395 13:59:07.953546 88 : 4252, 4029
7396 13:59:07.953650 92 : 4361, 4137
7397 13:59:07.956470 96 : 4250, 3270
7398 13:59:07.956567 100 : 4250, 0
7399 13:59:07.956670 104 : 4249, 0
7400 13:59:07.960029 108 : 4250, 0
7401 13:59:07.960135 112 : 4252, 0
7402 13:59:07.960226 116 : 4250, 0
7403 13:59:07.963495 120 : 4250, 0
7404 13:59:07.963596 124 : 4250, 0
7405 13:59:07.966976 128 : 4253, 0
7406 13:59:07.967109 132 : 4360, 0
7407 13:59:07.967216 136 : 4250, 0
7408 13:59:07.970428 140 : 4361, 0
7409 13:59:07.970531 144 : 4250, 0
7410 13:59:07.973205 148 : 4361, 0
7411 13:59:07.973301 152 : 4250, 0
7412 13:59:07.973391 156 : 4250, 0
7413 13:59:07.976425 160 : 4249, 0
7414 13:59:07.976524 164 : 4250, 0
7415 13:59:07.979703 168 : 4250, 0
7416 13:59:07.979802 172 : 4251, 0
7417 13:59:07.979901 176 : 4250, 0
7418 13:59:07.982959 180 : 4253, 0
7419 13:59:07.983060 184 : 4250, 0
7420 13:59:07.986284 188 : 4250, 0
7421 13:59:07.986385 192 : 4363, 0
7422 13:59:07.986476 196 : 4250, 0
7423 13:59:07.989584 200 : 4361, 0
7424 13:59:07.989684 204 : 4250, 0
7425 13:59:07.993596 208 : 4250, 0
7426 13:59:07.993697 212 : 4250, 0
7427 13:59:07.993796 216 : 4250, 0
7428 13:59:07.996307 220 : 4253, 190
7429 13:59:07.996405 224 : 4252, 3933
7430 13:59:07.999302 228 : 4250, 4027
7431 13:59:07.999377 232 : 4250, 4027
7432 13:59:08.003376 236 : 4252, 4029
7433 13:59:08.003450 240 : 4250, 4027
7434 13:59:08.005918 244 : 4250, 4027
7435 13:59:08.006012 248 : 4361, 4138
7436 13:59:08.009567 252 : 4250, 4027
7437 13:59:08.009666 256 : 4250, 4027
7438 13:59:08.009756 260 : 4360, 4138
7439 13:59:08.012499 264 : 4250, 4027
7440 13:59:08.012570 268 : 4249, 4027
7441 13:59:08.016250 272 : 4363, 4140
7442 13:59:08.016318 276 : 4250, 4027
7443 13:59:08.019606 280 : 4250, 4027
7444 13:59:08.019700 284 : 4249, 4027
7445 13:59:08.022746 288 : 4252, 4029
7446 13:59:08.022841 292 : 4250, 4027
7447 13:59:08.025876 296 : 4250, 4027
7448 13:59:08.025979 300 : 4361, 4138
7449 13:59:08.029226 304 : 4250, 4027
7450 13:59:08.029295 308 : 4250, 4026
7451 13:59:08.032941 312 : 4360, 4138
7452 13:59:08.033042 316 : 4250, 4027
7453 13:59:08.033136 320 : 4250, 4027
7454 13:59:08.035934 324 : 4363, 4140
7455 13:59:08.036008 328 : 4250, 4027
7456 13:59:08.039500 332 : 4250, 4021
7457 13:59:08.039574 336 : 4249, 2229
7458 13:59:08.042461 340 : 4252, 59
7459 13:59:08.042558
7460 13:59:08.045794 MIOCK jitter meter ch=0
7461 13:59:08.045888
7462 13:59:08.045976 1T = (340-100) = 240 dly cells
7463 13:59:08.052371 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7464 13:59:08.052447 ==
7465 13:59:08.055776 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 13:59:08.059364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7467 13:59:08.059463 ==
7468 13:59:08.065827 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7469 13:59:08.068679 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7470 13:59:08.075363 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7471 13:59:08.081925 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7472 13:59:08.089271 [CA 0] Center 43 (13~74) winsize 62
7473 13:59:08.092487 [CA 1] Center 42 (12~73) winsize 62
7474 13:59:08.096235 [CA 2] Center 37 (8~67) winsize 60
7475 13:59:08.099190 [CA 3] Center 37 (8~67) winsize 60
7476 13:59:08.102382 [CA 4] Center 36 (6~66) winsize 61
7477 13:59:08.105832 [CA 5] Center 35 (5~66) winsize 62
7478 13:59:08.105929
7479 13:59:08.109179 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7480 13:59:08.109279
7481 13:59:08.115514 [CATrainingPosCal] consider 1 rank data
7482 13:59:08.115600 u2DelayCellTimex100 = 271/100 ps
7483 13:59:08.122147 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7484 13:59:08.125467 CA1 delay=42 (12~73),Diff = 7 PI (25 cell)
7485 13:59:08.128695 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7486 13:59:08.132228 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7487 13:59:08.135343 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7488 13:59:08.138818 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7489 13:59:08.138900
7490 13:59:08.141769 CA PerBit enable=1, Macro0, CA PI delay=35
7491 13:59:08.141851
7492 13:59:08.145541 [CBTSetCACLKResult] CA Dly = 35
7493 13:59:08.148712 CS Dly: 11 (0~42)
7494 13:59:08.152089 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7495 13:59:08.154988 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7496 13:59:08.155071 ==
7497 13:59:08.158330 Dram Type= 6, Freq= 0, CH_0, rank 1
7498 13:59:08.165202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7499 13:59:08.165285 ==
7500 13:59:08.168056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7501 13:59:08.174706 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7502 13:59:08.177997 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7503 13:59:08.184923 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7504 13:59:08.192580 [CA 0] Center 44 (14~75) winsize 62
7505 13:59:08.195799 [CA 1] Center 44 (14~74) winsize 61
7506 13:59:08.199240 [CA 2] Center 39 (9~69) winsize 61
7507 13:59:08.202563 [CA 3] Center 39 (10~68) winsize 59
7508 13:59:08.205805 [CA 4] Center 37 (7~67) winsize 61
7509 13:59:08.209193 [CA 5] Center 36 (7~66) winsize 60
7510 13:59:08.209290
7511 13:59:08.212508 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7512 13:59:08.212616
7513 13:59:08.219252 [CATrainingPosCal] consider 2 rank data
7514 13:59:08.219339 u2DelayCellTimex100 = 271/100 ps
7515 13:59:08.225932 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7516 13:59:08.228767 CA1 delay=43 (14~73),Diff = 7 PI (25 cell)
7517 13:59:08.232207 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7518 13:59:08.236073 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7519 13:59:08.238893 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7520 13:59:08.242408 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7521 13:59:08.242505
7522 13:59:08.245365 CA PerBit enable=1, Macro0, CA PI delay=36
7523 13:59:08.245463
7524 13:59:08.248972 [CBTSetCACLKResult] CA Dly = 36
7525 13:59:08.252329 CS Dly: 11 (0~43)
7526 13:59:08.255367 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7527 13:59:08.258536 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7528 13:59:08.258684
7529 13:59:08.261957 ----->DramcWriteLeveling(PI) begin...
7530 13:59:08.262059 ==
7531 13:59:08.265390 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 13:59:08.271665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 13:59:08.271746 ==
7534 13:59:08.275633 Write leveling (Byte 0): 35 => 35
7535 13:59:08.278950 Write leveling (Byte 1): 29 => 29
7536 13:59:08.279051 DramcWriteLeveling(PI) end<-----
7537 13:59:08.281829
7538 13:59:08.281925 ==
7539 13:59:08.284850 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 13:59:08.288575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 13:59:08.288681 ==
7542 13:59:08.291426 [Gating] SW mode calibration
7543 13:59:08.298370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7544 13:59:08.304797 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7545 13:59:08.307884 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7546 13:59:08.311318 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 13:59:08.317929 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7548 13:59:08.321088 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7549 13:59:08.324613 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7550 13:59:08.330962 1 4 20 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7551 13:59:08.334280 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7552 13:59:08.337386 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7553 13:59:08.344179 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 13:59:08.347108 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 13:59:08.350305 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7556 13:59:08.357331 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7557 13:59:08.360372 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7558 13:59:08.363731 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
7559 13:59:08.370330 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7560 13:59:08.373820 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 13:59:08.377025 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 13:59:08.383450 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 13:59:08.386670 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7564 13:59:08.390078 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7565 13:59:08.396716 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7566 13:59:08.400794 1 6 20 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
7567 13:59:08.403421 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 13:59:08.410226 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 13:59:08.413379 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 13:59:08.416865 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 13:59:08.420162 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 13:59:08.426777 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7573 13:59:08.429864 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7574 13:59:08.433400 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7575 13:59:08.440306 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 13:59:08.443201 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 13:59:08.450168 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 13:59:08.452922 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 13:59:08.456537 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 13:59:08.459484 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 13:59:08.466393 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 13:59:08.469482 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 13:59:08.472724 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 13:59:08.479493 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 13:59:08.482971 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 13:59:08.486093 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 13:59:08.492707 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7588 13:59:08.496090 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7589 13:59:08.499263 Total UI for P1: 0, mck2ui 16
7590 13:59:08.502708 best dqsien dly found for B0: ( 1, 9, 8)
7591 13:59:08.506204 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7592 13:59:08.512598 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7593 13:59:08.515442 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7594 13:59:08.519249 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 13:59:08.522423 Total UI for P1: 0, mck2ui 16
7596 13:59:08.525889 best dqsien dly found for B1: ( 1, 9, 22)
7597 13:59:08.529008 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7598 13:59:08.535491 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7599 13:59:08.535567
7600 13:59:08.539138 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7601 13:59:08.542589 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7602 13:59:08.545613 [Gating] SW calibration Done
7603 13:59:08.545715 ==
7604 13:59:08.548642 Dram Type= 6, Freq= 0, CH_0, rank 0
7605 13:59:08.551938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 13:59:08.552036 ==
7607 13:59:08.554995 RX Vref Scan: 0
7608 13:59:08.555123
7609 13:59:08.555220 RX Vref 0 -> 0, step: 1
7610 13:59:08.555331
7611 13:59:08.558948 RX Delay 0 -> 252, step: 8
7612 13:59:08.562020 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7613 13:59:08.568475 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7614 13:59:08.571608 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7615 13:59:08.575019 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7616 13:59:08.578926 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7617 13:59:08.581910 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7618 13:59:08.584838 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7619 13:59:08.591773 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7620 13:59:08.594974 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7621 13:59:08.598012 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7622 13:59:08.601694 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7623 13:59:08.604953 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7624 13:59:08.611302 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7625 13:59:08.614605 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7626 13:59:08.618029 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7627 13:59:08.621294 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7628 13:59:08.625055 ==
7629 13:59:08.628042 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 13:59:08.631472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 13:59:08.631557 ==
7632 13:59:08.631624 DQS Delay:
7633 13:59:08.634907 DQS0 = 0, DQS1 = 0
7634 13:59:08.634989 DQM Delay:
7635 13:59:08.637606 DQM0 = 130, DQM1 = 125
7636 13:59:08.637688 DQ Delay:
7637 13:59:08.641168 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7638 13:59:08.644305 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7639 13:59:08.647804 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7640 13:59:08.650923 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7641 13:59:08.651006
7642 13:59:08.651078
7643 13:59:08.651142 ==
7644 13:59:08.654242 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 13:59:08.660655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 13:59:08.660737 ==
7647 13:59:08.660802
7648 13:59:08.660861
7649 13:59:08.664149 TX Vref Scan disable
7650 13:59:08.664240 == TX Byte 0 ==
7651 13:59:08.667200 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7652 13:59:08.674191 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7653 13:59:08.674272 == TX Byte 1 ==
7654 13:59:08.677493 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7655 13:59:08.683827 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7656 13:59:08.683938 ==
7657 13:59:08.687082 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 13:59:08.690060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 13:59:08.690140 ==
7660 13:59:08.704224
7661 13:59:08.707106 TX Vref early break, caculate TX vref
7662 13:59:08.710907 TX Vref=16, minBit 1, minWin=20, winSum=358
7663 13:59:08.714056 TX Vref=18, minBit 7, minWin=21, winSum=370
7664 13:59:08.717303 TX Vref=20, minBit 2, minWin=22, winSum=377
7665 13:59:08.720470 TX Vref=22, minBit 1, minWin=22, winSum=390
7666 13:59:08.724593 TX Vref=24, minBit 1, minWin=23, winSum=397
7667 13:59:08.730149 TX Vref=26, minBit 0, minWin=25, winSum=411
7668 13:59:08.733590 TX Vref=28, minBit 1, minWin=23, winSum=410
7669 13:59:08.737347 TX Vref=30, minBit 4, minWin=23, winSum=403
7670 13:59:08.740139 TX Vref=32, minBit 0, minWin=23, winSum=398
7671 13:59:08.744287 TX Vref=34, minBit 0, minWin=23, winSum=388
7672 13:59:08.749939 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 26
7673 13:59:08.750015
7674 13:59:08.753364 Final TX Range 0 Vref 26
7675 13:59:08.753467
7676 13:59:08.753556 ==
7677 13:59:08.756877 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 13:59:08.760143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 13:59:08.760221 ==
7680 13:59:08.760290
7681 13:59:08.760349
7682 13:59:08.763468 TX Vref Scan disable
7683 13:59:08.770053 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7684 13:59:08.770128 == TX Byte 0 ==
7685 13:59:08.773178 u2DelayCellOfst[0]=14 cells (4 PI)
7686 13:59:08.776682 u2DelayCellOfst[1]=14 cells (4 PI)
7687 13:59:08.779947 u2DelayCellOfst[2]=10 cells (3 PI)
7688 13:59:08.783058 u2DelayCellOfst[3]=10 cells (3 PI)
7689 13:59:08.786419 u2DelayCellOfst[4]=10 cells (3 PI)
7690 13:59:08.789711 u2DelayCellOfst[5]=0 cells (0 PI)
7691 13:59:08.793192 u2DelayCellOfst[6]=18 cells (5 PI)
7692 13:59:08.796369 u2DelayCellOfst[7]=18 cells (5 PI)
7693 13:59:08.799525 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7694 13:59:08.802802 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7695 13:59:08.806251 == TX Byte 1 ==
7696 13:59:08.809465 u2DelayCellOfst[8]=0 cells (0 PI)
7697 13:59:08.813018 u2DelayCellOfst[9]=0 cells (0 PI)
7698 13:59:08.815878 u2DelayCellOfst[10]=7 cells (2 PI)
7699 13:59:08.815960 u2DelayCellOfst[11]=0 cells (0 PI)
7700 13:59:08.819260 u2DelayCellOfst[12]=10 cells (3 PI)
7701 13:59:08.823146 u2DelayCellOfst[13]=10 cells (3 PI)
7702 13:59:08.825722 u2DelayCellOfst[14]=14 cells (4 PI)
7703 13:59:08.829307 u2DelayCellOfst[15]=10 cells (3 PI)
7704 13:59:08.835950 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7705 13:59:08.838889 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7706 13:59:08.838970 DramC Write-DBI on
7707 13:59:08.842556 ==
7708 13:59:08.845654 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 13:59:08.848964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 13:59:08.849046 ==
7711 13:59:08.849111
7712 13:59:08.849171
7713 13:59:08.852474 TX Vref Scan disable
7714 13:59:08.852556 == TX Byte 0 ==
7715 13:59:08.859231 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7716 13:59:08.859313 == TX Byte 1 ==
7717 13:59:08.862402 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7718 13:59:08.865804 DramC Write-DBI off
7719 13:59:08.865886
7720 13:59:08.865951 [DATLAT]
7721 13:59:08.869156 Freq=1600, CH0 RK0
7722 13:59:08.869238
7723 13:59:08.869303 DATLAT Default: 0xf
7724 13:59:08.872138 0, 0xFFFF, sum = 0
7725 13:59:08.872222 1, 0xFFFF, sum = 0
7726 13:59:08.875234 2, 0xFFFF, sum = 0
7727 13:59:08.875312 3, 0xFFFF, sum = 0
7728 13:59:08.878923 4, 0xFFFF, sum = 0
7729 13:59:08.879007 5, 0xFFFF, sum = 0
7730 13:59:08.882178 6, 0xFFFF, sum = 0
7731 13:59:08.885751 7, 0xFFFF, sum = 0
7732 13:59:08.885834 8, 0xFFFF, sum = 0
7733 13:59:08.888747 9, 0xFFFF, sum = 0
7734 13:59:08.888830 10, 0xFFFF, sum = 0
7735 13:59:08.891837 11, 0xFFFF, sum = 0
7736 13:59:08.891920 12, 0xFFFF, sum = 0
7737 13:59:08.895436 13, 0xFFFF, sum = 0
7738 13:59:08.895518 14, 0x0, sum = 1
7739 13:59:08.898745 15, 0x0, sum = 2
7740 13:59:08.898827 16, 0x0, sum = 3
7741 13:59:08.901912 17, 0x0, sum = 4
7742 13:59:08.901994 best_step = 15
7743 13:59:08.902060
7744 13:59:08.902120 ==
7745 13:59:08.905341 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 13:59:08.908573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 13:59:08.911710 ==
7748 13:59:08.911791 RX Vref Scan: 1
7749 13:59:08.911855
7750 13:59:08.915321 Set Vref Range= 24 -> 127
7751 13:59:08.915404
7752 13:59:08.918113 RX Vref 24 -> 127, step: 1
7753 13:59:08.918195
7754 13:59:08.918259 RX Delay 11 -> 252, step: 4
7755 13:59:08.918319
7756 13:59:08.921831 Set Vref, RX VrefLevel [Byte0]: 24
7757 13:59:08.924534 [Byte1]: 24
7758 13:59:08.928692
7759 13:59:08.928773 Set Vref, RX VrefLevel [Byte0]: 25
7760 13:59:08.932091 [Byte1]: 25
7761 13:59:08.936147
7762 13:59:08.936255 Set Vref, RX VrefLevel [Byte0]: 26
7763 13:59:08.939756 [Byte1]: 26
7764 13:59:08.944092
7765 13:59:08.944172 Set Vref, RX VrefLevel [Byte0]: 27
7766 13:59:08.947470 [Byte1]: 27
7767 13:59:08.952332
7768 13:59:08.952413 Set Vref, RX VrefLevel [Byte0]: 28
7769 13:59:08.955294 [Byte1]: 28
7770 13:59:08.959355
7771 13:59:08.959437 Set Vref, RX VrefLevel [Byte0]: 29
7772 13:59:08.962499 [Byte1]: 29
7773 13:59:08.967717
7774 13:59:08.967798 Set Vref, RX VrefLevel [Byte0]: 30
7775 13:59:08.970441 [Byte1]: 30
7776 13:59:08.974921
7777 13:59:08.975001 Set Vref, RX VrefLevel [Byte0]: 31
7778 13:59:08.977778 [Byte1]: 31
7779 13:59:08.982052
7780 13:59:08.982133 Set Vref, RX VrefLevel [Byte0]: 32
7781 13:59:08.985680 [Byte1]: 32
7782 13:59:08.989738
7783 13:59:08.989822 Set Vref, RX VrefLevel [Byte0]: 33
7784 13:59:08.993347 [Byte1]: 33
7785 13:59:08.997130
7786 13:59:08.997211 Set Vref, RX VrefLevel [Byte0]: 34
7787 13:59:09.000496 [Byte1]: 34
7788 13:59:09.005000
7789 13:59:09.005081 Set Vref, RX VrefLevel [Byte0]: 35
7790 13:59:09.008397 [Byte1]: 35
7791 13:59:09.012917
7792 13:59:09.012997 Set Vref, RX VrefLevel [Byte0]: 36
7793 13:59:09.016505 [Byte1]: 36
7794 13:59:09.020129
7795 13:59:09.020210 Set Vref, RX VrefLevel [Byte0]: 37
7796 13:59:09.023752 [Byte1]: 37
7797 13:59:09.027635
7798 13:59:09.027716 Set Vref, RX VrefLevel [Byte0]: 38
7799 13:59:09.030947 [Byte1]: 38
7800 13:59:09.035191
7801 13:59:09.035272 Set Vref, RX VrefLevel [Byte0]: 39
7802 13:59:09.038840 [Byte1]: 39
7803 13:59:09.043256
7804 13:59:09.043336 Set Vref, RX VrefLevel [Byte0]: 40
7805 13:59:09.046187 [Byte1]: 40
7806 13:59:09.050762
7807 13:59:09.050843 Set Vref, RX VrefLevel [Byte0]: 41
7808 13:59:09.053660 [Byte1]: 41
7809 13:59:09.058225
7810 13:59:09.058305 Set Vref, RX VrefLevel [Byte0]: 42
7811 13:59:09.061381 [Byte1]: 42
7812 13:59:09.065784
7813 13:59:09.065871 Set Vref, RX VrefLevel [Byte0]: 43
7814 13:59:09.068921 [Byte1]: 43
7815 13:59:09.073578
7816 13:59:09.073672 Set Vref, RX VrefLevel [Byte0]: 44
7817 13:59:09.076880 [Byte1]: 44
7818 13:59:09.080941
7819 13:59:09.081052 Set Vref, RX VrefLevel [Byte0]: 45
7820 13:59:09.084508 [Byte1]: 45
7821 13:59:09.088701
7822 13:59:09.088822 Set Vref, RX VrefLevel [Byte0]: 46
7823 13:59:09.091791 [Byte1]: 46
7824 13:59:09.096274
7825 13:59:09.096424 Set Vref, RX VrefLevel [Byte0]: 47
7826 13:59:09.099388 [Byte1]: 47
7827 13:59:09.104020
7828 13:59:09.104101 Set Vref, RX VrefLevel [Byte0]: 48
7829 13:59:09.106898 [Byte1]: 48
7830 13:59:09.111628
7831 13:59:09.111710 Set Vref, RX VrefLevel [Byte0]: 49
7832 13:59:09.114900 [Byte1]: 49
7833 13:59:09.119287
7834 13:59:09.119368 Set Vref, RX VrefLevel [Byte0]: 50
7835 13:59:09.122490 [Byte1]: 50
7836 13:59:09.126621
7837 13:59:09.126703 Set Vref, RX VrefLevel [Byte0]: 51
7838 13:59:09.130039 [Byte1]: 51
7839 13:59:09.134394
7840 13:59:09.134475 Set Vref, RX VrefLevel [Byte0]: 52
7841 13:59:09.137511 [Byte1]: 52
7842 13:59:09.141847
7843 13:59:09.141928 Set Vref, RX VrefLevel [Byte0]: 53
7844 13:59:09.145228 [Byte1]: 53
7845 13:59:09.149569
7846 13:59:09.149664 Set Vref, RX VrefLevel [Byte0]: 54
7847 13:59:09.152816 [Byte1]: 54
7848 13:59:09.157351
7849 13:59:09.157432 Set Vref, RX VrefLevel [Byte0]: 55
7850 13:59:09.160644 [Byte1]: 55
7851 13:59:09.164686
7852 13:59:09.164768 Set Vref, RX VrefLevel [Byte0]: 56
7853 13:59:09.167863 [Byte1]: 56
7854 13:59:09.172519
7855 13:59:09.172603 Set Vref, RX VrefLevel [Byte0]: 57
7856 13:59:09.175974 [Byte1]: 57
7857 13:59:09.179902
7858 13:59:09.179982 Set Vref, RX VrefLevel [Byte0]: 58
7859 13:59:09.183239 [Byte1]: 58
7860 13:59:09.187600
7861 13:59:09.187682 Set Vref, RX VrefLevel [Byte0]: 59
7862 13:59:09.190944 [Byte1]: 59
7863 13:59:09.195035
7864 13:59:09.195159 Set Vref, RX VrefLevel [Byte0]: 60
7865 13:59:09.198536 [Byte1]: 60
7866 13:59:09.202646
7867 13:59:09.202727 Set Vref, RX VrefLevel [Byte0]: 61
7868 13:59:09.206437 [Byte1]: 61
7869 13:59:09.210303
7870 13:59:09.210384 Set Vref, RX VrefLevel [Byte0]: 62
7871 13:59:09.213538 [Byte1]: 62
7872 13:59:09.218108
7873 13:59:09.218189 Set Vref, RX VrefLevel [Byte0]: 63
7874 13:59:09.221069 [Byte1]: 63
7875 13:59:09.225672
7876 13:59:09.225753 Set Vref, RX VrefLevel [Byte0]: 64
7877 13:59:09.228919 [Byte1]: 64
7878 13:59:09.233338
7879 13:59:09.233419 Set Vref, RX VrefLevel [Byte0]: 65
7880 13:59:09.236837 [Byte1]: 65
7881 13:59:09.240677
7882 13:59:09.240757 Set Vref, RX VrefLevel [Byte0]: 66
7883 13:59:09.244308 [Byte1]: 66
7884 13:59:09.248589
7885 13:59:09.248673 Set Vref, RX VrefLevel [Byte0]: 67
7886 13:59:09.251645 [Byte1]: 67
7887 13:59:09.256100
7888 13:59:09.256170 Set Vref, RX VrefLevel [Byte0]: 68
7889 13:59:09.259631 [Byte1]: 68
7890 13:59:09.263528
7891 13:59:09.263608 Set Vref, RX VrefLevel [Byte0]: 69
7892 13:59:09.267220 [Byte1]: 69
7893 13:59:09.271803
7894 13:59:09.271879 Set Vref, RX VrefLevel [Byte0]: 70
7895 13:59:09.274767 [Byte1]: 70
7896 13:59:09.278999
7897 13:59:09.279070 Set Vref, RX VrefLevel [Byte0]: 71
7898 13:59:09.282119 [Byte1]: 71
7899 13:59:09.286725
7900 13:59:09.286792 Set Vref, RX VrefLevel [Byte0]: 72
7901 13:59:09.289739 [Byte1]: 72
7902 13:59:09.293959
7903 13:59:09.294029 Set Vref, RX VrefLevel [Byte0]: 73
7904 13:59:09.297803 [Byte1]: 73
7905 13:59:09.301614
7906 13:59:09.301691 Set Vref, RX VrefLevel [Byte0]: 74
7907 13:59:09.304983 [Byte1]: 74
7908 13:59:09.309613
7909 13:59:09.309692 Set Vref, RX VrefLevel [Byte0]: 75
7910 13:59:09.312792 [Byte1]: 75
7911 13:59:09.316818
7912 13:59:09.316890 Set Vref, RX VrefLevel [Byte0]: 76
7913 13:59:09.320128 [Byte1]: 76
7914 13:59:09.325147
7915 13:59:09.325217 Final RX Vref Byte 0 = 57 to rank0
7916 13:59:09.327744 Final RX Vref Byte 1 = 64 to rank0
7917 13:59:09.331433 Final RX Vref Byte 0 = 57 to rank1
7918 13:59:09.334420 Final RX Vref Byte 1 = 64 to rank1==
7919 13:59:09.338244 Dram Type= 6, Freq= 0, CH_0, rank 0
7920 13:59:09.344841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7921 13:59:09.344932 ==
7922 13:59:09.344999 DQS Delay:
7923 13:59:09.347696 DQS0 = 0, DQS1 = 0
7924 13:59:09.347769 DQM Delay:
7925 13:59:09.347834 DQM0 = 128, DQM1 = 123
7926 13:59:09.350856 DQ Delay:
7927 13:59:09.354213 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7928 13:59:09.357255 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7929 13:59:09.361099 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =120
7930 13:59:09.364107 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =128
7931 13:59:09.364186
7932 13:59:09.364249
7933 13:59:09.364308
7934 13:59:09.367276 [DramC_TX_OE_Calibration] TA2
7935 13:59:09.370908 Original DQ_B0 (3 6) =30, OEN = 27
7936 13:59:09.374093 Original DQ_B1 (3 6) =30, OEN = 27
7937 13:59:09.377051 24, 0x0, End_B0=24 End_B1=24
7938 13:59:09.380551 25, 0x0, End_B0=25 End_B1=25
7939 13:59:09.380625 26, 0x0, End_B0=26 End_B1=26
7940 13:59:09.383578 27, 0x0, End_B0=27 End_B1=27
7941 13:59:09.387020 28, 0x0, End_B0=28 End_B1=28
7942 13:59:09.390188 29, 0x0, End_B0=29 End_B1=29
7943 13:59:09.390263 30, 0x0, End_B0=30 End_B1=30
7944 13:59:09.393938 31, 0x4141, End_B0=30 End_B1=30
7945 13:59:09.397092 Byte0 end_step=30 best_step=27
7946 13:59:09.400318 Byte1 end_step=30 best_step=27
7947 13:59:09.403545 Byte0 TX OE(2T, 0.5T) = (3, 3)
7948 13:59:09.406971 Byte1 TX OE(2T, 0.5T) = (3, 3)
7949 13:59:09.407045
7950 13:59:09.407113
7951 13:59:09.413180 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7952 13:59:09.417122 CH0 RK0: MR19=303, MR18=1916
7953 13:59:09.423070 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7954 13:59:09.423180
7955 13:59:09.426776 ----->DramcWriteLeveling(PI) begin...
7956 13:59:09.426847 ==
7957 13:59:09.429911 Dram Type= 6, Freq= 0, CH_0, rank 1
7958 13:59:09.433060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 13:59:09.433134 ==
7960 13:59:09.436952 Write leveling (Byte 0): 34 => 34
7961 13:59:09.439924 Write leveling (Byte 1): 28 => 28
7962 13:59:09.443298 DramcWriteLeveling(PI) end<-----
7963 13:59:09.443374
7964 13:59:09.443438 ==
7965 13:59:09.446945 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 13:59:09.453360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 13:59:09.453436 ==
7968 13:59:09.453500 [Gating] SW mode calibration
7969 13:59:09.462820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7970 13:59:09.466374 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7971 13:59:09.469876 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 13:59:09.475899 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 13:59:09.479390 1 4 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7974 13:59:09.482450 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7975 13:59:09.489950 1 4 16 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
7976 13:59:09.492695 1 4 20 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7977 13:59:09.495917 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7978 13:59:09.503062 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7979 13:59:09.506007 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7980 13:59:09.509089 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7981 13:59:09.516166 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7982 13:59:09.519731 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 1)
7983 13:59:09.522317 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7984 13:59:09.529127 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7985 13:59:09.532533 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 13:59:09.535781 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 13:59:09.542511 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 13:59:09.545959 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7989 13:59:09.548711 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7990 13:59:09.555900 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7991 13:59:09.558398 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7992 13:59:09.561975 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7993 13:59:09.568553 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 13:59:09.571681 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 13:59:09.575267 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 13:59:09.581759 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7997 13:59:09.584974 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7998 13:59:09.588826 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7999 13:59:09.594878 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8000 13:59:09.598541 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8001 13:59:09.601722 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 13:59:09.607932 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 13:59:09.611702 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 13:59:09.614777 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 13:59:09.621116 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 13:59:09.624858 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 13:59:09.627881 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 13:59:09.634441 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 13:59:09.637529 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 13:59:09.640883 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 13:59:09.647537 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 13:59:09.650970 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 13:59:09.654577 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8014 13:59:09.657809 Total UI for P1: 0, mck2ui 16
8015 13:59:09.660590 best dqsien dly found for B0: ( 1, 9, 6)
8016 13:59:09.667289 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8017 13:59:09.670557 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8018 13:59:09.674023 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8019 13:59:09.680521 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 13:59:09.683789 Total UI for P1: 0, mck2ui 16
8021 13:59:09.687271 best dqsien dly found for B1: ( 1, 9, 18)
8022 13:59:09.690314 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8023 13:59:09.693512 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8024 13:59:09.693585
8025 13:59:09.697308 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8026 13:59:09.700317 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8027 13:59:09.703768 [Gating] SW calibration Done
8028 13:59:09.703839 ==
8029 13:59:09.706758 Dram Type= 6, Freq= 0, CH_0, rank 1
8030 13:59:09.709838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 13:59:09.709909 ==
8032 13:59:09.713680 RX Vref Scan: 0
8033 13:59:09.713754
8034 13:59:09.716704 RX Vref 0 -> 0, step: 1
8035 13:59:09.716777
8036 13:59:09.716838 RX Delay 0 -> 252, step: 8
8037 13:59:09.723567 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8038 13:59:09.726440 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8039 13:59:09.729817 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8040 13:59:09.733264 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8041 13:59:09.736512 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8042 13:59:09.743004 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8043 13:59:09.746195 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8044 13:59:09.750055 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8045 13:59:09.752851 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8046 13:59:09.756504 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8047 13:59:09.762655 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8048 13:59:09.766819 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8049 13:59:09.769506 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8050 13:59:09.773210 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8051 13:59:09.779205 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8052 13:59:09.782323 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8053 13:59:09.782396 ==
8054 13:59:09.785580 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 13:59:09.788965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 13:59:09.789041 ==
8057 13:59:09.792467 DQS Delay:
8058 13:59:09.792557 DQS0 = 0, DQS1 = 0
8059 13:59:09.792620 DQM Delay:
8060 13:59:09.795811 DQM0 = 132, DQM1 = 128
8061 13:59:09.795911 DQ Delay:
8062 13:59:09.799233 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
8063 13:59:09.802217 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8064 13:59:09.808773 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8065 13:59:09.811895 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8066 13:59:09.811995
8067 13:59:09.812085
8068 13:59:09.812179 ==
8069 13:59:09.815771 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 13:59:09.818784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 13:59:09.818858 ==
8072 13:59:09.818920
8073 13:59:09.818978
8074 13:59:09.822295 TX Vref Scan disable
8075 13:59:09.825283 == TX Byte 0 ==
8076 13:59:09.828561 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8077 13:59:09.832264 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8078 13:59:09.835334 == TX Byte 1 ==
8079 13:59:09.838524 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8080 13:59:09.842069 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8081 13:59:09.842143 ==
8082 13:59:09.845041 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 13:59:09.848301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 13:59:09.851715 ==
8085 13:59:09.864869
8086 13:59:09.867808 TX Vref early break, caculate TX vref
8087 13:59:09.870938 TX Vref=16, minBit 1, minWin=22, winSum=377
8088 13:59:09.874161 TX Vref=18, minBit 0, minWin=23, winSum=383
8089 13:59:09.877880 TX Vref=20, minBit 3, minWin=23, winSum=395
8090 13:59:09.881313 TX Vref=22, minBit 0, minWin=24, winSum=401
8091 13:59:09.884396 TX Vref=24, minBit 1, minWin=24, winSum=409
8092 13:59:09.890895 TX Vref=26, minBit 2, minWin=24, winSum=413
8093 13:59:09.894941 TX Vref=28, minBit 2, minWin=24, winSum=415
8094 13:59:09.897760 TX Vref=30, minBit 0, minWin=24, winSum=410
8095 13:59:09.900982 TX Vref=32, minBit 0, minWin=24, winSum=401
8096 13:59:09.904292 TX Vref=34, minBit 1, minWin=23, winSum=395
8097 13:59:09.907643 TX Vref=36, minBit 0, minWin=23, winSum=387
8098 13:59:09.914244 [TxChooseVref] Worse bit 2, Min win 24, Win sum 415, Final Vref 28
8099 13:59:09.914329
8100 13:59:09.917580 Final TX Range 0 Vref 28
8101 13:59:09.917654
8102 13:59:09.917716 ==
8103 13:59:09.920817 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 13:59:09.924026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 13:59:09.924098 ==
8106 13:59:09.927089
8107 13:59:09.927160
8108 13:59:09.927221 TX Vref Scan disable
8109 13:59:09.933712 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8110 13:59:09.933791 == TX Byte 0 ==
8111 13:59:09.937488 u2DelayCellOfst[0]=14 cells (4 PI)
8112 13:59:09.940845 u2DelayCellOfst[1]=18 cells (5 PI)
8113 13:59:09.944006 u2DelayCellOfst[2]=10 cells (3 PI)
8114 13:59:09.947152 u2DelayCellOfst[3]=10 cells (3 PI)
8115 13:59:09.950556 u2DelayCellOfst[4]=7 cells (2 PI)
8116 13:59:09.953711 u2DelayCellOfst[5]=0 cells (0 PI)
8117 13:59:09.956984 u2DelayCellOfst[6]=18 cells (5 PI)
8118 13:59:09.960262 u2DelayCellOfst[7]=18 cells (5 PI)
8119 13:59:09.963924 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8120 13:59:09.967048 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8121 13:59:09.970208 == TX Byte 1 ==
8122 13:59:09.973267 u2DelayCellOfst[8]=0 cells (0 PI)
8123 13:59:09.976457 u2DelayCellOfst[9]=0 cells (0 PI)
8124 13:59:09.979914 u2DelayCellOfst[10]=7 cells (2 PI)
8125 13:59:09.983353 u2DelayCellOfst[11]=3 cells (1 PI)
8126 13:59:09.986425 u2DelayCellOfst[12]=10 cells (3 PI)
8127 13:59:09.989855 u2DelayCellOfst[13]=10 cells (3 PI)
8128 13:59:09.992849 u2DelayCellOfst[14]=18 cells (5 PI)
8129 13:59:09.992925 u2DelayCellOfst[15]=10 cells (3 PI)
8130 13:59:09.999600 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8131 13:59:10.003104 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8132 13:59:10.006010 DramC Write-DBI on
8133 13:59:10.006084 ==
8134 13:59:10.009838 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 13:59:10.012957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 13:59:10.013032 ==
8137 13:59:10.013095
8138 13:59:10.013154
8139 13:59:10.016137 TX Vref Scan disable
8140 13:59:10.016215 == TX Byte 0 ==
8141 13:59:10.022847 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8142 13:59:10.022970 == TX Byte 1 ==
8143 13:59:10.029137 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8144 13:59:10.029214 DramC Write-DBI off
8145 13:59:10.029282
8146 13:59:10.029343 [DATLAT]
8147 13:59:10.032662 Freq=1600, CH0 RK1
8148 13:59:10.032735
8149 13:59:10.035500 DATLAT Default: 0xf
8150 13:59:10.035566 0, 0xFFFF, sum = 0
8151 13:59:10.039484 1, 0xFFFF, sum = 0
8152 13:59:10.039551 2, 0xFFFF, sum = 0
8153 13:59:10.042502 3, 0xFFFF, sum = 0
8154 13:59:10.042568 4, 0xFFFF, sum = 0
8155 13:59:10.045525 5, 0xFFFF, sum = 0
8156 13:59:10.045592 6, 0xFFFF, sum = 0
8157 13:59:10.049310 7, 0xFFFF, sum = 0
8158 13:59:10.049384 8, 0xFFFF, sum = 0
8159 13:59:10.052323 9, 0xFFFF, sum = 0
8160 13:59:10.052395 10, 0xFFFF, sum = 0
8161 13:59:10.055440 11, 0xFFFF, sum = 0
8162 13:59:10.055511 12, 0xFFFF, sum = 0
8163 13:59:10.059185 13, 0xFFFF, sum = 0
8164 13:59:10.059264 14, 0x0, sum = 1
8165 13:59:10.062253 15, 0x0, sum = 2
8166 13:59:10.062324 16, 0x0, sum = 3
8167 13:59:10.065339 17, 0x0, sum = 4
8168 13:59:10.065410 best_step = 15
8169 13:59:10.065478
8170 13:59:10.065537 ==
8171 13:59:10.069046 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 13:59:10.075233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 13:59:10.075309 ==
8174 13:59:10.075371 RX Vref Scan: 0
8175 13:59:10.075437
8176 13:59:10.078614 RX Vref 0 -> 0, step: 1
8177 13:59:10.078683
8178 13:59:10.081904 RX Delay 19 -> 252, step: 4
8179 13:59:10.085100 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8180 13:59:10.088593 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8181 13:59:10.095013 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8182 13:59:10.098107 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8183 13:59:10.101545 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8184 13:59:10.104820 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8185 13:59:10.108512 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8186 13:59:10.114820 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8187 13:59:10.118039 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8188 13:59:10.121668 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8189 13:59:10.124734 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8190 13:59:10.127803 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8191 13:59:10.134809 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8192 13:59:10.137676 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8193 13:59:10.141301 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8194 13:59:10.144863 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8195 13:59:10.144937 ==
8196 13:59:10.147720 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 13:59:10.154326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 13:59:10.154406 ==
8199 13:59:10.154469 DQS Delay:
8200 13:59:10.157456 DQS0 = 0, DQS1 = 0
8201 13:59:10.157528 DQM Delay:
8202 13:59:10.161074 DQM0 = 129, DQM1 = 123
8203 13:59:10.161152 DQ Delay:
8204 13:59:10.164219 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8205 13:59:10.167391 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8206 13:59:10.170849 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =120
8207 13:59:10.173949 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =128
8208 13:59:10.174047
8209 13:59:10.174141
8210 13:59:10.174228
8211 13:59:10.177257 [DramC_TX_OE_Calibration] TA2
8212 13:59:10.180488 Original DQ_B0 (3 6) =30, OEN = 27
8213 13:59:10.184173 Original DQ_B1 (3 6) =30, OEN = 27
8214 13:59:10.187227 24, 0x0, End_B0=24 End_B1=24
8215 13:59:10.190665 25, 0x0, End_B0=25 End_B1=25
8216 13:59:10.190738 26, 0x0, End_B0=26 End_B1=26
8217 13:59:10.193982 27, 0x0, End_B0=27 End_B1=27
8218 13:59:10.197346 28, 0x0, End_B0=28 End_B1=28
8219 13:59:10.200610 29, 0x0, End_B0=29 End_B1=29
8220 13:59:10.203537 30, 0x0, End_B0=30 End_B1=30
8221 13:59:10.203617 31, 0x4141, End_B0=30 End_B1=30
8222 13:59:10.207126 Byte0 end_step=30 best_step=27
8223 13:59:10.210199 Byte1 end_step=30 best_step=27
8224 13:59:10.213416 Byte0 TX OE(2T, 0.5T) = (3, 3)
8225 13:59:10.217100 Byte1 TX OE(2T, 0.5T) = (3, 3)
8226 13:59:10.217198
8227 13:59:10.217291
8228 13:59:10.223423 [DQSOSCAuto] RK1, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
8229 13:59:10.227240 CH0 RK1: MR19=303, MR18=1815
8230 13:59:10.233612 CH0_RK1: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
8231 13:59:10.236432 [RxdqsGatingPostProcess] freq 1600
8232 13:59:10.243189 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8233 13:59:10.247098 best DQS0 dly(2T, 0.5T) = (1, 1)
8234 13:59:10.247179 best DQS1 dly(2T, 0.5T) = (1, 1)
8235 13:59:10.249876 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8236 13:59:10.252982 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8237 13:59:10.256752 best DQS0 dly(2T, 0.5T) = (1, 1)
8238 13:59:10.259675 best DQS1 dly(2T, 0.5T) = (1, 1)
8239 13:59:10.262949 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8240 13:59:10.266522 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8241 13:59:10.269451 Pre-setting of DQS Precalculation
8242 13:59:10.276002 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8243 13:59:10.276080 ==
8244 13:59:10.279333 Dram Type= 6, Freq= 0, CH_1, rank 0
8245 13:59:10.282373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 13:59:10.282453 ==
8247 13:59:10.289487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8248 13:59:10.292835 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8249 13:59:10.296021 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8250 13:59:10.302402 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8251 13:59:10.310856 [CA 0] Center 42 (12~72) winsize 61
8252 13:59:10.314145 [CA 1] Center 42 (12~72) winsize 61
8253 13:59:10.317742 [CA 2] Center 38 (9~68) winsize 60
8254 13:59:10.320935 [CA 3] Center 37 (8~67) winsize 60
8255 13:59:10.324043 [CA 4] Center 38 (8~68) winsize 61
8256 13:59:10.327455 [CA 5] Center 37 (7~67) winsize 61
8257 13:59:10.327526
8258 13:59:10.330950 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8259 13:59:10.331023
8260 13:59:10.334028 [CATrainingPosCal] consider 1 rank data
8261 13:59:10.337394 u2DelayCellTimex100 = 271/100 ps
8262 13:59:10.344150 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8263 13:59:10.347346 CA1 delay=42 (12~72),Diff = 5 PI (18 cell)
8264 13:59:10.350700 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8265 13:59:10.354030 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8266 13:59:10.357245 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8267 13:59:10.360635 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8268 13:59:10.360705
8269 13:59:10.363712 CA PerBit enable=1, Macro0, CA PI delay=37
8270 13:59:10.363779
8271 13:59:10.367440 [CBTSetCACLKResult] CA Dly = 37
8272 13:59:10.370104 CS Dly: 8 (0~39)
8273 13:59:10.373752 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8274 13:59:10.377202 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8275 13:59:10.377278 ==
8276 13:59:10.380400 Dram Type= 6, Freq= 0, CH_1, rank 1
8277 13:59:10.386650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 13:59:10.386727 ==
8279 13:59:10.389897 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8280 13:59:10.396883 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8281 13:59:10.399934 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8282 13:59:10.406250 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8283 13:59:10.414070 [CA 0] Center 42 (12~72) winsize 61
8284 13:59:10.417416 [CA 1] Center 43 (14~72) winsize 59
8285 13:59:10.420491 [CA 2] Center 38 (9~68) winsize 60
8286 13:59:10.423854 [CA 3] Center 37 (8~66) winsize 59
8287 13:59:10.427417 [CA 4] Center 38 (8~68) winsize 61
8288 13:59:10.430491 [CA 5] Center 37 (7~67) winsize 61
8289 13:59:10.430562
8290 13:59:10.433727 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8291 13:59:10.433801
8292 13:59:10.441467 [CATrainingPosCal] consider 2 rank data
8293 13:59:10.441552 u2DelayCellTimex100 = 271/100 ps
8294 13:59:10.446740 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8295 13:59:10.450057 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8296 13:59:10.454217 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8297 13:59:10.456965 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8298 13:59:10.460410 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8299 13:59:10.463608 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8300 13:59:10.463701
8301 13:59:10.467199 CA PerBit enable=1, Macro0, CA PI delay=37
8302 13:59:10.467272
8303 13:59:10.470256 [CBTSetCACLKResult] CA Dly = 37
8304 13:59:10.473415 CS Dly: 9 (0~42)
8305 13:59:10.476922 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8306 13:59:10.480048 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8307 13:59:10.480122
8308 13:59:10.483570 ----->DramcWriteLeveling(PI) begin...
8309 13:59:10.483644 ==
8310 13:59:10.486646 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 13:59:10.492981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 13:59:10.493090 ==
8313 13:59:10.496772 Write leveling (Byte 0): 25 => 25
8314 13:59:10.499647 Write leveling (Byte 1): 27 => 27
8315 13:59:10.499719 DramcWriteLeveling(PI) end<-----
8316 13:59:10.499784
8317 13:59:10.503460 ==
8318 13:59:10.506344 Dram Type= 6, Freq= 0, CH_1, rank 0
8319 13:59:10.509495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 13:59:10.509569 ==
8321 13:59:10.513295 [Gating] SW mode calibration
8322 13:59:10.519410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8323 13:59:10.523564 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8324 13:59:10.529870 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 13:59:10.532608 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 13:59:10.535913 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 13:59:10.542881 1 4 12 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
8328 13:59:10.545861 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 13:59:10.549577 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 13:59:10.556014 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 13:59:10.559261 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 13:59:10.562506 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 13:59:10.569088 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 13:59:10.572396 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 13:59:10.575862 1 5 12 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
8336 13:59:10.582653 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8337 13:59:10.585380 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 13:59:10.588899 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 13:59:10.595454 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 13:59:10.598509 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 13:59:10.601854 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 13:59:10.608577 1 6 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8343 13:59:10.611884 1 6 12 | B1->B0 | 3030 4545 | 0 0 | (0 0) (0 0)
8344 13:59:10.615488 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 13:59:10.621853 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 13:59:10.625362 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 13:59:10.628554 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 13:59:10.635170 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 13:59:10.638531 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 13:59:10.641356 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 13:59:10.648312 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8352 13:59:10.651977 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8353 13:59:10.655634 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 13:59:10.661236 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 13:59:10.664694 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 13:59:10.667829 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 13:59:10.674952 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 13:59:10.677826 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 13:59:10.681251 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 13:59:10.687586 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 13:59:10.690805 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 13:59:10.694172 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 13:59:10.701391 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 13:59:10.704241 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 13:59:10.707864 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 13:59:10.714216 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 13:59:10.717375 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8368 13:59:10.720995 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 13:59:10.723797 Total UI for P1: 0, mck2ui 16
8370 13:59:10.727427 best dqsien dly found for B0: ( 1, 9, 12)
8371 13:59:10.730911 Total UI for P1: 0, mck2ui 16
8372 13:59:10.733863 best dqsien dly found for B1: ( 1, 9, 12)
8373 13:59:10.737179 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8374 13:59:10.740739 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8375 13:59:10.740820
8376 13:59:10.747043 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8377 13:59:10.750180 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8378 13:59:10.753890 [Gating] SW calibration Done
8379 13:59:10.753970 ==
8380 13:59:10.757246 Dram Type= 6, Freq= 0, CH_1, rank 0
8381 13:59:10.760062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8382 13:59:10.760143 ==
8383 13:59:10.763882 RX Vref Scan: 0
8384 13:59:10.763961
8385 13:59:10.764025 RX Vref 0 -> 0, step: 1
8386 13:59:10.764085
8387 13:59:10.767328 RX Delay 0 -> 252, step: 8
8388 13:59:10.770240 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8389 13:59:10.773762 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8390 13:59:10.780285 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8391 13:59:10.783410 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8392 13:59:10.786953 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8393 13:59:10.789798 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8394 13:59:10.793547 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8395 13:59:10.800160 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8396 13:59:10.802941 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8397 13:59:10.806546 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8398 13:59:10.809807 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8399 13:59:10.816609 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8400 13:59:10.819447 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8401 13:59:10.822816 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8402 13:59:10.826312 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8403 13:59:10.829347 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8404 13:59:10.832415 ==
8405 13:59:10.836298 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 13:59:10.839397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 13:59:10.839476 ==
8408 13:59:10.839540 DQS Delay:
8409 13:59:10.842919 DQS0 = 0, DQS1 = 0
8410 13:59:10.842993 DQM Delay:
8411 13:59:10.845996 DQM0 = 133, DQM1 = 129
8412 13:59:10.846093 DQ Delay:
8413 13:59:10.849666 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8414 13:59:10.852581 DQ4 =127, DQ5 =143, DQ6 =147, DQ7 =127
8415 13:59:10.855958 DQ8 =115, DQ9 =119, DQ10 =127, DQ11 =123
8416 13:59:10.859235 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8417 13:59:10.859336
8418 13:59:10.859428
8419 13:59:10.859491 ==
8420 13:59:10.862459 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 13:59:10.868943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 13:59:10.869053 ==
8423 13:59:10.869146
8424 13:59:10.869237
8425 13:59:10.872788 TX Vref Scan disable
8426 13:59:10.872891 == TX Byte 0 ==
8427 13:59:10.875944 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8428 13:59:10.882334 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8429 13:59:10.882424 == TX Byte 1 ==
8430 13:59:10.885569 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8431 13:59:10.892170 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8432 13:59:10.892246 ==
8433 13:59:10.895338 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 13:59:10.899011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 13:59:10.899141 ==
8436 13:59:10.912802
8437 13:59:10.916148 TX Vref early break, caculate TX vref
8438 13:59:10.919611 TX Vref=16, minBit 9, minWin=21, winSum=372
8439 13:59:10.922693 TX Vref=18, minBit 8, minWin=22, winSum=379
8440 13:59:10.925834 TX Vref=20, minBit 8, minWin=23, winSum=386
8441 13:59:10.929117 TX Vref=22, minBit 8, minWin=23, winSum=395
8442 13:59:10.932536 TX Vref=24, minBit 8, minWin=24, winSum=404
8443 13:59:10.939316 TX Vref=26, minBit 1, minWin=25, winSum=413
8444 13:59:10.942411 TX Vref=28, minBit 8, minWin=25, winSum=418
8445 13:59:10.945907 TX Vref=30, minBit 0, minWin=25, winSum=417
8446 13:59:10.949022 TX Vref=32, minBit 8, minWin=24, winSum=407
8447 13:59:10.952223 TX Vref=34, minBit 9, minWin=23, winSum=398
8448 13:59:10.958652 TX Vref=36, minBit 9, minWin=22, winSum=386
8449 13:59:10.962121 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
8450 13:59:10.962196
8451 13:59:10.965499 Final TX Range 0 Vref 28
8452 13:59:10.965600
8453 13:59:10.965689 ==
8454 13:59:10.968760 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 13:59:10.972355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 13:59:10.975265 ==
8457 13:59:10.975368
8458 13:59:10.975463
8459 13:59:10.975552 TX Vref Scan disable
8460 13:59:10.982108 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8461 13:59:10.982210 == TX Byte 0 ==
8462 13:59:10.985077 u2DelayCellOfst[0]=14 cells (4 PI)
8463 13:59:10.988592 u2DelayCellOfst[1]=10 cells (3 PI)
8464 13:59:10.992008 u2DelayCellOfst[2]=0 cells (0 PI)
8465 13:59:10.995008 u2DelayCellOfst[3]=7 cells (2 PI)
8466 13:59:10.998271 u2DelayCellOfst[4]=10 cells (3 PI)
8467 13:59:11.002038 u2DelayCellOfst[5]=14 cells (4 PI)
8468 13:59:11.005238 u2DelayCellOfst[6]=14 cells (4 PI)
8469 13:59:11.008576 u2DelayCellOfst[7]=7 cells (2 PI)
8470 13:59:11.011584 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8471 13:59:11.014762 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8472 13:59:11.017850 == TX Byte 1 ==
8473 13:59:11.021589 u2DelayCellOfst[8]=0 cells (0 PI)
8474 13:59:11.024678 u2DelayCellOfst[9]=3 cells (1 PI)
8475 13:59:11.028033 u2DelayCellOfst[10]=10 cells (3 PI)
8476 13:59:11.031062 u2DelayCellOfst[11]=7 cells (2 PI)
8477 13:59:11.034582 u2DelayCellOfst[12]=14 cells (4 PI)
8478 13:59:11.037684 u2DelayCellOfst[13]=14 cells (4 PI)
8479 13:59:11.041590 u2DelayCellOfst[14]=18 cells (5 PI)
8480 13:59:11.044402 u2DelayCellOfst[15]=18 cells (5 PI)
8481 13:59:11.047894 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8482 13:59:11.051763 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8483 13:59:11.054938 DramC Write-DBI on
8484 13:59:11.055019 ==
8485 13:59:11.057647 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 13:59:11.060889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 13:59:11.060970 ==
8488 13:59:11.061036
8489 13:59:11.061096
8490 13:59:11.064204 TX Vref Scan disable
8491 13:59:11.064286 == TX Byte 0 ==
8492 13:59:11.070869 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8493 13:59:11.070951 == TX Byte 1 ==
8494 13:59:11.074232 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8495 13:59:11.077432 DramC Write-DBI off
8496 13:59:11.077513
8497 13:59:11.077578 [DATLAT]
8498 13:59:11.080842 Freq=1600, CH1 RK0
8499 13:59:11.080924
8500 13:59:11.080989 DATLAT Default: 0xf
8501 13:59:11.084024 0, 0xFFFF, sum = 0
8502 13:59:11.087047 1, 0xFFFF, sum = 0
8503 13:59:11.087176 2, 0xFFFF, sum = 0
8504 13:59:11.091293 3, 0xFFFF, sum = 0
8505 13:59:11.091375 4, 0xFFFF, sum = 0
8506 13:59:11.094074 5, 0xFFFF, sum = 0
8507 13:59:11.094157 6, 0xFFFF, sum = 0
8508 13:59:11.096883 7, 0xFFFF, sum = 0
8509 13:59:11.096966 8, 0xFFFF, sum = 0
8510 13:59:11.101100 9, 0xFFFF, sum = 0
8511 13:59:11.101183 10, 0xFFFF, sum = 0
8512 13:59:11.103858 11, 0xFFFF, sum = 0
8513 13:59:11.103942 12, 0xFFFF, sum = 0
8514 13:59:11.107379 13, 0xFFFF, sum = 0
8515 13:59:11.107461 14, 0x0, sum = 1
8516 13:59:11.110428 15, 0x0, sum = 2
8517 13:59:11.110511 16, 0x0, sum = 3
8518 13:59:11.113981 17, 0x0, sum = 4
8519 13:59:11.114073 best_step = 15
8520 13:59:11.114139
8521 13:59:11.114201 ==
8522 13:59:11.116969 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 13:59:11.123427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 13:59:11.123509 ==
8525 13:59:11.123574 RX Vref Scan: 1
8526 13:59:11.123635
8527 13:59:11.126708 Set Vref Range= 24 -> 127
8528 13:59:11.126789
8529 13:59:11.129952 RX Vref 24 -> 127, step: 1
8530 13:59:11.130033
8531 13:59:11.133162 RX Delay 19 -> 252, step: 4
8532 13:59:11.133243
8533 13:59:11.136517 Set Vref, RX VrefLevel [Byte0]: 24
8534 13:59:11.139961 [Byte1]: 24
8535 13:59:11.140043
8536 13:59:11.143016 Set Vref, RX VrefLevel [Byte0]: 25
8537 13:59:11.146402 [Byte1]: 25
8538 13:59:11.146483
8539 13:59:11.149966 Set Vref, RX VrefLevel [Byte0]: 26
8540 13:59:11.152935 [Byte1]: 26
8541 13:59:11.153017
8542 13:59:11.156639 Set Vref, RX VrefLevel [Byte0]: 27
8543 13:59:11.160124 [Byte1]: 27
8544 13:59:11.163848
8545 13:59:11.163930 Set Vref, RX VrefLevel [Byte0]: 28
8546 13:59:11.166997 [Byte1]: 28
8547 13:59:11.171350
8548 13:59:11.171431 Set Vref, RX VrefLevel [Byte0]: 29
8549 13:59:11.174815 [Byte1]: 29
8550 13:59:11.178823
8551 13:59:11.178905 Set Vref, RX VrefLevel [Byte0]: 30
8552 13:59:11.182135 [Byte1]: 30
8553 13:59:11.186423
8554 13:59:11.186526 Set Vref, RX VrefLevel [Byte0]: 31
8555 13:59:11.190043 [Byte1]: 31
8556 13:59:11.194419
8557 13:59:11.194500 Set Vref, RX VrefLevel [Byte0]: 32
8558 13:59:11.197584 [Byte1]: 32
8559 13:59:11.201706
8560 13:59:11.201787 Set Vref, RX VrefLevel [Byte0]: 33
8561 13:59:11.205119 [Byte1]: 33
8562 13:59:11.209481
8563 13:59:11.209562 Set Vref, RX VrefLevel [Byte0]: 34
8564 13:59:11.212715 [Byte1]: 34
8565 13:59:11.216904
8566 13:59:11.216985 Set Vref, RX VrefLevel [Byte0]: 35
8567 13:59:11.221307 [Byte1]: 35
8568 13:59:11.224446
8569 13:59:11.224527 Set Vref, RX VrefLevel [Byte0]: 36
8570 13:59:11.227571 [Byte1]: 36
8571 13:59:11.232337
8572 13:59:11.232418 Set Vref, RX VrefLevel [Byte0]: 37
8573 13:59:11.235613 [Byte1]: 37
8574 13:59:11.239328
8575 13:59:11.239409 Set Vref, RX VrefLevel [Byte0]: 38
8576 13:59:11.242535 [Byte1]: 38
8577 13:59:11.247033
8578 13:59:11.247121 Set Vref, RX VrefLevel [Byte0]: 39
8579 13:59:11.250203 [Byte1]: 39
8580 13:59:11.254758
8581 13:59:11.254840 Set Vref, RX VrefLevel [Byte0]: 40
8582 13:59:11.258354 [Byte1]: 40
8583 13:59:11.262315
8584 13:59:11.262396 Set Vref, RX VrefLevel [Byte0]: 41
8585 13:59:11.265720 [Byte1]: 41
8586 13:59:11.270038
8587 13:59:11.270137 Set Vref, RX VrefLevel [Byte0]: 42
8588 13:59:11.273052 [Byte1]: 42
8589 13:59:11.277117
8590 13:59:11.277222 Set Vref, RX VrefLevel [Byte0]: 43
8591 13:59:11.280690 [Byte1]: 43
8592 13:59:11.285026
8593 13:59:11.285127 Set Vref, RX VrefLevel [Byte0]: 44
8594 13:59:11.288451 [Byte1]: 44
8595 13:59:11.292369
8596 13:59:11.292443 Set Vref, RX VrefLevel [Byte0]: 45
8597 13:59:11.295625 [Byte1]: 45
8598 13:59:11.300096
8599 13:59:11.300170 Set Vref, RX VrefLevel [Byte0]: 46
8600 13:59:11.303063 [Byte1]: 46
8601 13:59:11.307512
8602 13:59:11.307587 Set Vref, RX VrefLevel [Byte0]: 47
8603 13:59:11.310936 [Byte1]: 47
8604 13:59:11.315284
8605 13:59:11.315386 Set Vref, RX VrefLevel [Byte0]: 48
8606 13:59:11.318661 [Byte1]: 48
8607 13:59:11.322931
8608 13:59:11.323033 Set Vref, RX VrefLevel [Byte0]: 49
8609 13:59:11.326050 [Byte1]: 49
8610 13:59:11.330325
8611 13:59:11.330404 Set Vref, RX VrefLevel [Byte0]: 50
8612 13:59:11.334287 [Byte1]: 50
8613 13:59:11.337957
8614 13:59:11.338040 Set Vref, RX VrefLevel [Byte0]: 51
8615 13:59:11.341297 [Byte1]: 51
8616 13:59:11.345409
8617 13:59:11.345490 Set Vref, RX VrefLevel [Byte0]: 52
8618 13:59:11.348597 [Byte1]: 52
8619 13:59:11.352940
8620 13:59:11.353021 Set Vref, RX VrefLevel [Byte0]: 53
8621 13:59:11.356234 [Byte1]: 53
8622 13:59:11.361156
8623 13:59:11.361238 Set Vref, RX VrefLevel [Byte0]: 54
8624 13:59:11.364157 [Byte1]: 54
8625 13:59:11.368406
8626 13:59:11.368498 Set Vref, RX VrefLevel [Byte0]: 55
8627 13:59:11.371658 [Byte1]: 55
8628 13:59:11.376123
8629 13:59:11.376204 Set Vref, RX VrefLevel [Byte0]: 56
8630 13:59:11.379203 [Byte1]: 56
8631 13:59:11.383633
8632 13:59:11.383714 Set Vref, RX VrefLevel [Byte0]: 57
8633 13:59:11.386658 [Byte1]: 57
8634 13:59:11.391399
8635 13:59:11.391480 Set Vref, RX VrefLevel [Byte0]: 58
8636 13:59:11.394134 [Byte1]: 58
8637 13:59:11.398374
8638 13:59:11.398455 Set Vref, RX VrefLevel [Byte0]: 59
8639 13:59:11.401571 [Byte1]: 59
8640 13:59:11.406340
8641 13:59:11.406421 Set Vref, RX VrefLevel [Byte0]: 60
8642 13:59:11.409262 [Byte1]: 60
8643 13:59:11.413474
8644 13:59:11.413555 Set Vref, RX VrefLevel [Byte0]: 61
8645 13:59:11.416854 [Byte1]: 61
8646 13:59:11.421458
8647 13:59:11.421539 Set Vref, RX VrefLevel [Byte0]: 62
8648 13:59:11.424566 [Byte1]: 62
8649 13:59:11.428557
8650 13:59:11.428638 Set Vref, RX VrefLevel [Byte0]: 63
8651 13:59:11.432158 [Byte1]: 63
8652 13:59:11.436494
8653 13:59:11.436575 Set Vref, RX VrefLevel [Byte0]: 64
8654 13:59:11.440219 [Byte1]: 64
8655 13:59:11.443971
8656 13:59:11.444052 Set Vref, RX VrefLevel [Byte0]: 65
8657 13:59:11.447400 [Byte1]: 65
8658 13:59:11.452507
8659 13:59:11.452588 Set Vref, RX VrefLevel [Byte0]: 66
8660 13:59:11.455669 [Byte1]: 66
8661 13:59:11.458945
8662 13:59:11.459026 Set Vref, RX VrefLevel [Byte0]: 67
8663 13:59:11.462387 [Byte1]: 67
8664 13:59:11.466590
8665 13:59:11.466700 Set Vref, RX VrefLevel [Byte0]: 68
8666 13:59:11.469985 [Byte1]: 68
8667 13:59:11.474562
8668 13:59:11.474661 Set Vref, RX VrefLevel [Byte0]: 69
8669 13:59:11.477526 [Byte1]: 69
8670 13:59:11.481666
8671 13:59:11.481764 Set Vref, RX VrefLevel [Byte0]: 70
8672 13:59:11.485490 [Byte1]: 70
8673 13:59:11.489501
8674 13:59:11.489598 Final RX Vref Byte 0 = 56 to rank0
8675 13:59:11.492851 Final RX Vref Byte 1 = 62 to rank0
8676 13:59:11.496013 Final RX Vref Byte 0 = 56 to rank1
8677 13:59:11.499413 Final RX Vref Byte 1 = 62 to rank1==
8678 13:59:11.502413 Dram Type= 6, Freq= 0, CH_1, rank 0
8679 13:59:11.509515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8680 13:59:11.509618 ==
8681 13:59:11.509711 DQS Delay:
8682 13:59:11.509808 DQS0 = 0, DQS1 = 0
8683 13:59:11.512529 DQM Delay:
8684 13:59:11.512627 DQM0 = 132, DQM1 = 128
8685 13:59:11.515775 DQ Delay:
8686 13:59:11.519296 DQ0 =140, DQ1 =128, DQ2 =116, DQ3 =130
8687 13:59:11.522760 DQ4 =130, DQ5 =144, DQ6 =144, DQ7 =126
8688 13:59:11.525906 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =120
8689 13:59:11.528912 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8690 13:59:11.528994
8691 13:59:11.529059
8692 13:59:11.529119
8693 13:59:11.532169 [DramC_TX_OE_Calibration] TA2
8694 13:59:11.535692 Original DQ_B0 (3 6) =30, OEN = 27
8695 13:59:11.539386 Original DQ_B1 (3 6) =30, OEN = 27
8696 13:59:11.542363 24, 0x0, End_B0=24 End_B1=24
8697 13:59:11.542446 25, 0x0, End_B0=25 End_B1=25
8698 13:59:11.545343 26, 0x0, End_B0=26 End_B1=26
8699 13:59:11.549010 27, 0x0, End_B0=27 End_B1=27
8700 13:59:11.551919 28, 0x0, End_B0=28 End_B1=28
8701 13:59:11.555297 29, 0x0, End_B0=29 End_B1=29
8702 13:59:11.555379 30, 0x0, End_B0=30 End_B1=30
8703 13:59:11.558803 31, 0x4141, End_B0=30 End_B1=30
8704 13:59:11.562050 Byte0 end_step=30 best_step=27
8705 13:59:11.565316 Byte1 end_step=30 best_step=27
8706 13:59:11.568557 Byte0 TX OE(2T, 0.5T) = (3, 3)
8707 13:59:11.571737 Byte1 TX OE(2T, 0.5T) = (3, 3)
8708 13:59:11.571815
8709 13:59:11.571879
8710 13:59:11.578928 [DQSOSCAuto] RK0, (LSB)MR18= 0xb14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8711 13:59:11.581534 CH1 RK0: MR19=303, MR18=B14
8712 13:59:11.588175 CH1_RK0: MR19=0x303, MR18=0xB14, DQSOSC=399, MR23=63, INC=23, DEC=15
8713 13:59:11.588254
8714 13:59:11.591338 ----->DramcWriteLeveling(PI) begin...
8715 13:59:11.591447 ==
8716 13:59:11.594877 Dram Type= 6, Freq= 0, CH_1, rank 1
8717 13:59:11.598113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 13:59:11.598193 ==
8719 13:59:11.601833 Write leveling (Byte 0): 25 => 25
8720 13:59:11.604903 Write leveling (Byte 1): 25 => 25
8721 13:59:11.608156 DramcWriteLeveling(PI) end<-----
8722 13:59:11.608238
8723 13:59:11.608303 ==
8724 13:59:11.611625 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 13:59:11.615008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 13:59:11.617887 ==
8727 13:59:11.617968 [Gating] SW mode calibration
8728 13:59:11.627910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8729 13:59:11.631148 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8730 13:59:11.634354 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 13:59:11.640955 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8732 13:59:11.644223 1 4 8 | B1->B0 | 2323 3332 | 0 1 | (0 0) (1 1)
8733 13:59:11.647624 1 4 12 | B1->B0 | 2828 3434 | 0 1 | (1 1) (1 1)
8734 13:59:11.654258 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 13:59:11.657492 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 13:59:11.660722 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 13:59:11.667414 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 13:59:11.670624 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 13:59:11.674278 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8740 13:59:11.680264 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8741 13:59:11.683772 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
8742 13:59:11.687060 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8743 13:59:11.693654 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 13:59:11.697286 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 13:59:11.700110 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 13:59:11.706539 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 13:59:11.709963 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 13:59:11.713253 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8749 13:59:11.719625 1 6 12 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8750 13:59:11.723302 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 13:59:11.726201 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 13:59:11.732894 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 13:59:11.736654 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 13:59:11.739772 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 13:59:11.746358 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 13:59:11.749658 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8757 13:59:11.753451 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8758 13:59:11.759611 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8759 13:59:11.763195 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 13:59:11.766084 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 13:59:11.772655 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 13:59:11.775981 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 13:59:11.778876 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 13:59:11.785903 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 13:59:11.789072 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 13:59:11.792424 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 13:59:11.798911 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 13:59:11.802101 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 13:59:11.805780 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 13:59:11.812028 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 13:59:11.815721 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8772 13:59:11.818686 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8773 13:59:11.825183 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8774 13:59:11.828355 Total UI for P1: 0, mck2ui 16
8775 13:59:11.831948 best dqsien dly found for B0: ( 1, 9, 6)
8776 13:59:11.834927 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8777 13:59:11.838262 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 13:59:11.841864 Total UI for P1: 0, mck2ui 16
8779 13:59:11.845200 best dqsien dly found for B1: ( 1, 9, 12)
8780 13:59:11.848355 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8781 13:59:11.852048 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8782 13:59:11.854784
8783 13:59:11.858160 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8784 13:59:11.861447 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8785 13:59:11.865022 [Gating] SW calibration Done
8786 13:59:11.865126 ==
8787 13:59:11.868029 Dram Type= 6, Freq= 0, CH_1, rank 1
8788 13:59:11.871032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 13:59:11.871155 ==
8790 13:59:11.874509 RX Vref Scan: 0
8791 13:59:11.874604
8792 13:59:11.874700 RX Vref 0 -> 0, step: 1
8793 13:59:11.874790
8794 13:59:11.878000 RX Delay 0 -> 252, step: 8
8795 13:59:11.880930 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8796 13:59:11.887890 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8797 13:59:11.890916 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8798 13:59:11.894273 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8799 13:59:11.897765 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8800 13:59:11.900895 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8801 13:59:11.907596 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8802 13:59:11.910726 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8803 13:59:11.914310 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8804 13:59:11.917356 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8805 13:59:11.920465 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8806 13:59:11.927000 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8807 13:59:11.930380 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8808 13:59:11.933656 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8809 13:59:11.936897 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8810 13:59:11.944487 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8811 13:59:11.944565 ==
8812 13:59:11.947234 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 13:59:11.950311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 13:59:11.950383 ==
8815 13:59:11.950457 DQS Delay:
8816 13:59:11.953355 DQS0 = 0, DQS1 = 0
8817 13:59:11.953461 DQM Delay:
8818 13:59:11.956935 DQM0 = 134, DQM1 = 130
8819 13:59:11.957031 DQ Delay:
8820 13:59:11.959986 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8821 13:59:11.963039 DQ4 =135, DQ5 =143, DQ6 =139, DQ7 =135
8822 13:59:11.966833 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8823 13:59:11.970458 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8824 13:59:11.970533
8825 13:59:11.973000
8826 13:59:11.973068 ==
8827 13:59:11.976717 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 13:59:11.979748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 13:59:11.979838 ==
8830 13:59:11.979912
8831 13:59:11.979975
8832 13:59:11.983029 TX Vref Scan disable
8833 13:59:11.983155 == TX Byte 0 ==
8834 13:59:11.989504 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8835 13:59:11.993199 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8836 13:59:11.993299 == TX Byte 1 ==
8837 13:59:11.999859 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8838 13:59:12.002699 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8839 13:59:12.002776 ==
8840 13:59:12.006408 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 13:59:12.009166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 13:59:12.009265 ==
8843 13:59:12.023591
8844 13:59:12.027068 TX Vref early break, caculate TX vref
8845 13:59:12.030380 TX Vref=16, minBit 9, minWin=21, winSum=374
8846 13:59:12.033705 TX Vref=18, minBit 9, minWin=22, winSum=389
8847 13:59:12.036678 TX Vref=20, minBit 9, minWin=22, winSum=389
8848 13:59:12.040119 TX Vref=22, minBit 9, minWin=23, winSum=401
8849 13:59:12.043365 TX Vref=24, minBit 6, minWin=24, winSum=407
8850 13:59:12.050027 TX Vref=26, minBit 9, minWin=24, winSum=416
8851 13:59:12.053708 TX Vref=28, minBit 9, minWin=25, winSum=423
8852 13:59:12.056437 TX Vref=30, minBit 0, minWin=25, winSum=415
8853 13:59:12.060019 TX Vref=32, minBit 9, minWin=24, winSum=408
8854 13:59:12.063036 TX Vref=34, minBit 0, minWin=24, winSum=406
8855 13:59:12.069728 TX Vref=36, minBit 9, minWin=23, winSum=398
8856 13:59:12.073270 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 28
8857 13:59:12.073372
8858 13:59:12.076438 Final TX Range 0 Vref 28
8859 13:59:12.076538
8860 13:59:12.076629 ==
8861 13:59:12.080021 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 13:59:12.083018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 13:59:12.083152 ==
8864 13:59:12.086039
8865 13:59:12.086135
8866 13:59:12.086225 TX Vref Scan disable
8867 13:59:12.092922 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8868 13:59:12.093020 == TX Byte 0 ==
8869 13:59:12.096105 u2DelayCellOfst[0]=14 cells (4 PI)
8870 13:59:12.099563 u2DelayCellOfst[1]=10 cells (3 PI)
8871 13:59:12.103306 u2DelayCellOfst[2]=0 cells (0 PI)
8872 13:59:12.106671 u2DelayCellOfst[3]=7 cells (2 PI)
8873 13:59:12.109668 u2DelayCellOfst[4]=7 cells (2 PI)
8874 13:59:12.112744 u2DelayCellOfst[5]=14 cells (4 PI)
8875 13:59:12.116556 u2DelayCellOfst[6]=14 cells (4 PI)
8876 13:59:12.119699 u2DelayCellOfst[7]=3 cells (1 PI)
8877 13:59:12.122767 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8878 13:59:12.126054 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8879 13:59:12.129600 == TX Byte 1 ==
8880 13:59:12.132384 u2DelayCellOfst[8]=0 cells (0 PI)
8881 13:59:12.136208 u2DelayCellOfst[9]=3 cells (1 PI)
8882 13:59:12.138957 u2DelayCellOfst[10]=14 cells (4 PI)
8883 13:59:12.142703 u2DelayCellOfst[11]=7 cells (2 PI)
8884 13:59:12.142775 u2DelayCellOfst[12]=14 cells (4 PI)
8885 13:59:12.145541 u2DelayCellOfst[13]=18 cells (5 PI)
8886 13:59:12.149024 u2DelayCellOfst[14]=21 cells (6 PI)
8887 13:59:12.152355 u2DelayCellOfst[15]=21 cells (6 PI)
8888 13:59:12.158711 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8889 13:59:12.162313 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8890 13:59:12.165444 DramC Write-DBI on
8891 13:59:12.165551 ==
8892 13:59:12.168725 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 13:59:12.172151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 13:59:12.172251 ==
8895 13:59:12.172344
8896 13:59:12.172407
8897 13:59:12.175302 TX Vref Scan disable
8898 13:59:12.175382 == TX Byte 0 ==
8899 13:59:12.182267 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8900 13:59:12.182343 == TX Byte 1 ==
8901 13:59:12.185362 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8902 13:59:12.188613 DramC Write-DBI off
8903 13:59:12.188684
8904 13:59:12.188747 [DATLAT]
8905 13:59:12.191882 Freq=1600, CH1 RK1
8906 13:59:12.191978
8907 13:59:12.192066 DATLAT Default: 0xf
8908 13:59:12.195361 0, 0xFFFF, sum = 0
8909 13:59:12.195464 1, 0xFFFF, sum = 0
8910 13:59:12.198468 2, 0xFFFF, sum = 0
8911 13:59:12.198568 3, 0xFFFF, sum = 0
8912 13:59:12.201797 4, 0xFFFF, sum = 0
8913 13:59:12.201870 5, 0xFFFF, sum = 0
8914 13:59:12.205347 6, 0xFFFF, sum = 0
8915 13:59:12.208563 7, 0xFFFF, sum = 0
8916 13:59:12.208640 8, 0xFFFF, sum = 0
8917 13:59:12.211555 9, 0xFFFF, sum = 0
8918 13:59:12.211632 10, 0xFFFF, sum = 0
8919 13:59:12.215421 11, 0xFFFF, sum = 0
8920 13:59:12.215492 12, 0xFFFF, sum = 0
8921 13:59:12.218783 13, 0xFFFF, sum = 0
8922 13:59:12.218880 14, 0x0, sum = 1
8923 13:59:12.221460 15, 0x0, sum = 2
8924 13:59:12.221532 16, 0x0, sum = 3
8925 13:59:12.225019 17, 0x0, sum = 4
8926 13:59:12.225091 best_step = 15
8927 13:59:12.225153
8928 13:59:12.225242 ==
8929 13:59:12.228344 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 13:59:12.231187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 13:59:12.234512 ==
8932 13:59:12.234609 RX Vref Scan: 0
8933 13:59:12.234699
8934 13:59:12.238566 RX Vref 0 -> 0, step: 1
8935 13:59:12.238668
8936 13:59:12.241533 RX Delay 19 -> 252, step: 4
8937 13:59:12.244512 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8938 13:59:12.248126 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8939 13:59:12.250965 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8940 13:59:12.257758 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8941 13:59:12.261274 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8942 13:59:12.264462 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8943 13:59:12.267692 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8944 13:59:12.271051 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8945 13:59:12.277567 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8946 13:59:12.280891 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8947 13:59:12.283952 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8948 13:59:12.287438 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8949 13:59:12.291002 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8950 13:59:12.297271 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8951 13:59:12.300970 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8952 13:59:12.303972 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8953 13:59:12.304074 ==
8954 13:59:12.307302 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 13:59:12.314162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 13:59:12.314266 ==
8957 13:59:12.314369 DQS Delay:
8958 13:59:12.314459 DQS0 = 0, DQS1 = 0
8959 13:59:12.316902 DQM Delay:
8960 13:59:12.316974 DQM0 = 131, DQM1 = 128
8961 13:59:12.320074 DQ Delay:
8962 13:59:12.323401 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
8963 13:59:12.327229 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
8964 13:59:12.330229 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8965 13:59:12.333581 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
8966 13:59:12.333657
8967 13:59:12.333721
8968 13:59:12.333785
8969 13:59:12.336924 [DramC_TX_OE_Calibration] TA2
8970 13:59:12.339967 Original DQ_B0 (3 6) =30, OEN = 27
8971 13:59:12.343337 Original DQ_B1 (3 6) =30, OEN = 27
8972 13:59:12.346607 24, 0x0, End_B0=24 End_B1=24
8973 13:59:12.346676 25, 0x0, End_B0=25 End_B1=25
8974 13:59:12.349976 26, 0x0, End_B0=26 End_B1=26
8975 13:59:12.353317 27, 0x0, End_B0=27 End_B1=27
8976 13:59:12.356643 28, 0x0, End_B0=28 End_B1=28
8977 13:59:12.360282 29, 0x0, End_B0=29 End_B1=29
8978 13:59:12.360356 30, 0x0, End_B0=30 End_B1=30
8979 13:59:12.362939 31, 0x4141, End_B0=30 End_B1=30
8980 13:59:12.366519 Byte0 end_step=30 best_step=27
8981 13:59:12.369666 Byte1 end_step=30 best_step=27
8982 13:59:12.373103 Byte0 TX OE(2T, 0.5T) = (3, 3)
8983 13:59:12.376409 Byte1 TX OE(2T, 0.5T) = (3, 3)
8984 13:59:12.376508
8985 13:59:12.376599
8986 13:59:12.383161 [DQSOSCAuto] RK1, (LSB)MR18= 0x1220, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
8987 13:59:12.386162 CH1 RK1: MR19=303, MR18=1220
8988 13:59:12.392575 CH1_RK1: MR19=0x303, MR18=0x1220, DQSOSC=393, MR23=63, INC=23, DEC=15
8989 13:59:12.396000 [RxdqsGatingPostProcess] freq 1600
8990 13:59:12.402772 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8991 13:59:12.402883 best DQS0 dly(2T, 0.5T) = (1, 1)
8992 13:59:12.405988 best DQS1 dly(2T, 0.5T) = (1, 1)
8993 13:59:12.409421 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8994 13:59:12.412618 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8995 13:59:12.415726 best DQS0 dly(2T, 0.5T) = (1, 1)
8996 13:59:12.419275 best DQS1 dly(2T, 0.5T) = (1, 1)
8997 13:59:12.422520 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8998 13:59:12.425732 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8999 13:59:12.428922 Pre-setting of DQS Precalculation
9000 13:59:12.432440 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9001 13:59:12.442321 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9002 13:59:12.448884 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9003 13:59:12.448972
9004 13:59:12.449063
9005 13:59:12.452080 [Calibration Summary] 3200 Mbps
9006 13:59:12.452175 CH 0, Rank 0
9007 13:59:12.455858 SW Impedance : PASS
9008 13:59:12.455935 DUTY Scan : NO K
9009 13:59:12.459024 ZQ Calibration : PASS
9010 13:59:12.461715 Jitter Meter : NO K
9011 13:59:12.461809 CBT Training : PASS
9012 13:59:12.465169 Write leveling : PASS
9013 13:59:12.469014 RX DQS gating : PASS
9014 13:59:12.469123 RX DQ/DQS(RDDQC) : PASS
9015 13:59:12.471658 TX DQ/DQS : PASS
9016 13:59:12.475417 RX DATLAT : PASS
9017 13:59:12.475488 RX DQ/DQS(Engine): PASS
9018 13:59:12.478329 TX OE : PASS
9019 13:59:12.478406 All Pass.
9020 13:59:12.478502
9021 13:59:12.481958 CH 0, Rank 1
9022 13:59:12.482058 SW Impedance : PASS
9023 13:59:12.484937 DUTY Scan : NO K
9024 13:59:12.488295 ZQ Calibration : PASS
9025 13:59:12.488366 Jitter Meter : NO K
9026 13:59:12.491632 CBT Training : PASS
9027 13:59:12.494846 Write leveling : PASS
9028 13:59:12.494945 RX DQS gating : PASS
9029 13:59:12.497762 RX DQ/DQS(RDDQC) : PASS
9030 13:59:12.501110 TX DQ/DQS : PASS
9031 13:59:12.501209 RX DATLAT : PASS
9032 13:59:12.504486 RX DQ/DQS(Engine): PASS
9033 13:59:12.508318 TX OE : PASS
9034 13:59:12.508419 All Pass.
9035 13:59:12.508511
9036 13:59:12.508610 CH 1, Rank 0
9037 13:59:12.511296 SW Impedance : PASS
9038 13:59:12.514384 DUTY Scan : NO K
9039 13:59:12.514482 ZQ Calibration : PASS
9040 13:59:12.518035 Jitter Meter : NO K
9041 13:59:12.521036 CBT Training : PASS
9042 13:59:12.521132 Write leveling : PASS
9043 13:59:12.524209 RX DQS gating : PASS
9044 13:59:12.524309 RX DQ/DQS(RDDQC) : PASS
9045 13:59:12.527689 TX DQ/DQS : PASS
9046 13:59:12.531156 RX DATLAT : PASS
9047 13:59:12.531242 RX DQ/DQS(Engine): PASS
9048 13:59:12.534415 TX OE : PASS
9049 13:59:12.534499 All Pass.
9050 13:59:12.534589
9051 13:59:12.537675 CH 1, Rank 1
9052 13:59:12.537770 SW Impedance : PASS
9053 13:59:12.541090 DUTY Scan : NO K
9054 13:59:12.544092 ZQ Calibration : PASS
9055 13:59:12.544176 Jitter Meter : NO K
9056 13:59:12.547571 CBT Training : PASS
9057 13:59:12.551013 Write leveling : PASS
9058 13:59:12.551111 RX DQS gating : PASS
9059 13:59:12.554393 RX DQ/DQS(RDDQC) : PASS
9060 13:59:12.557585 TX DQ/DQS : PASS
9061 13:59:12.557681 RX DATLAT : PASS
9062 13:59:12.560787 RX DQ/DQS(Engine): PASS
9063 13:59:12.563874 TX OE : PASS
9064 13:59:12.563968 All Pass.
9065 13:59:12.564056
9066 13:59:12.564154 DramC Write-DBI on
9067 13:59:12.567139 PER_BANK_REFRESH: Hybrid Mode
9068 13:59:12.570569 TX_TRACKING: ON
9069 13:59:12.577217 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9070 13:59:12.587051 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9071 13:59:12.593787 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9072 13:59:12.598329 [FAST_K] Save calibration result to emmc
9073 13:59:12.601087 sync common calibartion params.
9074 13:59:12.603617 sync cbt_mode0:1, 1:1
9075 13:59:12.603702 dram_init: ddr_geometry: 2
9076 13:59:12.607006 dram_init: ddr_geometry: 2
9077 13:59:12.610416 dram_init: ddr_geometry: 2
9078 13:59:12.613557 0:dram_rank_size:100000000
9079 13:59:12.613658 1:dram_rank_size:100000000
9080 13:59:12.620061 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9081 13:59:12.623526 DFS_SHUFFLE_HW_MODE: ON
9082 13:59:12.627101 dramc_set_vcore_voltage set vcore to 725000
9083 13:59:12.630365 Read voltage for 1600, 0
9084 13:59:12.630439 Vio18 = 0
9085 13:59:12.630502 Vcore = 725000
9086 13:59:12.632944 Vdram = 0
9087 13:59:12.633039 Vddq = 0
9088 13:59:12.633127 Vmddr = 0
9089 13:59:12.636639 switch to 3200 Mbps bootup
9090 13:59:12.636748 [DramcRunTimeConfig]
9091 13:59:12.639917 PHYPLL
9092 13:59:12.640018 DPM_CONTROL_AFTERK: ON
9093 13:59:12.642990 PER_BANK_REFRESH: ON
9094 13:59:12.646505 REFRESH_OVERHEAD_REDUCTION: ON
9095 13:59:12.646605 CMD_PICG_NEW_MODE: OFF
9096 13:59:12.649589 XRTWTW_NEW_MODE: ON
9097 13:59:12.649691 XRTRTR_NEW_MODE: ON
9098 13:59:12.653425 TX_TRACKING: ON
9099 13:59:12.653532 RDSEL_TRACKING: OFF
9100 13:59:12.656365 DQS Precalculation for DVFS: ON
9101 13:59:12.659663 RX_TRACKING: OFF
9102 13:59:12.659759 HW_GATING DBG: ON
9103 13:59:12.662718 ZQCS_ENABLE_LP4: ON
9104 13:59:12.662813 RX_PICG_NEW_MODE: ON
9105 13:59:12.665767 TX_PICG_NEW_MODE: ON
9106 13:59:12.669650 ENABLE_RX_DCM_DPHY: ON
9107 13:59:12.669748 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9108 13:59:12.672850 DUMMY_READ_FOR_TRACKING: OFF
9109 13:59:12.675911 !!! SPM_CONTROL_AFTERK: OFF
9110 13:59:12.678942 !!! SPM could not control APHY
9111 13:59:12.679040 IMPEDANCE_TRACKING: ON
9112 13:59:12.682419 TEMP_SENSOR: ON
9113 13:59:12.682517 HW_SAVE_FOR_SR: OFF
9114 13:59:12.686063 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9115 13:59:12.692122 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9116 13:59:12.692230 Read ODT Tracking: ON
9117 13:59:12.695482 Refresh Rate DeBounce: ON
9118 13:59:12.695590 DFS_NO_QUEUE_FLUSH: ON
9119 13:59:12.699310 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9120 13:59:12.702557 ENABLE_DFS_RUNTIME_MRW: OFF
9121 13:59:12.705931 DDR_RESERVE_NEW_MODE: ON
9122 13:59:12.706033 MR_CBT_SWITCH_FREQ: ON
9123 13:59:12.709260 =========================
9124 13:59:12.728495 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9125 13:59:12.731765 dram_init: ddr_geometry: 2
9126 13:59:12.749762 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9127 13:59:12.753086 dram_init: dram init end (result: 0)
9128 13:59:12.759884 DRAM-K: Full calibration passed in 24450 msecs
9129 13:59:12.762963 MRC: failed to locate region type 0.
9130 13:59:12.763060 DRAM rank0 size:0x100000000,
9131 13:59:12.766654 DRAM rank1 size=0x100000000
9132 13:59:12.776328 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9133 13:59:12.782960 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9134 13:59:12.789294 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9135 13:59:12.796187 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9136 13:59:12.799556 DRAM rank0 size:0x100000000,
9137 13:59:12.802441 DRAM rank1 size=0x100000000
9138 13:59:12.802537 CBMEM:
9139 13:59:12.805687 IMD: root @ 0xfffff000 254 entries.
9140 13:59:12.809136 IMD: root @ 0xffffec00 62 entries.
9141 13:59:12.812752 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9142 13:59:12.819292 WARNING: RO_VPD is uninitialized or empty.
9143 13:59:12.822232 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9144 13:59:12.829916 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9145 13:59:12.842687 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9146 13:59:12.853940 BS: romstage times (exec / console): total (unknown) / 23981 ms
9147 13:59:12.854042
9148 13:59:12.854134
9149 13:59:12.863901 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9150 13:59:12.867239 ARM64: Exception handlers installed.
9151 13:59:12.870696 ARM64: Testing exception
9152 13:59:12.873673 ARM64: Done test exception
9153 13:59:12.873770 Enumerating buses...
9154 13:59:12.877291 Show all devs... Before device enumeration.
9155 13:59:12.880155 Root Device: enabled 1
9156 13:59:12.883362 CPU_CLUSTER: 0: enabled 1
9157 13:59:12.883435 CPU: 00: enabled 1
9158 13:59:12.886786 Compare with tree...
9159 13:59:12.886881 Root Device: enabled 1
9160 13:59:12.890001 CPU_CLUSTER: 0: enabled 1
9161 13:59:12.893210 CPU: 00: enabled 1
9162 13:59:12.893304 Root Device scanning...
9163 13:59:12.896920 scan_static_bus for Root Device
9164 13:59:12.900223 CPU_CLUSTER: 0 enabled
9165 13:59:12.903368 scan_static_bus for Root Device done
9166 13:59:12.906614 scan_bus: bus Root Device finished in 8 msecs
9167 13:59:12.906717 done
9168 13:59:12.913256 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9169 13:59:12.916473 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9170 13:59:12.923051 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9171 13:59:12.929773 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9172 13:59:12.929875 Allocating resources...
9173 13:59:12.933094 Reading resources...
9174 13:59:12.936185 Root Device read_resources bus 0 link: 0
9175 13:59:12.940100 DRAM rank0 size:0x100000000,
9176 13:59:12.940198 DRAM rank1 size=0x100000000
9177 13:59:12.945898 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9178 13:59:12.946000 CPU: 00 missing read_resources
9179 13:59:12.952996 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9180 13:59:12.955771 Root Device read_resources bus 0 link: 0 done
9181 13:59:12.959026 Done reading resources.
9182 13:59:12.962423 Show resources in subtree (Root Device)...After reading.
9183 13:59:12.965731 Root Device child on link 0 CPU_CLUSTER: 0
9184 13:59:12.969186 CPU_CLUSTER: 0 child on link 0 CPU: 00
9185 13:59:12.979248 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9186 13:59:12.979355 CPU: 00
9187 13:59:12.985780 Root Device assign_resources, bus 0 link: 0
9188 13:59:12.989176 CPU_CLUSTER: 0 missing set_resources
9189 13:59:12.992367 Root Device assign_resources, bus 0 link: 0 done
9190 13:59:12.995835 Done setting resources.
9191 13:59:12.998655 Show resources in subtree (Root Device)...After assigning values.
9192 13:59:13.001943 Root Device child on link 0 CPU_CLUSTER: 0
9193 13:59:13.008749 CPU_CLUSTER: 0 child on link 0 CPU: 00
9194 13:59:13.015670 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9195 13:59:13.018680 CPU: 00
9196 13:59:13.018781 Done allocating resources.
9197 13:59:13.024983 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9198 13:59:13.025056 Enabling resources...
9199 13:59:13.028669 done.
9200 13:59:13.031597 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9201 13:59:13.035212 Initializing devices...
9202 13:59:13.035282 Root Device init
9203 13:59:13.038686 init hardware done!
9204 13:59:13.038752 0x00000018: ctrlr->caps
9205 13:59:13.041946 52.000 MHz: ctrlr->f_max
9206 13:59:13.045013 0.400 MHz: ctrlr->f_min
9207 13:59:13.045111 0x40ff8080: ctrlr->voltages
9208 13:59:13.048321 sclk: 390625
9209 13:59:13.048390 Bus Width = 1
9210 13:59:13.051764 sclk: 390625
9211 13:59:13.051842 Bus Width = 1
9212 13:59:13.054837 Early init status = 3
9213 13:59:13.057920 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9214 13:59:13.061493 in-header: 03 fc 00 00 01 00 00 00
9215 13:59:13.064950 in-data: 00
9216 13:59:13.067886 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9217 13:59:13.073283 in-header: 03 fd 00 00 00 00 00 00
9218 13:59:13.076483 in-data:
9219 13:59:13.079636 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9220 13:59:13.083949 in-header: 03 fc 00 00 01 00 00 00
9221 13:59:13.087322 in-data: 00
9222 13:59:13.090525 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9223 13:59:13.096183 in-header: 03 fd 00 00 00 00 00 00
9224 13:59:13.099838 in-data:
9225 13:59:13.102983 [SSUSB] Setting up USB HOST controller...
9226 13:59:13.106014 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9227 13:59:13.109584 [SSUSB] phy power-on done.
9228 13:59:13.112903 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9229 13:59:13.119380 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9230 13:59:13.123663 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9231 13:59:13.129504 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9232 13:59:13.136305 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9233 13:59:13.142565 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9234 13:59:13.148942 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9235 13:59:13.155588 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9236 13:59:13.159294 SPM: binary array size = 0x9dc
9237 13:59:13.162271 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9238 13:59:13.168642 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9239 13:59:13.175204 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9240 13:59:13.181893 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9241 13:59:13.185441 configure_display: Starting display init
9242 13:59:13.220135 anx7625_power_on_init: Init interface.
9243 13:59:13.222864 anx7625_disable_pd_protocol: Disabled PD feature.
9244 13:59:13.226580 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9245 13:59:13.254591 anx7625_start_dp_work: Secure OCM version=00
9246 13:59:13.257143 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9247 13:59:13.271917 sp_tx_get_edid_block: EDID Block = 1
9248 13:59:13.374962 Extracted contents:
9249 13:59:13.378081 header: 00 ff ff ff ff ff ff 00
9250 13:59:13.381471 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9251 13:59:13.384640 version: 01 04
9252 13:59:13.387746 basic params: 95 1f 11 78 0a
9253 13:59:13.390913 chroma info: 76 90 94 55 54 90 27 21 50 54
9254 13:59:13.394453 established: 00 00 00
9255 13:59:13.400730 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9256 13:59:13.407888 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9257 13:59:13.410686 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9258 13:59:13.417905 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9259 13:59:13.423855 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9260 13:59:13.427398 extensions: 00
9261 13:59:13.427498 checksum: fb
9262 13:59:13.427586
9263 13:59:13.434097 Manufacturer: IVO Model 57d Serial Number 0
9264 13:59:13.434199 Made week 0 of 2020
9265 13:59:13.437615 EDID version: 1.4
9266 13:59:13.437688 Digital display
9267 13:59:13.440598 6 bits per primary color channel
9268 13:59:13.443770 DisplayPort interface
9269 13:59:13.443842 Maximum image size: 31 cm x 17 cm
9270 13:59:13.447288 Gamma: 220%
9271 13:59:13.447355 Check DPMS levels
9272 13:59:13.453581 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9273 13:59:13.457064 First detailed timing is preferred timing
9274 13:59:13.457141 Established timings supported:
9275 13:59:13.460400 Standard timings supported:
9276 13:59:13.463403 Detailed timings
9277 13:59:13.467378 Hex of detail: 383680a07038204018303c0035ae10000019
9278 13:59:13.473890 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9279 13:59:13.476779 0780 0798 07c8 0820 hborder 0
9280 13:59:13.480154 0438 043b 0447 0458 vborder 0
9281 13:59:13.483453 -hsync -vsync
9282 13:59:13.483559 Did detailed timing
9283 13:59:13.490025 Hex of detail: 000000000000000000000000000000000000
9284 13:59:13.493470 Manufacturer-specified data, tag 0
9285 13:59:13.496700 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9286 13:59:13.500351 ASCII string: InfoVision
9287 13:59:13.503289 Hex of detail: 000000fe00523134304e574635205248200a
9288 13:59:13.506744 ASCII string: R140NWF5 RH
9289 13:59:13.506846 Checksum
9290 13:59:13.510166 Checksum: 0xfb (valid)
9291 13:59:13.513024 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9292 13:59:13.516367 DSI data_rate: 832800000 bps
9293 13:59:13.522864 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9294 13:59:13.526434 anx7625_parse_edid: pixelclock(138800).
9295 13:59:13.529573 hactive(1920), hsync(48), hfp(24), hbp(88)
9296 13:59:13.532867 vactive(1080), vsync(12), vfp(3), vbp(17)
9297 13:59:13.536494 anx7625_dsi_config: config dsi.
9298 13:59:13.542729 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9299 13:59:13.556851 anx7625_dsi_config: success to config DSI
9300 13:59:13.559980 anx7625_dp_start: MIPI phy setup OK.
9301 13:59:13.563367 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9302 13:59:13.566533 mtk_ddp_mode_set invalid vrefresh 60
9303 13:59:13.569821 main_disp_path_setup
9304 13:59:13.569892 ovl_layer_smi_id_en
9305 13:59:13.573296 ovl_layer_smi_id_en
9306 13:59:13.573393 ccorr_config
9307 13:59:13.573483 aal_config
9308 13:59:13.576339 gamma_config
9309 13:59:13.576436 postmask_config
9310 13:59:13.579823 dither_config
9311 13:59:13.583059 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9312 13:59:13.589483 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9313 13:59:13.593009 Root Device init finished in 553 msecs
9314 13:59:13.596061 CPU_CLUSTER: 0 init
9315 13:59:13.602843 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9316 13:59:13.609322 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9317 13:59:13.609424 APU_MBOX 0x190000b0 = 0x10001
9318 13:59:13.613218 APU_MBOX 0x190001b0 = 0x10001
9319 13:59:13.616331 APU_MBOX 0x190005b0 = 0x10001
9320 13:59:13.619466 APU_MBOX 0x190006b0 = 0x10001
9321 13:59:13.625885 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9322 13:59:13.635552 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9323 13:59:13.648059 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9324 13:59:13.655396 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9325 13:59:13.666575 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9326 13:59:13.675437 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9327 13:59:13.678828 CPU_CLUSTER: 0 init finished in 81 msecs
9328 13:59:13.681930 Devices initialized
9329 13:59:13.685562 Show all devs... After init.
9330 13:59:13.685670 Root Device: enabled 1
9331 13:59:13.688602 CPU_CLUSTER: 0: enabled 1
9332 13:59:13.692501 CPU: 00: enabled 1
9333 13:59:13.695193 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9334 13:59:13.698613 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9335 13:59:13.702195 ELOG: NV offset 0x57f000 size 0x1000
9336 13:59:13.708861 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9337 13:59:13.714995 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9338 13:59:13.718499 ELOG: Event(17) added with size 13 at 2023-09-21 13:59:14 UTC
9339 13:59:13.725252 out: cmd=0x121: 03 db 21 01 00 00 00 00
9340 13:59:13.728468 in-header: 03 12 00 00 2c 00 00 00
9341 13:59:13.738157 in-data: 4d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9342 13:59:13.744915 ELOG: Event(A1) added with size 10 at 2023-09-21 13:59:14 UTC
9343 13:59:13.751486 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9344 13:59:13.758071 ELOG: Event(A0) added with size 9 at 2023-09-21 13:59:14 UTC
9345 13:59:13.761320 elog_add_boot_reason: Logged dev mode boot
9346 13:59:13.767862 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9347 13:59:13.767961 Finalize devices...
9348 13:59:13.771070 Devices finalized
9349 13:59:13.774457 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9350 13:59:13.778107 Writing coreboot table at 0xffe64000
9351 13:59:13.781193 0. 000000000010a000-0000000000113fff: RAMSTAGE
9352 13:59:13.784915 1. 0000000040000000-00000000400fffff: RAM
9353 13:59:13.791582 2. 0000000040100000-000000004032afff: RAMSTAGE
9354 13:59:13.794408 3. 000000004032b000-00000000545fffff: RAM
9355 13:59:13.798252 4. 0000000054600000-000000005465ffff: BL31
9356 13:59:13.801317 5. 0000000054660000-00000000ffe63fff: RAM
9357 13:59:13.807791 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9358 13:59:13.810862 7. 0000000100000000-000000023fffffff: RAM
9359 13:59:13.814323 Passing 5 GPIOs to payload:
9360 13:59:13.817544 NAME | PORT | POLARITY | VALUE
9361 13:59:13.824197 EC in RW | 0x000000aa | low | undefined
9362 13:59:13.827272 EC interrupt | 0x00000005 | low | undefined
9363 13:59:13.830696 TPM interrupt | 0x000000ab | high | undefined
9364 13:59:13.837951 SD card detect | 0x00000011 | high | undefined
9365 13:59:13.840774 speaker enable | 0x00000093 | high | undefined
9366 13:59:13.843911 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9367 13:59:13.847785 in-header: 03 f9 00 00 02 00 00 00
9368 13:59:13.850735 in-data: 02 00
9369 13:59:13.853769 ADC[4]: Raw value=901847 ID=7
9370 13:59:13.853875 ADC[3]: Raw value=213546 ID=1
9371 13:59:13.857421 RAM Code: 0x71
9372 13:59:13.860485 ADC[6]: Raw value=75000 ID=0
9373 13:59:13.860592 ADC[5]: Raw value=213546 ID=1
9374 13:59:13.863533 SKU Code: 0x1
9375 13:59:13.870246 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 855a
9376 13:59:13.870353 coreboot table: 964 bytes.
9377 13:59:13.873529 IMD ROOT 0. 0xfffff000 0x00001000
9378 13:59:13.876651 IMD SMALL 1. 0xffffe000 0x00001000
9379 13:59:13.880312 RO MCACHE 2. 0xffffc000 0x00001104
9380 13:59:13.883559 CONSOLE 3. 0xfff7c000 0x00080000
9381 13:59:13.886852 FMAP 4. 0xfff7b000 0x00000452
9382 13:59:13.889878 TIME STAMP 5. 0xfff7a000 0x00000910
9383 13:59:13.894000 VBOOT WORK 6. 0xfff66000 0x00014000
9384 13:59:13.896938 RAMOOPS 7. 0xffe66000 0x00100000
9385 13:59:13.899688 COREBOOT 8. 0xffe64000 0x00002000
9386 13:59:13.903453 IMD small region:
9387 13:59:13.906442 IMD ROOT 0. 0xffffec00 0x00000400
9388 13:59:13.910399 VPD 1. 0xffffeb80 0x0000006c
9389 13:59:13.913304 MMC STATUS 2. 0xffffeb60 0x00000004
9390 13:59:13.919928 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9391 13:59:13.920030 Probing TPM: done!
9392 13:59:13.923291 Connected to device vid:did:rid of 1ae0:0028:00
9393 13:59:13.934346 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9394 13:59:13.937729 Initialized TPM device CR50 revision 0
9395 13:59:13.941457 Checking cr50 for pending updates
9396 13:59:13.944941 Reading cr50 TPM mode
9397 13:59:13.954052 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9398 13:59:13.960398 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9399 13:59:14.000636 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9400 13:59:14.003739 Checking segment from ROM address 0x40100000
9401 13:59:14.007251 Checking segment from ROM address 0x4010001c
9402 13:59:14.013565 Loading segment from ROM address 0x40100000
9403 13:59:14.013662 code (compression=0)
9404 13:59:14.023901 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9405 13:59:14.030212 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9406 13:59:14.030315 it's not compressed!
9407 13:59:14.037432 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9408 13:59:14.043403 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9409 13:59:14.060743 Loading segment from ROM address 0x4010001c
9410 13:59:14.060845 Entry Point 0x80000000
9411 13:59:14.064244 Loaded segments
9412 13:59:14.067830 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9413 13:59:14.073940 Jumping to boot code at 0x80000000(0xffe64000)
9414 13:59:14.080876 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9415 13:59:14.087276 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9416 13:59:14.095122 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9417 13:59:14.098648 Checking segment from ROM address 0x40100000
9418 13:59:14.101978 Checking segment from ROM address 0x4010001c
9419 13:59:14.108442 Loading segment from ROM address 0x40100000
9420 13:59:14.108546 code (compression=1)
9421 13:59:14.115241 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9422 13:59:14.125215 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9423 13:59:14.125304 using LZMA
9424 13:59:14.133937 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9425 13:59:14.140424 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9426 13:59:14.143474 Loading segment from ROM address 0x4010001c
9427 13:59:14.143548 Entry Point 0x54601000
9428 13:59:14.146863 Loaded segments
9429 13:59:14.150622 NOTICE: MT8192 bl31_setup
9430 13:59:14.157447 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9431 13:59:14.160614 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9432 13:59:14.163983 WARNING: region 0:
9433 13:59:14.167538 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9434 13:59:14.167605 WARNING: region 1:
9435 13:59:14.173943 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9436 13:59:14.177600 WARNING: region 2:
9437 13:59:14.180989 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9438 13:59:14.183783 WARNING: region 3:
9439 13:59:14.187003 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9440 13:59:14.190604 WARNING: region 4:
9441 13:59:14.197280 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9442 13:59:14.197382 WARNING: region 5:
9443 13:59:14.200597 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 13:59:14.204286 WARNING: region 6:
9445 13:59:14.206950 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 13:59:14.210340 WARNING: region 7:
9447 13:59:14.213480 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9448 13:59:14.220439 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9449 13:59:14.223891 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9450 13:59:14.226922 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9451 13:59:14.234124 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9452 13:59:14.236747 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9453 13:59:14.240554 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9454 13:59:14.246753 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9455 13:59:14.250198 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9456 13:59:14.256877 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9457 13:59:14.260120 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9458 13:59:14.263433 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9459 13:59:14.270502 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9460 13:59:14.273547 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9461 13:59:14.276918 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9462 13:59:14.283396 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9463 13:59:14.287303 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9464 13:59:14.293630 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9465 13:59:14.296679 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9466 13:59:14.300244 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9467 13:59:14.306685 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9468 13:59:14.310213 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9469 13:59:14.313688 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9470 13:59:14.320140 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9471 13:59:14.323489 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9472 13:59:14.330353 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9473 13:59:14.333502 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9474 13:59:14.340005 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9475 13:59:14.343383 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9476 13:59:14.346862 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9477 13:59:14.353108 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9478 13:59:14.356639 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9479 13:59:14.363024 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9480 13:59:14.366400 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9481 13:59:14.369737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9482 13:59:14.373092 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9483 13:59:14.379910 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9484 13:59:14.383422 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9485 13:59:14.386582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9486 13:59:14.389937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9487 13:59:14.396503 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9488 13:59:14.399595 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9489 13:59:14.403473 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9490 13:59:14.406830 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9491 13:59:14.413030 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9492 13:59:14.416328 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9493 13:59:14.419903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9494 13:59:14.423000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9495 13:59:14.429461 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9496 13:59:14.433178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9497 13:59:14.436627 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9498 13:59:14.443008 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9499 13:59:14.446496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9500 13:59:14.453249 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9501 13:59:14.456683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9502 13:59:14.463110 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9503 13:59:14.466566 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9504 13:59:14.469449 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9505 13:59:14.476083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9506 13:59:14.479470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9507 13:59:14.486777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9508 13:59:14.489576 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9509 13:59:14.495962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9510 13:59:14.499348 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9511 13:59:14.506238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9512 13:59:14.509344 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9513 13:59:14.513020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9514 13:59:14.519355 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9515 13:59:14.523066 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9516 13:59:14.529129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9517 13:59:14.532845 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9518 13:59:14.539339 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9519 13:59:14.542919 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9520 13:59:14.545847 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9521 13:59:14.552793 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9522 13:59:14.555945 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9523 13:59:14.562638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9524 13:59:14.565831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9525 13:59:14.572378 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9526 13:59:14.576120 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9527 13:59:14.582306 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9528 13:59:14.585969 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9529 13:59:14.589412 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9530 13:59:14.595764 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9531 13:59:14.598990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9532 13:59:14.606063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9533 13:59:14.609647 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9534 13:59:14.615528 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9535 13:59:14.618903 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9536 13:59:14.622282 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9537 13:59:14.629248 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9538 13:59:14.632471 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9539 13:59:14.638900 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9540 13:59:14.642513 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9541 13:59:14.649214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9542 13:59:14.652112 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9543 13:59:14.659011 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9544 13:59:14.662535 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9545 13:59:14.665903 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9546 13:59:14.669089 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9547 13:59:14.675505 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9548 13:59:14.678780 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9549 13:59:14.682179 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9550 13:59:14.688914 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9551 13:59:14.692337 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9552 13:59:14.695904 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9553 13:59:14.702358 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9554 13:59:14.705436 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9555 13:59:14.712092 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9556 13:59:14.715048 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9557 13:59:14.718447 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9558 13:59:14.725972 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9559 13:59:14.728491 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9560 13:59:14.735056 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9561 13:59:14.738434 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9562 13:59:14.742136 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9563 13:59:14.749077 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9564 13:59:14.751892 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9565 13:59:14.755551 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9566 13:59:14.761895 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9567 13:59:14.764943 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9568 13:59:14.768558 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9569 13:59:14.771643 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9570 13:59:14.778316 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9571 13:59:14.782336 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9572 13:59:14.785003 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9573 13:59:14.791729 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9574 13:59:14.794999 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9575 13:59:14.801985 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9576 13:59:14.805075 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9577 13:59:14.808436 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9578 13:59:14.815487 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9579 13:59:14.818660 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9580 13:59:14.822227 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9581 13:59:14.828061 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9582 13:59:14.831365 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9583 13:59:14.838186 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9584 13:59:14.841647 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9585 13:59:14.845246 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9586 13:59:14.851383 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9587 13:59:14.854988 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9588 13:59:14.861366 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9589 13:59:14.864644 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9590 13:59:14.868047 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9591 13:59:14.875157 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9592 13:59:14.878210 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9593 13:59:14.884577 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9594 13:59:14.888348 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9595 13:59:14.891637 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9596 13:59:14.897879 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9597 13:59:14.901205 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9598 13:59:14.907634 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9599 13:59:14.911096 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9600 13:59:14.914263 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9601 13:59:14.920918 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9602 13:59:14.924258 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9603 13:59:14.927808 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9604 13:59:14.934726 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9605 13:59:14.938085 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9606 13:59:14.944632 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9607 13:59:14.947737 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9608 13:59:14.950923 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9609 13:59:14.957692 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9610 13:59:14.961230 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9611 13:59:14.967829 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9612 13:59:14.970746 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9613 13:59:14.974235 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9614 13:59:14.980682 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9615 13:59:14.984023 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9616 13:59:14.990416 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9617 13:59:14.993544 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9618 13:59:14.997175 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9619 13:59:15.004041 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9620 13:59:15.006864 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9621 13:59:15.013629 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9622 13:59:15.017067 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9623 13:59:15.020734 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9624 13:59:15.027453 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9625 13:59:15.030253 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9626 13:59:15.036810 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9627 13:59:15.039668 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9628 13:59:15.043856 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9629 13:59:15.049601 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9630 13:59:15.052942 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9631 13:59:15.059584 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9632 13:59:15.063346 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9633 13:59:15.066459 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9634 13:59:15.072883 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9635 13:59:15.076010 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9636 13:59:15.082800 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9637 13:59:15.085951 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9638 13:59:15.092589 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9639 13:59:15.096496 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9640 13:59:15.099294 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9641 13:59:15.105725 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9642 13:59:15.109131 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9643 13:59:15.115648 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9644 13:59:15.119283 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9645 13:59:15.125938 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9646 13:59:15.129347 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9647 13:59:15.132614 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9648 13:59:15.138814 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9649 13:59:15.142077 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9650 13:59:15.149021 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9651 13:59:15.152020 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9652 13:59:15.158732 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9653 13:59:15.161919 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9654 13:59:15.165618 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9655 13:59:15.172032 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9656 13:59:15.175381 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9657 13:59:15.181814 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9658 13:59:15.185139 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9659 13:59:15.188683 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9660 13:59:15.195330 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9661 13:59:15.198455 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9662 13:59:15.204772 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9663 13:59:15.208889 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9664 13:59:15.214825 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9665 13:59:15.218590 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9666 13:59:15.221663 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9667 13:59:15.228115 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9668 13:59:15.231726 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9669 13:59:15.237969 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9670 13:59:15.240990 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9671 13:59:15.248129 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9672 13:59:15.251320 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9673 13:59:15.255250 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9674 13:59:15.261203 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9675 13:59:15.264486 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9676 13:59:15.270995 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9677 13:59:15.274720 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9678 13:59:15.277840 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9679 13:59:15.280881 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9680 13:59:15.287400 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9681 13:59:15.290763 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9682 13:59:15.294402 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9683 13:59:15.300629 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9684 13:59:15.303945 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9685 13:59:15.307230 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9686 13:59:15.313810 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9687 13:59:15.316966 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9688 13:59:15.320873 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9689 13:59:15.326809 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9690 13:59:15.330382 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9691 13:59:15.337326 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9692 13:59:15.339874 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9693 13:59:15.343832 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9694 13:59:15.350310 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9695 13:59:15.353042 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9696 13:59:15.356565 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9697 13:59:15.363520 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9698 13:59:15.366763 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9699 13:59:15.373003 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9700 13:59:15.376696 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9701 13:59:15.380134 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9702 13:59:15.386027 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9703 13:59:15.389895 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9704 13:59:15.395967 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9705 13:59:15.399783 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9706 13:59:15.403016 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9707 13:59:15.409376 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9708 13:59:15.412543 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9709 13:59:15.416118 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9710 13:59:15.422485 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9711 13:59:15.425962 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9712 13:59:15.428933 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9713 13:59:15.435420 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9714 13:59:15.439467 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9715 13:59:15.445759 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9716 13:59:15.448783 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9717 13:59:15.451956 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9718 13:59:15.455703 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9719 13:59:15.462034 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9720 13:59:15.465315 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9721 13:59:15.468765 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9722 13:59:15.471916 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9723 13:59:15.478472 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9724 13:59:15.481926 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9725 13:59:15.485360 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9726 13:59:15.488756 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9727 13:59:15.494988 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9728 13:59:15.498309 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9729 13:59:15.501576 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9730 13:59:15.508337 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9731 13:59:15.511880 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9732 13:59:15.518487 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9733 13:59:15.521598 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9734 13:59:15.524784 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9735 13:59:15.531506 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9736 13:59:15.534628 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9737 13:59:15.541738 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9738 13:59:15.544554 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9739 13:59:15.548256 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9740 13:59:15.554387 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9741 13:59:15.557864 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9742 13:59:15.564637 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9743 13:59:15.567734 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9744 13:59:15.574351 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9745 13:59:15.577762 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9746 13:59:15.580679 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9747 13:59:15.587520 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9748 13:59:15.590951 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9749 13:59:15.597137 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9750 13:59:15.600795 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9751 13:59:15.607346 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9752 13:59:15.610943 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9753 13:59:15.614026 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9754 13:59:15.620402 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9755 13:59:15.623617 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9756 13:59:15.629926 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9757 13:59:15.633532 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9758 13:59:15.640015 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9759 13:59:15.643180 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9760 13:59:15.646852 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9761 13:59:15.653432 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9762 13:59:15.656499 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9763 13:59:15.662990 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9764 13:59:15.666045 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9765 13:59:15.669651 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9766 13:59:15.676355 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9767 13:59:15.679344 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9768 13:59:15.686058 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9769 13:59:15.689371 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9770 13:59:15.692520 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9771 13:59:15.699086 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9772 13:59:15.702962 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9773 13:59:15.709034 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9774 13:59:15.712716 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9775 13:59:15.719395 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9776 13:59:15.722120 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9777 13:59:15.725538 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9778 13:59:15.732191 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9779 13:59:15.735916 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9780 13:59:15.741940 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9781 13:59:15.745527 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9782 13:59:15.752210 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9783 13:59:15.755622 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9784 13:59:15.758566 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9785 13:59:15.764973 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9786 13:59:15.768500 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9787 13:59:15.775231 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9788 13:59:15.779129 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9789 13:59:15.781838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9790 13:59:15.788190 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9791 13:59:15.791719 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9792 13:59:15.798179 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9793 13:59:15.802312 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9794 13:59:15.804604 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9795 13:59:15.811231 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9796 13:59:15.814645 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9797 13:59:15.821327 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9798 13:59:15.824430 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9799 13:59:15.831000 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9800 13:59:15.834310 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9801 13:59:15.837882 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9802 13:59:15.844367 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9803 13:59:15.847556 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9804 13:59:15.854549 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9805 13:59:15.857484 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9806 13:59:15.864198 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9807 13:59:15.867657 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9808 13:59:15.874502 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9809 13:59:15.877604 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9810 13:59:15.881069 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9811 13:59:15.887049 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9812 13:59:15.890853 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9813 13:59:15.897462 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9814 13:59:15.900363 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9815 13:59:15.906956 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9816 13:59:15.910477 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9817 13:59:15.913709 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9818 13:59:15.920310 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9819 13:59:15.923659 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9820 13:59:15.929895 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9821 13:59:15.933500 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9822 13:59:15.939797 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9823 13:59:15.943416 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9824 13:59:15.950026 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9825 13:59:15.953230 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9826 13:59:15.959713 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9827 13:59:15.963060 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9828 13:59:15.966302 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9829 13:59:15.973310 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9830 13:59:15.976260 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9831 13:59:15.982757 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9832 13:59:15.985923 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9833 13:59:15.992736 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9834 13:59:15.995916 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9835 13:59:16.002530 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9836 13:59:16.005548 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9837 13:59:16.012051 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9838 13:59:16.015431 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9839 13:59:16.019178 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9840 13:59:16.025231 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9841 13:59:16.028862 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9842 13:59:16.035396 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9843 13:59:16.038351 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9844 13:59:16.045074 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9845 13:59:16.048493 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9846 13:59:16.055778 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9847 13:59:16.058708 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9848 13:59:16.061976 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9849 13:59:16.068890 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9850 13:59:16.071763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9851 13:59:16.077879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9852 13:59:16.081349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9853 13:59:16.088045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9854 13:59:16.091234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9855 13:59:16.098051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9856 13:59:16.101137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9857 13:59:16.104982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9858 13:59:16.111237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9859 13:59:16.114618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9860 13:59:16.121487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9861 13:59:16.124700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9862 13:59:16.131045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9863 13:59:16.134295 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9864 13:59:16.140721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9865 13:59:16.143923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9866 13:59:16.150551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9867 13:59:16.153797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9868 13:59:16.160657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9869 13:59:16.163885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9870 13:59:16.170950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9871 13:59:16.173667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9872 13:59:16.180364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9873 13:59:16.183874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9874 13:59:16.190256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9875 13:59:16.193798 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9876 13:59:16.200192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9877 13:59:16.203195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9878 13:59:16.210182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9879 13:59:16.216972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9880 13:59:16.219983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9881 13:59:16.226606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9882 13:59:16.229691 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9883 13:59:16.229773 INFO: [APUAPC] vio 0
9884 13:59:16.237250 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9885 13:59:16.240539 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9886 13:59:16.243704 INFO: [APUAPC] D0_APC_0: 0x400510
9887 13:59:16.247012 INFO: [APUAPC] D0_APC_1: 0x0
9888 13:59:16.250282 INFO: [APUAPC] D0_APC_2: 0x1540
9889 13:59:16.253584 INFO: [APUAPC] D0_APC_3: 0x0
9890 13:59:16.257011 INFO: [APUAPC] D1_APC_0: 0xffffffff
9891 13:59:16.260255 INFO: [APUAPC] D1_APC_1: 0xffffffff
9892 13:59:16.263275 INFO: [APUAPC] D1_APC_2: 0x3fffff
9893 13:59:16.266716 INFO: [APUAPC] D1_APC_3: 0x0
9894 13:59:16.270344 INFO: [APUAPC] D2_APC_0: 0xffffffff
9895 13:59:16.273514 INFO: [APUAPC] D2_APC_1: 0xffffffff
9896 13:59:16.276630 INFO: [APUAPC] D2_APC_2: 0x3fffff
9897 13:59:16.279900 INFO: [APUAPC] D2_APC_3: 0x0
9898 13:59:16.283251 INFO: [APUAPC] D3_APC_0: 0xffffffff
9899 13:59:16.286902 INFO: [APUAPC] D3_APC_1: 0xffffffff
9900 13:59:16.289908 INFO: [APUAPC] D3_APC_2: 0x3fffff
9901 13:59:16.293234 INFO: [APUAPC] D3_APC_3: 0x0
9902 13:59:16.296429 INFO: [APUAPC] D4_APC_0: 0xffffffff
9903 13:59:16.299971 INFO: [APUAPC] D4_APC_1: 0xffffffff
9904 13:59:16.302727 INFO: [APUAPC] D4_APC_2: 0x3fffff
9905 13:59:16.306234 INFO: [APUAPC] D4_APC_3: 0x0
9906 13:59:16.309456 INFO: [APUAPC] D5_APC_0: 0xffffffff
9907 13:59:16.312716 INFO: [APUAPC] D5_APC_1: 0xffffffff
9908 13:59:16.316205 INFO: [APUAPC] D5_APC_2: 0x3fffff
9909 13:59:16.320035 INFO: [APUAPC] D5_APC_3: 0x0
9910 13:59:16.322703 INFO: [APUAPC] D6_APC_0: 0xffffffff
9911 13:59:16.326193 INFO: [APUAPC] D6_APC_1: 0xffffffff
9912 13:59:16.329613 INFO: [APUAPC] D6_APC_2: 0x3fffff
9913 13:59:16.329719 INFO: [APUAPC] D6_APC_3: 0x0
9914 13:59:16.336008 INFO: [APUAPC] D7_APC_0: 0xffffffff
9915 13:59:16.339256 INFO: [APUAPC] D7_APC_1: 0xffffffff
9916 13:59:16.342719 INFO: [APUAPC] D7_APC_2: 0x3fffff
9917 13:59:16.342817 INFO: [APUAPC] D7_APC_3: 0x0
9918 13:59:16.346259 INFO: [APUAPC] D8_APC_0: 0xffffffff
9919 13:59:16.352462 INFO: [APUAPC] D8_APC_1: 0xffffffff
9920 13:59:16.352571 INFO: [APUAPC] D8_APC_2: 0x3fffff
9921 13:59:16.356046 INFO: [APUAPC] D8_APC_3: 0x0
9922 13:59:16.359340 INFO: [APUAPC] D9_APC_0: 0xffffffff
9923 13:59:16.362696 INFO: [APUAPC] D9_APC_1: 0xffffffff
9924 13:59:16.365675 INFO: [APUAPC] D9_APC_2: 0x3fffff
9925 13:59:16.369538 INFO: [APUAPC] D9_APC_3: 0x0
9926 13:59:16.372155 INFO: [APUAPC] D10_APC_0: 0xffffffff
9927 13:59:16.376069 INFO: [APUAPC] D10_APC_1: 0xffffffff
9928 13:59:16.379187 INFO: [APUAPC] D10_APC_2: 0x3fffff
9929 13:59:16.382395 INFO: [APUAPC] D10_APC_3: 0x0
9930 13:59:16.385536 INFO: [APUAPC] D11_APC_0: 0xffffffff
9931 13:59:16.388748 INFO: [APUAPC] D11_APC_1: 0xffffffff
9932 13:59:16.395893 INFO: [APUAPC] D11_APC_2: 0x3fffff
9933 13:59:16.395997 INFO: [APUAPC] D11_APC_3: 0x0
9934 13:59:16.398594 INFO: [APUAPC] D12_APC_0: 0xffffffff
9935 13:59:16.405408 INFO: [APUAPC] D12_APC_1: 0xffffffff
9936 13:59:16.408752 INFO: [APUAPC] D12_APC_2: 0x3fffff
9937 13:59:16.408864 INFO: [APUAPC] D12_APC_3: 0x0
9938 13:59:16.415456 INFO: [APUAPC] D13_APC_0: 0xffffffff
9939 13:59:16.418910 INFO: [APUAPC] D13_APC_1: 0xffffffff
9940 13:59:16.421875 INFO: [APUAPC] D13_APC_2: 0x3fffff
9941 13:59:16.421976 INFO: [APUAPC] D13_APC_3: 0x0
9942 13:59:16.428865 INFO: [APUAPC] D14_APC_0: 0xffffffff
9943 13:59:16.432128 INFO: [APUAPC] D14_APC_1: 0xffffffff
9944 13:59:16.435286 INFO: [APUAPC] D14_APC_2: 0x3fffff
9945 13:59:16.438599 INFO: [APUAPC] D14_APC_3: 0x0
9946 13:59:16.441327 INFO: [APUAPC] D15_APC_0: 0xffffffff
9947 13:59:16.445229 INFO: [APUAPC] D15_APC_1: 0xffffffff
9948 13:59:16.448230 INFO: [APUAPC] D15_APC_2: 0x3fffff
9949 13:59:16.451723 INFO: [APUAPC] D15_APC_3: 0x0
9950 13:59:16.451791 INFO: [APUAPC] APC_CON: 0x4
9951 13:59:16.454802 INFO: [NOCDAPC] D0_APC_0: 0x0
9952 13:59:16.458330 INFO: [NOCDAPC] D0_APC_1: 0x0
9953 13:59:16.461481 INFO: [NOCDAPC] D1_APC_0: 0x0
9954 13:59:16.465283 INFO: [NOCDAPC] D1_APC_1: 0xfff
9955 13:59:16.468291 INFO: [NOCDAPC] D2_APC_0: 0x0
9956 13:59:16.471108 INFO: [NOCDAPC] D2_APC_1: 0xfff
9957 13:59:16.474558 INFO: [NOCDAPC] D3_APC_0: 0x0
9958 13:59:16.477749 INFO: [NOCDAPC] D3_APC_1: 0xfff
9959 13:59:16.481236 INFO: [NOCDAPC] D4_APC_0: 0x0
9960 13:59:16.484604 INFO: [NOCDAPC] D4_APC_1: 0xfff
9961 13:59:16.484684 INFO: [NOCDAPC] D5_APC_0: 0x0
9962 13:59:16.487777 INFO: [NOCDAPC] D5_APC_1: 0xfff
9963 13:59:16.491634 INFO: [NOCDAPC] D6_APC_0: 0x0
9964 13:59:16.494101 INFO: [NOCDAPC] D6_APC_1: 0xfff
9965 13:59:16.497457 INFO: [NOCDAPC] D7_APC_0: 0x0
9966 13:59:16.501206 INFO: [NOCDAPC] D7_APC_1: 0xfff
9967 13:59:16.504175 INFO: [NOCDAPC] D8_APC_0: 0x0
9968 13:59:16.507495 INFO: [NOCDAPC] D8_APC_1: 0xfff
9969 13:59:16.510615 INFO: [NOCDAPC] D9_APC_0: 0x0
9970 13:59:16.514522 INFO: [NOCDAPC] D9_APC_1: 0xfff
9971 13:59:16.517599 INFO: [NOCDAPC] D10_APC_0: 0x0
9972 13:59:16.521069 INFO: [NOCDAPC] D10_APC_1: 0xfff
9973 13:59:16.523683 INFO: [NOCDAPC] D11_APC_0: 0x0
9974 13:59:16.523798 INFO: [NOCDAPC] D11_APC_1: 0xfff
9975 13:59:16.527108 INFO: [NOCDAPC] D12_APC_0: 0x0
9976 13:59:16.530479 INFO: [NOCDAPC] D12_APC_1: 0xfff
9977 13:59:16.533735 INFO: [NOCDAPC] D13_APC_0: 0x0
9978 13:59:16.537174 INFO: [NOCDAPC] D13_APC_1: 0xfff
9979 13:59:16.540689 INFO: [NOCDAPC] D14_APC_0: 0x0
9980 13:59:16.543621 INFO: [NOCDAPC] D14_APC_1: 0xfff
9981 13:59:16.546858 INFO: [NOCDAPC] D15_APC_0: 0x0
9982 13:59:16.550783 INFO: [NOCDAPC] D15_APC_1: 0xfff
9983 13:59:16.553943 INFO: [NOCDAPC] APC_CON: 0x4
9984 13:59:16.556880 INFO: [APUAPC] set_apusys_apc done
9985 13:59:16.560253 INFO: [DEVAPC] devapc_init done
9986 13:59:16.563819 INFO: GICv3 without legacy support detected.
9987 13:59:16.566943 INFO: ARM GICv3 driver initialized in EL3
9988 13:59:16.570359 INFO: Maximum SPI INTID supported: 639
9989 13:59:16.576647 INFO: BL31: Initializing runtime services
9990 13:59:16.579852 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9991 13:59:16.583452 INFO: SPM: enable CPC mode
9992 13:59:16.589552 INFO: mcdi ready for mcusys-off-idle and system suspend
9993 13:59:16.592905 INFO: BL31: Preparing for EL3 exit to normal world
9994 13:59:16.596459 INFO: Entry point address = 0x80000000
9995 13:59:16.599435 INFO: SPSR = 0x8
9996 13:59:16.605234
9997 13:59:16.605315
9998 13:59:16.605379
9999 13:59:16.608925 Starting depthcharge on Spherion...
10000 13:59:16.609005
10001 13:59:16.609070 Wipe memory regions:
10002 13:59:16.609128
10003 13:59:16.609778 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10004 13:59:16.609876 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10005 13:59:16.609954 Setting prompt string to ['asurada:']
10006 13:59:16.610029 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10007 13:59:16.611837 [0x00000040000000, 0x00000054600000)
10008 13:59:16.734227
10009 13:59:16.734364 [0x00000054660000, 0x00000080000000)
10010 13:59:16.995129
10011 13:59:16.995271 [0x000000821a7280, 0x000000ffe64000)
10012 13:59:17.739054
10013 13:59:17.739246 [0x00000100000000, 0x00000240000000)
10014 13:59:19.629147
10015 13:59:19.631720 Initializing XHCI USB controller at 0x11200000.
10016 13:59:20.670148
10017 13:59:20.673246 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10018 13:59:20.673361
10019 13:59:20.673457
10020 13:59:20.673545
10021 13:59:20.673874 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10023 13:59:20.774219 asurada: tftpboot 192.168.201.1 11588083/tftp-deploy-103ah0cn/kernel/image.itb 11588083/tftp-deploy-103ah0cn/kernel/cmdline
10024 13:59:20.774343 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 13:59:20.774495 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10026 13:59:20.778737 tftpboot 192.168.201.1 11588083/tftp-deploy-103ah0cn/kernel/image.ittp-deploy-103ah0cn/kernel/cmdline
10027 13:59:20.778849
10028 13:59:20.778945 Waiting for link
10029 13:59:20.939463
10030 13:59:20.939636 R8152: Initializing
10031 13:59:20.939743
10032 13:59:20.942708 Version 6 (ocp_data = 5c30)
10033 13:59:20.942811
10034 13:59:20.946096 R8152: Done initializing
10035 13:59:20.946175
10036 13:59:20.946239 Adding net device
10037 13:59:22.817592
10038 13:59:22.818316 done.
10039 13:59:22.818807
10040 13:59:22.819282 MAC: 00:24:32:30:7c:7b
10041 13:59:22.819647
10042 13:59:22.820571 Sending DHCP discover... done.
10043 13:59:22.820965
10044 13:59:22.823925 Waiting for reply... done.
10045 13:59:22.824604
10046 13:59:22.827432 Sending DHCP request... done.
10047 13:59:22.827896
10048 13:59:22.828262 Waiting for reply... done.
10049 13:59:22.828610
10050 13:59:22.830657 My ip is 192.168.201.14
10051 13:59:22.831158
10052 13:59:22.833780 The DHCP server ip is 192.168.201.1
10053 13:59:22.834333
10054 13:59:22.837712 TFTP server IP predefined by user: 192.168.201.1
10055 13:59:22.838272
10056 13:59:22.843693 Bootfile predefined by user: 11588083/tftp-deploy-103ah0cn/kernel/image.itb
10057 13:59:22.844158
10058 13:59:22.847125 Sending tftp read request... done.
10059 13:59:22.847592
10060 13:59:22.856992 Waiting for the transfer...
10061 13:59:22.857561
10062 13:59:23.577298 00000000 ################################################################
10063 13:59:23.577845
10065 14:03:41.611122 end: 2.2.4 bootloader-commands (duration 00:04:25) [common]
10067 14:03:41.612856 depthcharge-retry failed: 1 of 1 attempts. 'bootloader-commands timed out after 265 seconds'
10069 14:03:41.614274 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
10072 14:03:41.615646 end: 2 depthcharge-action (duration 00:05:00) [common]
10074 14:03:41.615862 Cleaning after the job
10075 14:03:41.615955 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/ramdisk
10076 14:03:41.621373 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/kernel
10077 14:03:41.640349 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/dtb
10078 14:03:41.640551 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11588083/tftp-deploy-103ah0cn/modules
10079 14:03:41.647721 start: 4.1 power-off (timeout 00:00:30) [common]
10080 14:03:41.647894 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
10081 14:03:41.725694 >> Command sent successfully.
10082 14:03:41.730915 Returned 0 in 0 seconds
10083 14:03:41.831973 end: 4.1 power-off (duration 00:00:00) [common]
10085 14:03:41.833550 start: 4.2 read-feedback (timeout 00:10:00) [common]
10086 14:03:41.834934 Listened to connection for namespace 'common' for up to 1s
10087 14:03:42.835387 Finalising connection for namespace 'common'
10088 14:03:42.836084 Disconnecting from shell: Finalise
10089 14:03:42.836497 00080000 #########################
10090 14:03:42.937659 end: 4.2 read-feedback (duration 00:00:01) [common]
10091 14:03:42.938285 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11588083
10092 14:03:43.047084 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11588083
10093 14:03:43.047284 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.